STM32G0C1xx HAL User Manual: STM32G0xx HAL Drivers

STM32G0C1xx HAL User Manual
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STM32G0xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32G0C1xx HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
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STM32G0C1xx HAL User Manual: HAL Private Constants

  • Data Structures
  • Files
  • Directories
Defines
HAL Private Constants
HAL

Defines

#define | __STM32G0xx_HAL_VERSION_MAIN (0x01U)
STM32G0xx HAL Driver version number.
#define | __STM32G0xx_HAL_VERSION_SUB1 (0x04U)
#define | __STM32G0xx_HAL_VERSION_SUB2 (0x05U)
#define | __STM32G0xx_HAL_VERSION_RC (0x00U)
#define | __STM32G0xx_HAL_VERSION
#define | VREFBUF_TIMEOUT_VALUE 10U

Define Documentation

#define __STM32G0xx_HAL_VERSION
Value:
((__STM32G0xx_HAL_VERSION_MAIN << 24U)\
                                        |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\
                                        |(__STM32G0xx_HAL_VERSION_SUB2 << 8U )\
                                        |(__STM32G0xx_HAL_VERSION_RC))

Definition at line 62 of file stm32g0xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32G0xx_HAL_VERSION_MAIN (0x01U)

STM32G0xx HAL Driver version number.

[31:24] main version

Definition at line 58 of file stm32g0xx_hal.c.

#define __STM32G0xx_HAL_VERSION_RC (0x00U)

[7:0] release candidate

Definition at line 61 of file stm32g0xx_hal.c.

#define __STM32G0xx_HAL_VERSION_SUB1 (0x04U)

[23:16] sub1 version

Definition at line 59 of file stm32g0xx_hal.c.

#define __STM32G0xx_HAL_VERSION_SUB2 (0x05U)

[15:8] sub2 version

Definition at line 60 of file stm32g0xx_hal.c.

#define VREFBUF_TIMEOUT_VALUE 10U

10 ms

Definition at line 68 of file stm32g0xx_hal.c.

Referenced by HAL_SYSCFG_EnableVREFBUF().

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STM32G0C1xx HAL User Manual: HAL Exported Variables

Variables
HAL Exported Variables
HAL | HAL Exported Functions

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio = (1UL << __NVIC_PRIO_BITS)
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT
__IO uint32_t | uwTick
uint32_t | uwTickPrio
HAL_TickFreqTypeDef uwTickFreq

Variable Documentation

__IO uint32_t uwTick

Definition at line 80 of file stm32g0xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

__IO uint32_t uwTick

Definition at line 80 of file stm32g0xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT

Definition at line 82 of file stm32g0xx_hal.c.

Referenced by HAL_Delay(), HAL_GetTickFreq(), HAL_IncTick(), HAL_InitTick(), and HAL_SetTickFreq().

HAL_TickFreqTypeDef uwTickFreq

Definition at line 82 of file stm32g0xx_hal.c.

Referenced by HAL_Delay(), HAL_GetTickFreq(), HAL_IncTick(), HAL_InitTick(), and HAL_SetTickFreq().

uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS)

Definition at line 81 of file stm32g0xx_hal.c.

Referenced by HAL_GetTickPrio(), HAL_InitTick(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

uint32_t uwTickPrio

Definition at line 81 of file stm32g0xx_hal.c.

Referenced by HAL_GetTickPrio(), HAL_InitTick(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

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STM32G0C1xx HAL User Manual: Tick Frequency

Enumerations
Tick Frequency
HAL

Enumerations

enum HAL_TickFreqTypeDef { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ }

Enumeration Type Documentation

enum HAL_TickFreqTypeDef
Enumerator:
HAL_TICK_FREQ_10HZ
HAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT

Definition at line 43 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: Boot Mode

Defines
Boot Mode
SYSCFG Exported Constants

Defines

#define | SYSCFG_BOOT_MAINFLASH 0x00000000U
#define | SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0
#define | SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)

Define Documentation

#define SYSCFG_BOOT_MAINFLASH 0x00000000U

Main Flash memory mapped at 0x0000 0000

Definition at line 66 of file stm32g0xx_hal.h.

#define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)

Embedded SRAM mapped at 0x0000 0000

Definition at line 68 of file stm32g0xx_hal.h.

#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0

System Flash memory mapped at 0x0000 0000

Definition at line 67 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: Break

Defines
Break
SYSCFG Exported Constants

Defines

#define | SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL
#define | SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL
#define | SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL
#define | SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL

Define Documentation

#define SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17

Definition at line 82 of file stm32g0xx_hal.h.

#define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17

Definition at line 81 of file stm32g0xx_hal.h.

#define SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 79 of file stm32g0xx_hal.h.

#define SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL

Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17

Definition at line 77 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: Clamping Diode

Defines
Clamping Diode
SYSCFG Exported Constants

Defines

#define | SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN
#define | SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN
#define | SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN
#define | SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN
#define | SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN
#define | SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN
#define | SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN
#define | SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN

Define Documentation

#define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN

Enables Clamping Diode on PA1

Definition at line 91 of file stm32g0xx_hal.h.

#define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN

Enables Clamping Diode on PA13

Definition at line 95 of file stm32g0xx_hal.h.

#define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN

Enables Clamping Diode on PA3

Definition at line 92 of file stm32g0xx_hal.h.

#define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN

Enables Clamping Diode on PA5

Definition at line 93 of file stm32g0xx_hal.h.

#define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN

Enables Clamping Diode on PA6

Definition at line 94 of file stm32g0xx_hal.h.

#define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN

Enables Clamping Diode on PB0

Definition at line 96 of file stm32g0xx_hal.h.

#define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN

Enables Clamping Diode on PB1

Definition at line 97 of file stm32g0xx_hal.h.

#define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN

Enables Clamping Diode on PB2

Definition at line 98 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: Pin remapping

Defines
Pin remapping
SYSCFG Exported Constants

Defines

#define | SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP
#define | SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP

Define Documentation

#define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP

PA11 pad behaves digitally as PA9 GPIO pin

Definition at line 109 of file stm32g0xx_hal.h.

#define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP

PA12 pad behaves digitally as PA10 GPIO pin

Definition at line 110 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: IR Modulation Envelope signal selection

Defines
IR Modulation Envelope signal selection
SYSCFG Exported Constants

Defines

#define | HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)
#define | HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0)
#define | HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1)

Define Documentation

#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)

00: Timer16 is selected as IR Modulation envelope source

Definition at line 118 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0)

01: USART1 is selected as IR Modulation envelope source

Definition at line 119 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1)

10: USART4 is selected as IR Modulation envelope source

Definition at line 121 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: IR output polarity selection

Defines
IR output polarity selection
SYSCFG Exported Constants

Defines

#define | HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U
#define | HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL

Define Documentation

#define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL

01: IR output polarity inverted

Definition at line 134 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U

00: IR output polarity not inverted

Definition at line 133 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: VREFBUF Voltage Scale

Defines
VREFBUF Voltage Scale
SYSCFG Exported Constants

Defines

#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Define Documentation

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U

Voltage reference scale 0: VREF_OUT1 around 2.048 V. This requires VDDA equal to or higher than 2.4 V.

Definition at line 144 of file stm32g0xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Voltage reference scale 1: VREF_OUT1 around 2.5 V. This requires VDDA equal to or higher than 2.8 V.

Definition at line 146 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: VREFBUF High Impedance

Defines
VREFBUF High Impedance
SYSCFG Exported Constants

Defines

#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

Define Documentation

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U

VREF_plus pin is internally connected to Voltage reference buffer output

Definition at line 156 of file stm32g0xx_hal.h.

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

VREF_plus pin is high impedance

Definition at line 157 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: Fast mode Plus on GPIO

Defines
Fast mode Plus on GPIO
SYSCFG Exported Constants

Defines

#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
Fast mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP
#define | SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP

Define Documentation

#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP

Enable Fast mode Plus on PA10

Definition at line 175 of file stm32g0xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP

Enable Fast mode Plus on PA9

Definition at line 174 of file stm32g0xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Fast mode Plus driving capability on a specific GPIO.

Enable Fast mode Plus on PB6

Definition at line 170 of file stm32g0xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast mode Plus on PB7

Definition at line 171 of file stm32g0xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast mode Plus on PB8

Definition at line 172 of file stm32g0xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast mode Plus on PB9

Definition at line 173 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: Fast mode Plus driving capability activation for I2Cx

Defines
Fast mode Plus driving capability activation for I2Cx
SYSCFG Exported Constants

Defines

#define | SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
Fast mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | SYSCFG_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Fast mode Plus driving capability on a specific GPIO.

Enable Fast mode Plus on I2C1

Definition at line 187 of file stm32g0xx_hal.h.

#define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast mode Plus on I2C2

Definition at line 188 of file stm32g0xx_hal.h.

#define SYSCFG_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast mode Plus on I2C3

Definition at line 190 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: SYSCFG Dead Battery feature configuration

Defines
SYSCFG Dead Battery feature configuration
SYSCFG Exported Constants

Defines

#define | SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE
#define | SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE

Define Documentation

#define SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE

UCPD1 Dead battery sw configuration

Definition at line 200 of file stm32g0xx_hal.h.

#define SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE

UCPD2 Dead battery sw configuration

Definition at line 201 of file stm32g0xx_hal.h.

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STM32G0C1xx HAL User Manual: HAL ISR Wrapper

Defines
HAL ISR Wrapper
SYSCFG Exported Constants

ISR Wrapper. More...

Defines

#define | HAL_SYSCFG_ITLINE0 0x00000000U
#define | HAL_SYSCFG_ITLINE1 0x00000001U
#define | HAL_SYSCFG_ITLINE2 0x00000002U
#define | HAL_SYSCFG_ITLINE3 0x00000003U
#define | HAL_SYSCFG_ITLINE4 0x00000004U
#define | HAL_SYSCFG_ITLINE5 0x00000005U
#define | HAL_SYSCFG_ITLINE6 0x00000006U
#define | HAL_SYSCFG_ITLINE7 0x00000007U
#define | HAL_SYSCFG_ITLINE8 0x00000008U
#define | HAL_SYSCFG_ITLINE9 0x00000009U
#define | HAL_SYSCFG_ITLINE10 0x0000000AU
#define | HAL_SYSCFG_ITLINE11 0x0000000BU
#define | HAL_SYSCFG_ITLINE12 0x0000000CU
#define | HAL_SYSCFG_ITLINE13 0x0000000DU
#define | HAL_SYSCFG_ITLINE14 0x0000000EU
#define | HAL_SYSCFG_ITLINE15 0x0000000FU
#define | HAL_SYSCFG_ITLINE16 0x00000010U
#define | HAL_SYSCFG_ITLINE17 0x00000011U
#define | HAL_SYSCFG_ITLINE18 0x00000012U
#define | HAL_SYSCFG_ITLINE19 0x00000013U
#define | HAL_SYSCFG_ITLINE20 0x00000014U
#define | HAL_SYSCFG_ITLINE21 0x00000015U
#define | HAL_SYSCFG_ITLINE22 0x00000016U
#define | HAL_SYSCFG_ITLINE23 0x00000017U
#define | HAL_SYSCFG_ITLINE24 0x00000018U
#define | HAL_SYSCFG_ITLINE25 0x00000019U
#define | HAL_SYSCFG_ITLINE26 0x0000001AU
#define | HAL_SYSCFG_ITLINE27 0x0000001BU
#define | HAL_SYSCFG_ITLINE28 0x0000001CU
#define | HAL_SYSCFG_ITLINE29 0x0000001DU
#define | HAL_SYSCFG_ITLINE30 0x0000001EU
#define | HAL_SYSCFG_ITLINE31 0x0000001FU
#define | HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)
#define | HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)
#define | HAL_ITLINE_PVMOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT)
#define | HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC)
#define | HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER)
#define | HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC)
#define | HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)
#define | HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)
#define | HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)
#define | HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)
#define | HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)
#define | HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)
#define | HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)
#define | HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)
#define | HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)
#define | HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)
#define | HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)
#define | HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)
#define | HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)
#define | HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)
#define | HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)
#define | HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)
#define | HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)
#define | HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)
#define | HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)
#define | HAL_ITLINE_UCPD1 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1)
#define | HAL_ITLINE_UCPD2 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2)
#define | HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB)
#define | HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)
#define | HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)
#define | HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)
#define | HAL_ITLINE_DMAMUX1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1)
#define | HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)
#define | HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)
#define | HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)
#define | HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)
#define | HAL_ITLINE_DMA2_CH1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1)
#define | HAL_ITLINE_DMA2_CH2 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2)
#define | HAL_ITLINE_DMA2_CH3 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)
#define | HAL_ITLINE_DMA2_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)
#define | HAL_ITLINE_DMA2_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)
#define | HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)
#define | HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)
#define | HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)
#define | HAL_ITLINE_COMP3 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3)
#define | HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)
#define | HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)
#define | HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)
#define | HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)
#define | HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)
#define | HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)
#define | HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)
#define | HAL_ITLINE_TIM4 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB)
#define | HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)
#define | HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)
#define | HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB)
#define | HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)
#define | HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB)
#define | HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)
#define | HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)
#define | HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)
#define | HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0)
#define | HAL_ITLINE_FDCAN2_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0)
#define | HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)
#define | HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1)
#define | HAL_ITLINE_FDCAN2_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1)
#define | HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)
#define | HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)
#define | HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB)
#define | HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)
#define | HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)
#define | HAL_ITLINE_SPI3 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3)
#define | HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)
#define | HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)
#define | HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB)
#define | HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)
#define | HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)
#define | HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB)
#define | HAL_ITLINE_USART5 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)
#define | HAL_ITLINE_USART6 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)
#define | HAL_ITLINE_CEC ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)
#define | HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG)
#define | HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES)

Detailed Description

ISR Wrapper.

Define Documentation

#define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)

ADC Interrupt

Definition at line 301 of file stm32g0xx_hal.h.

#define HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES)

AES Interrupt

Definition at line 389 of file stm32g0xx_hal.h.

#define HAL_ITLINE_CEC ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)

CEC Interrupt -> exti[27]

Definition at line 383 of file stm32g0xx_hal.h.

#define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)

CLK Control Interrupt

Definition at line 255 of file stm32g0xx_hal.h.

#define HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)

COMP1 Interrupt -> exti[17]

Definition at line 303 of file stm32g0xx_hal.h.

#define HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)

COMP2 Interrupt -> exti[18]

Definition at line 306 of file stm32g0xx_hal.h.

#define HAL_ITLINE_COMP3 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3)

COMP3 Interrupt -> exti[1x]

Definition at line 309 of file stm32g0xx_hal.h.

#define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)

CRS Interrupt

Definition at line 257 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)

DAC Interrupt

Definition at line 327 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)

DMA1 Channel 1 Interrupt

Definition at line 284 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)

DMA1 Channel 2 Interrupt

Definition at line 285 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)

DMA1 Channel 3 Interrupt

Definition at line 286 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)

DMA1 Channel 4 Interrupt

Definition at line 288 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)

DMA1 Channel 5 Interrupt

Definition at line 289 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)

DMA1 Channel 6 Interrupt

Definition at line 291 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)

DMA1 Channel 7 Interrupt

Definition at line 292 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA2_CH1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1)

DMA2 Channel 1 Interrupt

Definition at line 295 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA2_CH2 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2)

DMA2 Channel 2 Interrupt

Definition at line 296 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA2_CH3 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)

DMA2 Channel 3 Interrupt

Definition at line 297 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA2_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)

DMA2 Channel 4 Interrupt

Definition at line 298 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMA2_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)

DMA2 Channel 5 Interrupt

Definition at line 299 of file stm32g0xx_hal.h.

#define HAL_ITLINE_DMAMUX1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1)

DMAMUX1 Interrupt

Definition at line 287 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)

External Interrupt 0

Definition at line 259 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)

External Interrupt 1

Definition at line 260 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)

EXTI10 Interrupt

Definition at line 269 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)

EXTI11 Interrupt

Definition at line 270 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)

EXTI12 Interrupt

Definition at line 271 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)

EXTI13 Interrupt

Definition at line 272 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)

EXTI14 Interrupt

Definition at line 273 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)

EXTI15 Interrupt

Definition at line 274 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)

External Interrupt 2

Definition at line 261 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)

External Interrupt 3

Definition at line 262 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)

EXTI4 Interrupt

Definition at line 263 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)

EXTI5 Interrupt

Definition at line 264 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)

EXTI6 Interrupt

Definition at line 265 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)

EXTI7 Interrupt

Definition at line 266 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)

EXTI8 Interrupt

Definition at line 267 of file stm32g0xx_hal.h.

#define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)

EXTI9 Interrupt

Definition at line 268 of file stm32g0xx_hal.h.

#define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0)

FDCAN1_IT0 Interrupt

Definition at line 344 of file stm32g0xx_hal.h.

#define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1)

FDCAN1_IT1 Interrupt

Definition at line 349 of file stm32g0xx_hal.h.

#define HAL_ITLINE_FDCAN2_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0)

FDCAN2_IT0 Interrupt

Definition at line 345 of file stm32g0xx_hal.h.

#define HAL_ITLINE_FDCAN2_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1)

FDCAN2_IT1 Interrupt

Definition at line 350 of file stm32g0xx_hal.h.

#define HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC)

Flash ECC Interrupt

Definition at line 253 of file stm32g0xx_hal.h.

#define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)

Flash ITF Interrupt

Definition at line 254 of file stm32g0xx_hal.h.

#define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)

I2C1 Interrupt -> exti[23]

Definition at line 352 of file stm32g0xx_hal.h.

#define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)

I2C2 Interrupt -> exti[24]

Definition at line 353 of file stm32g0xx_hal.h.

#define HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB)

I2C3 Interrupt -> exti[22]

Definition at line 355 of file stm32g0xx_hal.h.

#define HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB)

LPTIM1 Interrupt -> exti[29]

Definition at line 330 of file stm32g0xx_hal.h.

#define HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB)

LPTIM2 Interrupt -> exti[30]

Definition at line 336 of file stm32g0xx_hal.h.

#define HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB)

LPUART1 Interrupt -> exti[28]

Definition at line 374 of file stm32g0xx_hal.h.

#define HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB)

LPUART2 GLB Interrupt -> exti[26]

Definition at line 365 of file stm32g0xx_hal.h.

#define HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)

Power voltage detection Interrupt ....

Definition at line 246 of file stm32g0xx_hal.h.

#define HAL_ITLINE_PVMOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT)

Power voltage monitor Interrupt ....

Definition at line 249 of file stm32g0xx_hal.h.

#define HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG)

RNG Interrupt

Definition at line 386 of file stm32g0xx_hal.h.

#define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC)

RTC -> exti[19] Interrupt

Definition at line 251 of file stm32g0xx_hal.h.

#define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)

SPI1 Interrupt

Definition at line 357 of file stm32g0xx_hal.h.

#define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)

SPI2 Interrupt

Definition at line 358 of file stm32g0xx_hal.h.

#define HAL_ITLINE_SPI3 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3)

SPI3 Interrupt

Definition at line 360 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER)

TAMPER -> exti[21] interrupt ....

Definition at line 252 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)

TIM14 Interrupt

Definition at line 338 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)

TIM15 Interrupt

Definition at line 340 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)

TIM16 Interrupt

Definition at line 342 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)

TIM17 Interrupt

Definition at line 347 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)

TIM1 BRK Interrupt

Definition at line 311 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)

TIM1 CC Interrupt

Definition at line 315 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)

TIM1 CCU Interrupt

Definition at line 314 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)

TIM1 TRG Interrupt

Definition at line 313 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)

TIM1 UPD Interrupt

Definition at line 312 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)

TIM2 Interrupt

Definition at line 317 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)

TIM3 Interrupt

Definition at line 319 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM4 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB)

TIM4 Interrupt

Definition at line 321 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)

TIM6 Interrupt

Definition at line 324 of file stm32g0xx_hal.h.

#define HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)

TIM7 Interrupt

Definition at line 333 of file stm32g0xx_hal.h.

#define HAL_ITLINE_UCPD1 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1)

UCPD1 Interrupt

Definition at line 276 of file stm32g0xx_hal.h.

#define HAL_ITLINE_UCPD2 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2)

UCPD2 Interrupt

Definition at line 279 of file stm32g0xx_hal.h.

#define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)

USART1 GLB Interrupt -> exti[25]

Definition at line 362 of file stm32g0xx_hal.h.

#define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)

USART2 GLB Interrupt -> exti[26]

Definition at line 363 of file stm32g0xx_hal.h.

#define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)

USART3 Interrupt ....

Definition at line 368 of file stm32g0xx_hal.h.

#define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)

USART4 Interrupt ....

Definition at line 371 of file stm32g0xx_hal.h.

#define HAL_ITLINE_USART5 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)

USART5 Interrupt ....

Definition at line 377 of file stm32g0xx_hal.h.

#define HAL_ITLINE_USART6 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)

USART6 Interrupt ....

Definition at line 380 of file stm32g0xx_hal.h.

#define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB)

USB Interrupt

Definition at line 282 of file stm32g0xx_hal.h.

#define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)

WWDG has expired ....

Definition at line 244 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE0 0x00000000U

Internal define for macro handling

Definition at line 211 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE1 0x00000001U

Internal define for macro handling

Definition at line 212 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE10 0x0000000AU

Internal define for macro handling

Definition at line 221 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE11 0x0000000BU

Internal define for macro handling

Definition at line 222 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE12 0x0000000CU

Internal define for macro handling

Definition at line 223 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE13 0x0000000DU

Internal define for macro handling

Definition at line 224 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE14 0x0000000EU

Internal define for macro handling

Definition at line 225 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE15 0x0000000FU

Internal define for macro handling

Definition at line 226 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE16 0x00000010U

Internal define for macro handling

Definition at line 227 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE17 0x00000011U

Internal define for macro handling

Definition at line 228 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE18 0x00000012U

Internal define for macro handling

Definition at line 229 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE19 0x00000013U

Internal define for macro handling

Definition at line 230 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE2 0x00000002U

Internal define for macro handling

Definition at line 213 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE20 0x00000014U

Internal define for macro handling

Definition at line 231 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE21 0x00000015U

Internal define for macro handling

Definition at line 232 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE22 0x00000016U

Internal define for macro handling

Definition at line 233 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE23 0x00000017U

Internal define for macro handling

Definition at line 234 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE24 0x00000018U

Internal define for macro handling

Definition at line 235 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE25 0x00000019U

Internal define for macro handling

Definition at line 236 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE26 0x0000001AU

Internal define for macro handling

Definition at line 237 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE27 0x0000001BU

Internal define for macro handling

Definition at line 238 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE28 0x0000001CU

Internal define for macro handling

Definition at line 239 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE29 0x0000001DU

Internal define for macro handling

Definition at line 240 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE3 0x00000003U

Internal define for macro handling

Definition at line 214 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE30 0x0000001EU

Internal define for macro handling

Definition at line 241 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE31 0x0000001FU

Internal define for macro handling

Definition at line 242 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE4 0x00000004U

Internal define for macro handling

Definition at line 215 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE5 0x00000005U

Internal define for macro handling

Definition at line 216 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE6 0x00000006U

Internal define for macro handling

Definition at line 217 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE7 0x00000007U

Internal define for macro handling

Definition at line 218 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE8 0x00000008U

Internal define for macro handling

Definition at line 219 of file stm32g0xx_hal.h.

#define HAL_SYSCFG_ITLINE9 0x00000009U

Internal define for macro handling

Definition at line 220 of file stm32g0xx_hal.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DBG Exported Macros

Defines
DBG Exported Macros
HAL Exported Macros

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
Freeze and Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)

Define Documentation

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)

Definition at line 455 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)

Definition at line 460 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)

Definition at line 450 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM1 ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)

Definition at line 465 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM2 ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)

Definition at line 470 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)

Definition at line 440 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)

Definition at line 475 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM14 ( ) SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)

Definition at line 480 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM15 ( ) SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)

Definition at line 485 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM16 ( ) SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)

Definition at line 490 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM17 ( ) SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)

Definition at line 495 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)

Freeze and Unfreeze Peripherals in Debug mode.

Definition at line 415 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)

Definition at line 420 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)

Definition at line 425 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM6 ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)

Definition at line 430 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM7 ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)

Definition at line 435 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG ( ) SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)

Definition at line 445 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)

Definition at line 456 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)

Definition at line 461 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_IWDG ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)

Definition at line 451 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_LPTIM1 ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)

Definition at line 466 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_LPTIM2 ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)

Definition at line 471 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_RTC ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)

Definition at line 441 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM1 ( ) CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)

Definition at line 476 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM14 ( ) CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)

Definition at line 481 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM15 ( ) CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)

Definition at line 486 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM16 ( ) CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)

Definition at line 491 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM17 ( ) CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)

Definition at line 496 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM2 ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)

Definition at line 416 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM3 ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)

Definition at line 421 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM4 ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)

Definition at line 426 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM6 ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)

Definition at line 431 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM7 ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)

Definition at line 436 of file stm32g0xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_WWDG ( ) CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)

Definition at line 446 of file stm32g0xx_hal.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSCFG Exported Macros

Defines
SYSCFG Exported Macros
HAL Exported Macros

Defines

#define | __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
ISR wrapper check.
#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
Return the boot mode as configured by user.
#define | __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
SYSCFG Break ECC lock.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
SYSCFG Break Cortex-M0+ Lockup lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
SYSCFG Break SRAM PARITY lock Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17.
#define | __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
Parity check on RAM disable macro.
#define | __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
Set the PEF bit to clear the SRAM Parity Error Flag.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)
#define | __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__)
Clamping Diode on specific pins enable/disable macros.
#define | __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__)
#define | __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU))
ISR wrapper check.
#define | __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)
selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
#define | __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U)
#define | __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__)
IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register.
#define | __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
Return the IROut Polarity mode as configured by user.
#define | __HAL_SYSCFG_BREAK_ENABLE(__BREAK__)
Break input to TIM1/15/16/17 capability enable/disable macros.
#define | __HAL_SYSCFG_BREAK_DISABLE(__BREAK__)

Define Documentation

#define __HAL_GET_PENDING_IT ( __SOURCE__ ) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))

ISR wrapper check.

Note:
Allow to determine interrupt source per line.

Definition at line 511 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_BREAK_DISABLE ( __BREAK__ )
Value:
do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
                                                     CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
                                                    }while(0U)

Definition at line 632 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_BREAK_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)

SYSCFG Break ECC lock.

Enable and lock the connection of Flash ECC error connection to TIM1 Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 537 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_BREAK_ENABLE ( __BREAK__ )
Value:
do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
                                                     SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
                                                    }while(0U)

Break input to TIM1/15/16/17 capability enable/disable macros.

Parameters:
__BREAK__ This parameter can be a value of Break

Definition at line 628 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)

SYSCFG Break Cortex-M0+ Lockup lock.

Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 544 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_BREAK_PVD_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)

SYSCFG Break PVD lock.

Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register

Note:
The selected configuration is locked and can be unlocked only by system reset

Definition at line 551 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK ( ) SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)

SYSCFG Break SRAM PARITY lock Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17.

Note:
The selected configuration is locked and can only be unlocked by system reset

Definition at line 558 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE ( __PIN__ )
Value:
do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
                                                                CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
                                                               }while(0U)

Definition at line 589 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE ( __PIN__ )
Value:
do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
                                                                SET_BIT(SYSCFG->CFGR2, (__PIN__));\
                                                               }while(0U)

Clamping Diode on specific pins enable/disable macros.

Parameters:
__PIN__ This parameter can be a combination of values Clamping Diode

Definition at line 585 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_CLEAR_FLAG ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)

Set the PEF bit to clear the SRAM Parity Error Flag.

Definition at line 568 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
                                                               }while(0U)

Definition at line 577 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
                                                               }while(0U)

Fast-mode Plus driving capability enable/disable macros.

Parameters:
__FASTMODEPLUS__ This parameter can be a value of Fast mode Plus on GPIO

Definition at line 573 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_GET_BOOT_MODE ( ) READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)

Return the boot mode as configured by user.

Return values:
The boot mode as configured by user. The returned value can be one of the following values Boot Mode

Definition at line 531 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION ( ) ((SYSCFG->CFGR1) & 0x000000C0U)

Definition at line 608 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_GET_PENDING_IT ( __SOURCE__ ) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU))

ISR wrapper check.

Note:
Allow to determine interrupt source per line.

Definition at line 597 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_GET_POLARITY ( ) READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)

Return the IROut Polarity mode as configured by user.

Return values:
The IROut polarity as configured by user. The returned value can be one of IR output polarity selection

Definition at line 623 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_IRDA_ENV_SELECTION ( __SOURCE__ )
Value:
do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\
                                                         CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\
                                                         SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\
                                                        }while(0U)

selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register

Parameters:
__SOURCE__ This parameter can be a value of IR Modulation Envelope signal selection

Definition at line 603 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION ( __SEL__ )
Value:
do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\
                                                                CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\
                                                                SET_BIT(SYSCFG->CFGR1,(__SEL__));\
                                                              }while(0U)

IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register.

Parameters:
__SEL__ This parameter can be a value of IR output polarity selection

Definition at line 613 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE ( ) (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)

Parity check on RAM disable macro.

Note:
Disabling the parity check on RAM locks the configuration bit. To re-enable the parity check on RAM perform a system reset.

Definition at line 564 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_FLASH ( ) CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)

Main Flash memory mapped at 0x00000000.

Definition at line 515 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SRAM ( ) MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))

Embedded SRAM mapped at 0x00000000.

Definition at line 523 of file stm32g0xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH ( ) MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)

System Flash memory mapped at 0x00000000.

Definition at line 519 of file stm32g0xx_hal.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSCFG Private Macros

Defines
SYSCFG Private Macros
HAL

Defines

#define | IS_SYSCFG_BREAK_CONFIG(__CONFIG__)
#define | IS_SYSCFG_CLAMPINGDIODE(__PIN__)
#define | IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)
#define | IS_HAL_SYSCFG_IRDA_POL_SEL(SEL)
#define | IS_SYSCFG_DBATT_CONFIG(__CONFIG__)
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)
#define | IS_HAL_REMAP_PIN(RMP)

Define Documentation

#define IS_HAL_REMAP_PIN ( RMP )
Value:
(((RMP) == SYSCFG_REMAP_PA11) || \
                                             ((RMP) == SYSCFG_REMAP_PA12) || \
                                             ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12)))

Definition at line 705 of file stm32g0xx_hal.h.

Referenced by HAL_SYSCFG_DisableRemap(), and HAL_SYSCFG_EnableRemap().

#define IS_HAL_SYSCFG_IRDA_ENV_SEL ( SEL )
Value:
(((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)  || \
                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))

Definition at line 672 of file stm32g0xx_hal.h.

#define IS_HAL_SYSCFG_IRDA_POL_SEL ( SEL )
Value:
(((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED)   || \
                                           ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))

Definition at line 680 of file stm32g0xx_hal.h.

#define IS_SYSCFG_BREAK_CONFIG ( __CONFIG__ )
Value:
(((__CONFIG__) == SYSCFG_BREAK_SP)        || \
                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)       || \
                                            ((__CONFIG__) == SYSCFG_BREAK_ECC)       || \
                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))

Definition at line 650 of file stm32g0xx_hal.h.

#define IS_SYSCFG_CLAMPINGDIODE ( __PIN__ )
Value:
((((__PIN__) & SYSCFG_CDEN_PA1)  == SYSCFG_CDEN_PA1)  || \
                                          (((__PIN__) & SYSCFG_CDEN_PA3)  == SYSCFG_CDEN_PA3)  || \
                                          (((__PIN__) & SYSCFG_CDEN_PA5)  == SYSCFG_CDEN_PA5)  || \
                                          (((__PIN__) & SYSCFG_CDEN_PA6)  == SYSCFG_CDEN_PA6)  || \
                                          (((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \
                                          (((__PIN__) & SYSCFG_CDEN_PB0)  == SYSCFG_CDEN_PB0)  || \
                                          (((__PIN__) & SYSCFG_CDEN_PB1)  == SYSCFG_CDEN_PB1)  || \
                                          (((__PIN__) & SYSCFG_CDEN_PB2)  == SYSCFG_CDEN_PB2))

Definition at line 661 of file stm32g0xx_hal.h.

Referenced by HAL_SYSCFG_DisableClampingDiode(), and HAL_SYSCFG_EnableClampingDiode().

#define IS_SYSCFG_DBATT_CONFIG ( __CONFIG__ )
Value:
(((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \
                                            ((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \
                                            ((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE)))

Definition at line 684 of file stm32g0xx_hal.h.

Referenced by HAL_SYSCFG_StrobeDBattpinsConfig().

#define IS_SYSCFG_FASTMODEPLUS ( __PIN__ )
Value:
((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9)  == SYSCFG_FASTMODEPLUS_PA9)  || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))

Definition at line 698 of file stm32g0xx_hal.h.

#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE ( __VALUE__ )
Value:
(((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

Definition at line 692 of file stm32g0xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_HighImpedanceConfig().

#define IS_SYSCFG_VREFBUF_TRIMMING ( __VALUE__ ) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

Definition at line 695 of file stm32g0xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_TrimmingConfig().

#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE ( __SCALE__ )
Value:
(((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))

Definition at line 689 of file stm32g0xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_VoltageScalingConfig().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL Private Macros

Defines
HAL Private Macros
HAL

Defines

#define IS_TICKFREQ(FREQ)

Define Documentation

#define IS_TICKFREQ ( FREQ )
Value:
(((FREQ) == HAL_TICK_FREQ_10HZ)  || \
                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
                           ((FREQ) == HAL_TICK_FREQ_1KHZ))

Definition at line 715 of file stm32g0xx_hal.h.

Referenced by HAL_SetTickFreq().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL Initialization and Configuration functions

Functions
HAL Initialization and Configuration functions
HAL Exported Functions

HAL Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
Configure the Flash prefetch and the Instruction cache, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32g0xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Detailed Description

HAL Initialization and Configuration functions.

 ===============================================================================
           ##### HAL Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the Flash interface the NVIC allocation and initial time base
          clock configuration.
      (+) De-initialize common part of the HAL.
      (+) Configure the time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) SysTick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the source of time base.

Note:
This function is optional.
Return values:
HAL status

Definition at line 180 of file stm32g0xx_hal.c.

References __HAL_RCC_AHB_FORCE_RESET, __HAL_RCC_AHB_RELEASE_RESET, __HAL_RCC_APB1_FORCE_RESET, __HAL_RCC_APB1_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, __HAL_RCC_IOP_FORCE_RESET, __HAL_RCC_IOP_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

Configure the Flash prefetch and the Instruction cache, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32g0xx_hal_msp.c.

Note:
HAL_Init() function is called at the beginning of program after reset and before the clock configuration.
In the default implementation the System Timer (Systick) is used as source of time base. The Systick configuration is based on HSI clock, as HSI is the clock used after a system Reset. Once done, time base tick starts incrementing: the tick variable counter is incremented each 1ms in the SysTick_Handler() interrupt handler.
Return values:
HAL status

Definition at line 143 of file stm32g0xx_hal.c.

References __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_PREFETCH_BUFFER_ENABLE, HAL_InitTick(), HAL_MspInit(), and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority Tick interrupt priority.
Return values:
HAL status

Definition at line 240 of file stm32g0xx_hal.c.

References HAL_NVIC_SetPriority(), HAL_SYSTICK_Config(), uwTickFreq, and uwTickPrio.

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 217 of file stm32g0xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initialize the MSP.

Return values:
None

Definition at line 206 of file stm32g0xx_hal.c.

Referenced by HAL_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (HAL_TickFreqTypeDef Freq)
Set new tick Freq.
HAL_TickFreqTypeDef | HAL_GetTickFreq (void)
return tick frequency.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Returns first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Returns second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Returns third word of the unique device identifier (UID based on 96 bits)

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier

Function Documentation

void HAL_Delay ( uint32_t Delay )

This function provides minimum delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 383 of file stm32g0xx_hal.c.

References HAL_GetTick(), and uwTickFreq.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), HAL_HCD_HC_Close(), HAL_HCD_ResumePort(), and HAL_PCDEx_BCD_VBUSDetect().

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 453 of file stm32g0xx_hal.c.

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 435 of file stm32g0xx_hal.c.

References __STM32G0xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 444 of file stm32g0xx_hal.c.

uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 319 of file stm32g0xx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_WaitOnCCFlag(), FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_Calibration_Start(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_DAC_ConfigChannel(), HAL_Delay(), HAL_DMA_PollForTransfer(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_PCDEx_BCD_VBUSDetect(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSWaitSynchronization(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_GenerateRandomNumber(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SMBUS_IsDeviceReady(), HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SYSCFG_EnableVREFBUF(), HAL_TIMEx_ReArmBreakInput(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), I2C_IsErrorOccurred(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), I2S_WaitFlagStateUntilTimeout(), IRDA_CheckIdleState(), IRDA_WaitOnFlagUntilTimeout(), RTC_EnterInitMode(), SMARTCARD_CheckIdleState(), SMARTCARD_WaitOnFlagUntilTimeout(), SMBUS_WaitOnFlagUntilTimeout(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), UART_CheckIdleState(), UART_WaitOnFlagUntilTimeout(), USART_CheckIdleState(), and USART_WaitOnFlagUntilTimeout().

HAL_TickFreqTypeDef HAL_GetTickFreq ( void )

return tick frequency.

Return values:
tick period in Hz

Definition at line 367 of file stm32g0xx_hal.c.

References uwTickFreq.

uint32_t HAL_GetTickPrio ( void )

This function returns a tick priority.

Return values:
tick priority

Definition at line 328 of file stm32g0xx_hal.c.

References uwTickPrio.

uint32_t HAL_GetUIDw0 ( void )

Returns first word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 462 of file stm32g0xx_hal.c.

uint32_t HAL_GetUIDw1 ( void )

Returns second word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 471 of file stm32g0xx_hal.c.

uint32_t HAL_GetUIDw2 ( void )

Returns third word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 480 of file stm32g0xx_hal.c.

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in SysTick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 308 of file stm32g0xx_hal.c.

References uwTick, and uwTickFreq.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 425 of file stm32g0xx_hal.c.

HAL_StatusTypeDef HAL_SetTickFreq ( HAL_TickFreqTypeDef Freq )

Set new tick Freq.

Return values:
status

Definition at line 337 of file stm32g0xx_hal.c.

References assert_param, HAL_InitTick(), IS_TICKFREQ, uwTickFreq, and uwTickPrio.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 409 of file stm32g0xx_hal.c.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DBGMCU Control functions

Functions
DBGMCU Control functions
HAL Exported Functions

HAL Debug functions. More...

Functions

void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.

Detailed Description

HAL Debug functions.

 ===============================================================================
                      ##### HAL Debug functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 535 of file stm32g0xx_hal.c.

void HAL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Return values:
None

Definition at line 517 of file stm32g0xx_hal.c.

void HAL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 526 of file stm32g0xx_hal.c.

void HAL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Return values:
None

Definition at line 508 of file stm32g0xx_hal.c.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSCFG configuration functions

Functions
SYSCFG configuration functions
HAL Exported Functions

SYSCFG configuration functions. More...

Functions

void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOAnalogSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOAnalogSwitchBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableRemap (uint32_t PinRemap)
Enable the remap on PA11_PA12.
void | HAL_SYSCFG_DisableRemap (uint32_t PinRemap)
Disable the remap on PA11_PA12.
void | HAL_SYSCFG_EnableClampingDiode (uint32_t PinConfig)
Enable Clamping Diode on specified IO.
void | HAL_SYSCFG_DisableClampingDiode (uint32_t PinConfig)
Disable Clamping Diode on specified IO.
void | HAL_SYSCFG_StrobeDBattpinsConfig (uint32_t ConfigDeadBattery)
Strobe configuration of GPIO depending on UCPDx dead battery settings.

Detailed Description

SYSCFG configuration functions.

 ===============================================================================
                      ##### HAL SYSCFG configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Enable/Disable Pin remap
      (+) Configure the Voltage reference buffer
      (+) Enable/Disable the Voltage reference buffer
      (+) Enable/Disable the I/O analog switch voltage booster
      (+) Enable/Disable dead battery behavior(*)
      (+) Configure Clamping Diode on specific pins(*)
   (*) Feature not available on all devices

Function Documentation

void HAL_SYSCFG_DisableClampingDiode ( uint32_t PinConfig )

Disable Clamping Diode on specified IO.

Parameters:
PinConfig specifies on which pins clamping Diode has to be disabled This parameter can be any combination of the following values:
  • Clamping Diode
Return values:
None

Definition at line 717 of file stm32g0xx_hal.c.

References assert_param, and IS_SYSCFG_CLAMPINGDIODE.

void HAL_SYSCFG_DisableIOAnalogSwitchBooster ( void )

Disable the I/O analog switch voltage booster.

Return values:
None

Definition at line 660 of file stm32g0xx_hal.c.

void HAL_SYSCFG_DisableRemap ( uint32_t PinRemap )

Disable the remap on PA11_PA12.

Parameters:
PinRemap specifies which pins will behave normally This parameter can be any combination of the following values:
  • SYSCFG_REMAP_PA11
  • SYSCFG_REMAP_PA12
Return values:
None

Definition at line 688 of file stm32g0xx_hal.c.

References assert_param, and IS_HAL_REMAP_PIN.

void HAL_SYSCFG_DisableVREFBUF ( void )

Disable the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 641 of file stm32g0xx_hal.c.

void HAL_SYSCFG_EnableClampingDiode ( uint32_t PinConfig )

Enable Clamping Diode on specified IO.

Parameters:
PinConfig specifies on which pins clamping Diode has to be enabled This parameter can be any combination of the following values:
  • Clamping Diode
Return values:
None

Definition at line 703 of file stm32g0xx_hal.c.

References assert_param, and IS_SYSCFG_CLAMPINGDIODE.

void HAL_SYSCFG_EnableIOAnalogSwitchBooster ( void )

Enable the I/O analog switch voltage booster.

Return values:
None

Definition at line 651 of file stm32g0xx_hal.c.

void HAL_SYSCFG_EnableRemap ( uint32_t PinRemap )

Enable the remap on PA11_PA12.

Parameters:
PinRemap specifies which pins have to be remapped This parameter can be any combination of the following values:
  • SYSCFG_REMAP_PA11
  • SYSCFG_REMAP_PA12
Return values:
None

Definition at line 673 of file stm32g0xx_hal.c.

References assert_param, and IS_HAL_REMAP_PIN.

HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF ( void )

Enable the Internal Voltage Reference buffer (VREFBUF).

Return values:
HAL_OK/HAL_TIMEOUT

Definition at line 615 of file stm32g0xx_hal.c.

References HAL_GetTick(), and VREFBUF_TIMEOUT_VALUE.

void HAL_SYSCFG_StrobeDBattpinsConfig ( uint32_t ConfigDeadBattery )

Strobe configuration of GPIO depending on UCPDx dead battery settings.

Parameters:
ConfigDeadBattery specifies on which pins to make effective or not Dead Battery sw configuration This parameter can be any combination of the following values:
  • SYSCFG_UCPD1_STROBE
  • SYSCFG_UCPD2_STROBE
Return values:
None

Definition at line 734 of file stm32g0xx_hal.c.

References assert_param, and IS_SYSCFG_DBATT_CONFIG.

void HAL_SYSCFG_VREFBUF_HighImpedanceConfig ( uint32_t Mode )

Configure the internal voltage reference buffer high impedance mode.

Parameters:
Mode specifies the high impedance mode This parameter can be one of the following values:
  • VREFBUF High Impedance
Return values:
None

Definition at line 586 of file stm32g0xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE.

void HAL_SYSCFG_VREFBUF_TrimmingConfig ( uint32_t TrimmingValue )

Tune the Internal Voltage Reference buffer (VREFBUF).

Note:
VrefBuf voltage scale is calibrated in production for each device, using voltage scale 1. This calibration value is loaded as default trimming value at device power up. This trimming value can be fine tuned for voltage scales 0 and 1 using this function.
Return values:
None

Definition at line 603 of file stm32g0xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_TRIMMING.

void HAL_SYSCFG_VREFBUF_VoltageScalingConfig ( uint32_t VoltageScaling )

Configure the internal voltage reference buffer voltage scale.

Parameters:
VoltageScaling specifies the output voltage to achieve This parameter can be one of the following values:
  • VREFBUF Voltage Scale
Return values:
None

Definition at line 571 of file stm32g0xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_VOLTAGE_SCALE.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC | ADC Private Macros

Defines

#define | ADC_ENABLE_TIMEOUT (2UL)
#define | ADC_DISABLE_TIMEOUT (2UL)
#define | ADC_STOP_CONVERSION_TIMEOUT (2UL)
#define | ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL)
#define | ADC_CHSELR_SQ2_TO_SQ8
#define | ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
#define | ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */

Define Documentation

#define ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL)

Definition at line 313 of file stm32g0xx_hal_adc.c.

#define ADC_CHSELR_SQ2_TO_SQ8
Value:
(ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \
                                         ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)

Definition at line 316 of file stm32g0xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_DISABLE_TIMEOUT (2UL)

Definition at line 311 of file stm32g0xx_hal_adc.c.

Referenced by ADC_Disable().

#define ADC_ENABLE_TIMEOUT (2UL)

Definition at line 310 of file stm32g0xx_hal_adc.c.

Referenced by ADC_Enable().

#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)

Definition at line 1039 of file stm32g0xx_hal_adc.h.

#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */

Definition at line 1041 of file stm32g0xx_hal_adc.h.

#define ADC_STOP_CONVERSION_TIMEOUT (2UL)

Definition at line 312 of file stm32g0xx_hal_adc.c.

Referenced by ADC_ConversionStop().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC

Functions

static void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.

Function Documentation

HAL_StatusTypeDef ADC_ConversionStop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped to disable the ADC.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2635 of file stm32g0xx_hal_adc.c.

References ADC_STOP_CONVERSION_TIMEOUT, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_IsDisableOngoing(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StopConversion(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), and HAL_ADC_Stop_IT().

HAL_StatusTypeDef ADC_Disable ( ADC_HandleTypeDef * hadc )

Disable the selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2780 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_DISABLE_TIMEOUT, ADC_FLAG_EOSMP, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_Disable(), LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), and HAL_ADCEx_Calibration_Start().

static void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2842 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, ADC_FLAG_EOS, ADC_IT_EOC, ADC_IT_EOS, ADC_STATE_CLR_SET, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::DMA_Handle, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsTriggerSourceSWStart(), __ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADC_Start_DMA().

static void ADC_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2938 of file stm32g0xx_hal_adc.c.

References __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA().

static void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2920 of file stm32g0xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvHalfCpltCallback, and HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA().

HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc )

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2689 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, ADC_ENABLE_TIMEOUT, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US, LL_ADC_Enable(), LL_ADC_GetCommonPathInternalCh(), LL_ADC_IsEnabled(), LL_ADC_PATH_INTERNAL_TEMPSENSOR, ADC_InitTypeDef::LowPowerAutoPowerOff, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

ADC Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.

Detailed Description

ADC Initialization and Configuration functions.

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.

Note:
For devices with several ADCs: reset of ADC common registers is done only if all ADCs sharing the same common group are disabled. (function "HAL_ADC_MspDeInit()" is also called under the same conditions: all ADC instances use the same core clock at RCC level, disabling the core clock reset all ADC instances). If this is not the case, reset of these common parameters reset is bypassed without error reporting: it can be the intended behavior in case of reset of a single ADC while the other ADCs sharing the same common group is still running.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 726 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, ADC_CLEAR_ERRORCODE, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_OVR, ADC_FLAG_RDY, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_OVR, ADC_IT_RDY, __ADC_HandleTypeDef::ADCGroupRegularSequencerRanks, assert_param, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::Instance, LL_ADC_DisableInternalRegulator(), __ADC_HandleTypeDef::MspDeInitCallback, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level (refer to description of RCC configuration for ADC in header of this file).
Possibility to update parameters on the fly: This function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 378 of file stm32g0xx_hal_adc.c.

References ADC_CFGR1_AUTOOFF, ADC_CFGR1_AUTOWAIT, ADC_CFGR1_CONTINUOUS, ADC_CFGR1_DMACONTREQ, ADC_CFGR1_OVERRUN, ADC_CHSELR_SQ2_TO_SQ8, ADC_CLEAR_ERRORCODE, ADC_CLOCK_SYNC_PCLK_DIV1, ADC_CLOCK_SYNC_PCLK_DIV2, ADC_CLOCK_SYNC_PCLK_DIV4, ADC_REGULAR_RANK_2, ADC_SCAN_DISABLE, ADC_SCAN_ENABLE, ADC_SCAN_SEQ_MODE, ADC_SOFTWARE_START, ADC_STATE_CLR_SET, __ADC_HandleTypeDef::ADCGroupRegularSequencerRanks, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::DMAContinuousRequests, __ADC_HandleTypeDef::EndOfSamplingCallback, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ConvCpltCallback(), HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_RESET, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_CLOCKPRESCALER, IS_ADC_DATA_ALIGN, IS_ADC_EOC_SELECTION, IS_ADC_EXTTRIG, IS_ADC_EXTTRIG_EDGE, IS_ADC_OVERRUN, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_REGULAR_NB_CONV, IS_ADC_RESOLUTION, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SAMPLE_TIME, IS_ADC_SCAN_MODE, IS_ADC_TRIGGER_FREQ, IS_ADC_TRIGGERED_OVERSAMPLING_MODE, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, LL_ADC_DELAY_INTERNAL_REGUL_STAB_US, LL_ADC_EnableInternalRegulator(), LL_ADC_GetSamplingTimeCommonChannels(), LL_ADC_IsEnabled(), LL_ADC_IsInternalRegulatorEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SAMPLINGTIME_COMMON_1, LL_ADC_SAMPLINGTIME_COMMON_2, LL_ADC_SetSamplingTimeCommonChannels(), __ADC_HandleTypeDef::Lock, ADC_InitTypeDef::LowPowerAutoPowerOff, ADC_InitTypeDef::LowPowerAutoWait, __ADC_HandleTypeDef::MspInitCallback, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::Overrun, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_OversamplingTypeDef::Ratio, ADC_InitTypeDef::Resolution, ADC_OversamplingTypeDef::RightBitShift, ADC_InitTypeDef::SamplingTimeCommon1, ADC_InitTypeDef::SamplingTimeCommon2, ADC_InitTypeDef::ScanConvMode, __ADC_HandleTypeDef::State, ADC_OversamplingTypeDef::TriggeredMode, and ADC_InitTypeDef::TriggerFrequencyMode.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitialize the ADC MSP.

Parameters:
hadc ADC handle
Note:
All ADC instances use the same core clock at RCC level, disabling the core clock reset all ADC instances).
Return values:
None

Definition at line 869 of file stm32g0xx_hal_adc.c.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initialize the ADC MSP.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 852 of file stm32g0xx_hal_adc.c.

Referenced by HAL_ADC_Init(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADC_RegisterCallback | ( | ADC_HandleTypeDef * | hadc,
 |  | HAL_ADC_CallbackIDTypeDef | CallbackID,
 |  | pADC_CallbackTypeDef | pCallback
 | ) |  |

Register a User ADC Callback To be used instead of the weak predefined callback.

Parameters:
hadc | Pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  • HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  • HAL_ADC_ERROR_CB_ID ADC error callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  • HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  • HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  • HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
  • HAL_ADC_MSPINIT_CB_ID MspInit callback ID
  • HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 901 of file stm32g0xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_CONVERSION_COMPLETE_CB_ID, HAL_ADC_CONVERSION_HALF_CB_ID, HAL_ADC_END_OF_SAMPLING_CB_ID, HAL_ADC_ERROR_CB_ID, HAL_ADC_ERROR_INVALID_CALLBACK, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID, HAL_ADC_MSPDEINIT_CB_ID, HAL_ADC_MSPINIT_CB_ID, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, __ADC_HandleTypeDef::MspDeInitCallback, __ADC_HandleTypeDef::MspInitCallback, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_UnRegisterCallback | ( | ADC_HandleTypeDef * | hadc,
 |  | HAL_ADC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.

Parameters:
hadc Pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  • HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  • HAL_ADC_ERROR_CB_ID ADC error callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  • HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  • HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  • HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
  • HAL_ADC_MSPINIT_CB_ID MspInit callback ID
  • HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 1016 of file stm32g0xx_hal_adc.c.

References __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_CONVERSION_COMPLETE_CB_ID, HAL_ADC_CONVERSION_HALF_CB_ID, HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_END_OF_SAMPLING_CB_ID, HAL_ADC_ERROR_CB_ID, HAL_ADC_ERROR_INVALID_CALLBACK, HAL_ADC_ErrorCallback(), HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID, HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspDeInit(), HAL_ADC_MSPDEINIT_CB_ID, HAL_ADC_MspInit(), HAL_ADC_MSPINIT_CB_ID, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, __ADC_HandleTypeDef::MspDeInitCallback, __ADC_HandleTypeDef::MspInitCallback, and __ADC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Input and Output operation functions

Functions
ADC Input and Output operation functions
ADC Exported Functions

ADC IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Detailed Description

ADC IO operation functions.

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion complete callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2056 of file stm32g0xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion DMA half-transfer callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2071 of file stm32g0xx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt(), HAL_ADC_Init(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Note:
In case of error due to overrun when using ADC with DMA transfer (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
  • Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
  • If needed, restart a new ADC conversion using function "HAL_ADC_Start_DMA()" (this function is also clearing overrun flag)
Parameters:
hadc ADC handle
Return values:
None

Definition at line 2108 of file stm32g0xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Note:
Reading register DR automatically clears ADC flag EOC (ADC group regular end of unitary conversion).
This function does not clear ADC flag EOS (ADC group regular end of sequence conversion). Occurrence of flag EOS rising:
  • If sequencer is composed of 1 rank, flag EOS is equivalent to flag EOC.
  • If sequencer is composed of several ranks, during the scan sequence flag EOC only is raised, at the end of the scan sequence both flags EOC and EOS are raised. To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADC_PollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
Parameters:
hadc ADC handle
Return values:
ADC group regular conversion data

Definition at line 1829 of file stm32g0xx_hal_adc.c.

References assert_param, and __ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handle ADC interrupt request.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1846 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_CCRDY, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_OVR, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_CCRDY, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_OVR, ADC_OVR_DATA_PRESERVED, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ERROR_OVR, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADCEx_ChannelConfigReadyCallback(), HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_EOC_SELECTION, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, LL_ADC_REG_DMA_TRANSFER_NONE, LL_ADC_REG_GetDMATransfer(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsTriggerSourceSWStart(), ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog 1 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2086 of file stm32g0xx_hal_adc.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Note:
ADC conversion flags EOS (end of sequence) and EOC (end of conversion) are cleared by this function, with an exception: if low power feature "LowPowerAutoWait" is enabled, flags are not cleared to not interfere with this feature until data register is read using function HAL_ADC_GetValue().
This function cannot be used in a particular setup: ADC configured in DMA mode and polling for end of each conversion (ADC init parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. Nevertheless, polling can still be performed on the complete sequence (ADC init parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 1254 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_IT_EOC, ADC_IT_EOS, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsTriggerSourceSWStart(), ADC_InitTypeDef::LowPowerAutoWait, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for ADC event.

Parameters:
hadc | ADC handle
EventType the ADC event type. This parameter can be one of the following values:
  • ADC_EOSMP_EVENT ADC End of Sampling event
  • ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
  • ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
  • ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
  • ADC_OVR_EVENT ADC Overrun event
Timeout | Timeout value in millisecond.
Note:
The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. Indeed, the latter is reset only if hadc->Init.Overrun field is set to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten by a new converted data as soon as OVR is cleared. To reset OVR flag once the preserved data is retrieved, the user can resort to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
Return values:
HAL status

Definition at line 1384 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_AWD2_EVENT, ADC_AWD3_EVENT, ADC_AWD_EVENT, ADC_EOSMP_EVENT, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOSMP, ADC_FLAG_OVR, ADC_OVR_DATA_PRESERVED, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group.

Note:
Interruptions enabled in this function: None.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1136 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start conversion of regular group and transfer result through DMA.

Note:
Interruptions enabled in this function: overrun (if applicable), DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
Parameters:
hadc | ADC handle
pData | Destination Buffer address.
Length | Number of data to be transferred from ADC peripheral to memory
Return values:
HAL status.

Definition at line 1652 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), __ADC_HandleTypeDef::Instance, LL_ADC_Disable(), LL_ADC_IsEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), __ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : EOC (end of conversion), EOS (end of sequence), OVR overrun. Each of these interruptions has its dedicated callback function.
To guarantee a proper reset of all interruptions once all the needed conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure a correct stop of the IT-based conversions.
By default, HAL_ADC_Start_IT() does not enable the End Of Sampling interruption. If required (e.g. in case of oversampling with trigger mode), the user must: 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) before calling HAL_ADC_Start_IT().
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1514 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_OVR_DATA_PRESERVED, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1203 of file stm32g0xx_hal_adc.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1748 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_DMA_STATE_BUSY, __ADC_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1605 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
Configure the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | pAnalogWDGConfig
 | ) |  |

Configure the analog watchdog.

Note:
Possibility to update parameters on the fly: This function initializes the selected analog watchdog, successive calls to this function can be used to reconfigure some parameters of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_AnalogWDGConfTypeDef".
On this STM32 series, analog watchdog thresholds can be modified while ADC conversion is on going. In this case, some constraints must be taken into account: the programmed threshold values are effective from the next ADC EOC (end of unitary conversion). Considering that registers write delay may happen due to bus activity, this might cause an uncertainty on the effective timing of the new programmed threshold values.
Parameters:
hadc | ADC handle
pAnalogWDGConfig | Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 2361 of file stm32g0xx_hal_adc.c.

References __LL_ADC_ANALOGWD_CHANNEL_GROUP, __LL_ADC_CHANNEL_TO_DECIMAL_NB, ADC_ANALOGWATCHDOG_1, ADC_ANALOGWATCHDOG_2, ADC_ANALOGWATCHDOG_ALL_REG, ADC_ANALOGWATCHDOG_SINGLE_REG, ADC_AWD1THRESHOLD_SHIFT_RESOLUTION, ADC_Disable(), ADC_Enable(), ADC_GET_RESOLUTION, ADC_RESOLUTION_12B, assert_param, ADC_AnalogWDGConfTypeDef::Channel, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, ADC_AnalogWDGConfTypeDef::HighThreshold, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG_MODE, IS_ADC_ANALOG_WATCHDOG_NUMBER, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG, LL_ADC_AWD_DISABLE, LL_ADC_ClearFlag_AWD1(), LL_ADC_ClearFlag_AWD2(), LL_ADC_ClearFlag_AWD3(), LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_DisableIT_AWD1(), LL_ADC_DisableIT_AWD2(), LL_ADC_DisableIT_AWD3(), LL_ADC_EnableIT_AWD1(), LL_ADC_EnableIT_AWD2(), LL_ADC_EnableIT_AWD3(), LL_ADC_GROUP_REGULAR, LL_ADC_IsEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetAnalogWDMonitChannels(), ADC_AnalogWDGConfTypeDef::LowThreshold, ADC_InitTypeDef::OversamplingMode, __ADC_HandleTypeDef::State, ADC_AnalogWDGConfTypeDef::WatchdogMode, and ADC_AnalogWDGConfTypeDef::WatchdogNumber.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | pConfig
 | ) |  |

Configure a channel to be assigned to ADC group regular.

Note:
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: This function initializes channel into ADC group regular, following calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc | ADC handle
pConfig | Structure of ADC channel assigned to ADC group regular.
Return values:
HAL status

Definition at line 2154 of file stm32g0xx_hal_adc.c.

References __LL_ADC_CHANNEL_TO_DECIMAL_NB, __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_CHANNEL_INTERNAL, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_RANK_NONE, ADC_SCAN_SEQ_FIXED, ADC_SCAN_SEQ_FIXED_BACKWARD, __ADC_HandleTypeDef::ADCGroupRegularSequencerRanks, assert_param, ADC_ChannelConfTypeDef::Channel, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_REGULAR_NB_CONV, IS_ADC_REGULAR_RANK, IS_ADC_REGULAR_RANK_SEQ_FIXED, IS_ADC_SAMPLING_TIME_COMMON, LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_GetCommonPathInternalCh(), LL_ADC_PATH_INTERNAL_TEMPSENSOR, LL_ADC_PATH_INTERNAL_VBAT, LL_ADC_PATH_INTERNAL_VREFINT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_SetSequencerChAdd(), LL_ADC_REG_SetSequencerChRem(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetCommonPathInternalCh(), ADC_InitTypeDef::NbrOfConversion, ADC_ChannelConfTypeDef::Rank, ADC_ChannelConfTypeDef::SamplingTime, ADC_InitTypeDef::ScanConvMode, and __ADC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral state and errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc ADC handle
Return values:
ADC error code (bitfield on 32 bits)

Definition at line 2608 of file stm32g0xx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::ErrorCode, and __ADC_HandleTypeDef::Instance.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

Return the ADC handle state.

Note:
ADC state machine is managed by bitfields, ADC status must be compared with states bits. For example: " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
Parameters:
hadc ADC handle
Return values:
ADC handle state (bitfield on 32 bits)

Definition at line 2594 of file stm32g0xx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC States

Defines
ADC States
ADC Exported Types

Defines

#define | HAL_ADC_STATE_RESET (0x00000000UL)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001UL)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004UL)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100UL)
#define | HAL_ADC_STATE_REG_EOC (0x00000200UL)
#define | HAL_ADC_STATE_REG_OVR (0x00000400UL)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000UL)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
#define | HAL_ADC_STATE_AWD1 (0x00010000UL)
#define | HAL_ADC_STATE_AWD2 (0x00020000UL)
#define | HAL_ADC_STATE_AWD3 (0x00040000UL)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)

Define Documentation

#define HAL_ADC_STATE_AWD1 (0x00010000UL)

Out-of-window occurrence of ADC analog watchdog 1

Definition at line 345 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 (0x00020000UL)

Out-of-window occurrence of ADC analog watchdog 2

Definition at line 346 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD3 (0x00040000UL)

Out-of-window occurrence of ADC analog watchdog 3

Definition at line 347 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)

ADC is busy due to an internal process (initialization, calibration)

Definition at line 323 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)

Configuration error occurrence

Definition at line 328 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_Calibration_SetValue().

#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL)

DMA error occurrence

Definition at line 329 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), and HAL_ADC_Stop_DMA().

#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)

Internal error occurrence

Definition at line 327 of file stm32g0xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL)

Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 339 of file stm32g0xx_hal_adc.h.

#define HAL_ADC_STATE_INJ_EOC (0x00002000UL)

Not available on this STM32 series: Conversion data available on group injected

Definition at line 341 of file stm32g0xx_hal_adc.h.

#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)

Not available on this STM32 series: Injected queue overflow occurrence

Definition at line 342 of file stm32g0xx_hal_adc.h.

#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)

Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available)

Definition at line 350 of file stm32g0xx_hal_adc.h.

#define HAL_ADC_STATE_READY (0x00000001UL)

ADC peripheral ready for use

Definition at line 322 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_UnRegisterCallback(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_REG_BUSY (0x00000100UL)

A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 332 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_REG_EOC (0x00000200UL)

Conversion data available on group regular

Definition at line 334 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL)

Not available on this STM32 series: End Of Sampling flag raised

Definition at line 336 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_REG_OVR (0x00000400UL)

Overrun occurrence

Definition at line 335 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_RESET (0x00000000UL)

HAL ADC state machine: ADC states definition (bitfields)

Note:
ADC state machine is managed by bitfields, state must be compared with bit by bit. For example: " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " ADC not yet initialized or disabled

Definition at line 321 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

#define HAL_ADC_STATE_TIMEOUT (0x00000004UL)

TimeOut occurrence

Definition at line 324 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), and HAL_ADC_PollForEvent().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Exported Types

Data Structures | Modules | Typedefs | Enumerations
ADC Exported Types
ADC

Data Structures

struct | ADC_OversamplingTypeDef
ADC group regular oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...
struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Modules

ADC States

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.
typedef void(* | pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.

Enumerations

enum HAL_ADC_CallbackIDTypeDef {
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U,
HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, HAL_ADC_MSPINIT_CB_ID = 0x09U,
HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
}
HAL ADC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __ADC_HandleTypeDef ADC_HandleTypeDef

ADC handle Structure definition.

typedef void(* pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc)

HAL ADC Callback pointer definition.

pointer to a ADC callback function

Definition at line 407 of file stm32g0xx_hal_adc.h.

Enumeration Type Documentation

enum HAL_ADC_CallbackIDTypeDef

HAL ADC Callback ID enumeration definition.

Enumerator:
HAL_ADC_CONVERSION_COMPLETE_CB_ID

ADC conversion complete callback ID

HAL_ADC_CONVERSION_HALF_CB_ID

ADC conversion DMA half-transfer callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID

ADC analog watchdog 1 callback ID

HAL_ADC_ERROR_CB_ID

ADC error callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID

ADC analog watchdog 2 callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID

ADC analog watchdog 3 callback ID

HAL_ADC_END_OF_SAMPLING_CB_ID

ADC end of sampling callback ID

HAL_ADC_MSPINIT_CB_ID

ADC Msp Init callback ID

HAL_ADC_MSPDEINIT_CB_ID

ADC Msp DeInit callback ID

Definition at line 391 of file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC_OversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_OversamplingTypeDef Struct Reference
ADC Exported Types

ADC group regular oversampling structure definition. More...

#include <stm32g0xx_hal_adc.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift
uint32_t | TriggeredMode

Detailed Description

ADC group regular oversampling structure definition.

Definition at line 49 of file stm32g0xx_hal_adc.h.

Field Documentation

uint32_t ADC_OversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value of Oversampling - Ratio

Definition at line 51 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of Oversampling - Data shift

Definition at line 54 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::TriggeredMode

Selects the regular triggered oversampling mode. This parameter can be a value of Oversampling - Discontinuous mode

Definition at line 57 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_adc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC instance and ADC group regular. More...

#include <stm32g0xx_hal_adc.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | Resolution
uint32_t | DataAlign
uint32_t | ScanConvMode
uint32_t | EOCSelection
FunctionalState | LowPowerAutoWait
FunctionalState | LowPowerAutoPowerOff
FunctionalState | ContinuousConvMode
uint32_t | NbrOfConversion
FunctionalState | DiscontinuousConvMode
uint32_t | ExternalTrigConv
uint32_t | ExternalTrigConvEdge
FunctionalState | DMAContinuousRequests
uint32_t | Overrun
uint32_t | SamplingTimeCommon1
uint32_t | SamplingTimeCommon2
FunctionalState | OversamplingMode
ADC_OversamplingTypeDef Oversampling
uint32_t | TriggerFrequencyMode

Detailed Description

Structure definition of ADC instance and ADC group regular.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait.
  • Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 77 of file stm32g0xx_hal_adc.h.

Field Documentation

uint32_t ADC_InitTypeDef::ClockPrescaler

Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of ADC common - Clock source. Note: The ADC clock configuration is common to all ADC instances. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled.

Definition at line 79 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::ContinuousConvMode

Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 136 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

uint32_t ADC_InitTypeDef::DataAlign

Specify ADC data alignment in conversion data register (right or left). Refer to reference manual for alignments formats versus resolutions. This parameter can be a value of ADC conversion data alignment

Definition at line 91 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::DiscontinuousConvMode

Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one.

Definition at line 152 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::DMAContinuousRequests

Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) or in continuous mode (DMA transfer unlimited, whatever number of conversions). This parameter can be set to ENABLE or DISABLE. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.

Definition at line 168 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::EOCSelection

Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of ADC sequencer end of unitary conversion or sequence conversions.

Definition at line 118 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADC_Start_IT().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Select the external event source used to trigger ADC group regular conversion start. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC group regular trigger source. Caution: external trigger source is common to all ADC instances.

Definition at line 159 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConvEdge

Select the external event edge used to trigger ADC group regular conversion start. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of ADC group regular trigger edge (when external trigger is selected)

Definition at line 164 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::LowPowerAutoPowerOff

Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). This parameter can be set to ENABLE or DISABLE.

Definition at line 132 of file stm32g0xx_hal_adc.h.

Referenced by ADC_Enable(), and HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::LowPowerAutoWait

Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) has been retrieved by user software, using function HAL_ADC_GetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.

Definition at line 121 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_PollForConversion().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specify the number of ranks that will be converted within the regular group sequencer. This parameter is dependent on ScanConvMode:

  • sequencer configured to fully configurable: Number of ranks in the scan sequence is configurable using this parameter. Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
  • sequencer configured to not fully configurable: Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 140 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Overrun

Select the behavior in case of overrun: data overwritten or preserved (default). This parameter can be a value of ADC group regular - Overrun behavior on conversion data. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode:

  • Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
  • Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register).

Definition at line 173 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

ADC_OversamplingTypeDef ADC_InitTypeDef::Oversampling

Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled.

Definition at line 205 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::OversamplingMode

Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular.

Definition at line 201 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Resolution

Configure the ADC resolution. This parameter can be a value of ADC instance - Resolution

Definition at line 88 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::SamplingTimeCommon1

Set sampling time common to a group of channels. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. This parameter can be a value of Channel - Sampling time Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds).

Definition at line 183 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::SamplingTimeCommon2

Set sampling time common to a group of channels, second common setting possible. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. This parameter can be a value of Channel - Sampling time Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds).

Definition at line 192 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configure the sequencer of ADC group regular. On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available:

  • sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable.
    • Sequence length: Set number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
  • sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number.
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): If only 1 channel is set: Conversion is performed in single mode. If several channels are set: Conversions are performed in sequence mode. This parameter can be a value of ADC sequencer scan mode

Definition at line 95 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::TriggerFrequencyMode

Set ADC trigger frequency mode. This parameter can be a value of ADC group regular - Trigger frequency mode. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". Note: When ADC trigger frequency mode is set to low frequency, some rearm cycles are inserted before performing ADC conversion start, inducing a delay of 2 ADC clock cycles.

Definition at line 208 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_adc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32g0xx_hal_adc.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled or enabled without conversion on going on regular group. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 230 of file stm32g0xx_hal_adc.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specify the channel to configure into ADC regular group. This parameter can be a value of ADC instance - Channel number Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability.

Definition at line 232 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Rank

Add or remove the channel from ADC regular group sequencer and specify its conversion rank. This parameter is dependent on ScanConvMode:

  • sequencer configured to fully configurable: Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.
  • sequencer configured to not fully configurable: rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. This parameter can be a value of ADC group regular - Sequencer ranks

Definition at line 236 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of ADC instance - Sampling time common to a group of channels Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings.

Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values.

Definition at line 247 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_adc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC analog watchdog. More...

#include <stm32g0xx_hal_adc.h>

Data Fields

uint32_t | WatchdogNumber
uint32_t | WatchdogMode
uint32_t | Channel
FunctionalState | ITMode
uint32_t | HighThreshold
uint32_t | LowThreshold

Detailed Description

Structure definition of ADC analog watchdog.

Note:
The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. ADC state can be either:
  • For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular.
  • For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular.

Definition at line 267 of file stm32g0xx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of ADC instance - Channel number.

Definition at line 279 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).

Definition at line 287 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

FunctionalState ADC_AnalogWDGConfTypeDef::ITMode

Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 284 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).

Definition at line 297 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configure the ADC analog watchdog mode: single/all/none channels. For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular. For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. This parameter can be a value of ADC Analog Watchdog Mode.

Definition at line 274 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of Analog watchdog - Analog watchdog number.

Definition at line 269 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_adc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__ADC_HandleTypeDef Struct Reference
ADC Exported Types

ADC handle Structure definition. More...

#include <stm32g0xx_hal_adc.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
uint32_t | ADCGroupRegularSequencerRanks
void(* | ConvCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | ConvHalfCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindowCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | ErrorCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindow2Callback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindow3Callback )(struct __ADC_HandleTypeDef *hadc)
void(* | EndOfSamplingCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | MspInitCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | MspDeInitCallback )(struct __ADC_HandleTypeDef *hadc)

Detailed Description

ADC handle Structure definition.

Definition at line 361 of file stm32g0xx_hal_adc.h.

Field Documentation

uint32_t __ADC_HandleTypeDef::ADCGroupRegularSequencerRanks

ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode')

Definition at line 373 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), and HAL_ADC_Init().

void(* __ADC_HandleTypeDef::ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC conversion complete callback

Definition at line 375 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC conversion DMA half-transfer callback

Definition at line 376 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAHalfConvCplt(), HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

DMA_HandleTypeDef* __ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 368 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Start_DMA(), and HAL_ADC_Stop_DMA().

void(* __ADC_HandleTypeDef::EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc)

ADC end of sampling callback

Definition at line 381 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::ErrorCallback)(struct __ADC_HandleTypeDef *hadc)

ADC error callback

Definition at line 378 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

__IO uint32_t __ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 371 of file stm32g0xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_GetError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_RegisterCallback(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_SetValue(), and HAL_ADCEx_Calibration_Start().

ADC_InitTypeDef __ADC_HandleTypeDef::Init

ADC initialization parameters and regular conversions setting

Definition at line 367 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

ADC_TypeDef* __ADC_HandleTypeDef::Instance

Register base address

Definition at line 366 of file stm32g0xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), and HAL_ADCEx_DisableVoltageRegulator().

void(* __ADC_HandleTypeDef::LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 2 callback

Definition at line 379 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 3 callback

Definition at line 380 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 1 callback

Definition at line 377 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

HAL_LockTypeDef __ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 369 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

void(* __ADC_HandleTypeDef::MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc)

ADC Msp DeInit callback

Definition at line 383 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::MspInitCallback)(struct __ADC_HandleTypeDef *hadc)

ADC Msp Init callback

Definition at line 382 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

__IO uint32_t __ADC_HandleTypeDef::State

ADC communication state (bitmap of ADC states)

Definition at line 370 of file stm32g0xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_SetValue(), and HAL_ADCEx_Calibration_Start().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_adc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)

Define Documentation

#define HAL_ADC_ERROR_DMA (0x04U)

DMA transfer error

Definition at line 429 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAError().

#define HAL_ADC_ERROR_INTERNAL (0x01U)

ADC peripheral internal error (problem of clocking, enable/disable, erroneous state, ...)

Definition at line 426 of file stm32g0xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADCEx_Calibration_SetValue(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)

Invalid Callback error

Definition at line 431 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

#define HAL_ADC_ERROR_NONE (0x00U)

No error

Definition at line 425 of file stm32g0xx_hal_adc.h.

#define HAL_ADC_ERROR_OVR (0x02U)

Overrun error

Definition at line 428 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define | ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
#define | ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
#define | ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
#define | ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
#define | ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
#define | ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
#define | ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
#define | ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
#define | ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
#define | ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
#define | ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
#define | ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)

Define Documentation

#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)

ADC asynchronous clock without prescaler

Definition at line 444 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)

ADC asynchronous clock with prescaler division by 10

Definition at line 449 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)

ADC asynchronous clock with prescaler division by 12

Definition at line 450 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)

ADC asynchronous clock with prescaler division by 128

Definition at line 454 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)

ADC asynchronous clock with prescaler division by 16

Definition at line 451 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)

ADC asynchronous clock with prescaler division by 2

Definition at line 445 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)

ADC asynchronous clock with prescaler division by 256

Definition at line 455 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)

ADC asynchronous clock with prescaler division by 32

Definition at line 452 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)

ADC asynchronous clock with prescaler division by 4

Definition at line 446 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)

ADC asynchronous clock with prescaler division by 6

Definition at line 447 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)

ADC asynchronous clock with prescaler division by 64

Definition at line 453 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)

ADC asynchronous clock with prescaler division by 8

Definition at line 448 of file stm32g0xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)

ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)

Definition at line 440 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)

ADC synchronous clock derived from AHB clock with prescaler division by 2

Definition at line 441 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)

ADC synchronous clock derived from AHB clock with prescaler division by 4

Definition at line 442 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
#define | ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
#define | ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
#define | ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)

Define Documentation

#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)

ADC resolution 10 bits

Definition at line 464 of file stm32g0xx_hal_adc.h.

#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)

ADC resolution 12 bits

Definition at line 463 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)

ADC resolution 6 bits

Definition at line 466 of file stm32g0xx_hal_adc.h.

#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)

ADC resolution 8 bits

Definition at line 465 of file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC conversion data alignment

Defines
ADC conversion data alignment
ADC Exported Constants

Defines

#define | ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)
#define | ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)

Define Documentation

#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)

ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)

Definition at line 475 of file stm32g0xx_hal_adc.h.

#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 474 of file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC sequencer scan mode

Defines
ADC sequencer scan mode
ADC Exported Constants

Defines

#define | ADC_SCAN_DISABLE (0x00000000UL)
#define | ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD)
#define | ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT)
#define | ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR)
#define | ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */
#define | ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */

Define Documentation

#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */

Definition at line 503 of file stm32g0xx_hal_adc.h.

#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */

Definition at line 502 of file stm32g0xx_hal_adc.h.

#define ADC_SCAN_DISABLE (0x00000000UL)

Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks)

Definition at line 496 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD)

Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable.

Definition at line 497 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT)

Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18

Definition at line 499 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR)

Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0

Definition at line 500 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC group regular trigger source

Defines
ADC group regular trigger source
ADC Exported Constants

Defines

#define | ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4)
#define | ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)

Define Documentation

#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)

ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting).

Definition at line 528 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)

ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 526 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4)

ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 514 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 513 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)

ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 516 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)

ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 518 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)

ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 520 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)

ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 523 of file stm32g0xx_hal_adc.h.

#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)

ADC group regular conversion trigger internal: SW start.

Definition at line 512 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC group regular trigger edge (when external trigger is selected)

Defines
ADC group regular trigger edge (when external trigger is selected)
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)

ADC group regular conversion trigger polarity set to falling edge

Definition at line 538 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)

Regular conversions hardware trigger detection disabled

Definition at line 536 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 537 of file stm32g0xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 539 of file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC sequencer end of unitary conversion or sequence conversions

Defines
ADC sequencer end of unitary conversion or sequence conversions
ADC Exported Constants

Defines

#define | ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV (ADC_ISR_EOS)

Define Documentation

#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS)

End of sequence conversions flag

Definition at line 548 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), and HAL_ADC_Start_IT().

#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)

End of unitary conversion flag

Definition at line 547 of file stm32g0xx_hal_adc.h.

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STM32G0C1xx HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
#define | ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)

Define Documentation

#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 557 of file stm32g0xx_hal_adc.h.

#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)

ADC group regular behavior in case of overrun: data preserved

Definition at line 556 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | ADC_RANK_CHANNEL_NUMBER (0x00000001U)
#define | ADC_RANK_NONE (0x00000002U)
#define | ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
#define | ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
#define | ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
#define | ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
#define | ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
#define | ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
#define | ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
#define | ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)

Define Documentation

#define ADC_RANK_CHANNEL_NUMBER (0x00000001U)

Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...)

Definition at line 565 of file stm32g0xx_hal_adc.h.

#define ADC_RANK_NONE (0x00000002U)

Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer

Definition at line 566 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)

ADC group regular sequencer rank 1

Definition at line 568 of file stm32g0xx_hal_adc.h.

#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)

ADC group regular sequencer rank 2

Definition at line 569 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)

ADC group regular sequencer rank 3

Definition at line 570 of file stm32g0xx_hal_adc.h.

#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)

ADC group regular sequencer rank 4

Definition at line 571 of file stm32g0xx_hal_adc.h.

#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)

ADC group regular sequencer rank 5

Definition at line 572 of file stm32g0xx_hal_adc.h.

#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)

ADC group regular sequencer rank 6

Definition at line 573 of file stm32g0xx_hal_adc.h.

#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)

ADC group regular sequencer rank 7

Definition at line 574 of file stm32g0xx_hal_adc.h.

#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)

ADC group regular sequencer rank 8

Definition at line 575 of file stm32g0xx_hal_adc.h.

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STM32G0C1xx HAL User Manual: ADC instance - Sampling time common to a group of channels

Defines
ADC instance - Sampling time common to a group of channels
ADC Exported Constants

Defines

#define | ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1)
#define | ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2)

Define Documentation

#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1)

Set sampling time common to a group of channels: sampling time nb 1

Definition at line 583 of file stm32g0xx_hal_adc.h.

#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2)

Set sampling time common to a group of channels: sampling time nb 2

Definition at line 584 of file stm32g0xx_hal_adc.h.

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STM32G0C1xx HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5)
#define | ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5)
#define | ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5)
#define | ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)
#define | ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5)
#define | ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5)
#define | ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5)
#define | ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5)

Define Documentation

#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)

Sampling time 12.5 ADC clock cycles

Definition at line 595 of file stm32g0xx_hal_adc.h.

#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5)

Sampling time 160.5 ADC clock cycles

Definition at line 599 of file stm32g0xx_hal_adc.h.

#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5)

Sampling time 19.5 ADC clock cycles

Definition at line 596 of file stm32g0xx_hal_adc.h.

#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5)

Sampling time 1.5 ADC clock cycle

Definition at line 592 of file stm32g0xx_hal_adc.h.

#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5)

Sampling time 39.5 ADC clock cycles

Definition at line 597 of file stm32g0xx_hal_adc.h.

#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5)

Sampling time 3.5 ADC clock cycles

Definition at line 593 of file stm32g0xx_hal_adc.h.

#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5)

Sampling time 79.5 ADC clock cycles

Definition at line 598 of file stm32g0xx_hal_adc.h.

#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5)

Sampling time 7.5 ADC clock cycles

Definition at line 594 of file stm32g0xx_hal_adc.h.

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STM32G0C1xx HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
#define | ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
#define | ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
#define | ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
#define | ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
#define | ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
#define | ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
#define | ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
#define | ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
#define | ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
#define | ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
#define | ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
#define | ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
#define | ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
#define | ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
#define | ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
#define | ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
#define | ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
#define | ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
#define | ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
#define | ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)
#define | ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)

Define Documentation

#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 607 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 608 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 617 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 618 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 619 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 620 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 621 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 622 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 623 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 624 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)

ADC external channel (channel connected to GPIO pin) ADCx_IN18

Definition at line 625 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 609 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 610 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 611 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 612 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 613 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 614 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 615 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 616 of file stm32g0xx_hal_adc.h.

#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)

ADC internal channel connected to Temperature sensor.

Definition at line 627 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)

ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda.

Definition at line 628 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)

ADC internal channel connected to VrefInt: Internal voltage reference.

Definition at line 626 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

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STM32G0C1xx HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
#define | ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
#define | ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)

Define Documentation

#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)

ADC analog watchdog number 1

Definition at line 636 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)

ADC analog watchdog number 2

Definition at line 637 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)

ADC analog watchdog number 3

Definition at line 638 of file stm32g0xx_hal_adc.h.

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STM32G0C1xx HAL User Manual: ADC Analog Watchdog Mode

Defines
ADC Analog Watchdog Mode
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN)

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN)

Analog watchdog applied to regular group all channels

Definition at line 648 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL)

No analog watchdog selected

Definition at line 646 of file stm32g0xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN)

Analog watchdog applied to a regular group single channel

Definition at line 647 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

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STM32G0C1xx HAL User Manual: Oversampling - Ratio

Defines
Oversampling - Ratio
ADC Exported Constants

Defines

#define | ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)
#define | ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)
#define | ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)
#define | ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)
#define | ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)
#define | ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)
#define | ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)
#define | ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)

Define Documentation

#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)

ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 662 of file stm32g0xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)

ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 659 of file stm32g0xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)

ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 656 of file stm32g0xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)

ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 663 of file stm32g0xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)

ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 660 of file stm32g0xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)

ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 657 of file stm32g0xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)

ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 661 of file stm32g0xx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)

ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 658 of file stm32g0xx_hal_adc.h.

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STM32G0C1xx HAL User Manual: Oversampling - Data shift

Defines
Oversampling - Data shift
ADC Exported Constants

Defines

#define | ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

Define Documentation

#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)

ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data)

Definition at line 672 of file stm32g0xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)

ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data)

Definition at line 673 of file stm32g0xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)

ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data)

Definition at line 674 of file stm32g0xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)

ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data)

Definition at line 675 of file stm32g0xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)

ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data)

Definition at line 676 of file stm32g0xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)

ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data)

Definition at line 677 of file stm32g0xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)

ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data)

Definition at line 678 of file stm32g0xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data)

Definition at line 679 of file stm32g0xx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)

ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data)

Definition at line 671 of file stm32g0xx_hal_adc.h.

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STM32G0C1xx HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)

Define Documentation

#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger)

Definition at line 688 of file stm32g0xx_hal_adc.h.

#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger)

Definition at line 687 of file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC group regular - Trigger frequency mode

Defines
ADC group regular - Trigger frequency mode
ADC Exported Constants

Defines

#define | ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH)
#define | ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW)

Define Documentation

#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH)

ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle".

Definition at line 696 of file stm32g0xx_hal_adc.h.

#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW)

ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle".

Definition at line 697 of file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Event type

Defines
ADC Event type
ADC Exported Constants

Defines

#define | ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT (ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT (ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT (ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT (ADC_FLAG_OVR)

Define Documentation

#define ADC_AWD1_EVENT (ADC_FLAG_AWD1)

ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series)

Definition at line 706 of file stm32g0xx_hal_adc.h.

#define ADC_AWD2_EVENT (ADC_FLAG_AWD2)

ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series)

Definition at line 707 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_AWD3_EVENT (ADC_FLAG_AWD3)

ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series)

Definition at line 708 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)

ADC End of Sampling event

Definition at line 705 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_OVR_EVENT (ADC_FLAG_OVR)

ADC overrun event

Definition at line 709 of file stm32g0xx_hal_adc.h.

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STM32G0C1xx HAL User Manual: ADC interrupts definition

Defines
ADC interrupts definition
ADC Exported Constants

Defines

#define | ADC_IT_RDY ADC_IER_ADRDYIE
#define | ADC_IT_CCRDY ADC_IER_CCRDYIE
#define | ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | ADC_IT_EOC ADC_IER_EOCIE
#define | ADC_IT_EOS ADC_IER_EOSIE
#define | ADC_IT_OVR ADC_IER_OVRIE
#define | ADC_IT_AWD1 ADC_IER_AWD1IE
#define | ADC_IT_AWD2 ADC_IER_AWD2IE
#define | ADC_IT_AWD3 ADC_IER_AWD3IE

Define Documentation

#define ADC_IT_AWD1 ADC_IER_AWD1IE

ADC Analog watchdog 1 interrupt source (main analog watchdog)

Definition at line 724 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD2 ADC_IER_AWD2IE

ADC Analog watchdog 2 interrupt source (additional analog watchdog)

Definition at line 725 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD3 ADC_IER_AWD3IE

ADC Analog watchdog 3 interrupt source (additional analog watchdog)

Definition at line 726 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_CCRDY ADC_IER_CCRDYIE

ADC channel configuration ready interrupt source

Definition at line 719 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler().

#define ADC_IT_EOC ADC_IER_EOCIE

ADC End of regular conversion interrupt source

Definition at line 721 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), and HAL_ADC_Stop_IT().

#define ADC_IT_EOS ADC_IER_EOSIE

ADC End of regular sequence of conversions interrupt source

Definition at line 722 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), and HAL_ADC_Stop_IT().

#define ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC End of sampling interrupt source

Definition at line 720 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_OVR ADC_IER_OVRIE

ADC overrun interrupt source

Definition at line 723 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), and HAL_ADC_Stop_IT().

#define ADC_IT_RDY ADC_IER_ADRDYIE

ADC Ready interrupt source

Definition at line 718 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC flags definition

Defines
ADC flags definition
ADC Exported Constants

Defines

#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_CCRDY ADC_ISR_CCRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3

Define Documentation

#define ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC Analog watchdog 1 flag

Definition at line 740 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC Analog watchdog 2 flag

Definition at line 741 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC Analog watchdog 3 flag

Definition at line 742 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_CCRDY ADC_ISR_CCRDY

ADC channel configuration ready flag

Definition at line 735 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler().

#define ADC_FLAG_EOC ADC_ISR_EOC

ADC End of Regular Conversion flag

Definition at line 737 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define ADC_FLAG_EOS ADC_ISR_EOS

ADC End of Regular sequence of Conversions flag

Definition at line 738 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC End of Sampling flag

Definition at line 736 of file stm32g0xx_hal_adc.h.

Referenced by ADC_Disable(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_OVR ADC_ISR_OVR

ADC overrun flag

Definition at line 739 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define ADC_FLAG_RDY ADC_ISR_ADRDY

ADC Ready flag

Definition at line 734 of file stm32g0xx_hal_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), and HAL_ADC_DeInit().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Exported Constants

Modules | Defines
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC common - Clock source
ADC instance - Resolution
ADC conversion data alignment
ADC sequencer scan mode
ADC group regular trigger source
ADC group regular trigger edge (when external trigger is selected)
ADC sequencer end of unitary conversion or sequence conversions
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer ranks
ADC instance - Sampling time common to a group of channels
Channel - Sampling time
ADC instance - Channel number
Analog watchdog - Analog watchdog number
ADC Analog Watchdog Mode
Oversampling - Ratio
Oversampling - Data shift
Oversampling - Discontinuous mode
ADC group regular - Trigger frequency mode
ADC Event type
ADC interrupts definition
ADC flags definition

Defines

#define ADC_AWD_EVENT ADC_AWD1_EVENT

Define Documentation

#define ADC_AWD_EVENT ADC_AWD1_EVENT

ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 713 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Regular Conversion Number Verification

Defines
ADC Regular Conversion Number Verification
ADC Private Macros

Defines

#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))

Define Documentation

#define IS_ADC_REGULAR_NB_CONV ( LENGTH ) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))

Definition at line 1026 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADC_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL ADC macro to manage HAL ADC handle, IT and flags.

Defines
HAL ADC macro to manage HAL ADC handle, IT and flags.
ADC Exported Macros

Defines

#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable ADC interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear the specified ADC flag.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR) = (__FLAG__))

Clear the specified ADC flag.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready flag
  • ADC_FLAG_CCRDY ADC channel configuration ready flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
Return values:
None

Definition at line 1167 of file stm32g0xx_hal_adc.h.

Referenced by ADC_Disable(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable ADC interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_CCRDY ADC channel configuration ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
Return values:
None

Definition at line 1110 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), and HAL_ADC_Stop_IT().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable ADC interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_CCRDY ADC channel configuration ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
Return values:
None

Definition at line 1091 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))

Check whether the specified ADC flag is set or not.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready flag
  • ADC_FLAG_CCRDY ADC channel configuration ready flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
Return values:
State of flag (TRUE or FALSE).

Definition at line 1147 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADC_PollForEvent().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC interrupt source to check This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_CCRDY ADC channel configuration ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
Return values:
State of interruption (SET or RESET)

Definition at line 1128 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                                          \
    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
    (__HANDLE__)->MspInitCallback = NULL;                                      \
    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
  } while(0)

Reset ADC handle state.

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 1064 of file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL ADC helper macro

Defines
HAL ADC helper macro
ADC Exported Macros

Defines

#define | __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define | __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define | __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define | __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __HAL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
                              (__ADC_DATA__),\
                              (__ADC_RESOLUTION__))

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 1488 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
                          (__TEMPSENSOR_ADC_DATA__),\
                          (__ADC_RESOLUTION__))

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 series, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1570 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
                                     (__TEMPSENSOR_TYP_CALX_V__),\
                                     (__TEMPSENSOR_CALX_TEMP__),\
                                     (__VREFANALOG_VOLTAGE__),\
                                     (__TEMPSENSOR_ADC_DATA__),\
                                     (__ADC_RESOLUTION__))

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32G0, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1621 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
                                 (__ADC_RESOLUTION__))

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 series, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Analog reference voltage (unit: mV)

Definition at line 1520 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1
  • ADC_CHANNEL_2
  • ADC_CHANNEL_3
  • ADC_CHANNEL_4
  • ADC_CHANNEL_5
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15 (1)
  • ADC_CHANNEL_16 (1)
  • ADC_CHANNEL_17 (1)
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT
  • ADC_CHANNEL_TEMPSENSOR
  • ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
Returned value can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1
  • ADC_CHANNEL_2
  • ADC_CHANNEL_3
  • ADC_CHANNEL_4
  • ADC_CHANNEL_5
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18

Definition at line 1371 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))

Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.

Note:
Example: __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1
  • ADC_CHANNEL_2
  • ADC_CHANNEL_3
  • ADC_CHANNEL_4
  • ADC_CHANNEL_5
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15 (1)
  • ADC_CHANNEL_16 (1)
  • ADC_CHANNEL_17 (1)
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT
  • ADC_CHANNEL_TEMPSENSOR
  • ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 1216 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_COMMON_INSTANCE ( __ADCx__ ) __LL_ADC_COMMON_INSTANCE((__ADCx__))

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 1408 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
                                 (__ADC_RESOLUTION_CURRENT__),\
                                 (__ADC_RESOLUTION_TARGET__))

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data to the requested resolution

Definition at line 1465 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ ) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))

Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.

Note:
Example: __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1
  • ADC_CHANNEL_2
  • ADC_CHANNEL_3
  • ADC_CHANNEL_4
  • ADC_CHANNEL_5
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15 (1)
  • ADC_CHANNEL_16 (1)
  • ADC_CHANNEL_17 (1)
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (2)
  • ADC_CHANNEL_TEMPSENSOR (2)
  • ADC_CHANNEL_VBAT (2)
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
(2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1257 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data full-scale digital value

Definition at line 1444 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): ADC_CHANNEL_1, ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1
  • ADC_CHANNEL_2
  • ADC_CHANNEL_3
  • ADC_CHANNEL_4
  • ADC_CHANNEL_5
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15 (1)
  • ADC_CHANNEL_16 (1)
  • ADC_CHANNEL_17 (1)
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT
  • ADC_CHANNEL_TEMPSENSOR
  • ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1307 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_VREFINT
  • ADC_CHANNEL_TEMPSENSOR
  • ADC_CHANNEL_VBAT
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1395 of file stm32g0xx_hal_adc.h.

#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 1428 of file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Private Macros

Modules | Defines | Functions
ADC Private Macros
ADC

Modules

ADC Regular Conversion Number Verification
ADC Private Constants
ADC Exported Macros
ADC Exported Functions

Defines

#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_GET_RESOLUTION(__HANDLE__) (LL_ADC_GetResolution((__HANDLE__)->Instance))
Return resolution bits in CFGR1 register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U)
Enable ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR1_AUTOOFF(_AUTOOFF_) ((_AUTOOFF_) << 15U)
Enable the ADC auto off mode.
#define | ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U)
Enable the ADC auto delay mode.
#define | ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
Enable ADC continuous conversion mode.
#define | ADC_CFGR1_OVERRUN(_OVERRUN_MODE_)
Enable ADC overrun mode.
#define | ADC_SCAN_SEQ_MODE(_SCAN_MODE_)
Set ADC scan mode with differentiation of sequencer setting fixed or configurable.
#define | ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U)
Enable the ADC DMA continuous request.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
Shift the AWD threshold in function of the selected ADC resolution.
#define | IS_ADC_CLOCKPRESCALER(ADC_CLOCK)
#define | IS_ADC_RESOLUTION(RESOLUTION)
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
#define | IS_ADC_EXTTRIG_EDGE(EDGE)
#define | IS_ADC_EXTTRIG(REGTRIG)
#define | IS_ADC_EOC_SELECTION(EOC_SELECTION)
#define | IS_ADC_OVERRUN(OVR)
#define | IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK)
#define | IS_ADC_REGULAR_RANK(RANK)
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG)
#define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
#define | IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ)
#define | IS_ADC_EVENT_TYPE(EVENT)
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
Verify that a given value is aligned with the ADC resolution range.

Functions

HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.

Define Documentation

#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | _Threshold_
 | ) | ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))

Shift the AWD threshold in function of the selected ADC resolution.

Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2 ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If resolution 6 bits, shift of 6 ranks on the left. therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))

Parameters:
__HANDLE__ | ADC handle
_Threshold_ | Value to be shifted
Return values:
None

Definition at line 875 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_CFGR1_AUTOOFF ( _AUTOOFF_ ) ((_AUTOOFF_) << 15U)

Enable the ADC auto off mode.

Parameters:
_AUTOOFF_ Auto off bit enable or disable.
Return values:
None

Definition at line 805 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR1_AUTOWAIT ( _AUTOWAIT_ ) ((_AUTOWAIT_) << 14U)

Enable the ADC auto delay mode.

Parameters:
_AUTOWAIT_ Auto delay bit enable or disable.
Return values:
None

Definition at line 813 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR1_CONTINUOUS ( _CONTINUOUS_MODE_ ) ((_CONTINUOUS_MODE_) << 13U)

Enable ADC continuous conversion mode.

Parameters:
_CONTINUOUS_MODE_ Continuous mode.
Return values:
None

Definition at line 821 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR1_DMACONTREQ ( _DMACONTREQ_MODE_ ) ((_DMACONTREQ_MODE_) << 1U)

Enable the ADC DMA continuous request.

Parameters:
_DMACONTREQ_MODE_,: DMA continuous request mode.
Return values:
None

Definition at line 860 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR1_OVERRUN ( _OVERRUN_MODE_ )
Value:
( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED)                             \
    )? (ADC_CFGR1_OVRMOD) : (0x00000000UL)                                     \
  )

Enable ADC overrun mode.

Parameters:
_OVERRUN_MODE_ Overrun mode.
Return values:
Overrun bit setting to be programmed into CFGR register

Definition at line 832 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR1_REG_DISCCONTINUOUS ( _REG_DISCONTINUOUS_MODE_ ) ((_REG_DISCONTINUOUS_MODE_) << 16U)

Enable ADC discontinuous conversion mode for regular group.

Parameters:
_REG_DISCONTINUOUS_MODE_,: Regular discontinuous mode.
Return values:
None

Definition at line 797 of file stm32g0xx_hal_adc.h.

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 781 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define ADC_GET_RESOLUTION ( __HANDLE__ ) (LL_ADC_GetResolution((__HANDLE__)->Instance))

Return resolution bits in CFGR1 register RES[1:0] field.

Parameters:
__HANDLE__ ADC handle
Return values:
Value of bitfield RES in CFGR1 register.

Definition at line 773 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_IS_SOFTWARE_START_REGULAR ( __HANDLE__ ) (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL)

Test if conversion trigger of regular group is software start or external trigger.

Parameters:
__HANDLE__ ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 765 of file stm32g0xx_hal_adc.h.

#define ADC_SCAN_SEQ_MODE ( _SCAN_MODE_ )
Value:
( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL                           \
    )?                                                                         \
    ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT))                                \
    :                                                                          \
    (ADC_CFGR1_CHSELRMOD)                                                      \
  )

Set ADC scan mode with differentiation of sequencer setting fixed or configurable.

Parameters:
_SCAN_MODE_ Scan conversion mode.
Return values:
None

Definition at line 847 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clear and set specific bits of the handle State.

Note:
ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 790 of file stm32g0xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), and HAL_ADCEx_Calibration_Start().

#define IS_ADC_ANALOG_WATCHDOG_MODE ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)            )

Definition at line 1001 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_ANALOG_WATCHDOG_NUMBER ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
                                                 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
                                                 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3)   )

Definition at line 997 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == ADC_CHANNEL_0)           || \
                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
                                 ((CHANNEL) == ADC_CHANNEL_17)          || \
                                 ((CHANNEL) == ADC_CHANNEL_18)          || \
                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
                                 ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
                                 ((CHANNEL) == ADC_CHANNEL_VBAT)          )

Definition at line 962 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADC_ConfigChannel().

#define IS_ADC_CLOCKPRESCALER ( ADC_CLOCK )
Value:
(((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1  )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2  )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4  )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6  )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8  )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 )   ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 )  ||\
                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))

Definition at line 878 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_DATA_ALIGN ( ALIGN )
Value:
(((ALIGN) == ADC_DATAALIGN_RIGHT) || \
                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )

Definition at line 899 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EOC_SELECTION ( EOC_SELECTION )
Value:
(((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))

Definition at line 944 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_EVENT_TYPE ( EVENT )
Value:
(((EVENT) == ADC_EOSMP_EVENT) || \
                                  ((EVENT) == ADC_AWD1_EVENT)  || \
                                  ((EVENT) == ADC_AWD2_EVENT)  || \
                                  ((EVENT) == ADC_AWD3_EVENT)  || \
                                  ((EVENT) == ADC_OVR_EVENT)     )

Definition at line 1008 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXTTRIG ( REGTRIG )
Value:
(((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4)   || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO)  || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)  || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO)  || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) || \
                                 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
                                 ((REGTRIG) == ADC_SOFTWARE_START)          )

Definition at line 913 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXTTRIG_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )

Definition at line 907 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_OVERRUN ( OVR )
Value:
(((OVR) == ADC_OVR_DATA_PRESERVED)  || \
                             ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )

Definition at line 947 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RANGE | ( | __RESOLUTION__,
 |  | __ADC_VALUE__
 | ) | ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))

Verify that a given value is aligned with the ADC resolution range.

Parameters:
__RESOLUTION__ | ADC resolution (12, 10, 8 or 6 bits).
__ADC_VALUE__ | value checked against the resolution.
Return values:
SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)

Definition at line 1020 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_REGULAR_RANK ( RANK )
Value:
(((RANK) == ADC_REGULAR_RANK_1 ) || \
                                   ((RANK) == ADC_REGULAR_RANK_2 ) || \
                                   ((RANK) == ADC_REGULAR_RANK_3 ) || \
                                   ((RANK) == ADC_REGULAR_RANK_4 ) || \
                                   ((RANK) == ADC_REGULAR_RANK_5 ) || \
                                   ((RANK) == ADC_REGULAR_RANK_6 ) || \
                                   ((RANK) == ADC_REGULAR_RANK_7 ) || \
                                   ((RANK) == ADC_REGULAR_RANK_8 )   )

Definition at line 953 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_REGULAR_RANK_SEQ_FIXED ( RANK )
Value:
(((RANK) == ADC_RANK_CHANNEL_NUMBER) || \
                                             ((RANK) == ADC_RANK_NONE)             )

Definition at line 950 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_RESOLUTION ( RESOLUTION )
Value:
(((RESOLUTION) == ADC_RESOLUTION_12B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
                                       ((RESOLUTION) == ADC_RESOLUTION_6B)    )

Definition at line 894 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_SAMPLE_TIME ( TIME )
Value:
(((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
                                  ((TIME) == ADC_SAMPLETIME_3CYCLES_5)   || \
                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
                                  ((TIME) == ADC_SAMPLETIME_12CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_19CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_39CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_79CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_160CYCLES_5)   )

Definition at line 988 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_SAMPLING_TIME_COMMON ( SAMPLING_TIME_COMMON )
Value:
(((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \
                                                           ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2)   )

Definition at line 985 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_SCAN_MODE ( SCAN_MODE )
Value:
(((SCAN_MODE) == ADC_SCAN_DISABLE)            || \
                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)             || \
                                     ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED)          || \
                                     ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD)   )

Definition at line 902 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_TRIGGER_FREQ ( TRIGGER_FREQ )
Value:
(((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
                                           ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW)    )

Definition at line 1005 of file stm32g0xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Function Documentation

HAL_StatusTypeDef ADC_ConversionStop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped to disable the ADC.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2635 of file stm32g0xx_hal_adc.c.

References ADC_STOP_CONVERSION_TIMEOUT, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_IsDisableOngoing(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StopConversion(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), and HAL_ADC_Stop_IT().

HAL_StatusTypeDef ADC_Disable ( ADC_HandleTypeDef * hadc )

Disable the selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2780 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_DISABLE_TIMEOUT, ADC_FLAG_EOSMP, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_Disable(), LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), and HAL_ADCEx_Calibration_Start().

HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc )

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2689 of file stm32g0xx_hal_adc.c.

References __HAL_ADC_GET_FLAG, __LL_ADC_COMMON_INSTANCE, ADC_ENABLE_TIMEOUT, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US, LL_ADC_Enable(), LL_ADC_GetCommonPathInternalCh(), LL_ADC_IsEnabled(), LL_ADC_PATH_INTERNAL_TEMPSENSOR, ADC_InitTypeDef::LowPowerAutoPowerOff, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Extended Private Constants

Defines
ADC Extended Private Constants
ADCEx

Defines

#define | ADC_CALIBRATION_TIMEOUT (193024UL)
#define | ADC_DISABLE_TIMEOUT (2UL)

Define Documentation

#define ADC_CALIBRATION_TIMEOUT (193024UL)

ADC calibration time-out value (unit: CPU cycles)

Definition at line 59 of file stm32g0xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_DISABLE_TIMEOUT (2UL)

Definition at line 60 of file stm32g0xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Input and Output operation functions

Functions
Extended Input and Output operation functions
ADC Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
__weak void | HAL_ADCEx_ChannelConfigReadyCallback (ADC_HandleTypeDef *hadc)
ADC channel configuration ready callback in non-blocking mode.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

      (+) Perform the ADC self-calibration.
      (+) Get calibration factors.
      (+) Set calibration factors.

Function Documentation

uint32_t HAL_ADCEx_Calibration_GetValue ( ADC_HandleTypeDef * hadc )

Get the calibration factor.

Parameters:
hadc ADC handle.
Return values:
Calibration value.

Definition at line 220 of file stm32g0xx_hal_adc_ex.c.

References assert_param, and __ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set the calibration factor to overwrite automatic conversion result.

ADC must be enabled and no conversion is ongoing.

Parameters:
hadc | ADC handle
CalibrationFactor | Calibration factor (coded on 7 bits maximum)
Return values:
HAL state

Definition at line 236 of file stm32g0xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Instance, IS_ADC_CALFACT, LL_ADC_IsEnabled(), LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_Calibration_Start ( ADC_HandleTypeDef * hadc )

Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).

Note:
Calibration factor can be read after calibration, using function HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 101 of file stm32g0xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_Disable(), ADC_DISABLE_TIMEOUT, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_Disable(), LL_ADC_Enable(), LL_ADC_GetCalibrationFactor(), LL_ADC_IsCalibrationOnGoing(), LL_ADC_IsEnabled(), LL_ADC_SetCalibrationFactor(), LL_ADC_StartCalibration(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_ChannelConfigReadyCallback ( ADC_HandleTypeDef * hadc )

ADC channel configuration ready callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 325 of file stm32g0xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

void HAL_ADCEx_EndOfSamplingCallback ( ADC_HandleTypeDef * hadc )

End Of Sampling callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 310 of file stm32g0xx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADCEx_LevelOutOfWindow2Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 2 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 279 of file stm32g0xx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADCEx_LevelOutOfWindow3Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 3 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 294 of file stm32g0xx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADCEx_Exported_Functions_Group2

Functions
ADCEx_Exported_Functions_Group2
ADC Extended Exported Functions

Functions

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator ( ADC_HandleTypeDef * hadc )

Disable ADC voltage regulator.

Note:
Disabling voltage regulator allows to save power. This operation can be carried out only when ADC is disabled.
To enable again the voltage regulator, the user is expected to resort to HAL_ADC_Init() API.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 348 of file stm32g0xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_DisableInternalRegulator(), and LL_ADC_IsEnabled().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Extended Exported Functions

Modules | Functions
ADC Extended Exported Functions
ADCEx

Modules

Extended Input and Output operation functions

Extended IO operation functions.

ADCEx_Exported_Functions_Group2

Functions

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator ( ADC_HandleTypeDef * hadc )

Disable ADC voltage regulator.

Note:
Disabling voltage regulator allows to save power. This operation can be carried out only when ADC is disabled.
To enable again the voltage regulator, the user is expected to resort to HAL_ADC_Init() API.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 348 of file stm32g0xx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_DisableInternalRegulator(), and LL_ADC_IsEnabled().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Extended Exported Types

ADC Extended Exported Types
ADCEx
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Extended Exported Constants

Defines

#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)

Define Documentation

#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)

ADC group regular (available on all STM32 devices)

Definition at line 56 of file stm32g0xx_hal_adc_ex.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Extended Private Macros

Defines
ADC Extended Private Macros
ADCEx

Defines

#define | ADC_IS_INDEPENDENT(__HANDLE__) (SET)
Check whether or not ADC is independent.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_OVERSAMPLING_RATIO(__RATIO__)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.

Define Documentation

#define ADC_IS_INDEPENDENT ( __HANDLE__ ) (SET)

Check whether or not ADC is independent.

Parameters:
__HANDLE__ ADC handle.
Note:
When multimode feature is not available, the macro always returns SET.
Return values:
SET (ADC is independent) or RESET (ADC is not).

Definition at line 81 of file stm32g0xx_hal_adc_ex.h.

#define IS_ADC_CALFACT ( __CALIBRATION_FACTOR__ ) ((__CALIBRATION_FACTOR__) <= (0x7FU))

Calibration factor size verification (7 bits maximum).

Parameters:
__CALIBRATION_FACTOR__ Calibration factor value.
Return values:
SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)

Definition at line 89 of file stm32g0xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

#define IS_ADC_OVERSAMPLING_RATIO ( __RATIO__ )
Value:
(((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))

Verify the ADC oversampling ratio.

Parameters:
__RATIO__ programmed ADC oversampling ratio.
Return values:
SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)

Definition at line 96 of file stm32g0xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RIGHT_BIT_SHIFT ( __SHIFT__ )
Value:
(((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))

Verify the ADC oversampling shift.

Parameters:
__SHIFT__ programmed ADC oversampling shift.
Return values:
SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)

Definition at line 110 of file stm32g0xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )

Verify the ADC oversampling triggered mode.

Parameters:
__MODE__ programmed ADC oversampling triggered mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 125 of file stm32g0xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Private Constants

CEC Private Constants
CEC
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Private Functions

CEC Private Functions
CEC
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CEC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_RegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback)
Register a User CEC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
Unregister an CEC Callback CEC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_RegisterRxCpltCallback (CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
Register CEC RX complete Callback To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterRxCpltCallback (CEC_HandleTypeDef *hcec)
UnRegister CEC RX complete Callback CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the CEC
      (+) The following parameters need to be configured:
        (++) SignalFreeTime
        (++) Tolerance
        (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
        (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
        (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
        (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
        (++) SignalFreeTimeOption      (SFT Timer start definition)
        (++) OwnAddress                (CEC device address)
        (++) ListenMode

Function Documentation

HAL_StatusTypeDef HAL_CEC_DeInit ( CEC_HandleTypeDef * hcec )

DeInitializes the CEC peripheral.

Parameters:
hcec CEC handle
Return values:
HAL status

Definition at line 274 of file stm32g0xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_DISABLE, __HAL_CEC_DISABLE_IT, assert_param, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_TXBR, CEC_FLAG_TXEND, CEC_IER_RX_ALL_ERR, CEC_IER_TX_ALL_ERR, CEC_ISR_ALL_ERROR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_TXBR, CEC_IT_TXEND, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_MspDeInit(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_RESET, __CEC_HandleTypeDef::Instance, __CEC_HandleTypeDef::MspDeInitCallback, and __CEC_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_CEC_Init ( CEC_HandleTypeDef * hcec )

Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .

Parameters:
hcec CEC handle
Return values:
HAL status

Definition at line 181 of file stm32g0xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, __HAL_CEC_ENABLE_IT, assert_param, CEC_InitTypeDef::BREErrorBitGen, CEC_InitTypeDef::BRERxStop, CEC_InitTypeDef::BroadcastMsgNoErrorBitGen, CEC_IER_RX_ALL_ERR, CEC_IER_TX_ALL_ERR, CEC_IT_RXBR, CEC_IT_RXEND, CEC_IT_TXBR, CEC_IT_TXEND, __CEC_HandleTypeDef::ErrorCallback, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_ErrorCallback(), HAL_CEC_MspInit(), HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, HAL_CEC_TxCpltCallback(), __CEC_HandleTypeDef::Init, __CEC_HandleTypeDef::Instance, IS_CEC_BREERRORBITGEN, IS_CEC_BRERXSTOP, IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION, IS_CEC_LBPEERRORBITGEN, IS_CEC_LISTENING_MODE, IS_CEC_OWN_ADDRESS, IS_CEC_SFTOP, IS_CEC_SIGNALFREETIME, IS_CEC_TOLERANCE, CEC_InitTypeDef::LBPEErrorBitGen, CEC_InitTypeDef::ListenMode, __CEC_HandleTypeDef::Lock, __CEC_HandleTypeDef::MspInitCallback, CEC_InitTypeDef::OwnAddress, CEC_InitTypeDef::RxBuffer, __CEC_HandleTypeDef::RxCpltCallback, __CEC_HandleTypeDef::RxState, CEC_InitTypeDef::SignalFreeTime, CEC_InitTypeDef::SignalFreeTimeOption, CEC_InitTypeDef::Tolerance, and __CEC_HandleTypeDef::TxCpltCallback.

void HAL_CEC_MspDeInit ( CEC_HandleTypeDef * hcec )

CEC MSP DeInit.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 401 of file stm32g0xx_hal_cec.c.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_UnRegisterCallback().

void HAL_CEC_MspInit ( CEC_HandleTypeDef * hcec )

CEC MSP Init.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 387 of file stm32g0xx_hal_cec.c.

Referenced by HAL_CEC_Init(), and HAL_CEC_UnRegisterCallback().

HAL_StatusTypeDef HAL_CEC_RegisterCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | HAL_CEC_CallbackIDTypeDef | CallbackID,
 |  | pCEC_CallbackTypeDef | pCallback
 | ) |  |

Register a User CEC Callback To be used instead of the weak predefined callback.

Parameters:
hcec | CEC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
  • HAL_CEC_ERROR_CB_ID Error callback ID
  • HAL_CEC_MSPINIT_CB_ID MspInit callback ID
  • HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 423 of file stm32g0xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCallback, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_CB_ID, HAL_CEC_ERROR_INVALID_CALLBACK, HAL_CEC_MSPDEINIT_CB_ID, HAL_CEC_MSPINIT_CB_ID, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, HAL_CEC_TX_CPLT_CB_ID, __CEC_HandleTypeDef::MspDeInitCallback, __CEC_HandleTypeDef::MspInitCallback, and __CEC_HandleTypeDef::TxCpltCallback.

HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | pCEC_RxCallbackTypeDef | pCallback
 | ) |  |

Register CEC RX complete Callback To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback.

Parameters:
hcec | CEC handle
pCallback | pointer to the Rx transfer compelete Callback function
Return values:
HAL status

Definition at line 587 of file stm32g0xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_INVALID_CALLBACK, HAL_CEC_STATE_READY, __CEC_HandleTypeDef::RxCpltCallback, and __CEC_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_CEC_SetDeviceAddress | ( | CEC_HandleTypeDef * | hcec,
 |  | uint16_t | CEC_OwnAddress
 | ) |  |

Initializes the Own Address of the CEC device.

Parameters:
hcec | CEC handle
CEC_OwnAddress | The CEC own address.
Return values:
HAL status

Definition at line 341 of file stm32g0xx_hal_cec.c.

References __HAL_CEC_DISABLE, __HAL_CEC_ENABLE, assert_param, CEC_OWN_ADDRESS_NONE, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY, HAL_CEC_STATE_READY, __CEC_HandleTypeDef::Instance, IS_CEC_OWN_ADDRESS, and __CEC_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_CEC_UnRegisterCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | HAL_CEC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an CEC Callback CEC callback is redirected to the weak predefined callback.

Parameters:
hcec uart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
  • HAL_CEC_ERROR_CB_ID Error callback ID
  • HAL_CEC_MSPINIT_CB_ID MspInit callback ID
  • HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
status

Definition at line 511 of file stm32g0xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCallback, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_CB_ID, HAL_CEC_ERROR_INVALID_CALLBACK, HAL_CEC_ErrorCallback(), HAL_CEC_MspDeInit(), HAL_CEC_MSPDEINIT_CB_ID, HAL_CEC_MspInit(), HAL_CEC_MSPINIT_CB_ID, HAL_CEC_STATE_READY, HAL_CEC_STATE_RESET, HAL_CEC_TX_CPLT_CB_ID, HAL_CEC_TxCpltCallback(), __CEC_HandleTypeDef::MspDeInitCallback, __CEC_HandleTypeDef::MspInitCallback, and __CEC_HandleTypeDef::TxCpltCallback.

HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback ( CEC_HandleTypeDef * hcec )

UnRegister CEC RX complete Callback CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback.

Parameters:
hcec CEC handle
Return values:
HAL status

Definition at line 623 of file stm32g0xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCode, HAL_CEC_ERROR_INVALID_CALLBACK, HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_READY, __CEC_HandleTypeDef::RxCpltCallback, and __CEC_HandleTypeDef::RxState.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
CEC Exported Functions

CEC Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, const uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (const CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.

Detailed Description

CEC Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the CEC data transfers.

    (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
        logical addresses (4-bit long addresses, 0xF for broadcast messages destination)

    (#) The communication is performed using Interrupts.
           These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated CEC IRQ when using Interrupt mode.
           The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_CEC_ErrorCallback() user callback will be executed when a communication
           error is detected

    (#) API's with Interrupt are :
         (+) HAL_CEC_Transmit_IT()
         (+) HAL_CEC_IRQHandler()

    (#) A set of User Callbacks are provided:
         (+) HAL_CEC_TxCpltCallback()
         (+) HAL_CEC_RxCpltCallback()
         (+) HAL_CEC_ErrorCallback()

Function Documentation

void HAL_CEC_ChangeRxBuffer | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t * | Rxbuffer
 | ) |  |

Change Rx Buffer.

Parameters:
hcec | CEC handle
Rxbuffer | Rx Buffer
Note:
This function can be called only inside the HAL_CEC_RxCpltCallback()
Return values:
Frame size

Definition at line 765 of file stm32g0xx_hal_cec.c.

References __CEC_HandleTypeDef::Init, and CEC_InitTypeDef::RxBuffer.

void HAL_CEC_ErrorCallback ( CEC_HandleTypeDef * hcec )

CEC error callbacks.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 929 of file stm32g0xx_hal_cec.c.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), and HAL_CEC_UnRegisterCallback().

uint32_t HAL_CEC_GetLastReceivedFrameSize ( const CEC_HandleTypeDef * hcec )

Get size of the received frame.

Parameters:
hcec CEC handle
Return values:
Frame size

Definition at line 753 of file stm32g0xx_hal_cec.c.

References __CEC_HandleTypeDef::RxXferSize.

void HAL_CEC_IRQHandler ( CEC_HandleTypeDef * hcec )

This function handles CEC interrupt requests.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 775 of file stm32g0xx_hal_cec.c.

References __HAL_CEC_CLEAR_FLAG, __HAL_CEC_LAST_BYTE_TX_SET, CEC_FLAG_ARBLST, CEC_FLAG_LBPE, CEC_FLAG_RXBR, CEC_FLAG_RXEND, CEC_FLAG_SBPE, CEC_FLAG_TXBR, CEC_FLAG_TXEND, __CEC_HandleTypeDef::ErrorCallback, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_ARBLST, HAL_CEC_ERROR_BRE, HAL_CEC_ERROR_NONE, HAL_CEC_ERROR_RXACKE, HAL_CEC_ERROR_RXOVR, HAL_CEC_ERROR_TXACKE, HAL_CEC_ERROR_TXERR, HAL_CEC_ERROR_TXUDR, HAL_CEC_ErrorCallback(), HAL_CEC_RxCpltCallback(), HAL_CEC_STATE_BUSY_RX, HAL_CEC_STATE_READY, HAL_CEC_TxCpltCallback(), __CEC_HandleTypeDef::Init, __CEC_HandleTypeDef::Instance, __CEC_HandleTypeDef::pTxBuffPtr, CEC_InitTypeDef::RxBuffer, __CEC_HandleTypeDef::RxCpltCallback, __CEC_HandleTypeDef::RxState, __CEC_HandleTypeDef::RxXferSize, __CEC_HandleTypeDef::TxCpltCallback, and __CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_RxCpltCallback | ( | CEC_HandleTypeDef * | hcec,
 |  | uint32_t | RxFrameSize
 | ) |  |

Rx Transfer completed callback.

Parameters:
hcec | CEC handle
RxFrameSize | Size of frame
Return values:
None

Definition at line 914 of file stm32g0xx_hal_cec.c.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), and HAL_CEC_UnRegisterRxCpltCallback().

HAL_StatusTypeDef HAL_CEC_Transmit_IT | ( | CEC_HandleTypeDef * | hcec,
 |  | uint8_t | InitiatorAddress,
 |  | uint8_t | DestinationAddress,
 |  | const uint8_t * | pData,
 |  | uint32_t | Size
 | ) |  |

Send data in interrupt mode.

Parameters:
hcec | CEC handle
InitiatorAddress | Initiator address
DestinationAddress | destination logical address
pData | pointer to input byte data buffer
Size | amount of data to be sent in bytes (without counting the header). 0 means only the header is sent (ping operation). Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
Return values:
HAL status

Definition at line 697 of file stm32g0xx_hal_cec.c.

References __HAL_CEC_FIRST_BYTE_TX_SET, __HAL_CEC_LAST_BYTE_TX_SET, assert_param, CEC_INITIATOR_LSB_POS, __CEC_HandleTypeDef::ErrorCode, __CEC_HandleTypeDef::gState, HAL_CEC_ERROR_NONE, HAL_CEC_STATE_BUSY_TX, HAL_CEC_STATE_READY, __CEC_HandleTypeDef::Instance, IS_CEC_ADDRESS, IS_CEC_MSGSIZE, __CEC_HandleTypeDef::pTxBuffPtr, and __CEC_HandleTypeDef::TxXferCount.

void HAL_CEC_TxCpltCallback ( CEC_HandleTypeDef * hcec )

Tx Transfer completed callback.

Parameters:
hcec CEC handle
Return values:
None

Definition at line 899 of file stm32g0xx_hal_cec.c.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), and HAL_CEC_UnRegisterCallback().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control function

Functions
Peripheral Control function
CEC Exported Functions

CEC control functions. More...

Functions

HAL_CEC_StateTypeDef | HAL_CEC_GetState (const CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (const CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC control functions.

 ===============================================================================
                      ##### Peripheral Control function #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the CEC.
     (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
     (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.

Function Documentation

uint32_t HAL_CEC_GetError ( const CEC_HandleTypeDef * hcec )

Return the CEC error code.

Parameters:
hcec pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC.
Return values:
CEC Error Code

Definition at line 977 of file stm32g0xx_hal_cec.c.

References __CEC_HandleTypeDef::ErrorCode.

HAL_CEC_StateTypeDef HAL_CEC_GetState ( const CEC_HandleTypeDef * hcec )

return the CEC state

Parameters:
hcec pointer to a CEC_HandleTypeDef structure that contains the configuration information for the specified CEC module.
Return values:
HAL state

Definition at line 961 of file stm32g0xx_hal_cec.c.

References __CEC_HandleTypeDef::gState, and __CEC_HandleTypeDef::RxState.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Exported Types

Data Structures | Typedefs | Enumerations
CEC Exported Types
CEC

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | __CEC_HandleTypeDef
CEC handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_CEC_StateTypeDef
HAL CEC State definition.
typedef struct __CEC_HandleTypeDef | CEC_HandleTypeDef
CEC handle Structure definition.
typedef void(* | pCEC_CallbackTypeDef )(CEC_HandleTypeDef *hcec)
HAL CEC Callback pointer definition.
typedef void(* | pCEC_RxCallbackTypeDef )(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)

Enumerations

enum HAL_CEC_CallbackIDTypeDef {
HAL_CEC_TX_CPLT_CB_ID = 0x00U, HAL_CEC_RX_CPLT_CB_ID = 0x01U, HAL_CEC_ERROR_CB_ID = 0x02U, HAL_CEC_MSPINIT_CB_ID = 0x03U,
HAL_CEC_MSPDEINIT_CB_ID = 0x04U
}
HAL CEC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __CEC_HandleTypeDef CEC_HandleTypeDef

CEC handle Structure definition.

typedef uint32_t HAL_CEC_StateTypeDef

HAL CEC State definition.

Note:
HAL CEC State value is a combination of 2 different substates: gState and RxState (see CEC_State_Definition).
  • gState contains CEC state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7 (not used) x : Should be set to 0 b6 Error information 0 : No Error 1 : Error b5 CEC peripheral initialization status 0 : Reset (peripheral not initialized) 1 : Init done (peripheral initialized. HAL CEC Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 CEC peripheral initialization status 0 : Reset (peripheral not initialized) 1 : Init done (peripheral initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 161 of file stm32g0xx_hal_cec.h.

typedef void(* pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec)

HAL CEC Callback pointer definition.

pointer to an CEC callback function

Definition at line 223 of file stm32g0xx_hal_cec.h.

typedef void(* pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)

pointer to an Rx Transfer completed callback function

Definition at line 224 of file stm32g0xx_hal_cec.h.

Enumeration Type Documentation

enum HAL_CEC_CallbackIDTypeDef

HAL CEC Callback ID enumeration definition.

Enumerator:
HAL_CEC_TX_CPLT_CB_ID

CEC Tx Transfer completed callback ID

HAL_CEC_RX_CPLT_CB_ID

CEC Rx Transfer completed callback ID

HAL_CEC_ERROR_CB_ID

CEC error callback ID

HAL_CEC_MSPINIT_CB_ID

CEC Msp Init callback ID

HAL_CEC_MSPDEINIT_CB_ID

CEC Msp DeInit callback ID

Definition at line 211 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CEC_InitTypeDef Struct Reference
CEC Exported Types

CEC Init Structure definition. More...

#include <stm32g0xx_hal_cec.h>

Data Fields

uint32_t | SignalFreeTime
uint32_t | Tolerance
uint32_t | BRERxStop
uint32_t | BREErrorBitGen
uint32_t | LBPEErrorBitGen
uint32_t | BroadcastMsgNoErrorBitGen
uint32_t | SignalFreeTimeOption
uint32_t | ListenMode
uint16_t | OwnAddress
uint8_t * | RxBuffer

Detailed Description

CEC Init Structure definition.

Definition at line 48 of file stm32g0xx_hal_cec.h.

Field Documentation

uint32_t CEC_InitTypeDef::BREErrorBitGen

Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the CEC line upon Bit Rising Error detection. CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set.

Definition at line 65 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BRERxStop

Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. CEC_NO_RX_STOP_ON_BRE: reception is not stopped. CEC_RX_STOP_ON_BRE: reception is stopped.

Definition at line 60 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::BroadcastMsgNoErrorBitGen

Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line upon an error detected on a broadcast message.

It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:

1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.

2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. no error-bit generation in case neither a) nor b) are satisfied. Additionally, there is no error-bit generation in case of Short Bit Period Error detection in a broadcast message while LSTN bit is set.

Definition at line 77 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::LBPEErrorBitGen

Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the CEC line upon Long Bit Period Error detection. CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_LBPE_ERRORBIT_GENERATION: error-bit generation.

Definition at line 71 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::ListenMode

Set LSTN bit CEC_Listening_Mode : specifies device listening mode. It can take two values:

CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.

CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.

Definition at line 100 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint16_t CEC_InitTypeDef::OwnAddress

Own addresses configuration This parameter can be a value of CEC_OWN_ADDRESS

Definition at line 113 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint8_t* CEC_InitTypeDef::RxBuffer

CEC Rx buffer pointer

Definition at line 116 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_ChangeRxBuffer(), HAL_CEC_Init(), and HAL_CEC_IRQHandler().

uint32_t CEC_InitTypeDef::SignalFreeTime

Set SFT field, specifies the Signal Free Time. It can be one of CEC_Signal_Free_Time and belongs to the set {0,...,7} where 0x0 is the default configuration else means 0.5 + (SignalFreeTime - 1) nominal data bit periods

Definition at line 50 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::SignalFreeTimeOption

Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts. CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception.

Definition at line 95 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

uint32_t CEC_InitTypeDef::Tolerance

Set RXTOL bit, specifies the tolerance accepted on the received waveforms, it can be a value of CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE

Definition at line 56 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_cec.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __CEC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__CEC_HandleTypeDef Struct Reference
CEC Exported Types

CEC handle Structure definition. More...

#include <stm32g0xx_hal_cec.h>

Data Fields

CEC_TypeDef * | Instance
CEC_InitTypeDef Init
const uint8_t * | pTxBuffPtr
uint16_t | TxXferCount
uint16_t | RxXferSize
HAL_LockTypeDef | Lock
HAL_CEC_StateTypeDef gState
HAL_CEC_StateTypeDef RxState
uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __CEC_HandleTypeDef *hcec)
void(* | RxCpltCallback )(struct __CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
void(* | ErrorCallback )(struct __CEC_HandleTypeDef *hcec)
void(* | MspInitCallback )(struct __CEC_HandleTypeDef *hcec)
void(* | MspDeInitCallback )(struct __CEC_HandleTypeDef *hcec)

Detailed Description

CEC handle Structure definition.

Definition at line 167 of file stm32g0xx_hal_cec.h.

Field Documentation

void(* __CEC_HandleTypeDef::ErrorCallback)(struct __CEC_HandleTypeDef *hcec)

CEC error callback

Definition at line 199 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

uint32_t __CEC_HandleTypeDef::ErrorCode

For errors handling purposes, copy of ISR register in case error is reported

Definition at line 191 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetError(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), HAL_CEC_RegisterRxCpltCallback(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), HAL_CEC_UnRegisterCallback(), and HAL_CEC_UnRegisterRxCpltCallback().

HAL_CEC_StateTypeDef __CEC_HandleTypeDef::gState

CEC state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_CEC_StateTypeDef

Definition at line 184 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), and HAL_CEC_UnRegisterCallback().

CEC_InitTypeDef __CEC_HandleTypeDef::Init

CEC communication parameters

Definition at line 174 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_ChangeRxBuffer(), HAL_CEC_Init(), and HAL_CEC_IRQHandler().

CEC_TypeDef* __CEC_HandleTypeDef::Instance

CEC registers base address

Definition at line 172 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

HAL_LockTypeDef __CEC_HandleTypeDef::Lock

Locking object

Definition at line 182 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

void(* __CEC_HandleTypeDef::MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec)

CEC Msp DeInit callback

Definition at line 202 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

void(* __CEC_HandleTypeDef::MspInitCallback)(struct __CEC_HandleTypeDef *hcec)

CEC Msp Init callback

Definition at line 201 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

const uint8_t* __CEC_HandleTypeDef::pTxBuffPtr

Pointer to CEC Tx transfer Buffer

Definition at line 176 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

void(* __CEC_HandleTypeDef::RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)

CEC Rx Transfer completed callback

Definition at line 197 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterRxCpltCallback(), and HAL_CEC_UnRegisterRxCpltCallback().

HAL_CEC_StateTypeDef __CEC_HandleTypeDef::RxState

CEC state information related to Rx operations. This parameter can be a value of HAL_CEC_StateTypeDef

Definition at line 188 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_GetState(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterRxCpltCallback(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_UnRegisterRxCpltCallback().

uint16_t __CEC_HandleTypeDef::RxXferSize

CEC Rx Transfer size, 0: header received only

Definition at line 180 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_GetLastReceivedFrameSize(), and HAL_CEC_IRQHandler().

void(* __CEC_HandleTypeDef::TxCpltCallback)(struct __CEC_HandleTypeDef *hcec)

CEC Tx Transfer completed callback

Definition at line 195 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

uint16_t __CEC_HandleTypeDef::TxXferCount

CEC Tx Transfer Counter

Definition at line 178 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_cec.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC State Code Definition

Defines
CEC State Code Definition
CEC Exported Constants

Defines

#define | HAL_CEC_STATE_RESET ((uint32_t)0x00000000)
#define | HAL_CEC_STATE_READY ((uint32_t)0x00000020)
#define | HAL_CEC_STATE_BUSY ((uint32_t)0x00000024)
#define | HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022)
#define | HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021)
#define | HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)
#define | HAL_CEC_STATE_ERROR ((uint32_t)0x00000050)

Define Documentation

#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024)

an internal process is ongoing Value is allowed for gState only

Definition at line 243 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022)

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 245 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)

an internal process is ongoing Value is allowed for gState only

Definition at line 249 of file stm32g0xx_hal_cec.h.

#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021)

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 247 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050)

Error Value is allowed for gState only

Definition at line 251 of file stm32g0xx_hal_cec.h.

#define HAL_CEC_STATE_READY ((uint32_t)0x00000020)

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 241 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_RegisterCallback(), HAL_CEC_RegisterRxCpltCallback(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), HAL_CEC_UnRegisterCallback(), and HAL_CEC_UnRegisterRxCpltCallback().

#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000)

Peripheral is not yet Initialized Value is allowed for gState and RxState

Definition at line 239 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_RegisterCallback(), and HAL_CEC_UnRegisterCallback().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Error Code

Defines
CEC Error Code
CEC Exported Constants

Defines

#define | HAL_CEC_ERROR_NONE (uint32_t) 0x0000U
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
#define | HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U)

Define Documentation

#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST

CEC Arbitration Lost

Definition at line 264 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_BRE CEC_ISR_BRE

CEC Rx Bit Rising Error

Definition at line 260 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U)

Invalid Callback Error

Definition at line 269 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_RegisterCallback(), HAL_CEC_RegisterRxCpltCallback(), HAL_CEC_UnRegisterCallback(), and HAL_CEC_UnRegisterRxCpltCallback().

#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE

CEC Rx Long Bit period Error

Definition at line 262 of file stm32g0xx_hal_cec.h.

#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U

no error

Definition at line 258 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_IRQHandler(), HAL_CEC_SetDeviceAddress(), and HAL_CEC_Transmit_IT().

#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE

CEC Rx Missing Acknowledge

Definition at line 263 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR

CEC Rx-Overrun

Definition at line 259 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE

CEC Rx Short Bit period Error

Definition at line 261 of file stm32g0xx_hal_cec.h.

#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE

CEC Tx Missing Acknowledge

Definition at line 267 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR

CEC Tx-Error

Definition at line 266 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR

CEC Tx-Buffer Underrun

Definition at line 265 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

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STM32G0C1xx HAL User Manual: CEC Signal Free Time setting parameter

Defines
CEC Signal Free Time setting parameter
CEC Exported Constants

Defines

#define | CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define | CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define | CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define | CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define | CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define | CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define | CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define | CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)

Define Documentation

#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)

Definition at line 279 of file stm32g0xx_hal_cec.h.

#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)

Definition at line 280 of file stm32g0xx_hal_cec.h.

#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)

Definition at line 281 of file stm32g0xx_hal_cec.h.

#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)

Definition at line 282 of file stm32g0xx_hal_cec.h.

#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)

Definition at line 283 of file stm32g0xx_hal_cec.h.

#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)

Definition at line 284 of file stm32g0xx_hal_cec.h.

#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)

Definition at line 285 of file stm32g0xx_hal_cec.h.

#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)

Definition at line 278 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Receiver Tolerance

Defines
CEC Receiver Tolerance
CEC Exported Constants

Defines

#define | CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Define Documentation

#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)

Definition at line 294 of file stm32g0xx_hal_cec.h.

#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)

Definition at line 293 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Reception Stop on Error

Defines
CEC Reception Stop on Error
CEC Exported Constants

Defines

#define | CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Define Documentation

#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)

Definition at line 302 of file stm32g0xx_hal_cec.h.

#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)

Definition at line 303 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Error Bit Generation if Bit Rise Error reported

Defines
CEC Error Bit Generation if Bit Rise Error reported
CEC Exported Constants

Defines

#define | CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Define Documentation

#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)

Definition at line 312 of file stm32g0xx_hal_cec.h.

#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)

Definition at line 311 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Error Bit Generation if Long Bit Period Error reported

Defines
CEC Error Bit Generation if Long Bit Period Error reported
CEC Exported Constants

Defines

#define | CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Define Documentation

#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)

Definition at line 321 of file stm32g0xx_hal_cec.h.

#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)

Definition at line 320 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Error Bit Generation on Broadcast message

Defines
CEC Error Bit Generation on Broadcast message
CEC Exported Constants

Defines

#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Define Documentation

#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)

Definition at line 329 of file stm32g0xx_hal_cec.h.

#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)

Definition at line 330 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Signal Free Time start option

Defines
CEC Signal Free Time start option
CEC Exported Constants

Defines

#define | CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Define Documentation

#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)

Definition at line 339 of file stm32g0xx_hal_cec.h.

#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)

Definition at line 338 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Listening mode option

Defines
CEC Listening mode option
CEC Exported Constants

Defines

#define | CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Define Documentation

#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)

Definition at line 348 of file stm32g0xx_hal_cec.h.

#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)

Definition at line 347 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Device Own Address position in CEC CFGR register

Defines
CEC Device Own Address position in CEC CFGR register
CEC Exported Constants

Defines

#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)

Define Documentation

#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)

Definition at line 356 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Initiator logical address position in message header

Defines
CEC Initiator logical address position in message header
CEC Exported Constants

Defines

#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)

Define Documentation

#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)

Definition at line 364 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Own Address

Defines
CEC Own Address
CEC Exported Constants

Defines

#define | CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define | CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define | CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define | CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define | CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define | CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define | CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define | CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define | CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define | CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define | CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define | CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define | CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define | CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define | CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define | CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */

Define Documentation

#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */

Definition at line 373 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */

Definition at line 374 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */

Definition at line 383 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */

Definition at line 384 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */

Definition at line 385 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */

Definition at line 386 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */

Definition at line 387 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */

Definition at line 375 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */

Definition at line 376 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */

Definition at line 377 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */

Definition at line 378 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */

Definition at line 379 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */

Definition at line 380 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */

Definition at line 381 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */

Definition at line 382 of file stm32g0xx_hal_cec.h.

#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */

Definition at line 372 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_SetDeviceAddress().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Interrupts definition

Defines
CEC Interrupts definition
CEC Exported Constants

Defines

#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE

Define Documentation

#define CEC_IT_ARBLST CEC_IER_ARBLSTIE

Definition at line 400 of file stm32g0xx_hal_cec.h.

#define CEC_IT_BRE CEC_IER_BREIE

Definition at line 404 of file stm32g0xx_hal_cec.h.

#define CEC_IT_LBPE CEC_IER_LBPEIE

Definition at line 402 of file stm32g0xx_hal_cec.h.

#define CEC_IT_RXACKE CEC_IER_RXACKEIE

Definition at line 401 of file stm32g0xx_hal_cec.h.

#define CEC_IT_RXBR CEC_IER_RXBRIE

Definition at line 407 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_RXEND CEC_IER_RXENDIE

Definition at line 406 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_RXOVR CEC_IER_RXOVRIE

Definition at line 405 of file stm32g0xx_hal_cec.h.

#define CEC_IT_SBPE CEC_IER_SBPEIE

Definition at line 403 of file stm32g0xx_hal_cec.h.

#define CEC_IT_TXACKE CEC_IER_TXACKEIE

Definition at line 395 of file stm32g0xx_hal_cec.h.

#define CEC_IT_TXBR CEC_IER_TXBRIE

Definition at line 399 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_TXEND CEC_IER_TXENDIE

Definition at line 398 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

#define CEC_IT_TXERR CEC_IER_TXERRIE

Definition at line 396 of file stm32g0xx_hal_cec.h.

#define CEC_IT_TXUDR CEC_IER_TXUDRIE

Definition at line 397 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Flags definition

Defines
CEC Flags definition
CEC Exported Constants

Defines

#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR

Define Documentation

#define CEC_FLAG_ARBLST CEC_ISR_ARBLST

Definition at line 420 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_BRE CEC_ISR_BRE

Definition at line 424 of file stm32g0xx_hal_cec.h.

#define CEC_FLAG_LBPE CEC_ISR_LBPE

Definition at line 422 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_RXACKE CEC_ISR_RXACKE

Definition at line 421 of file stm32g0xx_hal_cec.h.

#define CEC_FLAG_RXBR CEC_ISR_RXBR

Definition at line 427 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_RXEND CEC_ISR_RXEND

Definition at line 426 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_RXOVR CEC_ISR_RXOVR

Definition at line 425 of file stm32g0xx_hal_cec.h.

#define CEC_FLAG_SBPE CEC_ISR_SBPE

Definition at line 423 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler().

#define CEC_FLAG_TXACKE CEC_ISR_TXACKE

Definition at line 415 of file stm32g0xx_hal_cec.h.

#define CEC_FLAG_TXBR CEC_ISR_TXBR

Definition at line 419 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_TXEND CEC_ISR_TXEND

Definition at line 418 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define CEC_FLAG_TXERR CEC_ISR_TXERR

Definition at line 416 of file stm32g0xx_hal_cec.h.

#define CEC_FLAG_TXUDR CEC_ISR_TXUDR

Definition at line 417 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC all RX or TX errors flags

Defines
CEC all RX or TX errors flags
CEC Exported Constants

Defines

#define CEC_ISR_ALL_ERROR

Define Documentation

#define CEC_ISR_ALL_ERROR
Value:
((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
                                 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)

Definition at line 435 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC all RX errors interrupts enabling flag

Defines
CEC all RX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Define Documentation

#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

Definition at line 444 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC all TX errors interrupts enabling flag

Defines
CEC all TX errors interrupts enabling flag
CEC Exported Constants

Defines

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Define Documentation

#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

Definition at line 452 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Exported Macros

Defines
CEC Exported Macros
CEC

Defines

#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__)
Reset CEC handle gstate & RxState.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Define Documentation

#define __HAL_CEC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR |= (__FLAG__))

Clears the interrupt or status flag when raised (write at 1)

Parameters:
__HANDLE__ specifies the CEC Handle.
__FLAG__ specifies the interrupt/status flag to clear. This parameter can be one of the following values:
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
none

Definition at line 522 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), and HAL_CEC_IRQHandler().

#define __HAL_CEC_CLEAR_OAR ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)

Clear OAR register.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 628 of file stm32g0xx_hal_cec.h.

#define __HAL_CEC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)

Disables the CEC device.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 597 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit(), HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define __HAL_CEC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disables the specified CEC interrupt.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to disable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 564 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_DeInit().

#define __HAL_CEC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)

Enables the CEC device.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 591 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define __HAL_CEC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enables the specified CEC interrupt.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to enable. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
none

Definition at line 543 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define __HAL_CEC_FIRST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)

Set Transmission Start flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none

Definition at line 603 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define __HAL_CEC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR & (__FLAG__))

Checks whether or not the specified CEC interrupt flag is set.

Parameters:
__HANDLE__ specifies the CEC Handle.
__FLAG__ specifies the flag to check.
  • CEC_FLAG_TXACKE: Tx Missing acknowledge Error
  • CEC_FLAG_TXERR: Tx Error.
  • CEC_FLAG_TXUDR: Tx-Buffer Underrun.
  • CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
  • CEC_FLAG_TXBR: Tx-Byte Request.
  • CEC_FLAG_ARBLST: Arbitration Lost
  • CEC_FLAG_RXACKE: Rx-Missing Acknowledge
  • CEC_FLAG_LBPE: Rx Long period Error
  • CEC_FLAG_SBPE: Rx Short period Error
  • CEC_FLAG_BRE: Rx Bit Rising Error
  • CEC_FLAG_RXOVR: Rx Overrun.
  • CEC_FLAG_RXEND: End Of Reception.
  • CEC_FLAG_RXBR: Rx-Byte Received.
Return values:
ITStatus

Definition at line 501 of file stm32g0xx_hal_cec.h.

#define __HAL_CEC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

Checks whether or not the specified CEC interrupt is enabled.

Parameters:
__HANDLE__ specifies the CEC Handle.
__INTERRUPT__ specifies the CEC interrupt to check. This parameter can be one of the following values:
  • CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
  • CEC_IT_TXERR: Tx Error IT Enable
  • CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
  • CEC_IT_TXEND: End of transmission IT Enable
  • CEC_IT_TXBR: Tx-Byte Request IT Enable
  • CEC_IT_ARBLST: Arbitration Lost IT Enable
  • CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
  • CEC_IT_LBPE: Rx Long period Error IT Enable
  • CEC_IT_SBPE: Rx Short period Error IT Enable
  • CEC_IT_BRE: Rx Bit Rising Error IT Enable
  • CEC_IT_RXOVR: Rx Overrun IT Enable
  • CEC_IT_RXEND: End Of Reception IT Enable
  • CEC_IT_RXBR: Rx-Byte Received IT Enable
Return values:
FlagStatus

Definition at line 585 of file stm32g0xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_END_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)

Get Transmission End flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 622 of file stm32g0xx_hal_cec.h.

#define __HAL_CEC_GET_TRANSMISSION_START_FLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)

Get Transmission Start flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
FlagStatus

Definition at line 616 of file stm32g0xx_hal_cec.h.

#define __HAL_CEC_LAST_BYTE_TX_SET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)

Set Transmission End flag.

Parameters:
__HANDLE__ specifies the CEC Handle.
Return values:
none If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.

Definition at line 610 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_IRQHandler(), and HAL_CEC_Transmit_IT().

#define __HAL_CEC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
                                                       (__HANDLE__)->MspInitCallback = NULL;           \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
                                                     } while(0)

Reset CEC handle gstate & RxState.

Parameters:
__HANDLE__ CEC handle.
Return values:
None

Definition at line 471 of file stm32g0xx_hal_cec.h.

#define __HAL_CEC_SET_OAR | ( | __HANDLE__,
 |  | __ADDRESS__
 | ) |
Value:
SET_BIT((__HANDLE__)->Instance->CFGR, \
                                                            (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)

Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.

Parameters:
__HANDLE__ | specifies the CEC Handle.
__ADDRESS__ | Own Address value (CEC logical address is identified by bit position)
Return values:
none

Definition at line 636 of file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Private Types

CEC Private Types
CEC
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Private Variables

CEC Private Variables
CEC
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Private Macros

Defines
CEC Private Macros
CEC

Defines

#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
Check CEC message size.
#define | IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
Check CEC initiator or destination logical address setting.

Define Documentation

#define IS_CEC_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0xFU)

Check CEC initiator or destination logical address setting.

Initiator and destination addresses are coded over 4 bits.

Parameters:
__ADDRESS__ CEC initiator or logical address.
Return values:
Test result (TRUE or FALSE).

Definition at line 777 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define IS_CEC_BREERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))

Definition at line 740 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BRERXSTOP ( __BRERXSTOP__ )
Value:
(((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))

Definition at line 737 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
   ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))

Definition at line 746 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LBPEERRORBITGEN ( __ERRORBITGEN__ )
Value:
(((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))

Definition at line 743 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_LISTENING_MODE ( __MODE__ )
Value:
(((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))

Definition at line 753 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_MSGSIZE ( __SIZE__ ) ((__SIZE__) <= 0x10U)

Check CEC message size.

The message size is the payload size: without counting the header, it varies from 0 byte (ping operation, one header only, no payload) to 15 bytes (1 opcode and up to 14 operands following the header).

Parameters:
__SIZE__ CEC message size.
Return values:
Test result (TRUE or FALSE).

Definition at line 763 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Transmit_IT().

#define IS_CEC_OWN_ADDRESS ( __ADDRESS__ ) ((__ADDRESS__) <= 0x7FFFU)

Check CEC device Own Address Register (OAR) setting.

OAR address is written in a 15-bit field within CEC_CFGR register.

Parameters:
__ADDRESS__ CEC own address.
Return values:
Test result (TRUE or FALSE).

Definition at line 770 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init(), and HAL_CEC_SetDeviceAddress().

#define IS_CEC_SFTOP ( __SFTOP__ )
Value:
(((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))

Definition at line 750 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_SIGNALFREETIME ( __SFT__ ) ((__SFT__) <= CEC_CFGR_SFT)

Definition at line 732 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

#define IS_CEC_TOLERANCE ( __RXTOL__ )
Value:
(((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))

Definition at line 734 of file stm32g0xx_hal_cec.h.

Referenced by HAL_CEC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
COMP Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions to initialize and de-initialize comparators

Function Documentation

HAL_StatusTypeDef HAL_COMP_DeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP peripheral.

Note:
Deinitialization cannot be performed if the COMP configuration is locked. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 521 of file stm32g0xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_MspDeInit(), HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, __COMP_HandleTypeDef::MspDeInitCallback, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Init ( COMP_HandleTypeDef * hcomp )

Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.

Note:
If the selected comparator is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 230 of file stm32g0xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_InitTypeDef::BlankingSrce, COMP_CLEAR_ERRORCODE, COMP_DELAY_VOLTAGE_SCALER_STAB_US, COMP_EXTI_EVENT, COMP_EXTI_FALLING, COMP_EXTI_IT, COMP_EXTI_RISING, COMP_GET_EXTI_LINE, COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON, COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON, COMP_WINDOWMODE_DISABLE, COMP_WINDOWOUTPUT_BOTH, COMP_WINDOWOUTPUT_COMP1, COMP_WINDOWOUTPUT_COMP2, HAL_COMP_MspInit(), HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TriggerCallback(), COMP_InitTypeDef::Hysteresis, __COMP_HandleTypeDef::Init, COMP_InitTypeDef::InputMinus, COMP_InitTypeDef::InputPlus, __COMP_HandleTypeDef::Instance, IS_COMP_BLANKINGSRC_INSTANCE, IS_COMP_HYSTERESIS, IS_COMP_INPUT_MINUS, IS_COMP_INPUT_PLUS, IS_COMP_OUTPUTPOL, IS_COMP_POWERMODE, IS_COMP_TRIGGERMODE, IS_COMP_WINDOWMODE, IS_COMP_WINDOWOUTPUT, LL_EXTI_ClearFallingFlag_0_31(), LL_EXTI_ClearRisingFlag_0_31(), LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableRisingTrig_0_31(), __COMP_HandleTypeDef::Lock, COMP_InitTypeDef::Mode, __COMP_HandleTypeDef::MspInitCallback, COMP_InitTypeDef::OutputPol, __COMP_HandleTypeDef::State, __COMP_HandleTypeDef::TriggerCallback, COMP_InitTypeDef::TriggerMode, COMP_InitTypeDef::WindowMode, and COMP_InitTypeDef::WindowOutput.

void HAL_COMP_MspDeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 585 of file stm32g0xx_hal_comp.c.

Referenced by HAL_COMP_DeInit(), and HAL_COMP_UnRegisterCallback().

void HAL_COMP_MspInit ( COMP_HandleTypeDef * hcomp )

Initialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 570 of file stm32g0xx_hal_comp.c.

Referenced by HAL_COMP_Init(), and HAL_COMP_UnRegisterCallback().

HAL_StatusTypeDef HAL_COMP_RegisterCallback | ( | COMP_HandleTypeDef * | hcomp,
 |  | HAL_COMP_CallbackIDTypeDef | CallbackID,
 |  | pCOMP_CallbackTypeDef | pCallback
 | ) |  |

Register a User COMP Callback To be used instead of the weak predefined callback.

Parameters:
hcomp | Pointer to a COMP_HandleTypeDef structure that contains the configuration information for the specified COMP.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_COMP_TRIGGER_CB_ID Trigger callback ID
  • HAL_COMP_MSPINIT_CB_ID MspInit callback ID
  • HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 609 of file stm32g0xx_hal_comp.c.

References __COMP_HandleTypeDef::ErrorCode, HAL_COMP_ERROR_INVALID_CALLBACK, HAL_COMP_MSPDEINIT_CB_ID, HAL_COMP_MSPINIT_CB_ID, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TRIGGER_CB_ID, __COMP_HandleTypeDef::MspDeInitCallback, __COMP_HandleTypeDef::MspInitCallback, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_COMP_UnRegisterCallback | ( | COMP_HandleTypeDef * | hcomp,
 |  | HAL_COMP_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.

Parameters:
hcomp Pointer to a COMP_HandleTypeDef structure that contains the configuration information for the specified COMP.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_COMP_TRIGGER_CB_ID Trigger callback ID
  • HAL_COMP_MSPINIT_CB_ID MspInit callback ID
  • HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 691 of file stm32g0xx_hal_comp.c.

References __COMP_HandleTypeDef::ErrorCode, HAL_COMP_ERROR_INVALID_CALLBACK, HAL_COMP_MspDeInit(), HAL_COMP_MSPDEINIT_CB_ID, HAL_COMP_MspInit(), HAL_COMP_MSPINIT_CB_ID, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TRIGGER_CB_ID, HAL_COMP_TriggerCallback(), __COMP_HandleTypeDef::MspDeInitCallback, __COMP_HandleTypeDef::MspInitCallback, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Start-Stop operation functions

Functions
Start-Stop operation functions
COMP Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.

Detailed Description

Start-Stop operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a comparator instance.
      (+) Stop a comparator instance.

Function Documentation

void HAL_COMP_IRQHandler ( COMP_HandleTypeDef * hcomp )

Comparator IRQ handler.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 873 of file stm32g0xx_hal_comp.c.

References COMP_EXTI_LINE_COMP1, COMP_EXTI_LINE_COMP2, COMP_EXTI_LINE_COMP3, COMP_GET_EXTI_LINE, HAL_COMP_TriggerCallback(), __COMP_HandleTypeDef::Instance, LL_EXTI_ClearFallingFlag_0_31(), LL_EXTI_ClearRisingFlag_0_31(), LL_EXTI_IsActiveFallingFlag_0_31(), LL_EXTI_IsActiveRisingFlag_0_31(), and __COMP_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_COMP_Start ( COMP_HandleTypeDef * hcomp )

Start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 779 of file stm32g0xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_DELAY_STARTUP_US, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Stop ( COMP_HandleTypeDef * hcomp )

Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 831 of file stm32g0xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
COMP Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the comparators.

Function Documentation

uint32_t HAL_COMP_GetOutputLevel ( COMP_HandleTypeDef * hcomp )

Return the output level (high or low) of the selected comparator.

The output level depends on the selected polarity. If the polarity is not inverted:

  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
    Parameters:
    hcomp COMP handle
    Return values:
    Returns the selected comparator output level:
    • COMP_OUTPUT_LEVEL_LOW
    • COMP_OUTPUT_LEVEL_HIGH

Definition at line 1057 of file stm32g0xx_hal_comp.c.

References assert_param, COMP_OUTPUT_LEVEL_BITOFFSET_POS, and __COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Lock ( COMP_HandleTypeDef * hcomp )

Lock the selected comparator configuration.

Note:
A system reset is required to unlock the comparator configuration.
Locking the comparator from reset state is possible if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 996 of file stm32g0xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, __HAL_COMP_LOCK, assert_param, HAL_COMP_STATE_BUSY_LOCKED, HAL_COMP_STATE_READY, HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_RESET, HAL_COMP_STATE_RESET_LOCKED, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

void HAL_COMP_TriggerCallback ( COMP_HandleTypeDef * hcomp )

Comparator trigger callback.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 1071 of file stm32g0xx_hal_comp.c.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), and HAL_COMP_UnRegisterCallback().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
COMP Exported Functions

Peripheral State functions. More...

Functions

HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral.

Function Documentation

uint32_t HAL_COMP_GetError ( COMP_HandleTypeDef * hcomp )

Return the COMP error code.

Parameters:
hcomp COMP handle
Return values:
COMP error code

Definition at line 1125 of file stm32g0xx_hal_comp.c.

References assert_param, __COMP_HandleTypeDef::ErrorCode, and __COMP_HandleTypeDef::Instance.

HAL_COMP_StateTypeDef HAL_COMP_GetState ( COMP_HandleTypeDef * hcomp )

Return the COMP handle state.

Parameters:
hcomp COMP handle
Return values:
HAL state

Definition at line 1105 of file stm32g0xx_hal_comp.c.

References assert_param, HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

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STM32G0C1xx HAL User Manual: COMP Exported Types

Data Structures | Defines | Typedefs | Enumerations
COMP Exported Types
COMP

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | __COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK (0x10U)
HAL COMP state machine: HAL COMP states definition.

Typedefs

typedef struct __COMP_HandleTypeDef | COMP_HandleTypeDef
COMP Handle Structure definition.
typedef void(* | pCOMP_CallbackTypeDef )(COMP_HandleTypeDef *hcomp)
HAL COMP Callback pointer definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00U, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01U, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02U, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}
enum | HAL_COMP_CallbackIDTypeDef { HAL_COMP_TRIGGER_CB_ID = 0x00U, HAL_COMP_MSPINIT_CB_ID = 0x01U, HAL_COMP_MSPDEINIT_CB_ID = 0x02U }
HAL COMP Callback ID enumeration definition. More...

Define Documentation

#define COMP_STATE_BITFIELD_LOCK (0x10U)

HAL COMP state machine: HAL COMP states definition.

Definition at line 87 of file stm32g0xx_hal_comp.h.

Typedef Documentation

typedef struct __COMP_HandleTypeDef COMP_HandleTypeDef

COMP Handle Structure definition.

typedef void(* pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp)

HAL COMP Callback pointer definition.

pointer to a COMP callback function

Definition at line 133 of file stm32g0xx_hal_comp.h.

Enumeration Type Documentation

enum HAL_COMP_CallbackIDTypeDef

HAL COMP Callback ID enumeration definition.

Enumerator:
HAL_COMP_TRIGGER_CB_ID

COMP trigger callback ID

HAL_COMP_MSPINIT_CB_ID

COMP Msp Init callback ID

HAL_COMP_MSPDEINIT_CB_ID

COMP Msp DeInit callback ID

Definition at line 123 of file stm32g0xx_hal_comp.h.

enum HAL_COMP_StateTypeDef
Enumerator:
HAL_COMP_STATE_RESET

COMP not yet initialized

HAL_COMP_STATE_RESET_LOCKED

COMP not yet initialized and configuration is locked

HAL_COMP_STATE_READY

COMP initialized and ready for use

HAL_COMP_STATE_READY_LOCKED

COMP initialized but configuration is locked

HAL_COMP_STATE_BUSY

COMP is running

HAL_COMP_STATE_BUSY_LOCKED

COMP is running and configuration is locked

Definition at line 88 of file stm32g0xx_hal_comp.h.

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STM32G0C1xx HAL User Manual: COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_InitTypeDef Struct Reference
COMP Exported Types

COMP Init structure definition. More...

#include <stm32g0xx_hal_comp.h>

Data Fields

uint32_t | WindowMode
uint32_t | WindowOutput
uint32_t | Mode
uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | Hysteresis
uint32_t | OutputPol
uint32_t | BlankingSrce
uint32_t | TriggerMode

Detailed Description

COMP Init structure definition.

Definition at line 48 of file stm32g0xx_hal_comp.h.

Field Documentation

uint32_t COMP_InitTypeDef::BlankingSrce

Set comparator blanking source. This parameter can be a value of COMP blanking source

Definition at line 76 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Hysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of COMP hysteresis

Definition at line 70 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of COMP input minus (inverting input)

Definition at line 67 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of COMP input plus (non-inverting input)

Definition at line 64 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Mode

Set comparator operating mode to adjust power and speed. Note: For the characteristics of comparator power modes (propagation delay and power consumption), refer to device datasheet. This parameter can be a value of COMP power mode

Definition at line 59 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::OutputPol

Set comparator output polarity. This parameter can be a value of COMP output Polarity

Definition at line 73 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::TriggerMode

Set the comparator output triggering External Interrupt Line (EXTI). This parameter can be a value of COMP output to EXTI

Definition at line 79 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::WindowMode

Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP<x> and COMP<x+1>). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode, except for window mode with COMP2 and COMP3 (for devices featuring COMP3): it must be set from COMP3 instance. This parameter can be a value of COMP Window Mode

Definition at line 51 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::WindowOutput

Set window mode output. This parameter can be a value of COMP Window output

Definition at line 56 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_comp.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __COMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__COMP_HandleTypeDef Struct Reference
COMP Exported Types

COMP Handle Structure definition. More...

#include <stm32g0xx_hal_comp.h>

Data Fields

COMP_TypeDef * | Instance
COMP_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_COMP_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TriggerCallback )(struct __COMP_HandleTypeDef *hcomp)
void(* | MspInitCallback )(struct __COMP_HandleTypeDef *hcomp)
void(* | MspDeInitCallback )(struct __COMP_HandleTypeDef *hcomp)

Detailed Description

COMP Handle Structure definition.

Definition at line 102 of file stm32g0xx_hal_comp.h.

Field Documentation

__IO uint32_t __COMP_HandleTypeDef::ErrorCode

COMP error code

Definition at line 111 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_GetError(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

COMP_InitTypeDef __COMP_HandleTypeDef::Init

COMP required parameters

Definition at line 108 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

COMP_TypeDef* __COMP_HandleTypeDef::Instance

Register base address

Definition at line 107 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetError(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

HAL_LockTypeDef __COMP_HandleTypeDef::Lock

Locking object

Definition at line 109 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

void(* __COMP_HandleTypeDef::MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP Msp DeInit callback

Definition at line 115 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

void(* __COMP_HandleTypeDef::MspInitCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP Msp Init callback

Definition at line 114 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

__IO HAL_COMP_StateTypeDef __COMP_HandleTypeDef::State

COMP communication state

Definition at line 110 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_RegisterCallback(), HAL_COMP_Start(), HAL_COMP_Stop(), and HAL_COMP_UnRegisterCallback().

void(* __COMP_HandleTypeDef::TriggerCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP trigger callback

Definition at line 113 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_comp.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Error Code

Defines
COMP Error Code
COMP Exported Constants

Defines

#define | HAL_COMP_ERROR_NONE (0x00UL)
#define | HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)

Define Documentation

#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)

Invalid Callback error

Definition at line 151 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

#define HAL_COMP_ERROR_NONE (0x00UL)

No error

Definition at line 149 of file stm32g0xx_hal_comp.h.

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STM32G0C1xx HAL User Manual: COMP Window Mode

Defines
COMP Window Mode
COMP Exported Constants

Defines

#define | COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)
#define | COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2)

Define Documentation

#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 161 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2)

Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). If used from COMP3 instance (when available), comparators instances pair COMP2 and COMP3 have their input plus connected together, the common input is COMP2 input plus (COMP3 input plus is no more accessible).

Definition at line 162 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWMODE_DISABLE (0x00000000UL)

Window mode disable: Comparators instances pair COMP1 and COMP2 are independent

Definition at line 160 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Window output

Defines
COMP Window output
COMP Exported Constants

Defines

#define | COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL)
#define | COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT)
#define | COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2)
#define | COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT)
#define | COMP_WINDOWOUTPUT_BOTH (0x00000001UL)

Define Documentation

#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL)

Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above.

Definition at line 178 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT)

Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.

Definition at line 171 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2)

Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.

Definition at line 173 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT)

Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window).

Definition at line 176 of file stm32g0xx_hal_comp.h.

#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL)

Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window.

Definition at line 170 of file stm32g0xx_hal_comp.h.

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STM32G0C1xx HAL User Manual: COMP power mode

Defines
COMP power mode
COMP Exported Constants

Defines

#define | COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)

Define Documentation

#define COMP_POWERMODE_HIGHSPEED (0x00000000UL)

High Speed

Definition at line 189 of file stm32g0xx_hal_comp.h.

#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)

Medium Speed

Definition at line 190 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP input plus (non-inverting input)

Defines
COMP input plus (non-inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)

Define Documentation

#define COMP_INPUT_PLUS_IO1 (0x00000000UL)

Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2, pin PB0 for COMP3 (for devices featuring COMP3 instance))

Definition at line 198 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2, pin PC1 for COMP3 (for devices featuring COMP3 instance))

Definition at line 199 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)

Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2, pin PE7 for COMP3 (for devices featuring COMP3 instance))

Definition at line 200 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP input minus (inverting input)

Defines
COMP input minus (inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO3 (COMP_CSR_INMSEL_3 )

Define Documentation

#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0)

Comparator input minus connected to 1/2 VrefInt

Definition at line 209 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL)

Comparator input minus connected to 1/4 VrefInt

Definition at line 208 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 )

Comparator input minus connected to 3/4 VrefInt

Definition at line 210 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)

Definition at line 212 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)

Definition at line 213 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )

Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2, pin PB2 for COMP3 (for devices featuring COMP3 instance))

Definition at line 214 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2, pin PC0 for COMP3 (for devices featuring COMP3 instance))

Definition at line 215 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO3 (COMP_CSR_INMSEL_3 )

Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2, pin PE8 for COMP3 (for devices featuring COMP3 instance))

Definition at line 216 of file stm32g0xx_hal_comp.h.

#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to VrefInt

Definition at line 211 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP hysteresis

Defines
COMP hysteresis
COMP Exported Constants

Defines

#define | COMP_HYSTERESIS_NONE (0x00000000UL)
#define | COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Define Documentation

#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level high

Definition at line 227 of file stm32g0xx_hal_comp.h.

#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)

Hysteresis level low

Definition at line 225 of file stm32g0xx_hal_comp.h.

#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )

Hysteresis level medium

Definition at line 226 of file stm32g0xx_hal_comp.h.

#define COMP_HYSTERESIS_NONE (0x00000000UL)

No hysteresis

Definition at line 224 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP output Polarity

Defines
COMP output Polarity
COMP Exported Constants

Defines

#define | COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

Define Documentation

#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus)

Definition at line 236 of file stm32g0xx_hal_comp.h.

#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)

COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus)

Definition at line 235 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP blanking source

Defines
COMP blanking source
COMP Exported Constants

Defines

#define | COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | COMP_BLANKINGSRC_TIM1_OC4 (COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_2)
#define | COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKING_3)
#define | COMP_BLANKINGSRC_TIM15_OC2 (COMP_CSR_BLANKING_4)

Define Documentation

#define COMP_BLANKINGSRC_NONE (0x00000000UL)

Comparator output without blanking

Definition at line 244 of file stm32g0xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM15_OC2 (COMP_CSR_BLANKING_4)

Comparator output blanking source TIM15 OC2 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 250 of file stm32g0xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC4 (COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC4 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 246 of file stm32g0xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_1)

Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 247 of file stm32g0xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_2)

Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 248 of file stm32g0xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKING_3)

Comparator output blanking source TIM3 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 249 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Output Level

Defines
COMP Output Level
COMP Exported Constants

Defines

#define | COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Define Documentation

#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Definition at line 267 of file stm32g0xx_hal_comp.h.

#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)

Definition at line 264 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP output to EXTI

Defines
COMP output to EXTI
COMP Exported Constants

Defines

#define | COMP_TRIGGERMODE_NONE (0x00000000UL)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Define Documentation

#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on falling edge

Definition at line 280 of file stm32g0xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event only (without interruption), on rising edge

Definition at line 279 of file stm32g0xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges

Definition at line 281 of file stm32g0xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on falling edge

Definition at line 277 of file stm32g0xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event with interruption, on rising edge

Definition at line 276 of file stm32g0xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges

Definition at line 278 of file stm32g0xx_hal_comp.h.

#define COMP_TRIGGERMODE_NONE (0x00000000UL)

Comparator output triggering no External Interrupt Line

Definition at line 275 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Handle Management

Defines
COMP Handle Management
COMP Exported Macros

Defines

#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)
Reset COMP handle state.
#define | COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
Check whether the specified comparator is locked.

Define Documentation

#define __HAL_COMP_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)

Disable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 332 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)

Enable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 325 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_IS_LOCKED ( __HANDLE__ ) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)

Check whether the specified comparator is locked.

Parameters:
__HANDLE__ COMP handle
Return values:
Value 0 if COMP instance is not locked, value 1 if COMP instance is locked

Definition at line 350 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

#define __HAL_COMP_LOCK ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)

Lock the specified comparator configuration.

Note:
Using this macro induce HAL COMP handle state machine being no more in line with COMP instance state. To keep HAL COMP handle state machine updated, it is recommended to use function "HAL_COMP_Lock')".
Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 343 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Lock().

#define __HAL_COMP_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
                                                      (__HANDLE__)->MspInitCallback = NULL;            \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                    } while(0)

Reset COMP handle state.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 304 of file stm32g0xx_hal_comp.h.

#define COMP_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)

Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 318 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP external interrupt line management

Defines
COMP external interrupt line management
COMP Exported Macros

Defines

#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line rising flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI rising flag.
#define | __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line falling flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI falling flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line rising flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI rising flag.
#define | __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line falling flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI falling flag.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP3 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP3 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
Generate a software interrupt on the COMP3 EXTI line.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line in event mode.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line in event mode.
#define | __HAL_COMP_COMP3_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP3)
Check whether the COMP3 EXTI line rising flag is set.
#define | __HAL_COMP_COMP3_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP3)
Clear the COMP3 EXTI rising flag.
#define | __HAL_COMP_COMP3_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP3)
Check whether the COMP3 EXTI line falling flag is set.
#define | __HAL_COMP_COMP3_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP3)
Clear the COMP3 EXTI falling flag.

Define Documentation

#define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG ( ) LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP1)

Clear the COMP1 EXTI falling flag.

Return values:
None

Definition at line 454 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG ( ) LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP1)

Clear the COMP1 EXTI rising flag.

Return values:
None

Definition at line 442 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 430 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 382 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 412 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 370 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                             } while(0)

Disable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 397 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 424 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 376 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 406 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 364 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                             } while(0)

Enable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 388 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)

Generate a software interrupt on the COMP1 EXTI line.

Return values:
None

Definition at line 418 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG ( ) LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP1)

Check whether the COMP1 EXTI line falling flag is set.

Return values:
RESET or SET

Definition at line 448 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG ( ) LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP1)

Check whether the COMP1 EXTI line rising flag is set.

Return values:
RESET or SET

Definition at line 436 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG ( ) LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP2)

Clear the COMP2 EXTI falling flag.

Return values:
None

Definition at line 550 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG ( ) LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP2)

Clear the COMP2 EXTI rising flag.

Return values:
None

Definition at line 538 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 526 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 478 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 508 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 466 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
                                                             } while(0)

Disable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 493 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 520 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 472 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 502 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 460 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
                                                             } while(0)

Enable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 484 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)

Generate a software interrupt on the COMP2 EXTI line.

Return values:
None

Definition at line 514 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG ( ) LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP2)

Check whether the COMP2 EXTI line falling flag is set.

Return values:
RESET or SET

Definition at line 544 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG ( ) LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP2)

Check whether the COMP2 EXTI line rising flag is set.

Return values:
RESET or SET

Definition at line 532 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_CLEAR_FALLING_FLAG ( ) LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP3)

Clear the COMP3 EXTI falling flag.

Return values:
None

Definition at line 646 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_CLEAR_RISING_FLAG ( ) LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP3)

Clear the COMP3 EXTI rising flag.

Return values:
None

Definition at line 634 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)

Disable the COMP3 EXTI line in event mode.

Return values:
None

Definition at line 622 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)

Disable the COMP3 EXTI line falling edge trigger.

Return values:
None

Definition at line 574 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)

Disable the COMP3 EXTI line in interrupt mode.

Return values:
None

Definition at line 604 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)

Disable the COMP3 EXTI line rising edge trigger.

Return values:
None

Definition at line 562 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
                                                             } while(0)

Disable the COMP3 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 589 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)

Enable the COMP3 EXTI line in event mode.

Return values:
None

Definition at line 616 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)

Enable the COMP3 EXTI line falling edge trigger.

Return values:
None

Definition at line 568 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)

Enable the COMP3 EXTI line in interrupt mode.

Return values:
None

Definition at line 598 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)

Enable the COMP3 EXTI line rising edge trigger.

Return values:
None

Definition at line 556 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
                                                             } while(0)

Enable the COMP3 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 580 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)

Generate a software interrupt on the COMP3 EXTI line.

Return values:
None

Definition at line 610 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_GET_FALLING_FLAG ( ) LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP3)

Check whether the COMP3 EXTI line falling flag is set.

Return values:
RESET or SET

Definition at line 640 of file stm32g0xx_hal_comp.h.

#define __HAL_COMP_COMP3_EXTI_GET_RISING_FLAG ( ) LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP3)

Check whether the COMP3 EXTI line rising flag is set.

Return values:
RESET or SET

Definition at line 628 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP window mode instance differentiator

Defines
COMP window mode instance differentiator
COMP Private Constants

Defines

#define COMP_WINDOWMODE_COMP2 0x00001000U

Define Documentation

#define COMP_WINDOWMODE_COMP2 0x00001000U

COMP window mode using common input of COMP instance: COMP2

Definition at line 666 of file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP EXTI Lines

Defines
COMP EXTI Lines
COMP Private Constants

Defines

#define | COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17)
#define | COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18)
#define | COMP_EXTI_LINE_COMP3 (EXTI_IMR1_IM20)
#define | COMP_EXTI_IT (0x00000001UL)
#define | COMP_EXTI_EVENT (0x00000002UL)
#define | COMP_EXTI_RISING (0x00000010UL)
#define | COMP_EXTI_FALLING (0x00000020UL)

Define Documentation

#define COMP_EXTI_EVENT (0x00000002UL)

EXTI line event only (without interruption)

Definition at line 687 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_FALLING (0x00000020UL)

EXTI line event on falling edge

Definition at line 689 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_IT (0x00000001UL)

EXTI line event with interruption

Definition at line 686 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17)

EXTI line 17 connected to COMP1 output

Definition at line 674 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18)

EXTI line 18 connected to COMP2 output

Definition at line 675 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_LINE_COMP3 (EXTI_IMR1_IM20)

EXTI line 20 connected to COMP3 output

Definition at line 677 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_RISING (0x00000010UL)

EXTI line event on rising edge

Definition at line 688 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Private Constants

Modules | Defines
COMP Private Constants
COMP

Modules

COMP window mode instance differentiator
COMP EXTI Lines

Defines

#define | COMP_DELAY_STARTUP_US (80UL)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)
#define | COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Define Documentation

#define COMP_DELAY_STARTUP_US (80UL)

Delay for COMP startup time

Definition at line 186 of file stm32g0xx_hal_comp.c.

Referenced by HAL_COMP_Start().

#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)

Delay for COMP voltage scaler stabilization time

Definition at line 192 of file stm32g0xx_hal_comp.c.

Referenced by HAL_COMP_Init().

#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Definition at line 194 of file stm32g0xx_hal_comp.c.

Referenced by HAL_COMP_GetOutputLevel().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP private macros to get EXTI line associated with comparators

Defines
COMP private macros to get EXTI line associated with comparators
COMP Private Macros

Defines

#define COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.

Define Documentation

#define COMP_GET_EXTI_LINE ( __INSTANCE__ )
Value:
(((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
                                             :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
                                             : COMP_EXTI_LINE_COMP3)

Get the specified EXTI line for a comparator instance.

Parameters:
__INSTANCE__ specifies the COMP instance.
Return values:
value of COMP EXTI Lines

Definition at line 712 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP private macros to check input parameters

Defines
COMP private macros to check input parameters
COMP Private Macros

Defines

#define | IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__)
#define | IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)
#define | IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Define Documentation

#define IS_COMP_BLANKINGSRC_INSTANCE | ( | __INSTANCE__,
 |  | __OUTPUT_BLANKING_SOURCE__
 | ) | (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))

Definition at line 785 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_BLANKINGSRCE ( __OUTPUT_BLANKING_SOURCE__ )
Value:
(   ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)               \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC4)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2)          \
  )

Definition at line 774 of file stm32g0xx_hal_comp.h.

#define IS_COMP_HYSTERESIS ( __HYSTERESIS__ )
Value:
(((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))

Definition at line 766 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3))

Definition at line 756 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))

Definition at line 752 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_OUTPUT_LEVEL ( __OUTPUT_LEVEL__ )
Value:
(((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))

Definition at line 797 of file stm32g0xx_hal_comp.h.

#define IS_COMP_OUTPUTPOL ( __POL__ )
Value:
(((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))

Definition at line 771 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_POWERMODE ( __POWERMODE__ )
Value:
(((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)    )

Definition at line 749 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_TRIGGERMODE ( __MODE__ )
Value:
(((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))

Definition at line 789 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_WINDOWMODE | ( | __INSTANCE__,
 |  | __WINDOWMODE__
 | ) |
Value:
(((__INSTANCE__) == COMP3) \
  ? \
  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                ||  \
   ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)  ) \
  :\
  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                ||  \
   ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)||  \
   ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)  ) \
)

Definition at line 727 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_WINDOWOUTPUT ( __WINDOWOUTPUT__ )
Value:
(((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \
                                                ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1)     || \
                                                ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP2)     || \
                                                ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH)        )

Definition at line 744 of file stm32g0xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32g0xx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 49 of file stm32g0xx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 63 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 55 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 65 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 51 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 71 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 69 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 67 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 53 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 57 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 59 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of CORTEX MPU TEX Levels

Definition at line 61 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_cortex.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX SysTick clock source

Defines
CORTEX SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | SYSTICK_CLKSOURCE_HCLK 0x00000004U

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK 0x00000004U

Definition at line 93 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

Definition at line 92 of file stm32g0xx_hal_cortex.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX MPU HFNMI and PRIVILEGED Access control

Defines
CORTEX MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define | MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define | MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)

Definition at line 104 of file stm32g0xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Definition at line 106 of file stm32g0xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U

Definition at line 103 of file stm32g0xx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)

Definition at line 105 of file stm32g0xx_hal_cortex.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00)

Definition at line 115 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01)

Definition at line 114 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Definition at line 124 of file stm32g0xx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)

Definition at line 123 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Definition at line 133 of file stm32g0xx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)

Definition at line 132 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)

Definition at line 141 of file stm32g0xx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Definition at line 142 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)

Definition at line 150 of file stm32g0xx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Definition at line 151 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX MPU TEX Levels

Defines
CORTEX MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00)

Definition at line 159 of file stm32g0xx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01)

Definition at line 160 of file stm32g0xx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02)

Definition at line 161 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Define Documentation

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)

Definition at line 178 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)

Definition at line 188 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)

Definition at line 175 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)

Definition at line 185 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)

Definition at line 191 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)

Definition at line 171 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)

Definition at line 181 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07)

Definition at line 169 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)

Definition at line 179 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)

Definition at line 189 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)

Definition at line 192 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)

Definition at line 172 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)

Definition at line 182 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)

Definition at line 176 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)

Definition at line 186 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Definition at line 193 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)

Definition at line 173 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)

Definition at line 183 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08)

Definition at line 170 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)

Definition at line 180 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)

Definition at line 190 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)

Definition at line 177 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)

Definition at line 187 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)

Definition at line 174 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)

Definition at line 184 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)

Definition at line 204 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)

Definition at line 201 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05)

Definition at line 205 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Definition at line 206 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01)

Definition at line 202 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)

Definition at line 203 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00)

Definition at line 214 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01)

Definition at line 215 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02)

Definition at line 216 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03)

Definition at line 217 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04)

Definition at line 218 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05)

Definition at line 219 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06)

Definition at line 220 of file stm32g0xx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07)

Definition at line 221 of file stm32g0xx_hal_cortex.h.

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STM32G0C1xx HAL User Manual: CORTEX Exported Macros

CORTEX Exported Macros
CORTEX
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STM32G0C1xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disable a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
Return values:
None

Definition at line 164 of file stm32g0xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enable a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
Return values:
None

Definition at line 148 of file stm32g0xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Sets the priority of an interrupt.

Parameters:
IRQn | External interrupt number . This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to stm32g0xx.h file)
PreemptPriority | The preemption priority for the IRQn channel. This parameter can be a value between 0 and 3. A lower priority value indicates a higher priority
SubPriority | the subpriority level for the IRQ channel. with stm32g0xx devices, this parameter is a dummy value and it is ignored, because no subpriority supported in Cortex M0+ based products.
Return values:
None

Definition at line 131 of file stm32g0xx_hal_cortex.c.

References assert_param, and IS_NVIC_PREEMPTION_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SystemReset ( void )

Initiate a system reset request to reset the MCU.

Return values:
None

Definition at line 177 of file stm32g0xx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 190 of file stm32g0xx_hal_cortex.c.

Referenced by HAL_InitTick().

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STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

uint32_t | HAL_NVIC_GetPriority (IRQn_Type IRQn)
Get the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_Disable (void)
Disable the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initialize and configure the Region and the memory to be protected.

Parameters:
MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 362 of file stm32g0xx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_MPU_Disable ( void )

Disable the MPU.

Return values:
None

Definition at line 346 of file stm32g0xx_hal_cortex.c.

void HAL_MPU_Enable ( uint32_t MPU_Control )

Enable the MPU.

Parameters:
MPU_Control Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged access to the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 331 of file stm32g0xx_hal_cortex.c.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clear the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
Return values:
None

Definition at line 268 of file stm32g0xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 252 of file stm32g0xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetPriority ( IRQn_Type IRQn )

Get the priority of an interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
Return values:
None

Definition at line 221 of file stm32g0xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Set Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
Return values:
None

Definition at line 234 of file stm32g0xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 312 of file stm32g0xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configure the SysTick clock source.

Parameters:
CLKSource specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 285 of file stm32g0xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

Handle SYSTICK interrupt request.

Return values:
None

Definition at line 303 of file stm32g0xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                                   ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 312 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                                   ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 309 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                                   ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 306 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                                   ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 303 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                                   ((STATE) == MPU_REGION_DISABLE))

Definition at line 300 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER1) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER2) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER3) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER4) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER5) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER6) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER7))

Definition at line 326 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 319 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_256B)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 335 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FFU)

Definition at line 361 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                                   ((TYPE) == MPU_TEX_LEVEL1)  || \
                                                   ((TYPE) == MPU_TEX_LEVEL2))

Definition at line 315 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) > SysTick_IRQn)

Definition at line 294 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetPendingIRQ(), and HAL_NVIC_SetPendingIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x4U)

Definition at line 292 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                                   ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 296 of file stm32g0xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC Private Functions

Functions
CRC Private Functions
CRC

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.

Function Documentation

static uint32_t CRC_Handle_16 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint16_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 16-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 483 of file stm32g0xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

static uint32_t CRC_Handle_8 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint8_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 8-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 432 of file stm32g0xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP (MCU Specific Package)
      (+) DeInitialize the CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 179 of file stm32g0xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 103 of file stm32g0xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 238 of file stm32g0xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initializes the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 223 of file stm32g0xx_hal_crc.c.

Referenced by HAL_CRC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

management functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Detailed Description

management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          using combination of the previous CRC value and the new one.

       [..]  or

      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          independently of the previous CRC value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 287 of file stm32g0xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 339 of file stm32g0xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC handle state.

Parameters:
hcrc CRC handle
Return values:
HAL state

Definition at line 406 of file stm32g0xx_hal_crc.c.

References CRC_HandleTypeDef::State.

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STM32G0C1xx HAL User Manual: CRC Exported Types

Data Structures | Enumerations
CRC Exported Types
CRC

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef

CRC HAL State Structure definition.

Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 46 of file stm32g0xx_hal_crc.h.

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STM32G0C1xx HAL User Manual: CRC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_InitTypeDef Struct Reference
CRC Exported Types

CRC Init Structure definition. More...

#include <stm32g0xx_hal_crc.h>

Data Fields

uint8_t | DefaultPolynomialUse
uint8_t | DefaultInitValueUse
uint32_t | GeneratingPolynomial
uint32_t | CRCLength
uint32_t | InitValue
uint32_t | InputDataInversionMode
uint32_t | OutputDataInversionMode

Detailed Description

CRC Init Structure definition.

Definition at line 58 of file stm32g0xx_hal_crc.h.

Field Documentation

uint32_t CRC_InitTypeDef::CRCLength

This parameter is a value of Polynomial sizes to configure the peripheral and indicates CRC length. Value can be either one of

  • CRC_POLYLENGTH_32B (32-bit CRC),
  • CRC_POLYLENGTH_16B (16-bit CRC),
  • CRC_POLYLENGTH_8B (8-bit CRC),
  • CRC_POLYLENGTH_7B (7-bit CRC).

Definition at line 79 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultInitValueUse

This parameter is a value of Indicates whether or not default init value is used and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set.

Definition at line 68 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultPolynomialUse

This parameter is a value of Indicates whether or not default polynomial is used and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set.

Definition at line 60 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::GeneratingPolynomial

Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree respectively equal to 7, 8, 16 or 32. This field is written in normal, representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.

Definition at line 73 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InitValue

Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE.

Definition at line 86 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InputDataInversionMode

This parameter is a value of Input Data Inversion Modes and specifies input data inversion mode. Can be either one of the following values

  • CRC_INPUTDATA_INVERSION_NONE no input data inversion
  • CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
  • CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
  • CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458

Definition at line 89 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::OutputDataInversionMode

This parameter is a value of Output Data Inversion Modes and specifies output data (i.e. CRC) inversion mode. Can be either

  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
  • CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488

Definition at line 99 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_crc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Exported Types

CRC Handle Structure definition. More...

#include <stm32g0xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
CRC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State
uint32_t | InputDataFormat

Detailed Description

CRC Handle Structure definition.

Definition at line 109 of file stm32g0xx_hal_crc.h.

Field Documentation

CRC_InitTypeDef CRC_HandleTypeDef::Init

CRC configuration parameters

Definition at line 113 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_HandleTypeDef::InputDataFormat

This parameter is a value of Input Buffer Format and specifies input data format. Can be either

  • CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
  • CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
  • CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)

Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed above

Definition at line 119 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), and HAL_CRC_Init().

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 111 of file stm32g0xx_hal_crc.h.

Referenced by CRC_Handle_16(), CRC_Handle_8(), HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), and HAL_CRCEx_Polynomial_Set().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC Locking object

Definition at line 115 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 117 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), and HAL_CRCEx_Output_Data_Reverse().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_crc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Default CRC generating polynomial

Defines
Default CRC generating polynomial
CRC Exported Constants

Defines

#define DEFAULT_CRC32_POLY 0x04C11DB7U

Define Documentation

#define DEFAULT_CRC32_POLY 0x04C11DB7U

X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1

Definition at line 144 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Initial CRC default value

Definition at line 152 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Indicates whether or not default polynomial is used

Defines
Indicates whether or not default polynomial is used
CRC Exported Constants

Defines

#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Disable default generating polynomial 0x04C11DB7

Definition at line 161 of file stm32g0xx_hal_crc.h.

#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)

Enable default generating polynomial 0x04C11DB7

Definition at line 160 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Indicates whether or not default init value is used

Defines
Indicates whether or not default init value is used
CRC Exported Constants

Defines

#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Disable initial CRC default value

Definition at line 170 of file stm32g0xx_hal_crc.h.

#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)

Enable initial CRC default value

Definition at line 169 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Polynomial sizes to configure the peripheral

Defines
Polynomial sizes to configure the peripheral
CRC Exported Constants

Defines

#define | CRC_POLYLENGTH_32B 0x00000000U
#define | CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | CRC_POLYLENGTH_7B CRC_CR_POLYSIZE

Define Documentation

#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

Resort to a 16-bit long generating polynomial

Definition at line 179 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_32B 0x00000000U

Resort to a 32-bit long generating polynomial

Definition at line 178 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE

Resort to a 7-bit long generating polynomial

Definition at line 181 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

Resort to a 8-bit long generating polynomial

Definition at line 180 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32G0C1xx HAL User Manual: CRC polynomial possible sizes actual definitions

Defines
CRC polynomial possible sizes actual definitions
CRC Exported Constants

Defines

#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U

Define Documentation

#define HAL_CRC_LENGTH_16B 16U

16-bit long CRC

Definition at line 190 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_32B 32U

32-bit long CRC

Definition at line 189 of file stm32g0xx_hal_crc.h.

#define HAL_CRC_LENGTH_7B 7U

7-bit long CRC

Definition at line 192 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_8B 8U

8-bit long CRC

Definition at line 191 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32G0C1xx HAL User Manual: Input Buffer Format

Defines
Input Buffer Format
CRC Exported Constants

Defines

#define | CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U
#define | CRC_INPUTDATA_FORMAT_BYTES 0x00000001U
#define | CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U
#define | CRC_INPUTDATA_FORMAT_WORDS 0x00000003U

Define Documentation

#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U

Input data in byte format

Definition at line 205 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U

Input data in half-word format

Definition at line 206 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U

Undefined input data format

Definition at line 204 of file stm32g0xx_hal_crc.h.

#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U

Input data in word format

Definition at line 207 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

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STM32G0C1xx HAL User Manual: CRC Exported Macros

Defines
CRC Exported Macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store data in the Independent Data (ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the data stored in the Independent Data (ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Reset CRC Data Register.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 232 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Return the data stored in the Independent Data (ID) register.

Parameters:
__HANDLE__ CRC handle
Note:
Refer to the Reference Manual to get the authorized __VALUE__ length in bits
Return values:
Value of the ID register

Definition at line 257 of file stm32g0xx_hal_crc.h.

#define __HAL_CRC_INITIALCRCVALUE_CONFIG | ( | __HANDLE__,
 |  | __INIT__
 | ) | ((__HANDLE__)->Instance->INIT = (__INIT__))

Set CRC INIT non-default value.

Parameters:
__HANDLE__ | CRC handle
__INIT__ | 32-bit initial value
Return values:
None

Definition at line 240 of file stm32g0xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__ CRC handle.
Return values:
None

Definition at line 225 of file stm32g0xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Store data in the Independent Data (ID) register.

Parameters:
__HANDLE__ | CRC handle
__VALUE__ | Value to be stored in the ID register
Note:
Refer to the Reference Manual to get the authorized __VALUE__ length in bits
Return values:
None

Definition at line 249 of file stm32g0xx_hal_crc.h.

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STM32G0C1xx HAL User Manual: CRC Private Macros

Defines
CRC Private Macros
CRC

Defines

#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Define Documentation

#define IS_CRC_INPUTDATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))

Definition at line 279 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_CRC_POL_LENGTH ( LENGTH )
Value:
(((LENGTH) == CRC_POLYLENGTH_32B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
                                       ((LENGTH) == CRC_POLYLENGTH_7B))

Definition at line 274 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define IS_DEFAULT_INIT_VALUE ( VALUE )
Value:
(((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))

Definition at line 271 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_DEFAULT_POLYNOMIAL ( DEFAULT )
Value:
(((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))

Definition at line 268 of file stm32g0xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32G0C1xx HAL User Manual: Extended Initialization/de-initialization functions

Functions
Extended Initialization/de-initialization functions
CRC Extended Exported Functions

Extended Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended Initialization and Configuration functions.

 ===============================================================================
            ##### Extended configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the generating polynomial
      (+) Configure the input data inversion
      (+) Configure the output data inversion

Function Documentation

HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | InputReverseMode
 | ) |  |

Set the Reverse Input data mode.

Parameters:
hcrc CRC handle
InputReverseMode Input Data inversion mode. This parameter can be one of the following values:
  • CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
  • CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
  • CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
  • CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
Return values:
HAL status

Definition at line 159 of file stm32g0xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | OutputReverseMode
 | ) |  |

Set the Reverse Output data mode.

Parameters:
hcrc CRC handle
OutputReverseMode Output Data inversion mode. This parameter can be one of the following values:
  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
  • CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
Return values:
HAL status

Definition at line 185 of file stm32g0xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_OUTPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | Pol,
 |  | uint32_t | PolyLength
 | ) |  |

Initialize the CRC polynomial if different from default one.

Parameters:
hcrc CRC handle
Pol CRC generating polynomial (7, 8, 16 or 32-bit long). This parameter is written in normal representation, e.g.
  • for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
  • for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
PolyLength CRC polynomial length. This parameter can be one of the following values:
  • CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
  • CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
  • CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
  • CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
Return values:
HAL status

Definition at line 89 of file stm32g0xx_hal_crc_ex.c.

References assert_param, CRC_POLYLENGTH_16B, CRC_POLYLENGTH_32B, CRC_POLYLENGTH_7B, CRC_POLYLENGTH_8B, HAL_CRC_LENGTH_16B, HAL_CRC_LENGTH_7B, HAL_CRC_LENGTH_8B, CRC_HandleTypeDef::Instance, and IS_CRC_POL_LENGTH.

Referenced by HAL_CRC_Init().

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STM32G0C1xx HAL User Manual: Input Data Inversion Modes

Defines
Input Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_INPUTDATA_INVERSION_NONE 0x00000000U
#define | CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0
#define | CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1
#define | CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN

Define Documentation

#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0

Byte-wise input data inversion

Definition at line 48 of file stm32g0xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1

HalfWord-wise input data inversion

Definition at line 49 of file stm32g0xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U

No input data inversion

Definition at line 47 of file stm32g0xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN

Word-wise input data inversion

Definition at line 50 of file stm32g0xx_hal_crc_ex.h.

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STM32G0C1xx HAL User Manual: Output Data Inversion Modes

Defines
Output Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U
#define | CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT

Define Documentation

#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U

No output data inversion

Definition at line 58 of file stm32g0xx_hal_crc_ex.h.

#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT

Bit-wise output data inversion

Definition at line 59 of file stm32g0xx_hal_crc_ex.h.

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STM32G0C1xx HAL User Manual: CRC Extended Exported Macros

Defines
CRC Extended Exported Macros
CRCEx

Defines

#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Define Documentation

#define __HAL_CRC_OUTPUTREVERSAL_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

Unset CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 85 of file stm32g0xx_hal_crc_ex.h.

#define __HAL_CRC_OUTPUTREVERSAL_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

Set CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 78 of file stm32g0xx_hal_crc_ex.h.

#define __HAL_CRC_POLYNOMIAL_CONFIG | ( | __HANDLE__,
 |  | __POLYNOMIAL__
 | ) | ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

Set CRC non-default polynomial.

Parameters:
__HANDLE__ | CRC handle
__POLYNOMIAL__ | 7, 8, 16 or 32-bit polynomial
Return values:
None

Definition at line 93 of file stm32g0xx_hal_crc_ex.h.

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STM32G0C1xx HAL User Manual: CRC Extended Private Macros

Defines
CRC Extended Private Macros
CRCEx

Defines

#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Define Documentation

#define IS_CRC_INPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))

Definition at line 104 of file stm32g0xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Input_Data_Reverse().

#define IS_CRC_OUTPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))

Definition at line 109 of file stm32g0xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Output_Data_Reverse().

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STM32G0C1xx HAL User Manual: HAL CRYP Callback ID enumeration definition

Enumerations
HAL CRYP Callback ID enumeration definition
CRYP Exported Types

HAL CRYP Callback ID enumeration definition. More...

Enumerations

enum HAL_CRYP_CallbackIDTypeDef {
HAL_CRYP_MSPINIT_CB_ID = 0x00U, HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U,
HAL_CRYP_ERROR_CB_ID = 0x04U
}

Detailed Description

HAL CRYP Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_CRYP_CallbackIDTypeDef
Enumerator:
HAL_CRYP_MSPINIT_CB_ID

CRYP MspInit callback ID

HAL_CRYP_MSPDEINIT_CB_ID

CRYP MspDeInit callback ID

HAL_CRYP_INPUT_COMPLETE_CB_ID

CRYP Input FIFO transfer completed callback ID

HAL_CRYP_OUTPUT_COMPLETE_CB_ID

CRYP Output FIFO transfer completed callback ID

HAL_CRYP_ERROR_CB_ID

CRYP Error callback ID

Definition at line 204 of file stm32g0xx_hal_cryp.h.

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STM32G0C1xx HAL User Manual: HAL CRYP Callback pointer definition

Typedefs
HAL CRYP Callback pointer definition
CRYP Exported Types

HAL CRYP Callback pointer definition. More...

Typedefs

typedef void(* pCRYP_CallbackTypeDef )(CRYP_HandleTypeDef *hcryp)

Detailed Description

HAL CRYP Callback pointer definition.

Typedef Documentation

typedef void(* pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp)

pointer to a common CRYP callback function

Definition at line 221 of file stm32g0xx_hal_cryp.h.

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STM32G0C1xx HAL User Manual: CRYP Exported Types

Data Structures | Modules | Typedefs | Enumerations
CRYP Exported Types
CRYP

Data Structures

struct | CRYP_ConfigTypeDef
CRYP Init Structure definition. More...
struct | __CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Modules

HAL CRYP Callback ID enumeration definition

HAL CRYP Callback ID enumeration definition.

HAL CRYP Callback pointer definition

HAL CRYP Callback pointer definition.

Typedefs

typedef struct __CRYP_HandleTypeDef | CRYP_HandleTypeDef
CRYP handle Structure definition.

Enumerations

enum | HAL_CRYP_STATETypeDef { HAL_CRYP_STATE_RESET = 0x00U, HAL_CRYP_STATE_READY = 0x01U, HAL_CRYP_STATE_BUSY = 0x02U, HAL_CRYP_STATE_SUSPENDED = 0x03U }
CRYP State Structure definition. More...
enum | HAL_SuspendTypeDef { HAL_CRYP_SUSPEND_NONE = 0x00U, HAL_CRYP_SUSPEND = 0x01U }
HAL CRYP mode suspend definitions. More...

Typedef Documentation

typedef struct __CRYP_HandleTypeDef CRYP_HandleTypeDef

CRYP handle Structure definition.

Enumeration Type Documentation

enum HAL_CRYP_STATETypeDef

CRYP State Structure definition.

Enumerator:
HAL_CRYP_STATE_RESET

CRYP not yet initialized or disabled

HAL_CRYP_STATE_READY

CRYP initialized and ready for use

HAL_CRYP_STATE_BUSY

CRYP BUSY, internal processing is ongoing

HAL_CRYP_STATE_SUSPENDED

CRYP suspended

Definition at line 81 of file stm32g0xx_hal_cryp.h.

enum HAL_SuspendTypeDef

HAL CRYP mode suspend definitions.

Enumerator:
HAL_CRYP_SUSPEND_NONE

CRYP processing suspension not requested

HAL_CRYP_SUSPEND

CRYP processing suspension requested

Definition at line 95 of file stm32g0xx_hal_cryp.h.

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STM32G0C1xx HAL User Manual: CRYP_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRYP_ConfigTypeDef Struct Reference
CRYP Exported Types

CRYP Init Structure definition. More...

#include <stm32g0xx_hal_cryp.h>

Data Fields

uint32_t | DataType
uint32_t | KeySize
uint32_t * | pKey
uint32_t * | pInitVect
uint32_t | Algorithm
uint32_t * | Header
uint32_t | HeaderSize
uint32_t * | B0
uint32_t | DataWidthUnit
uint32_t | HeaderWidthUnit
uint32_t | KeyIVConfigSkip

Detailed Description

CRYP Init Structure definition.

Definition at line 51 of file stm32g0xx_hal_cryp.h.

Field Documentation

uint32_t CRYP_ConfigTypeDef::Algorithm

DES/ TDES Algorithm ECB/CBC AES Algorithm ECB/CBC/CTR/GCM or CCM This parameter can be a value of CRYP Algorithm Mode

Definition at line 60 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), CRYP_SetDMAConfig(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_Resume(), HAL_CRYP_SetConfig(), and HAL_CRYP_Suspend().

uint32_t* CRYP_ConfigTypeDef::B0

B0 is first authentication block used only in AES CCM mode

Definition at line 67 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::DataType

32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of CRYP Data Type

Definition at line 53 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::DataWidthUnit

Payload Data Width Unit, this parameter can be value of CRYP Data Width Unit

Definition at line 68 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), and HAL_CRYP_Suspend().

uint32_t* CRYP_ConfigTypeDef::Header

used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data.

Definition at line 63 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::HeaderSize

The size of header buffer

Definition at line 66 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t CRYP_ConfigTypeDef::HeaderWidthUnit

Header Width Unit, this parameter can be value of CRYP Header Width Unit

Definition at line 69 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t CRYP_ConfigTypeDef::KeyIVConfigSkip

CRYP peripheral Key and IV configuration skip, to config Key and Initialization Vector only once and to skip configuration for consecutive processings. This parameter can be a value of CRYP Key and IV Configuration Skip Mode

Definition at line 70 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::KeySize

Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. 128 or 256 bit key length in TinyAES This parameter can be a value of CRYP Key Size

Definition at line 55 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_Resume(), HAL_CRYP_SetConfig(), and HAL_CRYP_Suspend().

uint32_t* CRYP_ConfigTypeDef::pInitVect

The initialization vector used also as initialization counter in CTR mode

Definition at line 58 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), HAL_CRYP_Resume(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::pKey

The key used for encryption/decryption

Definition at line 57 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_Read_KeyRegisters(), CRYP_SetKey(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_cryp.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __CRYP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__CRYP_HandleTypeDef Struct Reference
CRYP Exported Types

CRYP handle Structure definition. More...

#include <stm32g0xx_hal_cryp.h>

Data Fields

AES_TypeDef * | Instance
CRYP_ConfigTypeDef Init
FunctionalState | AutoKeyDerivation
uint32_t * | pCrypInBuffPtr
uint32_t * | pCrypOutBuffPtr
__IO uint16_t | CrypHeaderCount
__IO uint16_t | CrypInCount
__IO uint16_t | CrypOutCount
uint16_t | Size
uint32_t | Phase
DMA_HandleTypeDef * hdmain
DMA_HandleTypeDef * hdmaout
HAL_LockTypeDef | Lock
__IO HAL_CRYP_STATETypeDef | State
__IO uint32_t | ErrorCode
uint32_t | KeyIVConfig
uint32_t | SizesSum
void(* | InCpltCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | OutCpltCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | ErrorCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | MspInitCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | MspDeInitCallback )(struct __CRYP_HandleTypeDef *hcryp)
__IO HAL_SuspendTypeDef | SuspendRequest
CRYP_ConfigTypeDef Init_saved
uint32_t * | pCrypInBuffPtr_saved
uint32_t * | pCrypOutBuffPtr_saved
uint32_t | CrypInCount_saved
uint32_t | CrypOutCount_saved
uint32_t | Phase_saved
__IO HAL_CRYP_STATETypeDef | State_saved
uint32_t | IV_saved [4]
uint32_t | SUSPxR_saved [8]
uint32_t | CR_saved
uint32_t | Key_saved [8]
uint16_t | Size_saved
uint16_t | CrypHeaderCount_saved
uint32_t | SizesSum_saved
uint32_t | ResumingFlag
FunctionalState | AutoKeyDerivation_saved

Detailed Description

CRYP handle Structure definition.

Definition at line 106 of file stm32g0xx_hal_cryp.h.

Field Documentation

FunctionalState __CRYP_HandleTypeDef::AutoKeyDerivation

Used only in TinyAES to allow to bypass or not key write-up before decryption. This parameter can be a value of ENABLE/DISABLE

Definition at line 115 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), HAL_CRYP_Resume(), HAL_CRYP_Suspend(), HAL_CRYPEx_DisableAutoKeyDerivation(), and HAL_CRYPEx_EnableAutoKeyDerivation().

FunctionalState __CRYP_HandleTypeDef::AutoKeyDerivation_saved

copy of CRYP handle auto key derivation parameter

Definition at line 193 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::CR_saved

copy of CRYP control register when processing is suspended

Definition at line 181 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

__IO uint16_t __CRYP_HandleTypeDef::CrypHeaderCount

Counter of header data in words

Definition at line 122 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_DeInit(), HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

uint16_t __CRYP_HandleTypeDef::CrypHeaderCount_saved

copy of CRYP header data counter when processing is suspended

Definition at line 187 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

__IO uint16_t __CRYP_HandleTypeDef::CrypInCount

Counter of input data in words

Definition at line 124 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::CrypInCount_saved

copy of CRYP input data counter when processing is suspended

Definition at line 169 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Suspend().

__IO uint16_t __CRYP_HandleTypeDef::CrypOutCount

Counter of output data in words

Definition at line 126 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::CrypOutCount_saved

copy of CRYP output data counter when processing is suspended

Definition at line 171 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Suspend().

void(* __CRYP_HandleTypeDef::ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Error callback

Definition at line 152 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESGCM_Process(), CRYP_ClearCCFlagWhenHigh(), CRYP_DMAError(), CRYP_SetDMAConfig(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

__IO uint32_t __CRYP_HandleTypeDef::ErrorCode

CRYP peripheral error code

Definition at line 140 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_ClearCCFlagWhenHigh(), CRYP_DMAError(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_Read_SuspendRegisters(), CRYP_SetDMAConfig(), CRYP_SetHeaderDMAConfig(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_GetError(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_RegisterCallback(), HAL_CRYP_SetConfig(), HAL_CRYP_UnRegisterCallback(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_CRYPEx_DisableAutoKeyDerivation(), and HAL_CRYPEx_EnableAutoKeyDerivation().

DMA_HandleTypeDef* __CRYP_HandleTypeDef::hdmain

CRYP In DMA handle parameters

Definition at line 132 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_SetDMAConfig(), and CRYP_SetHeaderDMAConfig().

DMA_HandleTypeDef* __CRYP_HandleTypeDef::hdmaout

CRYP Out DMA handle parameters

Definition at line 134 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_SetDMAConfig().

void(* __CRYP_HandleTypeDef::InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Input FIFO transfer completed callback

Definition at line 150 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

CRYP_ConfigTypeDef __CRYP_HandleTypeDef::Init

CRYP required parameters

Definition at line 113 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), CRYP_Read_KeyRegisters(), CRYP_SetDMAConfig(), CRYP_SetKey(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_Resume(), HAL_CRYP_SetConfig(), HAL_CRYP_Suspend(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

CRYP_ConfigTypeDef __CRYP_HandleTypeDef::Init_saved

copy of CRYP required parameters when processing is suspended

Definition at line 163 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

AES_TypeDef* __CRYP_HandleTypeDef::Instance

AES Register base address

Definition at line 111 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_ClearCCFlagWhenHigh(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), CRYP_Read_IVRegisters(), CRYP_Read_SuspendRegisters(), CRYP_SetDMAConfig(), CRYP_SetHeaderDMAConfig(), CRYP_SetKey(), CRYP_WaitOnCCFlag(), CRYP_Write_IVRegisters(), CRYP_Write_KeyRegisters(), CRYP_Write_SuspendRegisters(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_Resume(), HAL_CRYP_SetConfig(), HAL_CRYP_Suspend(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t __CRYP_HandleTypeDef::IV_saved[4]

copy of Initialisation Vector registers

Definition at line 177 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::Key_saved[8]

copy of key registers

Definition at line 183 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::KeyIVConfig

CRYP peripheral Key and IV configuration flag, used when configuration can be skipped

Definition at line 142 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Init().

HAL_LockTypeDef __CRYP_HandleTypeDef::Lock

CRYP locking object

Definition at line 136 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

void(* __CRYP_HandleTypeDef::MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Msp DeInit callback

Definition at line 155 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_DeInit(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

void(* __CRYP_HandleTypeDef::MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Msp Init callback

Definition at line 154 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

void(* __CRYP_HandleTypeDef::OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Output FIFO transfer completed callback

Definition at line 151 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

uint32_t* __CRYP_HandleTypeDef::pCrypInBuffPtr

Pointer to CRYP processing (encryption, decryption,...) buffer

Definition at line 118 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Suspend().

uint32_t* __CRYP_HandleTypeDef::pCrypInBuffPtr_saved

copy of CRYP input pointer when processing is suspended

Definition at line 165 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

uint32_t* __CRYP_HandleTypeDef::pCrypOutBuffPtr

Pointer to CRYP processing (encryption, decryption,...) buffer

Definition at line 120 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Suspend().

uint32_t* __CRYP_HandleTypeDef::pCrypOutBuffPtr_saved

copy of CRYP output pointer when processing is suspended

Definition at line 167 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::Phase

CRYP peripheral phase

Definition at line 130 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), CRYP_SetHeaderDMAConfig(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_Resume(), HAL_CRYP_SetConfig(), HAL_CRYP_Suspend(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t __CRYP_HandleTypeDef::Phase_saved

copy of CRYP authentication phase when processing is suspended

Definition at line 173 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::ResumingFlag

resumption flag to bypass steps already carried out

Definition at line 191 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Resume().

uint16_t __CRYP_HandleTypeDef::Size

Length of input data

Definition at line 128 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Suspend().

uint16_t __CRYP_HandleTypeDef::Size_saved

copy of input buffer size

Definition at line 185 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::SizesSum

Sum of successive payloads lengths (in bytes), stored for a single signature computation after several messages processing

Definition at line 145 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Resume(), HAL_CRYP_Suspend(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t __CRYP_HandleTypeDef::SizesSum_saved

copy of SizesSum when processing is suspended

Definition at line 189 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

__IO HAL_CRYP_STATETypeDef __CRYP_HandleTypeDef::State

CRYP peripheral state

Definition at line 138 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_ClearCCFlagWhenHigh(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_Read_SuspendRegisters(), CRYP_SetHeaderDMAConfig(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_GetState(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), HAL_CRYP_Resume(), HAL_CRYP_SetConfig(), HAL_CRYP_Suspend(), HAL_CRYP_UnRegisterCallback(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_CRYPEx_DisableAutoKeyDerivation(), and HAL_CRYPEx_EnableAutoKeyDerivation().

__IO HAL_CRYP_STATETypeDef __CRYP_HandleTypeDef::State_saved

copy of CRYP peripheral state when processing is suspended

Definition at line 175 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

__IO HAL_SuspendTypeDef __CRYP_HandleTypeDef::SuspendRequest

CRYP peripheral suspension request flag

Definition at line 161 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_ProcessSuspend(), and HAL_CRYP_Suspend().

uint32_t __CRYP_HandleTypeDef::SUSPxR_saved[8]

copy of suspension registers

Definition at line 179 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_cryp.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Error Definition

Defines
CRYP Error Definition
CRYP Exported Constants

Defines

#define | HAL_CRYP_ERROR_NONE 0x00000000U
#define | HAL_CRYP_ERROR_WRITE 0x00000001U
#define | HAL_CRYP_ERROR_READ 0x00000002U
#define | HAL_CRYP_ERROR_DMA 0x00000004U
#define | HAL_CRYP_ERROR_BUSY 0x00000008U
#define | HAL_CRYP_ERROR_TIMEOUT 0x00000010U
#define | HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U
#define | HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U
#define | HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)

Define Documentation

#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U

Sequence are not respected only for GCM or CCM

Definition at line 248 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_BUSY 0x00000008U

Busy flag error

Definition at line 245 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_CRYPEx_DisableAutoKeyDerivation(), and HAL_CRYPEx_EnableAutoKeyDerivation().

#define HAL_CRYP_ERROR_DMA 0x00000004U

DMA error

Definition at line 244 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_DMAError(), CRYP_SetDMAConfig(), and CRYP_SetHeaderDMAConfig().

#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)

Invalid Callback error

Definition at line 250 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

#define HAL_CRYP_ERROR_NONE 0x00000000U

No error

Definition at line 241 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U

Not supported mode

Definition at line 247 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define HAL_CRYP_ERROR_READ 0x00000002U

Read error

Definition at line 243 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U

Timeout error

Definition at line 246 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_ClearCCFlagWhenHigh(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_Read_SuspendRegisters(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_WRITE 0x00000001U

Write error

Definition at line 242 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

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STM32G0C1xx HAL User Manual: CRYP Data Width Unit

Defines
CRYP Data Width Unit
CRYP Exported Constants

Defines

#define | CRYP_DATAWIDTHUNIT_WORD 0x00000000U
#define | CRYP_DATAWIDTHUNIT_BYTE 0x00000001U

Define Documentation

#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U

By default, size unit is byte

Definition at line 262 of file stm32g0xx_hal_cryp.h.

#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U

By default, size unit is word

Definition at line 261 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Suspend().

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STM32G0C1xx HAL User Manual: CRYP Header Width Unit

Defines
CRYP Header Width Unit
CRYP Exported Constants

Defines

#define | CRYP_HEADERWIDTHUNIT_WORD 0x00000000U
#define | CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U

Define Documentation

#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U

By default, header size unit is byte

Definition at line 273 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U

By default, header size unit is word

Definition at line 272 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_GCMCCM_SetHeaderPhase_IT().

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STM32G0C1xx HAL User Manual: CRYP Algorithm Mode

Defines
CRYP Algorithm Mode
CRYP Exported Constants

Defines

#define | CRYP_AES_ECB 0x00000000U
#define | CRYP_AES_CBC AES_CR_CHMOD_0
#define | CRYP_AES_CTR AES_CR_CHMOD_1
#define | CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)
#define | CRYP_AES_CCM AES_CR_CHMOD_2

Define Documentation

#define CRYP_AES_CBC AES_CR_CHMOD_0

Cipher block chaining algorithm

Definition at line 284 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

#define CRYP_AES_CCM AES_CR_CHMOD_2

Counter with Cipher Mode

Definition at line 287 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_IRQHandler(), and HAL_CRYP_Suspend().

#define CRYP_AES_CTR AES_CR_CHMOD_1

Counter mode chaining algorithm

Definition at line 285 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Resume(), and HAL_CRYP_Suspend().

#define CRYP_AES_ECB 0x00000000U

Electronic codebook chaining algorithm

Definition at line 283 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Resume().

#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)

Galois counter mode - Galois message authentication code

Definition at line 286 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), CRYP_Read_SuspendRegisters(), CRYP_SetDMAConfig(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_IRQHandler(), and HAL_CRYP_Suspend().

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STM32G0C1xx HAL User Manual: CRYP Key Size

Defines
CRYP Key Size
CRYP Exported Constants

Defines

#define | CRYP_KEYSIZE_128B 0x00000000U
#define | CRYP_KEYSIZE_256B AES_CR_KEYSIZE

Define Documentation

#define CRYP_KEYSIZE_128B 0x00000000U

128-bit long key

Definition at line 297 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_Read_KeyRegisters(), and CRYP_SetKey().

#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE

256-bit long key

Definition at line 298 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_Read_KeyRegisters(), CRYP_SetKey(), and CRYP_Write_KeyRegisters().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Data Type

Defines
CRYP Data Type
CRYP Exported Constants

Defines

#define | CRYP_DATATYPE_32B 0x00000000U
#define | CRYP_DATATYPE_16B AES_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B AES_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B AES_CR_DATATYPE

Define Documentation

#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0

16-bit data type (half-word swapping)

Definition at line 309 of file stm32g0xx_hal_cryp.h.

#define CRYP_DATATYPE_1B AES_CR_DATATYPE

1-bit data type (bit swapping)

Definition at line 311 of file stm32g0xx_hal_cryp.h.

#define CRYP_DATATYPE_32B 0x00000000U

32-bit data type (no swapping)

Definition at line 308 of file stm32g0xx_hal_cryp.h.

#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1

8-bit data type (byte swapping)

Definition at line 310 of file stm32g0xx_hal_cryp.h.

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STM32G0C1xx HAL User Manual: CRYP Interrupt

Defines
CRYP Interrupt
CRYP Exported Constants

Defines

#define | CRYP_IT_CCFIE AES_CR_CCFIE
#define | CRYP_IT_ERRIE AES_CR_ERRIE
#define | CRYP_IT_WRERR AES_SR_WRERR
#define | CRYP_IT_RDERR AES_SR_RDERR
#define | CRYP_IT_CCF AES_SR_CCF

Define Documentation

#define CRYP_IT_CCF AES_SR_CCF

Computation completed

Definition at line 325 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define CRYP_IT_CCFIE AES_CR_CCFIE

Computation Complete interrupt enable

Definition at line 321 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_IRQHandler(), and HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_IT_ERRIE AES_CR_ERRIE

Error interrupt enable

Definition at line 322 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_IRQHandler(), and HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_IT_RDERR AES_SR_RDERR

Read Error

Definition at line 324 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define CRYP_IT_WRERR AES_SR_WRERR

Write Error

Definition at line 323 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

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STM32G0C1xx HAL User Manual: CRYP Flags

Defines
CRYP Flags
CRYP Exported Constants

Defines

#define | CRYP_FLAG_BUSY AES_SR_BUSY
#define | CRYP_FLAG_WRERR AES_SR_WRERR
#define | CRYP_FLAG_RDERR AES_SR_RDERR
#define | CRYP_FLAG_CCF AES_SR_CCF
#define | CRYP_CCF_CLEAR AES_CR_CCFC
#define | CRYP_ERR_CLEAR AES_CR_ERRC

Define Documentation

#define CRYP_CCF_CLEAR AES_CR_CCFC

Computation Complete Flag Clear

Definition at line 341 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_ClearCCFlagWhenHigh(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_ERR_CLEAR AES_CR_ERRC

Error Flag Clear

Definition at line 342 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_PhaseProcessingResume(), and HAL_CRYP_SetConfig().

#define CRYP_FLAG_BUSY AES_SR_BUSY

GCM process suspension forbidden

Definition at line 336 of file stm32g0xx_hal_cryp.h.

#define CRYP_FLAG_CCF AES_SR_CCF

Computation completed

Definition at line 339 of file stm32g0xx_hal_cryp.h.

#define CRYP_FLAG_RDERR AES_SR_RDERR

Read error

Definition at line 338 of file stm32g0xx_hal_cryp.h.

#define CRYP_FLAG_WRERR AES_SR_WRERR

Write Error

Definition at line 337 of file stm32g0xx_hal_cryp.h.

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STM32G0C1xx HAL User Manual: CRYP Key and IV Configuration Skip Mode

Defines
CRYP Key and IV Configuration Skip Mode
CRYP Exported Constants

Defines

#define | CRYP_KEYIVCONFIG_ALWAYS 0x00000000U
#define | CRYP_KEYIVCONFIG_ONCE 0x00000001U

Define Documentation

#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U

Peripheral Key and IV configuration to do systematically

Definition at line 352 of file stm32g0xx_hal_cryp.h.

#define CRYP_KEYIVCONFIG_ONCE 0x00000001U

Peripheral Key and IV configuration to do only once

Definition at line 353 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), and HAL_CRYP_Encrypt_DMA().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Exported Macros

Defines
CRYP Exported Macros
CRYP

Defines

#define | __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__)
Reset CRYP handle state.
#define | __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
Enable/Disable the CRYP peripheral.
#define | __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
#define | CRYP_FLAG_MASK 0x0000001FU
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#define | __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
Clear the CRYP pending status flag.
#define | __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt source is enabled or not.
#define | __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.

Define Documentation

#define __HAL_CRYP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))

Clear the CRYP pending status flag.

Parameters:
__HANDLE__ specifies the CRYP handle.
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
  • CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
Return values:
None

Definition at line 425 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_ClearCCFlagWhenHigh(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define __HAL_CRYP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)

Definition at line 390 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_ClearCCFlagWhenHigh(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_DMA(), HAL_CRYP_DeInit(), HAL_CRYP_Resume(), HAL_CRYP_Suspend(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define __HAL_CRYP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the CRYP interrupt.

Parameters:
__HANDLE__ specifies the CRYP handle.
__INTERRUPT__ CRYP Interrupt. This parameter can be one of the following values for TinyAES:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt This parameter can be one of the following values for CRYP: @ CRYP_IT_INI : Input FIFO service interrupt mask. @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
Return values:
None

Definition at line 482 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), and HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define __HAL_CRYP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= AES_CR_EN)

Enable/Disable the CRYP peripheral.

Parameters:
__HANDLE__ specifies the CRYP handle.
Return values:
None

Definition at line 389 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_PhaseProcessingResume(), and CRYP_SetDMAConfig().

#define __HAL_CRYP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the CRYP interrupt.

Parameters:
__HANDLE__ specifies the CRYP handle.
__INTERRUPT__ CRYP Interrupt. This parameter can be one of the following values for TinyAES:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt This parameter can be one of the following values for CRYP: @ CRYP_IT_INI : Input FIFO service interrupt mask. @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
Return values:
None

Definition at line 467 of file stm32g0xx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), and CRYP_PhaseProcessingResume().

#define __HAL_CRYP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Definition at line 414 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define __HAL_CRYP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified CRYP interrupt is set or not.

Parameters:
__HANDLE__ specifies the CRYP handle.
__INTERRUPT__ specifies the interrupt to check. This parameter can be one of the following values for TinyAES:
  • CRYP_IT_WRERR Write Error
  • CRYP_IT_RDERR Read Error
  • CRYP_IT_CCF Computation Complete This parameter can be one of the following values for CRYP:
  • CRYP_IT_INI: Input FIFO service masked interrupt status
  • CRYP_IT_OUTI: Output FIFO service masked interrupt status
Return values:
The state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 452 of file stm32g0xx_hal_cryp.h.

#define __HAL_CRYP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified CRYP interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the CRYP handle.
__INTERRUPT__ CRYP interrupt source to check This parameter can be one of the following values for TinyAES:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt
Return values:
State of interruption (TRUE or FALSE).

Definition at line 437 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define __HAL_CRYP_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;\
                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
                                                     }while(0U)

Reset CRYP handle state.

Parameters:
__HANDLE__ specifies the CRYP handle.
Return values:
None

Definition at line 374 of file stm32g0xx_hal_cryp.h.

#define CRYP_FLAG_MASK 0x0000001FU

Check whether the specified CRYP status flag is set or not.

Parameters:
__HANDLE__ specifies the CRYP handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values for TinyAES:
  • CRYP_FLAG_BUSY GCM process suspension forbidden
  • CRYP_IT_WRERR Write Error
  • CRYP_IT_RDERR Read Error
  • CRYP_IT_CCF Computation Complete This parameter can be one of the following values for CRYP:
  • CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data or a key preparation (for AES decryption).
  • CRYP_FLAG_IFEM: Input FIFO is empty
  • CRYP_FLAG_IFNF: Input FIFO is not full
  • CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
  • CRYP_FLAG_OFNE: Output FIFO is not empty
  • CRYP_FLAG_OFFU: Output FIFO is full
  • CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
Return values:
The state of __FLAG__ (TRUE or FALSE).

Definition at line 413 of file stm32g0xx_hal_cryp.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRYP Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callback is redirected to the weak predefined callback.
void | HAL_CRYP_ProcessSuspend (CRYP_HandleTypeDef *hcryp)
Request CRYP processing suspension when in interruption mode.
HAL_StatusTypeDef | HAL_CRYP_Suspend (CRYP_HandleTypeDef *hcryp)
CRYP processing suspension and peripheral internal parameters storage.
HAL_StatusTypeDef | HAL_CRYP_Resume (CRYP_HandleTypeDef *hcryp)
CRYP processing resumption.

Detailed Description

Initialization and Configuration functions.

  ========================================================================================
     ##### Initialization, de-initialization and Set and Get configuration functions #####
  ========================================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRYP
      (+) DeInitialize the CRYP
      (+) Initialize the CRYP MSP
      (+) DeInitialize the CRYP MSP
      (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
          Parameters which are configured in This section are :
          (++) Key size
          (++) Data Type : 32,16, 8 or 1bit
          (++) AlgoMode :
              (+++) for CRYP1 peripheral :
                 ECB and CBC in DES/TDES Standard
                 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
              (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
      (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef

Function Documentation

HAL_StatusTypeDef HAL_CRYP_DeInit ( CRYP_HandleTypeDef * hcryp )

De-Initializes the CRYP peripheral.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 515 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_PHASE_READY, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_MspDeInit(), HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_GetConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | CRYP_ConfigTypeDef * | pConf
 | ) |  |

Get CRYP Configuration parameters in associated handle.

Parameters:
pConf | pointer to a CRYP_ConfigTypeDef structure
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 641 of file stm32g0xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_ConfigTypeDef::B0, CRYP_ConfigTypeDef::DataType, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::Init, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Init ( CRYP_HandleTypeDef * hcryp )

Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 447 of file stm32g0xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_PHASE_READY, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_NONE, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_MspInit(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_ALGORITHM, IS_CRYP_DATATYPE, IS_CRYP_INIT, IS_CRYP_KEYSIZE, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Lock, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Resume().

void HAL_CRYP_MspDeInit ( CRYP_HandleTypeDef * hcryp )

DeInitializes CRYP MSP.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 711 of file stm32g0xx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit(), and HAL_CRYP_UnRegisterCallback().

void HAL_CRYP_MspInit ( CRYP_HandleTypeDef * hcryp )

Initializes the CRYP MSP.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 695 of file stm32g0xx_hal_cryp.c.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

void HAL_CRYP_ProcessSuspend ( CRYP_HandleTypeDef * hcryp )

Request CRYP processing suspension when in interruption mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Note:
Set the handle field SuspendRequest to the appropriate value so that the on-going CRYP processing is suspended as soon as the required conditions are met.
HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done in non-blocking interrupt mode.
It is advised not to suspend the CRYP processing when the DMA controller is managing the data transfer.
Return values:
None

Definition at line 917 of file stm32g0xx_hal_cryp.c.

References HAL_CRYP_SUSPEND, and __CRYP_HandleTypeDef::SuspendRequest.

Referenced by HAL_CRYP_Suspend().

HAL_StatusTypeDef HAL_CRYP_RegisterCallback | ( | CRYP_HandleTypeDef * | hcryp,
 |  | HAL_CRYP_CallbackIDTypeDef | CallbackID,
 |  | pCRYP_CallbackTypeDef | pCallback
 | ) |  |

Register a User CRYP Callback To be used instead of the weak predefined callback.

Parameters:
hcryp | cryp handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
  • HAL_CRYP_ERROR_CB_ID Error callback ID
  • HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
  • HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 736 of file stm32g0xx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_CB_ID, HAL_CRYP_ERROR_INVALID_CALLBACK, HAL_CRYP_INPUT_COMPLETE_CB_ID, HAL_CRYP_MSPDEINIT_CB_ID, HAL_CRYP_MSPINIT_CB_ID, HAL_CRYP_OUTPUT_COMPLETE_CB_ID, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Resume ( CRYP_HandleTypeDef * hcryp )

CRYP processing resumption.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Note:
Processing restarts at the exact point where it was suspended, based on the parameters saved at suspension time.
Return values:
HAL status

Definition at line 1006 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_ConfigTypeDef::Algorithm, __CRYP_HandleTypeDef::AutoKeyDerivation, __CRYP_HandleTypeDef::AutoKeyDerivation_saved, __CRYP_HandleTypeDef::CR_saved, CRYP_AES_CBC, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_OPERATINGMODE_ENCRYPT, CRYP_Write_IVRegisters(), CRYP_Write_KeyRegisters(), CRYP_Write_SuspendRegisters(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypHeaderCount_saved, HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Init_saved, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::IV_saved, __CRYP_HandleTypeDef::Key_saved, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr_saved, __CRYP_HandleTypeDef::pCrypOutBuffPtr_saved, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Phase_saved, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::ResumingFlag, __CRYP_HandleTypeDef::Size_saved, __CRYP_HandleTypeDef::SizesSum, __CRYP_HandleTypeDef::SizesSum_saved, __CRYP_HandleTypeDef::State, __CRYP_HandleTypeDef::State_saved, and __CRYP_HandleTypeDef::SUSPxR_saved.

HAL_StatusTypeDef HAL_CRYP_SetConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | CRYP_ConfigTypeDef * | pConf
 | ) |  |

Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure
pConf | pointer to a CRYP_ConfigTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 568 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_ConfigTypeDef::B0, CRYP_ERR_CLEAR, CRYP_PHASE_READY, CRYP_ConfigTypeDef::DataType, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NONE, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_ALGORITHM, IS_CRYP_DATATYPE, IS_CRYP_KEYSIZE, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Suspend ( CRYP_HandleTypeDef * hcryp )

CRYP processing suspension and peripheral internal parameters storage.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Note:
peripheral internal parameters are stored to be readily available when suspended processing is resumed later on.
Return values:
HAL status

Definition at line 933 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_ConfigTypeDef::Algorithm, __CRYP_HandleTypeDef::AutoKeyDerivation, __CRYP_HandleTypeDef::AutoKeyDerivation_saved, __CRYP_HandleTypeDef::CR_saved, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_GCM_GMAC, CRYP_DATAWIDTHUNIT_WORD, CRYP_Read_IVRegisters(), CRYP_Read_KeyRegisters(), CRYP_Read_SuspendRegisters(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypHeaderCount_saved, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypInCount_saved, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::CrypOutCount_saved, CRYP_ConfigTypeDef::DataWidthUnit, HAL_CRYP_GetState(), HAL_CRYP_ProcessSuspend(), HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, HAL_CRYP_SUSPEND_NONE, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Init_saved, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::IV_saved, __CRYP_HandleTypeDef::Key_saved, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypInBuffPtr_saved, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr_saved, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Phase_saved, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::Size_saved, __CRYP_HandleTypeDef::SizesSum, __CRYP_HandleTypeDef::SizesSum_saved, __CRYP_HandleTypeDef::State, __CRYP_HandleTypeDef::State_saved, __CRYP_HandleTypeDef::SuspendRequest, and __CRYP_HandleTypeDef::SUSPxR_saved.

HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback | ( | CRYP_HandleTypeDef * | hcryp,
 |  | HAL_CRYP_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an CRYP Callback CRYP callback is redirected to the weak predefined callback.

Parameters:
hcryp cryp handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
  • HAL_CRYP_ERROR_CB_ID Error callback ID
  • HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
  • HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
status

Definition at line 829 of file stm32g0xx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_CB_ID, HAL_CRYP_ERROR_INVALID_CALLBACK, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_INPUT_COMPLETE_CB_ID, HAL_CRYP_MspDeInit(), HAL_CRYP_MSPDEINIT_CB_ID, HAL_CRYP_MspInit(), HAL_CRYP_MSPINIT_CB_ID, HAL_CRYP_OutCpltCallback(), HAL_CRYP_OUTPUT_COMPLETE_CB_ID, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, and __CRYP_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Encryption Decryption functions

Functions
Encryption Decryption functions
CRYP Exported Functions

Encryption Decryption functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.

Detailed Description

Encryption Decryption functions.

  ==============================================================================
                      ##### Encrypt Decrypt  functions #####
  ==============================================================================
    [..]  This section provides API allowing to Encrypt/Decrypt Data following
          Standard DES/TDES or AES, and Algorithm configured by the user:
      (+) Standard DES/TDES only supported by CRYP1 peripheral, below list of Algorithm supported :
           - Electronic Code Book(ECB)
           - Cipher Block Chaining (CBC)
      (+) Standard AES  supported by CRYP1 peripheral & TinyAES, list of Algorithm supported:
           - Electronic Code Book(ECB)
           - Cipher Block Chaining (CBC)
           - Counter mode (CTR)
           - Cipher Block Chaining (CBC)
           - Counter mode (CTR)
           - Galois/counter mode (GCM)
           - Counter with Cipher Block Chaining-Message(CCM)
    [..]  Three processing functions are available:
      (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
      (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
      (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

Function Documentation

HAL_StatusTypeDef HAL_CRYP_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output,
 |  | uint32_t | Timeout
 | ) |  |

Decryption mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (ciphertext )
Size | Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
Output | Pointer to the output buffer(plaintext)
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 1303 of file stm32g0xx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt(), CRYP_AES_ECB, CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_DECRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Decryption in DMA mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (ciphertext )
Size | Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
Output | Pointer to the output buffer(plaintext)
Return values:
HAL status

Definition at line 1748 of file stm32g0xx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt_DMA(), CRYP_AES_ECB, CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_DECRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Decrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Decryption in interrupt mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (ciphertext )
Size | Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
Output | Pointer to the output buffer(plaintext)
Return values:
HAL status

Definition at line 1512 of file stm32g0xx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt_IT(), CRYP_AES_ECB, CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_HEADER_SUSPENDED, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypInCount_saved, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::CrypOutCount_saved, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::ResumingFlag, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Resume().

HAL_StatusTypeDef HAL_CRYP_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output,
 |  | uint32_t | Timeout
 | ) |  |

Encryption mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (plaintext)
Size | Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
Output | Pointer to the output buffer(ciphertext)
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 1203 of file stm32g0xx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_Encrypt(), CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_ENCRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Encryption in DMA mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (plaintext)
Size | Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
Output | Pointer to the output buffer(ciphertext)
Return values:
HAL status

Definition at line 1621 of file stm32g0xx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DATAWIDTHUNIT_WORD, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_SetKey(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Encryption in interrupt mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (plaintext)
Size | Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
Output | Pointer to the output buffer(ciphertext)
Return values:
HAL status

Definition at line 1402 of file stm32g0xx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_Encrypt_IT(), CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_HEADER_SUSPENDED, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypInCount_saved, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::CrypOutCount_saved, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::ResumingFlag, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Resume().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP IRQ handler management

Functions
CRYP IRQ handler management
CRYP Exported Functions

CRYP IRQ handler. More...

Functions

void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.

Detailed Description

CRYP IRQ handler.

  ==============================================================================
                ##### CRYP IRQ handler management #####
  ==============================================================================
[..]  This section provides CRYP IRQ handler and callback functions.
      (+) HAL_CRYP_IRQHandler CRYP interrupt request
      (+) HAL_CRYP_InCpltCallback input data transfer complete callback
      (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
      (+) HAL_CRYP_ErrorCallback  CRYP error callback
      (+) HAL_CRYP_GetState return the CRYP state
      (+) HAL_CRYP_GetError return the CRYP error code

Function Documentation

void HAL_CRYP_ErrorCallback ( CRYP_HandleTypeDef * hcryp )

CRYP error callback.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1963 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESGCM_Process(), CRYP_ClearCCFlagWhenHigh(), CRYP_DMAError(), CRYP_Read_SuspendRegisters(), CRYP_SetDMAConfig(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

uint32_t HAL_CRYP_GetError ( CRYP_HandleTypeDef * hcryp )

Return the CRYP error code.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for the CRYP peripheral
Return values:
CRYP error code

Definition at line 1909 of file stm32g0xx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCode.

HAL_CRYP_STATETypeDef HAL_CRYP_GetState ( CRYP_HandleTypeDef * hcryp )

Returns the CRYP state.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL state

Definition at line 1920 of file stm32g0xx_hal_cryp.c.

References __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Suspend().

void HAL_CRYP_InCpltCallback ( CRYP_HandleTypeDef * hcryp )

Input FIFO transfer completed callback.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1931 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

void HAL_CRYP_IRQHandler ( CRYP_HandleTypeDef * hcryp )

This function handles cryptographic interrupt request.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1857 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_GET_FLAG, __HAL_CRYP_GET_IT_SOURCE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_AES_IT(), CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_IT_CCF, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_IT_RDERR, CRYP_IT_WRERR, CRYP_PHASE_HEADER, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_READ, HAL_CRYP_ERROR_WRITE, __CRYP_HandleTypeDef::Init, and __CRYP_HandleTypeDef::Instance.

void HAL_CRYP_OutCpltCallback ( CRYP_HandleTypeDef * hcryp )

Output FIFO transfer completed callback.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1947 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Private macros to check input parameters

Defines
CRYP Private macros to check input parameters
CRYP Private Macros

Defines

#define | IS_CRYP_ALGORITHM(ALGORITHM)
#define | IS_CRYP_KEYSIZE(KEYSIZE)
#define | IS_CRYP_DATATYPE(DATATYPE)
#define | IS_CRYP_INIT(CONFIG)
#define | IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)

Define Documentation

#define IS_CRYP_ALGORITHM ( ALGORITHM )
Value:
(((ALGORITHM) == CRYP_AES_ECB)      || \
                                      ((ALGORITHM)  == CRYP_AES_CBC)     || \
                                      ((ALGORITHM)  == CRYP_AES_CTR)     || \
                                      ((ALGORITHM)  == CRYP_AES_GCM_GMAC)|| \
                                      ((ALGORITHM)  == CRYP_AES_CCM))

Definition at line 563 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define IS_CRYP_BUFFERSIZE | ( | ALGO,
 |  | DATAWIDTH,
 |  | SIZE
 | ) |
Value:
(((((ALGO) == CRYP_AES_CTR)) &&                                             \
            ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U))           || \
             (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U))))        || \
         (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC)                  || \
          ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))

Definition at line 581 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define IS_CRYP_DATATYPE ( DATATYPE )
Value:
(((DATATYPE) == CRYP_DATATYPE_32B) || \
                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
                                   ((DATATYPE) == CRYP_DATATYPE_8B)  || \
                                   ((DATATYPE) == CRYP_DATATYPE_1B))

Definition at line 573 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define IS_CRYP_INIT ( CONFIG )
Value:
(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
                             ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))

Definition at line 578 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

#define IS_CRYP_KEYSIZE ( KEYSIZE )
Value:
(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))

Definition at line 570 of file stm32g0xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Private Macros

Modules | Defines
CRYP Private Macros
CRYP

Modules

CRYP Private macros to check input parameters

Defines

#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))

Define Documentation

#define CRYP_SET_PHASE | ( | __HANDLE__,
 |  | __PHASE__
 | ) | MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))

Definition at line 353 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_PhaseProcessingResume().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Private Constants

CRYP Private Constants
CRYP
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Private Defines

Defines
CRYP Private Defines
CRYP

Defines

#define | CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define | CRYP_PHASE_READY 0x00000001U
#define | CRYP_PHASE_PROCESS 0x00000002U
#define | CRYP_PHASE_HEADER_SUSPENDED 0x00000004U
#define | CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U
#define | CRYP_PHASE_HEADER_DMA_FEED 0x00000006U
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER AES_CR_GCMPH_0
#define | CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
#define | CRYP_PHASE_FINAL AES_CR_GCMPH
#define | CRYP_CCM_CTR1_0 0x07FFFFFFU
#define | CRYP_CCM_CTR1_1 0xFFFFFF00U
#define | CRYP_CCM_CTR1_2 0x00000001U

Define Documentation

#define CRYP_CCM_CTR1_0 0x07FFFFFFU

Definition at line 340 of file stm32g0xx_hal_cryp.c.

#define CRYP_CCM_CTR1_1 0xFFFFFF00U

Definition at line 341 of file stm32g0xx_hal_cryp.c.

#define CRYP_CCM_CTR1_2 0x00000001U

Definition at line 342 of file stm32g0xx_hal_cryp.c.

#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1

Decryption (Mode 3)

Definition at line 332 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Decrypt_IT().

#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U

Encryption mode(Mode 1)

Definition at line 330 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_Resume().

#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0

Key derivation mode only used when performing ECB and CBC decryptions (Mode 2)

Definition at line 331 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), and CRYP_AES_Decrypt_IT().

#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE

Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4)

Definition at line 333 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), and CRYP_AES_Decrypt_IT().

#define CRYP_PHASE_FINAL AES_CR_GCMPH

GCM/GMAC or CCM final phase

Definition at line 337 of file stm32g0xx_hal_cryp.c.

#define CRYP_PHASE_HEADER AES_CR_GCMPH_0

GCM/GMAC or CCM header phase

Definition at line 335 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_PhaseProcessingResume(), and HAL_CRYP_IRQHandler().

#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U

GCM/GMAC/CCM header is fed to the peripheral in DMA mode

Definition at line 328 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_DMAInCplt(), and CRYP_SetHeaderDMAConfig().

#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U

GCM/GMAC/CCM header phase is suspended

Definition at line 325 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_PhaseProcessingResume(), HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

#define CRYP_PHASE_INIT 0x00000000U

GCM/GMAC (or CCM) init phase

Definition at line 334 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), and CRYP_AESGCM_Process_IT().

#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1

GCM(/CCM) payload phase

Definition at line 336 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), and CRYP_PhaseProcessingResume().

#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U

GCM/CCM payload phase is suspended

Definition at line 326 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), and CRYP_PhaseProcessingResume().

#define CRYP_PHASE_PROCESS 0x00000002U

CRYP peripheral is in processing phase

Definition at line 323 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_PhaseProcessingResume(), and HAL_CRYP_Encrypt_DMA().

#define CRYP_PHASE_READY 0x00000001U

CRYP peripheral is ready for initialization.

Definition at line 322 of file stm32g0xx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/

Definition at line 320 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_GCMCCM_SetPayloadPhase_DMA().

#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/

Definition at line 319 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_DMA(), and CRYP_AESGCM_Process_IT().

#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/

Definition at line 318 of file stm32g0xx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt_DMA(), and CRYP_AES_Decrypt_IT().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Private Variables

CRYP Private Variables
CRYP
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Private Functions

Functions
CRYP Private Functions
CRYP

Functions

static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static HAL_StatusTypeDef | CRYP_SetHeaderDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
Set the DMA configuration and start the header DMA transfer.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_SetKey (CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
Writes Key in Key registers.
static void | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
static void | CRYP_GCMCCM_SetPayloadPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in interrupt mode.
static void | CRYP_GCMCCM_SetHeaderPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetPayloadPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in DMA mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
static HAL_StatusTypeDef | CRYP_AESCCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_IT (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static void | CRYP_AES_ProcessData (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
static HAL_StatusTypeDef | CRYP_AES_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_IT (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Encrypt_IT (CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_DMA (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
static HAL_StatusTypeDef | CRYP_WaitOnCCFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
static void | CRYP_ClearCCFlagWhenHigh (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Wait for Computation Complete Flag (CCF) to raise then clear it.
static void | CRYP_Read_IVRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Output)
In case of message processing suspension, read the Initialization Vector.
static void | CRYP_Write_IVRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Input)
In case of message processing resumption, rewrite the Initialization Vector in the AES_IVRx registers.
static void | CRYP_Read_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Output)
In case of message GCM/GMAC/CCM processing suspension, read the Suspend Registers.
static void | CRYP_Write_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Input)
In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend Registers in the AES_SUSPxR registers.
static void | CRYP_Read_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize)
In case of message GCM/GMAC/CCM processing suspension, read the Key Registers.
static void | CRYP_Write_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize)
In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key Registers in the AES_KEYRx registers.
static void | CRYP_PhaseProcessingResume (CRYP_HandleTypeDef *hcryp)
Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode.

Function Documentation

static HAL_StatusTypeDef CRYP_AES_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Decryption in ECB/CBC & CTR mode with AES Standard.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 2138 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, __CRYP_HandleTypeDef::AutoKeyDerivation, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_ProcessData(), CRYP_CCF_CLEAR, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_KEYDERIVATION, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT, CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt().

static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2383 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, __CRYP_HandleTypeDef::AutoKeyDerivation, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_CCF_CLEAR, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_KEYDERIVATION, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_KEYPREPARATION, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA().

static HAL_StatusTypeDef CRYP_AES_Decrypt_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2254 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, __CRYP_HandleTypeDef::AutoKeyDerivation, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_KEYDERIVATION, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT, CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_TIMEOUT_KEYPREPARATION, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT().

static HAL_StatusTypeDef CRYP_AES_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption in ECB/CBC & CTR Algorithm with AES Standard.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure
Timeout | specify Timeout value
Return values:
HAL status

Definition at line 1991 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_ECB, CRYP_AES_ProcessData(), CRYP_KEYIVCONFIG_ONCE, CRYP_PHASE_PROCESS, CRYP_SetKey(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AES_Encrypt_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2061 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_ECB, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYIVCONFIG_ONCE, CRYP_PHASE_PROCESS, CRYP_SetKey(), __CRYP_HandleTypeDef::CrypInCount, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Encrypt_IT().

static void CRYP_AES_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Handle CRYP block input/output data handling under interruption.

Note:
The function is called under interruption only, once interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL status

Definition at line 2912 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_PHASE_PAYLOAD_SUSPENDED, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, HAL_CRYP_SUSPEND, HAL_CRYP_SUSPEND_NONE, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::SuspendRequest.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_AES_ProcessData | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Process Data: Write Input data in polling mode and used in AES functions.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout | Specify Timeout value
Return values:
None

Definition at line 2850 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_CCF_CLEAR, CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

static HAL_StatusTypeDef CRYP_AESCCM_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

AES CCM encryption/decryption processing in polling mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3735 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_AES_ProcessData(), CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase(), CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

AES CCM encryption/decryption process in DMA mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 4292 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_KEYIVCONFIG_ONCE, CRYP_PHASE_INIT, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_AESCCM_Process_IT ( CRYP_HandleTypeDef * hcryp ) [static]

AES CCM encryption/decryption process in interrupt mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3934 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_ConfigTypeDef::B0, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_HEADERWIDTHUNIT_WORD, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_HEADER, CRYP_PHASE_HEADER_SUSPENDED, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PAYLOAD_SUSPENDED, CRYP_PHASE_PROCESS, CRYP_PhaseProcessingResume(), CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_InCpltCallback(), HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

static HAL_StatusTypeDef CRYP_AESGCM_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3062 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_AES_ProcessData(), CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase(), CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3631 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_KEYIVCONFIG_ONCE, CRYP_PHASE_INIT, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_AESGCM_Process_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3265 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_CCF_CLEAR, CRYP_HEADERWIDTHUNIT_WORD, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_HEADER, CRYP_PHASE_HEADER_SUSPENDED, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PAYLOAD_SUSPENDED, CRYP_PHASE_PROCESS, CRYP_PhaseProcessingResume(), CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_InCpltCallback(), HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

static void CRYP_ClearCCFlagWhenHigh | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Wait for Computation Complete Flag (CCF) to raise then clear it.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout | Timeout duration.
Note:
This function can be used in thread or handler mode.
Return values:
HAL status

Definition at line 5190 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_CCF_CLEAR, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Instance, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_DMAInCplt(), and CRYP_DMAOutCplt().

static void CRYP_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 2720 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_CCF_CLEAR, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_DMA, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig(), and CRYP_SetHeaderDMAConfig().

static void CRYP_DMAInCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP input data process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 2500 of file stm32g0xx_hal_cryp.c.

References CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_ClearCCFlagWhenHigh(), CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_HEADERWIDTHUNIT_WORD, CRYP_PHASE_HEADER_DMA_FEED, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_TIMEOUT_GCMCCMHEADERPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::DataType, HAL_CRYP_InCpltCallback(), CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::Size.

Referenced by CRYP_SetDMAConfig(), and CRYP_SetHeaderDMAConfig().

static void CRYP_DMAOutCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP output data process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 2609 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_ClearCCFlagWhenHigh(), CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_TIMEOUT_GCMCCMHEADERPHASE, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Sets the header phase in polling mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Timeout | Timeout value
Return values:
state

Definition at line 4683 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_CCF_CLEAR, CRYP_HEADERWIDTHUNIT_WORD, CRYP_PHASE_HEADER, CRYP_SET_PHASE, CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the header phase when using DMA in process.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 4843 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_CCF_CLEAR, CRYP_GCMCCM_SetPayloadPhase_DMA(), CRYP_HEADERWIDTHUNIT_WORD, CRYP_PHASE_HEADER, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetHeaderDMAConfig(), CRYP_TIMEOUT_GCMCCMHEADERPHASE, CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process_DMA(), and CRYP_AESGCM_Process_DMA().

static void CRYP_GCMCCM_SetHeaderPhase_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the header phase in interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 4961 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_HEADERWIDTHUNIT_WORD, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_HEADER_SUSPENDED, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, CRYP_ConfigTypeDef::DataType, HAL_CRYP_InCpltCallback(), HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, HAL_CRYP_SUSPEND, HAL_CRYP_SUSPEND_NONE, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::SuspendRequest.

Referenced by HAL_CRYP_IRQHandler().

static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the payload phase in DMA mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
state

Definition at line 4549 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_SetDMAConfig(), CRYP_TIMEOUT_GCMCCMHEADERPHASE, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DMAInCplt(), and CRYP_GCMCCM_SetHeaderPhase_DMA().

static void CRYP_GCMCCM_SetPayloadPhase_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the payload phase in interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
state

Definition at line 4395 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PAYLOAD_SUSPENDED, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, HAL_CRYP_SUSPEND, HAL_CRYP_SUSPEND_NONE, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::State, and __CRYP_HandleTypeDef::SuspendRequest.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_PhaseProcessingResume ( CRYP_HandleTypeDef * hcryp ) [static]

Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 5448 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_ERR_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_HEADER, CRYP_PHASE_HEADER_SUSPENDED, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PAYLOAD_SUSPENDED, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, HAL_CRYP_InCpltCallback(), CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::Size.

Referenced by CRYP_AESCCM_Process_IT(), and CRYP_AESGCM_Process_IT().

static void CRYP_Read_IVRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Output
 | ) |  | [static]

In case of message processing suspension, read the Initialization Vector.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Output | Pointer to the buffer containing the saved Initialization Vector.
Note:
This value has to be stored for reuse by writing the AES_IVRx registers as soon as the suspended processing has to be resumed.
Return values:
None

Definition at line 5234 of file stm32g0xx_hal_cryp.c.

References __CRYP_HandleTypeDef::Instance.

Referenced by HAL_CRYP_Suspend().

static void CRYP_Read_KeyRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Output,
 |  | uint32_t | KeySize
 | ) |  | [static]

In case of message GCM/GMAC/CCM processing suspension, read the Key Registers.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Output | Pointer to the buffer containing the saved Key Registers.
KeySize | Indicates the key size (128 or 256 bits).
Note:
These values have to be stored for reuse by writing back the AES_KEYRx registers as soon as the suspended processing has to be resumed.
Return values:
None

Definition at line 5369 of file stm32g0xx_hal_cryp.c.

References CRYP_KEYSIZE_128B, CRYP_KEYSIZE_256B, __CRYP_HandleTypeDef::Init, and CRYP_ConfigTypeDef::pKey.

Referenced by HAL_CRYP_Suspend().

static void CRYP_Read_SuspendRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Output
 | ) |  | [static]

In case of message GCM/GMAC/CCM processing suspension, read the Suspend Registers.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Output | Pointer to the buffer containing the saved Suspend Registers.
Note:
These values have to be stored for reuse by writing back the AES_SUSPxR registers as soon as the suspended processing has to be resumed.
Return values:
None

Definition at line 5280 of file stm32g0xx_hal_cryp.c.

References CRYP_AES_GCM_GMAC, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Instance, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Suspend().

static void CRYP_SetDMAConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | inputaddr,
 |  | uint16_t | Size,
 |  | uint32_t | outputaddr
 | ) |  | [static]

Set the DMA configuration and start the DMA transfer.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
inputaddr | address of the input buffer
Size | size of the input and output buffers in words, must be a multiple of 4
outputaddr | address of the output buffer
Return values:
None

Definition at line 2752 of file stm32g0xx_hal_cryp.c.

References __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_GCM_GMAC, CRYP_DMAError(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_DMA, HAL_CRYP_ErrorCallback(), HAL_DMA_Start_IT(), __CRYP_HandleTypeDef::hdmain, __CRYP_HandleTypeDef::hdmaout, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_GCMCCM_SetPayloadPhase_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | inputaddr,
 |  | uint16_t | Size
 | ) |  | [static]

Set the DMA configuration and start the header DMA transfer.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
inputaddr | address of the input buffer
Size | size of the input buffer in words, must be a multiple of 4
Return values:
None

Definition at line 2814 of file stm32g0xx_hal_cryp.c.

References CRYP_DMAError(), CRYP_DMAInCplt(), CRYP_PHASE_HEADER_DMA_FEED, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_DMA, HAL_CRYP_STATE_READY, HAL_DMA_Start_IT(), __CRYP_HandleTypeDef::hdmain, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by CRYP_GCMCCM_SetHeaderPhase_DMA().

static void CRYP_SetKey | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | KeySize
 | ) |  | [static]

Writes Key in Key registers.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
KeySize | Size of Key
Note:
If pKey is NULL, the Key registers are not written. This configuration occurs when the key is written out of HAL scope.
Return values:
None

Definition at line 3026 of file stm32g0xx_hal_cryp.c.

References CRYP_KEYSIZE_128B, CRYP_KEYSIZE_256B, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, and CRYP_ConfigTypeDef::pKey.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_WaitOnCCFlag | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout | Timeout duration.
Note:
This function can only be used in thread mode.
Return values:
HAL status

Definition at line 5161 of file stm32g0xx_hal_cryp.c.

References HAL_GetTick(), and __CRYP_HandleTypeDef::Instance.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_GCMCCM_SetHeaderPhase(), and CRYP_GCMCCM_SetHeaderPhase_DMA().

static void CRYP_Write_IVRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input
 | ) |  | [static]

In case of message processing resumption, rewrite the Initialization Vector in the AES_IVRx registers.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Input | Pointer to the buffer containing the saved Initialization Vector to write back in the CRYP hardware block.
Note:
AES must be disabled when reconfiguring the IV values.
Return values:
None

Definition at line 5257 of file stm32g0xx_hal_cryp.c.

References __CRYP_HandleTypeDef::Instance.

Referenced by HAL_CRYP_Resume().

static void CRYP_Write_KeyRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint32_t | KeySize
 | ) |  | [static]

In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key Registers in the AES_KEYRx registers.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Input | Pointer to the buffer containing the saved key registers to write back in the CRYP hardware block.
KeySize | Indicates the key size (128 or 256 bits)
Note:
AES must be disabled when reconfiguring the Key registers.
Return values:
None

Definition at line 5417 of file stm32g0xx_hal_cryp.c.

References CRYP_KEYSIZE_256B, and __CRYP_HandleTypeDef::Instance.

Referenced by HAL_CRYP_Resume().

static void CRYP_Write_SuspendRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input
 | ) |  | [static]

In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend Registers in the AES_SUSPxR registers.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Input | Pointer to the buffer containing the saved suspend registers to write back in the CRYP hardware block.
Note:
AES must be disabled when reconfiguring the suspend registers.
Return values:
None

Definition at line 5338 of file stm32g0xx_hal_cryp.c.

References __CRYP_HandleTypeDef::Instance.

Referenced by HAL_CRYP_Resume().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYPEx Private Types

CRYPEx Private Types
CRYPEx
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYPEx Private Variables

CRYPEx Private Variables
CRYPEx
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYPEx Private Constants

CRYPEx Private Constants
CRYPEx
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYPEx Private Macros

CRYPEx Private Macros
CRYPEx
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYPEx Private Functions

CRYPEx Private Functions
CRYPEx
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended AES processing functions

Functions
Extended AES processing functions
CRYPEx Exported Functions

Extended processing functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.

Detailed Description

Extended processing functions.

  ==============================================================================
              ##### Extended AES processing functions #####
  ==============================================================================
    [..]  This section provides functions allowing to generate the authentication
          TAG in Polling mode
      (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
      (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
         they should be used after Encrypt/Decrypt operation.

Function Documentation

HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | AuthTag,
 |  | uint32_t | Timeout
 | ) |  |

AES CCM Authentication TAG generation.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
AuthTag | Pointer to the authentication buffer
Timeout | Timeout duration
Return values:
HAL status

Definition at line 219 of file stm32g0xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_FINAL, CRYPEx_PHASE_FINAL, CRYPEx_PHASE_PROCESS, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | AuthTag,
 |  | uint32_t | Timeout
 | ) |  |

generate the GCM authentication TAG.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
AuthTag | Pointer to the authentication buffer
Timeout | Timeout duration
Return values:
HAL status

Definition at line 98 of file stm32g0xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_CCF_CLEAR, CRYP_HEADERWIDTHUNIT_BYTE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_FINAL, CRYPEx_PHASE_FINAL, CRYPEx_PHASE_PROCESS, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_GetTick(), CRYP_ConfigTypeDef::HeaderSize, CRYP_ConfigTypeDef::HeaderWidthUnit, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended AES Key Derivations functions

Functions
Extended AES Key Derivations functions
CRYPEx Exported Functions

Extended Key Derivations functions. More...

Functions

void | HAL_CRYPEx_EnableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES enable key derivation functions.
void | HAL_CRYPEx_DisableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES disable key derivation functions.

Detailed Description

Extended Key Derivations functions.

  ==============================================================================
              ##### Key Derivation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to Enable or Disable the
          the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
          These function are allowed only in TinyAES peripheral.

Function Documentation

void HAL_CRYPEx_DisableAutoKeyDerivation ( CRYP_HandleTypeDef * hcryp )

AES disable key derivation functions.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure.

Definition at line 356 of file stm32g0xx_hal_cryp_ex.c.

References __CRYP_HandleTypeDef::AutoKeyDerivation, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_STATE_READY, and __CRYP_HandleTypeDef::State.

void HAL_CRYPEx_EnableAutoKeyDerivation ( CRYP_HandleTypeDef * hcryp )

AES enable key derivation functions.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure.

Definition at line 340 of file stm32g0xx_hal_cryp_ex.c.

References __CRYP_HandleTypeDef::AutoKeyDerivation, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_STATE_READY, and __CRYP_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYPEx_Private_Defines

Defines
CRYPEx_Private_Defines
CRYPEx

Defines

#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER AES_CR_GCMPH_0
#define | CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
#define | CRYP_PHASE_FINAL AES_CR_GCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYPEx_PHASE_PROCESS 0x02U
#define | CRYPEx_PHASE_FINAL 0x03U
#define | CRYP_CCM_CTR0_0 0x07FFFFFFU
#define | CRYP_CCM_CTR0_3 0xFFFFFF00U

Define Documentation

#define CRYP_CCM_CTR0_0 0x07FFFFFFU

Definition at line 57 of file stm32g0xx_hal_cryp_ex.c.

#define CRYP_CCM_CTR0_3 0xFFFFFF00U

Definition at line 58 of file stm32g0xx_hal_cryp_ex.c.

#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1

Decryption

Definition at line 50 of file stm32g0xx_hal_cryp_ex.c.

#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U

Encryption mode

Definition at line 48 of file stm32g0xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0

Key derivation mode only used when performing ECB and CBC decryptions

Definition at line 49 of file stm32g0xx_hal_cryp_ex.c.

#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE

Key derivation and decryption only used when performing ECB and CBC decryptions

Definition at line 51 of file stm32g0xx_hal_cryp_ex.c.

#define CRYP_PHASE_FINAL AES_CR_GCMPH

GCM/GMAC or CCM final phase

Definition at line 46 of file stm32g0xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_PHASE_HEADER AES_CR_GCMPH_0

GCM/GMAC or CCM header phase

Definition at line 44 of file stm32g0xx_hal_cryp_ex.c.

#define CRYP_PHASE_INIT 0x00000000U

GCM/GMAC (or CCM) init phase

Definition at line 43 of file stm32g0xx_hal_cryp_ex.c.

#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1

GCM(/CCM) payload phase

Definition at line 45 of file stm32g0xx_hal_cryp_ex.c.

#define CRYPEx_PHASE_FINAL 0x03U

CRYP peripheral is in final phase this is relevant only with CCM and GCM modes

Definition at line 54 of file stm32g0xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYPEx_PHASE_PROCESS 0x02U

CRYP peripheral is in processing phase

Definition at line 53 of file stm32g0xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DAC.
      (+) De-initialize the DAC.

Function Documentation

HAL_StatusTypeDef HAL_DAC_DeInit ( DAC_HandleTypeDef * hdac )

Deinitialize the DAC peripheral registers to their default reset values.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 405 of file stm32g0xx_hal_dac.c.

References assert_param, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspDeInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::Instance, __DAC_HandleTypeDef::MspDeInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Init ( DAC_HandleTypeDef * hdac )

Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 344 of file stm32g0xx_hal_dac.c.

References assert_param, __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_NONE, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::Instance, __DAC_HandleTypeDef::Lock, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

void HAL_DAC_MspDeInit ( DAC_HandleTypeDef * hdac )

DeInitialize the DAC MSP.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 466 of file stm32g0xx_hal_dac.c.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_MspInit ( DAC_HandleTypeDef * hdac )

Initialize the DAC MSP.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 450 of file stm32g0xx_hal_dac.c.

Referenced by HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

HAL_StatusTypeDef HAL_DAC_RegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID,
 |  | pDAC_CallbackTypeDef | pCallback
 | ) |  |

Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hdac | DAC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 1224 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_UnRegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hdac DAC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
  • HAL_DAC_ALL_CB_ID DAC All callbacks
Return values:
status

Definition at line 1333 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ALL_CB_ID, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspDeInit(), HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MspInit(), HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
DAC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.

Function Documentation

void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 882 of file stm32g0xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 898 of file stm32g0xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 930 of file stm32g0xx_hal_dac.c.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 914 of file stm32g0xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handles DAC interrupt request This function uses the interruption of DMA underrun.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 775 of file stm32g0xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, __HAL_DAC_GET_IT_SOURCE, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_RegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID,
 |  | pDAC_CallbackTypeDef | pCallback
 | ) |  |

Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hdac | DAC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 1224 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Alignment Specifies the data alignment. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data | Data to be loaded in the selected data holding register.
Return values:
HAL status

Definition at line 848 of file stm32g0xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 508 of file stm32g0xx_hal_dac.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, DAC_TRIGGER_SOFTWARE, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to DAC peripheral
Alignment Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 595 of file stm32g0xx_hal_dac.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, __DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DAC_Stop | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 563 of file stm32g0xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, HAL_DAC_STATE_READY, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Stop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 727 of file stm32g0xx_hal_dac.c.

References __HAL_DAC_DISABLE, __HAL_DAC_DISABLE_IT, assert_param, DAC_CHANNEL_1, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, __DAC_HandleTypeDef::DMA_Handle1, __DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_READY, HAL_DMA_Abort(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_UnRegisterCallback | ( | DAC_HandleTypeDef * | hdac,
 |  | HAL_DAC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hdac DAC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
  • HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
  • HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
  • HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
  • HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
  • HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
  • HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
  • HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
  • HAL_DAC_ALL_CB_ID DAC All callbacks
Return values:
status

Definition at line 1333 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, __DAC_HandleTypeDef::ConvCpltCallbackCh2, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, __DAC_HandleTypeDef::DMAUnderrunCallbackCh1, __DAC_HandleTypeDef::DMAUnderrunCallbackCh2, __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ALL_CB_ID, HAL_DAC_CH1_COMPLETE_CB_ID, HAL_DAC_CH1_ERROR_ID, HAL_DAC_CH1_HALF_COMPLETE_CB_ID, HAL_DAC_CH1_UNDERRUN_CB_ID, HAL_DAC_CH2_COMPLETE_CB_ID, HAL_DAC_CH2_ERROR_ID, HAL_DAC_CH2_HALF_COMPLETE_CB_ID, HAL_DAC_CH2_UNDERRUN_CB_ID, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_ConvHalfCpltCallbackCh1(), HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_INVALID_CALLBACK, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_MspDeInit(), HAL_DAC_MSPDEINIT_CB_ID, HAL_DAC_MspInit(), HAL_DAC_MSPINIT_CB_ID, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, HAL_DACEx_ConvCpltCallbackCh2(), HAL_DACEx_ConvHalfCpltCallbackCh2(), HAL_DACEx_DMAUnderrunCallbackCh2(), HAL_DACEx_ErrorCallbackCh2(), __DAC_HandleTypeDef::MspDeInitCallback, __DAC_HandleTypeDef::MspInitCallback, and __DAC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DAC Exported Functions

Peripheral Control functions. More...

Functions

uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 1001 of file stm32g0xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral, DAC_SampleAndHoldConfTypeDef::DAC_HoldTime, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime, DAC_ChannelConfTypeDef::DAC_SampleAndHold, DAC_SAMPLEANDHOLD_ENABLE, DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig, DAC_SampleAndHoldConfTypeDef::DAC_SampleTime, DAC_ChannelConfTypeDef::DAC_Trigger, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_TIMEOUT, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_TIMEOUT, HAL_Delay(), HAL_GetTick(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_CHIP_CONNECTION, IS_DAC_HOLDTIME, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_REFRESHTIME, IS_DAC_SAMPLEANDHOLD, IS_DAC_SAMPLETIME, IS_DAC_TRIGGER, IS_DAC_TRIMMING, IS_DAC_TRIMMINGVALUE, __DAC_HandleTypeDef::State, and TIMEOUT_DAC_CALIBCONFIG.

uint32_t HAL_DAC_GetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Returns the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 969 of file stm32g0xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DAC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

Peripheral State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Errors functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DAC state.
      (+) Check the DAC Errors.

Function Documentation

uint32_t HAL_DAC_GetError ( DAC_HandleTypeDef * hdac )

Return the DAC error code.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
DAC Error Code

Definition at line 1182 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::ErrorCode.

HAL_DAC_StateTypeDef HAL_DAC_GetState ( DAC_HandleTypeDef * hdac )

return the DAC handle state

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL state

Definition at line 1169 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Exported Types

Data Structures | Typedefs | Enumerations
DAC Exported Types
DAC

Data Structures

struct | __DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Typedefs

typedef struct __DAC_HandleTypeDef | DAC_HandleTypeDef
DAC handle Structure definition.
typedef void(* | pDAC_CallbackTypeDef )(DAC_HandleTypeDef *hdac)
HAL DAC Callback pointer definition.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_DAC_CallbackIDTypeDef {
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, HAL_DAC_CH1_ERROR_ID = 0x02U, HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U,
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, HAL_DAC_CH2_ERROR_ID = 0x06U, HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U,
HAL_DAC_MSPINIT_CB_ID = 0x08U, HAL_DAC_MSPDEINIT_CB_ID = 0x09U, HAL_DAC_ALL_CB_ID = 0x0AU
}
HAL DAC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __DAC_HandleTypeDef DAC_HandleTypeDef

DAC handle Structure definition.

typedef void(* pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac)

HAL DAC Callback pointer definition.

Definition at line 167 of file stm32g0xx_hal_dac.h.

Enumeration Type Documentation

enum HAL_DAC_CallbackIDTypeDef

HAL DAC Callback ID enumeration definition.

Enumerator:
HAL_DAC_CH1_COMPLETE_CB_ID

DAC CH1 Complete Callback ID

HAL_DAC_CH1_HALF_COMPLETE_CB_ID

DAC CH1 half Complete Callback ID

HAL_DAC_CH1_ERROR_ID

DAC CH1 error Callback ID

HAL_DAC_CH1_UNDERRUN_CB_ID

DAC CH1 underrun Callback ID

HAL_DAC_CH2_COMPLETE_CB_ID

DAC CH2 Complete Callback ID

HAL_DAC_CH2_HALF_COMPLETE_CB_ID

DAC CH2 half Complete Callback ID

HAL_DAC_CH2_ERROR_ID

DAC CH2 error Callback ID

HAL_DAC_CH2_UNDERRUN_CB_ID

DAC CH2 underrun Callback ID

HAL_DAC_MSPINIT_CB_ID

DAC MspInit Callback ID

HAL_DAC_MSPDEINIT_CB_ID

DAC MspDeInit Callback ID

HAL_DAC_ALL_CB_ID

DAC All ID

Definition at line 147 of file stm32g0xx_hal_dac.h.

enum HAL_DAC_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_DAC_STATE_RESET

DAC not yet initialized or disabled

HAL_DAC_STATE_READY

DAC initialized and ready for use

HAL_DAC_STATE_BUSY

DAC internal processing is ongoing

HAL_DAC_STATE_TIMEOUT

DAC timeout state

HAL_DAC_STATE_ERROR

DAC error state

Definition at line 49 of file stm32g0xx_hal_dac.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __DAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DAC_HandleTypeDef Struct Reference
DAC Exported Types

DAC handle Structure definition. More...

#include <stm32g0xx_hal_dac.h>

Data Fields

DAC_TypeDef * | Instance
__IO HAL_DAC_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * DMA_Handle1
DMA_HandleTypeDef * DMA_Handle2
__IO uint32_t | ErrorCode
void(* | ConvCpltCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvHalfCpltCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ErrorCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | DMAUnderrunCallbackCh1 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvCpltCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | ConvHalfCpltCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | ErrorCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | DMAUnderrunCallbackCh2 )(struct __DAC_HandleTypeDef *hdac)
void(* | MspInitCallback )(struct __DAC_HandleTypeDef *hdac)
void(* | MspDeInitCallback )(struct __DAC_HandleTypeDef *hdac)

Detailed Description

DAC handle Structure definition.

Definition at line 63 of file stm32g0xx_hal_dac.h.

Field Documentation

void(* __DAC_HandleTypeDef::ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 81 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 86 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 82 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAHalfConvCpltCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 87 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAHalfConvCpltCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

DMA_HandleTypeDef* __DAC_HandleTypeDef::DMA_Handle1

Pointer DMA handler for channel 1

Definition at line 74 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

DMA_HandleTypeDef* __DAC_HandleTypeDef::DMA_Handle2

Pointer DMA handler for channel 2

Definition at line 76 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

void(* __DAC_HandleTypeDef::DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 84 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 89 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac)

Definition at line 83 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac)

Definition at line 88 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAErrorCh2(), HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

__IO uint32_t __DAC_HandleTypeDef::ErrorCode

DAC Error code

Definition at line 78 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetError(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), HAL_DAC_Start_DMA(), and HAL_DAC_UnRegisterCallback().

DAC_TypeDef* __DAC_HandleTypeDef::Instance

Register base address

Definition at line 68 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualGetValue(), HAL_DACEx_DualSetValue(), HAL_DACEx_DualStart(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

HAL_LockTypeDef __DAC_HandleTypeDef::Lock

DAC locking object

Definition at line 72 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Init().

void(* __DAC_HandleTypeDef::MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac)

Definition at line 93 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

void(* __DAC_HandleTypeDef::MspInitCallback)(struct __DAC_HandleTypeDef *hdac)

Definition at line 92 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Init(), HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

__IO HAL_DAC_StateTypeDef __DAC_HandleTypeDef::State

DAC communication state

Definition at line 70 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetState(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_RegisterCallback(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DAC_UnRegisterCallback(), HAL_DACEx_DualStart(), HAL_DACEx_DualStop(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_TriangleWaveGenerate().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_dac.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC_SampleAndHoldConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_SampleAndHoldConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration sample and hold Channel structure definition. More...

#include <stm32g0xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleTime
uint32_t | DAC_HoldTime
uint32_t | DAC_RefreshTime

Detailed Description

DAC Configuration sample and hold Channel structure definition.

Definition at line 101 of file stm32g0xx_hal_dac.h.

Field Documentation

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_HoldTime

Specifies the hold time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 107 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime

Specifies the refresh time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 255

Definition at line 111 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_SampleTime

Specifies the Sample time for the selected channel. This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 103 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_dac.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_ChannelConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration regular Channel structure definition. More...

#include <stm32g0xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleAndHold
uint32_t | DAC_Trigger
uint32_t | DAC_OutputBuffer
uint32_t | DAC_ConnectOnChipPeripheral
uint32_t | DAC_UserTrimming
uint32_t | DAC_TrimmingValue
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig

Detailed Description

DAC Configuration regular Channel structure definition.

Definition at line 119 of file stm32g0xx_hal_dac.h.

Field Documentation

uint32_t DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral

Specifies whether the DAC output is connected or not to on chip peripheral . This parameter can be a value of DAC ConnectOnChipPeripheral

Definition at line 130 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC output buffer

Definition at line 127 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_SampleAndHold

Specifies whether the DAC mode. This parameter can be a value of DAC power mode

Definition at line 121 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

DAC_SampleAndHoldConfTypeDef DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig

Sample and Hold settings

Definition at line 140 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC trigger selection

Definition at line 124 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_TrimmingValue

Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 137 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

uint32_t DAC_ChannelConfTypeDef::DAC_UserTrimming

Specifies the trimming mode This parameter must be a value of DAC User Trimming DAC_UserTrimming is either factory or user trimming

Definition at line 133 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_dac.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Error Code

Defines
DAC Error Code
DAC Exported Constants

Defines

#define | HAL_DAC_ERROR_NONE 0x00U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
#define | HAL_DAC_ERROR_DMA 0x04U
#define | HAL_DAC_ERROR_TIMEOUT 0x08U
#define | HAL_DAC_ERROR_INVALID_CALLBACK 0x10U

Define Documentation

#define HAL_DAC_ERROR_DMA 0x04U

DMA error

Definition at line 186 of file stm32g0xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), and HAL_DAC_Start_DMA().

#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U

DAC channel1 DMA underrun error

Definition at line 184 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U

DAC channel2 DMA underrun error

Definition at line 185 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U

Invalid callback error

Definition at line 189 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_RegisterCallback(), and HAL_DAC_UnRegisterCallback().

#define HAL_DAC_ERROR_NONE 0x00U

No error

Definition at line 183 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_Init().

#define HAL_DAC_ERROR_TIMEOUT 0x08U

Timeout error

Definition at line 187 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

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STM32G0C1xx HAL User Manual: DAC trigger selection

Defines
DAC trigger selection
DAC Exported Constants

Defines

#define | DAC_TRIGGER_NONE 0x00000000UL
#define | DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1)
#define | DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

Define Documentation

#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 209 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

LPTIM1_OUT selected as external conversion trigger for DAC channel

Definition at line 207 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)

LPTIM2_OUT selected as external conversion trigger for DAC channel

Definition at line 208 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_NONE 0x00000000UL

Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger

Definition at line 199 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1)

Conversion started by software trigger for DAC channel

Definition at line 200 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Start(), and HAL_DACEx_DualStart().

#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)

TIM15 TRGO selected as external conversion trigger for DAC channel

Definition at line 206 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1)

TIM1 TRGO selected as external conversion trigger for DAC channel

Definition at line 201 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1)

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 202 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

TIM3 TRGO selected as external conversion trigger for DAC channel

Definition at line 203 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 204 of file stm32g0xx_hal_dac.h.

#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 205 of file stm32g0xx_hal_dac.h.

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STM32G0C1xx HAL User Manual: DAC output buffer

Defines
DAC output buffer
DAC Exported Constants

Defines

#define | DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define | DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)

Define Documentation

#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)

Definition at line 219 of file stm32g0xx_hal_dac.h.

#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U

Definition at line 218 of file stm32g0xx_hal_dac.h.

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STM32G0C1xx HAL User Manual: DAC Channel selection

Defines
DAC Channel selection
DAC Exported Constants

Defines

#define | DAC_CHANNEL_1 0x00000000U
#define | DAC_CHANNEL_2 0x00000010U

Define Documentation

#define DAC_CHANNEL_1 0x00000000U

Definition at line 228 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualStart(), HAL_DACEx_DualStop(), and HAL_DACEx_SelfCalibrate().

#define DAC_CHANNEL_2 0x00000010U

Definition at line 230 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DACEx_DualStart(), and HAL_DACEx_DualStop().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC data alignment

Defines
DAC data alignment
DAC Exported Constants

Defines

#define | DAC_ALIGN_12B_R 0x00000000U
#define | DAC_ALIGN_12B_L 0x00000004U
#define | DAC_ALIGN_8B_R 0x00000008U

Define Documentation

#define DAC_ALIGN_12B_L 0x00000004U

Definition at line 240 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_12B_R 0x00000000U

Definition at line 239 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_SelfCalibrate().

#define DAC_ALIGN_8B_R 0x00000008U

Definition at line 241 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC flags definition

Defines
DAC flags definition
DAC Exported Constants

Defines

#define | DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

Define Documentation

#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)

Definition at line 250 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

Definition at line 252 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC IT definition

Defines
DAC IT definition
DAC Exported Constants

Defines

#define | DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)

Define Documentation

#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)

Definition at line 262 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)

Definition at line 264 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC ConnectOnChipPeripheral

Defines
DAC ConnectOnChipPeripheral
DAC Exported Constants

Defines

#define | DAC_CHIPCONNECT_DISABLE (0x00000000UL)
#define | DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0)

Define Documentation

#define DAC_CHIPCONNECT_DISABLE (0x00000000UL)

Definition at line 274 of file stm32g0xx_hal_dac.h.

#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0)

Definition at line 275 of file stm32g0xx_hal_dac.h.

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STM32G0C1xx HAL User Manual: DAC User Trimming

Defines
DAC User Trimming
DAC Exported Constants

Defines

#define | DAC_TRIMMING_FACTORY (0x00000000UL)
#define | DAC_TRIMMING_USER (0x00000001UL)

Define Documentation

#define DAC_TRIMMING_FACTORY (0x00000000UL)

Factory trimming

Definition at line 284 of file stm32g0xx_hal_dac.h.

#define DAC_TRIMMING_USER (0x00000001UL)

User trimming

Definition at line 285 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC power mode

Defines
DAC power mode
DAC Exported Constants

Defines

#define | DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define | DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)

Define Documentation

#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)

Definition at line 293 of file stm32g0xx_hal_dac.h.

#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)

Definition at line 294 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Exported Macros

Defines
DAC Exported Macros
DAC

Defines

#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.

Define Documentation

#define __HAL_DAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = (__FLAG__))

Clear the DAC's flag.

Parameters:
__HANDLE__ specifies the DAC handle.
__FLAG__ specifies the DAC flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 408 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_DISABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))

Disable the DAC channel.

Parameters:
__HANDLE__ | specifies the DAC handle
__DAC_Channel__ | specifies the DAC channel.
Return values:
None

Definition at line 336 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), and HAL_DACEx_DualStop().

#define __HAL_DAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the DAC interrupt.

Parameters:
__HANDLE__ specifies the DAC handle
__INTERRUPT__ specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 377 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Stop_DMA().

#define __HAL_DAC_ENABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))

Enable the DAC channel.

Parameters:
__HANDLE__ | specifies the DAC handle.
__DAC_Channel__ | specifies the DAC channel
Return values:
None

Definition at line 328 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Start(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualStart().

#define __HAL_DAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the DAC interrupt.

Parameters:
__HANDLE__ specifies the DAC handle
__INTERRUPT__ specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 367 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define __HAL_DAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected DAC's flag status.

Parameters:
__HANDLE__ specifies the DAC handle.
__FLAG__ specifies the DAC flag to get. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 398 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__HANDLE__)->Instance->CR\
                                                             & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified DAC interrupt source is enabled or not.

Parameters:
__HANDLE__ DAC handle
__INTERRUPT__ DAC interrupt source to check This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
Return values:
State of interruption (SET or RESET)

Definition at line 387 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
                                                     } while(0)

Reset DAC handle state.

Parameters:
__HANDLE__ specifies the DAC handle.
Return values:
None

Definition at line 314 of file stm32g0xx_hal_dac.h.

#define DAC_DHR12R1_ALIGNMENT ( __ALIGNMENT__ ) (0x00000008UL + (__ALIGNMENT__))

Set DHR12R1 alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 343 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_SelfCalibrate().

#define DAC_DHR12R2_ALIGNMENT ( __ALIGNMENT__ ) (0x00000014UL + (__ALIGNMENT__))

Set DHR12R2 alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 350 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_SelfCalibrate().

#define DAC_DHR12RD_ALIGNMENT ( __ALIGNMENT__ ) (0x00000020UL + (__ALIGNMENT__))

Set DHR12RD alignment.

Parameters:
__ALIGNMENT__ specifies the DAC alignment
Return values:
None

Definition at line 357 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)

Define Documentation

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_ALIGN_12B_R) || \
                             ((ALIGN) == DAC_ALIGN_12B_L) || \
                             ((ALIGN) == DAC_ALIGN_8B_R))

Definition at line 425 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_CHANNEL_1) || \
                                 ((CHANNEL) == DAC_CHANNEL_2))

Definition at line 422 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0UL)

Definition at line 429 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_DualSetValue().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

Definition at line 419 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_REFRESHTIME ( TIME ) ((TIME) <= 0x000000FFUL)

Definition at line 431 of file stm32g0xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Private Functions

Functions
DAC Private Functions
DAC

Functions

void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

void DAC_DMAConvCpltCh1 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1448 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh1, HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAErrorCh1 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1484 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::ErrorCallbackCh1, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAHalfConvCpltCh1 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1467 of file stm32g0xx_hal_dac.c.

References __DAC_HandleTypeDef::ConvHalfCpltCallbackCh1, and HAL_DAC_ConvHalfCpltCallbackCh1().

Referenced by HAL_DAC_Start_DMA().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */

Define Documentation

#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */

Definition at line 307 of file stm32g0xx_hal_dac.c.

Referenced by HAL_DAC_ConfigChannel().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
DACEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.

Detailed Description

Extended IO operation functions.

  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.
      (+) Get result of dual mode conversion.

Function Documentation

void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 315 of file stm32g0xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 331 of file stm32g0xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 363 of file stm32g0xx_hal_dac_ex.c.

Referenced by HAL_DAC_Init(), HAL_DAC_IRQHandler(), and HAL_DAC_UnRegisterCallback().

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 591 of file stm32g0xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment | Specifies the data alignment for dual channel DAC. This parameter can be one of the following values: DAC_ALIGN_8B_R: 8bit right data alignment selected DAC_ALIGN_12B_L: 12bit left data alignment selected DAC_ALIGN_12B_R: 12bit right data alignment selected
Data1 | Data for DAC Channel1 to be loaded in the selected data holding register.
Data2 | Data for DAC Channel2 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 279 of file stm32g0xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, __DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DACEx_DualStart ( DAC_HandleTypeDef * hdac )

Enables DAC and starts conversion of both channels.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 105 of file stm32g0xx_hal_dac_ex.c.

References __HAL_DAC_ENABLE, DAC_CHANNEL_1, DAC_CHANNEL_2, DAC_TRIGGER_SOFTWARE, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_DualStop ( DAC_HandleTypeDef * hdac )

Disables DAC and stop conversion of both channels.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 148 of file stm32g0xx_hal_dac_ex.c.

References __HAL_DAC_DISABLE, DAC_CHANNEL_1, DAC_CHANNEL_2, HAL_DAC_STATE_READY, and __DAC_HandleTypeDef::State.

void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 347 of file stm32g0xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2(), HAL_DAC_Init(), and HAL_DAC_UnRegisterCallback().

uint32_t HAL_DACEx_GetTrimOffset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac DAC handle
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Trimming value : range: 0->31

Definition at line 557 of file stm32g0xx_hal_dac_ex.c.

References assert_param, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Amplitude Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values:
  • DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  • DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
Return values:
HAL status

Definition at line 237 of file stm32g0xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SelfCalibrate | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Run the self calibration of one DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC channel configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Updates | DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
HAL | status
Note:
Calibration runs about 7 ms.

Definition at line 387 of file stm32g0xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_12B_R, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, HAL_DAC_STATE_BUSY, HAL_Delay(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure updated with new DAC trimming value.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
NewTrimmingValue | DAC new trimming value
Return values:
HAL status

Definition at line 515 of file stm32g0xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Amplitude Select max triangle amplitude. This parameter can be one of the following values:
  • DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  • DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  • DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  • DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  • DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  • DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  • DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  • DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  • DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  • DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  • DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  • DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
Return values:
HAL status

Definition at line 187 of file stm32g0xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and __DAC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DACEx Exported Functions

Extended Peripheral Control functions. More...

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.

Detailed Description

Extended Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 591 of file stm32g0xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::Instance.

uint32_t HAL_DACEx_GetTrimOffset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac DAC handle
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Trimming value : range: 0->31

Definition at line 557 of file stm32g0xx_hal_dac_ex.c.

References assert_param, __DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

HAL_StatusTypeDef HAL_DACEx_SelfCalibrate | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Run the self calibration of one DAC channel.

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC channel configuration structure.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Updates | DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
HAL | status
Note:
Calibration runs about 7 ms.

Definition at line 387 of file stm32g0xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_12B_R, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, HAL_DAC_STATE_BUSY, HAL_Delay(), __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and __DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac | pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig | DAC configuration structure updated with new DAC trimming value.
Channel The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
NewTrimmingValue | DAC new trimming value
Return values:
HAL status

Definition at line 515 of file stm32g0xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, __DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DACEx private functions

Functions
DACEx private functions
DACEx

Extended private functions. More...

Functions

void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended private functions.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 624 of file stm32g0xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ConvCpltCallbackCh2, HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 660 of file stm32g0xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ErrorCallbackCh2, __DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and __DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 643 of file stm32g0xx_hal_dac_ex.c.

References __DAC_HandleTypeDef::ConvHalfCpltCallbackCh2, and HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DACEx lfsrunmask triangle amplitude

Defines
DACEx lfsrunmask triangle amplitude
DACEx Exported Constants

Defines

#define | DAC_LFSRUNMASK_BIT0 0x00000000UL
#define | DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 0x00000000UL
#define | DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define DAC_LFSRUNMASK_BIT0 0x00000000UL

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 55 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 65 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 66 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 56 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 57 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 58 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 59 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 60 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 61 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 62 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 63 of file stm32g0xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 64 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL

Select max triangle amplitude of 1

Definition at line 67 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 1023

Definition at line 76 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Select max triangle amplitude of 127

Definition at line 73 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 15

Definition at line 70 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Select max triangle amplitude of 2047

Definition at line 77 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 255

Definition at line 74 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)

Select max triangle amplitude of 3

Definition at line 68 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )

Select max triangle amplitude of 31

Definition at line 71 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 4095

Definition at line 78 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )

Select max triangle amplitude of 511

Definition at line 75 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 63

Definition at line 72 of file stm32g0xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )

Select max triangle amplitude of 7

Definition at line 69 of file stm32g0xx_hal_dac_ex.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DACEx Private Macros

Defines
DACEx Private Macros
DACEx

Defines

#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Define Documentation

#define IS_DAC_CHIP_CONNECTION ( CONNECT )
Value:
(((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))

Definition at line 119 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_HOLDTIME ( TIME ) ((TIME) <= 0x000003FFU)

Definition at line 110 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

Definition at line 125 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_NEWTRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1FU)

Definition at line 117 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DACEx_SetUserTrimming().

#define IS_DAC_SAMPLEANDHOLD ( MODE )
Value:
(((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))

Definition at line 112 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_SAMPLETIME ( TIME ) ((TIME) <= 0x000003FFU)

Definition at line 108 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_TRIGGER_NONE)       || \
                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE)   || \
                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T3_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9))

Definition at line 96 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == DAC_TRIMMING_FACTORY) || \
                                   ((TRIMMING) == DAC_TRIMMING_USER))

Definition at line 122 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1FU)

Definition at line 115 of file stm32g0xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on channel number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.

Function Documentation

static void DMA_CalcDMAMUXChannelBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX channel and status mask depending on channel number.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 1118 of file stm32g0xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_CalcDMAMUXRequestGenBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX request generator params.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 1164 of file stm32g0xx_hal_dma.c.

References __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::Init, and DMA_InitTypeDef::Request.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 1071 of file stm32g0xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_FLAG_GI1, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Channel source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitialize the DMA peripheral.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 259 of file stm32g0xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __HAL_DMA_DISABLE, assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_FLAG_GI1, DMA_REQUEST_GENERATOR3, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::Request, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 152 of file stm32g0xx_hal_dma.c.

References assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_MEMORY_TO_MEMORY, DMA_REQUEST_GENERATOR3, DMA_REQUEST_MEM2MEM, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_ALL_REQUEST, IS_DMA_DIRECTION, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, DMA_InitTypeDef::Request, and __DMA_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
DMA Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

Input and Output operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request
      (+) Register and Unregister DMA callbacks

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Abort the DMA Transfer.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 507 of file stm32g0xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_GI1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Stop_DMA(), HAL_DAC_Stop_DMA(), HAL_I2S_DMAStop(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_SPI_DMAStop(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), HAL_USART_Abort(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

HAL_StatusTypeDef HAL_DMA_Abort_IT ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer in Interrupt mode.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 572 of file stm32g0xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_GI1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), and I2C_ITError().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handle DMA interrupt request.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 797 of file stm32g0xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_GI1, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_TE, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_LevelCompleteTypeDef | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CompleteLevel | Specifies the DMA level complete.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 637 of file stm32g0xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __HAL_DMA_GET_FLAG, __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_GI1, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, HAL_GetTick(), __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_RegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(DMA_HandleTypeDef *_hdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CallbackID | User Callback identifier a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
pCallback | Pointer to private callback function which has pointer to a DMA_HandleTypeDef structure as parameter.
Return values:
HAL status

Definition at line 903 of file stm32g0xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 382 of file stm32g0xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_BUSY, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 433 of file stm32g0xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __HAL_DMA_ENABLE, __HAL_DMA_ENABLE_IT, assert_param, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_BUSY, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by CRYP_SetDMAConfig(), CRYP_SetHeaderDMAConfig(), HAL_ADC_Start_DMA(), HAL_DAC_Start_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and UART_Start_Receive_DMA().

HAL_StatusTypeDef HAL_DMA_UnRegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CallbackID | User Callback identifier a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 954 of file stm32g0xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_ALL_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DMA Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA handle state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
DMA Error Code

Definition at line 1044 of file stm32g0xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Return the DMA handle state.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL state

Definition at line 1032 of file stm32g0xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Referenced by I2C_ITError().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04U
}
HAL DMA Callback ID structure definition. More...

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_CallbackIDTypeDef

HAL DMA Callback ID structure definition.

Enumerator:
HAL_DMA_XFER_CPLT_CB_ID

Full transfer

HAL_DMA_XFER_HALFCPLT_CB_ID

Half transfer

HAL_DMA_XFER_ERROR_CB_ID

Error

HAL_DMA_XFER_ABORT_CB_ID

Abort

HAL_DMA_XFER_ALL_CB_ID

All

Definition at line 100 of file stm32g0xx_hal_dma.h.

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Error Code structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 91 of file stm32g0xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_TIMEOUT

DMA timeout state

Definition at line 80 of file stm32g0xx_hal_dma.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32g0xx_hal_dma.h>

Data Fields

uint32_t | Request
uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority

Detailed Description

DMA Configuration Structure definition.

Definition at line 47 of file stm32g0xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 52 of file stm32g0xx_hal_dma.h.

Referenced by DMA_SetConfig(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 65 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 59 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Channelx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel

Definition at line 68 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init(), I2S_DMARxCplt(), I2S_DMATxCplt(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAPeriodElapsedCplt(), and TIM_DMATriggerCplt().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 62 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 56 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Channelx. This parameter can be a value of DMA Priority level

Definition at line 73 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Request

Specifies the request selected for the specified channel. This parameter can be a value of DMA request

Definition at line 49 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), HAL_DMA_DeInit(), and HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_dma.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32g0xx_hal_dma.h>

Data Fields

DMA_Channel_TypeDef * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferAbortCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
DMA_TypeDef * | DmaBaseAddress
uint32_t | ChannelIndex
DMAMUX_Channel_TypeDef * | DMAmuxChannel
DMAMUX_ChannelStatus_TypeDef * | DMAmuxChannelStatus
uint32_t | DMAmuxChannelStatusMask
DMAMUX_RequestGen_TypeDef * | DMAmuxRequestGen
DMAMUX_RequestGenStatus_TypeDef * | DMAmuxRequestGenStatus
uint32_t | DMAmuxRequestGenStatusMask

Detailed Description

DMA handle Structure definition.

Definition at line 113 of file stm32g0xx_hal_dma.h.

Field Documentation

uint32_t __DMA_HandleTypeDef::ChannelIndex

DMA Channel Index

Definition at line 139 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMA_TypeDef* __DMA_HandleTypeDef::DmaBaseAddress

DMA Channel Base Address

Definition at line 136 of file stm32g0xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMAMUX_Channel_TypeDef* __DMA_HandleTypeDef::DMAmuxChannel

Register base address

Definition at line 141 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxSync(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_ChannelStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxChannelStatus

DMAMUX Channels Status Base Address

Definition at line 143 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxChannelStatusMask

DMAMUX Channel Status Mask

Definition at line 145 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGen_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGen

DMAMUX request generator Base Address

Definition at line 147 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGenStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGenStatus

DMAMUX request generator Address

Definition at line 149 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask

DMAMUX request generator Status mask

Definition at line 151 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 133 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), and HAL_DMAEx_MUX_IRQHandler().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 117 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), I2S_DMARxCplt(), I2S_DMATxCplt(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAPeriodElapsedCplt(), and TIM_DMATriggerCplt().

DMA_Channel_TypeDef* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 115 of file stm32g0xx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_UART_IRQHandler(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 119 of file stm32g0xx_hal_dma.h.

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 123 of file stm32g0xx_hal_dma.h.

Referenced by IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxHalfCplt(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxHalfCplt(), UART_DMATxOnlyAbortCallback(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), and USART_DMATxHalfCplt().

__IO HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 121 of file stm32g0xx_hal_dma.h.

Referenced by HAL_ADC_Stop_DMA(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_RegisterCallback(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), and HAL_DMAEx_EnableMuxRequestGenerator().

void(* __DMA_HandleTypeDef::XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer abort callback

Definition at line 131 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Transmit_DMA(), HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), I2C_DMAAbort(), I2C_ITError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_Start_Receive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 125 of file stm32g0xx_hal_dma.h.

Referenced by CRYP_SetDMAConfig(), CRYP_SetHeaderDMAConfig(), HAL_ADC_Start_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and UART_Start_Receive_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 129 of file stm32g0xx_hal_dma.h.

Referenced by ADC_DMAConvCplt(), CRYP_SetDMAConfig(), CRYP_SetHeaderDMAConfig(), HAL_ADC_Start_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_MUX_IRQHandler(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and UART_Start_Receive_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 127 of file stm32g0xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and UART_Start_Receive_DMA().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_dma.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

Defines

#define | HAL_DMA_ERROR_NONE 0x00000000U
#define | HAL_DMA_ERROR_TE 0x00000001U
#define | HAL_DMA_ERROR_NO_XFER 0x00000004U
#define | HAL_DMA_ERROR_TIMEOUT 0x00000020U
#define | HAL_DMA_ERROR_PARAM 0x00000040U
#define | HAL_DMA_ERROR_BUSY 0x00000080U
#define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
#define | HAL_DMA_ERROR_SYNC 0x00000200U
#define | HAL_DMA_ERROR_REQGEN 0x00000400U

Define Documentation

#define HAL_DMA_ERROR_BUSY 0x00000080U

DMA Busy error

Definition at line 171 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), and HAL_DMAEx_ConfigMuxSync().

#define HAL_DMA_ERROR_NO_XFER 0x00000004U

Abort requested with no Xfer ongoing

Definition at line 168 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_NONE 0x00000000U

No error

Definition at line 166 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U

Not supported mode

Definition at line 172 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_PARAM 0x00000040U

Parameter error

Definition at line 170 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define HAL_DMA_ERROR_REQGEN 0x00000400U

DMAMUX request generator overrun error

Definition at line 174 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_SYNC 0x00000200U

DMAMUX sync overrun error

Definition at line 173 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_TE 0x00000001U

Transfer error

Definition at line 167 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT 0x00000020U

Timeout error

Definition at line 169 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA request

Defines
DMA request
DMA Exported Constants

Defines

#define | DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM
#define | DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0
#define | DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1
#define | DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2
#define | DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3
#define | DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1
#define | DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN
#define | DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT
#define | DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1
#define | DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2
#define | DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX
#define | DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX
#define | DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX
#define | DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX
#define | DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX
#define | DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX
#define | DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX
#define | DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX
#define | DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX
#define | DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX
#define | DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1
#define | DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2
#define | DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3
#define | DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4
#define | DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM
#define | DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP
#define | DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1
#define | DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2
#define | DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3
#define | DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4
#define | DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG
#define | DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP
#define | DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1
#define | DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2
#define | DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3
#define | DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4
#define | DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG
#define | DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP
#define | DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP
#define | DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP
#define | DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1
#define | DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2
#define | DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM
#define | DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP
#define | DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1
#define | DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM
#define | DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP
#define | DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1
#define | DMA_REQUEST_TIM17_COM LL_DMAMUX_REQ_TIM17_COM
#define | DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP
#define | DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX
#define | DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX
#define | DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX
#define | DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX
#define | DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX
#define | DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX
#define | DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX
#define | DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX
#define | DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX
#define | DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX
#define | DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX
#define | DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX
#define | DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX
#define | DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX
#define | DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX
#define | DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX
#define | DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX
#define | DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX
#define | DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1
#define | DMA_REQUEST_TIM4_CH2 LL_DMAMUX_REQ_TIM4_CH2
#define | DMA_REQUEST_TIM4_CH3 LL_DMAMUX_REQ_TIM4_CH3
#define | DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4
#define | DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG
#define | DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP
#define | DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX
#define | DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX
#define | DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX
#define | DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX
#define | DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ

Define Documentation

#define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ

Definition at line 303 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1

DMAMUX ADC1 request

Definition at line 188 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN

DMAMUX AES_IN request

Definition at line 190 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT

DMAMUX AES_OUT request

Definition at line 191 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1

DMAMUX DAC_CH1 request

Definition at line 194 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2

DMAMUX DAC_CH2 request

Definition at line 195 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0

DMAMUX request generator 0

Definition at line 184 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1

DMAMUX request generator 1

Definition at line 185 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2

DMAMUX request generator 2

Definition at line 186 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3

DMAMUX request generator 3

Definition at line 187 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX

DMAMUX I2C1 RX request

Definition at line 197 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX

DMAMUX I2C1 TX request

Definition at line 198 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX

DMAMUX I2C2 RX request

Definition at line 199 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX

DMAMUX I2C2 TX request

Definition at line 200 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX

DMAMUX I2C3 RX request

Definition at line 269 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX

DMAMUX I2C3 TX request

Definition at line 270 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX

DMAMUX LPUART1 RX request

Definition at line 202 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX

DMAMUX LPUART1 TX request

Definition at line 203 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX

DMAMUX LPUART2 RX request

Definition at line 274 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX

DMAMUX LPUART2 TX request

Definition at line 275 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM

memory to memory transfer

Definition at line 183 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX

DMAMUX SPI1 RX request

Definition at line 205 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX

DMAMUX SPI1 TX request

Definition at line 206 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX

DMAMUX SPI2 RX request

Definition at line 207 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX

DMAMUX SPI2 TX request

Definition at line 208 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX

DMAMUX SPI3 RX request

Definition at line 279 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX

DMAMUX SPI3 TX request

Definition at line 280 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1

DMAMUX TIM15 CH1 request

Definition at line 236 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2

DMAMUX TIM15 CH2 request

Definition at line 237 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM

DMAMUX TIM15 TRIG COM request

Definition at line 238 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP

DMAMUX TIM15 UP request

Definition at line 239 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1

DMAMUX TIM16 CH1 request

Definition at line 241 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM

DMAMUX TIM16 COM request

Definition at line 242 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP

DMAMUX TIM16 UP request

Definition at line 243 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1

DMAMUX TIM17 CH1 request

Definition at line 244 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM17_COM LL_DMAMUX_REQ_TIM17_COM

DMAMUX TIM17 COM request

Definition at line 245 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP

DMAMUX TIM17 UP request

Definition at line 246 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1

DMAMUX TIM1 CH1 request

Definition at line 209 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2

DMAMUX TIM1 CH2 request

Definition at line 210 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3

DMAMUX TIM1 CH3 request

Definition at line 211 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4

DMAMUX TIM1 CH4 request

Definition at line 212 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM

DMAMUX TIM1 TRIG COM request

Definition at line 213 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP

DMAMUX TIM1 UP request

Definition at line 214 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1

DMAMUX TIM2 CH1 request

Definition at line 216 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2

DMAMUX TIM2 CH2 request

Definition at line 217 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3

DMAMUX TIM2 CH3 request

Definition at line 218 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4

DMAMUX TIM2 CH4 request

Definition at line 219 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG

DMAMUX TIM2 TRIG request

Definition at line 220 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP

DMAMUX TIM2 UP request

Definition at line 221 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1

DMAMUX TIM3 CH1 request

Definition at line 223 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2

DMAMUX TIM3 CH2 request

Definition at line 224 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3

DMAMUX TIM3 CH3 request

Definition at line 225 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4

DMAMUX TIM3 CH4 request

Definition at line 226 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG

DMAMUX TIM3 TRIG request

Definition at line 227 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP

DMAMUX TIM3 UP request

Definition at line 228 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1

DMAMUX TIM4 CH1 request

Definition at line 284 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH2 LL_DMAMUX_REQ_TIM4_CH2

DMAMUX TIM4 CH2 request

Definition at line 285 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH3 LL_DMAMUX_REQ_TIM4_CH3

DMAMUX TIM4 CH3 request

Definition at line 286 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4

DMAMUX TIM4 CH4 request

Definition at line 287 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG

DMAMUX TIM4 TRIG request

Definition at line 288 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP

DMAMUX TIM4 UP request

Definition at line 289 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP

DMAMUX TIM6 UP request

Definition at line 230 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP

DMAMUX TIM7 UP request

Definition at line 233 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX

DMAMUX UCPD1 RX request

Definition at line 260 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX

DMAMUX UCPD1 TX request

Definition at line 261 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX

DMAMUX UCPD2 RX request

Definition at line 264 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX

DMAMUX UCPD2 TX request

Definition at line 265 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX

DMAMUX USART1 RX request

Definition at line 247 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX

DMAMUX USART1 TX request

Definition at line 248 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX

DMAMUX USART2 RX request

Definition at line 249 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX

DMAMUX USART2 TX request

Definition at line 250 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX

DMAMUX USART3 RX request

Definition at line 252 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX

DMAMUX USART3 TX request

Definition at line 253 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX

DMAMUX USART4 RX request

Definition at line 256 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX

DMAMUX USART4 TX request

Definition at line 257 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX

DMAMUX USART5 RX request

Definition at line 293 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX

DMAMUX USART5 TX request

Definition at line 294 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX

DMAMUX USART6 RX request

Definition at line 298 of file stm32g0xx_hal_dma.h.

#define DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX

DMAMUX USART6 TX request

Definition at line 299 of file stm32g0xx_hal_dma.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

Defines

#define | DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY
#define | DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH
#define | DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Define Documentation

#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Memory to memory direction

Definition at line 313 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH

Memory to peripheral direction

Definition at line 312 of file stm32g0xx_hal_dma.h.

Referenced by DMA_SetConfig().

#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY

Peripheral to memory direction

Definition at line 311 of file stm32g0xx_hal_dma.h.

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STM32G0C1xx HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

Defines

#define | DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT
#define | DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT

Define Documentation

#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT

Peripheral increment mode Disable

Definition at line 323 of file stm32g0xx_hal_dma.h.

#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT

Peripheral increment mode Enable

Definition at line 322 of file stm32g0xx_hal_dma.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

Defines

#define | DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT
#define | DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT

Define Documentation

#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT

Memory increment mode Disable

Definition at line 332 of file stm32g0xx_hal_dma.h.

#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT

Memory increment mode Enable

Definition at line 331 of file stm32g0xx_hal_dma.h.

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STM32G0C1xx HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

Defines

#define | DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE
#define | DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD
#define | DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD

Define Documentation

#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE

Peripheral data alignment : Byte

Definition at line 340 of file stm32g0xx_hal_dma.h.

#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD

Peripheral data alignment : HalfWord

Definition at line 341 of file stm32g0xx_hal_dma.h.

#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD

Peripheral data alignment : Word

Definition at line 342 of file stm32g0xx_hal_dma.h.

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STM32G0C1xx HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

Defines

#define | DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE
#define | DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD
#define | DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD

Define Documentation

#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE

Memory data alignment : Byte

Definition at line 350 of file stm32g0xx_hal_dma.h.

#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD

Memory data alignment : HalfWord

Definition at line 351 of file stm32g0xx_hal_dma.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD

Memory data alignment : Word

Definition at line 352 of file stm32g0xx_hal_dma.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

Defines

#define | DMA_NORMAL LL_DMA_MODE_NORMAL
#define | DMA_CIRCULAR LL_DMA_MODE_CIRCULAR

Define Documentation

#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR

Circular mode

Definition at line 361 of file stm32g0xx_hal_dma.h.

#define DMA_NORMAL LL_DMA_MODE_NORMAL

Normal mode

Definition at line 360 of file stm32g0xx_hal_dma.h.

Referenced by I2S_DMARxCplt(), I2S_DMATxCplt(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAPeriodElapsedCplt(), and TIM_DMATriggerCplt().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

Defines

#define | DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW
#define | DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM
#define | DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH
#define | DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH

Define Documentation

#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH

Priority level : High

Definition at line 371 of file stm32g0xx_hal_dma.h.

#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW

Priority level : Low

Definition at line 369 of file stm32g0xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM

Priority level : Medium

Definition at line 370 of file stm32g0xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH

Priority level : Very_High

Definition at line 372 of file stm32g0xx_hal_dma.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

Defines

#define | DMA_IT_TC DMA_CCR_TCIE
#define | DMA_IT_HT DMA_CCR_HTIE
#define | DMA_IT_TE DMA_CCR_TEIE

Define Documentation

#define DMA_IT_HT DMA_CCR_HTIE

Half Transfer Complete interrupt

Definition at line 381 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TC DMA_CCR_TCIE

Transfer Complete interrupt

Definition at line 380 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TE DMA_CCR_TEIE

Transfer Error interrupt

Definition at line 382 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

Defines

#define | DMA_FLAG_GI1 DMA_ISR_GIF1
#define | DMA_FLAG_TC1 DMA_ISR_TCIF1
#define | DMA_FLAG_HT1 DMA_ISR_HTIF1
#define | DMA_FLAG_TE1 DMA_ISR_TEIF1
#define | DMA_FLAG_GI2 DMA_ISR_GIF2
#define | DMA_FLAG_TC2 DMA_ISR_TCIF2
#define | DMA_FLAG_HT2 DMA_ISR_HTIF2
#define | DMA_FLAG_TE2 DMA_ISR_TEIF2
#define | DMA_FLAG_GI3 DMA_ISR_GIF3
#define | DMA_FLAG_TC3 DMA_ISR_TCIF3
#define | DMA_FLAG_HT3 DMA_ISR_HTIF3
#define | DMA_FLAG_TE3 DMA_ISR_TEIF3
#define | DMA_FLAG_GI4 DMA_ISR_GIF4
#define | DMA_FLAG_TC4 DMA_ISR_TCIF4
#define | DMA_FLAG_HT4 DMA_ISR_HTIF4
#define | DMA_FLAG_TE4 DMA_ISR_TEIF4
#define | DMA_FLAG_GI5 DMA_ISR_GIF5
#define | DMA_FLAG_TC5 DMA_ISR_TCIF5
#define | DMA_FLAG_HT5 DMA_ISR_HTIF5
#define | DMA_FLAG_TE5 DMA_ISR_TEIF5
#define | DMA_FLAG_GI6 DMA_ISR_GIF6
#define | DMA_FLAG_TC6 DMA_ISR_TCIF6
#define | DMA_FLAG_HT6 DMA_ISR_HTIF6
#define | DMA_FLAG_TE6 DMA_ISR_TEIF6
#define | DMA_FLAG_GI7 DMA_ISR_GIF7
#define | DMA_FLAG_TC7 DMA_ISR_TCIF7
#define | DMA_FLAG_HT7 DMA_ISR_HTIF7
#define | DMA_FLAG_TE7 DMA_ISR_TEIF7

Define Documentation

#define DMA_FLAG_GI1 DMA_ISR_GIF1

Global Interrupt flag for Channel 1

Definition at line 391 of file stm32g0xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_GI2 DMA_ISR_GIF2

Global Interrupt flag for Channel 2

Definition at line 395 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_GI3 DMA_ISR_GIF3

Global Interrupt flag for Channel 3

Definition at line 399 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_GI4 DMA_ISR_GIF4

Global Interrupt flag for Channel 4

Definition at line 403 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_GI5 DMA_ISR_GIF5

Global Interrupt flag for Channel 5

Definition at line 407 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_GI6 DMA_ISR_GIF6

Global Interrupt flag for Channel 6

Definition at line 412 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_GI7 DMA_ISR_GIF7

Global Interrupt flag for Channel 7

Definition at line 418 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_HT1 DMA_ISR_HTIF1

Half Transfer flag for Channel 1

Definition at line 393 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HT2 DMA_ISR_HTIF2

Half Transfer flag for Channel 2

Definition at line 397 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_HT3 DMA_ISR_HTIF3

Half Transfer flag for Channel 3

Definition at line 401 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_HT4 DMA_ISR_HTIF4

Half Transfer flag for Channel 4

Definition at line 405 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_HT5 DMA_ISR_HTIF5

Half Transfer flag for Channel 5

Definition at line 409 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_HT6 DMA_ISR_HTIF6

Half Transfer flag for Channel 6

Definition at line 414 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_HT7 DMA_ISR_HTIF7

Half Transfer flag for Channel 7

Definition at line 420 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TC1 DMA_ISR_TCIF1

Transfer Complete flag for Channel 1

Definition at line 392 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TC2 DMA_ISR_TCIF2

Transfer Complete flag for Channel 2

Definition at line 396 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TC3 DMA_ISR_TCIF3

Transfer Complete flag for Channel 3

Definition at line 400 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TC4 DMA_ISR_TCIF4

Transfer Complete flag for Channel 4

Definition at line 404 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TC5 DMA_ISR_TCIF5

Transfer Complete flag for Channel 5

Definition at line 408 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TC6 DMA_ISR_TCIF6

Transfer Complete flag for Channel 6

Definition at line 413 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TC7 DMA_ISR_TCIF7

Transfer Complete flag for Channel 7

Definition at line 419 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TE1 DMA_ISR_TEIF1

Transfer Error flag for Channel 1

Definition at line 394 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TE2 DMA_ISR_TEIF2

Transfer Error flag for Channel 2

Definition at line 398 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TE3 DMA_ISR_TEIF3

Transfer Error flag for Channel 3

Definition at line 402 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TE4 DMA_ISR_TEIF4

Transfer Error flag for Channel 4

Definition at line 406 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TE5 DMA_ISR_TEIF5

Transfer Error for Channel 5

Definition at line 410 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TE6 DMA_ISR_TEIF6

Transfer Error flag for Channel 6

Definition at line 415 of file stm32g0xx_hal_dma.h.

#define DMA_FLAG_TE7 DMA_ISR_TEIF7

Transfer Error flag for Channel 7

Definition at line 421 of file stm32g0xx_hal_dma.h.

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STM32G0C1xx HAL User Manual: DMA Exported Macros

Defines
DMA Exported Macros
DMA

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Channel pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enable the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Check whether the specified DMA Channel interrupt is enabled or disabled.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Returns the number of remaining data units in the current DMA Channel transfer.

Define Documentation

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
                                                    (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))

Clear the DMA Channel pending flags.

Parameters:
__HANDLE__ DMA handle
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag
  • DMA_FLAG_GIx: Global interrupt flag Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
Return values:
None

Definition at line 644 of file stm32g0xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define __HAL_DMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)

Disable the specified DMA Channel.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 454 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

Disable the specified DMA Channel interrupts.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 672 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)

Enable the specified DMA Channel.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 447 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

Enable the specified DMA Channel interrupts.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 660 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Start_IT().

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNDTR)

Returns the number of remaining data units in the current DMA Channel transfer.

Parameters:
__HANDLE__ DMA handle
Return values:
The number of remaining data units in the current DMA Channel transfer.

Definition at line 691 of file stm32g0xx_hal_dma.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
                                                  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))

Get the DMA Channel pending flags.

Parameters:
__HANDLE__ DMA handle
__FLAG__ Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag
  • DMA_FLAG_GIx: Global interrupt flag Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 625 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

#define __HAL_DMA_GET_GI_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
   DMA_FLAG_GI7)

Return the current DMA Channel Global interrupt flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer error flag index.

Definition at line 579 of file stm32g0xx_hal_dma.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
   DMA_FLAG_HT7)

Return the current DMA Channel half transfer complete flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 501 of file stm32g0xx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

Check whether the specified DMA Channel interrupt is enabled or disabled.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
The state of DMA_IT (SET or RESET).

Definition at line 684 of file stm32g0xx_hal_dma.h.

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
   DMA_FLAG_TC7)

Return the current DMA Channel transfer complete flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 462 of file stm32g0xx_hal_dma.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
   DMA_FLAG_TE7)

Return the current DMA Channel transfer error flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer error flag index.

Definition at line 540 of file stm32g0xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 440 of file stm32g0xx_hal_dma.h.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Define Documentation

#define IS_DMA_ALL_REQUEST ( REQUEST ) ((REQUEST) <= DMA_MAX_REQUEST)

Definition at line 766 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT))

Definition at line 758 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                                 ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                                 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 754 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                                 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                                 ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 772 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                                 ((STATE) == DMA_MINC_DISABLE))

Definition at line 763 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                                                 ((MODE) == DMA_CIRCULAR))

Definition at line 776 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                                 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                                 ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 768 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                                 ((STATE) == DMA_PINC_DISABLE))

Definition at line 760 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                                 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                                 ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                                 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 779 of file stm32g0xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMAEx Extended features functions

Functions
DMAEx Extended features functions
DMAEx Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Extended features functions.

 ===============================================================================
                #####  Extended features functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:

    (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
    (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
       to respectively enable/disable the request generator.
    (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
        the DMAMUX IRQ handler

Function Documentation

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxRequestGeneratorConfigTypeDef * | pRequestGeneratorConfig
 | ) |  |

Configure the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
pRequestGeneratorConfig | Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef contains the request generator parameters.
Return values:
HAL status

Definition at line 144 of file stm32g0xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_BUSY, HAL_DMA_ERROR_PARAM, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMAMUX_REQUEST_GEN_POLARITY, IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER, IS_DMAMUX_REQUEST_GEN_SIGNAL_ID, HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity, HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber, HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxSyncConfigTypeDef * | pSyncConfig
 | ) |  |

Configure the DMAMUX synchronization parameters for a given DMA channel (instance).

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
pSyncConfig | Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization parameters
Return values:
HAL status

Definition at line 95 of file stm32g0xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_MuxSyncConfigTypeDef::EventEnable, HAL_DMA_ERROR_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMAMUX_SYNC_EVENT, IS_DMAMUX_SYNC_POLARITY, IS_DMAMUX_SYNC_REQUEST_NUMBER, IS_DMAMUX_SYNC_SIGNAL_ID, IS_DMAMUX_SYNC_STATE, HAL_DMA_MuxSyncConfigTypeDef::RequestNumber, __DMA_HandleTypeDef::State, HAL_DMA_MuxSyncConfigTypeDef::SyncEnable, HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity, and HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID.

HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Disable the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
HAL status

Definition at line 231 of file stm32g0xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Enable the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
HAL status

Definition at line 203 of file stm32g0xx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

void HAL_DMAEx_MUX_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMAMUX interrupt request.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
None

Definition at line 259 of file stm32g0xx_hal_dma_ex.c.

References __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, and __DMA_HandleTypeDef::XferErrorCallback.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL_DMA_MuxSyncConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxSyncConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMAMUX Synchronization configuration structure definition. More...

#include <stm32g0xx_hal_dma_ex.h>

Data Fields

uint32_t | SyncSignalID
uint32_t | SyncPolarity
FunctionalState | SyncEnable
FunctionalState | EventEnable
uint32_t | RequestNumber

Detailed Description

HAL DMAMUX Synchronization configuration structure definition.

Definition at line 47 of file stm32g0xx_hal_dma_ex.h.

Field Documentation

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::EventEnable

Specifies if an event shall be generated once the RequestNumber is reached. This parameter can take the value ENABLE or DISABLE

Definition at line 58 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be authorized after a sync event This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 61 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::SyncEnable

Specifies if the synchronization shall be enabled or disabled This parameter can take the value ENABLE or DISABLE

Definition at line 55 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity

Specifies the polarity of the signal on which the DMA request is synchronized. This parameter can be a value of DMAMUX SyncPolarity selection

Definition at line 52 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID

Specifies the synchronization signal gating the DMA request in periodic mode. This parameter can be a value of DMAMUX SyncSignalID selection

Definition at line 49 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_dma_ex.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMAMUX request generator parameters structure definition. More...

#include <stm32g0xx_hal_dma_ex.h>

Data Fields

uint32_t | SignalID
uint32_t | Polarity
uint32_t | RequestNumber

Detailed Description

HAL DMAMUX request generator parameters structure definition.

Definition at line 71 of file stm32g0xx_hal_dma_ex.h.

Field Documentation

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity

Specifies the polarity of the signal on which the request is generated. This parameter can be a value of DMAMUX RequestGeneneratorPolarity selection

Definition at line 76 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be generated after a signal event This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 79 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID

Specifies the ID of the signal used for DMAMUX request generator This parameter can be a value of DMAMUX SignalGeneratorID selection

Definition at line 73 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_dma_ex.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMAMUX SyncSignalID selection

Defines
DMAMUX SyncSignalID selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0
#define | HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1
#define | HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2
#define | HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3
#define | HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4
#define | HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5
#define | HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6
#define | HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7
#define | HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8
#define | HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9
#define | HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10
#define | HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11
#define | HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12
#define | HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13
#define | HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14
#define | HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT LL_DMAMUX_SYNC_DMAMUX_CH2
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT
#define | HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT
#define | HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC
#define | HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC

Define Documentation

#define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC

Definition at line 124 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0

Synchronization signal from DMAMUX channel0 Event

Definition at line 112 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1

Synchronization signal from DMAMUX channel1 Event

Definition at line 113 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT LL_DMAMUX_SYNC_DMAMUX_CH2

Synchronization signal from DMAMUX channel2 Event

Definition at line 114 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3

Synchronization signal from DMAMUX channel3 Event

Definition at line 115 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0

Synchronization signal from EXTI Line0

Definition at line 96 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1

Synchronization signal from EXTI Line1

Definition at line 97 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10

Synchronization signal from EXTI Line10

Definition at line 106 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11

Synchronization signal from EXTI Line11

Definition at line 107 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12

Synchronization signal from EXTI Line12

Definition at line 108 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13

Synchronization signal from EXTI Line1 3

Definition at line 109 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14

Synchronization signal from EXTI Line1 4

Definition at line 110 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15

Synchronization signal from EXTI Line1 5

Definition at line 111 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2

Synchronization signal from EXTI Line2

Definition at line 98 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3

Synchronization signal from EXTI Line3

Definition at line 99 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4

Synchronization signal from EXTI Line4

Definition at line 100 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5

Synchronization signal from EXTI Line5

Definition at line 101 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6

Synchronization signal from EXTI Line6

Definition at line 102 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7

Synchronization signal from EXTI Line7

Definition at line 103 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8

Synchronization signal from EXTI Line8

Definition at line 104 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9

Synchronization signal from EXTI Line9

Definition at line 105 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT

Synchronization signal from LPTIM1 Output

Definition at line 117 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT

Synchronization signal from LPTIM2 Output

Definition at line 120 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC

Synchronization signal from TIM14 OC

Definition at line 122 of file stm32g0xx_hal_dma_ex.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMAMUX SyncPolarity selection

Defines
DMAMUX SyncPolarity selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT
#define | HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING
#define | HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING
#define | HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING

Define Documentation

#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING

synchronize with falling edge events

Definition at line 134 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT

block synchronization events

Definition at line 132 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING

synchronize with rising edge events

Definition at line 133 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING

synchronize with rising and falling edge events

Definition at line 135 of file stm32g0xx_hal_dma_ex.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMAMUX SignalGeneratorID selection

Defines
DMAMUX SignalGeneratorID selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0
#define | HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1
#define | HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2
#define | HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3
#define | HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4
#define | HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5
#define | HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6
#define | HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7
#define | HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8
#define | HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9
#define | HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10
#define | HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11
#define | HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12
#define | HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13
#define | HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14
#define | HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH2
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3
#define | HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT
#define | HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT
#define | HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC
#define | HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC

Define Documentation

#define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC

Definition at line 172 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0

Request signal generation from DMAMUX channel0 Event

Definition at line 160 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1

Request signal generation from DMAMUX channel1 Event

Definition at line 161 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH2

Request signal generation from DMAMUX channel2 Event

Definition at line 162 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3

Request signal generation from DMAMUX channel3 Event

Definition at line 163 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0

Request signal generation from EXTI Line0

Definition at line 144 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1

Request signal generation from EXTI Line1

Definition at line 145 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10

Request signal generation from EXTI Line10

Definition at line 154 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11

Request signal generation from EXTI Line11

Definition at line 155 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12

Request signal generation from EXTI Line12

Definition at line 156 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13

Request signal generation from EXTI Line13

Definition at line 157 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14

Request signal generation from EXTI Line14

Definition at line 158 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15

Request signal generation from EXTI Line15

Definition at line 159 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2

Request signal generation from EXTI Line2

Definition at line 146 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3

Request signal generation from EXTI Line3

Definition at line 147 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4

Request signal generation from EXTI Line4

Definition at line 148 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5

Request signal generation from EXTI Line5

Definition at line 149 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6

Request signal generation from EXTI Line6

Definition at line 150 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7

Request signal generation from EXTI Line7

Definition at line 151 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8

Request signal generation from EXTI Line8

Definition at line 152 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9

Request signal generation from EXTI Line9

Definition at line 153 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT

Request signal generation from LPTIM1 Output

Definition at line 165 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT

Request signal generation from LPTIM2 Output

Definition at line 168 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC

Request signal generation from TIM14 OC

Definition at line 170 of file stm32g0xx_hal_dma_ex.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMAMUX RequestGeneneratorPolarity selection

Defines
DMAMUX RequestGeneneratorPolarity selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT
#define | HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING
#define | HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING
#define | HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

Define Documentation

#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING

generate request on falling edge events

Definition at line 182 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT

block request generator events

Definition at line 180 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING

generate request on rising edge events

Definition at line 181 of file stm32g0xx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

generate request on rising and falling edge events

Definition at line 183 of file stm32g0xx_hal_dma_ex.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMAEx Private Macros

Defines
DMAEx Private Macros
DMAEx

DMAEx private macros. More...

Defines

#define | IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Detailed Description

DMAEx private macros.

Define Documentation

#define IS_DMAMUX_REQUEST_GEN_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \
                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \
                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))

Definition at line 255 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

Definition at line 253 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID ( SIGNAL_ID )
Value:
(((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \
                                                         (((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \
                                                          ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN)))

Definition at line 249 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_SYNC_EVENT ( EVENT )
Value:
(((EVENT) == DISABLE)   || \
                                                         ((EVENT) == ENABLE))

Definition at line 246 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
                                                         ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
                                                         ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
                                                         ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))

Definition at line 239 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

Definition at line 237 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_SIGNAL_ID ( SIGNAL_ID )
Value:
(((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \
                                                         (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \
                                                          ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC)))

Definition at line 233 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_STATE ( SYNC ) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))

Definition at line 244 of file stm32g0xx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI Private Constants

Defines
EXTI Private Constants
EXTI

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine. More...

Defines

#define | EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
#define | EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
#define | EXTI_PROPERTY_SHIFT 24u
EXTI Line property definition.
#define | EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define | EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
#define | EXTI_REG_SHIFT 16u
EXTI Register and bit usage.
#define | EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define | EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define | EXTI_PIN_MASK 0x0000001Fu
#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
EXTI Mask for interrupt & event mode.
#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
EXTI Mask for trigger possibilities.
#define | EXTI_LINE_NB 37uL
EXTI Line number.

Detailed Description

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine.

Define Documentation

#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)

Definition at line 248 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */

Definition at line 111 of file stm32g0xx_hal_exti.c.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)

Definition at line 247 of file stm32g0xx_hal_exti.h.

#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)

Definition at line 249 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_LINE_NB 37uL

EXTI Line number.

Definition at line 276 of file stm32g0xx_hal_exti.h.

#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)

EXTI Mask for interrupt & event mode.

Definition at line 265 of file stm32g0xx_hal_exti.h.

#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */

Definition at line 110 of file stm32g0xx_hal_exti.c.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_PIN_MASK 0x0000001Fu

Definition at line 260 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)

Definition at line 251 of file stm32g0xx_hal_exti.h.

#define EXTI_PROPERTY_SHIFT 24u

EXTI Line property definition.

Definition at line 246 of file stm32g0xx_hal_exti.h.

#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)

Definition at line 257 of file stm32g0xx_hal_exti.h.

#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)

Definition at line 258 of file stm32g0xx_hal_exti.h.

#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)

Definition at line 259 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_REG_SHIFT 16u

EXTI Register and bit usage.

Definition at line 256 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)

Definition at line 250 of file stm32g0xx_hal_exti.h.

#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

EXTI Mask for trigger possibilities.

Definition at line 270 of file stm32g0xx_hal_exti.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI Exported Types

Data Structures | Enumerations
EXTI Exported Types
EXTI

Data Structures

struct | EXTI_HandleTypeDef
EXTI Handle structure definition. More...
struct | EXTI_ConfigTypeDef
EXTI Configuration structure definition. More...

Enumerations

enum | EXTI_CallbackIDTypeDef { HAL_EXTI_COMMON_CB_ID = 0x00U, HAL_EXTI_RISING_CB_ID = 0x01U, HAL_EXTI_FALLING_CB_ID = 0x02U }

Enumeration Type Documentation

enum EXTI_CallbackIDTypeDef
Enumerator:
HAL_EXTI_COMMON_CB_ID
HAL_EXTI_RISING_CB_ID
HAL_EXTI_FALLING_CB_ID

Definition at line 44 of file stm32g0xx_hal_exti.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
EXTI_HandleTypeDef Struct Reference
EXTI Exported Types

EXTI Handle structure definition. More...

#include <stm32g0xx_hal_exti.h>

Data Fields

uint32_t | Line
void(* | RisingCallback )(void)
void(* | FallingCallback )(void)

Detailed Description

EXTI Handle structure definition.

Definition at line 55 of file stm32g0xx_hal_exti.h.

Field Documentation

void(* EXTI_HandleTypeDef::FallingCallback)(void)

Exti falling callback

Definition at line 59 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_IRQHandler(), and HAL_EXTI_RegisterCallback().

uint32_t EXTI_HandleTypeDef::Line

Exti line number

Definition at line 57 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

void(* EXTI_HandleTypeDef::RisingCallback)(void)

Exti rising callback

Definition at line 58 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_IRQHandler(), and HAL_EXTI_RegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_exti.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
EXTI_ConfigTypeDef Struct Reference
EXTI Exported Types

EXTI Configuration structure definition. More...

#include <stm32g0xx_hal_exti.h>

Data Fields

uint32_t | Line
uint32_t | Mode
uint32_t | Trigger
uint32_t | GPIOSel

Detailed Description

EXTI Configuration structure definition.

Definition at line 65 of file stm32g0xx_hal_exti.h.

Field Documentation

uint32_t EXTI_ConfigTypeDef::GPIOSel

The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of EXTI GPIOSel

Definition at line 73 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Line

The Exti line to be configured. This parameter can be a value of EXTI Line

Definition at line 67 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Mode

The Exit Mode to be configured for a core. This parameter can be a combination of EXTI Mode

Definition at line 69 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Trigger

The Exti Trigger to be configured. This parameter can be a value of EXTI Trigger

Definition at line 71 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_exti.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI Line

Defines
EXTI Line
EXTI Exported Constants

Defines

#define | EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
#define | EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
#define | EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
#define | EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
#define | EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
#define | EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
#define | EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
#define | EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
#define | EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
#define | EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
#define | EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
#define | EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
#define | EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
#define | EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
#define | EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
#define | EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
#define | EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
#define | EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
#define | EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u)
#define | EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13u)
#define | EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
#define | EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u)
#define | EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
#define | EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#define | EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#define | EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#define | EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
#define | EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
#define | EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#define | EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
#define | EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
#define | EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu)
#define | EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u)
#define | EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u)
#define | EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u)
#define | EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
#define | EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)

Define Documentation

#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)

Definition at line 90 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)

Definition at line 91 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)

Definition at line 100 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)

Definition at line 101 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)

Definition at line 102 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)

Definition at line 103 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)

Definition at line 104 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)

Definition at line 105 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)

Definition at line 106 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)

Definition at line 108 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u)

Definition at line 113 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13u)

Definition at line 117 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)

Definition at line 92 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)

Definition at line 119 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u)

Definition at line 123 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)

Definition at line 125 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)

Definition at line 129 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)

Definition at line 131 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)

Definition at line 135 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)

Definition at line 137 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)

Definition at line 142 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)

Definition at line 147 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)

Definition at line 152 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)

Definition at line 93 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)

Definition at line 157 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu)

Definition at line 161 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u)

Definition at line 163 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u)

Definition at line 168 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u)

Definition at line 173 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)

Definition at line 178 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)

Definition at line 183 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)

Definition at line 94 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)

Definition at line 95 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)

Definition at line 96 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)

Definition at line 97 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)

Definition at line 98 of file stm32g0xx_hal_exti.h.

#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)

Definition at line 99 of file stm32g0xx_hal_exti.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI Mode

Defines
EXTI Mode
EXTI Exported Constants

Defines

#define | EXTI_MODE_NONE 0x00000000u
#define | EXTI_MODE_INTERRUPT 0x00000001u
#define | EXTI_MODE_EVENT 0x00000002u

Define Documentation

#define EXTI_MODE_EVENT 0x00000002u

Definition at line 194 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_MODE_INTERRUPT 0x00000001u

Definition at line 193 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_MODE_NONE 0x00000000u

Definition at line 192 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI Trigger

Defines
EXTI Trigger
EXTI Exported Constants

Defines

#define | EXTI_TRIGGER_NONE 0x00000000u
#define | EXTI_TRIGGER_RISING 0x00000001u
#define | EXTI_TRIGGER_FALLING 0x00000002u
#define | EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

Define Documentation

#define EXTI_TRIGGER_FALLING 0x00000002u

Definition at line 204 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TRIGGER_NONE 0x00000000u

Definition at line 202 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine().

#define EXTI_TRIGGER_RISING 0x00000001u

Definition at line 203 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearPending(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), and HAL_EXTI_SetConfigLine().

#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

Definition at line 205 of file stm32g0xx_hal_exti.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI GPIOSel

Defines
EXTI GPIOSel
EXTI Exported Constants

Defines

#define | EXTI_GPIOA 0x00000000u
#define | EXTI_GPIOB 0x00000001u
#define | EXTI_GPIOC 0x00000002u
#define | EXTI_GPIOD 0x00000003u
#define | EXTI_GPIOE 0x00000004u
#define | EXTI_GPIOF 0x00000005u

Define Documentation

#define EXTI_GPIOA 0x00000000u

Definition at line 214 of file stm32g0xx_hal_exti.h.

#define EXTI_GPIOB 0x00000001u

Definition at line 215 of file stm32g0xx_hal_exti.h.

#define EXTI_GPIOC 0x00000002u

Definition at line 216 of file stm32g0xx_hal_exti.h.

#define EXTI_GPIOD 0x00000003u

Definition at line 217 of file stm32g0xx_hal_exti.h.

#define EXTI_GPIOE 0x00000004u

Definition at line 219 of file stm32g0xx_hal_exti.h.

#define EXTI_GPIOF 0x00000005u

Definition at line 221 of file stm32g0xx_hal_exti.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI Exported Macros

EXTI Exported Macros
EXTI
Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_EXTI_LINE(__EXTI_LINE__)
#define | IS_EXTI_MODE(__MODE__)
#define | IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define | IS_EXTI_PENDING_EDGE(__EXTI_LINE__)
#define | IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#define | IS_EXTI_GPIO_PORT(__PORT__)
#define | IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)

Define Documentation

#define IS_EXTI_CONFIG_LINE ( __EXTI_LINE__ ) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)

Definition at line 312 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), and HAL_EXTI_GetPending().

#define IS_EXTI_GPIO_PIN ( __PIN__ ) ((__PIN__) < 16u)

Definition at line 329 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define IS_EXTI_GPIO_PORT ( __PORT__ )
Value:
(((__PORT__) == EXTI_GPIOA) || \
                                         ((__PORT__) == EXTI_GPIOB) || \
                                         ((__PORT__) == EXTI_GPIOC) || \
                                         ((__PORT__) == EXTI_GPIOD) || \
                                         ((__PORT__) == EXTI_GPIOE) || \
                                         ((__PORT__) == EXTI_GPIOF))

Definition at line 315 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_LINE ( __EXTI_LINE__ )
Value:
((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
                                        ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
                                         (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
                                         (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
                                         (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
                                         (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))

Definition at line 297 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), and HAL_EXTI_SetConfigLine().

#define IS_EXTI_MODE ( __MODE__ )
Value:
((((__MODE__) & EXTI_MODE_MASK) != 0x00u) && \
                                         (((__MODE__) & ~EXTI_MODE_MASK) == 0x00u))

Definition at line 304 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_PENDING_EDGE ( __EXTI_LINE__ )
Value:
(((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
                                              ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING))

Definition at line 309 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_ClearPending(), and HAL_EXTI_GetPending().

#define IS_EXTI_TRIGGER ( __EXTI_LINE__ ) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)

Definition at line 307 of file stm32g0xx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions

Functions
Configuration functions
EXTI Exported Functions

Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicaated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.

Detailed Description

Configuration functions.

 ===============================================================================
              ##### Configuration functions #####
 ===============================================================================

Function Documentation

HAL_StatusTypeDef HAL_EXTI_ClearConfigLine ( EXTI_HandleTypeDef * hexti )

Clear whole configuration of a dedicated Exti line.

Parameters:
hexti Exti handle.
Return values:
HAL Status.

Definition at line 359 of file stm32g0xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_GPIO_PIN, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

HAL_StatusTypeDef HAL_EXTI_GetConfigLine | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_ConfigTypeDef * | pExtiConfig
 | ) |  |

Get configuration of a dedicated Exti line.

Parameters:
hexti | Exti handle.
pExtiConfig | Pointer on structure to store Exti configuration.
Return values:
HAL Status.

Definition at line 265 of file stm32g0xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_EVENT, EXTI_MODE_INTERRUPT, EXTI_MODE_NONE, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_NONE, EXTI_TRIGGER_RISING, EXTI_ConfigTypeDef::GPIOSel, IS_EXTI_GPIO_PIN, IS_EXTI_LINE, EXTI_HandleTypeDef::Line, EXTI_ConfigTypeDef::Line, EXTI_ConfigTypeDef::Mode, and EXTI_ConfigTypeDef::Trigger.

HAL_StatusTypeDef HAL_EXTI_GetHandle | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | ExtiLine
 | ) |  |

Store line number as handle private field.

Parameters:
hexti | Exti handle.
ExtiLine | Exti line number. This parameter can be from 0 to EXTI_LINE_NB.
Return values:
HAL Status.

Definition at line 460 of file stm32g0xx_hal_exti.c.

References assert_param, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

HAL_StatusTypeDef HAL_EXTI_RegisterCallback | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_CallbackIDTypeDef | CallbackID,
 |  | void(*)(void) | pPendingCbfn
 | ) |  |

Register callback for a dedicaated Exti line.

Parameters:
hexti | Exti handle.
CallbackID User callback identifier. This parameter can be one of
  • EXTI_CallbackIDTypeDef values.
pPendingCbfn | function pointer to be stored as callback.
Return values:
HAL Status.

Definition at line 425 of file stm32g0xx_hal_exti.c.

References EXTI_HandleTypeDef::FallingCallback, HAL_EXTI_COMMON_CB_ID, HAL_EXTI_FALLING_CB_ID, HAL_EXTI_RISING_CB_ID, and EXTI_HandleTypeDef::RisingCallback.

HAL_StatusTypeDef HAL_EXTI_SetConfigLine | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_ConfigTypeDef * | pExtiConfig
 | ) |  |

Set configuration of a dedicated Exti line.

Parameters:
hexti | Exti handle.
pExtiConfig | Pointer on EXTI configuration to be set.
Return values:
HAL Status.

Definition at line 143 of file stm32g0xx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_EVENT, EXTI_MODE_INTERRUPT, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_RISING, EXTI_ConfigTypeDef::GPIOSel, IS_EXTI_GPIO_PIN, IS_EXTI_GPIO_PORT, IS_EXTI_LINE, IS_EXTI_MODE, IS_EXTI_TRIGGER, EXTI_HandleTypeDef::Line, EXTI_ConfigTypeDef::Line, EXTI_ConfigTypeDef::Mode, and EXTI_ConfigTypeDef::Trigger.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
EXTI Exported Functions

IO operation functions. More...

Functions

void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

IO operation functions.

EXTI IO functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_EXTI_ClearPending | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | Edge
 | ) |  |

Clear interrupt pending bit of a dedicated line.

Parameters:
hexti Exti handle.
Edge Specify which pending edge as to be clear. This parameter can be one of the following values:
  • EXTI_TRIGGER_RISING
  • EXTI_TRIGGER_FALLING
Return values:
None.

Definition at line 599 of file stm32g0xx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TRIGGER_RISING, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, IS_EXTI_PENDING_EDGE, and EXTI_HandleTypeDef::Line.

void HAL_EXTI_GenerateSWI ( EXTI_HandleTypeDef * hexti )

Generate a software interrupt for a dedicated line.

Parameters:
hexti Exti handle.
Return values:
None.

Definition at line 635 of file stm32g0xx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

uint32_t HAL_EXTI_GetPending | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | Edge
 | ) |  |

Get interrupt pending bit of a dedicated line.

Parameters:
hexti Exti handle.
Edge Specify which pending edge as to be checked. This parameter can be one of the following values:
  • EXTI_TRIGGER_RISING
  • EXTI_TRIGGER_FALLING
Return values:
1 if interrupt is pending else 0.

Definition at line 555 of file stm32g0xx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TRIGGER_RISING, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, IS_EXTI_PENDING_EDGE, and EXTI_HandleTypeDef::Line.

void HAL_EXTI_IRQHandler ( EXTI_HandleTypeDef * hexti )

Handle EXTI interrupt request.

Parameters:
hexti Exti handle.
Return values:
none.

Definition at line 501 of file stm32g0xx_hal_exti.c.

References EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_HandleTypeDef::FallingCallback, EXTI_HandleTypeDef::Line, and EXTI_HandleTypeDef::RisingCallback.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
FDCAN Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void(*pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
Register a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback)

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the FDCAN.
      (+) De-initialize the FDCAN.
      (+) Enter FDCAN peripheral in power down mode.
      (+) Exit power down mode.
      (+) Register callbacks.
      (+) Unregister callbacks.

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_DeInit ( FDCAN_HandleTypeDef * hfdcan )

Deinitializes the FDCAN peripheral registers to their default reset values.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 531 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_MspDeInit(), HAL_FDCAN_STATE_RESET, HAL_FDCAN_Stop(), __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::MspDeInitCallback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode ( FDCAN_HandleTypeDef * hfdcan )

Enter FDCAN peripheral in sleep mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 607 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_GetTick(), __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode ( FDCAN_HandleTypeDef * hfdcan )

Exit power down mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 642 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_ERROR, HAL_GetTick(), __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_Init ( FDCAN_HandleTypeDef * hfdcan )

Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 283 of file stm32g0xx_hal_fdcan.c.

References assert_param, FDCAN_InitTypeDef::AutoRetransmission, FDCAN_InitTypeDef::ClockDivider, FDCAN_InitTypeDef::DataPrescaler, FDCAN_InitTypeDef::DataSyncJumpWidth, FDCAN_InitTypeDef::DataTimeSeg1, FDCAN_InitTypeDef::DataTimeSeg2, __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_CalcultateRamBlockAddresses(), FDCAN_FRAME_FD_BRS, FDCAN_MODE_BUS_MONITORING, FDCAN_MODE_INTERNAL_LOOPBACK, FDCAN_MODE_NORMAL, FDCAN_MODE_RESTRICTED_OPERATION, FDCAN_TIMEOUT_VALUE, FDCAN_InitTypeDef::FrameFormat, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_MspInit(), HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TxBufferAbortCallback(), HAL_FDCAN_TxBufferCompleteCallback(), HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxFifoEmptyCallback(), HAL_GetTick(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::Init, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_CKDIV, IS_FDCAN_DATA_PRESCALER, IS_FDCAN_DATA_SJW, IS_FDCAN_DATA_TSEG1, IS_FDCAN_DATA_TSEG2, IS_FDCAN_FRAME_FORMAT, IS_FDCAN_MAX_VALUE, IS_FDCAN_MODE, IS_FDCAN_NOMINAL_PRESCALER, IS_FDCAN_NOMINAL_SJW, IS_FDCAN_NOMINAL_TSEG1, IS_FDCAN_NOMINAL_TSEG2, IS_FDCAN_TX_FIFO_QUEUE_MODE, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, __FDCAN_HandleTypeDef::Lock, FDCAN_InitTypeDef::Mode, __FDCAN_HandleTypeDef::MspInitCallback, FDCAN_InitTypeDef::NominalPrescaler, FDCAN_InitTypeDef::NominalSyncJumpWidth, FDCAN_InitTypeDef::NominalTimeSeg1, FDCAN_InitTypeDef::NominalTimeSeg2, FDCAN_InitTypeDef::ProtocolException, __FDCAN_HandleTypeDef::RxFifo0Callback, __FDCAN_HandleTypeDef::RxFifo1Callback, SRAMCAN_FLE_NBR, SRAMCAN_FLS_NBR, __FDCAN_HandleTypeDef::State, FDCAN_InitTypeDef::StdFiltersNbr, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, FDCAN_InitTypeDef::TransmitPause, __FDCAN_HandleTypeDef::TxBufferAbortCallback, __FDCAN_HandleTypeDef::TxBufferCompleteCallback, __FDCAN_HandleTypeDef::TxEventFifoCallback, __FDCAN_HandleTypeDef::TxFifoEmptyCallback, and FDCAN_InitTypeDef::TxFifoQueueMode.

void HAL_FDCAN_MspDeInit ( FDCAN_HandleTypeDef * hfdcan )

DeInitializes the FDCAN MSP.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 592 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_DeInit(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_MspInit ( FDCAN_HandleTypeDef * hfdcan )

Initializes the FDCAN MSP.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 577 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), and HAL_FDCAN_UnRegisterCallback().

HAL_StatusTypeDef HAL_FDCAN_RegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID,
 |  | void(*)(FDCAN_HandleTypeDef *_hFDCAN) | pCallback
 | ) |  |

Register a FDCAN CallBack.

To be used instead of the weak predefined callback

Parameters:
hfdcan | pointer to a FDCAN_HandleTypeDef structure that contains the configuration information for FDCAN module
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
  • HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
  • HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 692 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_CALLBACK_CB_ID, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID, HAL_FDCAN_MSPDEINIT_CB_ID, HAL_FDCAN_MSPINIT_CB_ID, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID, HAL_FDCAN_TX_FIFO_EMPTY_CB_ID, __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::MspDeInitCallback, __FDCAN_HandleTypeDef::MspInitCallback, __FDCAN_HandleTypeDef::State, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID,
 |  | pFDCAN_CallbackTypeDef | pCallback
 | ) |  |
HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_ErrorStatusCallbackTypeDef | pCallback
 | ) |  |

Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Error Status Callback function
Return values:
HAL status

Definition at line 1187 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_RxFifo0CallbackTypeDef | pCallback
 | ) |  |

Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Rx Fifo 0 Callback function
Return values:
HAL status

Definition at line 941 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo0Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_RxFifo1CallbackTypeDef | pCallback
 | ) |  |

Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Rx Fifo 1 Callback function
Return values:
HAL status

Definition at line 1002 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo1Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxBufferAbortCallbackTypeDef | pCallback
 | ) |  |

Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Buffer Abort Callback function
Return values:
HAL status

Definition at line 1125 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferAbortCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxBufferCompleteCallbackTypeDef | pCallback
 | ) |  |

Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Buffer Complete Callback function
Return values:
HAL status

Definition at line 1063 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferCompleteCallback.

HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | pFDCAN_TxEventFifoCallbackTypeDef | pCallback
 | ) |  |

Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.

Parameters:
hfdcan | FDCAN handle
pCallback | pointer to the Tx Event Fifo Callback function
Return values:
HAL status

Definition at line 880 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxEventFifoCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | HAL_FDCAN_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a FDCAN CallBack.

FDCAN callback is redirected to the weak predefined callback

Parameters:
hfdcan pointer to a FDCAN_HandleTypeDef structure that contains the configuration information for FDCAN module
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
  • HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
  • HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 795 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_CALLBACK_CB_ID, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID, HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_MspDeInit(), HAL_FDCAN_MSPDEINIT_CB_ID, HAL_FDCAN_MspInit(), HAL_FDCAN_MSPINIT_CB_ID, HAL_FDCAN_STATE_READY, HAL_FDCAN_STATE_RESET, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID, HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID, HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TX_FIFO_EMPTY_CB_ID, HAL_FDCAN_TxFifoEmptyCallback(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::MspDeInitCallback, __FDCAN_HandleTypeDef::MspInitCallback, __FDCAN_HandleTypeDef::State, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1221 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_STATE_READY, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 975 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo0Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1036 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::RxFifo1Callback, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1160 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxBufferAbortCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferAbortCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 1098 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxBufferCompleteCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxBufferCompleteCallback.

HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback ( FDCAN_HandleTypeDef * hfdcan )

UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.

Parameters:
hfdcan FDCAN handle
Return values:
HAL status

Definition at line 914 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_INVALID_CALLBACK, HAL_FDCAN_STATE_READY, HAL_FDCAN_TxEventFifoCallback(), __FDCAN_HandleTypeDef::State, and __FDCAN_HandleTypeDef::TxEventFifoCallback.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions

Functions
Configuration functions
FDCAN Exported Functions

FDCAN Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.

Detailed Description

FDCAN Configuration functions.

  ==============================================================================
              ##### Configuration functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | Mask
 | ) |  |

Configure the extended ID mask.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Mask | Extended ID Mask. This parameter must be a number between 0 and 0x1FFFFFFF
Return values:
HAL status

Definition at line 1419 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigFilter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_FilterTypeDef * | sFilterConfig
 | ) |  |

Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
sFilterConfig | pointer to an FDCAN_FilterTypeDef structure that contains the filter configuration information
Return values:
HAL status

Definition at line 1291 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA, FDCAN_InitTypeDef::ExtFiltersNbr, FDCAN_STANDARD_ID, FDCAN_FilterTypeDef::FilterConfig, FDCAN_FilterTypeDef::FilterID1, FDCAN_FilterTypeDef::FilterID2, FDCAN_FilterTypeDef::FilterIndex, FDCAN_FilterTypeDef::FilterType, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, FDCAN_FilterTypeDef::IdType, __FDCAN_HandleTypeDef::Init, IS_FDCAN_EXT_FILTER_TYPE, IS_FDCAN_FILTER_CFG, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, IS_FDCAN_STD_FILTER_TYPE, __FDCAN_HandleTypeDef::msgRam, SRAMCAN_FLE_SIZE, SRAMCAN_FLS_SIZE, FDCAN_MsgRamAddressTypeDef::StandardFilterSA, __FDCAN_HandleTypeDef::State, and FDCAN_InitTypeDef::StdFiltersNbr.

HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | NonMatchingStd,
 |  | uint32_t | NonMatchingExt,
 |  | uint32_t | RejectRemoteStd,
 |  | uint32_t | RejectRemoteExt
 | ) |  |

Configure the FDCAN global filter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
NonMatchingStd Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. This parameter can be a value of
  • FDCAN_Non_Matching_Frames.
NonMatchingExt Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. This parameter can be a value of
  • FDCAN_Non_Matching_Frames.
RejectRemoteStd Filter or reject all the remote 11-bit IDs frames. This parameter can be a value of
  • FDCAN_Reject_Remote_Frames.
RejectRemoteExt Filter or reject all the remote 29-bit IDs frames. This parameter can be a value of
  • FDCAN_Reject_Remote_Frames.
Return values:
HAL status

Definition at line 1375 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_NON_MATCHING, IS_FDCAN_REJECT_REMOTE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | CounterStartValue
 | ) |  |

Configure the RAM watchdog.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
CounterStartValue | Start value of the Message RAM Watchdog Counter, This parameter must be a number between 0x00 and 0xFF, with the reset value of 0x00 the counter is disabled.
Return values:
HAL status

Definition at line 1493 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo,
 |  | uint32_t | OperationMode
 | ) |  |

Configure the Rx FIFO operation mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo Rx FIFO. This parameter can be one of the following values:
  • FDCAN_RX_FIFO0: Rx FIFO 0
  • FDCAN_RX_FIFO1: Rx FIFO 1
OperationMode operation mode. This parameter can be a value of
  • FDCAN_Rx_FIFO_operation_mode.
Return values:
HAL status

Definition at line 1453 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_RX_FIFO0, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_RX_FIFO, IS_FDCAN_RX_FIFO_MODE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimeoutOperation,
 |  | uint32_t | TimeoutPeriod
 | ) |  |

Configure the timeout counter.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimeoutOperation Timeout counter operation. This parameter can be a value of
  • FDCAN_Timeout_Operation.
TimeoutPeriod | Start value of the timeout down-counter. This parameter must be a number between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 1648 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, IS_FDCAN_TIMEOUT, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimestampPrescaler
 | ) |  |

Configure the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimestampPrescaler Timestamp Counter Prescaler. This parameter can be a value of
  • FDCAN_Timestamp_Prescaler.
Return values:
HAL status

Definition at line 1523 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TIMESTAMP_PRESCALER, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TdcOffset,
 |  | uint32_t | TdcFilter
 | ) |  |

Configure the transmitter delay compensation.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TdcOffset | Transmitter Delay Compensation Offset. This parameter must be a number between 0x00 and 0x7F.
TdcFilter | Transmitter Delay Compensation Filter Window Length. This parameter must be a number between 0x00 and 0x7F.
Return values:
HAL status

Definition at line 1770 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_MAX_VALUE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering ( FDCAN_HandleTypeDef * hfdcan )

Disable edge filtering during bus integration.

One dominant tq is required to detect an edge for hard synchronization.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1929 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableISOMode ( FDCAN_HandleTypeDef * hfdcan )

Disable ISO 11898-1 protocol mode.

CAN FD frame format is according to Bosch CAN FD specification V1.0.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1877 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Disable the timeout counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1704 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Disable the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1581 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation ( FDCAN_HandleTypeDef * hfdcan )

Disable the transmitter delay compensation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1825 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering ( FDCAN_HandleTypeDef * hfdcan )

Enable edge filtering during bus integration.

Two consecutive dominant tq are required to detect an edge for hard synchronization.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1903 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableISOMode ( FDCAN_HandleTypeDef * hfdcan )

Enable ISO 11898-1 protocol mode.

CAN FD frame format is according to ISO 11898-1 standard.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1851 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Enable the timeout counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1679 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TimestampOperation
 | ) |  |

Enable the timestamp counter.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TimestampOperation Timestamp counter operation. This parameter can be a value of
  • FDCAN_Timestamp.
Return values:
HAL status

Definition at line 1553 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TIMESTAMP, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation ( FDCAN_HandleTypeDef * hfdcan )

Enable the transmitter delay compensation.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1800 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

uint16_t HAL_FDCAN_GetTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Get the timeout counter value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Timeout counter value

Definition at line 1729 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint16_t HAL_FDCAN_GetTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Get the timestamp counter value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Timestamp counter value

Definition at line 1606 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter ( FDCAN_HandleTypeDef * hfdcan )

Reset the timeout counter to its start value.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1740 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_CONTINUOUS, HAL_FDCAN_ERROR_NOT_SUPPORTED, and __FDCAN_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter ( FDCAN_HandleTypeDef * hfdcan )

Reset the timestamp counter to zero.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1617 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMESTAMP_EXTERNAL, HAL_FDCAN_ERROR_NOT_SUPPORTED, and __FDCAN_HandleTypeDef::Instance.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Control functions

Functions
Control functions
FDCAN Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.

Detailed Description

Control functions.

  ==============================================================================
                          ##### Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_Start                         : Start the FDCAN module
      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding
                                                    transmission request
      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx FIFO zone into the message RAM
      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone
                                                    into the message RAM
      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending
                                                    on the selected Tx buffer
      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndex
 | ) |  |

Abort transmission request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndex buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
HAL status

Definition at line 2184 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_TX_LOCATION_LIST, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | uint8_t * | pTxData
 | ) |  |

Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader | pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData | pointer to a buffer containing the payload of the Tx frame.
Return values:
HAL status

Definition at line 2102 of file stm32g0xx_hal_fdcan.c.

References assert_param, FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_CopyMessageToRAM(), FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, HAL_FDCAN_ERROR_FIFO_FULL, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_BRS, IS_FDCAN_DLC, IS_FDCAN_EFC, IS_FDCAN_ESI, IS_FDCAN_FDF, IS_FDCAN_FRAME_TYPE, IS_FDCAN_ID_TYPE, IS_FDCAN_MAX_VALUE, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, FDCAN_TxHeaderTypeDef::MessageMarker, __FDCAN_HandleTypeDef::State, FDCAN_TxHeaderTypeDef::TxEventFifoControl, and FDCAN_TxHeaderTypeDef::TxFrameType.

HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode ( FDCAN_HandleTypeDef * hfdcan )

Exit Restricted Operation Mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2589 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ErrorCountersTypeDef * | ErrorCounters
 | ) |  |

Get error counter values.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ErrorCounters | pointer to an FDCAN_ErrorCountersTypeDef structure.
Return values:
HAL status

Definition at line 2478 of file stm32g0xx_hal_fdcan.c.

References FDCAN_ErrorCountersTypeDef::ErrorLogging, __FDCAN_HandleTypeDef::Instance, FDCAN_ErrorCountersTypeDef::RxErrorCnt, FDCAN_ErrorCountersTypeDef::RxErrorPassive, and FDCAN_ErrorCountersTypeDef::TxErrorCnt.

HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_HpMsgStatusTypeDef * | HpMsgStatus
 | ) |  |

Get high priority message status.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
HpMsgStatus | pointer to an FDCAN_HpMsgStatusTypeDef structure.
Return values:
HAL status

Definition at line 2428 of file stm32g0xx_hal_fdcan.c.

References FDCAN_HpMsgStatusTypeDef::FilterIndex, FDCAN_HpMsgStatusTypeDef::FilterList, __FDCAN_HandleTypeDef::Instance, FDCAN_HpMsgStatusTypeDef::MessageIndex, and FDCAN_HpMsgStatusTypeDef::MessageStorage.

uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer ( FDCAN_HandleTypeDef * hfdcan )

Get Tx buffer index of latest Tx FIFO/Queue request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Tx buffer index of last Tx FIFO/Queue request
  • Any value of
    • FDCAN_Tx_location if Tx request has been submitted.
  • 0 if no Tx FIFO/Queue request have been submitted.

Definition at line 2170 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::LatestTxFifoQRequest.

HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_ProtocolStatusTypeDef * | ProtocolStatus
 | ) |  |

Get protocol status.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ProtocolStatus | pointer to an FDCAN_ProtocolStatusTypeDef structure.
Return values:
HAL status

Definition at line 2447 of file stm32g0xx_hal_fdcan.c.

References FDCAN_ProtocolStatusTypeDef::Activity, FDCAN_ProtocolStatusTypeDef::BusOff, FDCAN_ProtocolStatusTypeDef::DataLastErrorCode, FDCAN_ProtocolStatusTypeDef::ErrorPassive, __FDCAN_HandleTypeDef::Instance, FDCAN_ProtocolStatusTypeDef::LastErrorCode, FDCAN_ProtocolStatusTypeDef::ProtocolException, FDCAN_ProtocolStatusTypeDef::RxBRSflag, FDCAN_ProtocolStatusTypeDef::RxESIflag, FDCAN_ProtocolStatusTypeDef::RxFDFflag, FDCAN_ProtocolStatusTypeDef::TDCvalue, and FDCAN_ProtocolStatusTypeDef::Warning.

uint32_t HAL_FDCAN_GetRxFifoFillLevel | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo
 | ) |  |

Return Rx FIFO fill level.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo Rx FIFO. This parameter can be one of the following values:
  • FDCAN_RX_FIFO0: Rx FIFO 0
  • FDCAN_RX_FIFO1: Rx FIFO 1
Return values:
Rx FIFO fill level.

Definition at line 2528 of file stm32g0xx_hal_fdcan.c.

References assert_param, FDCAN_RX_FIFO0, __FDCAN_HandleTypeDef::Instance, and IS_FDCAN_RX_FIFO.

HAL_StatusTypeDef HAL_FDCAN_GetRxMessage | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxLocation,
 |  | FDCAN_RxHeaderTypeDef * | pRxHeader,
 |  | uint8_t * | pRxData
 | ) |  |

Get an FDCAN frame from the Rx FIFO zone into the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxLocation Location of the received message to be read. This parameter can be a value of
  • FDCAN_Rx_location.
pRxHeader | pointer to a FDCAN_RxHeaderTypeDef structure.
pRxData | pointer to a buffer where the payload of the Rx frame will be stored.
Return values:
HAL status

Definition at line 2216 of file stm32g0xx_hal_fdcan.c.

References assert_param, FDCAN_RxHeaderTypeDef::BitRateSwitch, FDCAN_RxHeaderTypeDef::DataLength, DLCtoBytes, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_RxHeaderTypeDef::ErrorStateIndicator, FDCAN_ELEMENT_MASK_ANMF, FDCAN_ELEMENT_MASK_BRS, FDCAN_ELEMENT_MASK_DLC, FDCAN_ELEMENT_MASK_ESI, FDCAN_ELEMENT_MASK_EXTID, FDCAN_ELEMENT_MASK_FDF, FDCAN_ELEMENT_MASK_FIDX, FDCAN_ELEMENT_MASK_RTR, FDCAN_ELEMENT_MASK_STDID, FDCAN_ELEMENT_MASK_TS, FDCAN_ELEMENT_MASK_XTD, FDCAN_RX_FIFO0, FDCAN_STANDARD_ID, FDCAN_RxHeaderTypeDef::FDFormat, FDCAN_RxHeaderTypeDef::FilterIndex, HAL_FDCAN_ERROR_FIFO_EMPTY, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, FDCAN_RxHeaderTypeDef::Identifier, FDCAN_RxHeaderTypeDef::IdType, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_RX_FIFO, FDCAN_RxHeaderTypeDef::IsFilterMatchingFrame, __FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::RxFIFO0SA, FDCAN_MsgRamAddressTypeDef::RxFIFO1SA, FDCAN_RxHeaderTypeDef::RxFrameType, FDCAN_RxHeaderTypeDef::RxTimestamp, SRAMCAN_RF0_SIZE, SRAMCAN_RF1_SIZE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_GetTxEvent | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxEventFifoTypeDef * | pTxEvent
 | ) |  |

Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxEvent | pointer to a FDCAN_TxEventFifoTypeDef structure.
Return values:
HAL status

Definition at line 2345 of file stm32g0xx_hal_fdcan.c.

References FDCAN_TxEventFifoTypeDef::BitRateSwitch, FDCAN_TxEventFifoTypeDef::DataLength, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TxEventFifoTypeDef::ErrorStateIndicator, FDCAN_TxEventFifoTypeDef::EventType, FDCAN_ELEMENT_MASK_BRS, FDCAN_ELEMENT_MASK_DLC, FDCAN_ELEMENT_MASK_ESI, FDCAN_ELEMENT_MASK_ET, FDCAN_ELEMENT_MASK_EXTID, FDCAN_ELEMENT_MASK_FDF, FDCAN_ELEMENT_MASK_MM, FDCAN_ELEMENT_MASK_RTR, FDCAN_ELEMENT_MASK_STDID, FDCAN_ELEMENT_MASK_TS, FDCAN_ELEMENT_MASK_XTD, FDCAN_STANDARD_ID, FDCAN_TxEventFifoTypeDef::FDFormat, HAL_FDCAN_ERROR_FIFO_EMPTY, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_STATE_BUSY, FDCAN_TxEventFifoTypeDef::Identifier, FDCAN_TxEventFifoTypeDef::IdType, __FDCAN_HandleTypeDef::Instance, FDCAN_TxEventFifoTypeDef::MessageMarker, __FDCAN_HandleTypeDef::msgRam, SRAMCAN_TEF_SIZE, __FDCAN_HandleTypeDef::State, FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA, FDCAN_TxEventFifoTypeDef::TxFrameType, and FDCAN_TxEventFifoTypeDef::TxTimestamp.

uint32_t HAL_FDCAN_GetTxFifoFreeLevel ( FDCAN_HandleTypeDef * hfdcan )

Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Tx FIFO free level.

Definition at line 2555 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint32_t HAL_FDCAN_IsRestrictedOperationMode ( FDCAN_HandleTypeDef * hfdcan )

Check if the FDCAN peripheral entered Restricted Operation Mode.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
Status
  • 0 : Normal FDCAN operation.
  • 1 : Restricted Operation Mode active.

Definition at line 2573 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::Instance.

uint32_t HAL_FDCAN_IsTxBufferMessagePending | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TxBufferIndex
 | ) |  |

Check if a transmission request is pending on the selected Tx buffer.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TxBufferIndex Tx buffer index. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
Status
  • 0 : No pending transmission request on TxBufferIndex list
  • 1 : Pending transmission request on TxBufferIndex.

Definition at line 2505 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::Instance, and IS_FDCAN_TX_LOCATION_LIST.

HAL_StatusTypeDef HAL_FDCAN_Start ( FDCAN_HandleTypeDef * hfdcan )

Start the FDCAN module.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 1989 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_NOT_READY, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_Stop ( FDCAN_HandleTypeDef * hfdcan )

Stop the FDCAN module and enable access to configuration registers.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2020 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode, FDCAN_TIMEOUT_VALUE, HAL_FDCAN_ERROR_NOT_STARTED, HAL_FDCAN_ERROR_TIMEOUT, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_ERROR, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::LatestTxFifoQRequest, and __FDCAN_HandleTypeDef::State.

Referenced by HAL_FDCAN_DeInit().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Interrupts management

Functions
Interrupts management
FDCAN Exported Functions

Interrupts management. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.

Detailed Description

Interrupts management.

  ==============================================================================
                       ##### Interrupts management #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request

Function Documentation

HAL_StatusTypeDef HAL_FDCAN_ActivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ActiveITs,
 |  | uint32_t | BufferIndexes
 | ) |  |

Enable interrupts.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ActiveITs indicates which interrupts will be enabled. This parameter can be any combination of
  • FDCAN_Interrupts.
BufferIndexes Tx Buffer Indexes. This parameter can be any combination of
  • FDCAN_Tx_location. This parameter is ignored if ActiveITs does not include one of the following:
    • FDCAN_IT_TX_COMPLETE
    • FDCAN_IT_TX_ABORT_COMPLETE
Return values:
HAL status

Definition at line 2686 of file stm32g0xx_hal_fdcan.c.

References __HAL_FDCAN_ENABLE_IT, assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, FDCAN_IT_GROUP_BIT_LINE_ERROR, FDCAN_IT_GROUP_MISC, FDCAN_IT_GROUP_PROTOCOL_ERROR, FDCAN_IT_GROUP_RX_FIFO0, FDCAN_IT_GROUP_RX_FIFO1, FDCAN_IT_GROUP_SMSG, FDCAN_IT_GROUP_TX_FIFO_ERROR, FDCAN_IT_LIST_BIT_LINE_ERROR, FDCAN_IT_LIST_MISC, FDCAN_IT_LIST_PROTOCOL_ERROR, FDCAN_IT_LIST_RX_FIFO0, FDCAN_IT_LIST_RX_FIFO1, FDCAN_IT_LIST_SMSG, FDCAN_IT_LIST_TX_FIFO_ERROR, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, IS_FDCAN_TX_LOCATION_LIST, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ITList,
 |  | uint32_t | InterruptLine
 | ) |  |

Assign interrupts to either Interrupt line 0 or 1.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ITList indicates which interrupts group will be assigned to the selected interrupt line. This parameter can be any combination of
  • FDCAN_Interrupts_Group.
InterruptLine Interrupt line. This parameter can be a value of
  • FDCAN_Interrupt_Line.
Return values:
HAL status

Definition at line 2641 of file stm32g0xx_hal_fdcan.c.

References assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT_GROUP, IS_FDCAN_IT_LINE, and __FDCAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | InactiveITs
 | ) |  |

Disable interrupts.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
InactiveITs indicates which interrupts will be disabled. This parameter can be any combination of
  • FDCAN_Interrupts.
Return values:
HAL status

Definition at line 2779 of file stm32g0xx_hal_fdcan.c.

References __HAL_FDCAN_DISABLE_IT, assert_param, __FDCAN_HandleTypeDef::ErrorCode, FDCAN_INTERRUPT_LINE0, FDCAN_INTERRUPT_LINE1, FDCAN_IT_GROUP_BIT_LINE_ERROR, FDCAN_IT_GROUP_MISC, FDCAN_IT_GROUP_PROTOCOL_ERROR, FDCAN_IT_GROUP_RX_FIFO0, FDCAN_IT_GROUP_RX_FIFO1, FDCAN_IT_GROUP_SMSG, FDCAN_IT_GROUP_TX_FIFO_ERROR, FDCAN_IT_LIST_BIT_LINE_ERROR, FDCAN_IT_LIST_MISC, FDCAN_IT_LIST_PROTOCOL_ERROR, FDCAN_IT_LIST_RX_FIFO0, FDCAN_IT_LIST_RX_FIFO1, FDCAN_IT_LIST_SMSG, FDCAN_IT_LIST_TX_FIFO_ERROR, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, HAL_FDCAN_ERROR_NOT_INITIALIZED, HAL_FDCAN_STATE_BUSY, HAL_FDCAN_STATE_READY, __FDCAN_HandleTypeDef::Instance, IS_FDCAN_IT, and __FDCAN_HandleTypeDef::State.

void HAL_FDCAN_IRQHandler ( FDCAN_HandleTypeDef * hfdcan )

Handles FDCAN interrupt request.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL status

Definition at line 2875 of file stm32g0xx_hal_fdcan.c.

References __HAL_FDCAN_CLEAR_FLAG, __FDCAN_HandleTypeDef::ErrorCallback, __FDCAN_HandleTypeDef::ErrorCode, __FDCAN_HandleTypeDef::ErrorStatusCallback, FDCAN_CHECK_FLAG, FDCAN_CHECK_IT_SOURCE, FDCAN_ERROR_MASK, FDCAN_ERROR_STATUS_MASK, FDCAN_FLAG_RAM_ACCESS_FAILURE, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG, FDCAN_FLAG_TIMEOUT_OCCURRED, FDCAN_FLAG_TIMESTAMP_WRAPAROUND, FDCAN_FLAG_TX_ABORT_COMPLETE, FDCAN_FLAG_TX_COMPLETE, FDCAN_FLAG_TX_FIFO_EMPTY, FDCAN_IT_RAM_ACCESS_FAILURE, FDCAN_IT_RX_HIGH_PRIORITY_MSG, FDCAN_IT_TIMEOUT_OCCURRED, FDCAN_IT_TIMESTAMP_WRAPAROUND, FDCAN_IT_TX_ABORT_COMPLETE, FDCAN_IT_TX_COMPLETE, FDCAN_IT_TX_FIFO_EMPTY, FDCAN_RX_FIFO0_MASK, FDCAN_RX_FIFO1_MASK, FDCAN_TX_EVENT_FIFO_MASK, HAL_FDCAN_ERROR_NONE, HAL_FDCAN_ERROR_RAM_ACCESS, HAL_FDCAN_ErrorCallback(), HAL_FDCAN_ErrorStatusCallback(), HAL_FDCAN_HighPriorityMessageCallback(), HAL_FDCAN_RxFifo0Callback(), HAL_FDCAN_RxFifo1Callback(), HAL_FDCAN_TimeoutOccurredCallback(), HAL_FDCAN_TimestampWraparoundCallback(), HAL_FDCAN_TxBufferAbortCallback(), HAL_FDCAN_TxBufferCompleteCallback(), HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxFifoEmptyCallback(), __FDCAN_HandleTypeDef::HighPriorityMessageCallback, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::RxFifo0Callback, __FDCAN_HandleTypeDef::RxFifo1Callback, __FDCAN_HandleTypeDef::TimeoutOccurredCallback, __FDCAN_HandleTypeDef::TimestampWraparoundCallback, __FDCAN_HandleTypeDef::TxBufferAbortCallback, __FDCAN_HandleTypeDef::TxBufferCompleteCallback, __FDCAN_HandleTypeDef::TxEventFifoCallback, and __FDCAN_HandleTypeDef::TxFifoEmptyCallback.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Callback functions

Functions
Callback functions
FDCAN Exported Functions

FDCAN Callback functions. More...

Functions

__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.

Detailed Description

FDCAN Callback functions.

  ==============================================================================
                          ##### Callback functions #####
  ==============================================================================
    [..]
    This subsection provides the following callback functions:
      (+) HAL_FDCAN_TxEventFifoCallback
      (+) HAL_FDCAN_RxFifo0Callback
      (+) HAL_FDCAN_RxFifo1Callback
      (+) HAL_FDCAN_TxFifoEmptyCallback
      (+) HAL_FDCAN_TxBufferCompleteCallback
      (+) HAL_FDCAN_TxBufferAbortCallback
      (+) HAL_FDCAN_HighPriorityMessageCallback
      (+) HAL_FDCAN_TimestampWraparoundCallback
      (+) HAL_FDCAN_TimeoutOccurredCallback
      (+) HAL_FDCAN_ErrorCallback
      (+) HAL_FDCAN_ErrorStatusCallback

Function Documentation

void HAL_FDCAN_ErrorCallback ( FDCAN_HandleTypeDef * hfdcan )

Error callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3305 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_ErrorStatusCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | ErrorStatusITs
 | ) |  |

Error status callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
ErrorStatusITs indicates which Error Status interrupts are signaled. This parameter can be any combination of
  • FDCAN_Error_Status_Interrupts.
Return values:
None

Definition at line 3323 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterErrorStatusCallback().

void HAL_FDCAN_HighPriorityMessageCallback ( FDCAN_HandleTypeDef * hfdcan )

High Priority Message callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3289 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_RxFifo0Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo0ITs
 | ) |  |

Rx FIFO 0 callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled. This parameter can be any combination of
  • FDCAN_Rx_Fifo0_Interrupts.
Return values:
None

Definition at line 3167 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterRxFifo0Callback().

void HAL_FDCAN_RxFifo1Callback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | RxFifo1ITs
 | ) |  |

Rx FIFO 1 callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled. This parameter can be any combination of
  • FDCAN_Rx_Fifo1_Interrupts.
Return values:
None

Definition at line 3186 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterRxFifo1Callback().

void HAL_FDCAN_TimeoutOccurredCallback ( FDCAN_HandleTypeDef * hfdcan )

Timeout Occurred callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3273 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_TimestampWraparoundCallback ( FDCAN_HandleTypeDef * hfdcan )

Timestamp Wraparound callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3257 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

void HAL_FDCAN_TxBufferAbortCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndexes
 | ) |  |

Transmission Cancellation callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndexes Indexes of the aborted buffers. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
None

Definition at line 3240 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxBufferAbortCallback().

void HAL_FDCAN_TxBufferCompleteCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | BufferIndexes
 | ) |  |

Transmission Complete callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
BufferIndexes Indexes of the transmitted buffers. This parameter can be any combination of
  • FDCAN_Tx_location.
Return values:
None

Definition at line 3221 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxBufferCompleteCallback().

void HAL_FDCAN_TxEventFifoCallback | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | uint32_t | TxEventFifoITs
 | ) |  |

Tx Event callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled. This parameter can be any combination of
  • FDCAN_Tx_Event_Fifo_Interrupts.
Return values:
None

Definition at line 3148 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void HAL_FDCAN_TxFifoEmptyCallback ( FDCAN_HandleTypeDef * hfdcan )

Tx FIFO Empty callback.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
None

Definition at line 3203 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_UnRegisterCallback().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
FDCAN Exported Functions

FDCAN Peripheral State functions. More...

Functions

HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.

Detailed Description

FDCAN Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.

Function Documentation

uint32_t HAL_FDCAN_GetError ( FDCAN_HandleTypeDef * hfdcan )

Return the FDCAN error code.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
FDCAN Error Code

Definition at line 3371 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::ErrorCode.

HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState ( FDCAN_HandleTypeDef * hfdcan )

Return the FDCAN state.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
HAL state

Definition at line 3359 of file stm32g0xx_hal_fdcan.c.

References __FDCAN_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Private Functions

Functions
FDCAN Private Functions
FDCAN

Functions

static void | FDCAN_CalcultateRamBlockAddresses (FDCAN_HandleTypeDef *hfdcan)
Calculate each RAM block start address and size.
static void | FDCAN_CopyMessageToRAM (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Copy Tx message to the message RAM.

Function Documentation

static void FDCAN_CalcultateRamBlockAddresses ( FDCAN_HandleTypeDef * hfdcan ) [static]

Calculate each RAM block start address and size.

Parameters:
hfdcan pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
Return values:
none

Definition at line 3395 of file stm32g0xx_hal_fdcan.c.

References FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA, FDCAN_InitTypeDef::ExtFiltersNbr, __FDCAN_HandleTypeDef::Init, __FDCAN_HandleTypeDef::Instance, __FDCAN_HandleTypeDef::msgRam, FDCAN_MsgRamAddressTypeDef::RxFIFO0SA, FDCAN_MsgRamAddressTypeDef::RxFIFO1SA, SRAMCAN_FLESA, SRAMCAN_FLSSA, SRAMCAN_RF0SA, SRAMCAN_RF1SA, SRAMCAN_SIZE, SRAMCAN_TEFSA, SRAMCAN_TFQSA, FDCAN_MsgRamAddressTypeDef::StandardFilterSA, FDCAN_InitTypeDef::StdFiltersNbr, FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA, and FDCAN_MsgRamAddressTypeDef::TxFIFOQSA.

Referenced by HAL_FDCAN_Init().

static void FDCAN_CopyMessageToRAM | ( | FDCAN_HandleTypeDef * | hfdcan,
 |  | FDCAN_TxHeaderTypeDef * | pTxHeader,
 |  | uint8_t * | pTxData,
 |  | uint32_t | BufferIndex
 | ) |  | [static]

Copy Tx message to the message RAM.

Parameters:
hfdcan | pointer to an FDCAN_HandleTypeDef structure that contains the configuration information for the specified FDCAN.
pTxHeader | pointer to a FDCAN_TxHeaderTypeDef structure.
pTxData | pointer to a buffer containing the payload of the Tx frame.
BufferIndex | index of the buffer to be configured.
Return values:
none

Definition at line 3447 of file stm32g0xx_hal_fdcan.c.

References FDCAN_TxHeaderTypeDef::BitRateSwitch, FDCAN_TxHeaderTypeDef::DataLength, DLCtoBytes, FDCAN_TxHeaderTypeDef::ErrorStateIndicator, FDCAN_EXTENDED_ID, FDCAN_STANDARD_ID, FDCAN_TxHeaderTypeDef::FDFormat, FDCAN_TxHeaderTypeDef::Identifier, FDCAN_TxHeaderTypeDef::IdType, FDCAN_TxHeaderTypeDef::MessageMarker, __FDCAN_HandleTypeDef::msgRam, SRAMCAN_TFQ_SIZE, FDCAN_TxHeaderTypeDef::TxEventFifoControl, FDCAN_MsgRamAddressTypeDef::TxFIFOQSA, and FDCAN_TxHeaderTypeDef::TxFrameType.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Exported Types

Data Structures | Typedefs | Enumerations
FDCAN Exported Types
FDCAN

Data Structures

struct | FDCAN_InitTypeDef
FDCAN Init structure definition. More...
struct | FDCAN_FilterTypeDef
FDCAN filter structure definition. More...
struct | FDCAN_TxHeaderTypeDef
FDCAN Tx header structure definition. More...
struct | FDCAN_RxHeaderTypeDef
FDCAN Rx header structure definition. More...
struct | FDCAN_TxEventFifoTypeDef
FDCAN Tx event FIFO structure definition. More...
struct | FDCAN_HpMsgStatusTypeDef
FDCAN High Priority Message Status structure definition. More...
struct | FDCAN_ProtocolStatusTypeDef
FDCAN Protocol Status structure definition. More...
struct | FDCAN_ErrorCountersTypeDef
FDCAN Error Counters structure definition. More...
struct | FDCAN_MsgRamAddressTypeDef
FDCAN Message RAM blocks. More...
struct | __FDCAN_HandleTypeDef
FDCAN handle structure definition. More...

Typedefs

typedef struct
__FDCAN_HandleTypeDef 		FDCAN_HandleTypeDef
FDCAN handle structure definition.
typedef void(* | pFDCAN_CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan)
HAL FDCAN Callback pointer definition.
typedef void(* | pFDCAN_TxEventFifoCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
typedef void(* | pFDCAN_RxFifo0CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
typedef void(* | pFDCAN_RxFifo1CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
typedef void(* | pFDCAN_TxBufferCompleteCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_TxBufferAbortCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_ErrorStatusCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

Enumerations

enum | HAL_FDCAN_StateTypeDef { HAL_FDCAN_STATE_RESET = 0x00U, HAL_FDCAN_STATE_READY = 0x01U, HAL_FDCAN_STATE_BUSY = 0x02U, HAL_FDCAN_STATE_ERROR = 0x03U }
HAL State structures definition. More...
enum HAL_FDCAN_CallbackIDTypeDef {
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U,
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, HAL_FDCAN_MSPINIT_CB_ID = 0x05U, HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U
}
HAL FDCAN common Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __FDCAN_HandleTypeDef FDCAN_HandleTypeDef

FDCAN handle structure definition.

typedef void(* pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan)

HAL FDCAN Callback pointer definition.

pointer to a common FDCAN callback function

Definition at line 485 of file stm32g0xx_hal_fdcan.h.

typedef void(* pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

pointer to Error Status callback function

Definition at line 491 of file stm32g0xx_hal_fdcan.h.

typedef void(* pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)

pointer to Rx Fifo 0 FDCAN callback function

Definition at line 487 of file stm32g0xx_hal_fdcan.h.

typedef void(* pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)

pointer to Rx Fifo 1 FDCAN callback function

Definition at line 488 of file stm32g0xx_hal_fdcan.h.

typedef void(* pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

pointer to Tx Buffer abort FDCAN callback function

Definition at line 490 of file stm32g0xx_hal_fdcan.h.

typedef void(* pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

pointer to Tx Buffer complete FDCAN callback function

Definition at line 489 of file stm32g0xx_hal_fdcan.h.

typedef void(* pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)

pointer to Tx event Fifo FDCAN callback function

Definition at line 486 of file stm32g0xx_hal_fdcan.h.

Enumeration Type Documentation

enum HAL_FDCAN_CallbackIDTypeDef

HAL FDCAN common Callback ID enumeration definition.

Enumerator:
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID

FDCAN Tx Fifo Empty callback ID

HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID

FDCAN High priority message callback ID

HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID

FDCAN Timestamp wraparound callback ID

HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID

FDCAN Timeout occurred callback ID

HAL_FDCAN_ERROR_CALLBACK_CB_ID

FDCAN Error callback ID

HAL_FDCAN_MSPINIT_CB_ID

FDCAN MspInit callback ID

HAL_FDCAN_MSPDEINIT_CB_ID

FDCAN MspDeInit callback ID

Definition at line 469 of file stm32g0xx_hal_fdcan.h.

enum HAL_FDCAN_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_FDCAN_STATE_RESET

FDCAN not yet initialized or disabled

HAL_FDCAN_STATE_READY

FDCAN initialized and ready for use

HAL_FDCAN_STATE_BUSY

FDCAN process is ongoing

HAL_FDCAN_STATE_ERROR

FDCAN error state

Definition at line 48 of file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_InitTypeDef Struct Reference
FDCAN Exported Types

FDCAN Init structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | ClockDivider
uint32_t | FrameFormat
uint32_t | Mode
FunctionalState | AutoRetransmission
FunctionalState | TransmitPause
FunctionalState | ProtocolException
uint32_t | NominalPrescaler
uint32_t | NominalSyncJumpWidth
uint32_t | NominalTimeSeg1
uint32_t | NominalTimeSeg2
uint32_t | DataPrescaler
uint32_t | DataSyncJumpWidth
uint32_t | DataTimeSeg1
uint32_t | DataTimeSeg2
uint32_t | StdFiltersNbr
uint32_t | ExtFiltersNbr
uint32_t | TxFifoQueueMode

Detailed Description

FDCAN Init structure definition.

Definition at line 59 of file stm32g0xx_hal_fdcan.h.

Field Documentation

FunctionalState FDCAN_InitTypeDef::AutoRetransmission

Enable or disable the automatic retransmission mode. This parameter can be set to ENABLE or DISABLE

Definition at line 73 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::ClockDivider

Specifies the FDCAN kernel clock divider. The clock is common to all FDCAN instances. This parameter is applied only at initialisation of first FDCAN instance. This parameter can be a value of FDCAN Clock Divider.

Definition at line 61 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataPrescaler

Specifies the value by which the oscillator frequency is divided for generating the data bit time quanta. This parameter must be a number between 1 and 32

Definition at line 97 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataSyncJumpWidth

Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a data bit to perform resynchronization. This parameter must be a number between 1 and 16

Definition at line 101 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataTimeSeg1

Specifies the number of time quanta in Data Bit Segment 1. This parameter must be a number between 1 and 32

Definition at line 106 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::DataTimeSeg2

Specifies the number of time quanta in Data Bit Segment 2. This parameter must be a number between 1 and 16

Definition at line 109 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::ExtFiltersNbr

Specifies the number of extended Message ID filters. This parameter must be a number between 0 and 8

Definition at line 115 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::FrameFormat

Specifies the FDCAN frame format. This parameter can be a value of FDCAN Frame Format

Definition at line 67 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::Mode

Specifies the FDCAN mode. This parameter can be a value of FDCAN Operating Mode

Definition at line 70 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalPrescaler

Specifies the value by which the oscillator frequency is divided for generating the nominal bit time quanta. This parameter must be a number between 1 and 512

Definition at line 82 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalSyncJumpWidth

Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter must be a number between 1 and 128

Definition at line 86 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalTimeSeg1

Specifies the number of time quanta in Bit Segment 1. This parameter must be a number between 2 and 256

Definition at line 91 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::NominalTimeSeg2

Specifies the number of time quanta in Bit Segment 2. This parameter must be a number between 2 and 128

Definition at line 94 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

FunctionalState FDCAN_InitTypeDef::ProtocolException

Enable or disable the Protocol Exception Handling. This parameter can be set to ENABLE or DISABLE

Definition at line 79 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::StdFiltersNbr

Specifies the number of standard Message ID filters. This parameter must be a number between 0 and 28

Definition at line 112 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

FunctionalState FDCAN_InitTypeDef::TransmitPause

Enable or disable the Transmit Pause feature. This parameter can be set to ENABLE or DISABLE

Definition at line 76 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

uint32_t FDCAN_InitTypeDef::TxFifoQueueMode

Tx FIFO/Queue Mode selection. This parameter can be a value of FDCAN Tx FIFO/Queue Mode

Definition at line 118 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_FilterTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_FilterTypeDef Struct Reference
FDCAN Exported Types

FDCAN filter structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | IdType
uint32_t | FilterIndex
uint32_t | FilterType
uint32_t | FilterConfig
uint32_t | FilterID1
uint32_t | FilterID2

Detailed Description

FDCAN filter structure definition.

Definition at line 126 of file stm32g0xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_FilterTypeDef::FilterConfig

Specifies the filter configuration. This parameter can be a value of FDCAN Filter Configuration

Definition at line 141 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterID1

Specifies the filter identification 1. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 144 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterID2

Specifies the filter identification 2. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 149 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterIndex

Specifies the filter which will be initialized. This parameter must be a number between:

  • 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
  • 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID

Definition at line 131 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::FilterType

Specifies the filter type. This parameter can be a value of FDCAN Filter Type. The value FDCAN_FILTER_RANGE_NO_EIDM is permitted only when IdType is FDCAN_EXTENDED_ID.

Definition at line 136 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_FilterTypeDef::IdType

Specifies the identifier type. This parameter can be a value of FDCAN ID Type

Definition at line 128 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_TxHeaderTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TxHeaderTypeDef Struct Reference
FDCAN Exported Types

FDCAN Tx header structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | TxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | TxEventFifoControl
uint32_t | MessageMarker

Detailed Description

FDCAN Tx header structure definition.

Definition at line 159 of file stm32g0xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TxHeaderTypeDef::BitRateSwitch

Specifies whether the Tx frame will be transmitted with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 179 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::DataLength

Specifies the length of the frame that will be transmitted. This parameter can be a value of FDCAN Data Length Code

Definition at line 173 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 176 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::FDFormat

Specifies whether the Tx frame will be transmitted in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 183 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 161 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::IdType

Specifies the identifier type for the message that will be transmitted. This parameter can be a value of FDCAN ID Type

Definition at line 166 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::MessageMarker

Specifies the message marker to be copied into Tx Event FIFO element for identification of Tx message status. This parameter must be a number between 0 and 0xFF

Definition at line 190 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::TxEventFifoControl

Specifies the event FIFO control. This parameter can be a value of FDCAN Event FIFO control

Definition at line 187 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

uint32_t FDCAN_TxHeaderTypeDef::TxFrameType

Specifies the frame type of the message that will be transmitted. This parameter can be a value of FDCAN Frame Type

Definition at line 170 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_AddMessageToTxFifoQ().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_RxHeaderTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_RxHeaderTypeDef Struct Reference
FDCAN Exported Types

FDCAN Rx header structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | RxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | RxTimestamp
uint32_t | FilterIndex
uint32_t | IsFilterMatchingFrame

Detailed Description

FDCAN Rx header structure definition.

Definition at line 199 of file stm32g0xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_RxHeaderTypeDef::BitRateSwitch

Specifies whether the Rx frame is received with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 218 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::DataLength

Specifies the received frame length. This parameter can be a value of FDCAN Data Length Code

Definition at line 212 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 215 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::FDFormat

Specifies whether the Rx frame is received in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 222 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::FilterIndex

Specifies the index of matching Rx acceptance filter element. This parameter must be a number between:

  • 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
  • 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID When the frame is a Non-Filter matching frame, this parameter is unused.

Definition at line 230 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 201 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::IdType

Specifies the identifier type of the received message. This parameter can be a value of FDCAN ID Type

Definition at line 206 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::IsFilterMatchingFrame

Specifies whether the accepted frame did not match any Rx filter. Acceptance of non-matching frames may be enabled via HAL_FDCAN_ConfigGlobalFilter(). This parameter takes 0 if the frame matched an Rx filter or 1 if it did not match any Rx filter

Definition at line 237 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::RxFrameType

Specifies the the received message frame type. This parameter can be a value of FDCAN Frame Type

Definition at line 209 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_RxHeaderTypeDef::RxTimestamp

Specifies the timestamp counter value captured on start of frame reception. This parameter must be a number between 0 and 0xFFFF

Definition at line 226 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_TxEventFifoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_TxEventFifoTypeDef Struct Reference
FDCAN Exported Types

FDCAN Tx event FIFO structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | Identifier
uint32_t | IdType
uint32_t | TxFrameType
uint32_t | DataLength
uint32_t | ErrorStateIndicator
uint32_t | BitRateSwitch
uint32_t | FDFormat
uint32_t | TxTimestamp
uint32_t | MessageMarker
uint32_t | EventType

Detailed Description

FDCAN Tx event FIFO structure definition.

Definition at line 248 of file stm32g0xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_TxEventFifoTypeDef::BitRateSwitch

Specifies whether the Tx frame is transmitted with or without bit rate switching. This parameter can be a value of FDCAN Bit Rate Switching

Definition at line 267 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::DataLength

Specifies the length of the transmitted frame. This parameter can be a value of FDCAN Data Length Code

Definition at line 261 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::ErrorStateIndicator

Specifies the error state indicator. This parameter can be a value of FDCAN Error State Indicator

Definition at line 264 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::EventType

Specifies the event type. This parameter can be a value of FDCAN Event Type

Definition at line 283 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::FDFormat

Specifies whether the Tx frame is transmitted in classic or FD format. This parameter can be a value of FDCAN format

Definition at line 271 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::Identifier

Specifies the identifier. This parameter must be a number between:

  • 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
  • 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID

Definition at line 250 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::IdType

Specifies the identifier type for the transmitted message. This parameter can be a value of FDCAN ID Type

Definition at line 255 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::MessageMarker

Specifies the message marker copied into Tx Event FIFO element for identification of Tx message status. This parameter must be a number between 0 and 0xFF

Definition at line 279 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::TxFrameType

Specifies the frame type of the transmitted message. This parameter can be a value of FDCAN Frame Type

Definition at line 258 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_TxEventFifoTypeDef::TxTimestamp

Specifies the timestamp counter value captured on start of frame transmission. This parameter must be a number between 0 and 0xFFFF

Definition at line 275 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetTxEvent().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_HpMsgStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_HpMsgStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN High Priority Message Status structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | FilterList
uint32_t | FilterIndex
uint32_t | MessageStorage
uint32_t | MessageIndex

Detailed Description

FDCAN High Priority Message Status structure definition.

Definition at line 291 of file stm32g0xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_HpMsgStatusTypeDef::FilterIndex

Specifies the index of matching filter element. This parameter can be a number between:

  • 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard)
  • 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended)

Definition at line 298 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::FilterList

Specifies the filter list of the matching filter element. This parameter can be:

  • 0 : Standard Filter List
  • 1 : Extended Filter List

Definition at line 293 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::MessageIndex

Specifies the Index of Rx FIFO element to which the message was stored. This parameter is valid only when MessageStorage is: FDCAN_HP_STORAGE_RXFIFO0 or FDCAN_HP_STORAGE_RXFIFO1

Definition at line 306 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

uint32_t FDCAN_HpMsgStatusTypeDef::MessageStorage

Specifies the HP Message Storage. This parameter can be a value of FDCAN High Priority Message Storage

Definition at line 303 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetHighPriorityMessageStatus().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_ProtocolStatusTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ProtocolStatusTypeDef Struct Reference
FDCAN Exported Types

FDCAN Protocol Status structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | LastErrorCode
uint32_t | DataLastErrorCode
uint32_t | Activity
uint32_t | ErrorPassive
uint32_t | Warning
uint32_t | BusOff
uint32_t | RxESIflag
uint32_t | RxBRSflag
uint32_t | RxFDFflag
uint32_t | ProtocolException
uint32_t | TDCvalue

Detailed Description

FDCAN Protocol Status structure definition.

Definition at line 318 of file stm32g0xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ProtocolStatusTypeDef::Activity

Specifies the FDCAN module communication state. This parameter can be a value of FDCAN communication state

Definition at line 327 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::BusOff

Specifies the FDCAN module Bus_Off status. This parameter can be:

  • 0 : The FDCAN is not in Bus_Off state
  • 1 : The FDCAN is in Bus_Off state

Definition at line 341 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::DataLastErrorCode

Specifies the type of the last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. This parameter can be a value of FDCAN protocol error code

Definition at line 323 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::ErrorPassive

Specifies the FDCAN module error status. This parameter can be:

  • 0 : The FDCAN is in Error_Active state
  • 1 : The FDCAN is in Error_Passive state

Definition at line 330 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::LastErrorCode

Specifies the type of the last error that occurred on the FDCAN bus. This parameter can be a value of FDCAN protocol error code

Definition at line 320 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::ProtocolException

Specifies the FDCAN module Protocol Exception status. This parameter can be:

  • 0 : No protocol exception event occurred since last read access
  • 1 : Protocol exception event occurred

Definition at line 361 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxBRSflag

Specifies BRS flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its BRS flag set
  • 1 : Last received CAN FD message had its BRS flag set

Definition at line 351 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxESIflag

Specifies ESI flag of last received CAN FD message. This parameter can be:

  • 0 : Last received CAN FD message did not have its ESI flag set
  • 1 : Last received CAN FD message had its ESI flag set

Definition at line 346 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::RxFDFflag

Specifies if CAN FD message (FDF flag set) has been received since last protocol status.This parameter can be:

  • 0 : No CAN FD message received
  • 1 : CAN FD message received

Definition at line 356 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::TDCvalue

Specifies the Transmitter Delay Compensation Value. This parameter can be a number between 0 and 127

Definition at line 366 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

uint32_t FDCAN_ProtocolStatusTypeDef::Warning

Specifies the FDCAN module warning status. This parameter can be:

  • 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
  • 1 : at least one of error counters has reached the Error_Warning limit of 96

Definition at line 335 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetProtocolStatus().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_ErrorCountersTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_ErrorCountersTypeDef Struct Reference
FDCAN Exported Types

FDCAN Error Counters structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | TxErrorCnt
uint32_t | RxErrorCnt
uint32_t | RxErrorPassive
uint32_t | ErrorLogging

Detailed Description

FDCAN Error Counters structure definition.

Definition at line 374 of file stm32g0xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_ErrorCountersTypeDef::ErrorLogging

Specifies the Transmit/Receive error logging counter value. This parameter can be a number between 0 and 255. This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW

Definition at line 388 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::RxErrorCnt

Specifies the Receive Error Counter Value. This parameter can be a number between 0 and 127

Definition at line 379 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::RxErrorPassive

Specifies the Receive Error Passive status. This parameter can be:

  • 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
  • 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128

Definition at line 382 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

uint32_t FDCAN_ErrorCountersTypeDef::TxErrorCnt

Specifies the Transmit Error Counter Value. This parameter can be a number between 0 and 255

Definition at line 376 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetErrorCounters().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN_MsgRamAddressTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FDCAN_MsgRamAddressTypeDef Struct Reference
FDCAN Exported Types

FDCAN Message RAM blocks. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

uint32_t | StandardFilterSA
uint32_t | ExtendedFilterSA
uint32_t | RxFIFO0SA
uint32_t | RxFIFO1SA
uint32_t | TxEventFIFOSA
uint32_t | TxFIFOQSA

Detailed Description

FDCAN Message RAM blocks.

Definition at line 399 of file stm32g0xx_hal_fdcan.h.

Field Documentation

uint32_t FDCAN_MsgRamAddressTypeDef::ExtendedFilterSA

Specifies the Extended Filter List Start Address. This parameter must be a 32-bit word address

Definition at line 404 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_MsgRamAddressTypeDef::RxFIFO0SA

Specifies the Rx FIFO 0 Start Address. This parameter must be a 32-bit word address

Definition at line 407 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::RxFIFO1SA

Specifies the Rx FIFO 1 Start Address. This parameter must be a 32-bit word address

Definition at line 410 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetRxMessage().

uint32_t FDCAN_MsgRamAddressTypeDef::StandardFilterSA

Specifies the Standard Filter List Start Address. This parameter must be a 32-bit word address

Definition at line 401 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_ConfigFilter().

uint32_t FDCAN_MsgRamAddressTypeDef::TxEventFIFOSA

Specifies the Tx Event FIFO Start Address. This parameter must be a 32-bit word address

Definition at line 413 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and HAL_FDCAN_GetTxEvent().

uint32_t FDCAN_MsgRamAddressTypeDef::TxFIFOQSA

Specifies the Tx FIFO/Queue Start Address. This parameter must be a 32-bit word address

Definition at line 416 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), and FDCAN_CopyMessageToRAM().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __FDCAN_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__FDCAN_HandleTypeDef Struct Reference
FDCAN Exported Types

FDCAN handle structure definition. More...

#include <stm32g0xx_hal_fdcan.h>

Data Fields

FDCAN_GlobalTypeDef * | Instance
FDCAN_InitTypeDef Init
FDCAN_MsgRamAddressTypeDef msgRam
uint32_t | LatestTxFifoQRequest
__IO HAL_FDCAN_StateTypeDef | State
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode
void(* | TxEventFifoCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
void(* | RxFifo0Callback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
void(* | RxFifo1Callback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
void(* | TxFifoEmptyCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TxBufferCompleteCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
void(* | TxBufferAbortCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
void(* | HighPriorityMessageCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TimestampWraparoundCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | TimeoutOccurredCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | ErrorCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | ErrorStatusCallback )(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
void(* | MspInitCallback )(struct __FDCAN_HandleTypeDef *hfdcan)
void(* | MspDeInitCallback )(struct __FDCAN_HandleTypeDef *hfdcan)

Detailed Description

FDCAN handle structure definition.

Definition at line 425 of file stm32g0xx_hal_fdcan.h.

Field Documentation

void(* __FDCAN_HandleTypeDef::ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Error callback

Definition at line 455 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

__IO uint32_t __FDCAN_HandleTypeDef::ErrorCode

FDCAN Error code

Definition at line 443 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetError(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

FDCAN Error status callback

Definition at line 456 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterErrorStatusCallback(), and HAL_FDCAN_UnRegisterErrorStatusCallback().

void(* __FDCAN_HandleTypeDef::HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN High priority message callback

Definition at line 452 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

FDCAN_InitTypeDef __FDCAN_HandleTypeDef::Init

FDCAN required parameters

Definition at line 432 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_ConfigFilter(), and HAL_FDCAN_Init().

FDCAN_GlobalTypeDef* __FDCAN_HandleTypeDef::Instance

Register base address

Definition at line 430 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetErrorCounters(), HAL_FDCAN_GetHighPriorityMessageStatus(), HAL_FDCAN_GetProtocolStatus(), HAL_FDCAN_GetRxFifoFillLevel(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTimeoutCounter(), HAL_FDCAN_GetTimestampCounter(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_GetTxFifoFreeLevel(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_IsRestrictedOperationMode(), HAL_FDCAN_IsTxBufferMessagePending(), HAL_FDCAN_ResetTimeoutCounter(), HAL_FDCAN_ResetTimestampCounter(), HAL_FDCAN_Start(), and HAL_FDCAN_Stop().

uint32_t __FDCAN_HandleTypeDef::LatestTxFifoQRequest

FDCAN Tx buffer index of latest Tx FIFO/Queue request

Definition at line 436 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_GetLatestTxFifoQRequestBuffer(), HAL_FDCAN_Init(), and HAL_FDCAN_Stop().

HAL_LockTypeDef __FDCAN_HandleTypeDef::Lock

FDCAN locking object

Definition at line 441 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

FDCAN_MsgRamAddressTypeDef __FDCAN_HandleTypeDef::msgRam

FDCAN Message RAM blocks

Definition at line 434 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CalcultateRamBlockAddresses(), FDCAN_CopyMessageToRAM(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

void(* __FDCAN_HandleTypeDef::MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Msp DeInit callback

Definition at line 459 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeInit(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Msp Init callback

Definition at line 458 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)

FDCAN Rx Fifo 0 callback

Definition at line 447 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterRxFifo0Callback(), and HAL_FDCAN_UnRegisterRxFifo0Callback().

void(* __FDCAN_HandleTypeDef::RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)

FDCAN Rx Fifo 1 callback

Definition at line 448 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterRxFifo1Callback(), and HAL_FDCAN_UnRegisterRxFifo1Callback().

__IO HAL_FDCAN_StateTypeDef __FDCAN_HandleTypeDef::State

FDCAN communication state

Definition at line 439 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_ExitRestrictedOperationMode(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetState(), HAL_FDCAN_GetTxEvent(), HAL_FDCAN_Init(), HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_Start(), HAL_FDCAN_Stop(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Timeout occurred callback

Definition at line 454 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Timestamp wraparound callback

Definition at line 453 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

void(* __FDCAN_HandleTypeDef::TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

FDCAN Tx Buffer abort callback

Definition at line 451 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxBufferAbortCallback(), and HAL_FDCAN_UnRegisterTxBufferAbortCallback().

void(* __FDCAN_HandleTypeDef::TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)

FDCAN Tx Buffer complete callback

Definition at line 450 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxBufferCompleteCallback().

void(* __FDCAN_HandleTypeDef::TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)

FDCAN Tx Event Fifo callback

Definition at line 446 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterTxEventFifoCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

void(* __FDCAN_HandleTypeDef::TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan)

FDCAN Tx Fifo Empty callback

Definition at line 449 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), HAL_FDCAN_RegisterCallback(), and HAL_FDCAN_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_fdcan.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL FDCAN Error Code

Defines
HAL FDCAN Error Code
FDCAN Exported Constants

Defines

#define | HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)
#define | HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)
#define | HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)
#define | HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)
#define | HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)
#define | HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)
#define | HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)
#define | HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)
#define | HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)
#define | HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO
#define | HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI
#define | HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA
#define | HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED
#define | HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA
#define | HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)

Define Documentation

#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)

Put element in full FIFO

Definition at line 516 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)

Get element from empty FIFO

Definition at line 517 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)

Invalid Callback error

Definition at line 525 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_RegisterCallback(), HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), and HAL_FDCAN_UnRegisterTxEventFifoCallback().

#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO

Overflow of CAN Error Logging Counter

Definition at line 518 of file stm32g0xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 507 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeInit(), HAL_FDCAN_Init(), HAL_FDCAN_IRQHandler(), and HAL_FDCAN_Start().

#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)

Peripheral not initialized

Definition at line 509 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_ExitRestrictedOperationMode().

#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)

Peripheral not ready

Definition at line 510 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DisableEdgeFiltering(), HAL_FDCAN_DisableISOMode(), HAL_FDCAN_DisableTimeoutCounter(), HAL_FDCAN_DisableTimestampCounter(), HAL_FDCAN_DisableTxDelayCompensation(), HAL_FDCAN_EnableEdgeFiltering(), HAL_FDCAN_EnableISOMode(), HAL_FDCAN_EnableTimeoutCounter(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_EnableTxDelayCompensation(), and HAL_FDCAN_Start().

#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)

Peripheral not started

Definition at line 511 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_GetTxEvent(), and HAL_FDCAN_Stop().

#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)

Mode not supported

Definition at line 512 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimeoutCounter(), and HAL_FDCAN_ResetTimestampCounter().

#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)

Parameter error

Definition at line 513 of file stm32g0xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)

Pending operation

Definition at line 514 of file stm32g0xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA

Protocol Error in Arbitration Phase (Nominal Bit Time is used)

Definition at line 520 of file stm32g0xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED

Protocol Error in Data Phase (Data Bit Time is used)

Definition at line 521 of file stm32g0xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)

Message RAM Access Failure

Definition at line 515 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI

Message RAM Watchdog event occurred

Definition at line 519 of file stm32g0xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA

Access to Reserved Address

Definition at line 522 of file stm32g0xx_hal_fdcan.h.

#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)

Timeout error

Definition at line 508 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), and HAL_FDCAN_Stop().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Frame Format

Defines
FDCAN Frame Format
FDCAN Exported Constants

Defines

#define | FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)
#define | FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)
#define | FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))

Define Documentation

#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)

Classic mode

Definition at line 534 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))

FD mode with BitRate Switching

Definition at line 536 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)

FD mode without BitRate Switching

Definition at line 535 of file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Operating Mode

Defines
FDCAN Operating Mode
FDCAN Exported Constants

Defines

#define | FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)
#define | FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)
#define | FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)
#define | FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)
#define | FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)

Define Documentation

#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)

Bus Monitoring mode

Definition at line 546 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)

External LoopBack mode

Definition at line 548 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)

Internal LoopBack mode

Definition at line 547 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)

Normal mode

Definition at line 544 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)

Restricted Operation mode

Definition at line 545 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

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STM32G0C1xx HAL User Manual: FDCAN Clock Divider

Defines
FDCAN Clock Divider
FDCAN Exported Constants

Defines

#define | FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U)
#define | FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U)
#define | FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U)
#define | FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U)
#define | FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U)
#define | FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U)
#define | FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U)
#define | FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U)
#define | FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U)
#define | FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU)
#define | FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU)
#define | FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU)
#define | FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU)
#define | FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU)
#define | FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU)

Define Documentation

#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)

Divide kernel clock by 1

Definition at line 556 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U)

Divide kernel clock by 10

Definition at line 561 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U)

Divide kernel clock by 12

Definition at line 562 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U)

Divide kernel clock by 14

Definition at line 563 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U)

Divide kernel clock by 16

Definition at line 564 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U)

Divide kernel clock by 18

Definition at line 565 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U)

Divide kernel clock by 2

Definition at line 557 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU)

Divide kernel clock by 20

Definition at line 566 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU)

Divide kernel clock by 22

Definition at line 567 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU)

Divide kernel clock by 24

Definition at line 568 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU)

Divide kernel clock by 26

Definition at line 569 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU)

Divide kernel clock by 28

Definition at line 570 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU)

Divide kernel clock by 30

Definition at line 571 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U)

Divide kernel clock by 4

Definition at line 558 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U)

Divide kernel clock by 6

Definition at line 559 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U)

Divide kernel clock by 8

Definition at line 560 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Tx FIFO/Queue Mode

Defines
FDCAN Tx FIFO/Queue Mode
FDCAN Exported Constants

Defines

#define | FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)

Define Documentation

#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)

FIFO mode

Definition at line 579 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)

Queue mode

Definition at line 580 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN ID Type

Defines
FDCAN ID Type
FDCAN Exported Constants

Defines

#define | FDCAN_STANDARD_ID ((uint32_t)0x00000000U)
#define | FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)

Define Documentation

#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)

Extended ID element

Definition at line 589 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM().

#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U)

Standard ID element

Definition at line 588 of file stm32g0xx_hal_fdcan.h.

Referenced by FDCAN_CopyMessageToRAM(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Frame Type

Defines
FDCAN Frame Type
FDCAN Exported Constants

Defines

#define | FDCAN_DATA_FRAME ((uint32_t)0x00000000U)
#define | FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)

Define Documentation

#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U)

Data frame

Definition at line 597 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)

Remote frame

Definition at line 598 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Data Length Code

Defines
FDCAN Data Length Code
FDCAN Exported Constants

Defines

#define | FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)
#define | FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)
#define | FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)
#define | FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)
#define | FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)
#define | FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)
#define | FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)
#define | FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)
#define | FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)
#define | FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)
#define | FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)
#define | FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)
#define | FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)
#define | FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)
#define | FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)
#define | FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)

0 bytes data field

Definition at line 606 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)

1 bytes data field

Definition at line 607 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)

12 bytes data field

Definition at line 615 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)

16 bytes data field

Definition at line 616 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)

2 bytes data field

Definition at line 608 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)

20 bytes data field

Definition at line 617 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)

24 bytes data field

Definition at line 618 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)

3 bytes data field

Definition at line 609 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)

32 bytes data field

Definition at line 619 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)

4 bytes data field

Definition at line 610 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)

48 bytes data field

Definition at line 620 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)

5 bytes data field

Definition at line 611 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)

6 bytes data field

Definition at line 612 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)

64 bytes data field

Definition at line 621 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)

7 bytes data field

Definition at line 613 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)

8 bytes data field

Definition at line 614 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Error State Indicator

Defines
FDCAN Error State Indicator
FDCAN Exported Constants

Defines

#define | FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)
#define | FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)

Define Documentation

#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)

Transmitting node is error active

Definition at line 629 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)

Transmitting node is error passive

Definition at line 630 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Bit Rate Switching

Defines
FDCAN Bit Rate Switching
FDCAN Exported Constants

Defines

#define | FDCAN_BRS_OFF ((uint32_t)0x00000000U)
#define | FDCAN_BRS_ON ((uint32_t)0x00100000U)

Define Documentation

#define FDCAN_BRS_OFF ((uint32_t)0x00000000U)

FDCAN frames transmitted/received without bit rate switching

Definition at line 638 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_BRS_ON ((uint32_t)0x00100000U)

FDCAN frames transmitted/received with bit rate switching

Definition at line 639 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN format

Defines
FDCAN format
FDCAN Exported Constants

Defines

#define | FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)
#define | FDCAN_FD_CAN ((uint32_t)0x00200000U)

Define Documentation

#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)

Frame transmitted/received in Classic CAN format

Definition at line 647 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FD_CAN ((uint32_t)0x00200000U)

Frame transmitted/received in FDCAN format

Definition at line 648 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Event FIFO control

Defines
FDCAN Event FIFO control
FDCAN Exported Constants

Defines

#define | FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)
#define | FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)

Define Documentation

#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)

Do not store Tx events

Definition at line 656 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)

Store Tx events

Definition at line 657 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Filter Type

Defines
FDCAN Filter Type
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_MASK ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

Define Documentation

#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)

Dual ID filter for FilterID1 or FilterID2

Definition at line 666 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U)

Classic filter: FilterID1 = filter, FilterID2 = mask

Definition at line 667 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)

Range filter from FilterID1 to FilterID2

Definition at line 665 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

Range filter from FilterID1 to FilterID2, EIDM mask not applied

Definition at line 668 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Filter Configuration

Defines
FDCAN Filter Configuration
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_HP ((uint32_t)0x00000004U)
#define | FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)
#define | FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)

Define Documentation

#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)

Disable filter element

Definition at line 676 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_HP ((uint32_t)0x00000004U)

Set high priority if filter matches

Definition at line 680 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)

Reject ID if filter matches

Definition at line 679 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)

Store in Rx FIFO 0 if filter matches

Definition at line 677 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)

Set high priority and store in FIFO 0 if filter matches

Definition at line 681 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)

Store in Rx FIFO 1 if filter matches

Definition at line 678 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)

Set high priority and store in FIFO 1 if filter matches

Definition at line 682 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Tx Location

Defines
FDCAN Tx Location
FDCAN Exported Constants

Defines

#define | FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)
#define | FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)
#define | FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)

Define Documentation

#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)

Add message to Tx Buffer 0

Definition at line 690 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)

Add message to Tx Buffer 1

Definition at line 691 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)

Add message to Tx Buffer 2

Definition at line 692 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Rx Location

Defines
FDCAN Rx Location
FDCAN Exported Constants

Defines

#define | FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)
#define | FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)

Define Documentation

#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)

Get received message from Rx FIFO 0

Definition at line 700 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_GetRxFifoFillLevel(), and HAL_FDCAN_GetRxMessage().

#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)

Get received message from Rx FIFO 1

Definition at line 701 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Event Type

Defines
FDCAN Event Type
FDCAN Exported Constants

Defines

#define | FDCAN_TX_EVENT ((uint32_t)0x00400000U)
#define | FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)

Define Documentation

#define FDCAN_TX_EVENT ((uint32_t)0x00400000U)

Tx event

Definition at line 709 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)

Transmission in spite of cancellation

Definition at line 710 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN High Priority Message Storage

Defines
FDCAN High Priority Message Storage
FDCAN Exported Constants

Defines

#define | FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)
#define | FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)
#define | FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)

Define Documentation

#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)

FIFO message lost

Definition at line 719 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)

No FIFO selected

Definition at line 718 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)

Message stored in FIFO 0

Definition at line 720 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)

Message stored in FIFO 1

Definition at line 721 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN protocol error code

Defines
FDCAN protocol error code
FDCAN Exported Constants

Defines

#define | FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)
#define | FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)
#define | FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)
#define | FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)
#define | FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)
#define | FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)
#define | FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)
#define | FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)

Define Documentation

#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)

Acknowledge error

Definition at line 732 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)

Bit 0 (dominant) error

Definition at line 734 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)

Bit 1 (recessive) error

Definition at line 733 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)

CRC check sum error

Definition at line 735 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)

Form error

Definition at line 731 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)

No change since last read

Definition at line 736 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)

No error occurred

Definition at line 729 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)

Stuff error

Definition at line 730 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN communication state

Defines
FDCAN communication state
FDCAN Exported Constants

Defines

#define | FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)
#define | FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)
#define | FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)

Define Documentation

#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)

Node is neither receiver nor transmitter

Definition at line 745 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)

Node is operating as receiver

Definition at line 746 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)

Node is synchronizing on CAN communication

Definition at line 744 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)

Node is operating as transmitter

Definition at line 747 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN FIFO operation mode

Defines
FDCAN FIFO operation mode
FDCAN Exported Constants

Defines

#define | FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)
#define | FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U)

Define Documentation

#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)

Rx FIFO blocking mode

Definition at line 755 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U)

Rx FIFO overwrite mode

Definition at line 756 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN non-matching frames

Defines
FDCAN non-matching frames
FDCAN Exported Constants

Defines

#define | FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)
#define | FDCAN_REJECT ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)

Accept in Rx FIFO 0

Definition at line 764 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)

Accept in Rx FIFO 1

Definition at line 765 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_REJECT ((uint32_t)0x00000002U)

Reject

Definition at line 766 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN reject remote frames

Defines
FDCAN reject remote frames
FDCAN Exported Constants

Defines

#define | FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)
#define | FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)

Define Documentation

#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)

Filter remote frames

Definition at line 774 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)

Reject all remote frames

Definition at line 775 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN interrupt line

Defines
FDCAN interrupt line
FDCAN Exported Constants

Defines

#define | FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)

Interrupt Line 0

Definition at line 783 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_DeInit().

#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)

Interrupt Line 1

Definition at line 784 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_DeInit().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN timestamp

Defines
FDCAN timestamp
FDCAN Exported Constants

Defines

#define | FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)
#define | FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)

Define Documentation

#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)

External timestamp counter value used

Definition at line 793 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimestampCounter().

#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)

Timestamp counter value incremented according to TCP

Definition at line 792 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN timestamp prescaler

Defines
FDCAN timestamp prescaler
FDCAN Exported Constants

Defines

#define | FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)
#define | FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)
#define | FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)
#define | FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)
#define | FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)
#define | FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)
#define | FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)
#define | FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)
#define | FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)
#define | FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)
#define | FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)
#define | FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)
#define | FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)
#define | FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)
#define | FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)
#define | FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)

Define Documentation

#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)

Timestamp counter time unit in equal to CAN bit time

Definition at line 801 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 10

Definition at line 810 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 11

Definition at line 811 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 12

Definition at line 812 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 13

Definition at line 813 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 14

Definition at line 814 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 15

Definition at line 815 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 16

Definition at line 816 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 2

Definition at line 802 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 3

Definition at line 803 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 4

Definition at line 804 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 5

Definition at line 805 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 6

Definition at line 806 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 7

Definition at line 807 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 8

Definition at line 808 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)

Timestamp counter time unit in equal to CAN bit time multiplied by 9

Definition at line 809 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN timeout operation

Defines
FDCAN timeout operation
FDCAN Exported Constants

Defines

#define | FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)
#define | FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)
#define | FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)
#define | FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)

Define Documentation

#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)

Timeout continuous operation

Definition at line 824 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ResetTimeoutCounter().

#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)

Timeout controlled by Rx FIFO 0

Definition at line 826 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)

Timeout controlled by Rx FIFO 1

Definition at line 827 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)

Timeout controlled by Tx Event FIFO

Definition at line 825 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: Interrupt masks

Defines
Interrupt masks
FDCAN Exported Constants

Defines

#define | FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU)
#define | FDCAN_ILS_MASK ((uint32_t)0x0000007FU)

Define Documentation

#define FDCAN_ILS_MASK ((uint32_t)0x0000007FU)

FDCAN interrupts group mask

Definition at line 836 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU)

FDCAN interrupts mask

Definition at line 835 of file stm32g0xx_hal_fdcan.h.

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STM32G0C1xx HAL User Manual: FDCAN Flags

Defines
FDCAN Flags
FDCAN Exported Constants

Defines

#define | FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC
#define | FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF
#define | FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE
#define | FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM
#define | FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL
#define | FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF
#define | FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN
#define | FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L
#define | FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F
#define | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N
#define | FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L
#define | FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F
#define | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N
#define | FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF
#define | FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO
#define | FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP
#define | FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW
#define | FDCAN_FLAG_BUS_OFF FDCAN_IR_BO
#define | FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI
#define | FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA
#define | FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED
#define | FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA
#define | FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW
#define | FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO

Define Documentation

#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA

Protocol error in arbitration phase detected

Definition at line 863 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO

Bus_Off status changed

Definition at line 861 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED

Protocol error in data phase detected

Definition at line 864 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO

Overflow of FDCAN Error Logging Counter occurred

Definition at line 858 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP

Error_Passive status changed

Definition at line 859 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW

Error_Warning status changed

Definition at line 860 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF

Message RAM access failure occurred

Definition at line 857 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI

Message RAM Watchdog event due to missing READY

Definition at line 862 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA

Access to reserved address occurred

Definition at line 865 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F

Rx FIFO 0 full

Definition at line 852 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L

Rx FIFO 0 message lost

Definition at line 851 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N

New message written to Rx FIFO 0

Definition at line 853 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F

Rx FIFO 1 full

Definition at line 855 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L

Rx FIFO 1 message lost

Definition at line 854 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N

New message written to Rx FIFO 1

Definition at line 856 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM

High priority message received

Definition at line 847 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO

Timeout reached

Definition at line 867 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW

Timestamp counter wrapped around

Definition at line 866 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF

Transmission Cancellation Finished

Definition at line 845 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC

Transmission Completed

Definition at line 844 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL

Tx Event FIFO element lost

Definition at line 848 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF

Tx Event FIFO full

Definition at line 849 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN

Tx Handler wrote Tx Event FIFO element

Definition at line 850 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE

Tx FIFO Empty

Definition at line 846 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

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STM32G0C1xx HAL User Manual: FDCAN Tx Interrupts

Defines
FDCAN Tx Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE
#define | FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE
#define | FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE

Define Documentation

#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE

Transmission Cancellation Finished

Definition at line 880 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE

Transmission Completed

Definition at line 879 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), HAL_FDCAN_DeactivateNotification(), and HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE

Tx FIFO Empty

Definition at line 881 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Rx Interrupts

Defines
FDCAN Rx Interrupts
FDCAN Interrupts

Defines

#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME

Define Documentation

#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME

High priority message received

Definition at line 889 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Counter Interrupts

Defines
FDCAN Counter Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE
#define | FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE

Define Documentation

#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE

Timeout reached

Definition at line 898 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE

Timestamp counter wrapped around

Definition at line 897 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Tx Event FIFO Interrupts

Defines
FDCAN Tx Event FIFO Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE
#define | FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE
#define | FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE

Define Documentation

#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE

Tx Event FIFO element lost

Definition at line 906 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE

Tx Event FIFO full

Definition at line 907 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE

Tx Handler wrote Tx Event FIFO element

Definition at line 908 of file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Rx FIFO 0 Interrupts

Defines
FDCAN Rx FIFO 0 Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE
#define | FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE
#define | FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE

Define Documentation

#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE

Rx FIFO 0 full

Definition at line 917 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE

Rx FIFO 0 message lost

Definition at line 916 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE

New message written to Rx FIFO 0

Definition at line 918 of file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Rx FIFO 1 Interrupts

Defines
FDCAN Rx FIFO 1 Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE
#define | FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE
#define | FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE

Define Documentation

#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE

Rx FIFO 1 full

Definition at line 927 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE

Rx FIFO 1 message lost

Definition at line 926 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE

New message written to Rx FIFO 1

Definition at line 928 of file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Error Interrupts

Defines
FDCAN Error Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE
#define | FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE
#define | FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE
#define | FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE
#define | FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE
#define | FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE

Define Documentation

#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE

Protocol error in arbitration phase detected

Definition at line 939 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE

Protocol error in data phase detected

Definition at line 940 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE

Overflow of FDCAN Error Logging Counter occurred

Definition at line 937 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE

Message RAM access failure occurred

Definition at line 936 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE

Message RAM Watchdog event due to missing READY

Definition at line 938 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE

Access to reserved address occurred

Definition at line 941 of file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Error Status Interrupts

Defines
FDCAN Error Status Interrupts
FDCAN Interrupts

Defines

#define | FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE
#define | FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE
#define | FDCAN_IT_BUS_OFF FDCAN_IE_BOE

Define Documentation

#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE

Bus_Off status changed

Definition at line 951 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE

Error_Passive status changed

Definition at line 949 of file stm32g0xx_hal_fdcan.h.

#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE

Error_Warning status changed

Definition at line 950 of file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Interrupts List

Defines
FDCAN Interrupts List
FDCAN Exported Constants

Defines

#define | FDCAN_IT_LIST_RX_FIFO0
#define | FDCAN_IT_LIST_RX_FIFO1
#define | FDCAN_IT_LIST_SMSG
#define | FDCAN_IT_LIST_TX_FIFO_ERROR
#define | FDCAN_IT_LIST_MISC
#define | FDCAN_IT_LIST_BIT_LINE_ERROR
#define | FDCAN_IT_LIST_PROTOCOL_ERROR

Define Documentation

#define FDCAN_IT_LIST_BIT_LINE_ERROR
Value:
(FDCAN_IT_ERROR_PASSIVE | \
                                        FDCAN_IT_ERROR_LOGGING_OVERFLOW)

Bit and Line Error Interrupts List

Definition at line 979 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_MISC
Value:
(FDCAN_IT_TIMEOUT_OCCURRED | \
                                        FDCAN_IT_RAM_ACCESS_FAILURE | \
                                        FDCAN_IT_TIMESTAMP_WRAPAROUND)

Misc. Interrupts List

Definition at line 976 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_PROTOCOL_ERROR
Value:
(FDCAN_IT_RESERVED_ADDRESS_ACCESS | \
                                        FDCAN_IT_DATA_PROTOCOL_ERROR | \
                                        FDCAN_IT_ARB_PROTOCOL_ERROR | \
                                        FDCAN_IT_RAM_WATCHDOG | \
                                        FDCAN_IT_BUS_OFF | \
                                        FDCAN_IT_ERROR_WARNING)

Protocol Error Interrupts List

Definition at line 981 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_RX_FIFO0
Value:
(FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \
                                        FDCAN_IT_RX_FIFO0_FULL         | \
                                        FDCAN_IT_RX_FIFO0_NEW_MESSAGE)

RX FIFO 0 Interrupts List

Definition at line 963 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_RX_FIFO1
Value:
(FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \
                                        FDCAN_IT_RX_FIFO1_FULL         | \
                                        FDCAN_IT_RX_FIFO1_NEW_MESSAGE)

RX FIFO 1 Interrupts List

Definition at line 966 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_SMSG
Value:
(FDCAN_IT_TX_ABORT_COMPLETE | \
                                        FDCAN_IT_TX_COMPLETE | \
                                        FDCAN_IT_RX_HIGH_PRIORITY_MSG)

Status Message Interrupts List

Definition at line 969 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_LIST_TX_FIFO_ERROR
Value:
(FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \
                                        FDCAN_IT_TX_EVT_FIFO_FULL | \
                                        FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
                                        FDCAN_IT_TX_FIFO_EMPTY)

TX FIFO Error Interrupts List

Definition at line 972 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

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STM32G0C1xx HAL User Manual: FDCAN Interrupts Group

Defines
FDCAN Interrupts Group
FDCAN Exported Constants

Defines

#define | FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0
#define | FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1
#define | FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG
#define | FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR
#define | FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC
#define | FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR
#define | FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR

Define Documentation

#define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR

Bit and Line Error Interrupts Group: EPL: Error Passive ELOL: Error Logging Overflow

Definition at line 1015 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC

Misc. Interrupts Group: TOOL: Timeout Occurred MRAFL: Message RAM Access Failure TSWL: Timestamp Wraparound

Definition at line 1011 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR

Protocol Error Group: ARAL: Access to Reserved Address Line PEDL: Protocol Error in Data Phase Line PEAL: Protocol Error in Arbitration Phase Line WDIL: Watchdog Interrupt Line BOL: Bus_Off Status EWL: Warning Status

Definition at line 1018 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0

RX FIFO 0 Interrupts Group: RF0LL: Rx FIFO 0 Message Lost RF0FL: Rx FIFO 0 is Full RF0NL: Rx FIFO 0 Has New Message

Definition at line 994 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1

RX FIFO 1 Interrupts Group: RF1LL: Rx FIFO 1 Message Lost RF1FL: Rx FIFO 1 is Full RF1NL: Rx FIFO 1 Has New Message

Definition at line 998 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG

Status Message Interrupts Group: TCFL: Transmission Cancellation Finished TCL: Transmission Completed HPML: High Priority Message

Definition at line 1002 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR

TX FIFO Error Interrupts Group: TEFLL: Tx Event FIFO Element Lost TEFFL: Tx Event FIFO Full TEFNL: Tx Event FIFO New Entry TFEL: Tx FIFO Empty Interrupt Line

Definition at line 1006 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Exported Macros

Defines
FDCAN Exported Macros
FDCAN

Defines

#define | __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__)
Reset FDCAN handle state.
#define | __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
Enable the specified FDCAN interrupts.
#define | __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
Disable the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
Check whether the specified FDCAN interrupt is set or not.
#define | __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
Clear the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
Check whether the specified FDCAN flag is set or not.
#define | __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR) = (__FLAG__)
Clear the specified FDCAN flags.
#define | __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
Check if the specified FDCAN interrupt source is enabled or disabled.

Define Documentation

#define __HAL_FDCAN_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->IR) = (__FLAG__)

Clear the specified FDCAN flags.

Parameters:
__HANDLE__ FDCAN handle.
__FLAG__ specifies the flags to clear. This parameter can be any combination of
  • FDCAN_flags
Return values:
None

Definition at line 1107 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define __HAL_FDCAN_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)

Clear the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ specifies the interrupts to clear. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1088 of file stm32g0xx_hal_fdcan.h.

#define __HAL_FDCAN_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)

Disable the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1069 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_DeactivateNotification().

#define __HAL_FDCAN_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (__HANDLE__)->Instance->IE |= (__INTERRUPT__)

Enable the specified FDCAN interrupts.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be any combination of
  • FDCAN_Interrupts
Return values:
None

Definition at line 1059 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification().

#define __HAL_FDCAN_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->IR & (__FLAG__))

Check whether the specified FDCAN flag is set or not.

Parameters:
__HANDLE__ FDCAN handle.
__FLAG__ FDCAN flag. This parameter can be one of
  • FDCAN_flags
Return values:
FlagStatus

Definition at line 1098 of file stm32g0xx_hal_fdcan.h.

#define __HAL_FDCAN_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IR & (__INTERRUPT__))

Check whether the specified FDCAN interrupt is set or not.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ FDCAN interrupt. This parameter can be one of
  • FDCAN_Interrupts
Return values:
ITStatus

Definition at line 1079 of file stm32g0xx_hal_fdcan.h.

#define __HAL_FDCAN_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IE & (__INTERRUPT__))

Check if the specified FDCAN interrupt source is enabled or disabled.

Parameters:
__HANDLE__ FDCAN handle.
__INTERRUPT__ specifies the FDCAN interrupt source to check. This parameter can be a value of
  • FDCAN_Interrupts
Return values:
ITStatus

Definition at line 1116 of file stm32g0xx_hal_fdcan.h.

#define __HAL_FDCAN_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                \
                                                       (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
                                                       (__HANDLE__)->MspInitCallback = NULL;           \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
                                                     } while(0)

Reset FDCAN handle state.

Parameters:
__HANDLE__ FDCAN handle.
Return values:
None

Definition at line 1043 of file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Private Variables

Variables
FDCAN Private Variables
FDCAN

Variables

static const uint8_t DLCtoBytes [] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}

Variable Documentation

const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64} [static]

Definition at line 242 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CopyMessageToRAM(), and HAL_FDCAN_GetRxMessage().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Private Constants

Defines
FDCAN Private Constants
FDCAN

Defines

#define | FDCAN_TIMEOUT_VALUE 10U
#define | FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
#define | FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
#define | FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
#define | FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
#define | FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
#define | FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define | FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define | FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define | FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define | FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define | FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define | FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define | FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define | FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define | FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define | FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define | FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
#define | SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
#define | SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */
#define | SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */
#define | SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */
#define | SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */
#define | SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */
#define | SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */
#define | SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */
#define | SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
#define | SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
#define | SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */
#define | SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
#define | SRAMCAN_FLSSA
#define | SRAMCAN_FLESA
#define | SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
#define | SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
#define | SRAMCAN_TEFSA
#define | SRAMCAN_TFQSA
#define | SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */

Define Documentation

#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */

Definition at line 208 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */

Definition at line 203 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */

Definition at line 202 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */

Definition at line 205 of file stm32g0xx_hal_fdcan.c.

#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */

Definition at line 200 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */

Definition at line 209 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */

Definition at line 197 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */

Definition at line 204 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */

Definition at line 207 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */

Definition at line 206 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */

Definition at line 198 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */

Definition at line 196 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */

Definition at line 201 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */

Definition at line 199 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage(), and HAL_FDCAN_GetTxEvent().

#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)

Definition at line 193 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)

Definition at line 194 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)

Definition at line 191 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)

Definition at line 192 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_TIMEOUT_VALUE 10U

Definition at line 188 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_EnterPowerDownMode(), HAL_FDCAN_ExitPowerDownMode(), HAL_FDCAN_Init(), and HAL_FDCAN_Stop().

#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)

Definition at line 190 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_IRQHandler().

#define SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */

Definition at line 212 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init().

#define SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */

Definition at line 219 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_ConfigFilter().

#define SRAMCAN_FLESA
Value:
((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start
                                                                                Address                  */

Definition at line 226 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */

Definition at line 211 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_Init().

#define SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */

Definition at line 218 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_ConfigFilter().

#define SRAMCAN_FLSSA
Value:
((uint32_t)0)                                                      /* Filter List Standard Start
                                                                                Address                  */

Definition at line 225 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */

Definition at line 213 of file stm32g0xx_hal_fdcan.c.

#define SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */

Definition at line 220 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */

Definition at line 227 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */

Definition at line 214 of file stm32g0xx_hal_fdcan.c.

#define SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */

Definition at line 221 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetRxMessage().

#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */

Definition at line 228 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */

Definition at line 231 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */

Definition at line 215 of file stm32g0xx_hal_fdcan.c.

#define SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */

Definition at line 222 of file stm32g0xx_hal_fdcan.c.

Referenced by HAL_FDCAN_GetTxEvent().

#define SRAMCAN_TEFSA
Value:
((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start
                                                                                Address */

Definition at line 229 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

#define SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */

Definition at line 216 of file stm32g0xx_hal_fdcan.c.

#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */

Definition at line 223 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CopyMessageToRAM().

#define SRAMCAN_TFQSA
Value:
((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start
                                                                                Address                  */

Definition at line 230 of file stm32g0xx_hal_fdcan.c.

Referenced by FDCAN_CalcultateRamBlockAddresses().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FDCAN Private Macros

Defines
FDCAN Private Macros
FDCAN

Defines

#define | IS_FDCAN_FRAME_FORMAT(FORMAT)
#define | IS_FDCAN_MODE(MODE)
#define | IS_FDCAN_CKDIV(CKDIV)
#define | IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
#define | IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
#define | IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
#define | IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
#define | IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
#define | IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
#define | IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
#define | IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
#define | IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
#define | IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
#define | IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE)
#define | IS_FDCAN_ID_TYPE(ID_TYPE)
#define | IS_FDCAN_FILTER_CFG(CONFIG)
#define | IS_FDCAN_TX_LOCATION(LOCATION)
#define | IS_FDCAN_TX_LOCATION_LIST(LOCATION)
#define | IS_FDCAN_RX_FIFO(FIFO)
#define | IS_FDCAN_RX_FIFO_MODE(MODE)
#define | IS_FDCAN_STD_FILTER_TYPE(TYPE)
#define | IS_FDCAN_EXT_FILTER_TYPE(TYPE)
#define | IS_FDCAN_FRAME_TYPE(TYPE)
#define | IS_FDCAN_DLC(DLC)
#define | IS_FDCAN_ESI(ESI)
#define | IS_FDCAN_BRS(BRS)
#define | IS_FDCAN_FDF(FDF)
#define | IS_FDCAN_EFC(EFC)
#define | IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
#define | IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
#define | IS_FDCAN_NON_MATCHING(DESTINATION)
#define | IS_FDCAN_REJECT_REMOTE(DESTINATION)
#define | IS_FDCAN_IT_LINE(IT_LINE)
#define | IS_FDCAN_TIMESTAMP(OPERATION)
#define | IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER)
#define | IS_FDCAN_TIMEOUT(OPERATION)
#define | FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Define Documentation

#define FDCAN_CHECK_FLAG | ( | __IR__,
 |  | __FLAG__
 | ) | ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Definition at line 1415 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define FDCAN_CHECK_IT_SOURCE | ( | __IE__,
 |  | __IT__
 | ) | ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 1413 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_IRQHandler().

#define IS_FDCAN_BRS ( BRS )
Value:
(((BRS) == FDCAN_BRS_OFF) || \
                           ((BRS) == FDCAN_BRS_ON ))

Definition at line 1375 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_CKDIV ( CKDIV )
Value:
(((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
                               ((CKDIV) == FDCAN_CLOCK_DIV30))

Definition at line 1303 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))

Definition at line 1323 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_SJW ( SJW ) (((SJW) >= 1U) && ((SJW) <= 16U))

Definition at line 1324 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_TSEG1 ( TSEG1 ) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))

Definition at line 1325 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DATA_TSEG2 ( TSEG2 ) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))

Definition at line 1326 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_DLC ( DLC )
Value:
(((DLC) == FDCAN_DLC_BYTES_0 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
                           ((DLC) == FDCAN_DLC_BYTES_12) || \
                           ((DLC) == FDCAN_DLC_BYTES_16) || \
                           ((DLC) == FDCAN_DLC_BYTES_20) || \
                           ((DLC) == FDCAN_DLC_BYTES_24) || \
                           ((DLC) == FDCAN_DLC_BYTES_32) || \
                           ((DLC) == FDCAN_DLC_BYTES_48) || \
                           ((DLC) == FDCAN_DLC_BYTES_64))

Definition at line 1357 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_EFC ( EFC )
Value:
(((EFC) == FDCAN_NO_TX_EVENTS   ) || \
                           ((EFC) == FDCAN_STORE_TX_EVENTS))

Definition at line 1379 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_ESI ( ESI )
Value:
(((ESI) == FDCAN_ESI_ACTIVE ) || \
                           ((ESI) == FDCAN_ESI_PASSIVE))

Definition at line 1373 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_EXT_FILTER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_FILTER_RANGE        ) || \
                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))

Definition at line 1351 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_FDF ( FDF )
Value:
(((FDF) == FDCAN_CLASSIC_CAN) || \
                           ((FDF) == FDCAN_FD_CAN     ))

Definition at line 1377 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_FILTER_CFG ( CONFIG )
Value:
(((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))

Definition at line 1333 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_FRAME_FORMAT ( FORMAT )
Value:
(((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))

Definition at line 1295 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_FRAME_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_DATA_FRAME  ) || \
                                   ((TYPE) == FDCAN_REMOTE_FRAME))

Definition at line 1355 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ().

#define IS_FDCAN_ID_TYPE ( ID_TYPE )
Value:
(((ID_TYPE) == FDCAN_STANDARD_ID) || \
                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))

Definition at line 1331 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ(), and HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_IT ( IT ) (((IT) & ~(FDCAN_IR_MASK)) == 0U)

Definition at line 1381 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_DeactivateNotification().

#define IS_FDCAN_IT_GROUP ( IT_GROUP ) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)

Definition at line 1382 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigInterruptLines().

#define IS_FDCAN_IT_LINE ( IT_LINE )
Value:
(((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))

Definition at line 1388 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigInterruptLines().

#define IS_FDCAN_MAX_VALUE | ( | VALUE,
 |  | _MAX_
 | ) | ((VALUE) <= (_MAX_))

Definition at line 1327 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), and HAL_FDCAN_Init().

#define IS_FDCAN_MIN_VALUE | ( | VALUE,
 |  | _MIN_
 | ) | ((VALUE) >= (_MIN_))

Definition at line 1328 of file stm32g0xx_hal_fdcan.h.

#define IS_FDCAN_MODE ( MODE )
Value:
(((MODE) == FDCAN_MODE_NORMAL              ) || \
                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))

Definition at line 1298 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))

Definition at line 1319 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_SJW ( SJW ) (((SJW) >= 1U) && ((SJW) <= 128U))

Definition at line 1320 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_TSEG1 ( TSEG1 ) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))

Definition at line 1321 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NOMINAL_TSEG2 ( TSEG2 ) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))

Definition at line 1322 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_NON_MATCHING ( DESTINATION )
Value:
(((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
                                            ((DESTINATION) == FDCAN_REJECT            ))

Definition at line 1383 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigGlobalFilter().

#define IS_FDCAN_REJECT_REMOTE ( DESTINATION )
Value:
(((DESTINATION) == FDCAN_FILTER_REMOTE) || \
                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))

Definition at line 1386 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigGlobalFilter().

#define IS_FDCAN_RX_FIFO ( FIFO )
Value:
(((FIFO) == FDCAN_RX_FIFO0) || \
                                ((FIFO) == FDCAN_RX_FIFO1))

Definition at line 1344 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_GetRxFifoFillLevel(), and HAL_FDCAN_GetRxMessage().

#define IS_FDCAN_RX_FIFO_MODE ( MODE )
Value:
(((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))

Definition at line 1346 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigRxFifoOverwrite().

#define IS_FDCAN_STD_FILTER_TYPE ( TYPE )
Value:
(((TYPE) == FDCAN_FILTER_RANGE) || \
                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
                                        ((TYPE) == FDCAN_FILTER_MASK ))

Definition at line 1348 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigFilter().

#define IS_FDCAN_TIMEOUT ( OPERATION )
Value:
(((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))

Definition at line 1408 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigTimeoutCounter().

#define IS_FDCAN_TIMESTAMP ( OPERATION )
Value:
(((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))

Definition at line 1390 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_EnableTimestampCounter().

#define IS_FDCAN_TIMESTAMP_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))

Definition at line 1392 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_ConfigTimestampCounter().

#define IS_FDCAN_TX_FIFO_QUEUE_MODE ( MODE )
Value:
(((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))

Definition at line 1329 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_Init().

#define IS_FDCAN_TX_LOCATION ( LOCATION )
Value:
(((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
                                        ((LOCATION) == FDCAN_TX_BUFFER2 ))

Definition at line 1340 of file stm32g0xx_hal_fdcan.h.

#define IS_FDCAN_TX_LOCATION_LIST ( LOCATION )
Value:
(((LOCATION) >= FDCAN_TX_BUFFER0) && \
                                             ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))

Definition at line 1342 of file stm32g0xx_hal_fdcan.h.

Referenced by HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), and HAL_FDCAN_IsTxBufferMessagePending().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Variable Documentation

FLASH_ProcessTypeDef pFlash
Initial value:
 {.Lock = HAL_UNLOCKED,
                                .ErrorCode = HAL_FLASH_ERROR_NONE,
                                .ProcedureOnGoing = FLASH_TYPENONE,
                                .Address = 0U,
                                .Banks = 0U,
                                .Page = 0U,
                                .NbPagesToErase = 0U
                               }

Variable used for Program/Erase sectors under interruption.

Definition at line 109 of file stm32g0xx_hal_flash.c.

Referenced by HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

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STM32G0C1xx HAL User Manual: FLASH Private Functions

Functions
FLASH Private Functions
FLASH

Functions

static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program double-word (64-bit) at a specified address.
static void | FLASH_Program_Fast (uint32_t Address, uint32_t DataAddress)
Fast program a 32 row double-word (64-bit) at a specified address.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Function Documentation

static void FLASH_Program_DoubleWord | ( | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  | [static]

Program double-word (64-bit) at a specified address.

Parameters:
Address | Specifies the address to be programmed.
Data | Specifies the data to be programmed.
Return values:
None

Definition at line 646 of file stm32g0xx_hal_flash.c.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static __RAM_FUNC void FLASH_Program_Fast | ( | uint32_t | Address,
 |  | uint32_t | DataAddress
 | ) |  | [static]

Fast program a 32 row double-word (64-bit) at a specified address.

Parameters:
Address | Specifies the address to be programmed.
DataAddress | Specifies the address where the data are stored.
Return values:
None

Definition at line 668 of file stm32g0xx_hal_flash.c.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 590 of file stm32g0xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode, FLASH_SR_CLEAR, FLASH_SR_ERRORS, and HAL_GetTick().

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

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STM32G0C1xx HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported Functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

 ===============================================================================
                  ##### Programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FLASH
    program operations.

Function Documentation

void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase: 0 Page Erase: Page which has been erased Program: Address which was selected for data program
Return values:
None

Definition at line 382 of file stm32g0xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

Handle FLASH interrupt request.

Return values:
None

Definition at line 282 of file stm32g0xx_hal_flash.c.

References FLASH_ProcessTypeDef::Address, FLASH_ProcessTypeDef::Banks, FLASH_ProcessTypeDef::ErrorCode, FLASH_PageErase(), FLASH_SR_ERRORS, FLASH_TYPEERASE_MASS, FLASH_TYPEERASE_PAGES, FLASH_TYPENONE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_TYPEPROGRAM_FAST, HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbPagesToErase, FLASH_ProcessTypeDef::Page, and FLASH_ProcessTypeDef::ProcedureOnGoing.

void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase: 0 Page Erase: Page number which returned an error Program: Address which was selected for data program
Return values:
None

Definition at line 400 of file stm32g0xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program double word or fast program of a row at a specified address.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Program Type
Address | Specifies the address to be programmed.
Data | Specifies the data to be programmed This parameter is the data for the double word program and the address where are stored the data for the row fast program depending on the TypeProgram: TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit) TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit).
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 164 of file stm32g0xx_hal_flash.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_FAST_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program double word or fast program of a row at a specified address with interrupt enabled.

Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Program Type
Address | Specifies the address to be programmed.
Data | Specifies the data to be programmed This parameter is the data for the double word program and the address where are stored the data for the row fast program depending on the TypeProgram: TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit) TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit).
Return values:
HAL Status

Definition at line 226 of file stm32g0xx_hal_flash.c.

References FLASH_ProcessTypeDef::Address, assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_FAST_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Lock the FLASH control register access.

Return values:
HAL Status

Definition at line 457 of file stm32g0xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Return values:
HAL Status

Definition at line 521 of file stm32g0xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Bytes Registers access.

Return values:
HAL Status

Definition at line 501 of file stm32g0xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Bytes Registers access.

Return values:
HAL Status

Definition at line 477 of file stm32g0xx_hal_flash.c.

References FLASH_OPTKEY1, and FLASH_OPTKEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control register access.

Return values:
HAL Status

Definition at line 433 of file stm32g0xx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FLASH Exported Functions

Peripheral Errors functions. More...

Functions

uint32_t HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Peripheral Errors functions.

 ===============================================================================
                ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time Errors of the FLASH peripheral.

Function Documentation

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
FLASH_ErrorCode The returned value can be
  • HAL_FLASH_ERROR_NONE No error set
  • HAL_FLASH_ERROR_OP Operation error
  • HAL_FLASH_ERROR_PROG Programming error
  • HAL_FLASH_ERROR_WRP Write protection error
  • HAL_FLASH_ERROR_PGA Programming alignment error
  • HAL_FLASH_ERROR_SIZ Size error
  • HAL_FLASH_ERROR_PGS Programming sequence error
  • HAL_FLASH_ERROR_MIS Fast programming data miss error
  • HAL_FLASH_ERROR_FAST Fast programming error
  • HAL_FLASH_ERROR_RD Read Protection error (PCROP)(*)
  • HAL_FLASH_ERROR_OPTV Option validity error
  • HAL_FLASH_ERROR_ECCD two ECC errors have been detected
Note:
(*) availability depends on devices

Definition at line 566 of file stm32g0xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32g0xx_hal_flash.h>

Data Fields

uint32_t | TypeErase
uint32_t | Banks
uint32_t | Page
uint32_t | NbPages

Detailed Description

FLASH Erase structure definition.

Definition at line 45 of file stm32g0xx_hal_flash.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::Banks

Select bank to erase. This parameter must be a value of FLASH Banks (FLASH_BANK_BOTH should be used only for mass erase)

Definition at line 49 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::NbPages

Number of pages to be erased. This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)

Definition at line 54 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::Page

Initial Flash page to erase when page erase is enabled This parameter must be a value between 0 and (FLASH_PAGE_NB - 1)

Definition at line 52 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

Mass erase or page erase. This parameter can be a value of FLASH Erase Type

Definition at line 47 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_flash.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Option Bytes Program structure definition. More...

#include <stm32g0xx_hal_flash.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPArea
uint32_t | WRPStartOffset
uint32_t | WRPEndOffset
uint32_t | RDPLevel
uint32_t | USERType
uint32_t | USERConfig
uint32_t | PCROPConfig
uint32_t | PCROP1AStartAddr
uint32_t | PCROP1AEndAddr
uint32_t | PCROP1BStartAddr
uint32_t | PCROP1BEndAddr
uint32_t | PCROP2AStartAddr
uint32_t | PCROP2AEndAddr
uint32_t | PCROP2BStartAddr
uint32_t | PCROP2BEndAddr
uint32_t | BootEntryPoint
uint32_t | SecSize
uint32_t | SecSize2

Detailed Description

FLASH Option Bytes Program structure definition.

Definition at line 61 of file stm32g0xx_hal_flash.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::BootEntryPoint

Allow to force a unique boot entry point to Flash or system Flash

Definition at line 121 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

Option byte to be configured. This parameter can be a combination of the values of FLASH Option Bytes Type

Definition at line 63 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP1AEndAddr

PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.

Definition at line 103 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP1AStartAddr

PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.

Definition at line 101 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP1BEndAddr

PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.

Definition at line 107 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP1BStartAddr

PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.

Definition at line 105 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP2AEndAddr

PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.

Definition at line 112 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP2AStartAddr

PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.

Definition at line 110 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP2BEndAddr

PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.

Definition at line 116 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP2BStartAddr

PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.

Definition at line 114 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPConfig

Configuration of the PCROP (used for OPTIONBYTE_PCROP). This parameter must be a combination of FLASH Option Bytes PCROP ZONE and FLASH Option Bytes PCROP On RDP Level Type. Note that once set, Pcrop erase on RDP level 1 regression (PCROP_RDP bit) can not be reset. It will be reset by mass erase

Definition at line 97 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::RDPLevel

Set the read protection level (used for OPTIONBYTE_RDP). This parameter can be a value of FLASH Option Bytes Read Protection

Definition at line 72 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecSize

This parameter defines securable memory area width in number of pages starting from Flash base address. This parameter must be a value between [0] and [FLASH_PAGE_NB], [0] meaning no secure area defined, [1] meaning first page only protected, etc...

Definition at line 122 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecSize2

This parameter defines securable memory area width in number of pages starting from 2nd Bank start address. This parameter must be a value between [0] and [FLASH_PAGE_NB], [0] meaning no secure area defined, [1] meaning first page only protected, etc...

Definition at line 126 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERConfig

Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of FLASH Option Bytes User BOR enable, FLASH Option Bytes User BOR Level, FLASH Option Bytes User reset config bit, FLASH Option Bytes User Reset On Stop, FLASH Option Bytes User Reset On Standby, FLASH Option Bytes User Reset On Shutdown, FLASH Option Bytes User IWDG Type, FLASH Option Bytes User IWDG Mode On Stop, FLASH Option Bytes User IWDG Mode On Standby, FLASH Option Bytes User WWDG Type, FLASH Option Bytes User SRAM parity, FLASH Option Bytes User bank swap Type, FLASH Option Bytes User dual bank enable Type, FLASH Option Bytes User Boot0 Selection, FLASH Option Bytes User BOOT1 Type, FLASH Option Bytes User nBOOT0 option bit, FLASH Option Bytes User input reset holder bit

Note:
(*) availability depends on devices

Definition at line 76 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERType

User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of FLASH Option Bytes User Type

Definition at line 74 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPArea

Write protection area to be programmed (used for OPTIONBYTE_WRP). Only one WRP area could be programmed at the same time. This parameter can be value of FLASH WRP Area

Definition at line 65 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPEndOffset

Write protection end offset (used for OPTIONBYTE_WRP). This parameter must be a value between WRPStartOffset and [FLASH_PAGE_NB - 1]

Definition at line 70 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPStartOffset

Write protection start offset (used for OPTIONBYTE_WRP). This parameter must be a value between 0 and [FLASH_PAGE_NB - 1]

Definition at line 68 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_flash.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32g0xx_hal_flash.h>

Data Fields

HAL_LockTypeDef | Lock
uint32_t | ErrorCode
uint32_t | ProcedureOnGoing
uint32_t | Address
uint32_t | Banks
uint32_t | Page
uint32_t | NbPagesToErase

Detailed Description

FLASH handle Structure definition.

Definition at line 136 of file stm32g0xx_hal_flash.h.

Field Documentation

uint32_t FLASH_ProcessTypeDef::Address

Definition at line 141 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

uint32_t FLASH_ProcessTypeDef::Banks

Definition at line 142 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_ProcessTypeDef::ErrorCode

Definition at line 139 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), HAL_FLASH_GetError(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

Definition at line 138 of file stm32g0xx_hal_flash.h.

uint32_t FLASH_ProcessTypeDef::NbPagesToErase

Definition at line 144 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_ProcessTypeDef::Page

Definition at line 143 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_ProcessTypeDef::ProcedureOnGoing

Definition at line 140 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_flash.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH Keys

Defines
FLASH Keys
FLASH Exported Constants

Defines

#define | FLASH_KEY1 0x45670123U
#define | FLASH_KEY2 0xCDEF89ABU
#define | FLASH_OPTKEY1 0x08192A3BU
#define | FLASH_OPTKEY2 0x4C5D6E7FU

Define Documentation

#define FLASH_KEY1 0x45670123U

Flash key1

Definition at line 158 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_KEY2 0xCDEF89ABU

Flash key2: used with FLASH_KEY1 to unlock the FLASH registers access

Definition at line 159 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_OPTKEY1 0x08192A3BU

Flash option byte key1

Definition at line 161 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_OPTKEY2 0x4C5D6E7FU

Flash option byte key2: used with FLASH_OPTKEY1 to allow option bytes operations

Definition at line 162 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 0x00000000UL
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

Define Documentation

#define FLASH_LATENCY_0 0x00000000UL

FLASH Zero wait state

Definition at line 171 of file stm32g0xx_hal_flash.h.

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0

FLASH One wait state

Definition at line 172 of file stm32g0xx_hal_flash.h.

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

FLASH Two wait states

Definition at line 173 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Flags Definition

Defines
FLASH Flags Definition
FLASH Exported Constants

Defines

#define | FLASH_FLAG_EOP ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_EOP_Pos)
#define | FLASH_FLAG_OPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPERR_Pos)
#define | FLASH_FLAG_PROGERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PROGERR_Pos)
#define | FLASH_FLAG_WRPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_WRPERR_Pos)
#define | FLASH_FLAG_PGAERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGAERR_Pos)
#define | FLASH_FLAG_SIZERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_SIZERR_Pos)
#define | FLASH_FLAG_PGSERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGSERR_Pos)
#define | FLASH_FLAG_MISERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_MISERR_Pos)
#define | FLASH_FLAG_FASTERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_FASTERR_Pos)
#define | FLASH_FLAG_RDERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_RDERR_Pos)
#define | FLASH_FLAG_OPTVERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPTVERR_Pos)
#define | FLASH_FLAG_BSY1 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY1_Pos)
#define | FLASH_FLAG_BSY2 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY2_Pos)
#define | FLASH_FLAG_BSY FLASH_FLAG_BSY1
#define | FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos)
#define | FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos)
#define | FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos)
#define | FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos)
#define | FLASH_FLAG_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCC_Pos)
#define | FLASH_FLAG_ECCD2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCD_Pos)
#define | FLASH_FLAG_ECCC FLASH_FLAG_ECCC1
#define | FLASH_FLAG_ECCD FLASH_FLAG_ECCD1

Define Documentation

#define FLASH_FLAG_BSY FLASH_FLAG_BSY1

FLASH Operation Busy flag - legacy name for single bank

Definition at line 198 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_BSY1 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY1_Pos)

FLASH Operation Busy flag for Bank 1

Definition at line 194 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_BSY2 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY2_Pos)

FLASH Operation Busy flag for Bank 2

Definition at line 196 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos)

FLASH Configuration Busy flag

Definition at line 199 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_ECCC FLASH_FLAG_ECCC1

FLASH ECC correction - legacy name for single bank

Definition at line 209 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos)

FLASH ECC correction on bank 1

Definition at line 203 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCC_Pos)

FLASH ECC correction on bank 2

Definition at line 206 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_ECCD FLASH_FLAG_ECCD1

FLASH ECC detection - legacy name for single bank

Definition at line 210 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos)

FLASH ECC detection on bank 1

Definition at line 204 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_ECCD2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCD_Pos)

FLASH ECC detection on bank 2

Definition at line 207 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_EOP ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_EOP_Pos)

FLASH End of operation flag

Definition at line 181 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_FASTERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_FASTERR_Pos)

FLASH Fast programming error flag

Definition at line 189 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_MISERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_MISERR_Pos)

FLASH Fast programming data miss error flag

Definition at line 188 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_OPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPERR_Pos)

FLASH Operation error flag

Definition at line 182 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_OPTVERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPTVERR_Pos)

FLASH Option validity error flag

Definition at line 193 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos)

FLASH Programming/erase operation suspended

Definition at line 201 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_PGAERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGAERR_Pos)

FLASH Programming alignment error flag

Definition at line 185 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_PGSERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGSERR_Pos)

FLASH Programming sequence error flag

Definition at line 187 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_PROGERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PROGERR_Pos)

FLASH Programming error flag

Definition at line 183 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_RDERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_RDERR_Pos)

FLASH PCROP read error flag

Definition at line 191 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_SIZERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_SIZERR_Pos)

FLASH Size error flag

Definition at line 186 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_WRPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_WRPERR_Pos)

FLASH Write protection error flag

Definition at line 184 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Interrupts Definition

Defines
FLASH Interrupts Definition
FLASH Exported Constants

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_EOPIE_Pos)
#define | FLASH_IT_OPERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_ERRIE_Pos)
#define | FLASH_IT_RDERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_RDERRIE_Pos)
#define | FLASH_IT_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCCIE_Pos)
#define | FLASH_IT_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCCIE_Pos)
#define | FLASH_IT_ECCC FLASH_IT_ECCC1

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_ECCC FLASH_IT_ECCC1

ECC Correction - legacy name for single bank

Definition at line 228 of file stm32g0xx_hal_flash.h.

#define FLASH_IT_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCCIE_Pos)

ECC Correction on Bank 1 Interrupt source

Definition at line 224 of file stm32g0xx_hal_flash.h.

#define FLASH_IT_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCCIE_Pos)

ECC Correction on Bank 2 Interrupt source

Definition at line 226 of file stm32g0xx_hal_flash.h.

#define FLASH_IT_EOP ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_EOPIE_Pos)

End of FLASH Operation Interrupt source

Definition at line 219 of file stm32g0xx_hal_flash.h.

#define FLASH_IT_OPERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_ERRIE_Pos)

Error Interrupt source

Definition at line 220 of file stm32g0xx_hal_flash.h.

#define FLASH_IT_RDERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_RDERRIE_Pos)

PCROP Read Error Interrupt source

Definition at line 222 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Error

Defines
FLASH Error
FLASH Exported Constants

Defines

#define | HAL_FLASH_ERROR_NONE 0x00000000U
#define | HAL_FLASH_ERROR_OP FLASH_SR_OPERR
#define | HAL_FLASH_ERROR_PROG FLASH_SR_PROGERR
#define | HAL_FLASH_ERROR_WRP FLASH_SR_WRPERR
#define | HAL_FLASH_ERROR_PGA FLASH_SR_PGAERR
#define | HAL_FLASH_ERROR_SIZ FLASH_SR_SIZERR
#define | HAL_FLASH_ERROR_PGS FLASH_SR_PGSERR
#define | HAL_FLASH_ERROR_MIS FLASH_SR_MISERR
#define | HAL_FLASH_ERROR_FAST FLASH_SR_FASTERR
#define | HAL_FLASH_ERROR_RD FLASH_SR_RDERR
#define | HAL_FLASH_ERROR_OPTV FLASH_SR_OPTVERR
#define | HAL_FLASH_ERROR_ECCD FLASH_ECCR_ECCD

Define Documentation

#define HAL_FLASH_ERROR_ECCD FLASH_ECCR_ECCD

Definition at line 249 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_FAST FLASH_SR_FASTERR

Definition at line 244 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_MIS FLASH_SR_MISERR

Definition at line 243 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_NONE 0x00000000U

Definition at line 236 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

#define HAL_FLASH_ERROR_OP FLASH_SR_OPERR

Definition at line 237 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_OPTV FLASH_SR_OPTVERR

Definition at line 248 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_PGA FLASH_SR_PGAERR

Definition at line 240 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_PGS FLASH_SR_PGSERR

Definition at line 242 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_PROG FLASH_SR_PROGERR

Definition at line 238 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_RD FLASH_SR_RDERR

Definition at line 246 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_SIZ FLASH_SR_SIZERR

Definition at line 241 of file stm32g0xx_hal_flash.h.

#define HAL_FLASH_ERROR_WRP FLASH_SR_WRPERR

Definition at line 239 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Erase Type

Defines
FLASH Erase Type
FLASH Exported Constants

Defines

#define | FLASH_TYPEERASE_PAGES FLASH_CR_PER
#define | FLASH_TYPEERASE_MASS FLASH_CR_MER1

Define Documentation

#define FLASH_TYPEERASE_MASS FLASH_CR_MER1

Flash mass erase activation

Definition at line 258 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_PAGES FLASH_CR_PER

Pages erase only

Definition at line 257 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

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STM32G0C1xx HAL User Manual: FLASH Banks

Defines
FLASH Banks
FLASH Exported Constants

Defines

#define | FLASH_BANK_1 FLASH_CR_MER1
#define | FLASH_BANK_2 FLASH_CR_MER2

Define Documentation

#define FLASH_BANK_1 FLASH_CR_MER1

Bank 1

Definition at line 266 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_PageErase(), HAL_FLASHEx_EnableSecMemProtection(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_BANK_2 FLASH_CR_MER2

Bank 2

Definition at line 268 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_EnableSecMemProtection().

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STM32G0C1xx HAL User Manual: FLASH Program Type

Defines
FLASH Program Type
FLASH Exported Constants

Defines

#define | FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG
#define | FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG

Define Documentation

#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG

Program a double-word (64-bit) at a specified address

Definition at line 278 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG

Fast program a 32 row double-word (64-bit) at a specified address

Definition at line 279 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

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STM32G0C1xx HAL User Manual: FLASH Option Bytes Type

Defines
FLASH Option Bytes Type
FLASH Exported Constants

Defines

#define | OPTIONBYTE_WRP 0x00000001U
#define | OPTIONBYTE_RDP 0x00000002U
#define | OPTIONBYTE_USER 0x00000004U
#define | OPTIONBYTE_PCROP 0x00000008U
#define | OPTIONBYTE_SEC 0x00000010U
#define | OPTIONBYTE_ALL

Define Documentation

#define OPTIONBYTE_ALL
Value:
(OPTIONBYTE_WRP   | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
                                         OPTIONBYTE_PCROP | OPTIONBYTE_SEC)

All option byte configuration

Definition at line 298 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig().

#define OPTIONBYTE_PCROP 0x00000008U

PCROP option byte configuration

Definition at line 291 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP 0x00000002U

RDP option byte configuration

Definition at line 288 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_SEC 0x00000010U

SEC option byte configuration

Definition at line 294 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER 0x00000004U

USER option byte configuration

Definition at line 289 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP 0x00000001U

WRP option byte configuration

Definition at line 287 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

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STM32G0C1xx HAL User Manual: FLASH WRP Area

Defines
FLASH WRP Area
FLASH Exported Constants

Defines

#define | OB_WRPAREA_ZONE_A 0x00000001U
#define | OB_WRPAREA_ZONE_B 0x00000002U
#define | OB_WRPAREA_ZONE2_A 0x00000004U
#define | OB_WRPAREA_ZONE2_B 0x00000008U

Define Documentation

#define OB_WRPAREA_ZONE2_A 0x00000004U

Flash Bank 2 Zone A

Definition at line 313 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define OB_WRPAREA_ZONE2_B 0x00000008U

Flash Bank 2 Zone B

Definition at line 314 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define OB_WRPAREA_ZONE_A 0x00000001U

Flash Zone A

Definition at line 310 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define OB_WRPAREA_ZONE_B 0x00000002U

Flash Zone B

Definition at line 311 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes Read Protection

Defines
FLASH Option Bytes Read Protection
FLASH Exported Constants

Defines

#define | OB_RDP_LEVEL_0 0x000000AAU
#define | OB_RDP_LEVEL_1 0x000000BBU
#define | OB_RDP_LEVEL_2 0x000000CCU

Define Documentation

#define OB_RDP_LEVEL_0 0x000000AAU

Definition at line 323 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_1 0x000000BBU

Definition at line 324 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_2 0x000000CCU

Warning: When enabling read protection level 2 it is no more possible to go back to level 1 or 0

Definition at line 325 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User Type

Defines
FLASH Option Bytes User Type
FLASH Exported Constants

Defines

#define | OB_USER_BOR_EN FLASH_OPTR_BOR_EN
#define | OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV)
#define | OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP
#define | OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY
#define | OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW
#define | OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW
#define | OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP
#define | OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY
#define | OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW
#define | OB_USER_BANK_SWAP FLASH_OPTR_nSWAP_BANK
#define | OB_USER_DUAL_BANK FLASH_OPTR_DUAL_BANK
#define | OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK
#define | OB_USER_nBOOT_SEL FLASH_OPTR_nBOOT_SEL
#define | OB_USER_nBOOT1 FLASH_OPTR_nBOOT1
#define | OB_USER_nBOOT0 FLASH_OPTR_nBOOT0
#define | OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE
#define | OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN
#define | OB_USER_ALL

Define Documentation

#define OB_USER_ALL
Value:
(OB_USER_BOR_EN           | OB_USER_BOR_LEV    | OB_USER_nRST_STOP | \
                                         OB_USER_nRST_STDBY       | OB_USER_nRST_SHDW  | OB_USER_IWDG_SW   | \
                                         OB_USER_IWDG_STOP        | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | \
                                         OB_USER_BANK_SWAP        | OB_USER_DUAL_BANK                      | \
                                         OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL  | OB_USER_nBOOT1    | \
                                         OB_USER_nBOOT0           | OB_USER_NRST_MODE  | OB_USER_INPUT_RESET_HOLDER)

all option bits

Definition at line 364 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetUser(), and HAL_FLASHEx_OBGetConfig().

#define OB_USER_BANK_SWAP FLASH_OPTR_nSWAP_BANK

Swap bank memory addresses

Definition at line 348 of file stm32g0xx_hal_flash.h.

#define OB_USER_BOR_EN FLASH_OPTR_BOR_EN

BOR reset enable

Definition at line 335 of file stm32g0xx_hal_flash.h.

#define OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV)

BOR reset Level

Definition at line 336 of file stm32g0xx_hal_flash.h.

#define OB_USER_DUAL_BANK FLASH_OPTR_DUAL_BANK

Select single or dual bank (depending of device memory size)

Definition at line 349 of file stm32g0xx_hal_flash.h.

#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN

Internal reset holder enable

Definition at line 359 of file stm32g0xx_hal_flash.h.

#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY

Independent watchdog counter freeze in standby mode

Definition at line 345 of file stm32g0xx_hal_flash.h.

#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP

Independent watchdog counter freeze in stop mode

Definition at line 344 of file stm32g0xx_hal_flash.h.

#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW

Independent watchdog selection

Definition at line 343 of file stm32g0xx_hal_flash.h.

#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0

nBoot0 configuration

Definition at line 354 of file stm32g0xx_hal_flash.h.

#define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1

nBoot1 configuration

Definition at line 353 of file stm32g0xx_hal_flash.h.

#define OB_USER_nBOOT_SEL FLASH_OPTR_nBOOT_SEL

Boot Selection

Definition at line 352 of file stm32g0xx_hal_flash.h.

#define OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE

Reset pin configuration

Definition at line 356 of file stm32g0xx_hal_flash.h.

#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW

Reset generated when entering the shutdown mode

Definition at line 341 of file stm32g0xx_hal_flash.h.

#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY

Reset generated when entering the standby mode

Definition at line 339 of file stm32g0xx_hal_flash.h.

#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP

Reset generated when entering the stop mode

Definition at line 338 of file stm32g0xx_hal_flash.h.

#define OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK

Sram parity check control

Definition at line 351 of file stm32g0xx_hal_flash.h.

#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW

Window watchdog selection

Definition at line 346 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User BOR enable

Defines
FLASH Option Bytes User BOR enable
FLASH Exported Constants

Defines

#define | OB_BOR_DISABLE 0x00000000U
#define | OB_BOR_ENABLE FLASH_OPTR_BOR_EN

Define Documentation

#define OB_BOR_DISABLE 0x00000000U

BOR Reset set to default

Definition at line 401 of file stm32g0xx_hal_flash.h.

#define OB_BOR_ENABLE FLASH_OPTR_BOR_EN

Use option byte to define BOR thresholds

Definition at line 402 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User BOR Level

Defines
FLASH Option Bytes User BOR Level
FLASH Exported Constants

Defines

#define | OB_BOR_LEVEL_FALLING_0 0x00000000U
#define | OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0
#define | OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1
#define | OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1)
#define | OB_BOR_LEVEL_RISING_0 0x00000000U
#define | OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0
#define | OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1
#define | OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1)

Define Documentation

#define OB_BOR_LEVEL_FALLING_0 0x00000000U

BOR falling level 1 with threshold around 2.0V

Definition at line 410 of file stm32g0xx_hal_flash.h.

#define OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0

BOR falling level 2 with threshold around 2.2V

Definition at line 411 of file stm32g0xx_hal_flash.h.

#define OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1

BOR falling level 3 with threshold around 2.5V

Definition at line 412 of file stm32g0xx_hal_flash.h.

#define OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1)

BOR falling level 4 with threshold around 2.8V

Definition at line 413 of file stm32g0xx_hal_flash.h.

#define OB_BOR_LEVEL_RISING_0 0x00000000U

BOR rising level 1 with threshold around 2.1V

Definition at line 414 of file stm32g0xx_hal_flash.h.

#define OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0

BOR rising level 2 with threshold around 2.3V

Definition at line 415 of file stm32g0xx_hal_flash.h.

#define OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1

BOR rising level 3 with threshold around 2.6V

Definition at line 416 of file stm32g0xx_hal_flash.h.

#define OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1)

BOR rising level 4 with threshold around 2.9V

Definition at line 417 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User Reset On Stop

Defines
FLASH Option Bytes User Reset On Stop
FLASH Exported Constants

Defines

#define | OB_STOP_RST 0x00000000U
#define | OB_STOP_NORST FLASH_OPTR_nRST_STOP

Define Documentation

#define OB_STOP_NORST FLASH_OPTR_nRST_STOP

No reset generated when entering the stop mode

Definition at line 427 of file stm32g0xx_hal_flash.h.

#define OB_STOP_RST 0x00000000U

Reset generated when entering the stop mode

Definition at line 426 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User Reset On Standby

Defines
FLASH Option Bytes User Reset On Standby
FLASH Exported Constants

Defines

#define | OB_STANDBY_RST 0x00000000U
#define | OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY

Define Documentation

#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY

No reset generated when entering the standby mode

Definition at line 436 of file stm32g0xx_hal_flash.h.

#define OB_STANDBY_RST 0x00000000U

Reset generated when entering the standby mode

Definition at line 435 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User Reset On Shutdown

Defines
FLASH Option Bytes User Reset On Shutdown
FLASH Exported Constants

Defines

#define | OB_SHUTDOWN_RST 0x00000000U
#define | OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW

Define Documentation

#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW

No reset generated when entering the shutdown mode

Definition at line 446 of file stm32g0xx_hal_flash.h.

#define OB_SHUTDOWN_RST 0x00000000U

Reset generated when entering the shutdown mode

Definition at line 445 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User IWDG Type

Defines
FLASH Option Bytes User IWDG Type
FLASH Exported Constants

Defines

#define | OB_IWDG_HW 0x00000000U
#define | OB_IWDG_SW FLASH_OPTR_IWDG_SW

Define Documentation

#define OB_IWDG_HW 0x00000000U

Hardware independent watchdog

Definition at line 455 of file stm32g0xx_hal_flash.h.

#define OB_IWDG_SW FLASH_OPTR_IWDG_SW

Software independent watchdog

Definition at line 456 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User IWDG Mode On Stop

Defines
FLASH Option Bytes User IWDG Mode On Stop
FLASH Exported Constants

Defines

#define | OB_IWDG_STOP_FREEZE 0x00000000U
#define | OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP

Define Documentation

#define OB_IWDG_STOP_FREEZE 0x00000000U

Independent watchdog counter is frozen in Stop mode

Definition at line 464 of file stm32g0xx_hal_flash.h.

#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP

Independent watchdog counter is running in Stop mode

Definition at line 465 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User IWDG Mode On Standby

Defines
FLASH Option Bytes User IWDG Mode On Standby
FLASH Exported Constants

Defines

#define | OB_IWDG_STDBY_FREEZE 0x00000000U
#define | OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY

Define Documentation

#define OB_IWDG_STDBY_FREEZE 0x00000000U

Independent watchdog counter is frozen in Standby mode

Definition at line 473 of file stm32g0xx_hal_flash.h.

#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY

Independent watchdog counter is running in Standby mode

Definition at line 474 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User WWDG Type

Defines
FLASH Option Bytes User WWDG Type
FLASH Exported Constants

Defines

#define | OB_WWDG_HW 0x00000000U
#define | OB_WWDG_SW FLASH_OPTR_WWDG_SW

Define Documentation

#define OB_WWDG_HW 0x00000000U

Hardware window watchdog

Definition at line 482 of file stm32g0xx_hal_flash.h.

#define OB_WWDG_SW FLASH_OPTR_WWDG_SW

Software window watchdog

Definition at line 483 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User bank swap Type

Defines
FLASH Option Bytes User bank swap Type
FLASH Exported Constants

Defines

#define | OB_USER_DUALBANK_SWAP_ENABLE 0x00000000U
#define | OB_USER_DUALBANK_SWAP_DISABLE FLASH_OPTR_nSWAP_BANK

Define Documentation

#define OB_USER_DUALBANK_SWAP_DISABLE FLASH_OPTR_nSWAP_BANK

Disable bank swap

Definition at line 493 of file stm32g0xx_hal_flash.h.

#define OB_USER_DUALBANK_SWAP_ENABLE 0x00000000U

Enable bank swap

Definition at line 492 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User dual bank enable Type

Defines
FLASH Option Bytes User dual bank enable Type
FLASH Exported Constants

Defines

#define | OB_USER_DUALBANK_DISABLE 0x00000000U
#define | OB_USER_DUALBANK_ENABLE FLASH_OPTR_DUAL_BANK

Define Documentation

#define OB_USER_DUALBANK_DISABLE 0x00000000U

Disable dual bank

Definition at line 501 of file stm32g0xx_hal_flash.h.

#define OB_USER_DUALBANK_ENABLE FLASH_OPTR_DUAL_BANK

Enable dual bank

Definition at line 502 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User SRAM parity

Defines
FLASH Option Bytes User SRAM parity
FLASH Exported Constants

Defines

#define | OB_SRAM_PARITY_ENABLE 0x00000000U
#define | OB_SRAM_PARITY_DISABLE FLASH_OPTR_RAM_PARITY_CHECK

Define Documentation

#define OB_SRAM_PARITY_DISABLE FLASH_OPTR_RAM_PARITY_CHECK

Sram parity disable

Definition at line 512 of file stm32g0xx_hal_flash.h.

#define OB_SRAM_PARITY_ENABLE 0x00000000U

Sram parity enable

Definition at line 511 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User Boot0 Selection

Defines
FLASH Option Bytes User Boot0 Selection
FLASH Exported Constants

Defines

#define | OB_BOOT0_FROM_PIN 0x00000000U
#define | OB_BOOT0_FROM_OB FLASH_OPTR_nBOOT_SEL

Define Documentation

#define OB_BOOT0_FROM_OB FLASH_OPTR_nBOOT_SEL

BOOT0 signal is defined by nBOOT0 option bit

Definition at line 521 of file stm32g0xx_hal_flash.h.

#define OB_BOOT0_FROM_PIN 0x00000000U

BOOT0 signal is defined by PA14/BOOT0 pin value

Definition at line 520 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User BOOT1 Type

Defines
FLASH Option Bytes User BOOT1 Type
FLASH Exported Constants

Defines

#define | OB_BOOT1_SRAM 0x00000000U
#define | OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1

Define Documentation

#define OB_BOOT1_SRAM 0x00000000U

Embedded SRAM is selected as boot space (if nBOOT0=0 or BOOT0_pin=1)

Definition at line 529 of file stm32g0xx_hal_flash.h.

#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1

System memory is selected as boot space (if nBOOT0=0 or BOOT0_pin=1)

Definition at line 530 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User nBOOT0 option bit

Defines
FLASH Option Bytes User nBOOT0 option bit
FLASH Exported Constants

Defines

#define | OB_nBOOT0_RESET 0x00000000U
#define | OB_nBOOT0_SET FLASH_OPTR_nBOOT0

Define Documentation

#define OB_nBOOT0_RESET 0x00000000U

nBOOT0 = 0

Definition at line 538 of file stm32g0xx_hal_flash.h.

#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0

nBOOT0 = 1

Definition at line 539 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User reset config bit

Defines
FLASH Option Bytes User reset config bit
FLASH Exported Constants

Defines

#define | OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0
#define | OB_RESET_MODE_GPIO FLASH_OPTR_NRST_MODE_1
#define | OB_RESET_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE

Define Documentation

#define OB_RESET_MODE_GPIO FLASH_OPTR_NRST_MODE_1

Reset pin is in GPIO mode mode only

Definition at line 549 of file stm32g0xx_hal_flash.h.

#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0

Reset pin is in Reset input mode only

Definition at line 548 of file stm32g0xx_hal_flash.h.

#define OB_RESET_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE

Reset pin is in reset input and output mode

Definition at line 550 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes User input reset holder bit

Defines
FLASH Option Bytes User input reset holder bit
FLASH Exported Constants

Defines

#define | OB_IRH_ENABLE 0x00000000U
#define | OB_IRH_DISABLE FLASH_OPTR_IRHEN

Define Documentation

#define OB_IRH_DISABLE FLASH_OPTR_IRHEN

Internal Reset handler disable

Definition at line 561 of file stm32g0xx_hal_flash.h.

#define OB_IRH_ENABLE 0x00000000U

Internal Reset handler enable

Definition at line 560 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes PCROP ZONE

Defines
FLASH Option Bytes PCROP ZONE
FLASH Exported Constants

Defines

#define | OB_PCROP_ZONE_A 0x00000001U
#define | OB_PCROP_ZONE_B 0x00000002U
#define | OB_PCROP_ZONE2_A 0x00000004U
#define | OB_PCROP_ZONE2_B 0x00000008U

Define Documentation

#define OB_PCROP_ZONE2_A 0x00000004U

PCROP Bank 2 Zone A

Definition at line 574 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OB_PCROP_ZONE2_B 0x00000008U

PCROP Bank 2 Zone B

Definition at line 575 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OB_PCROP_ZONE_A 0x00000001U

PCROP Zone A

Definition at line 571 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_PCROP1AConfig(), HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OB_PCROP_ZONE_B 0x00000002U

PCROP Zone B

Definition at line 572 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

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STM32G0C1xx HAL User Manual: FLASH Option Bytes PCROP On RDP Level Type

Defines
FLASH Option Bytes PCROP On RDP Level Type
FLASH Exported Constants

Defines

#define | OB_PCROP_RDP_NOT_ERASE 0x00000000U
#define | OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP

Define Documentation

#define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP

PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase). Once this bit is set only, it will be reset by mass erase

Definition at line 586 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP1A(), FLASH_OB_PCROP1AConfig(), and HAL_FLASHEx_OBProgram().

#define OB_PCROP_RDP_NOT_ERASE 0x00000000U

PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0

Definition at line 584 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Option Bytes Secure boot lock

Defines
FLASH Option Bytes Secure boot lock
FLASH Exported Constants

Defines

#define | OB_BOOT_ENTRY_FORCED_NONE 0x00000000U
#define | OB_BOOT_ENTRY_FORCED_FLASH FLASH_SECR_BOOT_LOCK

Define Documentation

#define OB_BOOT_ENTRY_FORCED_FLASH FLASH_SECR_BOOT_LOCK

Boot entry is forced to Flash or System Flash

Definition at line 599 of file stm32g0xx_hal_flash.h.

#define OB_BOOT_ENTRY_FORCED_NONE 0x00000000U

Boot entry is free

Definition at line 598 of file stm32g0xx_hal_flash.h.

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STM32G0C1xx HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH

macros to control FLASH features More...

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Disable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Reset the FLASH instruction Cache.

Detailed Description

macros to control FLASH features

Define Documentation

#define __HAL_FLASH_GET_LATENCY ( ) READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)

Get the FLASH Latency.

Return values:
FLASH Latency Returned value can be one of the following values :
  • FLASH_LATENCY_0 FLASH Zero wait state
  • FLASH_LATENCY_1 FLASH One wait state
  • FLASH_LATENCY_2 FLASH Two wait states

Definition at line 634 of file stm32g0xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)

Disable the FLASH instruction cache.

Return values:
none

Definition at line 658 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_FlushCaches(), and HAL_Init().

#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)

Enable the FLASH instruction cache.

Return values:
none

Definition at line 652 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_INSTRUCTION_CACHE_RESET ( )
Value:
do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
                                                   } while (0U)

Reset the FLASH instruction Cache.

Note:
This function must be used only when the Instruction Cache is disabled.
Return values:
None

Definition at line 665 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)

Disable the FLASH prefetch buffer.

Return values:
None

Definition at line 646 of file stm32g0xx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)

Enable the FLASH prefetch buffer.

Return values:
None

Definition at line 640 of file stm32g0xx_hal_flash.h.

Referenced by HAL_Init().

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__ FLASH Latency This parameter can be one of the following values :
  • FLASH_LATENCY_0 FLASH Zero wait state
  • FLASH_LATENCY_1 FLASH One wait state
  • FLASH_LATENCY_2 FLASH Two wait states
Return values:
None

Definition at line 624 of file stm32g0xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

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STM32G0C1xx HAL User Manual: FLASH Interrupts Macros

Defines
FLASH Interrupts Macros
FLASH

macros to handle FLASH interrupts More...

Defines

#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Check whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the FLASH pending flags.

Detailed Description

macros to handle FLASH interrupts

Define Documentation

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ )
Value:
do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U)         { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); }    \
                                                     else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); }  \
                                                     else if(((__FLAG__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECC2R = (1uL << ((__FLAG__) & 0x1Fu)); }  \
                                                   } while(0U)

Clear the FLASH pending flags.

Parameters:
__FLAG__ specifies the FLASH flags to clear. This parameter can be one of the following values :
  • FLASH_FLAG_EOP FLASH End of Operation flag
  • FLASH_FLAG_OPERR FLASH Operation error flag
  • FLASH_FLAG_PROGERR FLASH Programming error flag
  • FLASH_FLAG_WRPERR FLASH Write protection error flag
  • FLASH_FLAG_PGAERR FLASH Programming alignment error flag
  • FLASH_FLAG_SIZERR FLASH Size error flag
  • FLASH_FLAG_PGSERR FLASH Programming sequence error flag
  • FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
  • FLASH_FLAG_FASTERR FLASH Fast programming error flag
  • FLASH_FLAG_RDERR FLASH PCROP read error flag
  • FLASH_FLAG_OPTVERR FLASH Option validity error flag
  • FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
  • FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1
  • FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*)
  • FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*)
  • FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank
  • FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank
Note:
(*) availability depends on devices
Return values:
None

Definition at line 790 of file stm32g0xx_hal_flash.h.

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ )
Value:
do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }             \
                                                     else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }   \
                                                     else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); }  \
                                                   } while(0U)

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be one of the following values :
  • FLASH_IT_EOP End of FLASH Operation Interrupt
  • FLASH_IT_OPERR Error Interrupt
  • FLASH_IT_RDERR PCROP Read Error Interrupt(*)
  • FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1
  • FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*)
  • FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank
Note:
(*) availability depends on devices
Return values:
none

Definition at line 715 of file stm32g0xx_hal_flash.h.

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ )
Value:
do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }             \
                                                     else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }   \
                                                     else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); }  \
                                                   } while(0U)

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be one of the following values :
  • FLASH_IT_EOP End of FLASH Operation Interrupt
  • FLASH_IT_OPERR Error Interrupt
  • FLASH_IT_RDERR PCROP Read Error Interrupt(*)
  • FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1
  • FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*)
  • FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank
Note:
(*) availability depends on devices
Return values:
none

Definition at line 691 of file stm32g0xx_hal_flash.h.

#define __HAL_FLASH_GET_FLAG ( __FLAG__ )
Value:
((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ?             \
                                                 (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) :        \
                                                 ((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
                                                  (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) :      \
                                                  (READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)))

Check whether the specified FLASH flag is set or not.

Parameters:
__FLAG__ specifies the FLASH flag to check. This parameter can be one of the following values :
  • FLASH_FLAG_EOP FLASH End of Operation flag
  • FLASH_FLAG_OPERR FLASH Operation error flag
  • FLASH_FLAG_PROGERR FLASH Programming error flag
  • FLASH_FLAG_WRPERR FLASH Write protection error flag
  • FLASH_FLAG_PGAERR FLASH Programming alignment error flag
  • FLASH_FLAG_SIZERR FLASH Size error flag
  • FLASH_FLAG_PGSERR FLASH Programming sequence error flag
  • FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
  • FLASH_FLAG_FASTERR FLASH Fast programming error flag
  • FLASH_FLAG_RDERR FLASH PCROP read error flag(*)
  • FLASH_FLAG_OPTVERR FLASH Option validity error flag
  • FLASH_FLAG_BSY1 FLASH bank 1 write/erase operations in progress flag
  • FLASH_FLAG_BSY2 FLASH bank 2 write/erase operations in progress flag(*)
  • FLASH_FLAG_BSY FLASH write/erase operations in progress flag - legacy name for single bank
  • FLASH_FLAG_CFGBSY FLASH configuration is busy : program or erase setting are used.
  • FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
  • FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1
  • FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*)
  • FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*)
  • FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank
  • FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank
Note:
(*) availability depends on devices
Return values:
The state of FLASH_FLAG (SET or RESET).

Definition at line 754 of file stm32g0xx_hal_flash.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH Exported Variables

Variables
FLASH Exported Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Variable Documentation

FLASH_ProcessTypeDef pFlash

Variable used for Program/Erase sectors under interruption.

Definition at line 109 of file stm32g0xx_hal_flash.c.

Referenced by HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH Private Types

Functions
FLASH Private Types
FLASH

Functions

HAL_StatusTypeDef FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Function Documentation

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 590 of file stm32g0xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode, FLASH_SR_CLEAR, FLASH_SR_ERRORS, and HAL_GetTick().

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define | FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
#define | OB_DUAL_BANK_BASE (FLASH_R_BASE + 0x20U)
#define | FLASH_SALES_TYPE_Pos (24U)
#define | FLASH_SALES_TYPE (0x3UL << FLASH_SALES_TYPE_Pos)
#define | FLASH_SALES_TYPE_0 (0x1UL << FLASH_SALES_TYPE_Pos)
#define | FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos)
#define | FLASH_SALES_VALUE ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE))
#define | OB_DUAL_BANK_VALUE ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK))
#define | FLASH_BANK_NB
#define | FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U))
#define | FLASH_PAGE_SIZE 0x00000800U
#define | FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of pages per bank */
#define | FLASH_TIMEOUT_VALUE 1000U
#define | FLASH_TYPENONE 0x00000000U
#define | FLASH_SR_ERRORS
#define | FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD)
#define | FLASH_FLAG_REG_POS 16u
#define | FLASH_FLAG_SR_ID 1u
#define | FLASH_FLAG_CR_ID 2u
#define | FLASH_FLAG_ECCR1_ID 4u
#define | FLASH_FLAG_ECCR2_ID 8u

Define Documentation

#define FLASH_BANK_NB
Value:
(((FLASH_SALES_VALUE == 0U)\
                                          || ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U)

Definition at line 884 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP1A(), FLASH_OB_GetPCROP1B(), FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), and FLASH_OB_SecMemConfig().

#define FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U))

FLASH Bank Size. Divided by 2 if 2 Banks

Definition at line 886 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP1A(), FLASH_OB_GetPCROP1B(), FLASH_OB_GetPCROP2A(), FLASH_OB_GetPCROP2B(), FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), FLASH_OB_PCROP2AConfig(), and FLASH_OB_PCROP2BConfig().

#define FLASH_FLAG_CR_ID 2u

Definition at line 917 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_ECCR1_ID 4u

Definition at line 918 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_ECCR2_ID 8u

Definition at line 919 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_REG_POS 16u

Definition at line 915 of file stm32g0xx_hal_flash.h.

#define FLASH_FLAG_SR_ID 1u

Definition at line 916 of file stm32g0xx_hal_flash.h.

#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of pages per bank */

Definition at line 892 of file stm32g0xx_hal_flash.h.

#define FLASH_PAGE_SIZE 0x00000800U

FLASH Page Size, 2 KBytes

Definition at line 891 of file stm32g0xx_hal_flash.h.

#define FLASH_SALES_TYPE (0x3UL << FLASH_SALES_TYPE_Pos)

0x000001E0

Definition at line 879 of file stm32g0xx_hal_flash.h.

#define FLASH_SALES_TYPE_0 (0x1UL << FLASH_SALES_TYPE_Pos)

0x01000000

Definition at line 880 of file stm32g0xx_hal_flash.h.

#define FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos)

0x02000000

Definition at line 881 of file stm32g0xx_hal_flash.h.

#define FLASH_SALES_TYPE_Pos (24U)

Definition at line 878 of file stm32g0xx_hal_flash.h.

#define FLASH_SALES_VALUE ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE))

Definition at line 882 of file stm32g0xx_hal_flash.h.

#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE

Definition at line 874 of file stm32g0xx_hal_flash.h.

#define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD)

Definition at line 909 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_SR_ERRORS
Value:
(FLASH_SR_OPERR  | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \
                                         FLASH_SR_PGAERR | FLASH_SR_SIZERR  | FLASH_SR_PGSERR |  \
                                         FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR |   \
                                         FLASH_SR_OPTVERR)

All SR error flags

Definition at line 897 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_TIMEOUT_VALUE 1000U

FLASH Execution Timeout, 1 s

Definition at line 893 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

#define FLASH_TYPENONE 0x00000000U

No programming Procedure On Going

Definition at line 894 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define OB_DUAL_BANK_BASE (FLASH_R_BASE + 0x20U)

Not use cmsis FLASH alias to avoid iar warning about volatile reading sequence

Definition at line 877 of file stm32g0xx_hal_flash.h.

#define OB_DUAL_BANK_VALUE ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK))

Definition at line 883 of file stm32g0xx_hal_flash.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH Private Macros

Defines
FLASH Private Macros
FLASH

Defines

#define | IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__)
#define | IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB)
#define | IS_FLASH_BANK(__BANK__)
#define | IS_FLASH_TYPEERASE(__VALUE__)
#define | IS_FLASH_TYPEPROGRAM(__VALUE__)
#define | IS_OPTIONBYTE(__VALUE__)
#define | IS_OB_WRPAREA(__VALUE__)
#define | IS_OB_RDP_LEVEL(__LEVEL__)
#define | IS_OB_USER_TYPE(__TYPE__)
#define | IS_OB_USER_CONFIG(__TYPE__, __CONFIG__) ((~(__TYPE__) & (__CONFIG__)) == 0x00U)
#define | IS_OB_PCROP_CONFIG(__CONFIG__)
#define | IS_OB_SEC_BOOT_LOCK(__VALUE__)
#define | IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U))
#define | IS_FLASH_LATENCY(__LATENCY__)

Define Documentation

#define IS_FLASH_BANK ( __BANK__ )
Value:
((FLASH_BANK_NB == 2U) ?                         \
   (((__BANK__) == FLASH_BANK_1)  ||               \
    ((__BANK__) == FLASH_BANK_2)  ||                \
    ((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \
   ((__BANK__) == FLASH_BANK_1))

Definition at line 954 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_PageErase(), and HAL_FLASHEx_EnableSecMemProtection().

#define IS_FLASH_FAST_PROGRAM_ADDRESS ( __ADDRESS__ )
Value:
(((__ADDRESS__) >= (FLASH_BASE))\
                                                        && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL)))

Definition at line 948 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_LATENCY ( __LATENCY__ )
Value:
(((__LATENCY__) == FLASH_LATENCY_0) || \
                                                        ((__LATENCY__) == FLASH_LATENCY_1) || \
                                                        ((__LATENCY__) == FLASH_LATENCY_2))

Definition at line 1013 of file stm32g0xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS ( __ADDRESS__ )
Value:
(((__ADDRESS__) >= (FLASH_BASE))\
                                                           && ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL)))

Definition at line 932 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), FLASH_OB_PCROP2AConfig(), and FLASH_OB_PCROP2BConfig().

#define IS_FLASH_MAIN_MEM_ADDRESS ( __ADDRESS__ )
Value:
(((__ADDRESS__) >= (FLASH_BASE))\
                                                        && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))

Definition at line 929 of file stm32g0xx_hal_flash.h.

#define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS ( __ADDRESS__ )
Value:
(((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE))\
                                                           && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))

Definition at line 935 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), FLASH_OB_PCROP2AConfig(), and FLASH_OB_PCROP2BConfig().

#define IS_FLASH_PAGE ( __PAGE__ ) ((__PAGE__) < FLASH_PAGE_NB)

Definition at line 951 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_WRPConfig(), and FLASH_PageErase().

#define IS_FLASH_PROGRAM_ADDRESS ( __ADDRESS__ )
Value:
((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__))\
                                                        || (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__)))

Definition at line 945 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS ( __ADDRESS__ )
Value:
(((__ADDRESS__) >= (FLASH_BASE))\
                                                        && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL)))

Definition at line 939 of file stm32g0xx_hal_flash.h.

#define IS_FLASH_PROGRAM_OTP_ADDRESS ( __ADDRESS__ )
Value:
(((__ADDRESS__) >= 0x1FFF7000U)\
                                                        && ((__ADDRESS__) <= (0x1FFF7400U - 8UL)))

Definition at line 942 of file stm32g0xx_hal_flash.h.

#define IS_FLASH_TYPEERASE ( __VALUE__ )
Value:
(((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
                                                        ((__VALUE__) == FLASH_TYPEERASE_MASS))

Definition at line 964 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_TYPEPROGRAM ( __VALUE__ )
Value:
(((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
                                                        ((__VALUE__) == FLASH_TYPEPROGRAM_FAST))

Definition at line 967 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_OB_PCROP_CONFIG ( __CONFIG__ )
Value:
((FLASH_BANK_NB == 2U) ?                                                                    \
   (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B |                                     \
                      OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U):   \
   (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U))

Definition at line 995 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_PCROP1AConfig(), and HAL_FLASHEx_OBProgram().

#define IS_OB_RDP_LEVEL ( __LEVEL__ )
Value:
(((__LEVEL__) == OB_RDP_LEVEL_0)   ||\
                                                        ((__LEVEL__) == OB_RDP_LEVEL_1)   ||\
                                                        ((__LEVEL__) == OB_RDP_LEVEL_2))

Definition at line 984 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_OptrConfig().

#define IS_OB_SEC_BOOT_LOCK ( __VALUE__ )
Value:
(((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE)\
                                                        || ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH))

Definition at line 1007 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_SecMemConfig().

#define IS_OB_SEC_SIZE ( __VALUE__ ) ((__VALUE__) < (FLASH_PAGE_NB + 1U))

Definition at line 1010 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_SecMemConfig().

#define IS_OB_USER_CONFIG | ( | __TYPE__,
 |  | __CONFIG__
 | ) | ((~(__TYPE__) & (__CONFIG__)) == 0x00U)

Definition at line 991 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_OptrConfig().

#define IS_OB_USER_TYPE ( __TYPE__ )
Value:
((((__TYPE__) & OB_USER_ALL) != 0x00U) && \
                                                        (((__TYPE__) & ~OB_USER_ALL) == 0x00U))

Definition at line 988 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_OptrConfig().

#define IS_OB_WRPAREA ( __VALUE__ )
Value:
((FLASH_BANK_NB == 2U) ?                                                        \
   (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) ||   \
    ((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) :  \
   (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B)))

Definition at line 974 of file stm32g0xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define IS_OPTIONBYTE ( __VALUE__ )
Value:
((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \
                                                        (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U))

Definition at line 970 of file stm32g0xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASHEx Private Functions

Functions
FLASHEx Private Functions
FLASHEx

Functions

static void | FLASH_MassErase (uint32_t Banks)
Mass erase of FLASH memory.
void | FLASH_FlushCaches (void)
Flush the instruction cache.
static void | FLASH_OB_WRPConfig (uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
Configure the write protection of the desired pages.
static void | FLASH_OB_GetWRP (uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
Return the FLASH Write Protection Option Bytes value.
static void | FLASH_OB_OptrConfig (uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel)
Set user & RDP configuration.
static uint32_t | FLASH_OB_GetRDP (void)
Return the FLASH Read Protection level.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_PCROP1AConfig (uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
Configure the 1A Proprietary code readout protection & erase configuration on RDP regression.
static void | FLASH_OB_PCROP1BConfig (uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
Configure the 1B Proprietary code readout protection.
static void | FLASH_OB_GetPCROP1A (uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr)
Return the FLASH PCROP Protection Option Bytes value.
static void | FLASH_OB_GetPCROP1B (uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr)
Return the FLASH PCROP Protection Option Bytes value.
static void | FLASH_OB_PCROP2AConfig (uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr)
Configure the 2A Proprietary code readout protection.
static void | FLASH_OB_PCROP2BConfig (uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr)
Configure the 2B Proprietary code readout protection.
static void | FLASH_OB_GetPCROP2A (uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr)
Return the FLASH PCROP Protection Option Bytes value.
static void | FLASH_OB_GetPCROP2B (uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr)
Return the FLASH PCROP Protection Option Bytes value.
static void | FLASH_OB_SecMemConfig (uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2)
Configure Securable Memory area feature.
static void | FLASH_OB_GetSecMem (uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2)
Return the FLASH Securable memory area protection Option Bytes value.
void | FLASH_PageErase (uint32_t Banks, uint32_t Page)
Erase the specified FLASH memory page.

Function Documentation

void FLASH_FlushCaches ( void )

Flush the instruction cache.

Return values:
None

Definition at line 619 of file stm32g0xx_hal_flash_ex.c.

References __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_ENABLE, and __HAL_FLASH_INSTRUCTION_CACHE_RESET.

static void FLASH_MassErase ( uint32_t Banks ) [static]

Mass erase of FLASH memory.

Parameters:
Banks,: Banks to be erased This parameter can be a combination of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased*
Note:
(*) availability depends on devices
Return values:
None

Definition at line 568 of file stm32g0xx_hal_flash_ex.c.

References assert_param, and IS_FLASH_BANK.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_OB_GetPCROP1A | ( | uint32_t * | PCROPConfig,
 |  | uint32_t * | PCROP1AStartAddr,
 |  | uint32_t * | PCROP1AEndAddr
 | ) |  | [static]

Return the FLASH PCROP Protection Option Bytes value.

Parameters:
PCROPConfig | [out] specifies the configuration of PCROP_RDP option.
PCROP1AStartAddr | [out] Specifies the address where to copied the start address of the 1A Proprietary code readout protection
PCROP1AEndAddr | [out] Specifies the address where to copied the end address of the 1A Proprietary code readout protection
Return values:
None

Definition at line 963 of file stm32g0xx_hal_flash_ex.c.

References FLASH_BANK_NB, FLASH_BANK_SIZE, FLASH_PCROP_GRANULARITY, FLASH_PCROP_GRANULARITY_OFFSET, and OB_PCROP_RDP_ERASE.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetPCROP1B | ( | uint32_t * | PCROP1BStartAddr,
 |  | uint32_t * | PCROP1BEndAddr
 | ) |  | [static]

Return the FLASH PCROP Protection Option Bytes value.

Parameters:
PCROP1BStartAddr | [out] Specifies the address where to copied the start address of the 1B Proprietary code readout protection
PCROP1BEndAddr | [out] Specifies the address where to copied the end address of the 1B Proprietary code readout protection
Return values:
None

Definition at line 1002 of file stm32g0xx_hal_flash_ex.c.

References FLASH_BANK_NB, FLASH_BANK_SIZE, FLASH_PCROP_GRANULARITY, and FLASH_PCROP_GRANULARITY_OFFSET.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetPCROP2A | ( | uint32_t * | PCROP2AStartAddr,
 |  | uint32_t * | PCROP2AEndAddr
 | ) |  | [static]

Return the FLASH PCROP Protection Option Bytes value.

Parameters:
PCROP2AStartAddr | [out] Specifies the address where to copied the start address of the 2A Proprietary code readout protection
PCROP2AEndAddr | [out] Specifies the address where to copied the end address of the 2A Proprietary code readout protection
Return values:
None

Definition at line 1137 of file stm32g0xx_hal_flash_ex.c.

References FLASH_BANK_SIZE, FLASH_PCROP_GRANULARITY, and FLASH_PCROP_GRANULARITY_OFFSET.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetPCROP2B | ( | uint32_t * | PCROP2BStartAddr,
 |  | uint32_t * | PCROP2BEndAddr
 | ) |  | [static]

Return the FLASH PCROP Protection Option Bytes value.

Parameters:
PCROP2BStartAddr | [out] Specifies the address where to copied the start address of the 2B Proprietary code readout protection
PCROP2BEndAddr | [out] Specifies the address where to copied the end address of the 2B Proprietary code readout protection
Return values:
None

Definition at line 1171 of file stm32g0xx_hal_flash_ex.c.

References FLASH_BANK_SIZE, FLASH_PCROP_GRANULARITY, and FLASH_PCROP_GRANULARITY_OFFSET.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetRDP ( void ) [static]

Return the FLASH Read Protection level.

Return values:
FLASH ReadOut Protection Status: This return value can be one of the following values:
  • OB_RDP_LEVEL_0 No protection
  • OB_RDP_LEVEL_1 Read protection of the memory
  • OB_RDP_LEVEL_2 Full chip protection

Definition at line 785 of file stm32g0xx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, OB_RDP_LEVEL_1, and OB_RDP_LEVEL_2.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

static void FLASH_OB_GetSecMem | ( | uint32_t * | BootEntry,
 |  | uint32_t * | SecSize,
 |  | uint32_t * | SecSize2
 | ) |  | [static]

Return the FLASH Securable memory area protection Option Bytes value.

Parameters:
BootEntry | specifies boot scheme configuration
SecSize | specifies number of pages to protect as secure memory area, starting from beginning of Bank1 (page 0).
SecSize2 | specifies number of pages to protect as secure memory area, starting from beginning of Bank2 (page 0).
Return values:
None

Definition at line 1240 of file stm32g0xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
The FLASH User Option Bytes values. It will be a combination of all the following values:
  • FLASH Option Bytes User BOR enable
  • FLASH Option Bytes User BOR Level
  • FLASH Option Bytes User reset config bit
  • FLASH Option Bytes User Reset On Stop
  • FLASH Option Bytes User Reset On Standby
  • FLASH Option Bytes User Reset On Shutdown
  • FLASH Option Bytes User IWDG Type
  • FLASH Option Bytes User IWDG Mode On Stop
  • FLASH Option Bytes User IWDG Mode On Standby
  • FLASH Option Bytes User WWDG Type
  • FLASH Option Bytes User SRAM parity
  • FLASH Option Bytes User bank swap Type
  • FLASH Option Bytes User dual bank enable Type
  • FLASH Option Bytes User Boot0 Selection
  • FLASH Option Bytes User BOOT1 Type
  • FLASH Option Bytes User nBOOT0 option bit
  • FLASH Option Bytes User input reset holder bit
Note:
(*) availability depends on devices

Definition at line 821 of file stm32g0xx_hal_flash_ex.c.

References OB_USER_ALL.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

static void FLASH_OB_GetWRP | ( | uint32_t | WRPArea,
 |  | uint32_t * | WRPStartOffset,
 |  | uint32_t * | WRDPEndOffset
 | ) |  | [static]

Return the FLASH Write Protection Option Bytes value.

Parameters:
[in] WRPArea Specifies the area to be returned. This parameter can be one of the following values:
  • OB_WRPAREA_ZONE_A Flash Zone A
  • OB_WRPAREA_ZONE_B Flash Zone B
  • OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*)
  • OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*)
Note:
(*) availability depends on devices
Parameters:
[out] | WRPStartOffset | Specifies the address where to copied the start page of the write protected area
[out] | WRDPEndOffset | Dpecifies the address where to copied the end page of the write protected area
Return values:
None

Definition at line 699 of file stm32g0xx_hal_flash_ex.c.

References assert_param, IS_OB_WRPAREA, OB_WRPAREA_ZONE2_A, OB_WRPAREA_ZONE2_B, and OB_WRPAREA_ZONE_A.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_OptrConfig | ( | uint32_t | UserType,
 |  | uint32_t | UserConfig,
 |  | uint32_t | RDPLevel
 | ) |  | [static]

Set user & RDP configuration.

Note:
!!! Warning : When enabling OB_RDP level 2 it is no more possible to go back to level 1 or 0 !!!
Parameters:
UserType The FLASH User Option Bytes to be modified. This parameter can be a combination of FLASH Option Bytes User Type
UserConfig The FLASH User Option Bytes values. This parameter can be a combination of:
  • FLASH Option Bytes User BOR enable
  • FLASH Option Bytes User BOR Level
  • FLASH Option Bytes User reset config bit
  • FLASH Option Bytes User Reset On Stop
  • FLASH Option Bytes User Reset On Standby
  • FLASH Option Bytes User Reset On Shutdown
  • FLASH Option Bytes User IWDG Type
  • FLASH Option Bytes User IWDG Mode On Stop
  • FLASH Option Bytes User IWDG Mode On Standby
  • FLASH Option Bytes User WWDG Type
  • FLASH Option Bytes User SRAM parity
  • FLASH Option Bytes User bank swap Type
  • FLASH Option Bytes User dual bank enable Type
  • FLASH Option Bytes User Boot0 Selection
  • FLASH Option Bytes User BOOT1 Type
  • FLASH Option Bytes User nBOOT0 option bit
  • FLASH Option Bytes User input reset holder bit
RDPLevel specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0 No protection
  • OB_RDP_LEVEL_1 Memory Read protection
  • OB_RDP_LEVEL_2 Full chip protection
Note:
(*) availability depends on devices
Return values:
None

Definition at line 762 of file stm32g0xx_hal_flash_ex.c.

References assert_param, IS_OB_RDP_LEVEL, IS_OB_USER_CONFIG, and IS_OB_USER_TYPE.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_PCROP1AConfig | ( | uint32_t | PCROPConfig,
 |  | uint32_t | PCROP1AStartAddr,
 |  | uint32_t | PCROP1AEndAddr
 | ) |  | [static]

Configure the 1A Proprietary code readout protection & erase configuration on RDP regression.

Note:
It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid having some executable code in a page where PCROP zone starts or ends.
Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. So if the requirement is to be able to read-protect 1KB areas, the ROP granularity has to be set to 512 Bytes
Parameters:
PCROPConfig | specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE) on RDP level 1 regression.
PCROP1AStartAddr | Specifies the Zone 1A Start address of the Proprietary code readout protection This parameter can be an address between begin and end of the flash
PCROP1AEndAddr | Specifies the Zone 1A end address of the Proprietary code readout protection This parameter can be an address between PCROP1AStartAddr and end of the flash
Return values:
None

Definition at line 843 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_NB, FLASH_BANK_SIZE, FLASH_PCROP_GRANULARITY_OFFSET, IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS, IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS, IS_OB_PCROP_CONFIG, OB_PCROP_RDP_ERASE, and OB_PCROP_ZONE_A.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_PCROP1BConfig | ( | uint32_t | PCROP1BStartAddr,
 |  | uint32_t | PCROP1BEndAddr
 | ) |  | [static]

Configure the 1B Proprietary code readout protection.

Note:
It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid having some executable code in a page where PCROP zone starts or ends.
Minimum PCROP area size is 2 times the chosen granularity: PCROPB_STRT and PCROPB_END. So if the requirement is to be able to read-protect 1KB areas, the ROP granularity has to be set to 512 Bytes
Parameters:
PCROP1BStartAddr | Specifies the Zone 1B Start address of the Proprietary code readout protection This parameter can be an address between begin and end of the flash
PCROP1BEndAddr | Specifies the Zone 1B end address of the Proprietary code readout protection This parameter can be an address between PCROP1BStartAddr and end of the flash
Return values:
None

Definition at line 916 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_NB, FLASH_BANK_SIZE, FLASH_PCROP_GRANULARITY_OFFSET, IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS, and IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_PCROP2AConfig | ( | uint32_t | PCROP2AStartAddr,
 |  | uint32_t | PCROP2AEndAddr
 | ) |  | [static]

Configure the 2A Proprietary code readout protection.

Note:
It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid having some executable code in a page where PCROP zone starts or ends.
Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. So if the requirement is to be able to read-protect 1KB areas, the ROP granularity has to be set to 512 Bytes
Parameters:
PCROP2AStartAddr | Specifies the Zone 2A Start address of the Proprietary code readout protection This parameter can be an address between begin and end of the flash
PCROP2AEndAddr | Specifies the Zone 2A end address of the Proprietary code readout protection This parameter can be an address between PCROP2AStartAddr and end of the flash
Return values:
None

Definition at line 1044 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_SIZE, FLASH_PCROP_GRANULARITY_OFFSET, IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS, and IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_PCROP2BConfig | ( | uint32_t | PCROP2BStartAddr,
 |  | uint32_t | PCROP2BEndAddr
 | ) |  | [static]

Configure the 2B Proprietary code readout protection.

Note:
It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid having some executable code in a page where PCROP zone starts or ends.
Minimum PCROP area size is 2 times the chosen granularity: PCROP_STRT and PCROP_END. So if the requirement is to be able to read-protect 1KB areas, the ROP granularity has to be set to 512 Bytes
Parameters:
PCROP2BStartAddr | Specifies the Zone 2B Start address of the Proprietary code readout protection This parameter can be an address between begin and end of the flash
PCROP2BEndAddr | Specifies the Zone 2B end address of the Proprietary code readout protection This parameter can be an address between PCROP2BStartAddr and end of the flash
Return values:
None

Definition at line 1093 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_SIZE, FLASH_PCROP_GRANULARITY_OFFSET, IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS, and IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_SecMemConfig | ( | uint32_t | BootEntry,
 |  | uint32_t | SecSize,
 |  | uint32_t | SecSize2
 | ) |  | [static]

Configure Securable Memory area feature.

Parameters:
BootEntry specifies if boot scheme is forced to Flash (System or user) or not This parameter can be one of the following values:
  • OB_BOOT_ENTRY_FORCED_NONE No boot entry forced
  • OB_BOOT_ENTRY_FORCED_FLASH Flash selected as unique entry boot
SecSize | specifies number of pages to protect as securable memory area, starting from beginning of Bank1 (page 0).
SecSize2 | specifies number of pages to protect as securable memory area, starting from beginning of Bank2 (page 0).
Return values:
None

Definition at line 1213 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_NB, IS_OB_SEC_BOOT_LOCK, and IS_OB_SEC_SIZE.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_WRPConfig | ( | uint32_t | WRPArea,
 |  | uint32_t | WRPStartOffset,
 |  | uint32_t | WRDPEndOffset
 | ) |  | [static]

Configure the write protection of the desired pages.

Note:
When WRP is active in a zone, it cannot be erased or programmed. Consequently, a software mass erase cannot be performed if one zone is write-protected.
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase Flash memory if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM or System flash, even if WRP is not activated.
Parameters:
WRPArea Specifies the area to be configured. This parameter can be one of the following values:
  • OB_WRPAREA_ZONE_A Flash Zone A
  • OB_WRPAREA_ZONE_B Flash Zone B
  • OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*)
  • OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*)
Note:
(*) availability depends on devices
Parameters:
WRPStartOffset | Specifies the start page of the write protected area This parameter can be page number between 0 and (max number of pages in the Flash Bank - 1)
WRDPEndOffset | Specifies the end page of the write protected area This parameter can be page number between WRPStartOffset and (max number of pages in the Flash Bank - 1)
Return values:
None

Definition at line 656 of file stm32g0xx_hal_flash_ex.c.

References assert_param, IS_FLASH_PAGE, IS_OB_WRPAREA, OB_WRPAREA_ZONE2_A, OB_WRPAREA_ZONE2_B, and OB_WRPAREA_ZONE_A.

Referenced by HAL_FLASHEx_OBProgram().

void FLASH_PageErase | ( | uint32_t | Banks,
 |  | uint32_t | Page
 | ) |  |

Erase the specified FLASH memory page.

Parameters:
Banks,: Banks to be erased This parameter can one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased*
Page FLASH page to erase This parameter must be a value between 0 and (max number of pages in Flash - 1)
Note:
(*) availability depends on devices
Return values:
None

Definition at line 588 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, IS_FLASH_BANK, and IS_FLASH_PAGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended IO operation functions

Functions
Extended IO operation functions
FLASH Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
void | HAL_FLASHEx_EnableDebugger (void)
Enable Debugger.
void | HAL_FLASHEx_DisableDebugger (void)
Disable Debugger.
uint32_t | HAL_FLASHEx_FlashEmptyCheck (void)
Flash Empty check.
void | HAL_FLASHEx_ForceFlashEmpty (uint32_t FlashEmpty)
Force Empty check value.
void | HAL_FLASHEx_EnableSecMemProtection (uint32_t Banks)
Securable memory area protection enable.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                ##### Extended programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the Extended FLASH
    programming operations Operations.

Function Documentation

void HAL_FLASHEx_DisableDebugger ( void )

Disable Debugger.

Note:
After calling this API, Debugger is disabled: it is no more possible to break, see CPU register, etc...
Return values:
None

Definition at line 476 of file stm32g0xx_hal_flash_ex.c.

void HAL_FLASHEx_EnableDebugger ( void )

Enable Debugger.

Note:
After calling this API, flash interface allow debugger intrusion.
Return values:
None

Definition at line 464 of file stm32g0xx_hal_flash_ex.c.

void HAL_FLASHEx_EnableSecMemProtection ( uint32_t Banks )

Securable memory area protection enable.

Parameters:
Banks Select Bank to be secured. This parameter can be a value of FLASH Banks
Note:
On some devices, there is only 1 bank so parameter has to be set FLASH_BANK_1.
This API locks Securable memory area which is defined in SEC_SIZE option byte (that can be retrieved calling HAL_FLASHEx_OBGetConfig API and checking Secsize).
SEC_PROT bit can only be set, it will be reset by system reset.
Return values:
None

Definition at line 524 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, and IS_FLASH_BANK.

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | PageError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory pages.

Parameters:
[in] | pEraseInit | Pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] | PageError | Pointer to variable that contains the configuration information on faulty page in case of error (0xFFFFFFFF means that all the pages have been correctly erased)
Return values:
HAL Status

Definition at line 154 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_MassErase(), FLASH_PageErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASS, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_EraseInitTypeDef::Page, pFlash, and FLASH_EraseInitTypeDef::TypeErase.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.

Parameters:
pEraseInit Pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL Status

Definition at line 226 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::Banks, FLASH_ProcessTypeDef::ErrorCode, FLASH_BANK_1, FLASH_MassErase(), FLASH_PageErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASS, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_ProcessTypeDef::NbPagesToErase, FLASH_EraseInitTypeDef::Page, FLASH_ProcessTypeDef::Page, pFlash, FLASH_ProcessTypeDef::ProcedureOnGoing, and FLASH_EraseInitTypeDef::TypeErase.

uint32_t HAL_FLASHEx_FlashEmptyCheck ( void )

Flash Empty check.

Note:
This API checks if first location in Flash is programmed or not. This check is done once by Option Byte Loader.
Return values:
0 if 1st location is not programmed else

Definition at line 488 of file stm32g0xx_hal_flash_ex.c.

void HAL_FLASHEx_ForceFlashEmpty ( uint32_t FlashEmpty )

Force Empty check value.

Note:
Allows to modify program empty check value in order to force this infrmation in Flash Interface, for all next reset that do not launch Option Byte Loader.
Parameters:
FlashEmpty this parameter can be a value of FLASHEx Empty Check
Return values:
None

Definition at line 502 of file stm32g0xx_hal_flash_ex.c.

References assert_param, and IS_FLASH_EMPTY_CHECK.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option bytes configuration.

Note:
warning: this API only read flash register, it does not reflect any change that would have been programmed between previous Option byte loading and current call.
Parameters:
pOBInit Pointer to an FLASH_OBProgramInitTypeDef structure that contains the configuration information. The fields pOBInit->WRPArea should indicate which area is requested for the WRP.
Return values:
None

Definition at line 421 of file stm32g0xx_hal_flash_ex.c.

References FLASH_OBProgramInitTypeDef::BootEntryPoint, FLASH_OB_GetPCROP1A(), FLASH_OB_GetPCROP1B(), FLASH_OB_GetPCROP2A(), FLASH_OB_GetPCROP2B(), FLASH_OB_GetRDP(), FLASH_OB_GetSecMem(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), OB_PCROP_ZONE2_A, OB_PCROP_ZONE2_B, OB_PCROP_ZONE_A, OB_PCROP_ZONE_B, OB_USER_ALL, OPTIONBYTE_ALL, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROP1AEndAddr, FLASH_OBProgramInitTypeDef::PCROP1AStartAddr, FLASH_OBProgramInitTypeDef::PCROP1BEndAddr, FLASH_OBProgramInitTypeDef::PCROP1BStartAddr, FLASH_OBProgramInitTypeDef::PCROP2AEndAddr, FLASH_OBProgramInitTypeDef::PCROP2AStartAddr, FLASH_OBProgramInitTypeDef::PCROP2BEndAddr, FLASH_OBProgramInitTypeDef::PCROP2BStartAddr, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecSize, FLASH_OBProgramInitTypeDef::SecSize2, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::USERType, FLASH_OBProgramInitTypeDef::WRPArea, FLASH_OBProgramInitTypeDef::WRPEndOffset, and FLASH_OBProgramInitTypeDef::WRPStartOffset.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program Option bytes.

Parameters:
pOBInit Pointer to an FLASH_OBProgramInitTypeDef structure that contains the configuration information for the programming.
Note:
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account only
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • a Power On Reset
  • an exit from Standby or Shutdown mode.
Return values:
HAL Status

Definition at line 297 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::BootEntryPoint, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_GetRDP(), FLASH_OB_GetUser(), FLASH_OB_OptrConfig(), FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), FLASH_OB_PCROP2AConfig(), FLASH_OB_PCROP2BConfig(), FLASH_OB_SecMemConfig(), FLASH_OB_WRPConfig(), FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_OB_PCROP_CONFIG, IS_OPTIONBYTE, OB_PCROP_RDP_ERASE, OB_PCROP_ZONE2_A, OB_PCROP_ZONE2_B, OB_PCROP_ZONE_A, OB_PCROP_ZONE_B, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_SEC, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROP1AEndAddr, FLASH_OBProgramInitTypeDef::PCROP1AStartAddr, FLASH_OBProgramInitTypeDef::PCROP1BEndAddr, FLASH_OBProgramInitTypeDef::PCROP1BStartAddr, FLASH_OBProgramInitTypeDef::PCROP2AEndAddr, FLASH_OBProgramInitTypeDef::PCROP2AStartAddr, FLASH_OBProgramInitTypeDef::PCROP2BEndAddr, FLASH_OBProgramInitTypeDef::PCROP2BStartAddr, FLASH_OBProgramInitTypeDef::PCROPConfig, pFlash, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecSize, FLASH_OBProgramInitTypeDef::SecSize2, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::USERType, FLASH_OBProgramInitTypeDef::WRPArea, FLASH_OBProgramInitTypeDef::WRPEndOffset, and FLASH_OBProgramInitTypeDef::WRPStartOffset.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASHEx Empty Check

Defines
FLASHEx Empty Check
FLASH Exported Constants

Defines

#define | FLASH_PROG_NOT_EMPTY 0x00000000u
#define | FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY

Define Documentation

#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY

1st location in Flash is empty

Definition at line 46 of file stm32g0xx_hal_flash_ex.h.

#define FLASH_PROG_NOT_EMPTY 0x00000000u

1st location in Flash is programmed

Definition at line 45 of file stm32g0xx_hal_flash_ex.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASHEx Private Constants

Defines
FLASHEx Private Constants
FLASHEx

Defines

#define | FLASH_PCROP_GRANULARITY_OFFSET 9u
#define | FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)

Define Documentation

#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)

FLASH Code Readout Protection granularity, 512 Bytes

Definition at line 88 of file stm32g0xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetPCROP1A(), FLASH_OB_GetPCROP1B(), FLASH_OB_GetPCROP2A(), and FLASH_OB_GetPCROP2B().

#define FLASH_PCROP_GRANULARITY_OFFSET 9u

FLASH Code Readout Protection granularity offset

Definition at line 87 of file stm32g0xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetPCROP1A(), FLASH_OB_GetPCROP1B(), FLASH_OB_GetPCROP2A(), FLASH_OB_GetPCROP2B(), FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), FLASH_OB_PCROP2AConfig(), and FLASH_OB_PCROP2BConfig().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASHEx Private Macros

Defines | Functions
FLASHEx Private Macros
FLASHEx

Defines

#define | IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))

Functions

void | FLASH_PageErase (uint32_t Banks, uint32_t Page)
Erase the specified FLASH memory page.

Define Documentation

#define IS_FLASH_EMPTY_CHECK ( __VALUE__ ) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))

Definition at line 97 of file stm32g0xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ForceFlashEmpty().

Function Documentation

void FLASH_PageErase | ( | uint32_t | Banks,
 |  | uint32_t | Page
 | ) |  |

Erase the specified FLASH memory page.

Parameters:
Banks,: Banks to be erased This parameter can one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased*
Page FLASH page to erase This parameter must be a value between 0 and (max number of pages in Flash - 1)
Note:
(*) availability depends on devices
Return values:
None

Definition at line 588 of file stm32g0xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, IS_FLASH_BANK, and IS_FLASH_PAGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 68 of file stm32g0xx_hal_gpio.h.

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STM32G0C1xx HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32g0xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 47 of file stm32g0xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins This parameter can be a value of GPIOEx Alternate function selection

Definition at line 61 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode

Definition at line 52 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins

Definition at line 49 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull

Definition at line 55 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed

Definition at line 58 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_gpio.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIO pins

Defines
GPIO pins
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */

Definition at line 84 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */

Definition at line 85 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */

Definition at line 94 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */

Definition at line 95 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */

Definition at line 96 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */

Definition at line 97 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */

Definition at line 98 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */

Definition at line 99 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */

Definition at line 86 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */

Definition at line 87 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */

Definition at line 88 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */

Definition at line 89 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */

Definition at line 90 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */

Definition at line 91 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */

Definition at line 92 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */

Definition at line 93 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */

Definition at line 100 of file stm32g0xx_hal_gpio.h.

#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */

Definition at line 102 of file stm32g0xx_hal_gpio.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIO mode

Defines
GPIO mode
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0x00WX00YZ. More...

Defines

#define | GPIO_MODE_INPUT MODE_INPUT
#define | GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)
#define | GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)
#define | GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)
#define | GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)
#define | GPIO_MODE_ANALOG MODE_ANALOG
#define | GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)
#define | GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)
#define | GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)
#define | GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)
#define | GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)
#define | GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)

Detailed Description

GPIO Configuration Mode Elements values convention: 0x00WX00YZ.

  • W : EXTI trigger detection on 3 bits
  • X : EXTI mode (IT or Event) on 2 bits
  • Y : Output type (Push Pull or Open Drain) on 1 bit
  • Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits

Define Documentation

#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)

Alternate Function Open Drain Mode

Definition at line 120 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)

Alternate Function Push Pull Mode

Definition at line 119 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG MODE_ANALOG

Analog Mode

Definition at line 121 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_RCCEx_EnableLSCO().

#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)

External Event Mode with Falling edge trigger detection

Definition at line 126 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)

External Event Mode with Rising edge trigger detection

Definition at line 125 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 127 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_INPUT MODE_INPUT

Input Floating Mode

Definition at line 116 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)

External Interrupt Mode with Falling edge trigger detection

Definition at line 123 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)

External Interrupt Mode with Rising edge trigger detection

Definition at line 122 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 124 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)

Output Open Drain Mode

Definition at line 118 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)

Output Push Pull Mode

Definition at line 117 of file stm32g0xx_hal_gpio.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIO speed

Defines
GPIO speed
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW 0x00000000u
#define | GPIO_SPEED_FREQ_MEDIUM 0x00000001u
#define | GPIO_SPEED_FREQ_HIGH 0x00000002u
#define | GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH 0x00000002u

High speed

Definition at line 138 of file stm32g0xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_LOW 0x00000000u

Low speed

Definition at line 136 of file stm32g0xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u

Medium speed

Definition at line 137 of file stm32g0xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u

Very high speed

Definition at line 139 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

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STM32G0C1xx HAL User Manual: GPIO pull

Defines
GPIO pull
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL 0x00000000u
#define | GPIO_PULLUP 0x00000001u
#define | GPIO_PULLDOWN 0x00000002u

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL 0x00000000u

No Pull-up or Pull-down activation

Definition at line 148 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

#define GPIO_PULLDOWN 0x00000002u

Pull-down activation

Definition at line 150 of file stm32g0xx_hal_gpio.h.

#define GPIO_PULLUP 0x00000001u

Pull-up activation

Definition at line 149 of file stm32g0xx_hal_gpio.h.

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STM32G0C1xx HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is rising edge asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__))
Clear the EXTI line rising pending bits.
#define | __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is falling edge asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__))
Clear the EXTI line falling pending bits.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
Clear the EXTI line pending flags.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT ( __EXTI_LINE__ ) (EXTI->FPR1 = (__EXTI_LINE__))

Clear the EXTI line falling pending bits.

Parameters:
__EXTI_LINE__ specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 194 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)

Clear the EXTI line pending flags.

Parameters:
__EXTI_LINE__ specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 240 of file stm32g0xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ )
Value:
do {                                                  \
    __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__);     \
    __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__);    \
  } while(0)

Clear the EXTI's line pending bits.

Parameters:
__EXTI_LINE__ specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 211 of file stm32g0xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_RISING_IT ( __EXTI_LINE__ ) (EXTI->RPR1 = (__EXTI_LINE__))

Clear the EXTI line rising pending bits.

Parameters:
__EXTI_LINE__ specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 178 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER1 |= (__EXTI_LINE__))

Generate a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 224 of file stm32g0xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FALLING_IT ( __EXTI_LINE__ ) (EXTI->FPR1 & (__EXTI_LINE__))

Check whether the specified EXTI line is falling edge asserted or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 186 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)

Check whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 232 of file stm32g0xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ )
Value:
(__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \
                                                       __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__))

Check whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 202 of file stm32g0xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_RISING_IT ( __EXTI_LINE__ ) (EXTI->RPR1 & (__EXTI_LINE__))

Check whether the specified EXTI line is rising edge asserted or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 170 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIO

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit. More...

Defines

#define | GPIO_NUMBER (16u)
#define | GPIO_MODE_Pos 0u
#define | GPIO_MODE (0x3uL << GPIO_MODE_Pos)
#define | MODE_INPUT (0x0uL << GPIO_MODE_Pos)
#define | MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
#define | MODE_AF (0x2uL << GPIO_MODE_Pos)
#define | MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
#define | OUTPUT_TYPE_Pos 4u
#define | OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
#define | OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
#define | OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
#define | EXTI_MODE_Pos 16u
#define | EXTI_MODE (0x3uL << EXTI_MODE_Pos)
#define | EXTI_IT (0x1uL << EXTI_MODE_Pos)
#define | EXTI_EVT (0x2uL << EXTI_MODE_Pos)
#define | TRIGGER_MODE_Pos 20u
#define | TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
#define | TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
#define | TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)

Detailed Description

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit.

Define Documentation

#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)

Definition at line 263 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define EXTI_IT (0x1uL << EXTI_MODE_Pos)

Definition at line 262 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)

Definition at line 261 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define EXTI_MODE_Pos 16u

Definition at line 260 of file stm32g0xx_hal_gpio.h.

#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)

Definition at line 251 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_Pos 0u

Definition at line 250 of file stm32g0xx_hal_gpio.h.

#define GPIO_NUMBER (16u)

Definition at line 129 of file stm32g0xx_hal_gpio.c.

Referenced by HAL_GPIO_TogglePin().

#define MODE_AF (0x2uL << GPIO_MODE_Pos)

Definition at line 254 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)

Definition at line 255 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)

Definition at line 252 of file stm32g0xx_hal_gpio.h.

#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)

Definition at line 253 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)

Definition at line 259 of file stm32g0xx_hal_gpio.h.

#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)

Definition at line 258 of file stm32g0xx_hal_gpio.h.

#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)

Definition at line 257 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define OUTPUT_TYPE_Pos 4u

Definition at line 256 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)

Definition at line 267 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)

Definition at line 265 of file stm32g0xx_hal_gpio.h.

#define TRIGGER_MODE_Pos 20u

Definition at line 264 of file stm32g0xx_hal_gpio.h.

#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)

Definition at line 266 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Define Documentation

#define IS_GPIO_MODE ( __MODE__ )
Value:
(((__MODE__) == GPIO_MODE_INPUT)              ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
                                     ((__MODE__) == GPIO_MODE_ANALOG))

Definition at line 280 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( __PIN__ )
Value:
((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))

Definition at line 277 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 275 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( __PULL__ )
Value:
(((__PULL__) == GPIO_NOPULL)   ||\
                                     ((__PULL__) == GPIO_PULLUP)   || \
                                     ((__PULL__) == GPIO_PULLDOWN))

Definition at line 298 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( __SPEED__ )
Value:
(((__SPEED__) == GPIO_SPEED_FREQ_LOW)    ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)   ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 293 of file stm32g0xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initialize the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
GPIO_Pin | specifies the port bit to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 289 of file stm32g0xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and IS_GPIO_PIN.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
GPIO_Init | pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 162 of file stm32g0xx_hal_gpio.c.

References GPIO_InitTypeDef::Alternate, assert_param, EXTI_EVT, EXTI_IT, EXTI_MODE, GPIO_GET_INDEX, GPIO_MODE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, MODE_AF, MODE_ANALOG, MODE_OUTPUT, OUTPUT_TYPE, OUTPUT_TYPE_Pos, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, GPIO_InitTypeDef::Speed, TRIGGER_FALLING, and TRIGGER_RISING.

Referenced by HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

IO operation functions. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Rising_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.
__weak void | HAL_GPIO_EXTI_Falling_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

IO operation functions.

GPIO Read, Write, Toggle, Lock and EXTI management functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Falling_Callback ( uint16_t GPIO_Pin )

EXTI line detection callback.

Parameters:
GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 523 of file stm32g0xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

Handle EXTI interrupt request.

Parameters:
GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 487 of file stm32g0xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_FALLING_IT, __HAL_GPIO_EXTI_CLEAR_RISING_IT, __HAL_GPIO_EXTI_GET_FALLING_IT, __HAL_GPIO_EXTI_GET_RISING_IT, HAL_GPIO_EXTI_Falling_Callback(), and HAL_GPIO_EXTI_Rising_Callback().

void HAL_GPIO_EXTI_Rising_Callback ( uint16_t GPIO_Pin )

EXTI line detection callback.

Parameters:
GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 508 of file stm32g0xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Lock GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
GPIO_Pin | specifies the port bits to be locked. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 452 of file stm32g0xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Read the specified input port pin.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
GPIO_Pin | specifies the port bit to read. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 370 of file stm32g0xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggle the specified GPIO pin.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
GPIO_Pin | specifies the pin to be toggled. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 427 of file stm32g0xx_hal_gpio.c.

References assert_param, GPIO_NUMBER, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Set or clear the selected data port bit.

Note:
This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
GPIO_Pin | specifies the port bit to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
PinState specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 404 of file stm32g0xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIOEx Alternate function selection

Defines
GPIOEx Alternate function selection
GPIOEx Exported Constants

Defines

#define | GPIO_AF0_CEC ((uint8_t)0x00)
AF 0 selection.
#define | GPIO_AF0_CRS ((uint8_t)0x00)
#define | GPIO_AF0_EVENTOUT ((uint8_t)0x00)
#define | GPIO_AF0_IR ((uint8_t)0x00)
#define | GPIO_AF0_LPTIM1 ((uint8_t)0x00)
#define | GPIO_AF0_MCO ((uint8_t)0x00)
#define | GPIO_AF0_OSC ((uint8_t)0x00)
#define | GPIO_AF0_OSC32 ((uint8_t)0x00)
#define | GPIO_AF0_SWJ ((uint8_t)0x00)
#define | GPIO_AF0_SPI1 ((uint8_t)0x00)
#define | GPIO_AF0_SPI2 ((uint8_t)0x00)
#define | GPIO_AF0_TIM14 ((uint8_t)0x00)
#define | GPIO_AF0_TIM15 ((uint8_t)0x00)
#define | GPIO_AF0_TIM16 ((uint8_t)0x00)
#define | GPIO_AF0_TIM17 ((uint8_t)0x00)
#define | GPIO_AF0_USART1 ((uint8_t)0x00)
#define | GPIO_AF0_USART2 ((uint8_t)0x00)
#define | GPIO_AF0_USART3 ((uint8_t)0x00)
#define | GPIO_AF0_USART4 ((uint8_t)0x00)
#define | GPIO_AF0_UCPD1 ((uint8_t)0x00)
#define | GPIO_AF0_UCPD2 ((uint8_t)0x00)
#define | GPIO_AF1_CEC ((uint8_t)0x01)
AF 1 selection.
#define | GPIO_AF1_EVENTOUT ((uint8_t)0x01)
#define | GPIO_AF1_IR ((uint8_t)0x01)
#define | GPIO_AF1_LPTIM2 ((uint8_t)0x01)
#define | GPIO_AF1_LPUART1 ((uint8_t)0x01)
#define | GPIO_AF1_LPUART2 ((uint8_t)0x01)
#define | GPIO_AF1_OSC ((uint8_t)0x01)
#define | GPIO_AF1_SPI1 ((uint8_t)0x01)
#define | GPIO_AF1_SPI2 ((uint8_t)0x01)
#define | GPIO_AF1_TIM1 ((uint8_t)0x01)
#define | GPIO_AF1_TIM3 ((uint8_t)0x01)
#define | GPIO_AF1_USART1 ((uint8_t)0x01)
#define | GPIO_AF1_USART2 ((uint8_t)0x01)
#define | GPIO_AF1_USART4 ((uint8_t)0x01)
#define | GPIO_AF1_UCPD1 ((uint8_t)0x01)
#define | GPIO_AF1_UCPD2 ((uint8_t)0x01)
#define | GPIO_AF2_LPTIM1 ((uint8_t)0x02)
AF 2 selection.
#define | GPIO_AF2_LPTIM2 ((uint8_t)0x02)
#define | GPIO_AF2_TIM1 ((uint8_t)0x02)
#define | GPIO_AF2_TIM2 ((uint8_t)0x02)
#define | GPIO_AF2_TIM4 ((uint8_t)0x02)
#define | GPIO_AF2_TIM14 ((uint8_t)0x02)
#define | GPIO_AF2_TIM15 ((uint8_t)0x02)
#define | GPIO_AF2_TIM16 ((uint8_t)0x02)
#define | GPIO_AF2_TIM17 ((uint8_t)0x02)
#define | GPIO_AF2_USB ((uint8_t)0x02)
#define | GPIO_AF3_FDCAN1 ((uint8_t)0x03)
AF 3 selection.
#define | GPIO_AF3_FDCAN2 ((uint8_t)0x03)
#define | GPIO_AF3_LPUART2 ((uint8_t)0x03)
#define | GPIO_AF3_USART5 ((uint8_t)0x03)
#define | GPIO_AF3_USART6 ((uint8_t)0x03)
#define | GPIO_AF3_MCO2 ((uint8_t)0x03)
#define | GPIO_AF4_CRS ((uint8_t)0x04)
AF 4 selection.
#define | GPIO_AF4_SPI2 ((uint8_t)0x04)
#define | GPIO_AF4_SPI3 ((uint8_t)0x04)
#define | GPIO_AF4_TIM14 ((uint8_t)0x04)
#define | GPIO_AF4_TIM15 ((uint8_t)0x04)
#define | GPIO_AF4_USART1 ((uint8_t)0x04)
#define | GPIO_AF4_USART3 ((uint8_t)0x04)
#define | GPIO_AF4_USART4 ((uint8_t)0x04)
#define | GPIO_AF4_USART6 ((uint8_t)0x04)
#define | GPIO_AF4_UCPD1 ((uint8_t)0x04)
#define | GPIO_AF4_UCPD2 ((uint8_t)0x04)
#define | GPIO_AF5_LPTIM1 ((uint8_t)0x05)
AF 5 selection.
#define | GPIO_AF5_LPTIM2 ((uint8_t)0x05)
#define | GPIO_AF5_SPI1 ((uint8_t)0x05)
#define | GPIO_AF5_SPI2 ((uint8_t)0x05)
#define | GPIO_AF5_TIM1 ((uint8_t)0x05)
#define | GPIO_AF5_TIM15 ((uint8_t)0x05)
#define | GPIO_AF5_TIM16 ((uint8_t)0x05)
#define | GPIO_AF5_TIM17 ((uint8_t)0x05)
#define | GPIO_AF5_USART3 ((uint8_t)0x05)
#define | GPIO_AF6_I2C1 ((uint8_t)0x06)
AF 6 selection.
#define | GPIO_AF6_I2C2 ((uint8_t)0x06)
#define | GPIO_AF6_I2C3 ((uint8_t)0x06)
#define | GPIO_AF6_LPUART1 ((uint8_t)0x06)
#define | GPIO_AF6_UCPD1 ((uint8_t)0x06)
#define | GPIO_AF6_UCPD2 ((uint8_t)0x06)
#define | GPIO_AF6_USB ((uint8_t)0x06)
#define | GPIO_AF7_COMP1 ((uint8_t)0x07)
AF 7 selection.
#define | GPIO_AF7_COMP2 ((uint8_t)0x07)
#define | GPIO_AF7_COMP3 ((uint8_t)0x07)
#define | GPIO_AF7_EVENTOUT ((uint8_t)0x07)
#define | GPIO_AF8_I2C2 ((uint8_t)0x08)
AF 8 selection.
#define | GPIO_AF8_USART5 ((uint8_t)0x08)
#define | GPIO_AF8_USART6 ((uint8_t)0x08)
#define | GPIO_AF9_I2C3 ((uint8_t)0x09)
AF 9 selection.
#define | GPIO_AF9_SPI3 ((uint8_t)0x09)
#define | GPIO_AF9_TIM4 ((uint8_t)0x09)
#define | GPIO_AF10_LPUART2 ((uint8_t)0x0A)
AF 10 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0A)

Define Documentation

#define GPIO_AF0_CEC ((uint8_t)0x00)

AF 0 selection.

CEC Alternate Function mapping

Definition at line 53 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_CRS ((uint8_t)0x00)

CRS Alternate Function mapping

Definition at line 54 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_EVENTOUT ((uint8_t)0x00)

EVENTOUT Alternate Function mapping

Definition at line 55 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_IR ((uint8_t)0x00)

IR Alternate Function mapping

Definition at line 56 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_LPTIM1 ((uint8_t)0x00)

LPTIM1 Alternate Function mapping

Definition at line 57 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_MCO ((uint8_t)0x00)

MCO (MCO1) Alternate Function mapping

Definition at line 58 of file stm32g0xx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF0_OSC ((uint8_t)0x00)

OSC (By pass and Enable) Alternate Function mapping

Definition at line 59 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_OSC32 ((uint8_t)0x00)

OSC32 (By pass and Enable) Alternate Function mapping

Definition at line 60 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_SPI1 ((uint8_t)0x00)

SPI1 Alternate Function mapping

Definition at line 62 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_SPI2 ((uint8_t)0x00)

SPI2 Alternate Function mapping

Definition at line 63 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_SWJ ((uint8_t)0x00)

SWJ (SWD) Alternate Function mapping

Definition at line 61 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_TIM14 ((uint8_t)0x00)

TIM14 Alternate Function mapping

Definition at line 64 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_TIM15 ((uint8_t)0x00)

TIM15 Alternate Function mapping

Definition at line 65 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_TIM16 ((uint8_t)0x00)

TIM16 Alternate Function mapping

Definition at line 66 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_TIM17 ((uint8_t)0x00)

TIM17 Alternate Function mapping

Definition at line 67 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_UCPD1 ((uint8_t)0x00)

UCPD1 Alternate Function mapping

Definition at line 72 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_UCPD2 ((uint8_t)0x00)

UCPD2 Alternate Function mapping

Definition at line 73 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_USART1 ((uint8_t)0x00)

USART1 Alternate Function mapping

Definition at line 68 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_USART2 ((uint8_t)0x00)

USART2 Alternate Function mapping

Definition at line 69 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_USART3 ((uint8_t)0x00)

USART3 Alternate Function mapping

Definition at line 70 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF0_USART4 ((uint8_t)0x00)

USART4 Alternate Function mapping

Definition at line 71 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF10_LPUART2 ((uint8_t)0x0A)

AF 10 selection.

LPUART2 Alternate Function mapping

Definition at line 184 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_CEC ((uint8_t)0x01)

AF 1 selection.

CEC Alternate Function mapping

Definition at line 78 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_EVENTOUT ((uint8_t)0x01)

EVENTOUT Alternate Function mapping

Definition at line 79 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_IR ((uint8_t)0x01)

IR Alternate Function mapping

Definition at line 80 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_LPTIM2 ((uint8_t)0x01)

LPTIM2 Alternate Function mapping

Definition at line 81 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_LPUART1 ((uint8_t)0x01)

LPUART1 Alternate Function mapping

Definition at line 82 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_LPUART2 ((uint8_t)0x01)

LPUART2 Alternate Function mapping

Definition at line 83 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_OSC ((uint8_t)0x01)

OSC (By pass and Enable) Alternate Function mapping

Definition at line 84 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_SPI1 ((uint8_t)0x01)

SPI2 Alternate Function mapping

Definition at line 85 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_SPI2 ((uint8_t)0x01)

SPI2 Alternate Function mapping

Definition at line 86 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM1 ((uint8_t)0x01)

TIM1 Alternate Function mapping

Definition at line 87 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM3 ((uint8_t)0x01)

TIM3 Alternate Function mapping

Definition at line 88 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_UCPD1 ((uint8_t)0x01)

UCPD1 Alternate Function mapping

Definition at line 92 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_UCPD2 ((uint8_t)0x01)

UCPD2 Alternate Function mapping

Definition at line 93 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_USART1 ((uint8_t)0x01)

USART1 Alternate Function mapping

Definition at line 89 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_USART2 ((uint8_t)0x01)

USART2 Alternate Function mapping

Definition at line 90 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF1_USART4 ((uint8_t)0x01)

USART4 Alternate Function mapping

Definition at line 91 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_LPTIM1 ((uint8_t)0x02)

AF 2 selection.

LPTIM1 Alternate Function mapping

Definition at line 98 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_LPTIM2 ((uint8_t)0x02)

LPTIM2 Alternate Function mapping

Definition at line 99 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM1 ((uint8_t)0x02)

TIM1 Alternate Function mapping

Definition at line 100 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM14 ((uint8_t)0x02)

TIM14 Alternate Function mapping

Definition at line 103 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM15 ((uint8_t)0x02)

TIM15 Alternate Function mapping

Definition at line 104 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM16 ((uint8_t)0x02)

TIM16 Alternate Function mapping

Definition at line 105 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM17 ((uint8_t)0x02)

TIM17 Alternate Function mapping

Definition at line 106 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM2 ((uint8_t)0x02)

TIM2 Alternate Function mapping

Definition at line 101 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM4 ((uint8_t)0x02)

TIM4 Alternate Function mapping

Definition at line 102 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF2_USB ((uint8_t)0x02)

USB Alternate Function mapping

Definition at line 107 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF3_FDCAN1 ((uint8_t)0x03)

AF 3 selection.

FDCAN1 Alternate Function mapping

Definition at line 113 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF3_FDCAN2 ((uint8_t)0x03)

FDCAN2 Alternate Function mapping

Definition at line 114 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF3_LPUART2 ((uint8_t)0x03)

LPUART2 Alternate Function mapping

Definition at line 115 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF3_MCO2 ((uint8_t)0x03)

MCO2 Alternate Function mapping

Definition at line 118 of file stm32g0xx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF3_USART5 ((uint8_t)0x03)

USART5 Alternate Function mapping

Definition at line 116 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF3_USART6 ((uint8_t)0x03)

USART6 Alternate Function mapping

Definition at line 117 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_CRS ((uint8_t)0x04)

AF 4 selection.

CRS Alternate Function mapping

Definition at line 123 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_SPI2 ((uint8_t)0x04)

SPI2 Alternate Function mapping

Definition at line 124 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_SPI3 ((uint8_t)0x04)

SPI3 Alternate Function mapping

Definition at line 125 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM14 ((uint8_t)0x04)

TIM14 Alternate Function mapping

Definition at line 126 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_TIM15 ((uint8_t)0x04)

TIM15 Alternate Function mapping

Definition at line 127 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_UCPD1 ((uint8_t)0x04)

UCPD1 Alternate Function mapping

Definition at line 132 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_UCPD2 ((uint8_t)0x04)

UCPD2 Alternate Function mapping

Definition at line 133 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_USART1 ((uint8_t)0x04)

USART1 Alternate Function mapping

Definition at line 128 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_USART3 ((uint8_t)0x04)

USART3 Alternate Function mapping

Definition at line 129 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_USART4 ((uint8_t)0x04)

USART4 Alternate Function mapping

Definition at line 130 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF4_USART6 ((uint8_t)0x04)

USART6 Alternate Function mapping

Definition at line 131 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_LPTIM1 ((uint8_t)0x05)

AF 5 selection.

LPTIM1 Alternate Function mapping

Definition at line 138 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_LPTIM2 ((uint8_t)0x05)

LPTIM2 Alternate Function mapping

Definition at line 139 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05)

SPI1 Alternate Function mapping

Definition at line 140 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05)

SPI2 Alternate Function mapping

Definition at line 141 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_TIM1 ((uint8_t)0x05)

TIM1 Alternate Function mapping

Definition at line 142 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_TIM15 ((uint8_t)0x05)

TIM15 Alternate Function mapping

Definition at line 143 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_TIM16 ((uint8_t)0x05)

TIM16 Alternate Function mapping

Definition at line 144 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_TIM17 ((uint8_t)0x05)

TIM17 Alternate Function mapping

Definition at line 145 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF5_USART3 ((uint8_t)0x05)

USART3 Alternate Function mapping

Definition at line 146 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF6_I2C1 ((uint8_t)0x06)

AF 6 selection.

I2C1 Alternate Function mapping

Definition at line 151 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF6_I2C2 ((uint8_t)0x06)

I2C2 Alternate Function mapping

Definition at line 152 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF6_I2C3 ((uint8_t)0x06)

I2C3 Alternate Function mapping

Definition at line 153 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF6_LPUART1 ((uint8_t)0x06)

LPUART1 Alternate Function mapping

Definition at line 154 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF6_UCPD1 ((uint8_t)0x06)

UCPD1 Alternate Function mapping

Definition at line 155 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF6_UCPD2 ((uint8_t)0x06)

UCPD2 Alternate Function mapping

Definition at line 156 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF6_USB ((uint8_t)0x06)

USB Alternate Function mapping

Definition at line 157 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF7_COMP1 ((uint8_t)0x07)

AF 7 selection.

COMP1 Alternate Function mapping

Definition at line 162 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF7_COMP2 ((uint8_t)0x07)

COMP2 Alternate Function mapping

Definition at line 163 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF7_COMP3 ((uint8_t)0x07)

COMP3 Alternate Function mapping

Definition at line 164 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF7_EVENTOUT ((uint8_t)0x07)

EVENTOUT Alternate Function mapping

Definition at line 165 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF8_I2C2 ((uint8_t)0x08)

AF 8 selection.

I2C2 Alternate Function mapping

Definition at line 170 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF8_USART5 ((uint8_t)0x08)

USART5 Alternate Function mapping

Definition at line 171 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF8_USART6 ((uint8_t)0x08)

USART5 Alternate Function mapping

Definition at line 172 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF9_I2C3 ((uint8_t)0x09)

AF 9 selection.

I2C3 Alternate Function mapping

Definition at line 177 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF9_SPI3 ((uint8_t)0x09)

SPI3 Alternate Function mapping

Definition at line 178 of file stm32g0xx_hal_gpio_ex.h.

#define GPIO_AF9_TIM4 ((uint8_t)0x09)

TIM4 Alternate Function mapping

Definition at line 179 of file stm32g0xx_hal_gpio_ex.h.

#define IS_GPIO_AF ( AF ) ((AF) <= (uint8_t)0x0A)

Definition at line 186 of file stm32g0xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIOEx Get Port Index

Defines
GPIOEx Get Port Index
GPIOEx Exported Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(((__GPIOx__) == (GPIOA))? 0uL :\
                                      ((__GPIOx__) == (GPIOB))? 1uL :\
                                      ((__GPIOx__) == (GPIOC))? 2uL :\
                                      ((__GPIOx__) == (GPIOD))? 3uL :\
                                      ((__GPIOx__) == (GPIOE))? 4uL : 5uL)

Definition at line 802 of file stm32g0xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Private Functions

HCD Private Functions
HCD
Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL USB OTG HCD Callback ID enumeration definition

Enumerations
HAL USB OTG HCD Callback ID enumeration definition
Initialization and de-initialization functions

HAL USB OTG HCD Callback ID enumeration definition. More...

Enumerations

enum HAL_HCD_CallbackIDTypeDef {
HAL_HCD_SOF_CB_ID = 0x01, HAL_HCD_CONNECT_CB_ID = 0x02, HAL_HCD_DISCONNECT_CB_ID = 0x03, HAL_HCD_PORT_ENABLED_CB_ID = 0x04,
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, HAL_HCD_MSPINIT_CB_ID = 0x06, HAL_HCD_MSPDEINIT_CB_ID = 0x07
}

Detailed Description

HAL USB OTG HCD Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_HCD_CallbackIDTypeDef
Enumerator:
HAL_HCD_SOF_CB_ID

USB HCD SOF callback ID

HAL_HCD_CONNECT_CB_ID

USB HCD Connect callback ID

HAL_HCD_DISCONNECT_CB_ID

USB HCD Disconnect callback ID

HAL_HCD_PORT_ENABLED_CB_ID

USB HCD Port Enable callback ID

HAL_HCD_PORT_DISABLED_CB_ID

USB HCD Port Disable callback ID

HAL_HCD_MSPINIT_CB_ID

USB HCD MspInit callback ID

HAL_HCD_MSPDEINIT_CB_ID

USB HCD MspDeInit callback ID

Definition at line 214 of file stm32g0xx_hal_hcd.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL USB OTG HCD Callback pointer definition

Typedefs
HAL USB OTG HCD Callback pointer definition
Initialization and de-initialization functions

HAL USB OTG HCD Callback pointer definition. More...

Typedefs

typedef void(* | pHCD_CallbackTypeDef )(HCD_HandleTypeDef *hhcd)
typedef void(* | pHCD_HC_NotifyURBChangeCallbackTypeDef )(HCD_HandleTypeDef *hhcd, uint8_t epnum, HCD_URBStateTypeDef urb_state)

Detailed Description

HAL USB OTG HCD Callback pointer definition.

Typedef Documentation

typedef void(* pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd)

pointer to a common USB OTG HCD callback function

Definition at line 235 of file stm32g0xx_hal_hcd.h.

typedef void(* pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, uint8_t epnum, HCD_URBStateTypeDef urb_state)

pointer to USB OTG HCD host channel callback

Definition at line 236 of file stm32g0xx_hal_hcd.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Modules | Functions
Initialization and de-initialization functions
HCD Exported Functions

Initialization and Configuration functions. More...

Modules

HAL USB OTG HCD Callback ID enumeration definition

HAL USB OTG HCD Callback ID enumeration definition.

HAL USB OTG HCD Callback pointer definition

HAL USB OTG HCD Callback pointer definition.

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Close (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
HAL_HCD_HC_Close Pipe.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
__weak void | HAL_HCD_SuspendCallback (HCD_HandleTypeDef *hhcd)
__weak void | HAL_HCD_ResumeCallback (HCD_HandleTypeDef *hhcd)
HAL_StatusTypeDef | HAL_HCD_RegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
Register a User USB HCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
Unregister an USB HCD Callback USB HCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_RegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd)
Unregister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Detailed Description

Initialization and Configuration functions.

===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_HCD_DeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the host driver.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 472 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ep0_PmaAllocState, HAL_HCD_MspDeInit(), HAL_HCD_PMAReset(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_RESET, HCD_HCD_STATE_DISCONNECTED, __HCD_HandleTypeDef::HostState, __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::phy_chin_state, __HCD_HandleTypeDef::phy_chout_state, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_HC_Close | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  |

HAL_HCD_HC_Close Pipe.

Parameters:
hhcd | HCD handle
ch_num | Channel number. This parameter can be a value from 1 to 15
Return values:
HAL status

Definition at line 418 of file stm32g0xx_hal_hcd.c.

References HAL_Delay(), HAL_HCD_HC_Halt(), HAL_HCD_PMADeAlloc(), __HCD_HandleTypeDef::hc, __HCD_HandleTypeDef::phy_chin_state, and __HCD_HandleTypeDef::phy_chout_state.

HAL_StatusTypeDef HAL_HCD_HC_Halt | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  |

Halt a host channel.

Parameters:
hhcd | HCD handle
ch_num | Channel number. This parameter can be a value from 1 to 15
Return values:
HAL status

Definition at line 449 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc, and __HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_HC_Close(), HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

HAL_StatusTypeDef HAL_HCD_HC_Init | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | epnum,
 |  | uint8_t | dev_address,
 |  | uint8_t | speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | mps
 | ) |  |

Initialize a host channel.

Parameters:
hhcd | HCD handle
ch_num | Channel number. This parameter can be a value from 1 to 15
epnum | Endpoint number. This parameter can be a value from 1 to 15
dev_address | Current device address This parameter can be a value from 0 to 255
speed | Current device speed. This parameter can be one of these values: HCD_DEVICE_SPEED_HIGH High speed mode, HCD_DEVICE_SPEED_FULL Full speed mode, HCD_DEVICE_SPEED_LOW Low speed mode
ep_type | Endpoint Type. This parameter can be one of these values: USBH_EP_CONTROL Control type, USBH_EP_ISO Isochronous type, USBH_EP_BULK Bulk type, USBH_EP_INTERRUPT Interrupt type
mps | Max Packet Size. This parameter can be a value from 0 to32K
Return values:
HAL status

Definition at line 212 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ep0_PmaAllocState, HAL_HCD_Check_usedChannel(), HAL_HCD_Get_FreePhyChannel(), HAL_HCD_PMAlloc(), __HCD_HandleTypeDef::hc, HCD_CLEAR_RX_DTOG, HCD_CLEAR_TX_DTOG, HCD_DBL_BUF, HCD_FREE_CH_NOT_FOUND, HCD_SNG_BUF, __HCD_HandleTypeDef::Init, and __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Init ( HCD_HandleTypeDef * hhcd )

Initialize the host driver.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 119 of file stm32g0xx_hal_hcd.c.

References __HAL_HCD_DISABLE, assert_param, __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, HAL_HCD_Connect_Callback(), HAL_HCD_Disconnect_Callback(), HAL_HCD_HC_NotifyURBChange_Callback(), HAL_HCD_MspInit(), HAL_HCD_PMAReset(), HAL_HCD_PortDisabled_Callback(), HAL_HCD_PortEnabled_Callback(), HAL_HCD_SOF_Callback(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, HCD_HCD_STATE_DISCONNECTED, __HCD_HandleTypeDef::HostState, __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::Instance, __HCD_HandleTypeDef::Lock, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

void HAL_HCD_MspDeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the HCD MSP.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 537 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_DeInit(), and HAL_HCD_UnRegisterCallback().

void HAL_HCD_MspInit ( HCD_HandleTypeDef * hhcd )

Initialize the HCD MSP.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 522 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), and HAL_HCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_HCD_RegisterCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | HAL_HCD_CallbackIDTypeDef | CallbackID,
 |  | pHCD_CallbackTypeDef | pCallback
 | ) |  |

Register a User USB HCD Callback To be used instead of the weak predefined callback.

Parameters:
hhcd | USB HCD handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
  • HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
  • HAL_HCD_DISCONNECT_CB_ID HCD Disconnect callback ID
  • HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
  • HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
  • HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 1010 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ErrorCode, HAL_HCD_CONNECT_CB_ID, HAL_HCD_DISCONNECT_CB_ID, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_MSPDEINIT_CB_ID, HAL_HCD_MSPINIT_CB_ID, HAL_HCD_PORT_DISABLED_CB_ID, HAL_HCD_PORT_ENABLED_CB_ID, HAL_HCD_SOF_CB_ID, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | pHCD_HC_NotifyURBChangeCallbackTypeDef | pCallback
 | ) |  |

Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Parameters:
hhcd | HCD handle
pCallback | pointer to the USB HCD Host Channel Notify URB Change Callback function
Return values:
HAL status

Definition at line 1205 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ErrorCode, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_STATE_READY, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, and __HCD_HandleTypeDef::State.

__weak void HAL_HCD_ResumeCallback ( HCD_HandleTypeDef * hhcd )

Definition at line 558 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

__weak void HAL_HCD_SuspendCallback ( HCD_HandleTypeDef * hhcd )

Definition at line 547 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

HAL_StatusTypeDef HAL_HCD_UnRegisterCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | HAL_HCD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USB HCD Callback USB HCD callback is redirected to the weak predefined callback.

Parameters:
hhcd USB HCD handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
  • HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
  • HAL_HCD_DISCONNECT_CB_ID DRD HCD Disconnect callback ID
  • HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
  • HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
  • HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 1113 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ErrorCode, HAL_HCD_Connect_Callback(), HAL_HCD_CONNECT_CB_ID, HAL_HCD_Disconnect_Callback(), HAL_HCD_DISCONNECT_CB_ID, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_MspDeInit(), HAL_HCD_MSPDEINIT_CB_ID, HAL_HCD_MspInit(), HAL_HCD_MSPINIT_CB_ID, HAL_HCD_PORT_DISABLED_CB_ID, HAL_HCD_PORT_ENABLED_CB_ID, HAL_HCD_PortDisabled_Callback(), HAL_HCD_PortEnabled_Callback(), HAL_HCD_SOF_Callback(), HAL_HCD_SOF_CB_ID, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback ( HCD_HandleTypeDef * hhcd )

Unregister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1247 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ErrorCode, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_HC_NotifyURBChange_Callback(), HAL_HCD_STATE_READY, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, and __HCD_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
HCD Exported Functions

HCD IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_PortEnabled_Callback (HCD_HandleTypeDef *hhcd)
Port Enabled Event callback.
__weak void | HAL_HCD_PortDisabled_Callback (HCD_HandleTypeDef *hhcd)
Port Disabled Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_RegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
Register a User USB HCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
Unregister an USB HCD Callback USB HCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_RegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd)
Unregister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
void | HAL_HCD_SuspendCallback (HCD_HandleTypeDef *hhcd)
void | HAL_HCD_ResumeCallback (HCD_HandleTypeDef *hhcd)

Detailed Description

HCD IO operation functions.

===============================================================================
##### IO operation functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to manage the USB Host Data
Transfer

Function Documentation

void HAL_HCD_Connect_Callback ( HCD_HandleTypeDef * hhcd )

Connection Event callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 913 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

void HAL_HCD_Disconnect_Callback ( HCD_HandleTypeDef * hhcd )

Disconnection Event callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 928 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

void HAL_HCD_HC_NotifyURBChange_Callback | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum,
 |  | HCD_URBStateTypeDef | urb_state
 | ) |  |

Notify URB state change callback.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
urb_state | This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL/
Return values:
None

Definition at line 981 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(), HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | direction,
 |  | uint8_t | ep_type,
 |  | uint8_t | token,
 |  | uint8_t * | pbuff,
 |  | uint16_t | length,
 |  | uint8_t | do_ping
 | ) |  |

Submit a new URB for processing.

Parameters:
hhcd | HCD handle
ch_num | Channel number. This parameter can be a value from 1 to 15
direction | Channel number. This parameter can be one of these values: 0 : Output / 1 : Input
ep_type | Endpoint Type. This parameter can be one of these values: USBH_EP_CONTROL : Control type/ USBH_EP_ISO : Isochronous type/ USBH_EP_BULK : Bulk type/ USBH_EP_INTERRUPT : Interrupt type/
token | Endpoint Type. This parameter can be one of these values: 0: HC_PID_SETUP / 1: HC_PID_DATA1
pbuff | pointer to URB data
length | Length of URB data
do_ping | activate do ping protocol (for high speed only). This parameter can be one of these values: 0 : do ping inactive / 1 : do ping active
Return values:
HAL status

Definition at line 610 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc, and __HCD_HandleTypeDef::Instance.

void HAL_HCD_IRQHandler ( HCD_HandleTypeDef * hhcd )

Handle HCD interrupt request.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 730 of file stm32g0xx_hal_hcd.c.

References __HAL_HCD_CLEAR_FLAG, HAL_HCD_GetLogical_Channel(), HAL_HCD_PortEnabled_Callback(), HAL_HCD_ResumeCallback(), HAL_HCD_SOF_Callback(), HAL_HCD_SuspendCallback(), HCD_GET_CHANNEL, HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_HCD_STATE_RESETED, HCD_HCD_STATE_RESUME, HCD_HCD_STATE_RUN, HCD_HCD_STATE_SUSPEND, HCD_LOGICAL_CH_NOT_OPENED, HCD_Port_IRQHandler(), HCD_SET_CHANNEL, __HCD_HandleTypeDef::HostState, __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::Instance, __HCD_HandleTypeDef::PortEnabledCallback, and __HCD_HandleTypeDef::SOFCallback.

void HAL_HCD_PortDisabled_Callback ( HCD_HandleTypeDef * hhcd )

Port Disabled Event callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 956 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), and HAL_HCD_UnRegisterCallback().

void HAL_HCD_PortEnabled_Callback ( HCD_HandleTypeDef * hhcd )

Port Enabled Event callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 942 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_IRQHandler(), and HAL_HCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_HCD_RegisterCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | HAL_HCD_CallbackIDTypeDef | CallbackID,
 |  | pHCD_CallbackTypeDef | pCallback
 | ) |  |

Register a User USB HCD Callback To be used instead of the weak predefined callback.

Parameters:
hhcd | USB HCD handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
  • HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
  • HAL_HCD_DISCONNECT_CB_ID HCD Disconnect callback ID
  • HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
  • HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
  • HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 1010 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ErrorCode, HAL_HCD_CONNECT_CB_ID, HAL_HCD_DISCONNECT_CB_ID, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_MSPDEINIT_CB_ID, HAL_HCD_MSPINIT_CB_ID, HAL_HCD_PORT_DISABLED_CB_ID, HAL_HCD_PORT_ENABLED_CB_ID, HAL_HCD_SOF_CB_ID, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | pHCD_HC_NotifyURBChangeCallbackTypeDef | pCallback
 | ) |  |

Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Parameters:
hhcd | HCD handle
pCallback | pointer to the USB HCD Host Channel Notify URB Change Callback function
Return values:
HAL status

Definition at line 1205 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ErrorCode, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_STATE_READY, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, and __HCD_HandleTypeDef::State.

void HAL_HCD_ResumeCallback ( HCD_HandleTypeDef * hhcd )

Definition at line 558 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

void HAL_HCD_SOF_Callback ( HCD_HandleTypeDef * hhcd )

SOF callback.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 898 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_Init(), HAL_HCD_IRQHandler(), and HAL_HCD_UnRegisterCallback().

void HAL_HCD_SuspendCallback ( HCD_HandleTypeDef * hhcd )

Definition at line 547 of file stm32g0xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

HAL_StatusTypeDef HAL_HCD_UnRegisterCallback | ( | HCD_HandleTypeDef * | hhcd,
 |  | HAL_HCD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USB HCD Callback USB HCD callback is redirected to the weak predefined callback.

Parameters:
hhcd USB HCD handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
  • HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
  • HAL_HCD_DISCONNECT_CB_ID DRD HCD Disconnect callback ID
  • HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
  • HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
  • HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 1113 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ErrorCode, HAL_HCD_Connect_Callback(), HAL_HCD_CONNECT_CB_ID, HAL_HCD_Disconnect_Callback(), HAL_HCD_DISCONNECT_CB_ID, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_MspDeInit(), HAL_HCD_MSPDEINIT_CB_ID, HAL_HCD_MspInit(), HAL_HCD_MSPINIT_CB_ID, HAL_HCD_PORT_DISABLED_CB_ID, HAL_HCD_PORT_ENABLED_CB_ID, HAL_HCD_PortDisabled_Callback(), HAL_HCD_PortEnabled_Callback(), HAL_HCD_SOF_Callback(), HAL_HCD_SOF_CB_ID, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, __HCD_HandleTypeDef::MspDeInitCallback, __HCD_HandleTypeDef::MspInitCallback, __HCD_HandleTypeDef::PortDisabledCallback, __HCD_HandleTypeDef::PortEnabledCallback, __HCD_HandleTypeDef::SOFCallback, and __HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback ( HCD_HandleTypeDef * hhcd )

Unregister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1247 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ErrorCode, HAL_HCD_ERROR_INVALID_CALLBACK, HAL_HCD_HC_NotifyURBChange_Callback(), HAL_HCD_STATE_READY, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, and __HCD_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
HCD Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_Suspend (HCD_HandleTypeDef *hhcd)
Put the Device in suspend mode.
HAL_StatusTypeDef | HAL_HCD_Resume (HCD_HandleTypeDef *hhcd)
Resume host port.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HAL_StatusTypeDef | HAL_HCD_ResumePort (HCD_HandleTypeDef *hhcd)
Resme the host port.

Detailed Description

Management functions.

===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the HCD data
transfers.

Function Documentation

HAL_StatusTypeDef HAL_HCD_ResetPort ( HCD_HandleTypeDef * hhcd )

Reset the host port.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1383 of file stm32g0xx_hal_hcd.c.

References HCD_HCD_STATE_CONNECTED, HCD_HCD_STATE_RESETED, __HCD_HandleTypeDef::HostState, and __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Resume ( HCD_HandleTypeDef * hhcd )

Resume host port.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1370 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_ResumePort ( HCD_HandleTypeDef * hhcd )

Resme the host port.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1404 of file stm32g0xx_hal_hcd.c.

References HAL_Delay(), and __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Start ( HCD_HandleTypeDef * hhcd )

Start the host driver.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1299 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Stop ( HCD_HandleTypeDef * hhcd )

Stop the host driver.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1322 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ep0_PmaAllocState, HAL_HCD_ClearPhyChannel(), HAL_HCD_PMAReset(), and __HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Suspend ( HCD_HandleTypeDef * hhcd )

Put the Device in suspend mode.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 1346 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Allocation

Functions
Allocation
Peripheral State functions

Functions

HAL_StatusTypeDef | HAL_HCD_PMAlloc (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint16_t ch_kind, uint16_t mps)
Allocate PMA buffer for Channel This API will fetch a free space.
HAL_StatusTypeDef | HAL_HCD_PMADeAlloc (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable.
HAL_StatusTypeDef | HAL_HCD_PMAReset (HCD_HandleTypeDef *hhcd)
PMA Reset.

Function Documentation

HAL_StatusTypeDef HAL_HCD_PMADeAlloc | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  |

PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable.

Parameters:
hhcd | Host instance
ch_num | Channel number
Return values:
HAL status

Definition at line 2684 of file stm32g0xx_hal_hcd.c.

References HAL_HCD_PMAFree(), and __HCD_HandleTypeDef::hc.

Referenced by HAL_HCD_HC_Close().

HAL_StatusTypeDef HAL_HCD_PMAlloc | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint16_t | ch_kind,
 |  | uint16_t | mps
 | ) |  |

Allocate PMA buffer for Channel This API will fetch a free space.

Parameters:
hhcd | Host instance
ch_num | Channel number
ch_kind | endpoint Kind USB_SNG_BUF Single Buffer used USB_DBL_BUF Double Buffer used
mps | Channel Max Packet Size
Return values:
HAL status

Definition at line 2581 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ep0_PmaAllocState, HAL_HCD_GetFreePMA(), HAL_HCD_PMAFree(), __HCD_HandleTypeDef::hc, and HCD_SNG_BUF.

Referenced by HAL_HCD_HC_Init().

HAL_StatusTypeDef HAL_HCD_PMAReset ( HCD_HandleTypeDef * hhcd )

PMA Reset.

Parameters:
hhcd Host instance
Return values:
HAL status

Definition at line 2733 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Init, PMA_BLOCKS, and __HCD_HandleTypeDef::PMALookupTable.

Referenced by HAL_HCD_DeInit(), HAL_HCD_Init(), HAL_HCD_Stop(), and HCD_Port_IRQHandler().

Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Modules | Functions
Peripheral State functions
HCD Exported Functions

Peripheral State functions. More...

Modules

Allocation

Functions

HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.
HAL_StatusTypeDef | HAL_HCD_PMAlloc (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint16_t ch_kind, uint16_t mps)
Allocate PMA buffer for Channel This API will fetch a free space.
HAL_StatusTypeDef | HAL_HCD_PMADeAlloc (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable.
HAL_StatusTypeDef | HAL_HCD_PMAReset (HCD_HandleTypeDef *hhcd)
PMA Reset.
static void | HCD_HC_OUT_BulkDb (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue)
Handle Host Channel OUT Double Buffer Bulk requests.
static void | HCD_HC_IN_BulkDb (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue)
Handle Host Channel IN Double Buffer Bulk requests.
static void | HCD_HC_IN_ISO (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue)
Handle Host Channel IN Isochronous Transaction.
static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Handle Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel OUT interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Host Port interrupt requests.
static uint8_t | HAL_HCD_Check_usedChannel (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Check if the ch_num are already reserved to a physical channel.
static uint8_t | HAL_HCD_GetLogical_Channel (HCD_HandleTypeDef *hhcd, uint8_t phy_chnum, uint8_t dir)
Get a Logical Channel number from physical Channel.
static uint8_t | HAL_HCD_Get_FreePhyChannel (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t ep_type)
Get a free physical Channel number according to the direction.
static void | HAL_HCD_ClearPhyChannel (HCD_HandleTypeDef *hhcd)
Free All Channel allocation.
static uint16_t | HAL_HCD_GetFreePMA (HCD_HandleTypeDef *hhcd, uint16_t mps)
Fetch in the PMA_LockupTable free space of number of mps byte.
static HAL_StatusTypeDef | HAL_HCD_PMAFree (HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps)
PMA Free.

Detailed Description

Peripheral State functions.

===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.

Function Documentation

static uint8_t HAL_HCD_Check_usedChannel | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  | [static]

Check if the ch_num are already reserved to a physical channel.

Parameters:
hhcd | HCD handle
ch_num | Channel number This parameter can be a value from 1 to 15
Return values:
HAL status

Definition at line 2249 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::phy_chin_state, and __HCD_HandleTypeDef::phy_chout_state.

Referenced by HAL_HCD_HC_Init().

static void HAL_HCD_ClearPhyChannel ( HCD_HandleTypeDef * hhcd ) [static]

Free All Channel allocation.

Parameters:
hhcd HCD handle
Return values:
HAL status

Definition at line 2441 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::phy_chin_state, and __HCD_HandleTypeDef::phy_chout_state.

Referenced by HAL_HCD_Stop(), and HCD_Port_IRQHandler().

static uint8_t HAL_HCD_Get_FreePhyChannel | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | epnum,
 |  | uint8_t | ep_type
 | ) |  | [static]

Get a free physical Channel number according to the direction.

Parameters:
hhcd | HCD handle
ch_num | Channel number This parameter can be a value from 1 to 15
epnum | Endpoint number This parameter can be a value from 1 to 15
ep_type | Endpoint Type This parameter can be one of these values: EP_TYPE_CTRL Control type, EP_TYPE_ISOC Isochronous type, EP_TYPE_BULK Bulk type, EP_TYPE_INTR Interrupt type
Return values:
if physical channel is available return Phy_channel number else return HCD_FREE_CH_NOT_FOUND

Definition at line 2331 of file stm32g0xx_hal_hcd.c.

References HCD_FREE_CH_NOT_FOUND, __HCD_HandleTypeDef::Init, __HCD_HandleTypeDef::phy_chin_state, and __HCD_HandleTypeDef::phy_chout_state.

Referenced by HAL_HCD_HC_Init().

uint32_t HAL_HCD_GetCurrentFrame ( HCD_HandleTypeDef * hhcd )

Return the current Host frame number.

Parameters:
hhcd HCD handle
Return values:
Current Host frame number

Definition at line 1505 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

uint32_t HAL_HCD_GetCurrentSpeed ( HCD_HandleTypeDef * hhcd )

Return the Host enumeration speed.

Parameters:
hhcd HCD handle
Return values:
speed : Device speed after Host enumeration This parameter can be one of these values:
  • HCD_DEVICE_SPEED_FULL: Full speed mode
  • HCD_DEVICE_SPEED_LOW: Low speed mode

Definition at line 1518 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Instance.

static uint16_t HAL_HCD_GetFreePMA | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint16_t | mps
 | ) |  | [static]

Fetch in the PMA_LockupTable free space of number of mps byte.

Parameters:
hhcd | Host instance
mps | Channel Max Packet Size
Return values:
PMA_Address of the first free block containing mps byte 0xFFFF in case of no space available

Definition at line 2474 of file stm32g0xx_hal_hcd.c.

References PMA_BLOCKS, and __HCD_HandleTypeDef::PMALookupTable.

Referenced by HAL_HCD_PMAlloc().

static uint8_t HAL_HCD_GetLogical_Channel | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | phy_chnum,
 |  | uint8_t | dir
 | ) |  | [static]

Get a Logical Channel number from physical Channel.

Parameters:
hhcd | HCD handle
phy_chnum | This parameter can be a value from 1 to 15
dir | Channel direction -0 OUT_Channel -1 IN_Channel
Return values:
HAL status

Definition at line 2283 of file stm32g0xx_hal_hcd.c.

References HCD_LOGICAL_CH_NOT_OPENED, __HCD_HandleTypeDef::phy_chin_state, and __HCD_HandleTypeDef::phy_chout_state.

Referenced by HAL_HCD_IRQHandler().

HCD_StateTypeDef HAL_HCD_GetState ( HCD_HandleTypeDef * hhcd )

Return the HCD handle state.

Parameters:
hhcd HCD handle
Return values:
HAL state

Definition at line 1441 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::State.

HCD_HCStateTypeDef HAL_HCD_HC_GetState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the Host Channel state.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
Return values:
Host channel state This parameter can be one of these values: HC_IDLE/ HC_XFRC/ HC_HALTED/ HC_NYET/ HC_NAK/ HC_STALL/ HC_XACTERR/ HC_BBLERR/ HC_DATATGLERR

Definition at line 1495 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc.

HCD_URBStateTypeDef HAL_HCD_HC_GetURBState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return URB state for a channel.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
Return values:
URB state. This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL

Definition at line 1460 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc.

uint32_t HAL_HCD_HC_GetXferCount | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the last host transfer size.

Parameters:
hhcd | HCD handle
chnum | Channel number. This parameter can be a value from 1 to 15
Return values:
last transfer size in byte

Definition at line 1473 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc.

HAL_StatusTypeDef HAL_HCD_PMADeAlloc | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  |

PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable.

Parameters:
hhcd | Host instance
ch_num | Channel number
Return values:
HAL status

Definition at line 2684 of file stm32g0xx_hal_hcd.c.

References HAL_HCD_PMAFree(), and __HCD_HandleTypeDef::hc.

Referenced by HAL_HCD_HC_Close().

static HAL_StatusTypeDef HAL_HCD_PMAFree | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint32_t | pma_base,
 |  | uint16_t | mps
 | ) |  | [static]

PMA Free.

Parameters:
hhcd | Host instance
pma_base | PMA base offset stored in hhcd->hc.pmaaddr
mps | Max Packet Size
Return values:
HAL status

Definition at line 2757 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::PMALookupTable.

Referenced by HAL_HCD_PMADeAlloc(), and HAL_HCD_PMAlloc().

HAL_StatusTypeDef HAL_HCD_PMAlloc | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint16_t | ch_kind,
 |  | uint16_t | mps
 | ) |  |

Allocate PMA buffer for Channel This API will fetch a free space.

Parameters:
hhcd | Host instance
ch_num | Channel number
ch_kind | endpoint Kind USB_SNG_BUF Single Buffer used USB_DBL_BUF Double Buffer used
mps | Channel Max Packet Size
Return values:
HAL status

Definition at line 2581 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ep0_PmaAllocState, HAL_HCD_GetFreePMA(), HAL_HCD_PMAFree(), __HCD_HandleTypeDef::hc, and HCD_SNG_BUF.

Referenced by HAL_HCD_HC_Init().

HAL_StatusTypeDef HAL_HCD_PMAReset ( HCD_HandleTypeDef * hhcd )

PMA Reset.

Parameters:
hhcd Host instance
Return values:
HAL status

Definition at line 2733 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::Init, PMA_BLOCKS, and __HCD_HandleTypeDef::PMALookupTable.

Referenced by HAL_HCD_DeInit(), HAL_HCD_Init(), HAL_HCD_Stop(), and HCD_Port_IRQHandler().

static void HCD_HC_IN_BulkDb | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | phy_chnum,
 |  | uint32_t | regvalue
 | ) |  | [static]

Handle Host Channel IN Double Buffer Bulk requests.

Parameters:
hhcd | HCD handle
ch_num | Channel number: This parameter can be a value from 1 to 15
phy_chnum | Physical Channel number [0..7]
regvalue | contain Snapshot of the EPCHn register when ISR is detected
Return values:
none

Definition at line 1678 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc, HCD_FREE_USER_BUFFER, HCD_GET_CH_DBUF0_CNT(), HCD_GET_CH_DBUF1_CNT(), HCD_SET_CH_RX_STATUS, and __HCD_HandleTypeDef::Instance.

Referenced by HCD_HC_IN_IRQHandler().

static void HCD_HC_IN_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  | [static]

Handle Host Channel IN interrupt requests.

Parameters:
hhcd | HCD handle
ch_num | Channel number This parameter can be a value from 1 to 15
Return values:
none

Definition at line 1836 of file stm32g0xx_hal_hcd.c.

References __HAL_HCD_GET_CHNUM, HAL_HCD_HC_Halt(), HAL_HCD_HC_NotifyURBChange_Callback(), __HCD_HandleTypeDef::hc, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, HCD_CLEAR_RX_CH_CTR, HCD_CLEAR_RX_CH_ERR, HCD_GET_CH_RX_CNT(), HCD_GET_CHANNEL, HCD_HC_IN_BulkDb(), HCD_HC_IN_ISO(), HCD_SET_CH_RX_STATUS, and __HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_HC_IN_ISO | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | phy_chnum,
 |  | uint32_t | regvalue
 | ) |  | [inline, static]

Handle Host Channel IN Isochronous Transaction.

Parameters:
hhcd | HCD handle
ch_num | Channel number: This parameter can be a value from 1 to 15
phy_chnum | Physical Channel number [0..7]
regvalue | contain Snapshot of the EPCHn register when ISR is detected
Return values:
none

Definition at line 1768 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc, HCD_CLEAR_RX_CH_CTR, HCD_GET_CH_DBUF0_CNT(), HCD_GET_CH_DBUF1_CNT(), HCD_GET_CH_RX_CNT(), and __HCD_HandleTypeDef::Instance.

Referenced by HCD_HC_IN_IRQHandler().

static void HCD_HC_OUT_BulkDb | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | phy_chnum,
 |  | uint32_t | regvalue
 | ) |  | [static]

Handle Host Channel OUT Double Buffer Bulk requests.

Parameters:
hhcd | HCD handle
ch_num | Channel number This parameter can be a value from 1 to 15
phy_chnum | Physical Channel number [0..7]
regvalue | contain Snapshot of the EPCHn register when ISR is detected
Return values:
none

Definition at line 1532 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::hc, HCD_CLEAR_RX_DTOG, HCD_CLEAR_TX_DTOG, HCD_RX_DTOG, HCD_SET_CH_DBUF0_CNT, HCD_SET_CH_DBUF1_CNT, HCD_SET_CH_TX_STATUS, HCD_TX_DTOG, and __HCD_HandleTypeDef::Instance.

Referenced by HCD_HC_OUT_IRQHandler().

static void HCD_HC_OUT_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

Handle Host Channel OUT interrupt requests.

Parameters:
hhcd | HCD handle
chnum | Channel number This parameter can be a value from 1 to 15
Return values:
none

Definition at line 1979 of file stm32g0xx_hal_hcd.c.

References __HAL_HCD_GET_CHNUM, HAL_HCD_HC_Halt(), HAL_HCD_HC_NotifyURBChange_Callback(), __HCD_HandleTypeDef::hc, __HCD_HandleTypeDef::HC_NotifyURBChangeCallback, HCD_CLEAR_TX_CH_CTR, HCD_CLEAR_TX_CH_ERR, HCD_HC_OUT_BulkDb(), HCD_SET_CH_RX_CNT, HCD_SET_CH_TX_CNT, HCD_SET_CH_TX_STATUS, HCD_SET_CHANNEL, and __HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_Port_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

Handle Host Port interrupt requests.

Parameters:
hhcd HCD handle
Return values:
None

Definition at line 2170 of file stm32g0xx_hal_hcd.c.

References __HCD_HandleTypeDef::ConnectCallback, __HCD_HandleTypeDef::DisconnectCallback, __HCD_HandleTypeDef::ep0_PmaAllocState, HAL_HCD_ClearPhyChannel(), HAL_HCD_Connect_Callback(), HAL_HCD_Disconnect_Callback(), HAL_HCD_PMAReset(), HCD_HCD_STATE_CONNECTED, HCD_HCD_STATE_DISCONNECTED, __HCD_HandleTypeDef::HostState, and __HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD State Structure definition

Defines | Typedefs | Enumerations
HCD State Structure definition
HCD Exported Types

Defines

#define | PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U))

Typedefs

typedef USB_DRD_TypeDef | HCD_TypeDef
typedef USB_DRD_CfgTypeDef | HCD_InitTypeDef
typedef USB_DRD_HCTypeDef | HCD_HCTypeDef
typedef USB_DRD_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_DRD_HCStateTypeDef | HCD_HCStateTypeDef

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}
enum HCD_HostStateTypeDef {
HCD_HCD_STATE_DISCONNECTED = 0x00U, HCD_HCD_STATE_CONNECTED = 0x01U, HCD_HCD_STATE_RESETED = 0x02U, HCD_HCD_STATE_RUN = 0x03U,
HCD_HCD_STATE_SUSPEND = 0x04U, HCD_HCD_STATE_RESUME = 0x05U
}

Define Documentation

#define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U))

Definition at line 75 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_GetFreePMA(), and HAL_HCD_PMAReset().

Typedef Documentation

typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef

Definition at line 60 of file stm32g0xx_hal_hcd.h.

typedef USB_DRD_HCTypeDef HCD_HCTypeDef

Definition at line 58 of file stm32g0xx_hal_hcd.h.

typedef USB_DRD_CfgTypeDef HCD_InitTypeDef

Definition at line 57 of file stm32g0xx_hal_hcd.h.

typedef USB_DRD_TypeDef HCD_TypeDef

Definition at line 56 of file stm32g0xx_hal_hcd.h.

typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef

Definition at line 59 of file stm32g0xx_hal_hcd.h.

Enumeration Type Documentation

enum HCD_HostStateTypeDef
Enumerator:
HCD_HCD_STATE_DISCONNECTED
HCD_HCD_STATE_CONNECTED
HCD_HCD_STATE_RESETED
HCD_HCD_STATE_RUN
HCD_HCD_STATE_SUSPEND
HCD_HCD_STATE_RESUME

Definition at line 62 of file stm32g0xx_hal_hcd.h.

enum HCD_StateTypeDef
Enumerator:
HAL_HCD_STATE_RESET
HAL_HCD_STATE_READY
HAL_HCD_STATE_ERROR
HAL_HCD_STATE_BUSY
HAL_HCD_STATE_TIMEOUT

Definition at line 47 of file stm32g0xx_hal_hcd.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Handle Structure definition

Data Structures | Typedefs
HCD Handle Structure definition
HCD Exported Types

Data Structures

struct | __HCD_HandleTypeDef

Typedefs

typedef struct __HCD_HandleTypeDef | HCD_HandleTypeDef

Typedef Documentation

typedef struct __HCD_HandleTypeDef HCD_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __HCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__HCD_HandleTypeDef Struct Reference
HCD Handle Structure definition

#include <stm32g0xx_hal_hcd.h>

Data Fields

HCD_TypeDef * Instance
HCD_InitTypeDef Init
HCD_HCTypeDef | hc [16]
uint32_t | ep0_PmaAllocState
uint16_t | phy_chin_state [8]
uint16_t | phy_chout_state [8]
uint32_t | PMALookupTable [PMA_BLOCKS]
HCD_HostStateTypeDef HostState
HAL_LockTypeDef | Lock
__IO HCD_StateTypeDef | State
__IO uint32_t | ErrorCode
void * | pData
void(* | SOFCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | ConnectCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | DisconnectCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | PortEnabledCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | PortDisabledCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | HC_NotifyURBChangeCallback )(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
void(* | MspInitCallback )(struct __HCD_HandleTypeDef *hhcd)
void(* | MspDeInitCallback )(struct __HCD_HandleTypeDef *hhcd)

Detailed Description

Definition at line 84 of file stm32g0xx_hal_hcd.h.

Field Documentation

void(* __HCD_HandleTypeDef::ConnectCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Connect callback

Definition at line 103 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterCallback(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

void(* __HCD_HandleTypeDef::DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Disconnect callback

Definition at line 104 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterCallback(), HAL_HCD_UnRegisterCallback(), and HCD_Port_IRQHandler().

uint32_t __HCD_HandleTypeDef::ep0_PmaAllocState

EP0 PMA allocation State (allocated, virtual Ch, EP0 direction)

Definition at line 92 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_HC_Init(), HAL_HCD_PMAlloc(), HAL_HCD_Stop(), and HCD_Port_IRQHandler().

__IO uint32_t __HCD_HandleTypeDef::ErrorCode

HCD Error code

Definition at line 99 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_RegisterCallback(), HAL_HCD_RegisterHC_NotifyURBChangeCallback(), HAL_HCD_UnRegisterCallback(), HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(), and I2C_ITError().

HCD_HCTypeDef __HCD_HandleTypeDef::hc[16]

Host channels parameters

Definition at line 91 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_HC_Close(), HAL_HCD_HC_GetState(), HAL_HCD_HC_GetURBState(), HAL_HCD_HC_GetXferCount(), HAL_HCD_HC_Halt(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HAL_HCD_PMADeAlloc(), HAL_HCD_PMAlloc(), HCD_HC_IN_BulkDb(), HCD_HC_IN_IRQHandler(), HCD_HC_IN_ISO(), HCD_HC_OUT_BulkDb(), and HCD_HC_OUT_IRQHandler().

void(* __HCD_HandleTypeDef::HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)

USB OTG HCD Host Channel Notify URB Change callback

Definition at line 107 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterHC_NotifyURBChangeCallback(), HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(), HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

HCD_HostStateTypeDef __HCD_HandleTypeDef::HostState

USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME

Definition at line 96 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_ResetPort(), and HCD_Port_IRQHandler().

HCD_InitTypeDef __HCD_HandleTypeDef::Init

HCD required parameters

Definition at line 90 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Check_usedChannel(), HAL_HCD_ClearPhyChannel(), HAL_HCD_DeInit(), HAL_HCD_Get_FreePhyChannel(), HAL_HCD_HC_Init(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), and HAL_HCD_PMAReset().

HCD_TypeDef* __HCD_HandleTypeDef::Instance

Register base address

Definition at line 89 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_GetCurrentFrame(), HAL_HCD_GetCurrentSpeed(), HAL_HCD_HC_Halt(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_ResetPort(), HAL_HCD_Resume(), HAL_HCD_ResumePort(), HAL_HCD_Start(), HAL_HCD_Stop(), HAL_HCD_Suspend(), HCD_HC_IN_BulkDb(), HCD_HC_IN_IRQHandler(), HCD_HC_IN_ISO(), HCD_HC_OUT_BulkDb(), HCD_HC_OUT_IRQHandler(), and HCD_Port_IRQHandler().

HAL_LockTypeDef __HCD_HandleTypeDef::Lock

HCD peripheral status

Definition at line 97 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init().

void(* __HCD_HandleTypeDef::MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Msp DeInit callback

Definition at line 111 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

void(* __HCD_HandleTypeDef::MspInitCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Msp Init callback

Definition at line 110 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

void* __HCD_HandleTypeDef::pData

Pointer Stack Handler

Definition at line 100 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

uint16_t __HCD_HandleTypeDef::phy_chin_state[8]

Physical Channel in State (Used/Free)

Definition at line 93 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Check_usedChannel(), HAL_HCD_ClearPhyChannel(), HAL_HCD_DeInit(), HAL_HCD_Get_FreePhyChannel(), HAL_HCD_GetLogical_Channel(), and HAL_HCD_HC_Close().

uint16_t __HCD_HandleTypeDef::phy_chout_state[8]

Physical Channel out State (Used/Free)

Definition at line 94 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Check_usedChannel(), HAL_HCD_ClearPhyChannel(), HAL_HCD_DeInit(), HAL_HCD_Get_FreePhyChannel(), HAL_HCD_GetLogical_Channel(), and HAL_HCD_HC_Close().

uint32_t __HCD_HandleTypeDef::PMALookupTable[PMA_BLOCKS]

Definition at line 95 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_GetFreePMA(), HAL_HCD_PMAFree(), and HAL_HCD_PMAReset().

void(* __HCD_HandleTypeDef::PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Port Disable callback

Definition at line 106 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

void(* __HCD_HandleTypeDef::PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD Port Enable callback

Definition at line 105 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

void(* __HCD_HandleTypeDef::SOFCallback)(struct __HCD_HandleTypeDef *hhcd)

USB OTG HCD SOF callback

Definition at line 102 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_RegisterCallback(), and HAL_HCD_UnRegisterCallback().

__IO HCD_StateTypeDef __HCD_HandleTypeDef::State

HCD communication state

Definition at line 98 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_GetState(), HAL_HCD_Init(), HAL_HCD_RegisterCallback(), HAL_HCD_RegisterHC_NotifyURBChangeCallback(), HAL_HCD_UnRegisterCallback(), and HAL_HCD_UnRegisterHC_NotifyURBChangeCallback().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_hcd.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Speed

Defines
HCD Speed
HCD Exported Constants

Defines

#define | HCD_SPEED_FULL USBH_FSLS_SPEED
#define | HCD_SPEED_LOW USBH_FSLS_SPEED

Define Documentation

#define HCD_SPEED_FULL USBH_FSLS_SPEED

Definition at line 130 of file stm32g0xx_hal_hcd.h.

#define HCD_SPEED_LOW USBH_FSLS_SPEED

Definition at line 131 of file stm32g0xx_hal_hcd.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Device Speed

Defines
HCD Device Speed
HCD Exported Constants

Defines

#define | HCD_DEVICE_SPEED_HIGH 0U
#define | HCD_DEVICE_SPEED_FULL 1U
#define | HCD_DEVICE_SPEED_LOW 2U

Define Documentation

#define HCD_DEVICE_SPEED_FULL 1U

Definition at line 140 of file stm32g0xx_hal_hcd.h.

#define HCD_DEVICE_SPEED_HIGH 0U

Definition at line 139 of file stm32g0xx_hal_hcd.h.

#define HCD_DEVICE_SPEED_LOW 2U

Definition at line 141 of file stm32g0xx_hal_hcd.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD PHY Module

Defines
HCD PHY Module
HCD Exported Constants

Defines

#define | HCD_PHY_ULPI 1U
#define | HCD_PHY_EMBEDDED 2U

Define Documentation

#define HCD_PHY_EMBEDDED 2U

Definition at line 150 of file stm32g0xx_hal_hcd.h.

#define HCD_PHY_ULPI 1U

Definition at line 149 of file stm32g0xx_hal_hcd.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Error Code definition

Defines
HCD Error Code definition
HCD Exported Constants

HCD Error Code definition. More...

Defines

#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U)

Detailed Description

HCD Error Code definition.

Define Documentation

#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U)

Invalid Callback error

Definition at line 160 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_RegisterCallback(), HAL_HCD_RegisterHC_NotifyURBChangeCallback(), HAL_HCD_UnRegisterCallback(), and HAL_HCD_UnRegisterHC_NotifyURBChangeCallback().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Exported Macros

Defines
HCD Exported Macros
HCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define | __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)
#define | __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_HCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))

Definition at line 181 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_DISABLE ( __HANDLE__ ) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 177 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Init().

#define __HAL_HCD_ENABLE ( __HANDLE__ ) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 176 of file stm32g0xx_hal_hcd.h.

#define __HAL_HCD_GET_CHDIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)

Definition at line 185 of file stm32g0xx_hal_hcd.h.

#define __HAL_HCD_GET_CHNUM ( __HANDLE__ ) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)

Definition at line 184 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((USB_ReadInterrupts((__HANDLE__)->Instance)\
                                                             & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 179 of file stm32g0xx_hal_hcd.h.

#define __HAL_HCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)

Definition at line 182 of file stm32g0xx_hal_hcd.h.

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Logical Channel

Defines
HCD Logical Channel
HCD Private Macros

Defines

#define | HCD_LOGICAL_CH_NOT_OPENED 0xFFU
#define | HCD_FREE_CH_NOT_FOUND 0xFFU

Define Documentation

#define HCD_FREE_CH_NOT_FOUND 0xFFU

Definition at line 337 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_Get_FreePhyChannel(), and HAL_HCD_HC_Init().

#define HCD_LOGICAL_CH_NOT_OPENED 0xFFU

Definition at line 336 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_GetLogical_Channel(), and HAL_HCD_IRQHandler().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Endpoint Kind

Defines
HCD Endpoint Kind
HCD Private Macros

Defines

#define | HCD_SNG_BUF 0U
#define | HCD_DBL_BUF 1U

Define Documentation

#define HCD_DBL_BUF 1U

Definition at line 346 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_HC_Init().

#define HCD_SNG_BUF 0U

Definition at line 345 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_HC_Init(), and HAL_HCD_PMAlloc().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HCD Private Macros

Modules | Defines | Functions
HCD Private Macros
HCD

Modules

HCD Logical Channel
HCD Endpoint Kind

Defines

#define | HCD_SET_CHANNEL USB_DRD_SET_CHEP
#define | HCD_GET_CHANNEL USB_DRD_GET_CHEP
#define | HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP
Set the Setup bit in the corresponding channel, when a Setup transaction is needed.
#define | HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
sets the status for rx transfer (bits STAT_TX[1:0])
#define | HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS
#define | HCD_SET_CH_KIND USB_DRD_SET_CH_KIND
Sets/clears CH_KIND bit in the Channel register.
#define | HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND
#define | HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND
#define | HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND
#define | HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR
Clears bit ERR_RX in the Channel register.
#define | HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR
Clears bit ERR_TX in the Channel register.
#define | HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR
#define | HCD_RX_DTOG USB_DRD_RX_DTOG
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | HCD_TX_DTOG USB_DRD_TX_DTOG
#define | HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
#define | HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT
sets counter for the tx/rx buffer.
#define | HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT
#define | HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT
gets counter of the tx buffer.
#define | HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
Gets buffer 0/1 address of a double buffer endpoint.
#define | HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
#define | HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT

Functions

__STATIC_INLINE uint16_t | HCD_GET_CH_RX_CNT (const HCD_TypeDef *Instance, uint16_t bChNum)
gets counter of the rx buffer.
__STATIC_INLINE uint16_t | HCD_GET_CH_DBUF0_CNT (const HCD_TypeDef *Instance, uint16_t bChNum)
gets counter of the rx buffer0.
__STATIC_INLINE uint16_t | HCD_GET_CH_DBUF1_CNT (const HCD_TypeDef *Instance, uint16_t bChNum)
gets counter of the rx buffer1.

Define Documentation

#define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP

Set the Setup bit in the corresponding channel, when a Setup transaction is needed.

Parameters:
USBx USB device.
bChNum
Return values:
None

Definition at line 374 of file stm32g0xx_hal_hcd.h.

#define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND

Definition at line 411 of file stm32g0xx_hal_hcd.h.

#define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND

Definition at line 409 of file stm32g0xx_hal_hcd.h.

#define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR

Clears bit CTR_RX / CTR_TX in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
Return values:
None

Definition at line 434 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_IN_ISO().

#define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR

Clears bit ERR_RX in the Channel register.

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
Return values:
None

Definition at line 419 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler().

#define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG

Clears DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
Return values:
None

Definition at line 451 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_HC_Init(), and HCD_HC_OUT_BulkDb().

#define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR

Definition at line 435 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_IRQHandler().

#define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR

Clears bit ERR_TX in the Channel register.

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
Return values:
None

Definition at line 427 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_IRQHandler().

#define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG

Definition at line 452 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_HC_Init(), and HCD_HC_OUT_BulkDb().

#define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER

free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register

Parameters:
USBx USB device.
bChNum,bDir
Return values:
None

Definition at line 365 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_IN_BulkDb().

#define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS

Definition at line 401 of file stm32g0xx_hal_hcd.h.

#define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT

gets counter of the tx buffer.

Parameters:
USBx | USB peripheral instance register address.
bChNum | channel Number.
Return values:
Counter value

Definition at line 470 of file stm32g0xx_hal_hcd.h.

#define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS

gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
Return values:
status

Definition at line 400 of file stm32g0xx_hal_hcd.h.

#define HCD_GET_CHANNEL USB_DRD_GET_CHEP

Definition at line 355 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler(), and HCD_HC_IN_IRQHandler().

#define HCD_RX_DTOG USB_DRD_RX_DTOG

Toggles DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
Return values:
None

Definition at line 443 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_BulkDb().

#define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND

Definition at line 410 of file stm32g0xx_hal_hcd.h.

#define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
bDir | endpoint dir EP_DBUF_OUT = OUT EP_DBUF_IN = IN
wCount,: Counter value
Return values:
None

Definition at line 501 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_BulkDb().

#define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT

Definition at line 502 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_BulkDb().

#define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT

Definition at line 503 of file stm32g0xx_hal_hcd.h.

#define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND

Sets/clears CH_KIND bit in the Channel register.

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
Return values:
None

Definition at line 408 of file stm32g0xx_hal_hcd.h.

#define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT

Definition at line 462 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_IRQHandler().

#define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS

sets the status for rx transfer (bits STAT_TX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 392 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_IN_BulkDb(), and HCD_HC_IN_IRQHandler().

#define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT

sets counter for the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
wCount | Counter value.
Return values:
None

Definition at line 461 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_IRQHandler().

#define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS

sets the status for tx transfer (bits STAT_TX[1:0]).

Parameters:
USBx | USB peripheral instance register address.
bChNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 383 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_BulkDb(), and HCD_HC_OUT_IRQHandler().

#define HCD_SET_CHANNEL USB_DRD_SET_CHEP

Definition at line 352 of file stm32g0xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define HCD_TX_DTOG USB_DRD_TX_DTOG

Definition at line 444 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_OUT_BulkDb().

Function Documentation

__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT | ( | const HCD_TypeDef * | Instance,
 |  | uint16_t | bChNum
 | ) |  |

gets counter of the rx buffer0.

Parameters:
Instance | USB peripheral instance register address.
bChNum | channel Number.
Return values:
Counter value

Definition at line 512 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_IN_BulkDb(), and HCD_HC_IN_ISO().

__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT | ( | const HCD_TypeDef * | Instance,
 |  | uint16_t | bChNum
 | ) |  |

gets counter of the rx buffer1.

Parameters:
Instance | USB peripheral instance register address.
bChNum | channel Number.
Return values:
Counter value

Definition at line 532 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_IN_BulkDb(), and HCD_HC_IN_ISO().

__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT | ( | const HCD_TypeDef * | Instance,
 |  | uint16_t | bChNum
 | ) |  |

gets counter of the rx buffer.

Parameters:
Instance | USB peripheral instance register address.
bChNum | channel Number.
Return values:
Counter value

Definition at line 478 of file stm32g0xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_IN_ISO().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Private Define

Defines
I2C Private Define
I2C

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SLAVE_ADDR_SHIFT 7U
#define | SLAVE_ADDR_MSK 0x06U
#define | I2C_STATE_MSK
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX
#define | I2C_STATE_MASTER_BUSY_RX
#define | I2C_STATE_SLAVE_BUSY_TX
#define | I2C_STATE_SLAVE_BUSY_RX
#define | I2C_STATE_MEM_BUSY_TX
#define | I2C_STATE_MEM_BUSY_RX
#define | I2C_XFER_TX_IT (uint16_t)(0x0001U)
#define | I2C_XFER_RX_IT (uint16_t)(0x0002U)
#define | I2C_XFER_LISTEN_IT (uint16_t)(0x8000U)
#define | I2C_XFER_ERROR_IT (uint16_t)(0x0010U)
#define | I2C_XFER_CPLT_IT (uint16_t)(0x0020U)
#define | I2C_XFER_RELOAD_IT (uint16_t)(0x0040U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)

Define Documentation

#define I2C_NO_OPTION_FRAME (0xFFFF0000U)

Definition at line 398 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMASlaveReceiveCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_STATE_MASTER_BUSY_RX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 367 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), I2C_ITError(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MASTER_BUSY_TX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 364 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ITError(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MEM_BUSY_RX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 379 of file stm32g0xx_hal_i2c.c.

#define I2C_STATE_MEM_BUSY_TX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 376 of file stm32g0xx_hal_i2c.c.

#define I2C_STATE_MSK
Value:
((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
                                                         (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
                                              (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))

Mask State define, keep only RX and TX bits

Definition at line 358 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 362 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_TreatErrorCallback().

#define I2C_STATE_SLAVE_BUSY_RX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 373 of file stm32g0xx_hal_i2c.c.

Referenced by I2C_ITError(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), and I2C_Slave_ISR_DMA().

#define I2C_STATE_SLAVE_BUSY_TX
Value:
((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
                                              (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 370 of file stm32g0xx_hal_i2c.c.

Referenced by I2C_ITError(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), and I2C_Slave_ISR_DMA().

#define I2C_TIMEOUT_ADDR (10000U)

10 s

Definition at line 343 of file stm32g0xx_hal_i2c.c.

#define I2C_TIMEOUT_BUSY (25U)

25 ms

Definition at line 344 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Write().

#define I2C_TIMEOUT_DIR (25U)

25 ms

Definition at line 345 of file stm32g0xx_hal_i2c.c.

#define I2C_TIMEOUT_FLAG (25U)

25 ms

Definition at line 351 of file stm32g0xx_hal_i2c.c.

#define I2C_TIMEOUT_RXNE (25U)

25 ms

Definition at line 346 of file stm32g0xx_hal_i2c.c.

#define I2C_TIMEOUT_STOPF (25U)

25 ms

Definition at line 347 of file stm32g0xx_hal_i2c.c.

Referenced by I2C_IsErrorOccurred().

#define I2C_TIMEOUT_TC (25U)

25 ms

Definition at line 348 of file stm32g0xx_hal_i2c.c.

#define I2C_TIMEOUT_TCR (25U)

25 ms

Definition at line 349 of file stm32g0xx_hal_i2c.c.

#define I2C_TIMEOUT_TXIS (25U)

25 ms

Definition at line 350 of file stm32g0xx_hal_i2c.c.

#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U)

Bit definition to manage only STOP evenement

Definition at line 394 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), and I2C_Mem_ISR_DMA().

#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U)

Bit definition to manage addition of global Error and NACK treatment

Definition at line 392 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), and I2C_Mem_ISR_DMA().

#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U)

Bit field can be combinated with I2C_XFER_TX_IT and I2C_XFER_RX_IT

Definition at line 389 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U)

Bit definition to manage only Reload of NBYTE

Definition at line 395 of file stm32g0xx_hal_i2c.c.

Referenced by I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Enable_IRQ().

#define I2C_XFER_RX_IT (uint16_t)(0x0002U)

Bit field can be combinated with I2C_XFER_LISTEN_IT

Definition at line 387 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

#define I2C_XFER_TX_IT (uint16_t)(0x0001U)

Bit field can be combinated with I2C_XFER_LISTEN_IT

Definition at line 385 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

#define MAX_NBYTE_SIZE 255U

Definition at line 353 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define SLAVE_ADDR_MSK 0x06U

Definition at line 355 of file stm32g0xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define SLAVE_ADDR_SHIFT 7U

Definition at line 354 of file stm32g0xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define TIMING_CLEAR_MASK (0xF0FFFFFFU)

I2C TIMING clear register Mask

Definition at line 342 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Private Functions

Functions
I2C Private Functions
I2C

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Mem_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Mem_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsErrorOccurred (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles errors detection during an I2C Communication.
static void | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static void | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_TreatErrorCallback (I2C_HandleTypeDef *hi2c)
I2C Error callback treatment.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | I2C_ConvertOtherXferOptions (I2C_HandleTypeDef *hi2c)
Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.

Function Documentation

static void I2C_ConvertOtherXferOptions ( I2C_HandleTypeDef * hi2c ) [static]

Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 7125 of file stm32g0xx_hal_i2c.c.

References I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_OTHER_AND_LAST_FRAME, I2C_OTHER_FRAME, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), and HAL_I2C_Master_Seq_Transmit_IT().

static void I2C_Disable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
None

Definition at line 7062 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_STATE_LISTEN, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

static void I2C_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 6611 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_TreatErrorCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), and I2C_ITError().

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6593 of file stm32g0xx_hal_i2c.c.

References HAL_I2C_ERROR_DMA, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6515 of file stm32g0xx_hal_i2c.c.

References HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmarx, I2C_Enable_IRQ(), I2C_ITError(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), and HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6437 of file stm32g0xx_hal_i2c.c.

References HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmatx, I2C_Enable_IRQ(), I2C_ITError(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6565 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::hdmarx, I2C_GET_DMA_REMAIN_DATA, I2C_ITSlaveSeqCplt(), I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Seq_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6487 of file stm32g0xx_hal_i2c.c.

References I2C_FIRST_FRAME, I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_Enable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
None

Definition at line 6985 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_Master_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::XferISR.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), and I2C_Mem_ISR_DMA().

static void I2C_Flush_TXDR ( I2C_HandleTypeDef * hi2c ) [static]

I2C Tx data register flush process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 6416 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_FLAG_TXE, I2C_FLAG_TXIS, and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Slave_Transmit(), I2C_IsErrorOccurred(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_IsErrorOccurred | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles errors detection during an I2C Communication.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6817 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_OVR, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_BUSY, I2C_FLAG_OVR, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_RESET_CR2, I2C_TIMEOUT_STOPF, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

static void I2C_ITAddrCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Address complete process callback.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5691 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::AddrCallback, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::AddrEventCount, HAL_I2C_AddrCallback(), HAL_I2C_STATE_LISTEN, I2C_ADDRESSINGMODE_10BIT, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_GET_ADDR_MATCH, I2C_GET_DIR, I2C_GET_OWN_ADDRESS1, I2C_GET_OWN_ADDRESS2, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Init, SLAVE_ADDR_MSK, SLAVE_ADDR_SHIFT, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITError | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ErrorCode
 | ) |  | [static]

I2C interrupts error process.

Parameters:
hi2c | I2C handle.
ErrorCode | Error code to handle.
Return values:
None

Definition at line 6266 of file stm32g0xx_hal_i2c.c.

References __HCD_HandleTypeDef::ErrorCode, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_GetState(), HAL_DMA_STATE_READY, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_TreatErrorCallback(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITListenCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Listen complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 6215 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_CHECK_FLAG, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITMasterCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Master complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5913 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_CHECK_FLAG, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_STATE_NONE, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

static void I2C_ITMasterSeqCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Master sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5786 of file stm32g0xx_hal_i2c.c.

References HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITSlaveCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Slave complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 6056 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Disable_IRQ(), I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_GET_DMA_REMAIN_DATA, I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveSeqCplt(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITSlaveSeqCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Slave sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5839 of file stm32g0xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_CHECK_IT_SOURCE, I2C_Disable_IRQ(), I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

Referenced by I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_Master_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5163 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Master_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4739 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Master_Transmit_IT().

static HAL_StatusTypeDef I2C_Mem_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5303 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GENERATE_START_READ, I2C_GENERATE_START_WRITE, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Write_DMA().

static HAL_StatusTypeDef I2C_Mem_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4885 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GENERATE_START_READ, I2C_GENERATE_START_WRITE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Mem_Read_IT(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5642 of file stm32g0xx_hal_i2c.c.

References I2C_FLAG_TC, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5587 of file stm32g0xx_hal_i2c.c.

References I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write().

static HAL_StatusTypeDef I2C_Slave_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5442 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_GET_DMA_REMAIN_DATA, I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_STOPI, I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Slave_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5022 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TXI, I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), and I2C_ITError().

static void I2C_TransferConfig | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hi2c | I2C handle.
DevAddress | Specifies the slave address to be programmed.
Size | Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_RELOAD_MODE Enable Reload mode .
  • I2C_AUTOEND_MODE Enable Automatic end mode.
  • I2C_SOFTEND_MODE Enable Software end mode.
Request New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_NO_STARTSTOP Don't Generate stop and start condition.
  • I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • I2C_GENERATE_START_READ Generate Restart for read request.
  • I2C_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 6958 of file stm32g0xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static void I2C_TreatErrorCallback ( I2C_HandleTypeDef * hi2c ) [static]

I2C Error callback treatment.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 6378 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_STATE_ABORT, HAL_I2C_STATE_READY, I2C_STATE_NONE, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

Referenced by I2C_DMAAbort(), and I2C_ITError().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Flag | Specifies the I2C flag to check.
Status | The actual Flag status (SET or RESET).
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6640 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6744 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IsErrorOccurred(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6709 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsErrorOccurred(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6671 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_TXIS, I2C_IsErrorOccurred(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C peripheral.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 638 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 528 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::AddrCallback, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::DualAddressMode, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_AbortCpltCallback(), HAL_I2C_AddrCallback(), HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_ListenCpltCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, I2C_ADDRESSINGMODE_10BIT, I2C_ADDRESSINGMODE_7BIT, I2C_DUALADDRESS_ENABLE, I2C_STATE_NONE, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_DUAL_ADDRESS, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, IS_I2C_OWN_ADDRESS2_MASK, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Lock, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::MspInitCallback, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_InitTypeDef::OwnAddress2Masks, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, __I2C_HandleTypeDef::State, I2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 700 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), and HAL_I2C_UnRegisterCallback().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

Initialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 684 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), and HAL_I2C_UnRegisterCallback().

HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | pI2C_AddrCallbackTypeDef | pCallback
 | ) |  |

Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pCallback | pointer to the Address Match Callback function
Return values:
HAL status

Definition at line 962 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::AddrCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_STATE_READY, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_RegisterCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | HAL_I2C_CallbackIDTypeDef | CallbackID,
 |  | pI2C_CallbackTypeDef | pCallback
 | ) |  |

Register a User I2C Callback To be used instead of the weak predefined callback.

Note:
The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
  • HAL_I2C_ERROR_CB_ID Error callback ID
  • HAL_I2C_ABORT_CB_ID Abort callback ID
  • HAL_I2C_MSPINIT_CB_ID MspInit callback ID
  • HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 734 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ABORT_CB_ID, HAL_I2C_ERROR_CB_ID, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_LISTEN_COMPLETE_CB_ID, HAL_I2C_MASTER_RX_COMPLETE_CB_ID, HAL_I2C_MASTER_TX_COMPLETE_CB_ID, HAL_I2C_MEM_RX_COMPLETE_CB_ID, HAL_I2C_MEM_TX_COMPLETE_CB_ID, HAL_I2C_MSPDEINIT_CB_ID, HAL_I2C_MSPINIT_CB_ID, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::MspInitCallback, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback ( I2C_HandleTypeDef * hi2c )

UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 997 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::AddrCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_AddrCallback(), HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_STATE_READY, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_UnRegisterCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | HAL_I2C_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.

Note:
The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
  • HAL_I2C_ERROR_CB_ID Error callback ID
  • HAL_I2C_ABORT_CB_ID Abort callback ID
  • HAL_I2C_MSPINIT_CB_ID MspInit callback ID
  • HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 860 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ABORT_CB_ID, HAL_I2C_AbortCpltCallback(), HAL_I2C_ERROR_CB_ID, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_ErrorCallback(), HAL_I2C_LISTEN_COMPLETE_CB_ID, HAL_I2C_ListenCpltCallback(), HAL_I2C_MASTER_RX_COMPLETE_CB_ID, HAL_I2C_MASTER_TX_COMPLETE_CB_ID, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MEM_RX_COMPLETE_CB_ID, HAL_I2C_MEM_TX_COMPLETE_CB_ID, HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MspDeInit(), HAL_I2C_MSPDEINIT_CB_ID, HAL_I2C_MspInit(), HAL_I2C_MSPINIT_CB_ID, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::MspInitCallback, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()
        (++) HAL_I2C_Master_Seq_Transmit_IT()
        (++) HAL_I2C_Master_Seq_Receive_IT()
        (++) HAL_I2C_Slave_Seq_Transmit_IT()
        (++) HAL_I2C_Slave_Seq_Receive_IT()
        (++) HAL_I2C_EnableListen_IT()
        (++) HAL_I2C_DisableListen_IT()
        (++) HAL_I2C_Master_Abort_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()
        (++) HAL_I2C_Master_Seq_Transmit_DMA()
        (++) HAL_I2C_Master_Seq_Receive_DMA()
        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
        (++) HAL_I2C_Slave_Seq_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_AddrCallback()
        (++) HAL_I2C_ListenCpltCallback()
        (++) HAL_I2C_ErrorCallback()
        (++) HAL_I2C_AbortCpltCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C
Return values:
HAL status

Definition at line 4343 of file stm32g0xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MSK, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 4319 of file stm32g0xx_hal_i2c.c.

References HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3101 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_GENERATE_START, I2C_WaitOnFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master I2C IT or DMA process communication with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 4376 of file stm32g0xx_hal_i2c.c.

References HAL_I2C_MODE_MASTER, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, I2C_AUTOEND_MODE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_GENERATE_STOP, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1226 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2006 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1688 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3589 of file stm32g0xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_ConvertOtherXferOptions(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3502 of file stm32g0xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_ConvertOtherXferOptions(), I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3334 of file stm32g0xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_ConvertOtherXferOptions(), I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3243 of file stm32g0xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ConvertOtherXferOptions(), I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1107 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1859 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1617 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2500 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 2956 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_Mem_ISR_DMA(), I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2724 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_Mem_ISR_IT(), I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2363 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2810 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_Mem_ISR_DMA(), I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2637 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::Devaddress, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_Mem_ISR_IT(), I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, __I2C_HandleTypeDef::Memaddress, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1487 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2255 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1807 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 4139 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 4039 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3855 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3755 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1344 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2151 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1757 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __HCD_HandleTypeDef::pData, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
I2C Exported Functions

Functions

void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.

Function Documentation

void HAL_I2C_AbortCpltCallback ( I2C_HandleTypeDef * hi2c )

I2C abort callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4656 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_TreatErrorCallback().

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection | Master request Transfer Direction (Write/Read), value of I2C Transfer Direction Master Point of View
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 4574 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterAddrCallback(), and I2C_ITAddrCplt().

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4457 of file stm32g0xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERRI, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4640 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_TreatErrorCallback().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4438 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferISR.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4592 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4525 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4509 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4624 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4608 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4556 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4540 of file stm32g0xx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
I2C Exported Functions

Peripheral State, Mode and Error functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State, Mode and Error functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 4714 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( I2C_HandleTypeDef * hi2c )

Returns the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 4703 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Return the I2C handle state.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 4691 of file stm32g0xx_hal_i2c.c.

References __I2C_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Configuration Structure definition

#include <stm32g0xx_hal_i2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 47 of file stm32g0xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C Addressing Mode

Definition at line 56 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C Dual Addressing Mode

Definition at line 59 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C General Call Addressing Mode

Definition at line 69 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C No-Stretch Mode

Definition at line 72 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 53 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 62 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected. This parameter can be a value of I2C Own Address2 Masks

Definition at line 65 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::Timing

Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

Definition at line 49 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_i2c.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
I2C Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}

Detailed Description

HAL State structure definition.

Note:
HAL I2C State value coding follow below described bitmap :
b7-b6 Error information
00 : No Error
01 : Abort (Abort user request on going)
10 : Timeout
11 : Error
b5 Peripheral initialization status
0 : Reset (peripheral not initialized)
1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)
b4 (not used)
x : Should be set to 0
b3
0 : Ready or Busy (No Listen mode ongoing)
1 : Listen (peripheral in Address Listen Mode)
b2 Intrinsic process state
0 : Ready
1 : Busy (peripheral busy with some configuration or internal operations)
b1 Rx state
0 : Ready (no Rx operation ongoing)
1 : Busy (Rx operation ongoing)
b0 Tx state
0 : Ready (no Tx operation ongoing)
1 : Busy (Tx operation ongoing)

Enumeration Type Documentation

enum HAL_I2C_StateTypeDef
Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_ABORT

Abort user request ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Error

Definition at line 108 of file stm32g0xx_hal_i2c.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL mode structure definition

Enumerations
HAL mode structure definition
I2C Exported Types

HAL Mode structure definition. More...

Enumerations

enum HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Detailed Description

HAL Mode structure definition.

Note:
HAL I2C Mode value coding follow below described bitmap :
b7 (not used)
x : Should be set to 0
b6
0 : None
1 : Memory (HAL I2C communication is in Memory Mode)
b5
0 : None
1 : Slave (HAL I2C communication is in Slave Mode)
b4
0 : None
1 : Master (HAL I2C communication is in Master Mode)
b3-b2-b1-b0 (not used)
xxxx : Should be set to 0000

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef
Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 148 of file stm32g0xx_hal_i2c.h.

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STM32G0C1xx HAL User Manual: I2C Error Code definition

Defines
I2C Error Code definition
I2C Exported Types

I2C Error Code definition. More...

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
#define | HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)

Detailed Description

I2C Error Code definition.

Define Documentation

#define HAL_I2C_ERROR_AF (0x00000004U)

ACKF error

Definition at line 168 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_IsErrorOccurred(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 167 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define HAL_I2C_ERROR_BERR (0x00000001U)

BERR error

Definition at line 166 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define HAL_I2C_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 170 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)

DMA Parameter Error

Definition at line 173 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)

Invalid Callback error

Definition at line 175 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterAddrCallback(), and HAL_I2C_UnRegisterCallback().

#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)

Invalid Parameters error

Definition at line 177 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), and HAL_I2C_Slave_Transmit_DMA().

#define HAL_I2C_ERROR_NONE (0x00000000U)

No error

Definition at line 165 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR (0x00000008U)

OVR error

Definition at line 169 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define HAL_I2C_ERROR_SIZE (0x00000040U)

Size Management error

Definition at line 172 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define HAL_I2C_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 171 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsErrorOccurred(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C handle Structure definition

Data Structures | Typedefs | Enumerations
I2C handle Structure definition
I2C Exported Types

I2C handle Structure definition. More...

Data Structures

struct | __I2C_HandleTypeDef

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef
typedef void(* | pI2C_CallbackTypeDef )(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
typedef void(* | pI2C_AddrCallbackTypeDef )(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_I2C_CallbackIDTypeDef {
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, HAL_I2C_ERROR_CB_ID = 0x07U,
HAL_I2C_ABORT_CB_ID = 0x08U, HAL_I2C_MSPINIT_CB_ID = 0x09U, HAL_I2C_MSPDEINIT_CB_ID = 0x0AU
}
HAL I2C Callback ID enumeration definition. More...

Detailed Description

I2C handle Structure definition.

Typedef Documentation

typedef struct __I2C_HandleTypeDef I2C_HandleTypeDef
typedef void(* pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

pointer to an I2C Address Match callback function

Definition at line 281 of file stm32g0xx_hal_i2c.h.

typedef void(* pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c)

HAL I2C Callback pointer definition.

pointer to an I2C callback function

Definition at line 279 of file stm32g0xx_hal_i2c.h.

Enumeration Type Documentation

enum HAL_I2C_CallbackIDTypeDef

HAL I2C Callback ID enumeration definition.

Enumerator:
HAL_I2C_MASTER_TX_COMPLETE_CB_ID

I2C Master Tx Transfer completed callback ID

HAL_I2C_MASTER_RX_COMPLETE_CB_ID

I2C Master Rx Transfer completed callback ID

HAL_I2C_SLAVE_TX_COMPLETE_CB_ID

I2C Slave Tx Transfer completed callback ID

HAL_I2C_SLAVE_RX_COMPLETE_CB_ID

I2C Slave Rx Transfer completed callback ID

HAL_I2C_LISTEN_COMPLETE_CB_ID

I2C Listen Complete callback ID

HAL_I2C_MEM_TX_COMPLETE_CB_ID

I2C Memory Tx Transfer callback ID

HAL_I2C_MEM_RX_COMPLETE_CB_ID

I2C Memory Rx Transfer completed callback ID

HAL_I2C_ERROR_CB_ID

I2C Error callback ID

HAL_I2C_ABORT_CB_ID

I2C Abort callback ID

HAL_I2C_MSPINIT_CB_ID

I2C Msp Init callback ID

HAL_I2C_MSPDEINIT_CB_ID

I2C Msp DeInit callback ID

Definition at line 259 of file stm32g0xx_hal_i2c.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2C_HandleTypeDef Struct Reference
I2C handle Structure definition

#include <stm32g0xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_StatusTypeDef(* | XferISR )(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | AddrEventCount
__IO uint32_t | Devaddress
__IO uint32_t | Memaddress
void(* | MasterTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MasterRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | SlaveTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | SlaveRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | ListenCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MemTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MemRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | ErrorCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | AbortCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | AddrCallback )(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
void(* | MspInitCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MspDeInitCallback )(struct __I2C_HandleTypeDef *hi2c)

Detailed Description

Definition at line 186 of file stm32g0xx_hal_i2c.h.

Field Documentation

void(* __I2C_HandleTypeDef::AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Abort callback

Definition at line 241 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_TreatErrorCallback().

void(* __I2C_HandleTypeDef::AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

I2C Slave Address Match callback

Definition at line 244 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_UnRegisterAddrCallback(), and I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::AddrEventCount

I2C Address Event counter

Definition at line 218 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::Devaddress

I2C Target device address

Definition at line 220 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

void(* __I2C_HandleTypeDef::ErrorCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Error callback

Definition at line 239 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_TreatErrorCallback().

__IO uint32_t __I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 216 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2C_UnRegisterAddrCallback(), HAL_I2C_UnRegisterCallback(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 208 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_DMAAbort(), I2C_DMAMasterReceiveCplt(), I2C_DMASlaveReceiveCplt(), I2C_ITError(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 206 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAAbort(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

I2C_InitTypeDef __I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 190 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

I2C_TypeDef* __I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 188 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_Flush_TXDR(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_IT(), and I2C_TransferConfig().

void(* __I2C_HandleTypeDef::ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Listen Complete callback

Definition at line 233 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

HAL_LockTypeDef __I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 210 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

void(* __I2C_HandleTypeDef::MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Master Rx Transfer completed callback

Definition at line 227 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void(* __I2C_HandleTypeDef::MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Master Tx Transfer completed callback

Definition at line 225 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

__IO uint32_t __I2C_HandleTypeDef::Memaddress

I2C Target memory address

Definition at line 222 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

void(* __I2C_HandleTypeDef::MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Memory Rx Transfer completed callback

Definition at line 237 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void(* __I2C_HandleTypeDef::MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Memory Tx Transfer completed callback

Definition at line 235 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

__IO HAL_I2C_ModeTypeDef __I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 214 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsErrorOccurred(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

void(* __I2C_HandleTypeDef::MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Msp DeInit callback

Definition at line 249 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_RegisterCallback(), and HAL_I2C_UnRegisterCallback().

void(* __I2C_HandleTypeDef::MspInitCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Msp Init callback

Definition at line 247 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), and HAL_I2C_UnRegisterCallback().

uint8_t* __I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 192 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Mem_ISR_IT(), and I2C_Slave_ISR_IT().

__IO uint32_t __I2C_HandleTypeDef::PreviousState

I2C communication Previous state

Definition at line 201 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Slave_ISR_DMA(), and I2C_TreatErrorCallback().

void(* __I2C_HandleTypeDef::SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Slave Rx Transfer completed callback

Definition at line 231 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void(* __I2C_HandleTypeDef::SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Slave Tx Transfer completed callback

Definition at line 229 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

__IO HAL_I2C_StateTypeDef __I2C_HandleTypeDef::State

I2C communication state

Definition at line 212 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2C_UnRegisterAddrCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_Disable_IRQ(), I2C_IsErrorOccurred(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Master_ISR_DMA(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_TreatErrorCallback(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

__IO uint16_t __I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 196 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_Slave_ISR_IT().

HAL_StatusTypeDef(* __I2C_HandleTypeDef::XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)

I2C transfer IRQ handler function pointer

Definition at line 203 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), and I2C_ITSlaveCplt().

__IO uint32_t __I2C_HandleTypeDef::XferOptions

I2C sequantial transfer options, this parameter can be a value of I2C Sequential Transfer Options

Definition at line 198 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ConvertOtherXferOptions(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

uint16_t __I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 194 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_i2c.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Sequential Transfer Options

Defines
I2C Sequential Transfer Options
I2C Exported Constants

Defines

#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_OTHER_FRAME (0x000000AAU)
#define | I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 305 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 303 of file stm32g0xx_hal_i2c.h.

#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 302 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions(), I2C_DMASlaveTransmitCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 306 of file stm32g0xx_hal_i2c.h.

#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 307 of file stm32g0xx_hal_i2c.h.

#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 304 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_DMASlaveTransmitCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)

Definition at line 313 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions().

#define I2C_OTHER_FRAME (0x000000AAU)

Definition at line 312 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Addressing Mode

Defines
I2C Addressing Mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 322 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 321 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

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STM32G0C1xx HAL User Manual: I2C Dual Addressing Mode

Defines
I2C Dual Addressing Mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define I2C_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 330 of file stm32g0xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 331 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Own Address2 Masks

Defines
I2C Own Address2 Masks
I2C Exported Constants

Defines

#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define I2C_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 340 of file stm32g0xx_hal_i2c.h.

#define I2C_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 341 of file stm32g0xx_hal_i2c.h.

#define I2C_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 342 of file stm32g0xx_hal_i2c.h.

#define I2C_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 343 of file stm32g0xx_hal_i2c.h.

#define I2C_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 344 of file stm32g0xx_hal_i2c.h.

#define I2C_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 345 of file stm32g0xx_hal_i2c.h.

#define I2C_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 346 of file stm32g0xx_hal_i2c.h.

#define I2C_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 339 of file stm32g0xx_hal_i2c.h.

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STM32G0C1xx HAL User Manual: I2C General Call Addressing Mode

Defines
I2C General Call Addressing Mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define I2C_GENERALCALL_DISABLE (0x00000000U)

Definition at line 354 of file stm32g0xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 355 of file stm32g0xx_hal_i2c.h.

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STM32G0C1xx HAL User Manual: I2C No-Stretch Mode

Defines
I2C No-Stretch Mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 363 of file stm32g0xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 364 of file stm32g0xx_hal_i2c.h.

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STM32G0C1xx HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT (0x00000002U)

Definition at line 373 of file stm32g0xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT (0x00000001U)

Definition at line 372 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

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STM32G0C1xx HAL User Manual: I2C Transfer Direction Master Point of View

Defines
I2C Transfer Direction Master Point of View
I2C Exported Constants

Defines

#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)

Define Documentation

#define I2C_DIRECTION_RECEIVE (0x00000001U)

Definition at line 382 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Seq_Transmit_IT().

#define I2C_DIRECTION_TRANSMIT (0x00000000U)

Definition at line 381 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), and HAL_I2C_Slave_Seq_Receive_IT().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Reload End Mode

Defines
I2C Reload End Mode
I2C Exported Constants

Defines

#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)

Define Documentation

#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 391 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define I2C_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 390 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_SOFTEND_MODE (0x00000000U)

Definition at line 392 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), and I2C_RequestMemoryRead().

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STM32G0C1xx HAL User Manual: I2C Start or Stop Mode

Defines
I2C Start or Stop Mode
I2C Exported Constants

Defines

#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 402 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Mem_Read(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Definition at line 403 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Definition at line 401 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT().

#define I2C_NO_STARTSTOP (0x00000000U)

Definition at line 400 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

I2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE

Detailed Description

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define I2C_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 418 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_ERRI I2C_CR1_ERRIE

Definition at line 414 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_IT_NACKI I2C_CR1_NACKIE

Definition at line 417 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_RXI I2C_CR1_RXIE

Definition at line 419 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), I2C_Mem_ISR_IT(), and I2C_Slave_ISR_IT().

#define I2C_IT_STOPI I2C_CR1_STOPIE

Definition at line 416 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_TCI I2C_CR1_TCIE

Definition at line 415 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), and I2C_Mem_ISR_IT().

#define I2C_IT_TXI I2C_CR1_TXIE

Definition at line 420 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_Slave_ISR_IT().

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STM32G0C1xx HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR

Define Documentation

#define I2C_FLAG_ADDR I2C_ISR_ADDR

Definition at line 431 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_ITAddrCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_AF I2C_ISR_NACKF

Definition at line 432 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), I2C_IsErrorOccurred(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_ALERT I2C_ISR_ALERT

Definition at line 441 of file stm32g0xx_hal_i2c.h.

#define I2C_FLAG_ARLO I2C_ISR_ARLO

Definition at line 437 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define I2C_FLAG_BERR I2C_ISR_BERR

Definition at line 436 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define I2C_FLAG_BUSY I2C_ISR_BUSY

Definition at line 442 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), and I2C_IsErrorOccurred().

#define I2C_FLAG_DIR I2C_ISR_DIR

Definition at line 443 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_OVR I2C_ISR_OVR

Definition at line 438 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and I2C_IsErrorOccurred().

#define I2C_FLAG_PECERR I2C_ISR_PECERR

Definition at line 439 of file stm32g0xx_hal_i2c.h.

#define I2C_FLAG_RXNE I2C_ISR_RXNE

Definition at line 430 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_STOPF I2C_ISR_STOPF

Definition at line 433 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsErrorOccurred(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TC I2C_ISR_TC

Definition at line 434 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_RequestMemoryRead().

#define I2C_FLAG_TCR I2C_ISR_TCR

Definition at line 435 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 440 of file stm32g0xx_hal_i2c.h.

#define I2C_FLAG_TXE I2C_ISR_TXE

Definition at line 428 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR().

#define I2C_FLAG_TXIS I2C_ISR_TXIS

Definition at line 429 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified I2C interrupt source is enabled or not.
#define | I2C_FLAG_MASK (0x0001FFFFU)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.

Define Documentation

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == I2C_FLAG_TXE) ? \
                                                    ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
                                                    ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the I2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 565 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_Flush_TXDR(), I2C_IsErrorOccurred(), I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 579 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 502 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), and I2C_Master_ISR_DMA().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 573 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 486 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Enable_IRQ().

#define __HAL_I2C_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge I2C peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 585 of file stm32g0xx_hal_i2c.h.

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((((__HANDLE__)->Instance->ISR) & \
                                                    (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Definition at line 545 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_Flush_TXDR(), I2C_IsErrorOccurred(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->CR1 & \
                                                                   (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified I2C interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 518 of file stm32g0xx_hal_i2c.h.

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                             \
                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                                  } while(0)

Reset I2C handle state.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 463 of file stm32g0xx_hal_i2c.h.

#define I2C_FLAG_MASK (0x0001FFFFU)

Check whether the specified I2C flag is set or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_TXIS Transmit interrupt status
  • I2C_FLAG_RXNE Receive data register not empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_TC Transfer complete (master mode)
  • I2C_FLAG_TCR Transfer complete reload
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
  • I2C_FLAG_BUSY Bus busy
  • I2C_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 544 of file stm32g0xx_hal_i2c.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__)
#define | I2C_GET_ADDR_MATCH(__HANDLE__)
#define | I2C_GET_DIR(__HANDLE__)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__)
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | I2C_CHECK_FLAG(__ISR__, __FLAG__)
#define | I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Define Documentation

#define I2C_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) |
Value:
((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
                                                    ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)

Definition at line 810 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_CHECK_IT_SOURCE | ( | __CR1__,
 |  | __IT__
 | ) | ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 812 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Mem_ISR_DMA(), I2C_Mem_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
                                                                 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
                                                                (~I2C_CR2_RD_WRN)) : \
                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
                                                                 (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
                                                                (~I2C_CR2_RD_WRN)))

Definition at line 802 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady().

#define I2C_GET_ADDR_MATCH ( __HANDLE__ )
Value:
((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
                                                              >> 16U))

Definition at line 787 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_DIR ( __HANDLE__ )
Value:
((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
                                                             >> 16U))

Definition at line 789 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), and I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS1 ( __HANDLE__ ) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))

Definition at line 792 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS2 ( __HANDLE__ ) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))

Definition at line 793 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 791 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 800 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ )
Value:
((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
                                                                         (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 798 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RESET_CR2 ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR2 &= \
                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
                                                                          I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
                                                                          I2C_CR2_RD_WRN)))

Definition at line 782 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_IsErrorOccurred(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define IS_I2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 738 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 741 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                         ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 753 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 759 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 756 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 795 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 796 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == I2C_OA2_NOMASK)  || \
                                         ((MASK) == I2C_OA2_MASK01) || \
                                         ((MASK) == I2C_OA2_MASK02) || \
                                         ((MASK) == I2C_OA2_MASK03) || \
                                         ((MASK) == I2C_OA2_MASK04) || \
                                         ((MASK) == I2C_OA2_MASK05) || \
                                         ((MASK) == I2C_OA2_MASK06) || \
                                         ((MASK) == I2C_OA2_MASK07))

Definition at line 744 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)          || \
                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))

Definition at line 771 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Seq_Transmit_IT().

#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_OTHER_FRAME)     || \
                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))

Definition at line 779 of file stm32g0xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), and HAL_I2C_Master_Seq_Transmit_IT().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == I2C_RELOAD_MODE)   || \
                                         ((MODE) == I2C_AUTOEND_MODE) || \
                                         ((MODE) == I2C_SOFTEND_MODE))

Definition at line 762 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_GENERATE_STOP)        || \
                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
                                         ((REQUEST) == I2C_NO_STARTSTOP))

Definition at line 766 of file stm32g0xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C

Modules | Defines
I2C
STM32G0xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Private Define
I2C Private Functions
I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros

Defines

#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)

Detailed Description

I2C HAL module driver.

Define Documentation

#define I2C_GET_DMA_REMAIN_DATA ( __HANDLE__ ) __HAL_DMA_GET_COUNTER(__HANDLE__)

Definition at line 405 of file stm32g0xx_hal_i2c.c.

Referenced by I2C_DMASlaveReceiveCplt(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

Generated on Mon Jun 6 2022 10:29:08 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Filter Mode Functions

Functions
Filter Mode Functions
I2C Extended Exported Functions

Filter Mode Functions. More...

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.

Detailed Description

Filter Mode Functions.

 ===============================================================================
                      ##### Filter Mode Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure I2C Analog noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter | New state of the Analog filter.
Return values:
HAL status

Definition at line 96 of file stm32g0xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure I2C Digital noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 140 of file stm32g0xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and __I2C_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WakeUp Mode Functions

Functions
WakeUp Mode Functions
I2C Extended Exported Functions

WakeUp Mode Functions. More...

Functions

HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).

Detailed Description

WakeUp Mode Functions.

 ===============================================================================
                      ##### WakeUp Mode Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Wake Up Feature

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp ( I2C_HandleTypeDef * hi2c )

Disable I2C wakeup from Stop mode(s).

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 247 of file stm32g0xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp ( I2C_HandleTypeDef * hi2c )

Enable I2C wakeup from Stop mode(s).

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 208 of file stm32g0xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Fast Mode Plus Functions

Functions
Fast Mode Plus Functions
I2C Extended Exported Functions

Fast Mode Plus Functions. More...

Functions

void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Fast Mode Plus Functions.

 ===============================================================================
                      ##### Fast Mode Plus Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Fast Mode Plus

Function Documentation

void HAL_I2CEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be disabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 339 of file stm32g0xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

void HAL_I2CEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be enabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 312 of file stm32g0xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

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STM32G0C1xx HAL User Manual: I2C Extended Analog Filter

Defines
I2C Extended Analog Filter
I2C Extended Exported Constants

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 48 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_ANALOGFILTER_ENABLE 0x00000000U

Definition at line 47 of file stm32g0xx_hal_i2c_ex.h.

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STM32G0C1xx HAL User Manual: I2C Extended Fast Mode Plus

Defines
I2C Extended Fast Mode Plus
I2C Extended Exported Constants

Defines

#define | I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP
#define | I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 63 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 64 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 66 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP

Enable Fast Mode Plus on PA10

Definition at line 58 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP

Enable Fast Mode Plus on PA9

Definition at line 57 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 59 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 60 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 61 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 62 of file stm32g0xx_hal_i2c_ex.h.

#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U

Fast Mode Plus not supported

Definition at line 56 of file stm32g0xx_hal_i2c_ex.h.

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STM32G0C1xx HAL User Manual: I2C Extended Exported Macros

I2C Extended Exported Macros
I2CEx
Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Extended Private Constants

I2C Extended Private Constants
I2CEx
Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Extended Private Macros

Defines
I2C Extended Private Macros
I2CEx

Defines

#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_I2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                         ((FILTER) == I2C_ANALOGFILTER_DISABLE))

Definition at line 137 of file stm32g0xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigAnalogFilter().

#define IS_I2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 140 of file stm32g0xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigDigitalFilter().

#define IS_I2C_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9))  == I2C_FASTMODEPLUS_PA9)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))

Definition at line 142 of file stm32g0xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

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STM32G0C1xx HAL User Manual: I2C Extended Private Functions

I2C Extended Private Functions
I2CEx
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STM32G0C1xx HAL User Manual: I2S Private Functions

Functions
I2S Private Functions
I2S

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
static void | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
This function handles I2S Communication Timeout.

Function Documentation

static void I2S_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1743 of file stm32g0xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::State, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA(), and HAL_I2S_Transmit_DMA().

static void I2S_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1699 of file stm32g0xx_hal_i2s.c.

References DMA_NORMAL, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, __DMA_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S receive process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1725 of file stm32g0xx_hal_i2s.c.

References HAL_I2S_RxHalfCpltCallback(), and __I2S_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_I2S_Receive_DMA().

static void I2S_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1654 of file stm32g0xx_hal_i2s.c.

References DMA_NORMAL, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), __DMA_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2S transmit process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1681 of file stm32g0xx_hal_i2s.c.

References HAL_I2S_TxHalfCpltCallback(), and __I2S_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_I2S_Transmit_DMA().

static void I2S_Receive_IT ( I2S_HandleTypeDef * hi2s ) [static]

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1798 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXNE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxXferCount, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_IRQHandler().

static void I2S_Transmit_IT ( I2S_HandleTypeDef * hi2s ) [static]

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1770 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_IT_ERR, I2S_IT_TXE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_IRQHandler().

static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2S Communication Timeout.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag | Flag checked
State | Value of the flag expected
Timeout | Duration of the timeout
Return values:
HAL status

Definition at line 1829 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and __I2S_HandleTypeDef::State.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive(), and HAL_I2S_Transmit().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Sx peripheral in simplex mode:

      (+) User must Implement HAL_I2S_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2S_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Standard
        (++) Data Format
        (++) MCLK Output
        (++) Audio frequency
        (++) Polarity

     (+) Call the function HAL_I2S_DeInit() to restore the default configuration
          of the selected I2Sx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2S_DeInit ( I2S_HandleTypeDef * hi2s )

DeInitializes the I2S peripheral.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 441 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_DISABLE, assert_param, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_MspDeInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_RESET, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::MspDeInitCallback, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Init ( I2S_HandleTypeDef * hi2s )

Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 264 of file stm32g0xx_hal_i2s.c.

References assert_param, I2S_InitTypeDef::AudioFreq, I2S_InitTypeDef::CPOL, I2S_InitTypeDef::DataFormat, __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_PRESCALER, HAL_I2S_ErrorCallback(), HAL_I2S_MspInit(), HAL_I2S_RxCpltCallback(), HAL_I2S_RxHalfCpltCallback(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TxCpltCallback(), HAL_I2S_TxHalfCpltCallback(), HAL_RCCEx_GetPeriphCLKFreq(), I2S_AUDIOFREQ_DEFAULT, I2S_DATAFORMAT_16B, I2S_MCLKOUTPUT_ENABLE, I2S_STANDARD_LSB, I2S_STANDARD_PCM_LONG, I2S_STANDARD_PCM_SHORT, __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, IS_I2S_AUDIO_FREQ, IS_I2S_CPOL, IS_I2S_DATA_FORMAT, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, __I2S_HandleTypeDef::Lock, I2S_InitTypeDef::MCLKOutput, I2S_InitTypeDef::Mode, __I2S_HandleTypeDef::MspInitCallback, RCC_PERIPHCLK_I2S1, RCC_PERIPHCLK_I2S2, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, I2S_InitTypeDef::Standard, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxHalfCpltCallback.

void HAL_I2S_MspDeInit ( I2S_HandleTypeDef * hi2s )

I2S MSP DeInit.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 501 of file stm32g0xx_hal_i2s.c.

Referenced by HAL_I2S_DeInit(), and HAL_I2S_UnRegisterCallback().

void HAL_I2S_MspInit ( I2S_HandleTypeDef * hi2s )

I2S MSP Init.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 485 of file stm32g0xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), and HAL_I2S_UnRegisterCallback().

HAL_StatusTypeDef HAL_I2S_RegisterCallback | ( | I2S_HandleTypeDef * | hi2s,
 |  | HAL_I2S_CallbackIDTypeDef | CallbackID,
 |  | pI2S_CallbackTypeDef | pCallback
 | ) |  |

Register a User I2S Callback To be used instead of the weak predefined callback.

Parameters:
hi2s | Pointer to a I2S_HandleTypeDef structure that contains the configuration information for the specified I2S.
CallbackID | ID of the callback to be registered
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 521 of file stm32g0xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_CB_ID, HAL_I2S_ERROR_INVALID_CALLBACK, HAL_I2S_MSPDEINIT_CB_ID, HAL_I2S_MSPINIT_CB_ID, HAL_I2S_RX_COMPLETE_CB_ID, HAL_I2S_RX_HALF_COMPLETE_CB_ID, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TX_COMPLETE_CB_ID, HAL_I2S_TX_HALF_COMPLETE_CB_ID, __I2S_HandleTypeDef::MspDeInitCallback, __I2S_HandleTypeDef::MspInitCallback, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_UnRegisterCallback | ( | I2S_HandleTypeDef * | hi2s,
 |  | HAL_I2S_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.

Parameters:
hi2s | Pointer to a I2S_HandleTypeDef structure that contains the configuration information for the specified I2S.
CallbackID | ID of the callback to be unregistered
Return values:
HAL status

Definition at line 620 of file stm32g0xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_CB_ID, HAL_I2S_ERROR_INVALID_CALLBACK, HAL_I2S_ErrorCallback(), HAL_I2S_MspDeInit(), HAL_I2S_MSPDEINIT_CB_ID, HAL_I2S_MspInit(), HAL_I2S_MSPINIT_CB_ID, HAL_I2S_RX_COMPLETE_CB_ID, HAL_I2S_RX_HALF_COMPLETE_CB_ID, HAL_I2S_RxCpltCallback(), HAL_I2S_RxHalfCpltCallback(), HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, HAL_I2S_TX_COMPLETE_CB_ID, HAL_I2S_TX_HALF_COMPLETE_CB_ID, HAL_I2S_TxCpltCallback(), HAL_I2S_TxHalfCpltCallback(), __I2S_HandleTypeDef::MspDeInitCallback, __I2S_HandleTypeDef::MspInitCallback, __I2S_HandleTypeDef::RxCpltCallback, __I2S_HandleTypeDef::RxHalfCpltCallback, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxCpltCallback, and __I2S_HandleTypeDef::TxHalfCpltCallback.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
I2S Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2S_Transmit()
        (++) HAL_I2S_Receive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2S_Transmit_IT()
        (++) HAL_I2S_Receive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2S_Transmit_DMA()
        (++) HAL_I2S_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2S_TxCpltCallback()
        (++) HAL_I2S_RxCpltCallback()
        (++) HAL_I2S_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2S_DMAPause ( I2S_HandleTypeDef * hi2s )

Pauses the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1291 of file stm32g0xx_hal_i2s.c.

References HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAResume ( I2S_HandleTypeDef * hi2s )

Resumes the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1323 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAStop ( I2S_HandleTypeDef * hi2s )

Stops the audio DMA Stream/Channel playing from the Media.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1362 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_CLEAR_UDRFLAG, __HAL_I2S_DISABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_I2S_ERROR_BUSY_LINE_RX, HAL_I2S_ERROR_DMA, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, __I2S_HandleTypeDef::hdmatx, I2S_FLAG_BSY, I2S_FLAG_TXE, I2S_MODE_MASTER_RX, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_RX, I2S_MODE_SLAVE_TX, I2S_TIMEOUT_FLAG, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Init, __I2S_HandleTypeDef::Instance, I2S_InitTypeDef::Mode, and __I2S_HandleTypeDef::State.

void HAL_I2S_ErrorCallback ( I2S_HandleTypeDef * hi2s )

I2S error callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1587 of file stm32g0xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

void HAL_I2S_IRQHandler ( I2S_HandleTypeDef * hi2s )

This function handles I2S interrupt request.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1462 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, __I2S_HandleTypeDef::ErrorCallback, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, I2S_CHECK_FLAG, I2S_CHECK_IT_SOURCE, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_IT_ERR, I2S_IT_RXNE, I2S_IT_TXE, I2S_Receive_IT(), I2S_Transmit_IT(), __I2S_HandleTypeDef::Instance, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
Parameters:
Timeout Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate in continuous way and as the I2S is not disabled at the end of the I2S transaction.
Return values:
HAL status

Definition at line 883 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_MODE_MASTER_RX, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, and __I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Receive data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 1202 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_DMA, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmarx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMARxCplt(), I2S_DMARxHalfCplt(), I2S_MODE_MASTER_RX, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, __I2S_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Receive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Receive data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
It is recommended to use DMA for the I2S receiver to avoid de-synchronization between Master and Slave otherwise the I2S interrupt should be optimized.
Return values:
HAL status

Definition at line 1047 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_RXNE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pRxBuffPtr, __I2S_HandleTypeDef::RxXferCount, __I2S_HandleTypeDef::RxXferSize, and __I2S_HandleTypeDef::State.

void HAL_I2S_RxCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1571 of file stm32g0xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), I2S_DMARxCplt(), and I2S_Receive_IT().

void HAL_I2S_RxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer half completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1555 of file stm32g0xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), and I2S_DMARxHalfCplt().

HAL_StatusTypeDef HAL_I2S_Transmit | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
Parameters:
Timeout Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 764 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_CLEAR_UDRFLAG, __HAL_I2S_ENABLE, __HAL_I2S_GET_FLAG, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_TIMEOUT, HAL_I2S_ERROR_UDR, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_BSY, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_MODE_SLAVE_RX, I2S_MODE_SLAVE_TX, I2S_WaitFlagStateUntilTimeout(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2S_Transmit_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to the Transmit data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 1111 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_DMA, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, __I2S_HandleTypeDef::hdmatx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMATxCplt(), I2S_DMATxHalfCplt(), __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, __I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Transmit_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s | pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData | a 16-bit pointer to data buffer.
Size | number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 24-bit or 32-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 981 of file stm32g0xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, __I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_TXE, __I2S_HandleTypeDef::Instance, __I2S_HandleTypeDef::pTxBuffPtr, __I2S_HandleTypeDef::State, __I2S_HandleTypeDef::TxXferCount, and __I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_TxCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1539 of file stm32g0xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), I2S_DMATxCplt(), and I2S_Transmit_IT().

void HAL_I2S_TxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer Half completed callbacks.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1523 of file stm32g0xx_hal_i2s.c.

Referenced by HAL_I2S_Init(), HAL_I2S_UnRegisterCallback(), and I2S_DMATxHalfCplt().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2S Exported Functions

Peripheral State functions. More...

Functions

HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2S_GetError ( I2S_HandleTypeDef * hi2s )

Return the I2S error code.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Error Code

Definition at line 1633 of file stm32g0xx_hal_i2s.c.

References __I2S_HandleTypeDef::ErrorCode.

HAL_I2S_StateTypeDef HAL_I2S_GetState ( I2S_HandleTypeDef * hi2s )

Return the I2S state.

Parameters:
hi2s pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL state

Definition at line 1622 of file stm32g0xx_hal_i2s.c.

References __I2S_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Exported Types

Data Structures | Typedefs | Enumerations
I2S Exported Types
I2S

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | __I2S_HandleTypeDef
I2S handle Structure definition. More...

Typedefs

typedef struct __I2S_HandleTypeDef | I2S_HandleTypeDef
I2S handle Structure definition.
typedef void(* | pI2S_CallbackTypeDef )(I2S_HandleTypeDef *hi2s)
HAL I2S Callback pointer definition.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x03U,
HAL_I2S_STATE_BUSY_RX = 0x04U, HAL_I2S_STATE_TIMEOUT = 0x06U, HAL_I2S_STATE_ERROR = 0x07U
}
HAL State structures definition. More...
enum HAL_I2S_CallbackIDTypeDef {
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U,
HAL_I2S_ERROR_CB_ID = 0x06U, HAL_I2S_MSPINIT_CB_ID = 0x07U, HAL_I2S_MSPDEINIT_CB_ID = 0x08U
}
HAL I2S Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __I2S_HandleTypeDef I2S_HandleTypeDef

I2S handle Structure definition.

typedef void(* pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s)

HAL I2S Callback pointer definition.

pointer to an I2S callback function

Definition at line 153 of file stm32g0xx_hal_i2s.h.

Enumeration Type Documentation

enum HAL_I2S_CallbackIDTypeDef

HAL I2S Callback ID enumeration definition.

Enumerator:
HAL_I2S_TX_COMPLETE_CB_ID

I2S Tx Completed callback ID

HAL_I2S_RX_COMPLETE_CB_ID

I2S Rx Completed callback ID

HAL_I2S_TX_HALF_COMPLETE_CB_ID

I2S Tx Half Completed callback ID

HAL_I2S_RX_HALF_COMPLETE_CB_ID

I2S Rx Half Completed callback ID

HAL_I2S_ERROR_CB_ID

I2S Error callback ID

HAL_I2S_MSPINIT_CB_ID

I2S Msp Init callback ID

HAL_I2S_MSPDEINIT_CB_ID

I2S Msp DeInit callback ID

Definition at line 138 of file stm32g0xx_hal_i2s.h.

enum HAL_I2S_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_I2S_STATE_RESET

I2S not yet initialized or disabled

HAL_I2S_STATE_READY

I2S initialized and ready for use

HAL_I2S_STATE_BUSY

I2S internal process is ongoing

HAL_I2S_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2S_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2S_STATE_TIMEOUT

I2S timeout state

HAL_I2S_STATE_ERROR

I2S error state

Definition at line 71 of file stm32g0xx_hal_i2s.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_InitTypeDef Struct Reference
I2S Exported Types

I2S Init structure definition. More...

#include <stm32g0xx_hal_i2s.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | CPOL

Detailed Description

I2S Init structure definition.

Definition at line 47 of file stm32g0xx_hal_i2s.h.

Field Documentation

uint32_t I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S Audio Frequency

Definition at line 61 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of I2S Clock Polarity

Definition at line 64 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of I2S Data Format

Definition at line 55 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S MCLK Output

Definition at line 58 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of I2S Mode

Definition at line 49 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S Standard

Definition at line 52 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_i2s.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __I2S_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2S_HandleTypeDef Struct Reference
I2S Exported Types

I2S handle Structure definition. More...

#include <stm32g0xx_hal_i2s.h>

Data Fields

SPI_TypeDef * | Instance
I2S_InitTypeDef Init
uint16_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint16_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
__IO HAL_LockTypeDef | Lock
__IO HAL_I2S_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | RxCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | TxHalfCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | RxHalfCpltCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | ErrorCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | MspInitCallback )(struct __I2S_HandleTypeDef *hi2s)
void(* | MspDeInitCallback )(struct __I2S_HandleTypeDef *hi2s)

Detailed Description

I2S handle Structure definition.

Definition at line 86 of file stm32g0xx_hal_i2s.h.

Field Documentation

void(* __I2S_HandleTypeDef::ErrorCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Error callback

Definition at line 127 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

__IO uint32_t __I2S_HandleTypeDef::ErrorCode

I2S Error code This parameter can be a value of I2S Error

Definition at line 119 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAStop(), HAL_I2S_GetError(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_RegisterCallback(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2S_UnRegisterCallback(), and I2S_DMAError().

DMA_HandleTypeDef* __I2S_HandleTypeDef::hdmarx

I2S Rx DMA handle parameters

Definition at line 113 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Receive_DMA().

DMA_HandleTypeDef* __I2S_HandleTypeDef::hdmatx

I2S Tx DMA handle parameters

Definition at line 111 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit_DMA().

I2S_InitTypeDef __I2S_HandleTypeDef::Init

I2S communication parameters

Definition at line 93 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Init().

SPI_TypeDef* __I2S_HandleTypeDef::Instance

I2S registers base address

Definition at line 91 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), and I2S_Transmit_IT().

__IO HAL_LockTypeDef __I2S_HandleTypeDef::Lock

I2S locking object

Definition at line 115 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

void(* __I2S_HandleTypeDef::MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Msp DeInit callback

Definition at line 129 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

void(* __I2S_HandleTypeDef::MspInitCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Msp Init callback

Definition at line 128 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

uint16_t* __I2S_HandleTypeDef::pRxBuffPtr

Pointer to I2S Rx transfer buffer

Definition at line 101 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

uint16_t* __I2S_HandleTypeDef::pTxBuffPtr

Pointer to I2S Tx transfer buffer

Definition at line 95 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

void(* __I2S_HandleTypeDef::RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Rx Completed callback

Definition at line 124 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), I2S_DMARxCplt(), and I2S_Receive_IT().

void(* __I2S_HandleTypeDef::RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Rx Half Completed callback

Definition at line 126 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMARxHalfCplt().

__IO uint16_t __I2S_HandleTypeDef::RxXferCount

I2S Rx transfer counter (This field is initialized at the same value as transfer size at the beginning of the transfer and decremented when a sample is received NbSamplesReceived = RxBufferSize-RxBufferCount)

Definition at line 105 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), I2S_DMAError(), I2S_DMARxCplt(), and I2S_Receive_IT().

__IO uint16_t __I2S_HandleTypeDef::RxXferSize

I2S Rx transfer size

Definition at line 103 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and HAL_I2S_Receive_IT().

__IO HAL_I2S_StateTypeDef __I2S_HandleTypeDef::State

I2S communication state

Definition at line 117 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_GetState(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_RegisterCallback(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), HAL_I2S_UnRegisterCallback(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), I2S_Transmit_IT(), and I2S_WaitFlagStateUntilTimeout().

void(* __I2S_HandleTypeDef::TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Tx Completed callback

Definition at line 123 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), I2S_DMATxCplt(), and I2S_Transmit_IT().

void(* __I2S_HandleTypeDef::TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s)

I2S Tx Half Completed callback

Definition at line 125 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), HAL_I2S_RegisterCallback(), HAL_I2S_UnRegisterCallback(), and I2S_DMATxHalfCplt().

__IO uint16_t __I2S_HandleTypeDef::TxXferCount

I2S Tx transfer Counter

Definition at line 99 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMATxCplt(), and I2S_Transmit_IT().

__IO uint16_t __I2S_HandleTypeDef::TxXferSize

I2S Tx transfer size

Definition at line 97 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_i2s.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Error

Defines
I2S Error
I2S Exported Constants

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000U)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000001U)
#define | HAL_I2S_ERROR_OVR (0x00000002U)
#define | HAL_I2S_ERROR_UDR (0x00000004U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_PRESCALER (0x00000010U)
#define | HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U)
#define | HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U)

Define Documentation

#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U)

Busy Rx Line error

Definition at line 176 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop().

#define HAL_I2S_ERROR_DMA (0x00000008U)

DMA transfer error

Definition at line 171 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), and I2S_DMAError().

#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U)

Invalid Callback error

Definition at line 174 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_RegisterCallback(), and HAL_I2S_UnRegisterCallback().

#define HAL_I2S_ERROR_NONE (0x00000000U)

No error

Definition at line 167 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define HAL_I2S_ERROR_OVR (0x00000002U)

OVR error

Definition at line 169 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define HAL_I2S_ERROR_PRESCALER (0x00000010U)

Prescaler Calculation error

Definition at line 172 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define HAL_I2S_ERROR_TIMEOUT (0x00000001U)

Timeout error

Definition at line 168 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive(), and HAL_I2S_Transmit().

#define HAL_I2S_ERROR_UDR (0x00000004U)

UDR error

Definition at line 170 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Mode

Defines
I2S Mode
I2S Exported Constants

Defines

#define | I2S_MODE_SLAVE_TX (0x00000000U)
#define | I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))

Define Documentation

#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))

Definition at line 187 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)

Definition at line 186 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop().

#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)

Definition at line 185 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit().

#define I2S_MODE_SLAVE_TX (0x00000000U)

Definition at line 184 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Standard

Defines
I2S Standard
I2S Exported Constants

Defines

#define | I2S_STANDARD_PHILIPS (0x00000000U)
#define | I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
#define | I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))

Define Documentation

#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)

Definition at line 197 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)

Definition at line 196 of file stm32g0xx_hal_i2s.h.

#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))

Definition at line 199 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))

Definition at line 198 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_PHILIPS (0x00000000U)

Definition at line 195 of file stm32g0xx_hal_i2s.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Data Format

Defines
I2S Data Format
I2S Exported Constants

Defines

#define | I2S_DATAFORMAT_16B (0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define | I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))

Define Documentation

#define I2S_DATAFORMAT_16B (0x00000000U)

Definition at line 207 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)

Definition at line 208 of file stm32g0xx_hal_i2s.h.

#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))

Definition at line 209 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))

Definition at line 210 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S MCLK Output

Defines
I2S MCLK Output
I2S Exported Constants

Defines

#define | I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000U)

Define Documentation

#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)

Definition at line 219 of file stm32g0xx_hal_i2s.h.

#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Definition at line 218 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Audio Frequency

Defines
I2S Audio Frequency
I2S Exported Constants

Defines

#define | I2S_AUDIOFREQ_192K (192000U)
#define | I2S_AUDIOFREQ_96K (96000U)
#define | I2S_AUDIOFREQ_48K (48000U)
#define | I2S_AUDIOFREQ_44K (44100U)
#define | I2S_AUDIOFREQ_32K (32000U)
#define | I2S_AUDIOFREQ_22K (22050U)
#define | I2S_AUDIOFREQ_16K (16000U)
#define | I2S_AUDIOFREQ_11K (11025U)
#define | I2S_AUDIOFREQ_8K (8000U)
#define | I2S_AUDIOFREQ_DEFAULT (2U)

Define Documentation

#define I2S_AUDIOFREQ_11K (11025U)

Definition at line 234 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_16K (16000U)

Definition at line 233 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_192K (192000U)

Definition at line 227 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_22K (22050U)

Definition at line 232 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_32K (32000U)

Definition at line 231 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_44K (44100U)

Definition at line 230 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_48K (48000U)

Definition at line 229 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_8K (8000U)

Definition at line 235 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_96K (96000U)

Definition at line 228 of file stm32g0xx_hal_i2s.h.

#define I2S_AUDIOFREQ_DEFAULT (2U)

Definition at line 236 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Clock Polarity

Defines
I2S Clock Polarity
I2S Exported Constants

Defines

#define | I2S_CPOL_LOW (0x00000000U)
#define | I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)

Define Documentation

#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)

Definition at line 245 of file stm32g0xx_hal_i2s.h.

#define I2S_CPOL_LOW (0x00000000U)

Definition at line 244 of file stm32g0xx_hal_i2s.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Interrupts Definition

Defines
I2S Interrupts Definition
I2S Exported Constants

Defines

#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define I2S_IT_ERR SPI_CR2_ERRIE

Definition at line 255 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define I2S_IT_RXNE SPI_CR2_RXNEIE

Definition at line 254 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

#define I2S_IT_TXE SPI_CR2_TXEIE

Definition at line 253 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Flags Definition

Defines
I2S Flags Definition
I2S Exported Constants

Defines

#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY
#define | I2S_FLAG_MASK

Define Documentation

#define I2S_FLAG_BSY SPI_SR_BSY

Definition at line 271 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit().

#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE

Definition at line 270 of file stm32g0xx_hal_i2s.h.

#define I2S_FLAG_FRE SPI_SR_FRE

Definition at line 268 of file stm32g0xx_hal_i2s.h.

#define I2S_FLAG_MASK
Value:
(SPI_SR_RXNE\
                                         | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)

Definition at line 273 of file stm32g0xx_hal_i2s.h.

#define I2S_FLAG_OVR SPI_SR_OVR

Definition at line 267 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_RXNE SPI_SR_RXNE

Definition at line 264 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_TXE SPI_SR_TXE

Definition at line 263 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define I2S_FLAG_UDR SPI_SR_UDR

Definition at line 266 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Exported Macros

Defines
I2S Exported Macros
I2S

Defines

#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
Enable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
Disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
Enable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
Disable the specified I2S interrupts.
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.
#define | __HAL_I2S_FLUSH_RX_DR(__HANDLE__)
Flush the I2S DR Register.

Define Documentation

#define __HAL_I2S_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{ \
                                                __IO uint32_t tmpreg_ovr = 0x00U; \
                                                tmpreg_ovr = (__HANDLE__)->Instance->DR; \
                                                tmpreg_ovr = (__HANDLE__)->Instance->SR; \
                                                UNUSED(tmpreg_ovr); \
                                              }while(0U)

Clears the I2S OVR pending flag.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 368 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), HAL_I2S_Receive(), and HAL_I2S_Receive_DMA().

#define __HAL_I2S_CLEAR_UDRFLAG ( __HANDLE__ )
Value:
do{\
                                                __IO uint32_t tmpreg_udr = 0x00U;\
                                                tmpreg_udr = ((__HANDLE__)->Instance->SR);\
                                                UNUSED(tmpreg_udr); \
                                              }while(0U)

Clears the I2S UDR pending flag.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 378 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit().

#define __HAL_I2S_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))

Disable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 312 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), and HAL_I2S_DMAStop().

#define __HAL_I2S_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))

Disable the specified I2S interrupts.

Parameters:
__HANDLE__ specifies the I2S Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 334 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define __HAL_I2S_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))

Enable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 306 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_DMAResume(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))

Enable the specified I2S interrupts.

Parameters:
__HANDLE__ specifies the I2S Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 323 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_FLUSH_RX_DR ( __HANDLE__ )
Value:
do{\
                                                __IO uint32_t tmpreg_dr = 0x00U;\
                                                tmpreg_dr = ((__HANDLE__)->Instance->DR);\
                                                UNUSED(tmpreg_dr); \
                                              }while(0U)

Flush the I2S DR Register.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 387 of file stm32g0xx_hal_i2s.h.

#define __HAL_I2S_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified I2S flag is set or not.

Parameters:
__HANDLE__ specifies the I2S Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXNE: Receive buffer not empty flag
  • I2S_FLAG_TXE: Transmit buffer empty flag
  • I2S_FLAG_UDR: Underrun flag
  • I2S_FLAG_OVR: Overrun flag
  • I2S_FLAG_FRE: Frame error flag
  • I2S_FLAG_CHSIDE: Channel Side flag
  • I2S_FLAG_BSY: Busy flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 362 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Transmit(), and I2S_WaitFlagStateUntilTimeout().

#define __HAL_I2S_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->CR2\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2S interrupt source is enabled or disabled.

Parameters:
__HANDLE__ specifies the I2S Handle. This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
__INTERRUPT__ specifies the I2S interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 346 of file stm32g0xx_hal_i2s.h.

#define __HAL_I2S_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset I2S handle state.

Parameters:
__HANDLE__ specifies the I2S Handle.
Return values:
None

Definition at line 293 of file stm32g0xx_hal_i2s.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | I2S_CHECK_FLAG(__SR__, __FLAG__)
Check whether the specified SPI flag is set or not.
#define | I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)
Check whether the specified SPI Interrupt is set or not.
#define | IS_I2S_MODE(__MODE__)
Checks if I2S Mode parameter is in allowed range.
#define | IS_I2S_STANDARD(__STANDARD__)
#define | IS_I2S_DATA_FORMAT(__FORMAT__)
#define | IS_I2S_MCLK_OUTPUT(__OUTPUT__)
#define | IS_I2S_AUDIO_FREQ(__FREQ__)
#define | IS_I2S_CPOL(__CPOL__)
Checks if I2S Serial clock steady state parameter is in allowed range.

Define Documentation

#define I2S_CHECK_FLAG | ( | __SR__,
 |  | __FLAG__
 | ) |
Value:
((((__SR__)\
                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)

Check whether the specified SPI flag is set or not.

Parameters:
__SR__ copy of I2S SR register.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXNE: Receive buffer not empty flag
  • I2S_FLAG_TXE: Transmit buffer empty flag
  • I2S_FLAG_UDR: Underrun error flag
  • I2S_FLAG_OVR: Overrun flag
  • I2S_FLAG_CHSIDE: Channel side flag
  • I2S_FLAG_BSY: Busy flag
Return values:
SET or RESET.

Definition at line 485 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define I2S_CHECK_IT_SOURCE | ( | __CR2__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__CR2__)\
                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI Interrupt is set or not.

Parameters:
__CR2__ copy of I2S CR2 register.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
SET or RESET.

Definition at line 497 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define IS_I2S_AUDIO_FREQ ( __FREQ__ )
Value:
((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))

Definition at line 524 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_CPOL ( __CPOL__ )
Value:
(((__CPOL__) == I2S_CPOL_LOW) || \
                               ((__CPOL__) == I2S_CPOL_HIGH))

Checks if I2S Serial clock steady state parameter is in allowed range.

Parameters:
__CPOL__ specifies the I2S serial clock steady state. This parameter can be a value of I2S Clock Polarity
Return values:
None

Definition at line 533 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_DATA_FORMAT ( __FORMAT__ )
Value:
(((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
                                        ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
                                        ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
                                        ((__FORMAT__) == I2S_DATAFORMAT_32B))

Definition at line 516 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MCLK_OUTPUT ( __OUTPUT__ )
Value:
(((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
                                        ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))

Definition at line 521 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MODE ( __MODE__ )
Value:
(((__MODE__) == I2S_MODE_SLAVE_TX)  || \
                               ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
                               ((__MODE__) == I2S_MODE_MASTER_TX) || \
                               ((__MODE__) == I2S_MODE_MASTER_RX))

Checks if I2S Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the I2S Mode. This parameter can be a value of I2S Mode
Return values:
None

Definition at line 505 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_STANDARD ( __STANDARD__ )
Value:
(((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
                                       ((__STANDARD__) == I2S_STANDARD_MSB)       || \
                                       ((__STANDARD__) == I2S_STANDARD_LSB)       || \
                                       ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
                                       ((__STANDARD__) == I2S_STANDARD_PCM_LONG))

Definition at line 510 of file stm32g0xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S

Modules | Defines
I2S
STM32G0xx_HAL_Driver

I2S HAL module driver. More...

Modules

I2S Private Functions
I2S Exported Functions
I2S Exported Types
I2S Exported Constants
I2S Exported Macros
I2S Private Macros

Defines

#define I2S_TIMEOUT_FLAG 100U

Detailed Description

I2S HAL module driver.

Define Documentation

#define I2S_TIMEOUT_FLAG 100U

Timeout 100 ms

Definition at line 203 of file stm32g0xx_hal_i2s.c.

Referenced by HAL_I2S_DMAStop().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000U
#define | IRDA_CR1_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Define Documentation

#define IRDA_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE \
                                     | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))

UART or USART CR1 fields of parameters set by IRDA_SetConfig API

Definition at line 209 of file stm32g0xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IRDA_TEACK_REACK_TIMEOUT 1000U

IRDA TX or RX enable acknowledge time-out value

Definition at line 207 of file stm32g0xx_hal_irda.c.

Referenced by IRDA_CheckIdleState().

#define USART_BRR_MAX 0x0000FFFFU

USART BRR maximum authorized value

Definition at line 214 of file stm32g0xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define USART_BRR_MIN 0x10U

USART BRR minimum authorized value

Definition at line 212 of file stm32g0xx_hal_irda.c.

Referenced by IRDA_SetConfig().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__)
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that IRDA clock Prescaler is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Define Documentation

#define IRDA_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __PRESCALER__
 | ) |
Value:
((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
                                                                  + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | IRDA clock source.
__BAUD__ | Baud rate set by the user.
__PRESCALER__ | IRDA clock prescaler value.
Return values:
Division result

Definition at line 229 of file stm32g0xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IS_IRDA_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 115201U)

Ensure that IRDA Baud rate is less or equal to maximum value.

Parameters:
__BAUDRATE__ specifies the IRDA Baudrate set by the user.
Return values:
True or False

Definition at line 702 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_CLOCKPRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))

Ensure that IRDA clock Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ IRDA clock Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 736 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))

Ensure that IRDA DMA RX mode is valid.

Parameters:
__DMARX__ IRDA DMA RX mode.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 781 of file stm32g0xx_hal_irda.h.

#define IS_IRDA_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

Ensure that IRDA DMA TX mode is valid.

Parameters:
__DMATX__ IRDA DMA TX mode.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 774 of file stm32g0xx_hal_irda.h.

#define IS_IRDA_MODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_MODE_DISABLE) || \
                                 ((__MODE__) == IRDA_MODE_ENABLE))

Ensure that IRDA associated UART/USART mode is valid.

Parameters:
__MODE__ IRDA associated UART/USART mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 760 of file stm32g0xx_hal_irda.h.

#define IS_IRDA_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

Ensure that IRDA sampling rate is valid.

Parameters:
__ONEBIT__ IRDA sampling rate.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 767 of file stm32g0xx_hal_irda.h.

#define IS_IRDA_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == IRDA_PARITY_NONE) || \
                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
                                    ((__PARITY__) == IRDA_PARITY_ODD))

Ensure that IRDA frame parity is valid.

Parameters:
__PARITY__ IRDA frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 714 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

Ensure that IRDA power mode is valid.

Parameters:
__MODE__ IRDA power mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 729 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PRESCALER ( __PRESCALER__ ) ((__PRESCALER__) > 0U)

Ensure that IRDA prescaler value is strictly larger than 0.

Parameters:
__PRESCALER__ specifies the IRDA prescaler value set by the user.
Return values:
True or False

Definition at line 708 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))

Ensure that IRDA request is valid.

Parameters:
__PARAM__ IRDA request.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 788 of file stm32g0xx_hal_irda.h.

#define IS_IRDA_STATE ( __STATE__ )
Value:
(((__STATE__) == IRDA_STATE_DISABLE) || \
                                  ((__STATE__) == IRDA_STATE_ENABLE))

Ensure that IRDA state is valid.

Parameters:
__STATE__ IRDA state mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 753 of file stm32g0xx_hal_irda.h.

#define IS_IRDA_TX_RX_MODE ( __MODE__ )
Value:
((((__MODE__)\
                                        & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that IRDA communication mode is valid.

Parameters:
__MODE__ IRDA communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 722 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IRDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  in asynchronous IRDA mode.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Parity: If the parity is enabled, then the MSB bit of the data written
           in the data register is transmitted but is changed by the parity bit.
      (++) Power mode
      (++) Prescaler setting
      (++) Receiver/transmitter modes

  [..]
  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
  (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible IRDA frame formats are listed in the following table.

Table 1. IRDA frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | IRDA frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 393 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::MspDeInitCallback, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 328 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, __IRDA_HandleTypeDef::gState, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, __IRDA_HandleTypeDef::Instance, IRDA_CheckIdleState(), IRDA_InitCallbacksToDefault(), IRDA_SetConfig(), __IRDA_HandleTypeDef::Lock, and __IRDA_HandleTypeDef::MspInitCallback.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 452 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_UnRegisterCallback().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 436 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_Init(), and HAL_IRDA_UnRegisterCallback().

HAL_StatusTypeDef HAL_IRDA_RegisterCallback | ( | IRDA_HandleTypeDef * | hirda,
 |  | HAL_IRDA_CallbackIDTypeDef | CallbackID,
 |  | pIRDA_CallbackTypeDef | pCallback
 | ) |  |

Register a User IRDA Callback To be used instead of the weak predefined callback.

Parameters:
hirda | irda handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_IRDA_ERROR_CB_ID Error Callback ID
  • HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
  • HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 482 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ABORT_COMPLETE_CB_ID, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_IRDA_ERROR_CB_ID, HAL_IRDA_ERROR_INVALID_CALLBACK, HAL_IRDA_MSPDEINIT_CB_ID, HAL_IRDA_MSPINIT_CB_ID, HAL_IRDA_RX_COMPLETE_CB_ID, HAL_IRDA_RX_HALFCOMPLETE_CB_ID, HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, HAL_IRDA_TX_COMPLETE_CB_ID, HAL_IRDA_TX_HALFCOMPLETE_CB_ID, __IRDA_HandleTypeDef::MspDeInitCallback, __IRDA_HandleTypeDef::MspInitCallback, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback | ( | IRDA_HandleTypeDef * | hirda,
 |  | HAL_IRDA_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.

Parameters:
hirda irda handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_IRDA_ERROR_CB_ID Error Callback ID
  • HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
  • HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 604 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ABORT_COMPLETE_CB_ID, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ERROR_CB_ID, HAL_IRDA_ERROR_INVALID_CALLBACK, HAL_IRDA_ErrorCallback(), HAL_IRDA_MspDeInit(), HAL_IRDA_MSPDEINIT_CB_ID, HAL_IRDA_MspInit(), HAL_IRDA_MSPINIT_CB_ID, HAL_IRDA_RX_COMPLETE_CB_ID, HAL_IRDA_RX_HALFCOMPLETE_CB_ID, HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, HAL_IRDA_TX_COMPLETE_CB_ID, HAL_IRDA_TX_HALFCOMPLETE_CB_ID, HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), __IRDA_HandleTypeDef::MspDeInitCallback, __IRDA_HandleTypeDef::MspInitCallback, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
IRDA Exported Functions

IRDA Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.

Detailed Description

IRDA Transmit and Receive functions.

 ===============================================================================
                         ##### IO operation functions #####
 ===============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the IRDA data transfers.

  [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

  [..]
    (#) There are two modes of transfer:
        (++) Blocking mode: the communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: the communication is performed using Interrupts
             or DMA, these API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()
        (++) HAL_IRDA_DMAPause()
        (++) HAL_IRDA_DMAResume()
        (++) HAL_IRDA_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
        (++) HAL_IRDA_TxHalfCpltCallback()
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxHalfCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_IRDA_Abort()
        (++) HAL_IRDA_AbortTransmit()
        (++) HAL_IRDA_AbortReceive()
        (++) HAL_IRDA_Abort_IT()
        (++) HAL_IRDA_AbortTransmit_IT()
        (++) HAL_IRDA_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (++) HAL_IRDA_AbortCpltCallback()
        (++) HAL_IRDA_AbortTransmitCpltCallback()
        (++) HAL_IRDA_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
             in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
             to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
             Transfer is kept ongoing on IRDA side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type, and
             HAL_IRDA_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_IRDA_Abort ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1502 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Abort_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1699 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2226 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_AbortReceive ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1641 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1910 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, HAL_DMA_Abort_IT(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxOnlyAbortCallback(), __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortReceiveCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Receive Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2258 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_AbortReceive_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_AbortTransmit ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1589 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1832 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_DMATxOnlyAbortCallback(), __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortTransmitCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2242 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pause the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1349 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resume the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1387 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_InitTypeDef::Parity, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stop the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1425 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), and __IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2210 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAAbortOnError(), IRDA_DMAError(), and IRDA_InitCallbacksToDefault().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

Handle IRDA interrupt request.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1986 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMAAbortOnError(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Specify timeout value.
Return values:
HAL status
Note:
When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.

Definition at line 916 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, __IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
When the IRDA parity is enabled (PCE = 1), the received data contains the parity bit (MSB position).
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status
Note:
When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.

Definition at line 1259 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferSize, IRDA_InitTypeDef::WordLength, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status
Note:
When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.

Definition at line 1085 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2178 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveCplt(), IRDA_InitCallbacksToDefault(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2194 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveHalfCplt(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Specify timeout value.
Return values:
HAL status
Note:
When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.

Definition at line 810 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status
Note:
When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.

Definition at line 1162 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_TCF, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, IRDA_InitTypeDef::WordLength, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status
Note:
When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.

Definition at line 1023 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2146 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_InitCallbacksToDefault().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 2162 of file stm32g0xx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitHalfCplt(), and IRDA_InitCallbacksToDefault().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
IRDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
         of the IRDA peripheral handle.
     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( const IRDA_HandleTypeDef * hirda )

Return the IRDA handle error code.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
IRDA Error Code

Definition at line 2314 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( const IRDA_HandleTypeDef * hirda )

Return the IRDA handle state.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 2297 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, and __IRDA_HandleTypeDef::RxState.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDA Private Functions

Functions
IRDA Private Functions
IRDA

Functions

void | IRDA_InitCallbacksToDefault (IRDA_HandleTypeDef *hirda)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static void | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static void | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.

Function Documentation

static HAL_StatusTypeDef IRDA_CheckIdleState ( IRDA_HandleTypeDef * hirda ) [static]

Check the IRDA Idle State.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2438 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, IRDA_TEACK_REACK_TIMEOUT, IRDA_WaitOnFlagUntilTimeout(), and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Init().

static void IRDA_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2708 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCallback, HAL_IRDA_ErrorCallback(), __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2668 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2613 of file stm32g0xx_hal_irda.c.

References HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxState, and __IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2649 of file stm32g0xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2779 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2854 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, and __IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_AbortReceive_IT().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2558 of file stm32g0xx_hal_irda.c.

References HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2594 of file stm32g0xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2731 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2827 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_AbortTransmit_IT().

static void IRDA_EndRxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2541 of file stm32g0xx_hal_irda.c.

References HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), and IRDA_DMAError().

static void IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2923 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::TxCpltCallback.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_EndTxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2525 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, and __IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_DMAStop(), and IRDA_DMAError().

void IRDA_InitCallbacksToDefault ( IRDA_HandleTypeDef * hirda )

Initialize the callbacks to their default values.

Parameters:
hirda IRDA handle.
Return values:
none

Definition at line 2337 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ErrorCallback(), HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_IRDA_Init().

static void IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receive an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Receive_IT()
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2948 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_SEND_REQ, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_RXDATA_FLUSH_REQUEST, IRDA_WORDLENGTH_9B, __IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configure the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2358 of file stm32g0xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, IRDA_InitTypeDef::ClockPrescaler, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_CLOCKSOURCE_HSI, IRDA_CLOCKSOURCE_LSE, IRDA_CLOCKSOURCE_PCLK1, IRDA_CLOCKSOURCE_SYSCLK, IRDA_CR1_FIELDS, IRDA_DIV_SAMPLING16, IRDA_GETCLOCKSOURCE, IS_IRDA_BAUDRATE, IS_IRDA_CLOCKPRESCALER, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_PRESCALER, IS_IRDA_TX_RX_MODE, IS_IRDA_WORD_LENGTH, LSE_VALUE, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, IRDA_InitTypeDef::PowerMode, IRDA_InitTypeDef::Prescaler, USART_BRR_MAX, USART_BRR_MIN, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static void IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Transmit_IT().
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2884 of file stm32g0xx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle IRDA Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag | Specifies the IRDA flag to check.
Status | The actual Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2490 of file stm32g0xx_hal_irda.c.

References __HAL_IRDA_GET_FLAG, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), and IRDA_CheckIdleState().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDA Exported Types

Data Structures | Typedefs | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | __IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_IRDA_StateTypeDef
HAL IRDA State definition.
typedef struct __IRDA_HandleTypeDef | IRDA_HandleTypeDef
IRDA handle Structure definition.
typedef void(* | pIRDA_CallbackTypeDef )(IRDA_HandleTypeDef *hirda)
HAL IRDA Callback pointer definition.

Enumerations

enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_SYSCLK = 0x04U, IRDA_CLOCKSOURCE_LSE = 0x10U,
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U
}
IRDA clock sources definition. More...
enum HAL_IRDA_CallbackIDTypeDef {
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U,
HAL_IRDA_ERROR_CB_ID = 0x04U, HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_IRDA_MSPINIT_CB_ID = 0x08U, HAL_IRDA_MSPDEINIT_CB_ID = 0x09U
}
HAL IRDA Callback ID enumeration definition. More...

Typedef Documentation

typedef uint32_t HAL_IRDA_StateTypeDef

HAL IRDA State definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState (see IRDA State Code Definition).
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 118 of file stm32g0xx_hal_irda.h.

typedef struct __IRDA_HandleTypeDef IRDA_HandleTypeDef

IRDA handle Structure definition.

typedef void(* pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda)

HAL IRDA Callback pointer definition.

pointer to an IRDA callback function

Definition at line 222 of file stm32g0xx_hal_irda.h.

Enumeration Type Documentation

enum HAL_IRDA_CallbackIDTypeDef

HAL IRDA Callback ID enumeration definition.

Enumerator:
HAL_IRDA_TX_HALFCOMPLETE_CB_ID

IRDA Tx Half Complete Callback ID

HAL_IRDA_TX_COMPLETE_CB_ID

IRDA Tx Complete Callback ID

HAL_IRDA_RX_HALFCOMPLETE_CB_ID

IRDA Rx Half Complete Callback ID

HAL_IRDA_RX_COMPLETE_CB_ID

IRDA Rx Complete Callback ID

HAL_IRDA_ERROR_CB_ID

IRDA Error Callback ID

HAL_IRDA_ABORT_COMPLETE_CB_ID

IRDA Abort Complete Callback ID

HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID

IRDA Abort Transmit Complete Callback ID

HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID

IRDA Abort Receive Complete Callback ID

HAL_IRDA_MSPINIT_CB_ID

IRDA MspInit callback ID

HAL_IRDA_MSPDEINIT_CB_ID

IRDA MspDeInit callback ID

Definition at line 203 of file stm32g0xx_hal_irda.h.

enum IRDA_ClockSourceTypeDef

IRDA clock sources definition.

Enumerator:
IRDA_CLOCKSOURCE_PCLK1

PCLK1 clock source

IRDA_CLOCKSOURCE_HSI

HSI clock source

IRDA_CLOCKSOURCE_SYSCLK

SYSCLK clock source

IRDA_CLOCKSOURCE_LSE

LSE clock source

IRDA_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 123 of file stm32g0xx_hal_irda.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32g0xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint16_t | PowerMode
uint32_t | ClockPrescaler

Detailed Description

IRDA Init Structure definition.

Definition at line 46 of file stm32g0xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate))) where usart_ker_ckpres is the IRDA input clock divided by a prescaler

Definition at line 48 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the IRDA clock source. This parameter can be a value of IRDA Clock Prescaler.

Definition at line 73 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 63 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 56 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint16_t IRDA_InitTypeDef::PowerMode

Specifies the IRDA power mode. This parameter can be a value of IRDA Low Power

Definition at line 70 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency.

Note:
Prescaler value 0 is forbidden

Definition at line 66 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDAEx Word Length

Definition at line 53 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_irda.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32g0xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
const uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | TxCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | RxHalfCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | RxCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | ErrorCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortTransmitCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortReceiveCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | MspInitCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | MspDeInitCallback )(struct __IRDA_HandleTypeDef *hirda)

Detailed Description

IRDA handle Structure definition.

Definition at line 136 of file stm32g0xx_hal_irda.h.

Field Documentation

void(* __IRDA_HandleTypeDef::AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Complete Callback

Definition at line 185 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Receive Complete Callback

Definition at line 189 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_AbortReceive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Transmit Complete Callback

Definition at line 187 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::ErrorCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Error Callback

Definition at line 183 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAAbortOnError(), IRDA_DMAError(), and IRDA_InitCallbacksToDefault().

__IO uint32_t __IRDA_HandleTypeDef::ErrorCode

IRDA Error code

Definition at line 172 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DeInit(), HAL_IRDA_DMAStop(), HAL_IRDA_GetError(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

__IO HAL_IRDA_StateTypeDef __IRDA_HandleTypeDef::gState

IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 165 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __IRDA_HandleTypeDef::hdmarx

IRDA Rx DMA Handle parameters

Definition at line 161 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

DMA_HandleTypeDef* __IRDA_HandleTypeDef::hdmatx

IRDA Tx DMA Handle parameters

Definition at line 159 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

IRDA_InitTypeDef __IRDA_HandleTypeDef::Init

IRDA communication parameters

Definition at line 143 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* __IRDA_HandleTypeDef::Instance

USART registers base address

Definition at line 141 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), IRDA_SetConfig(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

HAL_LockTypeDef __IRDA_HandleTypeDef::Lock

Locking object

Definition at line 163 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint16_t __IRDA_HandleTypeDef::Mask

USART RX RDR register mask

Definition at line 157 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Msp DeInit callback

Definition at line 194 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

void(* __IRDA_HandleTypeDef::MspInitCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Msp Init callback

Definition at line 192 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

uint8_t* __IRDA_HandleTypeDef::pRxBuffPtr

Pointer to IRDA Rx transfer Buffer

Definition at line 151 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

const uint8_t* __IRDA_HandleTypeDef::pTxBuffPtr

Pointer to IRDA Tx transfer Buffer

Definition at line 145 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

void(* __IRDA_HandleTypeDef::RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Rx Complete Callback

Definition at line 181 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveCplt(), IRDA_InitCallbacksToDefault(), and IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Rx Half Complete Callback

Definition at line 179 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveHalfCplt(), and IRDA_InitCallbacksToDefault().

__IO HAL_IRDA_StateTypeDef __IRDA_HandleTypeDef::RxState

IRDA state information related to Rx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 169 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_EndRxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

__IO uint16_t __IRDA_HandleTypeDef::RxXferCount

IRDA Rx Transfer Counter

Definition at line 155 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_Receive_IT().

uint16_t __IRDA_HandleTypeDef::RxXferSize

IRDA Rx Transfer size

Definition at line 153 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Tx Complete Callback

Definition at line 177 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Tx Half Complete Callback

Definition at line 175 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitHalfCplt(), and IRDA_InitCallbacksToDefault().

__IO uint16_t __IRDA_HandleTypeDef::TxXferCount

IRDA Tx Transfer Counter

Definition at line 149 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_Transmit_IT().

uint16_t __IRDA_HandleTypeDef::TxXferSize

IRDA Tx Transfer size

Definition at line 147 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_irda.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDA State Code Definition

Defines
IRDA State Code Definition
IRDA Exported Constants

Defines

#define | HAL_IRDA_STATE_RESET 0x00000000U
#define | HAL_IRDA_STATE_READY 0x00000020U
#define | HAL_IRDA_STATE_BUSY 0x00000024U
#define | HAL_IRDA_STATE_BUSY_TX 0x00000021U
#define | HAL_IRDA_STATE_BUSY_RX 0x00000022U
#define | HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_IRDA_STATE_TIMEOUT 0x000000A0U
#define | HAL_IRDA_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_IRDA_STATE_BUSY 0x00000024U

An internal process is ongoing Value is allowed for gState only

Definition at line 242 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define HAL_IRDA_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 246 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), and IRDA_Receive_IT().

#define HAL_IRDA_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 244 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), and IRDA_Transmit_IT().

#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 248 of file stm32g0xx_hal_irda.h.

#define HAL_IRDA_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 254 of file stm32g0xx_hal_irda.h.

#define HAL_IRDA_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 240 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define HAL_IRDA_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 238 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 252 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA Error Code Definition

Defines
IRDA Error Code Definition
IRDA Exported Constants

Defines

#define | HAL_IRDA_ERROR_NONE (0x00000000U)
#define | HAL_IRDA_ERROR_PE (0x00000001U)
#define | HAL_IRDA_ERROR_NE (0x00000002U)
#define | HAL_IRDA_ERROR_FE (0x00000004U)
#define | HAL_IRDA_ERROR_ORE (0x00000008U)
#define | HAL_IRDA_ERROR_DMA (0x00000010U)
#define | HAL_IRDA_ERROR_BUSY (0x00000020U)
#define | HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U)

Define Documentation

#define HAL_IRDA_ERROR_BUSY (0x00000020U)

Busy Error

Definition at line 269 of file stm32g0xx_hal_irda.h.

#define HAL_IRDA_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 268 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), and IRDA_DMAError().

#define HAL_IRDA_ERROR_FE (0x00000004U)

frame error

Definition at line 266 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U)

Invalid Callback error

Definition at line 271 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

#define HAL_IRDA_ERROR_NE (0x00000002U)

Noise error

Definition at line 265 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NONE (0x00000000U)

No error

Definition at line 263 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

#define HAL_IRDA_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 267 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_PE (0x00000001U)

Parity error

Definition at line 264 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

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STM32G0C1xx HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported Constants

Defines

#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN USART_CR1_PCE
#define | IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define IRDA_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 281 of file stm32g0xx_hal_irda.h.

#define IRDA_PARITY_NONE 0x00000000U

No parity

Definition at line 280 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 282 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_RX USART_CR1_RE
#define | IRDA_MODE_TX USART_CR1_TE
#define | IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define IRDA_MODE_RX USART_CR1_RE

RX mode

Definition at line 290 of file stm32g0xx_hal_irda.h.

#define IRDA_MODE_TX USART_CR1_TE

TX mode

Definition at line 291 of file stm32g0xx_hal_irda.h.

#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 292 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported Constants

Defines

#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP

Define Documentation

#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP

IRDA low power mode

Definition at line 301 of file stm32g0xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL 0x00000000U

IRDA normal power mode

Definition at line 300 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA Clock Prescaler

Defines
IRDA Clock Prescaler
IRDA Exported Constants

Defines

#define | IRDA_PRESCALER_DIV1 0x00000000U
#define | IRDA_PRESCALER_DIV2 0x00000001U
#define | IRDA_PRESCALER_DIV4 0x00000002U
#define | IRDA_PRESCALER_DIV6 0x00000003U
#define | IRDA_PRESCALER_DIV8 0x00000004U
#define | IRDA_PRESCALER_DIV10 0x00000005U
#define | IRDA_PRESCALER_DIV12 0x00000006U
#define | IRDA_PRESCALER_DIV16 0x00000007U
#define | IRDA_PRESCALER_DIV32 0x00000008U
#define | IRDA_PRESCALER_DIV64 0x00000009U
#define | IRDA_PRESCALER_DIV128 0x0000000AU
#define | IRDA_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define IRDA_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 309 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 314 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 315 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 319 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 316 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 310 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 320 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 317 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 311 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 312 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 318 of file stm32g0xx_hal_irda.h.

#define IRDA_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 313 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA State

Defines
IRDA State
IRDA Exported Constants

Defines

#define | IRDA_STATE_DISABLE 0x00000000U
#define | IRDA_STATE_ENABLE USART_CR1_UE

Define Documentation

#define IRDA_STATE_DISABLE 0x00000000U

IRDA disabled

Definition at line 328 of file stm32g0xx_hal_irda.h.

#define IRDA_STATE_ENABLE USART_CR1_UE

IRDA enabled

Definition at line 329 of file stm32g0xx_hal_irda.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDA Mode

Defines
IRDA Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_DISABLE 0x00000000U
#define | IRDA_MODE_ENABLE USART_CR3_IREN

Define Documentation

#define IRDA_MODE_DISABLE 0x00000000U

Associated UART disabled in IRDA mode

Definition at line 337 of file stm32g0xx_hal_irda.h.

#define IRDA_MODE_ENABLE USART_CR3_IREN

Associated UART enabled in IRDA mode

Definition at line 338 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA One Bit Sampling

Defines
IRDA One Bit Sampling
IRDA Exported Constants

Defines

#define | IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U

One-bit sampling disabled

Definition at line 346 of file stm32g0xx_hal_irda.h.

#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

One-bit sampling enabled

Definition at line 347 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA DMA Tx

Defines
IRDA DMA Tx
IRDA Exported Constants

Defines

#define | IRDA_DMA_TX_DISABLE 0x00000000U
#define | IRDA_DMA_TX_ENABLE USART_CR3_DMAT

Define Documentation

#define IRDA_DMA_TX_DISABLE 0x00000000U

IRDA DMA TX disabled

Definition at line 355 of file stm32g0xx_hal_irda.h.

#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT

IRDA DMA TX enabled

Definition at line 356 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA DMA Rx

Defines
IRDA DMA Rx
IRDA Exported Constants

Defines

#define | IRDA_DMA_RX_DISABLE 0x00000000U
#define | IRDA_DMA_RX_ENABLE USART_CR3_DMAR

Define Documentation

#define IRDA_DMA_RX_DISABLE 0x00000000U

IRDA DMA RX disabled

Definition at line 364 of file stm32g0xx_hal_irda.h.

#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR

IRDA DMA RX enabled

Definition at line 365 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA Request Parameters

Defines
IRDA Request Parameters
IRDA Exported Constants

Defines

#define | IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ

Auto-Baud Rate Request

Definition at line 373 of file stm32g0xx_hal_irda.h.

#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 374 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 375 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_REACK USART_ISR_REACK
#define | IRDA_FLAG_TEACK USART_ISR_TEACK
#define | IRDA_FLAG_BUSY USART_ISR_BUSY
#define | IRDA_FLAG_ABRF USART_ISR_ABRF
#define | IRDA_FLAG_ABRE USART_ISR_ABRE
#define | IRDA_FLAG_TXE USART_ISR_TXE_TXFNF
#define | IRDA_FLAG_TC USART_ISR_TC
#define | IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | IRDA_FLAG_ORE USART_ISR_ORE
#define | IRDA_FLAG_NE USART_ISR_NE
#define | IRDA_FLAG_FE USART_ISR_FE
#define | IRDA_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define IRDA_FLAG_ABRE USART_ISR_ABRE

IRDA auto Baud rate error

Definition at line 389 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_ABRF USART_ISR_ABRF

IRDA auto Baud rate flag

Definition at line 388 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_BUSY USART_ISR_BUSY

IRDA busy flag

Definition at line 387 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_FE USART_ISR_FE

IRDA frame error

Definition at line 395 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_NE USART_ISR_NE

IRDA noise error

Definition at line 394 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_ORE USART_ISR_ORE

IRDA overrun error

Definition at line 393 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_PE USART_ISR_PE

IRDA parity error

Definition at line 396 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_REACK USART_ISR_REACK

IRDA receive enable acknowledge flag

Definition at line 385 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE

IRDA read data register not empty

Definition at line 392 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Receive().

#define IRDA_FLAG_TC USART_ISR_TC

IRDA transmission complete

Definition at line 391 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

#define IRDA_FLAG_TEACK USART_ISR_TEACK

IRDA transmit enable acknowledge flag

Definition at line 386 of file stm32g0xx_hal_irda.h.

#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF

IRDA transmit data register empty

Definition at line 390 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

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STM32G0C1xx HAL User Manual: IRDA Interrupts Definition

Defines
IRDA Interrupts Definition
IRDA Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | IRDA_IT_PE 0x0028U
#define | IRDA_IT_TXE 0x0727U
#define | IRDA_IT_TC 0x0626U
#define | IRDA_IT_RXNE 0x0525U
#define | IRDA_IT_IDLE 0x0424U
#define | IRDA_IT_ERR 0x0060U
#define | IRDA_IT_ORE 0x0300U
#define | IRDA_IT_NE 0x0200U
#define | IRDA_IT_FE 0x0100U

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define IRDA_IT_ERR 0x0060U

IRDA Error interruption

Definition at line 423 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_FE 0x0100U

IRDA Frame error interruption

Definition at line 429 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_IDLE 0x0424U

IRDA Idle interruption

Definition at line 415 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_NE 0x0200U

IRDA Noise error interruption

Definition at line 428 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_ORE 0x0300U

IRDA Overrun error interruption

Definition at line 427 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_PE 0x0028U

IRDA Parity error interruption

Definition at line 411 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_RXNE 0x0525U

IRDA Read data register not empty interruption

Definition at line 414 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_TC 0x0626U

IRDA Transmission complete interruption

Definition at line 413 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_TXE 0x0727U

IRDA Transmit data register empty interruption

Definition at line 412 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA Interruption Clear Flags

Defines
IRDA Interruption Clear Flags
IRDA Exported Constants

Defines

#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NECF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define IRDA_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 438 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 441 of file stm32g0xx_hal_irda.h.

#define IRDA_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 439 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 440 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 437 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 442 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

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STM32G0C1xx HAL User Manual: IRDA interruptions flags mask

Defines
IRDA interruptions flags mask
IRDA Exported Constants

Defines

#define | IRDA_IT_MASK 0x001FU
#define | IRDA_CR_MASK 0x00E0U
#define | IRDA_CR_POS 5U
#define | IRDA_ISR_MASK 0x1F00U
#define | IRDA_ISR_POS 8U

Define Documentation

#define IRDA_CR_MASK 0x00E0U

IRDA control register mask

Definition at line 451 of file stm32g0xx_hal_irda.h.

#define IRDA_CR_POS 5U

IRDA control register position

Definition at line 452 of file stm32g0xx_hal_irda.h.

#define IRDA_ISR_MASK 0x1F00U

IRDA ISR register mask

Definition at line 453 of file stm32g0xx_hal_irda.h.

#define IRDA_ISR_POS 8U

IRDA ISR register position

Definition at line 454 of file stm32g0xx_hal_irda.h.

#define IRDA_IT_MASK 0x001FU

IRDA Interruptions flags mask

Definition at line 450 of file stm32g0xx_hal_irda.h.

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STM32G0C1xx HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 521 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified IRDA pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_CLEAR_PEF
  • IRDA_CLEAR_FEF
  • IRDA_CLEAR_NEF
  • IRDA_CLEAR_OREF
  • IRDA_CLEAR_TCF
  • IRDA_CLEAR_IDLEF
Return values:
None

Definition at line 508 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 539 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • IRDA_CLEAR_PEF Parity Error Clear Flag
  • IRDA_CLEAR_FEF Framing Error Clear Flag
  • IRDA_CLEAR_NEF Noise detected Clear Flag
  • IRDA_CLEAR_OREF OverRun Error Clear Flag
  • IRDA_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 650 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 527 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 533 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 514 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 687 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 595 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 681 of file stm32g0xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
                                                           ((__HANDLE__)->Instance->CR1 |= (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))):\
                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
                                                           ((__HANDLE__)->Instance->CR2 |= (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))):\
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << \
                                                               ((__INTERRUPT__) & IRDA_IT_MASK))))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 574 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                    \
    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
  } while(0U)

Flush the IRDA DR register.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 490 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_REACK Receive enable acknowledge flag
  • IRDA_FLAG_TEACK Transmit enable acknowledge flag
  • IRDA_FLAG_BUSY Busy flag
  • IRDA_FLAG_ABRF Auto Baud rate detection flag
  • IRDA_FLAG_ABRE Auto Baud rate detection error flag
  • IRDA_FLAG_TXE Transmit data register empty flag
  • IRDA_FLAG_TC Transmission Complete flag
  • IRDA_FLAG_RXNE Receive data register not empty flag
  • IRDA_FLAG_ORE OverRun Error flag
  • IRDA_FLAG_NE Noise Error flag
  • IRDA_FLAG_FE Framing Error flag
  • IRDA_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 559 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ORE OverRun Error interrupt
  • IRDA_IT_NE Noise Error interrupt
  • IRDA_IT_FE Framing Error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 618 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__)  \
      & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3))           \
     & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)

Check whether the specified IRDA interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ERR Framing, overrun or noise error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 633 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR3\
                                                       &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 674 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 668 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0U)

Reset IRDA handle state.

Parameters:
__HANDLE__ IRDA handle.
Return values:
None

Definition at line 473 of file stm32g0xx_hal_irda.h.

#define __HAL_IRDA_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific IRDA request flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 662 of file stm32g0xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDAEx Word Length

Defines
IRDAEx Word Length
IRDAEx Extended Exported Constants

Defines

#define | IRDA_WORDLENGTH_7B USART_CR1_M1
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define IRDA_WORDLENGTH_7B USART_CR1_M1

7-bit long frame

Definition at line 48 of file stm32g0xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_8B 0x00000000U

8-bit long frame

Definition at line 49 of file stm32g0xx_hal_irda_ex.h.

#define IRDA_WORDLENGTH_9B USART_CR1_M0

9-bit long frame

Definition at line 50 of file stm32g0xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRDAEx Private Macros

Defines
IRDAEx Private Macros
IRDAEx

Defines

#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.

Define Documentation

#define IRDA_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the IRDA clock source.

Parameters:
__HANDLE__ | specifies the IRDA Handle.
__CLOCKSOURCE__ | output variable.
Return values:
IRDA clocking source, written in __CLOCKSOURCE__.

Definition at line 73 of file stm32g0xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

#define IRDA_MASK_COMPUTATION ( __HANDLE__ )

Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None,the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 229 of file stm32g0xx_hal_irda_ex.h.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Receive_IT().

#define IS_IRDA_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))

Ensure that IRDA frame length is valid.

Parameters:
__LENGTH__ IRDA frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 274 of file stm32g0xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define | IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))

Definition at line 129 of file stm32g0xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)

Definition at line 130 of file stm32g0xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32g0xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload
uint32_t | Window

Detailed Description

IWDG Init structure definition.

Definition at line 46 of file stm32g0xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 48 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 51 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Window

Specifies the window value to be compared to the down-counter. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 54 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_iwdg.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32g0xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * Instance
IWDG_InitTypeDef Init

Detailed Description

IWDG Handle Structure definition.

Definition at line 62 of file stm32g0xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 66 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 64 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_iwdg.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

IWDG prescaler set to 128

Definition at line 87 of file stm32g0xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 IWDG_PR_PR_1

IWDG prescaler set to 16

Definition at line 84 of file stm32g0xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

IWDG prescaler set to 256

Definition at line 88 of file stm32g0xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

IWDG prescaler set to 32

Definition at line 85 of file stm32g0xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 0x00000000u

IWDG prescaler set to 4

Definition at line 82 of file stm32g0xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 IWDG_PR_PR_2

IWDG prescaler set to 64

Definition at line 86 of file stm32g0xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 IWDG_PR_PR_0

IWDG prescaler set to 8

Definition at line 83 of file stm32g0xx_hal_iwdg.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG Window option

Defines
IWDG Window option
IWDG Exported Constants

Defines

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Define Documentation

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Definition at line 96 of file stm32g0xx_hal_iwdg.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

Define Documentation

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 123 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Refresh().

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enable the IWDG peripheral.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 115 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and Start functions

Functions
Initialization and Start functions
IWDG Exported Functions

Initialization and Start functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Detailed Description

Initialization and Start functions.

 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Manage Window option.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Before exiting function, watchdog is refreshed in order to have correct time base.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 170 of file stm32g0xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IS_IWDG_WINDOW, IWDG_ENABLE_WRITE_ACCESS, IWDG_KERNEL_UPDATE_FLAGS, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, and IWDG_InitTypeDef::Window.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refresh the IWDG.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 257 of file stm32g0xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

Define Documentation

#define IWDG_KEY_ENABLE 0x0000CCCCu

IWDG Peripheral Enable

Definition at line 165 of file stm32g0xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD 0x0000AAAAu

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 164 of file stm32g0xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

IWDG KR Write Access Disable

Definition at line 167 of file stm32g0xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u

IWDG KR Write Access Enable

Definition at line 166 of file stm32g0xx_hal_iwdg.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__ IWDG prescaler value
Return values:
None

Definition at line 197 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= IWDG_RLR_RL)

Check IWDG reload value.

Parameters:
__RELOAD__ IWDG reload value
Return values:
None

Definition at line 210 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= IWDG_WINR_WIN)

Check IWDG window value.

Parameters:
__WINDOW__ IWDG window value
Return values:
None

Definition at line 217 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 190 of file stm32g0xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 183 of file stm32g0xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
LPTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the LPTIM according to the specified parameters in the
          LPTIM_InitTypeDef and initialize the associated handle.
      (+) DeInitialize the LPTIM peripheral.
      (+) Initialize the LPTIM MSP.
      (+) DeInitialize the LPTIM MSP.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 381 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_GetState(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::MspDeInitCallback, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 241 of file stm32g0xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, __LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, __LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ResetCallback(), LPTIM_TRIGSOURCE_SOFTWARE, __LPTIM_HandleTypeDef::MspInitCallback, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 443 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit(), and HAL_LPTIM_UnRegisterCallback().

void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 428 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init(), and HAL_LPTIM_UnRegisterCallback().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Start-Stop operation functions

Functions
LPTIM Start-Stop operation functions
LPTIM Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.

Detailed Description

Start-Stop operation functions.

  ==============================================================================
                ##### LPTIM Start Stop operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the PWM mode.
      (+) Stop the PWM mode.
      (+) Start the One pulse mode.
      (+) Stop the One pulse mode.
      (+) Start the Set once mode.
      (+) Stop the Set once mode.
      (+) Start the Encoder mode.
      (+) Stop the Encoder mode.
      (+) Start the Timeout mode.
      (+) Stop the Timeout mode.
      (+) Start the Counter mode.
      (+) Stop the Counter mode.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Return values:
HAL status

Definition at line 1576 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Return values:
HAL status

Definition at line 1655 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1625 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1724 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Return values:
HAL status

Definition at line 1160 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1252 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1219 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1329 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 715 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 802 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 770 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 887 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 492 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 579 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 547 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 664 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 939 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1026 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 994 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1111 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1372 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0001 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1464 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_CMPM, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1427 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1536 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and __LPTIM_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Read operation functions

Functions
LPTIM Read operation functions
LPTIM Exported Functions

Read operation functions. More...

Functions

uint32_t | HAL_LPTIM_ReadCounter (const LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (const LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (const LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.

Detailed Description

Read operation functions.

  ==============================================================================
                  ##### LPTIM Read operation functions #####
  ==============================================================================
[..]  This section provides LPTIM Reading functions.
      (+) Read the counter value.
      (+) Read the period (Auto-reload) value.
      (+) Read the pulse (Compare)value.

Function Documentation

uint32_t HAL_LPTIM_ReadAutoReload ( const LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim LPTIM handle
Return values:
Autoreload value.

Definition at line 1793 of file stm32g0xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( const LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim LPTIM handle
Return values:
Compare value.

Definition at line 1806 of file stm32g0xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( const LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim LPTIM handle
Return values:
Counter value.

Definition at line 1780 of file stm32g0xx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM IRQ handler and callbacks

Functions
LPTIM IRQ handler and callbacks
LPTIM Exported Functions

LPTIM IRQ handler. More...

Functions

void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Detailed Description

LPTIM IRQ handler.

LPTIM IRQ handler and callback functions.

  ==============================================================================
                      ##### LPTIM IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides LPTIM IRQ handler and callback functions called within
      the IRQ handler:
   (+) LPTIM interrupt request handler
   (+) Compare match Callback
   (+) Auto-reload match Callback
   (+) External trigger event detection Callback
   (+) Compare register write complete Callback
   (+) Auto-reload register write complete Callback
   (+) Up-counting direction change Callback
   (+) Down-counting direction change Callback

Function Documentation

void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1987 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2032 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1972 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2017 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2062 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2047 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1845 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_LPTIM_RegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID,
 |  | pLPTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User LPTIM callback to be used instead of the weak predefined callback.

Parameters:
hlptim | LPTIM handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 2090 of file stm32g0xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2002 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Parameters:
hlptim LPTIM handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
Return values:
status

Definition at line 2197 of file stm32g0xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MspInit(), HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, HAL_LPTIM_TriggerCallback(), __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
LPTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Return the LPTIM handle state.

Parameters:
hlptim LPTIM handle
Return values:
HAL state

Definition at line 2316 of file stm32g0xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::State.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Private Functions

Functions
LPTIM Private Functions
LPTIM | LPTIM

Functions

void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.
static void | LPTIM_ResetCallback (LPTIM_HandleTypeDef *lptim)
Reset interrupt callbacks to the legacy weak callbacks.
static HAL_StatusTypeDef | LPTIM_WaitForFlag (LPTIM_HandleTypeDef *hlptim, uint32_t flag)
LPTimer Wait for flag set.

Function Documentation

void LPTIM_Disable ( LPTIM_HandleTypeDef * hlptim )

Disable LPTIM HW instance.

Parameters:
hlptim pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 2388 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM1_FORCE_RESET, __HAL_RCC_LPTIM1_RELEASE_RESET, __HAL_RCC_LPTIM2_CONFIG, __HAL_RCC_LPTIM2_FORCE_RESET, __HAL_RCC_LPTIM2_RELEASE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), RCC_LPTIM1CLKSOURCE_PCLK1, RCC_LPTIM2CLKSOURCE_PCLK1, and __LPTIM_HandleTypeDef::State.

static void LPTIM_ResetCallback ( LPTIM_HandleTypeDef * lptim ) [static]

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
lptim pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
Return values:
None

Definition at line 2343 of file stm32g0xx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), and __LPTIM_HandleTypeDef::TriggerCallback.

Referenced by HAL_LPTIM_Init().

static HAL_StatusTypeDef LPTIM_WaitForFlag | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | flag
 | ) |  | [static]

LPTimer Wait for flag set.

Parameters:
hlptim | pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
flag | The lptim flag
Return values:
HAL status

Definition at line 2363 of file stm32g0xx_hal_lptim.c.

References __HAL_LPTIM_GET_FLAG, and TIMEOUT.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Exported Types

Data Structures | Defines | Typedefs | Enumerations
LPTIM Exported Types
LPTIM

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | __LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29
#define | LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30

Typedefs

typedef struct
__LPTIM_HandleTypeDef 		LPTIM_HandleTypeDef
LPTIM handle Structure definition.
typedef void(* | pLPTIM_CallbackTypeDef )(LPTIM_HandleTypeDef *hlptim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...
enum HAL_LPTIM_CallbackIDTypeDef {
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U,
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U
}
HAL LPTIM Callback ID enumeration definition. More...

Define Documentation

#define LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29

External interrupt line 29 Connected to the LPTIM1 EXTI Line

Definition at line 44 of file stm32g0xx_hal_lptim.h.

#define LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30

External interrupt line 30 Connected to the LPTIM2 EXTI Line

Definition at line 45 of file stm32g0xx_hal_lptim.h.

Typedef Documentation

typedef struct __LPTIM_HandleTypeDef LPTIM_HandleTypeDef

LPTIM handle Structure definition.

typedef void(* pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim)

HAL TIM Callback pointer definition.

pointer to the LPTIM callback function

Definition at line 190 of file stm32g0xx_hal_lptim.h.

Enumeration Type Documentation

enum HAL_LPTIM_CallbackIDTypeDef

HAL LPTIM Callback ID enumeration definition.

Enumerator:
HAL_LPTIM_MSPINIT_CB_ID

LPTIM Base Msp Init Callback ID

HAL_LPTIM_MSPDEINIT_CB_ID

LPTIM Base Msp DeInit Callback ID

HAL_LPTIM_COMPARE_MATCH_CB_ID

Compare match Callback ID

HAL_LPTIM_AUTORELOAD_MATCH_CB_ID

Auto-reload match Callback ID

HAL_LPTIM_TRIGGER_CB_ID

External trigger event detection Callback ID

HAL_LPTIM_COMPARE_WRITE_CB_ID

Compare register write complete Callback ID

HAL_LPTIM_AUTORELOAD_WRITE_CB_ID

Auto-reload register write complete Callback ID

HAL_LPTIM_DIRECTION_UP_CB_ID

Up-counting direction change Callback ID

HAL_LPTIM_DIRECTION_DOWN_CB_ID

Down-counting direction change Callback ID

Definition at line 174 of file stm32g0xx_hal_lptim.h.

enum HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumerator:
HAL_LPTIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_LPTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_LPTIM_STATE_BUSY

An internal process is ongoing

HAL_LPTIM_STATE_TIMEOUT

Timeout state

HAL_LPTIM_STATE_ERROR

Internal Process is ongoing

Definition at line 129 of file stm32g0xx_hal_lptim.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32g0xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | Prescaler

Detailed Description

LPTIM Clock configuration definition.

Definition at line 50 of file stm32g0xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ClockConfigTypeDef::Prescaler

Specifies the counter clock Prescaler. This parameter can be a value of LPTIM Clock Prescaler

Definition at line 55 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ClockConfigTypeDef::Source

Selects the clock source. This parameter can be a value of LPTIM Clock Source

Definition at line 52 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_lptim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM_ULPClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ULPClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32g0xx_hal_lptim.h>

Data Fields

uint32_t | Polarity
uint32_t | SampleTime

Detailed Description

LPTIM Clock configuration definition.

Definition at line 63 of file stm32g0xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ULPClockConfigTypeDef::Polarity

Selects the polarity of the active edge for the counter unit if the ULPTIM input is selected. Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. This parameter can be a value of LPTIM Clock Polarity

Definition at line 65 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ULPClockConfigTypeDef::SampleTime

Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of LPTIM Clock Sample Time

Definition at line 72 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_lptim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM_TriggerConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_TriggerConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Trigger configuration definition. More...

#include <stm32g0xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | ActiveEdge
uint32_t | SampleTime

Detailed Description

LPTIM Trigger configuration definition.

Definition at line 81 of file stm32g0xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_TriggerConfigTypeDef::ActiveEdge

Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM External Trigger Polarity

Definition at line 86 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::SampleTime

Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM Trigger Sample Time

Definition at line 90 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::Source

Selects the Trigger source. This parameter can be a value of LPTIM Trigger Source

Definition at line 83 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_lptim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_InitTypeDef Struct Reference
LPTIM Exported Types

LPTIM Initialization Structure definition. More...

#include <stm32g0xx_hal_lptim.h>

Data Fields

LPTIM_ClockConfigTypeDef Clock
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock
LPTIM_TriggerConfigTypeDef Trigger
uint32_t | OutputPolarity
uint32_t | UpdateMode
uint32_t | CounterSource
uint32_t | Input1Source
uint32_t | Input2Source

Detailed Description

LPTIM Initialization Structure definition.

Definition at line 98 of file stm32g0xx_hal_lptim.h.

Field Documentation

LPTIM_ClockConfigTypeDef LPTIM_InitTypeDef::Clock

Specifies the clock parameters

Definition at line 100 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::CounterSource

Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of LPTIM Counter Source

Definition at line 113 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input1Source

Specifies source selected for input1 (GPIO or comparator output). This parameter can be a value of LPTIM Input1 Source

Definition at line 117 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input2Source

Specifies source selected for input2 (GPIO or comparator output). Note: This parameter is used only for encoder feature so is used only for LPTIM1 instance. This parameter can be a value of LPTIM Input2 Source

Definition at line 120 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::OutputPolarity

Specifies the Output polarity. This parameter can be a value of LPTIM Output Polarity

Definition at line 106 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

LPTIM_TriggerConfigTypeDef LPTIM_InitTypeDef::Trigger

Specifies the Trigger parameters

Definition at line 104 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_ULPClockConfigTypeDef LPTIM_InitTypeDef::UltraLowPowerClock

Specifies the Ultra Low Power clock parameters

Definition at line 102 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::UpdateMode

Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. This parameter can be a value of LPTIM Updating Mode

Definition at line 109 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_lptim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __LPTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__LPTIM_HandleTypeDef Struct Reference
LPTIM Exported Types

LPTIM handle Structure definition. More...

#include <stm32g0xx_hal_lptim.h>

Data Fields

LPTIM_TypeDef * | Instance
LPTIM_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_LPTIM_StateTypeDef | State
void(* | MspInitCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | MspDeInitCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | CompareMatchCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | AutoReloadMatchCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | TriggerCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | CompareWriteCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | AutoReloadWriteCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | DirectionUpCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | DirectionDownCallback )(struct __LPTIM_HandleTypeDef *hlptim)

Detailed Description

LPTIM handle Structure definition.

Definition at line 142 of file stm32g0xx_hal_lptim.h.

Field Documentation

void(* __LPTIM_HandleTypeDef::AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Auto-reload match Callback

Definition at line 161 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Auto-reload register write complete Callback

Definition at line 164 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Compare match Callback

Definition at line 160 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Compare register write complete Callback

Definition at line 163 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Down-counting direction change Callback

Definition at line 166 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Up-counting direction change Callback

Definition at line 165 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

LPTIM_InitTypeDef __LPTIM_HandleTypeDef::Init

LPTIM required parameters

Definition at line 149 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_TypeDef* __LPTIM_HandleTypeDef::Instance

Register base address

Definition at line 147 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), and LPTIM_Disable().

HAL_LockTypeDef __LPTIM_HandleTypeDef::Lock

LPTIM locking object

Definition at line 153 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

void(* __LPTIM_HandleTypeDef::MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim)

LPTIM Base Msp DeInit Callback

Definition at line 159 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_DeInit(), HAL_LPTIM_RegisterCallback(), and HAL_LPTIM_UnRegisterCallback().

void(* __LPTIM_HandleTypeDef::MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim)

LPTIM Base Msp Init Callback

Definition at line 158 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_RegisterCallback(), and HAL_LPTIM_UnRegisterCallback().

__IO HAL_LPTIM_StateTypeDef __LPTIM_HandleTypeDef::State

LPTIM peripheral state

Definition at line 155 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_GetState(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_Disable().

HAL_StatusTypeDef __LPTIM_HandleTypeDef::Status

LPTIM peripheral status

Definition at line 151 of file stm32g0xx_hal_lptim.h.

void(* __LPTIM_HandleTypeDef::TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim)

External trigger event detection Callback

Definition at line 162 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_lptim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Clock Source

Defines
LPTIM Clock Source
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Define Documentation

#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U

Definition at line 205 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Definition at line 206 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Clock Prescaler

Defines
LPTIM Clock Prescaler
LPTIM Exported Constants

Defines

#define | LPTIM_PRESCALER_DIV1 0x00000000U
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LPTIM_PRESCALER_DIV1 0x00000000U

Definition at line 214 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Definition at line 221 of file stm32g0xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Definition at line 218 of file stm32g0xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Definition at line 215 of file stm32g0xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)

Definition at line 219 of file stm32g0xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Definition at line 216 of file stm32g0xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)

Definition at line 220 of file stm32g0xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)

Definition at line 217 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Output Polarity

Defines
LPTIM Output Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define | LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL

Define Documentation

#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U

Definition at line 230 of file stm32g0xx_hal_lptim.h.

#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL

Definition at line 231 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Clock Sample Time

Defines
LPTIM Clock Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Define Documentation

#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0

Definition at line 240 of file stm32g0xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1

Definition at line 241 of file stm32g0xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Definition at line 242 of file stm32g0xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U

Definition at line 239 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Clock Polarity

Defines
LPTIM Clock Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0

Definition at line 251 of file stm32g0xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U

Definition at line 250 of file stm32g0xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Definition at line 252 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Trigger Source

Defines
LPTIM Trigger Source
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define | LPTIM_TRIGSOURCE_0 0x00000000U
#define | LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Define Documentation

#define LPTIM_TRIGSOURCE_0 0x00000000U

Definition at line 261 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0

Definition at line 262 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1

Definition at line 263 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

Definition at line 264 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2

Definition at line 265 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 266 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 267 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Definition at line 268 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU

Definition at line 260 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

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STM32G0C1xx HAL User Manual: LPTIM External Trigger Polarity

Defines
LPTIM External Trigger Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1

Definition at line 277 of file stm32g0xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0

Definition at line 276 of file stm32g0xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Definition at line 278 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Trigger Sample Time

Defines
LPTIM Trigger Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Define Documentation

#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0

Definition at line 287 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1

Definition at line 288 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Definition at line 289 of file stm32g0xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U

Definition at line 286 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Updating Mode

Defines
LPTIM Updating Mode
LPTIM Exported Constants

Defines

#define | LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Definition at line 299 of file stm32g0xx_hal_lptim.h.

#define LPTIM_UPDATE_IMMEDIATE 0x00000000U

Definition at line 298 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Counter Source

Defines
LPTIM Counter Source
LPTIM Exported Constants

Defines

#define | LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Definition at line 309 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U

Definition at line 308 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Input1 Source

Defines
LPTIM Input1 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1SEL_1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)

Define Documentation

#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0

For LPTIM1 and LPTIM2

Definition at line 319 of file stm32g0xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)

For LPTIM2

Definition at line 321 of file stm32g0xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1SEL_1

For LPTIM2

Definition at line 320 of file stm32g0xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U

For LPTIM1 and LPTIM2

Definition at line 318 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Input2 Source

Defines
LPTIM Input2 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0

Define Documentation

#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0

For LPTIM1

Definition at line 331 of file stm32g0xx_hal_lptim.h.

#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U

For LPTIM1

Definition at line 330 of file stm32g0xx_hal_lptim.h.

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STM32G0C1xx HAL User Manual: LPTIM Flags Definition

Defines
LPTIM Flags Definition
LPTIM Exported Constants

Defines

#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Define Documentation

#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM

Definition at line 345 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK

Definition at line 342 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Definition at line 346 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK

Definition at line 343 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN

Definition at line 340 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG

Definition at line 344 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_UP LPTIM_ISR_UP

Definition at line 341 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

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STM32G0C1xx HAL User Manual: LPTIM Interrupts Definition

Defines
LPTIM Interrupts Definition
LPTIM Exported Constants

Defines

#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Define Documentation

#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE

Definition at line 359 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

Definition at line 356 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Definition at line 360 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE

Definition at line 357 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE

Definition at line 354 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE

Definition at line 358 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_UP LPTIM_IER_UPIE

Definition at line 355 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

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STM32G0C1xx HAL User Manual: LPTIM Exported Macros

Defines
LPTIM Exported Macros
LPTIM

Defines

#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified LPTIM interrupt source is enabled or not.
#define | __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
Enable the LPTIM1 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()
Disable the LPTIM1 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)
Enable the LPTIM1 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT()
Disable the LPTIM1 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
Enable the LPTIM2 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()
Disable the LPTIM2 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)
Enable the LPTIM2 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT()
Disable the LPTIM2 EXTI line in event mode.

Define Documentation

#define __HAL_LPTIM_AUTORELOAD_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->ARR = (__VALUE__))

Write the passed parameter in the Autoreload register.

Parameters:
__HANDLE__ | LPTIM handle
__VALUE__ | Autoreload value
Return values:
None
Note:
The ARR register can only be modified when the LPTIM instance is enabled.

Definition at line 441 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified LPTIM flag.

Parameters:
__HANDLE__ LPTIM handle.
__FLAG__ LPTIM flag to clear. This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
None.

Definition at line 482 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define __HAL_LPTIM_COMPARE_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->CMP = (__VALUE__))

Write the passed parameter in the Compare register.

Parameters:
__HANDLE__ | LPTIM handle
__VALUE__ | Compare value
Return values:
None
Note:
The CMP register can only be modified when the LPTIM instance is enabled.

Definition at line 450 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_DISABLE ( __HANDLE__ ) LPTIM_Disable(__HANDLE__)

Disable the LPTIM peripheral.

Parameters:
__HANDLE__ LPTIM handle
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Please call HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to check for TIMEOUT.
Return values:
None

Definition at line 405 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified LPTIM interrupt.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.
Note:
The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.

Definition at line 516 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

Enable the LPTIM peripheral.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 393 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified LPTIM interrupt.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.
Note:
The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.

Definition at line 499 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

Check whether the specified LPTIM flag is set or not.

Parameters:
__HANDLE__ LPTIM handle
__FLAG__ LPTIM flag to check This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
The state of the specified flag (SET or RESET).

Definition at line 466 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), and LPTIM_WaitForFlag().

#define __HAL_LPTIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->IER\
                                                                & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified LPTIM interrupt source is enabled or not.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to check. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
Interrupt status.

Definition at line 533 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT ( )
Value:
(EXTI->EMR1\
                                                        &= ~(LPTIM_EXTI_LINE_LPTIM1))

Disable the LPTIM1 EXTI line in event mode.

Return values:
None

Definition at line 559 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT ( )
Value:
(EXTI->IMR1\
                                                        &= ~(LPTIM_EXTI_LINE_LPTIM1))

Disable the LPTIM1 EXTI line in interrupt mode.

Return values:
None

Definition at line 546 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)

Enable the LPTIM1 EXTI line in event mode.

Return values:
None

Definition at line 553 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)

Enable the LPTIM1 EXTI line in interrupt mode.

Return values:
None

Definition at line 540 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT ( )
Value:
(EXTI->EMR1\
                                                        &= ~(LPTIM_EXTI_LINE_LPTIM2))

Disable the LPTIM2 EXTI line in event mode.

Return values:
None

Definition at line 585 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT ( )
Value:
(EXTI->IMR1\
                                                        &= ~(LPTIM_EXTI_LINE_LPTIM2))

Disable the LPTIM2 EXTI line in interrupt mode.

Return values:
None

Definition at line 572 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)

Enable the LPTIM2 EXTI line in event mode.

Return values:
None

Definition at line 579 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)

Enable the LPTIM2 EXTI line in interrupt mode.

Return values:
None

Definition at line 566 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)

Reset the LPTIM Counter register in synchronous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 425 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)

Reset after read of the LPTIM Counter register in asynchronous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 432 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                        (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
                                                        (__HANDLE__)->MspInitCallback   = NULL;                  \
                                                        (__HANDLE__)->MspDeInitCallback = NULL;                  \
                                                      } while(0)

Reset LPTIM handle state.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 379 of file stm32g0xx_hal_lptim.h.

#define __HAL_LPTIM_START_CONTINUOUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)

Start the LPTIM peripheral in Continuous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 412 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_START_SINGLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)

Start the LPTIM peripheral in single mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 418 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_SetOnce_Start(), and HAL_LPTIM_SetOnce_Start_IT().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Private Types

LPTIM Private Types
LPTIM
Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Private Variables

LPTIM Private Variables
LPTIM
Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Private Constants

Defines
LPTIM Private Constants
LPTIM

Defines

#define TIMEOUT 1000UL /* Timeout is 1s */

Define Documentation

#define TIMEOUT 1000UL /* Timeout is 1s */

Definition at line 180 of file stm32g0xx_hal_lptim.c.

Referenced by LPTIM_WaitForFlag().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PERIOD(__PERIOD__)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Define Documentation

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT ( __INSTANCE__ ) (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())

Definition at line 193 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_Counter_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT ( __INSTANCE__ ) (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())

Definition at line 190 of file stm32g0xx_hal_lptim.c.

Referenced by HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_AUTORELOAD ( __AUTORELOAD__ )
Value:
((0x00000001UL <= (__AUTORELOAD__)) &&\
                                                 ((__AUTORELOAD__) <= 0x0000FFFFUL))

Definition at line 804 of file stm32g0xx_hal_lptim.h.

#define IS_LPTIM_CLOCK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

Definition at line 775 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

Definition at line 756 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALERDIV1 ( __PRESCALER__ ) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)

Definition at line 765 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define IS_LPTIM_CLOCK_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

Definition at line 770 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

Definition at line 752 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_COMPARE ( __COMPARE__ ) ((__COMPARE__) <= 0x0000FFFFUL)

Definition at line 807 of file stm32g0xx_hal_lptim.h.

#define IS_LPTIM_COUNTER_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

Definition at line 801 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_EXT_TRG_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

Definition at line 789 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT1_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
((((__INSTANCE__) == LPTIM1) &&                       \
    (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
   ||                                                   \
   (((__INSTANCE__) == LPTIM2) &&                       \
    (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))

Definition at line 814 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT2_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
(((__INSTANCE__) == LPTIM1) &&                       \
   (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
    ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))

Definition at line 825 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

Definition at line 767 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_PERIOD ( __PERIOD__ )
Value:
((0x00000001UL <= (__PERIOD__)) &&\
                                                 ((__PERIOD__) <= 0x0000FFFFUL))

Definition at line 809 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_PULSE ( __PULSE__ ) ((__PULSE__) <= 0x0000FFFFUL)

Definition at line 812 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_TRG_SOURCE ( __TRIG__ )
Value:
(((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))

Definition at line 779 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_TRIG_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

Definition at line 793 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_UPDATE_MODE ( __MODE__ )
Value:
(((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

Definition at line 798 of file stm32g0xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PCD Private Macros

Defines | Functions
PCD Private Macros
PCD

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
#define | PCD_SET_ENDPOINT USB_DRD_SET_CHEP
#define | PCD_GET_ENDPOINT USB_DRD_GET_CHEP
#define | USB_EP0StartXfer USB_EPStartXfer
#define | PCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_SET_EP_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_KIND USB_DRD_SET_CHEP_KIND
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_EP_KIND USB_DRD_CLEAR_CHEP_KIND
#define | PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND
#define | PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND
#define | PCD_CLEAR_RX_EP_CTR USB_DRD_CLEAR_RX_CHEP_CTR
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR USB_DRD_CLEAR_TX_CHEP_CTR
#define | PCD_RX_DTOG USB_DRD_RX_DTOG
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG USB_DRD_TX_DTOG
#define | PCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
#define | PCD_SET_EP_ADDRESS USB_DRD_SET_CHEP_ADDRESS
Sets address in an endpoint register.
#define | PCD_SET_EP_TX_ADDRESS USB_DRD_SET_CHEP_TX_ADDRESS
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS USB_DRD_SET_CHEP_RX_ADDRESS
#define | PCD_SET_EP_TX_CNT USB_DRD_SET_CHEP_TX_CNT
sets counter for the tx/rx buffer.
#define | PCD_SET_EP_RX_CNT USB_DRD_SET_CHEP_RX_CNT
#define | PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT
gets counter of the tx buffer.
#define | PCD_SET_EP_DBUF_ADDR USB_DRD_SET_CHEP_DBUF_ADDR
Sets addresses in a double buffer endpoint.
#define | PCD_SET_EP_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
#define | PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT

Functions

__STATIC_INLINE uint16_t | PCD_GET_EP_RX_CNT (const PCD_TypeDef *Instance, uint16_t bEpNum)
gets counter of the rx buffer.
__STATIC_INLINE uint16_t | PCD_GET_EP_DBUF0_CNT (const PCD_TypeDef *Instance, uint16_t bEpNum)
gets counter of the rx buffer0.
__STATIC_INLINE uint16_t | PCD_GET_EP_DBUF1_CNT (const PCD_TypeDef *Instance, uint16_t bEpNum)
gets counter of the rx buffer1.

Define Documentation

#define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND

Definition at line 459 of file stm32g0xx_hal_pcd.h.

#define PCD_CLEAR_EP_KIND USB_DRD_CLEAR_CHEP_KIND

Definition at line 457 of file stm32g0xx_hal_pcd.h.

#define PCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG

Clears DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 484 of file stm32g0xx_hal_pcd.h.

#define PCD_CLEAR_RX_EP_CTR USB_DRD_CLEAR_RX_CHEP_CTR

Clears bit CTR_RX / CTR_TX in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 468 of file stm32g0xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG

Definition at line 485 of file stm32g0xx_hal_pcd.h.

#define PCD_CLEAR_TX_EP_CTR USB_DRD_CLEAR_TX_CHEP_CTR

Definition at line 469 of file stm32g0xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER

free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register

Parameters:
USBx USB device.
bEpNum,bDir
Return values:
None

Definition at line 430 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_GET_ENDPOINT USB_DRD_GET_CHEP

Definition at line 418 of file stm32g0xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT

gets counter of the tx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
Counter value

Definition at line 522 of file stm32g0xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Definition at line 80 of file stm32g0xx_hal_pcd.c.

#define PCD_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 79 of file stm32g0xx_hal_pcd.c.

#define PCD_RX_DTOG USB_DRD_RX_DTOG

Toggles DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 476 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND

Definition at line 458 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_ENDPOINT USB_DRD_SET_CHEP

Definition at line 415 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_EP_ADDRESS USB_DRD_SET_CHEP_ADDRESS

Sets address in an endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bAddr | Address.
Return values:
None

Definition at line 494 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_EP_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bDir | endpoint dir EP_DBUF_OUT = OUT EP_DBUF_IN = IN
wCount,: Counter value
Return values:
None

Definition at line 563 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_SET_EP_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT

Definition at line 564 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

#define PCD_SET_EP_DBUF_ADDR USB_DRD_SET_CHEP_DBUF_ADDR

Sets addresses in a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wBuf0Addr,: buffer 0 address.
wBuf1Addr | = buffer 1 address.
Return values:
None

Definition at line 552 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT

Definition at line 565 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_EP_KIND USB_DRD_SET_CHEP_KIND

Sets/clears directly EP_KIND bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 456 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_EP_RX_ADDRESS USB_DRD_SET_CHEP_RX_ADDRESS

Definition at line 504 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_EP_RX_CNT USB_DRD_SET_CHEP_RX_CNT

Definition at line 514 of file stm32g0xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_SET_EP_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS

sets the status for rx transfer (bits STAT_TX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 448 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Receive(), and PCD_EP_ISR_Handler().

#define PCD_SET_EP_TX_ADDRESS USB_DRD_SET_CHEP_TX_ADDRESS

sets address of the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wAddr | address to be set (must be word aligned).
Return values:
None

Definition at line 503 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_EP_TX_CNT USB_DRD_SET_CHEP_TX_CNT

sets counter for the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wCount | Counter value.
Return values:
None

Definition at line 513 of file stm32g0xx_hal_pcd.h.

#define PCD_SET_EP_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS

sets the status for tx transfer (bits STAT_TX[1:0]).

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 439 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Transmit().

#define PCD_TX_DTOG USB_DRD_TX_DTOG

Definition at line 477 of file stm32g0xx_hal_pcd.h.

#define USB_EP0StartXfer USB_EPStartXfer

Definition at line 421 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive(), and HAL_PCD_EP_Transmit().

Function Documentation

__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT | ( | const PCD_TypeDef * | Instance,
 |  | uint16_t | bEpNum
 | ) |  |

gets counter of the rx buffer0.

Parameters:
Instance | USB peripheral instance register address.
bEpNum | channel Number.
Return values:
Counter value

Definition at line 573 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT | ( | const PCD_TypeDef * | Instance,
 |  | uint16_t | bEpNum
 | ) |  |

gets counter of the rx buffer1.

Parameters:
Instance | USB peripheral instance register address.
bEpNum | channel Number.
Return values:
Counter value

Definition at line 593 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), and PCD_EP_ISR_Handler().

__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT | ( | const PCD_TypeDef * | Instance,
 |  | uint16_t | bEpNum
 | ) |  |

gets counter of the rx buffer.

Parameters:
Instance | USB peripheral instance register address.
bEpNum | channel Number.
Return values:
Counter value

Definition at line 530 of file stm32g0xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef | PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.
static HAL_StatusTypeDef | HAL_PCD_EP_DB_Transmit (PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal)
Manage double buffer bulk IN transaction from ISR.
static uint16_t | HAL_PCD_EP_DB_Receive (PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal)
Manage double buffer bulk out transaction from ISR.

Function Documentation

static uint16_t HAL_PCD_EP_DB_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_EPTypeDef * | ep,
 |  | uint16_t | wEPVal
 | ) |  | [static]

Manage double buffer bulk out transaction from ISR.

Parameters:
hpcd | PCD handle
ep | current endpoint handle
wEPVal | Last snapshot of EPRx register value taken in ISR
Return values:
HAL status

Definition at line 2007 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, PCD_FREE_USER_BUFFER, PCD_GET_EP_DBUF0_CNT(), PCD_GET_EP_DBUF1_CNT(), and PCD_SET_EP_RX_STATUS.

Referenced by PCD_EP_ISR_Handler().

static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_EPTypeDef * | ep,
 |  | uint16_t | wEPVal
 | ) |  | [static]

Manage double buffer bulk IN transaction from ISR.

Parameters:
hpcd | PCD handle
ep | current endpoint handle
wEPVal | Last snapshot of EPRx register value taken in ISR
Return values:
HAL status

Definition at line 2088 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, HAL_PCD_DataInStageCallback(), __PCD_HandleTypeDef::Instance, PCD_FREE_USER_BUFFER, PCD_GET_EP_DBUF0_CNT(), PCD_GET_EP_DBUF1_CNT(), PCD_SET_EP_DBUF0_CNT, PCD_SET_EP_DBUF1_CNT, and PCD_SET_EP_TX_STATUS.

Referenced by PCD_EP_ISR_Handler().

static HAL_StatusTypeDef PCD_EP_ISR_Handler ( PCD_HandleTypeDef * hpcd ) [static]

This function handles PCD Endpoint interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1728 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::DataOutStageCallback, HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), HAL_PCD_SetupStageCallback(), __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::OUT_ep, PCD_CLEAR_RX_EP_CTR, PCD_CLEAR_TX_EP_CTR, PCD_ENDP0, PCD_FREE_USER_BUFFER, PCD_GET_ENDPOINT, PCD_GET_EP_DBUF0_CNT(), PCD_GET_EP_DBUF1_CNT(), PCD_GET_EP_RX_CNT(), PCD_GET_EP_TX_CNT, PCD_SET_EP_DBUF0_CNT, PCD_SET_EP_DBUF1_CNT, PCD_SET_EP_RX_CNT, PCD_SET_EP_RX_STATUS, __PCD_HandleTypeDef::Setup, __PCD_HandleTypeDef::SetupStageCallback, and __PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL USB OTG PCD Callback ID enumeration definition

Enumerations
HAL USB OTG PCD Callback ID enumeration definition
Initialization and de-initialization functions

HAL USB OTG PCD Callback ID enumeration definition. More...

Enumerations

enum HAL_PCD_CallbackIDTypeDef {
HAL_PCD_SOF_CB_ID = 0x01, HAL_PCD_SETUPSTAGE_CB_ID = 0x02, HAL_PCD_RESET_CB_ID = 0x03, HAL_PCD_SUSPEND_CB_ID = 0x04,
HAL_PCD_RESUME_CB_ID = 0x05, HAL_PCD_CONNECT_CB_ID = 0x06, HAL_PCD_DISCONNECT_CB_ID = 0x07, HAL_PCD_MSPINIT_CB_ID = 0x08,
HAL_PCD_MSPDEINIT_CB_ID = 0x09
}

Detailed Description

HAL USB OTG PCD Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_PCD_CallbackIDTypeDef
Enumerator:
HAL_PCD_SOF_CB_ID

USB PCD SOF callback ID

HAL_PCD_SETUPSTAGE_CB_ID

USB PCD Setup Stage callback ID

HAL_PCD_RESET_CB_ID

USB PCD Reset callback ID

HAL_PCD_SUSPEND_CB_ID

USB PCD Suspend callback ID

HAL_PCD_RESUME_CB_ID

USB PCD Resume callback ID

HAL_PCD_CONNECT_CB_ID

USB PCD Connect callback ID

HAL_PCD_DISCONNECT_CB_ID

USB PCD Disconnect callback ID

HAL_PCD_MSPINIT_CB_ID

USB PCD MspInit callback ID

HAL_PCD_MSPDEINIT_CB_ID

USB PCD MspDeInit callback ID

Definition at line 225 of file stm32g0xx_hal_pcd.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL USB OTG PCD Callback pointer definition

Typedefs
HAL USB OTG PCD Callback pointer definition
Initialization and de-initialization functions

HAL USB OTG PCD Callback pointer definition. More...

Typedefs

typedef void(* | pPCD_CallbackTypeDef )(PCD_HandleTypeDef *hpcd)
typedef void(* | pPCD_DataOutStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_DataInStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoOutIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoInIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_LpmCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
typedef void(* | pPCD_BcdCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

Detailed Description

HAL USB OTG PCD Callback pointer definition.

Typedef Documentation

typedef void(* pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

pointer to USB OTG PCD BCD callback

Definition at line 254 of file stm32g0xx_hal_pcd.h.

typedef void(* pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd)

pointer to a common USB OTG PCD callback function

Definition at line 248 of file stm32g0xx_hal_pcd.h.

typedef void(* pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD Data IN Stage callback

Definition at line 250 of file stm32g0xx_hal_pcd.h.

typedef void(* pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD Data OUT Stage callback

Definition at line 249 of file stm32g0xx_hal_pcd.h.

typedef void(* pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD ISO IN Incomplete callback

Definition at line 252 of file stm32g0xx_hal_pcd.h.

typedef void(* pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD ISO OUT Incomplete callback

Definition at line 251 of file stm32g0xx_hal_pcd.h.

typedef void(* pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)

pointer to USB OTG PCD LPM callback

Definition at line 253 of file stm32g0xx_hal_pcd.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Modules | Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Modules

HAL USB OTG PCD Callback ID enumeration definition

HAL USB OTG PCD Callback ID enumeration definition.

HAL USB OTG PCD Callback pointer definition

HAL USB OTG PCD Callback pointer definition.

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 223 of file stm32g0xx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::MspDeInitCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 124 of file stm32g0xx_hal_pcd.c.

References __HAL_PCD_DISABLE, assert_param, __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::DisconnectCallback, HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_MspInit(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetupStageCallback(), HAL_PCD_SOFCallback(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SuspendCallback(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::ISOINIncompleteCallback, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, __PCD_HandleTypeDef::Lock, __PCD_HandleTypeDef::LPMCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::OUT_ep, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, __PCD_HandleTypeDef::SuspendCallback, and __PCD_HandleTypeDef::USB_Address.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 277 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_DeInit(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 262 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_BcdCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD BCD Callback function
Return values:
HAL status

Definition at line 816 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | HAL_PCD_CallbackIDTypeDef | CallbackID,
 |  | pPCD_CallbackTypeDef | pCallback
 | ) |  |

Register a User USB PCD Callback To be used instead of the weak predefined callback.

Parameters:
hpcd | USB PCD handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
  • HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
  • HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
  • HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
  • HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
  • HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
  • HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
  • HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 306 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DisconnectCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_CONNECT_CB_ID, HAL_PCD_DISCONNECT_CB_ID, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_MSPDEINIT_CB_ID, HAL_PCD_MSPINIT_CB_ID, HAL_PCD_RESET_CB_ID, HAL_PCD_RESUME_CB_ID, HAL_PCD_SETUPSTAGE_CB_ID, HAL_PCD_SOF_CB_ID, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SUSPEND_CB_ID, __PCD_HandleTypeDef::MspDeInitCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, and __PCD_HandleTypeDef::SuspendCallback.

HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_DataInStageCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Data IN Stage Callback function
Return values:
HAL status

Definition at line 592 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_DataOutStageCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Data OUT Stage Callback function
Return values:
HAL status

Definition at line 518 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_IsoInIncpltCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Iso IN incomplete Callback function
Return values:
HAL status

Definition at line 741 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOINIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_IsoOutIncpltCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Iso OUT incomplete Callback function
Return values:
HAL status

Definition at line 666 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_LpmCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD LPM Callback function
Return values:
HAL status

Definition at line 889 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::LPMCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 856 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, HAL_PCDEx_BCD_Callback(), and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | HAL_PCD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USB PCD Callback USB PCD callback is redirected to the weak predefined callback.

Parameters:
hpcd USB PCD handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
  • HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
  • HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
  • HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
  • HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
  • HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
  • HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
  • HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 419 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DisconnectCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_CONNECT_CB_ID, HAL_PCD_ConnectCallback(), HAL_PCD_DISCONNECT_CB_ID, HAL_PCD_DisconnectCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_MspDeInit(), HAL_PCD_MSPDEINIT_CB_ID, HAL_PCD_MspInit(), HAL_PCD_MSPINIT_CB_ID, HAL_PCD_RESET_CB_ID, HAL_PCD_ResetCallback(), HAL_PCD_RESUME_CB_ID, HAL_PCD_ResumeCallback(), HAL_PCD_SETUPSTAGE_CB_ID, HAL_PCD_SetupStageCallback(), HAL_PCD_SOF_CB_ID, HAL_PCD_SOFCallback(), HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SUSPEND_CB_ID, HAL_PCD_SuspendCallback(), __PCD_HandleTypeDef::MspDeInitCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, and __PCD_HandleTypeDef::SuspendCallback.

HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 633 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_DataInStageCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 559 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_DataOutStageCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 783 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOINIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 708 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback ( PCD_HandleTypeDef * hpcd )

Unregister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 929 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::LPMCallback, and __PCD_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1304 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1180 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_EP_DB_Transmit(), HAL_PCD_Init(), HAL_PCD_UnRegisterDataInStageCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data OUT stage callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1163 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterDataOutStageCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1319 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

This function handles PCD interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1011 of file stm32g0xx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __PCD_HandleTypeDef::BESL, HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetAddress(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::Instance, LPM_L0, LPM_L1, __PCD_HandleTypeDef::LPM_State, __PCD_HandleTypeDef::LPMCallback, PCD_EP_ISR_Handler(), PCD_LPM_L0_ACTIVE, PCD_LPM_L1_ACTIVE, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SOFCallback, and __PCD_HandleTypeDef::SuspendCallback.

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1288 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterIsoInIncpltCallback().

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1271 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterIsoOutIncpltCallback().

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1225 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1255 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1195 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1210 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 980 of file stm32g0xx_hal_pcd.c.

References __HAL_PCD_ENABLE, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 995 of file stm32g0xx_hal_pcd.c.

References __HAL_PCD_DISABLE, and __PCD_HandleTypeDef::Instance.

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1240 of file stm32g0xx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Abort (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Abort an USB EP transaction.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

Activate remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1665 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

De-activate remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1675 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1353 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1367 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_EP_Abort | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Abort an USB EP transaction.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1625 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1444 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1589 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1651 of file stm32g0xx_hal_pcd.c.

uint32_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
Data Size

Definition at line 1506 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
ep_mps | endpoint max packet size
ep_type | endpoint type
Return values:
HAL status

Definition at line 1399 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the reception buffer
len | amount of data to be received
Return values:
HAL status

Definition at line 1475 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::OUT_ep, and USB_EP0StartXfer.

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1551 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the transmission buffer
len | amount of data to be sent
Return values:
HAL status

Definition at line 1518 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and USB_EP0StartXfer.

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd | PCD handle
address | new device address
Return values:
HAL status

Definition at line 1382 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef * hpcd )

Return the PCD handle state.

Parameters:
hpcd PCD handle
Return values:
HAL state

Definition at line 1704 of file stm32g0xx_hal_pcd.c.

References __PCD_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | __PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_DRD_TypeDef | PCD_TypeDef
typedef USB_DRD_CfgTypeDef | PCD_InitTypeDef
typedef USB_DRD_EPTypeDef | PCD_EPTypeDef
typedef struct __PCD_HandleTypeDef | PCD_HandleTypeDef
PCD Handle Structure definition.

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }
enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}

Typedef Documentation

typedef USB_DRD_EPTypeDef PCD_EPTypeDef

Definition at line 85 of file stm32g0xx_hal_pcd.h.

typedef struct __PCD_HandleTypeDef PCD_HandleTypeDef

PCD Handle Structure definition.

typedef USB_DRD_CfgTypeDef PCD_InitTypeDef

Definition at line 84 of file stm32g0xx_hal_pcd.h.

typedef USB_DRD_TypeDef PCD_TypeDef

Definition at line 83 of file stm32g0xx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_BCD_MsgTypeDef
Enumerator:
PCD_BCD_ERROR
PCD_BCD_CONTACT_DETECTION
PCD_BCD_STD_DOWNSTREAM_PORT
PCD_BCD_CHARGING_DOWNSTREAM_PORT
PCD_BCD_DEDICATED_CHARGING_PORT
PCD_BCD_DISCOVERY_COMPLETED

Definition at line 72 of file stm32g0xx_hal_pcd.h.

enum PCD_LPM_MsgTypeDef
Enumerator:
PCD_LPM_L0_ACTIVE
PCD_LPM_L1_ACTIVE

Definition at line 66 of file stm32g0xx_hal_pcd.h.

enum PCD_LPM_StateTypeDef
Enumerator:
LPM_L0
LPM_L1
LPM_L2
LPM_L3

Definition at line 58 of file stm32g0xx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 48 of file stm32g0xx_hal_pcd.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32g0xx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
__IO uint8_t | USB_Address
PCD_EPTypeDef | IN_ep [8]
PCD_EPTypeDef | OUT_ep [8]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Setup [12]
PCD_LPM_StateTypeDef LPM_State
uint32_t | BESL
uint32_t | lpm_active
uint32_t | battery_charging_active
void * | pData
void(* | SOFCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | SetupStageCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ResetCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | SuspendCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ResumeCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ConnectCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | DisconnectCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | DataOutStageCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | DataInStageCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | ISOOUTIncompleteCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | ISOINIncompleteCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | BCDCallback )(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
void(* | LPMCallback )(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
void(* | MspInitCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | MspDeInitCallback )(struct __PCD_HandleTypeDef *hpcd)

Detailed Description

PCD Handle Structure definition.

Definition at line 91 of file stm32g0xx_hal_pcd.h.

Field Documentation

uint32_t __PCD_HandleTypeDef::battery_charging_active

Enable or disable Battery charging. This parameter can be set to ENABLE or DISABLE

Definition at line 112 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateBCD(), and HAL_PCDEx_DeActivateBCD().

void(* __PCD_HandleTypeDef::BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

USB OTG PCD BCD callback

Definition at line 129 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_UnRegisterBcdCallback(), and HAL_PCDEx_BCD_VBUSDetect().

uint32_t __PCD_HandleTypeDef::BESL

Definition at line 106 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

void(* __PCD_HandleTypeDef::ConnectCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Connect callback

Definition at line 122 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD Data IN Stage callback

Definition at line 126 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_DB_Transmit(), HAL_PCD_Init(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_UnRegisterDataInStageCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD Data OUT Stage callback

Definition at line 125 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Disconnect callback

Definition at line 123 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO uint32_t __PCD_HandleTypeDef::ErrorCode

PCD Error code

Definition at line 103 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

PCD_EPTypeDef __PCD_HandleTypeDef::IN_ep[8]

IN endpoint parameters

Definition at line 99 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Abort(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

PCD_InitTypeDef __PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 97 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_ClrStall(), HAL_PCD_EP_SetStall(), and HAL_PCD_Init().

PCD_TypeDef* __PCD_HandleTypeDef::Instance

Register base address

Definition at line 96 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_DeInit(), HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), HAL_PCD_EP_Abort(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_DB_Receive(), HAL_PCD_EP_DB_Transmit(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Start(), HAL_PCD_Stop(), HAL_PCDEx_ActivateBCD(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PCDEx_DeActivateBCD(), HAL_PCDEx_DeActivateLPM(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD ISO IN Incomplete callback

Definition at line 128 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterIsoInIncpltCallback(), and HAL_PCD_UnRegisterIsoInIncpltCallback().

void(* __PCD_HandleTypeDef::ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD ISO OUT Incomplete callback

Definition at line 127 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterIsoOutIncpltCallback().

HAL_LockTypeDef __PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 101 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

uint32_t __PCD_HandleTypeDef::lpm_active

Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE

Definition at line 109 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateLPM(), and HAL_PCDEx_DeActivateLPM().

PCD_LPM_StateTypeDef __PCD_HandleTypeDef::LPM_State

LPM State

Definition at line 105 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler(), and HAL_PCDEx_ActivateLPM().

void(* __PCD_HandleTypeDef::LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)

USB OTG PCD LPM callback

Definition at line 130 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterLpmCallback(), and HAL_PCD_UnRegisterLpmCallback().

void(* __PCD_HandleTypeDef::MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Msp DeInit callback

Definition at line 133 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::MspInitCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Msp Init callback

Definition at line 132 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

PCD_EPTypeDef __PCD_HandleTypeDef::OUT_ep[8]

OUT endpoint parameters

Definition at line 100 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Abort(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

void* __PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 114 of file stm32g0xx_hal_pcd.h.

void(* __PCD_HandleTypeDef::ResetCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Reset callback

Definition at line 119 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::ResumeCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Resume callback

Definition at line 121 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

uint32_t __PCD_HandleTypeDef::Setup[12]

Setup packet buffer

Definition at line 104 of file stm32g0xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Setup Stage callback

Definition at line 118 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), HAL_PCD_UnRegisterCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::SOFCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD SOF callback

Definition at line 117 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO PCD_StateTypeDef __PCD_HandleTypeDef::State

PCD communication state

Definition at line 102 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), HAL_PCD_Init(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

void(* __PCD_HandleTypeDef::SuspendCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Suspend callback

Definition at line 120 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO uint8_t __PCD_HandleTypeDef::USB_Address

USB Address

Definition at line 98 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_SetAddress(), and PCD_EP_ISR_Handler().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_pcd.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PCD Speed

Defines
PCD Speed
PCD Exported Constants

Defines

#define PCD_SPEED_FULL USBD_FS_SPEED

Define Documentation

#define PCD_SPEED_FULL USBD_FS_SPEED

Definition at line 152 of file stm32g0xx_hal_pcd.h.

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STM32G0C1xx HAL User Manual: PCD PHY Module

Defines
PCD PHY Module
PCD Exported Constants

Defines

#define | PCD_PHY_ULPI 1U
#define | PCD_PHY_EMBEDDED 2U
#define | PCD_PHY_UTMI 3U

Define Documentation

#define PCD_PHY_EMBEDDED 2U

Definition at line 161 of file stm32g0xx_hal_pcd.h.

#define PCD_PHY_ULPI 1U

Definition at line 160 of file stm32g0xx_hal_pcd.h.

#define PCD_PHY_UTMI 3U

Definition at line 162 of file stm32g0xx_hal_pcd.h.

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STM32G0C1xx HAL User Manual: PCD Error Code definition

Defines
PCD Error Code definition
PCD Exported Constants

PCD Error Code definition. More...

Defines

#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)

Detailed Description

PCD Error Code definition.

Define Documentation

#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)

Invalid Callback error

Definition at line 172 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PCD Exported Macros

Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__HANDLE__)->Instance->ISTR)\
                                                                   &= (uint16_t)(~(__INTERRUPT__)))

Definition at line 195 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_DISABLE ( __HANDLE__ ) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 191 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_Stop().

#define __HAL_PCD_ENABLE ( __HANDLE__ ) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 190 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCD_Start().

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((USB_ReadInterrupts((__HANDLE__)->Instance)\
                                                                    & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 192 of file stm32g0xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE)

Definition at line 199 of file stm32g0xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE

Definition at line 198 of file stm32g0xx_hal_pcd.h.

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STM32G0C1xx HAL User Manual: USB EXTI line interrupt

Defines
USB EXTI line interrupt
PCD Private Constants

Defines

#define USB_WAKEUP_EXTI_LINE (0x1U << 4)

Define Documentation

#define USB_WAKEUP_EXTI_LINE (0x1U << 4)

USB FS EXTI Line WakeUp Interrupt

Definition at line 364 of file stm32g0xx_hal_pcd.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PCD EP0 MPS

Defines
PCD EP0 MPS
PCD Private Constants

Defines

#define | PCD_EP0MPS_64 EP_MPS_64
#define | PCD_EP0MPS_32 EP_MPS_32
#define | PCD_EP0MPS_16 EP_MPS_16
#define | PCD_EP0MPS_08 EP_MPS_8

Define Documentation

#define PCD_EP0MPS_08 EP_MPS_8

Definition at line 377 of file stm32g0xx_hal_pcd.h.

#define PCD_EP0MPS_16 EP_MPS_16

Definition at line 376 of file stm32g0xx_hal_pcd.h.

#define PCD_EP0MPS_32 EP_MPS_32

Definition at line 375 of file stm32g0xx_hal_pcd.h.

#define PCD_EP0MPS_64 EP_MPS_64

Definition at line 374 of file stm32g0xx_hal_pcd.h.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PCD ENDP

Defines
PCD ENDP
PCD Private Constants

Defines

#define | PCD_ENDP0 0U
#define | PCD_ENDP1 1U
#define | PCD_ENDP2 2U
#define | PCD_ENDP3 3U
#define | PCD_ENDP4 4U
#define | PCD_ENDP5 5U
#define | PCD_ENDP6 6U
#define | PCD_ENDP7 7U

Define Documentation

#define PCD_ENDP0 0U

Definition at line 385 of file stm32g0xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_ENDP1 1U

Definition at line 386 of file stm32g0xx_hal_pcd.h.

#define PCD_ENDP2 2U

Definition at line 387 of file stm32g0xx_hal_pcd.h.

#define PCD_ENDP3 3U

Definition at line 388 of file stm32g0xx_hal_pcd.h.

#define PCD_ENDP4 4U

Definition at line 389 of file stm32g0xx_hal_pcd.h.

#define PCD_ENDP5 5U

Definition at line 390 of file stm32g0xx_hal_pcd.h.

#define PCD_ENDP6 6U

Definition at line 391 of file stm32g0xx_hal_pcd.h.

#define PCD_ENDP7 7U

Definition at line 392 of file stm32g0xx_hal_pcd.h.

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STM32G0C1xx HAL User Manual: PCD Endpoint Kind

Defines
PCD Endpoint Kind
PCD Private Constants

Defines

#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U

Define Documentation

#define PCD_DBL_BUF 1U

Definition at line 401 of file stm32g0xx_hal_pcd.h.

#define PCD_SNG_BUF 0U

Definition at line 400 of file stm32g0xx_hal_pcd.h.

Referenced by HAL_PCDEx_PMAConfig().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCDEx Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCDEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update FIFO configuration

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_ActivateBCD ( PCD_HandleTypeDef * hpcd )

Activate BatteryCharging feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 122 of file stm32g0xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::battery_charging_active, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_ActivateLPM ( PCD_HandleTypeDef * hpcd )

Activate LPM feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 251 of file stm32g0xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::lpm_active, LPM_L0, and __PCD_HandleTypeDef::LPM_State.

Referenced by HAL_PCD_Init().

void HAL_PCDEx_BCD_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_BCD_MsgTypeDef | msg
 | ) |  |

Send BatteryCharging message to user layer callback.

Parameters:
hpcd | PCD handle
msg | LPM message
Return values:
HAL status

Definition at line 306 of file stm32g0xx_hal_pcd_ex.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterBcdCallback(), and HAL_PCDEx_BCD_VBUSDetect().

void HAL_PCDEx_BCD_VBUSDetect ( PCD_HandleTypeDef * hpcd )

Handle BatteryCharging Process.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 159 of file stm32g0xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::BCDCallback, HAL_Delay(), HAL_GetTick(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_DeActivateBCD(), __PCD_HandleTypeDef::Instance, PCD_BCD_CHARGING_DOWNSTREAM_PORT, PCD_BCD_CONTACT_DETECTION, PCD_BCD_DEDICATED_CHARGING_PORT, PCD_BCD_DISCOVERY_COMPLETED, PCD_BCD_ERROR, and PCD_BCD_STD_DOWNSTREAM_PORT.

HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD ( PCD_HandleTypeDef * hpcd )

Deactivate BatteryCharging feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 143 of file stm32g0xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::battery_charging_active, and __PCD_HandleTypeDef::Instance.

Referenced by HAL_PCDEx_BCD_VBUSDetect().

HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM ( PCD_HandleTypeDef * hpcd )

Deactivate LPM feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 269 of file stm32g0xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::lpm_active.

void HAL_PCDEx_LPM_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_LPM_MsgTypeDef | msg
 | ) |  |

Send LPM message to user layer callback.

Parameters:
hpcd | PCD handle
msg | LPM message
Return values:
HAL status

Definition at line 289 of file stm32g0xx_hal_pcd_ex.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterLpmCallback().

HAL_StatusTypeDef HAL_PCDEx_PMAConfig | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | ep_addr,
 |  | uint16_t | ep_kind,
 |  | uint32_t | pmaadress
 | ) |  |

Configure PMA for EP.

Parameters:
hpcd | Device instance
ep_addr | endpoint address
ep_kind | endpoint Kind USB_SNG_BUF: Single Buffer used USB_DBL_BUF: Double Buffer used
pmaadress,: EP address in The PMA: In case of single buffer endpoint this parameter is 16-bit value providing the address in PMA allocated to endpoint. In case of double buffer endpoint this parameter is a 32-bit value providing the endpoint buffer 0 address in the LSB part of 32-bit value and endpoint buffer 1 address in the MSB part of 32-bit value.
Return values:
HAL status

Definition at line 80 of file stm32g0xx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::OUT_ep, and PCD_SNG_BUF.

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STM32G0C1xx HAL User Manual: PWR Private Defines

PWR Private Defines
PWR
Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Exported Types

PWR Exported Types
PWR
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STM32G0C1xx HAL User Manual: PWR WakeUp pins

Defines
PWR WakeUp pins
PWR Exported Constants

Defines

#define | PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN6 PWR_CR3_EWUP6
#define | PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN6_HIGH PWR_CR3_EWUP6
#define | PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)
#define | PWR_WAKEUP_PIN6_LOW ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6)

Define Documentation

#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1

Wakeup pin 1 (with high level detection)

Definition at line 56 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1

Wakeup pin 1 (with high level detection)

Definition at line 66 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)

Wakeup pin 1 (with low level detection)

Definition at line 76 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2

Wakeup pin 2 (with high level detection)

Definition at line 57 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2

Wakeup pin 2 (with high level detection)

Definition at line 67 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)

Wakeup pin 2 (with low level detection)

Definition at line 77 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3

Wakeup pin 3 (with high level detection)

Definition at line 59 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3

Wakeup pin 3 (with high level detection)

Definition at line 69 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)

Wakeup pin 3 (with low level detection)

Definition at line 79 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4

Wakeup pin 4 (with high level detection)

Definition at line 61 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4

Wakeup pin 4 (with high level detection)

Definition at line 71 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)

Wakeup pin 4 (with low level detection)

Definition at line 81 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5

Wakeup pin 5 (with high level detection)

Definition at line 63 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5

Wakeup pin 5 (with high level detection)

Definition at line 73 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)

Wakeup pin 5 (with low level detection)

Definition at line 83 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN6 PWR_CR3_EWUP6

Wakeup pin 6 (with high level detection)

Definition at line 65 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN6_HIGH PWR_CR3_EWUP6

Wakeup pin 6 (with high level detection)

Definition at line 75 of file stm32g0xx_hal_pwr.h.

#define PWR_WAKEUP_PIN6_LOW ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6)

Wakeup pin 6 (with low level detection)

Definition at line 85 of file stm32g0xx_hal_pwr.h.

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STM32G0C1xx HAL User Manual: PWR Low Power Mode Selection

Defines
PWR Low Power Mode Selection
PWR Exported Constants

Defines

#define | PWR_LOWPOWERMODE_STOP0 (0x00000000u)
#define | PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0)
#define | PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
#define | PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2)

Define Documentation

#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2)

Shutdown mode

Definition at line 97 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSHUTDOWNMode().

#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)

Standby mode

Definition at line 95 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTANDBYMode().

#define PWR_LOWPOWERMODE_STOP0 (0x00000000u)

Stop 0: stop mode with main regulator

Definition at line 93 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0)

Stop 1: stop mode with low power regulator

Definition at line 94 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

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STM32G0C1xx HAL User Manual: PWR regulator mode

Defines
PWR regulator mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON (0x00000000u)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR

Regulator in low-power mode

Definition at line 107 of file stm32g0xx_hal_pwr.h.

#define PWR_MAINREGULATOR_ON (0x00000000u)

Regulator in main mode

Definition at line 106 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), and HAL_PWR_EnterSTOPMode().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01u)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02u)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02u)

Wait For Event instruction to enter Sleep mode

Definition at line 116 of file stm32g0xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01u)

Wait For Interruption instruction to enter Sleep mode

Definition at line 115 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

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STM32G0C1xx HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01u)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02u)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02u)

Wait For Event instruction to enter Stop mode

Definition at line 125 of file stm32g0xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01u)

Wait For Interruption instruction to enter Stop mode

Definition at line 124 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Status Flags

Defines
PWR Status Flags
PWR Exported Constants | PWR Extended Exported Constants

Elements values convention: 0000 00XX 000Y YYYYb. More...

Defines

#define | PWR_FLAG_WUF1 (0x00010000u | PWR_SR1_WUF1)
#define | PWR_FLAG_WUF2 (0x00010000u | PWR_SR1_WUF2)
#define | PWR_FLAG_WUF3 (0x00010000u | PWR_SR1_WUF3)
#define | PWR_FLAG_WUF4 (0x00010000u | PWR_SR1_WUF4)
#define | PWR_FLAG_WUF5 (0x00010000u | PWR_SR1_WUF5)
#define | PWR_FLAG_WUF6 (0x00010000u | PWR_SR1_WUF6)
#define | PWR_FLAG_WUF (0x00010000u | PWR_SR1_WUF)
#define | PWR_FLAG_SB (0x00010000u | PWR_SR1_SBF)
#define | PWR_FLAG_WUFI (0x00010000u | PWR_SR1_WUFI)
#define | PWR_FLAG_FLASH_READY (0x00020000u | PWR_SR2_FLASH_RDY)
#define | PWR_FLAG_REGLPS (0x00020000u | PWR_SR2_REGLPS)
#define | PWR_FLAG_REGLPF (0x00020000u | PWR_SR2_REGLPF)
#define | PWR_FLAG_PVDO (0x00020000u | PWR_SR2_PVDO)
#define | PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_USB)
#define | PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB)

Detailed Description

Elements values convention: 0000 00XX 000Y YYYYb.

  • Y YYYY : Flag position in the XX register (5 bits)
  • XX : Status register (2 bits)
    • 01: SR1 register
    • 10: SR2 register The only exception is PWR_FLAG_WU, encompassing all wake-up flags and set to PWR_SR1_WUF.

Define Documentation

#define PWR_FLAG_FLASH_READY (0x00020000u | PWR_SR2_FLASH_RDY)

Flash ready

Definition at line 153 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_PVDO (0x00020000u | PWR_SR2_PVDO)

Power Voltage Detector output

Definition at line 157 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_USB)

Power Voltage Monitoring output

Definition at line 160 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB)

USB Peripheral Voltage Monitoring output

Definition at line 259 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_FLAG_REGLPF (0x00020000u | PWR_SR2_REGLPF)

Regulator Low Power flag

Definition at line 155 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_REGLPS (0x00020000u | PWR_SR2_REGLPS)

Regulator Low Power started

Definition at line 154 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_SB (0x00010000u | PWR_SR1_SBF)

Standby flag

Definition at line 151 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_WUF (0x00010000u | PWR_SR1_WUF)

Wakeup event on all wakeup pin

Definition at line 150 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_WUF1 (0x00010000u | PWR_SR1_WUF1)

Wakeup event on wakeup pin 1

Definition at line 140 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_WUF2 (0x00010000u | PWR_SR1_WUF2)

Wakeup event on wakeup pin 2

Definition at line 141 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_WUF3 (0x00010000u | PWR_SR1_WUF3)

Wakeup event on wakeup pin 3

Definition at line 143 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_WUF4 (0x00010000u | PWR_SR1_WUF4)

Wakeup event on wakeup pin 4

Definition at line 145 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_WUF5 (0x00010000u | PWR_SR1_WUF5)

Wakeup event on wakeup pin 5

Definition at line 147 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_WUF6 (0x00010000u | PWR_SR1_WUF6)

Wakeup event on wakeup pin 6

Definition at line 149 of file stm32g0xx_hal_pwr.h.

#define PWR_FLAG_WUFI (0x00010000u | PWR_SR1_WUFI)

Wakeup on internal wakeup line

Definition at line 152 of file stm32g0xx_hal_pwr.h.

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STM32G0C1xx HAL User Manual: PWR Exported Macros

Defines
PWR Exported Macros
PWR

Defines

#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check whether or not a specific PWR flag is set.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->SCR = (__FLAG__))
Clear a specific PWR flag.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ ) (PWR->SCR = (__FLAG__))

Clear a specific PWR flag.

Parameters:
__FLAG__ specifies the flag to clear. This parameter can be a combination of following values:
  • PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event was received from the WKUP pin 1.
  • PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event was received from the WKUP pin 2.
  • PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event was received from the WKUP pin 3. (*)
  • PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event was received from the WKUP pin 4.
  • PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event was received from the WKUP pin 5. (*)
  • PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event was received from the WKUP pin 6.
  • PWR_FLAG_WUF: Encompasses all Wake Up Flags.
  • PWR_FLAG_SB: Standby Flag. Indicates that the system entered Standby mode.
Return values:
None

Definition at line 231 of file stm32g0xx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ )
Value:
(((__FLAG__) & 0x00010000u) ?\
                                             ((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\
                                             ((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)))

Check whether or not a specific PWR flag is set.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one a combination of following values:
  • PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event was received from the WKUP pin 1.
  • PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event was received from the WKUP pin 2.
  • PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event was received from the WKUP pin 3. (*)
  • PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event was received from the WKUP pin 4.
  • PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event was received from the WKUP pin 5. (*)
  • PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event was received from the WKUP pin 6.
  • PWR_FLAG_SB: StandBy Flag. Indicates that the system entered StandBy mode.
  • PWR_FLAG_WUFI: Wake-Up Flag Internal. Set when a wakeup is detected on the internal wakeup line. OR a combination of following values:
  • PWR_FLAG_FLASH_READY: Flash is ready. Indicates whether flash can be used or not
  • PWR_FLAG_REGLPS: Low Power Regulator Started. Indicates whether or not the low-power regulator is ready.
  • PWR_FLAG_REGLPF: Low Power Regulator Flag. Indicates whether the regulator is ready in main mode or is in low-power mode.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 207 of file stm32g0xx_hal_pwr.h.

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STM32G0C1xx HAL User Manual: Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants

Defines
Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
PWR

Defines

#define PWR_WUP_POLARITY_SHIFT 0x08u

Define Documentation

#define PWR_WUP_POLARITY_SHIFT 0x08u

Internal constant used to retrieve wakeup pin polariry

Definition at line 241 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnableWakeUpPin().

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STM32G0C1xx HAL User Manual: PWR Private Macros

Defines
PWR Private Macros
PWR

Defines

#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY)
#define | IS_PWR_STOP_ENTRY(ENTRY)

Define Documentation

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                                   ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 254 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), and HAL_PWR_EnterSTOPMode().

#define IS_PWR_SLEEP_ENTRY ( ENTRY )
Value:
(((ENTRY) == PWR_SLEEPENTRY_WFI) || \
                                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 257 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY )
Value:
(((ENTRY) == PWR_STOPENTRY_WFI) || \
                                                   ((ENTRY) == PWR_STOPENTRY_WFE))

Definition at line 260 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
((((PIN) & ((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) != 0x00000000u) && \
                                                   (((PIN) & ~((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) == 0x00000000u))

Definition at line 251 of file stm32g0xx_hal_pwr.h.

Referenced by HAL_PWR_DisableWakeUpPin(), and HAL_PWR_EnableWakeUpPin().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PWR Exported Functions

Initialization and de-initialization functions. More...

Functions

void HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitialize the HAL PWR peripheral registers to their default reset values.

Return values:
None

Definition at line 73 of file stm32g0xx_hal_pwr.c.

References __HAL_RCC_PWR_FORCE_RESET, and __HAL_RCC_PWR_RELEASE_RESET.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC & TAMP registers, backup registers, RCC BDCR register).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Enable Sleep-On-Exit Cortex feature.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit Cortex feature.
void | HAL_PWR_EnableSEVOnPend (void)
Enable Cortex Sev On Pending feature.
void | HAL_PWR_DisableSEVOnPend (void)
Disable Cortex Sev On Pending feature.

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

    [..]
    *** WakeUp pin configuration ***
    ================================
    [..]
      (+) WakeUp pins are used to wakeup the system from Standby mode or
          Shutdown mode. WakeUp pins polarity can be set to configure event
          detection on high level (rising edge) or low level (falling edge).

    *** Low Power mode configuration ***
    =====================================
    [..]
      The devices feature 7 low-power modes:
      (+) Low-power run mode: core and peripherals are running at low frequency.
          Regulator is in low power mode.
      (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running,
          regulator is main mode.
      (+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running
          and regulator in low power mode.
      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is
           main mode.
      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator
          off, low power regulator on.
      (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is
          disable.
      (+) Shutdown mode: all clocks are stopped except LSE, regulator is
          disable.

   *** Low-power run mode ***
   ==========================
    [..]
      (+) Entry: (from main run mode)
          (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after
               having decreased the system clock below 2 MHz.
      (+) Exit:
          (++) clear LPR bit then wait for REGLPF bit to be reset with
               HAL_PWREx_DisableLowPowerRunMode() API. Only then can the
               system clock frequency be increased above 2 MHz.

   *** Sleep mode / Low-power sleep mode ***
   =========================================
    [..]
      (+) Entry:
          The Sleep & Low-power Sleep modes are entered through
          HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator
          is forced to low-power mode and if exit is interrupt or event
          triggered.
          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
          (++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low
               power mode). In this case, the system clock frequency must have
               been decreased below 2 MHz beforehand.
          (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction
      (+) WFI Exit:
        (++) Any interrupt enabled in nested vectored interrupt controller (NVIC)
      (+) WFE Exit:
        (++) Any wakeup event if cortex is configured with SEVONPEND = 0
        (++) Interrupt even when disabled in NVIC if cortex is configured with
             SEVONPEND = 1
    [..]  When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event,
          the MCU is in Low-power Run mode.

   *** Stop 0 & Stop 1 modes ***
   =============================
    [..]
      (+) Entry:
          The Stop modes are entered through the following APIs:
          (++) HAL_PWR_EnterSTOPMode() with following settings:
              (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode.
              (+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode.
      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
      (+) WFI Exit:
          (++) Any EXTI line (internal or external) configured in interrupt mode
               with corresponding interrupt enable in NVIC
      (+) WFE Exit:
          (++) Any EXTI line (internal or external) configured in event mode if
               cortex is configured with SEVONPEND = 0
          (++) Any EXTI line configured in interrupt mode (even if the
               corresponding EXTI Interrupt vector is disabled in the NVIC) if
               cortex is configured with SEVONPEND = 0. The interrupt source can
               be external interrupts or peripherals with wakeup capability.
    [..]  When exiting Stop, the MCU is either in Run mode or in Low-power Run mode
          depending on the LPR bit setting.

   *** Standby mode ***
   ====================
    [..] In Standby mode, it is possible to keep backup SRAM content (defined as
         full SRAM) keeping low power regulator on. This is achievable by setting
         Ram retention bit calling HAL_PWREx_EnableSRAMRetention API. This increases
         power consumption.
         Its also possible to define I/O states using APIs:
         HAL_PWREx_EnableGPIOPullUp, HAL_PWREx_EnableGPIOPullDown &
         HAL_PWREx_EnablePullUpPullDownConfig
      (+) Entry:
          (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by
               setting SLEEPDEEP in Cortex control register.
      (+) Exit:
          (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
               tamper event (internal & external), LSE CSS detection, reset on
               NRST pin, IWDG reset & BOR reset.
    [..] Exiting Standby generates a power reset: Cortex is reset and execute
         Reset handler vector, all registers in the Vcore domain are set to
         their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG,
         and Standby/Shutdown modes control) are not impacted.

    *** Shutdown mode ***
   ======================
    [..]
      In Shutdown mode,
        voltage regulator is disabled, all clocks are off except LSE, RRS bit is
        cleared. SRAM and registers contents are lost except for backup domain
        registers.
      (+) Entry:
          (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API,
               by setting SLEEPDEEP in Cortex control register.
      (+) Exit:
          (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
               tamper event (internal & external), LSE CSS detection, reset on
               NRST pin.
    [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute
         Reset handler vector, all registers are set to their reset value but ones
         in backup domain.

Function Documentation

void HAL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain.

Return values:
None

Definition at line 238 of file stm32g0xx_hal_pwr.c.

Referenced by HAL_RCCEx_DisableLSCO(), and HAL_RCCEx_EnableLSCO().

void HAL_PWR_DisableSEVOnPend ( void )

Disable Cortex Sev On Pending feature.

Note:
Clear SEVONPEND bit of SCR register. When this bit is clear, only enable interrupts or events can wakeup processor from WFE
Return values:
None

Definition at line 521 of file stm32g0xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disable Sleep-On-Exit Cortex feature.

Note:
Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor enters SLEEP or DEEPSLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 494 of file stm32g0xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disable the WakeUp PINx functionality.

Parameters:
WakeUpPinx Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2,PWR_WAKEUP_PIN3(*), PWR_WAKEUP_PIN4,PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
Note:
(*) availability depends on devices
Return values:
None

Definition at line 284 of file stm32g0xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain (RTC & TAMP registers, backup registers, RCC BDCR register).

Note:
After reset, the backup domain is protected against possible unwanted write accesses. All RTC & TAMP registers (backup registers included) and RCC BDCR register are concerned.
Return values:
None

Definition at line 228 of file stm32g0xx_hal_pwr.c.

Referenced by HAL_RCCEx_DisableLSCO(), and HAL_RCCEx_EnableLSCO().

void HAL_PWR_EnableSEVOnPend ( void )

Enable Cortex Sev On Pending feature.

Note:
Set SEVONPEND bit of SCR register. When this bit is set, enabled events and all interrupts, including disabled ones can wakeup processor from WFE.
Return values:
None

Definition at line 508 of file stm32g0xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Enable Sleep-On-Exit Cortex feature.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor enters SLEEP or DEEPSLEEP mode when an interruption handling is over returning to thread mode. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 480 of file stm32g0xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinPolarity )

Enable the WakeUp PINx functionality.

Parameters:
WakeUpPinPolarity Specifies which Wake-Up pin to enable. This parameter can be one of the following legacy values which set the default polarity i.e. detection on high level (rising edge):
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*), PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6 or one of the following value where the user can explicitly specify the enabled pin and the chosen polarity:
  • PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
  • PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
  • PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW (*)
  • PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
  • PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*)
  • PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
Note:
PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
(*) availability depends on devices
Return values:
None

Definition at line 262 of file stm32g0xx_hal_pwr.c.

References assert_param, IS_PWR_WAKEUP_PIN, and PWR_WUP_POLARITY_SHIFT.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enter Sleep or Low-power Sleep mode.

Note:
In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
Parameters:
Regulator Specifies the regulator state in Sleep/Low-power Sleep mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
  • PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
Note:
Low-power Sleep mode is entered from Low-power Run mode only. In case Regulator parameter is set to Low Power but MCU is in Run mode, we will first enter in Low-power Run mode. Therefore, user should take care that HCLK frequency is less than 2 MHz.
When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To switch back to Run mode, user must call HAL_PWREx_DisableLowPowerRunMode() API.
Parameters:
SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
  • PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
Note:
When WFI entry is used, tick interrupt have to be disabled if not desired as the interrupt wake up source.
Return values:
None

Definition at line 318 of file stm32g0xx_hal_pwr.c.

References assert_param, HAL_PWREx_DisableLowPowerRunMode(), HAL_PWREx_EnableLowPowerRunMode(), IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, PWR_MAINREGULATOR_ON, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enter Standby mode.

Note:
In Standby mode, the PLL, the HSI and the HSE oscillators are switched off. The voltage regulator is disabled. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. BOR is available.
The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and PullDown state. HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() disable the same. These states are effective in Standby mode only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
Sram content can be kept setting RRS through HAL_PWREx_EnableSRAMRetention()
Return values:
None

Definition at line 453 of file stm32g0xx_hal_pwr.c.

References PWR_LOWPOWERMODE_STANDBY.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enter Stop mode.

Note:
This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running on devices where only "Stop mode" is mentioned with main or low power regulator ON.
In Stop mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. SRAM and register contents are preserved. The BOR is available. The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock
When the voltage regulator operates in low power mode (Stop 1), an additional startup delay is incurred when waking up. By keeping the internal regulator ON during Stop mode (Stop 0), the consumption is higher although the startup time is reduced.
Parameters:
Regulator Specifies the regulator state in Stop mode This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
  • PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
STOPEntry Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
  • PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
Return values:
None

Definition at line 398 of file stm32g0xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, PWR_LOWPOWERMODE_STOP0, PWR_LOWPOWERMODE_STOP1, PWR_MAINREGULATOR_ON, and PWR_STOPENTRY_WFI.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Extended Private Defines

Defines

#define | PVD_MODE_IT 0x00010000U
#define | PVD_MODE_EVT 0x00020000U
#define | PVD_RISING_EDGE 0x00000001U
#define | PVD_FALLING_EDGE 0x00000002U

Define Documentation

#define PVD_FALLING_EDGE 0x00000002U

Mask for falling edge set as PVD trigger

Definition at line 53 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVD().

#define PVD_MODE_EVT 0x00020000U

Mask for event yielded by PVD threshold crossing

Definition at line 49 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVD().

#define PVD_MODE_IT 0x00010000U

Mask for interruption yielded by PVD threshold crossing

Definition at line 47 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVD().

#define PVD_RISING_EDGE 0x00000001U

Mask for rising edge set as PVD trigger

Definition at line 51 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVD().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWREx Flag Setting Time Out Value

Defines
PWREx Flag Setting Time Out Value
PWR Extended Private Defines

Defines

#define | PWR_REGLPF_SETTING_DELAY_6_US 6u
#define | PWR_VOSF_SETTING_DELAY_6_US 6u

Define Documentation

#define PWR_REGLPF_SETTING_DELAY_6_US 6u

REGLPF should rise in about 5 us plus 2 APB clock. Taking in account max Sysclk at 2 MHz, and rounded to upper value

Definition at line 63 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableLowPowerRunMode().

#define PWR_VOSF_SETTING_DELAY_6_US 6u

VOSF should rise in about 5 us plus 2 APB clock. Taking in account max Sysclk at 16 MHz, and rounded to upper value

Definition at line 67 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ControlVoltageScaling().

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWREx Gpio Pin Number

Defines
PWREx Gpio Pin Number
PWR Extended Private Defines

Defines

#define PWR_GPIO_PIN_NB 16u

Define Documentation

#define PWR_GPIO_PIN_NB 16u

Number of gpio pin in bank

Definition at line 77 of file stm32g0xx_hal_pwr_ex.c.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR PVM Mode Mask

Defines
PWR PVM Mode Mask
PWR Extended Private Defines

Defines

#define | PVM_MODE_IT ((uint32_t)0x00010000)
#define | PVM_MODE_EVT ((uint32_t)0x00020000)
#define | PVM_RISING_EDGE ((uint32_t)0x00000001)
#define | PVM_FALLING_EDGE ((uint32_t)0x00000002)

Define Documentation

#define PVM_FALLING_EDGE ((uint32_t)0x00000002)

Mask for falling edge set as PVM trigger

Definition at line 487 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_MODE_EVT ((uint32_t)0x00020000)

Mask for event yielded by PVM threshold crossing

Definition at line 485 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_MODE_IT ((uint32_t)0x00010000)

Mask for interruption yielded by PVM threshold crossing

Definition at line 484 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_RISING_EDGE ((uint32_t)0x00000001)

Mask for rising edge set as PVM trigger

Definition at line 486 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR_PVMTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVMTypeDef Struct Reference
PWR Extended Exported Types

PWR PVM configuration structure definition. More...

#include <stm32g0xx_hal_pwr_ex.h>

Data Fields

uint32_t | PVMType
uint32_t | Mode

Detailed Description

PWR PVM configuration structure definition.

Definition at line 48 of file stm32g0xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWR_PVMTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVM interrupt and event mode.

Definition at line 54 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

uint32_t PWR_PVMTypeDef::PVMType

PVMType: Specifies which voltage is monitored and against which threshold. This parameter can be a value of Peripheral Voltage Monitoring type.

  • PWR_PVM_USB Peripheral Voltage Monitoring USB enable

Definition at line 50 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_pwr_ex.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Extended Exported Types

PWR PVD configuration structure definition. More...

#include <stm32g0xx_hal_pwr_ex.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 63 of file stm32g0xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVD interrupt and event mode.

Definition at line 69 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value or a combination of Programmable Voltage Detection levels.

Definition at line 65 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_pwr_ex.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Programmable Voltage Detection levels

Defines
Programmable Voltage Detection levels
PWR Extended Exported Constants

Defines

#define | PWR_PVDLEVEL_RISING_0 (0x00000000u)
#define | PWR_PVDLEVEL_RISING_1 (PWR_CR2_PVDRT_0)
#define | PWR_PVDLEVEL_RISING_2 (PWR_CR2_PVDRT_1)
#define | PWR_PVDLEVEL_RISING_3 (PWR_CR2_PVDRT_0 | PWR_CR2_PVDRT_1)
#define | PWR_PVDLEVEL_RISING_4 (PWR_CR2_PVDRT_2)
#define | PWR_PVDLEVEL_RISING_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0)
#define | PWR_PVDLEVEL_RISING_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1)
#define | PWR_PVDLEVEL_FALLING_0 (0x00000000u)
#define | PWR_PVDLEVEL_FALLING_1 (PWR_CR2_PVDFT_0)
#define | PWR_PVDLEVEL_FALLING_2 (PWR_CR2_PVDFT_1)
#define | PWR_PVDLEVEL_FALLING_3 (PWR_CR2_PVDFT_0 | PWR_CR2_PVDFT_1)
#define | PWR_PVDLEVEL_FALLING_4 (PWR_CR2_PVDFT_2)
#define | PWR_PVDLEVEL_FALLING_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0)
#define | PWR_PVDLEVEL_FALLING_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1)
#define | PWR_PVDLEVEL_0 (PWR_PVDLEVEL_RISING_0 | PWR_PVDLEVEL_FALLING_0)
#define | PWR_PVDLEVEL_1 (PWR_PVDLEVEL_RISING_1 | PWR_PVDLEVEL_FALLING_1)
#define | PWR_PVDLEVEL_2 (PWR_PVDLEVEL_RISING_2 | PWR_PVDLEVEL_FALLING_2)
#define | PWR_PVDLEVEL_3 (PWR_PVDLEVEL_RISING_3 | PWR_PVDLEVEL_FALLING_3)
#define | PWR_PVDLEVEL_4 (PWR_PVDLEVEL_RISING_4 | PWR_PVDLEVEL_FALLING_4)
#define | PWR_PVDLEVEL_5 (PWR_PVDLEVEL_RISING_5 | PWR_PVDLEVEL_FALLING_5)
#define | PWR_PVDLEVEL_6 (PWR_PVDLEVEL_RISING_6 | PWR_PVDLEVEL_FALLING_6)
#define | PWR_PVDLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)

Detailed Description

Note:
see datasheet for selection voltage value

Define Documentation

#define PWR_PVDLEVEL_0 (PWR_PVDLEVEL_RISING_0 | PWR_PVDLEVEL_FALLING_0)

same PVD threshold level 0 on rising & falling

Definition at line 100 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_1 (PWR_PVDLEVEL_RISING_1 | PWR_PVDLEVEL_FALLING_1)

same PVD threshold level 1 on rising & falling

Definition at line 101 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_2 (PWR_PVDLEVEL_RISING_2 | PWR_PVDLEVEL_FALLING_2)

same PVD threshold level 2 on rising & falling

Definition at line 102 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_3 (PWR_PVDLEVEL_RISING_3 | PWR_PVDLEVEL_FALLING_3)

same PVD threshold level 3 on rising & falling

Definition at line 103 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_4 (PWR_PVDLEVEL_RISING_4 | PWR_PVDLEVEL_FALLING_4)

same PVD threshold level 4 on rising & falling

Definition at line 104 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_5 (PWR_PVDLEVEL_RISING_5 | PWR_PVDLEVEL_FALLING_5)

same PVD threshold level 5 on rising & falling

Definition at line 105 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_6 (PWR_PVDLEVEL_RISING_6 | PWR_PVDLEVEL_FALLING_6)

same PVD threshold level 6 on rising & falling

Definition at line 106 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)

External input analog voltage (compared internally to VREFINT)

Definition at line 107 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_FALLING_0 (0x00000000u)

PVD threshold level 0 for falling detection

Definition at line 93 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_FALLING_1 (PWR_CR2_PVDFT_0)

PVD threshold level 1 for falling detection

Definition at line 94 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_FALLING_2 (PWR_CR2_PVDFT_1)

PVD threshold level 2 for falling detection

Definition at line 95 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_FALLING_3 (PWR_CR2_PVDFT_0 | PWR_CR2_PVDFT_1)

PVD threshold level 3 for falling detection

Definition at line 96 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_FALLING_4 (PWR_CR2_PVDFT_2)

PVD threshold level 4 for falling detection

Definition at line 97 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_FALLING_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0)

PVD threshold level 5 for falling detection

Definition at line 98 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_FALLING_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1)

PVD threshold level 6 for falling detection

Definition at line 99 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_RISING_0 (0x00000000u)

PVD threshold level 0 for rising detection

Definition at line 86 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_RISING_1 (PWR_CR2_PVDRT_0)

PVD threshold level 1 for rising detection

Definition at line 87 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_RISING_2 (PWR_CR2_PVDRT_1)

PVD threshold level 2 for rising detection

Definition at line 88 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_RISING_3 (PWR_CR2_PVDRT_0 | PWR_CR2_PVDRT_1)

PVD threshold level 3 for rising detection

Definition at line 89 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_RISING_4 (PWR_CR2_PVDRT_2)

PVD threshold level 4 for rising detection

Definition at line 90 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_RISING_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0)

PVD threshold level 5 for rising detection

Definition at line 91 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVDLEVEL_RISING_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1)

PVD threshold level 6 for rising detection

Definition at line 92 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: PWR PVD interrupt and event mode

Defines
PWR PVD interrupt and event mode
PWR Extended Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL (0x00000000u)
#define | PWR_PVD_MODE_IT_RISING (0x00010001u)
#define | PWR_PVD_MODE_IT_FALLING (0x00010002u)
#define | PWR_PVD_MODE_IT_RISING_FALLING (0x00010003u)
#define | PWR_PVD_MODE_EVENT_RISING (0x00020001u)
#define | PWR_PVD_MODE_EVENT_FALLING (0x00020002u)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003u)

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING (0x00020002u)

Event Mode with Falling edge trigger detection

Definition at line 120 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_EVENT_RISING (0x00020001u)

Event Mode with Rising edge trigger detection

Definition at line 119 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003u)

Event Mode with Rising/Falling edge trigger detection

Definition at line 121 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_IT_FALLING (0x00010002u)

External Interrupt Mode with Falling edge trigger detection

Definition at line 117 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_IT_RISING (0x00010001u)

External Interrupt Mode with Rising edge trigger detection

Definition at line 116 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003u)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 118 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVD_MODE_NORMAL (0x00000000u)

basic mode is used

Definition at line 115 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: PWR PVD external interrupt line

Defines
PWR PVD external interrupt line
PWR Extended Exported Constants

Defines

#define PWR_EXTI_LINE_PVD (EXTI_IMR1_IM16)

Define Documentation

#define PWR_EXTI_LINE_PVD (EXTI_IMR1_IM16)

External interrupt line 16 connected to PVD

Definition at line 129 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: PWR PVD event line

Defines
PWR PVD event line
PWR Extended Exported Constants

Defines

#define PWR_EVENT_LINE_PVD (EXTI_EMR1_EM16)

Define Documentation

#define PWR_EVENT_LINE_PVD (EXTI_EMR1_EM16)

Event line 16 connected to PVD

Definition at line 137 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: Peripheral Voltage Monitoring type

Defines
Peripheral Voltage Monitoring type
PWR Extended Exported Constants

Defines

#define PWR_PVM_USB PWR_CR2_PVMEN_USB

Define Documentation

#define PWR_PVM_USB PWR_CR2_PVMEN_USB

Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2)

Definition at line 147 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVMUSB(), and HAL_PWREx_EnablePVMUSB().

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STM32G0C1xx HAL User Manual: PWR PVM interrupt and event mode

Defines
PWR PVM interrupt and event mode
PWR Extended Exported Constants

Defines

#define | PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Define Documentation

#define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002)

Event Mode with Falling edge trigger detection

Definition at line 159 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001)

Event Mode with Rising edge trigger detection

Definition at line 158 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Event Mode with Rising/Falling edge trigger detection

Definition at line 160 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002)

External Interrupt Mode with Falling edge trigger detection

Definition at line 156 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001)

External Interrupt Mode with Rising edge trigger detection

Definition at line 155 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 157 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000)

basic mode is used

Definition at line 154 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: PWR PVM external interrupt line

Defines
PWR PVM external interrupt line
PWR Extended Exported Constants

Defines

#define PWR_EXTI_LINE_PVM (EXTI_IMR2_IM34)

Define Documentation

#define PWR_EXTI_LINE_PVM (EXTI_IMR2_IM34)

External interrupt line 34 connected to PVM

Definition at line 167 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: PWR PVM event line

Defines
PWR PVM event line
PWR Extended Exported Constants

Defines

#define PWR_EVENT_LINE_PVM (EXTI_EMR2_EM34)

Define Documentation

#define PWR_EVENT_LINE_PVM (EXTI_EMR2_EM34)

Event line 34 connected to PVM

Definition at line 175 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: PWR battery charging resistor selection

Defines
PWR battery charging resistor selection
PWR Extended Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000u)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS

Define Documentation

#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS

VBAT charging through a 1.5 kOhms resistor

Definition at line 185 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000u)

VBAT charging through a 5 kOhms resistor

Definition at line 184 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: GPIO bit position

Defines
GPIO bit position
PWR Extended Exported Constants

for I/O pull up/down setting in standby/shutdown mode More...

Defines

#define | PWR_GPIO_BIT_0 PWR_PUCRB_PU0
#define | PWR_GPIO_BIT_1 PWR_PUCRB_PU1
#define | PWR_GPIO_BIT_2 PWR_PUCRB_PU2
#define | PWR_GPIO_BIT_3 PWR_PUCRB_PU3
#define | PWR_GPIO_BIT_4 PWR_PUCRB_PU4
#define | PWR_GPIO_BIT_5 PWR_PUCRB_PU5
#define | PWR_GPIO_BIT_6 PWR_PUCRB_PU6
#define | PWR_GPIO_BIT_7 PWR_PUCRB_PU7
#define | PWR_GPIO_BIT_8 PWR_PUCRB_PU8
#define | PWR_GPIO_BIT_9 PWR_PUCRB_PU9
#define | PWR_GPIO_BIT_10 PWR_PUCRB_PU10
#define | PWR_GPIO_BIT_11 PWR_PUCRB_PU11
#define | PWR_GPIO_BIT_12 PWR_PUCRB_PU12
#define | PWR_GPIO_BIT_13 PWR_PUCRB_PU13
#define | PWR_GPIO_BIT_14 PWR_PUCRB_PU14
#define | PWR_GPIO_BIT_15 PWR_PUCRB_PU15

Detailed Description

for I/O pull up/down setting in standby/shutdown mode

Define Documentation

#define PWR_GPIO_BIT_0 PWR_PUCRB_PU0

GPIO port I/O pin 0

Definition at line 194 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_1 PWR_PUCRB_PU1

GPIO port I/O pin 1

Definition at line 195 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_10 PWR_PUCRB_PU10

GPIO port I/O pin 10

Definition at line 204 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_11 PWR_PUCRB_PU11

GPIO port I/O pin 11

Definition at line 205 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_12 PWR_PUCRB_PU12

GPIO port I/O pin 12

Definition at line 206 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_13 PWR_PUCRB_PU13

GPIO port I/O pin 13

Definition at line 207 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_14 PWR_PUCRB_PU14

GPIO port I/O pin 14

Definition at line 208 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_15 PWR_PUCRB_PU15

GPIO port I/O pin 15

Definition at line 209 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_2 PWR_PUCRB_PU2

GPIO port I/O pin 2

Definition at line 196 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_3 PWR_PUCRB_PU3

GPIO port I/O pin 3

Definition at line 197 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_4 PWR_PUCRB_PU4

GPIO port I/O pin 4

Definition at line 198 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_5 PWR_PUCRB_PU5

GPIO port I/O pin 5

Definition at line 199 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_6 PWR_PUCRB_PU6

GPIO port I/O pin 6

Definition at line 200 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_7 PWR_PUCRB_PU7

GPIO port I/O pin 7

Definition at line 201 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_8 PWR_PUCRB_PU8

GPIO port I/O pin 8

Definition at line 202 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_9 PWR_PUCRB_PU9

GPIO port I/O pin 9

Definition at line 203 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: GPIO Port

Defines
GPIO Port
PWR Extended Exported Constants

Defines

#define | PWR_GPIO_A (0x00000000u)
#define | PWR_GPIO_B (0x00000001u)
#define | PWR_GPIO_C (0x00000002u)
#define | PWR_GPIO_D (0x00000003u)
#define | PWR_GPIO_E (0x00000004u)
#define | PWR_GPIO_F (0x00000005u)

Define Documentation

#define PWR_GPIO_A (0x00000000u)

GPIO port A

Definition at line 217 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_B (0x00000001u)

GPIO port B

Definition at line 218 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_C (0x00000002u)

GPIO port C

Definition at line 219 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_D (0x00000003u)

GPIO port D

Definition at line 220 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_E (0x00000004u)

GPIO port E

Definition at line 222 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_F (0x00000005u)

GPIO port F

Definition at line 224 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

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STM32G0C1xx HAL User Manual: Flash Power Down modes

Defines
Flash Power Down modes
PWR Extended Exported Constants

Defines

#define | PWR_FLASHPD_LPRUN PWR_CR1_FPD_LPRUN
#define | PWR_FLASHPD_LPSLEEP PWR_CR1_FPD_LPSLP
#define | PWR_FLASHPD_STOP PWR_CR1_FPD_STOP

Define Documentation

#define PWR_FLASHPD_LPRUN PWR_CR1_FPD_LPRUN

Enable Flash power down in low power run mode

Definition at line 232 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_FLASHPD_LPSLEEP PWR_CR1_FPD_LPSLP

Enable Flash power down in low power sleep mode

Definition at line 233 of file stm32g0xx_hal_pwr_ex.h.

#define PWR_FLASHPD_STOP PWR_CR1_FPD_STOP

Enable Flash power down in stop mode

Definition at line 234 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: PWR Regulator voltage scale

Defines
PWR Regulator voltage scale
PWR Extended Exported Constants

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Define Documentation

#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0

Voltage scaling range 1

Definition at line 242 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Voltage scaling range 2

Definition at line 243 of file stm32g0xx_hal_pwr_ex.h.

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STM32G0C1xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
PWR Extended Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnablePORMonitorSampling (void)
Enable POR Monitor sampling mode.
void | HAL_PWREx_DisablePORMonitorSampling (void)
Disable POR Monitor sampling mode.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the Power Voltage Detector (PVD).
void | HAL_PWREx_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWREx_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnableVddIO2 (void)
Enable VDDIO2 supply.
void | HAL_PWREx_DisableVddIO2 (void)
Disable VDDIO2 supply.
void | HAL_PWREx_EnablePVMUSB (void)
Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)
void | HAL_PWREx_DisablePVMUSB (void)
Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAMRetention (void)
Enable SRAM content retention in Standby mode.
void | HAL_PWREx_DisableSRAMRetention (void)
Disable SRAM content retention in Standby mode.
void | HAL_PWREx_EnableFlashPowerDown (uint32_t PowerMode)
Enable Flash Power Down.
void | HAL_PWREx_DisableFlashPowerDown (uint32_t PowerMode)
Disable Flash Power Down.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main regulator output voltage.
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWREx_PVD_PVM_Rising_Callback (void)
PWR PVD interrupt rising callback.
__weak void | HAL_PWREx_PVD_PVM_Falling_Callback (void)
PWR PVD interrupt Falling callback.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
  ##### Extended Peripheral Initialization and de-initialization functions #####
 ===============================================================================
    [..]
     *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PVDRT[2:0] & PVDFT[2:0] bits in
          PWR CR2 register).
      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line 16 and can generate an interrupt if enabled.
      (+) The PVD is stopped in Standby & Shutdown mode.

     *** PVM configuration ***
    =========================
    [..]

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configure the Power Voltage Detector (PVD).

Parameters:
sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD configuration information: threshold levels, operating mode.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage thresholds corresponding to each detection level.
User should take care that rising threshold is higher than falling one in order to avoid having always PVDO output set.
Return values:
HAL_OK

Definition at line 187 of file stm32g0xx_hal_pwr_ex.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

HAL_StatusTypeDef HAL_PWREx_ConfigPVM ( PWR_PVMTypeDef * sConfigPVM )

Configure the Peripheral Voltage Monitoring (PVM).

Parameters:
sConfigPVM,: pointer to a PWR_PVMTypeDef structure that contains the PVM configuration information.
Note:
The API configures a single PVM according to the information contained in the input structure. To configure several PVMs, the API must be singly called for each PVM used.
Refer to the electrical characteristics of your device datasheet for more details about the voltage thresholds corresponding to each detection level and to each monitored supply.
Return values:
HAL status

Definition at line 325 of file stm32g0xx_hal_pwr_ex.c.

References __HAL_PWR_PVM_EXTI_DISABLE_EVENT, __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM_EXTI_DISABLE_IT, __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM_EXTI_ENABLE_EVENT, __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM_EXTI_ENABLE_IT, __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVM_MODE, IS_PWR_PVM_TYPE, PWR_PVMTypeDef::Mode, PVM_FALLING_EDGE, PVM_MODE_EVT, PVM_MODE_IT, PVM_RISING_EDGE, PWR_PVMTypeDef::PVMType, and PWR_PVM_USB.

HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling ( uint32_t VoltageScaling )

Configure the main regulator output voltage.

Parameters:
VoltageScaling specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz.
Note:
When moving from Range 1 to Range 2, the system frequency must be decreased to a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API. When moving from Range 2 to Range 1, the system frequency can be increased to a value up to 64 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
When moving from Range 2 to Range 1, the API waits for VOSF flag to be cleared before returning the status. If the flag is not cleared within 6 microseconds, HAL_TIMEOUT status is reported.
Return values:
HAL Status

Definition at line 762 of file stm32g0xx_hal_pwr_ex.c.

References assert_param, IS_PWR_VOLTAGE_SCALING_RANGE, PWR_REGULATOR_VOLTAGE_SCALE1, and PWR_VOSF_SETTING_DELAY_6_US.

void HAL_PWREx_DisableBatteryCharging ( void )

Disable battery charging.

Return values:
None

Definition at line 146 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_DisableFlashPowerDown ( uint32_t PowerMode )

Disable Flash Power Down.

Note:
This API allows to disable flash power down capabilities in low power run, low power sleep and stop modes.
Parameters:
PowerMode this can be a combination of following values:
  • PWR_FLASHPD_LPRUN
  • PWR_FLASHPD_LPSLEEP
  • PWR_FLASHPD_STOP
Return values:
None

Definition at line 722 of file stm32g0xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_FLASH_POWERDOWN.

HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-down state in Standby and Shutdown modes.

Note:
Reset the relevant PDy bit of PWR_PDCRx register used to configure the I/O in pull-down state in Standby and Shutdown modes.
Parameters:
GPIO | Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F to select the GPIO peripheral.
GPIONumber | Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less I/O pins are available) or the logical OR of several of them to reset several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 600 of file stm32g0xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_13, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, and PWR_GPIO_F.

HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-up state in Standby mode and Shutdown modes.

Note:
Reset the relevant PUy bit of PWR_PUCRx register used to configure the I/O in pull-up state in Standby and Shutdown modes.
Parameters:
GPIO | Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F to select the GPIO peripheral.
GPIONumber | Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less I/O pins are available) or the logical OR of several of them to reset several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 476 of file stm32g0xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_14, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, and PWR_GPIO_F.

void HAL_PWREx_DisableInternalWakeUpLine ( void )

Disable Internal Wake-up Line.

Return values:
None

Definition at line 390 of file stm32g0xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode ( void )

Exit Low-power Run mode.

Note:
Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode returns HAL_TIMEOUT status). The system clock frequency can then be increased above 2 MHz.
Return values:
HAL Status

Definition at line 818 of file stm32g0xx_hal_pwr_ex.c.

References PWR_REGLPF_SETTING_DELAY_6_US.

Referenced by HAL_PWR_EnterSLEEPMode().

void HAL_PWREx_DisablePORMonitorSampling ( void )

Disable POR Monitor sampling mode.

Return values:
None

Definition at line 169 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_DisablePullUpPullDownConfig ( void )

Disable pull-up and pull-down configuration.

Note:
When APC bit is cleared, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
Return values:
None

Definition at line 664 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_DisablePVD ( void )

Disable the Power Voltage Detector (PVD).

Return values:
None

Definition at line 243 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_DisablePVMUSB ( void )

Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)

Return values:
None

Definition at line 306 of file stm32g0xx_hal_pwr_ex.c.

References PWR_PVM_USB.

void HAL_PWREx_DisableSRAMRetention ( void )

Disable SRAM content retention in Standby mode.

Note:
When RRS bit is reset, SRAM is powered off in Standby mode and its content is lost.
Return values:
None

Definition at line 688 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_DisableVddIO2 ( void )

Disable VDDIO2 supply.

Return values:
None

Definition at line 286 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_DisableVddUSB ( void )

Disable VDDUSB supply.

Return values:
None

Definition at line 264 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_EnableBatteryCharging ( uint32_t ResistorSelection )

Enable battery charging.

Note:
When VDD is present, charge the external battery on VBAT through an internal resistor.
Parameters:
ResistorSelection specifies the resistor impedance. This parameter can be one of the following values:
  • PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
Return values:
None

Definition at line 131 of file stm32g0xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_BATTERY_RESISTOR_SELECT.

void HAL_PWREx_EnableFlashPowerDown ( uint32_t PowerMode )

Enable Flash Power Down.

Note:
This API allows to enable flash power down capabilities in low power run, low power sleep and stop modes.
Parameters:
PowerMode this can be a combination of following values:
  • PWR_FLASHPD_LPRUN
  • PWR_FLASHPD_LPSLEEP
  • PWR_FLASHPD_STOP
Return values:
None

Definition at line 704 of file stm32g0xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_FLASH_POWERDOWN.

HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-down state in Standby and Shutdown modes.

Note:
Set the relevant PDy bit of PWR_PDCRx register to configure the I/O in pull-down state in Standby and Shutdown modes.
This state is effective in Standby and Shutdown modes only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
The configuration is lost when exiting the Shutdown mode due to the power-on reset, maintained when exiting the Standby mode.
To avoid any conflict at Standby and Shutdown modes exits, the corresponding PUy bit of PWR_PUCRx register is cleared unless it is reserved.
Parameters:
GPIO | Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F to select the GPIO peripheral.
GPIONumber | Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less I/O pins are available) or the logical OR of several of them to set several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 538 of file stm32g0xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_13, PWR_GPIO_BIT_14, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, and PWR_GPIO_F.

HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-up state in Standby and Shutdown modes.

Note:
Set the relevant PUy bit of PWR_PUCRx register to configure the I/O in pull-up state in Standby and Shutdown modes.
This state is effective in Standby and Shutdown modes only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
The configuration is lost when exiting the Shutdown mode due to the power-on reset, maintained when exiting the Standby mode.
To avoid any conflict at Standby and Shutdown modes exits, the corresponding PDy bit of PWR_PDCRx register is cleared unless it is reserved.
Parameters:
GPIO | Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F to select the GPIO peripheral.
GPIONumber | Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less I/O pins are available) or the logical OR of several of them to set several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 414 of file stm32g0xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_13, PWR_GPIO_BIT_14, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, and PWR_GPIO_F.

void HAL_PWREx_EnableInternalWakeUpLine ( void )

Enable Internal Wake-up Line.

Return values:
None

Definition at line 381 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_EnableLowPowerRunMode ( void )

Enter Low-power Run mode.

Note:
System clock frequency has to be decreased below 2 MHz before entering low power run mode
In Low-power Run mode, all I/O pins keep the same state as in Run mode.
Return values:
None

Definition at line 803 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWR_EnterSLEEPMode().

void HAL_PWREx_EnablePORMonitorSampling ( void )

Enable POR Monitor sampling mode.

Note:
When entering ultra low power modes (standby, shutdown) this feature can be enabled to reduce further consumption: Power On Reset monitor is then set in sampling mode, and no more in always on mode.
Return values:
None

Definition at line 159 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_EnablePullUpPullDownConfig ( void )

Enable pull-up and pull-down configuration.

Note:
When APC bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() APIs ensure there is no conflict when setting PUy or PDy bit.
Return values:
None

Definition at line 653 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_EnablePVD ( void )

Enable the Power Voltage Detector (PVD).

Return values:
None

Definition at line 233 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_EnablePVMUSB ( void )

Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)

Return values:
None

Definition at line 297 of file stm32g0xx_hal_pwr_ex.c.

References PWR_PVM_USB.

void HAL_PWREx_EnableSRAMRetention ( void )

Enable SRAM content retention in Standby mode.

Note:
When RRS bit is set, SRAM is powered by the low-power regulator in Standby mode and its content is kept.
Return values:
None

Definition at line 676 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_EnableVddIO2 ( void )

Enable VDDIO2 supply.

Note:
Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
Return values:
None

Definition at line 276 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_EnableVddUSB ( void )

Enable VDDUSB supply.

Note:
Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
Return values:
None

Definition at line 255 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_EnterSHUTDOWNMode ( void )

Enter Shutdown mode.

Note:
In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched off. The voltage regulator is disabled and Vcore domain is powered off. SRAM and registers contents are lost except for registers in the Backup domain. The BOR is not available.
The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and PullDown state. HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() disable the same. These states are effective in Standby mode only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
Return values:
None
None

Definition at line 860 of file stm32g0xx_hal_pwr_ex.c.

References PWR_LOWPOWERMODE_SHUTDOWN.

uint32_t HAL_PWREx_GetVoltageRange ( void )

Return Voltage Scaling Range.

Return values:
VOS bit field:
  • PWR_REGULATOR_VOLTAGE_SCALE1
  • PWR_REGULATOR_VOLTAGE_SCALE2

Definition at line 736 of file stm32g0xx_hal_pwr_ex.c.

void HAL_PWREx_PVD_PVM_Falling_Callback ( void )

PWR PVD interrupt Falling callback.

Return values:
None

Definition at line 942 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_PVD_PVM_IRQHandler ( void )

This function handles the PWR PVD interrupt request.

Note:
This API should be called under the PVD_IRQHandler().
Return values:
None

Definition at line 884 of file stm32g0xx_hal_pwr_ex.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG, __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG, __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG, __HAL_PWR_PVD_EXTI_GET_RISING_FLAG, __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG, __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG, __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG, __HAL_PWR_PVM_EXTI_GET_RISING_FLAG, HAL_PWREx_PVD_PVM_Falling_Callback(), and HAL_PWREx_PVD_PVM_Rising_Callback().

void HAL_PWREx_PVD_PVM_Rising_Callback ( void )

PWR PVD interrupt rising callback.

Return values:
None

Definition at line 931 of file stm32g0xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Extended Exported Macros

Defines
PWR Extended Exported Macros
PWREx

Defines

#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Enable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Disable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() (EXTI->RPR1 & PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt Rising flag is set.
#define | __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() (EXTI->FPR1 & PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt Falling flag is set.
#define | __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt Rising flag.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt Falling flag.
#define | __HAL_PWR_PVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)
Enable the PVM Extended Interrupt Line.
#define | __HAL_PWR_PVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)
Disable the PVM Extended Interrupt Line.
#define | __HAL_PWR_PVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)
Enable the PVM Event Line.
#define | __HAL_PWR_PVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)
Disable the PVM Event Line.
#define | __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)
Enable the PVM Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)
Disable the PVM Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)
Enable the PVM Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)
Disable the PVM Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVM Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM_EXTI_GET_RISING_FLAG() (EXTI->RPR2 & PWR_EXTI_LINE_PVM)
Check whether or not the PVM EXTI interrupt Rising flag is set.
#define | __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() (EXTI->FPR2 & PWR_EXTI_LINE_PVM)
Check whether or not the PVM EXTI interrupt Falling flag is set.
#define | __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM)
Clear the PVM EXTI interrupt Rising flag.
#define | __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM)
Clear the PVM EXTI interrupt Falling flag.

Define Documentation

#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG ( ) WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD)

Clear the PVD EXTI interrupt Falling flag.

Return values:
None

Definition at line 370 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG ( ) WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD)

Clear the PVD EXTI interrupt Rising flag.

Return values:
None

Definition at line 364 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)

Disable the PVD Event Line.

Return values:
None

Definition at line 296 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 320 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Line.

Return values:
None

Definition at line 284 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 308 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0U)

Disable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 336 of file stm32g0xx_hal_pwr_ex.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)

Enable the PVD Event Line.

Return values:
None

Definition at line 290 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 314 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Line.

Return values:
None

Definition at line 278 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 302 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                   \
    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0U)

Enable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 326 of file stm32g0xx_hal_pwr_ex.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 346 of file stm32g0xx_hal_pwr_ex.h.

#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG ( ) (EXTI->FPR1 & PWR_EXTI_LINE_PVD)

Check whether or not the PVD EXTI interrupt Falling flag is set.

Return values:
EXTI PVD Line Status.

Definition at line 358 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG ( ) (EXTI->RPR1 & PWR_EXTI_LINE_PVD)

Check whether or not the PVD EXTI interrupt Rising flag is set.

Return values:
EXTI PVD Line Status.

Definition at line 352 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG ( ) WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM)

Clear the PVM EXTI interrupt Falling flag.

Return values:
None

Definition at line 470 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG ( ) WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM)

Clear the PVM EXTI interrupt Rising flag.

Return values:
None

Definition at line 464 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)

Disable the PVM Event Line.

Return values:
None

Definition at line 396 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)

Disable the PVM Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 420 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)

Disable the PVM Extended Interrupt Line.

Return values:
None

Definition at line 384 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)

Disable the PVM Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 408 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0U)

Disable the PVM Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 436 of file stm32g0xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)

Enable the PVM Event Line.

Return values:
None

Definition at line 390 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)

Enable the PVM Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 414 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)

Enable the PVM Extended Interrupt Line.

Return values:
None

Definition at line 378 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)

Enable the PVM Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 402 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                   \
    __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0U)

Enable the PVM Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 426 of file stm32g0xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 446 of file stm32g0xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG ( ) (EXTI->FPR2 & PWR_EXTI_LINE_PVM)

Check whether or not the PVM EXTI interrupt Falling flag is set.

Return values:
EXTI PVM Line Status.

Definition at line 458 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM_EXTI_GET_RISING_FLAG ( ) (EXTI->RPR2 & PWR_EXTI_LINE_PVM)

Check whether or not the PVM EXTI interrupt Rising flag is set.

Return values:
EXTI PVM Line Status.

Definition at line 452 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Extended Private Macros

Defines
PWR Extended Private Macros
PWREx

Defines

#define | IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__)
#define | IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__)
#define | IS_PWR_GPIO(__GPIO__)
#define | IS_PWR_FLASH_POWERDOWN(__MODE__)
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) & ~(PWR_CR2_PVDRT | PWR_CR2_PVDFT)) == 0x00000000u)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB)
#define | IS_PWR_PVM_MODE(MODE)

Define Documentation

#define IS_PWR_BATTERY_RESISTOR_SELECT ( __RESISTOR__ )
Value:
(((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) || \
                                                      ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5))

Definition at line 500 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableBatteryCharging().

#define IS_PWR_FLASH_POWERDOWN ( __MODE__ )
Value:
((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \
                                             (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0x00u))

Definition at line 520 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableFlashPowerDown(), and HAL_PWREx_EnableFlashPowerDown().

#define IS_PWR_GPIO ( __GPIO__ )
Value:
(((__GPIO__) == PWR_GPIO_A) || \
                                             ((__GPIO__) == PWR_GPIO_B) || \
                                             ((__GPIO__) == PWR_GPIO_C) || \
                                             ((__GPIO__) == PWR_GPIO_D) || \
                                             ((__GPIO__) == PWR_GPIO_E) || \
                                             ((__GPIO__) == PWR_GPIO_F))

Definition at line 506 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define IS_PWR_GPIO_BIT_NUMBER ( __BIT_NUMBER__ )
Value:
((((__BIT_NUMBER__) & 0x0000FFFFu) != 0x00u) && \
                                                 (((__BIT_NUMBER__) & 0xFFFF0000u) == 0x00u))

Definition at line 503 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define IS_PWR_PVD_LEVEL ( LEVEL ) (((LEVEL) & ~(PWR_CR2_PVDRT | PWR_CR2_PVDFT)) == 0x00000000u)

Definition at line 527 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_NORMAL)              || \
                                                   ((MODE) == PWR_PVD_MODE_IT_RISING)           || \
                                                   ((MODE) == PWR_PVD_MODE_IT_FALLING)          || \
                                                   ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   || \
                                                   ((MODE) == PWR_PVD_MODE_EVENT_RISING)        || \
                                                   ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       || \
                                                   ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))

Definition at line 529 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVD().

#define IS_PWR_PVM_MODE ( MODE )
Value:
(((MODE) == PWR_PVM_MODE_NORMAL)              ||\
                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))

Definition at line 541 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define IS_PWR_PVM_TYPE ( TYPE ) ((TYPE) == PWR_PVM_USB)

Definition at line 539 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define IS_PWR_VOLTAGE_SCALING_RANGE ( RANGE )
Value:
(((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))

Definition at line 523 of file stm32g0xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define | PLLSOURCE_NONE (0U)
#define | CR_REG_INDEX 1U
#define | BDCR_REG_INDEX 2U
#define | CSR_REG_INDEX 3U
#define | CRRCR_REG_INDEX 4U
#define | RCC_FLAG_MASK 0x1FU
#define | RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1)

Define Documentation

#define BDCR_REG_INDEX 2U

Definition at line 44 of file stm32g0xx_hal_rcc.h.

#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */

Definition at line 77 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_DeInit().

#define CR_REG_INDEX 1U

Definition at line 43 of file stm32g0xx_hal_rcc.h.

#define CRRCR_REG_INDEX 4U

Definition at line 47 of file stm32g0xx_hal_rcc.h.

#define CSR_REG_INDEX 3U

Definition at line 45 of file stm32g0xx_hal_rcc.h.

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 69 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 75 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 70 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 71 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 72 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define PLLSOURCE_NONE (0U)

Definition at line 79 of file stm32g0xx_hal_rcc.c.

#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1)

All clocktype to configure

Definition at line 53 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_MASK 0x1FU

Definition at line 50 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOA
#define | MCO2_PIN GPIO_PIN_10
#define | RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
#define | IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U)
#define | IS_RCC_HSIDIV(__DIV__)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_PLLM_VALUE(__VALUE__)
#define | IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
#define | IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
#define | IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
#define | IS_RCC_CLOCKTYPE(__CLK__)
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) )
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_MCODIV(__DIV__)
#define | IS_RCC_MCO2SOURCE(__SOURCE__)
#define | IS_RCC_MCO2DIV(__DIV__)
#define | IS_RCC_LSE_DRIVE(__DRIVE__)

Define Documentation

#define IS_RCC_CLOCKTYPE ( __CLK__ )
Value:
((((__CLK__)\
                                      & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))

Definition at line 123 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HCLK ( __HCLK__ )
Value:
(((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
                               ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV512))

Definition at line 132 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( __HSE__ )
Value:
(((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
                              ((__HSE__) == RCC_HSE_BYPASS))

Definition at line 80 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( __HSI__ ) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))

Definition at line 86 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI48 ( __HSI48__ ) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))

Definition at line 89 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI_CALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= (uint32_t)127U)

Definition at line 92 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSIDIV ( __DIV__ )
Value:
(((__DIV__) == RCC_HSI_DIV1)  || ((__DIV__) == RCC_HSI_DIV2) || \
                                ((__DIV__) == RCC_HSI_DIV4)  || ((__DIV__) == RCC_HSI_DIV8) || \
                                ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \
                                ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128))

Definition at line 94 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( __LSE__ )
Value:
(((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
                              ((__LSE__) == RCC_LSE_BYPASS))

Definition at line 83 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE_DRIVE ( __DRIVE__ )
Value:
(((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))

Definition at line 238 of file stm32g0xx_hal_rcc.h.

#define IS_RCC_LSI ( __LSI__ ) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

Definition at line 99 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( __MCOX__ ) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) )

Definition at line 148 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO1SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI)   || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE)   || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI)    || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE)     || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK)  || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP))

Definition at line 154 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO2DIV ( __DIV__ )
Value:
(((__DIV__) == RCC_MCO2DIV_1)  || ((__DIV__) == RCC_MCO2DIV_2)  || \
                                 ((__DIV__) == RCC_MCO2DIV_4)  || ((__DIV__) == RCC_MCO2DIV_8)  || \
                                 ((__DIV__) == RCC_MCO2DIV_16) || ((__DIV__) == RCC_MCO2DIV_32) || \
                                 ((__DIV__) == RCC_MCO2DIV_64) || ((__DIV__) == RCC_MCO2DIV_128)|| \
                                 ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512)|| \
                                 ((__DIV__) == RCC_MCO2DIV_1024))

Definition at line 229 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO2SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK)  || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_HSI48)   || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_HSI)     || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_HSE)     || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK)  || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_LSI)     || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_LSE)     || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK)  || \
                                       ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP))

Definition at line 204 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( __DIV__ )
Value:
(((__DIV__) == RCC_MCODIV_1)  || ((__DIV__) == RCC_MCODIV_2)   || \
                                ((__DIV__) == RCC_MCODIV_4)  || ((__DIV__) == RCC_MCODIV_8)   || \
                                ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32)  || \
                                ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128) || \
                                ((__DIV__) == RCC_MCODIV_256)|| ((__DIV__) == RCC_MCODIV_512) || \
                                ((__DIV__) == RCC_MCODIV_1024))

Definition at line 189 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_OSCILLATORTYPE ( __OSCILLATOR__ )
Value:
(((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
   (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)     || \
   (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)     || \
   (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
   (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)     || \
   (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))

Definition at line 64 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK ( __PCLK__ )
Value:
(((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
                               ((__PCLK__) == RCC_HCLK_DIV16))

Definition at line 138 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( __PLL__ )
Value:
(((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
                             ((__PLL__) == RCC_PLL_ON))

Definition at line 101 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLM_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == RCC_PLLM_DIV1) || ((__VALUE__) == RCC_PLLM_DIV2) || \
                                      ((__VALUE__) == RCC_PLLM_DIV3) || ((__VALUE__) == RCC_PLLM_DIV4) || \
                                      ((__VALUE__) == RCC_PLLM_DIV5) || ((__VALUE__) == RCC_PLLM_DIV6) || \
                                      ((__VALUE__) == RCC_PLLM_DIV7) || ((__VALUE__) == RCC_PLLM_DIV8))

Definition at line 108 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLN_VALUE ( __VALUE__ ) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))

Definition at line 113 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLP_VALUE ( __VALUE__ ) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))

Definition at line 115 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLQ_VALUE ( __VALUE__ ) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))

Definition at line 118 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLR_VALUE ( __VALUE__ ) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))

Definition at line 121 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))

Definition at line 104 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))

Definition at line 142 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SYSCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SYSCLKSOURCE_HSI)  || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE)  || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE)  || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI)  || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 126 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 88 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 89 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 90 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 93 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_GPIO_PORT GPIOA

Definition at line 94 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_PIN GPIO_PIN_10

Definition at line 95 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define RCC_PLL_OSCSOURCE_CONFIG ( __HAL_RCC_PLLSOURCE__ ) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))

Definition at line 98 of file stm32g0xx_hal_rcc.c.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Private Variables

RCC Private Variables
RCC
Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal and external oscillators
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB)

    [..] Internal/external clock and PLL configuration
         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.

         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also optionally as RTC clock source.

         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.

         (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks:
           (++) The first output (R) is used to generate the high speed system clock (up to 64MHz).
           (++) The second output(Q) is used to generate the clock for the random analog generator and HStim.
           (++) The Third output (P) is used to generate the clock for the Analog to Digital Converter and I2S.

         (+) CSS (Clock security system): once enabled, if a HSE or LSE clock failure occurs
            (HSE used directly or through PLL as System clock source), the System clock
             is automatically switched respectively to HSI or LSI and an interrupt is generated
             if enabled. The interrupt is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt)
             exception vector.

         (+) MCOx (microcontroller clock output):
             (++) MCO1 used to output LSI, HSI48(*), HSI, LSE, HSE or main PLL clock (through a configurable prescaler) on PA8 pin.
             (++) MCO2(*) used to output LSI, HSI48(*), HSI, LSE, HSE, main PLLR clock, PLLQ clock, PLLP clock, RTC clock or RTC_Wakeup (through a configurable prescaler) on PA10 pin.
                 (*) available on certain devices only

    [..] System, AHB and APB buses clocks configuration
         (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
             HSE, LSI, LSE and main PLL.
             The AHB clock (HCLK) is derived from System clock through configurable
             prescaler and used to clock the CPU, memory and peripherals mapped
             on AHB bus (DMA, GPIO...).and APB (PCLK1) clock is derived
             from AHB clock through configurable prescalers and used to clock
             the peripherals mapped on these buses. You can use
             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:

            (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
                divided by 2 to 31.
                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
                 to configure this clock.

            (+@) RNG(*) requires a frequency equal or lower than 48 MHz.
                 This clock is derived from the main PLL or HSI or System clock.
                 (*) available on certain devices only

            (+@) IWDG clock which is always the LSI clock.

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK is 64 MHz.
             Depending on the device voltage range, the maximum frequency should be
             adapted accordingly.

(++) Table 1. HCLK clock frequency. (++) +-------------------------------------------------------+ (++) | Latency | HCLK clock frequency (MHz) | (++) | |-------------------------------------| (++) | | voltage range 1 | voltage range 2 | (++) | | 1.2 V | 1.0 V | (++) |-----------------|------------------|------------------| (++) |0WS(1 CPU cycles)| HCLK <= 24 | HCLK <= 8 | (++) |-----------------|------------------|------------------| (++) |1WS(2 CPU cycles)| HCLK <= 48 | HCLK <= 16 | (++) |-----------------|------------------|------------------| (++) |2WS(3 CPU cycles)| HCLK <= 64 | - | (++) |-----------------|------------------|------------------|

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct pointer to a RCC_ClkInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency FLASH Latency This parameter can be one of the following values:
  • FLASH_LATENCY_0 FLASH 0 Latency cycle
  • FLASH_LATENCY_1 FLASH 1 Latency cycle
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function
The HSI is used by default as system clock source after startup from Reset, wake-up from STANDBY mode. After restart from Reset, the HSI frequency is set to 8 Mhz, then it reaches its default value 16 MHz.
The HSI can be selected as system clock source after from STOP modes or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
The LSI can be selected as system clock source after in case of failure of the LSE used directly or indirectly as system clock (if the Clock Security System LSECSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source is ready.
You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Depending on the device voltage range, the software has to set correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")
Return values:
None

Definition at line 800 of file stm32g0xx_hal_rcc.c.

References __HAL_FLASH_GET_LATENCY, __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_SYSCLK_SOURCE, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLK, IS_RCC_PCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_SYSCLK, RCC_HCLK_DIV16, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_HSI, RCC_SYSCLKSOURCE_LSI, RCC_SYSCLKSOURCE_PLLCLK, RCC_ClkInitTypeDef::SYSCLKSource, and uwTickPrio.

HAL_StatusTypeDef HAL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE, PLL OFF
  • AHB and APB prescaler set to 1.
  • CSS, MCO1 OFF
  • All interrupts disabled
This function does not modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
HAL status

Definition at line 218 of file stm32g0xx_hal_rcc.c.

References CLOCKSWITCH_TIMEOUT_VALUE, HAL_GetTick(), HAL_InitTick(), HSI_TIMEOUT_VALUE, HSI_VALUE, PLL_TIMEOUT_VALUE, and uwTickPrio.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct pointer to a RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this function. User should request a transition to HSE Off first and then to HSE On or HSE Bypass.
Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this function. User should request a transition to LSE Off first and then to LSE On or LSE Bypass.
Return values:
HAL status

Definition at line 310 of file stm32g0xx_hal_rcc.c.

References __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI48_DISABLE, __HAL_RCC_HSI48_ENABLE, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_CONFIG, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, assert_param, HAL_GetTick(), HAL_InitTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI48_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSI48State, HSI_TIMEOUT_VALUE, HSI_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIDiv, RCC_OscInitTypeDef::HSIState, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_HSI48, IS_RCC_HSI_CALIBRATION_VALUE, IS_RCC_HSIDIV, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLR_VALUE, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_HSE_OFF, RCC_HSI48_OFF, RCC_HSI_OFF, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_NONE, RCC_PLL_OFF, RCC_PLL_ON, RCC_PLLRCLK, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, RCC_SYSCLKSOURCE_STATUS_LSE, RCC_SYSCLKSOURCE_STATUS_LSI, RCC_SYSCLKSOURCE_STATUS_PLLCLK, and uwTickPrio.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PA10)(*).
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCC_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
Handle the RCC HSE Clock Security System interrupt callback.
__weak void | HAL_RCC_LSECSSCallback (void)
RCC LSE Clock Security System interrupt callback.
uint32_t | HAL_RCC_GetResetSource (void)
Get and clear reset flags.

Detailed Description

RCC clocks control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to:

    (+) Output clock to MCO pin.
    (+) Retrieve current clock frequencies.
    (+) Enable the Clock Security System.

Function Documentation

void HAL_RCC_CSSCallback ( void )

Handle the RCC HSE Clock Security System interrupt callback.

Return values:
none

Definition at line 1398 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableLSECSS ( void )

Disable the LSE Clock Security System.

Note:
After LSE failure detection, the software must disable LSECSSON
The Clock Security System can only be cleared by reset otherwise.
Return values:
None

Definition at line 1362 of file stm32g0xx_hal_rcc.c.

void HAL_RCC_EnableCSS ( void )

Enable the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
The Clock Security System can only be cleared by reset.
Return values:
None

Definition at line 1335 of file stm32g0xx_hal_rcc.c.

void HAL_RCC_EnableLSECSS ( void )

Enable the LSE Clock Security System.

Note:
If a failure is detected on the LSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
The LSE Clock Security System Detection bit (LSECSSD in BDCR) can only be cleared by a backup domain reset.
Return values:
None

Definition at line 1351 of file stm32g0xx_hal_rcc.c.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct | Pointer to a RCC_ClkInitTypeDef structure that will be configured.
pFLatency | Pointer on the Flash Latency.
Return values:
None

Definition at line 1302 of file stm32g0xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, assert_param, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_SYSCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Return the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
Return values:
HCLK frequency in Hz

Definition at line 1175 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_GetPCLK1Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configure the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1199 of file stm32g0xx_hal_rcc.c.

References assert_param, RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSI48State, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIDiv, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI48_OFF, RCC_HSI48_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Return the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency in Hz

Definition at line 1186 of file stm32g0xx_hal_rcc.c.

References __LL_RCC_CALC_PCLK1_FREQ, HAL_RCC_GetHCLKFreq(), and LL_RCC_GetAPB1Prescaler().

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetResetSource ( void )

Get and clear reset flags.

Note:
Once reset flags are retrieved, this API is clearing them in order to isolate next reset reason.
Return values:
can be a combination of Reset Flag

Definition at line 1422 of file stm32g0xx_hal_rcc.c.

References RCC_RESET_FLAG_ALL.

uint32_t HAL_RCC_GetSysClockFreq ( void )

Return the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE/HSIDIV(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), or HSI_VALUE(*) multiplied/divided by the PLL factors.
If SYSCLK source is LSI, function returns values based on LSI_VALUE(***)
If SYSCLK source is LSE, function returns values based on LSE_VALUE(****)
(*) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
(***) LSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value 32768 Hz).
(****) LSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value 32000 Hz).
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 1107 of file stm32g0xx_hal_rcc.c.

References __HAL_RCC_GET_SYSCLK_SOURCE, HSE_VALUE, HSI_VALUE, LSE_VALUE, LSI_VALUE, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, RCC_SYSCLKSOURCE_STATUS_LSE, RCC_SYSCLKSOURCE_STATUS_LSI, and RCC_SYSCLKSOURCE_STATUS_PLLCLK.

Referenced by HAL_RCC_ClockConfig(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCC_LSECSSCallback ( void )

RCC LSE Clock Security System interrupt callback.

Return values:
none

Definition at line 1409 of file stm32g0xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PA10)(*).

Note:
PA8, PA10(*) should be configured in alternate function mode.
Parameters:
RCC_MCOx specifies the output direction for the clock source. For STM32G0xx family this parameter can have only one value:
  • RCC_MCO1 Clock source to output on MCO1 pin(PA8).
  • RCC_MCO2 Clock source to output on MCO2 pin(PA10)(*).
RCC_MCOSource specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
  • RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
  • RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48(*)
  • RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
  • RCC_MCO1SOURCE_PLLCLK main PLLR clock selected as MCO source
  • RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
  • RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
  • RCC_MCO1SOURCE_PLLPCLK PLLP clock selected as MCO1 source(*)
  • RCC_MCO1SOURCE_PLLQCLK PLLQ clock selected as MCO1 source(*)
  • RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO1 source(*)
  • RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*)
  • RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled, no clock on MCO2(*)
  • RCC_MCO2SOURCE_SYSCLK system clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48(*)
  • RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_PLLCLK main PLLR clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_PLLPCLK PLLP clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_PLLQCLK PLLQ clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source(*)
  • RCC_MCO2SOURCE_RTC_WKUP RTC_Wakeup selected as MCO2 source(*)
RCC_MCODiv specifies the MCO prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 no division applied to MCO clock
  • RCC_MCODIV_2 division by 2 applied to MCO clock
  • RCC_MCODIV_4 division by 4 applied to MCO clock
  • RCC_MCODIV_8 division by 8 applied to MCO clock
  • RCC_MCODIV_16 division by 16 applied to MCO clock
  • RCC_MCODIV_32 division by 32 applied to MCO clock
  • RCC_MCODIV_64 division by 64 applied to MCO clock
  • RCC_MCODIV_128 division by 128 applied to MCO clock
  • RCC_MCO2DIV_1 no division applied to MCO2 clock(*)
  • RCC_MCO2DIV_2 division by 2 applied to MCO2 clock(*)
  • RCC_MCO2DIV_4 division by 4 applied to MCO2 clock(*)
  • RCC_MCO2DIV_8 division by 8 applied to MCO2 clock(*)
  • RCC_MCO2DIV_16 division by 16 applied to MCO2 clock(*)
  • RCC_MCO2DIV_32 division by 32 applied to MCO2 clock(*)
  • RCC_MCO2DIV_64 division by 64 applied to MCO2 clock(*)
  • RCC_MCO2DIV_128 division by 128 applied to MCO2 clock(*)
  • RCC_MCO2DIV_256 division by 256 applied to MCO2 clock(*)
  • RCC_MCO2DIV_512 division by 512 applied to MCO2 clock(*)
  • RCC_MCO2DIV_1024 division by 1024 applied to MCO2 clock(*)
(*) Feature not available on all devices of the family
Return values:
None

Definition at line 1029 of file stm32g0xx_hal_rcc.c.

References GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_AF3_MCO2, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCO2DIV, IS_RCC_MCO2SOURCE, IS_RCC_MCODIV, MCO1_CLK_ENABLE, MCO1_GPIO_PORT, MCO1_PIN, MCO2_CLK_ENABLE, MCO2_GPIO_PORT, MCO2_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_MCO1, RCC_MCO2, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

Handle the RCC Clock Security System interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1372 of file stm32g0xx_hal_rcc.c.

References HAL_RCC_CSSCallback(), and HAL_RCC_LSECSSCallback().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32g0xx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ
uint32_t | PLLR

Detailed Description

RCC PLL configuration structure definition.

Definition at line 255 of file stm32g0xx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLM

PLLM: Division factor for PLL VCO input clock. This parameter must be a value of PLLM Clock Divider

Definition at line 263 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLN

PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86

Definition at line 266 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLP

PLLP: PLL Division factor. User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ. This parameter must be a value of PLLP Clock Divider

Definition at line 269 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLQ

PLLQ: PLL Division factor. User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ. This parameter must be a value of PLLQ Clock Divider

Definition at line 274 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLR

PLLR: PLL Division for the main system clock. User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ. This parameter must be a value of PLLR Clock Divider

Definition at line 279 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

RCC_PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 260 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

The new state of the PLL. This parameter can be a value of PLL Config

Definition at line 257 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rcc.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...

#include <stm32g0xx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSIDiv
uint32_t | HSICalibrationValue
uint32_t | LSIState
uint32_t | HSI48State
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.

Definition at line 288 of file stm32g0xx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of HSE Config

Definition at line 293 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSI48State

The new state of the HSI48 (only applicable to STM32G0C1xx/STM32G0B1xx/STM32G0B0xx devices). This parameter can be a value of HSI48 Config

Definition at line 312 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 305 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIDiv

The division factor of the HSI16. This parameter can be a value of HSI Div

Definition at line 302 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of HSI Config

Definition at line 299 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of LSE Config

Definition at line 296 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of LSI Config

Definition at line 308 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of Oscillator Type

Definition at line 290 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

Main PLL structure parameters

Definition at line 317 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rcc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB buses clock configuration structure definition. More...

#include <stm32g0xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider

Detailed Description

RCC System, AHB and APB buses clock configuration structure definition.

Definition at line 324 of file stm32g0xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 332 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB Clock Source

Definition at line 335 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a combination of System Clock Type

Definition at line 326 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source used as system clock (SYSCLK). This parameter can be a value of System Clock Source

Definition at line 329 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rcc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Timeout Values

Defines
Timeout Values
RCC Exported Constants

Defines

#define | RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */

Define Documentation

#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 353 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */

Definition at line 354 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Oscillator Type

Defines
Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE 0x00000000U
#define | RCC_OSCILLATORTYPE_HSE 0x00000001U
#define | RCC_OSCILLATORTYPE_HSI 0x00000002U
#define | RCC_OSCILLATORTYPE_LSE 0x00000004U
#define | RCC_OSCILLATORTYPE_LSI 0x00000008U
#define | RCC_OSCILLATORTYPE_HSI48 0x00000020U

Define Documentation

#define RCC_OSCILLATORTYPE_HSE 0x00000001U

HSE to configure

Definition at line 363 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI 0x00000002U

HSI to configure

Definition at line 364 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI48 0x00000020U

HSI48 to configure

Definition at line 368 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE 0x00000004U

LSE to configure

Definition at line 365 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI 0x00000008U

LSI to configure

Definition at line 366 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE 0x00000000U

Oscillator configuration unchanged

Definition at line 362 of file stm32g0xx_hal_rcc.h.

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STM32G0C1xx HAL User Manual: HSE Config

Defines
HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF 0x00000000U
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON)

Define Documentation

#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON)

External clock source for HSE clock

Definition at line 380 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF 0x00000000U

HSE clock deactivation

Definition at line 378 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

HSE clock activation

Definition at line 379 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LSE Config

Defines
LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF 0x00000000U
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)

Define Documentation

#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)

External clock source for LSE clock

Definition at line 390 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF 0x00000000U

LSE clock deactivation

Definition at line 388 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

LSE clock activation

Definition at line 389 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HSI Config

Defines
HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF 0x00000000U
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT 64U

Define Documentation

#define RCC_HSI_OFF 0x00000000U

HSI clock deactivation

Definition at line 398 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

HSI clock activation

Definition at line 399 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSICALIBRATION_DEFAULT 64U

Default HSI calibration trimming value

Definition at line 401 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HSI Div

Defines
HSI Div
RCC Exported Constants

Defines

#define | RCC_HSI_DIV1 0x00000000U
#define | RCC_HSI_DIV2 RCC_CR_HSIDIV_0
#define | RCC_HSI_DIV4 RCC_CR_HSIDIV_1
#define | RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)
#define | RCC_HSI_DIV16 RCC_CR_HSIDIV_2
#define | RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0)
#define | RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1)
#define | RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)

Define Documentation

#define RCC_HSI_DIV1 0x00000000U

HSI clock is not divided

Definition at line 409 of file stm32g0xx_hal_rcc.h.

#define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)

HSI clock is divided by 128

Definition at line 416 of file stm32g0xx_hal_rcc.h.

#define RCC_HSI_DIV16 RCC_CR_HSIDIV_2

HSI clock is divided by 16

Definition at line 413 of file stm32g0xx_hal_rcc.h.

#define RCC_HSI_DIV2 RCC_CR_HSIDIV_0

HSI clock is divided by 2

Definition at line 410 of file stm32g0xx_hal_rcc.h.

#define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0)

HSI clock is divided by 32

Definition at line 414 of file stm32g0xx_hal_rcc.h.

#define RCC_HSI_DIV4 RCC_CR_HSIDIV_1

HSI clock is divided by 4

Definition at line 411 of file stm32g0xx_hal_rcc.h.

#define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1)

HSI clock is divided by 64

Definition at line 415 of file stm32g0xx_hal_rcc.h.

#define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)

HSI clock is divided by 8

Definition at line 412 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LSI Config

Defines
LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF 0x00000000U
#define | RCC_LSI_ON RCC_CSR_LSION

Define Documentation

#define RCC_LSI_OFF 0x00000000U

LSI clock deactivation

Definition at line 424 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON RCC_CSR_LSION

LSI clock activation

Definition at line 425 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HSI48 Config

Defines
HSI48 Config
RCC Exported Constants

Defines

#define | RCC_HSI48_OFF 0x00000000U
#define | RCC_HSI48_ON RCC_CR_HSI48ON

Define Documentation

#define RCC_HSI48_OFF 0x00000000U

HSI48 clock deactivation

Definition at line 434 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI48_ON RCC_CR_HSI48ON

HSI48 clock activation

Definition at line 435 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLL Config

Defines
PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE 0x00000000U
#define | RCC_PLL_OFF 0x00000001U
#define | RCC_PLL_ON 0x00000002U

Define Documentation

#define RCC_PLL_NONE 0x00000000U

PLL configuration unchanged

Definition at line 444 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF 0x00000001U

PLL deactivation

Definition at line 445 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_PLL_ON 0x00000002U

PLL activation

Definition at line 446 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLLM Clock Divider

Defines
PLLM Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLM_DIV1 0x00000000U
#define | RCC_PLLM_DIV2 RCC_PLLCFGR_PLLM_0
#define | RCC_PLLM_DIV3 RCC_PLLCFGR_PLLM_1
#define | RCC_PLLM_DIV4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | RCC_PLLM_DIV5 RCC_PLLCFGR_PLLM_2
#define | RCC_PLLM_DIV6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
#define | RCC_PLLM_DIV7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
#define | RCC_PLLM_DIV8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0)

Define Documentation

#define RCC_PLLM_DIV1 0x00000000U

PLLM division factor = 8

Definition at line 454 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLM_DIV2 RCC_PLLCFGR_PLLM_0

PLLM division factor = 2

Definition at line 455 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLM_DIV3 RCC_PLLCFGR_PLLM_1

PLLM division factor = 3

Definition at line 456 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLM_DIV4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)

PLLM division factor = 4

Definition at line 457 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLM_DIV5 RCC_PLLCFGR_PLLM_2

PLLM division factor = 5

Definition at line 458 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLM_DIV6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)

PLLM division factor = 6

Definition at line 459 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLM_DIV7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)

PLLM division factor = 7

Definition at line 460 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLM_DIV8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0)

PLLM division factor = 8

Definition at line 461 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLLP Clock Divider

Defines
PLLP Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLP_DIV2 RCC_PLLCFGR_PLLP_0
#define | RCC_PLLP_DIV3 RCC_PLLCFGR_PLLP_1
#define | RCC_PLLP_DIV4 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV5 RCC_PLLCFGR_PLLP_2
#define | RCC_PLLP_DIV6 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV7 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV8 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV9 RCC_PLLCFGR_PLLP_3
#define | RCC_PLLP_DIV10 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV11 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV12 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV13 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2)
#define | RCC_PLLP_DIV14 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV15 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV16 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV17 RCC_PLLCFGR_PLLP_4
#define | RCC_PLLP_DIV18 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV19 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV20 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV21 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2)
#define | RCC_PLLP_DIV22 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV23 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV24 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV25 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3)
#define | RCC_PLLP_DIV26 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV27 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV28 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV29 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2)
#define | RCC_PLLP_DIV30 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV31 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV32 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

Define Documentation

#define RCC_PLLP_DIV10 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 10

Definition at line 477 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV11 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1)

PLLP division factor = 11

Definition at line 478 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV12 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 12

Definition at line 479 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV13 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2)

PLLP division factor = 13

Definition at line 480 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV14 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 14

Definition at line 481 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV15 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)

PLLP division factor = 15

Definition at line 482 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV16 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 16

Definition at line 483 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV17 RCC_PLLCFGR_PLLP_4

PLLP division factor = 17

Definition at line 484 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV18 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 18

Definition at line 485 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV19 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1)

PLLP division factor = 19

Definition at line 486 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV2 RCC_PLLCFGR_PLLP_0

PLLP division factor = 2

Definition at line 469 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV20 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 20

Definition at line 487 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV21 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2)

PLLP division factor = 21

Definition at line 488 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV22 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 22

Definition at line 489 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV23 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)

PLLP division factor = 23

Definition at line 490 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV24 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 24

Definition at line 491 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV25 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3)

PLLP division factor = 25

Definition at line 492 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV26 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 26

Definition at line 493 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV27 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1)

PLLP division factor = 27

Definition at line 494 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV28 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 28

Definition at line 495 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV29 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2)

PLLP division factor = 29

Definition at line 496 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV3 RCC_PLLCFGR_PLLP_1

PLLP division factor = 3

Definition at line 470 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV30 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 30

Definition at line 497 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV31 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)

PLLP division factor = 31

Definition at line 498 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV32 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 32

Definition at line 499 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV4 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 4

Definition at line 471 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV5 RCC_PLLCFGR_PLLP_2

PLLP division factor = 5

Definition at line 472 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV6 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 6

Definition at line 473 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV7 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)

PLLP division factor = 7

Definition at line 474 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV8 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)

PLLP division factor = 8

Definition at line 475 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLP_DIV9 RCC_PLLCFGR_PLLP_3

PLLP division factor = 9

Definition at line 476 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLLQ Clock Divider

Defines
PLLQ Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLQ_DIV2 RCC_PLLCFGR_PLLQ_0
#define | RCC_PLLQ_DIV3 RCC_PLLCFGR_PLLQ_1
#define | RCC_PLLQ_DIV4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0)
#define | RCC_PLLQ_DIV5 RCC_PLLCFGR_PLLQ_2
#define | RCC_PLLQ_DIV6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0)
#define | RCC_PLLQ_DIV7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1)
#define | RCC_PLLQ_DIV8 (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0)

Define Documentation

#define RCC_PLLQ_DIV2 RCC_PLLCFGR_PLLQ_0

PLLQ division factor = 2

Definition at line 508 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLQ_DIV3 RCC_PLLCFGR_PLLQ_1

PLLQ division factor = 3

Definition at line 509 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLQ_DIV4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0)

PLLQ division factor = 4

Definition at line 510 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLQ_DIV5 RCC_PLLCFGR_PLLQ_2

PLLQ division factor = 5

Definition at line 511 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLQ_DIV6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0)

PLLQ division factor = 6

Definition at line 512 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLQ_DIV7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1)

PLLQ division factor = 7

Definition at line 513 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLQ_DIV8 (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0)

PLLQ division factor = 8

Definition at line 514 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLLR Clock Divider

Defines
PLLR Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLR_DIV2 RCC_PLLCFGR_PLLR_0
#define | RCC_PLLR_DIV3 RCC_PLLCFGR_PLLR_1
#define | RCC_PLLR_DIV4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0)
#define | RCC_PLLR_DIV5 RCC_PLLCFGR_PLLR_2
#define | RCC_PLLR_DIV6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0)
#define | RCC_PLLR_DIV7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1)
#define | RCC_PLLR_DIV8 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0)

Define Documentation

#define RCC_PLLR_DIV2 RCC_PLLCFGR_PLLR_0

PLLR division factor = 2

Definition at line 522 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLR_DIV3 RCC_PLLCFGR_PLLR_1

PLLR division factor = 3

Definition at line 523 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLR_DIV4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0)

PLLR division factor = 4

Definition at line 524 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLR_DIV5 RCC_PLLCFGR_PLLR_2

PLLR division factor = 5

Definition at line 525 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLR_DIV6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0)

PLLR division factor = 6

Definition at line 526 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLR_DIV7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1)

PLLR division factor = 7

Definition at line 527 of file stm32g0xx_hal_rcc.h.

#define RCC_PLLR_DIV8 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0)

PLLR division factor = 8

Definition at line 528 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLL Clock Source

Defines
PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_NONE 0x00000000U
#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Define Documentation

#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

HSE clock selected as PLL entry clock source

Definition at line 537 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

HSI clock selected as PLL entry clock source

Definition at line 536 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_PLLSOURCE_NONE 0x00000000U

No clock selected as PLL entry clock source

Definition at line 535 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLL Clock Output

Defines
PLL Clock Output
RCC Exported Constants

Defines

#define | RCC_PLLPCLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLLQCLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLLRCLK RCC_PLLCFGR_PLLREN

Define Documentation

#define RCC_PLLPCLK RCC_PLLCFGR_PLLPEN

PLLPCLK selection from main PLL

Definition at line 545 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLLQCLK RCC_PLLCFGR_PLLQEN

PLLQCLK selection from main PLL

Definition at line 547 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLLRCLK RCC_PLLCFGR_PLLREN

PLLRCLK selection from main PLL

Definition at line 549 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: System Clock Type

Defines
System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define | RCC_CLOCKTYPE_HCLK 0x00000002U
#define | RCC_CLOCKTYPE_PCLK1 0x00000004U

Define Documentation

#define RCC_CLOCKTYPE_HCLK 0x00000002U

HCLK to configure

Definition at line 559 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 0x00000004U

PCLK1 to configure

Definition at line 560 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK 0x00000001U

SYSCLK to configure

Definition at line 558 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: System Clock Source

Defines
System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_HSI 0x00000000U
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_1
#define | RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)
#define | RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2

Define Documentation

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0

HSE selection as system clock

Definition at line 569 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI 0x00000000U

HSI selection as system clock

Definition at line 568 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2

LSE selection as system clock

Definition at line 572 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)

LSI selection as system clock

Definition at line 571 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_1

PLL selection as system clock

Definition at line 570 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_1
#define | RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)
#define | RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2

Define Documentation

#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0

HSE used as system clock

Definition at line 581 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U

HSI used as system clock

Definition at line 580 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2

LSE used as system clock

Definition at line 584 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)

LSI used as system clock

Definition at line 583 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_1

PLL used as system clock

Definition at line 582 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB Clock Source

Defines
AHB Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 0x00000000U
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3
#define | RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)
#define | RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)
#define | RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)
#define | RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)
#define | RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)
#define | RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

Define Documentation

#define RCC_SYSCLK_DIV1 0x00000000U

SYSCLK not divided

Definition at line 592 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)

SYSCLK divided by 128

Definition at line 598 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

SYSCLK divided by 16

Definition at line 596 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3

SYSCLK divided by 2

Definition at line 593 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)

SYSCLK divided by 256

Definition at line 599 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)

SYSCLK divided by 4

Definition at line 594 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

SYSCLK divided by 512

Definition at line 600 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)

SYSCLK divided by 64

Definition at line 597 of file stm32g0xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)

SYSCLK divided by 8

Definition at line 595 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB Clock Source

Defines
APB Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 0x00000000U
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE_2
#define | RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)
#define | RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)
#define | RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)

Define Documentation

#define RCC_HCLK_DIV1 0x00000000U

HCLK not divided

Definition at line 608 of file stm32g0xx_hal_rcc.h.

#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)

HCLK divided by 16

Definition at line 612 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_2

HCLK divided by 2

Definition at line 609 of file stm32g0xx_hal_rcc.h.

#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)

HCLK divided by 4

Definition at line 610 of file stm32g0xx_hal_rcc.h.

#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)

HCLK divided by 8

Definition at line 611 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Clock Source

Defines
RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_NONE 0x00000000U
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 623 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 621 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 622 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_NONE 0x00000000U

No clock configured for RTC

Definition at line 620 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO Index

Defines
MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 0x00000000U
#define | RCC_MCO2 0x00000001U
#define | RCC_MCO RCC_MCO1

Define Documentation

#define RCC_MCO RCC_MCO1

MCO1 to be compliant with other families with 2 MCOs

Definition at line 636 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1 0x00000000U

Definition at line 631 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO2 0x00000001U

MCO2 index

Definition at line 633 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO1 Clock Source

Defines
MCO1 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1
#define | RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3
#define | RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)
#define | RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)
#define | RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0)

Define Documentation

#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2

HSE selection as MCO1 source

Definition at line 650 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)

HSI selection as MCO1 source

Definition at line 649 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1

HSI48 selection as MCO1 source

Definition at line 647 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSE selection as MCO1 source

Definition at line 653 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSI selection as MCO1 source

Definition at line 652 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U

MCO1 output disabled, no clock on MCO1

Definition at line 644 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)

PLLCLK selection as MCO1 source

Definition at line 651 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3

PLLPCLK selection as MCO1 source

Definition at line 655 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)

PLLQCLK selection as MCO1 source

Definition at line 656 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0)

RTC_Wakeup selection as MCO1 source

Definition at line 658 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)

RTCCLK selection as MCO1 source

Definition at line 657 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0

SYSCLK selection as MCO1 source

Definition at line 645 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO1 Clock Prescaler

Defines
MCO1 Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCODIV_1 0x00000000U
#define | RCC_MCODIV_2 RCC_CFGR_MCOPRE_0
#define | RCC_MCODIV_4 RCC_CFGR_MCOPRE_1
#define | RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | RCC_MCODIV_16 RCC_CFGR_MCOPRE_2
#define | RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)
#define | RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)
#define | RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | RCC_MCODIV_256 RCC_CFGR_MCOPRE_3
#define | RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)
#define | RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)

Define Documentation

#define RCC_MCODIV_1 0x00000000U

MCO not divided

Definition at line 667 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)

MCO divided by 1024

Definition at line 678 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)

MCO divided by 128

Definition at line 674 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2

MCO divided by 16

Definition at line 671 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0

MCO divided by 2

Definition at line 668 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_256 RCC_CFGR_MCOPRE_3

MCO divided by 256

Definition at line 676 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)

MCO divided by 32

Definition at line 672 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1

MCO divided by 4

Definition at line 669 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)

MCO divided by 512

Definition at line 677 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)

MCO divided by 64

Definition at line 673 of file stm32g0xx_hal_rcc.h.

#define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)

MCO divided by 8

Definition at line 670 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO2 Clock Source

Defines
MCO2 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO2SOURCE_NOCLOCK 0x00000000U
#define | RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0
#define | RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1
#define | RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1| RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2
#define | RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1)
#define | RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3
#define | RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1)
#define | RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0)

Define Documentation

#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2

HSE selection as MCO2 source

Definition at line 694 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1| RCC_CFGR_MCO2SEL_0)

HSI selection as MCO2 source

Definition at line 693 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1

HSI48 selection as MCO2 source

Definition at line 691 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0)

LSE selection as MCO2 source

Definition at line 697 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1)

LSI selection as MCO2 source

Definition at line 696 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_NOCLOCK 0x00000000U

MCO2 output disabled, no clock on MCO2

Definition at line 688 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_0)

PLLCLK selection as MCO2 source

Definition at line 695 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3

PLLPCLK selection as MCO2 source

Definition at line 698 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0)

PLLQCLK selection as MCO2 source

Definition at line 699 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0)

RTC_Wakeup selection as MCO2 source

Definition at line 701 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1)

RTCCLK selection as MCO2 source

Definition at line 700 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0

SYSCLK selection as MCO2 source

Definition at line 689 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO2 Clock Prescaler

Defines
MCO2 Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCO2DIV_1 0x00000000U
#define | RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0
#define | RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1
#define | RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#define | RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2
#define | RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)
#define | RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)
#define | RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#define | RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3
#define | RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)
#define | RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)

Define Documentation

#define RCC_MCO2DIV_1 0x00000000U

MCO2 not divided

Definition at line 709 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)

MCO2 divided by 1024

Definition at line 719 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)

MCO2 divided by 128

Definition at line 716 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2

MCO2 divided by 16

Definition at line 713 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0

MCO2 divided by 2

Definition at line 710 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3

MCO2 divided by 256

Definition at line 717 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)

MCO2 divided by 32

Definition at line 714 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1

MCO2 divided by 4

Definition at line 711 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)

MCO2 divided by 512

Definition at line 718 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)

MCO2 divided by 64

Definition at line 715 of file stm32g0xx_hal_rcc.h.

#define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)

MCO2 divided by 8

Definition at line 712 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Interrupts

Defines
Interrupts
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
#define | RCC_IT_LSERDY RCC_CIFR_LSERDYF
#define | RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
#define | RCC_IT_HSERDY RCC_CIFR_HSERDYF
#define | RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
#define | RCC_IT_CSS RCC_CIFR_CSSF
#define | RCC_IT_LSECSS RCC_CIFR_LSECSSF
#define | RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF

Define Documentation

#define RCC_IT_CSS RCC_CIFR_CSSF

HSE Clock Security System Interrupt flag

Definition at line 733 of file stm32g0xx_hal_rcc.h.

#define RCC_IT_HSERDY RCC_CIFR_HSERDYF

HSE Ready Interrupt flag

Definition at line 731 of file stm32g0xx_hal_rcc.h.

#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF

HSI48 Ready Interrupt flag

Definition at line 736 of file stm32g0xx_hal_rcc.h.

#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF

HSI Ready Interrupt flag

Definition at line 730 of file stm32g0xx_hal_rcc.h.

#define RCC_IT_LSECSS RCC_CIFR_LSECSSF

LSE Clock Security System Interrupt flag

Definition at line 734 of file stm32g0xx_hal_rcc.h.

#define RCC_IT_LSERDY RCC_CIFR_LSERDYF

LSE Ready Interrupt flag

Definition at line 729 of file stm32g0xx_hal_rcc.h.

#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF

LSI Ready Interrupt flag

Definition at line 728 of file stm32g0xx_hal_rcc.h.

#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 732 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Flags

Defines
Flags
RCC Exported Constants

Elements values convention: XXXYYYYYb. More...

Defines

#define | RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)
#define | RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)
#define | RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)
#define | RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)
#define | RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)
#define | RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)
#define | RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)
#define | RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)
#define | RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)
#define | RCC_FLAG_PWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos)
#define | RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)
#define | RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)
#define | RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)
#define | RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)

Detailed Description

Elements values convention: XXXYYYYYb.

  • YYYYY : Flag position in the register
  • XXX : Register index
    • 001: CR register
    • 010: BDCR register
    • 011: CSR register

Define Documentation

#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)

HSE Ready flag

Definition at line 753 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)

HSI48 Ready flag

Definition at line 758 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)

HSI Ready flag

Definition at line 752 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)

Independent Watchdog reset flag

Definition at line 771 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)

Low-Power reset flag

Definition at line 773 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)

LSE Clock Security System Interrupt flag

Definition at line 763 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)

LSE Ready flag

Definition at line 762 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)

LSI Ready flag

Definition at line 766 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)

Option Byte Loader reset flag

Definition at line 767 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)

PIN reset flag

Definition at line 768 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)

PLL Ready flag

Definition at line 754 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_PWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos)

BOR or POR/PDR reset flag

Definition at line 769 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)

Software Reset flag

Definition at line 770 of file stm32g0xx_hal_rcc.h.

#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)

Window watchdog reset flag

Definition at line 772 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LSE Drive Configuration

Defines
LSE Drive Configuration
RCC Exported Constants

Defines

#define | RCC_LSEDRIVE_LOW 0x00000000U
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

LSE high drive capability

Definition at line 785 of file stm32g0xx_hal_rcc.h.

#define RCC_LSEDRIVE_LOW 0x00000000U

LSE low drive capability

Definition at line 782 of file stm32g0xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

LSE medium high drive capability

Definition at line 784 of file stm32g0xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

LSE medium low drive capability

Definition at line 783 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Reset Flag

Defines
Reset Flag
RCC Exported Constants

Defines

#define | RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF
#define | RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF
#define | RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF
#define | RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF
#define | RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF
#define | RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF
#define | RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF
#define | RCC_RESET_FLAG_ALL

Define Documentation

#define RCC_RESET_FLAG_ALL
Value:
(RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \
                                        RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \
                                        RCC_RESET_FLAG_LPWR)

Definition at line 800 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_GetResetSource().

#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF

Independent Watchdog reset flag

Definition at line 797 of file stm32g0xx_hal_rcc.h.

#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF

Low power reset flag

Definition at line 799 of file stm32g0xx_hal_rcc.h.

#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF

Option Byte Loader reset flag

Definition at line 793 of file stm32g0xx_hal_rcc.h.

#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF

PIN reset flag

Definition at line 794 of file stm32g0xx_hal_rcc.h.

#define RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF

BOR or POR/PDR reset flag

Definition at line 795 of file stm32g0xx_hal_rcc.h.

#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF

Software Reset flag

Definition at line 796 of file stm32g0xx_hal_rcc.h.

#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF

Window watchdog reset flag

Definition at line 798 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB Peripheral Clock Enable Disable

Defines
AHB Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB peripheral clock. More...

Defines

#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_FLASH_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_AES_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
#define | __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)
#define | __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN)
#define | __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
#define | __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN)
#define | __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN)

Detailed Description

Enable or disable the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_AES_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN)

Definition at line 891 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_AES_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 872 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)

Definition at line 886 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 853 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)

Definition at line 881 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 825 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)

Definition at line 883 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 834 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN)

Definition at line 885 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 845 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN)

Definition at line 888 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 862 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IOPORT Clock Enable Disable

Defines
IOPORT Clock Enable Disable
RCC Exported Macros

Enable or disable the IO Ports clock. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN)

Detailed Description

Enable or disable the IO Ports clock.

Note:
After reset, the IO ports clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)

Definition at line 955 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 905 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)

Definition at line 956 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 913 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)

Definition at line 957 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 921 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN)

Definition at line 958 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 929 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN)

Definition at line 960 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 938 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_DISABLE ( ) CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN)

Definition at line 962 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 947 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB1 Peripheral Clock Enable Disable

Defines
APB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_CRS_CLK_ENABLE()
#define | __HAL_RCC_RTCAPB_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_USART4_CLK_ENABLE()
#define | __HAL_RCC_USART5_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_LPUART2_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_UCPD1_CLK_ENABLE()
#define | __HAL_RCC_UCPD2_CLK_ENABLE()
#define | __HAL_RCC_USB_CLK_ENABLE()
#define | __HAL_RCC_FDCAN_CLK_ENABLE()
#define | __HAL_RCC_DBGMCU_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_DAC1_CLK_ENABLE()
#define | __HAL_RCC_LPTIM2_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()

Detailed Description

Enable or disable the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CEC_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1153 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0)

Definition at line 1020 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1219 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_CLK_ENABLE ( )
Value:
do { \
                                                       __IO uint32_t tmpreg; \
                                                       SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
      /* Delay after an RCC peripheral clock enabling */ \
                                                       tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
                                                       UNUSED(tmpreg); \
                                                     } while(0U)

Definition at line 1202 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_ENABLE ( )
Value:
do { \
                                                     __IO uint32_t tmpreg; \
                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
    /* Delay after an RCC peripheral clock enabling */ \
                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
                                                     UNUSED(tmpreg); \
                                                   } while(0)

Definition at line 1193 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1126 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1134 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1143 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1239 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1229 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1107 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1117 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1210 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTCAPB_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1029 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1045 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1053 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 976 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 985 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 994 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1003 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1011 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_CLK_ENABLE ( )
Value:
do { \
                                                      __IO uint32_t tmpreg; \
                                                      SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
     /* Delay after an RCC peripheral clock enabling */ \
                                                      tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
                                                      UNUSED(tmpreg); \
                                                    } while(0U)

Definition at line 1163 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_CLK_ENABLE ( )
Value:
do { \
                                                      __IO uint32_t tmpreg; \
                                                      SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
     /* Delay after an RCC peripheral clock enabling */ \
                                                      tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
                                                      UNUSED(tmpreg); \
                                                    } while(0U)

Definition at line 1173 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1062 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1070 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_CLK_ENABLE ( )
Value:
do { \
                                                     __IO uint32_t tmpreg; \
                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
    /* Delay after an RCC peripheral clock enabling */ \
                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
                                                     UNUSED(tmpreg); \
                                                   } while(0U)

Definition at line 1078 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_CLK_ENABLE ( )
Value:
do { \
                                                     __IO uint32_t tmpreg; \
                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
    /* Delay after an RCC peripheral clock enabling */ \
                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
                                                     UNUSED(tmpreg); \
                                                   } while(0U)

Definition at line 1087 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
                                                     __IO uint32_t tmpreg; \
                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
    /* Delay after an RCC peripheral clock enabling */ \
                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
                                                     UNUSED(tmpreg); \
                                                   } while(0U)

Definition at line 1097 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_ENABLE ( )
Value:
do { \
                                                      __IO uint32_t tmpreg; \
                                                      SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
     /* Delay after an RCC peripheral clock enabling */ \
                                                      tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
                                                      UNUSED(tmpreg); \
                                                    } while(0U)

Definition at line 1183 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1037 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB2 Peripheral Clock Enable Disable

Defines
APB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_ADC_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN)
#define | __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN);
#define | __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN)
#define | __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN)
#define | __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN)
#define | __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN)
#define | __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN)
#define | __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)
#define | __HAL_RCC_LPUART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN)
#define | __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN)
#define | __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN)
#define | __HAL_RCC_UCPD2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN)
#define | __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN)
#define | __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN)
#define | __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)
#define | __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)
#define | __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN)
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN)
#define | __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN)
#define | __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN)
#define | __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN)

Detailed Description

Enable or disable the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN)

Definition at line 1415 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_ADC_CLK_ENABLE ( )
Value:
do { \
                                                  __IO uint32_t tmpreg; \
                                                  SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
 /* Delay after an RCC peripheral clock enabling */ \
                                                  tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
                                                  UNUSED(tmpreg); \
                                                } while(0U)

Definition at line 1326 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN)

Definition at line 1380 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN);

Definition at line 1348 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN)

Definition at line 1397 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)

Definition at line 1394 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN)

Definition at line 1392 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN)

Definition at line 1374 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN)

Definition at line 1375 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN)

Definition at line 1377 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN)

Definition at line 1400 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN)

Definition at line 1403 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)

Definition at line 1369 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)

Definition at line 1372 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)

Definition at line 1395 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTCAPB_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN)

Definition at line 1350 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN)

Definition at line 1407 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1276 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN)

Definition at line 1351 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN)

Definition at line 1353 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN)

Definition at line 1405 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1260 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_EnableFastModePlus(), HAL_SMBUSEx_DisableFastModePlus(), and HAL_SMBUSEx_EnableFastModePlus().

#define __HAL_RCC_TIM14_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN)

Definition at line 1409 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
                                                     __IO uint32_t tmpreg; \
                                                     SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
    /* Delay after an RCC peripheral clock enabling */ \
                                                     tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
                                                     UNUSED(tmpreg); \
                                                   } while(0U)

Definition at line 1292 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN)

Definition at line 1411 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1301 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN)

Definition at line 1413 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1310 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN)

Definition at line 1414 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1318 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)

Definition at line 1406 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1268 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)

Definition at line 1335 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)

Definition at line 1337 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN)

Definition at line 1339 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN)

Definition at line 1342 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN)

Definition at line 1345 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN)

Definition at line 1383 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN)

Definition at line 1386 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN)

Definition at line 1408 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                                    __IO uint32_t tmpreg; \
                                                    SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
   /* Delay after an RCC peripheral clock enabling */ \
                                                    tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
                                                    UNUSED(tmpreg); \
                                                  } while(0U)

Definition at line 1284 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN)

Definition at line 1355 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN)

Definition at line 1357 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN)

Definition at line 1360 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN)

Definition at line 1363 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN)

Definition at line 1366 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_DISABLE ( ) CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN)

Definition at line 1389 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB Peripheral Clock Enabled or Disabled Status

Defines
AHB Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET)
#define | __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET)
#define | __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) == RESET)

Detailed Description

Check whether the AHB peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_AES_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) == RESET)

Definition at line 1452 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_AES_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) != RESET)

Definition at line 1439 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET)

Definition at line 1447 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)

Definition at line 1434 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET)

Definition at line 1442 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)

Definition at line 1429 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == RESET)

Definition at line 1444 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != RESET)

Definition at line 1431 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET)

Definition at line 1446 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET)

Definition at line 1433 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET)

Definition at line 1449 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET)

Definition at line 1436 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IOPORT Clock Enabled or Disabled Status

Defines
IOPORT Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the IO Port clock is enabled or not. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET)

Detailed Description

Check whether the IO Port clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET)

Definition at line 1475 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)

Definition at line 1465 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET)

Definition at line 1476 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)

Definition at line 1466 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET)

Definition at line 1477 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)

Definition at line 1467 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET)

Definition at line 1478 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET)

Definition at line 1468 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET)

Definition at line 1480 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET)

Definition at line 1470 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_DISABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET)

Definition at line 1482 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_ENABLED ( ) (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET)

Definition at line 1472 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB1 Peripheral Clock Enabled or Disabled Status

Defines
APB1 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB1 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) != 0U)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U)
#define | __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U)
#define | __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U)
#define | __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U)
#define | __HAL_RCC_LPUART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U)
#define | __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) != 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) != 0U)
#define | __HAL_RCC_UCPD2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) != 0U)
#define | __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U)
#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) == 0U)
#define | __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U)
#define | __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U)
#define | __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U)
#define | __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U)
#define | __HAL_RCC_LPUART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U)
#define | __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) == 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) == 0U)
#define | __HAL_RCC_UCPD2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) == 0U)
#define | __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U)
#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U)

Detailed Description

Check whether the APB1 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CEC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) == 0U)

Definition at line 1605 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CEC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) != 0U)

Definition at line 1541 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U)

Definition at line 1570 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U)

Definition at line 1506 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U)

Definition at line 1616 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U)

Definition at line 1552 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U)

Definition at line 1613 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U)

Definition at line 1549 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) == 0U)

Definition at line 1575 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) != 0U)

Definition at line 1511 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U)

Definition at line 1599 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U)

Definition at line 1535 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U)

Definition at line 1600 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U)

Definition at line 1536 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U)

Definition at line 1602 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U)

Definition at line 1538 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U)

Definition at line 1622 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U)

Definition at line 1558 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U)

Definition at line 1619 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U)

Definition at line 1555 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U)

Definition at line 1594 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U)

Definition at line 1530 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U)

Definition at line 1597 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U)

Definition at line 1533 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U)

Definition at line 1614 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U)

Definition at line 1550 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U)

Definition at line 1572 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U)

Definition at line 1508 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U)

Definition at line 1580 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U)

Definition at line 1516 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U)

Definition at line 1582 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U)

Definition at line 1518 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U)

Definition at line 1561 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U)

Definition at line 1497 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U)

Definition at line 1563 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U)

Definition at line 1499 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) == 0U)

Definition at line 1565 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) != 0U)

Definition at line 1501 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U)

Definition at line 1567 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U)

Definition at line 1503 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U)

Definition at line 1568 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U)

Definition at line 1504 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) == 0U)

Definition at line 1608 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) != 0U)

Definition at line 1544 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) == 0U)

Definition at line 1611 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) != 0U)

Definition at line 1547 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U)

Definition at line 1584 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U)

Definition at line 1520 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U)

Definition at line 1585 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U)

Definition at line 1521 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U)

Definition at line 1586 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U)

Definition at line 1522 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U)

Definition at line 1588 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U)

Definition at line 1524 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U)

Definition at line 1591 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U)

Definition at line 1527 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U)

Definition at line 1578 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U)

Definition at line 1514 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U)

Definition at line 1573 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U)

Definition at line 1509 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB2 Peripheral Clock Enabled or Disabled Status

Defines
APB2 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB2 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U)
#define | __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U)
#define | __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U)
#define | __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U)
#define | __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U)

Detailed Description

Check whether the APB2 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U)

Definition at line 1659 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_ADC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U)

Definition at line 1647 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U)

Definition at line 1651 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U)

Definition at line 1639 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U)

Definition at line 1649 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U)

Definition at line 1637 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U)

Definition at line 1653 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U)

Definition at line 1641 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U)

Definition at line 1655 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U)

Definition at line 1643 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U)

Definition at line 1657 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U)

Definition at line 1645 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U)

Definition at line 1658 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U)

Definition at line 1646 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U)

Definition at line 1650 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U)

Definition at line 1638 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U)

Definition at line 1652 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U)

Definition at line 1640 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB Peripheral Force Release Reset

Defines
AHB Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB1 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)
#define | __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)
#define | __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
#define | __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
#define | __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)
#define | __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)
#define | __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U)
#define | __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)
#define | __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)
#define | __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
#define | __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
#define | __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)
#define | __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)

Detailed Description

Force or release AHB1 peripheral reset.

Define Documentation

#define __HAL_RCC_AES_FORCE_RESET ( ) SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)

Definition at line 1680 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_AES_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)

Definition at line 1694 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_AHB_FORCE_RESET ( ) WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU)

Definition at line 1669 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB_RELEASE_RESET ( ) WRITE_REG(RCC->AHBRSTR, 0x00000000U)

Definition at line 1683 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CRC_FORCE_RESET ( ) SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)

Definition at line 1675 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)

Definition at line 1689 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_FORCE_RESET ( ) SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)

Definition at line 1670 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)

Definition at line 1684 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_FORCE_RESET ( ) SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)

Definition at line 1672 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)

Definition at line 1686 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_FORCE_RESET ( ) SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)

Definition at line 1674 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)

Definition at line 1688 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_FORCE_RESET ( ) SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)

Definition at line 1677 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)

Definition at line 1691 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IOPORT Force Release Reset

Defines
IOPORT Force Release Reset
RCC Exported Macros

Force or release IO Port reset. More...

Defines

#define | __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)
#define | __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)

Detailed Description

Force or release IO Port reset.

Define Documentation

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)

Definition at line 1705 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)

Definition at line 1715 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)

Definition at line 1706 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)

Definition at line 1716 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)

Definition at line 1707 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)

Definition at line 1717 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)

Definition at line 1708 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)

Definition at line 1718 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)

Definition at line 1710 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)

Definition at line 1720 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_FORCE_RESET ( ) SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)

Definition at line 1712 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_RELEASE_RESET ( ) CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)

Definition at line 1722 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_IOP_FORCE_RESET ( ) WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU)

Definition at line 1704 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_IOP_RELEASE_RESET ( ) WRITE_REG(RCC->IOPRSTR, 0x00000000U)

Definition at line 1714 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_DeInit().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB1 Peripheral Force Release Reset

Defines
APB1 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)
#define | __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)
#define | __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)
#define | __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)
#define | __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)
#define | __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)
#define | __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)
#define | __HAL_RCC_LPUART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)
#define | __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)
#define | __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)
#define | __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)
#define | __HAL_RCC_UCPD2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)
#define | __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)
#define | __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)
#define | __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
#define | __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
#define | __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)
#define | __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)
#define | __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)
#define | __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)
#define | __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)
#define | __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)
#define | __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)
#define | __HAL_RCC_LPUART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)
#define | __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)
#define | __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)
#define | __HAL_RCC_UCPD2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)
#define | __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)
#define | __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)
#define | __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
#define | __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
#define | __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_APB1_FORCE_RESET ( ) WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU)

Definition at line 1732 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1_RELEASE_RESET ( ) WRITE_REG(RCC->APBRSTR1, 0x00000000U)

Definition at line 1796 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CEC_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)

Definition at line 1771 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CEC_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)

Definition at line 1834 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)

Definition at line 1744 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_CRS_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)

Definition at line 1807 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_DAC1_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)

Definition at line 1788 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)

Definition at line 1851 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)

Definition at line 1785 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)

Definition at line 1848 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)

Definition at line 1783 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)

Definition at line 1846 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)

Definition at line 1765 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)

Definition at line 1828 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)

Definition at line 1766 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)

Definition at line 1829 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)

Definition at line 1768 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)

Definition at line 1831 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)

Definition at line 1794 of file stm32g0xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)

Definition at line 1857 of file stm32g0xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM2_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)

Definition at line 1791 of file stm32g0xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)

Definition at line 1854 of file stm32g0xx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPUART1_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)

Definition at line 1760 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)

Definition at line 1823 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)

Definition at line 1763 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)

Definition at line 1826 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PWR_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)

Definition at line 1786 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_PWR_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)

Definition at line 1849 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_SPI2_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)

Definition at line 1746 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)

Definition at line 1809 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)

Definition at line 1748 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)

Definition at line 1811 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)

Definition at line 1735 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)

Definition at line 1798 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)

Definition at line 1737 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)

Definition at line 1800 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)

Definition at line 1739 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)

Definition at line 1802 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)

Definition at line 1741 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)

Definition at line 1804 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)

Definition at line 1742 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)

Definition at line 1805 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)

Definition at line 1774 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)

Definition at line 1837 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)

Definition at line 1777 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)

Definition at line 1840 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)

Definition at line 1750 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)

Definition at line 1813 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)

Definition at line 1751 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)

Definition at line 1814 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)

Definition at line 1752 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)

Definition at line 1815 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)

Definition at line 1754 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)

Definition at line 1817 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)

Definition at line 1757 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)

Definition at line 1820 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)

Definition at line 1780 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)

Definition at line 1843 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB2 Peripheral Force Release Reset

Defines
APB2 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
#define | __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
#define | __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
#define | __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)
#define | __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
#define | __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
#define | __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
#define | __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)
#define | __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_ADC_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)

Definition at line 1878 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_ADC_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)

Definition at line 1891 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_APB2_FORCE_RESET ( ) WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU)

Definition at line 1867 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) WRITE_REG(RCC->APBRSTR2, 0x00U)

Definition at line 1880 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_SPI1_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)

Definition at line 1870 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)

Definition at line 1883 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)

Definition at line 1868 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)

Definition at line 1881 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)

Definition at line 1872 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)

Definition at line 1885 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)

Definition at line 1874 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)

Definition at line 1887 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)

Definition at line 1876 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)

Definition at line 1889 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)

Definition at line 1877 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)

Definition at line 1890 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)

Definition at line 1869 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)

Definition at line 1882 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)

Definition at line 1871 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)

Definition at line 1884 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB Peripherals Clock Sleep Enable Disable

Defines
AHB Peripherals Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB peripherals clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
#define | __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
#define | __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)

Detailed Description

Enable or disable the AHB peripherals clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_AES_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)

Definition at line 1930 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_AES_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)

Definition at line 1917 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)

Definition at line 1925 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)

Definition at line 1912 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)

Definition at line 1919 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)

Definition at line 1906 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)

Definition at line 1921 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)

Definition at line 1908 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)

Definition at line 1923 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)

Definition at line 1910 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)

Definition at line 1927 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)

Definition at line 1914 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)

Definition at line 1924 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)

Definition at line 1911 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IOPORT Clock Sleep Enable Disable

Defines
IOPORT Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the IOPORT clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)

Detailed Description

Enable or disable the IOPORT clock during Low Power (Sleep) mode.

Note:
IOPORT clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)

Definition at line 1955 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)

Definition at line 1946 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)

Definition at line 1956 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)

Definition at line 1947 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)

Definition at line 1957 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)

Definition at line 1948 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)

Definition at line 1958 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)

Definition at line 1949 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)

Definition at line 1960 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)

Definition at line 1951 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)

Definition at line 1962 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)

Definition at line 1953 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB1 Peripheral Clock Sleep Enable Disable

Defines
APB1 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)
#define | __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)
#define | __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)
#define | __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)
#define | __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)
#define | __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)
#define | __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)
#define | __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)
#define | __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)
#define | __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)
#define | __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)
#define | __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)
#define | __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)
#define | __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)
#define | __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)

Detailed Description

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)

Definition at line 2078 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)

Definition at line 2014 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)

Definition at line 2049 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)

Definition at line 1985 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)

Definition at line 2095 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)

Definition at line 2031 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)

Definition at line 2092 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)

Definition at line 2028 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)

Definition at line 2090 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)

Definition at line 2026 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)

Definition at line 2072 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)

Definition at line 2008 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)

Definition at line 2073 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)

Definition at line 2009 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)

Definition at line 2075 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)

Definition at line 2011 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)

Definition at line 2101 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)

Definition at line 2037 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)

Definition at line 2098 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)

Definition at line 2034 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)

Definition at line 2067 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)

Definition at line 2003 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)

Definition at line 2070 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)

Definition at line 2006 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)

Definition at line 2093 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)

Definition at line 2029 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)

Definition at line 2051 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)

Definition at line 1987 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)

Definition at line 2053 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)

Definition at line 1989 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)

Definition at line 2055 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)

Definition at line 1991 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)

Definition at line 2040 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)

Definition at line 1976 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)

Definition at line 2042 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)

Definition at line 1978 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)

Definition at line 2044 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)

Definition at line 1980 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)

Definition at line 2046 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)

Definition at line 1982 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)

Definition at line 2047 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)

Definition at line 1983 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)

Definition at line 2081 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)

Definition at line 2017 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)

Definition at line 2084 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)

Definition at line 2020 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)

Definition at line 2057 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)

Definition at line 1993 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)

Definition at line 2058 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)

Definition at line 1994 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)

Definition at line 2059 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)

Definition at line 1995 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)

Definition at line 2061 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)

Definition at line 1997 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)

Definition at line 2064 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)

Definition at line 2000 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)

Definition at line 2087 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)

Definition at line 2023 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)

Definition at line 2052 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)

Definition at line 1988 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB2 Peripheral Clock Sleep Enable Disable

Defines
APB2 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)
#define | __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)
#define | __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)

Detailed Description

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)

Definition at line 2138 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)

Definition at line 2126 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)

Definition at line 2130 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)

Definition at line 2118 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)

Definition at line 2128 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)

Definition at line 2116 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)

Definition at line 2132 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)

Definition at line 2120 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)

Definition at line 2134 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)

Definition at line 2122 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)

Definition at line 2136 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)

Definition at line 2124 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)

Definition at line 2137 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)

Definition at line 2125 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)

Definition at line 2129 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)

Definition at line 2117 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)

Definition at line 2131 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)

Definition at line 2119 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET)
#define | __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET)
#define | __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET)
#define | __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET)
#define | __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) == RESET)

Detailed Description

Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) == RESET)

Definition at line 2177 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) != RESET)

Definition at line 2164 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET)

Definition at line 2172 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)

Definition at line 2159 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET)

Definition at line 2166 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)

Definition at line 2153 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) == RESET)

Definition at line 2168 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) != RESET)

Definition at line 2155 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET)

Definition at line 2170 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET)

Definition at line 2157 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET)

Definition at line 2174 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET)

Definition at line 2161 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET)

Definition at line 2171 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)

Definition at line 2158 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IOPORT Clock Sleep Enabled or Disabled Status

Defines
IOPORT Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)!= RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET)

Detailed Description

Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET)

Definition at line 2205 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET)

Definition at line 2194 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET)

Definition at line 2206 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET)

Definition at line 2195 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET)

Definition at line 2207 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET)

Definition at line 2196 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET)

Definition at line 2208 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET)

Definition at line 2197 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET)

Definition at line 2210 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)!= RESET)

Definition at line 2199 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET)

Definition at line 2212 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET)

Definition at line 2201 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB1 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB1 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) != RESET)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET)
#define | __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET)
#define | __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) != RESET)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) != RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)!= RESET)
#define | __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)!= RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) != RESET)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) != RESET)
#define | __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) != RESET)
#define | __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) != RESET)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) != RESET)
#define | __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) != RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) == RESET)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET)
#define | __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET)
#define | __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) == RESET)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) == RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)== RESET)
#define | __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)== RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) == RESET)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) == RESET)
#define | __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) == RESET)
#define | __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) == RESET)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) == RESET)
#define | __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) == RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) == RESET)

Detailed Description

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) == RESET)

Definition at line 2345 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) != RESET)

Definition at line 2273 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET)

Definition at line 2312 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET)

Definition at line 2240 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) == RESET)

Definition at line 2362 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) != RESET)

Definition at line 2290 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET)

Definition at line 2359 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET)

Definition at line 2287 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) == RESET)

Definition at line 2357 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) != RESET)

Definition at line 2285 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET)

Definition at line 2339 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET)

Definition at line 2267 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET)

Definition at line 2340 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET)

Definition at line 2268 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) == RESET)

Definition at line 2342 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) != RESET)

Definition at line 2270 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) == RESET)

Definition at line 2368 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) != RESET)

Definition at line 2296 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) == RESET)

Definition at line 2365 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) != RESET)

Definition at line 2293 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)== RESET)

Definition at line 2334 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)!= RESET)

Definition at line 2262 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)== RESET)

Definition at line 2337 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)!= RESET)

Definition at line 2265 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET)

Definition at line 2360 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET)

Definition at line 2288 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET)

Definition at line 2314 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET)

Definition at line 2242 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET)

Definition at line 2316 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET)

Definition at line 2244 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) == RESET)

Definition at line 2318 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) != RESET)

Definition at line 2246 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET)

Definition at line 2299 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET)

Definition at line 2227 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET)

Definition at line 2301 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET)

Definition at line 2229 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) == RESET)

Definition at line 2303 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) != RESET)

Definition at line 2231 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) == RESET)

Definition at line 2306 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) != RESET)

Definition at line 2234 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) == RESET)

Definition at line 2309 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) != RESET)

Definition at line 2237 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) == RESET)

Definition at line 2348 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) != RESET)

Definition at line 2276 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) == RESET)

Definition at line 2351 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) != RESET)

Definition at line 2279 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET)

Definition at line 2320 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET)

Definition at line 2248 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET)

Definition at line 2322 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET)

Definition at line 2250 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET)

Definition at line 2325 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET)

Definition at line 2253 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) == RESET)

Definition at line 2328 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) != RESET)

Definition at line 2256 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) == RESET)

Definition at line 2331 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) != RESET)

Definition at line 2259 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET)

Definition at line 2354 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET)

Definition at line 2282 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET)

Definition at line 2315 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET)

Definition at line 2243 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB2 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB2 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET)

Detailed Description

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET)

Definition at line 2407 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET)

Definition at line 2394 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET)

Definition at line 2399 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET)

Definition at line 2386 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET)

Definition at line 2397 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET)

Definition at line 2384 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET)

Definition at line 2401 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET)

Definition at line 2388 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET)

Definition at line 2403 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET)

Definition at line 2390 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET)

Definition at line 2405 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET)

Definition at line 2392 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET)

Definition at line 2406 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET)

Definition at line 2393 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET)

Definition at line 2398 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET)

Definition at line 2385 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET)

Definition at line 2400 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET)

Definition at line 2387 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Backup Domain Reset

Defines
RCC Backup Domain Reset
RCC Exported Macros

Defines

#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Define Documentation

#define __HAL_RCC_BACKUPRESET_FORCE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Macros to force or release the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.
Return values:
None

Definition at line 2424 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Definition at line 2426 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC RTC Clock Configuration

Defines
RCC RTC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Macro to get the RTC clock source.

Define Documentation

#define __HAL_RCC_GET_RTC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))

Macro to get the RTC clock source.

Return values:
The returned value can be one of the following:
  • RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected

Definition at line 2665 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_RTC_CONFIG ( __RTC_CLKSOURCE__ ) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))

Macros to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it cannot be changed unless the Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by a Power On Reset (POR).
Parameters:
__RTC_CLKSOURCE__ specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values:
None

Definition at line 2654 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_DISABLE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Definition at line 2446 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Macros to enable or disable the RTC clock.

Note:
As the RTC is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the RTC (to be done once after reset).
These macros must be used after the RTC clock source was selected.
Return values:
None

Definition at line 2444 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Clock Configuration

Defines
RCC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Macros to disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_HSI_CONFIG(__HSIDIV__) MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__))
Macro to configure the HSISYS clock.
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON)
Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON)
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Macro to configure the PLL multiplication factor.
#define | __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
#define | __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the Microcontroller output clock.
#define | __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the Microcontroller output clock 2.

Define Documentation

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values:
The oscillator used as PLL clock source. The returned value can be one of the following:
  • RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source.

Definition at line 2780 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_PLLCLKOUT_CONFIG ( __PLLCLOCKOUT__ ) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)

Parameters:
__PLLCLOCKOUT__ specifies the output PLL clock to be checked. This parameter can be one of the following values:
  • RCC_PLLPCLK This clock may be used to generate the clock for ADC, I2S1.
  • RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz)
Return values:
SET / RESET
Note:
(*) RCC_PLLQCLK availability depends on devices

Definition at line 2831 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) (RCC->CFGR & RCC_CFGR_SWS)

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source.
  • RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source.

Definition at line 2856 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do {                                        \
                                              if((__STATE__) == RCC_HSE_ON)          \
                                              {                                      \
                                                SET_BIT(RCC->CR, RCC_CR_HSEON);      \
                                              }                                      \
                                              else if((__STATE__) == RCC_HSE_BYPASS) \
                                              {                                      \
                                                SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
                                                SET_BIT(RCC->CR, RCC_CR_HSEON);      \
                                              }                                      \
                                              else                                   \
                                              {                                      \
                                                CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
                                                CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
                                              }                                      \
                                            } while(0U)

Macro to configure the External High Speed oscillator (HSE).

Note:
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__ specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON Turn ON the HSE oscillator.
  • RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
Return values:
None

Definition at line 2554 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON)

Definition at line 2618 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSI48ON)

Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).

Note:
The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
After enabling the HSI48, the application software should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2616 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICALIBRATIONVALUE__ ) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__HSICALIBRATIONVALUE__ specifies the calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 127.
Return values:
None

Definition at line 2487 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CONFIG ( __HSIDIV__ ) MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__))

Macro to configure the HSISYS clock.

Parameters:
__HSIDIV__ specifies the HSI16 division factor. This parameter can be one of the following values:
  • RCC_HSI_DIV1 HSI clock source is divided by 1
  • RCC_HSI_DIV2 HSI clock source is divided by 2
  • RCC_HSI_DIV4 HSI clock source is divided by 4
  • RCC_HSI_DIV8 HSI clock source is divided by 8
  • RCC_HSI_DIV16 HSI clock source is divided by 16
  • RCC_HSI_DIV32 HSI clock source is divided by 32
  • RCC_HSI_DIV64 HSI clock source is divided by 64
  • RCC_HSI_DIV128 HSI clock source is divided by 128

Definition at line 2515 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSION)

Macros to disable the Internal High Speed oscillator (HSI).

Note:
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values:
None

Definition at line 2477 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSION)

Macros to enable the Internal High Speed oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2468 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSISTOP_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

Definition at line 2501 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSIKERON)

Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

Note:
Keeping the HSI ON in STOP mode allows to avoid slowing down the communication speed because of the HSI startup time.
The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2499 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do {                                          \
                                              if((__STATE__) == RCC_LSE_ON)            \
                                              {                                        \
                                                SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                                              }                                        \
                                              else if((__STATE__) == RCC_LSE_BYPASS)   \
                                              {                                        \
                                                SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
                                                SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                                              }                                        \
                                              else                                     \
                                              {                                        \
                                                CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
                                                CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
                                              }                                        \
                                            } while(0U)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__ specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON Turn ON the LSE oscillator.
  • RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
Return values:
None

Definition at line 2591 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSEDRIVE_CONFIG ( __LSEDRIVE__ ) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Note:
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
Parameters:
__LSEDRIVE__ specifies the new state of the LSE drive capability. This parameter can be one of the following values:
  • RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
  • RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
  • RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
  • RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Return values:
None

Definition at line 2872 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_LSI_DISABLE ( ) CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

Definition at line 2529 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) SET_BIT(RCC->CSR, RCC_CSR_LSION)

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
Return values:
None

Definition at line 2527 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

Macro to configure the Microcontroller output clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK MCO output disabled
  • RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
  • RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
  • RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
  • RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
  • RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
  • RCC_MCO1SOURCE_PLLPCLK PLLP output clock selected as MCO source
  • RCC_MCO1SOURCE_PLLQCLK PLLQ output clock selected as MCO source
  • RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO source
  • RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source
  • RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 MCO clock source is divided by 1
  • RCC_MCODIV_2 MCO clock source is divided by 2
  • RCC_MCODIV_4 MCO clock source is divided by 4
  • RCC_MCODIV_8 MCO clock source is divided by 8
  • RCC_MCODIV_16 MCO clock source is divided by 16
  • RCC_MCODIV_32 MCO clock source is divided by 32
  • RCC_MCODIV_64 MCO clock source is divided by 64
  • RCC_MCODIV_128 MCO clock source is divided by 128
  • RCC_MCODIV_256 MCO clock source is divided by 256
  • RCC_MCODIV_512 MCO clock source is divided by 512
  • RCC_MCODIV_1024 MCO clock source is divided by 1024

Definition at line 2908 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_MCO2_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

Macro to configure the Microcontroller output clock 2.

Parameters:
__MCOCLKSOURCE__ specifies the MCO2 clock source. This parameter can be one of the following values:
  • RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled
  • RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source
  • RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 sourcee
  • RCC_MCO2SOURCE_PLLCLK Main PLL clock selected as MCO2 source
  • RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source
  • RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLPCLK PLLP output clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLQCLK PLLQ output clock selected as MCO2 source
  • RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source
  • RCC_MCO2SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO2 source
  • RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCO2DIV_1 MCO2 clock source is divided by 1
  • RCC_MCO2DIV_2 MCO2 clock source is divided by 2
  • RCC_MCO2DIV_4 MCO2 clock source is divided by 4
  • RCC_MCO2DIV_8 MCO2 clock source is divided by 8
  • RCC_MCO2DIV_16 MCO2 clock source is divided by 16
  • RCC_MCO2DIV_32 MCO2 clock source is divided by 32
  • RCC_MCO2DIV_64 MCO2 clock source is divided by 64
  • RCC_MCO2DIV_128 MCO2 clock source is divided by 128
  • RCC_MCO2DIV_256 MCO2 clock source is divided by 256
  • RCC_MCO2DIV_512 MCO2 clock source is divided by 512
  • RCC_MCO2DIV_1024 MCO2 clock source is divided by 1024

Definition at line 2943 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PLL_CONFIG | ( | __PLLSOURCE__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__,
 |  | __PLLQ__,
 |  | __PLLR__
 | ) |
Value:
MODIFY_REG(RCC->PLLCFGR,                                                   \
             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |     \
              RCC_PLLCFGR_PLLP   | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR),     \
             ((uint32_t) (__PLLSOURCE__)                      |             \
              (uint32_t) (__PLLM__)                           |             \
              (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) |             \
              (uint32_t) (__PLLP__)                           |             \
              (uint32_t) (__PLLQ__)                           |             \
              (uint32_t) (__PLLR__)))

Macro to configure the main PLL clock source, multiplication and division factors.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__ specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
__PLLM__ specifies the division factor for PLL VCO input clock. This parameter must be a value of RCC_PLLM_Clock_Divider.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. It is recommended to select a frequency of 16 MHz to limit PLL jitter.
Parameters:
__PLLN__ specifies the multiplication factor for PLL VCO output clock. This parameter must be a number between 8 and 86.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz.
Parameters:
__PLLP__ | specifies the division factor for ADC clock. This parameter must be a value of PLLP Clock Divider.
__PLLQ__ | specifies the division factor for RBG & HS Timers clocks.(1) This parameter must be a value of PLLQ Clock Divider
Note:
(1)__PLLQ__ parameter availability depends on devices
If the USB FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the RNG needs a frequency lower than or equal to 48 MHz to work correctly.
Parameters:
__PLLR__ specifies the division factor for the main system clock. This parameter must be a value of RCC_PLLR_Clock_Divider
Note:
You have to set the PLL parameters correctly to not exceed 64MHZ.
Return values:
None

Definition at line 2752 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLLON)

Definition at line 2686 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLLON)

Definition at line 2684 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLM_CONFIG ( __PLLM__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))

Macro to configure the PLL multiplication factor.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLM__ specifies the division factor for PLL VCO input clock This parameter must be a value of RCC_PLLM_Clock_Divider.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. It is recommended to select a frequency of 16 MHz to limit PLL jitter.
Return values:
None

Definition at line 2711 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLL clock source.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__ specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Return values:
None

Definition at line 2698 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_DISABLE ( __PLLCLOCKOUT__ ) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)

Note:
Disabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot be stopped if used as System Clock.
(*) RCC_PLLQCLK availability depends on devices
Parameters:
__PLLCLOCKOUT__ specifies the PLL clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLLPCLK This clock may be used to generate the clock for the ADC, I2S1.
  • RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz)
Return values:
None

Definition at line 2816 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_ENABLE ( __PLLCLOCKOUT__ ) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)

Note:
Enabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot be stopped if used as System Clock.
(*) RCC_PLLQCLK availability depends on devices
Parameters:
__PLLCLOCKOUT__ specifies the PLL clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLLPCLK This clock is used to generate the clock for the ADC.
  • RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz)
Return values:
None

Definition at line 2798 of file stm32g0xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SYSCLK_CONFIG ( __SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__SYSCLKSOURCE__ specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
  • RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source.
Return values:
None

Definition at line 2844 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear RCC interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the RCC interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check whether the selected RCC flag is set or not.

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (RCC->CICR = (__INTERRUPT__))

Clear RCC interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_CSS HSE Clock security system interrupt
  • RCC_IT_LSECSS LSE Clock security system interrupt
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Return values:
None

Definition at line 3001 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (RCC->CSR |= RCC_CSR_RMVF)

Set RMVF bit to clear the reset flags.

The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.

Return values:
None

Definition at line 3025 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))

Disable RCC interrupt.

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Return values:
None

Definition at line 2984 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(RCC->CIER, (__INTERRUPT__))

Enable RCC interrupt.

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Return values:
None

Definition at line 2969 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GET_FLAG ( __FLAG__ )
Value:
(((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR :                    \
      ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR :              \
       ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR :                \
        ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) &  \
     (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)

Check whether the selected RCC flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY HSI oscillator clock ready
  • RCC_FLAG_HSERDY HSE oscillator clock ready
  • RCC_FLAG_PLLRDY Main PLL clock ready
  • RCC_FLAG_LSERDY LSE oscillator clock ready
  • RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
  • RCC_FLAG_LSIRDY LSI oscillator clock ready
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
  • RCC_FLAG_PWRRST BOR or POR/PDR reset
  • RCC_FLAG_OBLRST OBLRST reset
  • RCC_FLAG_PINRST Pin reset
  • RCC_FLAG_SFTRST Software reset
  • RCC_FLAG_IWDGRST Independent Watchdog reset
  • RCC_FLAG_WWDGRST Window Watchdog reset
  • RCC_FLAG_LPWRRST Low Power reset
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 3049 of file stm32g0xx_hal_rcc.h.

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the RCC interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_CSS HSE Clock security system interrupt
  • RCC_IT_LSECSS LSE Clock security system interrupt
  • RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 3018 of file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx Private Constants

Defines
RCCEx Private Constants
RCCEx

Defines

#define | PLL_TIMEOUT_VALUE 100U /* 100 ms (minimum Tick + 1) */
#define | LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | LSCO_GPIO_PORT GPIOA
#define | LSCO_PIN GPIO_PIN_2

Define Documentation

#define LSCO_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 45 of file stm32g0xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define LSCO_GPIO_PORT GPIOA

Definition at line 46 of file stm32g0xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define LSCO_PIN GPIO_PIN_2

Definition at line 47 of file stm32g0xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define PLL_TIMEOUT_VALUE 100U /* 100 ms (minimum Tick + 1) */

Definition at line 43 of file stm32g0xx_hal_rcc_ex.c.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RCCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLL.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) and RCC_BDCR register are set to their reset values.

Function Documentation

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks: I2C1, I2S1, USART1, RTC, ADC, LPTIM1 (1), LPTIM2 (1), TIM1 (2), TIM15 (1)(2), USART2 (2), LPUART1 (1), CEC (1) and RNG (1)
Note:
(1) Peripheral is not available on all devices
(2) Peripheral clock selection is not available on all devices
Return values:
None

Definition at line 469 of file stm32g0xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_CEC_SOURCE, __HAL_RCC_GET_FDCAN_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_I2S1_SOURCE, __HAL_RCC_GET_I2S2_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_LPUART2_SOURCE, __HAL_RCC_GET_RNG_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_TIM15_SOURCE, __HAL_RCC_GET_TIM1_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, __HAL_RCC_GET_USB_SOURCE, RCC_PeriphCLKInitTypeDef::AdcClockSelection, RCC_PeriphCLKInitTypeDef::CecClockSelection, RCC_PeriphCLKInitTypeDef::FdcanClockSelection, RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2s1ClockSelection, RCC_PeriphCLKInitTypeDef::I2s2ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart2ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2S1, RCC_PERIPHCLK_I2S2, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_LPUART2, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_TIM1, RCC_PERIPHCLK_TIM15, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Tim15ClockSelection, RCC_PeriphCLKInitTypeDef::Tim1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Return the peripheral clock frequency for peripherals with clock source from PLL.

Note:
Return 0 if peripheral clock identifier not managed by this API
Parameters:
PeriphClk Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (1)
  • RCC_PERIPHCLK_I2S1 I2S1 peripheral clock
  • RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (1)
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_USART2 USART2 peripheral clock (1)(2)
  • RCC_PERIPHCLK_USART3 USART3 peripheral clock (1)
  • RCC_PERIPHCLK_RNG RNG peripheral clock (1)
  • RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2)
  • RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2)
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1)
  • RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1)
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock(1)
  • RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock(1)
  • RCC_PERIPHCLK_CEC CEC peripheral clock (1)
  • RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (1)
  • RCC_PERIPHCLK_USB USB peripheral clock (1)
Note:
(1) Peripheral not available on all devices
(2) Peripheral Clock configuration not available on all devices
Return values:
Frequency in Hz

Definition at line 610 of file stm32g0xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_CEC_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_I2S1_SOURCE, __HAL_RCC_GET_I2S2_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_LPUART2_SOURCE, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_PLLCLKOUT_CONFIG, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, assert_param, EXTERNAL_I2S1_CLOCK_VALUE, EXTERNAL_I2S2_CLOCK_VALUE, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetSysClockFreq(), HSE_VALUE, HSI48_VALUE, HSI_VALUE, IS_RCC_PERIPHCLOCK, LSE_VALUE, LSI_VALUE, RCC_ADCCLKSOURCE_HSI, RCC_ADCCLKSOURCE_PLLADC, RCC_ADCCLKSOURCE_SYSCLK, RCC_CECCLKSOURCE_HSI_DIV488, RCC_CECCLKSOURCE_LSE, RCC_FDCANCLKSOURCE_HSE, RCC_FDCANCLKSOURCE_PCLK1, RCC_FDCANCLKSOURCE_PLL, RCC_I2C1CLKSOURCE_HSI, RCC_I2C1CLKSOURCE_PCLK1, RCC_I2C1CLKSOURCE_SYSCLK, RCC_I2C2CLKSOURCE_HSI, RCC_I2C2CLKSOURCE_PCLK1, RCC_I2C2CLKSOURCE_SYSCLK, RCC_I2S1CLKSOURCE_EXT, RCC_I2S1CLKSOURCE_HSI, RCC_I2S1CLKSOURCE_PLL, RCC_I2S1CLKSOURCE_SYSCLK, RCC_I2S2CLKSOURCE_EXT, RCC_I2S2CLKSOURCE_HSI, RCC_I2S2CLKSOURCE_PLL, RCC_I2S2CLKSOURCE_SYSCLK, RCC_LPTIM1CLKSOURCE_HSI, RCC_LPTIM1CLKSOURCE_LSE, RCC_LPTIM1CLKSOURCE_LSI, RCC_LPTIM1CLKSOURCE_PCLK1, RCC_LPTIM2CLKSOURCE_HSI, RCC_LPTIM2CLKSOURCE_LSE, RCC_LPTIM2CLKSOURCE_LSI, RCC_LPTIM2CLKSOURCE_PCLK1, RCC_LPUART1CLKSOURCE_HSI, RCC_LPUART1CLKSOURCE_LSE, RCC_LPUART1CLKSOURCE_PCLK1, RCC_LPUART1CLKSOURCE_SYSCLK, RCC_LPUART2CLKSOURCE_HSI, RCC_LPUART2CLKSOURCE_LSE, RCC_LPUART2CLKSOURCE_PCLK1, RCC_LPUART2CLKSOURCE_SYSCLK, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2S1, RCC_PERIPHCLK_I2S2, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_LPUART2, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_TIM1, RCC_PERIPHCLK_TIM15, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PLLPCLK, RCC_PLLQCLK, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_RNGCLKSOURCE_HSI_DIV8, RCC_RNGCLKSOURCE_PLL, RCC_RNGCLKSOURCE_SYSCLK, RCC_RTCCLKSOURCE_HSE_DIV32, RCC_RTCCLKSOURCE_LSE, RCC_RTCCLKSOURCE_LSI, RCC_TIM15CLKSOURCE_PCLK1, RCC_TIM15CLKSOURCE_PLL, RCC_TIM1CLKSOURCE_PCLK1, RCC_TIM1CLKSOURCE_PLL, RCC_USART1CLKSOURCE_HSI, RCC_USART1CLKSOURCE_LSE, RCC_USART1CLKSOURCE_PCLK1, RCC_USART1CLKSOURCE_SYSCLK, RCC_USART2CLKSOURCE_HSI, RCC_USART2CLKSOURCE_LSE, RCC_USART2CLKSOURCE_PCLK1, RCC_USART2CLKSOURCE_SYSCLK, RCC_USART3CLKSOURCE_HSI, RCC_USART3CLKSOURCE_LSE, RCC_USART3CLKSOURCE_PCLK1, RCC_USART3CLKSOURCE_SYSCLK, RCC_USBCLKSOURCE_HSE, RCC_USBCLKSOURCE_HSI48, and RCC_USBCLKSOURCE_PLL.

Referenced by HAL_I2S_Init().

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit pointer to a RCC_PeriphCLKInitTypeDef structure that contains a field PeriphClockSelection which can be a combination of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (2)
  • RCC_PERIPHCLK_I2S1 I2S1 peripheral clock
  • RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (1)
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_CEC CEC peripheral clock (1)
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1)
  • RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1)
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock (1)
  • RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock (1)
  • RCC_PERIPHCLK_RNG RNG peripheral clock (1)
  • RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2)
  • RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2)
  • RCC_PERIPHCLK_USART2 USART2 peripheral clock (2)
  • RCC_PERIPHCLK_USART3 USART3 peripheral clock (2)
  • RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (1)
  • RCC_PERIPHCLK_USB USB peripheral clock (1)
Note:
(1) Peripherals are not available on all devices
(2) Peripherals clock selection is not available on all devices
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source: in this case the access to Backup domain is enabled.
Return values:
HAL status

Definition at line 112 of file stm32g0xx_hal_rcc_ex.c.

References __HAL_RCC_ADC_CONFIG, __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_CEC_CONFIG, __HAL_RCC_FDCAN_CONFIG, __HAL_RCC_I2C1_CONFIG, __HAL_RCC_I2C2_CONFIG, __HAL_RCC_I2S1_CONFIG, __HAL_RCC_I2S2_CONFIG, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM2_CONFIG, __HAL_RCC_LPUART1_CONFIG, __HAL_RCC_LPUART2_CONFIG, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, __HAL_RCC_RNG_CONFIG, __HAL_RCC_RTC_CONFIG, __HAL_RCC_TIM15_CONFIG, __HAL_RCC_TIM1_CONFIG, __HAL_RCC_USART1_CONFIG, __HAL_RCC_USART2_CONFIG, __HAL_RCC_USART3_CONFIG, __HAL_RCC_USB_CONFIG, RCC_PeriphCLKInitTypeDef::AdcClockSelection, assert_param, RCC_PeriphCLKInitTypeDef::CecClockSelection, RCC_PeriphCLKInitTypeDef::FdcanClockSelection, HAL_GetTick(), RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2s1ClockSelection, RCC_PeriphCLKInitTypeDef::I2s2ClockSelection, IS_RCC_ADCCLKSOURCE, IS_RCC_CECCLKSOURCE, IS_RCC_FDCANCLKSOURCE, IS_RCC_I2C1CLKSOURCE, IS_RCC_I2C2CLKSOURCE, IS_RCC_I2S1CLKSOURCE, IS_RCC_I2S2CLKSOURCE, IS_RCC_LPTIM1CLKSOURCE, IS_RCC_LPTIM2CLKSOURCE, IS_RCC_LPUART1CLKSOURCE, IS_RCC_LPUART2CLKSOURCE, IS_RCC_PERIPHCLOCK, IS_RCC_RNGCLKSOURCE, IS_RCC_RTCCLKSOURCE, IS_RCC_TIM15CLKSOURCE, IS_RCC_TIM1CLKSOURCE, IS_RCC_USART1CLKSOURCE, IS_RCC_USART2CLKSOURCE, IS_RCC_USART3CLKSOURCE, IS_RCC_USBCLKSOURCE, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart2ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_ADCCLKSOURCE_PLLADC, RCC_DBP_TIMEOUT_VALUE, RCC_FDCANCLKSOURCE_PLL, RCC_I2S1CLKSOURCE_PLL, RCC_I2S2CLKSOURCE_PLL, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_FDCAN, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2S1, RCC_PERIPHCLK_I2S2, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_LPUART2, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_TIM1, RCC_PERIPHCLK_TIM15, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PLLPCLK, RCC_PLLQCLK, RCC_RNGCLKSOURCE_PLL, RCC_RTCCLKSOURCE_NONE, RCC_TIM15CLKSOURCE_PLL, RCC_TIM1CLKSOURCE_PLL, RCC_USBCLKSOURCE_PLL, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Tim15ClockSelection, RCC_PeriphCLKInitTypeDef::Tim1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Clock management functions

Functions
Extended Clock management functions
RCCEx Exported Functions

Extended Clock management functions. More...

Functions

void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.

Detailed Description

Extended Clock management functions.

 ===============================================================================
                ##### Extended clock management functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the
    activation or deactivation of LSE CSS, Low speed clock output and
    clock after wake-up from STOP mode.

Function Documentation

void HAL_RCCEx_DisableLSCO ( void )

Disable the Low Speed clock output.

Return values:
None

Definition at line 1263 of file stm32g0xx_hal_rcc_ex.c.

References __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, HAL_PWR_DisableBkUpAccess(), and HAL_PWR_EnableBkUpAccess().

void HAL_RCCEx_EnableLSCO ( uint32_t LSCOSource )

Select the Low Speed clock source to output on LSCO pin (PA2).

Parameters:
LSCOSource specifies the Low Speed clock source to output. This parameter can be one of the following values:
  • RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
  • RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
Return values:
None

Definition at line 1216 of file stm32g0xx_hal_rcc_ex.c.

References __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, assert_param, GPIO_MODE_ANALOG, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), HAL_PWR_DisableBkUpAccess(), HAL_PWR_EnableBkUpAccess(), IS_RCC_LSCOSOURCE, LSCO_CLK_ENABLE, LSCO_GPIO_PORT, LSCO_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, and GPIO_InitTypeDef::Speed.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Clock Recovery System Control functions

Functions
Extended Clock Recovery System Control functions
RCCEx Exported Functions

Extended Clock Recovery System Control functions. More...

Functions

void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended Clock Recovery System Control functions.

 ===============================================================================
                ##### Extended Clock Recovery System Control functions  #####
 ===============================================================================
    [..]
      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:

      (#) In System clock config, HSI48 needs to be enabled

      (#) Enable CRS clock in IP MSP init which will use CRS functions

      (#) Call CRS functions as follows:
          (##) Prepare synchronization configuration necessary for HSI48 calibration
              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
                        and also HSI48 oscillator smooth trimming.
              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
                        directly reload value with target and synchronization frequencies values
          (##) Call function HAL_RCCEx_CRSConfig which
              (+++) Resets CRS registers to their default values.
              (+++) Configures CRS registers with synchronization configuration
              (+++) Enables automatic calibration and frequency error counter feature
           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
           should be used as SYNC signal.

          (##) A polling function is provided to wait for complete synchronization
              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
              (+++) According to CRS status, user can decide to adjust again the calibration or continue
                        application if synchronization is OK

      (#) User can retrieve information related to synchronization in calling function
            HAL_RCCEx_CRSGetSynchronizationInfo()

      (#) Regarding synchronization status and synchronization information, user can try a new calibration
           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
           incremented), while when it is detected during the upcounting phase it means that the actual frequency
           is higher (and that the TRIM value should be decremented).

      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
              (++) Call function HAL_RCCEx_CRSConfig()
              (++) Enable CRS_IRQn (thanks to NVIC functions)
              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
              (++) Implement CRS status management in the following user callbacks called from
                   HAL_RCCEx_CRS_IRQHandler():
                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
                   (+++) HAL_RCCEx_CRS_ErrorCallback()

      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)

Function Documentation

void HAL_RCCEx_CRS_ErrorCallback ( uint32_t Error )

RCCEx Clock Recovery System Error interrupt callback.

Parameters:
Error Combination of Error status. This parameter can be a combination of the following values:
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF
Return values:
none

Definition at line 1641 of file stm32g0xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_ExpectedSyncCallback ( void )

RCCEx Clock Recovery System Expected SYNC interrupt callback.

Return values:
none

Definition at line 1625 of file stm32g0xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_IRQHandler ( void )

Handle the Clock Recovery System interrupt request.

Return values:
None

Definition at line 1538 of file stm32g0xx_hal_rcc_ex.c.

References HAL_RCCEx_CRS_ErrorCallback(), HAL_RCCEx_CRS_ExpectedSyncCallback(), HAL_RCCEx_CRS_SyncOkCallback(), HAL_RCCEx_CRS_SyncWarnCallback(), RCC_CRS_FLAG_ERR, RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_IT_ERR, RCC_CRS_IT_ESYNC, RCC_CRS_IT_SYNCOK, RCC_CRS_IT_SYNCWARN, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, and RCC_CRS_TRIMOVF.

void HAL_RCCEx_CRS_SyncOkCallback ( void )

RCCEx Clock Recovery System SYNCOK interrupt callback.

Return values:
none

Definition at line 1603 of file stm32g0xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_SyncWarnCallback ( void )

RCCEx Clock Recovery System SYNCWARN interrupt callback.

Return values:
none

Definition at line 1614 of file stm32g0xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRSConfig ( RCC_CRSInitTypeDef * pInit )

Start automatic synchronization for polling mode.

Parameters:
pInit Pointer on RCC_CRSInitTypeDef structure
Return values:
None

Definition at line 1370 of file stm32g0xx_hal_rcc_ex.c.

References __HAL_RCC_CRS_FORCE_RESET, __HAL_RCC_CRS_RELEASE_RESET, assert_param, RCC_CRSInitTypeDef::ErrorLimitValue, RCC_CRSInitTypeDef::HSI48CalibrationValue, IS_RCC_CRS_ERRORLIMIT, IS_RCC_CRS_HSI48CALIBRATION, IS_RCC_CRS_RELOADVALUE, IS_RCC_CRS_SYNC_DIV, IS_RCC_CRS_SYNC_POLARITY, IS_RCC_CRS_SYNC_SOURCE, RCC_CRSInitTypeDef::Polarity, RCC_CRSInitTypeDef::Prescaler, RCC_CRSInitTypeDef::ReloadValue, and RCC_CRSInitTypeDef::Source.

void HAL_RCCEx_CRSGetSynchronizationInfo ( RCC_CRSSynchroInfoTypeDef * pSynchroInfo )

Return synchronization info.

Parameters:
pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
Return values:
None

Definition at line 1422 of file stm32g0xx_hal_rcc_ex.c.

References assert_param, RCC_CRSSynchroInfoTypeDef::FreqErrorCapture, RCC_CRSSynchroInfoTypeDef::FreqErrorDirection, RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue, and RCC_CRSSynchroInfoTypeDef::ReloadValue.

void HAL_RCCEx_CRSSoftwareSynchronizationGenerate ( void )

Generate the software synchronization event.

Return values:
None

Definition at line 1412 of file stm32g0xx_hal_rcc_ex.c.

uint32_t HAL_RCCEx_CRSWaitSynchronization ( uint32_t Timeout )

Wait for CRS Synchronization status.

Parameters:
Timeout Duration of the timeout
Note:
Timeout is based on the maximum time to receive a SYNC event based on synchronization frequency.
If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
Return values:
Combination of Synchronization status This parameter can be a combination of the following values:
  • RCC_CRS_TIMEOUT
  • RCC_CRS_SYNCOK
  • RCC_CRS_SYNCWARN
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF

Definition at line 1455 of file stm32g0xx_hal_rcc_ex.c.

References __HAL_RCC_CRS_CLEAR_FLAG, __HAL_RCC_CRS_GET_FLAG, HAL_GetTick(), RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, RCC_CRS_SYNCOK, RCC_CRS_SYNCWARN, RCC_CRS_TIMEOUT, and RCC_CRS_TRIMOVF.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32g0xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
uint32_t | Usart1ClockSelection
uint32_t | Usart2ClockSelection
uint32_t | Usart3ClockSelection
uint32_t | Lpuart1ClockSelection
uint32_t | Lpuart2ClockSelection
uint32_t | I2c1ClockSelection
uint32_t | I2c2ClockSelection
uint32_t | I2s1ClockSelection
uint32_t | I2s2ClockSelection
uint32_t | Lptim1ClockSelection
uint32_t | Lptim2ClockSelection
uint32_t | RngClockSelection
uint32_t | AdcClockSelection
uint32_t | CecClockSelection
uint32_t | Tim1ClockSelection
uint32_t | Tim15ClockSelection
uint32_t | RTCClockSelection
uint32_t | UsbClockSelection
uint32_t | FdcanClockSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 46 of file stm32g0xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::AdcClockSelection

Specifies ADC interface clock source This parameter can be a value of RCC ADC Clock Source

Definition at line 99 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::CecClockSelection

Specifies CEC Clock clock source This parameter can be a value of RCC CEC Clock Source

Definition at line 102 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::FdcanClockSelection

Specifies FDCAN Clock clock source This parameter can be a value of RCC FDCAN Clock Source

Definition at line 120 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c1ClockSelection

Specifies I2C1 clock source This parameter can be a value of RCC I2C1 Clock Source

Definition at line 73 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c2ClockSelection

Specifies I2C2 clock source This parameter can be a value of RCC I2C2 Clock Source

Definition at line 77 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2s1ClockSelection

Specifies I2S1 clock source This parameter can be a value of RCC I2S1 Clock Source

Definition at line 81 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2s2ClockSelection

Specifies I2S2 clock source This parameter can be a value of RCC I2S2 Clock Source

Definition at line 84 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection

Specifies LPTIM1 clock source This parameter can be a value of RCC LPTIM1 Clock Source

Definition at line 88 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection

Specifies LPTIM2 clock source This parameter can be a value of RCC LPTIM2 Clock Source

Definition at line 92 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection

Specifies LPUART1 clock source This parameter can be a value of RCC LPUART1 Clock Source

Definition at line 64 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lpuart2ClockSelection

Specifies LPUART2 clock source This parameter can be a value of RCC LPUART2 Clock Source

Definition at line 69 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of Periph Clock Selection

Definition at line 48 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RngClockSelection

Specifies RNG clock source This parameter can be a value of RCC RNG Clock Source

Definition at line 96 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC clock source. This parameter can be a value of RTC Clock Source

Definition at line 113 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Tim15ClockSelection

Specifies TIM15 Clock clock source This parameter can be a value of RCC TIM15 Clock Source

Definition at line 110 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Tim1ClockSelection

Specifies TIM1 Clock clock source This parameter can be a value of RCC TIM1 Clock Source

Definition at line 106 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart1ClockSelection

Specifies USART1 clock source. This parameter can be a value of RCC USART1 Clock Source

Definition at line 51 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart2ClockSelection

Specifies USART2 clock source. This parameter can be a value of RCC USART2 Clock Source

Definition at line 54 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart3ClockSelection

Specifies USART3 clock source. This parameter can be a value of RCC USART3 Clock Source

Definition at line 59 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UsbClockSelection

Specifies USB Clock clock source This parameter can be a value of USB Clock Source

Definition at line 116 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rcc_ex.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC_CRSInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSInitTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Init structure definition. More...

#include <stm32g0xx_hal_rcc_ex.h>

Data Fields

uint32_t | Prescaler
uint32_t | Source
uint32_t | Polarity
uint32_t | ReloadValue
uint32_t | ErrorLimitValue
uint32_t | HSI48CalibrationValue

Detailed Description

RCC_CRS Init structure definition.

Definition at line 130 of file stm32g0xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSInitTypeDef::ErrorLimitValue

Specifies the value to be used to evaluate the captured frequency error value. This parameter must be a number between 0 and 0xFF or a value of RCCEx CRS ErrorLimitDefault

Definition at line 145 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::HSI48CalibrationValue

Specifies a user-programmable trimming value to the HSI48 oscillator. This parameter must be a number between 0 and 0x7F or a value of RCCEx CRS HSI48CalibrationDefault

Definition at line 148 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Polarity

Specifies the input polarity for the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroPolarity

Definition at line 138 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Prescaler

Specifies the division factor of the SYNC signal. This parameter can be a value of RCCEx CRS SynchroDivider

Definition at line 132 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::ReloadValue

Specifies the value to be loaded in the frequency error counter with each SYNC event. It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) This parameter must be a number between 0 and 0xFFFF or a value of RCCEx CRS ReloadValueDefault .

Definition at line 141 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Source

Specifies the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroSource

Definition at line 135 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rcc_ex.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC_CRSSynchroInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSSynchroInfoTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Synchronization structure definition. More...

#include <stm32g0xx_hal_rcc_ex.h>

Data Fields

uint32_t | ReloadValue
uint32_t | HSI48CalibrationValue
uint32_t | FreqErrorCapture
uint32_t | FreqErrorDirection

Detailed Description

RCC_CRS Synchronization structure definition.

Definition at line 156 of file stm32g0xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorCapture

Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF

Definition at line 164 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorDirection

Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of RCCEx CRS FreqErrorDirection

Definition at line 168 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue

Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x7F

Definition at line 161 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::ReloadValue

Specifies the value loaded in the Counter reload value. This parameter must be a number between 0 and 0xFFFF

Definition at line 158 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rcc_ex.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Low Speed Clock Source

Defines
Low Speed Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LSCOSOURCE_LSI 0x00000000U
#define | RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL

Define Documentation

#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL

LSE selection for low speed clock output

Definition at line 189 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_LSCOSOURCE_LSI 0x00000000U

LSI selection for low speed clock output

Definition at line 188 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Periph Clock Selection

Defines
Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_USART1 0x00000001U
#define | RCC_PERIPHCLK_USART2 0x00000002U
#define | RCC_PERIPHCLK_USART3 0x00000004U
#define | RCC_PERIPHCLK_LPUART1 0x00000010U
#define | RCC_PERIPHCLK_I2C1 0x00000020U
#define | RCC_PERIPHCLK_I2C2 0x00000040U
#define | RCC_PERIPHCLK_LPTIM1 0x00000200U
#define | RCC_PERIPHCLK_LPTIM2 0x00000400U
#define | RCC_PERIPHCLK_I2S1 0x00000800U
#define | RCC_PERIPHCLK_LPUART2 0x00001000U
#define | RCC_PERIPHCLK_I2S2 0x00002000U
#define | RCC_PERIPHCLK_ADC 0x00004000U
#define | RCC_PERIPHCLK_RTC 0x00020000U
#define | RCC_PERIPHCLK_RNG 0x00040000U
#define | RCC_PERIPHCLK_CEC 0x00080000U
#define | RCC_PERIPHCLK_TIM1 0x00200000U
#define | RCC_PERIPHCLK_TIM15 0x00400000U
#define | RCC_PERIPHCLK_USB 0x01000000U
#define | RCC_PERIPHCLK_FDCAN 0x02000000U

Define Documentation

#define RCC_PERIPHCLK_ADC 0x00004000U

Definition at line 224 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_CEC 0x00080000U

Definition at line 230 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_FDCAN 0x02000000U

Definition at line 242 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C1 0x00000020U

Definition at line 207 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C2 0x00000040U

Definition at line 209 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2S1 0x00000800U

Definition at line 217 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_I2S_Init(), HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2S2 0x00002000U

Definition at line 222 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_I2S_Init(), HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM1 0x00000200U

Definition at line 212 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM2 0x00000400U

Definition at line 215 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPUART1 0x00000010U

Definition at line 205 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPUART2 0x00001000U

Definition at line 219 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RNG 0x00040000U

Definition at line 227 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC 0x00020000U

Definition at line 225 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_TIM1 0x00200000U

Definition at line 233 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_TIM15 0x00400000U

Definition at line 236 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART1 0x00000001U

Definition at line 197 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART2 0x00000002U

Definition at line 199 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART3 0x00000004U

Definition at line 202 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USB 0x01000000U

Definition at line 239 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC USART1 Clock Source

Defines
RCC USART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define | RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define | RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)

Define Documentation

#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1

HSI clock selected as USART1 clock

Definition at line 254 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)

LSE clock selected as USART1 clock

Definition at line 255 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_PCLK1 0x00000000U

APB clock selected as USART1 clock

Definition at line 252 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0

SYSCLK clock selected as USART1 clock

Definition at line 253 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC USART2 Clock Source

Defines
RCC USART2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define | RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define | RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)

Define Documentation

#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1

HSI clock selected as USART2 clock

Definition at line 266 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)

LSE clock selected as USART2 clock

Definition at line 267 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U

APB clock selected as USART2 clock

Definition at line 264 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0

SYSCLK clock selected as USART2 clock

Definition at line 265 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC USART3 Clock Source

Defines
RCC USART3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART3CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define | RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define | RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)

Define Documentation

#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1

HSI clock selected as USART3 clock

Definition at line 278 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)

LSE clock selected as USART3 clock

Definition at line 279 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U

APB clock selected as USART3 clock

Definition at line 276 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0

SYSCLK clock selected as USART3 clock

Definition at line 277 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC LPUART1 Clock Source

Defines
RCC LPUART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)

Define Documentation

#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1

HSI clock selected as LPUART1 clock

Definition at line 291 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)

LSE clock selected as LPUART1 clock

Definition at line 292 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U

APB clock selected as LPUART1 clock

Definition at line 289 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0

SYSCLK clock selected as LPUART1 clock

Definition at line 290 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC LPUART2 Clock Source

Defines
RCC LPUART2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPUART2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPUART2CLKSOURCE_SYSCLK RCC_CCIPR_LPUART2SEL_0
#define | RCC_LPUART2CLKSOURCE_HSI RCC_CCIPR_LPUART2SEL_1
#define | RCC_LPUART2CLKSOURCE_LSE (RCC_CCIPR_LPUART2SEL_0 | RCC_CCIPR_LPUART2SEL_1)

Define Documentation

#define RCC_LPUART2CLKSOURCE_HSI RCC_CCIPR_LPUART2SEL_1

HSI clock selected as LPUART2 clock

Definition at line 304 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART2CLKSOURCE_LSE (RCC_CCIPR_LPUART2SEL_0 | RCC_CCIPR_LPUART2SEL_1)

LSE clock selected as LPUART2 clock

Definition at line 305 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART2CLKSOURCE_PCLK1 0x00000000U

APB clock selected as LPUART2 clock

Definition at line 302 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART2CLKSOURCE_SYSCLK RCC_CCIPR_LPUART2SEL_0

SYSCLK clock selected as LPUART2 clock

Definition at line 303 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC I2C1 Clock Source

Defines
RCC I2C1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1

Define Documentation

#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1

HSI clock selected as I2C1 clock

Definition at line 316 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U

APB clock selected as I2C1 clock

Definition at line 314 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0

SYSCLK clock selected as I2C1 clock

Definition at line 315 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC I2C2 Clock Source

Defines
RCC I2C2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1

Define Documentation

#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1

HSI clock selected as I2C2 clock

Definition at line 327 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U

APB clock selected as I2C2 clock

Definition at line 325 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0

SYSCLK clock selected as I2C2 clock

Definition at line 326 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC I2S1 Clock Source

Defines
RCC I2S1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U
#define | RCC_I2S1CLKSOURCE_PLL RCC_CCIPR2_I2S1SEL_0
#define | RCC_I2S1CLKSOURCE_HSI RCC_CCIPR2_I2S1SEL_1
#define | RCC_I2S1CLKSOURCE_EXT RCC_CCIPR2_I2S1SEL

Define Documentation

#define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR2_I2S1SEL

External I2S clock source selected as I2S1 clock

Definition at line 340 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2S1CLKSOURCE_HSI RCC_CCIPR2_I2S1SEL_1

HSI clock selected as I2S1 clock

Definition at line 339 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2S1CLKSOURCE_PLL RCC_CCIPR2_I2S1SEL_0

PLL "P" selected as I2S1 clock

Definition at line 338 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U

SYSCLK clock selected as I2S1 clock

Definition at line 337 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC I2S2 Clock Source

Defines
RCC I2S2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
#define | RCC_I2S2CLKSOURCE_PLL RCC_CCIPR2_I2S2SEL_0
#define | RCC_I2S2CLKSOURCE_HSI RCC_CCIPR2_I2S2SEL_1
#define | RCC_I2S2CLKSOURCE_EXT RCC_CCIPR2_I2S2SEL

Define Documentation

#define RCC_I2S2CLKSOURCE_EXT RCC_CCIPR2_I2S2SEL

External I2S clock source selected as I2S2 clock

Definition at line 358 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2S2CLKSOURCE_HSI RCC_CCIPR2_I2S2SEL_1

HSI clock selected as I2S2 clock

Definition at line 357 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2S2CLKSOURCE_PLL RCC_CCIPR2_I2S2SEL_0

PLL "P" selected as I2S2 clock

Definition at line 356 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U

SYSCLK clock selected as I2S2 clock

Definition at line 355 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC LPTIM1 Clock Source

Defines
RCC LPTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL

Define Documentation

#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1

HSI clock selected as LPTimer 1 clock

Definition at line 370 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL

LSE clock selected as LPTimer 1 clock

Definition at line 371 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0

LSI clock selected as LPTimer 1 clock

Definition at line 369 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U

APB clock selected as LPTimer 1 clock

Definition at line 368 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LPTIM_Disable().

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STM32G0C1xx HAL User Manual: RCC LPTIM2 Clock Source

Defines
RCC LPTIM2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
#define | RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
#define | RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL

Define Documentation

#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1

HSI clock selected as LPTimer 2 clock

Definition at line 383 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL

LSE clock selected as LPTimer 2 clock

Definition at line 384 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0

LSI clock selected as LPTimer 2 clock

Definition at line 382 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U

APB clock selected as LPTimer 2 clock

Definition at line 381 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LPTIM_Disable().

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STM32G0C1xx HAL User Manual: RCC RNG Clock Source

Defines
RCC RNG Clock Source
RCCEx Exported Constants

Defines

#define | RCC_RNGCLKSOURCE_NONE 0x00000000U
#define | RCC_RNGCLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0
#define | RCC_RNGCLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1
#define | RCC_RNGCLKSOURCE_PLL (RCC_CCIPR_RNGSEL_0|RCC_CCIPR_RNGSEL_1)

Define Documentation

#define RCC_RNGCLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0

HSI oscillator divided by 8 clock selected as RNG clock

Definition at line 395 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RNGCLKSOURCE_NONE 0x00000000U

No clock selected

Definition at line 394 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_RNGCLKSOURCE_PLL (RCC_CCIPR_RNGSEL_0|RCC_CCIPR_RNGSEL_1)

PLL "Q" selected as RNG clock

Definition at line 397 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_RNGCLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1

SYSCLK selected as RNG clock

Definition at line 396 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC RNG Division factor

Defines
RCC RNG Division factor
RCCEx Exported Constants

Defines

#define | RCC_RNGCLK_DIV1 0x00000000U
#define | RCC_RNGCLK_DIV2 RCC_CCIPR_RNGDIV_0
#define | RCC_RNGCLK_DIV4 RCC_CCIPR_RNGDIV_1
#define | RCC_RNGCLK_DIV8 (RCC_CCIPR_RNGDIV_0|RCC_CCIPR_RNGDIV_1)

Define Documentation

#define RCC_RNGCLK_DIV1 0x00000000U

RNG clock not divided

Definition at line 406 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_RNGCLK_DIV2 RCC_CCIPR_RNGDIV_0

RNG clock divided by 2

Definition at line 407 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_RNGCLK_DIV4 RCC_CCIPR_RNGDIV_1

RNG clock divided by 4

Definition at line 408 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_RNGCLK_DIV8 (RCC_CCIPR_RNGDIV_0|RCC_CCIPR_RNGDIV_1)

RNG clock divided by 8

Definition at line 409 of file stm32g0xx_hal_rcc_ex.h.

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STM32G0C1xx HAL User Manual: RCC FDCAN Clock Source

Defines
RCC FDCAN Clock Source
RCCEx Exported Constants

Defines

#define | RCC_FDCANCLKSOURCE_PCLK1 0x00000000U
#define | RCC_FDCANCLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0
#define | RCC_FDCANCLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1

Define Documentation

#define RCC_FDCANCLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1

HSE oscillator clock selected as FDCAN clock

Definition at line 422 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_FDCANCLKSOURCE_PCLK1 0x00000000U

PCLK1 selected as FDCAN clock

Definition at line 420 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0

PLL "Q" selected as FDCAN clock

Definition at line 421 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32G0C1xx HAL User Manual: USB Clock Source

Defines
USB Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USBCLKSOURCE_HSI48 0x00000000U
#define | RCC_USBCLKSOURCE_HSE RCC_CCIPR2_USBSEL_0
#define | RCC_USBCLKSOURCE_PLL RCC_CCIPR2_USBSEL_1

Define Documentation

#define RCC_USBCLKSOURCE_HSE RCC_CCIPR2_USBSEL_0

HSE oscillator clock selected as USB clock

Definition at line 436 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USBCLKSOURCE_HSI48 0x00000000U

HSI48 oscillator clock selected as USB clock

Definition at line 434 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USBCLKSOURCE_PLL RCC_CCIPR2_USBSEL_1

PLL "Q" selected as USB clock

Definition at line 437 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32G0C1xx HAL User Manual: RCC ADC Clock Source

Defines
RCC ADC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_ADCCLKSOURCE_SYSCLK 0x00000000U
#define | RCC_ADCCLKSOURCE_PLLADC RCC_CCIPR_ADCSEL_0
#define | RCC_ADCCLKSOURCE_HSI RCC_CCIPR_ADCSEL_1

Define Documentation

#define RCC_ADCCLKSOURCE_HSI RCC_CCIPR_ADCSEL_1

HSI used as ADC clock

Definition at line 449 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_ADCCLKSOURCE_PLLADC RCC_CCIPR_ADCSEL_0

PLL "P" (PLLADC) used as ADC clock

Definition at line 448 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_SYSCLK 0x00000000U

SYSCLK used as ADC clock

Definition at line 447 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC CEC Clock Source

Defines
RCC CEC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_CECCLKSOURCE_HSI_DIV488 0x00000000U
#define | RCC_CECCLKSOURCE_LSE RCC_CCIPR_CECSEL

Define Documentation

#define RCC_CECCLKSOURCE_HSI_DIV488 0x00000000U

HSI oscillator clock divided by 488 used as default CEC clock

Definition at line 458 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_CECCLKSOURCE_LSE RCC_CCIPR_CECSEL

LSE oscillator clock used as CEC clock

Definition at line 459 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32G0C1xx HAL User Manual: RCC TIM1 Clock Source

Defines
RCC TIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_TIM1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_TIM1CLKSOURCE_PLL RCC_CCIPR_TIM1SEL

Define Documentation

#define RCC_TIM1CLKSOURCE_PCLK1 0x00000000U

APB clock selected as Timer 1 clock

Definition at line 469 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_TIM1CLKSOURCE_PLL RCC_CCIPR_TIM1SEL

PLL "Q" clock selected as Timer 1 clock

Definition at line 470 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32G0C1xx HAL User Manual: RCC TIM15 Clock Source

Defines
RCC TIM15 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_TIM15CLKSOURCE_PCLK1 0x00000000U
#define | RCC_TIM15CLKSOURCE_PLL RCC_CCIPR_TIM15SEL

Define Documentation

#define RCC_TIM15CLKSOURCE_PCLK1 0x00000000U

APB clock selected as Timer 15 clock

Definition at line 480 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_TIM15CLKSOURCE_PLL RCC_CCIPR_TIM15SEL

PLL "Q" clock selected as Timer 15 clock

Definition at line 481 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32G0C1xx HAL User Manual: RCCEx CRS Status

Defines
RCCEx CRS Status
RCCEx Exported Constants

Defines

#define | RCC_CRS_NONE 0x00000000U
#define | RCC_CRS_TIMEOUT 0x00000001U
#define | RCC_CRS_SYNCOK 0x00000002U
#define | RCC_CRS_SYNCWARN 0x00000004U
#define | RCC_CRS_SYNCERR 0x00000008U
#define | RCC_CRS_SYNCMISS 0x00000010U
#define | RCC_CRS_TRIMOVF 0x00000020U

Define Documentation

#define RCC_CRS_NONE 0x00000000U

Definition at line 493 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCERR 0x00000008U

Definition at line 497 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCMISS 0x00000010U

Definition at line 498 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCOK 0x00000002U

Definition at line 495 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCWARN 0x00000004U

Definition at line 496 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TIMEOUT 0x00000001U

Definition at line 494 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TRIMOVF 0x00000020U

Definition at line 499 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS SynchroSource

Defines
RCCEx CRS SynchroSource
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Define Documentation

#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U

Synchro Signal source GPIO

Definition at line 507 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0

Synchro Signal source LSE

Definition at line 508 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Synchro Signal source USB SOF (default)

Definition at line 509 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS SynchroDivider

Defines
RCCEx CRS SynchroDivider
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_DIV1 0x00000000U
#define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
#define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
#define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
#define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV

Define Documentation

#define RCC_CRS_SYNC_DIV1 0x00000000U

Synchro Signal not divided (default)

Definition at line 517 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

Definition at line 524 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

Definition at line 521 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

Definition at line 518 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

Definition at line 522 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

Definition at line 519 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

Definition at line 523 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8

Definition at line 520 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS SynchroPolarity

Defines
RCCEx CRS SynchroPolarity
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Define Documentation

#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Synchro Active on falling edge

Definition at line 533 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U

Synchro Active on rising edge (default)

Definition at line 532 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS ReloadValueDefault

Defines
RCCEx CRS ReloadValueDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU

Define Documentation

#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU

The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB).

Definition at line 541 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS ErrorLimitDefault

Defines
RCCEx CRS ErrorLimitDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U

Define Documentation

#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U

Default Frequency error limit

Definition at line 550 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS HSI48CalibrationDefault

Defines
RCCEx CRS HSI48CalibrationDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U

Define Documentation

#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U

The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is specified in the product datasheet. A higher TRIM value corresponds to a higher output frequency

Definition at line 558 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS FreqErrorDirection

Defines
RCCEx CRS FreqErrorDirection
RCCEx Exported Constants

Defines

#define | RCC_CRS_FREQERRORDIR_UP 0x00000000U
#define | RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR

Define Documentation

#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR

Downcounting direction, the actual frequency is below the target

Definition at line 569 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_FREQERRORDIR_UP 0x00000000U

Upcounting direction, the actual frequency is above the target

Definition at line 568 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS Interrupt Sources

Defines
RCCEx CRS Interrupt Sources
RCCEx Exported Constants

Defines

#define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE

Define Documentation

#define RCC_CRS_IT_ERR CRS_CR_ERRIE

Error

Definition at line 579 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE

Expected SYNC

Definition at line 580 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE

SYNC error

Definition at line 581 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE

SYNC missed

Definition at line 582 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE

SYNC event OK

Definition at line 577 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE

SYNC warning

Definition at line 578 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE

Trimming overflow or underflow

Definition at line 583 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS Flags

Defines
RCCEx CRS Flags
RCCEx Exported Constants

Defines

#define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF

Define Documentation

#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF

Error flag

Definition at line 594 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF

Expected SYNC flag

Definition at line 595 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR

SYNC error

Definition at line 596 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS

SYNC missed

Definition at line 597 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF

SYNC event OK flag

Definition at line 592 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF

SYNC warning flag

Definition at line 593 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF

Trimming overflow or underflow

Definition at line 598 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx Exported Macros

Defines
RCCEx Exported Macros
RCCEx

Defines

#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))
Macro to configure the I2S1 clock (I2S1CLK).
#define | __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL)))
Macro to get the I2S1 clock source.
#define | __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__))
Macro to configure the I2S2 clock (I2S2CLK).
#define | __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL)))
Macro to get the I2S2 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
Macro to get the USART3 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
Macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
Macro to get the LPUART1 clock source.
#define | __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__))
Macro to configure the LPUART2 clock (LPUART2CLK).
#define | __HAL_RCC_GET_LPUART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART2SEL)))
Macro to get the LPUART2 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
Macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
Macro to configure the LPTIM2 clock (LPTIM2CLK).
#define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
Macro to get the LPTIM2 clock source.
#define | __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
Macro to configure the CEC clock (CECCLK).
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CECSEL)))
Macro to get the CEC clock source.
#define | __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__))
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL)))
Macro to get the RNG clock.
#define | __HAL_RCC_RNGDIV_CONFIG(__RNG_CLKDIV__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__))
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_DIV() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)))
Macro to get the RNG clock division factor.
#define | __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
Macro to configure the ADC interface clock.
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
Macro to get the ADC clock source.
#define | __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__))
Macro to configure the TIM1 interface clock.
#define | __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL)))
Macro to get the TIM1 clock source.
#define | __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__))
Macro to configure the TIM15 interface clock.
#define | __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL)))
Macro to get the TIM15 clock source.
#define | __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__))
Macro to configure the USB interface clock.
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL)))
Macro to get the USB clock source.
#define | __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
Macro to configure the FDCAN interface clock.
#define | __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL)))
Macro to get the FDCAN clock source.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)

Define Documentation

#define __HAL_RCC_ADC_CONFIG ( __ADC_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))

Macro to configure the ADC interface clock.

Parameters:
__ADC_CLKSOURCE__ specifies the ADC digital interface clock source. This parameter can be one of the following values:
  • RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock

Definition at line 935 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_CEC_CONFIG ( __CEC_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))

Macro to configure the CEC clock (CECCLK).

Parameters:
__CEC_CLKSOURCE__ specifies the CEC clock source. This parameter can be one of the following values:
  • RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 selected as CEC clock
  • RCC_CECCLKSOURCE_LSE LSE selected as CEC clock

Definition at line 871 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_CRS_CLEAR_FLAG ( __FLAG__ )
Value:
do { \
                                                    if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
                                                    { \
                                                      WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
                                                    } \
                                                    else \
                                                    { \
                                                      WRITE_REG(CRS->ICR, (__FLAG__)); \
                                                    } \
                                                  } while(0)

Definition at line 1118 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_CLEAR_IT ( __INTERRUPT__ )
Value:
do { \
                                                    if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
                                                    { \
                                                      WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
                                                    } \
                                                    else \
                                                    { \
                                                      WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
                                                    } \
                                                  } while(0)

Definition at line 1074 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(CRS->CR, (__INTERRUPT__))

Disable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 1047 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(CRS->CR, (__INTERRUPT__))

Enable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 1035 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_GET_FLAG ( __FLAG__ ) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified CRS flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Return values:
The new state of _FLAG_ (TRUE or FALSE).

Definition at line 1098 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_GET_IT_SOURCE ( __INTERRUPT__ ) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)

Check whether the CRS interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the CRS interrupt source to check. This parameter can be one of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1058 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_FDCAN_CONFIG ( __FDCAN_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))

Macro to configure the FDCAN interface clock.

Parameters:
__FDCAN_CLKSOURCE__ specifies the FDCAN digital interface clock source. This parameter can be one of the following values:
  • RCC_FDCANCLKSOURCE_PLL PLLQ Output Clock selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PCLK1 System Clock selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock

Definition at line 1011 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))

Macro to get the ADC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock

Definition at line 944 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_CEC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CECSEL)))

Macro to get the CEC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 Clock selected as CEC clock
  • RCC_CECCLKSOURCE_LSE LSE selected as CEC clock

Definition at line 879 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_FDCAN_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL)))

Macro to get the FDCAN clock source.

Return values:
The clock source can be one of the following values:
  • RCC_FDCANCLKSOURCE_PLL PLLQ Output Clock selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_PCLK1 System Clock selected as FDCAN clock
  • RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock

Definition at line 1020 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))

Macro to get the I2C1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Definition at line 631 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))

Macro to get the I2C2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock

Definition at line 649 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2S1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL)))

Macro to get the I2S1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock
  • RCC_I2S1CLKSOURCE_PLL PLLP Clock selected as I2S1 clock
  • RCC_I2S1CLKSOURCE_HSI HSI Clock selected as I2S1 clock
  • RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock

Definition at line 676 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2S2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL)))

Macro to get the I2S2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2S2CLKSOURCE_SYSCLK System Clock selected as I2S2 clock
  • RCC_I2S2CLKSOURCE_PLL PLLP Clock selected as I2S2 clock
  • RCC_I2S2CLKSOURCE_HSI HSI Clock selected as I2S2 clock
  • RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock

Definition at line 701 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))

Macro to get the LPTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 837 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPTIM2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))

Macro to get the LPTIM2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock

Definition at line 860 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPUART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))

Macro to get the LPUART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 791 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPUART2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART2SEL)))

Macro to get the LPUART2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPUART2CLKSOURCE_PCLK1 PCLK1 selected as LPUART2 clock
  • RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock
  • RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock
  • RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock

Definition at line 814 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_RNG_DIV ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)))

Macro to get the RNG clock division factor.

Return values:
The division factor can be one of the following values:
  • RCC_RNGCLK_DIV1 RNG Clock not divided
  • RCC_RNGCLK_DIV2 RNG Clock divided by 2
  • RCC_RNGCLK_DIV4 RNG Clock divided by 4
  • RCC_RNGCLK_DIV8 RNG Clock divided by 8

Definition at line 925 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_RNG_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL)))

Macro to get the RNG clock.

Return values:
The clock source can be one of the following values:
  • RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock
  • RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divide by 8 selected as RNG clock
  • RCC_RNGCLKSOURCE_SYSCLK System clock selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock

Definition at line 903 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_TIM15_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL)))

Macro to get the TIM15 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock
  • RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock

Definition at line 979 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_TIM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL)))

Macro to get the TIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock
  • RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock

Definition at line 961 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))

Macro to get the USART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock

Definition at line 723 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))

Macro to get the USART2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock

Definition at line 745 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))

Macro to get the USART3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock

Definition at line 768 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USB_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL)))

Macro to get the USB clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USBCLKSOURCE_HSI48 HSI48 Clock selected as USB clock
  • RCC_USBCLKSOURCE_HSE HSE Output Clock selected as USB clock
  • RCC_USBCLKSOURCE_PLL PLLQ Output Clock selected as USB clock

Definition at line 1000 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2C1_CONFIG ( __I2C1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))

Macro to configure the I2C1 clock (I2C1CLK).

Parameters:
__I2C1_CLKSOURCE__ specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Definition at line 623 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C2_CONFIG ( __I2C2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))

Macro to configure the I2C2 clock (I2C2CLK).

Parameters:
__I2C2_CLKSOURCE__ specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock

Definition at line 641 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2S1_CONFIG ( __I2S1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))

Macro to configure the I2S1 clock (I2S1CLK).

Parameters:
__I2S1_CLKSOURCE__ specifies the I2S1 clock source. This parameter can be one of the following values:
  • RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock
  • RCC_I2S1CLKSOURCE_PLL PLLP Clock selected as I2S1 clock
  • RCC_I2S1CLKSOURCE_HSI HSI Clock selected as I2S1 clock
  • RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock

Definition at line 662 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2S2_CONFIG ( __I2S2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__))

Macro to configure the I2S2 clock (I2S2CLK).

Parameters:
__I2S2_CLKSOURCE__ specifies the I2S2 clock source. This parameter can be one of the following values:
  • RCC_I2S2CLKSOURCE_SYSCLK System Clock selected as I2S2 clock
  • RCC_I2S2CLKSOURCE_PLL PLLP Clock selected as I2S2 clock
  • RCC_I2S2CLKSOURCE_HSI HSI Clock selected as I2S2 clock
  • RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock

Definition at line 691 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))

Macro to configure the LPTIM1 clock (LPTIM1CLK).

Parameters:
__LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock

Definition at line 827 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPTIM2_CONFIG ( __LPTIM2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))

Macro to configure the LPTIM2 clock (LPTIM2CLK).

Parameters:
__LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. This parameter can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock

Definition at line 850 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPUART1_CONFIG ( __LPUART1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))

Macro to configure the LPUART1 clock (LPUART1CLK).

Parameters:
__LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. This parameter can be one of the following values:
  • RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 781 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPUART2_CONFIG ( __LPUART2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__))

Macro to configure the LPUART2 clock (LPUART2CLK).

Parameters:
__LPUART2_CLKSOURCE__ specifies the LPUART2 clock source. This parameter can be one of the following values:
  • RCC_LPUART2CLKSOURCE_PCLK1 PCLK1 selected as LPUART2 clock
  • RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock
  • RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock
  • RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock

Definition at line 804 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RNG_CONFIG ( __RNG_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__))

Macro to configure the RNG clock.

Parameters:
__RNG_CLKSOURCE__ specifies the RNG clock source. This parameter can be one of the following values:
  • RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock
  • RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divided by 8 selected as RNG clock
  • RCC_RNGCLKSOURCE_SYSCLK System Clock selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock

Definition at line 893 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RNGDIV_CONFIG ( __RNG_CLKDIV__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__))

Macro to configure the RNG clock.

Parameters:
__RNG_CLKDIV__ specifies the RNG clock division factor. This parameter can be one of the following values:
  • RCC_RNGCLK_DIV1 RNG Clock not divided
  • RCC_RNGCLK_DIV2 RNG Clock divided by 2
  • RCC_RNGCLK_DIV4 RNG Clock divided by 4
  • RCC_RNGCLK_DIV8 RNG Clock divided by 8

Definition at line 915 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM15_CONFIG ( __TIM15_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__))

Macro to configure the TIM15 interface clock.

Parameters:
__TIM15_CLKSOURCE__ specifies the TIM15 digital interface clock source. This parameter can be one of the following values:
  • RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock
  • RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock

Definition at line 971 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIM1_CONFIG ( __TIM1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__))

Macro to configure the TIM1 interface clock.

Parameters:
__TIM1_CLKSOURCE__ specifies the TIM1 digital interface clock source. This parameter can be one of the following values:
  • RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock
  • RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock

Definition at line 953 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG ( __USART1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))

Macro to configure the USART1 clock (USART1CLK).

Parameters:
__USART1_CLKSOURCE__ specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock

Definition at line 713 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART2_CONFIG ( __USART2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))

Macro to configure the USART2 clock (USART2CLK).

Parameters:
__USART2_CLKSOURCE__ specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock

Definition at line 735 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART3_CONFIG ( __USART3_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))

Macro to configure the USART3 clock (USART3CLK).

Parameters:
__USART3_CLKSOURCE__ specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock

Definition at line 758 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USB_CONFIG ( __USB_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__))

Macro to configure the USB interface clock.

Parameters:
__USB_CLKSOURCE__ specifies the USB digital interface clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_PLL PLLQ Output Clock selected as USB clock (*)
  • RCC_USBCLKSOURCE_HSE HSE Output Clock selected as USB clock
  • RCC_USBCLKSOURCE_HSI48 HSI48 Clock selected as USB clock (*) (*) Feature not available on all devices

Definition at line 991 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)

Clear the CRS specified FLAG.

Parameters:
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Note:
RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
Return values:
None

Definition at line 1116 of file stm32g0xx_hal_rcc_ex.h.

#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)

Clear the CRS interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
  • RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
  • RCC_CRS_IT_SYNCERR SYNC error interrupt
  • RCC_CRS_IT_SYNCMISS SYNC missed interrupt

Definition at line 1072 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx CRS Extended Features

Defines
RCCEx CRS Extended Features
RCCEx

Defines

#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable or disable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE ( ) CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

Enable or disable the automatic hardware adjustment of TRIM bits.

Return values:
None

Definition at line 1164 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE ( ) SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

Enable the automatic hardware adjustment of TRIM bits.

Note:
When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 1158 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE ( ) CLEAR_BIT(CRS->CR, CRS_CR_CEN)

Disable the oscillator clock for frequency error counter.

Return values:
None

Definition at line 1151 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE ( ) SET_BIT(CRS->CR, CRS_CR_CEN)

Enable the oscillator clock for frequency error counter.

Note:
when the CEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 1145 of file stm32g0xx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | (((__FTARGET__) / (__FSYNC__)) - 1U)

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
None

Definition at line 1176 of file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx Private Macros

Defines
RCCEx Private Macros
RCCEx

Defines

#define | IS_RCC_LSCOSOURCE(__SOURCE__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C2CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2S1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2S2CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPTIM1CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPTIM2CLKSOURCE(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(__SOURCE__)
#define | IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define | IS_RCC_RNGDIV(__DIV__)
#define | IS_RCC_CECCLKSOURCE(__SOURCE__)
#define | IS_RCC_FDCANCLKSOURCE(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(__SOURCE__)
#define | IS_RCC_TIM1CLKSOURCE(__SOURCE__)
#define | IS_RCC_TIM15CLKSOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)

Define Documentation

#define IS_RCC_ADCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC)  || \
   ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)  || \
   ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI))

Definition at line 1493 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_CECCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \
   ((__SOURCE__) == RCC_CECCLKSOURCE_LSE))

Definition at line 1512 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_CRS_ERRORLIMIT ( __VALUE__ ) (((__VALUE__) <= 0xFFU))

Definition at line 1564 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_FREQERRORDIR ( __DIR__ )
Value:
(((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

Definition at line 1568 of file stm32g0xx_hal_rcc_ex.h.

#define IS_RCC_CRS_HSI48CALIBRATION ( __VALUE__ ) (((__VALUE__) <= 0x7FU))

Definition at line 1566 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_RELOADVALUE ( __VALUE__ ) (((__VALUE__) <= 0xFFFFU))

Definition at line 1562 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_DIV ( __DIV__ )
Value:
(((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))

Definition at line 1554 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))

Definition at line 1559 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))

Definition at line 1550 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_FDCANCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \
   ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \
   ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))

Definition at line 1518 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1)   || \
   ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)  || \
   ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))

Definition at line 1450 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1)   || \
   ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)  || \
   ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))

Definition at line 1456 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2S1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \
   ((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL)   || \
   ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI)   || \
   ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT))

Definition at line 1463 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2S2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \
   ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL)   || \
   ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI)   || \
   ((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT))

Definition at line 1470 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \
   ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
   ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
   ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))

Definition at line 1478 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \
   ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
   ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
   ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))

Definition at line 1486 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPUART1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))

Definition at line 1435 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPUART2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1)  || \
   ((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \
   ((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE)    || \
   ((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI))

Definition at line 1443 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LSCOSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))

Definition at line 1243 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSCO().

#define IS_RCC_PERIPHCLOCK ( __SELECTION__ )
Value:
((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
   (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
   (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
   (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
   (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \
   (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
   (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
   (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
   (((__SELECTION__) & RCC_PERIPHCLK_I2S2)    == RCC_PERIPHCLK_I2S2)    || \
   (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
   (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
   (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
   (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
   (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
   (((__SELECTION__) & RCC_PERIPHCLK_CEC)     == RCC_PERIPHCLK_CEC)     || \
   (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)   == RCC_PERIPHCLK_FDCAN)   || \
   (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
   (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1)    || \
   (((__SELECTION__) & RCC_PERIPHCLK_TIM15)   == RCC_PERIPHCLK_TIM15))

Definition at line 1248 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_RNGCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)         || \
   ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8)     || \
   ((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK)       || \
   ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))

Definition at line 1499 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_RNGDIV ( __DIV__ )
Value:
(((__DIV__) == RCC_RNGCLK_DIV1) || \
   ((__DIV__) == RCC_RNGCLK_DIV2) || \
   ((__DIV__) == RCC_RNGCLK_DIV4) || \
   ((__DIV__) == RCC_RNGCLK_DIV8))

Definition at line 1504 of file stm32g0xx_hal_rcc_ex.h.

#define IS_RCC_TIM15CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL)     || \
   ((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1))

Definition at line 1543 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_TIM1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL)     || \
   ((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1))

Definition at line 1537 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1)  || \
   ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
   ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
   ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))

Definition at line 1412 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
   ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
   ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
   ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))

Definition at line 1419 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART3CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
   ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
   ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
   ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))

Definition at line 1427 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USBCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \
   ((__SOURCE__) == RCC_USBCLKSOURCE_HSE)  || \
   ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))

Definition at line 1526 of file stm32g0xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Private Constants

Defines
RNG Private Constants
RNG

Defines

#define RNG_TIMEOUT_VALUE 2U

Define Documentation

#define RNG_TIMEOUT_VALUE 2U

Definition at line 118 of file stm32g0xx_hal_rng.c.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_InitTypeDef Struct Reference
RNG Init Structure definition

#include <stm32g0xx_hal_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

Definition at line 50 of file stm32g0xx_hal_rng.h.

Field Documentation

uint32_t RNG_InitTypeDef::ClockErrorDetection

CED Clock error detection

Definition at line 52 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rng.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG State Structure definition

Enumerations
RNG State Structure definition
RNG Exported Types

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}

Enumeration Type Documentation

enum HAL_RNG_StateTypeDef
Enumerator:
HAL_RNG_STATE_RESET

RNG not yet initialized or disabled

HAL_RNG_STATE_READY

RNG initialized and ready for use

HAL_RNG_STATE_BUSY

RNG internal process is ongoing

HAL_RNG_STATE_TIMEOUT

RNG timeout state

HAL_RNG_STATE_ERROR

RNG error state

Definition at line 62 of file stm32g0xx_hal_rng.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Handle Structure definition

Data Structures | Typedefs | Enumerations
RNG Handle Structure definition
RNG Exported Types

Data Structures

struct | __RNG_HandleTypeDef

Typedefs

typedef struct __RNG_HandleTypeDef | RNG_HandleTypeDef
typedef void(* | pRNG_CallbackTypeDef )(RNG_HandleTypeDef *hrng)
HAL RNG Callback pointer definition.
typedef void(* | pRNG_ReadyDataCallbackTypeDef )(RNG_HandleTypeDef *hrng, uint32_t random32bit)

Enumerations

enum | HAL_RNG_CallbackIDTypeDef { HAL_RNG_ERROR_CB_ID = 0x00U, HAL_RNG_MSPINIT_CB_ID = 0x01U, HAL_RNG_MSPDEINIT_CB_ID = 0x02U }
HAL RNG Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng)

HAL RNG Callback pointer definition.

pointer to a common RNG callback function

Definition at line 123 of file stm32g0xx_hal_rng.h.

typedef void(* pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit)

pointer to an RNG Data Ready specific callback function

Definition at line 124 of file stm32g0xx_hal_rng.h.

typedef struct __RNG_HandleTypeDef RNG_HandleTypeDef

Enumeration Type Documentation

enum HAL_RNG_CallbackIDTypeDef

HAL RNG Callback ID enumeration definition.

Enumerator:
HAL_RNG_ERROR_CB_ID

RNG Error Callback ID

HAL_RNG_MSPINIT_CB_ID

RNG MspInit callback ID

HAL_RNG_MSPDEINIT_CB_ID

RNG MspDeInit callback ID

Definition at line 111 of file stm32g0xx_hal_rng.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __RNG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RNG_HandleTypeDef Struct Reference
RNG Handle Structure definition

#include <stm32g0xx_hal_rng.h>

Data Fields

RNG_TypeDef * | Instance
RNG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RNG_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | RandomNumber
void(* | ReadyDataCallback )(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit)
void(* | ErrorCallback )(struct __RNG_HandleTypeDef *hrng)
void(* | MspInitCallback )(struct __RNG_HandleTypeDef *hrng)
void(* | MspDeInitCallback )(struct __RNG_HandleTypeDef *hrng)

Detailed Description

Definition at line 80 of file stm32g0xx_hal_rng.h.

Field Documentation

void(* __RNG_HandleTypeDef::ErrorCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Error Callback

Definition at line 99 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

__IO uint32_t __RNG_HandleTypeDef::ErrorCode

RNG Error code

Definition at line 93 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetError(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

RNG_InitTypeDef __RNG_HandleTypeDef::Init

RNG configuration parameters

Definition at line 87 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_Init().

RNG_TypeDef* __RNG_HandleTypeDef::Instance

Register base address

Definition at line 85 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

HAL_LockTypeDef __RNG_HandleTypeDef::Lock

RNG locking object

Definition at line 89 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_Init().

void(* __RNG_HandleTypeDef::MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Msp DeInit callback

Definition at line 102 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

void(* __RNG_HandleTypeDef::MspInitCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Msp Init callback

Definition at line 101 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

uint32_t __RNG_HandleTypeDef::RandomNumber

Last Generated RNG Data

Definition at line 95 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_IRQHandler(), and HAL_RNG_ReadLastRandomNumber().

void(* __RNG_HandleTypeDef::ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit)

RNG Data Ready Callback

Definition at line 98 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterReadyDataCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

__IO HAL_RNG_StateTypeDef __RNG_HandleTypeDef::State

RNG communication state

Definition at line 91 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetState(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rng.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Interrupt definition

Defines
RNG Interrupt definition
RNG Exported Constants

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS

Define Documentation

#define RNG_IT_CEI RNG_SR_CEIS

Clock error interrupt

Definition at line 145 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_DRDY RNG_SR_DRDY

Data Ready interrupt

Definition at line 144 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_SEI RNG_SR_SEIS

Seed error interrupt

Definition at line 146 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Flag definition

Defines
RNG Flag definition
RNG Exported Constants

Defines

#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS

Define Documentation

#define RNG_FLAG_CECS RNG_SR_CECS

Clock error current status

Definition at line 155 of file stm32g0xx_hal_rng.h.

#define RNG_FLAG_DRDY RNG_SR_DRDY

Data ready

Definition at line 154 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define RNG_FLAG_SECS RNG_SR_SECS

Seed error current status

Definition at line 156 of file stm32g0xx_hal_rng.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Clock Error Detection

Defines
RNG Clock Error Detection
RNG Exported Constants

Defines

#define | RNG_CED_ENABLE 0x00000000U
#define | RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define RNG_CED_DISABLE RNG_CR_CED

Clock error detection Disabled

Definition at line 165 of file stm32g0xx_hal_rng.h.

#define RNG_CED_ENABLE 0x00000000U

Clock error detection Enabled

Definition at line 164 of file stm32g0xx_hal_rng.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Error Definition

Defines
RNG Error Definition
RNG Exported Constants

Defines

#define | HAL_RNG_ERROR_NONE 0x00000000U
#define | HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U
#define | HAL_RNG_ERROR_TIMEOUT 0x00000002U
#define | HAL_RNG_ERROR_BUSY 0x00000004U
#define | HAL_RNG_ERROR_SEED 0x00000008U
#define | HAL_RNG_ERROR_CLOCK 0x00000010U

Define Documentation

#define HAL_RNG_ERROR_BUSY 0x00000004U

Busy error

Definition at line 178 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), and HAL_RNG_GenerateRandomNumber_IT().

#define HAL_RNG_ERROR_CLOCK 0x00000010U

Clock error

Definition at line 180 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U

Invalid Callback error

Definition at line 175 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

#define HAL_RNG_ERROR_NONE 0x00000000U

No error

Definition at line 173 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), and HAL_RNG_Init().

#define HAL_RNG_ERROR_SEED 0x00000008U

Seed error

Definition at line 179 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define HAL_RNG_ERROR_TIMEOUT 0x00000002U

Timeout error

Definition at line 177 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Exported Macros

Defines
RNG Exported Macros
RNG

Defines

#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Define Documentation

#define __HAL_RNG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* dummy macro */

Clears the selected RNG flag status.

Parameters:
__HANDLE__ | RNG handle
__FLAG__ | RNG flag to clear
Note:
WARNING: This is a dummy macro for HAL code alignment, flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
Return values:
None

Definition at line 242 of file stm32g0xx_hal_rng.h.

#define __HAL_RNG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

Clear the RNG interrupt status flags.

Parameters:
__HANDLE__ RNG Handle
__INTERRUPT__ specifies the RNG interrupt status flag to clear. This parameter can be one of the following values:
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Note:
RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
Return values:
None

Definition at line 280 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

Disables the RNG peripheral.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 220 of file stm32g0xx_hal_rng.h.

#define __HAL_RNG_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

Disables the RNG interrupts.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 256 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)

Enables the RNG peripheral.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 213 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define __HAL_RNG_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)

Enables the RNG interrupts.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 249 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber_IT().

#define __HAL_RNG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check the selected RNG flag status.

Parameters:
__HANDLE__ RNG Handle
__FLAG__ RNG flag This parameter can be one of the following values:
  • RNG_FLAG_DRDY: Data ready
  • RNG_FLAG_CECS: Clock error current status
  • RNG_FLAG_SECS: Seed error current status
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 232 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define __HAL_RNG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks whether the specified RNG interrupt has occurred or not.

Parameters:
__HANDLE__ RNG Handle
__INTERRUPT__ specifies the RNG interrupt status flag to check. This parameter can be one of the following values:
  • RNG_IT_DRDY: Data ready interrupt
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 268 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
                                                       (__HANDLE__)->MspInitCallback = NULL;            \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                    } while(0U)

Reset RNG handle state.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 199 of file stm32g0xx_hal_rng.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and configuration functions

Functions
Initialization and configuration functions
RNG Exported Functions

Initialization and configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.

Detailed Description

Initialization and configuration functions.

 ===============================================================================
          ##### Initialization and configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the RNG according to the specified parameters
          in the RNG_InitTypeDef and create the associated handle
      (+) DeInitialize the RNG peripheral
      (+) Initialize the RNG MSP
      (+) DeInitialize RNG MSP

Function Documentation

HAL_StatusTypeDef HAL_RNG_DeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG peripheral.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 219 of file stm32g0xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_NONE, HAL_RNG_MspDeInit(), HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::MspDeInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_Init ( RNG_HandleTypeDef * hrng )

Initializes the RNG peripheral and creates the associated handle.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 155 of file stm32g0xx_hal_rng.c.

References __HAL_RNG_ENABLE, assert_param, RNG_InitTypeDef::ClockErrorDetection, __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_NONE, HAL_RNG_ErrorCallback(), HAL_RNG_MspInit(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::Init, __RNG_HandleTypeDef::Instance, IS_RNG_CED, __RNG_HandleTypeDef::Lock, __RNG_HandleTypeDef::MspInitCallback, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

void HAL_RNG_MspDeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG MSP.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 282 of file stm32g0xx_hal_rng.c.

Referenced by HAL_RNG_DeInit(), and HAL_RNG_UnRegisterCallback().

void HAL_RNG_MspInit ( RNG_HandleTypeDef * hrng )

Initializes the RNG MSP.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 267 of file stm32g0xx_hal_rng.c.

Referenced by HAL_RNG_Init(), and HAL_RNG_UnRegisterCallback().

HAL_StatusTypeDef HAL_RNG_RegisterCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | HAL_RNG_CallbackIDTypeDef | CallbackID,
 |  | pRNG_CallbackTypeDef | pCallback
 | ) |  |

Register a User RNG Callback To be used instead of the weak predefined callback.

Parameters:
hrng | RNG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_RNG_ERROR_CB_ID Error callback ID
  • HAL_RNG_MSPINIT_CB_ID MspInit callback ID
  • HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 304 of file stm32g0xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CB_ID, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_MSPDEINIT_CB_ID, HAL_RNG_MSPINIT_CB_ID, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::MspDeInitCallback, __RNG_HandleTypeDef::MspInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | pRNG_ReadyDataCallbackTypeDef | pCallback
 | ) |  |

Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.

Parameters:
hrng | RNG handle
pCallback | pointer to the Data Ready Callback function
Return values:
HAL status

Definition at line 457 of file stm32g0xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_UnRegisterCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | HAL_RNG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an RNG Callback RNG callback is redirected to the weak predefined callback.

Parameters:
hrng RNG handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_RNG_ERROR_CB_ID Error callback ID
  • HAL_RNG_MSPINIT_CB_ID MspInit callback ID
  • HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 386 of file stm32g0xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CB_ID, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_ErrorCallback(), HAL_RNG_MspDeInit(), HAL_RNG_MSPDEINIT_CB_ID, HAL_RNG_MspInit(), HAL_RNG_MSPINIT_CB_ID, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::MspDeInitCallback, __RNG_HandleTypeDef::MspInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback ( RNG_HandleTypeDef * hrng )

UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.

Parameters:
hrng RNG handle
Return values:
HAL status

Definition at line 493 of file stm32g0xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_READY, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RNG Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the 32 bit Random number
      (+) Get the 32 bit Random number with interrupt enabled
      (+) Handle RNG interrupt request

Function Documentation

void HAL_RNG_ErrorCallback ( RNG_HandleTypeDef * hrng )

RNG error callbacks.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 771 of file stm32g0xx_hal_rng.c.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), and HAL_RNG_UnRegisterCallback().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t * | random32bit
 | ) |  |

Generates a 32-bit random number.

Note:
This function checks value of RNG_FLAG_DRDY flag to know if valid random number is available in the DR register (RNG_FLAG_DRDY flag set whenever a random number is available through the RNG_DR register). After transitioning from 0 to 1 (random number available), RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading four words from the RNG_DR register, i.e. further function calls will immediately return a new u32 random number (additional words are available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
When no more random number data is available in DR register, RNG_FLAG_DRDY flag is automatically cleared.
Parameters:
hrng | pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit | pointer to generated random number variable if successful.
Return values:
HAL status

Definition at line 557 of file stm32g0xx_hal_rng.c.

References __HAL_RNG_GET_FLAG, __RNG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_RNG_ERROR_BUSY, HAL_RNG_ERROR_TIMEOUT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::RandomNumber, RNG_FLAG_DRDY, RNG_TIMEOUT_VALUE, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Generates a 32-bit random number in interrupt mode.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 615 of file stm32g0xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_BUSY, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, and __RNG_HandleTypeDef::State.

void HAL_RNG_IRQHandler ( RNG_HandleTypeDef * hrng )

Handles RNG interrupt request.

Note:
In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User has to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random numbers is interrupted as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable the RNG peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once whether SEIS or CEIS are set.
Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 664 of file stm32g0xx_hal_rng.c.

References __HAL_RNG_CLEAR_IT, __HAL_RNG_DISABLE_IT, __HAL_RNG_GET_IT, __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CLOCK, HAL_RNG_ERROR_SEED, HAL_RNG_ErrorCallback(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::RandomNumber, __RNG_HandleTypeDef::ReadyDataCallback, RNG_IT_CEI, RNG_IT_DRDY, RNG_IT_SEI, and __RNG_HandleTypeDef::State.

uint32_t HAL_RNG_ReadLastRandomNumber ( RNG_HandleTypeDef * hrng )

Read latest generated random number.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
random value

Definition at line 738 of file stm32g0xx_hal_rng.c.

References __RNG_HandleTypeDef::RandomNumber.

void HAL_RNG_ReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t | random32bit
 | ) |  |

Data Ready callback in non-blocking mode.

Note:
When RNG_FLAG_DRDY flag value is set, first random number has been read from DR register in IRQ Handler and is provided as callback parameter. Depending on valid data available in the conditioning output buffer, additional words can be read by the application from DR register till DRDY bit remains high.
Parameters:
hrng | pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit | generated random number.
Return values:
None

Definition at line 755 of file stm32g0xx_hal_rng.c.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), and HAL_RNG_UnRegisterReadyDataCallback().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RNG Exported Functions

Peripheral State functions. More...

Functions

HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_RNG_GetError ( RNG_HandleTypeDef * hrng )

Return the RNG handle error code.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
RNG Error Code

Definition at line 815 of file stm32g0xx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode.

HAL_RNG_StateTypeDef HAL_RNG_GetState ( RNG_HandleTypeDef * hrng )

Returns the RNG state.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL state

Definition at line 805 of file stm32g0xx_hal_rng.c.

References __RNG_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG

Defines

#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(__MODE__)
Verify the RNG Clock Error Detection mode.

Define Documentation

#define IS_RNG_CED ( __MODE__ )
Value:
(((__MODE__) == RNG_CED_ENABLE) || \
                                ((__MODE__) == RNG_CED_DISABLE))

Verify the RNG Clock Error Detection mode.

Parameters:
__MODE__ RNG Clock Error Detection mode
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 357 of file stm32g0xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define IS_RNG_FLAG ( FLAG )
Value:
(((FLAG) == RNG_FLAG_DRDY) || \
                           ((FLAG) == RNG_FLAG_CECS) || \
                           ((FLAG) == RNG_FLAG_SECS))

Definition at line 348 of file stm32g0xx_hal_rng.h.

#define IS_RNG_IT ( IT )
Value:
(((IT) == RNG_IT_CEI) || \
                       ((IT) == RNG_IT_SEI))

Definition at line 345 of file stm32g0xx_hal_rng.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Exported Types

Data Structures | Typedefs | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | __RTC_HandleTypeDef
RTC Handle Structure definition. More...

Typedefs

typedef struct __RTC_HandleTypeDef | RTC_HandleTypeDef
RTC Handle Structure definition.
typedef void(* | pRTC_CallbackTypeDef )(RTC_HandleTypeDef *hrtc)
HAL RTC Callback pointer definition.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_RTC_CallbackIDTypeDef {
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U,
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 0x09U,
HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 0x0AU, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 0x0BU, HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 0x0CU, HAL_RTC_MSPINIT_CB_ID = 0x0EU,
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU
}
HAL RTC Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc)

HAL RTC Callback pointer definition.

pointer to an RTC callback function

Definition at line 243 of file stm32g0xx_hal_rtc.h.

typedef struct __RTC_HandleTypeDef RTC_HandleTypeDef

RTC Handle Structure definition.

Enumeration Type Documentation

enum HAL_RTC_CallbackIDTypeDef

HAL RTC Callback ID enumeration definition.

Enumerator:
HAL_RTC_ALARM_A_EVENT_CB_ID

RTC Alarm A Event Callback ID

HAL_RTC_ALARM_B_EVENT_CB_ID

RTC Alarm B Event Callback ID

HAL_RTC_TIMESTAMP_EVENT_CB_ID

RTC TimeStamp Event Callback ID

HAL_RTC_WAKEUPTIMER_EVENT_CB_ID

RTC WakeUp Timer Event Callback ID

HAL_RTC_TAMPER1_EVENT_CB_ID

RTC Tamper 1 Callback ID

HAL_RTC_TAMPER2_EVENT_CB_ID

RTC Tamper 2 Callback ID

HAL_RTC_TAMPER3_EVENT_CB_ID

RTC Tamper 3 Callback ID

HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID

RTC Internal Tamper 3 Callback ID

HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID

RTC Internal Tamper 4 Callback ID

HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID

RTC Internal Tamper 5 Callback ID

HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID

RTC Internal Tamper 6 Callback ID

HAL_RTC_MSPINIT_CB_ID

RTC Msp Init callback ID

HAL_RTC_MSPDEINIT_CB_ID

RTC Msp DeInit callback ID

Definition at line 221 of file stm32g0xx_hal_rtc.h.

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 46 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32g0xx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutRemap
uint32_t | OutPutPolarity
uint32_t | OutPutType
uint32_t | OutPutPullUp

Detailed Description

RTC Configuration Structure definition.

Definition at line 59 of file stm32g0xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 64 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC Hour Formats

Definition at line 61 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTCEx Output Selection Definition

Definition at line 70 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 76 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPullUp

Specifies the RTC Output Pull-Up mode. This parameter can be a value of RTC Output Pull-Up ALARM OUT

Definition at line 82 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutRemap

Specifies the remap for RTC output. This parameter can be a value of RTC Output ALARM OUT Remap

Definition at line 73 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 79 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

Definition at line 67 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rtc.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32g0xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint8_t | TimeFormat
uint32_t | SubSeconds
uint32_t | SecondFraction
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 89 of file stm32g0xx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions

Definition at line 114 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 91 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 95 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::SecondFraction

Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function

Definition at line 108 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 98 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions

Definition at line 117 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity

Definition at line 104 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 101 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rtc.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32g0xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 124 of file stm32g0xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 132 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions

Definition at line 129 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 126 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 135 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rtc.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32g0xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 143 of file stm32g0xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 160 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 156 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC AlarmDateWeekDay Definitions

Definition at line 153 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC AlarmMask Definitions

Definition at line 147 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 150 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 145 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rtc.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RTC_HandleTypeDef Struct Reference
RTC Exported Types

RTC Handle Structure definition. More...

#include <stm32g0xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
uint32_t | TampOffset
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State
void(* | AlarmAEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | AlarmBEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | TimeStampEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | WakeUpTimerEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper1EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper2EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper3EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper3EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper4EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper5EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | InternalTamper6EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | MspInitCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | MspDeInitCallback )(struct __RTC_HandleTypeDef *hrtc)

Detailed Description

RTC Handle Structure definition.

Definition at line 168 of file stm32g0xx_hal_rtc.h.

Field Documentation

void(* __RTC_HandleTypeDef::AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Alarm A Event callback

Definition at line 184 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

void(* __RTC_HandleTypeDef::AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Alarm B Event callback

Definition at line 186 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

RTC_InitTypeDef __RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 177 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* __RTC_HandleTypeDef::Instance

Register base address

Definition at line 173 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_DST_Add1Hour(), HAL_RTC_DST_ClearStoreOperation(), HAL_RTC_DST_ReadStoreOperation(), HAL_RTC_DST_SetStoreOperation(), HAL_RTC_DST_Sub1Hour(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperIRQHandler(), and RTC_EnterInitMode().

void(* __RTC_HandleTypeDef::InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 3 Event callback

Definition at line 200 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 4 Event callback

Definition at line 202 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 5 Event callback

Definition at line 204 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Internal Tamper 6 Event callback

Definition at line 206 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

HAL_LockTypeDef __RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 179 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

void(* __RTC_HandleTypeDef::MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Msp DeInit callback

Definition at line 211 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

void(* __RTC_HandleTypeDef::MspInitCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Msp Init callback

Definition at line 209 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

__IO HAL_RTCStateTypeDef __RTC_HandleTypeDef::State

Time communication state

Definition at line 181 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_RegisterCallback(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_UnRegisterCallback(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TimeStampIRQHandler(), HAL_RTCEx_WakeUpTimerIRQHandler(), RTC_EnterInitMode(), and RTC_ExitInitMode().

void(* __RTC_HandleTypeDef::Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 1 Event callback

Definition at line 192 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 2 Event callback

Definition at line 194 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 3 Event callback

Definition at line 197 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

uint32_t __RTC_HandleTypeDef::TampOffset

Offset to TAMP instance

Definition at line 175 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_TamperIRQHandler().

void(* __RTC_HandleTypeDef::TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC TimeStamp Event callback

Definition at line 188 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TimeStampIRQHandler().

void(* __RTC_HandleTypeDef::WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC WakeUpTimer Event callback

Definition at line 190 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rtc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Hour Formats

Defines
RTC Hour Formats
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 0x00000000u
#define | RTC_HOURFORMAT_12 RTC_CR_FMT

Define Documentation

#define RTC_HOURFORMAT_12 RTC_CR_FMT

Definition at line 259 of file stm32g0xx_hal_rtc.h.

#define RTC_HOURFORMAT_24 0x00000000u

Definition at line 258 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Output Selection Definition

Defines
RTCEx Output Selection Definition
RTC Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE 0x00000000u
#define | RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define | RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define | RTC_OUTPUT_WAKEUP RTC_CR_OSEL
#define | RTC_OUTPUT_TAMPER RTC_CR_TAMPOE

Define Documentation

#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0

Definition at line 268 of file stm32g0xx_hal_rtc.h.

#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1

Definition at line 269 of file stm32g0xx_hal_rtc.h.

#define RTC_OUTPUT_DISABLE 0x00000000u

Definition at line 267 of file stm32g0xx_hal_rtc.h.

#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE

Definition at line 271 of file stm32g0xx_hal_rtc.h.

#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL

Definition at line 270 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH 0x00000000u
#define | RTC_OUTPUT_POLARITY_LOW RTC_CR_POL

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u

Definition at line 279 of file stm32g0xx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL

Definition at line 280 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u
#define | RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE

Define Documentation

#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE

Definition at line 289 of file stm32g0xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u

Definition at line 288 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Output Pull-Up ALARM OUT

Defines
RTC Output Pull-Up ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_PULLUP_NONE 0x00000000u
#define | RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU

Define Documentation

#define RTC_OUTPUT_PULLUP_NONE 0x00000000u

Definition at line 297 of file stm32g0xx_hal_rtc.h.

#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU

Definition at line 298 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Output ALARM OUT Remap

Defines
RTC Output ALARM OUT Remap
RTC Exported Constants

Defines

#define | RTC_OUTPUT_REMAP_NONE 0x00000000u
#define | RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN

Define Documentation

#define RTC_OUTPUT_REMAP_NONE 0x00000000u

Definition at line 306 of file stm32g0xx_hal_rtc.h.

#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN

Definition at line 307 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM 0x0u
#define | RTC_HOURFORMAT12_PM 0x1u

Define Documentation

#define RTC_HOURFORMAT12_AM 0x0u

Definition at line 315 of file stm32g0xx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM 0x1u

Definition at line 316 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC DayLightSaving Definitions

Defines
RTC DayLightSaving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define | RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define | RTC_DAYLIGHTSAVING_NONE 0x00000000u

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H

Definition at line 325 of file stm32g0xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE 0x00000000u

Definition at line 326 of file stm32g0xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H

Definition at line 324 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC StoreOperation Definitions

Defines
RTC StoreOperation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET 0x00000000u
#define | RTC_STOREOPERATION_SET RTC_CR_BKP

Define Documentation

#define RTC_STOREOPERATION_RESET 0x00000000u

Definition at line 334 of file stm32g0xx_hal_rtc.h.

#define RTC_STOREOPERATION_SET RTC_CR_BKP

Definition at line 335 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Input Parameter Format Definitions

Defines
RTC Input Parameter Format Definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN 0x00000000u
#define | RTC_FORMAT_BCD 0x00000001u

Define Documentation

#define RTC_FORMAT_BCD 0x00000001u

Definition at line 344 of file stm32g0xx_hal_rtc.h.

#define RTC_FORMAT_BIN 0x00000000u

Definition at line 343 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Month Date Definitions

Defines
RTC Month Date Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | RTC_MONTH_MAY ((uint8_t)0x05U)
#define | RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | RTC_MONTH_JULY ((uint8_t)0x07U)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04U)

Definition at line 357 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08U)

Definition at line 361 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Definition at line 365 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)

Definition at line 355 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01U)

Definition at line 354 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07U)

Definition at line 360 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06U)

Definition at line 359 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03U)

Definition at line 356 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05U)

Definition at line 358 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)

Definition at line 364 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)

Definition at line 363 of file stm32g0xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)

Definition at line 362 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)

Definition at line 378 of file stm32g0xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)

Definition at line 374 of file stm32g0xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)

Definition at line 379 of file stm32g0xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Definition at line 380 of file stm32g0xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)

Definition at line 377 of file stm32g0xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)

Definition at line 375 of file stm32g0xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)

Definition at line 376 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC AlarmDateWeekDay Definitions

Defines
RTC AlarmDateWeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u

Definition at line 389 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Definition at line 390 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC AlarmMask Definitions

Defines
RTC AlarmMask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE 0x00000000u
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL

Define Documentation

#define RTC_ALARMMASK_ALL
Value:
(RTC_ALARMMASK_NONE | RTC_ALARMMASK_DATEWEEKDAY | \
                                            RTC_ALARMMASK_HOURS | RTC_ALARMMASK_MINUTES     | \
                                            RTC_ALARMMASK_SECONDS)

Definition at line 404 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 400 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 401 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 402 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMMASK_NONE 0x00000000u

Definition at line 399 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 403 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 415 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 416 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL 0x00000000u
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 426 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

SS[14:0] are compared and must match to activate alarm.

Definition at line 457 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14] not used in Alarm comparison.Only SS[13:0] are compared

Definition at line 455 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0

SS[14:1] not used in Alarm comparison. Only SS[0] is compared.

Definition at line 429 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

SS[14:10] not used in Alarm comparison. Only SS[9:0] are compared

Definition at line 447 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

SS[14:11] not used in Alarm comparison. Only SS[10:0] are compared

Definition at line 449 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14:12] not used in Alarm comparison.Only SS[11:0] are compared

Definition at line 451 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

SS[14:13] not used in Alarm comparison. Only SS[12:0] are compared

Definition at line 453 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1

SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared

Definition at line 431 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)

SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared

Definition at line 433 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2

SS[14:4] not used in Alarm comparison. Only SS[3:0] are compared

Definition at line 435 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)

SS[14:5] not used in Alarm comparison. Only SS[4:0] are compared

Definition at line 437 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

SS[14:6] not used in Alarm comparison. Only SS[5:0] are compared

Definition at line 439 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

SS[14:7] not used in Alarm comparison. Only SS[6:0] are compared

Definition at line 441 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3

SS[14:8] not used in Alarm comparison. Only SS[7:0] are compared

Definition at line 443 of file stm32g0xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)

SS[14:9] not used in Alarm comparison. Only SS[8:0] are compared

Definition at line 445 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS RTC_CR_TSIE
#define | RTC_IT_WUT RTC_CR_WUTIE
#define | RTC_IT_ALRA RTC_CR_ALRAIE
#define | RTC_IT_ALRB RTC_CR_ALRBIE

Define Documentation

#define RTC_IT_ALRA RTC_CR_ALRAIE

Enable Alarm A Interrupt

Definition at line 468 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_ALRB RTC_CR_ALRBIE

Enable Alarm B Interrupt

Definition at line 469 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_TS RTC_CR_TSIE

Enable Timestamp Interrupt

Definition at line 466 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define RTC_IT_WUT RTC_CR_WUTIE

Enable Wakeup timer Interrupt

Definition at line 467 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Flag Mask (5bits) describe in RTC_Flags_Definitions

Defines
RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
RTC Exported Constants

Defines

#define RTC_FLAG_MASK 0x001Fu

Define Documentation

#define RTC_FLAG_MASK 0x001Fu

RTC flags mask (5bits)

Definition at line 477 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Elements values convention: 000000XX000YYYYYb. More...

Defines

#define | RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos)
#define | RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos)
#define | RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos)
#define | RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos)
#define | RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos)
#define | RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos)
#define | RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos)
#define | RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos)
#define | RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos)
#define | RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos)
#define | RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos)
#define | RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos)
#define | RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos)
#define | RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos)

Detailed Description

Elements values convention: 000000XX000YYYYYb.

  • YYYYY : Interrupt flag position in the XX register (5bits)
  • XX : Interrupt status register (2bits)
    • 01: ICSR register
    • 10: SR or SCR or MISR or SMISR registers

Define Documentation

#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos)

Alarm A flag

Definition at line 503 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos)

Alarm A write flag

Definition at line 497 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos)

Alarm B flag

Definition at line 502 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), and HAL_RTCEx_PollForAlarmBEvent().

#define RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos)

Alarm B write flag

Definition at line 496 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos)

Initialization flag

Definition at line 491 of file stm32g0xx_hal_rtc.h.

#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos)

Initialization status flag

Definition at line 493 of file stm32g0xx_hal_rtc.h.

#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos)

Internal Time-stamp flag

Definition at line 498 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp().

#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos)

Recalibration pending Flag

Definition at line 490 of file stm32g0xx_hal_rtc.h.

#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos)

Registers synchronization flag

Definition at line 492 of file stm32g0xx_hal_rtc.h.

#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos)

Shift operation pending flag

Definition at line 494 of file stm32g0xx_hal_rtc.h.

#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos)

Time-stamp flag

Definition at line 500 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), and HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos)

Time-stamp overflow flag

Definition at line 499 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos)

Wakeup timer flag

Definition at line 501 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos)

Wakeup timer write flag

Definition at line 495 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Clear Flags Definitions

Defines
RTC Clear Flags Definitions
RTC Exported Constants

Defines

#define | RTC_CLEAR_ITSF RTC_SCR_CITSF
#define | RTC_CLEAR_TSOVF RTC_SCR_CTSOVF
#define | RTC_CLEAR_TSF RTC_SCR_CTSF
#define | RTC_CLEAR_WUTF RTC_SCR_CWUTF
#define | RTC_CLEAR_ALRBF RTC_SCR_CALRBF
#define | RTC_CLEAR_ALRAF RTC_SCR_CALRAF

Define Documentation

#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF

Clear Alarm A flag

Definition at line 516 of file stm32g0xx_hal_rtc.h.

#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF

Clear Alarm B flag

Definition at line 515 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), and HAL_RTC_SetAlarm_IT().

#define RTC_CLEAR_ITSF RTC_SCR_CITSF

Clear Internal Time-stamp flag

Definition at line 511 of file stm32g0xx_hal_rtc.h.

#define RTC_CLEAR_TSF RTC_SCR_CTSF

Clear Time-stamp flag

Definition at line 513 of file stm32g0xx_hal_rtc.h.

#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF

Clear Time-stamp overflow flag

Definition at line 512 of file stm32g0xx_hal_rtc.h.

#define RTC_CLEAR_WUTF RTC_SCR_CWUTF

Clear Wakeup timer flag

Definition at line 514 of file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
Check whether the RTC Calendar is initialized.
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)
Add 1 hour (summer time change).
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)
Subtract 1 hour (winter time change).
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR)& ((__INTERRUPT__)>> 12U)) != 0U)? 1U : 0U)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC Alarms flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the RTC Alarms pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == RTC_FLAG_ALRAF) ? (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ALRAF)) : \
                                                            (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ALRBF)))

Clear the RTC Alarms pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 704 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 658 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA Alarm A interrupt, RTC Interrupts Definitions
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 647 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 729 of file stm32g0xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 717 of file stm32g0xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 723 of file stm32g0xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 711 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))

Get the selected RTC Alarms flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
  • RTC_FLAG_ALRAWF
  • RTC_FLAG_ALRBWF
Return values:
None

Definition at line 693 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->SR)& ((__INTERRUPT__)>> 12U)) != 0U)? 1U : 0U)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 669 of file stm32g0xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Alarm interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA Alarm A interrupt
  • RTC_IT_ALRB Alarm B interrupt
Return values:
None

Definition at line 680 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 622 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 615 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 636 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 629 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H | ( | __HANDLE__,
 |  | __BKP__
 | ) |
Value:
do {                                                              \
                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
                            SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H);            \
                            MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
                        } while(0);

Add 1 hour (summer time change).

Note:
This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
Parameters:
__HANDLE__ specifies the RTC handle.
__BKP__ Backup This parameter can be:
  • RTC_STOREOPERATION_RESET
  • RTC_STOREOPERATION_SET
Return values:
None

Definition at line 583 of file stm32g0xx_hal_rtc.h.

#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H | ( | __HANDLE__,
 |  | __BKP__
 | ) |
Value:
do {                                                              \
                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
                            SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H);            \
                            MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
                        } while(0);

Subtract 1 hour (winter time change).

Note:
This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
Parameters:
__HANDLE__ specifies the RTC handle.
__BKP__ Backup This parameter can be:
  • RTC_STOREOPERATION_RESET
  • RTC_STOREOPERATION_SET
Return values:
None

Definition at line 602 of file stm32g0xx_hal_rtc.h.

#define __HAL_RTC_IS_CALENDAR_INITIALIZED ( __HANDLE__ ) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)

Check whether the RTC Calendar is initialized.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 570 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;\
                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
                                                     }while(0)

Reset RTC handle state.

Parameters:
__HANDLE__ RTC handle.
Return values:
None

Definition at line 535 of file stm32g0xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xCAU;   \
                            (__HANDLE__)->Instance->WPR = 0x53U;   \
                          } while(0U)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 549 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_DST_Add1Hour(), HAL_RTC_DST_ClearStoreOperation(), HAL_RTC_DST_SetStoreOperation(), HAL_RTC_DST_Sub1Hour(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xFFU;   \
                          } while(0U)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 560 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_DST_Add1Hour(), HAL_RTC_DST_ClearStoreOperation(), HAL_RTC_DST_SetStoreOperation(), HAL_RTC_DST_Sub1Hour(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callback is redirected to the weak predefined callback.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provides functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC peripheral.

Note:
This function does not reset the RTC Backup Data registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 358 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::MspDeInitCallback, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initialize the RTC peripheral.

Parameters:
hrtc RTC handle
Return values:
HAL status

< Legacy weak InternalTamper3EventCallback

< Legacy weak InternalTamper4EventCallback

< Legacy weak InternalTamper5EventCallback

< Legacy weak InternalTamper6EventCallback

Definition at line 242 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_IS_CALENDAR_INITIALIZED, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_AlarmAEventCallback(), HAL_RTC_MspDeInit(), HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), RTC_InitTypeDef::HourFormat, __RTC_HandleTypeDef::Init, __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_PULLUP, IS_RTC_OUTPUT_REMAP, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, __RTC_HandleTypeDef::Lock, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutPullUp, RTC_InitTypeDef::OutPutRemap, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), RTC_ExitInitMode(), __RTC_HandleTypeDef::State, RTC_InitTypeDef::SynchPrediv, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TampOffset, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 715 of file stm32g0xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 700 of file stm32g0xx_hal_rtc.c.

Referenced by HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

HAL_StatusTypeDef HAL_RTC_RegisterCallback | ( | RTC_HandleTypeDef * | hrtc,
 |  | HAL_RTC_CallbackIDTypeDef | CallbackID,
 |  | pRTC_CallbackTypeDef | pCallback
 | ) |  |

Register a User RTC Callback To be used instead of the weak predefined callback.

Parameters:
hrtc | RTC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
  • HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
  • HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
  • HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
  • HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID (*)
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
  • HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
  • HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 465 of file stm32g0xx_hal_rtc.c.

References __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_ALARM_A_EVENT_CB_ID, HAL_RTC_ALARM_B_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID, HAL_RTC_MSPDEINIT_CB_ID, HAL_RTC_MSPINIT_CB_ID, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_TAMPER1_EVENT_CB_ID, HAL_RTC_TAMPER2_EVENT_CB_ID, HAL_RTC_TAMPER3_EVENT_CB_ID, HAL_RTC_TIMESTAMP_EVENT_CB_ID, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

HAL_StatusTypeDef HAL_RTC_UnRegisterCallback | ( | RTC_HandleTypeDef * | hrtc,
 |  | HAL_RTC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an RTC Callback RTC callback is redirected to the weak predefined callback.

Parameters:
hrtc RTC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
  • HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
  • HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
  • HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
  • HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID (*)
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
  • HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
  • HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
Return values:
HAL status

Definition at line 592 of file stm32g0xx_hal_rtc.c.

References __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_ALARM_A_EVENT_CB_ID, HAL_RTC_ALARM_B_EVENT_CB_ID, HAL_RTC_AlarmAEventCallback(), HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID, HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID, HAL_RTC_MspDeInit(), HAL_RTC_MSPDEINIT_CB_ID, HAL_RTC_MspInit(), HAL_RTC_MSPINIT_CB_ID, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_TAMPER1_EVENT_CB_ID, HAL_RTC_TAMPER2_EVENT_CB_ID, HAL_RTC_TAMPER3_EVENT_CB_ID, HAL_RTC_TIMESTAMP_EVENT_CB_ID, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
void | HAL_RTC_DST_Add1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_Sub1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_SetStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Set the store operation bit.
void | HAL_RTC_DST_ClearStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Clear the store operation bit.
uint32_t | HAL_RTC_DST_ReadStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Read the store operation bit.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

void HAL_RTC_DST_Add1Hour ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1854 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_ClearStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Clear the store operation bit.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1892 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

uint32_t HAL_RTC_DST_ReadStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Read the store operation bit.

Parameters:
hrtc RTC handle
Return values:
operation see RTC_StoreOperation_Definitions

Definition at line 1904 of file stm32g0xx_hal_rtc.c.

References __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_SetStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Set the store operation bit.

Note:
It can be used by the software in order to memorize the DST status.
Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1880 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_Sub1Hour ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1867 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Get RTC current date.

Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Parameters:
hrtc | RTC handle
sDate | Pointer to Date structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 991 of file stm32g0xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Get RTC current time.

Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read to ensure consistency between the time and date values.
Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure with Hours, Minutes and Seconds fields returned with input format (BIN or BCD), also SubSeconds field returning the RTC_SSR register content and SecondFraction field the Synchronous pre-scaler factor to be used for second fraction ratio computation.
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 863 of file stm32g0xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::SecondFraction, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Set RTC current date.

Parameters:
hrtc | RTC handle
sDate | Pointer to date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 907 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_FORMAT_BIN, __RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Set RTC current time.

Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 753 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1612 of file stm32g0xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Alarm interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1563 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARM_GET_IT_SOURCE, __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), RTC_CLEAR_ALRBF, RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactivate the specified RTC Alarm.

Parameters:
hrtc RTC handle
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1408 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Date structure
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1502 of file stm32g0xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle AlarmA Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1628 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1045 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm with Interrupt.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1227 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_CLEAR_ALRBF, RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1687 of file stm32g0xx_hal_rtc.c.

References HAL_GetTick(), __RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTCEx_SetSynchroShift(), and RTC_ExitInitMode().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Return the RTC handle state.

Parameters:
hrtc RTC handle
Return values:
HAL state

Definition at line 1731 of file stm32g0xx_hal_rtc.c.

References __RTC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK
#define | RTC_DR_RESERVED_MASK
#define | RTC_INIT_MASK 0xFFFFFFFFu
#define | RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#define | RTC_TIMEOUT_VALUE 1000u
#define | RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM19

Define Documentation

#define RTC_DR_RESERVED_MASK
Value:
(RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
                                            RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
                                            RTC_DR_DU)

Definition at line 827 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM19

External interrupt line 19 Connected to the RTC Alarm event

Definition at line 835 of file stm32g0xx_hal_rtc.h.

#define RTC_INIT_MASK 0xFFFFFFFFu

Definition at line 830 of file stm32g0xx_hal_rtc.h.

#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))

Definition at line 831 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000u

Definition at line 833 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK
Value:
(RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
                                            RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
                                            RTC_TR_SU)

Definition at line 824 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_PULLUP(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT)
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)
#define | IS_RTC_ALARM(ALARM)
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7Fu)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFu)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)

Define Documentation

#define IS_RTC_ALARM ( ALARM )
Value:
(((ALARM) == RTC_ALARM_A) || \
                                  ((ALARM) == RTC_ALARM_B))

Definition at line 912 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) >0u) && ((DATE) <= 31u))

Definition at line 897 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 907 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 899 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( MASK ) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)

Definition at line 910 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))

Definition at line 917 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= RTC_ALRMASSR_SS)

Definition at line 915 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= 0x7Fu)

Definition at line 934 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= 1u) && ((DATE) <= 31u))

Definition at line 887 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 873 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_FORMAT_BIN) || \
                               ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 880 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > 0u) && ((HOUR) <= 12u))

Definition at line 938 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= 23u)

Definition at line 940 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HOURFORMAT_12) || \
                                        ((FORMAT) == RTC_HOURFORMAT_24))

Definition at line 855 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( PM )
Value:
(((PM) == RTC_HOURFORMAT12_AM) || \
                                  ((PM) == RTC_HOURFORMAT12_PM))

Definition at line 870 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= 59u)

Definition at line 942 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= 1u) && ((MONTH) <= 12u))

Definition at line 885 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_OUTPUT_DISABLE) || \
                                ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
                                ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
                                ((OUTPUT) == RTC_OUTPUT_WAKEUP)  || \
                                ((OUTPUT) == RTC_OUTPUT_TAMPER))

Definition at line 849 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 858 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_PULLUP ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
                                    ((TYPE) == RTC_OUTPUT_PULLUP_ON))

Definition at line 864 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_REMAP ( REMAP )
Value:
(((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))

Definition at line 867 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 861 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= 59u)

Definition at line 944 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                           ((OPERATION) == RTC_STOREOPERATION_SET))

Definition at line 877 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= 0x7FFFu)

Definition at line 936 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 889 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= 99u)

Definition at line 883 of file stm32g0xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Private Functions

Functions
RTC Private Functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
HAL_StatusTypeDef | RTC_ExitInitMode (RTC_HandleTypeDef *hrtc)
Exit the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.
void | HAL_RTC_DST_Add1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_Sub1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_SetStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Set the store operation bit.
void | HAL_RTC_DST_ClearStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Clear the store operation bit.
uint32_t | HAL_RTC_DST_ReadStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Read the store operation bit.

Function Documentation

void HAL_RTC_DST_Add1Hour ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1854 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_ClearStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Clear the store operation bit.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1892 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

uint32_t HAL_RTC_DST_ReadStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Read the store operation bit.

Parameters:
hrtc RTC handle
Return values:
operation see RTC_StoreOperation_Definitions

Definition at line 1904 of file stm32g0xx_hal_rtc.c.

References __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_SetStoreOperation ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Set the store operation bit.

Note:
It can be used by the software in order to memorize the DST status.
Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1880 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

void HAL_RTC_DST_Sub1Hour ( RTC_HandleTypeDef * hrtc )

Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1867 of file stm32g0xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, and __RTC_HandleTypeDef::Instance.

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Convert from 2 digit BCD to Binary.

Parameters:
Value BCD value to be converted
Return values:
Converted word

Definition at line 1841 of file stm32g0xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Convert a 2 digit decimal to BCD format.

Parameters:
Value Byte to be converted
Return values:
Converted byte

Definition at line 1822 of file stm32g0xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enter the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1754 of file stm32g0xx_hal_rtc.c.

References HAL_GetTick(), HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

HAL_StatusTypeDef RTC_ExitInitMode ( RTC_HandleTypeDef * hrtc )

Exit the RTC Initialization mode.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1785 of file stm32g0xx_hal_rtc.c.

References HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), and __RTC_HandleTypeDef::State.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTCEx Tamper structure definition

#include <stm32g0xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Trigger
uint32_t | NoErase
uint32_t | MaskFlag
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

Definition at line 46 of file stm32g0xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the TAMP Filter Tamper. This parameter can be a value of RTCEx Tamper Filter

Definition at line 60 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::MaskFlag

Specifies the Tamper Flag masking. This parameter can be a value of RTCEx Tamper MaskFlag

Definition at line 57 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::NoErase

Specifies the Tamper no erase mode. This parameter can be a value of RTCEx Tamper EraseBackUp

Definition at line 54 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTCEx Tamper Pin Precharge Duration

Definition at line 66 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTCEx Tamper Sampling Frequencies

Definition at line 63 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTCEx Tamper Pins Definition

Definition at line 48 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTCEx Tamper Pull UP

Definition at line 69 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTCEx Tamper TimeStamp On Tamper Detection Definitions

Definition at line 72 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTCEx Tamper Trigger

Definition at line 51 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rtc_ex.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC_InternalTamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InternalTamperTypeDef Struct Reference
RTCEx Internal Tamper structure definition

#include <stm32g0xx_hal_rtc_ex.h>

Data Fields

uint32_t | IntTamper
uint32_t | TimeStampOnTamperDetection

Detailed Description

Definition at line 83 of file stm32g0xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_InternalTamperTypeDef::IntTamper

Specifies the Internal Tamper Pin. This parameter can be a value of RTCEx Internal Tamper Pins Definition

Definition at line 85 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

uint32_t RTC_InternalTamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTCEx Tamper TimeStamp On Tamper Detection Definitions

Definition at line 88 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_rtc_ex.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Time Stamp Edges definition

Defines
RTCEx Time Stamp Edges definition
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING 0x00000000u
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Definition at line 108 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING 0x00000000u

Definition at line 107 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx TimeStamp Pin Selection

Defines
RTCEx TimeStamp Pin Selection
RTCEx Exported Constants

Defines

#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u

Definition at line 116 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Wakeup Timer Definitions

Defines
RTCEx Wakeup Timer Definitions
RTCEx Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2

Definition at line 128 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

Definition at line 129 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u

Definition at line 124 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)

Definition at line 127 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1

Definition at line 126 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0

Definition at line 125 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Smooth calib period Definitions

Defines
RTCEx Smooth calib period Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16

If RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK pulses

Definition at line 139 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u

If RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK pulses

Definition at line 137 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

If RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK pulses

Definition at line 141 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Smooth calib Plus pulses Definitions

Defines
RTCEx Smooth calib Plus pulses Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 153 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 150 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Calib Output selection Definitions

Defines
RTCEx Calib Output selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ 0x00000000u
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Define Documentation

#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Definition at line 163 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ 0x00000000u

Definition at line 162 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Add 1 Second Parameter Definitions

Defines
RTCEx Add 1 Second Parameter Definitions
RTCEx Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET 0x00000000u
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Define Documentation

#define RTC_SHIFTADD1S_RESET 0x00000000u

Definition at line 173 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Definition at line 174 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Tamper Pins Definition

Defines
RTCEx Tamper Pins Definition
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)

Define Documentation

#define RTC_TAMPER_1 TAMP_CR1_TAMP1E

Definition at line 182 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_TAMPER_2 TAMP_CR1_TAMP2E

Definition at line 183 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_TAMPER_3 TAMP_CR1_TAMP3E

Definition at line 185 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)

Definition at line 186 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Internal Tamper Pins Definition

Defines
RTCEx Internal Tamper Pins Definition
RTCEx Exported Constants

Defines

#define | RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
#define | RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E
#define | RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
#define | RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
#define | RTC_INT_TAMPER_ALL

Define Documentation

#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E

Definition at line 197 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E

Definition at line 198 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E

Definition at line 199 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E

Definition at line 200 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

#define RTC_INT_TAMPER_ALL
Value:
(TAMP_CR1_ITAMP3E | TAMP_CR1_ITAMP4E | \
                                             TAMP_CR1_ITAMP5E | TAMP_CR1_ITAMP6E)

Definition at line 201 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Tamper Trigger

Defines
RTCEx Tamper Trigger
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE 0x00u
#define | RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Define Documentation

#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u

Definition at line 211 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Definition at line 213 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE

Definition at line 212 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u

Definition at line 210 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Tamper MaskFlag

Defines
RTCEx Tamper MaskFlag
RTCEx Exported Constants

Defines

#define | RTC_TAMPERMASK_FLAG_DISABLE 0x00u
#define | RTC_TAMPERMASK_FLAG_ENABLE 0x01u

Define Documentation

#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u

Definition at line 221 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u

Definition at line 222 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Tamper EraseBackUp

Defines
RTCEx Tamper EraseBackUp
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u

Define Documentation

#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u

Definition at line 231 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u

Definition at line 230 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Tamper Filter

Defines
RTCEx Tamper Filter
RTCEx Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE 0x00000000U
#define | RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 240 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 242 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level

Definition at line 244 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 239 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Tamper Sampling Frequencies

Defines
RTCEx Tamper Sampling Frequencies
RTCEx Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 263 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 255 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 261 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
Value:
(TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
                                                  TAMP_FLTCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 267 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 253 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 259 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 265 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 257 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Tamper Pin Precharge Duration

Defines
RTCEx Tamper Pin Precharge Duration
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 277 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 279 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 281 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 283 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Tamper Pull UP

Defines
RTCEx Tamper Pull UP
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE 0x00000000u
#define | RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS

Tamper pins pre-charge is disabled

Definition at line 293 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u

Tamper pins are pre-charged before sampling

Definition at line 292 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Tamper TimeStamp On Tamper Detection Definitions

Defines
RTCEx Tamper TimeStamp On Tamper Detection Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u

TimeStamp on Tamper Detection event is not saved

Definition at line 301 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS

TimeStamp on Tamper Detection event saved

Definition at line 302 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Internal Tamper Interrupt

Defines
RTCEx Internal Tamper Interrupt
RTCEx Exported Constants

Defines

#define | RTC_IT_TAMP1 TAMP_IER_TAMP1IE
#define | RTC_IT_TAMP2 TAMP_IER_TAMP2IE
#define | RTC_IT_TAMP3 TAMP_IER_TAMP3IE
#define | RTC_IT_TAMPALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE)
#define | RTC_IT_INT_TAMP3 TAMP_IER_ITAMP3IE
#define | RTC_IT_INT_TAMP4 TAMP_IER_ITAMP4IE
#define | RTC_IT_INT_TAMP5 TAMP_IER_ITAMP5IE
#define | RTC_IT_INT_TAMP6 TAMP_IER_ITAMP6IE
#define | RTC_IT_INT_TAMPALL

Define Documentation

#define RTC_IT_INT_TAMP3 TAMP_IER_ITAMP3IE

Definition at line 320 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP4 TAMP_IER_ITAMP4IE

Definition at line 321 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP5 TAMP_IER_ITAMP5IE

Definition at line 322 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMP6 TAMP_IER_ITAMP6IE

Definition at line 323 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_IT_INT_TAMPALL
Value:
(RTC_IT_INT_TAMP3 | RTC_IT_INT_TAMP4 | \
                                            RTC_IT_INT_TAMP5 | RTC_IT_INT_TAMP6)

Definition at line 324 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_IT_TAMP1 TAMP_IER_TAMP1IE

Tamper 1 Interrupt

Definition at line 311 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_IT_TAMP2 TAMP_IER_TAMP2IE

Tamper 2 Interrupt

Definition at line 312 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_IT_TAMP3 TAMP_IER_TAMP3IE

Tamper 3 Interrupt

Definition at line 314 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_IT_TAMPALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE)

Definition at line 315 of file stm32g0xx_hal_rtc_ex.h.

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STM32G0C1xx HAL User Manual: RTCEx Flags

Defines
RTCEx Flags
RTCEx Exported Constants

Defines

#define | RTC_FLAG_TAMP1 TAMP_SR_TAMP1F
#define | RTC_FLAG_TAMP2 TAMP_SR_TAMP2F
#define | RTC_FLAG_TAMP3 TAMP_SR_TAMP3F
#define | RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3)
#define | RTC_FLAG_INT_TAMP3 TAMP_SR_ITAMP3F
#define | RTC_FLAG_INT_TAMP4 TAMP_SR_ITAMP4F
#define | RTC_FLAG_INT_TAMP5 TAMP_SR_ITAMP5F
#define | RTC_FLAG_INT_TAMP6 TAMP_SR_ITAMP6F
#define | RTC_FLAG_INT_TAMPALL

Define Documentation

#define RTC_FLAG_INT_TAMP3 TAMP_SR_ITAMP3F

Definition at line 341 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP4 TAMP_SR_ITAMP4F

Definition at line 342 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP5 TAMP_SR_ITAMP5F

Definition at line 343 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMP6 TAMP_SR_ITAMP6F

Definition at line 344 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_FLAG_INT_TAMPALL
Value:
(RTC_FLAG_INT_TAMP3 | RTC_FLAG_INT_TAMP4 | \
                                            RTC_FLAG_INT_TAMP5 | RTC_FLAG_INT_TAMP6)

Definition at line 345 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_FLAG_TAMP1 TAMP_SR_TAMP1F

Definition at line 333 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_FLAG_TAMP2 TAMP_SR_TAMP2F

Definition at line 334 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_FLAG_TAMP3 TAMP_SR_TAMP3F

Definition at line 336 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3)

Definition at line 337 of file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Backup Registers Definition

Defines
RTCEx Backup Registers Definition
RTCEx Exported Constants

Defines

#define | RTC_BKP_NUMBER 0x00000005u
#define | RTC_BKP_DR0 0x00000000u
#define | RTC_BKP_DR1 0x00000001u
#define | RTC_BKP_DR2 0x00000002u
#define | RTC_BKP_DR3 0x00000003u
#define | RTC_BKP_DR4 0x00000004u

Define Documentation

#define RTC_BKP_DR0 0x00000000u

Definition at line 356 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_BKP_DR1 0x00000001u

Definition at line 357 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 0x00000002u

Definition at line 358 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 0x00000003u

Definition at line 359 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 0x00000004u

Definition at line 360 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_BKP_NUMBER 0x00000005u

Definition at line 355 of file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC WakeUp Timer

Defines
RTC WakeUp Timer
RTCEx Exported Macros

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC WakeUpTimers flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
Clear the RTC Wake Up timers pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.

Define Documentation

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))

Clear the RTC Wake Up timers pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag to clear. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 488 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 427 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 447 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer().

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 420 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 437 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 514 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 502 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 508 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 496 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))

Get the selected RTC WakeUpTimers flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. This parameter can be:
  • RTC_FLAG_WUTF
  • RTC_FLAG_WUTWF
Return values:
None

Definition at line 478 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 457 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Wake Up timer interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT WakeUpTimer interrupt
Return values:
None

Definition at line 467 of file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Timestamp

Defines
RTC Timestamp
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
Get the selected RTC TimeStamps flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
Clear the RTC Time Stamps pending flags.
#define | __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
Enable interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
Disable interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
Enable event on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
Disable event on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
Get the selected RTC Internal Time Stamps flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
Clear the RTC Internal Time Stamps pending flags.
#define | __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))
Enable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))
Disable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
Enable the RTC Tamper detection output.
#define | __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
Disable the RTC Tamper detection output.

Define Documentation

#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))

Clear the RTC Internal Time Stamps pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 656 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))

Disable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 636 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))

Enable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 629 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))

Get the selected RTC Internal Time Stamps flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 646 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPOE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))

Disable the RTC Tamper detection output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 684 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))

Enable the RTC Tamper detection output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 677 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPTS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))

Disable the RTC TimeStamp on Tamper detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 670 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPTS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))

Enable the RTC TimeStamp on Tamper detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 663 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))

Clear the RTC Time Stamps pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC TimeStamp Flag to clear. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 598 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), and HAL_RTCEx_PollForTimeStampEvent().

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 536 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 556 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 529 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 546 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))

Disable event on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 622 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))

Disable interrupt on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 610 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)

Enable event on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 616 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)

Enable interrupt on the RTC Timestamp associated Exti line.

Return values:
None

Definition at line 604 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))

Get the selected RTC TimeStamps flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC TimeStamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 587 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt to check. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 566 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Time Stamp interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS TimeStamp interrupt
Return values:
None

Definition at line 576 of file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Calibration

Defines
RTC Calibration
RTCEx Exported Macros

Defines

#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC shift operations flag status.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 709 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCalibrationOutPut().

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 702 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 724 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateRefClock().

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 717 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetRefClock().

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))

Get the selected RTC shift operations flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
None

Definition at line 735 of file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx tamper

Defines
RTCEx tamper
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 |= (__TAMPER__))
Enable the TAMP Tamper input detection.
#define | __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 &= ~(__TAMPER__))
Disable the TAMP Tamper input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER |= (__INTERRUPT__))
Enable the TAMP Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER &= ~(__INTERRUPT__))
Disable the TAMP Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified TAMP Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified TAMP Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__FLAG__)) != 0U)
Get the selected TAMP Tampers flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SCR) |= (__FLAG__))
Clear the TAMP Tampers pending flags.
#define | __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable interrupt on the TAMP associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
Disable interrupt on the TAMP associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable event on the TAMP associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
Disable event on the TAMP associated Exti line.

Define Documentation

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SCR) |= (__FLAG__))

Clear the TAMP Tampers pending flags.

Parameters:
__HANDLE__ specifies the TAMP handle.
__FLAG__ specifies the TAMP Tamper Flag to clear. This parameter can be:
  • RTC_FLAG_TAMPALL: All Tamper flags
  • RTC_FLAG_TAMP1: Tamper1 flag
  • RTC_FLAG_TAMP2: Tamper2 flag
  • RTC_FLAG_TAMP3: Tamper3 flag (*)
  • RTC_FLAG_INT_TAMP3: Internal Tamper3 flag
  • RTC_FLAG_INT_TAMP4: Internal Tamper4 flag
  • RTC_FLAG_INT_TAMP5: Internal Tamper5 flag
  • RTC_FLAG_INT_TAMP6: Internal Tamper6 flag
Return values:
None

Definition at line 868 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_DISABLE | ( | __HANDLE__,
 |  | __TAMPER__
 | ) | (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 &= ~(__TAMPER__))

Disable the TAMP Tamper input detection.

Parameters:
__HANDLE__ specifies the TAMP handle.
__TAMPER__ specifies the TAMP Tamper sources to be enabled. This parameter can be any combination of the following values:
  • RTC_ALL_TAMPER: All tampers
  • RTC_TAMPER_1: Tamper1
  • RTC_TAMPER_2: Tamper2
  • RTC_TAMPER_3: Tamper3 (*)

Definition at line 768 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER &= ~(__INTERRUPT__))

Disable the TAMP Tamper interrupt.

Parameters:
__HANDLE__ specifies the TAMP handle.
__INTERRUPT__ specifies the TAMP Tamper interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMPALL: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
Return values:
None

Definition at line 796 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE | ( | __HANDLE__,
 |  | __TAMPER__
 | ) | (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 |= (__TAMPER__))

Enable the TAMP Tamper input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
__TAMPER__ specifies the RTC Tamper source to be enabled. This parameter can be any combination of the following values:
  • RTC_ALL_TAMPER: All tampers
  • RTC_TAMPER_1: Tamper1
  • RTC_TAMPER_2: Tamper2
  • RTC_TAMPER_3: Tamper3 (*)
Return values:
None

Definition at line 756 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER |= (__INTERRUPT__))

Enable the TAMP Tamper interrupt.

Parameters:
__HANDLE__ specifies the TAMP handle.
__INTERRUPT__ specifies the TAMP Tamper interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMPALL: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
Return values:
None

Definition at line 783 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))

Disable event on the TAMP associated Exti line.

Return values:
None

Definition at line 892 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))

Disable interrupt on the TAMP associated Exti line.

Return values:
None

Definition at line 880 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)

Enable event on the TAMP associated Exti line.

Return values:
None

Definition at line 886 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)

Enable interrupt on the TAMP associated Exti line.

Return values:
None

Definition at line 874 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper_IT(), and HAL_RTCEx_SetTamper_IT().

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__FLAG__)) != 0U)

Get the selected TAMP Tampers flag status.

Parameters:
__HANDLE__ specifies the TAMP handle.
__FLAG__ specifies the TAMP Tamper Flag is pending or not. This parameter can be:
  • RTC_FLAG_TAMP1: Tamper1 flag
  • RTC_FLAG_TAMP2: Tamper2 flag
  • RTC_FLAG_TAMP3: Tamper3 flag (*)
  • RTC_FLAG_INT_TAMP3: Internal Tamper3 flag
  • RTC_FLAG_INT_TAMP4: Internal Tamper4 flag
  • RTC_FLAG_INT_TAMP5: Internal Tamper5 flag
  • RTC_FLAG_INT_TAMP6: Internal Tamper6 flag
Return values:
None

Definition at line 851 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified TAMP Tamper interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the TAMP handle.
__INTERRUPT__ specifies the TAMP Tamper interrupt to check. This parameter can be:
  • RTC_IT_TAMPALL: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
  • RTC_IT_INT_TAMP3: Internal Tamper3 interrupt
  • RTC_IT_INT_TAMP4: Internal Tamper4 interrupt
  • RTC_IT_INT_TAMP5: Internal Tamper5 interrupt
  • RTC_IT_INT_TAMP6: Internal Tamper6 interrupt
Return values:
None

Definition at line 815 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified TAMP Tamper interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the TAMP handle.
__INTERRUPT__ specifies the TAMP Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMPALL: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
  • RTC_IT_INT_TAMPALL: All internal tampers interrupts
  • RTC_IT_INT_TAMP3: Internal Tamper3 interrupt
  • RTC_IT_INT_TAMP4: Internal Tamper4 interrupt
  • RTC_IT_INT_TAMP5: Internal Tamper5 interrupt
  • RTC_IT_INT_TAMP6: Internal Tamper6 interrupt
Return values:
None

Definition at line 834 of file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Exported Macros

Modules | Defines
RTCEx Exported Macros
RTCEx

Modules

RTC WakeUp Timer
RTC Timestamp
RTC Calibration
RTCEx tamper

Defines

#define | __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= (__FLAG__))
Clear the specified RTC pending flag.
#define | __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified RTC flag is set or not.

Define Documentation

#define __HAL_RTC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SCR |= (__FLAG__))

Clear the specified RTC pending flag.

Parameters:
__HANDLE__ specifies the RTC Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • RTC_CLEAR_ITSF Clear Internal Time-stamp flag
  • RTC_CLEAR_TSOVF Clear Time-stamp overflow flag
  • RTC_CLEAR_TSF Clear Time-stamp flag
  • RTC_CLEAR_WUTF Clear Wakeup timer flag
  • RTC_CLEAR_ALRBF Clear Alarm B flag
  • RTC_CLEAR_ALRAF Clear Alarm A flag
Return values:
None

Definition at line 386 of file stm32g0xx_hal_rtc_ex.h.

#define __HAL_RTC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U) :\
                                                     ((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U))

Check whether the specified RTC flag is set or not.

Parameters:
__HANDLE__ specifies the RTC Handle.
__FLAG__ specifies the flag to check. This parameter can be:
  • RTC_FLAG_RECALPF Recalibration pending Flag
  • RTC_FLAG_INITF Initialization flag
  • RTC_FLAG_RSF Registers synchronization flag
  • RTC_FLAG_INITS Initialization status flag
  • RTC_FLAG_SHPF Shift operation pending flag
  • RTC_FLAG_WUTWF Wakeup timer write flag
  • RTC_FLAG_ALRBWF Alarm B write flag
  • RTC_FLAG_ALRAWF Alarm A write flag
  • RTC_FLAG_ITSF Internal Time-stamp flag
  • RTC_FLAG_TSOVF Time-stamp overflow flag
  • RTC_FLAG_TSF Time-stamp flag
  • RTC_FLAG_WUTF Wakeup timer flag
  • RTC_FLAG_ALRBF Alarm B flag
  • RTC_FLAG_ALRAF Alarm A flag
Return values:
None

Definition at line 408 of file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended RTC TimeStamp functions

Functions
Extended RTC TimeStamp functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
void | HAL_RTCEx_TimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate Internal TimeStamp.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 347 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate TimeStamp.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 279 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_IT_TS, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Get the RTC TimeStamp value.

Parameters:
hrtc | RTC handle
sTimeStamp | Pointer to Time structure
sTimeStampDate | Pointer to Date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 382 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_ITSF, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle TimeStamp polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 476 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Set Internal TimeStamp.

Note:
This API must be called before enabling the internal TimeStamp feature.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 317 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc RTC handle
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 169 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp with Interrupt.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc RTC handle
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 228 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_IT_TS, and __RTC_HandleTypeDef::State.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 432 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TimeStampIRQHandler().

void HAL_RTCEx_TimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle TimeStamp interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 448 of file stm32g0xx_hal_rtc_ex.c.

References HAL_RTC_STATE_READY, HAL_RTCEx_TimeStampEventCallback(), __RTC_HandleTypeDef::State, and __RTC_HandleTypeDef::TimeStampEventCallback.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended RTC Wake-up functions

Functions
Extended RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Wake-up feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivate wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 685 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Get wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
Counter value

Definition at line 737 of file stm32g0xx_hal_rtc_ex.c.

References __RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Wake Up Timer Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 791 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 534 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer with interrupt.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 606 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTF, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 774 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Wake Up Timer interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 748 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), RTC_FLAG_WUTF, __RTC_HandleTypeDef::State, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RTCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Coarse calibration parameters.
      (+) Deactivate the Coarse calibration parameters
      (+) Set the Smooth calibration parameters.
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1067 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1138 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_EnterInitMode(), RTC_ExitInitMode(), and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disable the Bypass Shadow feature.

Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1214 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enable the Bypass Shadow feature.

Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1182 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
CalibOutput Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1029 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1096 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_EnterInitMode(), RTC_ExitInitMode(), and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmoothCalibMinusPulsesValue
 | ) |  |

Set the Smooth calibration parameters.

Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmoothCalibMinusPulsesValue must be equal to 0.
Parameters:
hrtc | RTC handle
SmoothCalibPeriod Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmoothCalibMinusPulsesValue | Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Return values:
HAL status

Definition at line 868 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configure the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc | RTC handle
ShiftAdd1S Select to add or not 1 second to the time calendar. This parameter can be one of the following values:
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS | Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 936 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alarm B callback
      (+) RTC Poll for Alarm B request

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1263 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Alarm B Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1279 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and __RTC_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended RTC Tamper functions

Functions
Extended RTC Tamper functions
RTCEx Exported Functions

Extended RTC Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper in IT mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
Tamper event polling.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.

Detailed Description

Extended RTC Tamper functions.

  ==============================================================================
                         ##### Tamper functions #####
  ==============================================================================
  [..]
   (+) Before calling any tamper or internal tamper function, you have to call first
       HAL_RTC_Init() function.
   (+) In that ine you can select to output tamper event on RTC pin.
  [..]
   (+) Enable the Tamper and configure the Tamper filter count, trigger Edge
       or Level according to the Tamper filter (if equal to 0 Edge else Level)
       value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
       Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function.
       You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
   (+) The default configuration of the Tamper erases the backup registers. To avoid
       erase, enable the NoErase field on the TAMP_TAMPCR register.
  [..]
   (+) Enable Internal Tamper and configure it with interrupt, timestamp using
       the HAL_RTCEx_SetInternalTamper() function.

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | IntTamper
 | ) |  |

Deactivate Internal Tamper.

Parameters:
hrtc | RTC handle
IntTamper | Selected internal tamper event. This parameter can be any combination of existing internal tampers.
Return values:
HAL status

Definition at line 1615 of file stm32g0xx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, IS_RTC_INTERNAL_TAMPER, and __RTC_HandleTypeDef::TampOffset.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivate Tamper.

Parameters:
hrtc RTC handle
Tamper Selected tamper pin. This parameter can be a combination of the following values:
  • RTC_TAMPER_1
  • RTC_TAMPER_2
Return values:
HAL status

Definition at line 1478 of file stm32g0xx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, and __RTC_HandleTypeDef::TampOffset.

void HAL_RTCEx_InternalTamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 3 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1827 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_InternalTamper4EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 4 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1843 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_InternalTamper5EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 5 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1859 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_InternalTamper6EventCallback ( RTC_HandleTypeDef * hrtc )

Internal Tamper 6 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1875 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | IntTamper,
 |  | uint32_t | Timeout
 | ) |  |

Internal Tamper event polling.

Parameters:
hrtc | RTC handle
IntTamper | selected tamper. This parameter can be any combination of existing internal tampers.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1640 of file stm32g0xx_hal_rtc_ex.c.

References assert_param, HAL_GetTick(), __RTC_HandleTypeDef::Instance, IS_RTC_INTERNAL_TAMPER, and __RTC_HandleTypeDef::TampOffset.

HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper,
 |  | uint32_t | Timeout
 | ) |  |

Tamper event polling.

Parameters:
hrtc | RTC handle
Tamper Selected tamper pin. This parameter can be a combination of the following values:
  • RTC_TAMPER_1
  • RTC_TAMPER_2
  • RTC_TAMPER_3 (*)
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1509 of file stm32g0xx_hal_rtc_ex.c.

References assert_param, HAL_GetTick(), __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, and __RTC_HandleTypeDef::TampOffset.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_InternalTamperTypeDef * | sIntTamper
 | ) |  |

Set Internal Tamper in interrupt mode.

Parameters:
hrtc | RTC handle
sIntTamper | Pointer to Internal Tamper Structure.
Return values:
HAL status

Definition at line 1543 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, __RTC_HandleTypeDef::Instance, RTC_InternalTamperTypeDef::IntTamper, IS_RTC_INTERNAL_TAMPER, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, __RTC_HandleTypeDef::TampOffset, and RTC_InternalTamperTypeDef::TimeStampOnTamperDetection.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_InternalTamperTypeDef * | sIntTamper
 | ) |  |

Set Internal Tamper.

Parameters:
hrtc | RTC handle
sIntTamper | Pointer to Internal Tamper Structure.
Return values:
HAL status

Definition at line 1576 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_EXTI_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, __RTC_HandleTypeDef::Instance, RTC_InternalTamperTypeDef::IntTamper, IS_RTC_INTERNAL_TAMPER, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, __RTC_HandleTypeDef::TampOffset, and RTC_InternalTamperTypeDef::TimeStampOnTamperDetection.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper.

Parameters:
hrtc | RTC handle
sTamper | Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 1342 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TamperTypeDef::Filter, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, __RTC_HandleTypeDef::TampOffset, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper in IT mode.

Parameters:
hrtc | RTC handle
sTamper | Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 1405 of file stm32g0xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_EXTI_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TamperTypeDef::Filter, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, __RTC_HandleTypeDef::TampOffset, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1779 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1795 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1811 of file stm32g0xx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_TamperIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Tamper interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1673 of file stm32g0xx_hal_rtc_ex.c.

References HAL_RTCEx_InternalTamper3EventCallback(), HAL_RTCEx_InternalTamper4EventCallback(), HAL_RTCEx_InternalTamper5EventCallback(), HAL_RTCEx_InternalTamper6EventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::InternalTamper3EventCallback, __RTC_HandleTypeDef::InternalTamper4EventCallback, __RTC_HandleTypeDef::InternalTamper5EventCallback, __RTC_HandleTypeDef::InternalTamper6EventCallback, RTC_INT_TAMPER_3, RTC_INT_TAMPER_4, RTC_INT_TAMPER_5, RTC_INT_TAMPER_6, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, and __RTC_HandleTypeDef::TampOffset.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended RTC Backup register functions

Functions
Extended RTC Backup register functions
RTCEx Exported Functions

Extended RTC Backup register functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.

Detailed Description

Extended RTC Backup register functions.

  ===============================================================================
             ##### Extended RTC Backup register functions #####
  ===============================================================================
  [..]
   (+) Before calling any tamper or internal tamper function, you have to call first
       HAL_RTC_Init() function.
   (+) In that ine you can select to output tamper event on RTC pin.
  [..]
   This subsection provides functions allowing to
   (+) Write a data in a specified RTC Backup data register
   (+) Read a data in a specified RTC Backup data register

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 specify the register.
Return values:
Read value

Definition at line 1946 of file stm32g0xx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, IS_RTC_BKP, and __RTC_HandleTypeDef::TampOffset.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Write a data in a specified RTC Backup data register.

Parameters:
hrtc | RTC handle
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 specify the register.
Data | Data to be written in the specified Backup data register.
Return values:
None

Definition at line 1921 of file stm32g0xx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, IS_RTC_BKP, and __RTC_HandleTypeDef::TampOffset.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Private Constants

Defines
RTCEx Private Constants
RTCEx

Defines

#define | RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM19
#define | RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM21

Define Documentation

#define RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM21

External interrupt line 19 Connected to the RTC tamper events

Definition at line 1018 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19

External interrupt line 19 Connected to the RTC Time Stamp events

Definition at line 1016 of file stm32g0xx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM19

External interrupt line 19 Connected to the RTC Wakeup event

Definition at line 1017 of file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Smooth calib Minus pulses Definitions

Defines
RTCEx Smooth calib Minus pulses Definitions
Private macros to check input parameters

Defines

#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)

Define Documentation

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= RTC_CALR_CALM)

Definition at line 1111 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Subtract Fraction Of Second Value

Defines
RTCEx Subtract Fraction Of Second Value
Private macros to check input parameters

Defines

#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)

Define Documentation

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= RTC_SHIFTR_SUBFS)

Definition at line 1125 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Private macros to check input parameters

Modules | Defines
Private macros to check input parameters
RTCEx Private Macros

Modules

RTCEx Smooth calib Minus pulses Definitions
RTCEx Subtract Fraction Of Second Value

Defines

#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_TAMPER(__TAMPER__)
#define | IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_TAMPER_ERASE_MODE(__MODE__)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)
#define | IS_RTC_TAMPER_FILTER(__FILTER__)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)
#define | IS_RTC_TAMPER_PULLUP_STATE(__STATE__)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Define Documentation

#define IS_RTC_BKP ( __BKP__ ) ((__BKP__) < RTC_BKP_NUMBER)

Definition at line 1105 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

Definition at line 1129 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_INTERNAL_TAMPER ( __INT_TAMPER__ )
Value:
((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
                                                   (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))

Definition at line 1066 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_SetInternalTamper(), and HAL_RTCEx_SetInternalTamper_IT().

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_SHIFTADD1S_RESET) || \
                                 ((SEL) == RTC_SHIFTADD1S_SET))

Definition at line 1117 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 1056 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 1060 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( __TAMPER__ )
Value:
((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
                                                   (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))

Definition at line 1063 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_ERASE_MODE ( __MODE__ )
Value:
(((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
                                                   ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

Definition at line 1074 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( __FILTER__ )
Value:
(((__FILTER__) == RTC_TAMPERFILTER_DISABLE)  || \
                                                   ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
                                                   ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
                                                   ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 1080 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_MASKFLAG_STATE ( __STATE__ )
Value:
(((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
                                                   ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))

Definition at line 1077 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( __DURATION__ )
Value:
(((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                           ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                           ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                           ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 1094 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( __STATE__ )
Value:
(((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
                                                   ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 1099 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( __FREQ__ )
Value:
(((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                                   ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 1085 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT ( MODE )
Value:
(((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
                                                      ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))

Definition at line 1043 of file stm32g0xx_hal_rtc_ex.h.

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 1102 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( __TRIGGER__ )
Value:
(((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)  || \
                                                   ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
                                                   ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)    || \
                                                   ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 1069 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( PIN ) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))

Definition at line 1036 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 1040 of file stm32g0xx_hal_rtc_ex.h.

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 1047 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= RTC_WUTR_WUT)

Definition at line 1054 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 1032 of file stm32g0xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Define Documentation

#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U

SMARTCARD TX or RX enable acknowledge time-out value

Definition at line 202 of file stm32g0xx_hal_smartcard.c.

Referenced by SMARTCARD_CheckIdleState().

#define USART_BRR_MAX 0x0000FFFFU

USART BRR maximum authorized value

Definition at line 219 of file stm32g0xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_BRR_MIN 0x10U

USART BRR minimum authorized value

Definition at line 217 of file stm32g0xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
                                      USART_CR1_RE | USART_CR1_OVER8| \
                                      USART_CR1_FIFOEN))

USART CR1 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 204 of file stm32g0xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR2_CLK_FIELDS
Value:
((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
                                          USART_CR2_CPHA | USART_CR2_LBCL))

SMARTCARD clock-related USART CR2 fields of parameters

Definition at line 208 of file stm32g0xx_hal_smartcard.c.

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
                                      USART_CR2_STOP))

USART CR2 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 211 of file stm32g0xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART CR3 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 214 of file stm32g0xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  associated to the SmartCard.
  (+) These parameters can be configured:
      (++) Baud Rate
      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
      (++) Receiver/transmitter modes
      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
      (++) Prescaler value
      (++) Guard bit time
      (++) NACK enabling or disabling on transmission error

  (+) The following advanced features can be configured as well:
      (++) TX and/or RX pin level inversion
      (++) data logical level inversion
      (++) RX and TX pins swap
      (++) RX overrun detection disabling
      (++) DMA disabling on RX error
      (++) MSB first on communication line
      (++) Time out enabling (and if activated, timeout value)
      (++) Block length
      (++) Auto-retry counter
  [..]
  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
  (details for the procedures are available in reference manual).

The USART frame format is given in the following table:

Table 1. USART frame format. +---------------------------------------------------------------+ | M1M0 bits | PCE bit | USART frame | |-----------------------|---------------------------------------| | 01 | 1 | | SB | 8 bit data | PB | STB | | +---------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 391 of file stm32g0xx_hal_smartcard.c.

References assert_param, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::MspDeInitCallback, and __SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 318 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::Lock, __SMARTCARD_HandleTypeDef::MspInitCallback, SMARTCARD_ADVFEATURE_NO_INIT, SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_SetConfig(), and SMARTCARD_TRANSMISSION_COMPLETION_SETTING.

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 457 of file stm32g0xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit(), and HAL_SMARTCARD_UnRegisterCallback().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 441 of file stm32g0xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init(), and HAL_SMARTCARD_UnRegisterCallback().

HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | HAL_SMARTCARD_CallbackIDTypeDef | CallbackID,
 |  | pSMARTCARD_CallbackTypeDef | pCallback
 | ) |  |

Register a User SMARTCARD Callback To be used instead of the weak predefined callback.

Parameters:
hsmartcard | smartcard handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
  • HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 487 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_SMARTCARD_ERROR_CB_ID, HAL_SMARTCARD_ERROR_INVALID_CALLBACK, HAL_SMARTCARD_MSPDEINIT_CB_ID, HAL_SMARTCARD_MSPINIT_CB_ID, HAL_SMARTCARD_RX_COMPLETE_CB_ID, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, HAL_SMARTCARD_TX_COMPLETE_CB_ID, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID, __SMARTCARD_HandleTypeDef::MspDeInitCallback, __SMARTCARD_HandleTypeDef::MspInitCallback, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | HAL_SMARTCARD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.

Parameters:
hsmartcard smartcard handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
  • HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 611 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ERROR_CB_ID, HAL_SMARTCARD_ERROR_INVALID_CALLBACK, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_MSPDEINIT_CB_ID, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_MSPINIT_CB_ID, HAL_SMARTCARD_RX_COMPLETE_CB_ID, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, HAL_SMARTCARD_TX_COMPLETE_CB_ID, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID, HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::MspDeInitCallback, __SMARTCARD_HandleTypeDef::MspInitCallback, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

  [..]
    Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard. The USART should be configured as:
    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

  [..]
    (#) There are two modes of transfer:
        (##) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (##) Non-Blocking mode: The communication is performed using Interrupts
             or DMA, the relevant API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
        (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
             error is detected.

    (#) Blocking mode APIs are :
        (##) HAL_SMARTCARD_Transmit()
        (##) HAL_SMARTCARD_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (##) HAL_SMARTCARD_Transmit_IT()
        (##) HAL_SMARTCARD_Receive_IT()
        (##) HAL_SMARTCARD_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (##) HAL_SMARTCARD_Transmit_DMA()
        (##) HAL_SMARTCARD_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (##) HAL_SMARTCARD_TxCpltCallback()
        (##) HAL_SMARTCARD_RxCpltCallback()
        (##) HAL_SMARTCARD_ErrorCallback()

  [..]
    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (##) HAL_SMARTCARD_Abort()
        (##) HAL_SMARTCARD_AbortTransmit()
        (##) HAL_SMARTCARD_AbortReceive()
        (##) HAL_SMARTCARD_Abort_IT()
        (##) HAL_SMARTCARD_AbortTransmit_IT()
        (##) HAL_SMARTCARD_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
        a set of Abort Complete Callbacks are provided:
        (##) HAL_SMARTCARD_AbortCpltCallback()
        (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
        (##) HAL_SMARTCARD_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error,
           Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer,
           Error code is set to allow user to identify error type,
           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
           If user wants to abort it, Abort services should be called by user.
       (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
           mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type,
           and HAL_SMARTCARD_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_Abort ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1322 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1544 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2208 of file stm32g0xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1476 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1781 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortReceiveCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Receive Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2240 of file stm32g0xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1413 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1686 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, SMARTCARD_DMATxOnlyAbortCallback(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortTransmitCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2224 of file stm32g0xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD error callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2192 of file stm32g0xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsmartcard )

Handle SMARTCARD interrupt requests.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1875 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, __HAL_SMARTCARD_GET_IT, __HAL_SMARTCARD_GET_IT_SOURCE, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ERROR_RTO, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMAAbortOnError(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback, __SMARTCARD_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 918 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Note:
The SMARTCARD-associated USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 1242 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When FIFO mode is disabled, USART interrupt is generated whenever USART_RDR register can be read, i.e one interrupt per data to receive.
When FIFO mode is enabled, USART interrupt is generated whenever RXFIFO threshold reached. In that case the interrupt rate depends on RXFIFO threshold configuration.
This function sets the hsmartcard->RxIsr function pointer according to the FIFO mode (data reception processing depends on FIFO mode).
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 1080 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::FifoMode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FIFOMODE_ENABLE, SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Rx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2176 of file stm32g0xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When FIFO mode is enabled, writing a data in the TDR register adds one data to the TXFIFO. Write operations to the TDR register are performed when TXFNF flag is set. From hardware perspective, TXFNF flag and TXE are mapped on the same bit-field.
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 812 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_FLUSH_DRREGISTER, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, SMARTCARD_FLAG_TXE, SMARTCARD_MODE_TX, SMARTCARD_MODE_TX_RX, SMARTCARD_NACK_ENABLE, SMARTCARD_TRANSMISSION_COMPLETION_FLAG, SMARTCARD_WaitOnFlagUntilTimeout(), __SMARTCARD_HandleTypeDef::TxXferCount, and __SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 1144 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_FLUSH_DRREGISTER, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_MODE_TX, SMARTCARD_NACK_ENABLE, __SMARTCARD_HandleTypeDef::TxXferCount, __SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When FIFO mode is disabled, USART interrupt is generated whenever USART_TDR register is empty, i.e one interrupt per data to transmit.
When FIFO mode is enabled, USART interrupt is generated whenever TXFIFO threshold reached. In that case the interrupt rate depends on TXFIFO threshold configuration.
This function sets the hsmartcard->TxIsr function pointer according to the FIFO mode (data transmission processing depends on FIFO mode).
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 986 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_FLUSH_DRREGISTER, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_FIFOMODE_ENABLE, SMARTCARD_MODE_TX, SMARTCARD_NACK_ENABLE, SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Tx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2160 of file stm32g0xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_InitCallbacksToDefault().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of SmartCard
    handle and also return Peripheral Errors occurred during communication process
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
         of the SMARTCARD peripheral.
     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( const SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle error code.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle Error Code

Definition at line 2296 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( const SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle state.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle state

Definition at line 2279 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::gState, and __SMARTCARD_HandleTypeDef::RxState.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Private Functions

Functions
SMARTCARD Private Functions
SMARTCARD

Functions

void | SMARTCARD_InitCallbacksToDefault (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | SMARTCARD_TxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_TxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static void | SMARTCARD_RxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
static void | SMARTCARD_RxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.

Function Documentation

static void SMARTCARD_AdvFeatureConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral advanced features.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2472 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_AdvFeatureInitTypeDef::DataInvert, SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_ADVFEATURE_DATAINV, IS_SMARTCARD_ADVFEATURE_DMAONRXERROR, IS_SMARTCARD_ADVFEATURE_INIT, IS_SMARTCARD_ADVFEATURE_MSBFIRST, IS_SMARTCARD_ADVFEATURE_RXINV, IS_SMARTCARD_ADVFEATURE_SWAP, IS_SMARTCARD_ADVFEATURE_TXINV, IS_SMARTCARD_OVERRUN, SMARTCARD_AdvFeatureInitTypeDef::MSBFirst, SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable, SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert, SMARTCARD_ADVFEATURE_DATAINVERT_INIT, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT, SMARTCARD_ADVFEATURE_MSBFIRST_INIT, SMARTCARD_ADVFEATURE_RXINVERT_INIT, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT, SMARTCARD_ADVFEATURE_SWAP_INIT, SMARTCARD_ADVFEATURE_TXINVERT_INIT, SMARTCARD_AdvFeatureInitTypeDef::Swap, and SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_CheckIdleState ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Check the SMARTCARD Idle State.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2534 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_TEACK_REACK_TIMEOUT, and SMARTCARD_WaitOnFlagUntilTimeout().

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2747 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCallback, HAL_SMARTCARD_ErrorCallback(), __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxXferCount, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2707 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_EndRxTransfer(), SMARTCARD_EndTxTransfer(), and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2676 of file stm32g0xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxState, and __SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2819 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2897 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, and SMARTCARD_CLEAR_RTOF.

Referenced by HAL_SMARTCARD_AbortReceive_IT().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2657 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2770 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2868 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, SMARTCARD_CLEAR_FEF, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_AbortTransmit_IT().

static void SMARTCARD_EndRxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2640 of file stm32g0xx_hal_smartcard.c.

References HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and __SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static void SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2997 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __HAL_SMARTCARD_FLUSH_DRREGISTER, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_MODE_TX, SMARTCARD_MODE_TX_RX, SMARTCARD_NACK_ENABLE, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxISR.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_EndTxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2623 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

void SMARTCARD_InitCallbacksToDefault ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the callbacks to their default values.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
none

Definition at line 2319 of file stm32g0xx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_RxISR ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT() and when the FIFO mode is disabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 3050 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_RXDATA_FLUSH_REQUEST.

Referenced by HAL_SMARTCARD_Receive_IT(), and SMARTCARD_RxISR_FIFOEN().

static void SMARTCARD_RxISR_FIFOEN ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT() and when the FIFO mode is enabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 3103 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_RXDATA_FLUSH_REQUEST, and SMARTCARD_RxISR().

Referenced by HAL_SMARTCARD_Receive_IT().

static HAL_StatusTypeDef SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2344 of file stm32g0xx_hal_smartcard.c.

References assert_param, SMARTCARD_InitTypeDef::AutoRetryCount, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::BlockLength, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, SMARTCARD_InitTypeDef::ClockPrescaler, SMARTCARD_InitTypeDef::GuardTime, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_AUTORETRY_COUNT, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_CLOCKPRESCALER, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK, IS_SMARTCARD_ONE_BIT_SAMPLE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_TIMEOUT, IS_SMARTCARD_TIMEOUT_VALUE, IS_SMARTCARD_WORD_LENGTH, LSE_VALUE, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, SMARTCARD_InitTypeDef::OneBitSampling, SMARTCARD_InitTypeDef::Parity, SMARTCARD_InitTypeDef::Prescaler, __SMARTCARD_HandleTypeDef::RxISR, SMARTCARD_CLOCKSOURCE_HSI, SMARTCARD_CLOCKSOURCE_LSE, SMARTCARD_CLOCKSOURCE_PCLK1, SMARTCARD_CLOCKSOURCE_SYSCLK, SMARTCARD_GETCLOCKSOURCE, SMARTCARD_TIMEOUT_ENABLE, SMARTCARD_InitTypeDef::StopBits, SMARTCARD_InitTypeDef::TimeOutEnable, SMARTCARD_InitTypeDef::TimeOutValue, __SMARTCARD_HandleTypeDef::TxISR, USART_BRR_MAX, USART_BRR_MIN, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_TxISR ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() and when the FIFO mode is disabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2929 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_IT().

static void SMARTCARD_TxISR_FIFOEN ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() and when the FIFO mode is enabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2960 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_IT().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMARTCARD Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Flag | Specifies the SMARTCARD flag to check.
Status | The actual Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 2588 of file stm32g0xx_hal_smartcard.c.

References __HAL_SMARTCARD_GET_FLAG, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and __SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), and SMARTCARD_CheckIdleState().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Exported Types

Data Structures | Typedefs | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initialization structure definition. More...
struct | __SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_SMARTCARD_StateTypeDef
HAL SMARTCARD State definition.
typedef struct
__SMARTCARD_HandleTypeDef 		SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition.
typedef void(* | pSMARTCARD_CallbackTypeDef )(SMARTCARD_HandleTypeDef *hsmartcard)
HAL SMARTCARD Callback pointer definition.

Enumerations

enum HAL_SMARTCARD_CallbackIDTypeDef {
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, HAL_SMARTCARD_ERROR_CB_ID = 0x02U, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U,
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U,
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U
}
HAL SMARTCARD Callback ID enumeration definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, SMARTCARD_CLOCKSOURCE_HSI = 0x02U, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, SMARTCARD_CLOCKSOURCE_LSE = 0x08U,
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U
}
SMARTCARD clock sources. More...

Typedef Documentation

typedef uint32_t HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see SMARTCARD State Code Definition).
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 191 of file stm32g0xx_hal_smartcard.h.

typedef void(* pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard)

HAL SMARTCARD Callback pointer definition.

pointer to an SMARTCARD callback function

Definition at line 292 of file stm32g0xx_hal_smartcard.h.

typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_HandleTypeDef

SMARTCARD handle Structure definition.

Enumeration Type Documentation

enum HAL_SMARTCARD_CallbackIDTypeDef

HAL SMARTCARD Callback ID enumeration definition.

Enumerator:
HAL_SMARTCARD_TX_COMPLETE_CB_ID

SMARTCARD Tx Complete Callback ID

HAL_SMARTCARD_RX_COMPLETE_CB_ID

SMARTCARD Rx Complete Callback ID

HAL_SMARTCARD_ERROR_CB_ID

SMARTCARD Error Callback ID

HAL_SMARTCARD_ABORT_COMPLETE_CB_ID

SMARTCARD Abort Complete Callback ID

HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID

SMARTCARD Abort Transmit Complete Callback ID

HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID

SMARTCARD Abort Receive Complete Callback ID

HAL_SMARTCARD_RX_FIFO_FULL_CB_ID

SMARTCARD Rx Fifo Full Callback ID

HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID

SMARTCARD Tx Fifo Empty Callback ID

HAL_SMARTCARD_MSPINIT_CB_ID

SMARTCARD MspInit callback ID

HAL_SMARTCARD_MSPDEINIT_CB_ID

SMARTCARD MspDeInit callback ID

Definition at line 273 of file stm32g0xx_hal_smartcard.h.

enum SMARTCARD_ClockSourceTypeDef

SMARTCARD clock sources.

Enumerator:
SMARTCARD_CLOCKSOURCE_PCLK1

PCLK1 clock source

SMARTCARD_CLOCKSOURCE_HSI

HSI clock source

SMARTCARD_CLOCKSOURCE_SYSCLK

SYSCLK clock source

SMARTCARD_CLOCKSOURCE_LSE

LSE clock source

SMARTCARD_CLOCKSOURCE_UNDEFINED

undefined clock source

Definition at line 299 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32g0xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint16_t | Parity
uint16_t | Mode
uint16_t | CLKPolarity
uint16_t | CLKPhase
uint16_t | CLKLastBit
uint16_t | OneBitSampling
uint8_t | Prescaler
uint8_t | GuardTime
uint16_t | NACKEnable
uint32_t | TimeOutEnable
uint32_t | TimeOutValue
uint8_t | BlockLength
uint8_t | AutoRetryCount
uint32_t | ClockPrescaler

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 46 of file stm32g0xx_hal_smartcard.h.

Field Documentation

uint8_t SMARTCARD_InitTypeDef::AutoRetryCount

Specifies the SmartCard auto-retry count (number of retries in receive and transmit mode). When set to 0, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error)

Definition at line 104 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BaudRate

Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) where usart_ker_ckpres is the USART input clock divided by a prescaler

Definition at line 48 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::BlockLength

Specifies the SmartCard Block Length in T=1 Reception mode. This parameter can be any value from 0x0 to 0xFF

Definition at line 101 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 75 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 72 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 69 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of SMARTCARD Clock Prescaler.

Definition at line 109 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time applied after stop bits.

Definition at line 88 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Transfer Mode

Definition at line 66 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::NACKEnable

Specifies whether the SmartCard NACK transmission is enabled in case of parity error. This parameter can be a value of SMARTCARD NACK Enable

Definition at line 90 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of SMARTCARD One Bit Sampling Method.

Definition at line 79 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
The parity is enabled by default (PCE is forced to 1). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit.

Definition at line 60 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler. This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied by 2 to give the division factor of the source clock frequency

Definition at line 84 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits. This parameter can be a value of SMARTCARD Number of Stop Bits.

Definition at line 57 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutEnable

Specifies whether the receiver timeout is enabled. This parameter can be a value of SMARTCARD Timeout Enable

Definition at line 94 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutValue

Specifies the receiver time out value in number of baud blocks: it is used to implement the Character Wait Time (CWT) and Block Wait Time (BWT). It is coded over 24 bits.

Definition at line 97 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter SMARTCARD Word Length can only be set to 9 (8 data + 1 parity bits).

Definition at line 53 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_smartcard.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_AdvFeatureInitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD advanced features initialization structure definition. More...

#include <stm32g0xx_hal_smartcard.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | MSBFirst
uint16_t | TxCompletionIndication

Detailed Description

SMARTCARD advanced features initialization structure definition.

Definition at line 117 of file stm32g0xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced SMARTCARD features is initialized. Several advanced features may be initialized at the same time. This parameter can be a value of SMARTCARD advanced feature initialization type

Definition at line 119 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of SMARTCARD advanced feature Binary Data inversion

Definition at line 129 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of SMARTCARD advanced feature DMA Disable on Rx Error

Definition at line 139 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of SMARTCARD advanced feature MSB first

Definition at line 142 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of SMARTCARD advanced feature Overrun Disable

Definition at line 136 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature RX pin active level inversion

Definition at line 126 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of SMARTCARD advanced feature RX TX pins swap

Definition at line 133 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint16_t SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication

Specifies which transmission completion indication is used: before (when relevant flag is available) or once guard time period has elapsed. This parameter can be a value of SMARTCARD Transmission Completion Indication.

Definition at line 145 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature TX pin active level inversion

Definition at line 123 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_smartcard.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32g0xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit
const uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
uint32_t | FifoMode
void(* | RxISR )(struct __SMARTCARD_HandleTypeDef *huart)
void(* | TxISR )(struct __SMARTCARD_HandleTypeDef *huart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | RxCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | ErrorCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortTransmitCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortReceiveCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | RxFifoFullCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | TxFifoEmptyCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | MspInitCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | MspDeInitCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 196 of file stm32g0xx_hal_smartcard.h.

Field Documentation

void(* __SMARTCARD_HandleTypeDef::AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Complete Callback

Definition at line 252 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Receive Complete Callback

Definition at line 256 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Transmit Complete Callback

Definition at line 254 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

SMARTCARD_AdvFeatureInitTypeDef __SMARTCARD_HandleTypeDef::AdvancedInit

SmartCard advanced features initialization parameters

Definition at line 202 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Error Callback

Definition at line 250 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), and SMARTCARD_InitCallbacksToDefault().

__IO uint32_t __SMARTCARD_HandleTypeDef::ErrorCode

SmartCard Error code

Definition at line 243 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

uint32_t __SMARTCARD_HandleTypeDef::FifoMode

Specifies if the FIFO mode will be used. This parameter can be a value of SMARTCARD FIFO mode.

Definition at line 220 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), and SMARTCARDEx_SetNbDataToProcess().

__IO HAL_SMARTCARD_StateTypeDef __SMARTCARD_HandleTypeDef::gState

SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 234 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __SMARTCARD_HandleTypeDef::hdmarx

SmartCard Rx DMA Handle parameters

Definition at line 230 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

DMA_HandleTypeDef* __SMARTCARD_HandleTypeDef::hdmatx

SmartCard Tx DMA Handle parameters

Definition at line 228 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

SMARTCARD_InitTypeDef __SMARTCARD_HandleTypeDef::Init

SmartCard communication parameters

Definition at line 200 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

USART_TypeDef* __SMARTCARD_HandleTypeDef::Instance

USART registers base address

Definition at line 198 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_BlockLength_Config(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_SetConfig(), SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), SMARTCARD_WaitOnFlagUntilTimeout(), and SMARTCARDEx_SetNbDataToProcess().

HAL_LockTypeDef __SMARTCARD_HandleTypeDef::Lock

Locking object

Definition at line 232 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

void(* __SMARTCARD_HandleTypeDef::MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Msp DeInit callback

Definition at line 264 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

void(* __SMARTCARD_HandleTypeDef::MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Msp Init callback

Definition at line 262 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

uint16_t __SMARTCARD_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 216 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_SetConfig(), and SMARTCARDEx_SetNbDataToProcess().

uint16_t __SMARTCARD_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 218 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig(), SMARTCARD_TxISR_FIFOEN(), and SMARTCARDEx_SetNbDataToProcess().

uint8_t* __SMARTCARD_HandleTypeDef::pRxBuffPtr

Pointer to SmartCard Rx transfer Buffer

Definition at line 210 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

const uint8_t* __SMARTCARD_HandleTypeDef::pTxBuffPtr

Pointer to SmartCard Tx transfer Buffer

Definition at line 204 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Rx Complete Callback

Definition at line 248 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Rx Fifo Full Callback

Definition at line 258 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::RxISR)(struct __SMARTCARD_HandleTypeDef *huart)

Function pointer on Rx IRQ handler

Definition at line 224 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_SetConfig().

__IO HAL_SMARTCARD_StateTypeDef __SMARTCARD_HandleTypeDef::RxState

SmartCard state information related to Rx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 239 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

__IO uint16_t __SMARTCARD_HandleTypeDef::RxXferCount

SmartCard Rx Transfer Counter

Definition at line 214 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

uint16_t __SMARTCARD_HandleTypeDef::RxXferSize

SmartCard Rx Transfer size

Definition at line 212 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

void(* __SMARTCARD_HandleTypeDef::TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Tx Complete Callback

Definition at line 246 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Tx Fifo Empty Callback

Definition at line 260 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::TxISR)(struct __SMARTCARD_HandleTypeDef *huart)

Function pointer on Tx IRQ handler

Definition at line 226 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

__IO uint16_t __SMARTCARD_HandleTypeDef::TxXferCount

SmartCard Tx Transfer Counter

Definition at line 208 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

uint16_t __SMARTCARD_HandleTypeDef::TxXferSize

SmartCard Tx Transfer size

Definition at line 206 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_smartcard.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD State Code Definition

Defines
SMARTCARD State Code Definition
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_STATE_RESET 0x00000000U
#define | HAL_SMARTCARD_STATE_READY 0x00000020U
#define | HAL_SMARTCARD_STATE_BUSY 0x00000024U
#define | HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U
#define | HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U
#define | HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U
#define | HAL_SMARTCARD_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_SMARTCARD_STATE_BUSY 0x00000024U

an internal process is ongoing Value is allowed for gState only

Definition at line 325 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 329 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 327 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 331 of file stm32g0xx_hal_smartcard.h.

#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 338 of file stm32g0xx_hal_smartcard.h.

#define HAL_SMARTCARD_STATE_READY 0x00000020U

Peripheral Initialized and ready for use. Value is allowed for gState and RxState

Definition at line 322 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define HAL_SMARTCARD_STATE_RESET 0x00000000U

Peripheral is not initialized. Value is allowed for gState and RxState

Definition at line 320 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 336 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Error Code Definition

Defines
SMARTCARD Error Code Definition
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_ERROR_NONE (0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE (0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE (0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE (0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE (0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA (0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO (0x00000020U)
#define | HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)

Define Documentation

#define HAL_SMARTCARD_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 352 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), and SMARTCARD_DMAError().

#define HAL_SMARTCARD_ERROR_FE (0x00000004U)

frame error

Definition at line 350 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)

Invalid Callback error

Definition at line 355 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

#define HAL_SMARTCARD_ERROR_NE (0x00000002U)

Noise error

Definition at line 349 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NONE (0x00000000U)

No error

Definition at line 347 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define HAL_SMARTCARD_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 351 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_PE (0x00000001U)

Parity error

Definition at line 348 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_RTO (0x00000020U)

Receiver TimeOut error

Definition at line 353 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported Constants

Defines

#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0

SMARTCARD frame length

Definition at line 364 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0
#define | SMARTCARD_STOPBITS_1_5 USART_CR2_STOP

Define Documentation

#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0

SMARTCARD frame with 0.5 stop bit

Definition at line 372 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP

SMARTCARD frame with 1.5 stop bits

Definition at line 373 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PARITY_EVEN USART_CR1_PCE
#define | SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define SMARTCARD_PARITY_EVEN USART_CR1_PCE

SMARTCARD frame even parity

Definition at line 381 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

SMARTCARD frame odd parity

Definition at line 382 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Transfer Mode

Defines
SMARTCARD Transfer Mode
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_MODE_RX USART_CR1_RE
#define | SMARTCARD_MODE_TX USART_CR1_TE
#define | SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define SMARTCARD_MODE_RX USART_CR1_RE

SMARTCARD RX mode

Definition at line 390 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX USART_CR1_TE

SMARTCARD TX mode

Definition at line 391 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_EndTransmit_IT().

#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

SMARTCARD RX and TX mode

Definition at line 392 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), and SMARTCARD_EndTransmit_IT().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL

SMARTCARD frame high polarity

Definition at line 401 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW 0x00000000U

SMARTCARD frame low polarity

Definition at line 400 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define SMARTCARD_PHASE_1EDGE 0x00000000U

SMARTCARD frame phase on first clock transition

Definition at line 409 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA

SMARTCARD frame phase on second clock transition

Definition at line 410 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE 0x00000000U

SMARTCARD frame last data bit clock pulse not output to SCLK pin

Definition at line 418 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL

SMARTCARD frame last data bit clock pulse output to SCLK pin

Definition at line 419 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD One Bit Sampling Method

Defines
SMARTCARD One Bit Sampling Method
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U

SMARTCARD frame one-bit sample disabled

Definition at line 427 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

SMARTCARD frame one-bit sample enabled

Definition at line 428 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD NACK Enable

Defines
SMARTCARD NACK Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_NACK_ENABLE USART_CR3_NACK

Define Documentation

#define SMARTCARD_NACK_DISABLE 0x00000000U

SMARTCARD NACK transmission disabled

Definition at line 436 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE USART_CR3_NACK

SMARTCARD NACK transmission enabled

Definition at line 437 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_EndTransmit_IT().

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STM32G0C1xx HAL User Manual: SMARTCARD Timeout Enable

Defines
SMARTCARD Timeout Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_TIMEOUT_DISABLE 0x00000000U
#define | SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN

Define Documentation

#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U

SMARTCARD receiver timeout disabled

Definition at line 445 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN

SMARTCARD receiver timeout enabled

Definition at line 446 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

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STM32G0C1xx HAL User Manual: SMARTCARD Clock Prescaler

Defines
SMARTCARD Clock Prescaler
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PRESCALER_DIV1 0x00000000U
#define | SMARTCARD_PRESCALER_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_DIV16 0x00000007U
#define | SMARTCARD_PRESCALER_DIV32 0x00000008U
#define | SMARTCARD_PRESCALER_DIV64 0x00000009U
#define | SMARTCARD_PRESCALER_DIV128 0x0000000AU
#define | SMARTCARD_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define SMARTCARD_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 454 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 459 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 460 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 464 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 461 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 455 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 465 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 462 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 456 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 457 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 463 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 458 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD advanced feature TX pin active level inversion

Defines
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

Define Documentation

#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U

TX pin active level inversion disable

Definition at line 473 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

TX pin active level inversion enable

Definition at line 474 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD advanced feature RX pin active level inversion

Defines
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

Define Documentation

#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U

RX pin active level inversion disable

Definition at line 482 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

RX pin active level inversion enable

Definition at line 483 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD advanced feature Binary Data inversion

Defines
SMARTCARD advanced feature Binary Data inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U

Binary data inversion disable

Definition at line 491 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Binary data inversion enable

Definition at line 492 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD advanced feature RX TX pins swap

Defines
SMARTCARD advanced feature RX TX pins swap
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

Define Documentation

#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U

TX/RX pins swap disable

Definition at line 500 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

TX/RX pins swap enable

Definition at line 501 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD advanced feature Overrun Disable

Defines
SMARTCARD advanced feature Overrun Disable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

Define Documentation

#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

RX overrun disable

Definition at line 510 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U

RX overrun enable

Definition at line 509 of file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD advanced feature DMA Disable on Rx Error

Defines
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

Define Documentation

#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

DMA disable on Reception Error

Definition at line 519 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U

DMA enable on Reception Error

Definition at line 518 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD advanced feature MSB first

Defines
SMARTCARD advanced feature MSB first
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Define Documentation

#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U

Most significant bit sent/received first disable

Definition at line 527 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Most significant bit sent/received first enable

Definition at line 528 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD Request Parameters

Defines
SMARTCARD Request Parameters
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive data flush request

Definition at line 536 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush request

Definition at line 537 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD interruptions flags mask

Defines
SMARTCARD interruptions flags mask
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_IT_MASK 0x001FU
#define | SMARTCARD_CR_MASK 0x00E0U
#define | SMARTCARD_CR_POS 5U
#define | SMARTCARD_ISR_MASK 0x1F00U
#define | SMARTCARD_ISR_POS 8U

Define Documentation

#define SMARTCARD_CR_MASK 0x00E0U

SMARTCARD control register mask

Definition at line 546 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_CR_POS 5U

SMARTCARD control register position

Definition at line 547 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ISR_MASK 0x1F00U

SMARTCARD ISR register mask

Definition at line 548 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_ISR_POS 8U

SMARTCARD ISR register position

Definition at line 549 of file stm32g0xx_hal_smartcard.h.

#define SMARTCARD_IT_MASK 0x001FU

SMARTCARD interruptions flags mask

Definition at line 545 of file stm32g0xx_hal_smartcard.h.

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STM32G0C1xx HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 619 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified SMARTCARD pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
  • SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
Return values:
None

Definition at line 607 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 637 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))

Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
  • SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 810 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 625 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 631 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 613 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 845 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                  SMARTCARD_CR_POS) == 1U)?\
                                                                ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                  SMARTCARD_CR_POS) == 2U)?\
                                                                ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Disable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to disable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
None

Definition at line 722 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_EndTransmit_IT().

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 839 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                  SMARTCARD_CR_POS) == 1U)?\
                                                                ((__HANDLE__)->Instance->CR1 |= (1UL <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                  SMARTCARD_CR_POS) == 2U)?\
                                                                ((__HANDLE__)->Instance->CR2 |= (1UL <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 |= (1UL <<\
                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Enable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
None

Definition at line 689 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_DMATransmitCplt(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                     \
    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
  } while(0U)

Flush the Smartcard Data registers.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 585 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_EndTransmit_IT().

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
  • SMARTCARD_FLAG_REACK Receive enable acknowledge flag
  • SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
  • SMARTCARD_FLAG_BUSY Busy flag
  • SMARTCARD_FLAG_EOBF End of block flag
  • SMARTCARD_FLAG_RTOF Receiver timeout flag
  • SMARTCARD_FLAG_TXE Transmit data register empty flag
  • SMARTCARD_FLAG_TC Transmission complete flag
  • SMARTCARD_FLAG_RXNE Receive data register not empty flag
  • SMARTCARD_FLAG_IDLE Idle line detection flag
  • SMARTCARD_FLAG_ORE Overrun error flag
  • SMARTCARD_FLAG_NE Noise error flag
  • SMARTCARD_FLAG_FE Framing error flag
  • SMARTCARD_FLAG_PE Parity error flag
  • SMARTCARD_FLAG_TXFNF TXFIFO not full flag
  • SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
  • SMARTCARD_FLAG_TXFE TXFIFO Empty flag
  • SMARTCARD_FLAG_RXFF RXFIFO Full flag
  • SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag
  • SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 665 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(\
                                                           (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
                                                               & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
                                                           ? SET : RESET)

Check whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 755 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                       SMARTCARD_CR_POS) == 0x01U)?\
                                                                     (__HANDLE__)->Instance->CR1 : \
                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
                                                                        SMARTCARD_CR_POS) == 0x02U)?\
                                                                      (__HANDLE__)->Instance->CR2 : \
                                                                      (__HANDLE__)->Instance->CR3)) &\
                                                                    (0x01UL << (((uint16_t)(__INTERRUPT__))\
                                                                                & SMARTCARD_IT_MASK)))  != 0U)\
                                                                  ? SET : RESET)

Check whether the specified SmartCard interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 782 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR3\
                                                            &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 832 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 826 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                       \
                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
                                                            (__HANDLE__)->MspInitCallback = NULL;                 \
                                                            (__HANDLE__)->MspDeInitCallback = NULL;               \
                                                          } while(0U)

Reset SMARTCARD handle states.

Parameters:
__HANDLE__ SMARTCARD handle.
Return values:
None

Definition at line 568 of file stm32g0xx_hal_smartcard.h.

#define __HAL_SMARTCARD_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific SMARTCARD request flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
  • SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 820 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__)
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that SMARTCARD clock Prescaler is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Define Documentation

#define IS_SMARTCARD_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

Ensure that SMARTCARD frame data inversion setting is valid.

Parameters:
__DATAINV__ SMARTCARD frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1001 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ SMARTCARD DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1022 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

Ensure that SMARTCARD advanced features initialization is valid.

Parameters:
__INIT__ SMARTCARD advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 974 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that SMARTCARD frame MSB first setting is valid.

Parameters:
__MSBFIRST__ SMARTCARD frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1029 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

Ensure that SMARTCARD frame RX inversion setting is valid.

Parameters:
__RXINV__ SMARTCARD frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 994 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

Ensure that SMARTCARD frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ SMARTCARD frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1008 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

Ensure that SMARTCARD frame TX inversion setting is valid.

Parameters:
__TXINV__ SMARTCARD frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 987 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_AUTORETRY_COUNT ( __COUNT__ ) ((__COUNT__) <= 0x7U)

Check the SMARTCARD autoretry counter value.

Note:
The maximum number of retransmissions is 0x7.
Parameters:
__COUNT__ number of retransmissions.
Return values:
Test result (TRUE or FALSE)

Definition at line 884 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 4000001U)

Check the Baud rate range.

Note:
The maximum Baud Rate is derived from the maximum clock on G0 (64 MHz) divided by the oversampling used on the SMARTCARD (i.e. 16).
Parameters:
__BAUDRATE__ Baud rate set by the configuration function.
Return values:
Test result (TRUE or FALSE)

Definition at line 863 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BLOCKLENGTH ( __LENGTH__ ) ((__LENGTH__) <= 0xFFU)

Check the block length range.

Note:
The maximum SMARTCARD block length is 0xFF.
Parameters:
__LENGTH__ block length.
Return values:
Test result (TRUE or FALSE)

Definition at line 870 of file stm32g0xx_hal_smartcard.h.

#define IS_SMARTCARD_CLOCKPRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))

Ensure that SMARTCARD clock Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 957 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

Ensure that SMARTCARD frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ SMARTCARD frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 929 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( __MODE__ ) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that SMARTCARD communication mode is valid.

Parameters:
__MODE__ SMARTCARD communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 910 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK ( __NACK__ )
Value:
(((__NACK__) == SMARTCARD_NACK_ENABLE) || \
                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

Ensure that SMARTCARD NACK transmission setting is valid.

Parameters:
__NACK__ SMARTCARD NACK transmission setting.
Return values:
SET (__NACK__ is valid) or RESET (__NACK__ is invalid)

Definition at line 943 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

Ensure that SMARTCARD frame sampling is valid.

Parameters:
__ONEBIT__ SMARTCARD frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 936 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

Ensure that SMARTCARD frame overrun setting is valid.

Parameters:
__OVERRUN__ SMARTCARD frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1015 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

Ensure that SMARTCARD frame parity is valid.

Parameters:
__PARITY__ SMARTCARD frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 903 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( __CPHA__ ) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

Ensure that SMARTCARD frame phase is valid.

Parameters:
__CPHA__ SMARTCARD frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 923 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( __CPOL__ )
Value:
(((__CPOL__) == SMARTCARD_POLARITY_LOW)\
                                         || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

Ensure that SMARTCARD frame polarity is valid.

Parameters:
__CPOL__ SMARTCARD frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 916 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))

Ensure that SMARTCARD request parameter is valid.

Parameters:
__PARAM__ SMARTCARD request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1036 of file stm32g0xx_hal_smartcard.h.

#define IS_SMARTCARD_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))

Ensure that SMARTCARD frame number of stop bits is valid.

Parameters:
__STOPBITS__ SMARTCARD frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 896 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

Ensure that SMARTCARD receiver timeout setting is valid.

Parameters:
__TIMEOUT__ SMARTCARD receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 950 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 877 of file stm32g0xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( __LENGTH__ ) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

Ensure that SMARTCARD frame length is valid.

Parameters:
__LENGTH__ SMARTCARD frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 890 of file stm32g0xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Extended Private Constants

Defines
SMARTCARD Extended Private Constants
SMARTCARDEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 62 of file stm32g0xx_hal_smartcard_ex.c.

Referenced by SMARTCARDEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 65 of file stm32g0xx_hal_smartcard_ex.c.

Referenced by SMARTCARDEx_SetNbDataToProcess().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
SMARTCARD Extended Exported Functions

Extended control functions. More...

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Extended control functions.

  ===============================================================================
                      ##### Peripheral Control functions #####
  ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
BlockLength | SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 104 of file stm32g0xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 157 of file stm32g0xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 127 of file stm32g0xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
TimeOutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 116 of file stm32g0xx_hal_smartcard_ex.c.

References assert_param, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Peripheral IO operation functions

Functions
Extended Peripheral IO operation functions
SMARTCARD Extended Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of FIFO mode related callback functions.

    (#) TX/RX Fifos Callbacks:
        (++) HAL_SMARTCARDEx_RxFifoFullCallback()
        (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()

Function Documentation

void HAL_SMARTCARDEx_RxFifoFullCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD RX Fifo full callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 210 of file stm32g0xx_hal_smartcard_ex.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARDEx_TxFifoEmptyCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD TX Fifo empty callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 226 of file stm32g0xx_hal_smartcard_ex.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Peripheral FIFO Control functions

Functions
Extended Peripheral FIFO Control functions
SMARTCARD Extended Exported Functions

SMARTCARD control functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

SMARTCARD control functions.

 ===============================================================================
                  ##### Peripheral FIFO Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SMARTCARD
    FIFO feature.
     (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 304 of file stm32g0xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 263 of file stm32g0xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FIFOMODE_ENABLE, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_RXFIFO_THRESHOLD_1_8
  • SMARTCARD_RXFIFO_THRESHOLD_1_4
  • SMARTCARD_RXFIFO_THRESHOLD_1_2
  • SMARTCARD_RXFIFO_THRESHOLD_3_4
  • SMARTCARD_RXFIFO_THRESHOLD_7_8
  • SMARTCARD_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 399 of file stm32g0xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_RXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_TXFIFO_THRESHOLD_1_8
  • SMARTCARD_TXFIFO_THRESHOLD_1_4
  • SMARTCARD_TXFIFO_THRESHOLD_1_2
  • SMARTCARD_TXFIFO_THRESHOLD_3_4
  • SMARTCARD_TXFIFO_THRESHOLD_7_8
  • SMARTCARD_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 350 of file stm32g0xx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Extended Private Functions

Functions
SMARTCARD Extended Private Functions
SMARTCARDEx

Functions

static void SMARTCARDEx_SetNbDataToProcess (SMARTCARD_HandleTypeDef *hsmartcard)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void SMARTCARDEx_SetNbDataToProcess ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the USART configuration registers.
Parameters:
hsmartcard SMARTCARD handle.
Return values:
None

Definition at line 454 of file stm32g0xx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, SMARTCARD_FIFOMODE_DISABLE, and TX_FIFO_DEPTH.

Referenced by HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Extended Private Macros

Defines
SMARTCARD Extended Private Macros
SMARTCARDEx

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.
#define | IS_SMARTCARD_FIFOMODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Define Documentation

#define IS_SMARTCARD_FIFOMODE_STATE ( __STATE__ )
Value:
(((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
                                                ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))

Ensure that SMARTCARD FIFO mode is valid.

Parameters:
__STATE__ SMARTCARD FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 395 of file stm32g0xx_hal_smartcard_ex.h.

#define IS_SMARTCARD_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ SMARTCARD RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 413 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_SetRxFifoThreshold().

#define IS_SMARTCARD_TRANSMISSION_COMPLETION ( __TXCOMPLETE__ )
Value:
(((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))

Ensure that SMARTCARD frame transmission completion used flag is valid.

Parameters:
__TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
Return values:
SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)

Definition at line 388 of file stm32g0xx_hal_smartcard_ex.h.

#define IS_SMARTCARD_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ SMARTCARD TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 402 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_SetTxFifoThreshold().

#define SMARTCARD_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the SMARTCARD clock source.

Parameters:
__HANDLE__ | specifies the SMARTCARD Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the SMARTCARD clocking source, written in __CLOCKSOURCE__.

Definition at line 204 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG ( __HANDLE__ ) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))

Return the transmission completion flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Note:
Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is reported.
Return values:
Transmission completion flag

Definition at line 380 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING ( __HANDLE__ )
Value:
do {                                                                                                       \
    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
    {                                                                                                        \
      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
    }                                                                                                        \
    else                                                                                                     \
    {                                                                                                        \
      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
    }                                                                                                        \
  } while(0U)

Set the Transmission Completion flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Note:
If TCBGT (Transmission Complete Before Guard Time) flag is not available or if AdvancedInit.TxCompletionIndication is not already filled, the latter is forced to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
Return values:
None

Definition at line 361 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Transmission Completion Indication

Defines
SMARTCARD Transmission Completion Indication
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC

Define Documentation

#define SMARTCARD_TC SMARTCARD_IT_TC

SMARTCARD transmission complete (flag raised when guard time has elapsed)

Definition at line 49 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT

SMARTCARD transmission complete before guard time

Definition at line 48 of file stm32g0xx_hal_smartcard_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD advanced feature initialization type

Defines
SMARTCARD advanced feature initialization type
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U

Binary data inversion

Definition at line 60 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U

DMA disable on Reception Error

Definition at line 63 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Most significant bit sent/received first

Definition at line 64 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U

No advanced feature initialization

Definition at line 57 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U

RX pin active level inversion

Definition at line 59 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U

RX overrun disable

Definition at line 62 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U

TX/RX pins swap

Definition at line 61 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U

TX completion indication before of after guard time

Definition at line 65 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U

TX pin active level inversion

Definition at line 58 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD FIFO mode

Defines
SMARTCARD FIFO mode
SMARTCARD Extended Exported Constants

SMARTCARD FIFO mode. More...

Defines

#define | SMARTCARD_FIFOMODE_DISABLE 0x00000000U
#define | SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

SMARTCARD FIFO mode.

Define Documentation

#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 74 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_DisableFifoMode(), and SMARTCARDEx_SetNbDataToProcess().

#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 75 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), and HAL_SMARTCARDEx_EnableFifoMode().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD TXFIFO threshold level

Defines
SMARTCARD TXFIFO threshold level
SMARTCARD Extended Exported Constants

SMARTCARD TXFIFO level. More...

Defines

#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

SMARTCARD TXFIFO level.

Define Documentation

#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 86 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 85 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 84 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 87 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 88 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 89 of file stm32g0xx_hal_smartcard_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD RXFIFO threshold level

Defines
SMARTCARD RXFIFO threshold level
SMARTCARD Extended Exported Constants

SMARTCARD RXFIFO level. More...

Defines

#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

SMARTCARD RXFIFO level.

Define Documentation

#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 100 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 99 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 98 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 101 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 102 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 103 of file stm32g0xx_hal_smartcard_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Extended Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY

SMARTCARD busy flag

Definition at line 116 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF

SMARTCARD end of block flag

Definition at line 117 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_FE USART_ISR_FE

SMARTCARD frame error

Definition at line 127 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE

SMARTCARD idle line detection

Definition at line 124 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_NE USART_ISR_NE

SMARTCARD noise error

Definition at line 126 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_ORE USART_ISR_ORE

SMARTCARD overrun error

Definition at line 125 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_PE USART_ISR_PE

SMARTCARD parity error

Definition at line 128 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_REACK USART_ISR_REACK

SMARTCARD receive enable acknowledge flag

Definition at line 114 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF

SMARTCARD receiver timeout flag

Definition at line 118 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF

SMARTCARD RXFIFO Full flag

Definition at line 130 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE

SMARTCARD RXFIFO not empty

Definition at line 123 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT

SMARTCARD RXFIFO threshold flag

Definition at line 131 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE

SMARTCARD read data register not empty

Definition at line 122 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC USART_ISR_TC

SMARTCARD transmission complete

Definition at line 121 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT

SMARTCARD transmission complete before guard time completion

Definition at line 113 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK

SMARTCARD transmit enable acknowledge flag

Definition at line 115 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF

SMARTCARD transmit data register empty

Definition at line 119 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE

SMARTCARD TXFIFO Empty flag

Definition at line 129 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF

SMARTCARD TXFIFO not full

Definition at line 120 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT

SMARTCARD TXFIFO threshold flag

Definition at line 132 of file stm32g0xx_hal_smartcard_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Extended Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | SMARTCARD_IT_PE 0x0028U
#define | SMARTCARD_IT_TXE 0x0727U
#define | SMARTCARD_IT_TXFNF 0x0727U
#define | SMARTCARD_IT_TC 0x0626U
#define | SMARTCARD_IT_RXNE 0x0525U
#define | SMARTCARD_IT_RXFNE 0x0525U
#define | SMARTCARD_IT_IDLE 0x0424U
#define | SMARTCARD_IT_ERR 0x0060U
#define | SMARTCARD_IT_ORE 0x0300U
#define | SMARTCARD_IT_NE 0x0200U
#define | SMARTCARD_IT_FE 0x0100U
#define | SMARTCARD_IT_EOB 0x0C3BU
#define | SMARTCARD_IT_RTO 0x0B3AU
#define | SMARTCARD_IT_TCBGT 0x1978U
#define | SMARTCARD_IT_RXFF 0x183FU
#define | SMARTCARD_IT_TXFE 0x173EU
#define | SMARTCARD_IT_RXFT 0x1A7CU
#define | SMARTCARD_IT_TXFT 0x1B77U

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5 bits)
  • XX : Interrupt source register (2 bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5 bits)

Define Documentation

#define SMARTCARD_IT_EOB 0x0C3BU

SMARTCARD end of block interruption

Definition at line 160 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ERR 0x0060U

SMARTCARD error interruption

Definition at line 155 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_FE 0x0100U

SMARTCARD frame error interruption

Definition at line 158 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_IDLE 0x0424U

SMARTCARD idle line detection interruption

Definition at line 153 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_NE 0x0200U

SMARTCARD noise error interruption

Definition at line 157 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ORE 0x0300U

SMARTCARD overrun error interruption

Definition at line 156 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_PE 0x0028U

SMARTCARD parity error interruption

Definition at line 147 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RTO 0x0B3AU

SMARTCARD receiver timeout interruption

Definition at line 161 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFF 0x183FU

SMARTCARD RXFIFO full interruption

Definition at line 164 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFNE 0x0525U

SMARTCARD RXFIFO not empty interruption

Definition at line 152 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFT 0x1A7CU

SMARTCARD RXFIFO threshold reached interruption

Definition at line 166 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXNE 0x0525U

SMARTCARD read data register not empty interruption

Definition at line 151 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TC 0x0626U

SMARTCARD transmission complete interruption

Definition at line 150 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TCBGT 0x1978U

SMARTCARD transmission complete before guard time completion interruption

Definition at line 162 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXE 0x0727U

SMARTCARD transmit data register empty interruption

Definition at line 148 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFE 0x173EU

SMARTCARD TXFIFO empty interruption

Definition at line 165 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFNF 0x0727U

SMARTCARD TX FIFO not full interruption

Definition at line 149 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFT 0x1B77U

SMARTCARD TXFIFO threshold reached interruption

Definition at line 167 of file stm32g0xx_hal_smartcard_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Interruption Clear Flags

Defines
SMARTCARD Interruption Clear Flags
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NECF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

Define Documentation

#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

SMARTCARD end of block clear flag

Definition at line 184 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_FEF USART_ICR_FECF

SMARTCARD framing error clear flag

Definition at line 176 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF

SMARTCARD idle line detected clear flag

Definition at line 179 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_NEF USART_ICR_NECF

SMARTCARD noise error detected clear flag

Definition at line 177 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF

SMARTCARD overrun error clear flag

Definition at line 178 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_PEF USART_ICR_PECF

SMARTCARD parity error clear flag

Definition at line 175 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF

SMARTCARD receiver time out clear flag

Definition at line 183 of file stm32g0xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF

SMARTCARD transmission complete before guard time completion clear flag

Definition at line 182 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF

SMARTCARD transmission complete clear flag

Definition at line 181 of file stm32g0xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty Clear Flag

Definition at line 180 of file stm32g0xx_hal_smartcard_ex.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Private Constants

Defines
SMBUS Private Constants
SMBUS

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFUL)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Define Documentation

#define HAL_TIMEOUT_ADDR (10000U)

10 s

Definition at line 192 of file stm32g0xx_hal_smbus.c.

#define HAL_TIMEOUT_BUSY (25U)

25 ms

Definition at line 193 of file stm32g0xx_hal_smbus.c.

#define HAL_TIMEOUT_DIR (25U)

25 ms

Definition at line 194 of file stm32g0xx_hal_smbus.c.

#define HAL_TIMEOUT_RXNE (25U)

25 ms

Definition at line 195 of file stm32g0xx_hal_smbus.c.

#define HAL_TIMEOUT_STOPF (25U)

25 ms

Definition at line 196 of file stm32g0xx_hal_smbus.c.

#define HAL_TIMEOUT_TC (25U)

25 ms

Definition at line 197 of file stm32g0xx_hal_smbus.c.

#define HAL_TIMEOUT_TCR (25U)

25 ms

Definition at line 198 of file stm32g0xx_hal_smbus.c.

#define HAL_TIMEOUT_TXIS (25U)

25 ms

Definition at line 199 of file stm32g0xx_hal_smbus.c.

#define MAX_NBYTE_SIZE 255U

Definition at line 200 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define TIMING_CLEAR_MASK (0xF0FFFFFFUL)

SMBUS TIMING clear register Mask

Definition at line 191 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMBUS Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the SMBUSx peripheral:

      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).

      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Bus Timeout
        (++) Analog Filer mode
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode
        (++) Packet Error Check mode
        (++) Peripheral mode

      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
          of the selected SMBUSx peripheral.

      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
          HAL_SMBUS_ConfigDigitalFilter().

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure Analog noise filter.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
AnalogFilter This parameter can be one of the following values:
  • SMBUS_ANALOGFILTER_ENABLE
  • SMBUS_ANALOGFILTER_DISABLE
Return values:
HAL status

Definition at line 494 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_ANALOG_FILTER, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital noise filter.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 538 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_DIGITAL_FILTER, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_DeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS peripheral.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 414 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspDeInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::PreviousState, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Init ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 289 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __SMBUS_HandleTypeDef::AddrCallback, SMBUS_InitTypeDef::AddressingMode, SMBUS_InitTypeDef::AnalogFilter, assert_param, SMBUS_InitTypeDef::DualAddressMode, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, SMBUS_InitTypeDef::GeneralCallMode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspInit(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_ADDRESSING_MODE, IS_SMBUS_ANALOG_FILTER, IS_SMBUS_DUAL_ADDRESS, IS_SMBUS_GENERAL_CALL, IS_SMBUS_NO_STRETCH, IS_SMBUS_OWN_ADDRESS1, IS_SMBUS_OWN_ADDRESS2, IS_SMBUS_OWN_ADDRESS2_MASK, IS_SMBUS_PEC, IS_SMBUS_PERIPHERAL_MODE, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::Lock, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspInitCallback, SMBUS_InitTypeDef::NoStretchMode, SMBUS_InitTypeDef::OwnAddress1, SMBUS_InitTypeDef::OwnAddress2, SMBUS_InitTypeDef::OwnAddress2Masks, SMBUS_InitTypeDef::PacketErrorCheckMode, SMBUS_InitTypeDef::PeripheralMode, __SMBUS_HandleTypeDef::PreviousState, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, SMBUS_ADDRESSINGMODE_10BIT, SMBUS_ADDRESSINGMODE_7BIT, SMBUS_PEC_ENABLE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP, SMBUS_InitTypeDef::SMBusTimeout, __SMBUS_HandleTypeDef::State, SMBUS_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_SMBUS_MspDeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 475 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_DeInit(), and HAL_SMBUS_UnRegisterCallback().

void HAL_SMBUS_MspInit ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 459 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_UnRegisterCallback().

HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | pSMBUS_AddrCallbackTypeDef | pCallback
 | ) |  |

Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pCallback | pointer to the Address Match Callback function
Return values:
HAL status

Definition at line 809 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_STATE_READY, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_RegisterCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | HAL_SMBUS_CallbackIDTypeDef | CallbackID,
 |  | pSMBUS_CallbackTypeDef | pCallback
 | ) |  |

Register a User SMBUS Callback To be used instead of the weak predefined callback.

Note:
The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and HAL_SMBUS_MSPDEINIT_CB_ID.
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_SMBUS_ERROR_CB_ID Error callback ID
  • HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  • HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 605 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_CB_ID, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_LISTEN_COMPLETE_CB_ID, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID, HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID, HAL_SMBUS_MSPDEINIT_CB_ID, HAL_SMBUS_MSPINIT_CB_ID, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::MspInitCallback, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback ( SMBUS_HandleTypeDef * hsmbus )

UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 845 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_STATE_READY, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | HAL_SMBUS_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.

Note:
The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and HAL_SMBUS_MSPDEINIT_CB_ID
Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_SMBUS_ERROR_CB_ID Error callback ID
  • HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  • HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 718 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_CB_ID, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_LISTEN_COMPLETE_CB_ID, HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID, HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID, HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspDeInit(), HAL_SMBUS_MSPDEINIT_CB_ID, HAL_SMBUS_MspInit(), HAL_SMBUS_MSPINIT_CB_ID, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID, HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::MspInitCallback, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, and __SMBUS_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Blocking mode Polling

Functions
Blocking mode Polling
Input and Output operation functions

Functions

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1451 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and __SMBUS_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Non-Blocking mode Interrupt

Functions
Non-Blocking mode Interrupt
Input and Output operation functions

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1430 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1387 of file stm32g0xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1411 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1371 of file stm32g0xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 1128 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1031 of file stm32g0xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 925 of file stm32g0xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1291 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1193 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
SMBUS Exported Functions | Input and Output operation functions

Functions

void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.

Function Documentation

void HAL_SMBUS_AddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
TransferDirection | Master request Transfer Direction (Write/Read)
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 1746 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterAddrCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_ER_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS error interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1670 of file stm32g0xx_hal_smbus.c.

References SMBUS_ITErrorHandler().

void HAL_SMBUS_ErrorCallback ( SMBUS_HandleTypeDef * hsmbus )

SMBUS error callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1781 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

void HAL_SMBUS_EV_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS event interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1592 of file stm32g0xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, SMBUS_CHECK_FLAG, SMBUS_CHECK_IT_SOURCE, SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_IT_ADDRI, SMBUS_IT_NACKI, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TXI, SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and __SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ListenCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Listen Complete callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1765 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_MasterRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1697 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void HAL_SMBUS_MasterTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1681 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void HAL_SMBUS_SlaveRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1728 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_SlaveTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1712 of file stm32g0xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMBUS Exported Functions | Input and Output operation functions

Peripheral State and Errors functions. More...

Functions

uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SMBUS_GetError ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS error code.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
SMBUS Error Code

Definition at line 1828 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode.

uint32_t HAL_SMBUS_GetState ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS handle state.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL state

Definition at line 1816 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Input and Output operation functions

Modules | Functions
Input and Output operation functions
SMBUS Exported Functions

Data transfers functions. More...

Modules

Blocking mode Polling
Non-Blocking mode Interrupt
IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SMBUS data
    transfers.

    (#) Blocking mode function to check if device is ready for usage is :
        (++) HAL_SMBUS_IsDeviceReady()

    (#) There is only one mode of transfer:
       (++) Non-Blocking mode : The communication is performed using Interrupts.
            These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated SMBUS IRQ when using Interrupt mode.

    (#) Non-Blocking mode functions with Interrupt are :
        (++) HAL_SMBUS_Master_Transmit_IT()
        (++) HAL_SMBUS_Master_Receive_IT()
        (++) HAL_SMBUS_Slave_Transmit_IT()
        (++) HAL_SMBUS_Slave_Receive_IT()
        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
        (++) HAL_SMBUS_DisableListen_IT()
        (++) HAL_SMBUS_EnableAlert_IT()
        (++) HAL_SMBUS_DisableAlert_IT()

    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
        (++) HAL_SMBUS_MasterTxCpltCallback()
        (++) HAL_SMBUS_MasterRxCpltCallback()
        (++) HAL_SMBUS_SlaveTxCpltCallback()
        (++) HAL_SMBUS_SlaveRxCpltCallback()
        (++) HAL_SMBUS_AddrCallback()
        (++) HAL_SMBUS_ListenCpltCallback()
        (++) HAL_SMBUS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1430 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1387 of file stm32g0xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1411 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1371 of file stm32g0xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1451 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 1128 of file stm32g0xx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1031 of file stm32g0xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 925 of file stm32g0xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1291 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1193 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Private Functions

Functions
SMBUS Private Functions
SMBUS Exported Functions | SMBUS

Data transfers Private functions. More...

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ITErrorHandler (SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the enabling of Interrupts.
static void | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the disabling of Interrupts.
static void | SMBUS_Flush_TXDR (SMBUS_HandleTypeDef *hsmbus)
SMBUS Tx data register flush process.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | SMBUS_ConvertOtherXferOptions (SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.

Detailed Description

Data transfers Private functions.

Function Documentation

static void SMBUS_ConvertOtherXferOptions ( SMBUS_HandleTypeDef * hsmbus ) [static]

Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2727 of file stm32g0xx_hal_smbus.c.

References SMBUS_FIRST_AND_LAST_FRAME_NO_PEC, SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC, SMBUS_FIRST_FRAME, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC, SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC, SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_SENDPEC_MODE, and __SMBUS_HandleTypeDef::XferOptions.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_Disable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 2451 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE_IT, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_GET_ALERT_ENABLED, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, SMBUS_IT_TXI, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static void SMBUS_Enable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 2411 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_ENABLE_IT, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, and SMBUS_IT_TXI.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_Flush_TXDR ( SMBUS_HandleTypeDef * hsmbus ) [static]

SMBUS Tx data register flush process.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2668 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_TXE, and SMBUS_FLAG_TXIS.

Referenced by SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static void SMBUS_ITErrorHandler ( SMBUS_HandleTypeDef * hsmbus ) [static]

SMBUS interrupts error handler.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2523 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ERROR_ALERT, HAL_SMBUS_ERROR_ARLO, HAL_SMBUS_ERROR_BERR, HAL_SMBUS_ERROR_BUSTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ERROR_OVR, HAL_SMBUS_ERROR_PECERR, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::PreviousState, SMBUS_FLAG_ALERT, SMBUS_FLAG_ARLO, SMBUS_FLAG_BERR, SMBUS_FLAG_OVR, SMBUS_FLAG_PECERR, SMBUS_FLAG_TIMEOUT, SMBUS_Flush_TXDR(), SMBUS_IT_ERRI, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_ER_IRQHandler(), and SMBUS_Master_ISR().

static HAL_StatusTypeDef SMBUS_Master_ISR | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | StatusFlags
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
StatusFlags | Value of Interrupt Flags.
Return values:
HAL status

Definition at line 1853 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_CHECK_FLAG, SMBUS_Disable_IRQ(), SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_Flush_TXDR(), SMBUS_GET_PEC_MODE, SMBUS_GET_STOP_MODE, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_ITErrorHandler(), SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static HAL_StatusTypeDef SMBUS_Slave_ISR | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | StatusFlags
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
StatusFlags | Value of Interrupt Flags.
Return values:
HAL status

Definition at line 2143 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE_IT, __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::ListenCpltCallback, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, SMBUS_CHECK_FLAG, SMBUS_Disable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_Flush_TXDR(), SMBUS_GET_ADDR_MATCH, SMBUS_GET_DIR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static void SMBUS_TransferConfig | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hsmbus | SMBUS handle.
DevAddress | specifies the slave address to be programmed.
Size | specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the SMBUS START condition generation. This parameter can be one or a combination of the following values:
  • SMBUS_RELOAD_MODE Enable Reload mode.
  • SMBUS_AUTOEND_MODE Enable Automatic end mode.
  • SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
  • SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
Request New state of the SMBUS START condition generation. This parameter can be one of the following values:
  • SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
  • SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • SMBUS_GENERATE_START_READ Generate Restart for read request.
  • SMBUS_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 2704 of file stm32g0xx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_MODE, and IS_SMBUS_TRANSFER_REQUEST.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMBUS Communication Timeout.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Flag | Specifies the SMBUS flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2633 of file stm32g0xx_hal_smbus.c.

References __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_InitTypeDef Struct Reference
SMBUS Configuration Structure definition

#include <stm32g0xx_hal_smbus.h>

Data Fields

uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode
uint32_t | PacketErrorCheckMode
uint32_t | PeripheralMode
uint32_t | SMBusTimeout

Detailed Description

Definition at line 47 of file stm32g0xx_hal_smbus.h.

Field Documentation

uint32_t SMBUS_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode for master is selected. This parameter can be a value of SMBUS addressing mode

Definition at line 58 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

uint32_t SMBUS_InitTypeDef::AnalogFilter

Specifies if Analog Filter is enable or not. This parameter can be a value of SMBUS Analog Filter

Definition at line 52 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of SMBUS dual addressing mode

Definition at line 61 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of SMBUS general call addressing mode.

Definition at line 71 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of SMBUS nostretch mode

Definition at line 74 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 55 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 64 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of SMBUS ownaddress2 masks.

Definition at line 67 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PacketErrorCheckMode

Specifies if Packet Error Check mode is selected. This parameter can be a value of SMBUS packet error check mode

Definition at line 77 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PeripheralMode

Specifies which mode of Periphal is selected. This parameter can be a value of SMBUS peripheral mode

Definition at line 80 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::SMBusTimeout

Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 83 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::Timing

Specifies the SMBUS_TIMINGR_register value. This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 49 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_smbus.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HAL state definition

Defines
HAL state definition
SMBUS Exported Types

HAL State definition. More...

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)

Detailed Description

HAL State definition.

Define Documentation

#define HAL_SMBUS_STATE_BUSY (0x00000002U)

SMBUS internal process is ongoing

Definition at line 98 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUSEx_DisableWakeUp(), and HAL_SMBUSEx_EnableWakeUp().

#define HAL_SMBUS_STATE_ERROR (0x00000004U)

Reception process is ongoing

Definition at line 104 of file stm32g0xx_hal_smbus.h.

#define HAL_SMBUS_STATE_LISTEN (0x00000008U)

Address Listen Mode is ongoing

Definition at line 105 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)

Master Data Reception process is ongoing

Definition at line 100 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)

Master Data Transmission process is ongoing

Definition at line 99 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_READY (0x00000001U)

SMBUS initialized and ready for use

Definition at line 97 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_STATE_RESET (0x00000000U)

SMBUS not yet initialized or disabled

Definition at line 96 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)

Slave Data Reception process is ongoing

Definition at line 102 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)

Slave Data Transmission process is ongoing

Definition at line 101 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U)

Timeout state

Definition at line 103 of file stm32g0xx_hal_smbus.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Error Code definition

Defines
SMBUS Error Code definition
SMBUS Exported Types

SMBUS Error Code definition. More...

Defines

#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)

Detailed Description

SMBUS Error Code definition.

Define Documentation

#define HAL_SMBUS_ERROR_ACKF (0x00000004U)

ACKF error

Definition at line 117 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_ERROR_ALERT (0x00000040U)

Alert error

Definition at line 121 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 116 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BERR (0x00000001U)

BERR error

Definition at line 115 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)

Bus Timeout error

Definition at line 120 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)

Timeout error

Definition at line 119 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)

Invalid Callback error

Definition at line 124 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterAddrCallback(), and HAL_SMBUS_UnRegisterCallback().

#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)

Invalid Parameters error

Definition at line 126 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define HAL_SMBUS_ERROR_NONE (0x00000000U)

No error

Definition at line 114 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_OVR (0x00000008U)

OVR error

Definition at line 118 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_PECERR (0x00000080U)

PEC error

Definition at line 122 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS handle Structure definition

Data Structures | Typedefs | Enumerations
SMBUS handle Structure definition
SMBUS Exported Types

SMBUS handle Structure definition. More...

Data Structures

struct | __SMBUS_HandleTypeDef

Typedefs

typedef struct
__SMBUS_HandleTypeDef 		SMBUS_HandleTypeDef
typedef void(* | pSMBUS_CallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus)
HAL SMBUS Callback pointer definition.
typedef void(* | pSMBUS_AddrCallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_SMBUS_CallbackIDTypeDef {
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_SMBUS_ERROR_CB_ID = 0x05U, HAL_SMBUS_MSPINIT_CB_ID = 0x06U, HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
}
HAL SMBUS Callback ID enumeration definition. More...

Detailed Description

SMBUS handle Structure definition.

Typedef Documentation

typedef void(* pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

pointer to an SMBUS Address Match callback function

Definition at line 209 of file stm32g0xx_hal_smbus.h.

typedef void(* pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus)

HAL SMBUS Callback pointer definition.

pointer to an SMBUS callback function

Definition at line 207 of file stm32g0xx_hal_smbus.h.

typedef struct __SMBUS_HandleTypeDef SMBUS_HandleTypeDef

Enumeration Type Documentation

enum HAL_SMBUS_CallbackIDTypeDef

HAL SMBUS Callback ID enumeration definition.

Enumerator:
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID

SMBUS Master Tx Transfer completed callback ID

HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID

SMBUS Master Rx Transfer completed callback ID

HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID

SMBUS Slave Tx Transfer completed callback ID

HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID

SMBUS Slave Rx Transfer completed callback ID

HAL_SMBUS_LISTEN_COMPLETE_CB_ID

SMBUS Listen Complete callback ID

HAL_SMBUS_ERROR_CB_ID

SMBUS Error callback ID

HAL_SMBUS_MSPINIT_CB_ID

SMBUS Msp Init callback ID

HAL_SMBUS_MSPDEINIT_CB_ID

SMBUS Msp DeInit callback ID

Definition at line 190 of file stm32g0xx_hal_smbus.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __SMBUS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SMBUS_HandleTypeDef Struct Reference
SMBUS handle Structure definition

#include <stm32g0xx_hal_smbus.h>

Data Fields

I2C_TypeDef * | Instance
SMBUS_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
void(* | MasterTxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | MasterRxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | SlaveTxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | SlaveRxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | ListenCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | ErrorCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | AddrCallback )(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
void(* | MspInitCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | MspDeInitCallback )(struct __SMBUS_HandleTypeDef *hsmbus)

Detailed Description

Definition at line 136 of file stm32g0xx_hal_smbus.h.

Field Documentation

void(* __SMBUS_HandleTypeDef::AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

SMBUS Slave Address Match callback

Definition at line 175 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_UnRegisterAddrCallback(), and SMBUS_Slave_ISR().

void(* __SMBUS_HandleTypeDef::ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Error callback

Definition at line 172 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::ErrorCode

SMBUS Error code

Definition at line 159 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_GetError(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

SMBUS_InitTypeDef __SMBUS_HandleTypeDef::Init

SMBUS communication parameters

Definition at line 143 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

I2C_TypeDef* __SMBUS_HandleTypeDef::Instance

SMBUS registers base address

Definition at line 141 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), SMBUS_Flush_TXDR(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_TransferConfig().

void(* __SMBUS_HandleTypeDef::ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Listen Complete callback

Definition at line 170 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

HAL_LockTypeDef __SMBUS_HandleTypeDef::Lock

SMBUS locking object

Definition at line 155 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

void(* __SMBUS_HandleTypeDef::MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Master Rx Transfer completed callback

Definition at line 164 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void(* __SMBUS_HandleTypeDef::MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Master Tx Transfer completed callback

Definition at line 162 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void(* __SMBUS_HandleTypeDef::MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Msp DeInit callback

Definition at line 180 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

void(* __SMBUS_HandleTypeDef::MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Msp Init callback

Definition at line 178 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

uint8_t* __SMBUS_HandleTypeDef::pBuffPtr

Pointer to SMBUS transfer buffer

Definition at line 145 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::PreviousState

SMBUS communication Previous state

Definition at line 153 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

void(* __SMBUS_HandleTypeDef::SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Slave Rx Transfer completed callback

Definition at line 168 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void(* __SMBUS_HandleTypeDef::SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Slave Tx Transfer completed callback

Definition at line 166 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::State

SMBUS communication state

Definition at line 157 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_GetState(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), SMBUS_WaitOnFlagUntilTimeout(), and SPI_WaitFifoStateUntilTimeout().

__IO uint16_t __SMBUS_HandleTypeDef::XferCount

SMBUS transfer counter

Definition at line 149 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::XferOptions

SMBUS transfer options

Definition at line 151 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

uint16_t __SMBUS_HandleTypeDef::XferSize

SMBUS transfer size

Definition at line 147 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_smbus.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Analog Filter

Defines
SMBUS Analog Filter
SMBUS Exported Constants

Defines

#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 231 of file stm32g0xx_hal_smbus.h.

#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)

Definition at line 230 of file stm32g0xx_hal_smbus.h.

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STM32G0C1xx HAL User Manual: SMBUS addressing mode

Defines
SMBUS addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 240 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 239 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

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STM32G0C1xx HAL User Manual: SMBUS dual addressing mode

Defines
SMBUS dual addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 249 of file stm32g0xx_hal_smbus.h.

#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 250 of file stm32g0xx_hal_smbus.h.

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STM32G0C1xx HAL User Manual: SMBUS ownaddress2 masks

Defines
SMBUS ownaddress2 masks
SMBUS Exported Constants

Defines

#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 260 of file stm32g0xx_hal_smbus.h.

#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 261 of file stm32g0xx_hal_smbus.h.

#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 262 of file stm32g0xx_hal_smbus.h.

#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 263 of file stm32g0xx_hal_smbus.h.

#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 264 of file stm32g0xx_hal_smbus.h.

#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 265 of file stm32g0xx_hal_smbus.h.

#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 266 of file stm32g0xx_hal_smbus.h.

#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 259 of file stm32g0xx_hal_smbus.h.

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STM32G0C1xx HAL User Manual: SMBUS general call addressing mode

Defines
SMBUS general call addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define SMBUS_GENERALCALL_DISABLE (0x00000000U)

Definition at line 275 of file stm32g0xx_hal_smbus.h.

#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 276 of file stm32g0xx_hal_smbus.h.

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STM32G0C1xx HAL User Manual: SMBUS nostretch mode

Defines
SMBUS nostretch mode
SMBUS Exported Constants

Defines

#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 284 of file stm32g0xx_hal_smbus.h.

#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 285 of file stm32g0xx_hal_smbus.h.

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STM32G0C1xx HAL User Manual: SMBUS packet error check mode

Defines
SMBUS packet error check mode
SMBUS Exported Constants

Defines

#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN

Define Documentation

#define SMBUS_PEC_DISABLE (0x00000000U)

Definition at line 293 of file stm32g0xx_hal_smbus.h.

#define SMBUS_PEC_ENABLE I2C_CR1_PECEN

Definition at line 294 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

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STM32G0C1xx HAL User Manual: SMBUS peripheral mode

Defines
SMBUS peripheral mode
SMBUS Exported Constants

Defines

#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Define Documentation

#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN

Definition at line 302 of file stm32g0xx_hal_smbus.h.

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)

Definition at line 303 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Definition at line 304 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

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STM32G0C1xx HAL User Manual: SMBUS ReloadEndMode definition

Defines
SMBUS ReloadEndMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Define Documentation

#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 315 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 314 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Definition at line 316 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SOFTEND_MODE (0x00000000U)

Definition at line 313 of file stm32g0xx_hal_smbus.h.

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STM32G0C1xx HAL User Manual: SMBUS StartStopMode definition

Defines
SMBUS StartStopMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 327 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT().

#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Definition at line 328 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT().

#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Definition at line 326 of file stm32g0xx_hal_smbus.h.

#define SMBUS_NO_STARTSTOP (0x00000000U)

Definition at line 325 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

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STM32G0C1xx HAL User Manual: SMBUS XferOptions definition

Defines
SMBUS XferOptions definition
SMBUS Exported Constants

Defines

#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Define Documentation

#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 343 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 346 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE

Definition at line 341 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 345 of file stm32g0xx_hal_smbus.h.

#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 344 of file stm32g0xx_hal_smbus.h.

#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 347 of file stm32g0xx_hal_smbus.h.

#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))

Definition at line 342 of file stm32g0xx_hal_smbus.h.

#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)

Definition at line 354 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Definition at line 355 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)

Definition at line 352 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)

Definition at line 353 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

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STM32G0C1xx HAL User Manual: SMBUS Interrupt configuration definition

Defines
SMBUS Interrupt configuration definition
SMBUS Exported Constants

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX
#define | SMBUS_IT_RX
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Detailed Description

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Definition at line 378 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 370 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)

Definition at line 377 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_ERRI I2C_CR1_ERRIE

Definition at line 366 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_ITErrorHandler().

#define SMBUS_IT_NACKI I2C_CR1_NACKIE

Definition at line 369 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_RX
Value:
(SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
                                                 SMBUS_IT_RXI)

Definition at line 375 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_RXI I2C_CR1_RXIE

Definition at line 371 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_STOPI I2C_CR1_STOPIE

Definition at line 368 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TCI I2C_CR1_TCIE

Definition at line 367 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TX
Value:
(SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
                                                 SMBUS_IT_NACKI | SMBUS_IT_TXI)

Definition at line 373 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_TXI I2C_CR1_TXIE

Definition at line 372 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

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STM32G0C1xx HAL User Manual: SMBUS Flag definition

Defines
SMBUS Flag definition
SMBUS Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXXXXXX : Flag mask

Define Documentation

#define SMBUS_FLAG_ADDR I2C_ISR_ADDR

Definition at line 393 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_AF I2C_ISR_NACKF

Definition at line 394 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_ALERT I2C_ISR_ALERT

Definition at line 403 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), and SMBUS_ITErrorHandler().

#define SMBUS_FLAG_ARLO I2C_ISR_ARLO

Definition at line 399 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BERR I2C_ISR_BERR

Definition at line 398 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BUSY I2C_ISR_BUSY

Definition at line 404 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_FLAG_DIR I2C_ISR_DIR

Definition at line 405 of file stm32g0xx_hal_smbus.h.

#define SMBUS_FLAG_OVR I2C_ISR_OVR

Definition at line 400 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_PECERR I2C_ISR_PECERR

Definition at line 401 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_RXNE I2C_ISR_RXNE

Definition at line 392 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_STOPF I2C_ISR_STOPF

Definition at line 395 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TC I2C_ISR_TC

Definition at line 396 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), and SMBUS_Master_ISR().

#define SMBUS_FLAG_TCR I2C_ISR_TCR

Definition at line 397 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 402 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_TXE I2C_ISR_TXE

Definition at line 390 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Flush_TXDR().

#define SMBUS_FLAG_TXIS I2C_ISR_TXIS

Definition at line 391 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Flush_TXDR(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Exported Macros

Defines
SMBUS Exported Macros
SMBUS

Defines

#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Define Documentation

#define __HAL_SMBUS_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == SMBUS_FLAG_TXE) ? \
                                                       ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
                                                       ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • SMBUS_FLAG_TXE Transmit data register empty
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 527 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Flush_TXDR(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 541 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 463 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 535 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_Init(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableWakeUp(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 447 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Enable_IRQ().

#define __HAL_SMBUS_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 547 of file stm32g0xx_hal_smbus.h.

#define __HAL_SMBUS_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
    ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

Definition at line 506 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), SMBUS_Flush_TXDR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define __HAL_SMBUS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SMBUS interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the SMBUS interrupt source to check. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 479 of file stm32g0xx_hal_smbus.h.

#define __HAL_SMBUS_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                               \
                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
                                                                 (__HANDLE__)->MspInitCallback = NULL;            \
                                                                 (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                               } while(0)

Reset SMBUS handle state.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 424 of file stm32g0xx_hal_smbus.h.

#define SMBUS_FLAG_MASK (0x0001FFFFU)

Check whether the specified SMBUS flag is set or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMBUS_FLAG_TXE Transmit data register empty
  • SMBUS_FLAG_TXIS Transmit interrupt status
  • SMBUS_FLAG_RXNE Receive data register not empty
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_TC Transfer complete (master mode)
  • SMBUS_FLAG_TCR Transfer complete reload
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
  • SMBUS_FLAG_BUSY Bus busy
  • SMBUS_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 505 of file stm32g0xx_hal_smbus.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Private Macros

Defines
SMBUS Private Macros
SMBUS

Defines

#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__)
#define | SMBUS_RESET_CR2(__HANDLE__)
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__)
#define | SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Define Documentation

#define IS_SMBUS_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
                                                         ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))

Definition at line 566 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
                                                         ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))

Definition at line 561 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), and HAL_SMBUS_Init().

#define IS_SMBUS_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 564 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigDigitalFilter().

#define IS_SMBUS_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
                                                         ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))

Definition at line 569 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_GENERAL_CALL ( CALL )
Value:
(((CALL) == SMBUS_GENERALCALL_DISABLE) || \
                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))

Definition at line 581 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))

Definition at line 584 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 651 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 652 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == SMBUS_OA2_NOMASK)    || \
                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
                                                         ((MASK) == SMBUS_OA2_MASK07))

Definition at line 572 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PEC ( PEC )
Value:
(((PEC) == SMBUS_PEC_DISABLE) || \
                                                         ((PEC) == SMBUS_PEC_ENABLE))

Definition at line 587 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PERIPHERAL_MODE ( MODE )
Value:
(((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))

Definition at line 590 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SMBUS_RELOAD_MODE)                          || \
                                                      ((MODE) == SMBUS_AUTOEND_MODE)                         || \
                                                      ((MODE) == SMBUS_SOFTEND_MODE)                         || \
                                                      ((MODE) == SMBUS_SENDPEC_MODE)                         || \
                                                      ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
                                                                  SMBUS_RELOAD_MODE )))

Definition at line 594 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
                                                      ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
                                                      ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
                                                      ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
                                                      ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
                                                      ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))

Definition at line 611 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))

Definition at line 620 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), and HAL_SMBUS_Master_Transmit_IT().

#define IS_SMBUS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_GENERATE_STOP)              || \
                                                         ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
                                                         ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
                                                         ((REQUEST) == SMBUS_NO_STARTSTOP))

Definition at line 605 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define SMBUS_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) |
Value:
((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
                                                          ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

Definition at line 647 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_CHECK_IT_SOURCE | ( | __CR1__,
 |  | __IT__
 | ) | ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 649 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
                                                                       (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
                                                                      (~I2C_CR2_RD_WRN)) : \
                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & \
                                                                        (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
                                                                       (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 633 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)

Definition at line 641 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ALERT_ENABLED ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)

Definition at line 645 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ().

#define SMBUS_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

Definition at line 642 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_PEC_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)

Definition at line 644 of file stm32g0xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 643 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR().

#define SMBUS_RESET_CR1 ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR1 &= \
                                                        (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
                                                                               I2C_CR1_PECEN)))

Definition at line 625 of file stm32g0xx_hal_smbus.h.

#define SMBUS_RESET_CR2 ( __HANDLE__ )
Value:
((__HANDLE__)->Instance->CR2 &= \
                                                        (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
                                                                               I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
                                                                               I2C_CR2_RD_WRN)))

Definition at line 628 of file stm32g0xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WakeUp Mode Functions

Functions
WakeUp Mode Functions
SMBUS Extended Exported Functions

WakeUp Mode Functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUSEx_EnableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Enable SMBUS wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_SMBUSEx_DisableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Disable SMBUS wakeup from Stop mode(s).

Detailed Description

WakeUp Mode Functions.

 ===============================================================================
                      ##### WakeUp Mode Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Wake Up Feature

Function Documentation

HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp ( SMBUS_HandleTypeDef * hsmbus )

Disable SMBUS wakeup from Stop mode(s).

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 127 of file stm32g0xx_hal_smbus_ex.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp ( SMBUS_HandleTypeDef * hsmbus )

Enable SMBUS wakeup from Stop mode(s).

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 88 of file stm32g0xx_hal_smbus_ex.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, and __SMBUS_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Fast Mode Plus Functions

Functions
Fast Mode Plus Functions
SMBUS Extended Exported Functions

Fast Mode Plus Functions. More...

Functions

void | HAL_SMBUSEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the SMBUS fast mode plus driving capability.
void | HAL_SMBUSEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the SMBUS fast mode plus driving capability.

Detailed Description

Fast Mode Plus Functions.

 ===============================================================================
                      ##### Fast Mode Plus Functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Fast Mode Plus

Function Documentation

void HAL_SMBUSEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the SMBUS fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the SMBUS Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be disabled on all selected I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be disabled only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be disabled only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 219 of file stm32g0xx_hal_smbus_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_SMBUS_FASTMODEPLUS.

void HAL_SMBUSEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the SMBUS fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the SMBUS Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be enabled on all selected I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be enabled only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be enabled only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 192 of file stm32g0xx_hal_smbus_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_SMBUS_FASTMODEPLUS.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Extended Fast Mode Plus

Defines
SMBUS Extended Fast Mode Plus
SMBUS Extended Exported Constants

Defines

#define | SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | SMBUS_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP
#define | SMBUS_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP
#define | SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 54 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 55 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 57 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP

Enable Fast Mode Plus on PA10

Definition at line 49 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP

Enable Fast Mode Plus on PA9

Definition at line 48 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 50 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 51 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 52 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 53 of file stm32g0xx_hal_smbus_ex.h.

#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U

Fast Mode Plus not supported

Definition at line 47 of file stm32g0xx_hal_smbus_ex.h.

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STM32G0C1xx HAL User Manual: SMBUS Extended Exported Macros

SMBUS Extended Exported Macros
SMBUSEx
Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Extended Private Constants

SMBUS Extended Private Constants
SMBUSEx
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STM32G0C1xx HAL User Manual: SMBUS Extended Private Macros

Defines
SMBUS Extended Private Macros
SMBUSEx

Defines

#define IS_SMBUS_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_SMBUS_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
                                           ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA9))  == SMBUS_FASTMODEPLUS_PA9)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA10)) == SMBUS_FASTMODEPLUS_PA10) || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6))  == SMBUS_FASTMODEPLUS_PB6)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7))  == SMBUS_FASTMODEPLUS_PB7)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8))  == SMBUS_FASTMODEPLUS_PB8)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9))  == SMBUS_FASTMODEPLUS_PB9)  || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
                                            (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3)))

Definition at line 119 of file stm32g0xx_hal_smbus_ex.h.

Referenced by HAL_SMBUSEx_DisableFastModePlus(), and HAL_SMBUSEx_EnableFastModePlus().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Extended Private Functions

SMBUS Extended Private Functions
SMBUSEx
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STM32G0C1xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 100U

Define Documentation

#define SPI_DEFAULT_TIMEOUT 100U

Definition at line 217 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.

Detailed Description

Private functions.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3594 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_16BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3628 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), and SPI_IT_RXNE.

Referenced by SPI_2linesRxISR_16BIT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3462 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_8BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_ERR, SPI_IT_RXNE, SPI_RXFIFO_THRESHOLD, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3513 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by SPI_2linesRxISR_8BIT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3650 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3547 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_AbortRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Rx transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4259 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_AbortTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Tx or Rx/Tx transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4303 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4153 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::RxCpltCallback, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), and SPI_RxISR_8BITCRC().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RXTX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4076 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::RxCpltCallback, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxRxCpltCallback.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the TX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4210 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, SPI_IT_TXE, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxCpltCallback.

Referenced by SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3309 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCallback, HAL_SPI_ErrorCallback(), __SPI_HandleTypeDef::RxXferCount, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_IRQHandler().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3286 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3250 of file stm32g0xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback(), and __SPI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3232 of file stm32g0xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback(), and __SPI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3268 of file stm32g0xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback(), and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3015 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_IT_ERR, SPI_MODE_MASTER, SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3397 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2958 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3132 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_8BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_FRLVL_QUARTER_FULL, SPI_IT_ERR, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3331 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static HAL_StatusTypeDef SPI_EndRxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RX transaction complete.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 4008 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_MODE_MASTER, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Receive(), SPI_CloseRx_ISR(), and SPI_DMAReceiveCplt().

static HAL_StatusTypeDef SPI_EndRxTxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RXTX or TX transaction complete.

Parameters:
hspi | SPI handle
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 4044 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FLAG_FTLVL, SPI_FRLVL_EMPTY, SPI_FTLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Abort(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_AbortTx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3771 of file stm32g0xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_16BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3749 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRx_ISR(), SPI_IT_ERR, and SPI_IT_RXNE.

Referenced by SPI_RxISR_16BIT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3715 of file stm32g0xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_8BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 8-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3688 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, and SPI_CloseRx_ISR().

Referenced by SPI_RxISR_8BIT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3829 of file stm32g0xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3804 of file stm32g0xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Fifo,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI FIFO Communication Timeout.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Fifo | Fifo to check
State | Fifo state to check
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3928 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, __SPI_HandleTypeDef::State, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag | SPI flag to check
State | flag state to check
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3859 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled
        (++) CRC Length, used only with Data8 and Data16
        (++) FIFO reception threshold

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI peripheral.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 489 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::MspDeInitCallback, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 314 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FirstBit, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_MspInit(), HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_LENGTH, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_NSSP, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::MspInitCallback, SPI_InitTypeDef::NSS, SPI_InitTypeDef::NSSPMode, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, SPI_BAUDRATEPRESCALER_2, SPI_CRC_LENGTH_16BIT, SPI_CRC_LENGTH_8BIT, SPI_CRC_LENGTH_DATASIZE, SPI_CRCCALCULATION_DISABLE, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_MODE_MASTER, SPI_PHASE_1EDGE, SPI_POLARITY_LOW, SPI_RXFIFO_THRESHOLD_HF, SPI_RXFIFO_THRESHOLD_QF, SPI_TIMODE_DISABLE, __SPI_HandleTypeDef::State, SPI_InitTypeDef::TIMode, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI MSP.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 549 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_DeInit(), and HAL_SPI_UnRegisterCallback().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 533 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Init(), and HAL_SPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SPI_RegisterCallback | ( | SPI_HandleTypeDef * | hspi,
 |  | HAL_SPI_CallbackIDTypeDef | CallbackID,
 |  | pSPI_CallbackTypeDef | pCallback
 | ) |  |

Register a User SPI Callback To be used instead of the weak predefined callback.

Parameters:
hspi | Pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI.
CallbackID | ID of the callback to be registered
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 569 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ABORT_CB_ID, HAL_SPI_ERROR_CB_ID, HAL_SPI_ERROR_INVALID_CALLBACK, HAL_SPI_MSPDEINIT_CB_ID, HAL_SPI_MSPINIT_CB_ID, HAL_SPI_RX_COMPLETE_CB_ID, HAL_SPI_RX_HALF_COMPLETE_CB_ID, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TX_COMPLETE_CB_ID, HAL_SPI_TX_HALF_COMPLETE_CB_ID, HAL_SPI_TX_RX_COMPLETE_CB_ID, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID, __SPI_HandleTypeDef::MspDeInitCallback, __SPI_HandleTypeDef::MspInitCallback, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_UnRegisterCallback | ( | SPI_HandleTypeDef * | hspi,
 |  | HAL_SPI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.

Parameters:
hspi | Pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI.
CallbackID | ID of the callback to be unregistered
Return values:
HAL status

Definition at line 680 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ABORT_CB_ID, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_CB_ID, HAL_SPI_ERROR_INVALID_CALLBACK, HAL_SPI_ErrorCallback(), HAL_SPI_MspDeInit(), HAL_SPI_MSPDEINIT_CB_ID, HAL_SPI_MspInit(), HAL_SPI_MSPINIT_CB_ID, HAL_SPI_RX_COMPLETE_CB_ID, HAL_SPI_RX_HALF_COMPLETE_CB_ID, HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TX_COMPLETE_CB_ID, HAL_SPI_TX_HALF_COMPLETE_CB_ID, HAL_SPI_TX_RX_COMPLETE_CB_ID, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID, HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), __SPI_HandleTypeDef::MspDeInitCallback, __SPI_HandleTypeDef::MspInitCallback, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or Receive process
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_Abort ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (blocking mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 2264 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Abort_IT ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (Interrupt mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2424 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SPI_AbortCpltCallback ( SPI_HandleTypeDef * hspi )

SPI Abort Complete callback.

Parameters:
hspi SPI handle.
Return values:
None

Definition at line 2886 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Abort_IT(), HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2585 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2605 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2625 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_SPI_ERROR_DMA, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2868 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 2665 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_OVR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_CHECK_FLAG, SPI_CHECK_IT_SOURCE, SPI_DMAAbortOnError(), SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 986 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Note:
In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Parameters:
Size amount of data to be sent
Return values:
HAL status

Definition at line 1927 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_IT_ERR, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1586 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2788 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2836 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 821 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_TXE, SPI_MODE_SLAVE, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1802 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_IT_ERR, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1501 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_IT_ERR, SPI_IT_TXE, SPI_RESET_CRC, SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Size | amount of data to be sent and received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1226 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_MODE_MASTER, SPI_MODE_SLAVE, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size amount of data to be sent
Return values:
HAL status

Definition at line 2072 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_IT_ERR, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Size | amount of data to be sent and received
Return values:
HAL status

Definition at line 1693 of file stm32g0xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2772 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2820 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2804 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2852 of file stm32g0xx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitReceiveCplt().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 2933 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 2921 of file stm32g0xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.
typedef void(* | pSPI_CallbackTypeDef )(SPI_HandleTypeDef *hspi)
HAL SPI Callback pointer definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...
enum HAL_SPI_CallbackIDTypeDef {
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U,
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, HAL_SPI_ERROR_CB_ID = 0x06U, HAL_SPI_ABORT_CB_ID = 0x07U,
HAL_SPI_MSPINIT_CB_ID = 0x08U, HAL_SPI_MSPDEINIT_CB_ID = 0x09U
}
HAL SPI Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi)

HAL SPI Callback pointer definition.

pointer to an SPI callback function

Definition at line 186 of file stm32g0xx_hal_spi.h.

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_CallbackIDTypeDef

HAL SPI Callback ID enumeration definition.

Enumerator:
HAL_SPI_TX_COMPLETE_CB_ID

SPI Tx Completed callback ID

HAL_SPI_RX_COMPLETE_CB_ID

SPI Rx Completed callback ID

HAL_SPI_TX_RX_COMPLETE_CB_ID

SPI TxRx Completed callback ID

HAL_SPI_TX_HALF_COMPLETE_CB_ID

SPI Tx Half Completed callback ID

HAL_SPI_RX_HALF_COMPLETE_CB_ID

SPI Rx Half Completed callback ID

HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID

SPI TxRx Half Completed callback ID

HAL_SPI_ERROR_CB_ID

SPI Error callback ID

HAL_SPI_ABORT_CB_ID

SPI Abort callback ID

HAL_SPI_MSPINIT_CB_ID

SPI Msp Init callback ID

HAL_SPI_MSPDEINIT_CB_ID

SPI Msp DeInit callback ID

Definition at line 168 of file stm32g0xx_hal_spi.h.

enum HAL_SPI_StateTypeDef

HAL SPI State structure definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

HAL_SPI_STATE_ABORT

SPI abort is ongoing

Definition at line 100 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32g0xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial
uint32_t | CRCLength
uint32_t | NSSPMode

Detailed Description

SPI Configuration Structure definition.

Definition at line 46 of file stm32g0xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 67 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 60 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 57 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 79 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of SPI CRC Length

Definition at line 85 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535

Definition at line 82 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 54 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 51 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 73 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 48 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 63 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored)..

Definition at line 89 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 76 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_spi.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32g0xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint32_t | CRCSize
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | RxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxRxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | RxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxRxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | ErrorCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | AbortCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | MspInitCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | MspDeInitCallback )(struct __SPI_HandleTypeDef *hspi)

Detailed Description

SPI handle Structure definition.

Definition at line 115 of file stm32g0xx_hal_spi.h.

Field Documentation

void(* __SPI_HandleTypeDef::AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Abort callback

Definition at line 157 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort_IT(), HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

uint32_t __SPI_HandleTypeDef::CRCSize

SPI CRC size used for the transfer

Definition at line 133 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BITCRC(), and SPI_RxISR_8BITCRC().

void(* __SPI_HandleTypeDef::ErrorCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Error callback

Definition at line 156 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

SPI Error code

Definition at line 147 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_RegisterCallback(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPI_UnRegisterCallback(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

SPI Rx DMA Handle parameters

Definition at line 141 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

SPI Tx DMA Handle parameters

Definition at line 139 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

SPI communication parameters

Definition at line 119 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

SPI registers base address

Definition at line 117 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_FlushRxFifo(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), SPI_RxISR_8BITCRC(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFifoStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Locking object

Definition at line 143 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

void(* __SPI_HandleTypeDef::MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Msp DeInit callback

Definition at line 159 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

void(* __SPI_HandleTypeDef::MspInitCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Msp Init callback

Definition at line 158 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Pointer to SPI Rx transfer Buffer

Definition at line 127 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Pointer to SPI Tx transfer Buffer

Definition at line 121 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Rx Completed callback

Definition at line 151 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void(* __SPI_HandleTypeDef::RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Rx Half Completed callback

Definition at line 154 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfReceiveCplt().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Rx ISR

Definition at line 135 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

__IO uint16_t __SPI_HandleTypeDef::RxXferCount

SPI Rx Transfer Counter

Definition at line 131 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

SPI Rx Transfer size

Definition at line 129 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

SPI communication state

Definition at line 145 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_RegisterCallback(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPI_UnRegisterCallback(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Tx Completed callback

Definition at line 150 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void(* __SPI_HandleTypeDef::TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Tx Half Completed callback

Definition at line 153 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitCplt().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Tx ISR

Definition at line 137 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

void(* __SPI_HandleTypeDef::TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI TxRx Completed callback

Definition at line 152 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void(* __SPI_HandleTypeDef::TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI TxRx Half Completed callback

Definition at line 155 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitReceiveCplt().

__IO uint16_t __SPI_HandleTypeDef::TxXferCount

SPI Tx Transfer Counter

Definition at line 125 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

SPI Tx Transfer size

Definition at line 123 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_spi.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Error Code

Defines
SPI Error Code
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)

Define Documentation

#define HAL_SPI_ERROR_ABORT (0x00000040U)

Error during SPI Abort procedure

Definition at line 208 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_CRC (0x00000002U)

CRC error

Definition at line 203 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 206 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), and SPI_DMAError().

#define HAL_SPI_ERROR_FLAG (0x00000020U)

Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag

Definition at line 207 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define HAL_SPI_ERROR_FRE (0x00000008U)

FRE error

Definition at line 205 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)

Invalid Callback error

Definition at line 210 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

#define HAL_SPI_ERROR_MODF (0x00000001U)

MODF error

Definition at line 202 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE (0x00000000U)

No error

Definition at line 201 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_OVR (0x00000004U)

OVR error

Definition at line 204 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Define Documentation

#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Definition at line 220 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE (0x00000000U)

Definition at line 219 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Definition at line 230 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES (0x00000000U)

Definition at line 228 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY

Definition at line 229 of file stm32g0xx_hal_spi.h.

Referenced by SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_4BIT (0x00000300U)
#define | SPI_DATASIZE_5BIT (0x00000400U)
#define | SPI_DATASIZE_6BIT (0x00000500U)
#define | SPI_DATASIZE_7BIT (0x00000600U)
#define | SPI_DATASIZE_8BIT (0x00000700U)
#define | SPI_DATASIZE_9BIT (0x00000800U)
#define | SPI_DATASIZE_10BIT (0x00000900U)
#define | SPI_DATASIZE_11BIT (0x00000A00U)
#define | SPI_DATASIZE_12BIT (0x00000B00U)
#define | SPI_DATASIZE_13BIT (0x00000C00U)
#define | SPI_DATASIZE_14BIT (0x00000D00U)
#define | SPI_DATASIZE_15BIT (0x00000E00U)
#define | SPI_DATASIZE_16BIT (0x00000F00U)

Define Documentation

#define SPI_DATASIZE_10BIT (0x00000900U)

Definition at line 244 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_11BIT (0x00000A00U)

Definition at line 245 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_12BIT (0x00000B00U)

Definition at line 246 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_13BIT (0x00000C00U)

Definition at line 247 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_14BIT (0x00000D00U)

Definition at line 248 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_15BIT (0x00000E00U)

Definition at line 249 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_16BIT (0x00000F00U)

Definition at line 250 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), and HAL_SPI_TransmitReceive().

#define SPI_DATASIZE_4BIT (0x00000300U)

Definition at line 238 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_5BIT (0x00000400U)

Definition at line 239 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_6BIT (0x00000500U)

Definition at line 240 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_7BIT (0x00000600U)

Definition at line 241 of file stm32g0xx_hal_spi.h.

#define SPI_DATASIZE_8BIT (0x00000700U)

Definition at line 242 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_DATASIZE_9BIT (0x00000800U)

Definition at line 243 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CR1_CPOL

Definition at line 259 of file stm32g0xx_hal_spi.h.

#define SPI_POLARITY_LOW (0x00000000U)

Definition at line 258 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA

Define Documentation

#define SPI_PHASE_1EDGE (0x00000000U)

Definition at line 267 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_PHASE_2EDGE SPI_CR1_CPHA

Definition at line 268 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Slave Select Management

Defines
SPI Slave Select Management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)

Define Documentation

#define SPI_NSS_HARD_INPUT (0x00000000U)

Definition at line 277 of file stm32g0xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)

Definition at line 278 of file stm32g0xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CR1_SSM

Definition at line 276 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI NSS Pulse Mode

Defines
SPI NSS Pulse Mode
SPI Exported Constants

Defines

#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)

Define Documentation

#define SPI_NSS_PULSE_DISABLE (0x00000000U)

Definition at line 287 of file stm32g0xx_hal_spi.h.

#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP

Definition at line 286 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define | SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

Definition at line 301 of file stm32g0xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 298 of file stm32g0xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)

Definition at line 295 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 302 of file stm32g0xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)

Definition at line 299 of file stm32g0xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)

Definition at line 296 of file stm32g0xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

Definition at line 300 of file stm32g0xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)

Definition at line 297 of file stm32g0xx_hal_spi.h.

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STM32G0C1xx HAL User Manual: SPI MSB LSB Transmission

Defines
SPI MSB LSB Transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Definition at line 311 of file stm32g0xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB (0x00000000U)

Definition at line 310 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI TI Mode

Defines
SPI TI Mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF

Define Documentation

#define SPI_TIMODE_DISABLE (0x00000000U)

Definition at line 319 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_TIMODE_ENABLE SPI_CR2_FRF

Definition at line 320 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE (0x00000000U)

Definition at line 328 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Definition at line 329 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI CRC Length

Defines
SPI CRC Length
SPI Exported Constants

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit. More...

Defines

#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_8BIT (0x00000001U)
#define | SPI_CRC_LENGTH_16BIT (0x00000002U)

Detailed Description

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

Define Documentation

#define SPI_CRC_LENGTH_16BIT (0x00000002U)

Definition at line 343 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), and SPI_DMAReceiveCplt().

#define SPI_CRC_LENGTH_8BIT (0x00000001U)

Definition at line 342 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and SPI_DMATransmitReceiveCplt().

#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)

Definition at line 341 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI FIFO Reception Threshold

Defines
SPI FIFO Reception Threshold
SPI Exported Constants

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits). More...

Defines

#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF (0x00000000U)

Detailed Description

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits).

SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO level is greater or equal to 1/2(16 bits).

Define Documentation

#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH

Definition at line 356 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and SPI_2linesRxISR_8BIT().

#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)

Definition at line 358 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH

Definition at line 357 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Interrupt Definition

Defines
SPI Interrupt Definition
SPI Exported Constants

Defines

#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define SPI_IT_ERR SPI_CR2_ERRIE

Definition at line 368 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_CR2_RXNEIE

Definition at line 367 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_CR2_TXEIE

Definition at line 366 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Flags Definition

Defines
SPI Flags Definition
SPI Exported Constants

Defines

#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FLAG_MASK

Define Documentation

#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */

Definition at line 378 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */

Definition at line 379 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */

Definition at line 382 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Definition at line 384 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */

Definition at line 383 of file stm32g0xx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FLAG_MASK
Value:
(SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)

Definition at line 385 of file stm32g0xx_hal_spi.h.

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 380 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 381 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */

Definition at line 376 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), and SPI_DMAReceiveCplt().

#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */

Definition at line 377 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Transmission FIFO Status Level

Defines
SPI Transmission FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FTLVL_EMPTY (0x00000000U)
#define | SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define | SPI_FTLVL_HALF_FULL (0x00001000U)
#define | SPI_FTLVL_FULL (0x00001800U)

Define Documentation

#define SPI_FTLVL_EMPTY (0x00000000U)

Definition at line 394 of file stm32g0xx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FTLVL_FULL (0x00001800U)

Definition at line 397 of file stm32g0xx_hal_spi.h.

#define SPI_FTLVL_HALF_FULL (0x00001000U)

Definition at line 396 of file stm32g0xx_hal_spi.h.

#define SPI_FTLVL_QUARTER_FULL (0x00000800U)

Definition at line 395 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Reception FIFO Status Level

Defines
SPI Reception FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define | SPI_FRLVL_HALF_FULL (0x00000400U)
#define | SPI_FRLVL_FULL (0x00000600U)

Define Documentation

#define SPI_FRLVL_EMPTY (0x00000000U)

Definition at line 406 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), and SPI_WaitFifoStateUntilTimeout().

#define SPI_FRLVL_FULL (0x00000600U)

Definition at line 409 of file stm32g0xx_hal_spi.h.

#define SPI_FRLVL_HALF_FULL (0x00000400U)

Definition at line 408 of file stm32g0xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

#define SPI_FRLVL_QUARTER_FULL (0x00000200U)

Definition at line 407 of file stm32g0xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 498 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg_fre = 0x00U;              \
    tmpreg_fre = (__HANDLE__)->Instance->SR;       \
    UNUSED(tmpreg_fre);                            \
  }while(0U)

Clear the SPI FRE pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 531 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ )
Value:
do{                                                    \
    __IO uint32_t tmpreg_modf = 0x00U;                   \
    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
    UNUSED(tmpreg_modf);                                 \
  } while(0U)

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 505 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg_ovr = 0x00U;              \
    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
    UNUSED(tmpreg_ovr);                            \
  } while(0U)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 518 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), SPI_CloseTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Disable the SPI peripheral.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 550 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))

Disable the specified SPI interrupts.

Parameters:
__HANDLE__ specifies the SPI handle. This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 460 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 543 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))

Enable the specified SPI interrupts.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 448 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 491 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->CR2\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 472 of file stm32g0xx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset SPI handle state.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 429 of file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | SPI_CHECK_FLAG(__SR__, __FLAG__)
Check whether the specified SPI flag is set or not.
#define | SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)
Check whether the specified SPI Interrupt is set or not.
#define | IS_SPI_MODE(__MODE__)
Checks if SPI Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION(__MODE__)
Checks if SPI Direction Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
Checks if SPI Direction Mode parameter is 2 lines.
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__)
Checks if SPI Direction Mode parameter is 1 or 2 lines.
#define | IS_SPI_DATASIZE(__DATASIZE__)
Checks if SPI Data Size parameter is in allowed range.
#define | IS_SPI_CPOL(__CPOL__)
Checks if SPI Serial clock steady state parameter is in allowed range.
#define | IS_SPI_CPHA(__CPHA__)
Checks if SPI Clock Phase parameter is in allowed range.
#define | IS_SPI_NSS(__NSS__)
Checks if SPI Slave Select parameter is in allowed range.
#define | IS_SPI_NSSP(__NSSP__)
Checks if SPI NSS Pulse parameter is in allowed range.
#define | IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__)
Checks if SPI Baudrate prescaler parameter is in allowed range.
#define | IS_SPI_FIRST_BIT(__BIT__)
Checks if SPI MSB LSB transmission parameter is in allowed range.
#define | IS_SPI_TIMODE(__MODE__)
Checks if SPI TI mode parameter is in allowed range.
#define | IS_SPI_CRC_CALCULATION(__CALCULATION__)
Checks if SPI CRC calculation enabled state is in allowed range.
#define | IS_SPI_CRC_LENGTH(__LENGTH__)
Checks if SPI CRC length is in allowed range.
#define | IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__)
Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
#define | IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
Checks if DMA handle is valid.

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))

Checks if SPI Baudrate prescaler parameter is in allowed range.

Parameters:
__PRESCALER__ specifies the SPI Baudrate prescaler. This parameter can be a value of SPI BaudRate Prescaler
Return values:
None

Definition at line 700 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( __CPHA__ )
Value:
(((__CPHA__) == SPI_PHASE_1EDGE) || \
                                    ((__CPHA__) == SPI_PHASE_2EDGE))

Checks if SPI Clock Phase parameter is in allowed range.

Parameters:
__CPHA__ specifies the SPI Clock Phase. This parameter can be a value of SPI Clock Phase
Return values:
None

Definition at line 675 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( __CPOL__ )
Value:
(((__CPOL__) == SPI_POLARITY_LOW) || \
                                    ((__CPOL__) == SPI_POLARITY_HIGH))

Checks if SPI Serial clock steady state parameter is in allowed range.

Parameters:
__CPOL__ specifies the SPI serial clock steady state. This parameter can be a value of SPI Clock Polarity
Return values:
None

Definition at line 667 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( __CALCULATION__ )
Value:
(((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))

Checks if SPI CRC calculation enabled state is in allowed range.

Parameters:
__CALCULATION__ specifies the SPI CRC calculation enable state. This parameter can be a value of SPI CRC Calculation
Return values:
None

Definition at line 730 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
                                       ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)     || \
                                       ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))

Checks if SPI CRC length is in allowed range.

Parameters:
__LENGTH__ specifies the SPI CRC length. This parameter can be a value of SPI CRC Length
Return values:
None

Definition at line 738 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( __POLYNOMIAL__ )
Value:
(((__POLYNOMIAL__) >= 0x1U)    && \
                                               ((__POLYNOMIAL__) <= 0xFFFFU) && \
                                              (((__POLYNOMIAL__)&0x1U) != 0U))

Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.

Parameters:
__POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535
Return values:
None

Definition at line 747 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( __DATASIZE__ )
Value:
(((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_4BIT))

Checks if SPI Data Size parameter is in allowed range.

Parameters:
__DATASIZE__ specifies the SPI Data Size. This parameter can be a value of SPI Data Size
Return values:
None

Definition at line 648 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( __MODE__ )
Value:
(((__MODE__) == SPI_DIRECTION_2LINES)        || \
                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
                                    ((__MODE__) == SPI_DIRECTION_1LINE))

Checks if SPI Direction Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI Direction Mode. This parameter can be a value of SPI Direction Mode
Return values:
None

Definition at line 626 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( __MODE__ ) ((__MODE__) == SPI_DIRECTION_2LINES)

Checks if SPI Direction Mode parameter is 2 lines.

Parameters:
__MODE__ specifies the SPI Direction Mode.
Return values:
None

Definition at line 634 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE ( __MODE__ )
Value:
(((__MODE__) == SPI_DIRECTION_2LINES) || \
                                                    ((__MODE__) == SPI_DIRECTION_1LINE))

Checks if SPI Direction Mode parameter is 1 or 2 lines.

Parameters:
__MODE__ specifies the SPI Direction Mode.
Return values:
None

Definition at line 640 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_DMA_HANDLE ( __HANDLE__ ) ((__HANDLE__) != NULL)

Checks if DMA handle is valid.

Parameters:
__HANDLE__ specifies a DMA Handle.
Return values:
None

Definition at line 755 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define IS_SPI_FIRST_BIT ( __BIT__ )
Value:
(((__BIT__) == SPI_FIRSTBIT_MSB) || \
                                    ((__BIT__) == SPI_FIRSTBIT_LSB))

Checks if SPI MSB LSB transmission parameter is in allowed range.

Parameters:
__BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). This parameter can be a value of SPI MSB LSB Transmission
Return values:
None

Definition at line 714 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( __MODE__ )
Value:
(((__MODE__) == SPI_MODE_SLAVE)   || \
                                    ((__MODE__) == SPI_MODE_MASTER))

Checks if SPI Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI Mode. This parameter can be a value of SPI Mode
Return values:
None

Definition at line 618 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( __NSS__ )
Value:
(((__NSS__) == SPI_NSS_SOFT)       || \
                                    ((__NSS__) == SPI_NSS_HARD_INPUT) || \
                                    ((__NSS__) == SPI_NSS_HARD_OUTPUT))

Checks if SPI Slave Select parameter is in allowed range.

Parameters:
__NSS__ specifies the SPI Slave Select management parameter. This parameter can be a value of SPI Slave Select Management
Return values:
None

Definition at line 683 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSSP ( __NSSP__ )
Value:
(((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
                                    ((__NSSP__) == SPI_NSS_PULSE_DISABLE))

Checks if SPI NSS Pulse parameter is in allowed range.

Parameters:
__NSSP__ specifies the SPI NSS Pulse Mode parameter. This parameter can be a value of SPI NSS Pulse Mode
Return values:
None

Definition at line 692 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( __MODE__ )
Value:
(((__MODE__) == SPI_TIMODE_DISABLE) || \
                                    ((__MODE__) == SPI_TIMODE_ENABLE))

Checks if SPI TI mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI TI mode. This parameter can be a value of SPI TI Mode
Return values:
None

Definition at line 722 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_1LINE_RX ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)

Set the SPI receive-only mode.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 573 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 566 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_CHECK_FLAG | ( | __SR__,
 |  | __FLAG__
 | ) |
Value:
((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
                                          ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)

Check whether the specified SPI flag is set or not.

Parameters:
__SR__ copy of SPI SR register.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
SET or RESET.

Definition at line 598 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_CHECK_IT_SOURCE | ( | __CR2__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__CR2__) & (__INTERRUPT__)) == \
                                                     (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI Interrupt is set or not.

Parameters:
__CR2__ copy of SPI CR2 register.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
SET or RESET.

Definition at line 610 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_RESET_CRC ( __HANDLE__ )
Value:
do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)

Reset the CRC calculation of the SPI.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 580 of file stm32g0xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPIEx Private Constants

Defines
SPIEx Private Constants
SPIEx

Defines

#define SPI_FIFO_SIZE 4UL

Define Documentation

#define SPI_FIFO_SIZE 4UL

Definition at line 41 of file stm32g0xx_hal_spi_ex.c.

Referenced by HAL_SPIEx_FlushRxFifo().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPIEx Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of extended functions to manage the SPI
    data transfers.

    (#) Rx data flush function:
        (++) HAL_SPIEx_FlushRxFifo()

Function Documentation

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo ( SPI_HandleTypeDef * hspi )

Flush the RX fifo.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 79 of file stm32g0xx_hal_spi_ex.c.

References __SPI_HandleTypeDef::Instance, SPI_FIFO_SIZE, SPI_FLAG_FRLVL, and SPI_FRLVL_EMPTY.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Time Base functions

Functions
TIM Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Base peripheral.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 337 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_Base_MspDeInit(), HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CHANNEL_N_STATE_SET_ALL, and TIM_CHANNEL_STATE_SET_ALL.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 277 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, __TIM_HandleTypeDef::Base_MspInitCallback, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_Base_MspInit(), HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_N_STATE_SET_ALL, TIM_CHANNEL_STATE_SET_ALL, and TIM_ResetCallback().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Base MSP.

Parameters:
htim TIM Base handle
Return values:
None

Definition at line 395 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim TIM Base handle
Return values:
None

Definition at line 380 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_Base_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 411 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim | TIM Base handle
pData | The source Buffer address.
Length | The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 537 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 470 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 450 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 606 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 512 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, and TIM_IT_UPDATE.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Output Compare functions

Functions
TIM Output Compare functions
TIM Exported Functions

TIM Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

TIM Output Compare functions.

  ==============================================================================
                  ##### TIM Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the TIM Output Compare.
    (+) Stop the TIM Output Compare.
    (+) Start the TIM Output Compare and enable interrupt.
    (+) Stop the TIM Output Compare and disable interrupt.
    (+) Start the TIM Output Compare and enable DMA transfer.
    (+) Stop the TIM Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 721 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::State, TIM_CHANNEL_N_STATE_SET_ALL, and TIM_CHANNEL_STATE_SET_ALL.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 661 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::OC_MspInitCallback, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_N_STATE_SET_ALL, TIM_CHANNEL_STATE_SET_ALL, and TIM_ResetCallback().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Output Compare MSP.

Parameters:
htim TIM Output Compare handle
Return values:
None

Definition at line 779 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim TIM Output Compare handle
Return values:
None

Definition at line 764 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_OC_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 802 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1063 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 893 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 858 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1227 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 986 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM PWM functions

Functions
TIM PWM functions
TIM Exported Functions

TIM PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

TIM PWM functions.

  ==============================================================================
                          ##### TIM PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM PWM.
    (+) De-initialize the TIM PWM.
    (+) Start the TIM PWM.
    (+) Stop the TIM PWM.
    (+) Start the TIM PWM and enable interrupt.
    (+) Stop the TIM PWM and disable interrupt.
    (+) Start the TIM PWM and enable DMA transfer.
    (+) Stop the TIM PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM PWM handle
Return values:
HAL status

Definition at line 1390 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::State, TIM_CHANNEL_N_STATE_SET_ALL, and TIM_CHANNEL_STATE_SET_ALL.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
Parameters:
htim TIM PWM handle
Return values:
HAL status

Definition at line 1330 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_N_STATE_SET_ALL, TIM_CHANNEL_STATE_SET_ALL, and TIM_ResetCallback().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM PWM MSP.

Parameters:
htim TIM PWM handle
Return values:
None

Definition at line 1448 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim TIM PWM handle
Return values:
None

Definition at line 1433 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim TIM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1471 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim | TIM PWM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1732 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim TIM PWM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1562 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1527 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1895 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1655 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Input Capture functions

Functions
TIM Input Capture functions
TIM Exported Functions

TIM Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.

Detailed Description

TIM Input Capture functions.

  ==============================================================================
              ##### TIM Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the TIM Input Capture.
   (+) Stop the TIM Input Capture.
   (+) Start the TIM Input Capture and enable interrupt.
   (+) Stop the TIM Input Capture and disable interrupt.
   (+) Start the TIM Input Capture and enable DMA transfer.
   (+) Stop the TIM Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 2058 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CHANNEL_N_STATE_SET_ALL, and TIM_CHANNEL_STATE_SET_ALL.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 1998 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_N_STATE_SET_ALL, TIM_CHANNEL_STATE_SET_ALL, and TIM_ResetCallback().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Input Capture MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2116 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture MSP.

Parameters:
htim TIM Input Capture handle
Return values:
None

Definition at line 2101 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IC_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2137 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement in DMA mode.

Parameters:
htim | TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2383 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2219 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2189 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in DMA mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2542 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2311 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM One Pulse functions

Functions
TIM One Pulse functions
TIM Exported Functions

TIM One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

TIM One Pulse functions.

  ==============================================================================
                        ##### TIM One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the TIM One Pulse.
    (+) Stop the TIM One Pulse.
    (+) Start the TIM One Pulse and enable interrupt.
    (+) Stop the TIM One Pulse and disable interrupt.
    (+) Start the TIM One Pulse and enable DMA transfer.
    (+) Stop the TIM One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM One Pulse.

Parameters:
htim TIM One Pulse handle
Return values:
HAL status

Definition at line 2716 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
When the timer instance is initialized in One Pulse mode, timer channels 1 and channel 2 are reserved and cannot be used for other purpose.
Parameters:
htim TIM One Pulse handle
OnePulseMode Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
Return values:
HAL status

Definition at line 2647 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::OnePulse_MspInitCallback, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, and TIM_ResetCallback().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM One Pulse MSP.

Parameters:
htim TIM One Pulse handle
Return values:
None

Definition at line 2776 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim TIM One Pulse handle
Return values:
None

Definition at line 2761 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Note:
Though OutputChannel parameter is deprecated and ignored by the function it has been kept to avoid HAL_TIM API compatibility break.
The pulse output channel is determined when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim | TIM One Pulse handle
OutputChannel | See note above
Return values:
HAL status

Definition at line 2796 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Note:
Though OutputChannel parameter is deprecated and ignored by the function it has been kept to avoid HAL_TIM API compatibility break.
The pulse output channel is determined when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim | TIM One Pulse handle
OutputChannel | See note above
Return values:
HAL status

Definition at line 2896 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Note:
Though OutputChannel parameter is deprecated and ignored by the function it has been kept to avoid HAL_TIM API compatibility break.
The pulse output channel is determined when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim | TIM One Pulse handle
OutputChannel | See note above
Return values:
HAL status

Definition at line 2853 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Note:
Though OutputChannel parameter is deprecated and ignored by the function it has been kept to avoid HAL_TIM API compatibility break.
The pulse output channel is determined when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim | TIM One Pulse handle
OutputChannel | See note above
Return values:
HAL status

Definition at line 2959 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Encoder functions

Functions
TIM Encoder functions
TIM Exported Functions

TIM Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

TIM Encoder functions.

  ==============================================================================
                          ##### TIM Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the TIM Encoder.
    (+) Stop the TIM Encoder.
    (+) Start the TIM Encoder and enable interrupt.
    (+) Stop the TIM Encoder and disable interrupt.
    (+) Start the TIM Encoder and enable DMA transfer.
    (+) Stop the TIM Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Encoder interface.

Parameters:
htim TIM Encoder Interface handle
Return values:
HAL status

Definition at line 3153 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and initialize the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
Encoder mode and External clock mode 2 are not compatible and must not be selected together Ex: A call for HAL_TIM_Encoder_Init will erase the settings of HAL_TIM_ConfigClockSource using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
When the timer instance is initialized in Encoder mode, timer channels 1 and channel 2 are reserved and cannot be used for other purpose.
Parameters:
htim | TIM Encoder Interface handle
sConfig | TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 3038 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, __TIM_HandleTypeDef::Encoder_MspInitCallback, TIM_Encoder_InitTypeDef::EncoderMode, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_ENCODER_MODE, IS_TIM_ENCODERINPUT_POLARITY, IS_TIM_IC_FILTER, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_Base_InitTypeDef::Period, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, and TIM_ResetCallback().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Encoder Interface MSP.

Parameters:
htim TIM Encoder Interface handle
Return values:
None

Definition at line 3213 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim TIM Encoder Interface handle
Return values:
None

Definition at line 3198 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3233 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim | TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1 | The destination Buffer address for IC1.
pData2 | The destination Buffer address for IC2.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 3552 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3387 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3327 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3765 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, and TIM_DMA_ID_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3487 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

TIM IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

TIM IRQ handler management.

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3842 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_CLEAR_FLAG, __HAL_TIM_CLEAR_IT, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::Channel, __TIM_HandleTypeDef::CommutationCallback, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, TIM_FLAG_BREAK, TIM_FLAG_BREAK2, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, TIM_IT_UPDATE, and __TIM_HandleTypeDef::TriggerCallback.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Peripheral Control functions

Functions
TIM Peripheral Control functions
TIM Exported Functions

TIM Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (const TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

TIM Peripheral Control functions.

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim | TIM handle
sClockSourceConfig | pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 5475 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, __TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim | TIM handle
sClearInputConfig | pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5
  • TIM_CHANNEL_6: TIM Channel 6
Return values:
HAL status

Definition at line 5291 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_CLEARINPUTPRESCALER_DIV1, TIM_CLEARINPUTSOURCE_COMP1, TIM_CLEARINPUTSOURCE_COMP2, TIM_CLEARINPUTSOURCE_COMP3, TIM_CLEARINPUTSOURCE_ETR, TIM_CLEARINPUTSOURCE_NONE, TIM_ETR_SetConfig(), and TIMx_OR1_OCREF_CLR.

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim TIM handle.
TI1_Selection Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 5629 of file stm32g0xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength,
 |  | uint32_t | DataLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_OR1
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_TISEL
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
DataLength | Data length. This parameter can be one value between 1 and 0xFFFF.
Return values:
HAL status

Definition at line 4984 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_BUSY, HAL_DMA_BURST_STATE_READY, HAL_DMA_Start_IT(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_DATA_LENGTH, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_ReadStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | const uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength,
 |  | uint32_t | DataLength
 | ) |  |

Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_OR1
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_TISEL
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
DataLength | Data length. This parameter can be one value between 1 and 0xFFFF.
Return values:
HAL status

Definition at line 4634 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_BUSY, HAL_DMA_BURST_STATE_READY, HAL_DMA_Start_IT(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_DATA_LENGTH, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_WriteStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_OR1
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_TISEL
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Note:
This function should be used only when BurstLength is equal to DMA data transfer length.
Return values:
HAL status

Definition at line 4926 of file stm32g0xx_hal_tim.c.

References HAL_TIM_DMABurst_MultiReadStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 5168 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_Abort_IT(), HAL_DMA_BURST_STATE_READY, __TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | const uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_OR1
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
  • TIM_DMABASE_TISEL
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Note:
This function should be used only when BurstLength is equal to DMA data transfer length.
Return values:
HAL status

Definition at line 4575 of file stm32g0xx_hal_tim.c.

References HAL_TIM_DMABurst_MultiWriteStart().

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 4818 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_Abort_IT(), HAL_DMA_BURST_STATE_READY, __TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim TIM handle
EventSource specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
  • TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
Note:
Basic timers can only generate an update event.
TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant only for timer instances supporting break input(s).
Return values:
HAL status

Definition at line 5252 of file stm32g0xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim | TIM IC handle
sConfig | TIM Input Capture configuration structure
Channel TIM Channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 4171 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, __TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM Output Compare handle
sConfig | TIM Output Compare configuration structure
Channel TIM Channels to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 4072 of file stm32g0xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim | TIM One Pulse handle
sConfig | TIM One Pulse configuration structure
OutputChannel TIM output channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel TIM input Channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Note:
To output a waveform with a minimum delay user can enable the fast mode by calling the __HAL_TIM_ENABLE_OCxFAST macro. Then CCx output is forced in response to the edge detection on TIx input, without taking in account the comparison.
Return values:
HAL status

Definition at line 4420 of file stm32g0xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, __TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM PWM handle
sConfig | TIM PWM configuration structure
Channel TIM Channels to be configured This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 4272 of file stm32g0xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | const TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim TIM handle.
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 5744 of file stm32g0xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 5661 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, __TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 5701 of file stm32g0xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, __TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) TIM Period elapsed callback
   (+) TIM Output Compare callback
   (+) TIM Input capture callback
   (+) TIM Trigger callback
   (+) TIM Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5963 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_ResetCallback().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non-blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 5873 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureCplt(), and TIM_ResetCallback().

void HAL_TIM_IC_CaptureHalfCpltCallback ( TIM_HandleTypeDef * htim )

Input Capture half complete callback in non-blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 5888 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMACaptureHalfCplt(), and TIM_ResetCallback().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non-blocking mode.

Parameters:
htim TIM OC handle
Return values:
None

Definition at line 5858 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5828 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedCplt(), and TIM_ResetCallback().

void HAL_TIM_PeriodElapsedHalfCpltCallback ( TIM_HandleTypeDef * htim )

Period elapsed half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5843 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedHalfCplt(), and TIM_ResetCallback().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5903 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), and TIM_ResetCallback().

void HAL_TIM_PWM_PulseFinishedHalfCpltCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5918 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseHalfCplt(), and TIM_ResetCallback().

HAL_StatusTypeDef HAL_TIM_RegisterCallback | ( | TIM_HandleTypeDef * | htim,
 |  | HAL_TIM_CallbackIDTypeDef | CallbackID,
 |  | pTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User TIM callback to be used instead of the weak predefined callback.

Parameters:
htim | tim handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  • HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  • HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  • HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  • HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  • HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  • HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  • HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  • HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  • HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  • HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  • HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  • HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  • HAL_TIM_ERROR_CB_ID Error Callback ID
  • HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  • HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  • HAL_TIM_BREAK_CB_ID Break Callback ID
  • HAL_TIM_BREAK2_CB_ID Break2 Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 6010 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::Base_MspInitCallback, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, __TIM_HandleTypeDef::Encoder_MspInitCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_BASE_MSPDEINIT_CB_ID, HAL_TIM_BASE_MSPINIT_CB_ID, HAL_TIM_BREAK2_CB_ID, HAL_TIM_BREAK_CB_ID, HAL_TIM_COMMUTATION_CB_ID, HAL_TIM_COMMUTATION_HALF_CB_ID, HAL_TIM_ENCODER_MSPDEINIT_CB_ID, HAL_TIM_ENCODER_MSPINIT_CB_ID, HAL_TIM_ERROR_CB_ID, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID, HAL_TIM_IC_CAPTURE_CB_ID, HAL_TIM_IC_CAPTURE_HALF_CB_ID, HAL_TIM_IC_MSPDEINIT_CB_ID, HAL_TIM_IC_MSPINIT_CB_ID, HAL_TIM_OC_DELAY_ELAPSED_CB_ID, HAL_TIM_OC_MSPDEINIT_CB_ID, HAL_TIM_OC_MSPINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID, HAL_TIM_PERIOD_ELAPSED_CB_ID, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID, HAL_TIM_PWM_MSPDEINIT_CB_ID, HAL_TIM_PWM_MSPINIT_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIM_TRIGGER_CB_ID, HAL_TIM_TRIGGER_HALF_CB_ID, __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::HallSensor_MspInitCallback, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5933 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerCplt(), and TIM_ResetCallback().

void HAL_TIM_TriggerHalfCpltCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5948 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMATriggerHalfCplt(), and TIM_ResetCallback().

HAL_StatusTypeDef HAL_TIM_UnRegisterCallback | ( | TIM_HandleTypeDef * | htim,
 |  | HAL_TIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a TIM callback TIM callback is redirected to the weak predefined callback.

Parameters:
htim tim handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  • HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  • HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  • HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  • HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  • HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  • HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  • HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  • HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  • HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  • HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  • HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  • HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  • HAL_TIM_ERROR_CB_ID Error Callback ID
  • HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  • HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  • HAL_TIM_BREAK_CB_ID Break Callback ID
  • HAL_TIM_BREAK2_CB_ID Break2 Callback ID
Return values:
status

Definition at line 6258 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::Base_MspInitCallback, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, __TIM_HandleTypeDef::Encoder_MspInitCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_Base_MspDeInit(), HAL_TIM_BASE_MSPDEINIT_CB_ID, HAL_TIM_Base_MspInit(), HAL_TIM_BASE_MSPINIT_CB_ID, HAL_TIM_BREAK2_CB_ID, HAL_TIM_BREAK_CB_ID, HAL_TIM_COMMUTATION_CB_ID, HAL_TIM_COMMUTATION_HALF_CB_ID, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_ENCODER_MSPDEINIT_CB_ID, HAL_TIM_Encoder_MspInit(), HAL_TIM_ENCODER_MSPINIT_CB_ID, HAL_TIM_ERROR_CB_ID, HAL_TIM_ErrorCallback(), HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID, HAL_TIM_IC_CAPTURE_CB_ID, HAL_TIM_IC_CAPTURE_HALF_CB_ID, HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_IC_MspDeInit(), HAL_TIM_IC_MSPDEINIT_CB_ID, HAL_TIM_IC_MspInit(), HAL_TIM_IC_MSPINIT_CB_ID, HAL_TIM_OC_DELAY_ELAPSED_CB_ID, HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_OC_MspDeInit(), HAL_TIM_OC_MSPDEINIT_CB_ID, HAL_TIM_OC_MspInit(), HAL_TIM_OC_MSPINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_OnePulse_MspInit(), HAL_TIM_PERIOD_ELAPSED_CB_ID, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID, HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_MspDeInit(), HAL_TIM_PWM_MSPDEINIT_CB_ID, HAL_TIM_PWM_MspInit(), HAL_TIM_PWM_MSPINIT_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIM_TRIGGER_CB_ID, HAL_TIM_TRIGGER_HALF_CB_ID, HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), HAL_TIMEx_HallSensor_MspDeInit(), HAL_TIMEx_HallSensor_MspInit(), __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::HallSensor_MspInitCallback, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Peripheral State functions

Functions
TIM Peripheral State functions
TIM Exported Functions

TIM Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (const TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (const TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ActiveChannel | HAL_TIM_GetActiveChannel (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIM_GetChannelState (const TIM_HandleTypeDef *htim, uint32_t Channel)
Return actual state of the TIM channel.
HAL_TIM_DMABurstStateTypeDef | HAL_TIM_DMABurstState (const TIM_HandleTypeDef *htim)
Return actual state of a DMA burst operation.

Detailed Description

TIM Peripheral State functions.

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM Base handle state.

Parameters:
htim TIM Base handle
Return values:
HAL state

Definition at line 6532 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState ( const TIM_HandleTypeDef * htim )

Return actual state of a DMA burst operation.

Parameters:
htim TIM handle
Return values:
DMA burst state

Definition at line 6627 of file stm32g0xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::DMABurstState, and __TIM_HandleTypeDef::Instance.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode handle state.

Parameters:
htim TIM Encoder Interface handle
Return values:
HAL state

Definition at line 6582 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel ( const TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode handle state.

Parameters:
htim TIM handle
Return values:
Active channel

Definition at line 6592 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel.

HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState | ( | const TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Return actual state of the TIM channel.

Parameters:
htim TIM handle
Channel TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5
  • TIM_CHANNEL_6: TIM Channel 6
Return values:
TIM Channel state

Definition at line 6610 of file stm32g0xx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, and TIM_CHANNEL_STATE_GET.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM Input Capture handle state.

Parameters:
htim TIM IC handle
Return values:
HAL state

Definition at line 6562 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM OC handle state.

Parameters:
htim TIM Output Compare handle
Return values:
HAL state

Definition at line 6542 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode handle state.

Parameters:
htim TIM OPM handle
Return values:
HAL state

Definition at line 6572 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM PWM handle state.

Parameters:
htim TIM handle
Return values:
HAL state

Definition at line 6552 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse half complete callback.
static void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger half complete callback.
static HAL_StatusTypeDef | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Slave Timer configuration function.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx | TIM peripheral
Structure | TIM Base configuration structure
Return values:
None

Definition at line 6970 of file stm32g0xx_hal_tim.c.

References TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
ChannelState | specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
Return values:
None

Definition at line 7870 of file stm32g0xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), and HAL_TIMEx_OnePulseN_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6793 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, DMA_NORMAL, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_IC_CaptureCallback(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::IC_CaptureCallback, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMACaptureHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6856 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureHalfCpltCallback(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

static void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Delay Pulse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6695 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, DMA_NORMAL, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_PWM_PulseFinishedCallback(), __TIM_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_OC_Start_DMA(), and HAL_TIM_PWM_Start_DMA().

void TIM_DMADelayPulseHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6754 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6652 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6895 of file stm32g0xx_hal_tim.c.

References DMA_NORMAL, HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::State, and TIM_DMA_ID_UPDATE.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMAPeriodElapsedHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6916 of file stm32g0xx_hal_tim.c.

References HAL_TIM_PeriodElapsedHalfCpltCallback(), and __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6932 of file stm32g0xx_hal_tim.c.

References DMA_NORMAL, HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), __TIM_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __TIM_HandleTypeDef::State, TIM_DMA_ID_TRIGGER, and __TIM_HandleTypeDef::TriggerCallback.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

static void TIM_DMATriggerHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 6953 of file stm32g0xx_hal_tim.c.

References HAL_TIM_TriggerHalfCpltCallback(), and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx | to select the TIM peripheral
TIM_ExtTRGPrescaler The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
ExtTRGFilter | External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 7838 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | InputTriggerSource
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
InputTriggerSource The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 7808 of file stm32g0xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

static void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 1 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7018 of file stm32g0xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Timer Output Compare 2 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7093 of file stm32g0xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 3 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7169 of file stm32g0xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 4 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7243 of file stm32g0xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC5_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 5 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7303 of file stm32g0xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC6_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | const TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 6 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The output configuration structure
Return values:
None

Definition at line 7356 of file stm32g0xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_ResetCallback ( TIM_HandleTypeDef * htim )

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
htim pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 7894 of file stm32g0xx_hal_tim.c.

References __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ErrorCallback(), HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Slave Timer configuration function.

Parameters:
htim | TIM handle
sSlaveConfig | Slave timer configuration
Return values:
None

Definition at line 7410 of file stm32g0xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_SLAVEMODE_GATED, TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 7591 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 7544 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 7674 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 7634 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 7717 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 7765 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Exported Types

Data Structures | Typedefs | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | __TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Typedefs

typedef struct __TIM_HandleTypeDef | TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
typedef void(* | pTIM_CallbackTypeDef )(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum | HAL_TIM_ChannelStateTypeDef { HAL_TIM_CHANNEL_STATE_RESET = 0x00U, HAL_TIM_CHANNEL_STATE_READY = 0x01U, HAL_TIM_CHANNEL_STATE_BUSY = 0x02U }
TIM Channel States definition. More...
enum | HAL_TIM_DMABurstStateTypeDef { HAL_DMA_BURST_STATE_RESET = 0x00U, HAL_DMA_BURST_STATE_READY = 0x01U, HAL_DMA_BURST_STATE_BUSY = 0x02U }
DMA Burst States definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...
enum HAL_TIM_CallbackIDTypeDef {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U,
HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U,
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU,
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU,
HAL_TIM_TRIGGER_CB_ID = 0x10U, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U,
HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U, HAL_TIM_ERROR_CB_ID = 0x17U,
HAL_TIM_COMMUTATION_CB_ID = 0x18U, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U, HAL_TIM_BREAK_CB_ID = 0x1AU, HAL_TIM_BREAK2_CB_ID = 0x1BU
}
HAL TIM Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim)

HAL TIM Callback pointer definition.

pointer to the TIM callback function

Definition at line 439 of file stm32g0xx_hal_tim.h.

typedef struct __TIM_HandleTypeDef TIM_HandleTypeDef

TIM Time Base Handle Structure definition.

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_5

The active channel is 5

HAL_TIM_ACTIVE_CHANNEL_6

The active channel is 6

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 336 of file stm32g0xx_hal_tim.h.

enum HAL_TIM_CallbackIDTypeDef

HAL TIM Callback ID enumeration definition.

Enumerator:
HAL_TIM_BASE_MSPINIT_CB_ID

TIM Base MspInit Callback ID

HAL_TIM_BASE_MSPDEINIT_CB_ID

TIM Base MspDeInit Callback ID

HAL_TIM_IC_MSPINIT_CB_ID

TIM IC MspInit Callback ID

HAL_TIM_IC_MSPDEINIT_CB_ID

TIM IC MspDeInit Callback ID

HAL_TIM_OC_MSPINIT_CB_ID

TIM OC MspInit Callback ID

HAL_TIM_OC_MSPDEINIT_CB_ID

TIM OC MspDeInit Callback ID

HAL_TIM_PWM_MSPINIT_CB_ID

TIM PWM MspInit Callback ID

HAL_TIM_PWM_MSPDEINIT_CB_ID

TIM PWM MspDeInit Callback ID

HAL_TIM_ONE_PULSE_MSPINIT_CB_ID

TIM One Pulse MspInit Callback ID

HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID

TIM One Pulse MspDeInit Callback ID

HAL_TIM_ENCODER_MSPINIT_CB_ID

TIM Encoder MspInit Callback ID

HAL_TIM_ENCODER_MSPDEINIT_CB_ID

TIM Encoder MspDeInit Callback ID

HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID

TIM Hall Sensor MspDeInit Callback ID

HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID

TIM Hall Sensor MspDeInit Callback ID

HAL_TIM_PERIOD_ELAPSED_CB_ID

TIM Period Elapsed Callback ID

HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID

TIM Period Elapsed half complete Callback ID

HAL_TIM_TRIGGER_CB_ID

TIM Trigger Callback ID

HAL_TIM_TRIGGER_HALF_CB_ID

TIM Trigger half complete Callback ID

HAL_TIM_IC_CAPTURE_CB_ID

TIM Input Capture Callback ID

HAL_TIM_IC_CAPTURE_HALF_CB_ID

TIM Input Capture half complete Callback ID

HAL_TIM_OC_DELAY_ELAPSED_CB_ID

TIM Output Compare Delay Elapsed Callback ID

HAL_TIM_PWM_PULSE_FINISHED_CB_ID

TIM PWM Pulse Finished Callback ID

HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID

TIM PWM Pulse Finished half complete Callback ID

HAL_TIM_ERROR_CB_ID

TIM Error Callback ID

HAL_TIM_COMMUTATION_CB_ID

TIM Commutation Callback ID

HAL_TIM_COMMUTATION_HALF_CB_ID

TIM Commutation half complete Callback ID

HAL_TIM_BREAK_CB_ID

TIM Break Callback ID

HAL_TIM_BREAK2_CB_ID

TIM Break2 Callback ID

Definition at line 403 of file stm32g0xx_hal_tim.h.

enum HAL_TIM_ChannelStateTypeDef

TIM Channel States definition.

Enumerator:
HAL_TIM_CHANNEL_STATE_RESET

TIM Channel initial state

HAL_TIM_CHANNEL_STATE_READY

TIM Channel ready for use

HAL_TIM_CHANNEL_STATE_BUSY

An internal process is ongoing on the TIM channel

Definition at line 316 of file stm32g0xx_hal_tim.h.

enum HAL_TIM_DMABurstStateTypeDef

DMA Burst States definition.

Enumerator:
HAL_DMA_BURST_STATE_RESET

DMA Burst initial state

HAL_DMA_BURST_STATE_READY

DMA Burst ready for use

HAL_DMA_BURST_STATE_BUSY

Ongoing DMA Burst

Definition at line 326 of file stm32g0xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 304 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter
uint32_t | AutoReloadPreload

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 46 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::AutoReloadPreload

Specifies the auto-reload preload. This parameter can be a value of TIM Auto-Reload Preload

Definition at line 72 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 58 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 51 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 54 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 48 of file stm32g0xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 61 of file stm32g0xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 79 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 94 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 99 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 81 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 103 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 90 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 87 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 84 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 111 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 140 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 134 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 137 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 126 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 113 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 130 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 122 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 119 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 116 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 147 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 158 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 149 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 155 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 152 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 165 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 167 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 179 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Input Polarity

Definition at line 170 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 176 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 173 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 191 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Input Polarity

Definition at line 182 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 188 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 185 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

Clock Configuration Handle Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

Clock Configuration Handle Structure definition.

Definition at line 198 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 206 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity This parameter can be a value of TIM Clock Polarity

Definition at line 202 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler This parameter can be a value of TIM Clock Prescaler

Definition at line 204 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources This parameter can be a value of TIM Clock Source

Definition at line 200 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

TIM Clear Input Configuration Handle Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

TIM Clear Input Configuration Handle Structure definition.

Definition at line 213 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 224 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity

Definition at line 219 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off

Definition at line 221 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources This parameter can be a value of TIM Clear Input Source

Definition at line 217 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state This parameter can be ENABLE or DISABLE

Definition at line 215 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIM Exported Types

TIM Master configuration Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterOutputTrigger2
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Note:
Advanced timers provide TRGO2 internal line which is redirected to the ADC

Definition at line 233 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection

Definition at line 235 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger2

Trigger output2 (TRGO2) selection This parameter can be a value of TIM Master Mode Selection 2 (TRGO2)

Definition at line 237 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection This parameter can be a value of TIM Master/Slave Mode

Note:
When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode.

Definition at line 239 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 251 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 255 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIM Slave mode

Definition at line 253 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 261 of file stm32g0xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 257 of file stm32g0xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 259 of file stm32g0xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIM Exported Types

TIM Break input(s) and Dead time configuration Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | BreakAFMode
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | Break2AFMode
uint32_t | AutomaticOutput

Detailed Description

TIM Break input(s) and Dead time configuration Structure definition.

Note:
2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.

Definition at line 271 of file stm32g0xx_hal_tim.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state, This parameter can be a value of TIM Automatic Output Enable

Definition at line 297 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2AFMode

Specifies the alternate function mode of the break2 input.This parameter can be a value of TIM Break2 Input Alternate Function Mode

Definition at line 295 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Filter

TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 293 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Polarity

TIM Break2 input polarity, This parameter can be a value of TIM Break Input 2 Polarity

Definition at line 291 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2State

TIM Break2 State, This parameter can be a value of TIM Break input 2 Enable

Definition at line 289 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakAFMode

Specifies the alternate function mode of the break input.This parameter can be a value of TIM Break Input Alternate Function Mode

Definition at line 287 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakFilter

Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 285 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity, This parameter can be a value of TIM Break Input Polarity

Definition at line 283 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State, This parameter can be a value of TIM Break Input Enable

Definition at line 281 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 279 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level, This parameter can be a value of TIM Lock level

Definition at line 277 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode, This parameter can be a value of TIM OSSI OffState Selection for Idle mode state

Definition at line 275 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode, This parameter can be a value of TIM OSSR OffState Selection for Run mode state

Definition at line 273 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32g0xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State
__IO HAL_TIM_ChannelStateTypeDef | ChannelState [6]
__IO HAL_TIM_ChannelStateTypeDef | ChannelNState [4]
__IO HAL_TIM_DMABurstStateTypeDef | DMABurstState
void(* | Base_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Base_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OnePulse_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OnePulse_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Encoder_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Encoder_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | HallSensor_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | HallSensor_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PeriodElapsedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PeriodElapsedHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TriggerCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TriggerHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_CaptureCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_CaptureHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_DelayElapsedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_PulseFinishedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_PulseFinishedHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | ErrorCallback )(struct __TIM_HandleTypeDef *htim)
void(* | CommutationCallback )(struct __TIM_HandleTypeDef *htim)
void(* | CommutationHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | BreakCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Break2Callback )(struct __TIM_HandleTypeDef *htim)

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 351 of file stm32g0xx_hal_tim.h.

Field Documentation

void(* __TIM_HandleTypeDef::Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Base Msp DeInit Callback

Definition at line 369 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Base Msp Init Callback

Definition at line 368 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Break2Callback)(struct __TIM_HandleTypeDef *htim)

TIM Break2 Callback

Definition at line 395 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::BreakCallback)(struct __TIM_HandleTypeDef *htim)

TIM Break Callback

Definition at line 394 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

HAL_TIM_ActiveChannel __TIM_HandleTypeDef::Channel

Active channel

Definition at line 358 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_GetActiveChannel(), HAL_TIM_IRQHandler(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

__IO HAL_TIM_ChannelStateTypeDef __TIM_HandleTypeDef::ChannelNState[4]

TIM complementary channel operation state

Definition at line 364 of file stm32g0xx_hal_tim.h.

__IO HAL_TIM_ChannelStateTypeDef __TIM_HandleTypeDef::ChannelState[6]

TIM channel operation state

Definition at line 363 of file stm32g0xx_hal_tim.h.

void(* __TIM_HandleTypeDef::CommutationCallback)(struct __TIM_HandleTypeDef *htim)

TIM Commutation Callback

Definition at line 392 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationCplt().

void(* __TIM_HandleTypeDef::CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Commutation half complete Callback

Definition at line 393 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationHalfCplt().

__IO HAL_TIM_DMABurstStateTypeDef __TIM_HandleTypeDef::DMABurstState

DMA burst operation state

Definition at line 365 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMABurstState(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_DeInit(), and HAL_TIMEx_HallSensor_Init().

void(* __TIM_HandleTypeDef::Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Msp DeInit Callback

Definition at line 379 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Msp Init Callback

Definition at line 378 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::ErrorCallback)(struct __TIM_HandleTypeDef *htim)

TIM Error Callback

Definition at line 391 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Hall Sensor Msp DeInit Callback

Definition at line 381 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_DeInit().

void(* __TIM_HandleTypeDef::HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Hall Sensor Msp Init Callback

Definition at line 380 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_Init().

DMA_HandleTypeDef* __TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a TIM DMA Handle Index

Definition at line 359 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), and UART_DMARxOnlyAbortCallback().

void(* __TIM_HandleTypeDef::IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim)

TIM Input Capture Callback

Definition at line 386 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Input Capture half complete Callback

Definition at line 387 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureHalfCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM IC Msp DeInit Callback

Definition at line 371 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM IC Msp Init Callback

Definition at line 370 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

TIM_Base_InitTypeDef __TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 357 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* __TIM_HandleTypeDef::Instance

Register base address

Definition at line 356 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurstState(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_GetChannelState(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_DisarmBreakInput(), HAL_TIMEx_GetChannelNState(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_ReArmBreakInput(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef __TIM_HandleTypeDef::Lock

Locking object

Definition at line 361 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void(* __TIM_HandleTypeDef::OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim)

TIM Output Compare Delay Elapsed Callback

Definition at line 388 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM OC Msp DeInit Callback

Definition at line 373 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM OC Msp Init Callback

Definition at line 372 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM One Pulse Msp DeInit Callback

Definition at line 377 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM One Pulse Msp Init Callback

Definition at line 376 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim)

TIM Period Elapsed Callback

Definition at line 382 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Period Elapsed half complete Callback

Definition at line 383 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedHalfCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Msp DeInit Callback

Definition at line 375 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_PWM_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Msp Init Callback

Definition at line 374 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_PWM_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Pulse Finished Callback

Definition at line 389 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Pulse Finished half complete Callback

Definition at line 390 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseHalfCplt(), and TIM_ResetCallback().

__IO HAL_TIM_StateTypeDef __TIM_HandleTypeDef::State

TIM operation state

Definition at line 362 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_RegisterCallback(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIM_UnRegisterCallback(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_MasterConfigSynchronization(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), and TIMEx_DMACommutationHalfCplt().

void(* __TIM_HandleTypeDef::TriggerCallback)(struct __TIM_HandleTypeDef *htim)

TIM Trigger Callback

Definition at line 384 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Trigger half complete Callback

Definition at line 385 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerHalfCplt(), and TIM_ResetCallback().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Clear Input Source

Defines
TIM Clear Input Source
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_NONE 0x10000000U
#define | TIM_CLEARINPUTSOURCE_ETR 0x20000000U
#define | TIM_CLEARINPUTSOURCE_COMP1 0x00000000U
#define | TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR_0
#define | TIM_CLEARINPUTSOURCE_COMP3 TIM1_OR1_OCREF_CLR_1

Define Documentation

#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U

OCREF_CLR_INT is connected to COMP1 output

Definition at line 459 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR_0

OCREF_CLR_INT is connected to COMP2 output

Definition at line 460 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_COMP3 TIM1_OR1_OCREF_CLR_1

OCREF_CLR_INT is connected to COMP3 output

Definition at line 461 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_ETR 0x20000000U

OCREF_CLR is connected to ETRF input

Definition at line 457 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE 0x10000000U

OCREF_CLR is disabled

Definition at line 456 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM DMA Base Address

Defines
TIM DMA Base Address
TIM Exported Constants

Defines

#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_DCR 0x00000012U
#define | TIM_DMABASE_DMAR 0x00000013U
#define | TIM_DMABASE_OR1 0x00000014U
#define | TIM_DMABASE_CCMR3 0x00000015U
#define | TIM_DMABASE_CCR5 0x00000016U
#define | TIM_DMABASE_CCR6 0x00000017U
#define | TIM_DMABASE_AF1 0x00000018U
#define | TIM_DMABASE_AF2 0x00000019U
#define | TIM_DMABASE_TISEL 0x0000001AU

Define Documentation

#define TIM_DMABASE_AF1 0x00000018U

Definition at line 497 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_AF2 0x00000019U

Definition at line 498 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_ARR 0x0000000BU

Definition at line 484 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_BDTR 0x00000011U

Definition at line 490 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCER 0x00000008U

Definition at line 481 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCMR1 0x00000006U

Definition at line 479 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCMR2 0x00000007U

Definition at line 480 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCMR3 0x00000015U

Definition at line 494 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCR1 0x0000000DU

Definition at line 486 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCR2 0x0000000EU

Definition at line 487 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCR3 0x0000000FU

Definition at line 488 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCR4 0x00000010U

Definition at line 489 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCR5 0x00000016U

Definition at line 495 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CCR6 0x00000017U

Definition at line 496 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CNT 0x00000009U

Definition at line 482 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CR1 0x00000000U

Definition at line 473 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_CR2 0x00000001U

Definition at line 474 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_DCR 0x00000012U

Definition at line 491 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_DIER 0x00000003U

Definition at line 476 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_DMAR 0x00000013U

Definition at line 492 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_EGR 0x00000005U

Definition at line 478 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_OR1 0x00000014U

Definition at line 493 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_PSC 0x0000000AU

Definition at line 483 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_RCR 0x0000000CU

Definition at line 485 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_SMCR 0x00000002U

Definition at line 475 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_SR 0x00000004U

Definition at line 477 of file stm32g0xx_hal_tim.h.

#define TIM_DMABASE_TISEL 0x0000001AU

Definition at line 499 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Event Source

Defines
TIM Event Source
TIM Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

A break event is generated

Definition at line 514 of file stm32g0xx_hal_tim.h.

#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

A break 2 event is generated

Definition at line 515 of file stm32g0xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

A capture/compare event is generated on channel 1

Definition at line 508 of file stm32g0xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

A capture/compare event is generated on channel 2

Definition at line 509 of file stm32g0xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

A capture/compare event is generated on channel 3

Definition at line 510 of file stm32g0xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

A capture/compare event is generated on channel 4

Definition at line 511 of file stm32g0xx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

A commutation event is generated

Definition at line 512 of file stm32g0xx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

A trigger event is generated

Definition at line 513 of file stm32g0xx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Reinitialize the counter and generates an update of the registers

Definition at line 507 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Input Channel polarity

Defines
TIM Input Channel polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 525 of file stm32g0xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P

Polarity for TIx source

Definition at line 524 of file stm32g0xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U

Polarity for TIx source

Definition at line 523 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Define Documentation

#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP

Polarity for ETR source

Definition at line 533 of file stm32g0xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Polarity for ETR source

Definition at line 534 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define TIM_ETRPRESCALER_DIV1 0x00000000U

No prescaler is used

Definition at line 542 of file stm32g0xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR input source is divided by 2

Definition at line 543 of file stm32g0xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR input source is divided by 4

Definition at line 544 of file stm32g0xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS

ETR input source is divided by 8

Definition at line 545 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Center-aligned mode 1

Definition at line 555 of file stm32g0xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Center-aligned mode 2

Definition at line 556 of file stm32g0xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Center-aligned mode 3

Definition at line 557 of file stm32g0xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as down-counter

Definition at line 554 of file stm32g0xx_hal_tim.h.

#define TIM_COUNTERMODE_UP 0x00000000U

Counter used as up-counter

Definition at line 553 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Update Interrupt Flag Remap

Defines
TIM Update Interrupt Flag Remap
TIM Exported Constants

Defines

#define | TIM_UIFREMAP_DISABLE 0x00000000U
#define | TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP

Define Documentation

#define TIM_UIFREMAP_DISABLE 0x00000000U

Update interrupt flag remap disabled

Definition at line 565 of file stm32g0xx_hal_tim.h.

#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP

Update interrupt flag remap enabled

Definition at line 566 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 0x00000000U

Clock division: tDTS=tCK_INT

Definition at line 574 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

Clock division: tDTS=2*tCK_INT

Definition at line 575 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Clock division: tDTS=4*tCK_INT

Definition at line 576 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Output Compare State

Defines
TIM Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define TIM_OUTPUTSTATE_DISABLE 0x00000000U

Capture/Compare 1 output disabled

Definition at line 584 of file stm32g0xx_hal_tim.h.

#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E

Capture/Compare 1 output enabled

Definition at line 585 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Auto-Reload Preload

Defines
TIM Auto-Reload Preload
TIM Exported Constants

Defines

#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE

Define Documentation

#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U

TIMx_ARR register is not buffered

Definition at line 593 of file stm32g0xx_hal_tim.h.

#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE

TIMx_ARR register is buffered

Definition at line 594 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE

Define Documentation

#define TIM_OCFAST_DISABLE 0x00000000U

Output Compare fast disable

Definition at line 603 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE

Output Compare fast enable

Definition at line 604 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Complementary Output Compare State

Defines
TIM Complementary Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE

Define Documentation

#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U

OCxN is disabled

Definition at line 612 of file stm32g0xx_hal_tim.h.

#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE

OCxN is enabled

Definition at line 613 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define TIM_OCPOLARITY_HIGH 0x00000000U

Capture/Compare output polarity

Definition at line 621 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Capture/Compare output polarity

Definition at line 622 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP

Define Documentation

#define TIM_OCNPOLARITY_HIGH 0x00000000U

Capture/Compare complementary output polarity

Definition at line 630 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP

Capture/Compare complementary output polarity

Definition at line 631 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET TIM_CR2_OIS1
#define | TIM_OCIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCIDLESTATE_RESET 0x00000000U

Output Idle state: OCx=0 when MOE=0

Definition at line 640 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1

Output Idle state: OCx=1 when MOE=0

Definition at line 639 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Complementary Output Compare Idle State

Defines
TIM Complementary Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
#define | TIM_OCNIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCNIDLESTATE_RESET 0x00000000U

Complementary output Idle state: OCxN=0 when MOE=0

Definition at line 649 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N

Complementary output Idle state: OCxN=1 when MOE=0

Definition at line 648 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Capture triggered by both rising and falling edges on timer input

Definition at line 659 of file stm32g0xx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Capture triggered by falling edge on timer input

Definition at line 658 of file stm32g0xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Capture triggered by rising edge on timer input

Definition at line 657 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Encoder Input Polarity

Defines
TIM Encoder Input Polarity
TIM Exported Constants

Defines

#define | TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Define Documentation

#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Encoder input with falling edge polarity

Definition at line 668 of file stm32g0xx_hal_tim.h.

#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Encoder input with rising edge polarity

Definition at line 667 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
#define | TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
#define | TIM_ICSELECTION_TRC TIM_CCMR1_CC1S

Define Documentation

#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 676 of file stm32g0xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 677 of file stm32g0xx_hal_tim.h.

#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 678 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

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STM32G0C1xx HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
#define | TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
#define | TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC

Define Documentation

#define TIM_ICPSC_DIV1 0x00000000U

Capture performed each time an edge is detected on the capture input

Definition at line 686 of file stm32g0xx_hal_tim.h.

#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0

Capture performed once every 2 events

Definition at line 687 of file stm32g0xx_hal_tim.h.

#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1

Capture performed once every 4 events

Definition at line 688 of file stm32g0xx_hal_tim.h.

#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC

Capture performed once every 8 events

Definition at line 689 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE TIM_CR1_OPM
#define | TIM_OPMODE_REPETITIVE 0x00000000U

Define Documentation

#define TIM_OPMODE_REPETITIVE 0x00000000U

Counter is not stopped at update event

Definition at line 698 of file stm32g0xx_hal_tim.h.

#define TIM_OPMODE_SINGLE TIM_CR1_OPM

Counter stops counting at the next update event

Definition at line 697 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
#define | TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0

Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 706 of file stm32g0xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

Definition at line 708 of file stm32g0xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1

Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level.

Definition at line 707 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM interrupt Definition

Defines
TIM interrupt Definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE TIM_DIER_UIE
#define | TIM_IT_CC1 TIM_DIER_CC1IE
#define | TIM_IT_CC2 TIM_DIER_CC2IE
#define | TIM_IT_CC3 TIM_DIER_CC3IE
#define | TIM_IT_CC4 TIM_DIER_CC4IE
#define | TIM_IT_COM TIM_DIER_COMIE
#define | TIM_IT_TRIGGER TIM_DIER_TIE
#define | TIM_IT_BREAK TIM_DIER_BIE

Define Documentation

#define TIM_IT_BREAK TIM_DIER_BIE

Break interrupt

Definition at line 723 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 TIM_DIER_CC1IE

Capture/Compare 1 interrupt

Definition at line 717 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 TIM_DIER_CC2IE

Capture/Compare 2 interrupt

Definition at line 718 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 TIM_DIER_CC3IE

Capture/Compare 3 interrupt

Definition at line 719 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 TIM_DIER_CC4IE

Capture/Compare 4 interrupt

Definition at line 720 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), and HAL_TIM_PWM_Stop_IT().

#define TIM_IT_COM TIM_DIER_COMIE

Commutation interrupt

Definition at line 721 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define TIM_IT_TRIGGER TIM_DIER_TIE

Trigger interrupt

Definition at line 722 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define TIM_IT_UPDATE TIM_DIER_UIE

Update interrupt

Definition at line 716 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

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STM32G0C1xx HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI TIM_CR2_CCUS
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U

Define Documentation

#define TIM_COMMUTATION_SOFTWARE 0x00000000U

When Capture/compare control bits are preloaded, they are updated by setting the COMG bit

Definition at line 732 of file stm32g0xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS

When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input

Definition at line 731 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM DMA Sources

Defines
TIM DMA Sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE TIM_DIER_UDE
#define | TIM_DMA_CC1 TIM_DIER_CC1DE
#define | TIM_DMA_CC2 TIM_DIER_CC2DE
#define | TIM_DMA_CC3 TIM_DIER_CC3DE
#define | TIM_DMA_CC4 TIM_DIER_CC4DE
#define | TIM_DMA_COM TIM_DIER_COMDE
#define | TIM_DMA_TRIGGER TIM_DIER_TDE

Define Documentation

#define TIM_DMA_CC1 TIM_DIER_CC1DE

DMA request is triggered by the capture/compare macth 1 event

Definition at line 741 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 TIM_DIER_CC2DE

DMA request is triggered by the capture/compare macth 2 event event

Definition at line 742 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 TIM_DIER_CC3DE

DMA request is triggered by the capture/compare macth 3 event event

Definition at line 743 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 TIM_DIER_CC4DE

DMA request is triggered by the capture/compare macth 4 event event

Definition at line 744 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), and HAL_TIM_PWM_Stop_DMA().

#define TIM_DMA_COM TIM_DIER_COMDE

DMA request is triggered by the commutation event

Definition at line 745 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define TIM_DMA_TRIGGER TIM_DIER_TDE

DMA request is triggered by the trigger event

Definition at line 746 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define TIM_DMA_UPDATE TIM_DIER_UDE

DMA request is triggered by the update event

Definition at line 740 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CCx DMA request selection

Defines
CCx DMA request selection
TIM Exported Constants

Defines

#define | TIM_CCDMAREQUEST_CC 0x00000000U
#define | TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define TIM_CCDMAREQUEST_CC 0x00000000U

CCx DMA request sent when capture or compare match event occurs

Definition at line 754 of file stm32g0xx_hal_tim.h.

#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 755 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Flag Definition

Defines
TIM Flag Definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE TIM_SR_UIF
#define | TIM_FLAG_CC1 TIM_SR_CC1IF
#define | TIM_FLAG_CC2 TIM_SR_CC2IF
#define | TIM_FLAG_CC3 TIM_SR_CC3IF
#define | TIM_FLAG_CC4 TIM_SR_CC4IF
#define | TIM_FLAG_CC5 TIM_SR_CC5IF
#define | TIM_FLAG_CC6 TIM_SR_CC6IF
#define | TIM_FLAG_COM TIM_SR_COMIF
#define | TIM_FLAG_TRIGGER TIM_SR_TIF
#define | TIM_FLAG_BREAK TIM_SR_BIF
#define | TIM_FLAG_BREAK2 TIM_SR_B2IF
#define | TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
#define | TIM_FLAG_CC1OF TIM_SR_CC1OF
#define | TIM_FLAG_CC2OF TIM_SR_CC2OF
#define | TIM_FLAG_CC3OF TIM_SR_CC3OF
#define | TIM_FLAG_CC4OF TIM_SR_CC4OF

Define Documentation

#define TIM_FLAG_BREAK TIM_SR_BIF

Break interrupt flag

Definition at line 772 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_BREAK2 TIM_SR_B2IF

Break 2 interrupt flag

Definition at line 773 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 TIM_SR_CC1IF

Capture/Compare 1 interrupt flag

Definition at line 764 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF TIM_SR_CC1OF

Capture 1 overcapture flag

Definition at line 775 of file stm32g0xx_hal_tim.h.

#define TIM_FLAG_CC2 TIM_SR_CC2IF

Capture/Compare 2 interrupt flag

Definition at line 765 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF TIM_SR_CC2OF

Capture 2 overcapture flag

Definition at line 776 of file stm32g0xx_hal_tim.h.

#define TIM_FLAG_CC3 TIM_SR_CC3IF

Capture/Compare 3 interrupt flag

Definition at line 766 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF TIM_SR_CC3OF

Capture 3 overcapture flag

Definition at line 777 of file stm32g0xx_hal_tim.h.

#define TIM_FLAG_CC4 TIM_SR_CC4IF

Capture/Compare 4 interrupt flag

Definition at line 767 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF TIM_SR_CC4OF

Capture 4 overcapture flag

Definition at line 778 of file stm32g0xx_hal_tim.h.

#define TIM_FLAG_CC5 TIM_SR_CC5IF

Capture/Compare 5 interrupt flag

Definition at line 768 of file stm32g0xx_hal_tim.h.

#define TIM_FLAG_CC6 TIM_SR_CC6IF

Capture/Compare 6 interrupt flag

Definition at line 769 of file stm32g0xx_hal_tim.h.

#define TIM_FLAG_COM TIM_SR_COMIF

Commutation interrupt flag

Definition at line 770 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF

System Break interrupt flag

Definition at line 774 of file stm32g0xx_hal_tim.h.

#define TIM_FLAG_TRIGGER TIM_SR_TIF

Trigger interrupt flag

Definition at line 771 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE TIM_SR_UIF

Update interrupt flag

Definition at line 763 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Channel

Defines
TIM Channel
TIM Exported Constants

Defines

#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_5 0x00000010U
#define | TIM_CHANNEL_6 0x00000014U
#define | TIM_CHANNEL_ALL 0x0000003CU

Define Documentation

#define TIM_CHANNEL_1 0x00000000U

Capture/compare channel 1 identifier

Definition at line 786 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_OC1_SetConfig().

#define TIM_CHANNEL_2 0x00000004U

Capture/compare channel 2 identifier

Definition at line 787 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_OC2_SetConfig().

#define TIM_CHANNEL_3 0x00000008U

Capture/compare channel 3 identifier

Definition at line 788 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_TISelection(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), TIM_DMAErrorCCxN(), and TIM_OC3_SetConfig().

#define TIM_CHANNEL_4 0x0000000CU

Capture/compare channel 4 identifier

Definition at line 789 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseNCplt(), and TIM_DMAError().

#define TIM_CHANNEL_5 0x00000010U

Compare channel 5 identifier

Definition at line 790 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_6 0x00000014U

Compare channel 6 identifier

Definition at line 791 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_ALL 0x0000003CU

Global Capture/compare channel identifier

Definition at line 792 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
#define | TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
#define | TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
#define | TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
#define | TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
#define | TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
#define | TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
#define | TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
#define | TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
#define | TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
#define | TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF

External clock source mode 1 (ETRF)

Definition at line 801 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1

External clock source mode 2

Definition at line 802 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0

Internal clock source

Definition at line 800 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0

External clock source mode 1 (ITR0)

Definition at line 806 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1

External clock source mode 1 (ITR1)

Definition at line 807 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2

External clock source mode 1 (ITR2)

Definition at line 808 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3

External clock source mode 1 (ITR3)

Definition at line 809 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7

External clock source mode 1 (ITR7)

Definition at line 811 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1

External clock source mode 1 (TTI1FP1)

Definition at line 804 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED

External clock source mode 1 (TTI1FP1 + edge detect.)

Definition at line 803 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2

External clock source mode 1 (TTI2FP2)

Definition at line 805 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 824 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 823 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 820 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 821 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 822 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 832 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 833 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 834 of file stm32g0xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 835 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 843 of file stm32g0xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 844 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 852 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 853 of file stm32g0xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 854 of file stm32g0xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 855 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM OSSR OffState Selection for Run mode state

Defines
TIM OSSR OffState Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | TIM_OSSR_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSR_DISABLE 0x00000000U

When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer)

Definition at line 864 of file stm32g0xx_hal_tim.h.

#define TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled (still controlled by the timer)

Definition at line 863 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM OSSI OffState Selection for Idle mode state

Defines
TIM OSSI OffState Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | TIM_OSSI_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSI_DISABLE 0x00000000U

When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer)

Definition at line 873 of file stm32g0xx_hal_tim.h.

#define TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OC/OCN outputs are enabled (still controlled by the timer)

Definition at line 872 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 881 of file stm32g0xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 882 of file stm32g0xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 883 of file stm32g0xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF

Definition at line 880 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Break Input Enable

Defines
TIM Break Input Enable
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | TIM_BREAK_DISABLE 0x00000000U

Define Documentation

#define TIM_BREAK_DISABLE 0x00000000U

Break input BRK is disabled

Definition at line 892 of file stm32g0xx_hal_tim.h.

#define TIM_BREAK_ENABLE TIM_BDTR_BKE

Break input BRK is enabled

Definition at line 891 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Break Input Polarity

Defines
TIM Break Input Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 901 of file stm32g0xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 900 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Break Input Alternate Function Mode

Defines
TIM Break Input Alternate Function Mode
TIM Exported Constants

Defines

#define | TIM_BREAK_AFMODE_INPUT 0x00000000U
#define | TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID

Define Documentation

#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID

Break input BRK in bidirectional mode

Definition at line 910 of file stm32g0xx_hal_tim.h.

#define TIM_BREAK_AFMODE_INPUT 0x00000000U

Break input BRK in input mode

Definition at line 909 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Break input 2 Enable

Defines
TIM Break input 2 Enable
TIM Exported Constants

Defines

#define | TIM_BREAK2_DISABLE 0x00000000U
#define | TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Define Documentation

#define TIM_BREAK2_DISABLE 0x00000000U

Break input BRK2 is disabled

Definition at line 918 of file stm32g0xx_hal_tim.h.

#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Break input BRK2 is enabled

Definition at line 919 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Break Input 2 Polarity

Defines
TIM Break Input 2 Polarity
TIM Exported Constants

Defines

#define | TIM_BREAK2POLARITY_LOW 0x00000000U
#define | TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 928 of file stm32g0xx_hal_tim.h.

#define TIM_BREAK2POLARITY_LOW 0x00000000U

Break input BRK2 is active low

Definition at line 927 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Break2 Input Alternate Function Mode

Defines
TIM Break2 Input Alternate Function Mode
TIM Exported Constants

Defines

#define | TIM_BREAK2_AFMODE_INPUT 0x00000000U
#define | TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID

Define Documentation

#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID

Break2 input BRK2 in bidirectional mode

Definition at line 937 of file stm32g0xx_hal_tim.h.

#define TIM_BREAK2_AFMODE_INPUT 0x00000000U

Break2 input BRK2 in input mode

Definition at line 936 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Automatic Output Enable

Defines
TIM Automatic Output Enable
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 945 of file stm32g0xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

Definition at line 946 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Group Channel 5 and Channel 1, 2 or 3

Defines
TIM Group Channel 5 and Channel 1, 2 or 3
TIM Exported Constants

Defines

#define | TIM_GROUPCH5_NONE 0x00000000U
#define | TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

Define Documentation

#define TIM_GROUPCH5_NONE 0x00000000U

No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC

Definition at line 954 of file stm32g0xx_hal_tim.h.

#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1

OC1REFC is the logical AND of OC1REFC and OC5REF

Definition at line 955 of file stm32g0xx_hal_tim.h.

#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2

OC2REFC is the logical AND of OC2REFC and OC5REF

Definition at line 956 of file stm32g0xx_hal_tim.h.

#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

OC3REFC is the logical AND of OC3REFC and OC5REF

Definition at line 957 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define TIM_TRGO_ENABLE TIM_CR2_MMS_0

TIMx_CR1.CEN bit is used as trigger output (TRGO)

Definition at line 966 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Capture or a compare match 1 is used as trigger output (TRGO)

Definition at line 968 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output (TRGO)

Definition at line 969 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output(TRGO)

Definition at line 970 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output(TRGO)

Definition at line 971 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output(TRGO)

Definition at line 972 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO_RESET 0x00000000U

TIMx_EGR.UG bit is used as trigger output (TRGO)

Definition at line 965 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output (TRGO)

Definition at line 967 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Master Mode Selection 2 (TRGO2)

Defines
TIM Master Mode Selection 2 (TRGO2)
TIM Exported Constants

Defines

#define | TIM_TRGO2_RESET 0x00000000U
#define | TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
#define | TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
#define | TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

TIMx_CR1.CEN bit is used as trigger output (TRGO2)

Definition at line 981 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Capture or a compare match 1 is used as trigger output (TRGO2)

Definition at line 983 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2

OC1REF signal is used as trigger output (TRGO2)

Definition at line 984 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output (TRGO2)

Definition at line 985 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output (TRGO2)

Definition at line 986 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output (TRGO2)

Definition at line 987 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges generate pulses on TRGO2

Definition at line 993 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 992 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges generate pulses on TRGO2

Definition at line 990 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3

OC5REF signal is used as trigger output (TRGO2)

Definition at line 988 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 995 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 994 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output (TRGO2)

Definition at line 989 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges generate pulses on TRGO2

Definition at line 991 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_RESET 0x00000000U

TIMx_EGR.UG bit is used as trigger output (TRGO2)

Definition at line 980 of file stm32g0xx_hal_tim.h.

#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output (TRGO2)

Definition at line 982 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Master/Slave Mode

Defines
TIM Master/Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Master/slave mode is selected

Definition at line 1004 of file stm32g0xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM

No action

Definition at line 1003 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM Slave mode

Defines
TIM Slave mode
TIM Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Define Documentation

#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode

Definition at line 1017 of file stm32g0xx_hal_tim.h.

#define TIM_SLAVEMODE_DISABLE 0x00000000U

Slave mode disabled

Definition at line 1012 of file stm32g0xx_hal_tim.h.

#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

External Clock Mode 1

Definition at line 1016 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode

Definition at line 1014 of file stm32g0xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode

Definition at line 1013 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode

Definition at line 1015 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

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STM32G0C1xx HAL User Manual: TIM Output Compare and PWM Modes

Defines
TIM Output Compare and PWM Modes
TIM Exported Constants

Defines

#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M

Define Documentation

#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

Set channel to active level on match

Definition at line 1026 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 1037 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M

Asymmetric PWM mode 2

Definition at line 1038 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 1035 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 1036 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

Force active level

Definition at line 1031 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

Force inactive level

Definition at line 1032 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

Set channel to inactive level on match

Definition at line 1027 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

PWM mode 1

Definition at line 1029 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

PWM mode 2

Definition at line 1030 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 1033 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 1034 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_TIMING 0x00000000U

Frozen

Definition at line 1025 of file stm32g0xx_hal_tim.h.

#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Toggle

Definition at line 1028 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 TIM_SMCR_TS_0
#define | TIM_TS_ITR2 TIM_SMCR_TS_1
#define | TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_NONE 0x0000FFFFU

Define Documentation

#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Filtered External Trigger input (ETRF)

Definition at line 1056 of file stm32g0xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0)

Definition at line 1046 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1)

Definition at line 1047 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2)

Definition at line 1048 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3)

Definition at line 1049 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)

Internal Trigger 7 (ITR7)

Definition at line 1051 of file stm32g0xx_hal_tim.h.

#define TIM_TS_NONE 0x0000FFFFU

No trigger selected

Definition at line 1057 of file stm32g0xx_hal_tim.h.

#define TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED)

Definition at line 1053 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Filtered Timer Input 1 (TI1FP1)

Definition at line 1054 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Filtered Timer Input 2 (TI2FP2)

Definition at line 1055 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1069 of file stm32g0xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1068 of file stm32g0xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 1065 of file stm32g0xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 1066 of file stm32g0xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 1067 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 1077 of file stm32g0xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 1078 of file stm32g0xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 1079 of file stm32g0xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 1080 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM TI1 Input Selection

Defines
TIM TI1 Input Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S

Define Documentation

#define TIM_TI1SELECTION_CH1 0x00000000U

The TIMx_CH1 pin is connected to TI1 input

Definition at line 1088 of file stm32g0xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S

The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

Definition at line 1089 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U

The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1106 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U

The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1107 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U

The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1108 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U

The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1109 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U

The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1110 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U

The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1111 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U

The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1112 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U

The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1113 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1114 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U

The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1097 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U

The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1098 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U

The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1099 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U

The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1100 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U

The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1101 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U

The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1102 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U

The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1103 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U

The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1104 of file stm32g0xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U

The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1105 of file stm32g0xx_hal_tim.h.

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STM32G0C1xx HAL User Manual: TIM DMA Handle Index

Defines
TIM DMA Handle Index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 1123 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 1124 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 1125 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAError(), and TIM_DMAErrorCCxN().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 1126 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), and TIM_DMAError().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)

Index of the DMA handle used for Commutation DMA requests

Definition at line 1127 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)

Index of the DMA handle used for Trigger DMA requests

Definition at line 1128 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), and TIM_DMATriggerCplt().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)

Index of the DMA handle used for Update DMA requests

Definition at line 1122 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), and TIM_DMAPeriodElapsedCplt().

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STM32G0C1xx HAL User Manual: TIM Capture/Compare Channel State

Defines
TIM Capture/Compare Channel State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U

Define Documentation

#define TIM_CCx_DISABLE 0x00000000U

Input or output channel is disabled

Definition at line 1137 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), and HAL_TIMEx_OnePulseN_Stop_IT().

#define TIM_CCx_ENABLE 0x00000001U

Input or output channel is enabled

Definition at line 1136 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OnePulseN_Start(), and HAL_TIMEx_OnePulseN_Start_IT().

#define TIM_CCxN_DISABLE 0x00000000U

Complementary output channel is enabled

Definition at line 1139 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE 0x00000004U

Complementary output channel is enabled

Definition at line 1138 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Break System

Defines
TIM Break System
TIM Exported Constants

Defines

#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/15/16/17

Definition at line 1147 of file stm32g0xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17

Definition at line 1150 of file stm32g0xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 1148 of file stm32g0xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL

Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17

Definition at line 1149 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
#define | __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
Disable update interrupt flag (UIF) remapping.
#define | __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
Get update interrupt flag (UIF) copy status.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Set the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Reset the TIM Output compare preload.
#define | __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Enable fast mode for a given channel.
#define | __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Disable fast mode for a given channel.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
Select the Capture/compare DMA request source.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the specified TIM interrupt flag.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to clear. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1379 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Clear the TIM interrupt pending bits.

Parameters:
__HANDLE__ TIM handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1413 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
    { \
      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
      { \
        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
      } \
    } \
  } while(0)

Disable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1234 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Disable the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to disable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1331 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Disable the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to disable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1301 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchro(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_OCxFAST | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))

Disable fast mode for a given channel.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Note:
When fast mode is disabled CCx output behaves normally depending on counter and CCRx values even when the trigger is ON. The minimum delay to activate CCx output when an active edge occurs on the trigger input is 5 clock cycles.
Return values:
None

Definition at line 1694 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_DISABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))

Reset the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
None

Definition at line 1644 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1220 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Enable the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to enable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1316 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Enable the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to enable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1285 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_OCxFAST | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))

Enable fast mode for a given channel.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Note:
When fast mode is enabled an active edge on the trigger input acts like a compare match on CCx output. Delay to sample the trigger input and to activate CCx output is reduced to 3 clock cycles.
Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
Return values:
None

Definition at line 1669 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_ENABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))

Set the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
None

Definition at line 1623 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Get the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)

Definition at line 1493 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Get the TIM Clock Division value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
The clock division can be one of the following values:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

Definition at line 1520 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
   ((__HANDLE__)->Instance->CCR6))

Get the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
  • TIM_CHANNEL_5: get capture/compare 5 register value
  • TIM_CHANNEL_6: get capture/compare 6 register value
Return values:
16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)

Definition at line 1602 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Get the TIM Counter Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer counter register (TIMx_CNT)

Definition at line 1474 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Check whether the specified TIM interrupt flag is set or not.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to check. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1355 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

Get the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
The input capture prescaler can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events

Definition at line 1561 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
                                                             == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TIM interrupt source is enabled or not.

Parameters:
__HANDLE__ TIM handle
__INTERRUPT__ specifies the TIM interrupt source to check. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
The state of TIM_IT (SET or RESET).

Definition at line 1396 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_UIFCPY ( __COUNTER__ ) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))

Get update interrupt flag (UIF) copy status.

Parameters:
__COUNTER__ Counter value.
Return values:
The state of UIFCPY (TRUE or FALSE). mode.

Definition at line 1439 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Indicates whether or not the TIM Counter is used as downcounter.

Parameters:
__HANDLE__ TIM handle.
Return values:
False (Counter used as upcounter) or True (Counter used as downcounter)
Note:
This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.

Definition at line 1448 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
    { \
      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
      { \
        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
      } \
    } \
  } while(0)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

Definition at line 1252 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY ( __HANDLE__ ) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled unconditionally

Definition at line 1269 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1227 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                               \
                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
                                                     } while(0)

Reset TIM handle state.

Parameters:
__HANDLE__ TIM handle.
Return values:
None

Definition at line 1170 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_SELECT_CCDMAREQUEST | ( | __HANDLE__,
 |  | __CCDMA__
 | ) | MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))

Select the Capture/compare DMA request source.

Parameters:
__HANDLE__ specifies the TIM Handle.
__CCDMA__ specifies Capture/compare DMA request source This parameter can be one of the following values:
  • TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
  • TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
Return values:
None

Definition at line 1754 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                    \
    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
  } while(0)

Set the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ | TIM handle.
__AUTORELOAD__ | specifies the Counter register new value.
Return values:
None

Definition at line 1482 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                     \
    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
  }while(0)

Set the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__ Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Return values:
None

Definition at line 1740 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                   \
    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
  } while(0)

Set the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ TIM handle.
__CKD__ specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
Return values:
None

Definition at line 1505 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))

Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__ | TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
__COMPARE__ | specifies the Capture Compare register new value.
Return values:
None

Definition at line 1581 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Set the TIM Counter Register value on runtime.

Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.

Parameters:
__HANDLE__ | TIM handle.
__COUNTER__ | specifies the Counter register new value.
Return values:
None

Definition at line 1467 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  } while(0)

Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__ specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1540 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Set the TIM Prescaler on runtime.

Parameters:
__HANDLE__ | TIM handle.
__PRESC__ | specifies the Prescaler new value.
Return values:
None

Definition at line 1456 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_UIFREMAP_DISABLE ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))

Disable update interrupt flag (UIF) remapping.

Parameters:
__HANDLE__ TIM handle.
Return values:
None mode.

Definition at line 1431 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_UIFREMAP_ENABLE ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))

Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

Note:
This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
Parameters:
__HANDLE__ TIM handle.
Return values:
None mode.

Definition at line 1423 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the URS bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): _ Counter overflow underflow _ Setting the UG bit _ Update generation through the slave mode controller
Return values:
None

Definition at line 1723 of file stm32g0xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the URS bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 1710 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIMx_OR1_OCREF_CLR 0x00000001U
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Define Documentation

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 1768 of file stm32g0xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 1769 of file stm32g0xx_hal_tim.h.

#define TIMx_OR1_OCREF_CLR 0x00000001U

Definition at line 205 of file stm32g0xx_hal_tim.c.

Referenced by HAL_TIM_ConfigOCrefClear().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_UIFREMAP_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK_AFMODE(__AFMODE__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_AFMODE(__AFMODE__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define | TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__)
#define | TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define | TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1965 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_AUTORELOAD_PRELOAD ( PRELOAD )
Value:
(((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

Definition at line 1836 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_BREAK2_AFMODE ( __AFMODE__ )
Value:
(((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
                                          ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))

Definition at line 1961 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))

Definition at line 1958 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK2_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK2_DISABLE))

Definition at line 1955 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_AFMODE ( __AFMODE__ )
Value:
(((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
                                         ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))

Definition at line 1951 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_FILTER ( __BRKFILTER__ ) ((__BRKFILTER__) <= 0xFUL)

Definition at line 1942 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1948 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK_DISABLE))

Definition at line 1945 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_SYSTEM ( __CONFIG__ )
Value:
(((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))

Definition at line 2092 of file stm32g0xx_hal_tim.h.

#define IS_TIM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))

Definition at line 1879 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1929 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 1921 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 1924 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( __MODE__ )
Value:
(((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))

Definition at line 1780 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( __DIV__ )
Value:
(((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1832 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1919 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 1908 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 1914 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( __CLOCK__ )
Value:
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))

Definition at line 1897 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_3))

Definition at line 1893 of file stm32g0xx_hal_tim.h.

#define IS_TIM_COUNTER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_COUNTERMODE_UP)              || \
                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1823 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DEADTIME ( __DEADTIME__ ) ((__DEADTIME__) <= 0xFFU)

Definition at line 2089 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_DMA_BASE ( __BASE__ )
Value:
(((__BASE__) == TIM_DMABASE_CR1)   || \
                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
                                   ((__BASE__) == TIM_DMABASE_SR)    || \
                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
                                   ((__BASE__) == TIM_DMABASE_OR1)    || \
                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
                                   ((__BASE__) == TIM_DMABASE_TISEL))

Definition at line 1795 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_DATA_LENGTH ( LENGTH ) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))

Definition at line 2085 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 2066 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), and HAL_TIM_DMABurst_MultiWriteStart().

#define IS_TIM_DMA_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1877 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_ENCODERMODE_TI1) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI12))

Definition at line 1873 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_ENCODERINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))

Definition at line 1854 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1821 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCFAST_DISABLE) || \
                                            ((__STATE__) == TIM_OCFAST_ENABLE))

Definition at line 1839 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_GROUPCH5 ( __OCREF__ ) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))

Definition at line 1968 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_GroupChannel5().

#define IS_TIM_IC_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 2087 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1857 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_ICPSC_DIV1) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))

Definition at line 1865 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))

Definition at line 1861 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
                                                               ((__SELECTION__) == TIM_TS_NONE))

Definition at line 2044 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define IS_TIM_LOCK_LEVEL ( __LEVEL__ )
Value:
(((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))

Definition at line 1937 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1997 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_TIMING)             || \
                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))

Definition at line 2014 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))

Definition at line 1842 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))

Definition at line 1848 of file stm32g0xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

Definition at line 1845 of file stm32g0xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCNIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))

Definition at line 1851 of file stm32g0xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OPM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2))

Definition at line 1887 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OPMODE_SINGLE) || \
                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))

Definition at line 1870 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSI_ENABLE) || \
                                            ((__STATE__) == TIM_OSSI_DISABLE))

Definition at line 1934 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSR_ENABLE) || \
                                            ((__STATE__) == TIM_OSSR_DISABLE))

Definition at line 1931 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PERIOD | ( | __HANDLE__,
 |  | __PERIOD__
 | ) | ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))

Definition at line 1890 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_PWM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_PWM1)               || \
                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 2007 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_SLAVE_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 2000 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED ( __TRIGGER__ )
Value:
(((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 2102 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define IS_TIM_TI1SELECTION ( __TI1SELECTION__ )
Value:
(((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 2063 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO2_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO2_RESET)                        || \
                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))

Definition at line 1979 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRGO_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO_RESET)  || \
                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC4REF))

Definition at line 1970 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0)    || \
                                                 ((__SELECTION__) == TIM_TS_ITR1)    || \
                                                 ((__SELECTION__) == TIM_TS_ITR2)    || \
                                                 ((__SELECTION__) == TIM_TS_ITR3)    || \
                                                 ((__SELECTION__) == TIM_TS_ITR7)    || \
                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
                                                 ((__SELECTION__) == TIM_TS_TI1FP1)  || \
                                                 ((__SELECTION__) == TIM_TS_TI2FP2)  || \
                                                 ((__SELECTION__) == TIM_TS_ETRF))

Definition at line 2024 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define IS_TIM_TRIGGERFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 2061 of file stm32g0xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 2050 of file stm32g0xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 2056 of file stm32g0xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_UIFREMAP_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_UIFREMAP_DISABLE) || \
                                            ((__MODE__) == TIM_UIFREMAP_ENABLE))

Definition at line 1829 of file stm32g0xx_hal_tim.h.

#define TIM_CHANNEL_N_STATE_GET | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
   (__HANDLE__)->ChannelNState[3])

Definition at line 2160 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIMEx_GetChannelNState(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define TIM_CHANNEL_N_STATE_SET | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __CHANNEL_STATE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))

Definition at line 2166 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), TIM_DMACaptureCplt(), TIM_DMADelayPulseNCplt(), and TIM_DMAErrorCCxN().

#define TIM_CHANNEL_N_STATE_SET_ALL | ( | __HANDLE__,
 |  | __CHANNEL_STATE__
 | ) |
Value:
do { \
                                                                         (__HANDLE__)->ChannelNState[0] = \
                                                                         (__CHANNEL_STATE__);  \
                                                                         (__HANDLE__)->ChannelNState[1] = \
                                                                         (__CHANNEL_STATE__);  \
                                                                         (__HANDLE__)->ChannelNState[2] = \
                                                                         (__CHANNEL_STATE__);  \
                                                                         (__HANDLE__)->ChannelNState[3] = \
                                                                         (__CHANNEL_STATE__);  \
                                                                       } while(0)

Definition at line 2172 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_PWM_DeInit(), and HAL_TIM_PWM_Init().

#define TIM_CHANNEL_STATE_GET | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
   (__HANDLE__)->ChannelState[5])

Definition at line 2129 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_GetChannelState(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OnePulseN_Start(), and HAL_TIMEx_OnePulseN_Start_IT().

#define TIM_CHANNEL_STATE_SET | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __CHANNEL_STATE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
   ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))

Definition at line 2137 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), and TIM_DMAError().

#define TIM_CHANNEL_STATE_SET_ALL | ( | __HANDLE__,
 |  | __CHANNEL_STATE__
 | ) |
Value:
do { \
                                                                       (__HANDLE__)->ChannelState[0]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[1]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[2]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[3]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[4]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                       (__HANDLE__)->ChannelState[5]  = \
                                                                       (__CHANNEL_STATE__);  \
                                                                     } while(0)

Definition at line 2145 of file stm32g0xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_PWM_DeInit(), and HAL_TIM_PWM_Init().

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

Definition at line 2123 of file stm32g0xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))

Definition at line 2111 of file stm32g0xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

Definition at line 2117 of file stm32g0xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

Definition at line 2105 of file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Private Constants

Defines
TIM Extended Private Constants
TIMEx

Defines

#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */

Define Documentation

#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */

Definition at line 103 of file stm32g0xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_ReArmBreakInput().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Timer Hall Sensor functions

Functions
Extended Timer Hall Sensor functions
TIM Extended Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Hall Sensor interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 253 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_RESET, HAL_TIM_CHANNEL_STATE_RESET, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and initialize the associated handle.

Note:
When the timer instance is initialized in Hall Sensor Interface mode, timer channels 1 and channel 2 are reserved and cannot be used for other purpose.
Parameters:
htim | TIM Hall Sensor Interface handle
sConfig | TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 151 of file stm32g0xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::DMABurstState, HAL_DMA_BURST_STATE_READY, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspInit(), __TIM_HandleTypeDef::HallSensor_MspInitCallback, TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_PERIOD, __TIM_HandleTypeDef::Lock, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_Base_InitTypeDef::Period, TIM_OC_InitTypeDef::Pulse, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_ResetCallback(), TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Hall Sensor MSP.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
None

Definition at line 313 of file stm32g0xx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
None

Definition at line 298 of file stm32g0xx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 328 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim | TIM Hall Sensor Interface handle
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 500 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, TIM_DMA_ID_CC1, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 410 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 382 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 576 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_DMA_CC1, and TIM_DMA_ID_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 467 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, and TIM_IT_CC1.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Timer Complementary Output Compare functions

Functions
Extended Timer Complementary Output Compare functions
TIM Extended Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 638 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_N_STATE_GET, and TIM_CHANNEL_N_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 883 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAErrorCCxN(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM OC handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 721 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 689 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), and TIM_CHANNEL_N_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1021 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, and TIM_DMA_ID_CC3.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 808 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_SET, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Timer Complementary PWM functions

Functions
Extended Timer Complementary PWM functions
TIM Extended Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1122 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_N_STATE_GET, and TIM_CHANNEL_N_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | const uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1365 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMADelayPulseHalfCplt(), TIM_DMADelayPulseNCplt(), TIM_DMAErrorCCxN(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1204 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1172 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), and TIM_CHANNEL_N_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1503 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_SET, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, and TIM_DMA_ID_CC3.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1290 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_SET, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Timer Complementary One Pulse functions

Functions
Extended Timer Complementary One Pulse functions
TIM Extended Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complementary output.

Note:
OutputChannel must match the pulse output channel chosen when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim TIM One Pulse handle
OutputChannel pulse output channel to enable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1594 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Note:
OutputChannel must match the pulse output channel chosen when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim TIM One Pulse handle
OutputChannel pulse output channel to enable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1682 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, HAL_TIM_CHANNEL_STATE_BUSY, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Note:
OutputChannel must match the pulse output channel chosen when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim TIM One Pulse handle
OutputChannel pulse output channel to disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1643 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, and TIM_CHANNEL_STATE_SET.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Note:
OutputChannel must match the pulse output channel chosen when calling HAL_TIM_OnePulse_ConfigChannel().
Parameters:
htim TIM One Pulse handle
OutputChannel pulse output channel to disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1737 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_CHANNEL_STATE_READY, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_N_STATE_SET, TIM_CHANNEL_STATE_SET, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
TIM Extended Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_DisarmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Disarm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_ReArmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Arm the designated break input (when it operates in bidirectional mode).

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Output channels for OC and PWM mode.

      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.
      (+) Configure timer remapping capabilities.
      (+) Select timer input source.
      (+) Enable or disable channel grouping.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim | TIM handle
sBreakDeadTimeConfig | pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Note:
Interrupts can be generated when an active level is detected on the break input, the break 2 input or the system break input. Break interrupt can be enabled by calling the __HAL_TIM_ENABLE_IT macro.
Return values:
HAL status

Definition at line 2053 of file stm32g0xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, TIM_BreakDeadTimeConfigTypeDef::Break2AFMode, TIM_BreakDeadTimeConfigTypeDef::Break2Filter, TIM_BreakDeadTimeConfigTypeDef::Break2Polarity, TIM_BreakDeadTimeConfigTypeDef::Break2State, TIM_BreakDeadTimeConfigTypeDef::BreakAFMode, TIM_BreakDeadTimeConfigTypeDef::BreakFilter, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, __TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK2_AFMODE, IS_TIM_BREAK2_POLARITY, IS_TIM_BREAK2_STATE, IS_TIM_BREAK_AFMODE, IS_TIM_BREAK_FILTER, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, and TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode.

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput,
 |  | const TIMEx_BreakInputConfigTypeDef * | sBreakInputConfig
 | ) |  |

Configures the break input source.

Parameters:
htim | TIM handle.
BreakInput Break input to configure This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
sBreakInputConfig | Break input source configuration
Return values:
HAL status

Definition at line 2135 of file stm32g0xx_hal_tim_ex.c.

References assert_param, TIMEx_BreakInputConfigTypeDef::Enable, __TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, IS_TIM_BREAKINPUTSOURCE, IS_TIM_BREAKINPUTSOURCE_POLARITY, IS_TIM_BREAKINPUTSOURCE_STATE, TIMEx_BreakInputConfigTypeDef::Polarity, TIMEx_BreakInputConfigTypeDef::Source, TIM_BREAKINPUT_BRK, TIM_BREAKINPUT_BRK2, TIM_BREAKINPUTSOURCE_BKIN, TIM_BREAKINPUTSOURCE_COMP1, TIM_BREAKINPUTSOURCE_COMP2, and TIM_BREAKINPUTSOURCE_COMP3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1818 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
The user should configure the DMA in his own software, in This function only the COMDE bit is set
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1931 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_IT, __HAL_TIM_ENABLE_DMA, assert_param, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_DMAError(), TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1874 of file stm32g0xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput
 | ) |  |

Disarm the designated break input (when it operates in bidirectional mode).

Parameters:
htim TIM handle.
BreakInput Break input to disarm This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
Note:
The break input can be disarmed only when it is configured in bidirectional mode and when when MOE is reset.
Purpose is to be able to have the input voltage back to high-state, whatever the time constant on the output .
Return values:
HAL status

Definition at line 2462 of file stm32g0xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, TIM_BREAKINPUT_BRK, and TIM_BREAKINPUT_BRK2.

HAL_StatusTypeDef HAL_TIMEx_GroupChannel5 | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channels
 | ) |  |

Group channel 5 and channel 1, 2 or 3.

Parameters:
htim | TIM handle.
Channels | specifies the reference signal(s) the OC5REF is combined with. This parameter can be any combination of the following values: TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
Return values:
HAL status

Definition at line 2424 of file stm32g0xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_GROUPCH5, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | const TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim | TIM handle.
sMasterConfig | pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 1980 of file stm32g0xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO2_SOURCE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterOutputTrigger2, TIM_MasterConfigTypeDef::MasterSlaveMode, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput
 | ) |  |

Arm the designated break input (when it operates in bidirectional mode).

Parameters:
htim TIM handle.
BreakInput Break input to arm This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
Note:
Arming is possible at anytime, even if fault is present.
Break input is automatically armed as soon as MOE bit is set.
Return values:
HAL status

Definition at line 2517 of file stm32g0xx_hal_tim_ex.c.

References assert_param, HAL_GetTick(), __TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, TIM_BREAKINPUT_BRK, TIM_BREAKINPUT_BRK2, and TIM_BREAKINPUT_REARM_TIMEOUT.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIMx Remapping input capabilities.

Parameters:
htim TIM handle.
Remap specifies the TIM remapping source. For TIM1, the parameter can take one of the following values:
  • TIM_TIM1_ETR_GPIO: TIM1 ETR is is connected to GPIO
  • TIM_TIM1_ETR_COMP1: TIM1 ETR is connected to COMP1 output
  • TIM_TIM1_ETR_COMP2: TIM1 ETR is connected to COMP2 output
  • TIM_TIM1_ETR_COMP3: TIM1 ETR is connected to COMP3 output (**)
  • TIM_TIM1_ETR_ADC1_AWD1: TIM1 ETR is connected to ADC1 AWD1
  • TIM_TIM1_ETR_ADC1_AWD2: TIM1 ETR is connected to ADC1 AWD2
  • TIM_TIM1_ETR_ADC1_AWD3: TIM1 ETR is connected to ADC1 AWD3
For TIM2, the parameter can take one of the following values: (*)
  • TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
  • TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
  • TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
  • TIM_TIM2_ETR_COMP3: TIM2_ETR is connected to COMP3 output (**)
  • TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
  • TIM_TIM2_ETR_MCO: TIM2_ETR is connected to MCO (**)
  • TIM_TIM2_ETR_MCO2: TIM2_ETR is connected to MCO2 (**)
For TIM3, the parameter can take one of the following values:
  • TIM_TIM3_ETR_GPIO TIM3_ETR is connected to GPIO
  • TIM_TIM3_ETR_COMP1 TIM3_ETR is connected to COMP1 output
  • TIM_TIM3_ETR_COMP2 TIM3_ETR is connected to COMP2 output
  • TIM_TIM3_ETR_COMP3 TIM3_ETR is connected to COMP3 output (**)
For TIM4, the parameter can take one of the following values:(*)
  • TIM_TIM4_ETR_GPIO TIM4_ETR is connected to GPIO
  • TIM_TIM4_ETR_COMP1 TIM4_ETR is connected to COMP1 output
  • TIM_TIM4_ETR_COMP2 TIM4_ETR is connected to COMP2 output
  • TIM_TIM4_ETR_COMP3 TIM4_ETR is connected to COMP3 output (**)
(*) Timer instance not available on all devices
(**) Value not defined in all devices.
Return values:
HAL status

Definition at line 2291 of file stm32g0xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_REMAP.

HAL_StatusTypeDef HAL_TIMEx_TISelection | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TISelection,
 |  | uint32_t | Channel
 | ) |  |

Select the timer input source.

Parameters:
htim | TIM handle.
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TI1 input channel
  • TIM_CHANNEL_2: TI2 input channel
  • TIM_CHANNEL_3: TI3 input channel
TISelection | specifies the timer input source

For TIM1 this parameter can be one of the following values:

  • TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
  • TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
  • TIM_TIM1_TI2_GPIO: TIM1 TI2 is connected to GPIO
  • TIM_TIM1_TI2_COMP2: TIM1 TI2 is connected to COMP2 output
  • TIM_TIM1_TI3_GPIO: TIM1 TI3 is connected to GPIO
  • TIM_TIM1_TI3_COMP3: TIM1 TI3 is connected to COMP3 output (**)

For TIM2, the parameter is one of the following values: (*)

  • TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
  • TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
  • TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO
  • TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output
  • TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO
  • TIM_TIM2_TI3_COMP3: TIM2 TI3 is connected to COMP3 output (**)

For TIM3, the parameter is one of the following values:

  • TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
  • TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
  • TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
  • TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output
  • TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO
  • TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output (**)

For TIM4, the parameter is one of the following values: (*)

  • TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
  • TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output
  • TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
  • TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output
  • TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO
  • TIM_TIM4_TI3_COMP3: TIM4 TI3 is connected to COMP3 output

For TIM14, the parameter is one of the following values:

  • TIM_TIM14_TI1_GPIO: TIM14 TI1 is connected to GPIO
  • TIM_TIM14_TI1_RTC: TIM14 TI1 is connected to RTC clock
  • TIM_TIM14_TI1_HSE_32: TIM14 TI1 is connected to HSE div 32
  • TIM_TIM14_TI1_MCO: TIM14 TI1 is connected to MCO
  • TIM_TIM14_TI1_MCO2: TIM14 TI1 is connected to MCO2 (**)

For TIM15, the parameter is one of the following values:

  • TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
  • TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1
  • TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1
  • TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
  • TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2
  • TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2

For TIM16, the parameter can have the following values:

  • TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
  • TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
  • TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
  • TIM_TIM16_TI1_RTC_WAKEUP: TIM16 TI1 is connected to TRC wakeup interrupt
  • TIM_TIM16_TI1_MCO2: TIM16 TI1 is connected to MCO2 (**)

For TIM17, the parameter can have the following values:

  • TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
  • TIM_TIM14_TI1_HSI: TIM17 TI1 is connected to HSI (**)
  • TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
  • TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
  • TIM_TIM17_TI1_MCO2: TIM17 TI1 is connected to MCO2 (**)

(*) Timer instance not available on all devices
(**) Value not defined in all devices.

Return values:
HAL status

Definition at line 2382 of file stm32g0xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_TISEL, TIM_CHANNEL_1, TIM_CHANNEL_2, and TIM_CHANNEL_3.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Callbacks functions

Functions
Extended Callbacks functions
TIM Extended Exported Functions

Extended Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.

Detailed Description

Extended Callbacks functions.

  ==============================================================================
                    ##### Extended Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extended TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_Break2Callback ( TIM_HandleTypeDef * htim )

Hall Break2 detection callback in non blocking mode.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2650 of file stm32g0xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2635 of file stm32g0xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_CommutCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2606 of file stm32g0xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationCplt().

void HAL_TIMEx_CommutHalfCpltCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2620 of file stm32g0xx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationHalfCplt().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Extended Peripheral State functions

Functions
Extended Peripheral State functions
TIM Extended Exported Functions

Extended Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIMEx_GetChannelNState (const TIM_HandleTypeDef *htim, uint32_t ChannelN)
Return actual state of the TIM complementary channel.

Detailed Description

Extended Peripheral State functions.

  ==============================================================================
                ##### Extended Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState | ( | const TIM_HandleTypeDef * | htim,
 |  | uint32_t | ChannelN
 | ) |  |

Return actual state of the TIM complementary channel.

Parameters:
htim TIM handle
ChannelN TIM Complementary channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
Return values:
TIM Complementary channel state

Definition at line 2698 of file stm32g0xx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, and TIM_CHANNEL_N_STATE_GET.

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( const TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface handle state.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL state

Definition at line 2683 of file stm32g0xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Private Functions

Functions
TIM Extended Private Functions
TIMEx

Functions

void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.
static void | TIM_DMADelayPulseNCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback (complementary channel).
static void | TIM_DMAErrorCCxN (DMA_HandleTypeDef *hdma)
TIM DMA error callback (complementary channel)
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.

Function Documentation

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
ChannelNState | specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 2870 of file stm32g0xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

static void TIM_DMADelayPulseNCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Delay Pulse complete callback (complementary channel).

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2766 of file stm32g0xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::Channel, DMA_NORMAL, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_PWM_PulseFinishedCallback(), __TIM_HandleTypeDef::hdma, __DMA_HandleTypeDef::Init, DMA_InitTypeDef::Mode, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_N_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

static void TIM_DMAErrorCCxN ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA error callback (complementary channel)

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2825 of file stm32g0xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::Channel, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_CHANNEL_STATE_READY, HAL_TIM_ErrorCallback(), __TIM_HandleTypeDef::hdma, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_N_STATE_SET, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, and TIM_DMA_ID_CC3.

Referenced by HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2727 of file stm32g0xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::CommutationCallback, HAL_TIM_STATE_READY, HAL_TIMEx_CommutCallback(), __TIM_HandleTypeDef::hdma, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), and HAL_TIMEx_ConfigCommutEvent_DMA().

void TIMEx_DMACommutationHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2746 of file stm32g0xx_hal_tim_ex.c.

References __TIM_HandleTypeDef::CommutationHalfCpltCallback, HAL_TIM_STATE_READY, HAL_TIMEx_CommutHalfCpltCallback(), __TIM_HandleTypeDef::hdma, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), and HAL_TIMEx_ConfigCommutEvent_DMA().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIM Extended Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32g0xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 47 of file stm32g0xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 58 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 55 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 49 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 52 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim_ex.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIMEx_BreakInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIMEx_BreakInputConfigTypeDef Struct Reference
TIM Extended Exported Types

TIM Break/Break2 input configuration. More...

#include <stm32g0xx_hal_tim_ex.h>

Data Fields

uint32_t | Source
uint32_t | Enable
uint32_t | Polarity

Detailed Description

TIM Break/Break2 input configuration.

Definition at line 65 of file stm32g0xx_hal_tim_ex.h.

Field Documentation

uint32_t TIMEx_BreakInputConfigTypeDef::Enable

Specifies whether or not the break input source is enabled. This parameter can be a value of TIM Extended Break input source enabling

Definition at line 69 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Polarity

Specifies the break input source polarity. This parameter can be a value of TIM Extended Break input polarity

Definition at line 71 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Source

Specifies the source of the timer break input. This parameter can be a value of TIM Extended Break input source

Definition at line 67 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_tim_ex.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Remapping

Defines
TIM Extended Remapping
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
#define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
#define | TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to COMP3 output */
#define | TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define | TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
#define | TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
#define | TIM_TIM2_ETR_LSE (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to LSE */
#define | TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to MCO */
#define | TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to MCO2 */
#define | TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP3 output */
#define | TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define | TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */
#define | TIM_TIM3_ETR_COMP2 TIM3_AF1_ETRSEL_1 /* !< TIM3_ETR is connected to COMP2 output */
#define | TIM_TIM3_ETR_COMP3 (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0) /* !< TIM3_ETR is connected to COMP3 output */
#define | TIM_TIM4_ETR_GPIO 0x00000000U /* !< TIM4_ETR is connected to GPIO */
#define | TIM_TIM4_ETR_COMP1 TIM4_AF1_ETRSEL_0 /* !< TIM4_ETR is connected to COMP1 output */
#define | TIM_TIM4_ETR_COMP2 TIM4_AF1_ETRSEL_1 /* !< TIM4_ETR is connected to COMP2 output */
#define | TIM_TIM4_ETR_COMP3 (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0) /* !< TIM4_ETR is connected to COMP3 output */

Define Documentation

#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */

Definition at line 93 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /* !< TIM1_ETR is connected to ADC1 AWD2 */

Definition at line 94 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */

Definition at line 95 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */

Definition at line 90 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */

Definition at line 91 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to COMP3 output */

Definition at line 97 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */

Definition at line 88 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */

Definition at line 101 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */

Definition at line 102 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP3 output */

Definition at line 107 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */

Definition at line 100 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_LSE (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to LSE */

Definition at line 103 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to MCO */

Definition at line 105 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to MCO2 */

Definition at line 106 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */

Definition at line 113 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP2 TIM3_AF1_ETRSEL_1 /* !< TIM3_ETR is connected to COMP2 output */

Definition at line 114 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP3 (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0) /* !< TIM3_ETR is connected to COMP3 output */

Definition at line 117 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */

Definition at line 111 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_COMP1 TIM4_AF1_ETRSEL_0 /* !< TIM4_ETR is connected to COMP1 output */

Definition at line 123 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_COMP2 TIM4_AF1_ETRSEL_1 /* !< TIM4_ETR is connected to COMP2 output */

Definition at line 124 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_COMP3 (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0) /* !< TIM4_ETR is connected to COMP3 output */

Definition at line 127 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_ETR_GPIO 0x00000000U /* !< TIM4_ETR is connected to GPIO */

Definition at line 121 of file stm32g0xx_hal_tim_ex.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Break input

Defines
TIM Extended Break input
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUT_BRK 0x00000001U
#define | TIM_BREAKINPUT_BRK2 0x00000002U

Define Documentation

#define TIM_BREAKINPUT_BRK 0x00000001U

Timer break input

Definition at line 137 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_DisarmBreakInput(), and HAL_TIMEx_ReArmBreakInput().

#define TIM_BREAKINPUT_BRK2 0x00000002U

Timer break2 input

Definition at line 138 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_DisarmBreakInput(), and HAL_TIMEx_ReArmBreakInput().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Break input source

Defines
TIM Extended Break input source
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */

Define Documentation

#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */

Definition at line 146 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */

Definition at line 148 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */

Definition at line 149 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */

Definition at line 152 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Break input source enabling

Defines
TIM Extended Break input source enabling
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U
#define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U

Define Documentation

#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U

Break input source is disabled

Definition at line 161 of file stm32g0xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U

Break input source is enabled

Definition at line 162 of file stm32g0xx_hal_tim_ex.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Break input polarity

Defines
TIM Extended Break input polarity
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U

Define Documentation

#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U

Break input source is active_high

Definition at line 171 of file stm32g0xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U

Break input source is active low

Definition at line 170 of file stm32g0xx_hal_tim_ex.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Timer input selection

Defines
TIM Extended Timer input selection
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */
#define | TIM_TIM1_TI1_COMP1 0x00000001U /* !< TIM1_TI1 is connected to COMP1 OUT */
#define | TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */
#define | TIM_TIM1_TI2_COMP2 0x00000100U /* !< TIM1_TI2 is connected to COMP2 OUT */
#define | TIM_TIM1_TI3_GPIO 0x00000000U /* !< TIM1_TI3 is connected to GPIO */
#define | TIM_TIM1_TI3_COMP3 0x00010000U /* !< TIM1_TI3 is connected to COMP3 OUT */
#define | TIM_TIM2_TI1_GPIO 0x00000000U /* !< TIM2_TI1 is connected to GPIO */
#define | TIM_TIM2_TI1_COMP1 0x00000001U /* !< TIM2_TI1 is connected to COMP1 OUT */
#define | TIM_TIM2_TI2_GPIO 0x00000000U /* !< TIM2_TI2 is connected to GPIO */
#define | TIM_TIM2_TI2_COMP2 0x00000100U /* !< TIM2_TI2 is connected to COMP2 OUT */
#define | TIM_TIM2_TI3_GPIO 0x00000000U /* !< TIM2_TI3 is connected to GPIO */
#define | TIM_TIM2_TI3_COMP3 0x00010000U /* !< TIM2_TI3 is connected to COMP3 OUT */
#define | TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */
#define | TIM_TIM3_TI1_COMP1 0x00000001U /* !< TIM3_TI1 is connected to COMP1 OUT */
#define | TIM_TIM3_TI2_GPIO 0x00000000U /* !< TIM3_TI2 is connected to GPIO */
#define | TIM_TIM3_TI2_COMP2 0x00000100U /* !< TIM3_TI2 is connected to COMP2 OUT */
#define | TIM_TIM3_TI3_GPIO 0x00000000U /* !< TIM3_TI3 is connected to GPIO */
#define | TIM_TIM3_TI3_COMP3 0x00010000U /* !< TIM3_TI3 is connected to COMP3 OUT */
#define | TIM_TIM4_TI1_GPIO 0x00000000U /* !< TIM4_TI1 is connected to GPIO */
#define | TIM_TIM4_TI1_COMP1 0x00000001U /* !< TIM4_TI1 is connected to COMP1 OUT */
#define | TIM_TIM4_TI2_GPIO 0x00000000U /* !< TIM4_TI2 is connected to GPIO */
#define | TIM_TIM4_TI2_COMP2 0x00000100U /* !< TIM4_TI2 is connected to COMP2 OUT */
#define | TIM_TIM4_TI3_GPIO 0x00000000U /* !< TIM4_TI3 is connected to GPIO */
#define | TIM_TIM4_TI3_COMP3 0x00010000U /* !< TIM4_TI3 is connected to COMP3 OUT */
#define | TIM_TIM14_TI1_GPIO 0x00000000U /* !< TIM14_TI1 is connected to GPIO */
#define | TIM_TIM14_TI1_RTC 0x00000001U /* !< TIM14_TI1 is connected to RTC clock */
#define | TIM_TIM14_TI1_HSE_32 0x00000002U /* !< TIM14_TI1 is connected to HSE div 32 */
#define | TIM_TIM14_TI1_MCO 0x00000003U /* !< TIM14_TI1 is connected to MCO */
#define | TIM_TIM14_TI1_MCO2 0x00000004U /* !< TIM14_TI1 is connected to MCO2 */
#define | TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
#define | TIM_TIM15_TI1_TIM2_CH1 0x00000001U /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define | TIM_TIM15_TI1_TIM3_CH1 0x00000002U /* !< TIM15_TI1 is connected to TIM3 CH1 */
#define | TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */
#define | TIM_TIM15_TI2_TIM2_CH2 0x00000100U /* !< TIM15_TI2 is connected to TIM2 CH2 */
#define | TIM_TIM15_TI2_TIM3_CH2 0x00000200U /* !< TIM15_TI2 is connected to TIM3 CH2 */
#define | TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to GPIO */
#define | TIM_TIM16_TI1_LSI 0x00000001U /* !< TIM16_TI1 is connected to LSI */
#define | TIM_TIM16_TI1_LSE 0x00000002U /* !< TIM16_TI1 is connected to LSE */
#define | TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /* !< TIM16_TI1 is connected to TRC wakeup interrupt */
#define | TIM_TIM16_TI1_MCO2 0x00000004U /* !< TIM16_TI1 is connected to MCO2 */
#define | TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to GPIO */
#define | TIM_TIM17_TI1_HSI48 0x00000001U /* !< TIM17_TI1 is connected to HSI48/256 */
#define | TIM_TIM17_TI1_HSE_32 0x00000002U /* !< TIM17_TI1 is connected to HSE div 32 */
#define | TIM_TIM17_TI1_MCO 0x00000003U /* !< TIM17_TI1 is connected to MCO */
#define | TIM_TIM17_TI1_MCO2 0x00000004U /* !< TIM17_TI1 is connected to MCO2 */

Define Documentation

#define TIM_TIM14_TI1_GPIO 0x00000000U /* !< TIM14_TI1 is connected to GPIO */

Definition at line 239 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM14_TI1_HSE_32 0x00000002U /* !< TIM14_TI1 is connected to HSE div 32 */

Definition at line 241 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM14_TI1_MCO 0x00000003U /* !< TIM14_TI1 is connected to MCO */

Definition at line 242 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM14_TI1_MCO2 0x00000004U /* !< TIM14_TI1 is connected to MCO2 */

Definition at line 244 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM14_TI1_RTC 0x00000001U /* !< TIM14_TI1 is connected to RTC clock */

Definition at line 240 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */

Definition at line 248 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_TIM2_CH1 0x00000001U /* !< TIM15_TI1 is connected to TIM2 CH1 */

Definition at line 249 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_TIM3_CH1 0x00000002U /* !< TIM15_TI1 is connected to TIM3 CH1 */

Definition at line 250 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */

Definition at line 252 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_TIM2_CH2 0x00000100U /* !< TIM15_TI2 is connected to TIM2 CH2 */

Definition at line 253 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM15_TI2_TIM3_CH2 0x00000200U /* !< TIM15_TI2 is connected to TIM3 CH2 */

Definition at line 254 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to GPIO */

Definition at line 257 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_LSE 0x00000002U /* !< TIM16_TI1 is connected to LSE */

Definition at line 259 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_LSI 0x00000001U /* !< TIM16_TI1 is connected to LSI */

Definition at line 258 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_MCO2 0x00000004U /* !< TIM16_TI1 is connected to MCO2 */

Definition at line 262 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /* !< TIM16_TI1 is connected to TRC wakeup interrupt */

Definition at line 260 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to GPIO */

Definition at line 265 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_HSE_32 0x00000002U /* !< TIM17_TI1 is connected to HSE div 32 */

Definition at line 269 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_HSI48 0x00000001U /* !< TIM17_TI1 is connected to HSI48/256 */

Definition at line 267 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_MCO 0x00000003U /* !< TIM17_TI1 is connected to MCO */

Definition at line 270 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_MCO2 0x00000004U /* !< TIM17_TI1 is connected to MCO2 */

Definition at line 272 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP1 0x00000001U /* !< TIM1_TI1 is connected to COMP1 OUT */

Definition at line 181 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */

Definition at line 179 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_TI2_COMP2 0x00000100U /* !< TIM1_TI2 is connected to COMP2 OUT */

Definition at line 186 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */

Definition at line 184 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_TI3_COMP3 0x00010000U /* !< TIM1_TI3 is connected to COMP3 OUT */

Definition at line 191 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM1_TI3_GPIO 0x00000000U /* !< TIM1_TI3 is connected to GPIO */

Definition at line 189 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_TI1_COMP1 0x00000001U /* !< TIM2_TI1 is connected to COMP1 OUT */

Definition at line 196 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_TI1_GPIO 0x00000000U /* !< TIM2_TI1 is connected to GPIO */

Definition at line 195 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_TI2_COMP2 0x00000100U /* !< TIM2_TI2 is connected to COMP2 OUT */

Definition at line 199 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_TI2_GPIO 0x00000000U /* !< TIM2_TI2 is connected to GPIO */

Definition at line 198 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_TI3_COMP3 0x00010000U /* !< TIM2_TI3 is connected to COMP3 OUT */

Definition at line 203 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM2_TI3_GPIO 0x00000000U /* !< TIM2_TI3 is connected to GPIO */

Definition at line 201 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP1 0x00000001U /* !< TIM3_TI1 is connected to COMP1 OUT */

Definition at line 209 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */

Definition at line 207 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_TI2_COMP2 0x00000100U /* !< TIM3_TI2 is connected to COMP2 OUT */

Definition at line 214 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_TI2_GPIO 0x00000000U /* !< TIM3_TI2 is connected to GPIO */

Definition at line 212 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_TI3_COMP3 0x00010000U /* !< TIM3_TI3 is connected to COMP3 OUT */

Definition at line 219 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM3_TI3_GPIO 0x00000000U /* !< TIM3_TI3 is connected to GPIO */

Definition at line 217 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_TI1_COMP1 0x00000001U /* !< TIM4_TI1 is connected to COMP1 OUT */

Definition at line 225 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_TI1_GPIO 0x00000000U /* !< TIM4_TI1 is connected to GPIO */

Definition at line 223 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_TI2_COMP2 0x00000100U /* !< TIM4_TI2 is connected to COMP2 OUT */

Definition at line 230 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_TI2_GPIO 0x00000000U /* !< TIM4_TI2 is connected to GPIO */

Definition at line 228 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_TI3_COMP3 0x00010000U /* !< TIM4_TI3 is connected to COMP3 OUT */

Definition at line 235 of file stm32g0xx_hal_tim_ex.h.

#define TIM_TIM4_TI3_GPIO 0x00000000U /* !< TIM4_TI3 is connected to GPIO */

Definition at line 233 of file stm32g0xx_hal_tim_ex.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Exported Macros

TIM Extended Exported Macros
TIMEx
Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Private Macros

Defines
TIM Extended Private Macros
TIMEx

Defines

#define | IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)
#define | IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))

Define Documentation

#define IS_TIM_BREAKINPUT ( __BREAKINPUT__ )
Value:
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))

Definition at line 299 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_DisarmBreakInput(), and HAL_TIMEx_ReArmBreakInput().

#define IS_TIM_BREAKINPUTSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3))

Definition at line 303 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))

Definition at line 318 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))

Definition at line 315 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_REMAP ( __REMAP__ ) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))

Definition at line 297 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

#define IS_TIM_TISEL ( __TISEL__ ) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))

Definition at line 321 of file stm32g0xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_TISelection().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define | USART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define | LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define | UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define | UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Define Documentation

#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */

Definition at line 187 of file stm32g0xx_hal_uart.c.

Referenced by UART_SetConfig().

#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */

Definition at line 186 of file stm32g0xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Definition at line 190 of file stm32g0xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */

Definition at line 189 of file stm32g0xx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
                                      USART_CR1_OVER8 | USART_CR1_FIFOEN))

UART or USART CR1 fields of parameters set by UART_SetConfig API

Definition at line 180 of file stm32g0xx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
                                      USART_CR3_RXFTCFG))

UART or USART CR3 fields of parameters set by UART_SetConfig API

Definition at line 183 of file stm32g0xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_RegisterRxEventCallback (UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
Register a User UART Rx Event Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterRxEventCallback (UART_HandleTypeDef *huart)
UnRegister the UART Rx Event Callback UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
    and UART multiprocessor mode configuration procedures (details for the procedures
    are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 380 of file stm32g0xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_InitCallbacksToDefault(), and UART_SetConfig().

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
BreakDetectLength Specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
Return values:
HAL status

Definition at line 453 of file stm32g0xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_InitTypeDef::OverSampling, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_InitCallbacksToDefault(), UART_OVERSAMPLING_8, UART_SetConfig(), UART_WORDLENGTH_8B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart | UART handle.
Address | UART node address (4-, 6-, 7- or 8-bit long).
WakeUpMethod Specifies the UART wakeup method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
Note:
If the user resorts to idle line detection wake up, the Address parameter is useless and ignored by the initialization function.
If the user resorts to address mark wake up, the address length detection is configured by default to 4 bits only. For the UART to be able to manage 6-, 7- or 8-bit long addresses detection, the API HAL_MultiProcessorEx_AddressLength_Set() must be called after HAL_MultiProcessor_Init().
Return values:
HAL status

Definition at line 550 of file stm32g0xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, IS_UART_WAKEUPMETHOD, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR2_ADDRESS_LSB_POS, UART_InitCallbacksToDefault(), UART_SetConfig(), and UART_WAKEUPMETHOD_ADDRESSMARK.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 624 of file stm32g0xx_hal_uart.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 307 of file stm32g0xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_HWCONTROL_NONE, UART_InitCallbacksToDefault(), and UART_SetConfig().

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 686 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_DeInit(), and HAL_UART_UnRegisterCallback().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

Initialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 671 of file stm32g0xx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UART_UnRegisterCallback().

HAL_StatusTypeDef HAL_UART_RegisterCallback | ( | UART_HandleTypeDef * | huart,
 |  | HAL_UART_CallbackIDTypeDef | CallbackID,
 |  | pUART_CallbackTypeDef | pCallback
 | ) |  |

Register a User UART Callback To be used instead of the weak predefined callback.

Parameters:
huart | uart handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_UART_ERROR_CB_ID Error Callback ID
  • HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
  • HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_UART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 719 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ABORT_COMPLETE_CB_ID, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_UART_ERROR_CB_ID, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_MSPDEINIT_CB_ID, HAL_UART_MSPINIT_CB_ID, HAL_UART_RX_COMPLETE_CB_ID, HAL_UART_RX_FIFO_FULL_CB_ID, HAL_UART_RX_HALFCOMPLETE_CB_ID, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, HAL_UART_TX_COMPLETE_CB_ID, HAL_UART_TX_FIFO_EMPTY_CB_ID, HAL_UART_TX_HALFCOMPLETE_CB_ID, HAL_UART_WAKEUP_CB_ID, __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::MspInitCallback, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback | ( | UART_HandleTypeDef * | huart,
 |  | pUART_RxEventCallbackTypeDef | pCallback
 | ) |  |

Register a User UART Rx Event Callback To be used instead of the weak predefined callback.

Parameters:
huart | Uart handle
pCallback | Pointer to the Rx Event Callback function
Return values:
HAL status

Definition at line 957 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_STATE_READY, and __UART_HandleTypeDef::RxEventCallback.

HAL_StatusTypeDef HAL_UART_UnRegisterCallback | ( | UART_HandleTypeDef * | huart,
 |  | HAL_UART_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Parameters:
huart uart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_UART_ERROR_CB_ID Error Callback ID
  • HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
  • HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_UART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 848 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ABORT_COMPLETE_CB_ID, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ERROR_CB_ID, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_ErrorCallback(), HAL_UART_MspDeInit(), HAL_UART_MSPDEINIT_CB_ID, HAL_UART_MspInit(), HAL_UART_MSPINIT_CB_ID, HAL_UART_RX_COMPLETE_CB_ID, HAL_UART_RX_FIFO_FULL_CB_ID, HAL_UART_RX_HALFCOMPLETE_CB_ID, HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_STATE_READY, HAL_UART_STATE_RESET, HAL_UART_TX_COMPLETE_CB_ID, HAL_UART_TX_FIFO_EMPTY_CB_ID, HAL_UART_TX_HALFCOMPLETE_CB_ID, HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UART_WAKEUP_CB_ID, HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::MspInitCallback, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback ( UART_HandleTypeDef * huart )

UnRegister the UART Rx Event Callback UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback.

Parameters:
huart Uart handle
Return values:
HAL status

Definition at line 994 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), and __UART_HandleTypeDef::RxEventCallback.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
__weak void | HAL_UARTEx_RxEventCallback (UART_HandleTypeDef *huart, uint16_t Size)
Reception Event Callback (Rx event notification called after use of advanced reception service).

Detailed Description

UART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two mode of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
           The HAL status of all data processing is returned by the same function
           after finishing transfer.
       (+) Non-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (+) HAL_UART_Transmit()
        (+) HAL_UART_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_UART_Transmit_IT()
        (+) HAL_UART_Receive_IT()
        (+) HAL_UART_IRQHandler()

    (#) Non-Blocking mode API's with DMA are :
        (+) HAL_UART_Transmit_DMA()
        (+) HAL_UART_Receive_DMA()
        (+) HAL_UART_DMAPause()
        (+) HAL_UART_DMAResume()
        (+) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (+) HAL_UART_TxHalfCpltCallback()
        (+) HAL_UART_TxCpltCallback()
        (+) HAL_UART_RxHalfCpltCallback()
        (+) HAL_UART_RxCpltCallback()
        (+) HAL_UART_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_UART_Abort()
        (+) HAL_UART_AbortTransmit()
        (+) HAL_UART_AbortReceive()
        (+) HAL_UART_Abort_IT()
        (+) HAL_UART_AbortTransmit_IT()
        (+) HAL_UART_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_UART_AbortCpltCallback()
        (+) HAL_UART_AbortTransmitCpltCallback()
        (+) HAL_UART_AbortReceiveCpltCallback()

    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
        reception services:
        (+) HAL_UARTEx_RxEventCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
           in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
           to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
           Transfer is kept ongoing on UART side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
           user callback is executed.

    -@- In the Half duplex communication, it is forbidden to run the transmit
        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_Abort ( UART_HandleTypeDef * huart )

Abort ongoing transfers (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1736 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_FIFOMODE_ENABLE, UART_RXDATA_FLUSH_REQUEST, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Abort_IT ( UART_HandleTypeDef * huart )

Abort ongoing transfers (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1966 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_FIFOMODE_ENABLE, UART_RXDATA_FLUSH_REQUEST, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2708 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_Abort_IT(), HAL_UART_UnRegisterCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_AbortReceive ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1898 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortReceive_IT ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2210 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortReceiveCpltCallback, HAL_DMA_Abort_IT(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxOnlyAbortCallback(), UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortReceiveCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Receive Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2738 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_UnRegisterCallback(), UART_DMARxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_AbortTransmit ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1839 of file stm32g0xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxXferCount, UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortTransmit_IT ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2119 of file stm32g0xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, UART_DMATxOnlyAbortCallback(), UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortTransmitCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2723 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_AbortTransmit_IT(), HAL_UART_UnRegisterCallback(), UART_DMATxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pause the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1600 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resume the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1630 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::RxState, UART_CLEAR_OREF, and UART_PARITY_NONE.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stop the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1661 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, UART_EndRxTransfer(), and UART_EndTxTransfer().

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2693 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

Handle UART interrupt request.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2303 of file stm32g0xx_hal_uart.c.

References __HAL_DMA_GET_COUNTER, __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ERROR_RTO, HAL_UART_ErrorCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_IDLE, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::hdmarx, __DMA_HandleTypeDef::Instance, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxISR, UART_CLEAR_FEF, UART_CLEAR_IDLEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_CLEAR_RTOF, UART_CLEAR_WUF, UART_DMAAbortOnError(), UART_EndRxTransfer(), UART_EndTransmit_IT(), __UART_HandleTypeDef::WakeupCallback, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1228 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1553 of file stm32g0xx_hal_uart.c.

References HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, UART_PARITY_NONE, UART_Start_Receive_DMA(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1410 of file stm32g0xx_hal_uart.c.

References HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, UART_PARITY_NONE, UART_Start_Receive_IT(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2663 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMAReceiveCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2678 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMARxHalfCplt(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
When FIFO mode is enabled, writing a data in the TDR register adds one data to the TXFIFO. Write operations to the TDR register are performed when TXFNF flag is set. From hardware perspective, TXFNF flag and TXE are mapped on the same bit-field.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1127 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1467 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pTxBuffPtr, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_CLEAR_TCF, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), UART_PARITY_NONE, UART_WORDLENGTH_9B, UART_InitTypeDef::WordLength, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | const uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1326 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pTxBuffPtr, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_FIFOMODE_ENABLE, UART_PARITY_NONE, UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2633 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_InitCallbacksToDefault().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2648 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMATxHalfCplt(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_RxEventCallback | ( | UART_HandleTypeDef * | huart,
 |  | uint16_t | Size
 | ) |  |

Reception Event Callback (Rx event notification called after use of advanced reception service).

Parameters:
huart | UART handle
Size | Number of data available in application reception buffer (indicates a position in reception buffer until which, data are available)
Return values:
None

Definition at line 2755 of file stm32g0xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterRxEventCallback(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.

Detailed Description

UART control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the UART.
     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
     (+) UART_SetConfig() API configures the UART peripheral
     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
     (+) HAL_LIN_SendBreak() API transmits the break characters

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enable the UART receiver and disable the UART transmitter.

Parameters:
huart UART handle.
Return values:
HAL status.

Definition at line 2967 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enable the UART transmitter and disable the UART receiver.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2944 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmit break characters.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2991 of file stm32g0xx_hal_uart.c.

References __HAL_UART_SEND_REQ, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_SENDBREAK_REQUEST.

HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode ( UART_HandleTypeDef * huart )

Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2914 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode ( UART_HandleTypeDef * huart )

Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2894 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_CheckIdleState().

void HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enter UART mute mode (means UART actually enters mute mode).

Note:
To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
Parameters:
huart UART handle.
Return values:
None

Definition at line 2934 of file stm32g0xx_hal_uart.c.

References __HAL_UART_SEND_REQ, and UART_MUTE_MODE_REQUEST.

HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout ( UART_HandleTypeDef * huart )

Disable the UART receiver timeout feature.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2856 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout ( UART_HandleTypeDef * huart )

Enable the UART receiver timeout feature.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2818 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

void HAL_UART_ReceiverTimeout_Config | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | TimeoutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
huart | Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
TimeoutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 2803 of file stm32g0xx_hal_uart.c.

References assert_param, __UART_HandleTypeDef::Instance, and IS_UART_RECEIVER_TIMEOUT_VALUE.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
UART Exported Functions

UART Peripheral State functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (const UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (const UART_HandleTypeDef *huart)
Return the UART handle error code.

Detailed Description

UART Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the UART handle state.
      (+) Return the UART handle error code

Function Documentation

uint32_t HAL_UART_GetError ( const UART_HandleTypeDef * huart )

Return the UART handle error code.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 3052 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( const UART_HandleTypeDef * huart )

Return the UART handle state.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
HAL state

Definition at line 3036 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, and __UART_HandleTypeDef::RxState.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Private Functions

Functions
UART Private Functions
UART

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | UART_TxISR_8BIT (UART_HandleTypeDef *huart)
TX interrupt handler for 7 or 8 bits data word length .
static void | UART_TxISR_16BIT (UART_HandleTypeDef *huart)
TX interrupt handler for 9 bits data word length.
static void | UART_TxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_TxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
static void | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static void | UART_RxISR_8BIT (UART_HandleTypeDef *huart)
RX interrupt handler for 7 or 8 bits data word length .
static void | UART_RxISR_16BIT (UART_HandleTypeDef *huart)
RX interrupt handler for 9 bits data word length .
static void | UART_RxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_RxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles UART Communication Timeout.
HAL_StatusTypeDef | UART_Start_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in interrupt mode.
HAL_StatusTypeDef | UART_Start_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in DMA mode.

Function Documentation

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart UART handle.
Return values:
None

Definition at line 3309 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, __UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 3383 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_RXEVENT_TC, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3862 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCallback, HAL_UART_ErrorCallback(), __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxXferCount, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_IRQHandler().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3822 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_EndRxTransfer(), and UART_EndTxTransfer().

Referenced by HAL_UART_Transmit_DMA(), and UART_Start_Receive_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3723 of file stm32g0xx_hal_uart.c.

References HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __DMA_HandleTypeDef::Instance, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, and __UART_HandleTypeDef::RxXferSize.

Referenced by UART_Start_Receive_DMA().

static void UART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3940 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3784 of file stm32g0xx_hal_uart.c.

References HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_HT, HAL_UART_RxHalfCpltCallback(), HAL_UARTEx_RxEventCallback(), __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxHalfCpltCallback, and __UART_HandleTypeDef::RxXferSize.

Referenced by UART_Start_Receive_DMA().

static void UART_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 4025 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortReceiveCpltCallback, HAL_UART_AbortReceiveCpltCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __TIM_HandleTypeDef::hdma, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and UART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_AbortReceive_IT().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3671 of file stm32g0xx_hal_uart.c.

References HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::TxCpltCallback, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3885 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_STANDARD, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3705 of file stm32g0xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __UART_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3992 of file stm32g0xx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::TxXferCount, UART_FIFOMODE_ENABLE, and UART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_AbortTransmit_IT().

static void UART_EndRxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 3645 of file stm32g0xx_hal_uart.c.

References HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxISR, and __UART_HandleTypeDef::RxState.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), and UART_DMAError().

static void UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
huart pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 4200 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxCpltCallback, and __UART_HandleTypeDef::TxISR.

Referenced by HAL_UART_IRQHandler().

static void UART_EndTxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 3629 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

Referenced by HAL_UART_DMAStop(), and UART_DMAError().

void UART_InitCallbacksToDefault ( UART_HandleTypeDef * huart )

Initialize the callbacks to their default values.

Parameters:
huart UART handle.
Return values:
none

Definition at line 3074 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ErrorCallback(), HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UARTEx_RxEventCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_RxISR_16BIT ( UART_HandleTypeDef * huart ) [static]

RX interrupt handler for 9 bits data word length .

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 4306 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __HAL_UART_SEND_REQ, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_IDLEF, UART_FLAG_IDLE, and UART_RXDATA_FLUSH_REQUEST.

Referenced by UART_RxISR_16BIT_FIFOEN(), and UART_Start_Receive_IT().

static void UART_RxISR_16BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

RX interrupt handler for 9 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 4541 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_FEF, UART_CLEAR_IDLEF, UART_CLEAR_NEF, UART_CLEAR_PEF, UART_FLAG_IDLE, UART_RXDATA_FLUSH_REQUEST, and UART_RxISR_16BIT().

Referenced by UART_Start_Receive_IT().

static void UART_RxISR_8BIT ( UART_HandleTypeDef * huart ) [static]

RX interrupt handler for 7 or 8 bits data word length .

Parameters:
huart UART handle.
Return values:
None

Definition at line 4225 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __HAL_UART_SEND_REQ, HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_IDLEF, UART_FLAG_IDLE, and UART_RXDATA_FLUSH_REQUEST.

Referenced by UART_RxISR_8BIT_FIFOEN(), and UART_Start_Receive_IT().

static void UART_RxISR_8BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 4389 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RxCpltCallback(), HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, HAL_UARTEx_RxEventCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxEventCallback, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_FEF, UART_CLEAR_IDLEF, UART_CLEAR_NEF, UART_CLEAR_PEF, UART_FLAG_IDLE, UART_RXDATA_FLUSH_REQUEST, and UART_RxISR_8BIT().

Referenced by UART_Start_Receive_IT().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 3098 of file stm32g0xx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, UART_InitTypeDef::ClockPrescaler, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, IS_LPUART_STOPBITS, IS_UART_BAUDRATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_OVERSAMPLING, IS_UART_PARITY, IS_UART_PRESCALER, IS_UART_STOPBITS, IS_UART_WORD_LENGTH, LPUART_BRR_MAX, LPUART_BRR_MIN, LSE_VALUE, UART_InitTypeDef::Mode, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbTxDataToProcess, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, __UART_HandleTypeDef::RxISR, UART_InitTypeDef::StopBits, __UART_HandleTypeDef::TxISR, UART_BRR_MAX, UART_BRR_MIN, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PCLK1, UART_CLOCKSOURCE_SYSCLK, UART_DIV_LPUART, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_GETCLOCKSOURCE, UART_INSTANCE_LOWPOWER, UART_OVERSAMPLING_8, UARTPrescTable, USART_CR1_FIELDS, USART_CR3_FIELDS, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_Start_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Start Receive operation in DMA mode.

Note:
This function could be called by all HAL UART API providing reception in DMA mode.
When calling this function, parameters validity is considered as already checked, i.e. Rx State, buffer address, ... UART Handle is assumed as Locked.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 3572 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_PARITY_NONE, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_UART_Receive_DMA(), and HAL_UARTEx_ReceiveToIdle_DMA().

HAL_StatusTypeDef UART_Start_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Start Receive operation in interrupt mode.

Note:
This function could be called by all HAL UART API providing reception in Interrupt mode.
When calling this function, parameters validity is considered as already checked, i.e. Rx State, buffer address, ... UART Handle is assumed as Locked.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 3500 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbRxDataToProcess, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_FIFOMODE_ENABLE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_Receive_IT(), and HAL_UARTEx_ReceiveToIdle_IT().

static void UART_TxISR_16BIT ( UART_HandleTypeDef * huart ) [static]

TX interrupt handler for 9 bits data word length.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 4087 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_16BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

TX interrupt handler for 9 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 4159 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbTxDataToProcess, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_8BIT ( UART_HandleTypeDef * huart ) [static]

TX interrupt handler for 7 or 8 bits data word length .

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 4058 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_8BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 4119 of file stm32g0xx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbTxDataToProcess, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  |

This function handles UART Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
huart | UART handle.
Flag | Specifies the UART flag to check
Status | The actual Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3436 of file stm32g0xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_RTO, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, UART_CLEAR_RTOF, and UART_FLAG_RTOF.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Exported Types

Data Structures | Typedefs | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | __UART_HandleTypeDef
UART handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_UART_StateTypeDef
HAL UART State definition.
typedef uint32_t | HAL_UART_RxTypeTypeDef
HAL UART Reception type definition.
typedef uint32_t | HAL_UART_RxEventTypeTypeDef
HAL UART Rx Event type definition.
typedef struct __UART_HandleTypeDef | UART_HandleTypeDef
UART handle Structure definition.
typedef void(* | pUART_CallbackTypeDef )(UART_HandleTypeDef *huart)
HAL UART Callback pointer definition.
typedef void(* | pUART_RxEventCallbackTypeDef )(struct __UART_HandleTypeDef *huart, uint16_t Pos)

Enumerations

enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00U, UART_CLOCKSOURCE_HSI = 0x02U, UART_CLOCKSOURCE_SYSCLK = 0x04U, UART_CLOCKSOURCE_LSE = 0x08U,
UART_CLOCKSOURCE_UNDEFINED = 0x10U
}
UART clock sources definition. More...
enum HAL_UART_CallbackIDTypeDef {
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_UART_TX_COMPLETE_CB_ID = 0x01U, HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_UART_RX_COMPLETE_CB_ID = 0x03U,
HAL_UART_ERROR_CB_ID = 0x04U, HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_UART_WAKEUP_CB_ID = 0x08U, HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, HAL_UART_MSPINIT_CB_ID = 0x0BU,
HAL_UART_MSPDEINIT_CB_ID = 0x0CU
}
HAL UART Callback ID enumeration definition. More...

Typedef Documentation

typedef uint32_t HAL_UART_RxEventTypeTypeDef

HAL UART Rx Event type definition.

Note:
HAL UART Rx Event type value aims to identify which type of Event has occurred leading to call of the RxEvent callback. This parameter can be a value of UART RxEvent type values : HAL_UART_RXEVENT_TC = 0x00U, HAL_UART_RXEVENT_HT = 0x01U, HAL_UART_RXEVENT_IDLE = 0x02U,

Definition at line 213 of file stm32g0xx_hal_uart.h.

typedef uint32_t HAL_UART_RxTypeTypeDef

HAL UART Reception type definition.

Note:
HAL UART Reception type value aims to identify which type of Reception is ongoing. This parameter can be a value of UART Reception type values : HAL_UART_RECEPTION_STANDARD = 0x00U, HAL_UART_RECEPTION_TOIDLE = 0x01U, HAL_UART_RECEPTION_TORTO = 0x02U, HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,

Definition at line 202 of file stm32g0xx_hal_uart.h.

typedef uint32_t HAL_UART_StateTypeDef

HAL UART State definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState (see UART State Code Definition).
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 179 of file stm32g0xx_hal_uart.h.

typedef void(* pUART_CallbackTypeDef)(UART_HandleTypeDef *huart)

HAL UART Callback pointer definition.

pointer to an UART callback function

Definition at line 316 of file stm32g0xx_hal_uart.h.

typedef void(* pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos)

pointer to a UART Rx Event specific callback function

Definition at line 318 of file stm32g0xx_hal_uart.h.

typedef struct __UART_HandleTypeDef UART_HandleTypeDef

UART handle Structure definition.

Enumeration Type Documentation

enum HAL_UART_CallbackIDTypeDef

HAL UART Callback ID enumeration definition.

Enumerator:
HAL_UART_TX_HALFCOMPLETE_CB_ID

UART Tx Half Complete Callback ID

HAL_UART_TX_COMPLETE_CB_ID

UART Tx Complete Callback ID

HAL_UART_RX_HALFCOMPLETE_CB_ID

UART Rx Half Complete Callback ID

HAL_UART_RX_COMPLETE_CB_ID

UART Rx Complete Callback ID

HAL_UART_ERROR_CB_ID

UART Error Callback ID

HAL_UART_ABORT_COMPLETE_CB_ID

UART Abort Complete Callback ID

HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID

UART Abort Transmit Complete Callback ID

HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID

UART Abort Receive Complete Callback ID

HAL_UART_WAKEUP_CB_ID

UART Wakeup Callback ID

HAL_UART_RX_FIFO_FULL_CB_ID

UART Rx Fifo Full Callback ID

HAL_UART_TX_FIFO_EMPTY_CB_ID

UART Tx Fifo Empty Callback ID

HAL_UART_MSPINIT_CB_ID

UART MspInit callback ID

HAL_UART_MSPDEINIT_CB_ID

UART MspDeInit callback ID

Definition at line 294 of file stm32g0xx_hal_uart.h.

enum UART_ClockSourceTypeDef

UART clock sources definition.

Enumerator:
UART_CLOCKSOURCE_PCLK1

PCLK1 clock source

UART_CLOCKSOURCE_HSI

HSI clock source

UART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

UART_CLOCKSOURCE_LSE

LSE clock source

UART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 184 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32g0xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling
uint32_t | OneBitSampling
uint32_t | ClockPrescaler

Detailed Description

UART Init Structure definition.

Definition at line 46 of file stm32g0xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate register is computed using the following formula: LPUART: ======= Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the UART input clock divided by a prescaler UART: =====

  • If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
  • If oversampling is 8, Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where uart_ker_ck_pres is the UART input clock divided by a prescaler

Definition at line 48 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of UART Clock Prescaler.

Definition at line 94 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control.

Definition at line 82 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode.

Definition at line 79 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of UART One Bit Sampling Method.

Definition at line 90 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). This parameter can be a value of UART Over Sampling.

Definition at line 86 of file stm32g0xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 72 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_SetConfig(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits.

Definition at line 69 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UARTEx Word Length.

Definition at line 66 of file stm32g0xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_SetConfig(), and UART_Start_Receive_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_uart.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_AdvFeatureInitTypeDef Struct Reference
UART Exported Types

UART Advanced Features initialization structure definition. More...

#include <stm32g0xx_hal_uart.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | AutoBaudRateEnable
uint32_t | AutoBaudRateMode
uint32_t | MSBFirst

Detailed Description

UART Advanced Features initialization structure definition.

Definition at line 102 of file stm32g0xx_hal_uart.h.

Field Documentation

uint32_t UART_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of UART Advanced Feature Initialization Type.

Definition at line 104 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateEnable

Specifies whether auto Baud rate detection is enabled. This parameter can be a value of UART Advanced Feature Auto BaudRate Enable.

Definition at line 128 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateMode

If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of UART Advanced Feature AutoBaud Rate Mode.

Definition at line 131 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of UART Advanced Feature Binary Data Inversion.

Definition at line 115 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of UART Advanced Feature DMA Disable On Rx Error.

Definition at line 125 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of UART Advanced Feature MSB First.

Definition at line 135 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of UART Advanced Feature Overrun Disable.

Definition at line 122 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of UART Advanced Feature RX Pin Active Level Inversion.

Definition at line 112 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of UART Advanced Feature RX TX Pins Swap.

Definition at line 119 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of UART Advanced Feature TX Pin Active Level Inversion.

Definition at line 109 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_uart.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32g0xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
UART_AdvFeatureInitTypeDef AdvancedInit
const uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
uint32_t | FifoMode
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
__IO HAL_UART_RxTypeTypeDef | ReceptionType
__IO HAL_UART_RxEventTypeTypeDef | RxEventType
void(* | RxISR )(struct __UART_HandleTypeDef *huart)
void(* | TxISR )(struct __UART_HandleTypeDef *huart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | TxCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxHalfCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | ErrorCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortTransmitCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortReceiveCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | WakeupCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxFifoFullCallback )(struct __UART_HandleTypeDef *huart)
void(* | TxFifoEmptyCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxEventCallback )(struct __UART_HandleTypeDef *huart, uint16_t Pos)
void(* | MspInitCallback )(struct __UART_HandleTypeDef *huart)
void(* | MspDeInitCallback )(struct __UART_HandleTypeDef *huart)

Detailed Description

UART handle Structure definition.

Definition at line 218 of file stm32g0xx_hal_uart.h.

Field Documentation

void(* __UART_HandleTypeDef::AbortCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Complete Callback

Definition at line 276 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Receive Complete Callback

Definition at line 278 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Transmit Complete Callback

Definition at line 277 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_AbortTransmit_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

UART_AdvFeatureInitTypeDef __UART_HandleTypeDef::AdvancedInit

UART Advanced Features initialization parameters

Definition at line 224 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

void(* __UART_HandleTypeDef::ErrorCallback)(struct __UART_HandleTypeDef *huart)

UART Error Callback

Definition at line 275 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

__IO uint32_t __UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 268 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DeInit(), HAL_UART_DMAStop(), HAL_UART_GetError(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_RegisterCallback(), HAL_UART_RegisterRxEventCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UART_UnRegisterRxEventCallback(), HAL_UARTEx_ReceiveToIdle(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), UART_Start_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

uint32_t __UART_HandleTypeDef::FifoMode

Specifies if the FIFO mode is being used. This parameter can be a value of UARTEx FIFO mode.

Definition at line 240 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_Start_Receive_IT(), and UARTEx_SetNbDataToProcess().

__IO HAL_UART_StateTypeDef __UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 261 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_EnableReceiverTimeout(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_RegisterCallback(), HAL_UART_RegisterRxEventCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UART_UnRegisterRxEventCallback(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 257 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_Start_Receive_DMA().

DMA_HandleTypeDef* __UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 255 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

UART_InitTypeDef __UART_HandleTypeDef::Init

UART communication parameters

Definition at line 222 of file stm32g0xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_DMAResume(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_SetConfig(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

USART_TypeDef* __UART_HandleTypeDef::Instance

UART registers base address

Definition at line 220 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_ReceiverTimeout_Config(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), UART_Start_Receive_DMA(), UART_Start_Receive_IT(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), UART_WaitOnFlagUntilTimeout(), UARTEx_SetNbDataToProcess(), and UARTEx_Wakeup_AddressConfig().

HAL_LockTypeDef __UART_HandleTypeDef::Lock

Locking object

Definition at line 259 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

uint16_t __UART_HandleTypeDef::Mask

UART Rx RDR register mask

Definition at line 238 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::MspDeInitCallback)(struct __UART_HandleTypeDef *huart)

UART Msp DeInit callback

Definition at line 285 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

void(* __UART_HandleTypeDef::MspInitCallback)(struct __UART_HandleTypeDef *huart)

UART Msp Init callback

Definition at line 284 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

uint16_t __UART_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 243 of file stm32g0xx_hal_uart.h.

Referenced by UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), UART_Start_Receive_IT(), UARTEx_SetNbDataToProcess(), USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 245 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT_FIFOEN(), and UARTEx_SetNbDataToProcess().

uint8_t* __UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 232 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_AbortReceive_IT(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

const uint8_t* __UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 226 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

__IO HAL_UART_RxTypeTypeDef __UART_HandleTypeDef::ReceptionType

Type of ongoing reception

Definition at line 247 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxHalfCplt(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Complete Callback

Definition at line 274 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMAReceiveCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos)

UART Reception Event Callback

Definition at line 282 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterRxEventCallback(), HAL_UART_UnRegisterRxEventCallback(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

__IO HAL_UART_RxEventTypeTypeDef __UART_HandleTypeDef::RxEventType

Type of Rx Event

Definition at line 249 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UARTEx_GetRxEventType(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxFifoFullCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Fifo Full Callback

Definition at line 280 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Half Complete Callback

Definition at line 273 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxHalfCplt(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::RxISR)(struct __UART_HandleTypeDef *huart)

Function pointer on Rx IRQ handler

Definition at line 251 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_IRQHandler(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), and UART_Start_Receive_IT().

__IO HAL_UART_StateTypeDef __UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 265 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), UART_Start_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

__IO uint16_t __UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 236 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_Start_Receive_IT().

uint16_t __UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 234 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

void(* __UART_HandleTypeDef::TxCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Complete Callback

Definition at line 272 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Fifo Empty Callback

Definition at line 281 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Half Complete Callback

Definition at line 271 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATxHalfCplt(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxISR)(struct __UART_HandleTypeDef *huart)

Function pointer on Tx IRQ handler

Definition at line 253 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Transmit_IT(), UART_EndTransmit_IT(), and UART_SetConfig().

__IO uint16_t __UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 230 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 228 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

void(* __UART_HandleTypeDef::WakeupCallback)(struct __UART_HandleTypeDef *huart)

UART Wakeup Callback

Definition at line 279 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_uart.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART State Code Definition

Defines
UART State Code Definition
UART Exported Constants

Defines

#define | HAL_UART_STATE_RESET 0x00000000U
#define | HAL_UART_STATE_READY 0x00000020U
#define | HAL_UART_STATE_BUSY 0x00000024U
#define | HAL_UART_STATE_BUSY_TX 0x00000021U
#define | HAL_UART_STATE_BUSY_RX 0x00000022U
#define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_UART_STATE_TIMEOUT 0x000000A0U
#define | HAL_UART_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_UART_STATE_BUSY 0x00000024U

an internal process is ongoing Value is allowed for gState only

Definition at line 338 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Init(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define HAL_UART_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 342 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), UART_DMAError(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

#define HAL_UART_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 340 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState.Value is result of combination (Or) between gState and RxState values

Definition at line 344 of file stm32g0xx_hal_uart.h.

#define HAL_UART_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 349 of file stm32g0xx_hal_uart.h.

#define HAL_UART_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 336 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DisableReceiverTimeout(), HAL_UART_EnableReceiverTimeout(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_RegisterCallback(), HAL_UART_RegisterRxEventCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UART_UnRegisterRxEventCallback(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_WaitOnFlagUntilTimeout().

#define HAL_UART_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 334 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

#define HAL_UART_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 347 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Error Definition

Defines
UART Error Definition
UART Exported Constants

Defines

#define | HAL_UART_ERROR_NONE (0x00000000U)
#define | HAL_UART_ERROR_PE (0x00000001U)
#define | HAL_UART_ERROR_NE (0x00000002U)
#define | HAL_UART_ERROR_FE (0x00000004U)
#define | HAL_UART_ERROR_ORE (0x00000008U)
#define | HAL_UART_ERROR_DMA (0x00000010U)
#define | HAL_UART_ERROR_RTO (0x00000020U)
#define | HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)

Define Documentation

#define HAL_UART_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 363 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMAError(), and UART_Start_Receive_DMA().

#define HAL_UART_ERROR_FE (0x00000004U)

Frame error

Definition at line 361 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)

Invalid Callback error

Definition at line 367 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_RegisterRxEventCallback(), HAL_UART_UnRegisterCallback(), and HAL_UART_UnRegisterRxEventCallback().

#define HAL_UART_ERROR_NE (0x00000002U)

Noise error

Definition at line 360 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_ERROR_NONE (0x00000000U)

No error

Definition at line 358 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), UART_CheckIdleState(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT_FIFOEN(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

#define HAL_UART_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 362 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_PE (0x00000001U)

Parity error

Definition at line 359 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_ERROR_RTO (0x00000020U)

Receiver Timeout error

Definition at line 364 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

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STM32G0C1xx HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported Constants

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define UART_STOPBITS_0_5 USART_CR2_STOP_0

UART frame with 0.5 stop bit

Definition at line 376 of file stm32g0xx_hal_uart.h.

#define UART_STOPBITS_1 0x00000000U

UART frame with 1 stop bit

Definition at line 377 of file stm32g0xx_hal_uart.h.

#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

UART frame with 1.5 stop bits

Definition at line 378 of file stm32g0xx_hal_uart.h.

#define UART_STOPBITS_2 USART_CR2_STOP_1

UART frame with 2 stop bits

Definition at line 379 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Parity

Defines
UART Parity
UART Exported Constants

Defines

#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN USART_CR1_PCE
#define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define UART_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 388 of file stm32g0xx_hal_uart.h.

#define UART_PARITY_NONE 0x00000000U

No parity

Definition at line 387 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_Start_Receive_DMA(), and UART_Start_Receive_IT().

#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 389 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported Constants

Defines

#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS USART_CR3_RTSE
#define | UART_HWCONTROL_CTS USART_CR3_CTSE
#define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define UART_HWCONTROL_CTS USART_CR3_CTSE

Clear To Send

Definition at line 399 of file stm32g0xx_hal_uart.h.

#define UART_HWCONTROL_NONE 0x00000000U

No hardware control

Definition at line 397 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS USART_CR3_RTSE

Request To Send

Definition at line 398 of file stm32g0xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Request and Clear To Send

Definition at line 400 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported Constants

Defines

#define | UART_MODE_RX USART_CR1_RE
#define | UART_MODE_TX USART_CR1_TE
#define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define UART_MODE_RX USART_CR1_RE

RX mode

Definition at line 408 of file stm32g0xx_hal_uart.h.

#define UART_MODE_TX USART_CR1_TE

TX mode

Definition at line 409 of file stm32g0xx_hal_uart.h.

#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 410 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART State

Defines
UART State
UART Exported Constants

Defines

#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE USART_CR1_UE

Define Documentation

#define UART_STATE_DISABLE 0x00000000U

UART disabled

Definition at line 418 of file stm32g0xx_hal_uart.h.

#define UART_STATE_ENABLE USART_CR1_UE

UART enabled

Definition at line 419 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported Constants

Defines

#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define UART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 427 of file stm32g0xx_hal_uart.h.

#define UART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 428 of file stm32g0xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

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STM32G0C1xx HAL User Manual: UART One Bit Sampling Method

Defines
UART One Bit Sampling Method
UART Exported Constants

Defines

#define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U

One-bit sampling disable

Definition at line 436 of file stm32g0xx_hal_uart.h.

#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

One-bit sampling enable

Definition at line 437 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Clock Prescaler

Defines
UART Clock Prescaler
UART Exported Constants

Defines

#define | UART_PRESCALER_DIV1 0x00000000U
#define | UART_PRESCALER_DIV2 0x00000001U
#define | UART_PRESCALER_DIV4 0x00000002U
#define | UART_PRESCALER_DIV6 0x00000003U
#define | UART_PRESCALER_DIV8 0x00000004U
#define | UART_PRESCALER_DIV10 0x00000005U
#define | UART_PRESCALER_DIV12 0x00000006U
#define | UART_PRESCALER_DIV16 0x00000007U
#define | UART_PRESCALER_DIV32 0x00000008U
#define | UART_PRESCALER_DIV64 0x00000009U
#define | UART_PRESCALER_DIV128 0x0000000AU
#define | UART_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define UART_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 445 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 450 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 451 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 455 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 452 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 446 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 456 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 453 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 447 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 448 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 454 of file stm32g0xx_hal_uart.h.

#define UART_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 449 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Advanced Feature AutoBaud Rate Mode

Defines
UART Advanced Feature AutoBaud Rate Mode
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE

Auto Baud rate detection on 0x55 frame detection

Definition at line 470 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1

Auto Baud rate detection on 0x7F frame detection

Definition at line 468 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0

Auto Baud rate detection on falling edge

Definition at line 466 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U

Auto Baud rate detection on start bit

Definition at line 464 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Receiver Timeout

Defines
UART Receiver Timeout
UART Exported Constants

Defines

#define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
#define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN

Define Documentation

#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U

UART Receiver Timeout disable

Definition at line 479 of file stm32g0xx_hal_uart.h.

#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN

UART Receiver Timeout enable

Definition at line 480 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Local Interconnection Network mode

Defines
UART Local Interconnection Network mode
UART Exported Constants

Defines

#define | UART_LIN_DISABLE 0x00000000U
#define | UART_LIN_ENABLE USART_CR2_LINEN

Define Documentation

#define UART_LIN_DISABLE 0x00000000U

Local Interconnect Network disable

Definition at line 488 of file stm32g0xx_hal_uart.h.

#define UART_LIN_ENABLE USART_CR2_LINEN

Local Interconnect Network enable

Definition at line 489 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART LIN Break Detection

Defines
UART LIN Break Detection
UART Exported Constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U

LIN 10-bit break detection length

Definition at line 497 of file stm32g0xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL

LIN 11-bit break detection length

Definition at line 498 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART DMA Tx

Defines
UART DMA Tx
UART Exported Constants

Defines

#define | UART_DMA_TX_DISABLE 0x00000000U
#define | UART_DMA_TX_ENABLE USART_CR3_DMAT

Define Documentation

#define UART_DMA_TX_DISABLE 0x00000000U

UART DMA TX disabled

Definition at line 506 of file stm32g0xx_hal_uart.h.

#define UART_DMA_TX_ENABLE USART_CR3_DMAT

UART DMA TX enabled

Definition at line 507 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART DMA Rx

Defines
UART DMA Rx
UART Exported Constants

Defines

#define | UART_DMA_RX_DISABLE 0x00000000U
#define | UART_DMA_RX_ENABLE USART_CR3_DMAR

Define Documentation

#define UART_DMA_RX_DISABLE 0x00000000U

UART DMA RX disabled

Definition at line 515 of file stm32g0xx_hal_uart.h.

#define UART_DMA_RX_ENABLE USART_CR3_DMAR

UART DMA RX enabled

Definition at line 516 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Half Duplex Selection

Defines
UART Half Duplex Selection
UART Exported Constants

Defines

#define | UART_HALF_DUPLEX_DISABLE 0x00000000U
#define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL

Define Documentation

#define UART_HALF_DUPLEX_DISABLE 0x00000000U

UART half-duplex disabled

Definition at line 524 of file stm32g0xx_hal_uart.h.

#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL

UART half-duplex enabled

Definition at line 525 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART WakeUp Methods

Defines
UART WakeUp Methods
UART Exported Constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE

UART wake-up on address mark

Definition at line 534 of file stm32g0xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U

UART wake-up on idle line

Definition at line 533 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Request Parameters

Defines
UART Request Parameters
UART Exported Constants

Defines

#define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
#define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
#define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ

Auto-Baud Rate Request

Definition at line 542 of file stm32g0xx_hal_uart.h.

#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ

Mute Mode Request

Definition at line 544 of file stm32g0xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode().

#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 545 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ

Send Break Request

Definition at line 543 of file stm32g0xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak().

#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 546 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), UART_DMATxAbortCallback(), and UART_DMATxOnlyAbortCallback().

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STM32G0C1xx HAL User Manual: UART Advanced Feature Initialization Type

Defines
UART Advanced Feature Initialization Type
UART Exported Constants

Defines

#define | UART_ADVFEATURE_NO_INIT 0x00000000U
#define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | UART_ADVFEATURE_SWAP_INIT 0x00000008U
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
#define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U

Auto Baud rate detection initialization

Definition at line 561 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U

Binary data inversion

Definition at line 557 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U

DMA disable on Reception Error

Definition at line 560 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Most significant bit sent/received first

Definition at line 562 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_NO_INIT 0x00000000U

No advanced feature initialization

Definition at line 554 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U

RX pin active level inversion

Definition at line 556 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U

RX overrun disable

Definition at line 559 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_SWAP_INIT 0x00000008U

TX/RX pins swap

Definition at line 558 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U

TX pin active level inversion

Definition at line 555 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32G0C1xx HAL User Manual: UART Advanced Feature TX Pin Active Level Inversion

Defines
UART Advanced Feature TX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

Define Documentation

#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U

TX pin active level inversion disable

Definition at line 570 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

TX pin active level inversion enable

Definition at line 571 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Advanced Feature RX Pin Active Level Inversion

Defines
UART Advanced Feature RX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

Define Documentation

#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U

RX pin active level inversion disable

Definition at line 579 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

RX pin active level inversion enable

Definition at line 580 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Advanced Feature Binary Data Inversion

Defines
UART Advanced Feature Binary Data Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Define Documentation

#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U

Binary data inversion disable

Definition at line 588 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Binary data inversion enable

Definition at line 589 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Advanced Feature RX TX Pins Swap

Defines
UART Advanced Feature RX TX Pins Swap
UART Exported Constants

Defines

#define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

Define Documentation

#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U

TX/RX pins swap disable

Definition at line 597 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

TX/RX pins swap enable

Definition at line 598 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Advanced Feature Overrun Disable

Defines
UART Advanced Feature Overrun Disable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

Define Documentation

#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

RX overrun disable

Definition at line 607 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U

RX overrun enable

Definition at line 606 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Advanced Feature Auto BaudRate Enable

Defines
UART Advanced Feature Auto BaudRate Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U

RX Auto Baud rate detection enable

Definition at line 615 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN

RX Auto Baud rate detection disable

Definition at line 616 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Advanced Feature DMA Disable On Rx Error

Defines
UART Advanced Feature DMA Disable On Rx Error
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

Define Documentation

#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

DMA disable on Reception Error

Definition at line 625 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U

DMA enable on Reception Error

Definition at line 624 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Advanced Feature MSB First

Defines
UART Advanced Feature MSB First
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Define Documentation

#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U

Most significant bit sent/received first disable

Definition at line 633 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Most significant bit sent/received first enable

Definition at line 635 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Advanced Feature Stop Mode Enable

Defines
UART Advanced Feature Stop Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM

Define Documentation

#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U

UART stop mode disable

Definition at line 644 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM

UART stop mode enable

Definition at line 645 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Advanced Feature Mute Mode Enable

Defines
UART Advanced Feature Mute Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME

Define Documentation

#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U

UART mute mode disable

Definition at line 653 of file stm32g0xx_hal_uart.h.

#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME

UART mute mode enable

Definition at line 654 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Address-matching LSB Position In CR2 Register

Defines
UART Address-matching LSB Position In CR2 Register
UART Exported Constants

Defines

#define UART_CR2_ADDRESS_LSB_POS 24U

Define Documentation

#define UART_CR2_ADDRESS_LSB_POS 24U

UART address-matching LSB position in CR2 register

Definition at line 662 of file stm32g0xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init(), and UARTEx_Wakeup_AddressConfig().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART WakeUp From Stop Selection

Defines
UART WakeUp From Stop Selection
UART Exported Constants

Defines

#define | UART_WAKEUP_ON_ADDRESS 0x00000000U
#define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS

Define Documentation

#define UART_WAKEUP_ON_ADDRESS 0x00000000U

UART wake-up on address

Definition at line 670 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS

UART wake-up on receive data register not empty or RXFIFO is not empty

Definition at line 672 of file stm32g0xx_hal_uart.h.

#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

UART wake-up on start bit

Definition at line 671 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART DriverEnable Polarity

Defines
UART DriverEnable Polarity
UART Exported Constants

Defines

#define | UART_DE_POLARITY_HIGH 0x00000000U
#define | UART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define UART_DE_POLARITY_HIGH 0x00000000U

Driver enable signal is active high

Definition at line 681 of file stm32g0xx_hal_uart.h.

#define UART_DE_POLARITY_LOW USART_CR3_DEP

Driver enable signal is active low

Definition at line 682 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Driver Enable Assertion Time LSB Position In CR1 Register

Defines
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U

Define Documentation

#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U

UART Driver Enable assertion time LSB position in CR1 register

Definition at line 690 of file stm32g0xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Driver Enable DeAssertion Time LSB Position In CR1 Register

Defines
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U

Define Documentation

#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U

UART Driver Enable de-assertion time LSB position in CR1 register

Definition at line 699 of file stm32g0xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Interruptions Flag Mask

Defines
UART Interruptions Flag Mask
UART Exported Constants

Defines

#define UART_IT_MASK 0x001FU

Define Documentation

#define UART_IT_MASK 0x001FU

UART interruptions flags mask

Definition at line 708 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART polling-based communications time-out value

Defines
UART polling-based communications time-out value
UART Exported Constants

Defines

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

Define Documentation

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

UART polling-based communications time-out value

Definition at line 716 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Status Flags

Defines
UART Status Flags
UART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define UART_FLAG_ABRE USART_ISR_ABRE

UART auto Baud rate error

Definition at line 738 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_ABRF USART_ISR_ABRF

UART auto Baud rate flag

Definition at line 737 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_BUSY USART_ISR_BUSY

UART busy flag

Definition at line 736 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_CMF USART_ISR_CMF

UART character match flag

Definition at line 735 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_CTS USART_ISR_CTS

UART clear to send flag

Definition at line 740 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_CTSIF USART_ISR_CTSIF

UART clear to send interrupt flag

Definition at line 741 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_FE USART_ISR_FE

UART frame error

Definition at line 751 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_IDLE USART_ISR_IDLE

UART idle flag

Definition at line 748 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UARTEx_ReceiveToIdle(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define UART_FLAG_LBDF USART_ISR_LBDF

UART LIN break detection flag

Definition at line 742 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_NE USART_ISR_NE

UART noise error

Definition at line 750 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_ORE USART_ISR_ORE

UART overrun error

Definition at line 749 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_PE USART_ISR_PE

UART parity error

Definition at line 752 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_REACK USART_ISR_REACK

UART receive enable acknowledge flag

Definition at line 730 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_RTOF USART_ISR_RTOF

UART receiver timeout flag

Definition at line 739 of file stm32g0xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define UART_FLAG_RWU USART_ISR_RWU

UART receiver wake-up from mute mode flag

Definition at line 733 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_RXFF USART_ISR_RXFF

UART RXFIFO Full flag

Definition at line 728 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE

UART RXFIFO not empty

Definition at line 747 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_RXFT USART_ISR_RXFT

UART RXFIFO threshold flag

Definition at line 727 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE

UART read data register not empty

Definition at line 746 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Receive(), and HAL_UARTEx_ReceiveToIdle().

#define UART_FLAG_SBKF USART_ISR_SBKF

UART send break flag

Definition at line 734 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_TC USART_ISR_TC

UART transmission complete

Definition at line 745 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TEACK USART_ISR_TEACK

UART transmit enable acknowledge flag

Definition at line 731 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_TXE USART_ISR_TXE_TXFNF

UART transmit data register empty

Definition at line 743 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TXFE USART_ISR_TXFE

UART TXFIFO Empty flag

Definition at line 729 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF

UART TXFIFO not full

Definition at line 744 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_TXFT USART_ISR_TXFT

UART TXFIFO threshold flag

Definition at line 726 of file stm32g0xx_hal_uart.h.

#define UART_FLAG_WUF USART_ISR_WUF

UART wake-up from stop mode flag

Definition at line 732 of file stm32g0xx_hal_uart.h.

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STM32G0C1xx HAL User Manual: UART Interrupts Definition

Defines
UART Interrupts Definition
UART Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | UART_IT_PE 0x0028U
#define | UART_IT_TXE 0x0727U
#define | UART_IT_TXFNF 0x0727U
#define | UART_IT_TC 0x0626U
#define | UART_IT_RXNE 0x0525U
#define | UART_IT_RXFNE 0x0525U
#define | UART_IT_IDLE 0x0424U
#define | UART_IT_LBD 0x0846U
#define | UART_IT_CTS 0x096AU
#define | UART_IT_CM 0x112EU
#define | UART_IT_WUF 0x1476U
#define | UART_IT_RXFF 0x183FU
#define | UART_IT_TXFE 0x173EU
#define | UART_IT_RXFT 0x1A7CU
#define | UART_IT_TXFT 0x1B77U
#define | UART_IT_RTO 0x0B3AU
#define | UART_IT_ERR 0x0060U
#define | UART_IT_ORE 0x0300U
#define | UART_IT_NE 0x0200U
#define | UART_IT_FE 0x0100U

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5bits) Elements values convention: 000000000XXYYYYYb
  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register Elements values convention: 0000ZZZZ00000000b
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define UART_IT_CM 0x112EU

UART character match interruption

Definition at line 784 of file stm32g0xx_hal_uart.h.

#define UART_IT_CTS 0x096AU

UART CTS interruption

Definition at line 783 of file stm32g0xx_hal_uart.h.

#define UART_IT_ERR 0x0060U

UART error interruption

Definition at line 792 of file stm32g0xx_hal_uart.h.

#define UART_IT_FE 0x0100U

UART frame error interruption

Definition at line 796 of file stm32g0xx_hal_uart.h.

#define UART_IT_IDLE 0x0424U

UART idle interruption

Definition at line 781 of file stm32g0xx_hal_uart.h.

#define UART_IT_LBD 0x0846U

UART LIN break detection interruption

Definition at line 782 of file stm32g0xx_hal_uart.h.

#define UART_IT_NE 0x0200U

UART noise error interruption

Definition at line 795 of file stm32g0xx_hal_uart.h.

#define UART_IT_ORE 0x0300U

UART overrun error interruption

Definition at line 794 of file stm32g0xx_hal_uart.h.

#define UART_IT_PE 0x0028U

UART parity error interruption

Definition at line 775 of file stm32g0xx_hal_uart.h.

#define UART_IT_RTO 0x0B3AU

UART receiver timeout interruption

Definition at line 790 of file stm32g0xx_hal_uart.h.

#define UART_IT_RXFF 0x183FU

UART RXFIFO full interruption

Definition at line 786 of file stm32g0xx_hal_uart.h.

#define UART_IT_RXFNE 0x0525U

UART RXFIFO not empty interruption

Definition at line 780 of file stm32g0xx_hal_uart.h.

#define UART_IT_RXFT 0x1A7CU

UART RXFIFO threshold reached interruption

Definition at line 788 of file stm32g0xx_hal_uart.h.

#define UART_IT_RXNE 0x0525U

UART read data register not empty interruption

Definition at line 779 of file stm32g0xx_hal_uart.h.

#define UART_IT_TC 0x0626U

UART transmission complete interruption

Definition at line 778 of file stm32g0xx_hal_uart.h.

#define UART_IT_TXE 0x0727U

UART transmit data register empty interruption

Definition at line 776 of file stm32g0xx_hal_uart.h.

#define UART_IT_TXFE 0x173EU

UART TXFIFO empty interruption

Definition at line 787 of file stm32g0xx_hal_uart.h.

#define UART_IT_TXFNF 0x0727U

UART TX FIFO not full interruption

Definition at line 777 of file stm32g0xx_hal_uart.h.

#define UART_IT_TXFT 0x1B77U

UART TXFIFO threshold reached interruption

Definition at line 789 of file stm32g0xx_hal_uart.h.

#define UART_IT_WUF 0x1476U

UART wake-up from stop mode interruption

Definition at line 785 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Interruption Clear Flags

Defines
UART Interruption Clear Flags
UART Exported Constants

Defines

#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NECF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF

Define Documentation

#define UART_CLEAR_CMF USART_ICR_CMCF

Character Match Clear Flag

Definition at line 813 of file stm32g0xx_hal_uart.h.

#define UART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 812 of file stm32g0xx_hal_uart.h.

#define UART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 805 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define UART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 808 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define UART_CLEAR_LBDF USART_ICR_LBDCF

LIN Break Detection Clear Flag

Definition at line 811 of file stm32g0xx_hal_uart.h.

#define UART_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 806 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define UART_CLEAR_OREF USART_ICR_ORECF

Overrun Error Clear Flag

Definition at line 807 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 804 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT_FIFOEN(), and UART_RxISR_8BIT_FIFOEN().

#define UART_CLEAR_RTOF USART_ICR_RTOCF

UART receiver timeout clear flag

Definition at line 815 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

#define UART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 810 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define UART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty clear flag

Definition at line 809 of file stm32g0xx_hal_uart.h.

#define UART_CLEAR_WUF USART_ICR_WUCF

Wake Up from stop mode Clear Flag

Definition at line 814 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Reception type values

Defines
UART Reception type values
UART Exported Constants

Defines

#define | HAL_UART_RECEPTION_STANDARD (0x00000000U)
#define | HAL_UART_RECEPTION_TOIDLE (0x00000001U)
#define | HAL_UART_RECEPTION_TORTO (0x00000002U)
#define | HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U)

Define Documentation

#define HAL_UART_RECEPTION_STANDARD (0x00000000U)

Standard reception

Definition at line 823 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_CheckIdleState(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U)

Reception till completion or CM event

Definition at line 826 of file stm32g0xx_hal_uart.h.

#define HAL_UART_RECEPTION_TOIDLE (0x00000001U)

Reception till completion or IDLE event

Definition at line 824 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_RECEPTION_TORTO (0x00000002U)

Reception till completion or RTO event

Definition at line 825 of file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART RxEvent type values

Defines
UART RxEvent type values
UART Exported Constants

Defines

#define | HAL_UART_RXEVENT_TC (0x00000000U)
#define | HAL_UART_RXEVENT_HT (0x00000001U)
#define | HAL_UART_RXEVENT_IDLE (0x00000002U)

Define Documentation

#define HAL_UART_RXEVENT_HT (0x00000001U)

RxEvent linked to Half Transfer event

Definition at line 835 of file stm32g0xx_hal_uart.h.

Referenced by UART_DMARxHalfCplt().

#define HAL_UART_RXEVENT_IDLE (0x00000002U)

RxEvent linked to IDLE event

Definition at line 836 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and HAL_UARTEx_ReceiveToIdle().

#define HAL_UART_RXEVENT_TC (0x00000000U)

RxEvent linked to Transfer Complete event

Definition at line 834 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)

Clear the UART FE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 908 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified UART pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_TXFECF TXFIFO empty clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_RTOF Receiver Timeout clear flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 896 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), HAL_UART_Transmit_DMA(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 926 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified UART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_RTOF Receiver timeout clear flag
  • UART_CLEAR_TXFECF TXFIFO empty Clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 1110 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)

Clear the UART NE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 914 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 920 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)

Clear the UART PE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 902 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)

Clear the UART TX FIFO empty clear flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 932 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1147 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(\
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))))

Disable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 1024 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1141 of file stm32g0xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(\
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
                                                           ((__HANDLE__)->Instance->CR1 |= (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
                                                           ((__HANDLE__)->Instance->CR2 |= (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U <<\
                                                               ((__INTERRUPT__) & UART_IT_MASK))))

Enable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
Return values:
None

Definition at line 991 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
  }  while(0U)

Flush the UART Data registers.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 872 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified UART flag is set or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_TXFT TXFIFO threshold flag
  • UART_FLAG_RXFT RXFIFO threshold flag
  • UART_FLAG_RXFF RXFIFO Full flag
  • UART_FLAG_TXFE TXFIFO Empty flag
  • UART_FLAG_REACK Receive enable acknowledge flag
  • UART_FLAG_TEACK Transmit enable acknowledge flag
  • UART_FLAG_WUF Wake up from stop mode flag
  • UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
  • UART_FLAG_SBKF Send Break flag
  • UART_FLAG_CMF Character match flag
  • UART_FLAG_BUSY Busy flag
  • UART_FLAG_ABRF Auto Baud rate detection flag
  • UART_FLAG_ABRE Auto Baud rate detection error flag
  • UART_FLAG_CTS CTS Change flag
  • UART_FLAG_LBDF LIN Break detection flag
  • UART_FLAG_TXE Transmit data register empty flag
  • UART_FLAG_TXFNF UART TXFIFO not full flag
  • UART_FLAG_TC Transmission Complete flag
  • UART_FLAG_RXNE Receive data register not empty flag
  • UART_FLAG_RXFNE UART RXFIFO not empty flag
  • UART_FLAG_RTOF Receiver Timeout flag
  • UART_FLAG_IDLE Idle Line detection flag
  • UART_FLAG_ORE Overrun Error flag
  • UART_FLAG_NE Noise Error flag
  • UART_FLAG_FE Framing Error flag
  • UART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 966 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UARTEx_ReceiveToIdle(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)

Check whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt to check. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1057 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
                                                                (__HANDLE__)->Instance->CR1 : \
                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
                                                                 (__HANDLE__)->Instance->CR2 : \
                                                                 (__HANDLE__)->Instance->CR3)) & (1U <<\
                                                                     (((uint16_t)(__INTERRUPT__)) &\
                                                                      UART_IT_MASK)))  != RESET) ? SET : RESET)

Check whether the specified UART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1083 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                              \
    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
  } while(0U)

Disable CTS flow control.

Note:
This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1181 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                             \
    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
  } while(0U)

Enable CTS flow control.

Note:
This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1162 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                             \
    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
  } while(0U)

Disable RTS flow control.

Note:
This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1219 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                            \
    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
  } while(0U)

Enable RTS flow control.

Note:
This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1200 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

Disable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1135 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1129 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0U)

Reset UART handle states.

Parameters:
__HANDLE__ UART handle.
Return values:
None

Definition at line 855 of file stm32g0xx_hal_uart.h.

#define __HAL_UART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific UART request flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • UART_SENDBREAK_REQUEST Send Break Request
  • UART_MUTE_MODE_REQUEST Mute Mode Request
  • UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 1123 of file stm32g0xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get UART clok division factor from clock prescaler value.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__CLOCKPRESCALER__)
Ensure that UART Prescaler is valid.

Define Documentation

#define IS_LPUART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_1) || \
                                          ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that LPUART frame number of stop bits is valid.

Parameters:
__STOPBITS__ LPUART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1320 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATE ( __AUTOBAUDRATE__ )
Value:
(((__AUTOBAUDRATE__) == \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
                                                           ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

Ensure that UART auto Baud rate state is valid.

Parameters:
__AUTOBAUDRATE__ UART auto Baud rate state.
Return values:
SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)

Definition at line 1518 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE ( __MODE__ )
Value:
(((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

Ensure that UART auto Baud rate detection mode is valid.

Parameters:
__MODE__ UART auto Baud rate detection mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1379 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))

Ensure that UART frame data inversion setting is valid.

Parameters:
__DATAINV__ UART frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1494 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that UART DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ UART DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1527 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
                                                            UART_ADVFEATURE_SWAP_INIT              | \
                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
                                                            UART_ADVFEATURE_MSBFIRST_INIT))

Ensure that UART advanced features initialization is valid.

Parameters:
__INIT__ UART advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1463 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that UART frame MSB first setting is valid.

Parameters:
__MSBFIRST__ UART frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1535 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))

Ensure that UART frame RX inversion setting is valid.

Parameters:
__RXINV__ UART frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1486 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_STOPMODE ( __STOPMODE__ )
Value:
(((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))

Ensure that UART stop mode state is valid.

Parameters:
__STOPMODE__ UART stop mode state.
Return values:
SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)

Definition at line 1543 of file stm32g0xx_hal_uart.h.

#define IS_UART_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))

Ensure that UART frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ UART frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1502 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))

Ensure that UART frame TX inversion setting is valid.

Parameters:
__TXINV__ UART frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1478 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART assertion time.

Parameters:
__TIME__ 5-bit value assertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1297 of file stm32g0xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 8000001U)

Check UART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 64 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 1291 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_DE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))

Ensure that UART driver enable polarity is valid.

Parameters:
__POLARITY__ UART driver enable polarity.
Return values:
SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)

Definition at line 1568 of file stm32g0xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DEASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART deassertion time.

Parameters:
__TIME__ 5-bit value deassertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1303 of file stm32g0xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == UART_DMA_RX_DISABLE) || \
                                       ((__DMARX__) == UART_DMA_RX_ENABLE))

Ensure that UART DMA RX state is valid.

Parameters:
__DMARX__ UART DMA RX state.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 1428 of file stm32g0xx_hal_uart.h.

#define IS_UART_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == UART_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == UART_DMA_TX_ENABLE))

Ensure that UART DMA TX state is valid.

Parameters:
__DMATX__ UART DMA TX state.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 1420 of file stm32g0xx_hal_uart.h.

#define IS_UART_HALF_DUPLEX ( __HDSEL__ )
Value:
(((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))

Ensure that UART half-duplex state is valid.

Parameters:
__HDSEL__ UART half-duplex state.
Return values:
SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)

Definition at line 1436 of file stm32g0xx_hal_uart.h.

#define IS_UART_HARDWARE_FLOW_CONTROL ( __CONTROL__ )
Value:
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))

Ensure that UART hardware flow control is valid.

Parameters:
__CONTROL__ UART hardware flow control.
Return values:
SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)

Definition at line 1337 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_LIN ( __LIN__ )
Value:
(((__LIN__) == UART_LIN_DISABLE) || \
                                     ((__LIN__) == UART_LIN_ENABLE))

Ensure that UART LIN state is valid.

Parameters:
__LIN__ UART LIN state.
Return values:
SET (__LIN__ is valid) or RESET (__LIN__ is invalid)

Definition at line 1404 of file stm32g0xx_hal_uart.h.

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))

Ensure that UART LIN break detection length is valid.

Parameters:
__LENGTH__ UART LIN break detection length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 1412 of file stm32g0xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that UART communication mode is valid.

Parameters:
__MODE__ UART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1348 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_MUTE_MODE ( __MUTE__ )
Value:
(((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))

Ensure that UART mute mode state is valid.

Parameters:
__MUTE__ UART mute mode state.
Return values:
SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)

Definition at line 1551 of file stm32g0xx_hal_uart.h.

#define IS_UART_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))

Ensure that UART frame sampling is valid.

Parameters:
__ONEBIT__ UART frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1371 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))

Ensure that UART frame overrun setting is valid.

Parameters:
__OVERRUN__ UART frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1510 of file stm32g0xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == UART_OVERSAMPLING_16) || \
                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))

Ensure that UART oversampling is valid.

Parameters:
__SAMPLING__ UART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 1363 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == UART_PARITY_NONE) || \
                                    ((__PARITY__) == UART_PARITY_EVEN) || \
                                    ((__PARITY__) == UART_PARITY_ODD))

Ensure that UART frame parity is valid.

Parameters:
__PARITY__ UART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1328 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))

Ensure that UART Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ UART Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 1576 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_RECEIVER_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))

Ensure that UART receiver timeout setting is valid.

Parameters:
__TIMEOUT__ UART receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1389 of file stm32g0xx_hal_uart.h.

#define IS_UART_RECEIVER_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum UART receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 1397 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UART_ReceiverTimeout_Config().

#define IS_UART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))

Ensure that UART request parameter is valid.

Parameters:
__PARAM__ UART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1452 of file stm32g0xx_hal_uart.h.

#define IS_UART_STATE ( __STATE__ )
Value:
(((__STATE__) == UART_STATE_DISABLE) || \
                                  ((__STATE__) == UART_STATE_ENABLE))

Ensure that UART state is valid.

Parameters:
__STATE__ UART state.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 1355 of file stm32g0xx_hal_uart.h.

#define IS_UART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_0_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that UART frame number of stop bits is valid.

Parameters:
__STOPBITS__ UART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1310 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUP_SELECTION ( __WAKE__ )
Value:
(((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))

Ensure that UART wake-up selection is valid.

Parameters:
__WAKE__ UART wake-up selection.
Return values:
SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)

Definition at line 1559 of file stm32g0xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define IS_UART_WAKEUPMETHOD ( __WAKEUP__ )
Value:
(((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))

Ensure that UART wake-up method is valid.

Parameters:
__WAKEUP__ UART wake-up method .
Return values:
SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)

Definition at line 1444 of file stm32g0xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_DIV_LPUART | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
               (uint32_t)((__BAUD__)/2U)) / (__BAUD__))                                \
  )

BRR division operation to set BRR register with LPUART.

Parameters:
__PCLK__ | LPUART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1256 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) | ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1276 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) | (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1267 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_GET_DIV_FACTOR ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)

Get UART clok division factor from clock prescaler value.

Parameters:
__CLOCKPRESCALER__ UART prescaler value.
Return values:
UART clock division factor

Definition at line 1236 of file stm32g0xx_hal_uart.h.

#define UART_INSTANCE_LOWPOWER ( __HANDLE__ ) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))

Check whether or not UART instance is Low Power UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
SET (instance is LPUART) or RESET (instance isn't LPUART)

Definition at line 1283 of file stm32g0xx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Private variables

Variables
UART Private variables
UART

Variables

const uint16_t | UARTPrescTable [12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}
const uint16_t | UARTPrescTable [12]

Variable Documentation

const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}

Definition at line 229 of file stm32g0xx_hal_uart.c.

Referenced by UART_SetConfig().

const uint16_t UARTPrescTable[12]

Definition at line 229 of file stm32g0xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx Private Constants

Defines
UARTEx Private Constants
UARTEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 63 of file stm32g0xx_hal_uart_ex.c.

Referenced by UARTEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 66 of file stm32g0xx_hal_uart_ex.c.

Referenced by UARTEx_SetNbDataToProcess().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx Private Functions

Functions
UARTEx Private Functions
UARTEx

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
static void | UARTEx_SetNbDataToProcess (UART_HandleTypeDef *huart)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void UARTEx_SetNbDataToProcess ( UART_HandleTypeDef * huart ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the UART configuration registers.
Parameters:
huart UART handle.
Return values:
None

Definition at line 1053 of file stm32g0xx_hal_uart_ex.c.

References __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, TX_FIFO_DEPTH, and UART_FIFOMODE_DISABLE.

Referenced by HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), and HAL_UARTEx_SetTxFifoThreshold().

static void UARTEx_Wakeup_AddressConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  | [static]

Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Parameters:
huart | UART handle.
WakeUpSelection | UART wake up from stop mode parameters.
Return values:
None

Definition at line 1035 of file stm32g0xx_hal_uart_ex.c.

References UART_WakeUpTypeDef::Address, UART_WakeUpTypeDef::AddressLength, assert_param, __UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CR2_ADDRESS_LSB_POS.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UARTEx Exported Functions

Extended Initialization and Configuration Functions. More...

Functions

HAL_StatusTypeDef HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Detailed Description

Extended Initialization and Configuration Functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
     procedures (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RS485Ex_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Polarity,
 |  | uint32_t | AssertionTime,
 |  | uint32_t | DeassertionTime
 | ) |  |

Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart | UART handle.
Polarity Select the driver enable polarity. This parameter can be one of the following values:
  • UART_DE_POLARITY_HIGH DE signal is active high
  • UART_DE_POLARITY_LOW DE signal is active low
AssertionTime | Driver Enable assertion time: 5-bit value defining the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate)
DeassertionTime | Driver Enable deassertion time: 5-bit value defining the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).
Return values:
HAL status

Definition at line 166 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, IS_UART_ASSERTIONTIME, IS_UART_DE_POLARITY, IS_UART_DEASSERTIONTIME, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR1_DEAT_ADDRESS_LSB_POS, UART_CR1_DEDT_ADDRESS_LSB_POS, UART_InitCallbacksToDefault(), and UART_SetConfig().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
UARTEx Exported Functions

Extended functions. More...

Functions

__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.

Detailed Description

Extended functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of Wakeup and FIFO mode related callback functions.

    (#) Wakeup from Stop mode Callback:
        (+) HAL_UARTEx_WakeupCallback()

    (#) TX/RX Fifos Callbacks:
        (+) HAL_UARTEx_RxFifoFullCallback()
        (+) HAL_UARTEx_TxFifoEmptyCallback()

Function Documentation

void HAL_UARTEx_RxFifoFullCallback ( UART_HandleTypeDef * huart )

UART RX Fifo full callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 287 of file stm32g0xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_TxFifoEmptyCallback ( UART_HandleTypeDef * huart )

UART TX Fifo empty callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 302 of file stm32g0xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_WakeupCallback ( UART_HandleTypeDef * huart )

UART wakeup from Stop mode callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 272 of file stm32g0xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
HAL_UART_RxEventTypeTypeDef | HAL_UARTEx_GetRxEventType (UART_HandleTypeDef *huart)
Provide Rx Event type that has lead to RxEvent callback execution.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
         detection length to more than 4 bits for multiprocessor address mark wake up.
     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
         trigger: address match, Start Bit detection or RXNE bit status.
     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold

    [..] This subsection also provides a set of additional functions providing enhanced reception
    services to user. (For example, these functions allow application to handle use cases
    where number of data to be received is unknown).

    (#) Compared to standard reception services which only consider number of received
        data elements as reception completion criteria, these functions also consider additional events
        as triggers for updating reception status to caller :
       (+) Detection of inactivity period (RX line has not been active for a given period).
          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
               for 1 frame time, after last received byte.
          (++) RX inactivity detected by RTO, i.e. line has been in idle state
               for a programmable time, after last received byte.
       (+) Detection that a specific character has been received.

    (#) There are two mode of transfer:
       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
           or till IDLE event occurs. Reception is handled only during function execution.
           When function exits, no data reception could occur. HAL status and number of actually received data elements,
           are returned by function after finishing transfer.
       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
           These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.

    (#) Blocking mode API:
        (+) HAL_UARTEx_ReceiveToIdle()

    (#) Non-Blocking mode API with Interrupt:
        (+) HAL_UARTEx_ReceiveToIdle_IT()

    (#) Non-Blocking mode API with DMA:
        (+) HAL_UARTEx_ReceiveToIdle_DMA()

Function Documentation

HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | AddressLength
 | ) |  |

By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).

Note:
Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
Parameters:
huart UART handle.
AddressLength This parameter can be one of the following values:
  • UART_ADDRESS_DETECT_4B 4-bit long address
  • UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
Return values:
HAL status

Definition at line 387 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, __UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode ( UART_HandleTypeDef * huart )

Disable the FIFO mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 559 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_UARTEx_DisableStopMode ( UART_HandleTypeDef * huart )

Disable UART Stop Mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 499 of file stm32g0xx_hal_uart_ex.c.

References __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode ( UART_HandleTypeDef * huart )

Enable the FIFO mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 518 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, UART_FIFOMODE_ENABLE, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_EnableStopMode ( UART_HandleTypeDef * huart )

Enable UART Stop Mode.

Note:
The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 480 of file stm32g0xx_hal_uart_ex.c.

References __UART_HandleTypeDef::Instance.

HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType ( UART_HandleTypeDef * huart )

Provide Rx Event type that has lead to RxEvent callback execution.

Note:
When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress of reception process is provided to application through calls of Rx Event callback (either default one HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead to Rx Event callback execution.
This function is expected to be called within the user implementation of Rx Event Callback, in order to provide the accurate value : In Interrupt Mode :
  • HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
  • HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of received data is lower than expected one) In DMA Mode :
  • HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
  • HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
  • HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of received data is lower than expected one). In DMA mode, RxEvent callback could be called several times; When DMA is configured in Normal Mode, HT event does not stop Reception process; When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
Parameters:
huart UART handle.
Return values:
Rx Event Type (return vale will be a value of UART RxEvent type values)

Definition at line 1011 of file stm32g0xx_hal_uart_ex.c.

References __UART_HandleTypeDef::RxEventType.

HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint16_t * | RxLen,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.

Note:
HAL_OK is returned if reception is completed (expected number of data has been received) or if reception is stopped after IDLE event (less than the expected number of data has been received) In this case, RxLen output parameter indicates number of data available in reception buffer.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of uint16_t. In this case, Size must indicate the number of uint16_t available through pData.
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (uint8_t or uint16_t data elements).
Size | Amount of data elements (uint8_t or uint16_t) to be received.
RxLen | Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
Timeout | Timeout duration expressed in ms (covers the whole reception sequence).
Return values:
HAL status

Definition at line 716 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_IDLE, HAL_UART_RXEVENT_TC, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_CLEAR_IDLEF, UART_FLAG_IDLE, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.

Note:
Reception is initiated by this function call. Further progress of reception is achieved thanks to DMA services, transferring automatically received data elements in user reception buffer and calling registered callbacks at half/end of reception. UART IDLE events are also used to consider reception phase as ended. In all cases, callback execution will indicate number of received data elements.
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of uint16_t. In this case, Size must indicate the number of uint16_t available through pData.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (uint8_t or uint16_t data elements).
Size | Amount of data elements (uint8_t or uint16_t) to be received.
Return values:
HAL status

Definition at line 932 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_CLEAR_FLAG, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_TC, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, UART_CLEAR_IDLEF, UART_PARITY_NONE, UART_Start_Receive_DMA(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.

Note:
Reception is initiated by this function call. Further progress of reception is achieved thanks to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating number of received data elements.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of uint16_t. In this case, Size must indicate the number of uint16_t available through pData.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (uint8_t or uint16_t data elements).
Size | Amount of data elements (uint8_t or uint16_t) to be received.
Return values:
HAL status

Definition at line 855 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_CLEAR_FLAG, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RXEVENT_TC, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::ReceptionType, __UART_HandleTypeDef::RxEventType, __UART_HandleTypeDef::RxState, UART_CLEAR_IDLEF, UART_PARITY_NONE, UART_Start_Receive_IT(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
huart UART handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • UART_RXFIFO_THRESHOLD_1_8
  • UART_RXFIFO_THRESHOLD_1_4
  • UART_RXFIFO_THRESHOLD_1_2
  • UART_RXFIFO_THRESHOLD_3_4
  • UART_RXFIFO_THRESHOLD_7_8
  • UART_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 654 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, IS_UART_RXFIFO_THRESHOLD, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
huart UART handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • UART_TXFIFO_THRESHOLD_1_8
  • UART_TXFIFO_THRESHOLD_1_4
  • UART_TXFIFO_THRESHOLD_1_2
  • UART_TXFIFO_THRESHOLD_3_4
  • UART_TXFIFO_THRESHOLD_7_8
  • UART_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 605 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, IS_UART_TXFIFO_THRESHOLD, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  |

Set Wakeup from Stop mode interrupt flag selection.

Note:
It is the application responsibility to enable the interrupt used as usart_wkup interrupt source before entering low-power mode.
Parameters:
huart UART handle.
WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. This parameter can be one of the following values:
  • UART_WAKEUP_ON_ADDRESS
  • UART_WAKEUP_ON_STARTBIT
  • UART_WAKEUP_ON_READDATA_NONEMPTY
Return values:
HAL status

Definition at line 425 of file stm32g0xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, __UART_HandleTypeDef::Instance, IS_UART_WAKEUP_SELECTION, UART_WaitOnFlagUntilTimeout(), UART_WAKEUP_ON_ADDRESS, UARTEx_Wakeup_AddressConfig(), and UART_WakeUpTypeDef::WakeUpEvent.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART_WakeUpTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_WakeUpTypeDef Struct Reference
UARTEx Exported Types

UART wake up from stop mode parameters. More...

#include <stm32g0xx_hal_uart_ex.h>

Data Fields

uint32_t | WakeUpEvent
uint16_t | AddressLength
uint8_t | Address

Detailed Description

UART wake up from stop mode parameters.

Definition at line 46 of file stm32g0xx_hal_uart_ex.h.

Field Documentation

uint8_t UART_WakeUpTypeDef::Address

UART/USART node address (7-bit long max).

Definition at line 56 of file stm32g0xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint16_t UART_WakeUpTypeDef::AddressLength

Specifies whether the address is 4 or 7-bit long. This parameter can be a value of UARTEx WakeUp Address Length.

Definition at line 53 of file stm32g0xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint32_t UART_WakeUpTypeDef::WakeUpEvent

Specifies which event will activate the Wakeup from Stop mode flag (WUF). This parameter can be a value of UART WakeUp From Stop Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up.

Definition at line 48 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_uart_ex.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx Word Length

Defines
UARTEx Word Length
UARTEx Exported Constants

Defines

#define | UART_WORDLENGTH_7B USART_CR1_M1
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define UART_WORDLENGTH_7B USART_CR1_M1

7-bit long UART frame

Definition at line 71 of file stm32g0xx_hal_uart_ex.h.

#define UART_WORDLENGTH_8B 0x00000000U

8-bit long UART frame

Definition at line 72 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_LIN_Init().

#define UART_WORDLENGTH_9B USART_CR1_M0

9-bit long UART frame

Definition at line 73 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_ReceiveToIdle(), HAL_UARTEx_ReceiveToIdle_DMA(), HAL_UARTEx_ReceiveToIdle_IT(), and UART_Start_Receive_IT().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx WakeUp Address Length

Defines
UARTEx WakeUp Address Length
UARTEx Exported Constants

Defines

#define | UART_ADDRESS_DETECT_4B 0x00000000U
#define | UART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define UART_ADDRESS_DETECT_4B 0x00000000U

4-bit long wake-up address

Definition at line 81 of file stm32g0xx_hal_uart_ex.h.

#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit long wake-up address

Definition at line 82 of file stm32g0xx_hal_uart_ex.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx FIFO mode

Defines
UARTEx FIFO mode
UARTEx Exported Constants

UART FIFO mode. More...

Defines

#define | UART_FIFOMODE_DISABLE 0x00000000U
#define | UART_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

UART FIFO mode.

Define Documentation

#define UART_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 91 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_DisableFifoMode(), and UARTEx_SetNbDataToProcess().

#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 92 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit_IT(), HAL_UARTEx_EnableFifoMode(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), and UART_Start_Receive_IT().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx TXFIFO threshold level

Defines
UARTEx TXFIFO threshold level
UARTEx Exported Constants

UART TXFIFO threshold level. More...

Defines

#define | UART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

UART TXFIFO threshold level.

Define Documentation

#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TX FIFO reaches 1/2 of its depth

Definition at line 103 of file stm32g0xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TX FIFO reaches 1/4 of its depth

Definition at line 102 of file stm32g0xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U

TX FIFO reaches 1/8 of its depth

Definition at line 101 of file stm32g0xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TX FIFO reaches 3/4 of its depth

Definition at line 104 of file stm32g0xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TX FIFO reaches 7/8 of its depth

Definition at line 105 of file stm32g0xx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TX FIFO becomes empty

Definition at line 106 of file stm32g0xx_hal_uart_ex.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx RXFIFO threshold level

Defines
UARTEx RXFIFO threshold level
UARTEx Exported Constants

UART RXFIFO threshold level. More...

Defines

#define | UART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

UART RXFIFO threshold level.

Define Documentation

#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RX FIFO reaches 1/2 of its depth

Definition at line 117 of file stm32g0xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RX FIFO reaches 1/4 of its depth

Definition at line 116 of file stm32g0xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U

RX FIFO reaches 1/8 of its depth

Definition at line 115 of file stm32g0xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RX FIFO reaches 3/4 of its depth

Definition at line 118 of file stm32g0xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RX FIFO reaches 7/8 of its depth

Definition at line 119 of file stm32g0xx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RX FIFO becomes full

Definition at line 120 of file stm32g0xx_hal_uart_ex.h.

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STM32G0C1xx HAL User Manual: UARTEx Private Macros

Defines
UARTEx Private Macros
UARTEx

Defines

#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Define Documentation

#define IS_UART_ADDRESSLENGTH_DETECT ( __ADDRESS__ )
Value:
(((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

Ensure that UART wake-up address length is valid.

Parameters:
__ADDRESS__ UART wake-up address length.
Return values:
SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)

Definition at line 725 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_MultiProcessorEx_AddressLength_Set(), and UARTEx_Wakeup_AddressConfig().

#define IS_UART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))

Ensure that UART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ UART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 745 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_SetRxFifoThreshold().

#define IS_UART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))

Ensure that UART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ UART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 733 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_SetTxFifoThreshold().

#define IS_UART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

Ensure that UART frame length is valid.

Parameters:
__LENGTH__ UART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 716 of file stm32g0xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the UART clock source.

Parameters:
__HANDLE__ | specifies the UART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
UART clocking source, written in __CLOCKSOURCE__.

Definition at line 203 of file stm32g0xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_MASK_COMPUTATION ( __HANDLE__ )

Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None,the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 670 of file stm32g0xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UARTEx_ReceiveToIdle(), and UART_Start_Receive_IT().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))
#define | USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
#define | USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Define Documentation

#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Definition at line 171 of file stm32g0xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */

Definition at line 170 of file stm32g0xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
                                              USART_CR1_FIFOEN ))

USART CR1 fields of parameters set by USART_SetConfig API

Definition at line 160 of file stm32g0xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
                                              USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
                                              USART_CR2_DIS_NSS))

USART CR2 fields of parameters set by USART_SetConfig API

Definition at line 164 of file stm32g0xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART or USART CR3 fields of parameters set by USART_SetConfig API

Definition at line 168 of file stm32g0xx_hal_usart.c.

#define USART_DUMMY_DATA ((uint16_t) 0xFFFF)

USART transmitted dummy data

Definition at line 158 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define USART_TEACK_REACK_TIMEOUT 1000U

USART TX or RX enable acknowledge time-out value

Definition at line 159 of file stm32g0xx_hal_usart.c.

Referenced by USART_CheckIdleState().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an USART Callback USART callaback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USART
    in asynchronous and in synchronous modes.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) USART polarity
        (++) USART phase
        (++) USART LastBit
        (++) Receiver/transmitter modes

    [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible USART formats are listed in the following table.

Table 1. USART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | USART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 338 of file stm32g0xx_hal_usart.c.

References assert_param, __USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::MspDeInitCallback, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 276 of file stm32g0xx_hal_usart.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Lock, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::State, USART_CheckIdleState(), USART_InitCallbacksToDefault(), and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 396 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_DeInit(), and HAL_USART_UnRegisterCallback().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

Initialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 381 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_Init(), and HAL_USART_UnRegisterCallback().

HAL_StatusTypeDef HAL_USART_RegisterCallback | ( | USART_HandleTypeDef * | husart,
 |  | HAL_USART_CallbackIDTypeDef | CallbackID,
 |  | pUSART_CallbackTypeDef | pCallback
 | ) |  |

Register a User USART Callback To be used instead of the weak predefined callback.

Parameters:
husart | usart handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_ERROR_CB_ID Error Callback ID
  • HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_USART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status +

Definition at line 427 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ABORT_COMPLETE_CB_ID, HAL_USART_ERROR_CB_ID, HAL_USART_ERROR_INVALID_CALLBACK, HAL_USART_MSPDEINIT_CB_ID, HAL_USART_MSPINIT_CB_ID, HAL_USART_RX_COMPLETE_CB_ID, HAL_USART_RX_FIFO_FULL_CB_ID, HAL_USART_RX_HALFCOMPLETE_CB_ID, HAL_USART_STATE_READY, HAL_USART_STATE_RESET, HAL_USART_TX_COMPLETE_CB_ID, HAL_USART_TX_FIFO_EMPTY_CB_ID, HAL_USART_TX_HALFCOMPLETE_CB_ID, HAL_USART_TX_RX_COMPLETE_CB_ID, __USART_HandleTypeDef::MspDeInitCallback, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

HAL_StatusTypeDef HAL_USART_UnRegisterCallback | ( | USART_HandleTypeDef * | husart,
 |  | HAL_USART_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USART Callback USART callaback is redirected to the weak predefined callback.

Parameters:
husart usart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_ERROR_CB_ID Error Callback ID
  • HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_USART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 554 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ABORT_COMPLETE_CB_ID, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_CB_ID, HAL_USART_ERROR_INVALID_CALLBACK, HAL_USART_ErrorCallback(), HAL_USART_MspDeInit(), HAL_USART_MSPDEINIT_CB_ID, HAL_USART_MspInit(), HAL_USART_MSPINIT_CB_ID, HAL_USART_RX_COMPLETE_CB_ID, HAL_USART_RX_FIFO_FULL_CB_ID, HAL_USART_RX_HALFCOMPLETE_CB_ID, HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_STATE_READY, HAL_USART_STATE_RESET, HAL_USART_TX_COMPLETE_CB_ID, HAL_USART_TX_FIFO_EMPTY_CB_ID, HAL_USART_TX_HALFCOMPLETE_CB_ID, HAL_USART_TX_RX_COMPLETE_CB_ID, HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::MspDeInitCallback, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.

Detailed Description

USART Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

    [..] The USART supports master mode only: it cannot receive or send data related to an input
         clock (SCLK is always an output).

    [..]

    (#) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
             or DMA, These API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
             will be executed respectively at the end of the transmit or Receive process
             The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_USART_Transmit() in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_USART_Transmit_IT() in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) No-Blocking mode API's  with DMA are :
        (++) HAL_USART_Transmit_DMA() in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_USART_Abort()
        (++) HAL_USART_Abort_IT()

    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
        (++) HAL_USART_AbortCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error,
             Parity Error or Noise Error in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
             error type, and HAL_USART_ErrorCallback() user callback is executed.
             Transfer is kept ongoing on USART side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type,
             and HAL_USART_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_USART_Abort ( USART_HandleTypeDef * husart )

Abort ongoing transfers (blocking mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 2036 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_FIFOMODE_ENABLE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Abort_IT ( USART_HandleTypeDef * husart )

Abort ongoing transfers (Interrupt mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2134 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_DMA_Abort_IT(), HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_FIFOMODE_ENABLE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_USART_AbortCpltCallback ( USART_HandleTypeDef * husart )

USART Abort Complete callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2596 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_Abort_IT(), HAL_USART_UnRegisterCallback(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and USART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pause the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1882 of file stm32g0xx_hal_usart.c.

References HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resume the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1929 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::State, USART_CLEAR_OREF, and USART_PARITY_NONE.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stop the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1976 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_USART_ERROR_DMA, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_EndTransfer().

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2581 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), USART_DMAAbortOnError(), USART_DMAError(), and USART_InitCallbacksToDefault().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

Handle USART interrupt request.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2266 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, __HAL_USART_CLEAR_UDRFLAG, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ERROR_RTO, HAL_USART_ERROR_UDR, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxISR, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_CLEAR_RTOF, USART_DMAAbortOnError(), USART_EndTransfer(), USART_EndTransmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
Parameters:
husart | USART handle.
pRxData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 870 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, USART_TXDATA_FLUSH_REQUEST, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When the USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
The USART DMA transmit channel must be configured in order to generate the clock for the slave.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1615 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_PARITY_NONE, USART_SLAVEMODE_DISABLE, USART_WORDLENGTH_9B, USART_InitTypeDef::WordLength, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1260 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FIFOMODE_ENABLE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_SLAVEMODE_DISABLE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2536 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2551 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMARxHalfCplt(), and USART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex send an amount of data in blocking mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
Parameters:
husart | USART handle.
pTxData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 756 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_CLEAR_OREFLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_FLAG_TC, USART_FLAG_TXE, USART_PARITY_NONE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
Parameters:
husart | USART handle.
pTxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1514 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_PARITY_NONE, USART_WORDLENGTH_9B, USART_InitTypeDef::WordLength, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
Parameters:
husart | USART handle.
pTxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1161 of file stm32g0xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FIFOMODE_ENABLE, USART_IT_TXE, USART_IT_TXFT, USART_PARITY_NONE, USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send and Receive an amount of data in blocking mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent (same amount to be received).
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 998 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_ENABLE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received/sent.
Return values:
HAL status

Definition at line 1751 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_PARITY_NONE, USART_WORDLENGTH_9B, USART_InitTypeDef::WordLength, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | const uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send and Receive an amount of data in interrupt mode.

Note:
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain, use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent (same amount to be received).
Return values:
HAL status

Definition at line 1390 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FIFOMODE_ENABLE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2506 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_InitCallbacksToDefault().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2521 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMATxHalfCplt(), and USART_InitCallbacksToDefault().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2566 of file stm32g0xx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_EndTransmit_IT(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
USART Exported Functions

USART Peripheral State and Error functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (const USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (const USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART Peripheral State and Error functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the USART handle state
      (+) Return the USART handle error code

Function Documentation

uint32_t HAL_USART_GetError ( const USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle Error Code

Definition at line 2644 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( const USART_HandleTypeDef * husart )

Return the USART handle state.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle state

Definition at line 2633 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::State.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Private Functions

Functions
USART Private Functions
USART

Functions

void | USART_InitCallbacksToDefault (USART_HandleTypeDef *husart)
Initialize the callbacks to their default values.
static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_TxISR_8BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static void | USART_RxISR_8BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.

Function Documentation

static HAL_StatusTypeDef USART_CheckIdleState ( USART_HandleTypeDef * husart ) [static]

Check the USART Idle State.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 3128 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, USART_TEACK_REACK_TIMEOUT, and USART_WaitOnFlagUntilTimeout().

Referenced by HAL_USART_Init().

static void USART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2880 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCallback, HAL_USART_ErrorCallback(), __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, and __USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_IRQHandler().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2854 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, and USART_EndTransfer().

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2761 of file stm32g0xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __DMA_HandleTypeDef::Instance, __USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, and __USART_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2951 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2836 of file stm32g0xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __USART_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2703 of file stm32g0xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2903 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2743 of file stm32g0xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __USART_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_EndTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing transfer on USART peripheral (following error detection or Transfer completion).

Parameters:
husart USART handle.
Return values:
None

Definition at line 2687 of file stm32g0xx_hal_usart.c.

References HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, and __USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), and USART_DMAError().

static void USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
husart Pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 3337 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_OREFLAG, __HAL_USART_DISABLE_IT, __HAL_USART_SEND_REQ, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxRxCpltCallback, USART_IT_ERR, USART_IT_TC, and USART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_IRQHandler().

void USART_InitCallbacksToDefault ( USART_HandleTypeDef * husart )

Initialize the callbacks to their default values.

Parameters:
husart USART handle.
Return values:
none

Definition at line 2667 of file stm32g0xx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, HAL_USART_AbortCpltCallback(), HAL_USART_ErrorCallback(), HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_USART_Init().

static void USART_RxISR_16BIT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is disabled and when the data word length is 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3485 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_RxISR_16BIT_FIFOEN().

static void USART_RxISR_16BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is enabled and when the data word length is 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3711 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_GET_FLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_FLAG_RXFNE, USART_RXDATA_FLUSH_REQUEST, USART_RxISR_16BIT(), USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_RxISR_8BIT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is disabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3394 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_RxISR_8BIT_FIFOEN().

static void USART_RxISR_8BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is enabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3578 of file stm32g0xx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_GET_FLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_FLAG_RXFNE, USART_RXDATA_FLUSH_REQUEST, USART_RxISR_8BIT(), USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), and HAL_USART_TransmitReceive_IT().

static HAL_StatusTypeDef USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configure the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 3028 of file stm32g0xx_hal_usart.c.

References assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, USART_InitTypeDef::ClockPrescaler, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_PRESCALER, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, LSE_VALUE, USART_InitTypeDef::Mode, __USART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::NbTxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxISR, USART_InitTypeDef::StopBits, __USART_HandleTypeDef::TxISR, USART_BRR_MAX, USART_BRR_MIN, USART_CLOCK_ENABLE, USART_CLOCKSOURCE_HSI, USART_CLOCKSOURCE_LSE, USART_CLOCKSOURCE_PCLK1, USART_CLOCKSOURCE_SYSCLK, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_DIV_SAMPLING8, USART_GETCLOCKSOURCE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static void USART_TxISR_16BIT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is disabled and when the data word length is 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3213 of file stm32g0xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_IT_TC, and USART_IT_TXE.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_16BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is enabled and when the data word length is 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3294 of file stm32g0xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbTxDataToProcess, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_FLAG_TXFNF, USART_IT_TC, and USART_IT_TXFT.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_8BIT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is disabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3178 of file stm32g0xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_IT_TC, and USART_IT_TXE.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_8BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is enabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3249 of file stm32g0xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbTxDataToProcess, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_FLAG_TXFNF, USART_IT_TC, and USART_IT_TXFT.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle USART Communication Timeout.

It waits until a flag is no longer in the specified status.

Parameters:
husart | USART handle.
Flag | Specifies the USART flag to check.
Status | the actual Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 3000 of file stm32g0xx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, and __USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_CheckIdleState().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Exported Types

Data Structures | Typedefs | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | __USART_HandleTypeDef
USART handle Structure definition. More...

Typedefs

typedef struct
__USART_HandleTypeDef 		USART_HandleTypeDef
USART handle Structure definition.
typedef void(* | pUSART_CallbackTypeDef )(USART_HandleTypeDef *husart)
HAL USART Callback pointer definition.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00U, USART_CLOCKSOURCE_HSI = 0x02U, USART_CLOCKSOURCE_SYSCLK = 0x04U, USART_CLOCKSOURCE_LSE = 0x08U,
USART_CLOCKSOURCE_UNDEFINED = 0x10U
}
USART clock sources definitions. More...
enum HAL_USART_CallbackIDTypeDef {
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_USART_TX_COMPLETE_CB_ID = 0x01U, HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_USART_RX_COMPLETE_CB_ID = 0x03U,
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, HAL_USART_ERROR_CB_ID = 0x05U, HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U,
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, HAL_USART_MSPINIT_CB_ID = 0x09U, HAL_USART_MSPDEINIT_CB_ID = 0x0AU
}
HAL USART Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart)

HAL USART Callback pointer definition.

pointer to an USART callback function

Definition at line 205 of file stm32g0xx_hal_usart.h.

typedef struct __USART_HandleTypeDef USART_HandleTypeDef

USART handle Structure definition.

Enumeration Type Documentation

enum HAL_USART_CallbackIDTypeDef

HAL USART Callback ID enumeration definition.

Enumerator:
HAL_USART_TX_HALFCOMPLETE_CB_ID

USART Tx Half Complete Callback ID

HAL_USART_TX_COMPLETE_CB_ID

USART Tx Complete Callback ID

HAL_USART_RX_HALFCOMPLETE_CB_ID

USART Rx Half Complete Callback ID

HAL_USART_RX_COMPLETE_CB_ID

USART Rx Complete Callback ID

HAL_USART_TX_RX_COMPLETE_CB_ID

USART Tx Rx Complete Callback ID

HAL_USART_ERROR_CB_ID

USART Error Callback ID

HAL_USART_ABORT_COMPLETE_CB_ID

USART Abort Complete Callback ID

HAL_USART_RX_FIFO_FULL_CB_ID

USART Rx Fifo Full Callback ID

HAL_USART_TX_FIFO_EMPTY_CB_ID

USART Tx Fifo Empty Callback ID

HAL_USART_MSPINIT_CB_ID

USART MspInit callback ID

HAL_USART_MSPDEINIT_CB_ID

USART MspDeInit callback ID

Definition at line 185 of file stm32g0xx_hal_usart.h.

enum HAL_USART_StateTypeDef

HAL USART State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 93 of file stm32g0xx_hal_usart.h.

enum USART_ClockSourceTypeDef

USART clock sources definitions.

Enumerator:
USART_CLOCKSOURCE_PCLK1

PCLK1 clock source

USART_CLOCKSOURCE_HSI

HSI clock source

USART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

USART_CLOCKSOURCE_LSE

LSE clock source

USART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 108 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32g0xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit
uint32_t | ClockPrescaler

Detailed Description

USART Init Structure definition.

Definition at line 46 of file stm32g0xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula: Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.

Note:
Oversampling by 8 is systematically applied to achieve high baud rates.

Definition at line 48 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit.

Definition at line 82 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase.

Definition at line 79 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity.

Definition at line 76 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of USART Clock Prescaler.

Definition at line 86 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode.

Definition at line 73 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 66 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits.

Definition at line 63 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USARTEx Word Length.

Definition at line 60 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_usart.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32g0xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
const uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
uint32_t | SlaveMode
uint32_t | FifoMode
void(* | RxISR )(struct __USART_HandleTypeDef *husart)
void(* | TxISR )(struct __USART_HandleTypeDef *husart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxHalfCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxRxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | ErrorCallback )(struct __USART_HandleTypeDef *husart)
void(* | AbortCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxFifoFullCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxFifoEmptyCallback )(struct __USART_HandleTypeDef *husart)
void(* | MspInitCallback )(struct __USART_HandleTypeDef *husart)
void(* | MspDeInitCallback )(struct __USART_HandleTypeDef *husart)

Detailed Description

USART handle Structure definition.

Definition at line 120 of file stm32g0xx_hal_usart.h.

Field Documentation

void(* __USART_HandleTypeDef::AbortCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Abort Complete Callback

Definition at line 171 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort_IT(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::ErrorCallback)(struct __USART_HandleTypeDef *husart)

USART Error Callback

Definition at line 170 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAAbortOnError(), USART_DMAError(), and USART_InitCallbacksToDefault().

__IO uint32_t __USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 162 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAStop(), HAL_USART_GetError(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_RegisterCallback(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USART_UnRegisterCallback(), USART_CheckIdleState(), USART_DMAError(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

uint32_t __USART_HandleTypeDef::FifoMode

Specifies if the FIFO mode will be used. This parameter can be a value of USARTEx FIFO mode.

Definition at line 147 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_EnableFifoMode(), and USARTEx_SetNbDataToProcess().

DMA_HandleTypeDef* __USART_HandleTypeDef::hdmarx

USART Rx DMA Handle parameters

Definition at line 156 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* __USART_HandleTypeDef::hdmatx

USART Tx DMA Handle parameters

Definition at line 154 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

USART_InitTypeDef __USART_HandleTypeDef::Init

USART communication parameters

Definition at line 124 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

USART_TypeDef* __USART_HandleTypeDef::Instance

USART registers base address

Definition at line 122 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), USART_CheckIdleState(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransfer(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_SetConfig(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), and USARTEx_SetNbDataToProcess().

HAL_LockTypeDef __USART_HandleTypeDef::Lock

Locking object

Definition at line 158 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint16_t __USART_HandleTypeDef::Mask

USART Rx RDR register mask

Definition at line 138 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::MspDeInitCallback)(struct __USART_HandleTypeDef *husart)

USART Msp DeInit callback

Definition at line 176 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

void(* __USART_HandleTypeDef::MspInitCallback)(struct __USART_HandleTypeDef *husart)

USART Msp Init callback

Definition at line 175 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

uint16_t __USART_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 140 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT_FIFOEN(), USART_SetConfig(), and USARTEx_SetNbDataToProcess().

uint16_t __USART_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 142 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT_FIFOEN(), and USARTEx_SetNbDataToProcess().

uint8_t* __USART_HandleTypeDef::pRxBuffPtr

Pointer to USART Rx transfer Buffer

Definition at line 132 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

const uint8_t* __USART_HandleTypeDef::pTxBuffPtr

Pointer to USART Tx transfer Buffer

Definition at line 126 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::RxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Complete Callback

Definition at line 168 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::RxFifoFullCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Fifo Full Callback

Definition at line 172 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Half Complete Callback

Definition at line 167 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMARxHalfCplt(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::RxISR)(struct __USART_HandleTypeDef *husart)

Function pointer on Rx IRQ handler

Definition at line 150 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), and USART_SetConfig().

__IO uint16_t __USART_HandleTypeDef::RxXferCount

USART Rx Transfer Counter

Definition at line 136 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

uint16_t __USART_HandleTypeDef::RxXferSize

USART Rx Transfer size

Definition at line 134 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

uint32_t __USART_HandleTypeDef::SlaveMode

Enable/Disable UART SPI Slave Mode. This parameter can be a value of USARTEx Synchronous Slave mode enable

Definition at line 144 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

__IO HAL_USART_StateTypeDef __USART_HandleTypeDef::State

USART communication state

Definition at line 160 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_RegisterCallback(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USART_UnRegisterCallback(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), USART_CheckIdleState(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), and USART_WaitOnFlagUntilTimeout().

void(* __USART_HandleTypeDef::TxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Complete Callback

Definition at line 166 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Fifo Empty Callback

Definition at line 173 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Half Complete Callback

Definition at line 165 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMATxHalfCplt(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxISR)(struct __USART_HandleTypeDef *husart)

Function pointer on Tx IRQ handler

Definition at line 152 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_EndTransmit_IT(), and USART_SetConfig().

void(* __USART_HandleTypeDef::TxRxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Rx Complete Callback

Definition at line 169 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_EndTransmit_IT(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

__IO uint16_t __USART_HandleTypeDef::TxXferCount

USART Tx Transfer Counter

Definition at line 130 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

uint16_t __USART_HandleTypeDef::TxXferSize

USART Tx Transfer size

Definition at line 128 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_usart.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Error Definition

Defines
USART Error Definition
USART Exported Constants

Defines

#define | HAL_USART_ERROR_NONE (0x00000000U)
#define | HAL_USART_ERROR_PE (0x00000001U)
#define | HAL_USART_ERROR_NE (0x00000002U)
#define | HAL_USART_ERROR_FE (0x00000004U)
#define | HAL_USART_ERROR_ORE (0x00000008U)
#define | HAL_USART_ERROR_DMA (0x00000010U)
#define | HAL_USART_ERROR_UDR (0x00000020U)
#define | HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)
#define | HAL_USART_ERROR_RTO (0x00000080U)

Define Documentation

#define HAL_USART_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 226 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and USART_DMAError().

#define HAL_USART_ERROR_FE (0x00000004U)

Frame error

Definition at line 224 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)

Invalid Callback error

Definition at line 229 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

#define HAL_USART_ERROR_NE (0x00000002U)

Noise error

Definition at line 223 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NONE (0x00000000U)

No error

Definition at line 221 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define HAL_USART_ERROR_ORE (0x00000008U)

Overrun error

Definition at line 225 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_PE (0x00000001U)

Parity error

Definition at line 222 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_RTO (0x00000080U)

Receiver Timeout error

Definition at line 231 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_UDR (0x00000020U)

SPI slave underrun error

Definition at line 227 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define USART_STOPBITS_0_5 USART_CR2_STOP_0

USART frame with 0.5 stop bit

Definition at line 239 of file stm32g0xx_hal_usart.h.

#define USART_STOPBITS_1 0x00000000U

USART frame with 1 stop bit

Definition at line 240 of file stm32g0xx_hal_usart.h.

#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

USART frame with 1.5 stop bits

Definition at line 241 of file stm32g0xx_hal_usart.h.

#define USART_STOPBITS_2 USART_CR2_STOP_1

USART frame with 2 stop bits

Definition at line 242 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN USART_CR1_PCE
#define | USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define USART_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 251 of file stm32g0xx_hal_usart.h.

#define USART_PARITY_NONE 0x00000000U

No parity

Definition at line 250 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 252 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX USART_CR1_RE
#define | USART_MODE_TX USART_CR1_TE
#define | USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define USART_MODE_RX USART_CR1_RE

RX mode

Definition at line 260 of file stm32g0xx_hal_usart.h.

#define USART_MODE_TX USART_CR1_TE

TX mode

Definition at line 261 of file stm32g0xx_hal_usart.h.

#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 262 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define USART_CLOCK_DISABLE 0x00000000U

USART clock disable

Definition at line 270 of file stm32g0xx_hal_usart.h.

#define USART_CLOCK_ENABLE USART_CR2_CLKEN

USART clock enable

Definition at line 271 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define USART_POLARITY_HIGH USART_CR2_CPOL

Driver enable signal is active low

Definition at line 280 of file stm32g0xx_hal_usart.h.

#define USART_POLARITY_LOW 0x00000000U

Driver enable signal is active high

Definition at line 279 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define USART_PHASE_1EDGE 0x00000000U

USART frame phase on first clock transition

Definition at line 288 of file stm32g0xx_hal_usart.h.

#define USART_PHASE_2EDGE USART_CR2_CPHA

USART frame phase on second clock transition

Definition at line 289 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE USART_CR2_LBCL

Define Documentation

#define USART_LASTBIT_DISABLE 0x00000000U

USART frame last data bit clock pulse not output to SCLK pin

Definition at line 297 of file stm32g0xx_hal_usart.h.

#define USART_LASTBIT_ENABLE USART_CR2_LBCL

USART frame last data bit clock pulse output to SCLK pin

Definition at line 298 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Clock Prescaler

Defines
USART Clock Prescaler
USART Exported Constants

Defines

#define | USART_PRESCALER_DIV1 0x00000000U
#define | USART_PRESCALER_DIV2 0x00000001U
#define | USART_PRESCALER_DIV4 0x00000002U
#define | USART_PRESCALER_DIV6 0x00000003U
#define | USART_PRESCALER_DIV8 0x00000004U
#define | USART_PRESCALER_DIV10 0x00000005U
#define | USART_PRESCALER_DIV12 0x00000006U
#define | USART_PRESCALER_DIV16 0x00000007U
#define | USART_PRESCALER_DIV32 0x00000008U
#define | USART_PRESCALER_DIV64 0x00000009U
#define | USART_PRESCALER_DIV128 0x0000000AU
#define | USART_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define USART_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 306 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 311 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 312 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 316 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 313 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 307 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 317 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 314 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 308 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 309 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 315 of file stm32g0xx_hal_usart.h.

#define USART_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 310 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Request Parameters

Defines
USART Request Parameters
USART Exported Constants

Defines

#define | USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 326 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), USART_EndTransmit_IT(), USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 327 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Transmit(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | USART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | USART_FLAG_RTOF USART_ISR_RTOF
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define USART_FLAG_BUSY USART_ISR_BUSY

USART busy flag

Definition at line 343 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_FE USART_ISR_FE

USART frame error

Definition at line 354 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_IDLE USART_ISR_IDLE

USART idle flag

Definition at line 351 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_NE USART_ISR_NE

USART noise error

Definition at line 353 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_ORE USART_ISR_ORE

USART overrun error

Definition at line 352 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_PE USART_ISR_PE

USART parity error

Definition at line 355 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_REACK USART_ISR_REACK

USART receive enable acknowledge flag

Definition at line 341 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_RTOF USART_ISR_RTOF

USART receiver timeout flag

Definition at line 347 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_RXFF USART_ISR_RXFF

USART RXFIFO Full flag

Definition at line 339 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE

USART RXFIFO not empty

Definition at line 350 of file stm32g0xx_hal_usart.h.

Referenced by USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

#define USART_FLAG_RXFT USART_ISR_RXFT

USART RXFIFO threshold flag

Definition at line 338 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE

USART read data register not empty

Definition at line 349 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TC USART_ISR_TC

USART transmission complete

Definition at line 348 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Transmit().

#define USART_FLAG_TEACK USART_ISR_TEACK

USART transmit enable acknowledge flag

Definition at line 342 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_TXE USART_ISR_TXE_TXFNF

USART transmit data register empty

Definition at line 345 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TXFE USART_ISR_TXFE

USART TXFIFO Empty flag

Definition at line 340 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF

USART TXFIFO not full

Definition at line 346 of file stm32g0xx_hal_usart.h.

Referenced by USART_TxISR_16BIT_FIFOEN(), and USART_TxISR_8BIT_FIFOEN().

#define USART_FLAG_TXFT USART_ISR_TXFT

USART TXFIFO threshold flag

Definition at line 337 of file stm32g0xx_hal_usart.h.

#define USART_FLAG_UDR USART_ISR_UDR

SPI slave underrun error flag

Definition at line 344 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | USART_IT_PE 0x0028U
#define | USART_IT_TXE 0x0727U
#define | USART_IT_TXFNF 0x0727U
#define | USART_IT_TC 0x0626U
#define | USART_IT_RXNE 0x0525U
#define | USART_IT_RXFNE 0x0525U
#define | USART_IT_IDLE 0x0424U
#define | USART_IT_ERR 0x0060U
#define | USART_IT_ORE 0x0300U
#define | USART_IT_NE 0x0200U
#define | USART_IT_FE 0x0100U
#define | USART_IT_RXFF 0x183FU
#define | USART_IT_TXFE 0x173EU
#define | USART_IT_RXFT 0x1A7CU
#define | USART_IT_TXFT 0x1B77U

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define USART_IT_ERR 0x0060U

USART error interruption

Definition at line 378 of file stm32g0xx_hal_usart.h.

Referenced by USART_EndTransmit_IT().

#define USART_IT_FE 0x0100U

USART frame error interruption

Definition at line 381 of file stm32g0xx_hal_usart.h.

#define USART_IT_IDLE 0x0424U

USART idle interruption

Definition at line 377 of file stm32g0xx_hal_usart.h.

#define USART_IT_NE 0x0200U

USART noise error interruption

Definition at line 380 of file stm32g0xx_hal_usart.h.

#define USART_IT_ORE 0x0300U

USART overrun error interruption

Definition at line 379 of file stm32g0xx_hal_usart.h.

#define USART_IT_PE 0x0028U

USART parity error interruption

Definition at line 371 of file stm32g0xx_hal_usart.h.

#define USART_IT_RXFF 0x183FU

USART RXFIFO full interruption

Definition at line 382 of file stm32g0xx_hal_usart.h.

#define USART_IT_RXFNE 0x0525U

USART RXFIFO not empty interruption

Definition at line 376 of file stm32g0xx_hal_usart.h.

#define USART_IT_RXFT 0x1A7CU

USART RXFIFO threshold reached interruption

Definition at line 384 of file stm32g0xx_hal_usart.h.

#define USART_IT_RXNE 0x0525U

USART read data register not empty interruption

Definition at line 375 of file stm32g0xx_hal_usart.h.

#define USART_IT_TC 0x0626U

USART transmission complete interruption

Definition at line 374 of file stm32g0xx_hal_usart.h.

Referenced by USART_DMATransmitCplt(), USART_EndTransmit_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define USART_IT_TXE 0x0727U

USART transmit data register empty interruption

Definition at line 372 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_TxISR_16BIT(), and USART_TxISR_8BIT().

#define USART_IT_TXFE 0x173EU

USART TXFIFO empty interruption

Definition at line 383 of file stm32g0xx_hal_usart.h.

#define USART_IT_TXFNF 0x0727U

USART TX FIFO not full interruption

Definition at line 373 of file stm32g0xx_hal_usart.h.

#define USART_IT_TXFT 0x1B77U

USART TXFIFO threshold reached interruption

Definition at line 385 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_TxISR_16BIT_FIFOEN(), and USART_TxISR_8BIT_FIFOEN().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Interruption Clear Flags

Defines
USART Interruption Clear Flags
USART Exported Constants

Defines

#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NECF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF
#define | USART_CLEAR_RTOF USART_ICR_RTOCF

Define Documentation

#define USART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 395 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 398 of file stm32g0xx_hal_usart.h.

#define USART_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 396 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 397 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 394 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_RTOF USART_ICR_RTOCF

USART receiver timeout clear flag

Definition at line 402 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 399 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define USART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO Empty Clear Flag

Definition at line 401 of file stm32g0xx_hal_usart.h.

#define USART_CLEAR_UDRF USART_ICR_UDRCF

SPI slave underrun error Clear Flag

Definition at line 400 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Interruption Flags Mask

Defines
USART Interruption Flags Mask
USART Exported Constants

Defines

#define | USART_IT_MASK 0x001FU
#define | USART_CR_MASK 0x00E0U
#define | USART_CR_POS 5U
#define | USART_ISR_MASK 0x1F00U
#define | USART_ISR_POS 8U

Define Documentation

#define USART_CR_MASK 0x00E0U

USART control register mask

Definition at line 411 of file stm32g0xx_hal_usart.h.

#define USART_CR_POS 5U

USART control register position

Definition at line 412 of file stm32g0xx_hal_usart.h.

#define USART_ISR_MASK 0x1F00U

USART ISR register mask

Definition at line 413 of file stm32g0xx_hal_usart.h.

#define USART_ISR_POS 8U

USART ISR register position

Definition at line 414 of file stm32g0xx_hal_usart.h.

#define USART_IT_MASK 0x001FU

USART interruptions flags mask

Definition at line 410 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
Clear SPI slave underrun error flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)

Clear the USART FE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 496 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified USART pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF Overrun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_TXFECF TXFIFO empty clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
  • USART_CLEAR_RTOF Receiver Timeout clear flag
  • USART_CLEAR_UDRF SPI slave underrun error Clear Flag
Return values:
None

Definition at line 484 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 514 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified USART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF Overrun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_RTOF Receiver timeout clear flag
  • USART_CLEAR_TXFECF TXFIFO empty clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 645 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)

Clear the USART NE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 502 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)

Clear the USART ORE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 508 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), and USART_EndTransmit_IT().

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)

Clear the USART PE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 490 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)

Clear the USART TX FIFO empty clear flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 520 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_CLEAR_UDRFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)

Clear SPI slave underrun error flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 526 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define __HAL_USART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 680 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), and HAL_USARTEx_SetTxFifoThreshold().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
   ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
   ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
   ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
   ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Disable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 571 of file stm32g0xx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define __HAL_USART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 674 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Init(), and HAL_USARTEx_EnableSlaveMode().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
   ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
   ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
   ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
   ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Enable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 546 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_DMATransmitCplt(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified USART flag is set or not.

Parameters:
__HANDLE__ specifies the USART Handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_TXFT TXFIFO threshold flag
  • USART_FLAG_RXFT RXFIFO threshold flag
  • USART_FLAG_RXFF RXFIFO Full flag
  • USART_FLAG_TXFE TXFIFO Empty flag
  • USART_FLAG_REACK Receive enable acknowledge flag
  • USART_FLAG_TEACK Transmit enable acknowledge flag
  • USART_FLAG_BUSY Busy flag
  • USART_FLAG_UDR SPI slave underrun error flag
  • USART_FLAG_TXE Transmit data register empty flag
  • USART_FLAG_TXFNF TXFIFO not full flag
  • USART_FLAG_TC Transmission Complete flag
  • USART_FLAG_RXNE Receive data register not empty flag
  • USART_FLAG_RXFNE RXFIFO not empty flag
  • USART_FLAG_RTOF Receiver Timeout flag
  • USART_FLAG_IDLE Idle Line detection flag
  • USART_FLAG_ORE OverRun Error flag
  • USART_FLAG_NE Noise Error flag
  • USART_FLAG_FE Framing Error flag
  • USART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 467 of file stm32g0xx_hal_usart.h.

Referenced by USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT_FIFOEN(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                         & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
                                                                      USART_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 598 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
                                                                 (__HANDLE__)->Instance->CR1 : \
                                                                 (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
                                                                  (__HANDLE__)->Instance->CR2 : \
                                                                  (__HANDLE__)->Instance->CR3)) & (0x01U <<\
                                                                      (((uint16_t)(__INTERRUPT__)) &\
                                                                       USART_IT_MASK)))  != 0U) ? SET : RESET)

Check whether the specified USART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 622 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

Disable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 668 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 662 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                        (__HANDLE__)->State = HAL_USART_STATE_RESET; \
                                                        (__HANDLE__)->MspInitCallback = NULL;        \
                                                        (__HANDLE__)->MspDeInitCallback = NULL;      \
                                                      } while(0U)

Reset USART handle state.

Parameters:
__HANDLE__ USART handle.
Return values:
None

Definition at line 433 of file stm32g0xx_hal_usart.h.

#define __HAL_USART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific USART request flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__REQ__ specifies the request flag to set. This parameter can be one of the following values:
  • USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 656 of file stm32g0xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Transmit(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | USART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get USART clock division factor from clock prescaler value.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__CLOCKPRESCALER__)
Ensure that USART Prescaler is valid.

Define Documentation

#define IS_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 8000000U)

Check USART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 64 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 724 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == USART_CLOCK_DISABLE) || \
                                   ((__CLOCK__) == USART_CLOCK_ENABLE))

Ensure that USART clock state is valid.

Parameters:
__CLOCK__ USART clock state.
Return values:
SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)

Definition at line 757 of file stm32g0xx_hal_usart.h.

#define IS_USART_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

Ensure that USART frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ USART frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 779 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( __MODE__ ) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that USART communication mode is valid.

Parameters:
__MODE__ USART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 750 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == USART_PARITY_NONE) || \
                                     ((__PARITY__) == USART_PARITY_EVEN) || \
                                     ((__PARITY__) == USART_PARITY_ODD))

Ensure that USART frame parity is valid.

Parameters:
__PARITY__ USART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 741 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( __CPHA__ ) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

Ensure that USART frame phase is valid.

Parameters:
__CPHA__ USART frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 772 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( __CPOL__ ) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

Ensure that USART frame polarity is valid.

Parameters:
__CPOL__ USART frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 765 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))

Ensure that USART Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ USART Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 795 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

Ensure that USART request parameter is valid.

Parameters:
__PARAM__ USART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 787 of file stm32g0xx_hal_usart.h.

#define IS_USART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == USART_STOPBITS_0_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_2))

Ensure that USART frame number of stop bits is valid.

Parameters:
__STOPBITS__ USART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 731 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
(((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
    + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | USART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | USART prescaler value.
Return values:
Division result

Definition at line 715 of file stm32g0xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_GET_DIV_FACTOR ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)

Get USART clock division factor from clock prescaler value.

Parameters:
__CLOCKPRESCALER__ USART prescaler value.
Return values:
USART clock division factor

Definition at line 695 of file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx Private Constants

Defines
USARTEx Private Constants
USARTEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 61 of file stm32g0xx_hal_usart_ex.c.

Referenced by USARTEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 64 of file stm32g0xx_hal_usart_ex.c.

Referenced by USARTEx_SetNbDataToProcess().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx Private Functions

Functions
USARTEx Private Functions
USARTEx

Functions

static void USARTEx_SetNbDataToProcess (USART_HandleTypeDef *husart)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void USARTEx_SetNbDataToProcess ( USART_HandleTypeDef * husart ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the USART configuration registers.
Parameters:
husart USART handle.
Return values:
None

Definition at line 499 of file stm32g0xx_hal_usart_ex.c.

References __USART_HandleTypeDef::FifoMode, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, TX_FIFO_DEPTH, and USART_FIFOMODE_DISABLE.

Referenced by HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_SetRxFifoThreshold(), and HAL_USARTEx_SetTxFifoThreshold().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
USARTEx Exported Functions

Extended USART Transmit/Receive functions. More...

Functions

__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.

Detailed Description

Extended USART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of FIFO mode related callback functions.

    (#) TX/RX Fifos Callbacks:
        (+) HAL_USARTEx_RxFifoFullCallback()
        (+) HAL_USARTEx_TxFifoEmptyCallback()

Function Documentation

void HAL_USARTEx_RxFifoFullCallback ( USART_HandleTypeDef * husart )

USART RX Fifo full callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 109 of file stm32g0xx_hal_usart_ex.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void HAL_USARTEx_TxFifoEmptyCallback ( USART_HandleTypeDef * husart )

USART TX Fifo empty callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 124 of file stm32g0xx_hal_usart_ex.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
USARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
     (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
     (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
     (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_USARTEx_ConfigNSS | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | NSSConfig
 | ) |  |

Configure the Slave Select input pin (NSS).

Note:
Software NSS management: SPI slave will always be selected and NSS input pin will be ignored.
Hardware NSS management: the SPI slave selection depends on NSS input pin. The slave is selected when NSS is low and deselected when NSS is high.
Parameters:
husart USART handle.
NSSConfig NSS configuration. This parameter can be one of the following values:
  • USART_NSS_HARD
  • USART_NSS_SOFT
Return values:
HAL status

Definition at line 270 of file stm32g0xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_NSS, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode ( USART_HandleTypeDef * husart )

Disable the FIFO mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 349 of file stm32g0xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, __USART_HandleTypeDef::FifoMode, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode ( USART_HandleTypeDef * husart )

Disable the SPI slave mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 222 of file stm32g0xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, and USART_SLAVEMODE_DISABLE.

HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode ( USART_HandleTypeDef * husart )

Enable the FIFO mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 308 of file stm32g0xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, __USART_HandleTypeDef::FifoMode, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, USART_FIFOMODE_ENABLE, and USARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode ( USART_HandleTypeDef * husart )

Enable the SPI slave mode.

Note:
When the USART operates in SPI slave mode, it handles data flow using the serial interface clock derived from the external SCLK signal provided by the external master SPI device.
In SPI slave mode, the USART must be enabled before starting the master communications (or between frames while the clock is stable). Otherwise, if the USART slave is enabled while the master is in the middle of a frame, it will become desynchronized with the master.
The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication, otherwise the SPI slave will transmit zeros.
Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 174 of file stm32g0xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, and USART_SLAVEMODE_ENABLE.

HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
husart USART handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • USART_RXFIFO_THRESHOLD_1_8
  • USART_RXFIFO_THRESHOLD_1_4
  • USART_RXFIFO_THRESHOLD_1_2
  • USART_RXFIFO_THRESHOLD_3_4
  • USART_RXFIFO_THRESHOLD_7_8
  • USART_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 444 of file stm32g0xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_RXFIFO_THRESHOLD, __USART_HandleTypeDef::State, and USARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
husart USART handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • USART_TXFIFO_THRESHOLD_1_8
  • USART_TXFIFO_THRESHOLD_1_4
  • USART_TXFIFO_THRESHOLD_1_2
  • USART_TXFIFO_THRESHOLD_3_4
  • USART_TXFIFO_THRESHOLD_7_8
  • USART_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 395 of file stm32g0xx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_TXFIFO_THRESHOLD, __USART_HandleTypeDef::State, and USARTEx_SetNbDataToProcess().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx Word Length

Defines
USARTEx Word Length
USARTEx Exported Constants

Defines

#define | USART_WORDLENGTH_7B (USART_CR1_M1)
#define | USART_WORDLENGTH_8B (0x00000000U)
#define | USART_WORDLENGTH_9B (USART_CR1_M0)

Define Documentation

#define USART_WORDLENGTH_7B (USART_CR1_M1)

7-bit long USART frame

Definition at line 47 of file stm32g0xx_hal_usart_ex.h.

#define USART_WORDLENGTH_8B (0x00000000U)

8-bit long USART frame

Definition at line 48 of file stm32g0xx_hal_usart_ex.h.

#define USART_WORDLENGTH_9B (USART_CR1_M0)

9-bit long USART frame

Definition at line 49 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx Slave Select Management

Defines
USARTEx Slave Select Management
USARTEx Exported Constants

Defines

#define | USART_NSS_HARD 0x00000000U
#define | USART_NSS_SOFT USART_CR2_DIS_NSS

Define Documentation

#define USART_NSS_HARD 0x00000000U

SPI slave selection depends on NSS input pin

Definition at line 57 of file stm32g0xx_hal_usart_ex.h.

#define USART_NSS_SOFT USART_CR2_DIS_NSS

SPI slave is always selected and NSS input pin is ignored

Definition at line 58 of file stm32g0xx_hal_usart_ex.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx Synchronous Slave mode enable

Defines
USARTEx Synchronous Slave mode enable
USARTEx Exported Constants

USART SLAVE mode. More...

Defines

#define | USART_SLAVEMODE_DISABLE 0x00000000U
#define | USART_SLAVEMODE_ENABLE USART_CR2_SLVEN

Detailed Description

USART SLAVE mode.

Define Documentation

#define USART_SLAVEMODE_DISABLE 0x00000000U

USART SPI Slave Mode Enable

Definition at line 68 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USARTEx_DisableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN

USART SPI Slave Mode Disable

Definition at line 69 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), HAL_USARTEx_EnableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx FIFO mode

Defines
USARTEx FIFO mode
USARTEx Exported Constants

USART FIFO mode. More...

Defines

#define | USART_FIFOMODE_DISABLE 0x00000000U
#define | USART_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

USART FIFO mode.

Define Documentation

#define USART_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 78 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_DisableFifoMode(), and USARTEx_SetNbDataToProcess().

#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 79 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), and HAL_USARTEx_EnableFifoMode().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx TXFIFO threshold level

Defines
USARTEx TXFIFO threshold level
USARTEx Exported Constants

USART TXFIFO level. More...

Defines

#define | USART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

USART TXFIFO level.

Define Documentation

#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 90 of file stm32g0xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 89 of file stm32g0xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 88 of file stm32g0xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 91 of file stm32g0xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 92 of file stm32g0xx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 93 of file stm32g0xx_hal_usart_ex.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx RXFIFO threshold level

Defines
USARTEx RXFIFO threshold level
USARTEx Exported Constants

USART RXFIFO level. More...

Defines

#define | USART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

USART RXFIFO level.

Define Documentation

#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 104 of file stm32g0xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 103 of file stm32g0xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 102 of file stm32g0xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 105 of file stm32g0xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 106 of file stm32g0xx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 107 of file stm32g0xx_hal_usart_ex.h.

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STM32G0C1xx HAL User Manual: USARTEx Private Macros

Defines
USARTEx Private Macros
USARTEx

Defines

#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.
#define | IS_USART_NSS(__NSS__)
Ensure that USART Negative Slave Select (NSS) pin management is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.

Define Documentation

#define IS_USART_FIFO_MODE_STATE ( __STATE__ )
Value:
(((__STATE__) == USART_FIFOMODE_DISABLE ) || \
                                             ((__STATE__) == USART_FIFOMODE_ENABLE))

Ensure that USART FIFO mode is valid.

Parameters:
__STATE__ USART FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 381 of file stm32g0xx_hal_usart_ex.h.

#define IS_USART_NSS ( __NSS__ )
Value:
(((__NSS__) == USART_NSS_HARD) || \
                               ((__NSS__) == USART_NSS_SOFT))

Ensure that USART Negative Slave Select (NSS) pin management is valid.

Parameters:
__NSS__ USART Negative Slave Select pin management.
Return values:
SET (__NSS__ is valid) or RESET (__NSS__ is invalid)

Definition at line 365 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_ConfigNSS().

#define IS_USART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))

Ensure that USART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ USART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 401 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_SetRxFifoThreshold().

#define IS_USART_SLAVEMODE ( __STATE__ )
Value:
(((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
                                         ((__STATE__) == USART_SLAVEMODE_ENABLE))

Ensure that USART Slave Mode is valid.

Parameters:
__STATE__ USART Slave Mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 373 of file stm32g0xx_hal_usart_ex.h.

#define IS_USART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))

Ensure that USART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ USART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 389 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USARTEx_SetTxFifoThreshold().

#define IS_USART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == USART_WORDLENGTH_7B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

Ensure that USART frame length is valid.

Parameters:
__LENGTH__ USART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 356 of file stm32g0xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the USART clock source.

Parameters:
__HANDLE__ | specifies the USART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 127 of file stm32g0xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_MASK_COMPUTATION ( __HANDLE__ )

Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None,the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 310 of file stm32g0xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

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STM32G0C1xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Initialize and start the WWDG according to the specified parameters
          in the WWDG_InitTypeDef of associated handle.
      (+) Initialize the WWDG MSP.

Function Documentation

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG according to the specified.

parameters in the WWDG_InitTypeDef of associated handle.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 176 of file stm32g0xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, __WWDG_HandleTypeDef::EwiCallback, WWDG_InitTypeDef::EWIMode, HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_MspInit(), __WWDG_HandleTypeDef::Init, __WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_EWI_MODE, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, __WWDG_HandleTypeDef::MspInitCallback, WWDG_InitTypeDef::Prescaler, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG MSP.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Note:
When rewriting this function in user file, mechanism may be added to avoid multiple initialize when HAL_WWDG_Init function is called again to change parameters.
Return values:
None

Definition at line 230 of file stm32g0xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_UnRegisterCallback().

HAL_StatusTypeDef HAL_WWDG_RegisterCallback | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | HAL_WWDG_CallbackIDTypeDef | CallbackID,
 |  | pWWDG_CallbackTypeDef | pCallback
 | ) |  |

Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hwwdg | WWDG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
  • HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 253 of file stm32g0xx_hal_wwdg.c.

References __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EWI_CB_ID, HAL_WWDG_MSPINIT_CB_ID, and __WWDG_HandleTypeDef::MspInitCallback.

HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | HAL_WWDG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hwwdg WWDG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
  • HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
Return values:
status

Definition at line 294 of file stm32g0xx_hal_wwdg.c.

References __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_EWI_CB_ID, HAL_WWDG_MspInit(), HAL_WWDG_MSPINIT_CB_ID, and __WWDG_HandleTypeDef::MspInitCallback.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request and associated function callback.

Function Documentation

void HAL_WWDG_EarlyWakeupCallback ( WWDG_HandleTypeDef * hwwdg )

WWDG Early Wakeup callback.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 395 of file stm32g0xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), and HAL_WWDG_UnRegisterCallback().

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handle WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Init function with EWIMode set to WWDG_EWI_ENABLE. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 366 of file stm32g0xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EarlyWakeupCallback(), WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh ( WWDG_HandleTypeDef * hwwdg )

Refresh the WWDG.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 343 of file stm32g0xx_hal_wwdg.c.

References WWDG_InitTypeDef::Counter, __WWDG_HandleTypeDef::Init, and __WWDG_HandleTypeDef::Instance.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Exported Types

Data Structures | Typedefs | Enumerations
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | __WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Typedefs

typedef struct __WWDG_HandleTypeDef | WWDG_HandleTypeDef
WWDG handle Structure definition.
typedef void(* | pWWDG_CallbackTypeDef )(WWDG_HandleTypeDef *hppp)
HAL WWDG Callback pointer definition.

Enumerations

enum | HAL_WWDG_CallbackIDTypeDef { HAL_WWDG_EWI_CB_ID = 0x00U, HAL_WWDG_MSPINIT_CB_ID = 0x01U }
HAL WWDG common Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp)

HAL WWDG Callback pointer definition.

pointer to a WWDG common callback functions

Definition at line 96 of file stm32g0xx_hal_wwdg.h.

typedef struct __WWDG_HandleTypeDef WWDG_HandleTypeDef

WWDG handle Structure definition.

Enumeration Type Documentation

enum HAL_WWDG_CallbackIDTypeDef

HAL WWDG common Callback ID enumeration definition.

Enumerator:
HAL_WWDG_EWI_CB_ID

WWDG EWI callback ID

HAL_WWDG_MSPINIT_CB_ID

WWDG MspInit callback ID

Definition at line 87 of file stm32g0xx_hal_wwdg.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32g0xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter
uint32_t | EWIMode

Detailed Description

WWDG Init structure definition.

Definition at line 47 of file stm32g0xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 55 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

uint32_t WWDG_InitTypeDef::EWIMode

Specifies if WWDG Early Wakeup Interrupt is enable or not. This parameter can be a value of WWDG Early Wakeup Interrupt Mode

Definition at line 58 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 49 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 52 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_wwdg.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: __WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32g0xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * | Instance
WWDG_InitTypeDef Init
void(* | EwiCallback )(struct __WWDG_HandleTypeDef *hwwdg)
void(* | MspInitCallback )(struct __WWDG_HandleTypeDef *hwwdg)

Detailed Description

WWDG handle Structure definition.

Definition at line 67 of file stm32g0xx_hal_wwdg.h.

Field Documentation

void(* __WWDG_HandleTypeDef::EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg)

WWDG Early WakeUp Interrupt callback

Definition at line 77 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), HAL_WWDG_RegisterCallback(), and HAL_WWDG_UnRegisterCallback().

WWDG_InitTypeDef __WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 74 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

WWDG_TypeDef* __WWDG_HandleTypeDef::Instance

Register base address

Definition at line 72 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

void(* __WWDG_HandleTypeDef::MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg)

WWDG Msp Init callback

Definition at line 79 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), HAL_WWDG_RegisterCallback(), and HAL_WWDG_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32g0xx_hal_wwdg.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 112 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 121 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 129 of file stm32g0xx_hal_wwdg.h.

#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096)/128

Definition at line 136 of file stm32g0xx_hal_wwdg.h.

#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2

WWDG counter clock = (PCLK1/4096)/16

Definition at line 133 of file stm32g0xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 130 of file stm32g0xx_hal_wwdg.h.

#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/32

Definition at line 134 of file stm32g0xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 131 of file stm32g0xx_hal_wwdg.h.

#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/64

Definition at line 135 of file stm32g0xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 132 of file stm32g0xx_hal_wwdg.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Early Wakeup Interrupt Mode

Defines
WWDG Early Wakeup Interrupt Mode
WWDG Exported Constants

Defines

#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI

Define Documentation

#define WWDG_EWI_DISABLE 0x00000000u

EWI Disable

Definition at line 144 of file stm32g0xx_hal_wwdg.h.

#define WWDG_EWI_ENABLE WWDG_CFR_EWI

EWI Enable

Definition at line 145 of file stm32g0xx_hal_wwdg.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))

Definition at line 170 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_EWI_MODE ( __MODE__ )
Value:
(((__MODE__) == WWDG_EWI_ENABLE) || \
                                             ((__MODE__) == WWDG_EWI_DISABLE))

Definition at line 172 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_16) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_32) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_64) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_128))

Definition at line 159 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))

Definition at line 168 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified WWDG interrupt source is enabled or not.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the WWDG's pending flags.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 240 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG interrupt pending bits.

bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 220 of file stm32g0xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enable the WWDG peripheral.

Parameters:
__HANDLE__ WWDG handle
Return values:
None

Definition at line 190 of file stm32g0xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enable the WWDG early wakeup interrupt.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 201 of file stm32g0xx_hal_wwdg.h.

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified WWDG flag is set or not.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 230 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Check whether the selected WWDG interrupt has occurred or not.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 211 of file stm32g0xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__HANDLE__)->Instance->CFR\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified WWDG interrupt source is enabled or not.

Parameters:
__HANDLE__ WWDG Handle.
__INTERRUPT__ specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 249 of file stm32g0xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
#define | ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
#define | ADC_CHANNEL_ID_MASK
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
#define | ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
#define | ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define | ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
#define | ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
#define | ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
#define | ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_15_NUMBER
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
#define | ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
#define | ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
#define | ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
#define | ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define | ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define | ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define | ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define | ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
#define | ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
#define | ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
#define | ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */
#define | ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
#define | ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
#define | ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
#define | ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
#define | ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
#define | ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
#define | ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
#define | ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
#define | ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
#define | ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
#define | ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
#define | ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
#define | ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
#define | ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
#define | ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
#define | ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
#define | ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
#define | ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
#define | ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
#define | ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
#define | ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
#define | ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
#define | ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
#define | ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
#define | ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define | VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

Define Documentation

#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)

Definition at line 187 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)

Definition at line 188 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

Definition at line 193 of file stm32g0xx_ll_adc.h.

#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)

Definition at line 181 of file stm32g0xx_ll_adc.h.

#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 194 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)

Definition at line 182 of file stm32g0xx_ll_adc.h.

#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)

Definition at line 183 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

Definition at line 195 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)

Definition at line 191 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_SetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

Definition at line 190 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

Definition at line 197 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)

Definition at line 200 of file stm32g0xx_ll_adc.h.

#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)

Definition at line 201 of file stm32g0xx_ll_adc.h.

#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))

Definition at line 202 of file stm32g0xx_ll_adc.h.

#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */

Definition at line 205 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */

Definition at line 206 of file stm32g0xx_ll_adc.h.

#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */

Definition at line 207 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)

Definition at line 208 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

Definition at line 203 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */

Definition at line 204 of file stm32g0xx_ll_adc.h.

#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */

Definition at line 214 of file stm32g0xx_ll_adc.h.

#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */

Definition at line 213 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)

Definition at line 139 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_0_NUMBER (0x00000000UL)

Definition at line 116 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)

Definition at line 149 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)

Definition at line 126 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)

Definition at line 150 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)

Definition at line 127 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)

Definition at line 151 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)

Definition at line 128 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)

Definition at line 152 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)

Definition at line 129 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)

Definition at line 153 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)

Definition at line 130 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)

Definition at line 154 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_15_NUMBER
Value:
(ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
                                            ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)

Definition at line 131 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)

Definition at line 155 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)

Definition at line 133 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)

Definition at line 156 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)

Definition at line 134 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)

Definition at line 157 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)

Definition at line 135 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)

Definition at line 140 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)

Definition at line 117 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)

Definition at line 141 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)

Definition at line 118 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)

Definition at line 142 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)

Definition at line 119 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)

Definition at line 143 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)

Definition at line 120 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)

Definition at line 144 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)

Definition at line 121 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)

Definition at line 145 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)

Definition at line 122 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)

Definition at line 146 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)

Definition at line 123 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)

Definition at line 147 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)

Definition at line 124 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)

Definition at line 148 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)

Definition at line 125 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)

Definition at line 102 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_SetSequencerChAdd(), LL_ADC_REG_SetSequencerChannels(), and LL_ADC_REG_SetSequencerChRem().

#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */

Definition at line 111 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)

Definition at line 112 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_ID_MASK
Value:
(ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
                                            ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Definition at line 105 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */

Definition at line 104 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)

Definition at line 101 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime().

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

Definition at line 108 of file stm32g0xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */

Definition at line 103 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_SetSequencerRanks().

#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */

Definition at line 216 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */

Definition at line 226 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */

Definition at line 227 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */

Definition at line 228 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */

Definition at line 229 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */

Definition at line 230 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */

Definition at line 231 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */

Definition at line 232 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */

Definition at line 233 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */

Definition at line 234 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */

Definition at line 217 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */

Definition at line 218 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */

Definition at line 219 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */

Definition at line 220 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */

Definition at line 221 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */

Definition at line 222 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */

Definition at line 223 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */

Definition at line 224 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */

Definition at line 225 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)

Definition at line 66 of file stm32g0xx_ll_adc.c.

#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

Definition at line 241 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_Disable(), LL_ADC_DisableInternalRegulator(), LL_ADC_Enable(), LL_ADC_EnableInternalRegulator(), LL_ADC_REG_StartConversion(), LL_ADC_REG_StopConversion(), and LL_ADC_StartCalibration().

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */

Definition at line 56 of file stm32g0xx_ll_adc.h.

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */

Definition at line 57 of file stm32g0xx_ll_adc.h.

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */

Definition at line 58 of file stm32g0xx_ll_adc.h.

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */

Definition at line 59 of file stm32g0xx_ll_adc.h.

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */

Definition at line 60 of file stm32g0xx_ll_adc.h.

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */

Definition at line 61 of file stm32g0xx_ll_adc.h.

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */

Definition at line 62 of file stm32g0xx_ll_adc.h.

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */

Definition at line 63 of file stm32g0xx_ll_adc.h.

#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 52 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_TRIG_EDGE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

Definition at line 84 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 71 of file stm32g0xx_ll_adc.h.

#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */

Definition at line 91 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */

Definition at line 90 of file stm32g0xx_ll_adc.h.

#define ADC_REG_TRIG_SOURCE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 1UL)) | \
                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 2UL)) | \
                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 3UL))  )

Definition at line 76 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)

Definition at line 167 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)

Definition at line 168 of file stm32g0xx_ll_adc.h.

#define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)

Definition at line 169 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetSamplingTimeCommonChannels(), and LL_ADC_SetSamplingTimeCommonChannels().

#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */

Definition at line 235 of file stm32g0xx_ll_adc.h.

#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */

Definition at line 236 of file stm32g0xx_ll_adc.h.

#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */

Definition at line 237 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)

Definition at line 72 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 67 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 68 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */

Definition at line 215 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds().

#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 249 of file stm32g0xx_ll_adc.h.

#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 251 of file stm32g0xx_ll_adc.h.

#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 250 of file stm32g0xx_ll_adc.h.

#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 252 of file stm32g0xx_ll_adc.h.

#define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

Definition at line 253 of file stm32g0xx_ll_adc.h.

#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 246 of file stm32g0xx_ll_adc.h.

#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

Definition at line 247 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__)
#define | IS_LL_ADC_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __ADC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 273 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDMonitChannels(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_SetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDThresholds().

#define IS_LL_ADC_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC)                                      \
  )

Definition at line 108 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_CLOCK_FREQ_MODE ( __CLOCK_FREQ_MODE__ )
Value:
(((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH)                      \
   || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW)                    \
  )

Definition at line 101 of file stm32g0xx_ll_adc.c.

#define IS_LL_ADC_COMMON_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                    \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
  )

Definition at line 86 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_DATA_ALIGN ( __DATA_ALIGN__ )
Value:
(((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                               \
   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
  )

Definition at line 122 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_LOW_POWER ( __LOW_POWER__ )
Value:
(((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                    \
   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
   || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF)                              \
   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF)                     \
  )

Definition at line 127 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_REG_CONTINUOUS_MODE ( __REG_CONTINUOUS_MODE__ )
Value:
(((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
  )

Definition at line 176 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_DMA_TRANSFER ( __REG_DMA_TRANSFER__ )
Value:
(((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                    \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
  )

Definition at line 181 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR ( __REG_OVR_DATA_BEHAVIOR__ )
Value:
(((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
  )

Definition at line 187 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_MODE ( __REG_SEQ_MODE__ )
Value:
(((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED)                                \
   || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE)                      \
  )

Definition at line 192 of file stm32g0xx_ll_adc.c.

#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE ( __REG_SEQ_DISCONT_MODE__ )
Value:
(((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)              \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
  )

Definition at line 208 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH ( __REG_SEQ_SCAN_LENGTH__ )
Value:
(((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
  )

Definition at line 197 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_TRIG_SOURCE ( __REG_TRIG_SOURCE__ )
Value:
(((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
  )

Definition at line 137 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                                 \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
  )

Definition at line 115 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_Init().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_ADC_CommonInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_CommonInitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...

#include <stm32g0xx_ll_adc.h>

Data Fields

uint32_t CommonClock

Detailed Description

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance).

Note:
The setting of these parameters by function LL_ADC_CommonInit() is conditioned to ADC instances state (all ADC instances sharing the same ADC common instance): All ADC instances sharing the same ADC common instance must be disabled.

Definition at line 297 of file stm32g0xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_CommonInitTypeDef::CommonClock

Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of ADC common - Clock source

This feature can be modified afterwards using unitary function LL_ADC_SetCommonClock().

Definition at line 299 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_adc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC instance. More...

#include <stm32g0xx_ll_adc.h>

Data Fields

uint32_t | Clock
uint32_t | Resolution
uint32_t | DataAlignment
uint32_t | LowPowerMode

Detailed Description

Structure definition of some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 324 of file stm32g0xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_InitTypeDef::Clock

Set ADC instance clock source and prescaler. This parameter can be a value of ADC instance - Clock source

Note:
On this STM32 series, this parameter has some clock ratio constraints: ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).

This feature can be modified afterwards using unitary function LL_ADC_SetClock(). For more details, refer to description of this function.

Definition at line 326 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::DataAlignment

Set ADC conversion data alignment. This parameter can be a value of ADC instance - Data alignment

This feature can be modified afterwards using unitary function LL_ADC_SetDataAlignment().

Definition at line 340 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::LowPowerMode

Set ADC low power mode. This parameter can be a value of ADC instance - Low power mode

This feature can be modified afterwards using unitary function LL_ADC_SetLowPowerMode().

Definition at line 345 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::Resolution

Set ADC resolution. This parameter can be a value of ADC instance - Resolution

This feature can be modified afterwards using unitary function LL_ADC_SetResolution().

Definition at line 335 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_adc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_ADC_REG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_REG_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group regular. More...

#include <stm32g0xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | ContinuousMode
uint32_t | DMATransfer
uint32_t | Overrun

Detailed Description

Structure definition of some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_REG_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 371 of file stm32g0xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_REG_InitTypeDef::ContinuousMode

Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of ADC group regular - Continuous mode Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

This feature can be modified afterwards using unitary function LL_ADC_REG_SetContinuousMode().

Definition at line 394 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::DMATransfer

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of ADC group regular - DMA transfer of ADC conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetDMATransfer().

Definition at line 400 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::Overrun

Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of ADC group regular - Overrun behavior on conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetOverrun().

Definition at line 405 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerDiscont

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group regular - Sequencer discontinuous mode

Note:
This parameter has an effect only if group regular sequencer is enabled (depending on the sequencer mode: scan length of 2 ranks or more, or several ADC channels enabled in group regular sequencer. Refer to function LL_ADC_REG_SetSequencerConfigurable() ).

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerDiscont().

Definition at line 387 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerLength

Set ADC group regular sequencer length.

Note:
This parameter has an effect only if group regular sequencer is set to mode "fully configurable". Refer to function LL_ADC_REG_SetSequencerConfigurable(). This parameter can be a value of ADC group regular - Sequencer scan length

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerLength().

Definition at line 381 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::TriggerSource

Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of ADC group regular - Trigger source

Note:
On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().

This feature can be modified afterwards using unitary function LL_ADC_REG_SetTriggerSource().

Definition at line 373 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_adc.h
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STM32G0C1xx HAL User Manual: ADC flags

Defines
ADC flags
ADC Exported Constants

Flags defines which can be used with LL_ADC_ReadReg function. More...

Defines

#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL

Detailed Description

Flags defines which can be used with LL_ADC_ReadReg function.

Define Documentation

#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY

ADC flag ADC instance ready

Definition at line 427 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_ADRDY(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_ADRDY().

#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC flag ADC analog watchdog 1

Definition at line 433 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD1(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD1().

#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC flag ADC analog watchdog 2

Definition at line 434 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD2(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD2().

#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC flag ADC analog watchdog 3

Definition at line 435 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD3(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD3().

#define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY

ADC flag ADC channel configuration ready

Definition at line 428 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_CCRDY(), LL_ADC_DeInit(), LL_ADC_DisableIT_CCRDY(), LL_ADC_EnableIT_CCRDY(), LL_ADC_IsActiveFlag_CCRDY(), and LL_ADC_IsEnabledIT_CCRDY().

#define LL_ADC_FLAG_EOC ADC_ISR_EOC

ADC flag ADC group regular end of unitary conversion

Definition at line 429 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOC(), and LL_ADC_DeInit().

#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL

ADC flag end of calibration

Definition at line 436 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOCAL(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOCAL().

#define LL_ADC_FLAG_EOS ADC_ISR_EOS

ADC flag ADC group regular end of sequence conversions

Definition at line 430 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOS().

#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC flag ADC group regular end of sampling phase

Definition at line 432 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOSMP(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOSMP().

#define LL_ADC_FLAG_OVR ADC_ISR_OVR

ADC flag ADC group regular overrun

Definition at line 431 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_OVR(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_OVR().

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STM32G0C1xx HAL User Manual: ADC interruptions for configuration (interruption enable or disable)

Defines
ADC interruptions for configuration (interruption enable or disable)
ADC Exported Constants

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions. More...

Defines

#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_CCRDY ADC_IER_CCRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE
#define | LL_ADC_IT_EOCAL ADC_IER_EOCALIE

Detailed Description

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

Define Documentation

#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE

ADC interruption ADC instance ready

Definition at line 445 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_ADRDY(), LL_ADC_EnableIT_ADRDY(), and LL_ADC_IsEnabledIT_ADRDY().

#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE

ADC interruption ADC analog watchdog 1

Definition at line 451 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD1(), LL_ADC_EnableIT_AWD1(), and LL_ADC_IsEnabledIT_AWD1().

#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE

ADC interruption ADC analog watchdog 2

Definition at line 452 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD2(), LL_ADC_EnableIT_AWD2(), and LL_ADC_IsEnabledIT_AWD2().

#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE

ADC interruption ADC analog watchdog 3

Definition at line 453 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD3(), LL_ADC_EnableIT_AWD3(), and LL_ADC_IsEnabledIT_AWD3().

#define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE

ADC interruption channel configuration ready

Definition at line 446 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_IT_EOC ADC_IER_EOCIE

ADC interruption ADC group regular end of unitary conversion

Definition at line 447 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOC(), LL_ADC_EnableIT_EOC(), and LL_ADC_IsEnabledIT_EOC().

#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE

ADC interruption ADC end of calibration

Definition at line 454 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOCAL(), LL_ADC_EnableIT_EOCAL(), and LL_ADC_IsEnabledIT_EOCAL().

#define LL_ADC_IT_EOS ADC_IER_EOSIE

ADC interruption ADC group regular end of sequence conversions

Definition at line 448 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOS(), LL_ADC_EnableIT_EOS(), and LL_ADC_IsEnabledIT_EOS().

#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC interruption ADC group regular end of sampling phase

Definition at line 450 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOSMP(), LL_ADC_EnableIT_EOSMP(), and LL_ADC_IsEnabledIT_EOSMP().

#define LL_ADC_IT_OVR ADC_IER_OVRIE

ADC interruption ADC group regular overrun

Definition at line 449 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_OVR(), LL_ADC_EnableIT_OVR(), and LL_ADC_IsEnabledIT_OVR().

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STM32G0C1xx HAL User Manual: ADC registers compliant with specific purpose

Defines
ADC registers compliant with specific purpose
ADC Exported Constants

Defines

#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Define Documentation

#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Definition at line 465 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

Define Documentation

#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)

ADC asynchronous clock without prescaler

Definition at line 473 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 478 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )

ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 479 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 483 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 480 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 474 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 484 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)

ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 481 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )

ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 475 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 476 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 482 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )

ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function LL_ADC_SetClock() ).

Definition at line 477 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC common - Clock frequency mode

Defines
ADC common - Clock frequency mode
ADC Exported Constants

Defines

#define | LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL)
#define | LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN)

Define Documentation

#define LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL)

ADC clock mode to high frequency. On STM32G0, ADC clock frequency above 3.5MHz.

Definition at line 492 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN)

ADC clock mode to low frequency. On STM32G0, ADC clock frequency below 3.5MHz.

Definition at line 493 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC common - Measurement path to internal channels

Defines
ADC common - Measurement path to internal channels
ADC Exported Constants

Defines

#define | LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

Define Documentation

#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)

ADC measurement paths all disabled

Definition at line 506 of file stm32g0xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)

ADC measurement path to internal channel temperature sensor

Definition at line 508 of file stm32g0xx_ll_adc.h.

Referenced by ADC_Enable(), and HAL_ADC_ConfigChannel().

#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

ADC measurement path to internal channel Vbat

Definition at line 509 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)

ADC measurement path to internal channel VrefInt

Definition at line 507 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel().

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STM32G0C1xx HAL User Manual: ADC instance - Clock source

Defines
ADC instance - Clock source
ADC Exported Constants

Defines

#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC (0x00000000UL)

Define Documentation

#define LL_ADC_CLOCK_ASYNC (0x00000000UL)

ADC asynchronous clock. Asynchronous clock prescaler can be configured using function LL_ADC_SetCommonClock().

Definition at line 520 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0)

ADC synchronous clock derived from AHB clock not divided

Definition at line 519 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0)

ADC synchronous clock derived from AHB clock divided by 2

Definition at line 518 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1)

ADC synchronous clock derived from AHB clock divided by 4

Definition at line 517 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | LL_ADC_RESOLUTION_12B (0x00000000UL)
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 )
#define | LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)

Define Documentation

#define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0)

ADC resolution 10 bits

Definition at line 529 of file stm32g0xx_ll_adc.h.

#define LL_ADC_RESOLUTION_12B (0x00000000UL)

ADC resolution 12 bits

Definition at line 528 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)

ADC resolution 6 bits

Definition at line 531 of file stm32g0xx_ll_adc.h.

#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 )

ADC resolution 8 bits

Definition at line 530 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC instance - Data alignment

Defines
ADC instance - Data alignment
ADC Exported Constants

Defines

#define | LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN)

Define Documentation

#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN)

ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)

Definition at line 540 of file stm32g0xx_ll_adc.h.

#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 539 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

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STM32G0C1xx HAL User Manual: ADC instance - Low power mode

Defines
ADC instance - Low power mode
ADC Exported Constants

Defines

#define | LL_ADC_LP_MODE_NONE (0x00000000UL)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT)
#define | LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF)
#define | LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)

Define Documentation

#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF)

ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function LL_ADC_SetLowPowerMode().

Definition at line 550 of file stm32g0xx_ll_adc.h.

#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT)

ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function LL_ADC_SetLowPowerMode().

Definition at line 549 of file stm32g0xx_ll_adc.h.

#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)

ADC low power modes auto wait and auto power-off combined. See description with function LL_ADC_SetLowPowerMode().

Definition at line 551 of file stm32g0xx_ll_adc.h.

#define LL_ADC_LP_MODE_NONE (0x00000000UL)

No ADC low power mode activated

Definition at line 548 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

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STM32G0C1xx HAL User Manual: ADC group regular - Trigger frequency mode

Defines
ADC group regular - Trigger frequency mode
ADC Exported Constants

Defines

#define | LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL)
#define | LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG)

Define Documentation

#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL)

ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle".

Definition at line 559 of file stm32g0xx_ll_adc.h.

#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG)

ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle".

Definition at line 560 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC instance - Sampling time common to a group of channels

Defines
ADC instance - Sampling time common to a group of channels
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS)
#define | LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK)

Define Documentation

#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS)

Set sampling time common to a group of channels: sampling time nb 1

Definition at line 568 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_Init(), and LL_ADC_GetChannelSamplingTime().

#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK)

Set sampling time common to a group of channels: sampling time nb 2

Definition at line 569 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_Init(), and LL_ADC_GetChannelSamplingTime().

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STM32G0C1xx HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Exported Constants

Defines

#define LL_ADC_GROUP_REGULAR (0x00000001UL)

Define Documentation

#define LL_ADC_GROUP_REGULAR (0x00000001UL)

ADC group regular (available on all STM32 devices)

Definition at line 577 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

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STM32G0C1xx HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD )
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD )
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD )
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD )
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD )
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD )
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD )
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD )
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD )
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD )
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD)
#define | LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)

Define Documentation

#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 585 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 586 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 595 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 596 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 597 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 598 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 599 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 600 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 601 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 602 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN18

Definition at line 603 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 587 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 588 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 589 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 590 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 591 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 592 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 593 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 594 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerChannels().

#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Temperature sensor.

Definition at line 605 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda.

Definition at line 606 of file stm32g0xx_ll_adc.h.

#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to VrefInt: Internal voltage reference.

Definition at line 604 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC group regular - Trigger source

Defines
ADC group regular - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting).

Definition at line 630 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 628 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 616 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 615 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 618 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 620 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 622 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 625 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)

ADC group regular conversion trigger internal: SW start.

Definition at line 614 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_REG_IsTriggerSourceSWStart(), and LL_ADC_REG_StructInit().

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STM32G0C1xx HAL User Manual: ADC group regular - Trigger edge

Defines
ADC group regular - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 )
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 )

ADC group regular conversion trigger polarity set to falling edge

Definition at line 639 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 638 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 640 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC group regular - Continuous mode

Defines
ADC group regular - Continuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_CONV_SINGLE (0x00000000UL)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT)

Define Documentation

#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT)

ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically

Definition at line 649 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_CONV_SINGLE (0x00000000UL)

ADC conversions are performed in single mode: one conversion per trigger

Definition at line 648 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

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STM32G0C1xx HAL User Manual: ADC group regular - DMA transfer of ADC conversion data

Defines
ADC group regular - DMA transfer of ADC conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)

Define Documentation

#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN)

ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.

Definition at line 658 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)

ADC conversions are not transferred by DMA

Definition at line 657 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)

ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Definition at line 659 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD)

Define Documentation

#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 668 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)

ADC group regular behavior in case of overrun: data preserved

Definition at line 667 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC group regular - Sequencer configuration flexibility

Defines
ADC group regular - Sequencer configuration flexibility
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_FIXED (0x00000000UL)
#define | LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD)

Define Documentation

#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD)

Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().

Definition at line 677 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_FIXED (0x00000000UL)

Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function LL_ADC_REG_SetSequencerChannels().

Definition at line 676 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

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STM32G0C1xx HAL User Manual: ADC group regular - Sequencer scan length

Defines
ADC group regular - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL)

Define Documentation

#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2)

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 685 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3)

ADC group regular sequencer enable with 2 ranks in the sequence

Definition at line 686 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4)

ADC group regular sequencer enable with 3 ranks in the sequence

Definition at line 687 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5)

ADC group regular sequencer enable with 4 ranks in the sequence

Definition at line 688 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6)

ADC group regular sequencer enable with 5 ranks in the sequence

Definition at line 689 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7)

ADC group regular sequencer enable with 6 ranks in the sequence

Definition at line 690 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8)

ADC group regular sequencer enable with 7 ranks in the sequence

Definition at line 691 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL)

ADC group regular sequencer enable with 8 ranks in the sequence

Definition at line 692 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerLength().

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STM32G0C1xx HAL User Manual: ADC group regular - Sequencer scan direction

Defines
ADC group regular - Sequencer scan direction
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR)

Define Documentation

#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR)

On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer)

Definition at line 701 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL)

On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward.

Definition at line 700 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: ADC group regular - Sequencer discontinuous mode

Defines
ADC group regular - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN)

Define Documentation

#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 710 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group regular sequencer discontinuous mode disable

Definition at line 709 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

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STM32G0C1xx HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS)

Define Documentation

#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 1

Definition at line 718 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 2

Definition at line 719 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 3

Definition at line 720 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 4

Definition at line 721 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 5

Definition at line 722 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 6

Definition at line 723 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 7

Definition at line 724 of file stm32g0xx_ll_adc.h.

#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 8

Definition at line 725 of file stm32g0xx_ll_adc.h.

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STM32G0C1xx HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0)
#define | LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1)
#define | LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0)
#define | LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2)
#define | LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0)
#define | LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1)
#define | LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0)

Define Documentation

#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0)

Sampling time 12.5 ADC clock cycles

Definition at line 736 of file stm32g0xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0)

Sampling time 160.5 ADC clock cycles

Definition at line 740 of file stm32g0xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2)

Sampling time 19.5 ADC clock cycles

Definition at line 737 of file stm32g0xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)

Sampling time 1.5 ADC clock cycle

Definition at line 733 of file stm32g0xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0)

Sampling time 39.5 ADC clock cycles

Definition at line 738 of file stm32g0xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0)

Sampling time 3.5 ADC clock cycles

Definition at line 734 of file stm32g0xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1)

Sampling time 79.5 ADC clock cycles

Definition at line 739 of file stm32g0xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1)

Sampling time 7.5 ADC clock cycles

Definition at line 735 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define | LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)

Define Documentation

#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)

ADC analog watchdog number 1

Definition at line 748 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)

ADC analog watchdog number 2

Definition at line 749 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)

ADC analog watchdog number 3

Definition at line 750 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Analog watchdog - Monitored channels

Defines
Analog watchdog - Monitored channels
ADC Exported Constants

Defines

#define | LL_ADC_AWD_DISABLE (0x00000000UL)
#define | LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR1_AWD1EN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

Define Documentation

#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR1_AWD1EN )

ADC analog watchdog monitoring of all channels, converted by group regular only

Definition at line 759 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only

Definition at line 780 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only

Definition at line 781 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only

Definition at line 779 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only

Definition at line 760 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only

Definition at line 770 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only

Definition at line 771 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only

Definition at line 772 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only

Definition at line 773 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only

Definition at line 774 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only

Definition at line 775 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only

Definition at line 776 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only

Definition at line 777 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only

Definition at line 778 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only

Definition at line 761 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only

Definition at line 762 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only

Definition at line 763 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only

Definition at line 764 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only

Definition at line 765 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only

Definition at line 766 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only

Definition at line 767 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only

Definition at line 768 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only

Definition at line 769 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_DISABLE (0x00000000UL)

ADC analog watchdog monitoring disabled

Definition at line 758 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Analog watchdog - Thresholds

Defines
Analog watchdog - Thresholds
ADC Exported Constants

Defines

#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 )
#define | LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1)
#define | LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1)

Define Documentation

#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 )

ADC analog watchdog threshold high

Definition at line 789 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1)

ADC analog watchdog threshold low

Definition at line 790 of file stm32g0xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1)

ADC analog watchdog both thresholds high and low concatenated into the same data

Definition at line 791 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Oversampling - Oversampling scope

Defines
Oversampling - Oversampling scope
ADC Exported Constants

Defines

#define | LL_ADC_OVS_DISABLE (0x00000000UL)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE)

Define Documentation

#define LL_ADC_OVS_DISABLE (0x00000000UL)

ADC oversampling disabled.

Definition at line 799 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE)

ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available.

Definition at line 800 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_OVS_REG_CONT (0x00000000UL)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS)

Define Documentation

#define LL_ADC_OVS_REG_CONT (0x00000000UL)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger)

Definition at line 808 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger)

Definition at line 809 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Oversampling - Ratio

Defines
Oversampling - Ratio
ADC Exported Constants

Defines

#define | LL_ADC_OVS_RATIO_2 (0x00000000UL)
#define | LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )
#define | LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

Define Documentation

#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )

ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 823 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 820 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_2 (0x00000000UL)

ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 817 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 824 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )

ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 821 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 818 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 822 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )

ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 819 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Oversampling - Data shift

Defines
Oversampling - Data shift
ADC Exported Constants

Defines

#define | LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define | LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )

Define Documentation

#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL)

ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data)

Definition at line 832 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)

ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data)

Definition at line 833 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data)

Definition at line 834 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data)

Definition at line 835 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )

ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data)

Definition at line 836 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data)

Definition at line 837 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data)

Definition at line 838 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data)

Definition at line 839 of file stm32g0xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )

ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data)

Definition at line 840 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Definitions of constants used by helper macro

Defines
Definitions of constants used by helper macro
ADC Exported Constants

Defines

#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */

Define Documentation

#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */

Definition at line 848 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Definitions of ADC hardware constraints delays

Defines
Definitions of ADC hardware constraints delays
ADC Exported Constants

Defines

#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)
#define | LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)
#define | LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL)

Detailed Description

Note:
Only ADC peripheral HW delays are defined in ADC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL)

Delay required between ADC end of calibration and ADC enable

Definition at line 905 of file stm32g0xx_ll_adc.h.

#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)

Delay for ADC stabilization time (ADC voltage regulator start-up time)

Definition at line 883 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_Init().

#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)

Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to LL_ADC_Enable())

Definition at line 896 of file stm32g0xx_ll_adc.h.

Referenced by ADC_Enable().

#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)

Delay for temperature sensor stabilization time (starting from temperature sensor enable, refer to LL_ADC_SetCommonPathInternalCh())

Definition at line 895 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)

Delay for internal voltage reference stabilization time

Definition at line 889 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
ADC Exported Macros

Defines

#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.

Define Documentation

#define LL_ADC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 940 of file stm32g0xx_ll_adc.h.

#define LL_ADC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 932 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC helper macro

Defines
ADC helper macro
ADC Exported Macros

Defines

#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC1_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) LL_ADC_IsEnabled(ADC1)
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __LL_ADC_ANALOGWD_CHANNEL_GROUP | ( | __CHANNEL__,
 |  | __GROUP__
 | ) | (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)

Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.

Note:
To be used with function LL_ADC_SetAnalogWDMonitChannels(). Example: LL_ADC_SetAnalogWDMonitChannels( ADC1, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (2)
  • LL_ADC_CHANNEL_TEMPSENSOR (2)
  • LL_ADC_CHANNEL_VBAT (2)
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
(2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
__GROUP__ This parameter can be one of the following values:
  • LL_ADC_GROUP_REGULAR
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_18_REG
  • LL_ADC_AWD_CH_VREFINT_REG
  • LL_ADC_AWD_CH_TEMPSENSOR_REG
  • LL_ADC_AWD_CH_VBAT_REG

Definition at line 1263 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD_12_BITS__
 | ) | ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))

Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to get the value of analog watchdog threshold high (on 8 bits): < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B, LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1308 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD__
 | ) | ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))

Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_ConfigAnalogWDThresholds() or LL_ADC_SetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to set the value of analog watchdog threshold high (on 8 bits): LL_ADC_SetAnalogWDThresholds (< ADCx param >, __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1286 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW | ( | __AWD_THRESHOLD_TYPE__,
 |  | __AWD_THRESHOLDS__
 | ) | (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)

Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, to get analog watchdog threshold high from the register raw value: __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
Parameters:
__AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
__AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1323 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
)

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 1417 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ?        \
  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
                                                    (__ADC_RESOLUTION__),          \
                                                    LL_ADC_RESOLUTION_12B)         \
                   * (__VREFANALOG_VOLTAGE__))                                     \
                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
   ) + TEMPSENSOR_CAL1_TEMP                                                        \
  )                                                                                \
  :                                                                                \
  ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR)                                         \
)

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 series, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius) In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)

Definition at line 1503 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
               / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
              * 1000UL)                                                     \
    -                                                                       \
    (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
              * 1000UL)                                                     \
   )                                                                        \
  ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
)

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12 bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32G0, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1565 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
                                    (__ADC_RESOLUTION__),                    \
                                    LL_ADC_RESOLUTION_12B)                   \
)

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 series, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Analog reference voltage (unit: mV)

Definition at line 1449 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18

Definition at line 1167 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ )
Value:
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                                            \
   (                                                                                                    \
       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS              \
   )                                                                                                    \
   :                                                                                                    \
   ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) :                      \
    ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) :                     \
     ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) :                    \
      ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) :                   \
       ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) :                  \
        ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) :                 \
         ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) :                \
          ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) :               \
           ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) :              \
            ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) :             \
             ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) :         \
              ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) :        \
               ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) :       \
                ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) :      \
                 ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) :     \
                  ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) :    \
                   ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) :   \
                    ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) :  \
                     ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) : \
                      (0UL)))))))))))))))))))))

Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.

Note:
Example: __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 987 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and LL_ADC_GetAnalogWDMonitChannels().

#define __LL_ADC_COMMON_INSTANCE ( __ADCx__ ) (ADC1_COMMON)

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 1336 of file stm32g0xx_ll_adc.h.

Referenced by ADC_Enable(), and HAL_ADC_ConfigChannel().

#define __LL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
(((__DATA__)                                                                 \
  << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))  \
 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))     \
)

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data to the requested resolution

Definition at line 1393 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) |                 \
   (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))

Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.

Note:
Example: __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "LL_ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (2)
  • LL_ADC_CHANNEL_TEMPSENSOR (2)
  • LL_ADC_CHANNEL_VBAT (2)
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
(2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1052 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)

Definition at line 1372 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1103 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                             \
   ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                             \
   ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT))

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1191 of file stm32g0xx_ll_adc.h.

#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) LL_ADC_IsEnabled(ADC1)

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 1356 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_CommonInit().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC DMA management

Functions
ADC DMA management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Note:
These ADC registers are data registers: when ADC conversion data is available in ADC data registers, ADC generates a DMA transfer request.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
For devices with several ADC: in multimode, some devices use a different data register outside of ADC instance scope (common data register). This macro manages this register difference, only ADC instance has to be set as parameter.
Reference Manual to LL API cross reference:
DR DATA LL_ADC_DMA_GetRegAddr
Parameters:
ADCx ADC instance
Register This parameter can be one of the following values:
  • LL_ADC_DMA_REG_REGULAR_DATA
Return values:
ADC register address

Definition at line 1628 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of ADC hierarchical scope: common to several ADC instances

Functions
Configuration of ADC hierarchical scope: common to several ADC instances
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonFrequencyMode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonFrequencyMode)
Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonFrequencyMode (ADC_Common_TypeDef *ADCxy_COMMON)
Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalChAdd (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalChRem (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCommonClock ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: Clock source and prescaler.

Reference Manual to LL API cross reference:
CCR PRESC LL_ADC_GetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_CLOCK_ASYNC_DIV1 (1)
  • LL_ADC_CLOCK_ASYNC_DIV2 (1)
  • LL_ADC_CLOCK_ASYNC_DIV4 (1)
  • LL_ADC_CLOCK_ASYNC_DIV6 (1)
  • LL_ADC_CLOCK_ASYNC_DIV8 (1)
  • LL_ADC_CLOCK_ASYNC_DIV10 (1)
  • LL_ADC_CLOCK_ASYNC_DIV12 (1)
  • LL_ADC_CLOCK_ASYNC_DIV16 (1)
  • LL_ADC_CLOCK_ASYNC_DIV32 (1)
  • LL_ADC_CLOCK_ASYNC_DIV64 (1)
  • LL_ADC_CLOCK_ASYNC_DIV128 (1)
  • LL_ADC_CLOCK_ASYNC_DIV256 (1)
(1) ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous. (refer to function LL_ADC_SetClock() ).

Definition at line 1705 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode ( ADC_Common_TypeDef * ADCxy_COMMON )

Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0).

Function kept for legacy purpose.

Reference Manual to LL API cross reference:
CCR LFMEN LL_ADC_GetCommonFrequencyMode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_CLOCK_FREQ_MODE_HIGH
  • LL_ADC_CLOCK_FREQ_MODE_LOW

Definition at line 1742 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_GetCommonPathInternalCh
CCR TSEN LL_ADC_GetCommonPathInternalCh
CCR VBATEN LL_ADC_GetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT

Definition at line 1879 of file stm32g0xx_ll_adc.h.

Referenced by ADC_Enable(), and HAL_ADC_ConfigChannel().

__STATIC_INLINE void LL_ADC_SetCommonClock | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | CommonClock
 | ) |  |

Set parameter common to several ADC: Clock source and prescaler.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR PRESC LL_ADC_SetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
CommonClock This parameter can be one of the following values:
  • LL_ADC_CLOCK_ASYNC_DIV1 (1)
  • LL_ADC_CLOCK_ASYNC_DIV2 (1)
  • LL_ADC_CLOCK_ASYNC_DIV4 (1)
  • LL_ADC_CLOCK_ASYNC_DIV6 (1)
  • LL_ADC_CLOCK_ASYNC_DIV8 (1)
  • LL_ADC_CLOCK_ASYNC_DIV10 (1)
  • LL_ADC_CLOCK_ASYNC_DIV12 (1)
  • LL_ADC_CLOCK_ASYNC_DIV16 (1)
  • LL_ADC_CLOCK_ASYNC_DIV32 (1)
  • LL_ADC_CLOCK_ASYNC_DIV64 (1)
  • LL_ADC_CLOCK_ASYNC_DIV128 (1)
  • LL_ADC_CLOCK_ASYNC_DIV256 (1)
(1) ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous. (refer to function LL_ADC_SetClock() ).
Return values:
None

Definition at line 1676 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_CommonInit().

__STATIC_INLINE void LL_ADC_SetCommonFrequencyMode | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | CommonFrequencyMode
 | ) |  |

Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0).

Function kept for legacy purpose.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CCR LFMEN LL_ADC_SetCommonFrequencyMode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
CommonFrequencyMode This parameter can be one of the following values:
  • LL_ADC_CLOCK_FREQ_MODE_HIGH
  • LL_ADC_CLOCK_FREQ_MODE_LOW
Return values:
None

Definition at line 1726 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Configure all paths (overwrite current configuration).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR) The values not selected are removed from configuration.
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_VREFINT_STAB_US. Refer to literals LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
On this STM32 series, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalCh
CCR TSEN LL_ADC_SetCommonPathInternalCh
CCR VBATEN LL_ADC_SetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 1785 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel().

__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Add paths to the current configuration.

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_VREFINT_STAB_US. Refer to literals LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
On this STM32 series, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalChAdd
CCR TSEN LL_ADC_SetCommonPathInternalChAdd
CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 1827 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Remove paths to the current configuration.

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
On this STM32 series, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalChRem
CCR TSEN LL_ADC_SetCommonPathInternalChRem
CCR VBATEN LL_ADC_SetCommonPathInternalChRem
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 1857 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of ADC hierarchical scope: ADC instance

Functions
Configuration of ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetClock (ADC_TypeDef *ADCx, uint32_t ClockSource)
Set ADC instance clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetClock (ADC_TypeDef *ADCx)
Get ADC instance clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationFactor (ADC_TypeDef *ADCx)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetTriggerFrequencyMode (ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
Set ADC trigger frequency mode.
__STATIC_INLINE uint32_t | LL_ADC_GetTriggerFrequencyMode (ADC_TypeDef *ADCx)
Get ADC trigger frequency mode.
__STATIC_INLINE void | LL_ADC_SetSamplingTimeCommonChannels (ADC_TypeDef *ADCx, uint32_t SamplingTimeY, uint32_t SamplingTime)
Set sampling time common to a group of channels.
__STATIC_INLINE uint32_t | LL_ADC_GetSamplingTimeCommonChannels (ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
Get sampling time common to a group of channels.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor ( ADC_TypeDef * ADCx )

Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
Calibration factors are set by hardware after performing a calibration run using function LL_ADC_StartCalibration().
Reference Manual to LL API cross reference:
CALFACT CALFACT LL_ADC_GetCalibrationFactor
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7F

Definition at line 1975 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_Start().

__STATIC_INLINE uint32_t LL_ADC_GetClock ( ADC_TypeDef * ADCx )

Get ADC instance clock source and prescaler.

Reference Manual to LL API cross reference:
CFGR2 CKMODE LL_ADC_GetClock
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
  • LL_ADC_CLOCK_ASYNC (1)
(1) Asynchronous clock prescaler can be retrieved using function LL_ADC_GetCommonClock().
(2) Caution: This parameter has some clock ratio constraints: This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual.

Definition at line 1939 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment ( ADC_TypeDef * ADCx )

Get ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
Reference Manual to LL API cross reference:
CFGR1 ALIGN LL_ADC_GetDataAlignment
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT

Definition at line 2047 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode ( ADC_TypeDef * ADCx )

Get ADC low power mode:

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • It is not recommended to use with interruption or DMA since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
  • ADC low power mode "auto power-off" (feature available on this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): the ADC automatically powers-off after a conversion and automatically wakes up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with low power mode "auto wait".
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
Reference Manual to LL API cross reference:
CFGR1 WAIT LL_ADC_GetLowPowerMode
CFGR1 AUTOFF LL_ADC_GetLowPowerMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT
  • LL_ADC_LP_AUTOPOWEROFF
  • LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF

Definition at line 2157 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetResolution ( ADC_TypeDef * ADCx )

Get ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Reference Manual to LL API cross reference:
CFGR1 RES LL_ADC_GetResolution
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B

Definition at line 2013 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SamplingTimeY
 | ) |  |

Get sampling time common to a group of channels.

Note:
Unit: ADC clock cycles.
On this STM32 series, sampling time scope is on ADC instance: Sampling time common to all channels. (on some other STM32 families, sampling time is channel wise)
Conversion time is the addition of sampling time and processing time. Refer to reference manual for ADC processing time of this STM32 series.
Reference Manual to LL API cross reference:
SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels
Reference Manual to LL API cross reference:
SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
Parameters:
ADCx ADC instance
SamplingTimeY This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_COMMON_1
  • LL_ADC_SAMPLINGTIME_COMMON_2
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_1CYCLE_5
  • LL_ADC_SAMPLINGTIME_3CYCLES_5
  • LL_ADC_SAMPLINGTIME_7CYCLES_5
  • LL_ADC_SAMPLINGTIME_12CYCLES_5
  • LL_ADC_SAMPLINGTIME_19CYCLES_5
  • LL_ADC_SAMPLINGTIME_39CYCLES_5
  • LL_ADC_SAMPLINGTIME_79CYCLES_5
  • LL_ADC_SAMPLINGTIME_160CYCLES_5

Definition at line 2282 of file stm32g0xx_ll_adc.h.

References ADC_SAMPLING_TIME_SMP_SHIFT_MASK.

Referenced by HAL_ADC_Init().

__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode ( ADC_TypeDef * ADCx )

Get ADC trigger frequency mode.

Reference Manual to LL API cross reference:
CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_TRIGGER_FREQ_HIGH
  • LL_ADC_TRIGGER_FREQ_LOW

Definition at line 2200 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCalibrationFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
This function is intended to set calibration parameters without having to perform a new calibration using LL_ADC_StartCalibration().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled, without calibration on going, without conversion on going on group regular.
Reference Manual to LL API cross reference:
CALFACT CALFACT LL_ADC_SetCalibrationFactor
Parameters:
ADCx | ADC instance
CalibrationFactor | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
None

Definition at line 1959 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_Start().

__STATIC_INLINE void LL_ADC_SetClock | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ClockSource
 | ) |  |

Set ADC instance clock source and prescaler.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR2 CKMODE LL_ADC_SetClock
Parameters:
ADCx ADC instance
ClockSource This parameter can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
  • LL_ADC_CLOCK_ASYNC (1)
(1) Asynchronous clock prescaler can be configured using function LL_ADC_SetCommonClock().
(2) Caution: This parameter has some clock ratio constraints: This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual.
Return values:
None

Definition at line 1915 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetDataAlignment | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DataAlignment
 | ) |  |

Set ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 ALIGN LL_ADC_SetDataAlignment
Parameters:
ADCx ADC instance
DataAlignment This parameter can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT
Return values:
None

Definition at line 2032 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetLowPowerMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | LowPowerMode
 | ) |  |

Set ADC low power mode.

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • It is not recommended to use with interruption or DMA since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
  • ADC low power mode "auto power-off" (feature available on this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): the ADC automatically powers-off after a conversion and automatically wakes up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with low power mode "auto wait".
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 WAIT LL_ADC_SetLowPowerMode
CFGR1 AUTOFF LL_ADC_SetLowPowerMode
Parameters:
ADCx ADC instance
LowPowerMode This parameter can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT
  • LL_ADC_LP_AUTOPOWEROFF
  • LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
Return values:
None

Definition at line 2104 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetResolution | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Resolution
 | ) |  |

Set ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 RES LL_ADC_SetResolution
Parameters:
ADCx ADC instance
Resolution This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
None

Definition at line 1996 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SamplingTimeY,
 |  | uint32_t | SamplingTime
 | ) |  |

Set sampling time common to a group of channels.

Note:
Unit: ADC clock cycles.
On this STM32 series, sampling time scope is on ADC instance: Sampling time common to all channels. (on some other STM32 families, sampling time is channel wise)
In case of internal channel (VrefInt, TempSensor, ...) to be converted: sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values (parameters TS_vrefint, TS_temp, ...).
Conversion time is the addition of sampling time and processing time. On this STM32 series, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
In case of ADC conversion of internal channel (VrefInt, temperature sensor, ...), a sampling time minimum value is required. Refer to device datasheet.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels
Reference Manual to LL API cross reference:
SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
Parameters:
ADCx ADC instance
SamplingTimeY This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_COMMON_1
  • LL_ADC_SAMPLINGTIME_COMMON_2
SamplingTime This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_1CYCLE_5
  • LL_ADC_SAMPLINGTIME_3CYCLES_5
  • LL_ADC_SAMPLINGTIME_7CYCLES_5
  • LL_ADC_SAMPLINGTIME_12CYCLES_5
  • LL_ADC_SAMPLINGTIME_19CYCLES_5
  • LL_ADC_SAMPLINGTIME_39CYCLES_5
  • LL_ADC_SAMPLINGTIME_79CYCLES_5
  • LL_ADC_SAMPLINGTIME_160CYCLES_5
Return values:
None

Definition at line 2249 of file stm32g0xx_ll_adc.h.

References ADC_SAMPLING_TIME_SMP_SHIFT_MASK.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerFrequencyMode
 | ) |  |

Set ADC trigger frequency mode.

Note:
ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle".
When ADC trigger frequency mode is set to low frequency, some rearm cycles are inserted before performing ADC conversion start, inducing a delay of 2 ADC clock cycles.
Usage of ADC trigger frequency mode with ADC low power mode:
  • Low power mode auto wait: Only the first ADC conversion start trigger inserts the rearm delay.
  • Low power mode auto power-off: ADC trigger frequency mode is discarded.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
Parameters:
ADCx ADC instance
TriggerFrequencyMode This parameter can be one of the following values:
  • LL_ADC_TRIGGER_FREQ_HIGH
  • LL_ADC_TRIGGER_FREQ_LOW
Return values:
None

Definition at line 2187 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of ADC hierarchical scope: group regular

Functions
Configuration of ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerConfigurable (ADC_TypeDef *ADCx, uint32_t Configurability)
Set ADC group regular sequencer configuration flexibility.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerConfigurable (ADC_TypeDef *ADCx)
Get ADC group regular sequencer configuration flexibility.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerScanDirection (ADC_TypeDef *ADCx, uint32_t ScanDirection)
Set ADC group regular sequencer scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerScanDirection (ADC_TypeDef *ADCx)
Get ADC group regular sequencer scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerChannels (ADC_TypeDef *ADCx, uint32_t Channel)
Set ADC group regular sequence: channel on rank corresponding to channel number.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerChAdd (ADC_TypeDef *ADCx, uint32_t Channel)
Add channel to ADC group regular sequence: channel on rank corresponding to channel number.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerChRem (ADC_TypeDef *ADCx, uint32_t Channel)
Remove channel to ADC group regular sequence: channel on rank corresponding to channel number.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerChannels (ADC_TypeDef *ADCx)
Get ADC group regular sequence: channel on rank corresponding to channel number.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode ( ADC_TypeDef * ADCx )

Get ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
Reference Manual to LL API cross reference:
CFGR1 CONT LL_ADC_REG_GetContinuousMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS

Definition at line 3303 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CFGR1 DMAEN LL_ADC_REG_GetDMATransfer
CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Definition at line 3373 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler().

__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun ( ADC_TypeDef * ADCx )

Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Reference Manual to LL API cross reference:
CFGR1 OVRMOD LL_ADC_REG_GetOverrun
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN

Definition at line 3411 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels ( ADC_TypeDef * ADCx )

Get ADC group regular sequence: channel on rank corresponding to channel number.

Note:
This function performs:
  • Channels order reading into each rank of scan sequence: rank of each channel is fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available, they can be chosen using function LL_ADC_REG_SetSequencerConfigurable(). This function can be used with setting "not fully configurable". Refer to description of functions LL_ADC_REG_SetSequencerConfigurable() and LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 series, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
One or several values can be retrieved. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels
CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
Parameters:
ADCx ADC instance
Return values:
Returned value can be a combination of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().

Definition at line 3240 of file stm32g0xx_ll_adc.h.

References ADC_CHSELR_CHSEL0_BITOFFSET_POS, ADC_CHSELR_CHSEL10_BITOFFSET_POS, ADC_CHSELR_CHSEL11_BITOFFSET_POS, ADC_CHSELR_CHSEL12_BITOFFSET_POS, ADC_CHSELR_CHSEL13_BITOFFSET_POS, ADC_CHSELR_CHSEL14_BITOFFSET_POS, ADC_CHSELR_CHSEL15_BITOFFSET_POS, ADC_CHSELR_CHSEL16_BITOFFSET_POS, ADC_CHSELR_CHSEL17_BITOFFSET_POS, ADC_CHSELR_CHSEL18_BITOFFSET_POS, ADC_CHSELR_CHSEL1_BITOFFSET_POS, ADC_CHSELR_CHSEL2_BITOFFSET_POS, ADC_CHSELR_CHSEL3_BITOFFSET_POS, ADC_CHSELR_CHSEL4_BITOFFSET_POS, ADC_CHSELR_CHSEL5_BITOFFSET_POS, ADC_CHSELR_CHSEL6_BITOFFSET_POS, ADC_CHSELR_CHSEL7_BITOFFSET_POS, ADC_CHSELR_CHSEL8_BITOFFSET_POS, ADC_CHSELR_CHSEL9_BITOFFSET_POS, LL_ADC_CHANNEL_0, LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_10, LL_ADC_CHANNEL_11, LL_ADC_CHANNEL_12, LL_ADC_CHANNEL_13, LL_ADC_CHANNEL_14, LL_ADC_CHANNEL_15, LL_ADC_CHANNEL_16, LL_ADC_CHANNEL_17, LL_ADC_CHANNEL_18, LL_ADC_CHANNEL_2, LL_ADC_CHANNEL_3, LL_ADC_CHANNEL_4, LL_ADC_CHANNEL_5, LL_ADC_CHANNEL_6, LL_ADC_CHANNEL_7, LL_ADC_CHANNEL_8, and LL_ADC_CHANNEL_9.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer configuration flexibility.

Note:
On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available:
  • sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
  • sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function LL_ADC_REG_SetSequencerChannels().
Reference Manual to LL API cross reference:
CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_FIXED
  • LL_ADC_REG_SEQ_CONFIGURABLE

Definition at line 2487 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK

Definition at line 2721 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()". To set scan direction differently, refer to function LL_ADC_REG_SetSequencerScanDirection().
On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available, they can be chosen using function LL_ADC_REG_SetSequencerConfigurable().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
CHSELR SQ1 LL_ADC_REG_GetSequencerLength
CHSELR SQ2 LL_ADC_REG_GetSequencerLength
CHSELR SQ3 LL_ADC_REG_GetSequencerLength
CHSELR SQ4 LL_ADC_REG_GetSequencerLength
CHSELR SQ5 LL_ADC_REG_GetSequencerLength
CHSELR SQ6 LL_ADC_REG_GetSequencerLength
CHSELR SQ7 LL_ADC_REG_GetSequencerLength
CHSELR SQ8 LL_ADC_REG_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

Definition at line 2618 of file stm32g0xx_ll_adc.h.

References LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:
On this STM32 series, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
CHSELR SQ1 LL_ADC_REG_GetSequencerRanks
CHSELR SQ2 LL_ADC_REG_GetSequencerRanks
CHSELR SQ3 LL_ADC_REG_GetSequencerRanks
CHSELR SQ4 LL_ADC_REG_GetSequencerRanks
CHSELR SQ5 LL_ADC_REG_GetSequencerRanks
CHSELR SQ6 LL_ADC_REG_GetSequencerRanks
CHSELR SQ7 LL_ADC_REG_GetSequencerRanks
CHSELR SQ8 LL_ADC_REG_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (2)
  • LL_ADC_CHANNEL_TEMPSENSOR (2)
  • LL_ADC_CHANNEL_VBAT (2)
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
(2) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 2881 of file stm32g0xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, and ADC_REG_RANK_ID_SQRX_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer scan direction.

Note:
On this STM32 series, parameter relevant only is sequencer is set to mode not fully configurable, refer to function LL_ADC_REG_SetSequencerConfigurable().
On some other STM32 families, this setting is not available and the default scan direction is forward.
Reference Manual to LL API cross reference:
CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
  • LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD

Definition at line 2685 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
Reference Manual to LL API cross reference:
CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING

Definition at line 2424 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") use function LL_ADC_REG_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource
CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH4
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO (1)
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11
(1) On STM32G0, parameter not available on all devices

Definition at line 2363 of file stm32g0xx_ll_adc.h.

References ADC_REG_TRIG_EDGE_MASK, ADC_REG_TRIG_EXTEN_BITOFFSET_POS, and ADC_REG_TRIG_SOURCE_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source internal (SW start) or external.

Note:
In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTriggerSource().
Reference Manual to LL API cross reference:
CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 2390 of file stm32g0xx_ll_adc.h.

References LL_ADC_REG_TRIG_SOFTWARE.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

__STATIC_INLINE void LL_ADC_REG_SetContinuousMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Continuous
 | ) |  |

Set ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 CONT LL_ADC_REG_SetContinuousMode
Parameters:
ADCx ADC instance
Continuous This parameter can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS
Return values:
None

Definition at line 3286 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetDMATransfer | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DMATransfer
 | ) |  |

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 DMAEN LL_ADC_REG_SetDMATransfer
CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
Parameters:
ADCx ADC instance
DMATransfer This parameter can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED
Return values:
None

Definition at line 3340 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetOverrun | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Overrun
 | ) |  |

Set ADC group regular behavior in case of overrun: data preserved or overwritten.

Note:
Compatibility with devices without feature overrun: other devices without this feature have a behavior equivalent to data overwritten. The default setting of overrun is data preserved. Therefore, for compatibility with all devices, parameter overrun should be set to data overwritten.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 OVRMOD LL_ADC_REG_SetOverrun
Parameters:
ADCx ADC instance
Overrun This parameter can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN
Return values:
None

Definition at line 3397 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Add channel to ADC group regular sequence: channel on rank corresponding to channel number.

Note:
This function performs:
  • Channels ordering into each rank of scan sequence: rank of each channel is fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
  • Set channels selected by adding them to the current sequencer configuration.
On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available, they can be chosen using function LL_ADC_REG_SetSequencerConfigurable(). This function can be used with setting "not fully configurable". Refer to description of functions LL_ADC_REG_SetSequencerConfigurable() and LL_ADC_REG_SetSequencerLength().
On this STM32 series, after modifying sequencer (functions LL_ADC_REG_SetSequencerLength() LL_ADC_REG_SetSequencerRanks(), ...) it is mandatory to wait for the assertion of CCRDY flag using LL_ADC_IsActiveFlag_CCRDY(). Otherwise, some actions may be ignored. Refer to description of LL_ADC_IsActiveFlag_CCRDY for more details.
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 series, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
One or several values can be selected. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd
CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
Parameters:
ADCx ADC instance
Channel This parameter can be a combination of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
None

Definition at line 3067 of file stm32g0xx_ll_adc.h.

References ADC_CHANNEL_ID_BITFIELD_MASK.

Referenced by HAL_ADC_ConfigChannel().

__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group regular sequence: channel on rank corresponding to channel number.

Note:
This function performs:
  • Channels ordering into each rank of scan sequence: rank of each channel is fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
  • Set channels selected by overwriting the current sequencer configuration.
On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available, they can be chosen using function LL_ADC_REG_SetSequencerConfigurable(). This function can be used with setting "not fully configurable". Refer to description of functions LL_ADC_REG_SetSequencerConfigurable() and LL_ADC_REG_SetSequencerLength().
On this STM32 series, after modifying sequencer (functions LL_ADC_REG_SetSequencerLength() LL_ADC_REG_SetSequencerRanks(), ...) it is mandatory to wait for the assertion of CCRDY flag using LL_ADC_IsActiveFlag_CCRDY(). Otherwise, some actions may be ignored. Refer to description of LL_ADC_IsActiveFlag_CCRDY for more details.
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 series, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
One or several values can be selected. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels
CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
Parameters:
ADCx ADC instance
Channel This parameter can be a combination of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
None

Definition at line 2975 of file stm32g0xx_ll_adc.h.

References ADC_CHANNEL_ID_BITFIELD_MASK.

__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Remove channel to ADC group regular sequence: channel on rank corresponding to channel number.

Note:
This function performs:
  • Channels ordering into each rank of scan sequence: rank of each channel is fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
  • Set channels selected by removing them to the current sequencer configuration.
On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available, they can be chosen using function LL_ADC_REG_SetSequencerConfigurable(). This function can be used with setting "not fully configurable". Refer to description of functions LL_ADC_REG_SetSequencerConfigurable() and LL_ADC_REG_SetSequencerLength().
On this STM32 series, after modifying sequencer (functions LL_ADC_REG_SetSequencerLength() LL_ADC_REG_SetSequencerRanks(), ...) it is mandatory to wait for the assertion of CCRDY flag using LL_ADC_IsActiveFlag_CCRDY(). Otherwise, some actions may be ignored. Refer to description of LL_ADC_IsActiveFlag_CCRDY for more details.
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 series, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
One or several values can be selected. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem
CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
Parameters:
ADCx ADC instance
Channel This parameter can be a combination of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
None

Definition at line 3159 of file stm32g0xx_ll_adc.h.

References ADC_CHANNEL_ID_BITFIELD_MASK.

Referenced by HAL_ADC_ConfigChannel().

__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Configurability
 | ) |  |

Set ADC group regular sequencer configuration flexibility.

Note:
On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available:
  • sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
  • sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function LL_ADC_REG_SetSequencerChannels().
On this STM32 series, after modifying sequencer (functions LL_ADC_REG_SetSequencerLength() LL_ADC_REG_SetSequencerRanks(), ...) it is mandatory to wait for the assertion of CCRDY flag Otherwise, some actions may be ignored. Refer to description of LL_ADC_IsActiveFlag_CCRDY for more details.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
Parameters:
ADCx ADC instance
Configurability This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_FIXED
  • LL_ADC_REG_SEQ_CONFIGURABLE
Return values:
None

Definition at line 2461 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
Return values:
None

Definition at line 2706 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()". To set scan direction differently, refer to function LL_ADC_REG_SetSequencerScanDirection().
On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are available, they can be chosen using function LL_ADC_REG_SetSequencerConfigurable().
On this STM32 series, after modifying sequencer (functions LL_ADC_REG_SetSequencerLength() LL_ADC_REG_SetSequencerRanks(), ...) it is mandatory to wait for the assertion of CCRDY flag using LL_ADC_IsActiveFlag_CCRDY(). Otherwise, some actions may be ignored. Refer to description of LL_ADC_IsActiveFlag_CCRDY for more details.
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CHSELR SQ1 LL_ADC_REG_SetSequencerLength
CHSELR SQ2 LL_ADC_REG_SetSequencerLength
CHSELR SQ3 LL_ADC_REG_SetSequencerLength
CHSELR SQ4 LL_ADC_REG_SetSequencerLength
CHSELR SQ5 LL_ADC_REG_SetSequencerLength
CHSELR SQ6 LL_ADC_REG_SetSequencerLength
CHSELR SQ7 LL_ADC_REG_SetSequencerLength
CHSELR SQ8 LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
Return values:
None

Definition at line 2559 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group regular sequence: channel on the selected scan sequence rank.

Note:
This function performs configuration of:
  • Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.
On this STM32 series, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 series, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 series, after modifying sequencer (functions LL_ADC_REG_SetSequencerLength() LL_ADC_REG_SetSequencerRanks(), ...) it is mandatory to wait for the assertion of CCRDY flag using LL_ADC_IsActiveFlag_CCRDY(). Otherwise, some actions may be ignored. Refer to description of LL_ADC_IsActiveFlag_CCRDY for more details.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CHSELR SQ1 LL_ADC_REG_SetSequencerRanks
CHSELR SQ2 LL_ADC_REG_SetSequencerRanks
CHSELR SQ3 LL_ADC_REG_SetSequencerRanks
CHSELR SQ4 LL_ADC_REG_SetSequencerRanks
CHSELR SQ5 LL_ADC_REG_SetSequencerRanks
CHSELR SQ6 LL_ADC_REG_SetSequencerRanks
CHSELR SQ7 LL_ADC_REG_SetSequencerRanks
CHSELR SQ8 LL_ADC_REG_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
None

Definition at line 2801 of file stm32g0xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK_SEQ, and ADC_REG_RANK_ID_SQRX_MASK.

Referenced by HAL_ADC_ConfigChannel().

__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ScanDirection
 | ) |  |

Set ADC group regular sequencer scan direction.

Note:
On this STM32 series, parameter relevant only is sequencer is set to mode not fully configurable, refer to function LL_ADC_REG_SetSequencerConfigurable().
On some other STM32 series, this setting is not available and the default scan direction is forward.
On this STM32 series, after modifying sequencer (functions LL_ADC_REG_SetSequencerLength() LL_ADC_REG_SetSequencerRanks(), ...) it is mandatory to wait for the assertion of CCRDY flag using LL_ADC_IsActiveFlag_CCRDY(). Otherwise, some actions may be ignored. Refer to description of LL_ADC_IsActiveFlag_CCRDY for more details.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
Parameters:
ADCx ADC instance
ScanDirection This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
  • LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
Return values:
None

Definition at line 2667 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 2409 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().
On this STM32 series, ADC trigger frequency mode must be set in function of frequency of ADC group regular conversion trigger. Refer to description of function LL_ADC_SetTriggerFrequencyMode().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource
CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH4
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO (1)
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11
(1) On STM32G0, parameter not available on all devices
Return values:
None

Definition at line 2331 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of ADC hierarchical scope: channels

Functions
Configuration of ADC hierarchical scope: channels
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
Conversion time is the addition of sampling time and processing time. Refer to reference manual for ADC processing time of this STM32 series.
Reference Manual to LL API cross reference:
SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime
SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_COMMON_1
  • LL_ADC_SAMPLINGTIME_COMMON_2

Definition at line 3568 of file stm32g0xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_SAMPLING_TIME_CH_MASK, ADC_SMPR_SMPSEL0_BITOFFSET_POS, LL_ADC_SAMPLINGTIME_COMMON_1, and LL_ADC_SAMPLINGTIME_COMMON_2.

__STATIC_INLINE void LL_ADC_SetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SamplingTimeY
 | ) |  |

Set sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
In case of internal channel (VrefInt, TempSensor, ...) to be converted: sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values (parameters TS_vrefint, TS_temp, ...).
Conversion time is the addition of sampling time and processing time. Refer to reference manual for ADC processing time of this STM32 series.
In case of ADC conversion of internal channel (VrefInt, temperature sensor, ...), a sampling time minimum value is required. Refer to device datasheet.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime
SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be a combination of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15 (1)
  • LL_ADC_CHANNEL_16 (1)
  • LL_ADC_CHANNEL_17 (1)
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(1) On STM32G0, parameter can be set in ADC group sequencer only if sequencer is set in mode "not fully configurable", refer to function LL_ADC_REG_SetSequencerConfigurable().
SamplingTimeY This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_COMMON_1
  • LL_ADC_SAMPLINGTIME_COMMON_2
Return values:
None

Definition at line 3499 of file stm32g0xx_ll_adc.h.

References ADC_SAMPLING_TIME_CH_MASK, and ADC_SMPR_SMPSEL0_BITOFFSET_POS.

Referenced by HAL_ADC_ConfigChannel().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of ADC transversal scope: analog watchdog

Functions
Configuration of ADC transversal scope: analog watchdog
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdHighValue,
 |  | uint32_t | AWDThresholdLowValue
 | ) |  |

Set ADC analog watchdog thresholds value of both thresholds high and low.

Note:
If value of only one threshold high or low must be set, use function LL_ADC_SetAnalogWDThresholds().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 series, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC group regular.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). Examples:
  • Oversampling ratio and shift selected to have ADC conversion data on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): ADC analog watchdog thresholds must be divided by 16.
  • Oversampling ratio and shift selected to have ADC conversion data on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): ADC analog watchdog thresholds must be divided by 4.
  • Oversampling ratio and shift selected to have ADC conversion data on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): ADC analog watchdog thresholds match directly to ADC data register.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds
AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds
AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds
AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds
AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds
AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdHighValue | Value between Min_Data=0x000 and Max_Data=0xFFF
AWDThresholdLowValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 3877 of file stm32g0xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_CR3_REGOFFSET, ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS, ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS, ADC_AWD_TRX_REGOFFSET_MASK, and ADC_TR1_HT1_BITOFFSET_POS.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy
 | ) |  |

Get ADC analog watchdog monitored channel.

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Applicable only when the analog watchdog is set to monitor one channel.
On this STM32 series, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC group regular.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels
CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels
CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2 (1)
  • LL_ADC_AWD3 (1)
(1) On this AWD number, monitored channel can be retrieved if only 1 channel is programmed (or none or all channels). This function cannot retrieve monitored channel if multiple channels are programmed simultaneously by bitfield.
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_18_REG

Definition at line 3760 of file stm32g0xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, __LL_ADC_CHANNEL_TO_DECIMAL_NB, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR23_CHANNEL_MASK, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_MASK, ADC_AWD_CRX_REGOFFSET_POS, and LL_ADC_AWD1.

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow
 | ) |  |

Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Note:
If raw data with ADC thresholds high and low is retrieved, the data of each threshold high or low can be isolated using helper macro: __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
Reference Manual to LL API cross reference:
AWD1TR HT1 LL_ADC_GetAnalogWDThresholds
AWD2TR HT2 LL_ADC_GetAnalogWDThresholds
AWD3TR HT3 LL_ADC_GetAnalogWDThresholds
AWD1TR LT1 LL_ADC_GetAnalogWDThresholds
AWD2TR LT2 LL_ADC_GetAnalogWDThresholds
AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 4000 of file stm32g0xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_CR3_REGOFFSET, ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS, ADC_AWD_TRX_BIT_HIGH_MASK, ADC_AWD_TRX_BIT_HIGH_SHIFT4, ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS, and ADC_AWD_TRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDChannelGroup
 | ) |  |

Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC group regular.

Note:
Once monitored channels are selected, analog watchdog is enabled.
In case of need to define a single channel to monitor with analog watchdog from sequencer channel definition, use helper macro __LL_ADC_ANALOGWD_CHANNEL_GROUP().
On this STM32 series, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC group regular.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels
CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels
CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDChannelGroup This parameter can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_18_REG
  • LL_ADC_AWD_CH_VREFINT_REG
  • LL_ADC_AWD_CH_TEMPSENSOR_REG
  • LL_ADC_AWD_CH_VBAT_REG
Return values:
None

Definition at line 3660 of file stm32g0xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS, ADC_AWD_CRX_REGOFFSET_MASK, and LL_ADC_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow,
 |  | uint32_t | AWDThresholdValue
 | ) |  |

Set ADC analog watchdog threshold value of threshold high or low.

Note:
If values of both thresholds high or low must be set, use function LL_ADC_ConfigAnalogWDThresholds().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 series, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC group regular.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). Examples:
  • Oversampling ratio and shift selected to have ADC conversion data on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): ADC analog watchdog thresholds must be divided by 16.
  • Oversampling ratio and shift selected to have ADC conversion data on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): ADC analog watchdog thresholds must be divided by 4.
  • Oversampling ratio and shift selected to have ADC conversion data on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): ADC analog watchdog thresholds match directly to ADC data register.
On this STM32 series, setting of this feature is not conditioned to ADC state: ADC can be disabled, enabled with or without conversion on going on ADC group regular.
Reference Manual to LL API cross reference:
AWD1TR HT1 LL_ADC_SetAnalogWDThresholds
AWD2TR HT2 LL_ADC_SetAnalogWDThresholds
AWD3TR HT3 LL_ADC_SetAnalogWDThresholds
AWD1TR LT1 LL_ADC_SetAnalogWDThresholds
AWD2TR LT2 LL_ADC_SetAnalogWDThresholds
AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
AWDThresholdValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 3955 of file stm32g0xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_CR3_REGOFFSET, ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS, ADC_AWD_TRX_BIT_HIGH_MASK, ADC_AWD_TRX_BIT_HIGH_SHIFT4, ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS, and ADC_AWD_TRX_REGOFFSET_MASK.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of ADC transversal scope: oversampling

Functions
Configuration of ADC transversal scope: oversampling
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
Get ADC oversampling scope.
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
Get ADC oversampling ratio.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
Get ADC oversampling shift.

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Ratio,
 |  | uint32_t | Shift
 | ) |  |

Set ADC oversampling.

Note:
This function set the 2 items of oversampling configuration:
  • ratio
  • shift
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift
CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
Parameters:
ADCx ADC instance
Ratio This parameter can be one of the following values:
  • LL_ADC_OVS_RATIO_2
  • LL_ADC_OVS_RATIO_4
  • LL_ADC_OVS_RATIO_8
  • LL_ADC_OVS_RATIO_16
  • LL_ADC_OVS_RATIO_32
  • LL_ADC_OVS_RATIO_64
  • LL_ADC_OVS_RATIO_128
  • LL_ADC_OVS_RATIO_256
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8
Return values:
None

Definition at line 4129 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont ( ADC_TypeDef * ADCx )

Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
Reference Manual to LL API cross reference:
CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT

Definition at line 4092 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio ( ADC_TypeDef * ADCx )

Get ADC oversampling ratio.

Reference Manual to LL API cross reference:
CFGR2 OVSR LL_ADC_GetOverSamplingRatio
Parameters:
ADCx ADC instance
Return values:
Ratio This parameter can be one of the following values:
  • LL_ADC_OVS_RATIO_2
  • LL_ADC_OVS_RATIO_4
  • LL_ADC_OVS_RATIO_8
  • LL_ADC_OVS_RATIO_16
  • LL_ADC_OVS_RATIO_32
  • LL_ADC_OVS_RATIO_64
  • LL_ADC_OVS_RATIO_128
  • LL_ADC_OVS_RATIO_256

Definition at line 4148 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope ( ADC_TypeDef * ADCx )

Get ADC oversampling scope.

Reference Manual to LL API cross reference:
CFGR2 OVSE LL_ADC_GetOverSamplingScope
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED

Definition at line 4050 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift ( ADC_TypeDef * ADCx )

Get ADC oversampling shift.

Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_GetOverSamplingShift
Parameters:
ADCx ADC instance
Return values:
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8

Definition at line 4168 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OverSamplingDiscont
 | ) |  |

Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
Parameters:
ADCx ADC instance
OverSamplingDiscont This parameter can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT
Return values:
None

Definition at line 4073 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingScope | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OvsScope
 | ) |  |

Set ADC oversampling scope.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be disabled.
Reference Manual to LL API cross reference:
CFGR2 OVSE LL_ADC_SetOverSamplingScope
Parameters:
ADCx ADC instance
OvsScope This parameter can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
Return values:
None

Definition at line 4037 of file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Operation on ADC hierarchical scope: ADC instance

Functions
Operation on ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.

Function Documentation

__STATIC_INLINE void LL_ADC_Disable ( ADC_TypeDef * ADCx )

Disable the selected ADC instance.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be not disabled. Must be enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_Disable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4274 of file stm32g0xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_Disable(), HAL_ADC_Start_DMA(), HAL_ADCEx_Calibration_Start(), and LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_DisableInternalRegulator ( ADC_TypeDef * ADCx )

Disable ADC internal voltage regulator.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_DisableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4222 of file stm32g0xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_DisableVoltageRegulator().

__STATIC_INLINE void LL_ADC_Enable ( ADC_TypeDef * ADCx )

Enable the selected ADC instance.

Note:
On this STM32 series, after ADC enable, a delay for ADC internal analog stabilization is required before performing a ADC conversion start. Refer to device datasheet, parameter tSTAB.
On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled and ADC internal voltage regulator enabled.
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_Enable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4254 of file stm32g0xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_Enable(), and HAL_ADCEx_Calibration_Start().

__STATIC_INLINE void LL_ADC_EnableInternalRegulator ( ADC_TypeDef * ADCx )

Enable ADC instance internal voltage regulator.

Note:
On this STM32 series, there are three possibilities to enable the voltage regulator:
  • by enabling it manually using function LL_ADC_EnableInternalRegulator().
  • by launching a calibration using function LL_ADC_StartCalibration().
  • by enabling the ADC using function LL_ADC_Enable().
On this STM32 series, after ADC internal voltage regulator enable, a delay for ADC internal voltage regulator stabilization is required before performing a ADC calibration or ADC enable. Refer to device datasheet, parameter "tADCVREG_STUP". Refer to literal LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_EnableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4203 of file stm32g0xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_Init().

__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing ( ADC_TypeDef * ADCx )

Get ADC calibration state.

Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_IsCalibrationOnGoing
Parameters:
ADCx ADC instance
Return values:
0,: calibration complete, 1: calibration in progress.

Definition at line 4353 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_Start().

__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing ( ADC_TypeDef * ADCx )

Get the selected ADC instance disable state.

Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_IsDisableOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no ADC disable command on going.

Definition at line 4304 of file stm32g0xx_ll_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_IsEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance enable state.

Note:
On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_IsEnabled
Parameters:
ADCx ADC instance
Return values:
0,: ADC is disabled, 1: ADC is enabled.

Definition at line 4293 of file stm32g0xx_ll_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_Init(), HAL_ADC_Start_DMA(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableVoltageRegulator(), LL_ADC_DeInit(), LL_ADC_Init(), and LL_ADC_REG_Init().

__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance internal voltage regulator state.

Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
Parameters:
ADCx ADC instance
Return values:
0,: internal regulator is disabled, 1: internal regulator is enabled.

Definition at line 4233 of file stm32g0xx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_StartCalibration ( ADC_TypeDef * ADCx )

Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).

Note:
On this STM32 series, a minimum number of ADC clock cycles are required between ADC end of calibration and ADC enable. Refer to literal LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
In case of usage of ADC with DMA transfer: On this STM32 series, ADC DMA transfer request should be disabled during calibration: Calibration factor is available in data register and also transferred by DMA. To not insert ADC calibration factor among ADC conversion data in array variable, DMA transfer must be disabled during calibration. (DMA transfer setting backup and disable before calibration, DMA transfer setting restore after calibration. Refer to functions LL_ADC_REG_GetDMATransfer(), LL_ADC_REG_SetDMATransfer() ).
In case of usage of feature auto power-off: This mode must be disabled during calibration Refer to function LL_ADC_SetLowPowerMode().
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_StartCalibration
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4337 of file stm32g0xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADCEx_Calibration_Start().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Operation on ADC hierarchical scope: group regular

Functions
Operation on ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData6 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group regular conversion state.

Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group regular.

Definition at line 4420 of file stm32g0xx_ll_adc.h.

Referenced by ADC_ConversionStop(), ADC_DMAConvCplt(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_Calibration_SetValue(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group regular command of conversion stop state.

Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group regular.

Definition at line 4431 of file stm32g0xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR DATA LL_ADC_REG_ReadConversionData10
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 4475 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR DATA LL_ADC_REG_ReadConversionData12
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 4460 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
DR DATA LL_ADC_REG_ReadConversionData32
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 4445 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 6 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR DATA LL_ADC_REG_ReadConversionData6
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 4505 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR DATA LL_ADC_REG_ReadConversionData8
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 4490 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group regular conversion.

Note:
On this STM32 series, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group regular, without conversion stop command on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4384 of file stm32g0xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

__STATIC_INLINE void LL_ADC_REG_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group regular conversion.

Note:
On this STM32 series, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4404 of file stm32g0xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_ConversionStop(), and LL_ADC_DeInit().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC flag management

Functions
ADC flag management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_CCRDY (ADC_TypeDef *ADCx)
Get flag ADC channel configuration ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOCAL (ADC_TypeDef *ADCx)
Get flag ADC end of calibration.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_CCRDY (ADC_TypeDef *ADCx)
Clear flag ADC channel configuration ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOCAL (ADC_TypeDef *ADCx)
Clear flag ADC end of calibration.

Function Documentation

__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY ( ADC_TypeDef * ADCx )

Clear flag ADC ready.

Note:
On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_ClearFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4656 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE void LL_ADC_ClearFlag_AWD1 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 1.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_ClearFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4722 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_AWD2 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_ClearFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4733 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_AWD3 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_ClearFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4744 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_CCRDY ( ADC_TypeDef * ADCx )

Clear flag ADC channel configuration ready.

Reference Manual to LL API cross reference:
ISR CCRDY LL_ADC_ClearFlag_CCRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4667 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_CCRDY.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_ClearFlag_EOC ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_ClearFlag_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4678 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_EOC.

__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL ( ADC_TypeDef * ADCx )

Clear flag ADC end of calibration.

Reference Manual to LL API cross reference:
ISR EOCAL LL_ADC_ClearFlag_EOCAL
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4755 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_EOCAL.

__STATIC_INLINE void LL_ADC_ClearFlag_EOS ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_ClearFlag_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4689 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_ClearFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4711 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP.

__STATIC_INLINE void LL_ADC_ClearFlag_OVR ( ADC_TypeDef * ADCx )

Clear flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_ClearFlag_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4700 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY ( ADC_TypeDef * ADCx )

Get flag ADC ready.

Note:
On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4527 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 1 flag.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_IsActiveFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4609 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_IsActiveFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4620 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_IsActiveFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4631 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY ( ADC_TypeDef * ADCx )

Get flag ADC channel configuration ready.

Note:
On this STM32 series, after modifying sequencer it is mandatory to wait for the assertion of CCRDY flag using LL_ADC_IsActiveFlag_CCRDY(). Otherwise, performing some actions (configuration update, ADC conversion start, ... ) will be ignored. Functions requiring wait for CCRDY flag are: LL_ADC_REG_SetSequencerLength() LL_ADC_REG_SetSequencerRanks() LL_ADC_REG_SetSequencerChannels() LL_ADC_REG_SetSequencerChAdd() LL_ADC_REG_SetSequencerChRem() LL_ADC_REG_SetSequencerScanDirection() LL_ADC_REG_SetSequencerConfigurable()
Duration of ADC channel configuration ready: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles after the channel configuration has been changed.
Reference Manual to LL API cross reference:
ISR CCRDY LL_ADC_IsActiveFlag_CCRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4554 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_CCRDY.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_IsActiveFlag_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4565 of file stm32g0xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL ( ADC_TypeDef * ADCx )

Get flag ADC end of calibration.

Reference Manual to LL API cross reference:
ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4642 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_EOCAL.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_IsActiveFlag_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4576 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4598 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR ( ADC_TypeDef * ADCx )

Get flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_IsActiveFlag_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4587 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_OVR.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC IT management

Functions
ADC IT management
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_CCRDY (ADC_TypeDef *ADCx)
Enable interruption ADC channel configuration ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_EnableIT_EOCAL (ADC_TypeDef *ADCx)
Enable interruption ADC end of calibration.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_CCRDY (ADC_TypeDef *ADCx)
Disable interruption ADC channel configuration ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_EOCAL (ADC_TypeDef *ADCx)
Disable interruption ADC end of calibration.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_CCRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC channel configuration ready.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOCAL (ADC_TypeDef *ADCx)
Get state of interruption ADC end of calibration (0: interrupt disabled, 1: interrupt enabled).

Function Documentation

__STATIC_INLINE void LL_ADC_DisableIT_ADRDY ( ADC_TypeDef * ADCx )

Disable interruption ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_DisableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4884 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_DisableIT_AWD1 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_DisableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4950 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_AWD2 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_DisableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4961 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_AWD3 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_DisableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4972 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_CCRDY ( ADC_TypeDef * ADCx )

Disable interruption ADC channel configuration ready.

Reference Manual to LL API cross reference:
IER CCRDYIE LL_ADC_DisableIT_CCRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4895 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_CCRDY.

__STATIC_INLINE void LL_ADC_DisableIT_EOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_DisableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4906 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE void LL_ADC_DisableIT_EOCAL ( ADC_TypeDef * ADCx )

Disable interruption ADC end of calibration.

Reference Manual to LL API cross reference:
IER EOCALIE LL_ADC_DisableIT_EOCAL
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4983 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOCAL.

__STATIC_INLINE void LL_ADC_DisableIT_EOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_DisableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4917 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE void LL_ADC_DisableIT_EOSMP ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_DisableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4939 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE void LL_ADC_DisableIT_OVR ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_DisableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4928 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE void LL_ADC_EnableIT_ADRDY ( ADC_TypeDef * ADCx )

Enable ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_EnableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4774 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_EnableIT_AWD1 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4840 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_AWD2 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_EnableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4851 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_AWD3 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_EnableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4862 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_CCRDY ( ADC_TypeDef * ADCx )

Enable interruption ADC channel configuration ready.

Reference Manual to LL API cross reference:
IER CCRDYIE LL_ADC_EnableIT_CCRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4785 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_CCRDY.

__STATIC_INLINE void LL_ADC_EnableIT_EOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_EnableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4796 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE void LL_ADC_EnableIT_EOCAL ( ADC_TypeDef * ADCx )

Enable interruption ADC end of calibration.

Reference Manual to LL API cross reference:
IER EOCALIE LL_ADC_EnableIT_EOCAL
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4873 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOCAL.

__STATIC_INLINE void LL_ADC_EnableIT_EOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_EnableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4807 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE void LL_ADC_EnableIT_EOSMP ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_EnableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4829 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE void LL_ADC_EnableIT_OVR ( ADC_TypeDef * ADCx )

Enable ADC group regular interruption overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_EnableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4818 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY ( ADC_TypeDef * ADCx )

Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 4995 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1 ( ADC_TypeDef * ADCx )

Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_IsEnabledIT_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5066 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2 ( ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_IsEnabledIT_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5078 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3 ( ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_IsEnabledIT_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5090 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY ( ADC_TypeDef * ADCx )

Get state of interruption ADC channel configuration ready.

Reference Manual to LL API cross reference:
IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5006 of file stm32g0xx_ll_adc.h.

References LL_ADC_FLAG_CCRDY.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_IsEnabledIT_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5018 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL ( ADC_TypeDef * ADCx )

Get state of interruption ADC end of calibration (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5102 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOCAL.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_IsEnabledIT_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5030 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5054 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_IsEnabledIT_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5042 of file stm32g0xx_ll_adc.h.

References LL_ADC_IT_OVR.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *pADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_ADC_CommonDeInit ( ADC_Common_TypeDef * ADCxy_COMMON )

De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.

Note:
This function is performing a hard reset, using high level clock source RCC ADC reset.
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are de-initialized
  • ERROR: not applicable

Definition at line 240 of file stm32g0xx_ll_adc.c.

References assert_param, LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_ADC, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_ADC_CommonInit | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | LL_ADC_CommonInitTypeDef * | pADC_CommonInitStruct
 | ) |  |

Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).

Note:
The setting of ADC common parameters is conditioned to ADC instances state: All ADC instances belonging to the same ADC common instance must be disabled.
Parameters:
ADCxy_COMMON | ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
pADC_CommonInitStruct | Pointer to a LL_ADC_CommonInitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are initialized
  • ERROR: ADC common registers are not initialized

Definition at line 272 of file stm32g0xx_ll_adc.c.

References __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, assert_param, LL_ADC_CommonInitTypeDef::CommonClock, IS_LL_ADC_COMMON_CLOCK, and LL_ADC_SetCommonClock().

void LL_ADC_CommonStructInit ( LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct )

Set each LL_ADC_CommonInitTypeDef field to default value.

Parameters:
pADC_CommonInitStruct Pointer to a LL_ADC_CommonInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 309 of file stm32g0xx_ll_adc.c.

References LL_ADC_CommonInitTypeDef::CommonClock, and LL_ADC_CLOCK_ASYNC_DIV2.

ErrorStatus LL_ADC_DeInit ( ADC_TypeDef * ADCx )

De-initialize registers of the selected ADC instance to their default reset values.

Note:
To reset all ADC instances quickly (perform a hard reset), use function LL_ADC_CommonDeInit().
If this functions returns error status, it means that ADC instance is in an unknown state. In this case, perform a hard reset using high level clock source RCC ADC reset. Refer to function LL_ADC_CommonDeInit().
Parameters:
ADCx ADC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are de-initialized
  • ERROR: ADC registers are not de-initialized

Definition at line 333 of file stm32g0xx_ll_adc.c.

References ADC_TIMEOUT_CCRDY_CPU_CYCLES, ADC_TIMEOUT_DISABLE_CPU_CYCLES, ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES, assert_param, LL_ADC_ClearFlag_CCRDY(), LL_ADC_Disable(), LL_ADC_FLAG_ADRDY, LL_ADC_FLAG_AWD1, LL_ADC_FLAG_AWD2, LL_ADC_FLAG_AWD3, LL_ADC_FLAG_CCRDY, LL_ADC_FLAG_EOC, LL_ADC_FLAG_EOCAL, LL_ADC_FLAG_EOS, LL_ADC_FLAG_EOSMP, LL_ADC_FLAG_OVR, LL_ADC_IsActiveFlag_CCRDY(), LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), LL_ADC_IT_ADRDY, LL_ADC_IT_AWD1, LL_ADC_IT_AWD2, LL_ADC_IT_AWD3, LL_ADC_IT_CCRDY, LL_ADC_IT_EOC, LL_ADC_IT_EOCAL, LL_ADC_IT_EOS, LL_ADC_IT_EOSMP, LL_ADC_IT_OVR, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsStopConversionOngoing(), LL_ADC_REG_SetTriggerSource(), LL_ADC_REG_StopConversion(), and LL_ADC_REG_TRIG_SOFTWARE.

ErrorStatus LL_ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_InitTypeDef * | pADC_InitStruct
 | ) |  |

Initialize some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, some other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular sequencer: Depending on the sequencer mode (refer to function LL_ADC_REG_SetSequencerConfigurable() ):
    • map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks();
    • map channel on rank corresponding to channel number. Refer to function LL_ADC_REG_SetSequencerChannels();
  • Set ADC channel sampling time Refer to function LL_ADC_SetSamplingTimeCommonChannels(); Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
pADC_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 543 of file stm32g0xx_ll_adc.c.

References assert_param, LL_ADC_InitTypeDef::Clock, LL_ADC_InitTypeDef::DataAlignment, IS_LL_ADC_CLOCK, IS_LL_ADC_DATA_ALIGN, IS_LL_ADC_LOW_POWER, IS_LL_ADC_RESOLUTION, LL_ADC_IsEnabled(), LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

ErrorStatus LL_ADC_REG_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_REG_InitTypeDef * | pADC_RegInitStruct
 | ) |  |

Initialize some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
Before using this function, ADC group regular sequencer must be configured: refer to function LL_ADC_REG_SetSequencerConfigurable().
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular sequencer: Depending on the sequencer mode (refer to function LL_ADC_REG_SetSequencerConfigurable() ):
    • map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks();
    • map channel on rank corresponding to channel number. Refer to function LL_ADC_REG_SetSequencerChannels();
  • Set ADC channel sampling time Refer to function LL_ADC_SetSamplingTimeCommonChannels(); Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
pADC_RegInitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 647 of file stm32g0xx_ll_adc.c.

References assert_param, LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, IS_LL_ADC_REG_CONTINUOUS_MODE, IS_LL_ADC_REG_DMA_TRANSFER, IS_LL_ADC_REG_OVR_DATA_BEHAVIOR, IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_REG_SEQ_SCAN_LENGTH, IS_LL_ADC_REG_TRIG_SOURCE, LL_ADC_IsEnabled(), LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_GetSequencerConfigurable(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_FIXED, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_SetSequencerLength(), LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_REG_StructInit ( LL_ADC_REG_InitTypeDef * pADC_RegInitStruct )

Set each LL_ADC_REG_InitTypeDef field to default value.

Parameters:
pADC_RegInitStruct Pointer to a LL_ADC_REG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 755 of file stm32g0xx_ll_adc.c.

References LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_DMA_TRANSFER_NONE, LL_ADC_REG_OVR_DATA_OVERWRITTEN, LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_TRIG_SOFTWARE, LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_StructInit ( LL_ADC_InitTypeDef * pADC_InitStruct )

Set each LL_ADC_InitTypeDef field to default value.

Parameters:
pADC_InitStruct Pointer to a LL_ADC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 596 of file stm32g0xx_ll_adc.c.

References LL_ADC_InitTypeDef::Clock, LL_ADC_InitTypeDef::DataAlignment, LL_ADC_CLOCK_SYNC_PCLK_DIV2, LL_ADC_DATA_ALIGN_RIGHT, LL_ADC_LP_MODE_NONE, LL_ADC_RESOLUTION_12B, LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB1 GRP1 PERIPH

Defines
AHB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
#define | LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
#define | LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN

Define Documentation

#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 72 of file stm32g0xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN

Definition at line 80 of file stm32g0xx_ll_bus.h.

Referenced by LL_CRC_DeInit().

#define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN

Definition at line 83 of file stm32g0xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN

Definition at line 73 of file stm32g0xx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN

Definition at line 75 of file stm32g0xx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN

Definition at line 77 of file stm32g0xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN

Definition at line 86 of file stm32g0xx_ll_bus.h.

Referenced by LL_RNG_DeInit().

#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN

Definition at line 78 of file stm32g0xx_ll_bus.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB1 GRP1 PERIPH

Defines
APB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APBENR1_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APBENR1_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APBENR1_TIM7EN
#define | LL_APB1_GRP1_PERIPH_LPUART2 RCC_APBENR1_LPUART2EN
#define | LL_APB1_GRP1_PERIPH_USART5 RCC_APBENR1_USART5EN
#define | LL_APB1_GRP1_PERIPH_USART6 RCC_APBENR1_USART6EN
#define | LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
#define | LL_APB1_GRP1_PERIPH_FDCAN RCC_APBENR1_FDCANEN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APBENR1_SPI3EN
#define | LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN
#define | LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN
#define | LL_APB1_GRP1_PERIPH_LPUART1 RCC_APBENR1_LPUART1EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APBENR1_I2C3EN
#define | LL_APB1_GRP1_PERIPH_CEC RCC_APBENR1_CECEN
#define | LL_APB1_GRP1_PERIPH_UCPD1 RCC_APBENR1_UCPD1EN
#define | LL_APB1_GRP1_PERIPH_UCPD2 RCC_APBENR1_UCPD2EN
#define | LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
#define | LL_APB1_GRP1_PERIPH_DAC1 RCC_APBENR1_DAC1EN
#define | LL_APB1_GRP1_PERIPH_LPTIM2 RCC_APBENR1_LPTIM2EN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIM1EN

Define Documentation

#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 96 of file stm32g0xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_CEC RCC_APBENR1_CECEN

Definition at line 152 of file stm32g0xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN

Definition at line 134 of file stm32g0xx_ll_bus.h.

Referenced by LL_CRS_DeInit().

#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APBENR1_DAC1EN

Definition at line 163 of file stm32g0xx_ll_bus.h.

Referenced by LL_DAC_DeInit().

#define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN

Definition at line 160 of file stm32g0xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_FDCAN RCC_APBENR1_FDCANEN

Definition at line 124 of file stm32g0xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN

Definition at line 146 of file stm32g0xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN

Definition at line 147 of file stm32g0xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APBENR1_I2C3EN

Definition at line 149 of file stm32g0xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIM1EN

Definition at line 169 of file stm32g0xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB1_GRP1_PERIPH_LPTIM2 RCC_APBENR1_LPTIM2EN

Definition at line 166 of file stm32g0xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APBENR1_LPUART1EN

Definition at line 144 of file stm32g0xx_ll_bus.h.

Referenced by LL_LPUART_DeInit().

#define LL_APB1_GRP1_PERIPH_LPUART2 RCC_APBENR1_LPUART2EN

Definition at line 113 of file stm32g0xx_ll_bus.h.

Referenced by LL_LPUART_DeInit().

#define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN

Definition at line 161 of file stm32g0xx_ll_bus.h.

Referenced by LL_PWR_DeInit().

#define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN

Definition at line 121 of file stm32g0xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN

Definition at line 129 of file stm32g0xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APBENR1_SPI3EN

Definition at line 131 of file stm32g0xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN

Definition at line 98 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN

Definition at line 101 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APBENR1_TIM4EN

Definition at line 104 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APBENR1_TIM6EN

Definition at line 107 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APBENR1_TIM7EN

Definition at line 110 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_UCPD1 RCC_APBENR1_UCPD1EN

Definition at line 155 of file stm32g0xx_ll_bus.h.

Referenced by LL_UCPD_DeInit(), and LL_UCPD_Init().

#define LL_APB1_GRP1_PERIPH_UCPD2 RCC_APBENR1_UCPD2EN

Definition at line 158 of file stm32g0xx_ll_bus.h.

Referenced by LL_UCPD_DeInit(), and LL_UCPD_Init().

#define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN

Definition at line 136 of file stm32g0xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN

Definition at line 138 of file stm32g0xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN

Definition at line 141 of file stm32g0xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART5 RCC_APBENR1_USART5EN

Definition at line 116 of file stm32g0xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART6 RCC_APBENR1_USART6EN

Definition at line 119 of file stm32g0xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN

Definition at line 127 of file stm32g0xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN

Definition at line 122 of file stm32g0xx_ll_bus.h.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB2 GRP1 PERIPH

Defines
APB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APBENR2_TIM1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APBENR2_SPI1EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APBENR2_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM14 RCC_APBENR2_TIM14EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APBENR2_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APBENR2_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APBENR2_TIM17EN
#define | LL_APB2_GRP1_PERIPH_ADC RCC_APBENR2_ADCEN

Define Documentation

#define LL_APB2_GRP1_PERIPH_ADC RCC_APBENR2_ADCEN

Definition at line 196 of file stm32g0xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit().

#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 178 of file stm32g0xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APBENR2_SPI1EN

Definition at line 181 of file stm32g0xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN

Definition at line 179 of file stm32g0xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APBENR2_TIM1EN

Definition at line 180 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM14 RCC_APBENR2_TIM14EN

Definition at line 184 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APBENR2_TIM15EN

Definition at line 187 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APBENR2_TIM16EN

Definition at line 190 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APBENR2_TIM17EN

Definition at line 193 of file stm32g0xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_USART1 RCC_APBENR2_USART1EN

Definition at line 182 of file stm32g0xx_ll_bus.h.

Referenced by LL_USART_DeInit().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IOP GRP1 PERIPH

Defines
IOP GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
#define | LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
#define | LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN
#define | LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN
#define | LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN
#define | LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN

Define Documentation

#define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU

Definition at line 205 of file stm32g0xx_ll_bus.h.

#define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN

Definition at line 206 of file stm32g0xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN

Definition at line 207 of file stm32g0xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN

Definition at line 208 of file stm32g0xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN

Definition at line 209 of file stm32g0xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN

Definition at line 211 of file stm32g0xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN

Definition at line 214 of file stm32g0xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB1

Functions
AHB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB1 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHBENR DMA1EN LL_AHB1_GRP1_DisableClock
AHBENR FLASHEN LL_AHB1_GRP1_DisableClock
AHBENR CRCEN LL_AHB1_GRP1_DisableClock
AHBENR AESEN LL_AHB1_GRP1_DisableClock
AHBENR RNGEN LL_AHB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_CRYP (*)
  • LL_AHB1_GRP1_PERIPH_RNG (*)
Note:
(*) RNG & CRYP Peripherals available only on STM32G081xx
Return values:
None

Definition at line 296 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable AHB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHBSMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHBSMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHBSMENR AESSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_SRAM
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_CRYP (*)
  • LL_AHB1_GRP1_PERIPH_RNG (*)
Note:
(*) RNG & CRYP Peripherals available only on STM32G081xx
Return values:
None

Definition at line 390 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHBENR DMA1EN LL_AHB1_GRP1_EnableClock
AHBENR FLASHEN LL_AHB1_GRP1_EnableClock
AHBENR CRCEN LL_AHB1_GRP1_EnableClock
AHBENR AESEN LL_AHB1_GRP1_EnableClock
AHBENR RNGEN LL_AHB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_CRYP (*)
  • LL_AHB1_GRP1_PERIPH_RNG (*)
Note:
(*) RNG & CRYP Peripherals available only on STM32G081xx
Return values:
None

Definition at line 250 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable AHB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHBSMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHBSMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHBSMENR AESSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_SRAM
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_CRYP (*)
  • LL_AHB1_GRP1_PERIPH_RNG (*)
Note:
(*) RNG & CRYP Peripherals available only on STM32G081xx
Return values:
None

Definition at line 363 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ForceReset ( uint32_t Periphs )

Force AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHBRSTR FLASHRST LL_AHB1_GRP1_ForceReset
AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset
AHBRSTR AESRST LL_AHB1_GRP1_ForceReset
AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_CRYP (*)
  • LL_AHB1_GRP1_PERIPH_RNG (*)
Note:
(*) RNG & CRYP Peripherals available only on STM32G081xx
Return values:
None

Definition at line 318 of file stm32g0xx_ll_bus.h.

Referenced by LL_CRC_DeInit(), LL_DMA_DeInit(), and LL_RNG_DeInit().

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHBENR FLASHEN LL_AHB1_GRP1_IsEnabledClock
AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock
AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_CRYP (*)
  • LL_AHB1_GRP1_PERIPH_RNG (*)
Note:
(*) RNG & CRYP Peripherals available only on STM32G081xx
Return values:
State of Periphs (1 or 0).

Definition at line 275 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHBRSTR FLASHRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset
AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_CRYP (*)
  • LL_AHB1_GRP1_PERIPH_RNG (*)
Note:
(*) RNG & CRYP Peripherals available only on STM32G081xx
Return values:
None

Definition at line 340 of file stm32g0xx_ll_bus.h.

Referenced by LL_CRC_DeInit(), LL_DMA_DeInit(), and LL_RNG_DeInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB1

Functions
APB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_APB1_GRP1_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APBENR1 TIM2EN LL_APB1_GRP1_DisableClock
APBENR1 TIM3EN LL_APB1_GRP1_DisableClock
APBENR1 TIM4EN LL_APB1_GRP1_DisableClock
APBENR1 TIM6EN LL_APB1_GRP1_DisableClock
APBENR1 TIM7EN LL_APB1_GRP1_DisableClock
APBENR1 RTCAPBEN LL_APB1_GRP1_DisableClock
APBENR1 WWDGEN LL_APB1_GRP1_DisableClock
APBENR1 SPI2EN LL_APB1_GRP1_DisableClock
APBENR1 SPI3EN LL_APB1_GRP1_DisableClock
APBENR1 USART2EN LL_APB1_GRP1_DisableClock
APBENR1 USART3EN LL_APB1_GRP1_DisableClock
APBENR1 USART4EN LL_APB1_GRP1_DisableClock
APBENR1 USART5EN LL_APB1_GRP1_DisableClock
APBENR1 USART6EN LL_APB1_GRP1_DisableClock
APBENR1 LPUART1EN LL_APB1_GRP1_DisableClock
APBENR1 LPUART2EN LL_APB1_GRP1_DisableClock
APBENR1 I2C1EN LL_APB1_GRP1_DisableClock
APBENR1 I2C2EN LL_APB1_GRP1_DisableClock
APBENR1 I2C3EN LL_APB1_GRP1_DisableClock
APBENR1 CECEN LL_APB1_GRP1_DisableClock
APBENR1 UCPD1EN LL_APB1_GRP1_DisableClock
APBENR1 UCPD2EN LL_APB1_GRP1_DisableClock
APBENR1 USBEN LL_APB1_GRP1_DisableClock
APBENR1 FDCANEN LL_APB1_GRP1_DisableClock
APBENR1 DBGEN LL_APB1_GRP1_DisableClock
APBENR1 PWREN LL_APB1_GRP1_DisableClock
APBENR1 DAC1EN LL_APB1_GRP1_DisableClock
APBENR1 LPTIM2EN LL_APB1_GRP1_DisableClock
APBENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2 (1)
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (1)
  • LL_APB1_GRP1_PERIPH_TIM6 (1)
  • LL_APB1_GRP1_PERIPH_TIM7 (1)
  • LL_APB1_GRP1_PERIPH_RTC
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3 (1)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (1)
  • LL_APB1_GRP1_PERIPH_USART4 (1)
  • LL_APB1_GRP1_PERIPH_USART5 (1)
  • LL_APB1_GRP1_PERIPH_USART6 (1)
  • LL_APB1_GRP1_PERIPH_LPUART1 (1)
  • LL_APB1_GRP1_PERIPH_LPUART2 (1)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3 (1)
  • LL_APB1_GRP1_PERIPH_CEC (1)
  • LL_APB1_GRP1_PERIPH_UCPD1 (1)
  • LL_APB1_GRP1_PERIPH_UCPD2 (1)
  • LL_APB1_GRP1_PERIPH_USB (1)
  • LL_APB1_GRP1_PERIPH_FDCAN (1)
  • LL_APB1_GRP1_PERIPH_DBGMCU
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM2 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM1 (1)
Note:
Peripheral marked with (1) are not available all devices
Return values:
None

Definition at line 609 of file stm32g0xx_ll_bus.h.

Referenced by LL_UCPD_DeInit().

__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APBSMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 TIM'SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 USART4SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 USART5SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 USART6SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 LPUART1SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 LPUART2SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 CECSMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 UCPD1SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 UCPD2SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 FSCANSMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 DBGSMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_DisableClockStopSleep
APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2 (1)
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (1)
  • LL_APB1_GRP1_PERIPH_TIM6 (1)
  • LL_APB1_GRP1_PERIPH_TIM7 (1)
  • LL_APB1_GRP1_PERIPH_RTC
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3 (1)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (1)
  • LL_APB1_GRP1_PERIPH_USART4 (1)
  • LL_APB1_GRP1_PERIPH_USART5 (1)
  • LL_APB1_GRP1_PERIPH_USART6 (1)
  • LL_APB1_GRP1_PERIPH_LPUART1 (1)
  • LL_APB1_GRP1_PERIPH_LPUART2 (1)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3 (1)
  • LL_APB1_GRP1_PERIPH_CEC (1)
  • LL_APB1_GRP1_PERIPH_UCPD1 (1)
  • LL_APB1_GRP1_PERIPH_UCPD2 (1)
  • LL_APB1_GRP1_PERIPH_USB (1)
  • LL_APB1_GRP1_PERIPH_FDCAN (1)
  • LL_APB1_GRP1_PERIPH_DBGMCU
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM2 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM1 (1)
Note:
Peripheral marked with (1) are not available all devices
Return values:
None

Definition at line 884 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APBENR1 TIM2EN LL_APB1_GRP1_EnableClock
APBENR1 TIM3EN LL_APB1_GRP1_EnableClock
APBENR1 TIM4EN LL_APB1_GRP1_EnableClock
APBENR1 TIM6EN LL_APB1_GRP1_EnableClock
APBENR1 TIM7EN LL_APB1_GRP1_EnableClock
APBENR1 RTCAPBEN LL_APB1_GRP1_EnableClock
APBENR1 WWDGEN LL_APB1_GRP1_EnableClock
APBENR1 SPI2EN LL_APB1_GRP1_EnableClock
APBENR1 SPI3EN LL_APB1_GRP1_EnableClock
APBENR1 USART2EN LL_APB1_GRP1_EnableClock
APBENR1 USART3EN LL_APB1_GRP1_EnableClock
APBENR1 USART4EN LL_APB1_GRP1_EnableClock
APBENR1 USART5EN LL_APB1_GRP1_EnableClock
APBENR1 USART6EN LL_APB1_GRP1_EnableClock
APBENR1 LPUART1EN LL_APB1_GRP1_EnableClock
APBENR1 LPUART2EN LL_APB1_GRP1_EnableClock
APBENR1 I2C1EN LL_APB1_GRP1_EnableClock
APBENR1 I2C2EN LL_APB1_GRP1_EnableClock
APBENR1 I2C3EN LL_APB1_GRP1_EnableClock
APBENR1 CECEN LL_APB1_GRP1_EnableClock
APBENR1 UCPD1EN LL_APB1_GRP1_EnableClock
APBENR1 UCPD2EN LL_APB1_GRP1_EnableClock
APBENR1 USBEN LL_APB1_GRP1_EnableClock
APBENR1 FDCANEN LL_APB1_GRP1_EnableClock
APBENR1 DBGEN LL_APB1_GRP1_EnableClock
APBENR1 PWREN LL_APB1_GRP1_EnableClock
APBENR1 DAC1EN LL_APB1_GRP1_EnableClock
APBENR1 LPTIM2EN LL_APB1_GRP1_EnableClock
APBENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2 (1)
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (1)
  • LL_APB1_GRP1_PERIPH_TIM6 (1)
  • LL_APB1_GRP1_PERIPH_TIM7 (1)
  • LL_APB1_GRP1_PERIPH_RTC
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3 (1)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (1)
  • LL_APB1_GRP1_PERIPH_USART4 (1)
  • LL_APB1_GRP1_PERIPH_USART5 (1)
  • LL_APB1_GRP1_PERIPH_USART6 (1)
  • LL_APB1_GRP1_PERIPH_LPUART1 (1)
  • LL_APB1_GRP1_PERIPH_LPUART2 (1)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3 (1)
  • LL_APB1_GRP1_PERIPH_CEC (1)
  • LL_APB1_GRP1_PERIPH_UCPD1 (1)
  • LL_APB1_GRP1_PERIPH_UCPD2 (1)
  • LL_APB1_GRP1_PERIPH_USB (1)
  • LL_APB1_GRP1_PERIPH_FDCAN (1)
  • LL_APB1_GRP1_PERIPH_DBGMCU
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM2 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM1 (1)
Note:
Peripheral marked with (1) are not available all devices
Return values:
None

Definition at line 467 of file stm32g0xx_ll_bus.h.

Referenced by LL_UCPD_Init().

__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APBSMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 USART4SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 USART5SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 USART6SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 LPUART1SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 LPUART2SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 CECSMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 UCPD1SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 UCPD2SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 DBGSMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_EnableClockStopSleep
APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2 (1)
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (1)
  • LL_APB1_GRP1_PERIPH_TIM6 (1)
  • LL_APB1_GRP1_PERIPH_TIM7 (1)
  • LL_APB1_GRP1_PERIPH_RTC
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3 (1)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (1)
  • LL_APB1_GRP1_PERIPH_USART4 (1)
  • LL_APB1_GRP1_PERIPH_USART5 (1)
  • LL_APB1_GRP1_PERIPH_USART6 (1)
  • LL_APB1_GRP1_PERIPH_LPUART1 (1)
  • LL_APB1_GRP1_PERIPH_LPUART2 (1)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3 (1)
  • LL_APB1_GRP1_PERIPH_CEC (1)
  • LL_APB1_GRP1_PERIPH_UCPD1 (1)
  • LL_APB1_GRP1_PERIPH_UCPD2 (1)
  • LL_APB1_GRP1_PERIPH_USB (1)
  • LL_APB1_GRP1_PERIPH_FDCAN (1)
  • LL_APB1_GRP1_PERIPH_DBGMCU
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM2 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM1 (1)
Note:
Peripheral marked with (1) are not available all devices
Return values:
None

Definition at line 811 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APBRSTR1 TIM2RST LL_APB1_GRP1_ForceReset
APBRSTR1 TIM3RST LL_APB1_GRP1_ForceReset
APBRSTR1 TIM4RST LL_APB1_GRP1_ForceReset
APBRSTR1 TIM6RST LL_APB1_GRP1_ForceReset
APBRSTR1 TIM7RST LL_APB1_GRP1_ForceReset
APBRSTR1 RTCRST LL_APB1_GRP1_ForceReset
APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset
APBRSTR1 SPI3RST LL_APB1_GRP1_ForceReset
APBRSTR1 USART2RST LL_APB1_GRP1_ForceReset
APBRSTR1 USART3RST LL_APB1_GRP1_ForceReset
APBRSTR1 USART4RST LL_APB1_GRP1_ForceReset
APBRSTR1 USART5RST LL_APB1_GRP1_ForceReset
APBRSTR1 USART6RST LL_APB1_GRP1_ForceReset
APBRSTR1 LPUART1RST LL_APB1_GRP1_ForceReset
APBRSTR1 LPUART2RST LL_APB1_GRP1_ForceReset
APBRSTR1 I2C1RST LL_APB1_GRP1_ForceReset
APBRSTR1 I2C2RST LL_APB1_GRP1_ForceReset
APBRSTR1 I2C3RST LL_APB1_GRP1_ForceReset
APBRSTR1 CECRST LL_APB1_GRP1_ForceReset
APBRSTR1 UCPD1RST LL_APB1_GRP1_ForceReset
APBRSTR1 UCPD2RST LL_APB1_GRP1_ForceReset
APBRSTR1 USBRST LL_APB1_GRP1_ForceReset
APBRSTR1 FDCANRST LL_APB1_GRP1_ForceReset
APBRSTR1 DBGRST LL_APB1_GRP1_ForceReset
APBRSTR1 PWRRST LL_APB1_GRP1_ForceReset
APBRSTR1 DAC1RST LL_APB1_GRP1_ForceReset
APBRSTR1 LPTIM2RST LL_APB1_GRP1_ForceReset
APBRSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2 (1)
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (1)
  • LL_APB1_GRP1_PERIPH_TIM6 (1)
  • LL_APB1_GRP1_PERIPH_TIM7 (1)
  • LL_APB1_GRP1_PERIPH_RTC
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3 (1)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (1)
  • LL_APB1_GRP1_PERIPH_USART4 (1)
  • LL_APB1_GRP1_PERIPH_USART5 (1)
  • LL_APB1_GRP1_PERIPH_USART6 (1)
  • LL_APB1_GRP1_PERIPH_LPUART1 (1)
  • LL_APB1_GRP1_PERIPH_LPUART2 (1)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3 (1)
  • LL_APB1_GRP1_PERIPH_CEC (1)
  • LL_APB1_GRP1_PERIPH_UCPD1 (1)
  • LL_APB1_GRP1_PERIPH_UCPD2 (1)
  • LL_APB1_GRP1_PERIPH_USB (1)
  • LL_APB1_GRP1_PERIPH_FDCAN (1)
  • LL_APB1_GRP1_PERIPH_DBGMCU
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM2 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM1 (1)
Note:
Peripheral marked with (1) are not available all devices
Return values:
None

Definition at line 676 of file stm32g0xx_ll_bus.h.

Referenced by LL_CRS_DeInit(), LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_LPUART_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), LL_UCPD_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APBENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock
APBENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock
APBENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock
APBENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock
APBENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock
APBENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock
APBENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock
APBENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock
APBENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock
APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock
APBENR1 USART3EN LL_APB1_GRP1_IsEnabledClock
APBENR1 USART4EN LL_APB1_GRP1_IsEnabledClock
APBENR1 USART5EN LL_APB1_GRP1_IsEnabledClock
APBENR1 USART6EN LL_APB1_GRP1_IsEnabledClock
APBENR1 LPUART1EN LL_APB1_GRP1_IsEnabledClock
APBENR1 LPUART2EN LL_APB1_GRP1_IsEnabledClock
APBENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock
APBENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock
APBENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock
APBENR1 CECEN LL_APB1_GRP1_IsEnabledClock
APBENR1 UCPD1EN LL_APB1_GRP1_IsEnabledClock
APBENR1 UCPD2EN LL_APB1_GRP1_IsEnabledClock
APBENR1 USBEN LL_APB1_GRP1_IsEnabledClock
APBENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock
APBENR1 DBGEN LL_APB1_GRP1_IsEnabledClock
APBENR1 PWREN LL_APB1_GRP1_IsEnabledClock
APBENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock
APBENR1 LPTIM2EN LL_APB1_GRP1_IsEnabledClock
APBENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2 (1)
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (1)
  • LL_APB1_GRP1_PERIPH_TIM6 (1)
  • LL_APB1_GRP1_PERIPH_TIM7 (1)
  • LL_APB1_GRP1_PERIPH_RTC
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3 (1)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (1)
  • LL_APB1_GRP1_PERIPH_USART4 (1)
  • LL_APB1_GRP1_PERIPH_USART5 (1)
  • LL_APB1_GRP1_PERIPH_USART6 (1)
  • LL_APB1_GRP1_PERIPH_LPUART1 (1)
  • LL_APB1_GRP1_PERIPH_LPUART2 (1)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3 (1)
  • LL_APB1_GRP1_PERIPH_CEC (1)
  • LL_APB1_GRP1_PERIPH_UCPD1 (1)
  • LL_APB1_GRP1_PERIPH_UCPD2 (1)
  • LL_APB1_GRP1_PERIPH_USB (1)
  • LL_APB1_GRP1_PERIPH_FDCAN (1)
  • LL_APB1_GRP1_PERIPH_DBGMCU
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM2 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM1 (1)
Note:
Peripheral marked with (1) are not available all devices
Return values:
State of Periphs (1 or 0).

Definition at line 540 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APBRSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 RTCRST LL_APB1_GRP1_ReleaseReset
APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 USART2RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 USART3RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 USART4RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 USART5RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 USART6RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 LPUART1RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 LPUART2RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 CECRST LL_APB1_GRP1_ReleaseReset
APBRSTR1 UCPD1RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 UCPD2RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 USBRST LL_APB1_GRP1_ReleaseReset
APBRSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset
APBRSTR1 DBGRST LL_APB1_GRP1_ReleaseReset
APBRSTR1 PWRRST LL_APB1_GRP1_ReleaseReset
APBRSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 LPTIM2RST LL_APB1_GRP1_ReleaseReset
APBRSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2 (1)
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (1)
  • LL_APB1_GRP1_PERIPH_TIM6 (1)
  • LL_APB1_GRP1_PERIPH_TIM7 (1)
  • LL_APB1_GRP1_PERIPH_RTC
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_SPI3 (1)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (1)
  • LL_APB1_GRP1_PERIPH_USART4 (1)
  • LL_APB1_GRP1_PERIPH_USART5 (1)
  • LL_APB1_GRP1_PERIPH_USART6 (1)
  • LL_APB1_GRP1_PERIPH_LPUART1 (1)
  • LL_APB1_GRP1_PERIPH_LPUART2 (1)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2
  • LL_APB1_GRP1_PERIPH_I2C3 (1)
  • LL_APB1_GRP1_PERIPH_CEC (1)
  • LL_APB1_GRP1_PERIPH_UCPD1 (1)
  • LL_APB1_GRP1_PERIPH_UCPD2 (1)
  • LL_APB1_GRP1_PERIPH_USB (1)
  • LL_APB1_GRP1_PERIPH_FDCAN (1)
  • LL_APB1_GRP1_PERIPH_DBGMCU
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM2 (1)
  • LL_APB1_GRP1_PERIPH_LPTIM1 (1)
Note:
Peripheral marked with (1) are not available all devices
Return values:
None

Definition at line 742 of file stm32g0xx_ll_bus.h.

Referenced by LL_CRS_DeInit(), LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_LPUART_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), LL_UCPD_DeInit(), and LL_USART_DeInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB2

Functions
APB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB2 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_APB2_GRP1_DisableClock ( uint32_t Periphs )

Disable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APBENR2 SYSCFGEN LL_APB2_GRP1_DisableClock
APBENR2 TIM1EN LL_APB2_GRP1_DisableClock
APBENR2 SPI1EN LL_APB2_GRP1_DisableClock
APBENR2 USART1EN LL_APB2_GRP1_DisableClock
APBENR2 TIM14EN LL_APB2_GRP1_DisableClock
APBENR2 TIM15EN LL_APB2_GRP1_DisableClock
APBENR2 TIM16EN LL_APB2_GRP1_DisableClock
APBENR2 TIM17EN LL_APB2_GRP1_DisableClock
APBENR2 ADCEN LL_APB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM14
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_ADC
Note:
(*) peripheral not available on all devices
Return values:
None

Definition at line 983 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable APB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep
APBSMENR2 TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
APBSMENR2 SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep
APBSMENR2 USART1SMEN LL_APB2_GRP1_DisableClockStopSleep
APBSMENR2 TIM14SMEN LL_APB2_GRP1_DisableClockStopSleep
APBSMENR2 TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep
APBSMENR2 TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep
APBSMENR2 TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep
APBSMENR2 ADCSMEN LL_APB2_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM14
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_ADC
Note:
(*) peripheral not available on all devices
Return values:
None

Definition at line 1105 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClock ( uint32_t Periphs )

Enable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APBENR2 SYSCFGEN LL_APB2_GRP1_EnableClock
APBENR2 TIM1EN LL_APB2_GRP1_EnableClock
APBENR2 SPI1EN LL_APB2_GRP1_EnableClock
APBENR2 USART1EN LL_APB2_GRP1_EnableClock
APBENR2 TIM14EN LL_APB2_GRP1_EnableClock
APBENR2 TIM15EN LL_APB2_GRP1_EnableClock
APBENR2 TIM16EN LL_APB2_GRP1_EnableClock
APBENR2 TIM17EN LL_APB2_GRP1_EnableClock
APBENR2 ADCEN LL_APB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM14
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_ADC
Note:
(*) peripheral not available on all devices
Return values:
None

Definition at line 921 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable APB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep
APBSMENR2 TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
APBSMENR2 SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep
APBSMENR2 USART1SMEN LL_APB2_GRP1_EnableClockStopSleep
APBSMENR2 TIM14SMEN LL_APB2_GRP1_EnableClockStopSleep
APBSMENR2 TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep
APBSMENR2 TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep
APBSMENR2 TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep
APBSMENR2 ADCSMEN LL_APB2_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM14
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_ADC
Note:
(*) peripheral not available on all devices
Return values:
None

Definition at line 1072 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ForceReset ( uint32_t Periphs )

Force APB2 peripherals reset.

Reference Manual to LL API cross reference:
APBRSTR2 SYSCFGRST LL_APB2_GRP1_ForceReset
APBRSTR2 TIM1RST LL_APB2_GRP1_ForceReset
APBRSTR2 SPI1RST LL_APB2_GRP1_ForceReset
APBRSTR2 USART1RST LL_APB2_GRP1_ForceReset
APBRSTR2 TIM14RST LL_APB2_GRP1_ForceReset
APBRSTR2 TIM15RST LL_APB2_GRP1_ForceReset
APBRSTR2 TIM16RST LL_APB2_GRP1_ForceReset
APBRSTR2 TIM17RST LL_APB2_GRP1_ForceReset
APBRSTR2 ADCRST LL_APB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM14
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_ADC
Note:
(*) peripheral not available on all devices
Return values:
None

Definition at line 1013 of file stm32g0xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APBENR2 SYSCFGEN LL_APB2_GRP1_IsEnabledClock
APBENR2 TIM1EN LL_APB2_GRP1_IsEnabledClock
APBENR2 SPI1EN LL_APB2_GRP1_IsEnabledClock
APBENR2 USART1EN LL_APB2_GRP1_IsEnabledClock
APBENR2 TIM14EN LL_APB2_GRP1_IsEnabledClock
APBENR2 TIM15EN LL_APB2_GRP1_IsEnabledClock
APBENR2 TIM16EN LL_APB2_GRP1_IsEnabledClock
APBENR2 TIM17EN LL_APB2_GRP1_IsEnabledClock
APBENR2 ADCEN LL_APB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM14
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_ADC
Note:
(*) peripheral not available on all devices
Return values:
State of Periphs (1 or 0).

Definition at line 954 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB2 peripherals reset.

Reference Manual to LL API cross reference:
APBRSTR2 SYSCFGRST LL_APB2_GRP1_ReleaseReset
APBRSTR2 TIM1RST LL_APB2_GRP1_ReleaseReset
APBRSTR2 SPI1RST LL_APB2_GRP1_ReleaseReset
APBRSTR2 USART1RST LL_APB2_GRP1_ReleaseReset
APBRSTR2 TIM14RST LL_APB2_GRP1_ReleaseReset
APBRSTR2 TIM15RST LL_APB2_GRP1_ReleaseReset
APBRSTR2 TIM16RST LL_APB2_GRP1_ReleaseReset
APBRSTR2 TIM17RST LL_APB2_GRP1_ReleaseReset
APBRSTR2 ADCRST LL_APB2_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM14
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_ADC
Note:
(*) peripheral not available on all devices
Return values:
None

Definition at line 1043 of file stm32g0xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IOP

Functions
IOP
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_IOP_GRP1_EnableClock (uint32_t Periphs)
Enable IOP peripherals clock.
__STATIC_INLINE uint32_t | LL_IOP_GRP1_IsEnabledClock (uint32_t Periphs)
Check if IOP peripheral clock is enabled or not.
__STATIC_INLINE void | LL_IOP_GRP1_DisableClock (uint32_t Periphs)
Disable IOP peripherals clock.
__STATIC_INLINE void | LL_IOP_GRP1_ForceReset (uint32_t Periphs)
Disable IOP peripherals clock.
__STATIC_INLINE void | LL_IOP_GRP1_ReleaseReset (uint32_t Periphs)
Release IOP peripherals reset.
__STATIC_INLINE void | LL_IOP_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable IOP peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_IOP_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable IOP peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_IOP_GRP1_DisableClock ( uint32_t Periphs )

Disable IOP peripherals clock.

Reference Manual to LL API cross reference:
IOPENR GPIOAEN LL_IOP_GRP1_DisableClock
IOPENR GPIOBEN LL_IOP_GRP1_DisableClock
IOPENR GPIOCEN LL_IOP_GRP1_DisableClock
IOPENR GPIODEN LL_IOP_GRP1_DisableClock
IOPENR GPIOEEN LL_IOP_GRP1_DisableClock
IOPENR GPIOFEN LL_IOP_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_IOP_GRP1_PERIPH_GPIOA
  • LL_IOP_GRP1_PERIPH_GPIOB
  • LL_IOP_GRP1_PERIPH_GPIOC
  • LL_IOP_GRP1_PERIPH_GPIOD
  • LL_IOP_GRP1_PERIPH_GPIOE
  • LL_IOP_GRP1_PERIPH_GPIOF
Return values:
None

Definition at line 1183 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable IOP peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
IOPSMENR GPIOASMEN LL_IOP_GRP1_DisableClockStopSleep
IOPSMENR GPIOBSMEN LL_IOP_GRP1_DisableClockStopSleep
IOPSMENR GPIOCSMEN LL_IOP_GRP1_DisableClockStopSleep
IOPSMENR GPIODSMEN LL_IOP_GRP1_DisableClockStopSleep
IOPSMENR GPIOESMEN LL_IOP_GRP1_DisableClockStopSleep
IOPSMENR GPIOFSMEN LL_IOP_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_IOP_GRP1_PERIPH_GPIOA
  • LL_IOP_GRP1_PERIPH_GPIOB
  • LL_IOP_GRP1_PERIPH_GPIOC
  • LL_IOP_GRP1_PERIPH_GPIOD
  • LL_IOP_GRP1_PERIPH_GPIOE
  • LL_IOP_GRP1_PERIPH_GPIOF
Return values:
None

Definition at line 1277 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_IOP_GRP1_EnableClock ( uint32_t Periphs )

Enable IOP peripherals clock.

Reference Manual to LL API cross reference:
IOPENR GPIOAEN LL_IOP_GRP1_EnableClock
IOPENR GPIOBEN LL_IOP_GRP1_EnableClock
IOPENR GPIOCEN LL_IOP_GRP1_EnableClock
IOPENR GPIODEN LL_IOP_GRP1_EnableClock
IOPENR GPIOEEN LL_IOP_GRP1_EnableClock
IOPENR GPIOFEN LL_IOP_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_IOP_GRP1_PERIPH_GPIOA
  • LL_IOP_GRP1_PERIPH_GPIOB
  • LL_IOP_GRP1_PERIPH_GPIOC
  • LL_IOP_GRP1_PERIPH_GPIOD
  • LL_IOP_GRP1_PERIPH_GPIOE
  • LL_IOP_GRP1_PERIPH_GPIOF
Return values:
None

Definition at line 1135 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable IOP peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
IOPSMENR GPIOASMEN LL_IOP_GRP1_EnableClockStopSleep
IOPSMENR GPIOBSMEN LL_IOP_GRP1_EnableClockStopSleep
IOPSMENR GPIOCSMEN LL_IOP_GRP1_EnableClockStopSleep
IOPSMENR GPIODSMEN LL_IOP_GRP1_EnableClockStopSleep
IOPSMENR GPIOESMEN LL_IOP_GRP1_EnableClockStopSleep
IOPSMENR GPIOFSMEN LL_IOP_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_IOP_GRP1_PERIPH_GPIOA
  • LL_IOP_GRP1_PERIPH_GPIOB
  • LL_IOP_GRP1_PERIPH_GPIOC
  • LL_IOP_GRP1_PERIPH_GPIOD
  • LL_IOP_GRP1_PERIPH_GPIOE
  • LL_IOP_GRP1_PERIPH_GPIOF
Return values:
None

Definition at line 1251 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_IOP_GRP1_ForceReset ( uint32_t Periphs )

Disable IOP peripherals clock.

Reference Manual to LL API cross reference:
IOPRSTR GPIOARST LL_IOP_GRP1_ForceReset
IOPRSTR GPIOBRST LL_IOP_GRP1_ForceReset
IOPRSTR GPIOCRST LL_IOP_GRP1_ForceReset
IOPRSTR GPIODRST LL_IOP_GRP1_ForceReset
IOPRSTR GPIOERST LL_IOP_GRP1_ForceReset
IOPRSTR GPIOFRST LL_IOP_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_IOP_GRP1_PERIPH_ALL
  • LL_IOP_GRP1_PERIPH_GPIOA
  • LL_IOP_GRP1_PERIPH_GPIOB
  • LL_IOP_GRP1_PERIPH_GPIOC
  • LL_IOP_GRP1_PERIPH_GPIOD
  • LL_IOP_GRP1_PERIPH_GPIOE
  • LL_IOP_GRP1_PERIPH_GPIOF
Return values:
None

Definition at line 1206 of file stm32g0xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if IOP peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock
IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock
IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock
IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock
IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock
IOPENR GPIOFEN LL_IOP_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_IOP_GRP1_PERIPH_GPIOA
  • LL_IOP_GRP1_PERIPH_GPIOB
  • LL_IOP_GRP1_PERIPH_GPIOC
  • LL_IOP_GRP1_PERIPH_GPIOD
  • LL_IOP_GRP1_PERIPH_GPIOE
  • LL_IOP_GRP1_PERIPH_GPIOF
Return values:
State of Periphs (1 or 0).

Definition at line 1161 of file stm32g0xx_ll_bus.h.

__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset ( uint32_t Periphs )

Release IOP peripherals reset.

Reference Manual to LL API cross reference:
IOPRSTR GPIOARST LL_IOP_GRP1_ReleaseReset
IOPRSTR GPIOBRST LL_IOP_GRP1_ReleaseReset
IOPRSTR GPIOCRST LL_IOP_GRP1_ReleaseReset
IOPRSTR GPIODRST LL_IOP_GRP1_ReleaseReset
IOPRSTR GPIOERST LL_IOP_GRP1_ReleaseReset
IOPRSTR GPIOFRST LL_IOP_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_IOP_GRP1_PERIPH_ALL
  • LL_IOP_GRP1_PERIPH_GPIOA
  • LL_IOP_GRP1_PERIPH_GPIOB
  • LL_IOP_GRP1_PERIPH_GPIOC
  • LL_IOP_GRP1_PERIPH_GPIOD
  • LL_IOP_GRP1_PERIPH_GPIOE
  • LL_IOP_GRP1_PERIPH_GPIOF
Return values:
None

Definition at line 1229 of file stm32g0xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Private Constants

Defines
COMP Private Constants
COMP

Defines

#define | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...) defined as reference register */
#define | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) offset vs register of COMP instance odd */
#define | LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
#define | LL_COMP_WINDOWMODE_COMPX_SETTING_MASK (COMP_CSR_WINMODE)
#define | LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK (COMP_CSR_WINOUT)
#define | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK (COMP_CSR_WINOUT << 1UL)
#define | LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW (1UL)
#define | LL_COMP_WINDOWMODE_BITOFFSET_POS (11UL) /* Value equivalent to POSITION_VAL(COMP_CSR_WINMODE) */
#define | LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

Definition at line 63 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_ReadOutputLevel().

#define LL_COMP_WINDOWMODE_BITOFFSET_POS (11UL) /* Value equivalent to POSITION_VAL(COMP_CSR_WINMODE) */

Definition at line 62 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_GetCommonWindowMode().

#define LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) offset vs register of COMP instance odd */

Definition at line 54 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_GetCommonWindowMode(), and LL_COMP_GetCommonWindowOutput().

#define LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...) defined as reference register */

Definition at line 53 of file stm32g0xx_ll_comp.h.

#define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)

Definition at line 55 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowMode(), and LL_COMP_SetCommonWindowOutput().

#define LL_COMP_WINDOWMODE_COMPX_SETTING_MASK (COMP_CSR_WINMODE)

Definition at line 56 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowMode().

#define LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW (1UL)

Definition at line 59 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowOutput().

#define LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK (COMP_CSR_WINOUT << 1UL)

Definition at line 58 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowOutput().

#define LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK (COMP_CSR_WINOUT)

Definition at line 57 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowOutput().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Private Macros

Defines
COMP Private Macros
COMP

Defines

#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)
#define | __COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __COMP_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 82 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowMode(), and LL_COMP_SetCommonWindowOutput().

#define IS_LL_COMP_INPUT_HYSTERESIS ( __INPUT_HYSTERESIS__ )
Value:
(   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
  )

Definition at line 82 of file stm32g0xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
  )

Definition at line 70 of file stm32g0xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                             \
  )

Definition at line 60 of file stm32g0xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE ( __OUTPUT_BLANKING_SOURCE__ )
Value:
(   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC4)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2)          \
  )

Definition at line 94 of file stm32g0xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
  )

Definition at line 89 of file stm32g0xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_POWER_MODE ( __POWER_MODE__ )
Value:
(   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
  )

Definition at line 51 of file stm32g0xx_ll_comp.c.

Referenced by LL_COMP_Init().

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STM32G0C1xx HAL User Manual: LL_COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_COMP_InitTypeDef Struct Reference
COMP Exported Init structure

Structure definition of some features of COMP instance. More...

#include <stm32g0xx_ll_comp.h>

Data Fields

uint32_t | PowerMode
uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | InputHysteresis
uint32_t | OutputPolarity
uint32_t | OutputBlankingSource

Detailed Description

Structure definition of some features of COMP instance.

Definition at line 98 of file stm32g0xx_ll_comp.h.

Field Documentation

uint32_t LL_COMP_InitTypeDef::InputHysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of Comparator input - Hysteresis

This feature can be modified afterwards using unitary function LL_COMP_SetInputHysteresis().

Definition at line 115 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of Comparator inputs - Input minus (input inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputMinus().

Definition at line 110 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of Comparator inputs - Input plus (input non-inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputPlus().

Definition at line 105 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputBlankingSource

Set comparator blanking source. This parameter can be a value of Comparator output - Blanking source

This feature can be modified afterwards using unitary function LL_COMP_SetOutputBlankingSource().

Definition at line 125 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputPolarity

Set comparator output polarity. This parameter can be a value of Comparator output - Output polarity

This feature can be modified afterwards using unitary function LL_COMP_SetOutputPolarity().

Definition at line 120 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::PowerMode

Set comparator operating mode to adjust power and speed. This parameter can be a value of Comparator modes - Power mode

This feature can be modified afterwards using unitary function LL_COMP_SetPowerMode().

Definition at line 100 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_comp.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Comparator common modes - Window mode

Defines
Comparator common modes - Window mode
COMP Exported Constants

Defines

#define | LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
#define | LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)

Define Documentation

#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 146 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowMode().

#define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)

Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). If used from COMP3 instance (when available), comparators instances pair COMP2 and COMP3 have their input plus connected together, the common input is COMP2 input plus (COMP3 input plus is no more accessible).

Definition at line 147 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowMode().

#define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)

Window mode disable: Comparators 1 and 2 are independent

Definition at line 145 of file stm32g0xx_ll_comp.h.

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STM32G0C1xx HAL User Manual: Comparator common modes - Window output

Defines
Comparator common modes - Window output
COMP Exported Constants

Defines

#define | LL_COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL)
#define | LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)
#define | LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
#define | LL_COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)
#define | LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK)

Define Documentation

#define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK)

Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above.

Definition at line 161 of file stm32g0xx_ll_comp.h.

#define LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)

Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.

Definition at line 156 of file stm32g0xx_ll_comp.h.

#define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)

Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.

Definition at line 157 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowOutput().

#define LL_COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)

Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Available only on devices featuring COMP3 instance.

Definition at line 159 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_SetCommonWindowOutput().

#define LL_COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL)

Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. The same way, if both comparators output are high, then monitored signal is below window.

Definition at line 155 of file stm32g0xx_ll_comp.h.

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STM32G0C1xx HAL User Manual: Comparator modes - Power mode

Defines
Comparator modes - Power mode
COMP Exported Constants

Defines

#define | LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)

Define Documentation

#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)

COMP power mode to high speed

Definition at line 169 of file stm32g0xx_ll_comp.h.

#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)

COMP power mode to medium speed

Definition at line 170 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Comparator inputs - Input plus (input non-inverting) selection

Defines
Comparator inputs - Input plus (input non-inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)

Define Documentation

#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)

Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2, pin PB0 for COMP3 (for devices featuring COMP3 instance))

Definition at line 178 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2, pin PC1 for COMP3 (for devices featuring COMP3 instance))

Definition at line 179 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)

Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2, pin PE7 for COMP3 (for devices featuring COMP3 instance))

Definition at line 180 of file stm32g0xx_ll_comp.h.

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STM32G0C1xx HAL User Manual: Comparator inputs - Input minus (input inverting) selection

Defines
Comparator inputs - Input minus (input inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_INMSEL_3 )

Define Documentation

#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0)

Comparator input minus connected to 1/2 VrefInt

Definition at line 189 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL)

Comparator input minus connected to 1/4 VrefInt

Definition at line 188 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 )

Comparator input minus connected to 3/4 VrefInt

Definition at line 190 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)

Definition at line 192 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)

Definition at line 193 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )

Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2, pin PB2 for COMP3 (for devices featuring COMP3 instance))

Definition at line 194 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2, pin PC0 for COMP3 (for devices featuring COMP3 instance))

Definition at line 195 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_INMSEL_3 )

Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2, pin PE8 for COMP3 (for devices featuring COMP3 instance))

Definition at line 196 of file stm32g0xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to VrefInt

Definition at line 191 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

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STM32G0C1xx HAL User Manual: Comparator input - Hysteresis

Defines
Comparator input - Hysteresis
COMP Exported Constants

Defines

#define | LL_COMP_HYSTERESIS_NONE (0x00000000UL)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Define Documentation

#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level high

Definition at line 207 of file stm32g0xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)

Hysteresis level low

Definition at line 205 of file stm32g0xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )

Hysteresis level medium

Definition at line 206 of file stm32g0xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_NONE (0x00000000UL)

No hysteresis

Definition at line 204 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Comparator output - Output polarity

Defines
Comparator output - Output polarity
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

Define Documentation

#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input

Definition at line 216 of file stm32g0xx_ll_comp.h.

#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)

COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input

Definition at line 215 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Comparator output - Blanking source

Defines
Comparator output - Blanking source
COMP Exported Constants

Defines

#define | LL_COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | LL_COMP_BLANKINGSRC_TIM1_OC4 (COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_2)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKING_3)
#define | LL_COMP_BLANKINGSRC_TIM15_OC2 (COMP_CSR_BLANKING_4)

Define Documentation

#define LL_COMP_BLANKINGSRC_NONE (0x00000000UL)

Comparator output without blanking

Definition at line 224 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_BLANKINGSRC_TIM15_OC2 (COMP_CSR_BLANKING_4)

Comparator output blanking source TIM15 OC2 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 230 of file stm32g0xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC4 (COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC4 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 226 of file stm32g0xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_1)

Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 227 of file stm32g0xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_2)

Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 228 of file stm32g0xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKING_3)

Comparator output blanking source TIM3 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available))

Definition at line 229 of file stm32g0xx_ll_comp.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Comparator output - Output level

Defines
Comparator output - Output level
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Comparator output level high (if the polarity is not inverted, otherwise to be complemented)

Definition at line 239 of file stm32g0xx_ll_comp.h.

#define LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)

Comparator output level low (if the polarity is not inverted, otherwise to be complemented)

Definition at line 238 of file stm32g0xx_ll_comp.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Definitions of COMP hardware constraints delays

Defines
Definitions of COMP hardware constraints delays
COMP Exported Constants

Defines

#define | LL_COMP_DELAY_STARTUP_US ( 80UL)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)

Detailed Description

Note:
Only COMP peripheral HW delays are defined in COMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_COMP_DELAY_STARTUP_US ( 80UL)

Delay for COMP startup time

Definition at line 257 of file stm32g0xx_ll_comp.h.

#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)

Delay for COMP voltage scaler stabilization time

Definition at line 265 of file stm32g0xx_ll_comp.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
COMP Exported Macros

Defines

#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in COMP register.

Define Documentation

#define LL_COMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 298 of file stm32g0xx_ll_comp.h.

#define LL_COMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 290 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_DeInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP helper macro

Defines
COMP helper macro
COMP Exported Macros

Defines

#define __LL_COMP_COMMON_INSTANCE(__COMPx__)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Define Documentation

#define __LL_COMP_COMMON_INSTANCE ( __COMPx__ )
Value:
((((__COMPx__) == COMP3))                                                    \
    ? (                                                                        \
       (COMP23_COMMON)                                                         \
      )                                                                        \
      :                                                                        \
      (                                                                        \
       (COMP12_COMMON)                                                         \
      )                                                                        \
  )

Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Note:
COMP common register instance can be used to set parameters common to several COMP instances. Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
__COMPx__ COMP instance
Return values:
COMP common instance or value "0" if there is no COMP common instance.

Definition at line 317 of file stm32g0xx_ll_comp.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of COMP hierarchical scope: common to several COMP instances

Functions
Configuration of COMP hierarchical scope: common to several COMP instances
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).
__STATIC_INLINE void | LL_COMP_SetCommonWindowOutput (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput)
Set window output of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowOutput (COMP_Common_TypeDef *COMPxy_COMMON)
Get window output of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode ( COMP_Common_TypeDef * COMPxy_COMMON )

Get window mode of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WINMODE LL_COMP_GetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
  • LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1)(2)
(1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON (2) Parameter specificity on devices STM32G0B1xx and STM32G0C1xx: only parameter that can be used only with comparator common instance COMP23_COMMON

Definition at line 412 of file stm32g0xx_ll_comp.h.

References LL_COMP_WINDOWMODE_BITOFFSET_POS, and LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput ( COMP_Common_TypeDef * COMPxy_COMMON )

Get window output of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WINMODE LL_COMP_GetCommonWindowOutput
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_COMP_WINDOWOUTPUT_EACH_COMP
  • LL_COMP_WINDOWOUTPUT_COMP1 (1)
  • LL_COMP_WINDOWOUTPUT_COMP2 (1)
  • LL_COMP_WINDOWOUTPUT_COMP3 (2)
  • LL_COMP_WINDOWOUTPUT_BOTH
(1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON (2) Parameter available only on devices STM32G0B1xx and STM32G0C1xx, must be used with comparator common instance COMP23_COMMON

Definition at line 518 of file stm32g0xx_ll_comp.h.

References LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK.

__STATIC_INLINE void LL_COMP_SetCommonWindowMode | ( | COMP_Common_TypeDef * | COMPxy_COMMON,
 |  | uint32_t | WindowMode
 | ) |  |

Set window mode of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WINMODE LL_COMP_SetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
WindowMode This parameter can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
  • LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1)(2)
(1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON (2) Parameter specificity on devices STM32G0B1xx and STM32G0C1xx: only parameter that can be used only with comparator common instance COMP23_COMMON
Return values:
None

Definition at line 364 of file stm32g0xx_ll_comp.h.

References __COMP_PTR_REG_OFFSET, LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON, LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON, LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK, and LL_COMP_WINDOWMODE_COMPX_SETTING_MASK.

__STATIC_INLINE void LL_COMP_SetCommonWindowOutput | ( | COMP_Common_TypeDef * | COMPxy_COMMON,
 |  | uint32_t | WindowOutput
 | ) |  |

Set window output of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WINOUT LL_COMP_SetCommonWindowOutput
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
WindowOutput This parameter can be one of the following values:
  • LL_COMP_WINDOWOUTPUT_EACH_COMP
  • LL_COMP_WINDOWOUTPUT_COMP1 (1)
  • LL_COMP_WINDOWOUTPUT_COMP2 (1)
  • LL_COMP_WINDOWOUTPUT_COMP3 (2)
  • LL_COMP_WINDOWOUTPUT_BOTH
(1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON (2) Parameter available only on devices STM32G0B1xx and STM32G0C1xx, must be used with comparator common instance COMP23_COMMON
Return values:
None

Definition at line 460 of file stm32g0xx_ll_comp.h.

References __COMP_PTR_REG_OFFSET, LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK, LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW, LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK, LL_COMP_WINDOWOUTPUT_COMP2, LL_COMP_WINDOWOUTPUT_COMP3, and LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of comparator modes

Functions
Configuration of comparator modes
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetPowerMode ( COMP_TypeDef * COMPx )

Get comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CSR PWRMODE LL_COMP_GetPowerMode
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED

Definition at line 579 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetPowerMode | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | PowerMode
 | ) |  |

Set comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CSR PWRMODE LL_COMP_SetPowerMode
Parameters:
COMPx Comparator instance
PowerMode This parameter can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
Return values:
None

Definition at line 566 of file stm32g0xx_ll_comp.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of comparator inputs

Functions
Configuration of comparator inputs
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.

Function Documentation

__STATIC_INLINE void LL_COMP_ConfigInputs | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator inputs minus (inverting) and plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 series, a voltage scaler is used when COMP input is based on VrefInt (VrefInt or subdivision of VrefInt): Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_ConfigInputs
CSR INPSEL LL_COMP_ConfigInputs
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3
Return values:
None

Definition at line 621 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis ( COMP_TypeDef * COMPx )

Get comparator instance hysteresis mode of the minus (inverting) input.

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_GetInputHysteresis
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH

Definition at line 741 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputMinus ( COMP_TypeDef * COMPx )

Get comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_GetInputMinus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3

Definition at line 710 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputPlus ( COMP_TypeDef * COMPx )

Get comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INPSEL LL_COMP_GetInputPlus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3

Definition at line 658 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputHysteresis | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputHysteresis
 | ) |  |

Set comparator instance hysteresis mode of the input minus (inverting input).

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_SetInputHysteresis
Parameters:
COMPx Comparator instance
InputHysteresis This parameter can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH
Return values:
None

Definition at line 726 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputMinus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus
 | ) |  |

Set comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 series, a voltage scaler is used when COMP input is based on VrefInt (VrefInt or subdivision of VrefInt): Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_SetInputMinus
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3
Return values:
None

Definition at line 687 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputPlus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INPSEL LL_COMP_SetInputPlus
Parameters:
COMPx Comparator instance
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3
Return values:
None

Definition at line 641 of file stm32g0xx_ll_comp.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration of comparator output

Functions
Configuration of comparator output
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (COMP_TypeDef *COMPx)
Get comparator instance blanking source.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource ( COMP_TypeDef * COMPx )

Get comparator instance blanking source.

Note:
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR BLANKING LL_COMP_GetOutputBlankingSource
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC4 (1)
  • LL_COMP_BLANKINGSRC_TIM1_OC5 (1)
  • LL_COMP_BLANKINGSRC_TIM2_OC3 (1)
  • LL_COMP_BLANKINGSRC_TIM3_OC3 (1)
  • LL_COMP_BLANKINGSRC_TIM15_OC2 (1)
(1) Parameter availability depending on timer availability on the selected device.

Definition at line 825 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity ( COMP_TypeDef * COMPx )

Get comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR POLARITY LL_COMP_GetOutputPolarity
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED

Definition at line 776 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputBlankingSource | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | BlankingSource
 | ) |  |

Set comparator instance blanking source.

Note:
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CSR BLANKING LL_COMP_SetOutputBlankingSource
Parameters:
COMPx Comparator instance
BlankingSource This parameter can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC4 (1)
  • LL_COMP_BLANKINGSRC_TIM1_OC5 (1)
  • LL_COMP_BLANKINGSRC_TIM2_OC3 (1)
  • LL_COMP_BLANKINGSRC_TIM3_OC3 (1)
  • LL_COMP_BLANKINGSRC_TIM15_OC2 (1)
(1) Parameter availability depending on timer availability on the selected device.
Return values:
None

Definition at line 801 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputPolarity | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | OutputPolarity
 | ) |  |

Set comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR POLARITY LL_COMP_SetOutputPolarity
Parameters:
COMPx Comparator instance
OutputPolarity This parameter can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED
Return values:
None

Definition at line 763 of file stm32g0xx_ll_comp.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Operation on comparator instance

Functions
Operation on comparator instance
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.

Function Documentation

__STATIC_INLINE void LL_COMP_Disable ( COMP_TypeDef * COMPx )

Disable comparator instance.

Reference Manual to LL API cross reference:
CSR EN LL_COMP_Disable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 858 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_Enable ( COMP_TypeDef * COMPx )

Enable comparator instance.

Note:
After enable from off state, comparator requires a delay to reach reach propagation delay specification. Refer to device datasheet, parameter "tSTART".
Reference Manual to LL API cross reference:
CSR EN LL_COMP_Enable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 847 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsEnabled ( COMP_TypeDef * COMPx )

Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)

Reference Manual to LL API cross reference:
CSR EN LL_COMP_IsEnabled
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 870 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsLocked ( COMP_TypeDef * COMPx )

Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_COMP_IsLocked
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 897 of file stm32g0xx_ll_comp.h.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

__STATIC_INLINE void LL_COMP_Lock ( COMP_TypeDef * COMPx )

Lock comparator instance.

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_COMP_Lock
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 883 of file stm32g0xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel ( COMP_TypeDef * COMPx )

Read comparator instance output level.

Note:
The comparator output level depends on the selected polarity (Refer to function LL_COMP_SetOutputPolarity()). If the comparator polarity is not inverted:
  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the comparator polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
Reference Manual to LL API cross reference:
CSR VALUE LL_COMP_ReadOutputLevel
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUT_LEVEL_LOW
  • LL_COMP_OUTPUT_LEVEL_HIGH

Definition at line 922 of file stm32g0xx_ll_comp.h.

References LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS.

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STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
COMP Exported Functions

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_COMP_DeInit ( COMP_TypeDef * COMPx )

De-initialize registers of the selected COMP instance to their default reset values.

Note:
If comparator is locked, de-initialization by software is not possible. The only way to unlock the comparator is a device hardware reset.
Parameters:
COMPx COMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are de-initialized
  • ERROR: COMP registers are not de-initialized

Definition at line 130 of file stm32g0xx_ll_comp.c.

References assert_param, LL_COMP_IsLocked(), and LL_COMP_WriteReg.

ErrorStatus LL_COMP_Init | ( | COMP_TypeDef * | COMPx,
 |  | LL_COMP_InitTypeDef * | COMP_InitStruct
 | ) |  |

Initialize some features of COMP instance.

Note:
This function configures features of the selected COMP instance. Some features are also available at scope COMP common instance (common to several COMP instances). Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
COMPx | COMP instance
COMP_InitStruct | Pointer to a LL_COMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are initialized
  • ERROR: COMP registers are not initialized

Definition at line 167 of file stm32g0xx_ll_comp.c.

References assert_param, LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, IS_LL_COMP_INPUT_HYSTERESIS, IS_LL_COMP_INPUT_MINUS, IS_LL_COMP_INPUT_PLUS, IS_LL_COMP_OUTPUT_BLANKING_SOURCE, IS_LL_COMP_OUTPUT_POLARITY, IS_LL_COMP_POWER_MODE, LL_COMP_IsLocked(), LL_COMP_InitTypeDef::OutputBlankingSource, LL_COMP_InitTypeDef::OutputPolarity, and LL_COMP_InitTypeDef::PowerMode.

void LL_COMP_StructInit ( LL_COMP_InitTypeDef * COMP_InitStruct )

Set each LL_COMP_InitTypeDef field to default value.

Parameters:
COMP_InitStruct Pointer to a LL_COMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 223 of file stm32g0xx_ll_comp.c.

References LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, LL_COMP_BLANKINGSRC_NONE, LL_COMP_HYSTERESIS_NONE, LL_COMP_INPUT_MINUS_VREFINT, LL_COMP_INPUT_PLUS_IO1, LL_COMP_OUTPUTPOL_NONINVERTED, LL_COMP_POWERMODE_MEDIUMSPEED, LL_COMP_InitTypeDef::OutputBlankingSource, LL_COMP_InitTypeDef::OutputPolarity, and LL_COMP_InitTypeDef::PowerMode.

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STM32G0C1xx HAL User Manual: SYSTICK Clock Source

Defines
SYSTICK Clock Source
CORTEX Exported Constants

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

Define Documentation

#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

AHB clock selected as SysTick clock source.

Definition at line 69 of file stm32g0xx_ll_cortex.h.

Referenced by LL_SYSTICK_GetClkSource(), and LL_SYSTICK_SetClkSource().

#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

AHB clock divided by 8 selected as SysTick clock source.

Definition at line 68 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU Control

Defines
MPU Control
CORTEX Exported Constants

Defines

#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk

Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers

Definition at line 80 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Enable NMI and privileged SW access

Definition at line 82 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U

Disable NMI and privileged SW access

Definition at line 79 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk

Enable privileged software access to default memory map

Definition at line 81 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU Region Number

Defines
MPU Region Number
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NUMBER0 0x00U
#define | LL_MPU_REGION_NUMBER1 0x01U
#define | LL_MPU_REGION_NUMBER2 0x02U
#define | LL_MPU_REGION_NUMBER3 0x03U
#define | LL_MPU_REGION_NUMBER4 0x04U
#define | LL_MPU_REGION_NUMBER5 0x05U
#define | LL_MPU_REGION_NUMBER6 0x06U
#define | LL_MPU_REGION_NUMBER7 0x07U

Define Documentation

#define LL_MPU_REGION_NUMBER0 0x00U

REGION Number 0

Definition at line 90 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER1 0x01U

REGION Number 1

Definition at line 91 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER2 0x02U

REGION Number 2

Definition at line 92 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER3 0x03U

REGION Number 3

Definition at line 93 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER4 0x04U

REGION Number 4

Definition at line 94 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER5 0x05U

REGION Number 5

Definition at line 95 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER6 0x06U

REGION Number 6

Definition at line 96 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER7 0x07U

REGION Number 7

Definition at line 97 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU Region Size

Defines
MPU Region Size
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)

Define Documentation

#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)

128KB Size of the MPU protection region

Definition at line 114 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)

128MB Size of the MPU protection region

Definition at line 124 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)

16KB Size of the MPU protection region

Definition at line 111 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)

16MB Size of the MPU protection region

Definition at line 121 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)

1GB Size of the MPU protection region

Definition at line 127 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)

1KB Size of the MPU protection region

Definition at line 107 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)

1MB Size of the MPU protection region

Definition at line 117 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)

256B Size of the MPU protection region

Definition at line 105 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)

256KB Size of the MPU protection region

Definition at line 115 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)

256MB Size of the MPU protection region

Definition at line 125 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)

2GB Size of the MPU protection region

Definition at line 128 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)

2KB Size of the MPU protection region

Definition at line 108 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)

2MB Size of the MPU protection region

Definition at line 118 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)

32KB Size of the MPU protection region

Definition at line 112 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)

32MB Size of the MPU protection region

Definition at line 122 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)

4GB Size of the MPU protection region

Definition at line 129 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)

4KB Size of the MPU protection region

Definition at line 109 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)

4MB Size of the MPU protection region

Definition at line 119 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)

512B Size of the MPU protection region

Definition at line 106 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)

512KB Size of the MPU protection region

Definition at line 116 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)

512MB Size of the MPU protection region

Definition at line 126 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)

64KB Size of the MPU protection region

Definition at line 113 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)

64MB Size of the MPU protection region

Definition at line 123 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)

8KB Size of the MPU protection region

Definition at line 110 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)

8MB Size of the MPU protection region

Definition at line 120 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU Region Privileges

Defines
MPU Region Privileges
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)

Define Documentation

#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)

RW privileged & user (Full access)

Definition at line 140 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)

No access

Definition at line 137 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)

RO privileged (privileged read only)

Definition at line 141 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)

RO privileged & user (read only)

Definition at line 142 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)

RW privileged (privileged access only)

Definition at line 138 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)

RW privileged - RO user (Write in a user program generates a fault)

Definition at line 139 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU TEX Level

Defines
MPU TEX Level
CORTEX Exported Constants

Defines

#define | LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)

Define Documentation

#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)

b000 for TEX bits

Definition at line 150 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)

b001 for TEX bits

Definition at line 151 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)

b010 for TEX bits

Definition at line 152 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)

b100 for TEX bits

Definition at line 153 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU Instruction Access

Defines
MPU Instruction Access
CORTEX Exported Constants

Defines

#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Define Documentation

#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Instruction fetches disabled

Definition at line 162 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U

Instruction fetches enabled

Definition at line 161 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU Shareable Access

Defines
MPU Shareable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U

Not Shareable memory attribute

Definition at line 171 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk

Shareable memory attribute

Definition at line 170 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU Cacheable Access

Defines
MPU Cacheable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk

Cacheable memory attribute

Definition at line 179 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U

Not Cacheable memory attribute

Definition at line 180 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU Bufferable Access

Defines
MPU Bufferable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk

Bufferable memory attribute

Definition at line 188 of file stm32g0xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Not Bufferable memory attribute

Definition at line 189 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: SYSTICK

Functions
SYSTICK
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_SYSTICK_DisableIT ( void )

Disable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_DisableIT
Return values:
None

Definition at line 267 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_EnableIT ( void )

Enable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_EnableIT
Return values:
None

Definition at line 257 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource ( void )

Get the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Return values:
Returned value can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK

Definition at line 247 of file stm32g0xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag ( void )

This function checks if the Systick counter flag is active or not.

Note:
It can be used in timeout function on application side.
Reference Manual to LL API cross reference:
STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Return values:
State of bit (1 or 0).

Definition at line 215 of file stm32g0xx_ll_cortex.h.

Referenced by LL_RTC_EnterInitMode(), and LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT ( void )

Checks if the SYSTICK interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Return values:
State of bit (1 or 0).

Definition at line 277 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_SetClkSource ( uint32_t Source )

Configures the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK
Return values:
None

Definition at line 228 of file stm32g0xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

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STM32G0C1xx HAL User Manual: LOW POWER MODE

Functions
LOW POWER MODE
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Function Documentation

__STATIC_INLINE void LL_LPM_DisableEventOnPend ( void )

Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Return values:
None

Definition at line 354 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_DisableSleepOnExit ( void )

Do not sleep when returning to Thread mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Return values:
None

Definition at line 330 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableDeepSleep ( void )

Processor uses deep sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Return values:
None

Definition at line 306 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableEventOnPend ( void )

Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Return values:
None

Definition at line 342 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleep ( void )

Processor uses sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Return values:
None

Definition at line 295 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleepOnExit ( void )

Configures sleep-on-exit when returning from Handler mode to Thread mode.

Note:
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Return values:
None

Definition at line 319 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MCU INFO

Functions
MCU INFO
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetArchitecture (void)
Get Architecture number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Function Documentation

__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture ( void )

Get Architecture number.

Reference Manual to LL API cross reference:
SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
Return values:
Value should be equal to 0xC for Cortex-M0+ devices

Definition at line 393 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetImplementer ( void )

Get Implementer code.

Reference Manual to LL API cross reference:
SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Return values:
Value should be equal to 0x41 for ARM

Definition at line 373 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetParNo ( void )

Get Part number.

Reference Manual to LL API cross reference:
SCB_CPUID PARTNO LL_CPUID_GetParNo
Return values:
Value should be equal to 0xC60 for Cortex-M0+

Definition at line 403 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetRevision ( void )

Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Reference Manual to LL API cross reference:
SCB_CPUID REVISION LL_CPUID_GetRevision
Return values:
Value between 0 and 255 (0x1: patch 1)

Definition at line 413 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetVariant ( void )

Get Variant number (The r value in the rnpn product revision identifier)

Reference Manual to LL API cross reference:
SCB_CPUID VARIANT LL_CPUID_GetVariant
Return values:
Value between 0 and 255 (0x0: revision 0)

Definition at line 383 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: MPU

Functions
MPU
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Function Documentation

__STATIC_INLINE void LL_MPU_ConfigRegion | ( | uint32_t | Region,
 |  | uint32_t | SubRegionDisable,
 |  | uint32_t | Address,
 |  | uint32_t | Attributes
 | ) |  |

Configure and enable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_ConfigRegion
MPU_RBAR REGION LL_MPU_ConfigRegion
MPU_RBAR ADDR LL_MPU_ConfigRegion
MPU_RASR XN LL_MPU_ConfigRegion
MPU_RASR AP LL_MPU_ConfigRegion
MPU_RASR S LL_MPU_ConfigRegion
MPU_RASR C LL_MPU_ConfigRegion
MPU_RASR B LL_MPU_ConfigRegion
MPU_RASR SIZE LL_MPU_ConfigRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Address | Value of region base address
SubRegionDisable | Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Attributes This parameter can be a combination of the following values:
  • LL_MPU_REGION_SIZE_256B or LL_MPU_REGION_SIZE_512B or LL_MPU_REGION_SIZE_1KB or LL_MPU_REGION_SIZE_2KB or LL_MPU_REGION_SIZE_4KB or LL_MPU_REGION_SIZE_8KB or LL_MPU_REGION_SIZE_16KB or LL_MPU_REGION_SIZE_32KB or LL_MPU_REGION_SIZE_64KB or LL_MPU_REGION_SIZE_128KB or LL_MPU_REGION_SIZE_256KB or LL_MPU_REGION_SIZE_512KB or LL_MPU_REGION_SIZE_1MB or LL_MPU_REGION_SIZE_2MB or LL_MPU_REGION_SIZE_4MB or LL_MPU_REGION_SIZE_8MB or LL_MPU_REGION_SIZE_16MB or LL_MPU_REGION_SIZE_32MB or LL_MPU_REGION_SIZE_64MB or LL_MPU_REGION_SIZE_128MB or LL_MPU_REGION_SIZE_256MB or LL_MPU_REGION_SIZE_512MB or LL_MPU_REGION_SIZE_1GB or LL_MPU_REGION_SIZE_2GB or LL_MPU_REGION_SIZE_4GB
  • LL_MPU_REGION_NO_ACCESS or LL_MPU_REGION_PRIV_RW or LL_MPU_REGION_PRIV_RW_URO or LL_MPU_REGION_FULL_ACCESS or LL_MPU_REGION_PRIV_RO or LL_MPU_REGION_PRIV_RO_URO
  • LL_MPU_TEX_LEVEL0 or LL_MPU_TEX_LEVEL1 or LL_MPU_TEX_LEVEL2 or LL_MPU_TEX_LEVEL4
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE or LL_MPU_INSTRUCTION_ACCESS_DISABLE
  • LL_MPU_ACCESS_SHAREABLE or LL_MPU_ACCESS_NOT_SHAREABLE
  • LL_MPU_ACCESS_CACHEABLE or LL_MPU_ACCESS_NOT_CACHEABLE
  • LL_MPU_ACCESS_BUFFERABLE or LL_MPU_ACCESS_NOT_BUFFERABLE
Return values:
None

Definition at line 530 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Disable ( void )

Disable MPU.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Disable
Return values:
None

Definition at line 452 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_DisableRegion ( uint32_t Region )

Disable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_DisableRegion
MPU_RASR ENABLE LL_MPU_DisableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 555 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Enable ( uint32_t Options )

Enable MPU with input options.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Enable
Parameters:
Options This parameter can be one of the following values:
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
  • LL_MPU_CTRL_HARDFAULT_NMI
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT
  • LL_MPU_CTRL_HFNMI_PRIVDEF
Return values:
None

Definition at line 437 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_EnableRegion ( uint32_t Region )

Enable a MPU region.

Reference Manual to LL API cross reference:
MPU_RASR ENABLE LL_MPU_EnableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 484 of file stm32g0xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_MPU_IsEnabled ( void )

Check if MPU is enabled or not.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 465 of file stm32g0xx_ll_cortex.h.

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STM32G0C1xx HAL User Manual: Polynomial length

Defines
Polynomial length
CRC Exported Constants

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

Define Documentation

#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

16 bits Polynomial size

Definition at line 55 of file stm32g0xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_32B 0x00000000U

32 bits Polynomial size

Definition at line 54 of file stm32g0xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

7 bits Polynomial size

Definition at line 57 of file stm32g0xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

8 bits Polynomial size

Definition at line 56 of file stm32g0xx_ll_crc.h.

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STM32G0C1xx HAL User Manual: Input Data Reverse

Defines
Input Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Define Documentation

#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0

Input Data bit reversal done by byte

Definition at line 66 of file stm32g0xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1

Input Data bit reversal done by half-word

Definition at line 67 of file stm32g0xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U

Input Data bit order not affected

Definition at line 65 of file stm32g0xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Input Data bit reversal done by word

Definition at line 68 of file stm32g0xx_ll_crc.h.

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STM32G0C1xx HAL User Manual: Output Data Reverse

Defines
Output Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Define Documentation

#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Output Data bit reversal done by bit

Definition at line 77 of file stm32g0xx_ll_crc.h.

#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U

Output Data bit order not affected

Definition at line 76 of file stm32g0xx_ll_crc.h.

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STM32G0C1xx HAL User Manual: Default CRC generating polynomial value

Defines
Default CRC generating polynomial value
CRC Exported Constants

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . More...

Defines

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Detailed Description

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Define Documentation

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Default CRC generating polynomial value

Definition at line 87 of file stm32g0xx_ll_crc.h.

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STM32G0C1xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Default CRC computation initialization value

Definition at line 95 of file stm32g0xx_ll_crc.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRC Exported Macros

Defines

#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Define Documentation

#define LL_CRC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 128 of file stm32g0xx_ll_crc.h.

#define LL_CRC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, __VALUE__)

Write a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 120 of file stm32g0xx_ll_crc.h.

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STM32G0C1xx HAL User Manual: CRC Configuration functions

Functions
CRC Configuration functions
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.

Function Documentation

__STATIC_INLINE uint32_t LL_CRC_GetInitialData ( CRC_TypeDef * CRCx )

Return current Initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to read the correct value
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_GetInitialData
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable initial CRC value register

Definition at line 273 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode ( CRC_TypeDef * CRCx )

Return type of reversal for input data bit order.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_GetInputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD

Definition at line 218 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode ( CRC_TypeDef * CRCx )

Return type of reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_GetOutputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT

Definition at line 245 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef ( CRC_TypeDef * CRCx )

Return current Programmable polynomial value.

Note:
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_GetPolynomialCoef
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable Polynomial value register

Definition at line 304 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize ( CRC_TypeDef * CRCx )

Return size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_GetPolynomialSize
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B

Definition at line 187 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit ( CRC_TypeDef * CRCx )

Reset the CRC calculation unit.

Note:
If Programmable Initial CRC value feature is available, also set the Data Register to the value stored in the CRC_INIT register, otherwise, reset Data Register to its default value.
Reference Manual to LL API cross reference:
CR RESET LL_CRC_ResetCRCCalculationUnit
Parameters:
CRCx CRC Instance
Return values:
None

Definition at line 156 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInitialData | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InitCrc
 | ) |  |

Initialize the Programmable initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to write the correct value
LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_SetInitialData
Parameters:
CRCx | CRC Instance
InitCrc | Value to be programmed in Programmable initial CRC value register
Return values:
None

Definition at line 260 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the input data.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_SetInputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD
Return values:
None

Definition at line 203 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_SetOutputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT
Return values:
None

Definition at line 232 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialCoef | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolynomCoef
 | ) |  |

Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).

Note:
LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_SetPolynomialCoef
Parameters:
CRCx | CRC Instance
PolynomCoef | Value to be programmed in Programmable Polynomial value register
Return values:
None

Definition at line 290 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialSize | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolySize
 | ) |  |

Configure size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_SetPolynomialSize
Parameters:
CRCx CRC Instance
PolySize This parameter can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B
Return values:
None

Definition at line 172 of file stm32g0xx_ll_crc.h.

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STM32G0C1xx HAL User Manual: Data_Management

Functions
Data_Management
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.

Function Documentation

__STATIC_INLINE void LL_CRC_FeedData16 | ( | CRC_TypeDef * | CRCx,
 |  | uint16_t | InData
 | ) |  |

Write given 16-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData16
Parameters:
CRCx | CRC Instance
InData | 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 336 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData32 | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Write given 32-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData32
Parameters:
CRCx | CRC Instance
InData | value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 324 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData8 | ( | CRC_TypeDef * | CRCx,
 |  | uint8_t | InData
 | ) |  |

Write given 8-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData8
Parameters:
CRCx | CRC Instance
InData | 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 351 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_Read_IDR ( CRC_TypeDef * CRCx )

Return data stored in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one 32-bit long data.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Read_IDR
Parameters:
CRCx CRC Instance
Return values:
Value stored in CRC_IDR register (General-purpose 32-bit data register).

Definition at line 410 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint16_t LL_CRC_ReadData16 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

16 bits value is returned.

Note:
This function is expected to be used in a 16 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData16
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (16 bits).

Definition at line 374 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_ReadData32 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

32 bits value is returned.

Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData32
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (32 bits).

Definition at line 362 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData7 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

7 bits value is returned.

Note:
This function is expected to be used in a 7 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData7
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (7 bits).

Definition at line 398 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData8 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

8 bits value is returned.

Note:
This function is expected to be used in a 8 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData8
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (8 bits).

Definition at line 386 of file stm32g0xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_Write_IDR | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Store data in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one 32-bit long data.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Write_IDR
Parameters:
CRCx | CRC Instance
InData | value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 423 of file stm32g0xx_ll_crc.h.

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STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Functions

ErrorStatus LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Function Documentation

ErrorStatus LL_CRC_DeInit ( CRC_TypeDef * CRCx )

De-initialize CRC registers (Registers restored to their default values).

Parameters:
CRCx CRC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRC registers are de-initialized
  • ERROR: CRC registers are not de-initialized

Definition at line 62 of file stm32g0xx_ll_crc.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_CRC, and LL_AHB1_GRP1_ReleaseReset().

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STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
CRS Exported Constants

Flags defines which can be used with LL_CRS_ReadReg function. More...

Defines

#define | LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define | LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define | LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define | LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define | LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define | LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define | LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF

Detailed Description

Flags defines which can be used with LL_CRS_ReadReg function.

Define Documentation

#define LL_CRS_ISR_ERRF CRS_ISR_ERRF

Definition at line 57 of file stm32g0xx_ll_crs.h.

#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF

Definition at line 58 of file stm32g0xx_ll_crs.h.

#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR

Definition at line 59 of file stm32g0xx_ll_crs.h.

#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS

Definition at line 60 of file stm32g0xx_ll_crs.h.

#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF

Definition at line 55 of file stm32g0xx_ll_crs.h.

#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF

Definition at line 56 of file stm32g0xx_ll_crs.h.

#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF

Definition at line 61 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
CRS Exported Constants

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions. More...

Defines

#define | LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define | LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define | LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define | LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE

Detailed Description

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions.

Define Documentation

#define LL_CRS_CR_ERRIE CRS_CR_ERRIE

Definition at line 72 of file stm32g0xx_ll_crs.h.

#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE

Definition at line 73 of file stm32g0xx_ll_crs.h.

#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE

Definition at line 70 of file stm32g0xx_ll_crs.h.

#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE

Definition at line 71 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: Synchronization Signal Divider

Defines
Synchronization Signal Divider
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_DIV_1 0x00000000U
#define | LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0
#define | LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1
#define | LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2
#define | LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV

Define Documentation

#define LL_CRS_SYNC_DIV_1 0x00000000U

Synchro Signal not divided (default)

Definition at line 81 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

Definition at line 88 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

Definition at line 85 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

Definition at line 82 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

Definition at line 86 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

Definition at line 83 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

Definition at line 87 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8

Definition at line 84 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: Synchronization Signal Source

Defines
Synchronization Signal Source
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Define Documentation

#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U

Synchro Signal source GPIO

Definition at line 96 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0

Synchro Signal source LSE

Definition at line 97 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Synchro Signal source USB SOF (default)

Definition at line 98 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: Synchronization Signal Polarity

Defines
Synchronization Signal Polarity
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Define Documentation

#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Synchro Active on falling edge

Definition at line 107 of file stm32g0xx_ll_crs.h.

#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U

Synchro Active on rising edge (default)

Definition at line 106 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: Frequency Error Direction

Defines
Frequency Error Direction
CRS Exported Constants

Defines

#define | LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U
#define | LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR

Define Documentation

#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR

Downcounting direction, the actual frequency is below the target

Definition at line 116 of file stm32g0xx_ll_crs.h.

#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U

Upcounting direction, the actual frequency is above the target

Definition at line 115 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: Default Values

Defines
Default Values
CRS Exported Constants

Defines

#define | LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
Reset value of the RELOAD field.
#define | LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
Reset value of Frequency error limit.
#define | LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
Reset value of the HSI48 Calibration field.

Define Documentation

#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U

Reset value of Frequency error limit.

Definition at line 134 of file stm32g0xx_ll_crs.h.

#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U

Reset value of the HSI48 Calibration field.

Note:
The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is specified in the product datasheet. A higher TRIM value corresponds to a higher output frequency.

Definition at line 142 of file stm32g0xx_ll_crs.h.

#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU

Reset value of the RELOAD field.

Note:
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB)

Definition at line 129 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRS Exported Macros

Defines

#define | LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRS register.
#define | LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRS register.

Define Documentation

#define LL_CRS_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRS register.

Parameters:
__INSTANCE__ | CRS Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 175 of file stm32g0xx_ll_crs.h.

#define LL_CRS_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in CRS register.

Parameters:
__INSTANCE__ | CRS Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 167 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: Exported_Macros_Calculate_Reload

Defines
Exported_Macros_Calculate_Reload
CRS Exported Macros

Defines

#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __LL_CRS_CALC_CALCULATE_RELOADVALUE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | (((__FTARGET__) / (__FSYNC__)) - 1U)

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
Reload value (in Hz)

Definition at line 195 of file stm32g0xx_ll_crs.h.

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STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_EnableFreqErrorCounter (void)
Enable Frequency error counter.
__STATIC_INLINE void | LL_CRS_DisableFreqErrorCounter (void)
Disable Frequency error counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledFreqErrorCounter (void)
Check if Frequency error counter is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableAutoTrimming (void)
Enable Automatic trimming counter.
__STATIC_INLINE void | LL_CRS_DisableAutoTrimming (void)
Disable Automatic trimming counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledAutoTrimming (void)
Check if Automatic trimming is enabled or not.
__STATIC_INLINE void | LL_CRS_SetHSI48SmoothTrimming (uint32_t Value)
Set HSI48 oscillator smooth trimming.
__STATIC_INLINE uint32_t | LL_CRS_GetHSI48SmoothTrimming (void)
Get HSI48 oscillator smooth trimming.
__STATIC_INLINE void | LL_CRS_SetReloadCounter (uint32_t Value)
Set counter reload value.
__STATIC_INLINE uint32_t | LL_CRS_GetReloadCounter (void)
Get counter reload value.
__STATIC_INLINE void | LL_CRS_SetFreqErrorLimit (uint32_t Value)
Set frequency error limit.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorLimit (void)
Get frequency error limit.
__STATIC_INLINE void | LL_CRS_SetSyncDivider (uint32_t Divider)
Set division factor for SYNC signal.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncDivider (void)
Get division factor for SYNC signal.
__STATIC_INLINE void | LL_CRS_SetSyncSignalSource (uint32_t Source)
Set SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncSignalSource (void)
Get SYNC signal source.
__STATIC_INLINE void | LL_CRS_SetSyncPolarity (uint32_t Polarity)
Set input polarity for the SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncPolarity (void)
Get input polarity for the SYNC signal source.
__STATIC_INLINE void | LL_CRS_ConfigSynchronization (uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
Configure CRS for the synchronization.

Function Documentation

__STATIC_INLINE void LL_CRS_ConfigSynchronization | ( | uint32_t | HSI48CalibrationValue,
 |  | uint32_t | ErrorLimitValue,
 |  | uint32_t | ReloadValue,
 |  | uint32_t | Settings
 | ) |  |

Configure CRS for the synchronization.

Reference Manual to LL API cross reference:
CR TRIM LL_CRS_ConfigSynchronization
CFGR RELOAD LL_CRS_ConfigSynchronization
CFGR FELIM LL_CRS_ConfigSynchronization
CFGR SYNCDIV LL_CRS_ConfigSynchronization
CFGR SYNCSRC LL_CRS_ConfigSynchronization
CFGR SYNCPOL LL_CRS_ConfigSynchronization
Parameters:
HSI48CalibrationValue | a number between Min_Data = 0 and Max_Data = 127
ErrorLimitValue | a number between Min_Data = 0 and Max_Data = 0xFFFF
ReloadValue | a number between Min_Data = 0 and Max_Data = 255
Settings This parameter can be a combination of the following values:
  • LL_CRS_SYNC_DIV_1 or LL_CRS_SYNC_DIV_2 or LL_CRS_SYNC_DIV_4 or LL_CRS_SYNC_DIV_8 or LL_CRS_SYNC_DIV_16 or LL_CRS_SYNC_DIV_32 or LL_CRS_SYNC_DIV_64 or LL_CRS_SYNC_DIV_128
  • LL_CRS_SYNC_SOURCE_GPIO or LL_CRS_SYNC_SOURCE_LSE or LL_CRS_SYNC_SOURCE_USB
  • LL_CRS_SYNC_POLARITY_RISING or LL_CRS_SYNC_POLARITY_FALLING
Return values:
None

Definition at line 450 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableAutoTrimming ( void )

Disable Automatic trimming counter.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
Return values:
None

Definition at line 260 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter ( void )

Disable Frequency error counter.

Reference Manual to LL API cross reference:
CR CEN LL_CRS_DisableFreqErrorCounter
Return values:
None

Definition at line 230 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableAutoTrimming ( void )

Enable Automatic trimming counter.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
Return values:
None

Definition at line 250 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter ( void )

Enable Frequency error counter.

Note:
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
Reference Manual to LL API cross reference:
CR CEN LL_CRS_EnableFreqErrorCounter
Return values:
None

Definition at line 220 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit ( void )

Get frequency error limit.

Reference Manual to LL API cross reference:
CFGR FELIM LL_CRS_GetFreqErrorLimit
Return values:
A number between Min_Data = 0 and Max_Data = 255

Definition at line 338 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming ( void )

Get HSI48 oscillator smooth trimming.

Reference Manual to LL API cross reference:
CR TRIM LL_CRS_GetHSI48SmoothTrimming
Return values:
a number between Min_Data = 0 and Max_Data = 127

Definition at line 293 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter ( void )

Get counter reload value.

Reference Manual to LL API cross reference:
CFGR RELOAD LL_CRS_GetReloadCounter
Return values:
a number between Min_Data = 0 and Max_Data = 0xFFFF

Definition at line 316 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider ( void )

Get division factor for SYNC signal.

Reference Manual to LL API cross reference:
CFGR SYNCDIV LL_CRS_GetSyncDivider
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_DIV_1
  • LL_CRS_SYNC_DIV_2
  • LL_CRS_SYNC_DIV_4
  • LL_CRS_SYNC_DIV_8
  • LL_CRS_SYNC_DIV_16
  • LL_CRS_SYNC_DIV_32
  • LL_CRS_SYNC_DIV_64
  • LL_CRS_SYNC_DIV_128

Definition at line 375 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity ( void )

Get input polarity for the SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCPOL LL_CRS_GetSyncPolarity
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_POLARITY_RISING
  • LL_CRS_SYNC_POLARITY_FALLING

Definition at line 427 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource ( void )

Get SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCSRC LL_CRS_GetSyncSignalSource
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_SOURCE_GPIO
  • LL_CRS_SYNC_SOURCE_LSE
  • LL_CRS_SYNC_SOURCE_USB

Definition at line 402 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming ( void )

Check if Automatic trimming is enabled or not.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
Return values:
State of bit (1 or 0).

Definition at line 270 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter ( void )

Check if Frequency error counter is enabled or not.

Reference Manual to LL API cross reference:
CR CEN LL_CRS_IsEnabledFreqErrorCounter
Return values:
State of bit (1 or 0).

Definition at line 240 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetFreqErrorLimit ( uint32_t Value )

Set frequency error limit.

Reference Manual to LL API cross reference:
CFGR FELIM LL_CRS_SetFreqErrorLimit
Parameters:
Value a number between Min_Data = 0 and Max_Data = 255
Note:
Default value can be set thanks to LL_CRS_ERRORLIMIT_DEFAULT
Return values:
None

Definition at line 328 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming ( uint32_t Value )

Set HSI48 oscillator smooth trimming.

Note:
When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
Reference Manual to LL API cross reference:
CR TRIM LL_CRS_SetHSI48SmoothTrimming
Parameters:
Value a number between Min_Data = 0 and Max_Data = 127
Note:
Default value can be set thanks to LL_CRS_HSI48CALIBRATION_DEFAULT
Return values:
None

Definition at line 283 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetReloadCounter ( uint32_t Value )

Set counter reload value.

Reference Manual to LL API cross reference:
CFGR RELOAD LL_CRS_SetReloadCounter
Parameters:
Value a number between Min_Data = 0 and Max_Data = 0xFFFF
Note:
Default value can be set thanks to LL_CRS_RELOADVALUE_DEFAULT Otherwise it can be calculated in using macro __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
Return values:
None

Definition at line 306 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncDivider ( uint32_t Divider )

Set division factor for SYNC signal.

Reference Manual to LL API cross reference:
CFGR SYNCDIV LL_CRS_SetSyncDivider
Parameters:
Divider This parameter can be one of the following values:
  • LL_CRS_SYNC_DIV_1
  • LL_CRS_SYNC_DIV_2
  • LL_CRS_SYNC_DIV_4
  • LL_CRS_SYNC_DIV_8
  • LL_CRS_SYNC_DIV_16
  • LL_CRS_SYNC_DIV_32
  • LL_CRS_SYNC_DIV_64
  • LL_CRS_SYNC_DIV_128
Return values:
None

Definition at line 357 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncPolarity ( uint32_t Polarity )

Set input polarity for the SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCPOL LL_CRS_SetSyncPolarity
Parameters:
Polarity This parameter can be one of the following values:
  • LL_CRS_SYNC_POLARITY_RISING
  • LL_CRS_SYNC_POLARITY_FALLING
Return values:
None

Definition at line 415 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncSignalSource ( uint32_t Source )

Set SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCSRC LL_CRS_SetSyncSignalSource
Parameters:
Source This parameter can be one of the following values:
  • LL_CRS_SYNC_SOURCE_GPIO
  • LL_CRS_SYNC_SOURCE_LSE
  • LL_CRS_SYNC_SOURCE_USB
Return values:
None

Definition at line 389 of file stm32g0xx_ll_crs.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRS_Management

Functions
CRS_Management
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_GenerateEvent_SWSYNC (void)
Generate software SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorDirection (void)
Get the frequency error direction latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorCapture (void)
Get the frequency error counter value latched in the time of the last SYNC event.

Function Documentation

__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC ( void )

Generate software SYNC event.

Reference Manual to LL API cross reference:
CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
Return values:
None

Definition at line 471 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture ( void )

Get the frequency error counter value latched in the time of the last SYNC event.

Reference Manual to LL API cross reference:
ISR FECAP LL_CRS_GetFreqErrorCapture
Return values:
A number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 494 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection ( void )

Get the frequency error direction latched in the time of the last SYNC event.

Reference Manual to LL API cross reference:
ISR FEDIR LL_CRS_GetFreqErrorDirection
Return values:
Returned value can be one of the following values:
  • LL_CRS_FREQ_ERROR_DIR_UP
  • LL_CRS_FREQ_ERROR_DIR_DOWN

Definition at line 484 of file stm32g0xx_ll_crs.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
CRS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCOK (void)
Check if SYNC event OK signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCWARN (void)
Check if SYNC warning signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ERR (void)
Check if Synchronization or trimming error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ESYNC (void)
Check if Expected SYNC signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCERR (void)
Check if SYNC error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCMISS (void)
Check if SYNC missed error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_TRIMOVF (void)
Check if Trimming overflow or underflow occurred or not.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCOK (void)
Clear the SYNC event OK flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCWARN (void)
Clear the SYNC warning flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ERR (void)
Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ESYNC (void)
Clear Expected SYNC flag.

Function Documentation

__STATIC_INLINE void LL_CRS_ClearFlag_ERR ( void )

Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.

Reference Manual to LL API cross reference:
ICR ERRC LL_CRS_ClearFlag_ERR
Return values:
None

Definition at line 603 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC ( void )

Clear Expected SYNC flag.

Reference Manual to LL API cross reference:
ICR ESYNCC LL_CRS_ClearFlag_ESYNC
Return values:
None

Definition at line 613 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK ( void )

Clear the SYNC event OK flag.

Reference Manual to LL API cross reference:
ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
Return values:
None

Definition at line 582 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN ( void )

Clear the SYNC warning flag.

Reference Manual to LL API cross reference:
ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
Return values:
None

Definition at line 592 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR ( void )

Check if Synchronization or trimming error signal occurred or not.

Reference Manual to LL API cross reference:
ISR ERRF LL_CRS_IsActiveFlag_ERR
Return values:
State of bit (1 or 0).

Definition at line 532 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC ( void )

Check if Expected SYNC signal occurred or not.

Reference Manual to LL API cross reference:
ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
Return values:
State of bit (1 or 0).

Definition at line 542 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR ( void )

Check if SYNC error signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
Return values:
State of bit (1 or 0).

Definition at line 552 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS ( void )

Check if SYNC missed error signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
Return values:
State of bit (1 or 0).

Definition at line 562 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK ( void )

Check if SYNC event OK signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
Return values:
State of bit (1 or 0).

Definition at line 512 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN ( void )

Check if SYNC warning signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
Return values:
State of bit (1 or 0).

Definition at line 522 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF ( void )

Check if Trimming overflow or underflow occurred or not.

Reference Manual to LL API cross reference:
ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
Return values:
State of bit (1 or 0).

Definition at line 572 of file stm32g0xx_ll_crs.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT_Management

Functions
IT_Management
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_EnableIT_SYNCOK (void)
Enable SYNC event OK interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCOK (void)
Disable SYNC event OK interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCOK (void)
Check if SYNC event OK interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCWARN (void)
Enable SYNC warning interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCWARN (void)
Disable SYNC warning interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCWARN (void)
Check if SYNC warning interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ERR (void)
Enable Synchronization or trimming error interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ERR (void)
Disable Synchronization or trimming error interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ERR (void)
Check if Synchronization or trimming error interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ESYNC (void)
Enable Expected SYNC interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ESYNC (void)
Disable Expected SYNC interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ESYNC (void)
Check if Expected SYNC interrupt is enabled or not.

Function Documentation

__STATIC_INLINE void LL_CRS_DisableIT_ERR ( void )

Disable Synchronization or trimming error interrupt.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_DisableIT_ERR
Return values:
None

Definition at line 701 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_ESYNC ( void )

Disable Expected SYNC interrupt.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_DisableIT_ESYNC
Return values:
None

Definition at line 731 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK ( void )

Disable SYNC event OK interrupt.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
Return values:
None

Definition at line 641 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN ( void )

Disable SYNC warning interrupt.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
Return values:
None

Definition at line 671 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_ERR ( void )

Enable Synchronization or trimming error interrupt.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_EnableIT_ERR
Return values:
None

Definition at line 691 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_ESYNC ( void )

Enable Expected SYNC interrupt.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_EnableIT_ESYNC
Return values:
None

Definition at line 721 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK ( void )

Enable SYNC event OK interrupt.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
Return values:
None

Definition at line 631 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN ( void )

Enable SYNC warning interrupt.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
Return values:
None

Definition at line 661 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR ( void )

Check if Synchronization or trimming error interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_IsEnabledIT_ERR
Return values:
State of bit (1 or 0).

Definition at line 711 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC ( void )

Check if Expected SYNC interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
Return values:
State of bit (1 or 0).

Definition at line 741 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK ( void )

Check if SYNC event OK interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
Return values:
State of bit (1 or 0).

Definition at line 651 of file stm32g0xx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN ( void )

Check if SYNC warning interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
Return values:
State of bit (1 or 0).

Definition at line 681 of file stm32g0xx_ll_crs.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRS Exported Functions

Functions

ErrorStatus LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.

Function Documentation

ErrorStatus LL_CRS_DeInit ( void )

De-Initializes CRS peripheral registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRS registers are de-initialized
  • ERROR: not applicable

Definition at line 55 of file stm32g0xx_ll_crs.c.

References LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_CRS, and LL_APB1_GRP1_ReleaseReset().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define | DAC_CR_CH1_BITOFFSET
#define | DAC_CR_CH2_BITOFFSET
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET
#define | DAC_REG_DHR8R1_REGOFFSET
#define | DAC_REG_DHR12R2_REGOFFSET
#define | DAC_REG_DHR12L2_REGOFFSET
#define | DAC_REG_DHR8R2_REGOFFSET
#define | DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define | DAC_REG_DHRX_REGOFFSET_MASK
#define | DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define | DAC_REG_SHSR2_REGOFFSET
#define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define | DAC_REG_DHR_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_DORX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DORX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
#define | DAC_DIGITAL_SCALE_12BITS

Define Documentation

#define DAC_CR_CH1_BITOFFSET
Value:
0UL   /* Position of channel bits into registers
                                                CR, MCR, CCR, SHHR, SHRR of channel 1 */

Definition at line 55 of file stm32g0xx_ll_dac.h.

#define DAC_CR_CH2_BITOFFSET
Value:
16UL  /* Position of channel bits into registers
                                                CR, MCR, CCR, SHHR, SHRR of channel 2 */

Definition at line 56 of file stm32g0xx_ll_dac.h.

#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)

Definition at line 57 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_Disable(), LL_DAC_DisableDMAReq(), LL_DAC_DisableTrigger(), LL_DAC_EnableTrigger(), LL_DAC_GetMode(), LL_DAC_GetOutputBuffer(), LL_DAC_GetOutputMode(), LL_DAC_GetSampleAndHoldHoldTime(), LL_DAC_GetSampleAndHoldRefreshTime(), LL_DAC_GetTrimmingValue(), LL_DAC_GetWaveAutoGeneration(), LL_DAC_GetWaveNoiseLFSR(), LL_DAC_GetWaveTriangleAmplitude(), LL_DAC_Init(), LL_DAC_IsDMAReqEnabled(), LL_DAC_IsEnabled(), LL_DAC_IsTriggerEnabled(), LL_DAC_SetOutputBuffer(), LL_DAC_SetOutputConnection(), LL_DAC_SetSampleAndHoldRefreshTime(), LL_DAC_SetSampleAndHoldSampleTime(), LL_DAC_SetTriggerSource(), LL_DAC_SetTrimmingValue(), LL_DAC_SetWaveAutoGeneration(), LL_DAC_SetWaveNoiseLFSR(), and LL_DAC_SetWaveTriangleAmplitude().

#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos

Definition at line 99 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData8RightAligned().

#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos

Definition at line 98 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12LeftAligned().

#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos

Definition at line 100 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_RetrieveOutputData().

#define DAC_DIGITAL_SCALE_12BITS
Value:
4095UL   /* Full-scale digital value with a resolution of 12
                                                              bits (voltage range determined by analog voltage
                                                              references Vref+ and Vref-, refer to reference manual) */

Definition at line 103 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR12L1_REGOFFSET
Value:
0x00100000UL            /* Register offset of DHR12Lx channel 1 versus
                                                                  DHR12Rx channel 1 (shifted left of 20 bits)   */

Definition at line 64 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR12L2_REGOFFSET
Value:
0x00400000UL            /* Register offset of DHR12Lx channel 2 versus
                                                                  DHR12Rx channel 1 (shifted left of 20 bits)   */

Definition at line 68 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
Value:
20UL  /* Position of bits register offset of DHR12Lx
                                                                   channel 1 or 2 versus DHR12Rx channel 1
                                                                   (shifted left of 20 bits)                   */

Definition at line 92 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ConvertData8RightAligned().

#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL

Definition at line 72 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */

Definition at line 63 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR12R2_REGOFFSET
Value:
0x30000000UL            /* Register offset of DHR12Rx channel 2 versus
                                                                  DHR12Rx channel 1 (shifted left of 28 bits)   */

Definition at line 67 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
Value:
28UL  /* Position of bits register offset of DHR12Rx
                                                                   channel 1 or 2 versus DHR12Rx channel 1
                                                                   (shifted left of 28 bits)                   */

Definition at line 91 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned().

#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL

Definition at line 71 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR8R1_REGOFFSET
Value:
0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus
                                                                  DHR12Rx channel 1 (shifted left of 24 bits)   */

Definition at line 65 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR8R2_REGOFFSET
Value:
0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus
                                                                  DHR12Rx channel 1 (shifted left of 24 bits)   */

Definition at line 69 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
Value:
24UL  /* Position of bits register offset of DHR8Rx
                                                                   channel 1 or 2 versus DHR12Rx channel 1
                                                                   (shifted left of 24 bits)                   */

Definition at line 93 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12RightAligned().

#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL

Definition at line 73 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0
Value:
0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
                                                                   DHR12Lx, DHR8Rx, ...) when shifted to position 0 */

Definition at line 87 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData8RightAligned(), and LL_DAC_ConvertDualData12RightAligned().

#define DAC_REG_DHRX_REGOFFSET_MASK
Value:
(DAC_REG_DHR12RX_REGOFFSET_MASK\
                                        | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)

Definition at line 74 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */

Definition at line 77 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DOR2_REGOFFSET
Value:
0x00000020UL            /* Register offset of DORx channel 1 versus
                                                                  DORx channel 2 (shifted left of 5 bits)    */

Definition at line 79 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS
Value:
5UL  /* Position of bits register offset of DORx
                                                                   channel 1 or 2 versus DORx channel 1
                                                                   (shifted left of 5 bits)                    */

Definition at line 94 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_CAL1().

#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)

Definition at line 80 of file stm32g0xx_ll_dac.h.

#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0
Value:
0x00000001UL /* Mask of DORx registers offset when shifted
                                                                   to position 0                                    */

Definition at line 88 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_CAL1().

#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */

Definition at line 82 of file stm32g0xx_ll_dac.h.

#define DAC_REG_SHSR2_REGOFFSET
Value:
0x00000040UL            /* Register offset of SHSRx channel 1 versus
                                                                  SHSRx channel 2 (shifted left of 6 bits)    */

Definition at line 83 of file stm32g0xx_ll_dac.h.

#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS
Value:
6UL  /* Position of bits register offset of SHSRx
                                                                   channel 1 or 2 versus SHSRx channel 1
                                                                   (shifted left of 6 bits)                    */

Definition at line 95 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldHoldTime().

#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)

Definition at line 84 of file stm32g0xx_ll_dac.h.

#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0
Value:
0x00000001UL /* Mask of SHSRx registers offset when shifted
                                                                   to position 0                                    */

Definition at line 89 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldHoldTime().

#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */

Definition at line 59 of file stm32g0xx_ll_dac.h.

#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */

Definition at line 60 of file stm32g0xx_ll_dac.h.

#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)

Definition at line 61 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12RightAligned().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)
#define | IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __DAC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 123 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData8RightAligned(), LL_DAC_ConvertDualData12RightAligned(), LL_DAC_GetSampleAndHoldSampleTime(), LL_DAC_IsActiveFlag_CAL1(), and LL_DAC_SetSampleAndHoldHoldTime().

#define IS_LL_DAC_CHANNEL ( __DAC_CHANNEL__ )
Value:
(  ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)      \
     || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)   \
  )

Definition at line 48 of file stm32g0xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_BUFFER ( __OUTPUT_BUFFER__ )
Value:
(   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
      || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                 \
  )

Definition at line 103 of file stm32g0xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_CONNECTION ( __OUTPUT_CONNECTION__ )
Value:
(   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
      || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)           \
  )

Definition at line 108 of file stm32g0xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_MODE ( __OUTPUT_MODE__ )
Value:
(   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
      || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)             \
  )

Definition at line 113 of file stm32g0xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_TRIGGER_SOURCE ( __TRIGGER_SOURCE__ )
Value:
(   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT)                     \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT)                     \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
  )

Definition at line 53 of file stm32g0xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG | ( | __WAVE_AUTO_GENERATION_MODE__,
 |  | __WAVE_AUTO_GENERATION_CONFIG__
 | ) |
Value:
( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)                               \
     && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                           \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                     \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                    \
           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                   \
    )                                                                                                     \
    ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)                          \
       && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                           \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                        \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                        \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                       \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                       \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                       \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                      \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                      \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                      \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                     \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                     \
             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                    \
      )                                                                                                   \
  )

Definition at line 72 of file stm32g0xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_MODE ( __WAVE_AUTO_GENERATION_MODE__ )
Value:
(   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)        \
      || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
      || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
  )

Definition at line 66 of file stm32g0xx_ll_dac.c.

Referenced by LL_DAC_Init().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_DAC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DAC_InitTypeDef Struct Reference
DAC Exported Init structure

Structure definition of some features of DAC instance. More...

#include <stm32g0xx_ll_dac.h>

Data Fields

uint32_t | TriggerSource
uint32_t | WaveAutoGeneration
uint32_t | WaveAutoGenerationConfig
uint32_t | OutputBuffer
uint32_t | OutputConnection
uint32_t | OutputMode

Detailed Description

Structure definition of some features of DAC instance.

Definition at line 140 of file stm32g0xx_ll_dac.h.

Field Documentation

uint32_t LL_DAC_InitTypeDef::OutputBuffer

Set the output buffer for the selected DAC channel. This parameter can be a value of DAC channel output buffer

This feature can be modified afterwards using unitary function LL_DAC_SetOutputBuffer().

Definition at line 169 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::OutputConnection

Set the output connection for the selected DAC channel. This parameter can be a value of DAC channel output connection

This feature can be modified afterwards using unitary function LL_DAC_SetOutputConnection().

Definition at line 175 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::OutputMode

Set the output mode normal or sample-and-hold for the selected DAC channel. This parameter can be a value of DAC channel output mode

This feature can be modified afterwards using unitary function LL_DAC_SetOutputMode().

Definition at line 181 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::TriggerSource

Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of DAC trigger source

This feature can be modified afterwards using unitary function LL_DAC_SetTriggerSource().

Definition at line 142 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGeneration

Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of DAC waveform automatic generation mode

This feature can be modified afterwards using unitary function LL_DAC_SetWaveAutoGeneration().

Definition at line 150 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGenerationConfig

Set the waveform automatic generation mode for the selected DAC channel. If waveform automatic generation mode is set to noise, this parameter can be a value of DAC wave generation - Noise LFSR unmask bits If waveform automatic generation mode is set to triangle, this parameter can be a value of DAC wave generation - Triangle amplitude

Note:
If waveform automatic generation mode is disabled, this parameter is discarded.

This feature can be modified afterwards using unitary function LL_DAC_SetWaveNoiseLFSR(), LL_DAC_SetWaveTriangleAmplitude() depending on the wave automatic generation selected.

Definition at line 156 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_dac.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC flags

Defines
DAC flags
DAC Exported Constants

Flags defines which can be used with LL_DAC_ReadReg function. More...

Defines

#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
#define | LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
#define | LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)

Detailed Description

Flags defines which can be used with LL_DAC_ReadReg function.

Define Documentation

#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)

DAC channel 1 flag busy writing sample time

Definition at line 205 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_DMAUDR1().

#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)

DAC channel 2 flag busy writing sample time

Definition at line 210 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_DMAUDR2().

#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)

DAC channel 1 flag offset calibration status

Definition at line 204 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_BWST1().

#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)

DAC channel 2 flag offset calibration status

Definition at line 209 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_BWST2().

#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)

DAC channel 1 flag DMA underrun

Definition at line 203 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR1().

#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

DAC channel 2 flag DMA underrun

Definition at line 208 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR2(), and LL_DAC_EnableIT_DMAUDR1().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC interruptions

Defines
DAC interruptions
DAC Exported Constants

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions. More...

Defines

#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

Detailed Description

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

Define Documentation

#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)

DAC channel 1 interruption DMA underrun

Definition at line 220 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR1(), and LL_DAC_IsEnabledIT_DMAUDR1().

#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

DAC channel 2 interruption DMA underrun

Definition at line 222 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR2(), and LL_DAC_IsEnabledIT_DMAUDR2().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC channels

Defines
DAC channels
DAC Exported Constants

Defines

#define | LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)

Define Documentation

#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)

DAC channel 1

Definition at line 231 of file stm32g0xx_ll_dac.h.

#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)

DAC channel 2

Definition at line 232 of file stm32g0xx_ll_dac.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC operating mode

Defines
DAC operating mode
DAC Exported Constants

Defines

#define | LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL
#define | LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)

Define Documentation

#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)

DAC channel in mode calibration

Definition at line 241 of file stm32g0xx_ll_dac.h.

#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL

DAC channel in mode normal operation

Definition at line 240 of file stm32g0xx_ll_dac.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC trigger source

Defines
DAC trigger source
DAC Exported Constants

Defines

#define | LL_DAC_TRIG_SOFTWARE 0x00000000UL
#define | LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 )
#define | LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

Define Documentation

#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: external interrupt line 9.

Definition at line 258 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: LPTIM1 TRGO.

Definition at line 256 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )

DAC channel conversion trigger from external peripheral: LPTIM2 TRGO.

Definition at line 257 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 )

DAC channel conversion trigger from external peripheral: TIM15 TRGO.

Definition at line 255 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: TIM1 TRGO.

Definition at line 250 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external peripheral: TIM2 TRGO.

Definition at line 251 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: TIM3 TRGO.

Definition at line 252 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external peripheral: TIM6 TRGO.

Definition at line 253 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external peripheral: TIM7 TRGO.

Definition at line 254 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIG_SOFTWARE 0x00000000UL

DAC channel conversion trigger internal (SW start)

Definition at line 249 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC waveform automatic generation mode

Defines
DAC waveform automatic generation mode
DAC Exported Constants

Defines

#define | LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )

Define Documentation

#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)

DAC channel wave auto generation mode enabled, set generated noise waveform.

Definition at line 267 of file stm32g0xx_ll_dac.h.

#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL

DAC channel wave auto generation mode disabled.

Definition at line 266 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )

DAC channel wave auto generation mode enabled, set generated triangle waveform.

Definition at line 268 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: DAC wave generation - Noise LFSR unmask bits

Defines
DAC wave generation - Noise LFSR unmask bits
DAC Exported Constants

Defines

#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL

Noise wave generation, unmask LFSR bit0, for the selected DAC channel

Definition at line 276 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel

Definition at line 286 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel

Definition at line 287 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel

Definition at line 277 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel

Definition at line 278 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel

Definition at line 279 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )

Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel

Definition at line 280 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel

Definition at line 281 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel

Definition at line 282 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel

Definition at line 283 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )

Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel

Definition at line 284 of file stm32g0xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel

Definition at line 285 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: DAC wave generation - Triangle amplitude

Defines
DAC wave generation - Triangle amplitude
DAC Exported Constants

Defines

#define | LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL

Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel

Definition at line 295 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel

Definition at line 304 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel

Definition at line 301 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel

Definition at line 298 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel

Definition at line 305 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel

Definition at line 302 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel

Definition at line 296 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )

Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel

Definition at line 299 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel

Definition at line 306 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )

Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel

Definition at line 303 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel

Definition at line 300 of file stm32g0xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel

Definition at line 297 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: DAC channel output mode

Defines
DAC channel output mode
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL
#define | LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)

Define Documentation

#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL

The selected DAC channel output is on mode normal.

Definition at line 314 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)

The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function LL_DAC_ConfigOutput() or LL_DAC_SetOutputMode().

Definition at line 315 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: DAC channel output buffer

Defines
DAC channel output buffer
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)

Define Documentation

#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)

The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption

Definition at line 324 of file stm32g0xx_ll_dac.h.

#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL

The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption

Definition at line 323 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

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STM32G0C1xx HAL User Manual: DAC channel output connection

Defines
DAC channel output connection
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL
#define | LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)

Define Documentation

#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL

The selected DAC channel output is connected to external pin

Definition at line 332 of file stm32g0xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)

The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function LL_DAC_SetOutputConnection().

Definition at line 333 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: DAC channel output resolution

Defines
DAC channel output resolution
DAC Exported Constants

Defines

#define | LL_DAC_RESOLUTION_12B 0x00000000UL
#define | LL_DAC_RESOLUTION_8B 0x00000002UL

Define Documentation

#define LL_DAC_RESOLUTION_12B 0x00000000UL

DAC channel resolution 12 bits

Definition at line 341 of file stm32g0xx_ll_dac.h.

#define LL_DAC_RESOLUTION_8B 0x00000002UL

DAC channel resolution 8 bits

Definition at line 342 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: DAC registers compliant with specific purpose

Defines
DAC registers compliant with specific purpose
DAC Exported Constants

Defines

#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS

Define Documentation

#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 12 bits left aligned

Definition at line 354 of file stm32g0xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 12 bits right aligned

Definition at line 353 of file stm32g0xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS

DAC channel data holding register 8 bits right aligned

Definition at line 355 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: Definitions of DAC hardware constraints delays

Defines
Definitions of DAC hardware constraints delays
DAC Exported Constants

Defines

#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL

Detailed Description

Note:
Only DAC peripheral HW delays are defined in DAC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL

Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable)

Definition at line 380 of file stm32g0xx_ll_dac.h.

#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL

Delay for DAC channel voltage settling time

Definition at line 393 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: Common write and read registers macros

Defines
Common write and read registers macros
DAC Exported Macros

Defines

#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.

Define Documentation

#define LL_DAC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 427 of file stm32g0xx_ll_dac.h.

#define LL_DAC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 419 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: DAC helper macro

Defines
DAC helper macro
DAC Exported Macros

Defines

#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Define Documentation

#define __LL_DAC_CALC_VOLTAGE_TO_DATA | ( | __VREFANALOG_VOLTAGE__,
 |  | __DAC_VOLTAGE__,
 |  | __DAC_RESOLUTION__
 | ) |
Value:
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
 / (__VREFANALOG_VOLTAGE__)                                                  \
)

Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Note:
This helper macro is intended to provide input data in voltage rather than digital value, to be used with LL DAC functions such as LL_DAC_ConvertData12RightAligned().
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__DAC_VOLTAGE__ | Voltage to be generated by DAC channel (unit: mVolt).
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
DAC conversion data (unit: digital value)

Definition at line 501 of file stm32g0xx_ll_dac.h.

#define __LL_DAC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)

Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.

Example: __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) will return decimal number "1".

Note:
The input can be a value from functions where a channel number is returned.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
1...2

Definition at line 450 of file stm32g0xx_ll_dac.h.

#define __LL_DAC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ ) (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))

Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.

Example: __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) will return a data equivalent to "LL_DAC_CHANNEL_1".

Note:
If the input parameter does not correspond to a DAC channel, this macro returns value '0'.
Parameters:
__DECIMAL_NB__ 1...2
Return values:
Returned value can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2

Definition at line 466 of file stm32g0xx_ll_dac.h.

#define __LL_DAC_DIGITAL_SCALE ( __DAC_RESOLUTION__ ) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))

Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.

Note:
DAC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 480 of file stm32g0xx_ll_dac.h.

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STM32G0C1xx HAL User Manual: Configuration of DAC channels

Functions
Configuration of DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_SetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
Set the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE uint32_t | LL_DAC_GetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE void | LL_DAC_SetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
Set the offset trimming value for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the offset trimming value for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_ConfigOutput (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
Set the output for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
Set the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
Set the output connection for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output connection for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
Set the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
Set the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
Set the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: refresh time.

Function Documentation

__STATIC_INLINE void LL_DAC_ConfigOutput | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputMode,
 |  | uint32_t | OutputBuffer,
 |  | uint32_t | OutputConnection
 | ) |  |

Set the output for the selected DAC channel.

Note:
This function set several features:
  • mode normal or sample-and-hold
  • buffer
  • connection to GPIO or internal path. These features can also be set individually using dedicated functions:
  • LL_DAC_SetOutputBuffer()
  • LL_DAC_SetOutputMode()
  • LL_DAC_SetOutputConnection()
On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Mode sample-and-hold requires an external capacitor to be connected between DAC channel output and ground. Capacitor value depends on load on DAC channel output and sample-and-hold timings configured. As indication, capacitor typical value is 100nF (refer to device datasheet, parameter "CSH").
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_ConfigOutput
CR MODE2 LL_DAC_ConfigOutput
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputMode This parameter can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
OutputConnection This parameter can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL
Return values:
None

Definition at line 890 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_GetMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the operating mode for the selected DAC channel: calibration or normal operating mode.

Reference Manual to LL API cross reference:
CR CEN1 LL_DAC_GetMode
CR CEN2 LL_DAC_GetMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_MODE_NORMAL_OPERATION
  • LL_DAC_MODE_CALIBRATION

Definition at line 559 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output buffer state for the selected DAC channel.

Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputBuffer
CR MODE2 LL_DAC_GetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE

Definition at line 980 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output connection for the selected DAC channel.

Note:
On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputConnection
CR MODE2 LL_DAC_GetOutputConnection
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL

Definition at line 1039 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_GetOutputMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output mode normal or sample-and-hold for the selected DAC channel.

Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputMode
CR MODE2 LL_DAC_GetOutputMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD

Definition at line 937 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: hold time.

Reference Manual to LL API cross reference:
SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime
SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 1119 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: refresh time.

Reference Manual to LL API cross reference:
SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime
SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1156 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: sample time.

Reference Manual to LL API cross reference:
SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime
SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 1081 of file stm32g0xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_GetTriggerSource
CR TSEL2 LL_DAC_GetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_LPTIM1_OUT
  • LL_DAC_TRIG_EXT_LPTIM2_OUT
  • LL_DAC_TRIG_EXT_EXTI_LINE9

Definition at line 663 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the offset trimming value for the selected DAC channel.

Trimming has an impact when output buffer is enabled and is intended to replace factory calibration default values.

Reference Manual to LL API cross reference:
CCR OTRIM1 LL_DAC_GetTrimmingValue
CCR OTRIM2 LL_DAC_GetTrimmingValue
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F

Definition at line 598 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_GetWaveAutoGeneration
CR WAVE2 LL_DAC_GetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE

Definition at line 706 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveNoiseLFSR
CR MAMP2 LL_DAC_GetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0

Definition at line 772 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveTriangleAmplitude
CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095

Definition at line 839 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | ChannelMode
 | ) |  |

Set the operating mode for the selected DAC channel: calibration or normal operating mode.

Reference Manual to LL API cross reference:
CR CEN1 LL_DAC_SetMode
CR CEN2 LL_DAC_SetMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
ChannelMode This parameter can be one of the following values:
  • LL_DAC_MODE_NORMAL_OPERATION
  • LL_DAC_MODE_CALIBRATION
Return values:
None

Definition at line 539 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputBuffer
 | ) |  |

Set the output buffer for the selected DAC channel.

Note:
On this STM32 series, when buffer is enabled, its offset can be trimmed: factory calibration default values can be replaced by user trimming values, using function LL_DAC_SetTrimmingValue().
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputBuffer
CR MODE2 LL_DAC_SetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
Return values:
None

Definition at line 961 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputConnection | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputConnection
 | ) |  |

Set the output connection for the selected DAC channel.

Note:
On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputConnection
CR MODE2 LL_DAC_SetOutputConnection
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputConnection This parameter can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL
Return values:
None

Definition at line 1010 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputMode
 | ) |  |

Set the output mode normal or sample-and-hold for the selected DAC channel.

Note:
Mode sample-and-hold requires an external capacitor to be connected between DAC channel output and ground. Capacitor value depends on load on DAC channel output and sample-and-hold timings configured. As indication, capacitor typical value is 100nF (refer to device datasheet, parameter "CSH").
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputMode
CR MODE2 LL_DAC_SetOutputMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputMode This parameter can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
Return values:
None

Definition at line 918 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | HoldTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: hold time.

Reference Manual to LL API cross reference:
SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime
SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
HoldTime | Value between Min_Data=0x000 and Max_Data=0x3FF
Return values:
None

Definition at line 1101 of file stm32g0xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS, and DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | RefreshTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: refresh time.

Reference Manual to LL API cross reference:
SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime
SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
RefreshTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1138 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | SampleTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: sample time.

Note:
Sample time must be set when DAC channel is disabled or during DAC operation when DAC channel flag BWSTx is reset, otherwise the setting is ignored. Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
Reference Manual to LL API cross reference:
SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime
SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
SampleTime | Value between Min_Data=0x000 and Max_Data=0x3FF
Return values:
None

Definition at line 1062 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriggerSource
 | ) |  |

Set the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
To set conversion trigger source, DAC channel must be disabled. Otherwise, the setting is discarded.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_SetTriggerSource
CR TSEL2 LL_DAC_SetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TriggerSource This parameter can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM1_TRGO
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM3_TRGO
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM15_TRGO
  • LL_DAC_TRIG_EXT_LPTIM1_OUT
  • LL_DAC_TRIG_EXT_LPTIM2_OUT
  • LL_DAC_TRIG_EXT_EXTI_LINE9
Return values:
None

Definition at line 632 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetTrimmingValue | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TrimmingValue
 | ) |  |

Set the offset trimming value for the selected DAC channel.

Trimming has an impact when output buffer is enabled and is intended to replace factory calibration default values.

Reference Manual to LL API cross reference:
CCR OTRIM1 LL_DAC_SetTrimmingValue
CCR OTRIM2 LL_DAC_SetTrimmingValue
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TrimmingValue | Value between Min_Data=0x00 and Max_Data=0x1F
Return values:
None

Definition at line 579 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | WaveAutoGeneration
 | ) |  |

Set the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_SetWaveAutoGeneration
CR WAVE2 LL_DAC_SetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
WaveAutoGeneration This parameter can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
Return values:
None

Definition at line 685 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | NoiseLFSRMask
 | ) |  |

Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveNoiseLFSR
CR MAMP2 LL_DAC_SetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
NoiseLFSRMask This parameter can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
Return values:
None

Definition at line 742 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriangleAmplitude
 | ) |  |

Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveTriangleAmplitude
CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TriangleAmplitude This parameter can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095
Return values:
None

Definition at line 808 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Management

Functions
DMA Management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_DisableDMAReq
CR DMAEN2 LL_DAC_DisableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1201 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Note:
These DAC registers are data holding registers: when DAC conversion is requested, DAC generates a DMA transfer request to have data available in DAC data holding registers.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, (uint32_t)&< array or variable >, LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Register This parameter can be one of the following values:
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
Return values:
DAC register address

Definition at line 1257 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_EnableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_EnableDMAReq
CR DMAEN2 LL_DAC_EnableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1183 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC DMA transfer request state of the selected channel.

(0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)

Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_IsDMAReqEnabled
CR DMAEN2 LL_DAC_IsDMAReqEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1218 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Operation on DAC channels

Functions
Operation on DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.

Function Documentation

__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned
DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1444 of file stm32g0xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned
DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1423 of file stm32g0xx_ll_dac.h.

References DAC_SWTR_CHX_MASK.

__STATIC_INLINE void LL_DAC_ConvertData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned
DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1465 of file stm32g0xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned
DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1504 of file stm32g0xx_ll_dac.h.

References DAC_DHR12RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned
DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1485 of file stm32g0xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DHR_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned
DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x00 and Max_Data=0xFF
DataChannel2 | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1526 of file stm32g0xx_ll_dac.h.

References DAC_DHR12LD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_Disable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Disable
CR EN2 LL_DAC_Disable
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1301 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_DisableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC trigger of the selected channel.

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_DisableTrigger
CR TEN2 LL_DAC_DisableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1359 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_Enable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Enable
CR EN2 LL_DAC_Enable
Note:
After enable from off state, DAC channel requires a delay for output voltage to reach accuracy +/- 1 LSB. Refer to device datasheet, parameter "tWAKEUP".
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1285 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE void LL_DAC_EnableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC trigger of the selected channel.

Note:
- If DAC trigger is disabled, DAC conversion is performed automatically once the data holding register is updated, using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...
  • If DAC trigger is enabled, DAC conversion is performed only when a hardware of software trigger event is occurring. Select trigger source using function LL_DAC_SetTriggerSource().
Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_EnableTrigger
CR TEN2 LL_DAC_EnableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1343 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC enable state of the selected channel.

(0: DAC channel is disabled, 1: DAC channel is enabled)

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_IsEnabled
CR EN2 LL_DAC_IsEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1318 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Referenced by LL_DAC_Init().

__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC trigger state of the selected channel.

(0: DAC trigger is disabled, 1: DAC trigger is enabled)

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_IsTriggerEnabled
CR TEN2 LL_DAC_IsTriggerEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1376 of file stm32g0xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Retrieve output data currently generated for the selected DAC channel.

Note:
Whatever alignment and resolution settings (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...), output data format is 12 bits right aligned (LSB aligned on bit 0).
Reference Manual to LL API cross reference:
DOR1 DACC1DOR LL_DAC_RetrieveOutputData
DOR2 DACC2DOR LL_DAC_RetrieveOutputData
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1549 of file stm32g0xx_ll_dac.h.

References DAC_DHR8RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_TrigSWConversion | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Trig DAC conversion by software for the selected DAC channel.

Note:
Preliminarily, DAC trigger must be set to software trigger using function LL_DAC_Init() LL_DAC_SetTriggerSource() with parameter "LL_DAC_TRIGGER_SOFTWARE". and DAC trigger must be enabled using function LL_DAC_EnableTrigger().
For devices featuring DAC with 2 channels: this function can perform a SW start of both DAC channels simultaneously. Two channels can be selected as parameter. Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
Reference Manual to LL API cross reference:
SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion
SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
Parameters:
DACx DAC instance
DAC_Channel This parameter can a combination of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1404 of file stm32g0xx_ll_dac.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG Management

Functions
FLAG Management
DAC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL1 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL2 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST1 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST2 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1642 of file stm32g0xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR1.

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1654 of file stm32g0xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1 ( DAC_TypeDef * DACx )

Get DAC busy writing sample time flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR BWST1 LL_DAC_IsActiveFlag_BWST1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1595 of file stm32g0xx_ll_dac.h.

References LL_DAC_FLAG_CAL1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2 ( DAC_TypeDef * DACx )

Get DAC busy writing sample time flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR BWST2 LL_DAC_IsActiveFlag_BWST2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1606 of file stm32g0xx_ll_dac.h.

References LL_DAC_FLAG_CAL2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1 ( DAC_TypeDef * DACx )

Get DAC calibration offset flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1571 of file stm32g0xx_ll_dac.h.

References __DAC_PTR_REG_OFFSET, DAC_REG_DORX_REGOFFSET_BITOFFSET_POS, and DAC_REG_DORX_REGOFFSET_MASK_POSBIT0.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2 ( DAC_TypeDef * DACx )

Get DAC calibration offset flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1583 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1618 of file stm32g0xx_ll_dac.h.

References LL_DAC_FLAG_BWST1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1630 of file stm32g0xx_ll_dac.h.

References LL_DAC_FLAG_BWST2.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT management

Functions
IT management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1698 of file stm32g0xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1710 of file stm32g0xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1674 of file stm32g0xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1686 of file stm32g0xx_ll_dac.h.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1 ( DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1722 of file stm32g0xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2 ( DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1734 of file stm32g0xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Functions

ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_DAC_DeInit ( DAC_TypeDef * DACx )

De-initialize registers of the selected DAC instance to their default reset values.

Parameters:
DACx DAC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are de-initialized
  • ERROR: not applicable

Definition at line 142 of file stm32g0xx_ll_dac.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_DAC1, and LL_APB1_GRP1_ReleaseReset().

ErrorStatus LL_DAC_Init | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | LL_DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initialize some features of DAC channel.

Note:
LL_DAC_Init() aims to ease basic configuration of a DAC channel. Leaving it ready to be enabled and output: a level by calling one of LL_DAC_ConvertData12RightAligned LL_DAC_ConvertData12LeftAligned LL_DAC_ConvertData8RightAligned or one of the supported autogenerated wave.
This function allows configuration of:
  • Output mode
  • Trigger
  • Wave generation
The setting of these parameters by function LL_DAC_Init() is conditioned to DAC state: DAC channel must be disabled.
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
DAC_InitStruct | Pointer to a LL_DAC_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are initialized
  • ERROR: DAC registers are not initialized

Definition at line 181 of file stm32g0xx_ll_dac.c.

References assert_param, DAC_CR_CHX_BITOFFSET_MASK, IS_LL_DAC_CHANNEL, IS_LL_DAC_OUTPUT_BUFFER, IS_LL_DAC_OUTPUT_CONNECTION, IS_LL_DAC_OUTPUT_MODE, IS_LL_DAC_TRIGGER_SOURCE, IS_LL_DAC_WAVE_AUTO_GENER_CONFIG, IS_LL_DAC_WAVE_AUTO_GENER_MODE, LL_DAC_IsEnabled(), LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::OutputConnection, LL_DAC_InitTypeDef::OutputMode, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

void LL_DAC_StructInit ( LL_DAC_InitTypeDef * DAC_InitStruct )

Set each LL_DAC_InitTypeDef field to default value.

Parameters:
DAC_InitStruct pointer to a LL_DAC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 261 of file stm32g0xx_ll_dac.c.

References LL_DAC_NOISE_LFSR_UNMASK_BIT0, LL_DAC_OUTPUT_BUFFER_ENABLE, LL_DAC_OUTPUT_CONNECT_GPIO, LL_DAC_OUTPUT_MODE_NORMAL, LL_DAC_TRIG_SOFTWARE, LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::OutputConnection, LL_DAC_InitTypeDef::OutputMode, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Private Variables

Variables
DMA Private Variables
DMA

Variables

static const uint8_t CHANNEL_OFFSET_TAB []

Variable Documentation

const uint8_t CHANNEL_OFFSET_TAB[] [static]
Initial value:
{
  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),

  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),

  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),

}

Definition at line 47 of file stm32g0xx_ll_dma.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_MAX_REQ)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)
#define | __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
Helper macro to convert DMA Instance DMAx into DMAMUX channel.

Define Documentation

#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL ( __DMA_INSTANCE__ ) (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)

Helper macro to convert DMA Instance DMAx into DMAMUX channel.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Parameters:
__DMA_INSTANCE__ DMAx
Return values:
Channel_Offset (LL_DMA_CHANNEL_7 or 0).

Definition at line 78 of file stm32g0xx_ll_dma.h.

#define IS_LL_DMA_ALL_CHANNEL_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) |
Value:
((((INSTANCE) == DMA1) && \
                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_6) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
                                                            (((INSTANCE) == DMA2) && \
                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                              ((CHANNEL) == LL_DMA_CHANNEL_5))))

Definition at line 77 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

#define IS_LL_DMA_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))

Definition at line 46 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))

Definition at line 63 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))

Definition at line 56 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MODE_NORMAL) || \
                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))

Definition at line 50 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_NBDATA ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 67 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))

Definition at line 59 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))

Definition at line 53 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHREQUEST ( __VALUE__ ) ((__VALUE__) <= LL_DMAMUX_MAX_REQ)

Definition at line 69 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))

Definition at line 71 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_Init().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA_InitTypeDef Struct Reference
DMA Exported Init structure

#include <stm32g0xx_ll_dma.h>

Data Fields

uint32_t | PeriphOrM2MSrcAddress
uint32_t | MemoryOrM2MDstAddress
uint32_t | Direction
uint32_t | Mode
uint32_t | PeriphOrM2MSrcIncMode
uint32_t | MemoryOrM2MDstIncMode
uint32_t | PeriphOrM2MSrcDataSize
uint32_t | MemoryOrM2MDstDataSize
uint32_t | NbData
uint32_t | PeriphRequest
uint32_t | Priority

Detailed Description

Definition at line 88 of file stm32g0xx_ll_dma.h.

Field Documentation

uint32_t LL_DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of Transfer Direction

This feature can be modified afterwards using unitary function LL_DMA_SetDataTransferDirection().

Definition at line 100 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstAddress

Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 95 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize

Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Memory data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetMemorySize().

Definition at line 131 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode

Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Memory increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetMemoryIncMode().

Definition at line 119 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Mode

Specifies the normal or circular operation mode. This parameter can be a value of Transfer mode

Note:
: The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Channel

This feature can be modified afterwards using unitary function LL_DMA_SetMode().

Definition at line 106 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::NbData

Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

This feature can be modified afterwards using unitary function LL_DMA_SetDataLength().

Definition at line 137 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress

Specifies the peripheral base address for DMA transfer or as Source base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 90 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize

Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Peripheral data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphSize().

Definition at line 125 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode

Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Peripheral increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphIncMode().

Definition at line 113 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphRequest

Specifies the peripheral request. This parameter can be a value of Transfer request

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphRequest().

Definition at line 144 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of Transfer Priority level

This feature can be modified afterwards using unitary function LL_DMA_SetChannelPriorityLevel().

Definition at line 149 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_dma.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_WriteReg function. More...

Defines

#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Detailed Description

Flags defines which can be used with LL_DMA_WriteReg function.

Define Documentation

#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1

Channel 1 global flag

Definition at line 168 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2

Channel 2 global flag

Definition at line 172 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3

Channel 3 global flag

Definition at line 176 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4

Channel 4 global flag

Definition at line 180 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5

Channel 5 global flag

Definition at line 184 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6

Channel 6 global flag

Definition at line 189 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7

Channel 7 global flag

Definition at line 195 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1

Channel 1 half transfer flag

Definition at line 170 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2

Channel 2 half transfer flag

Definition at line 174 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3

Channel 3 half transfer flag

Definition at line 178 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4

Channel 4 half transfer flag

Definition at line 182 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5

Channel 5 half transfer flag

Definition at line 186 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6

Channel 6 half transfer flag

Definition at line 191 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7

Channel 7 half transfer flag

Definition at line 197 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1

Channel 1 transfer complete flag

Definition at line 169 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2

Channel 2 transfer complete flag

Definition at line 173 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3

Channel 3 transfer complete flag

Definition at line 177 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4

Channel 4 transfer complete flag

Definition at line 181 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5

Channel 5 transfer complete flag

Definition at line 185 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6

Channel 6 transfer complete flag

Definition at line 190 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7

Channel 7 transfer complete flag

Definition at line 196 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1

Channel 1 transfer error flag

Definition at line 171 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2

Channel 2 transfer error flag

Definition at line 175 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3

Channel 3 transfer error flag

Definition at line 179 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4

Channel 4 transfer error flag

Definition at line 183 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5

Channel 5 transfer error flag

Definition at line 187 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6

Channel 6 transfer error flag

Definition at line 192 of file stm32g0xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Channel 7 transfer error flag

Definition at line 198 of file stm32g0xx_ll_dma.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_ReadReg function. More...

Defines

#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Detailed Description

Flags defines which can be used with LL_DMA_ReadReg function.

Define Documentation

#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1

Channel 1 global flag

Definition at line 208 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2

Channel 2 global flag

Definition at line 212 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3

Channel 3 global flag

Definition at line 216 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4

Channel 4 global flag

Definition at line 220 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5

Channel 5 global flag

Definition at line 224 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6

Channel 6 global flag

Definition at line 229 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7

Channel 7 global flag

Definition at line 235 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1

Channel 1 half transfer flag

Definition at line 210 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2

Channel 2 half transfer flag

Definition at line 214 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3

Channel 3 half transfer flag

Definition at line 218 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4

Channel 4 half transfer flag

Definition at line 222 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5

Channel 5 half transfer flag

Definition at line 226 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6

Channel 6 half transfer flag

Definition at line 231 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7

Channel 7 half transfer flag

Definition at line 237 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1

Channel 1 transfer complete flag

Definition at line 209 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2

Channel 2 transfer complete flag

Definition at line 213 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3

Channel 3 transfer complete flag

Definition at line 217 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4

Channel 4 transfer complete flag

Definition at line 221 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5

Channel 5 transfer complete flag

Definition at line 225 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6

Channel 6 transfer complete flag

Definition at line 230 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7

Channel 7 transfer complete flag

Definition at line 236 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1

Channel 1 transfer error flag

Definition at line 211 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2

Channel 2 transfer error flag

Definition at line 215 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3

Channel 3 transfer error flag

Definition at line 219 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4

Channel 4 transfer error flag

Definition at line 223 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5

Channel 5 transfer error flag

Definition at line 227 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6

Channel 6 transfer error flag

Definition at line 232 of file stm32g0xx_ll_dma.h.

#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Channel 7 transfer error flag

Definition at line 238 of file stm32g0xx_ll_dma.h.

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STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
DMA Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions. More...

Defines

#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

Define Documentation

#define LL_DMA_CCR_HTIE DMA_CCR_HTIE

Half Transfer interrupt

Definition at line 249 of file stm32g0xx_ll_dma.h.

#define LL_DMA_CCR_TCIE DMA_CCR_TCIE

Transfer complete interrupt

Definition at line 248 of file stm32g0xx_ll_dma.h.

#define LL_DMA_CCR_TEIE DMA_CCR_TEIE

Transfer error interrupt

Definition at line 250 of file stm32g0xx_ll_dma.h.

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STM32G0C1xx HAL User Manual: CHANNEL

Defines
CHANNEL
DMA Exported Constants

Defines

#define | LL_DMA_CHANNEL_1 0x00000000U
#define | LL_DMA_CHANNEL_2 0x00000001U
#define | LL_DMA_CHANNEL_3 0x00000002U
#define | LL_DMA_CHANNEL_4 0x00000003U
#define | LL_DMA_CHANNEL_5 0x00000004U
#define | LL_DMA_CHANNEL_6 0x00000005U
#define | LL_DMA_CHANNEL_7 0x00000006U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U

Define Documentation

#define LL_DMA_CHANNEL_1 0x00000000U

DMA Channel 1

Definition at line 258 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_2 0x00000001U

DMA Channel 2

Definition at line 259 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_3 0x00000002U

DMA Channel 3

Definition at line 260 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_4 0x00000003U

DMA Channel 4

Definition at line 261 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_5 0x00000004U

DMA Channel 5

Definition at line 262 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_6 0x00000005U

DMA Channel 6

Definition at line 264 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_7 0x00000006U

DMA Channel 7

Definition at line 267 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_ALL 0xFFFF0000U

DMA Channel all (used only for function LL_DMA_DeInit().

Definition at line 270 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

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STM32G0C1xx HAL User Manual: Transfer Direction

Defines
Transfer Direction
DMA Exported Constants

Defines

#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Define Documentation

#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Memory to memory direction

Definition at line 281 of file stm32g0xx_ll_dma.h.

#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR

Memory to peripheral direction

Definition at line 280 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_ConfigAddresses().

#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 279 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32G0C1xx HAL User Manual: Transfer mode

Defines
Transfer mode
DMA Exported Constants

Defines

#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Define Documentation

#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Circular Mode

Definition at line 290 of file stm32g0xx_ll_dma.h.

#define LL_DMA_MODE_NORMAL 0x00000000U

Normal Mode

Definition at line 289 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32G0C1xx HAL User Manual: Peripheral increment mode

Defines
Peripheral increment mode
DMA Exported Constants

Defines

#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC

Peripheral increment mode Enable

Definition at line 298 of file stm32g0xx_ll_dma.h.

#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Peripheral increment mode Disable

Definition at line 299 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32G0C1xx HAL User Manual: Memory increment mode

Defines
Memory increment mode
DMA Exported Constants

Defines

#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC

Memory increment mode Enable

Definition at line 307 of file stm32g0xx_ll_dma.h.

#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Memory increment mode Disable

Definition at line 308 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32G0C1xx HAL User Manual: Peripheral data alignment

Defines
Peripheral data alignment
DMA Exported Constants

Defines

#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Define Documentation

#define LL_DMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment : Byte

Definition at line 316 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 317 of file stm32g0xx_ll_dma.h.

#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 318 of file stm32g0xx_ll_dma.h.

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STM32G0C1xx HAL User Manual: Memory data alignment

Defines
Memory data alignment
DMA Exported Constants

Defines

#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Define Documentation

#define LL_DMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment : Byte

Definition at line 326 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 327 of file stm32g0xx_ll_dma.h.

#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Memory data alignment : Word

Definition at line 328 of file stm32g0xx_ll_dma.h.

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STM32G0C1xx HAL User Manual: Transfer Priority level

Defines
Transfer Priority level
DMA Exported Constants

Defines

#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Define Documentation

#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1

Priority level : High

Definition at line 338 of file stm32g0xx_ll_dma.h.

#define LL_DMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 336 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0

Priority level : Medium

Definition at line 337 of file stm32g0xx_ll_dma.h.

#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Priority level : Very_High

Definition at line 339 of file stm32g0xx_ll_dma.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMA Exported Macros

Defines

#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.

Define Documentation

#define LL_DMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 371 of file stm32g0xx_ll_dma.h.

#define LL_DMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 363 of file stm32g0xx_ll_dma.h.

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STM32G0C1xx HAL User Manual: Convert DMAxChannely

Defines
Convert DMAxChannely
DMA Exported Macros

Defines

#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Define Documentation

#define __LL_DMA_GET_CHANNEL ( __CHANNEL_INSTANCE__ )
Value:
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
   LL_DMA_CHANNEL_7)

Convert DMAx_Channely into LL_DMA_CHANNEL_y.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
LL_DMA_CHANNEL_y

Definition at line 397 of file stm32g0xx_ll_dma.h.

#define __LL_DMA_GET_CHANNEL_INSTANCE | ( | __DMA_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
   DMA1_Channel7)

Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Parameters:
__DMA_INSTANCE__ | DMAx
__CHANNEL__ | LL_DMA_CHANNEL_y
Return values:
DMAx_Channely

Definition at line 437 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define __LL_DMA_GET_INSTANCE ( __CHANNEL_INSTANCE__ ) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)

Convert DMAx_Channely into DMAx.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
DMAx

Definition at line 385 of file stm32g0xx_ll_dma.h.

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STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
Set DMA request for DMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA request for DMA Channels on DMAMUX Channel x.

Function Documentation

__STATIC_INLINE void LL_DMA_ConfigAddresses | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Direction
 | ) |  |

Configure the Source and Destination addresses.

Note:
This API must not be called when the DMA channel is enabled.
Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_ConfigAddresses
CMAR MA LL_DMA_ConfigAddresses
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
SrcAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
DstAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 997 of file stm32g0xx_ll_dma.h.

References LL_DMA_DIRECTION_MEMORY_TO_PERIPH.

__STATIC_INLINE void LL_DMA_ConfigTransfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure all parameters link to DMA transfer.

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_ConfigTransfer
CCR MEM2MEM LL_DMA_ConfigTransfer
CCR CIRC LL_DMA_ConfigTransfer
CCR PINC LL_DMA_ConfigTransfer
CCR MINC LL_DMA_ConfigTransfer
CCR PSIZE LL_DMA_ConfigTransfer
CCR MSIZE LL_DMA_ConfigTransfer
CCR PL LL_DMA_ConfigTransfer
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Configuration This parameter must be a combination of all the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH or LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  • LL_DMA_MODE_NORMAL or LL_DMA_MODE_CIRCULAR
  • LL_DMA_PERIPH_INCREMENT or LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT or LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_PDATAALIGN_BYTE or LL_DMA_PDATAALIGN_HALFWORD or LL_DMA_PDATAALIGN_WORD
  • LL_DMA_MDATAALIGN_BYTE or LL_DMA_MDATAALIGN_HALFWORD or LL_DMA_MDATAALIGN_WORD
  • LL_DMA_PRIORITY_LOW or LL_DMA_PRIORITY_MEDIUM or LL_DMA_PRIORITY_HIGH or LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 576 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_DisableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_DisableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 520 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_EnableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 500 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_GetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH

Definition at line 920 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Number of data to transfer.

Note:
Once the channel is enabled, the return value indicate the remaining bytes to be transmitted.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_GetDataLength
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 967 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_GetDataTransferDirection
CCR MEM2MEM LL_DMA_GetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Definition at line 628 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetM2MDstAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1185 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetM2MSrcAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1164 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetMemoryAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1076 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_GetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT

Definition at line 771 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_GetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD

Definition at line 869 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA mode circular or normal.

Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_GetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR

Definition at line 677 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetPeriphAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1097 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_GetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT

Definition at line 724 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA request for DMA Channels on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_AES_IN
  • LL_DMAMUX_REQ_AES_OUT
  • LL_DMAMUX_REQ_DAC1_CH1
  • LL_DMAMUX_REQ_DAC1_CH2
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C2_RX
  • LL_DMAMUX_REQ_I2C2_TX
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_TRIG_COM
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_TRIG
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM3_CH1
  • LL_DMAMUX_REQ_TIM3_CH2
  • LL_DMAMUX_REQ_TIM3_CH3
  • LL_DMAMUX_REQ_TIM3_CH4
  • LL_DMAMUX_REQ_TIM3_TRIG
  • LL_DMAMUX_REQ_TIM3_UP
  • LL_DMAMUX_REQ_TIM6_UP
  • LL_DMAMUX_REQ_TIM7_UP
  • LL_DMAMUX_REQ_TIM15_CH1
  • LL_DMAMUX_REQ_TIM15_CH2
  • LL_DMAMUX_REQ_TIM15_TRIG_COM
  • LL_DMAMUX_REQ_TIM15_UP
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_COM
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_COM
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_USART2_RX
  • LL_DMAMUX_REQ_USART2_TX
  • LL_DMAMUX_REQ_USART3_RX
  • LL_DMAMUX_REQ_USART3_TX
  • LL_DMAMUX_REQ_USART4_RX
  • LL_DMAMUX_REQ_USART4_TX
  • LL_DMAMUX_REQ_UCPD1_RX
  • LL_DMAMUX_REQ_UCPD1_TX
  • LL_DMAMUX_REQ_UCPD2_RX
  • LL_DMAMUX_REQ_UCPD2_TX

Definition at line 1354 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_GetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD

Definition at line 820 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if DMA channel is enabled or disabled.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_IsEnabledChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 540 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Priority
 | ) |  |

Set Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_SetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Priority This parameter can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 895 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | NbData
 | ) |  |

Set Number of data to transfer.

Note:
This action has no effect if channel is enabled.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_SetDataLength
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
NbData | Between Min_Data = 0 and Max_Data = 0x0000FFFF
Return values:
None

Definition at line 944 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Direction
 | ) |  |

Set Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_SetDataTransferDirection
CCR MEM2MEM LL_DMA_SetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 603 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetM2MDstAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1143 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetM2MSrcAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1120 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetMemoryAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1032 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstIncMode
 | ) |  |

Set Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_SetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstIncMode This parameter can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT
Return values:
None

Definition at line 748 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstDataSize
 | ) |  |

Set Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_SetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstDataSize This parameter can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD
Return values:
None

Definition at line 845 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Set DMA mode circular or normal.

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel.
Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_SetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Mode This parameter can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR
Return values:
None

Definition at line 654 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphAddress
 | ) |  |

Set the Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetPeriphAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1055 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcIncMode
 | ) |  |

Set Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_SetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT
Return values:
None

Definition at line 701 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Request
 | ) |  |

Set DMA request for DMA Channels on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Request This parameter can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_AES_IN
  • LL_DMAMUX_REQ_AES_OUT
  • LL_DMAMUX_REQ_DAC1_CH1
  • LL_DMAMUX_REQ_DAC1_CH2
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C2_RX
  • LL_DMAMUX_REQ_I2C2_TX
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_TRIG_COM
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_TRIG
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM3_CH1
  • LL_DMAMUX_REQ_TIM3_CH2
  • LL_DMAMUX_REQ_TIM3_CH3
  • LL_DMAMUX_REQ_TIM3_CH4
  • LL_DMAMUX_REQ_TIM3_TRIG
  • LL_DMAMUX_REQ_TIM3_UP
  • LL_DMAMUX_REQ_TIM6_UP
  • LL_DMAMUX_REQ_TIM7_UP
  • LL_DMAMUX_REQ_TIM15_CH1
  • LL_DMAMUX_REQ_TIM15_CH2
  • LL_DMAMUX_REQ_TIM15_TRIG_COM
  • LL_DMAMUX_REQ_TIM15_UP
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_COM
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_COM
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_USART2_RX
  • LL_DMAMUX_REQ_USART2_TX
  • LL_DMAMUX_REQ_USART3_RX
  • LL_DMAMUX_REQ_USART3_TX
  • LL_DMAMUX_REQ_USART4_RX
  • LL_DMAMUX_REQ_USART4_TX
  • LL_DMAMUX_REQ_UCPD1_RX
  • LL_DMAMUX_REQ_UCPD1_TX
  • LL_DMAMUX_REQ_UCPD2_RX
  • LL_DMAMUX_REQ_UCPD2_TX
Return values:
None

Definition at line 1270 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcDataSize
 | ) |  |

Set Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_SetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD
Return values:
None

Definition at line 796 of file stm32g0xx_ll_dma.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.

Function Documentation

__STATIC_INLINE void LL_DMA_ClearFlag_GI1 ( DMA_TypeDef * DMAx )

Clear Channel 1 global interrupt flag.

Note:
Do not Clear Channel 1 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF1 LL_DMA_ClearFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1702 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI2 ( DMA_TypeDef * DMAx )

Clear Channel 2 global interrupt flag.

Note:
Do not Clear Channel 2 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF2 LL_DMA_ClearFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1717 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI3 ( DMA_TypeDef * DMAx )

Clear Channel 3 global interrupt flag.

Note:
Do not Clear Channel 3 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF3 LL_DMA_ClearFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1732 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI4 ( DMA_TypeDef * DMAx )

Clear Channel 4 global interrupt flag.

Note:
Do not Clear Channel 4 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF4 LL_DMA_ClearFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1747 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI5 ( DMA_TypeDef * DMAx )

Clear Channel 5 global interrupt flag.

Note:
Do not Clear Channel 5 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF5 LL_DMA_ClearFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1762 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI6 ( DMA_TypeDef * DMAx )

Clear Channel 6 global interrupt flag.

Note:
Do not Clear Channel 6 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF6 LL_DMA_ClearFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1778 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI7 ( DMA_TypeDef * DMAx )

Clear Channel 7 global interrupt flag.

Note:
Do not Clear Channel 7 global interrupt flag when the channel in ON. Instead clear specific flags transfer complete, half transfer & transfer error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet.
Reference Manual to LL API cross reference:
IFCR CGIF7 LL_DMA_ClearFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1795 of file stm32g0xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_HT1 ( DMA_TypeDef * DMAx )

Clear Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF1 LL_DMA_ClearFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1888 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT2 ( DMA_TypeDef * DMAx )

Clear Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF2 LL_DMA_ClearFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1899 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT3 ( DMA_TypeDef * DMAx )

Clear Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF3 LL_DMA_ClearFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1910 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT4 ( DMA_TypeDef * DMAx )

Clear Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF4 LL_DMA_ClearFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1921 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT5 ( DMA_TypeDef * DMAx )

Clear Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF5 LL_DMA_ClearFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1932 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT6 ( DMA_TypeDef * DMAx )

Clear Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF6 LL_DMA_ClearFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1944 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT7 ( DMA_TypeDef * DMAx )

Clear Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF7 LL_DMA_ClearFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1957 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF1 LL_DMA_ClearFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1807 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF2 LL_DMA_ClearFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1818 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF3 LL_DMA_ClearFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1829 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF4 LL_DMA_ClearFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1840 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF5 LL_DMA_ClearFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1851 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF6 LL_DMA_ClearFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1863 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF7 LL_DMA_ClearFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1876 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF1 LL_DMA_ClearFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1969 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF2 LL_DMA_ClearFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1980 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF3 LL_DMA_ClearFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1991 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF4 LL_DMA_ClearFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2002 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF5 LL_DMA_ClearFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2013 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF6 LL_DMA_ClearFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2025 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF7 LL_DMA_ClearFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 2038 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1 ( DMA_TypeDef * DMAx )

Get Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF1 LL_DMA_IsActiveFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1374 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2 ( DMA_TypeDef * DMAx )

Get Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF2 LL_DMA_IsActiveFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1385 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3 ( DMA_TypeDef * DMAx )

Get Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF3 LL_DMA_IsActiveFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1396 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4 ( DMA_TypeDef * DMAx )

Get Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF4 LL_DMA_IsActiveFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1407 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5 ( DMA_TypeDef * DMAx )

Get Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF5 LL_DMA_IsActiveFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1418 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6 ( DMA_TypeDef * DMAx )

Get Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF6 LL_DMA_IsActiveFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1430 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7 ( DMA_TypeDef * DMAx )

Get Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF7 LL_DMA_IsActiveFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1443 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1 ( DMA_TypeDef * DMAx )

Get Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF1 LL_DMA_IsActiveFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1536 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2 ( DMA_TypeDef * DMAx )

Get Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF2 LL_DMA_IsActiveFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1547 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3 ( DMA_TypeDef * DMAx )

Get Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF3 LL_DMA_IsActiveFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1558 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4 ( DMA_TypeDef * DMAx )

Get Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF4 LL_DMA_IsActiveFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1569 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5 ( DMA_TypeDef * DMAx )

Get Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF5 LL_DMA_IsActiveFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1580 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6 ( DMA_TypeDef * DMAx )

Get Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF6 LL_DMA_IsActiveFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1592 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7 ( DMA_TypeDef * DMAx )

Get Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF7 LL_DMA_IsActiveFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1605 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF1 LL_DMA_IsActiveFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1455 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF2 LL_DMA_IsActiveFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1466 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF3 LL_DMA_IsActiveFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1477 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF4 LL_DMA_IsActiveFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1488 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF5 LL_DMA_IsActiveFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1499 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF6 LL_DMA_IsActiveFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1511 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF7 LL_DMA_IsActiveFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1524 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF1 LL_DMA_IsActiveFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1617 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF2 LL_DMA_IsActiveFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1628 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF3 LL_DMA_IsActiveFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1639 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF4 LL_DMA_IsActiveFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1650 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF5 LL_DMA_IsActiveFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1661 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF6 LL_DMA_IsActiveFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1673 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF7 LL_DMA_IsActiveFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1686 of file stm32g0xx_ll_dma.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT_Management

Functions
IT_Management
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_DMA_DisableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_DisableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2145 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_DisableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2125 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_DisableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2165 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_EnableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2085 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_EnableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2065 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_EnableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2105 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Half transfer Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_IsEnabledIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2206 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer complete Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_IsEnabledIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2185 of file stm32g0xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer error Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_IsEnabledIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2227 of file stm32g0xx_ll_dma.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Functions

ErrorStatus | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
ErrorStatus | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_DMA_DeInit | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

De-initialize the DMA registers to their default reset values.

Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
  • LL_DMA_CHANNEL_ALL
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are de-initialized
  • ERROR: DMA registers are not de-initialized

Definition at line 141 of file stm32g0xx_ll_dma.c.

References __LL_DMA_GET_CHANNEL_INSTANCE, assert_param, IS_LL_DMA_ALL_CHANNEL_INSTANCE, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_DMA1, LL_AHB1_GRP1_PERIPH_DMA2, LL_AHB1_GRP1_ReleaseReset(), LL_DMA_CHANNEL_1, LL_DMA_CHANNEL_2, LL_DMA_CHANNEL_3, LL_DMA_CHANNEL_4, LL_DMA_CHANNEL_5, LL_DMA_CHANNEL_6, LL_DMA_CHANNEL_7, LL_DMA_CHANNEL_ALL, LL_DMA_ClearFlag_GI1(), LL_DMA_ClearFlag_GI2(), LL_DMA_ClearFlag_GI3(), LL_DMA_ClearFlag_GI4(), LL_DMA_ClearFlag_GI5(), LL_DMA_ClearFlag_GI6(), LL_DMA_ClearFlag_GI7(), LL_DMA_SetPeriphRequest(), and LL_DMAMUX_REQ_MEM2MEM.

ErrorStatus LL_DMA_Init | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | LL_DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initialize the DMA registers according to the specified parameters in DMA_InitStruct.

Note:
To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
  • __LL_DMA_GET_INSTANCE
  • __LL_DMA_GET_CHANNEL
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
DMA_InitStruct | pointer to a LL_DMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are initialized
  • ERROR: Not applicable

Definition at line 264 of file stm32g0xx_ll_dma.c.

References assert_param, LL_DMA_InitTypeDef::Direction, IS_LL_DMA_ALL_CHANNEL_INSTANCE, IS_LL_DMA_DIRECTION, IS_LL_DMA_MEMORYDATASIZE, IS_LL_DMA_MEMORYINCMODE, IS_LL_DMA_MODE, IS_LL_DMA_NBDATA, IS_LL_DMA_PERIPHDATASIZE, IS_LL_DMA_PERIPHINCMODE, IS_LL_DMA_PERIPHREQUEST, IS_LL_DMA_PRIORITY, LL_DMA_ConfigTransfer(), LL_DMA_SetDataLength(), LL_DMA_SetMemoryAddress(), LL_DMA_SetPeriphAddress(), LL_DMA_SetPeriphRequest(), LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

void LL_DMA_StructInit ( LL_DMA_InitTypeDef * DMA_InitStruct )

Set each LL_DMA_InitTypeDef field to default value.

Parameters:
DMA_InitStruct Pointer to a LL_DMA_InitTypeDef structure.
Return values:
None

Definition at line 332 of file stm32g0xx_ll_dma.c.

References LL_DMA_InitTypeDef::Direction, LL_DMA_DIRECTION_PERIPH_TO_MEMORY, LL_DMA_MDATAALIGN_BYTE, LL_DMA_MEMORY_NOINCREMENT, LL_DMA_MODE_NORMAL, LL_DMA_PDATAALIGN_BYTE, LL_DMA_PERIPH_NOINCREMENT, LL_DMA_PRIORITY_LOW, LL_DMAMUX_REQ_MEM2MEM, LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMAMUX Private Constants

Defines
DMAMUX Private Constants
DMAMUX

Defines

#define | DMAMUX_CCR_SIZE 0x00000004UL
#define | DMAMUX_RGCR_SIZE 0x00000004UL

Define Documentation

#define DMAMUX_CCR_SIZE 0x00000004UL

Definition at line 47 of file stm32g0xx_ll_dmamux.h.

#define DMAMUX_RGCR_SIZE 0x00000004UL

Definition at line 50 of file stm32g0xx_ll_dmamux.h.

Referenced by LL_DMAMUX_DisableRequestGen(), LL_DMAMUX_EnableRequestGen(), LL_DMAMUX_GetGenRequestNb(), LL_DMAMUX_GetRequestGenPolarity(), LL_DMAMUX_GetRequestSignalID(), LL_DMAMUX_IsEnabledRequestGen(), LL_DMAMUX_SetGenRequestNb(), LL_DMAMUX_SetRequestGenPolarity(), and LL_DMAMUX_SetRequestSignalID().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMAMUX Exported Constants

Flags defines which can be used with LL_DMAMUX_WriteReg function. More...

Defines

#define | LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0
#define | LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1
#define | LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2
#define | LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3
#define | LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4
#define | LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5
#define | LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6
#define | LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7
#define | LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8
#define | LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9
#define | LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10
#define | LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11
#define | LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0
#define | LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1
#define | LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2
#define | LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3

Detailed Description

Flags defines which can be used with LL_DMAMUX_WriteReg function.

Define Documentation

#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0

Synchronization Event Overrun Flag Channel 0

Definition at line 65 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1

Synchronization Event Overrun Flag Channel 1

Definition at line 66 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10

Synchronization Event Overrun Flag Channel 10

Definition at line 80 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11

Synchronization Event Overrun Flag Channel 11

Definition at line 81 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2

Synchronization Event Overrun Flag Channel 2

Definition at line 67 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3

Synchronization Event Overrun Flag Channel 3

Definition at line 68 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4

Synchronization Event Overrun Flag Channel 4

Definition at line 69 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5

Synchronization Event Overrun Flag Channel 5

Definition at line 71 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6

Synchronization Event Overrun Flag Channel 6

Definition at line 74 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7

Synchronization Event Overrun Flag Channel 7

Definition at line 77 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8

Synchronization Event Overrun Flag Channel 8

Definition at line 78 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9

Synchronization Event Overrun Flag Channel 9

Definition at line 79 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0

Request Generator 0 Trigger Event Overrun Flag

Definition at line 83 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1

Request Generator 1 Trigger Event Overrun Flag

Definition at line 84 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2

Request Generator 2 Trigger Event Overrun Flag

Definition at line 85 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3

Request Generator 3 Trigger Event Overrun Flag

Definition at line 86 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMAMUX Exported Constants

Flags defines which can be used with LL_DMAMUX_ReadReg function. More...

Defines

#define | LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0
#define | LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1
#define | LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2
#define | LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3
#define | LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4
#define | LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5
#define | LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6
#define | LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7
#define | LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8
#define | LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9
#define | LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10
#define | LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11
#define | LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0
#define | LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1
#define | LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2
#define | LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3

Detailed Description

Flags defines which can be used with LL_DMAMUX_ReadReg function.

Define Documentation

#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0

Synchronization Event Overrun Flag Channel 0

Definition at line 95 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1

Synchronization Event Overrun Flag Channel 1

Definition at line 96 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10

Synchronization Event Overrun Flag Channel 10

Definition at line 110 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11

Synchronization Event Overrun Flag Channel 11

Definition at line 111 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2

Synchronization Event Overrun Flag Channel 2

Definition at line 97 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3

Synchronization Event Overrun Flag Channel 3

Definition at line 98 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4

Synchronization Event Overrun Flag Channel 4

Definition at line 99 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5

Synchronization Event Overrun Flag Channel 5

Definition at line 101 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6

Synchronization Event Overrun Flag Channel 6

Definition at line 104 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7

Synchronization Event Overrun Flag Channel 7

Definition at line 107 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8

Synchronization Event Overrun Flag Channel 8

Definition at line 108 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9

Synchronization Event Overrun Flag Channel 9

Definition at line 109 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0

Request Generator 0 Trigger Event Overrun Flag

Definition at line 113 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1

Request Generator 1 Trigger Event Overrun Flag

Definition at line 114 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2

Request Generator 2 Trigger Event Overrun Flag

Definition at line 115 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3

Request Generator 3 Trigger Event Overrun Flag

Definition at line 116 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
DMAMUX Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions. More...

Defines

#define | LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE
#define | LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions.

Define Documentation

#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE

Synchronization Event Overrun Interrupt

Definition at line 125 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE

Request Generation Trigger Event Overrun Interrupt

Definition at line 126 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Transfer request

Defines
Transfer request
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_MEM2MEM 0x00000000U
#define | LL_DMAMUX_REQ_GENERATOR0 0x00000001U
#define | LL_DMAMUX_REQ_GENERATOR1 0x00000002U
#define | LL_DMAMUX_REQ_GENERATOR2 0x00000003U
#define | LL_DMAMUX_REQ_GENERATOR3 0x00000004U
#define | LL_DMAMUX_REQ_ADC1 0x00000005U
#define | LL_DMAMUX_REQ_AES_IN 0x00000006U
#define | LL_DMAMUX_REQ_AES_OUT 0x00000007U
#define | LL_DMAMUX_REQ_DAC1_CH1 0x00000008U
#define | LL_DMAMUX_REQ_DAC1_CH2 0x00000009U
#define | LL_DMAMUX_REQ_I2C1_RX 0x0000000AU
#define | LL_DMAMUX_REQ_I2C1_TX 0x0000000BU
#define | LL_DMAMUX_REQ_I2C2_RX 0x0000000CU
#define | LL_DMAMUX_REQ_I2C2_TX 0x0000000DU
#define | LL_DMAMUX_REQ_LPUART1_RX 0x0000000EU
#define | LL_DMAMUX_REQ_LPUART1_TX 0x0000000FU
#define | LL_DMAMUX_REQ_SPI1_RX 0x00000010U
#define | LL_DMAMUX_REQ_SPI1_TX 0x00000011U
#define | LL_DMAMUX_REQ_SPI2_RX 0x00000012U
#define | LL_DMAMUX_REQ_SPI2_TX 0x00000013U
#define | LL_DMAMUX_REQ_TIM1_CH1 0x00000014U
#define | LL_DMAMUX_REQ_TIM1_CH2 0x00000015U
#define | LL_DMAMUX_REQ_TIM1_CH3 0x00000016U
#define | LL_DMAMUX_REQ_TIM1_CH4 0x00000017U
#define | LL_DMAMUX_REQ_TIM1_TRIG_COM 0x00000018U
#define | LL_DMAMUX_REQ_TIM1_UP 0x00000019U
#define | LL_DMAMUX_REQ_TIM2_CH1 0x0000001AU
#define | LL_DMAMUX_REQ_TIM2_CH2 0x0000001BU
#define | LL_DMAMUX_REQ_TIM2_CH3 0x0000001CU
#define | LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU
#define | LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU
#define | LL_DMAMUX_REQ_TIM2_UP 0x0000001FU
#define | LL_DMAMUX_REQ_TIM3_CH1 0x00000020U
#define | LL_DMAMUX_REQ_TIM3_CH2 0x00000021U
#define | LL_DMAMUX_REQ_TIM3_CH3 0x00000022U
#define | LL_DMAMUX_REQ_TIM3_CH4 0x00000023U
#define | LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U
#define | LL_DMAMUX_REQ_TIM3_UP 0x00000025U
#define | LL_DMAMUX_REQ_TIM6_UP 0x00000026U
#define | LL_DMAMUX_REQ_TIM7_UP 0x00000027U
#define | LL_DMAMUX_REQ_TIM15_CH1 0x00000028U
#define | LL_DMAMUX_REQ_TIM15_CH2 0x00000029U
#define | LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU
#define | LL_DMAMUX_REQ_TIM15_UP 0x0000002BU
#define | LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU
#define | LL_DMAMUX_REQ_TIM16_COM 0x0000002DU
#define | LL_DMAMUX_REQ_TIM16_UP 0x0000002EU
#define | LL_DMAMUX_REQ_TIM17_CH1 0x0000002FU
#define | LL_DMAMUX_REQ_TIM17_COM 0x00000030U
#define | LL_DMAMUX_REQ_TIM17_UP 0x00000031U
#define | LL_DMAMUX_REQ_USART1_RX 0x00000032U
#define | LL_DMAMUX_REQ_USART1_TX 0x00000033U
#define | LL_DMAMUX_REQ_USART2_RX 0x00000034U
#define | LL_DMAMUX_REQ_USART2_TX 0x00000035U
#define | LL_DMAMUX_REQ_USART3_RX 0x00000036U
#define | LL_DMAMUX_REQ_USART3_TX 0x00000037U
#define | LL_DMAMUX_REQ_USART4_RX 0x00000038U
#define | LL_DMAMUX_REQ_USART4_TX 0x00000039U
#define | LL_DMAMUX_REQ_UCPD1_RX 0x0000003AU
#define | LL_DMAMUX_REQ_UCPD1_TX 0x0000003BU
#define | LL_DMAMUX_REQ_UCPD2_RX 0x0000003CU
#define | LL_DMAMUX_REQ_UCPD2_TX 0x0000003DU
#define | LL_DMAMUX_REQ_I2C3_RX 0x0000003EU
#define | LL_DMAMUX_REQ_I2C3_TX 0x0000003FU
#define | LL_DMAMUX_REQ_LPUART2_RX 0x00000040U
#define | LL_DMAMUX_REQ_LPUART2_TX 0x00000041U
#define | LL_DMAMUX_REQ_SPI3_RX 0x00000042U
#define | LL_DMAMUX_REQ_SPI3_TX 0x00000043U
#define | LL_DMAMUX_REQ_TIM4_CH1 0x00000044U
#define | LL_DMAMUX_REQ_TIM4_CH2 0x00000045U
#define | LL_DMAMUX_REQ_TIM4_CH3 0x00000046U
#define | LL_DMAMUX_REQ_TIM4_CH4 0x00000047U
#define | LL_DMAMUX_REQ_TIM4_TRIG 0x00000048U
#define | LL_DMAMUX_REQ_TIM4_UP 0x00000049U
#define | LL_DMAMUX_REQ_USART5_RX 0x0000004AU
#define | LL_DMAMUX_REQ_USART5_TX 0x0000004BU
#define | LL_DMAMUX_REQ_USART6_RX 0x0000004CU
#define | LL_DMAMUX_REQ_USART6_TX 0x0000004DU
#define | LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX

Define Documentation

#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX

Definition at line 254 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_ADC1 0x00000005U

DMAMUX ADC1 request

Definition at line 139 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_AES_IN 0x00000006U

DMAMUX AES_IN request

Definition at line 141 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_AES_OUT 0x00000007U

DMAMUX AES_OUT request

Definition at line 142 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC1_CH1 0x00000008U

DMAMUX DAC_CH1 request

Definition at line 145 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_DAC1_CH2 0x00000009U

DMAMUX DAC_CH2 request

Definition at line 146 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U

DMAMUX request generator 0

Definition at line 135 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U

DMAMUX request generator 1

Definition at line 136 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U

DMAMUX request generator 2

Definition at line 137 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U

DMAMUX request generator 3

Definition at line 138 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU

DMAMUX I2C1 RX request

Definition at line 148 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU

DMAMUX I2C1 TX request

Definition at line 149 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C2_RX 0x0000000CU

DMAMUX I2C2 RX request

Definition at line 150 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C2_TX 0x0000000DU

DMAMUX I2C2 TX request

Definition at line 151 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C3_RX 0x0000003EU

DMAMUX I2C3 RX request

Definition at line 220 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C3_TX 0x0000003FU

DMAMUX I2C3 TX request

Definition at line 221 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_LPUART1_RX 0x0000000EU

DMAMUX LPUART1 RX request

Definition at line 153 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_LPUART1_TX 0x0000000FU

DMAMUX LPUART1 TX request

Definition at line 154 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_LPUART2_RX 0x00000040U

DMAMUX LPUART2 RX request

Definition at line 225 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_LPUART2_TX 0x00000041U

DMAMUX LPUART2 TX request

Definition at line 226 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U

memory to memory transfer

Definition at line 134 of file stm32g0xx_ll_dmamux.h.

Referenced by LL_DMA_DeInit(), and LL_DMA_StructInit().

#define LL_DMAMUX_REQ_SPI1_RX 0x00000010U

DMAMUX SPI1 RX request

Definition at line 156 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI1_TX 0x00000011U

DMAMUX SPI1 TX request

Definition at line 157 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI2_RX 0x00000012U

DMAMUX SPI2 RX request

Definition at line 158 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI2_TX 0x00000013U

DMAMUX SPI2 TX request

Definition at line 159 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI3_RX 0x00000042U

DMAMUX SPI3 RX request

Definition at line 230 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI3_TX 0x00000043U

DMAMUX SPI3 TX request

Definition at line 231 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM15_CH1 0x00000028U

DMAMUX TIM15 CH1 request

Definition at line 187 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM15_CH2 0x00000029U

DMAMUX TIM15 CH2 request

Definition at line 188 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU

DMAMUX TIM15 TRIG COM request

Definition at line 189 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM15_UP 0x0000002BU

DMAMUX TIM15 UP request

Definition at line 190 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU

DMAMUX TIM16 CH1 request

Definition at line 192 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM16_COM 0x0000002DU

DMAMUX TIM16 COM request

Definition at line 193 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM16_UP 0x0000002EU

DMAMUX TIM16 UP request

Definition at line 194 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM17_CH1 0x0000002FU

DMAMUX TIM17 CH1 request

Definition at line 195 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM17_COM 0x00000030U

DMAMUX TIM17 COM request

Definition at line 196 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM17_UP 0x00000031U

DMAMUX TIM17 UP request

Definition at line 197 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH1 0x00000014U

DMAMUX TIM1 CH1 request

Definition at line 160 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH2 0x00000015U

DMAMUX TIM1 CH2 request

Definition at line 161 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH3 0x00000016U

DMAMUX TIM1 CH3 request

Definition at line 162 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH4 0x00000017U

DMAMUX TIM1 CH4 request

Definition at line 163 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_TRIG_COM 0x00000018U

DMAMUX TIM1 TRIG COM request

Definition at line 164 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_UP 0x00000019U

DMAMUX TIM1 UP request

Definition at line 165 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH1 0x0000001AU

DMAMUX TIM2 CH1 request

Definition at line 167 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH2 0x0000001BU

DMAMUX TIM2 CH2 request

Definition at line 168 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH3 0x0000001CU

DMAMUX TIM2 CH3 request

Definition at line 169 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU

DMAMUX TIM2 CH4 request

Definition at line 170 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU

DMAMUX TIM2 TRIG request

Definition at line 171 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_UP 0x0000001FU

DMAMUX TIM2 UP request

Definition at line 172 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_CH1 0x00000020U

DMAMUX TIM3 CH1 request

Definition at line 174 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_CH2 0x00000021U

DMAMUX TIM3 CH2 request

Definition at line 175 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_CH3 0x00000022U

DMAMUX TIM3 CH3 request

Definition at line 176 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_CH4 0x00000023U

DMAMUX TIM3 CH4 request

Definition at line 177 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U

DMAMUX TIM3 TRIG request

Definition at line 178 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM3_UP 0x00000025U

DMAMUX TIM3 UP request

Definition at line 179 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_CH1 0x00000044U

DMAMUX TIM4 CH1 request

Definition at line 235 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_CH2 0x00000045U

DMAMUX TIM4 CH2 request

Definition at line 236 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_CH3 0x00000046U

DMAMUX TIM4 CH3 request

Definition at line 237 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_CH4 0x00000047U

DMAMUX TIM4 CH4 request

Definition at line 238 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_TRIG 0x00000048U

DMAMUX TIM4 TRIG request

Definition at line 239 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM4_UP 0x00000049U

DMAMUX TIM4 UP request

Definition at line 240 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM6_UP 0x00000026U

DMAMUX TIM6 UP request

Definition at line 181 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM7_UP 0x00000027U

DMAMUX TIM7 UP request

Definition at line 184 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UCPD1_RX 0x0000003AU

DMAMUX UCPD1 RX request

Definition at line 211 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UCPD1_TX 0x0000003BU

DMAMUX UCPD1 TX request

Definition at line 212 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UCPD2_RX 0x0000003CU

DMAMUX UCPD2 RX request

Definition at line 215 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_UCPD2_TX 0x0000003DU

DMAMUX UCPD2 TX request

Definition at line 216 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART1_RX 0x00000032U

DMAMUX USART1 RX request

Definition at line 198 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART1_TX 0x00000033U

DMAMUX USART1 TX request

Definition at line 199 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART2_RX 0x00000034U

DMAMUX USART2 RX request

Definition at line 200 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART2_TX 0x00000035U

DMAMUX USART2 TX request

Definition at line 201 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART3_RX 0x00000036U

DMAMUX USART3 RX request

Definition at line 203 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART3_TX 0x00000037U

DMAMUX USART3 TX request

Definition at line 204 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART4_RX 0x00000038U

DMAMUX USART4 RX request

Definition at line 207 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART4_TX 0x00000039U

DMAMUX USART4 TX request

Definition at line 208 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART5_RX 0x0000004AU

DMAMUX USART5 RX request

Definition at line 244 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART5_TX 0x0000004BU

DMAMUX USART5 TX request

Definition at line 245 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART6_RX 0x0000004CU

DMAMUX USART6 RX request

Definition at line 249 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART6_TX 0x0000004DU

DMAMUX USART6 TX request

Definition at line 250 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMAMUX Channel

Defines
DMAMUX Channel
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_CHANNEL_0 0x00000000U
#define | LL_DMAMUX_CHANNEL_1 0x00000001U
#define | LL_DMAMUX_CHANNEL_2 0x00000002U
#define | LL_DMAMUX_CHANNEL_3 0x00000003U
#define | LL_DMAMUX_CHANNEL_4 0x00000004U
#define | LL_DMAMUX_CHANNEL_5 0x00000005U
#define | LL_DMAMUX_CHANNEL_6 0x00000006U
#define | LL_DMAMUX_CHANNEL_7 0x00000007U
#define | LL_DMAMUX_CHANNEL_8 0x00000008U
#define | LL_DMAMUX_CHANNEL_9 0x00000009U
#define | LL_DMAMUX_CHANNEL_10 0x0000000AU
#define | LL_DMAMUX_CHANNEL_11 0x0000000BU

Define Documentation

#define LL_DMAMUX_CHANNEL_0 0x00000000U

DMAMUX Channel 0 connected to DMA1 Channel 1

Definition at line 271 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_1 0x00000001U

DMAMUX Channel 1 connected to DMA1 Channel 2

Definition at line 272 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_10 0x0000000AU

DMAMUX Channel 10 connected to DMA2 Channel 4

Definition at line 286 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_11 0x0000000BU

DMAMUX Channel 11 connected to DMA2 Channel 5

Definition at line 287 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_2 0x00000002U

DMAMUX Channel 2 connected to DMA1 Channel 3

Definition at line 273 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_3 0x00000003U

DMAMUX Channel 3 connected to DMA1 Channel 4

Definition at line 274 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_4 0x00000004U

DMAMUX Channel 4 connected to DMA1 Channel 5

Definition at line 275 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_5 0x00000005U

DMAMUX Channel 5 connected to DMA1 Channel 6

Definition at line 277 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_6 0x00000006U

DMAMUX Channel 6 connected to DMA1 Channel 7

Definition at line 280 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_7 0x00000007U

DMAMUX Channel 7 connected to DMA2 Channel 1

Definition at line 283 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_8 0x00000008U

DMAMUX Channel 8 connected to DMA2 Channel 2

Definition at line 284 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_9 0x00000009U

DMAMUX Channel 9 connected to DMA2 Channel 3

Definition at line 285 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Synchronization Signal Polarity

Defines
Synchronization Signal Polarity
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0
#define | LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1
#define | LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)

Define Documentation

#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U

All requests are blocked

Definition at line 296 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1

Synchronization on event on falling edge

Definition at line 298 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0

Synchronization on event on rising edge

Definition at line 297 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)

Synchronization on event on rising and falling edge

Definition at line 299 of file stm32g0xx_ll_dmamux.h.

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STM32G0C1xx HAL User Manual: Synchronization Signal Event

Defines
Synchronization Signal Event
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0
#define | LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1
#define | LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2
#define | LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3
#define | LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4
#define | LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)

Define Documentation

#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4

Synchronization signal from DMAMUX channel0 Event

Definition at line 323 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from DMAMUX channel1 Event

Definition at line 324 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from DMAMUX channel2 Event

Definition at line 325 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from DMAMUX channel3 Event

Definition at line 326 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U

Synchronization signal from EXTI Line0

Definition at line 307 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0

Synchronization signal from EXTI Line1

Definition at line 308 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line10

Definition at line 317 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line11

Definition at line 318 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)

Synchronization signal from EXTI Line12

Definition at line 319 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line1 3

Definition at line 320 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line1 4

Definition at line 321 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line1 5

Definition at line 322 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1

Synchronization signal from EXTI Line2

Definition at line 309 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line3

Definition at line 310 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2

Synchronization signal from EXTI Line4

Definition at line 311 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line5

Definition at line 312 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line6

Definition at line 313 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line7

Definition at line 314 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3

Synchronization signal from EXTI Line8

Definition at line 315 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line9

Definition at line 316 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)

Synchronization signal from LPTIM1 Output

Definition at line 328 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from LPTIM2 Output

Definition at line 331 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from TIM14 OC

Definition at line 333 of file stm32g0xx_ll_dmamux.h.

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STM32G0C1xx HAL User Manual: Request Generator Channel

Defines
Request Generator Channel
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_1 0x00000001U
#define | LL_DMAMUX_REQ_GEN_2 0x00000002U
#define | LL_DMAMUX_REQ_GEN_3 0x00000003U

Define Documentation

#define LL_DMAMUX_REQ_GEN_0 0x00000000U

Definition at line 341 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_1 0x00000001U

Definition at line 342 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_2 0x00000002U

Definition at line 343 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_3 0x00000003U

Definition at line 344 of file stm32g0xx_ll_dmamux.h.

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STM32G0C1xx HAL User Manual: External Request Signal Generation Polarity

Defines
External Request Signal Generation Polarity
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0
#define | LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1
#define | LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)

Define Documentation

#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U

No external DMA request generation

Definition at line 352 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1

External DMA request generation on event on falling edge

Definition at line 354 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0

External DMA request generation on event on rising edge

Definition at line 353 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)

External DMA request generation on rising and falling edge

Definition at line 355 of file stm32g0xx_ll_dmamux.h.

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STM32G0C1xx HAL User Manual: External Request Signal Generation

Defines
External Request Signal Generation
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)

Define Documentation

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4

Request signal generation from DMAMUX channel0 Event

Definition at line 379 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from DMAMUX channel1 Event

Definition at line 380 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from DMAMUX channel2 Event

Definition at line 381 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from DMAMUX channel3 Event

Definition at line 382 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U

Request signal generation from EXTI Line0

Definition at line 363 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0

Request signal generation from EXTI Line1

Definition at line 364 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line10

Definition at line 373 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line11

Definition at line 374 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)

Request signal generation from EXTI Line12

Definition at line 375 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line13

Definition at line 376 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line14

Definition at line 377 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line15

Definition at line 378 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1

Request signal generation from EXTI Line2

Definition at line 365 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line3

Definition at line 366 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2

Request signal generation from EXTI Line4

Definition at line 367 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line5

Definition at line 368 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line6

Definition at line 369 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line7

Definition at line 370 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3

Request signal generation from EXTI Line8

Definition at line 371 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line9

Definition at line 372 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)

Request signal generation from LPTIM1 Output

Definition at line 384 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from LPTIM2 Output

Definition at line 387 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from TIM14 OC

Definition at line 389 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMAMUX Exported Macros

Defines

#define | LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMAMUX register.
#define | LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMAMUX register.

Define Documentation

#define LL_DMAMUX_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMAMUX register.

Parameters:
__INSTANCE__ | DMAMUX Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 421 of file stm32g0xx_ll_dmamux.h.

#define LL_DMAMUX_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMAMUX register.

Parameters:
__INSTANCE__ | DMAMUX Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 413 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
DMAMUX Exported Functions

Functions

__STATIC_INLINE void | LL_DMAMUX_SetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
Set DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_SetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE void | LL_DMAMUX_SetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE void | LL_DMAMUX_EnableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Event Generation on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Event Generation on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Event Generation on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the synchronization mode.
__STATIC_INLINE void | LL_DMAMUX_DisableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the synchronization mode.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the synchronization mode is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
Set DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_EnableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generator.
__STATIC_INLINE void | LL_DMAMUX_DisableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generator.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generator is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE void | LL_DMAMUX_SetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE void | LL_DMAMUX_SetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the Event Generation on DMAMUX channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_DisableEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
None

Definition at line 799 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_DisableRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Disable the Request Generator.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_DisableRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1055 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_DisableSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the synchronization mode.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_DisableSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
None

Definition at line 886 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the Event Generation on DMAMUX channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_EnableEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
None

Definition at line 770 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Enable the Request Generator.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_EnableRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1037 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_EnableSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the synchronization mode.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_EnableSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
None

Definition at line 857 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get the number of DMA request that will be autorized after a generation event.

Reference Manual to LL API cross reference:
RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Between Min_Data = 1 and Max_Data = 32

Definition at line 1158 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get the polarity of the signal on which the DMA request is generated.

Reference Manual to LL API cross reference:
RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_GEN_NO_EVENT
  • LL_DMAMUX_REQ_GEN_POL_RISING
  • LL_DMAMUX_REQ_GEN_POL_FALLING
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

Definition at line 1119 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get DMAMUX request ID for DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_AES_IN
  • LL_DMAMUX_REQ_AES_OUT
  • LL_DMAMUX_REQ_DAC1_CH1
  • LL_DMAMUX_REQ_DAC1_CH2
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C2_RX
  • LL_DMAMUX_REQ_I2C2_TX
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_TRIG_COM
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_TRIG
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM3_CH1
  • LL_DMAMUX_REQ_TIM3_CH2
  • LL_DMAMUX_REQ_TIM3_CH3
  • LL_DMAMUX_REQ_TIM3_CH4
  • LL_DMAMUX_REQ_TIM3_TRIG
  • LL_DMAMUX_REQ_TIM3_UP
  • LL_DMAMUX_REQ_TIM6_UP
  • LL_DMAMUX_REQ_TIM7_UP
  • LL_DMAMUX_REQ_TIM15_CH1
  • LL_DMAMUX_REQ_TIM15_CH2
  • LL_DMAMUX_REQ_TIM15_TRIG_COM
  • LL_DMAMUX_REQ_TIM15_UP
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_COM
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_COM
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_USART2_RX
  • LL_DMAMUX_REQ_USART2_TX
  • LL_DMAMUX_REQ_USART3_RX
  • LL_DMAMUX_REQ_USART3_TX
  • LL_DMAMUX_REQ_USART4_RX
  • LL_DMAMUX_REQ_USART4_TX
  • LL_DMAMUX_REQ_UCPD1_RX
  • LL_DMAMUX_REQ_UCPD1_TX
  • LL_DMAMUX_REQ_UCPD2_RX
  • LL_DMAMUX_REQ_UCPD2_TX

Definition at line 615 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

Reference Manual to LL API cross reference:
RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH2
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH3
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT
  • LL_DMAMUX_REQ_GEN_LPTIM2_OUT
  • LL_DMAMUX_REQ_GEN_TIM14_OC

Definition at line 1242 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get DMAMUX synchronization ID on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SYNC_ID LL_DMAMUX_GetSyncID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_SYNC_EXTI_LINE0
  • LL_DMAMUX_SYNC_EXTI_LINE1
  • LL_DMAMUX_SYNC_EXTI_LINE2
  • LL_DMAMUX_SYNC_EXTI_LINE3
  • LL_DMAMUX_SYNC_EXTI_LINE4
  • LL_DMAMUX_SYNC_EXTI_LINE5
  • LL_DMAMUX_SYNC_EXTI_LINE6
  • LL_DMAMUX_SYNC_EXTI_LINE7
  • LL_DMAMUX_SYNC_EXTI_LINE8
  • LL_DMAMUX_SYNC_EXTI_LINE9
  • LL_DMAMUX_SYNC_EXTI_LINE10
  • LL_DMAMUX_SYNC_EXTI_LINE11
  • LL_DMAMUX_SYNC_EXTI_LINE12
  • LL_DMAMUX_SYNC_EXTI_LINE13
  • LL_DMAMUX_SYNC_EXTI_LINE14
  • LL_DMAMUX_SYNC_EXTI_LINE15
  • LL_DMAMUX_SYNC_DMAMUX_CH0
  • LL_DMAMUX_SYNC_DMAMUX_CH1
  • LL_DMAMUX_SYNC_DMAMUX_CH2
  • LL_DMAMUX_SYNC_DMAMUX_CH3
  • LL_DMAMUX_SYNC_LPTIM1_OUT
  • LL_DMAMUX_SYNC_LPTIM2_OUT
  • LL_DMAMUX_SYNC_TIM14_OC

Definition at line 1020 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of the signal on which the DMA request is synchronized.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SPOL LL_DMAMUX_GetSyncPolarity
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_SYNC_NO_EVENT
  • LL_DMAMUX_SYNC_POL_RISING
  • LL_DMAMUX_SYNC_POL_FALLING
  • LL_DMAMUX_SYNC_POL_RISING_FALLING

Definition at line 741 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
Between Min_Data = 1 and Max_Data = 32

Definition at line 674 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the Event Generation on DMAMUX channel x is enabled or disabled.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
State of bit (1 or 0).

Definition at line 828 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Check if the Request Generator is enabled or disabled.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_IsEnabledRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
State of bit (1 or 0).

Definition at line 1073 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the synchronization mode is enabled or disabled.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_IsEnabledSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
State of bit (1 or 0).

Definition at line 915 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | RequestNb
 | ) |  |

Set the number of DMA request that will be autorized after a generation event.

Note:
This field can only be written when Generator is disabled.
Reference Manual to LL API cross reference:
RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
Parameters:
DMAMUXx | DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
RequestNb | This parameter must be a value between Min_Data = 1 and Max_Data = 32.
Return values:
None

Definition at line 1139 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the signal on which the DMA request is generated.

Reference Manual to LL API cross reference:
RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Polarity This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_NO_EVENT
  • LL_DMAMUX_REQ_GEN_POL_RISING
  • LL_DMAMUX_REQ_GEN_POL_FALLING
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
Return values:
None

Definition at line 1096 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetRequestID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | Request
 | ) |  |

Set DMAMUX request ID for DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Request This parameter can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_AES_IN
  • LL_DMAMUX_REQ_AES_OUT
  • LL_DMAMUX_REQ_DAC1_CH1
  • LL_DMAMUX_REQ_DAC1_CH2
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C2_RX
  • LL_DMAMUX_REQ_I2C2_TX
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_TRIG_COM
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_TRIG
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM3_CH1
  • LL_DMAMUX_REQ_TIM3_CH2
  • LL_DMAMUX_REQ_TIM3_CH3
  • LL_DMAMUX_REQ_TIM3_CH4
  • LL_DMAMUX_REQ_TIM3_TRIG
  • LL_DMAMUX_REQ_TIM3_UP
  • LL_DMAMUX_REQ_TIM6_UP
  • LL_DMAMUX_REQ_TIM7_UP
  • LL_DMAMUX_REQ_TIM15_CH1
  • LL_DMAMUX_REQ_TIM15_CH2
  • LL_DMAMUX_REQ_TIM15_TRIG_COM
  • LL_DMAMUX_REQ_TIM15_UP
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_COM
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_COM
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_USART2_RX
  • LL_DMAMUX_REQ_USART2_TX
  • LL_DMAMUX_REQ_USART3_RX
  • LL_DMAMUX_REQ_USART3_TX
  • LL_DMAMUX_REQ_USART4_RX
  • LL_DMAMUX_REQ_USART4_TX
  • LL_DMAMUX_REQ_UCPD1_RX
  • LL_DMAMUX_REQ_UCPD1_TX
  • LL_DMAMUX_REQ_UCPD2_RX
  • LL_DMAMUX_REQ_UCPD2_TX
Return values:
None

Definition at line 524 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | RequestSignalID
 | ) |  |

Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.

Reference Manual to LL API cross reference:
RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
RequestSignalID This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH2
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH3
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT
  • LL_DMAMUX_REQ_GEN_LPTIM2_OUT
  • LL_DMAMUX_REQ_GEN_TIM14_OC
Return values:
None

Definition at line 1200 of file stm32g0xx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetSyncID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | SyncID
 | ) |  |

Set DMAMUX synchronization ID on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SYNC_ID LL_DMAMUX_SetSyncID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
SyncID This parameter can be one of the following values:
  • LL_DMAMUX_SYNC_EXTI_LINE0
  • LL_DMAMUX_SYNC_EXTI_LINE1
  • LL_DMAMUX_SYNC_EXTI_LINE2
  • LL_DMAMUX_SYNC_EXTI_LINE3
  • LL_DMAMUX_SYNC_EXTI_LINE4
  • LL_DMAMUX_SYNC_EXTI_LINE5
  • LL_DMAMUX_SYNC_EXTI_LINE6
  • LL_DMAMUX_SYNC_EXTI_LINE7
  • LL_DMAMUX_SYNC_EXTI_LINE8
  • LL_DMAMUX_SYNC_EXTI_LINE9
  • LL_DMAMUX_SYNC_EXTI_LINE10
  • LL_DMAMUX_SYNC_EXTI_LINE11
  • LL_DMAMUX_SYNC_EXTI_LINE12
  • LL_DMAMUX_SYNC_EXTI_LINE13
  • LL_DMAMUX_SYNC_EXTI_LINE14
  • LL_DMAMUX_SYNC_EXTI_LINE15
  • LL_DMAMUX_SYNC_DMAMUX_CH0
  • LL_DMAMUX_SYNC_DMAMUX_CH1
  • LL_DMAMUX_SYNC_DMAMUX_CH2
  • LL_DMAMUX_SYNC_DMAMUX_CH3
  • LL_DMAMUX_SYNC_LPTIM1_OUT
  • LL_DMAMUX_SYNC_LPTIM2_OUT
  • LL_DMAMUX_SYNC_TIM14_OC
Return values:
None

Definition at line 968 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the signal on which the DMA request is synchronized.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SPOL LL_DMAMUX_SetSyncPolarity
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Polarity This parameter can be one of the following values:
  • LL_DMAMUX_SYNC_NO_EVENT
  • LL_DMAMUX_SYNC_POL_RISING
  • LL_DMAMUX_SYNC_POL_FALLING
  • LL_DMAMUX_SYNC_POL_RISING_FALLING
Return values:
None

Definition at line 708 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | RequestNb
 | ) |  |

Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
Parameters:
DMAMUXx | DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
RequestNb | This parameter must be a value between Min_Data = 1 and Max_Data = 32.
Return values:
None

Definition at line 645 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMAMUX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 3 Trigger Event Overrun Flag.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 0 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1627 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 1 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1639 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 2 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1651 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 3 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1663 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 0.

Reference Manual to LL API cross reference:
CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1469 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 1.

Reference Manual to LL API cross reference:
CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1481 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 10.

Reference Manual to LL API cross reference:
CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1600 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 11.

Reference Manual to LL API cross reference:
CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1614 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 2.

Reference Manual to LL API cross reference:
CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1493 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 3.

Reference Manual to LL API cross reference:
CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1505 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 4.

Reference Manual to LL API cross reference:
CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1517 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 5.

Reference Manual to LL API cross reference:
CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1530 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 6.

Reference Manual to LL API cross reference:
CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1544 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 7.

Reference Manual to LL API cross reference:
CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1558 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 8.

Reference Manual to LL API cross reference:
CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1572 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 9.

Reference Manual to LL API cross reference:
CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1586 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 0 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1421 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 1 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1433 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 2 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1445 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 3 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1457 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 0.

Reference Manual to LL API cross reference:
CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1263 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 1.

Reference Manual to LL API cross reference:
CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1275 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 10.

Reference Manual to LL API cross reference:
CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1394 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 11.

Reference Manual to LL API cross reference:
CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1408 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 2.

Reference Manual to LL API cross reference:
CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1287 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 3.

Reference Manual to LL API cross reference:
CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1299 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 4.

Reference Manual to LL API cross reference:
CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1311 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 5.

Reference Manual to LL API cross reference:
CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1324 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 6.

Reference Manual to LL API cross reference:
CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1338 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 7.

Reference Manual to LL API cross reference:
CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1352 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 8.

Reference Manual to LL API cross reference:
CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1366 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 9.

Reference Manual to LL API cross reference:
CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1380 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT_Management

Functions
IT_Management
DMAMUX Exported Functions

Functions

__STATIC_INLINE void | LL_DMAMUX_EnableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_DisableIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1792 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_DisableIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_DisableIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
None

Definition at line 1729 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_EnableIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1775 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_EnableIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
None

Definition at line 1700 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
State of bit (1 or 0).

Definition at line 1809 of file stm32g0xx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
  • LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
  • All the next values are only available on chip which support DMA2:
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
Return values:
State of bit (1 or 0).

Definition at line 1758 of file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Define Documentation

#define IS_LL_EXTI_LINE_0_31 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)

Definition at line 46 of file stm32g0xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_LINE_32_63 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)

Definition at line 48 of file stm32g0xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_MODE_IT)            \
                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))

Definition at line 50 of file stm32g0xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_TRIGGER ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))

Definition at line 55 of file stm32g0xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_EXTI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_EXTI_InitTypeDef Struct Reference
EXTI Exported Init structure

#include <stm32g0xx_ll_exti.h>

Data Fields

uint32_t | Line_0_31
uint32_t | Line_32_63
FunctionalState | LineCommand
uint8_t | Mode
uint8_t | Trigger

Detailed Description

Definition at line 59 of file stm32g0xx_ll_exti.h.

Field Documentation

uint32_t LL_EXTI_InitTypeDef::Line_0_31

Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 This parameter can be any combination of LINE

Definition at line 62 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint32_t LL_EXTI_InitTypeDef::Line_32_63

Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 This parameter can be any combination of LINE

Definition at line 65 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

FunctionalState LL_EXTI_InitTypeDef::LineCommand

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 68 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Mode

Specifies the mode for the EXTI lines. This parameter can be a value of Mode.

Definition at line 71 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of Edge Trigger.

Definition at line 74 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_exti.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI CONFIG PORT

Defines
EXTI CONFIG PORT
LINE

Defines

#define | LL_EXTI_CONFIG_PORTA 0U
#define | LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0
#define | LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1
#define | LL_EXTI_CONFIG_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0)
#define | LL_EXTI_CONFIG_PORTE EXTI_EXTICR1_EXTI0_2
#define | LL_EXTI_CONFIG_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0)

Define Documentation

#define LL_EXTI_CONFIG_PORTA 0U

EXTI PORT A

Definition at line 181 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0

EXTI PORT B

Definition at line 182 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1

EXTI PORT C

Definition at line 183 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0)

EXTI PORT D

Definition at line 185 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_PORTE EXTI_EXTICR1_EXTI0_2

EXTI PORT E

Definition at line 188 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0)

EXTI PORT F

Definition at line 190 of file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI CONFIG LINE

Defines
EXTI CONFIG LINE
LINE

Defines

#define | LL_EXTI_CONFIG_LINE0 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)
#define | LL_EXTI_CONFIG_LINE1 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)
#define | LL_EXTI_CONFIG_LINE2 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)
#define | LL_EXTI_CONFIG_LINE3 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)
#define | LL_EXTI_CONFIG_LINE4 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)
#define | LL_EXTI_CONFIG_LINE5 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)
#define | LL_EXTI_CONFIG_LINE6 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)
#define | LL_EXTI_CONFIG_LINE7 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)
#define | LL_EXTI_CONFIG_LINE8 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)
#define | LL_EXTI_CONFIG_LINE9 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)
#define | LL_EXTI_CONFIG_LINE10 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)
#define | LL_EXTI_CONFIG_LINE11 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)
#define | LL_EXTI_CONFIG_LINE12 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)
#define | LL_EXTI_CONFIG_LINE13 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)
#define | LL_EXTI_CONFIG_LINE14 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)
#define | LL_EXTI_CONFIG_LINE15 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)

Define Documentation

#define LL_EXTI_CONFIG_LINE0 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)

EXTI_POSITION_0 | EXTICR[0]

Definition at line 198 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE1 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)

EXTI_POSITION_8 | EXTICR[0]

Definition at line 199 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE10 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)

EXTI_POSITION_16 | EXTICR[2]

Definition at line 208 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE11 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)

EXTI_POSITION_24 | EXTICR[2]

Definition at line 209 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE12 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)

EXTI_POSITION_0 | EXTICR[3]

Definition at line 210 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE13 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)

EXTI_POSITION_8 | EXTICR[3]

Definition at line 211 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE14 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)

EXTI_POSITION_16 | EXTICR[3]

Definition at line 212 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE15 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)

EXTI_POSITION_24 | EXTICR[3]

Definition at line 213 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE2 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)

EXTI_POSITION_16 | EXTICR[0]

Definition at line 200 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE3 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)

EXTI_POSITION_24 | EXTICR[0]

Definition at line 201 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE4 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)

EXTI_POSITION_0 | EXTICR[1]

Definition at line 202 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE5 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)

EXTI_POSITION_8 | EXTICR[1]

Definition at line 203 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE6 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)

EXTI_POSITION_16 | EXTICR[1]

Definition at line 204 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE7 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)

EXTI_POSITION_24 | EXTICR[1]

Definition at line 205 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE8 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)

EXTI_POSITION_0 | EXTICR[2]

Definition at line 206 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_CONFIG_LINE9 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)

EXTI_POSITION_8 | EXTICR[2]

Definition at line 207 of file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LINE

Modules | Defines
LINE
EXTI Exported Constants

Modules

EXTI CONFIG PORT
EXTI CONFIG LINE

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR1_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR1_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_31 EXTI_IMR1_IM31
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM
#define | LL_EXTI_LINE_32 EXTI_IMR2_IM32
#define | LL_EXTI_LINE_33 EXTI_IMR2_IM33
#define | LL_EXTI_LINE_34 EXTI_IMR2_IM34
#define | LL_EXTI_LINE_35 EXTI_IMR2_IM35
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM
#define | LL_EXTI_LINE_ALL 0xFFFFFFFFU
#define | LL_EXTI_LINE_NONE 0x00000000U

Define Documentation

#define LL_EXTI_LINE_0 EXTI_IMR1_IM0

Extended line 0

Definition at line 91 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_1 EXTI_IMR1_IM1

Extended line 1

Definition at line 92 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_10 EXTI_IMR1_IM10

Extended line 10

Definition at line 101 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_11 EXTI_IMR1_IM11

Extended line 11

Definition at line 102 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_12 EXTI_IMR1_IM12

Extended line 12

Definition at line 103 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_13 EXTI_IMR1_IM13

Extended line 13

Definition at line 104 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_14 EXTI_IMR1_IM14

Extended line 14

Definition at line 105 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_15 EXTI_IMR1_IM15

Extended line 15

Definition at line 106 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_16 EXTI_IMR1_IM16

Extended line 16

Definition at line 108 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_17 EXTI_IMR1_IM17

Extended line 17

Definition at line 111 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_18 EXTI_IMR1_IM18

Extended line 18

Definition at line 114 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_19 EXTI_IMR1_IM19

Extended line 19

Definition at line 116 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_2 EXTI_IMR1_IM2

Extended line 2

Definition at line 93 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_20 EXTI_IMR1_IM20

Extended line 20

Definition at line 118 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_21 EXTI_IMR1_IM21

Extended line 21

Definition at line 121 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_22 EXTI_IMR1_IM22

Extended line 22

Definition at line 124 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_23 EXTI_IMR1_IM23

Extended line 23

Definition at line 126 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_24 EXTI_IMR1_IM24

Extended line 24

Definition at line 128 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_25 EXTI_IMR1_IM25

Extended line 25

Definition at line 131 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_26 EXTI_IMR1_IM26

Extended line 26

Definition at line 134 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_27 EXTI_IMR1_IM27

Extended line 27

Definition at line 137 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_28 EXTI_IMR1_IM28

Extended line 28

Definition at line 140 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_29 EXTI_IMR1_IM29

Extended line 29

Definition at line 143 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_3 EXTI_IMR1_IM3

Extended line 3

Definition at line 94 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_30 EXTI_IMR1_IM30

Extended line 30

Definition at line 146 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_31 EXTI_IMR1_IM31

Extended line 31

Definition at line 149 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_32 EXTI_IMR2_IM32

Extended line 32

Definition at line 154 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_33 EXTI_IMR2_IM33

Extended line 33

Definition at line 157 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_34 EXTI_IMR2_IM34

Extended line 34

Definition at line 160 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_35 EXTI_IMR2_IM35

Extended line 35

Definition at line 163 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_36 EXTI_IMR2_IM36

Extended line 36

Definition at line 166 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_4 EXTI_IMR1_IM4

Extended line 4

Definition at line 95 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_5 EXTI_IMR1_IM5

Extended line 5

Definition at line 96 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_6 EXTI_IMR1_IM6

Extended line 6

Definition at line 97 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_7 EXTI_IMR1_IM7

Extended line 7

Definition at line 98 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_8 EXTI_IMR1_IM8

Extended line 8

Definition at line 99 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_9 EXTI_IMR1_IM9

Extended line 9

Definition at line 100 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_ALL 0xFFFFFFFFU

All Extended line

Definition at line 172 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM

All Extended line not reserved

Definition at line 151 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM

All Extended line not reserved

Definition at line 169 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_LINE_NONE 0x00000000U

None Extended line

Definition at line 175 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Mode

Defines
Mode
EXTI Exported Constants

Defines

#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Define Documentation

#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U)

Event Mode

Definition at line 226 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_MODE_IT ((uint8_t)0x00U)

Interrupt Mode

Definition at line 225 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Interrupt & Event Mode

Definition at line 227 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Edge Trigger

Defines
Edge Trigger
EXTI Exported Constants

Defines

#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Define Documentation

#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)

Trigger Falling Mode

Definition at line 237 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)

No Trigger Mode

Definition at line 235 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)

Trigger Rising Mode

Definition at line 236 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Trigger Rising & Falling Mode

Definition at line 238 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
EXTI Exported Macros

Defines

#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Define Documentation

#define LL_EXTI_ReadReg ( __REG__ ) READ_REG(EXTI->__REG__)

Read a value in EXTI register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 274 of file stm32g0xx_ll_exti.h.

#define LL_EXTI_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(EXTI->__REG__, (__VALUE__))

Write a value in EXTI register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 267 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_DeInit().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT_Management

Functions
IT_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableIT_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_DisableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 402 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableIT_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines 32 & 33) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_DisableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_ALL_32_63
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 424 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_EnableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 334 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines 32 & 33) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_EnableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_ALL_32_63
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 356 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_IsEnabledIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 470 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines 32 & 33) is set to 1 in order to enable the interrupt by default.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_IsEnabledIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_ALL_32_63
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 491 of file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Event_Management

Functions
Event_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableEvent_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_DisableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 604 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableEvent_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_DisableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_ALL_32_63
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 623 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_EnableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 542 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_EnableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_ALL_32_63
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 562 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 665 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_ALL_32_63
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 684 of file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Rising_Trigger_Management

Functions
Rising_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 794 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 816 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 732 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 753 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 849 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 863 of file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Falling_Trigger_Management

Functions
Falling_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 971 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 991 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 911 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 932 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1024 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1038 of file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Software_Interrupt_Management

Functions
Software_Interrupt_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 0 to 31.

Note:
If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1083 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 32 to 63.

Note:
If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1102 of file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Flag_Management

Functions
Flag_Management
EXTI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFallingFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFallingFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFallingFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Falling Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFallingFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Falling Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFallingFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Falling Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFallingFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Falling Flags for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveRisingFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveRisingFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadRisingFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Rising Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadRisingFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Rising Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearRisingFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Rising Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearRisingFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Rising Flags for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31 ( uint32_t ExtiLine )

Clear ExtLine Falling Flags for Lines in range 0 to 31.

Note:
This bit is set when the falling edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1247 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63 ( uint32_t ExtiLine )

Clear ExtLine Falling Flags for Lines in range 32 to 63.

Note:
This bit is set when the falling edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
FPR2 FPIFx LL_EXTI_ClearFallingFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1263 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31 ( uint32_t ExtiLine )

Clear ExtLine Rising Flags for Lines in range 0 to 31.

Note:
This bit is set when the Rising edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1400 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63 ( uint32_t ExtiLine )

Clear ExtLine Rising Flags for Lines in range 32 to 63.

Note:
This bit is set when the Rising edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
RPR2 RPIFx LL_EXTI_ClearRisingFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1416 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31 ( uint32_t ExtiLine )

Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31.

Note:
This bit is set when the falling edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1145 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_IRQHandler().

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63 ( uint32_t ExtiLine )

Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63.

Note:
This bit is set when the falling edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
FPR2 FPIFx LL_EXTI_IsActiveFallingFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1161 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31 ( uint32_t ExtiLine )

Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31.

Note:
This bit is set when the Rising edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1298 of file stm32g0xx_ll_exti.h.

Referenced by HAL_COMP_IRQHandler().

__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63 ( uint32_t ExtiLine )

Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63.

Note:
This bit is set when the Rising edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
RPR2 RPIFx LL_EXTI_IsActiveRisingFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1314 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31 ( uint32_t ExtiLine )

Read ExtLine Combination Falling Flag for Lines in range 0 to 31.

Note:
This bit is set when the falling edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1196 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63 ( uint32_t ExtiLine )

Read ExtLine Combination Falling Flag for Lines in range 32 to 63.

Note:
This bit is set when the falling edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
FPR2 FPIFx LL_EXTI_ReadFallingFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1212 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31 ( uint32_t ExtiLine )

Read ExtLine Combination Rising Flag for Lines in range 0 to 31.

Note:
This bit is set when the Rising edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_20
Note:
Please check each device line mapping for EXTI Line availability
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1349 of file stm32g0xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63 ( uint32_t ExtiLine )

Read ExtLine Combination Rising Flag for Lines in range 32 to 63.

Note:
This bit is set when the Rising edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
RPR2 RPIFx LL_EXTI_ReadRisingFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_34
Note:
Please check each device line mapping for EXTI Line availability
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1365 of file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EF configuration functions

Functions
EF configuration functions
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_EXTI_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.

Function Documentation

__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource ( uint32_t Line )

Get the configured defined for specific EXTI Line.

Reference Manual to LL API cross reference:
EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource
EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource
EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource
EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource
EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource
EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource
EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource
EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource
EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource
EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource
EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource
EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource
EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource
EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource
EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource
EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource
Parameters:
Line This parameter can be one of the following values:
  • LL_EXTI_CONFIG_LINE0
  • LL_EXTI_CONFIG_LINE1
  • LL_EXTI_CONFIG_LINE2
  • LL_EXTI_CONFIG_LINE3
  • LL_EXTI_CONFIG_LINE4
  • LL_EXTI_CONFIG_LINE5
  • LL_EXTI_CONFIG_LINE6
  • LL_EXTI_CONFIG_LINE7
  • LL_EXTI_CONFIG_LINE8
  • LL_EXTI_CONFIG_LINE9
  • LL_EXTI_CONFIG_LINE10
  • LL_EXTI_CONFIG_LINE11
  • LL_EXTI_CONFIG_LINE12
  • LL_EXTI_CONFIG_LINE13
  • LL_EXTI_CONFIG_LINE14
  • LL_EXTI_CONFIG_LINE15
Return values:
Returned value can be one of the following values:
  • EXTI CONFIG PORT
(*) value not defined in all devices

Definition at line 1515 of file stm32g0xx_ll_exti.h.

References LL_EXTI_REGISTER_PINPOS_SHFT.

__STATIC_INLINE void LL_EXTI_SetEXTISource | ( | uint32_t | Port,
 |  | uint32_t | Line
 | ) |  |

Configure source input for the EXTI external interrupt.

Reference Manual to LL API cross reference:
EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource
EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource
EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource
EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource
EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource
EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource
EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource
EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource
EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource
EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource
EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource
EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource
EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource
EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource
EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource
EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource
Parameters:
Port This parameter can be one of the following values:
  • EXTI CONFIG PORT
(*) value not defined in all devices
Line This parameter can be one of the following values:
  • LL_EXTI_CONFIG_LINE0
  • LL_EXTI_CONFIG_LINE1
  • LL_EXTI_CONFIG_LINE2
  • LL_EXTI_CONFIG_LINE3
  • LL_EXTI_CONFIG_LINE4
  • LL_EXTI_CONFIG_LINE5
  • LL_EXTI_CONFIG_LINE6
  • LL_EXTI_CONFIG_LINE7
  • LL_EXTI_CONFIG_LINE8
  • LL_EXTI_CONFIG_LINE9
  • LL_EXTI_CONFIG_LINE10
  • LL_EXTI_CONFIG_LINE11
  • LL_EXTI_CONFIG_LINE12
  • LL_EXTI_CONFIG_LINE13
  • LL_EXTI_CONFIG_LINE14
  • LL_EXTI_CONFIG_LINE15
Return values:
None

Definition at line 1470 of file stm32g0xx_ll_exti.h.

References LL_EXTI_REGISTER_PINPOS_SHFT.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
EXTI Exported Functions

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Function Documentation

uint32_t LL_EXTI_DeInit ( void )

De-initialize the EXTI registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • 0x00: EXTI registers are de-initialized

Definition at line 80 of file stm32g0xx_ll_exti.c.

References LL_EXTI_WriteReg.

uint32_t LL_EXTI_Init ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.

Parameters:
EXTI_InitStruct pointer to a LL_EXTI_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • 0x00: EXTI registers are initialized
  • any other value : wrong configuration

Definition at line 143 of file stm32g0xx_ll_exti.c.

References assert_param, IS_LL_EXTI_LINE_0_31, IS_LL_EXTI_LINE_32_63, IS_LL_EXTI_MODE, IS_LL_EXTI_TRIGGER, LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableEvent_32_63(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableIT_32_63(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableEvent_32_63(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableIT_32_63(), LL_EXTI_EnableRisingTrig_0_31(), LL_EXTI_LINE_NONE, LL_EXTI_MODE_EVENT, LL_EXTI_MODE_IT, LL_EXTI_MODE_IT_EVENT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_TRIGGER_NONE, LL_EXTI_TRIGGER_RISING, LL_EXTI_TRIGGER_RISING_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

void LL_EXTI_StructInit ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Set each LL_EXTI_InitTypeDef field to default value.

Parameters:
EXTI_InitStruct Pointer to a LL_EXTI_InitTypeDef structure.
Return values:
None

Definition at line 263 of file stm32g0xx_ll_exti.c.

References LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_LINE_NONE, LL_EXTI_MODE_IT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EXTI

Modules | Defines
EXTI
STM32G0xx_LL_Driver

Modules

EXTI Private Macros
EXTI Exported Init structure
EXTI Exported Constants
EXTI Exported Macros
EXTI Exported Functions

Defines

#define LL_EXTI_REGISTER_PINPOS_SHFT 16u

Define Documentation

#define LL_EXTI_REGISTER_PINPOS_SHFT 16u

Define used to shift pin position in EXTICR register

Definition at line 43 of file stm32g0xx_ll_exti.h.

Referenced by LL_EXTI_GetEXTISource(), and LL_EXTI_SetEXTISource().

Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15. More...

Defines

#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Detailed Description

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15.

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : LL_GPIO_Init.

Define Documentation

#define IS_LL_GPIO_ALTERNATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_AF_0  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_10 ))

Definition at line 71 of file stm32g0xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))

Definition at line 53 of file stm32g0xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_OUTPUT_TYPE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))

Definition at line 58 of file stm32g0xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PIN ( __VALUE__ ) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))

Definition at line 51 of file stm32g0xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PULL ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_PULL_NO)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))

Definition at line 66 of file stm32g0xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_SPEED ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 61 of file stm32g0xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_GPIO_InitTypeDef Struct Reference
GPIO Exported Init structures

LL GPIO Init Structure definition. More...

#include <stm32g0xx_ll_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Speed
uint32_t | OutputType
uint32_t | Pull
uint32_t | Alternate

Detailed Description

LL GPIO Init Structure definition.

Definition at line 71 of file stm32g0xx_ll_gpio.h.

Field Documentation

uint32_t LL_GPIO_InitTypeDef::Alternate

Specifies the Peripheral to be connected to the selected pins. This parameter can be a value of Alternate Function.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().

Definition at line 96 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of Mode.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinMode().

Definition at line 76 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::OutputType

Specifies the operating output type for the selected pins. This parameter can be a value of Output Type.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinOutputType().

Definition at line 86 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of PIN

Definition at line 73 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pull

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of Pull Up Pull Down.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinPull().

Definition at line 91 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of Output Speed.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinSpeed().

Definition at line 81 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_gpio.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PIN

Defines
PIN
GPIO Exported Constants

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL

Define Documentation

#define LL_GPIO_PIN_0 GPIO_BSRR_BS0

Select pin 0

Definition at line 115 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_1 GPIO_BSRR_BS1

Select pin 1

Definition at line 116 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_10 GPIO_BSRR_BS10

Select pin 10

Definition at line 125 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_11 GPIO_BSRR_BS11

Select pin 11

Definition at line 126 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_12 GPIO_BSRR_BS12

Select pin 12

Definition at line 127 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_13 GPIO_BSRR_BS13

Select pin 13

Definition at line 128 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_14 GPIO_BSRR_BS14

Select pin 14

Definition at line 129 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_15 GPIO_BSRR_BS15

Select pin 15

Definition at line 130 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_2 GPIO_BSRR_BS2

Select pin 2

Definition at line 117 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_3 GPIO_BSRR_BS3

Select pin 3

Definition at line 118 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_4 GPIO_BSRR_BS4

Select pin 4

Definition at line 119 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_5 GPIO_BSRR_BS5

Select pin 5

Definition at line 120 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_6 GPIO_BSRR_BS6

Select pin 6

Definition at line 121 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_7 GPIO_BSRR_BS7

Select pin 7

Definition at line 122 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_8 GPIO_BSRR_BS8

Select pin 8

Definition at line 123 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_PIN_9 GPIO_BSRR_BS9

Select pin 9

Definition at line 124 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PIN_ALL
Value:
(GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
                                           GPIO_BSRR_BS15)

Select all pins

Definition at line 131 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Mode

Defines
Mode
GPIO Exported Constants

Defines

#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Define Documentation

#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1

Select alternate function mode

Definition at line 146 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Select analog mode

Definition at line 147 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_MODE_INPUT (0x00000000U)

Select input mode

Definition at line 144 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0

Select output mode

Definition at line 145 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Output Type

Defines
Output Type
GPIO Exported Constants

Defines

#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Define Documentation

#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Select open-drain as output type

Definition at line 156 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)

Select push-pull as output type

Definition at line 155 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Output Speed

Defines
Output Speed
GPIO Exported Constants

Defines

#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Define Documentation

#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1

Select I/O fast output speed

Definition at line 166 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U)

Select I/O low output speed

Definition at line 164 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0

Select I/O medium output speed

Definition at line 165 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Select I/O high output speed

Definition at line 167 of file stm32g0xx_ll_gpio.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Pull Up Pull Down

Defines
Pull Up Pull Down
GPIO Exported Constants

Defines

#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Define Documentation

#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Select I/O pull down

Definition at line 182 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_PULL_NO (0x00000000U)

Select I/O no pull

Definition at line 180 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0

Select I/O pull up

Definition at line 181 of file stm32g0xx_ll_gpio.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Alternate Function

Defines
Alternate Function
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)

Define Documentation

#define LL_GPIO_AF_0 (0x0000000U)

Select alternate function 0

Definition at line 190 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_AF_1 (0x0000001U)

Select alternate function 1

Definition at line 191 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_10 (0x000000AU)

Select alternate function 10

Definition at line 201 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_2 (0x0000002U)

Select alternate function 2

Definition at line 192 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_3 (0x0000003U)

Select alternate function 3

Definition at line 193 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_4 (0x0000004U)

Select alternate function 4

Definition at line 194 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_5 (0x0000005U)

Select alternate function 5

Definition at line 195 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_6 (0x0000006U)

Select alternate function 6

Definition at line 196 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_7 (0x0000007U)

Select alternate function 7

Definition at line 197 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_8 (0x0000008U)

Select alternate function 8

Definition at line 199 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_AF_9 (0x0000009U)

Select alternate function 9

Definition at line 200 of file stm32g0xx_ll_gpio.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: GPIO Exported Constants

Modules | Defines
GPIO Exported Constants
GPIO

Modules

PIN
Mode
Output Type
Output Speed
Pull Up Pull Down
Alternate Function

Defines

#define | LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define | LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define | LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define | LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH

Define Documentation

#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH

Definition at line 173 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 174 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW

Definition at line 171 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM

Definition at line 172 of file stm32g0xx_ll_gpio.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
GPIO Exported Macros

Defines

#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Define Documentation

#define LL_GPIO_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 235 of file stm32g0xx_ll_gpio.h.

#define LL_GPIO_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 227 of file stm32g0xx_ll_gpio.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Port Configuration

Functions
Port Configuration
GPIO Exported Functions

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_GetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7

Definition at line 583 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF7 depending on target.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_GetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7

Definition at line 645 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_GetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG

Definition at line 317 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_GetPinOutputType
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
Returned value can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN

Definition at line 385 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_GetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN

Definition at line 523 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 458 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked ( GPIO_TypeDef * GPIOx )

Return 1 if one of the pin of a dedicated port is locked.

else return 0.

Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_IsAnyPinLocked
Parameters:
GPIOx GPIO Port
Return values:
State of bit (1 or 0).

Definition at line 728 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return 1 if all pins passed as parameter, of a dedicated port, are locked.

else Return 0.

Reference Manual to LL API cross reference:
LCKR LCKy LL_GPIO_IsPinLocked
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 717 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Lock configuration of several pins for a dedicated port.

Note:
When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset.
Each lock bit freezes a specific configuration register (control and alternate function registers).
Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_LockPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 682 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Note:
Possible values are from AF0 to AF7 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_SetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
Return values:
None

Definition at line 554 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF7 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_SetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
Return values:
None

Definition at line 615 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Mode
 | ) |  |

Configure gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_SetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Mode This parameter can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG
Return values:
None

Definition at line 283 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask,
 |  | uint32_t | OutputType
 | ) |  |

Configure gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_SetPinOutputType
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
OutputType This parameter can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN
Return values:
None

Definition at line 351 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Pull
 | ) |  |

Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_SetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Pull This parameter can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN
Return values:
None

Definition at line 491 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Speed
 | ) |  |

Configure gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Speed This parameter can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH
Return values:
None

Definition at line 422 of file stm32g0xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Access

Functions
Data Access
GPIO Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_IsInputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 776 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_IsOutputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 828 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort ( GPIO_TypeDef * GPIOx )

Return full input data register value for a dedicated port.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_ReadInputPort
Parameters:
GPIOx GPIO Port
Return values:
Input data register value of port

Definition at line 747 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort ( GPIO_TypeDef * GPIOx )

Return full output data register value for a dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_ReadOutputPort
Parameters:
GPIOx GPIO Port
Return values:
Output data register value of port

Definition at line 799 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_ResetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to low level on dedicated gpio port.

Reference Manual to LL API cross reference:
BRR BRy LL_GPIO_ResetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 886 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to high level on dedicated gpio port.

Reference Manual to LL API cross reference:
BSRR BSy LL_GPIO_SetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 857 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Toggle data value for several pin of dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_TogglePin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 915 of file stm32g0xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_WriteOutputPort | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PortValue
 | ) |  |

Write output data register for the port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_WriteOutputPort
Parameters:
GPIOx | GPIO Port
PortValue | Level value for each pin of the port
Return values:
None

Definition at line 788 of file stm32g0xx_ll_gpio.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_GPIO_DeInit ( GPIO_TypeDef * GPIOx )

De-initialize GPIO registers (Registers restored to their default values).

Parameters:
GPIOx GPIO Port
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are de-initialized
  • ERROR: Wrong GPIO Port

Definition at line 114 of file stm32g0xx_ll_gpio.c.

References assert_param, LL_IOP_GRP1_ForceReset(), LL_IOP_GRP1_PERIPH_GPIOA, LL_IOP_GRP1_PERIPH_GPIOB, LL_IOP_GRP1_PERIPH_GPIOC, LL_IOP_GRP1_PERIPH_GPIOD, LL_IOP_GRP1_PERIPH_GPIOE, LL_IOP_GRP1_PERIPH_GPIOF, and LL_IOP_GRP1_ReleaseReset().

ErrorStatus LL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | LL_GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.

Parameters:
GPIOx | GPIO Port
GPIO_InitStruct | pointer to a LL_GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
  • ERROR: Not applicable

Definition at line 175 of file stm32g0xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, assert_param, IS_LL_GPIO_ALTERNATE, IS_LL_GPIO_MODE, IS_LL_GPIO_OUTPUT_TYPE, IS_LL_GPIO_PIN, IS_LL_GPIO_PULL, IS_LL_GPIO_SPEED, LL_GPIO_MODE_ALTERNATE, LL_GPIO_MODE_OUTPUT, LL_GPIO_PIN_8, LL_GPIO_SetAFPin_0_7(), LL_GPIO_SetAFPin_8_15(), LL_GPIO_SetPinMode(), LL_GPIO_SetPinOutputType(), LL_GPIO_SetPinPull(), LL_GPIO_SetPinSpeed(), LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

void LL_GPIO_StructInit ( LL_GPIO_InitTypeDef * GPIO_InitStruct )

Set each LL_GPIO_InitTypeDef field to default value.

Parameters:
GPIO_InitStruct pointer to a LL_GPIO_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 248 of file stm32g0xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, LL_GPIO_AF_0, LL_GPIO_MODE_ANALOG, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PIN_ALL, LL_GPIO_PULL_NO, LL_GPIO_SPEED_FREQ_LOW, LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

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STM32G0C1xx HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
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STM32G0C1xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Define Documentation

#define IS_LL_I2C_ANALOG_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))

Definition at line 52 of file stm32g0xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_DIGITAL_FILTER ( __VALUE__ ) ((__VALUE__) <= 0x0000000FU)

Definition at line 55 of file stm32g0xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRESS1 ( __VALUE__ ) ((__VALUE__) <= 0x000003FFU)

Definition at line 57 of file stm32g0xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))

Definition at line 62 of file stm32g0xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_PERIPHERAL_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_MODE_I2C)          || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))

Definition at line 47 of file stm32g0xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_TYPE_ACKNOWLEDGE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ACK) || \
                                                 ((__VALUE__) == LL_I2C_NACK))

Definition at line 59 of file stm32g0xx_ll_i2c.c.

Referenced by LL_I2C_Init().

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STM32G0C1xx HAL User Manual: LL_I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2C_InitTypeDef Struct Reference
I2C Exported Init structure

#include <stm32g0xx_ll_i2c.h>

Data Fields

uint32_t | PeripheralMode
uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | DigitalFilter
uint32_t | OwnAddress1
uint32_t | TypeAcknowledge
uint32_t | OwnAddrSize

Detailed Description

Definition at line 66 of file stm32g0xx_ll_i2c.h.

Field Documentation

uint32_t LL_I2C_InitTypeDef::AnalogFilter

Enables or disables analog noise filter. This parameter can be a value of Analog Filter Selection.

This feature can be modified afterwards using unitary functions LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter().

Definition at line 81 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::DigitalFilter

Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.

This feature can be modified afterwards using unitary function LL_I2C_SetDigitalFilter().

Definition at line 87 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddress1

Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 93 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddrSize

Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of Own Address 1 Length.

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 106 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::PeripheralMode

Specifies the peripheral mode. This parameter can be a value of Peripheral Mode.

This feature can be modified afterwards using unitary function LL_I2C_SetMode().

Definition at line 68 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::Timing

Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro __LL_I2C_CONVERT_TIMINGS().

This feature can be modified afterwards using unitary function LL_I2C_SetTiming().

Definition at line 74 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::TypeAcknowledge

Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. This parameter can be a value of Acknowledge Generation.

This feature can be modified afterwards using unitary function LL_I2C_AcknowledgeNextData().

Definition at line 99 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_i2c.h
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STM32G0C1xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_WriteReg function. More...

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Detailed Description

Flags defines which can be used with LL_I2C_WriteReg function.

Define Documentation

#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF

Address Matched flag

Definition at line 126 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Alert flag

Definition at line 134 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF

Arbitration Lost flag

Definition at line 130 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF

Bus error flag

Definition at line 129 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF

Not Acknowledge flag

Definition at line 127 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF

Overrun/Underrun flag

Definition at line 131 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ICR_PECCF I2C_ICR_PECCF

PEC error flag

Definition at line 132 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF

Stop detection flag

Definition at line 128 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF

Timeout detection flag

Definition at line 133 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_ReadReg function. More...

Defines

#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY

Detailed Description

Flags defines which can be used with LL_I2C_ReadReg function.

Define Documentation

#define LL_I2C_ISR_ADDR I2C_ISR_ADDR

Address matched (slave mode)

Definition at line 146 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_ALERT I2C_ISR_ALERT

SMBus alert (SMBus mode)

Definition at line 156 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_ARLO I2C_ISR_ARLO

Arbitration lost

Definition at line 152 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_BERR I2C_ISR_BERR

Bus error

Definition at line 151 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_BUSY I2C_ISR_BUSY

Bus busy

Definition at line 157 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_NACKF I2C_ISR_NACKF

Not Acknowledge received flag

Definition at line 147 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_OVR I2C_ISR_OVR

Overrun/Underrun (slave mode)

Definition at line 153 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_PECERR I2C_ISR_PECERR

PEC Error in reception (SMBus mode)

Definition at line 154 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_RXNE I2C_ISR_RXNE

Receive data register not empty

Definition at line 145 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_STOPF I2C_ISR_STOPF

Stop detection flag

Definition at line 148 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_TC I2C_ISR_TC

Transfer Complete (master mode)

Definition at line 149 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_TCR I2C_ISR_TCR

Transfer Complete Reload

Definition at line 150 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT

Timeout detection flag (SMBus mode)

Definition at line 155 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_TXE I2C_ISR_TXE

Transmit data register empty

Definition at line 143 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ISR_TXIS I2C_ISR_TXIS

Transmit interrupt status

Definition at line 144 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
I2C Exported Constants

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions. More...

Defines

#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Detailed Description

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Define Documentation

#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE

Address match Interrupt enable (slave only)

Definition at line 168 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Error interrupts enable

Definition at line 172 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE

Not acknowledge received Interrupt enable

Definition at line 169 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_CR1_RXIE I2C_CR1_RXIE

RX Interrupt enable

Definition at line 167 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE

STOP detection Interrupt enable

Definition at line 170 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_CR1_TCIE I2C_CR1_TCIE

Transfer Complete interrupt enable

Definition at line 171 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_CR1_TXIE I2C_CR1_TXIE

TX Interrupt enable

Definition at line 166 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Peripheral Mode

Defines
Peripheral Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

Define Documentation

#define LL_I2C_MODE_I2C 0x00000000U

I2C Master or Slave mode

Definition at line 180 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U

SMBus Device default mode (Default address not acknowledge)

Definition at line 182 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

SMBus Device Default address acknowledge

Definition at line 184 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN

SMBus Host address acknowledge

Definition at line 181 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Analog Filter Selection

Defines
Analog Filter Selection
I2C Exported Constants

Defines

#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Analog filter is disabled.

Definition at line 193 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U

Analog filter is enabled.

Definition at line 192 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

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STM32G0C1xx HAL User Manual: Master Addressing Mode

Defines
Master Addressing Mode
I2C Exported Constants

Defines

#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Master operates in 10-bit addressing mode.

Definition at line 202 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U

Master operates in 7-bit addressing mode.

Definition at line 201 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Own Address 1 Length

Defines
Own Address 1 Length
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Define Documentation

#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Own address 1 is a 10-bit address.

Definition at line 211 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U

Own address 1 is a 7-bit address.

Definition at line 210 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

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STM32G0C1xx HAL User Manual: Own Address 2 Masks

Defines
Own Address 2 Masks
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

Define Documentation

#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01

Only Address2 bits[7:2] are compared.

Definition at line 220 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02

Only Address2 bits[7:3] are compared.

Definition at line 221 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03

Only Address2 bits[7:4] are compared.

Definition at line 222 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04

Only Address2 bits[7:5] are compared.

Definition at line 223 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05

Only Address2 bits[7:6] are compared.

Definition at line 224 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06

Only Address2 bits[7] are compared.

Definition at line 225 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

No comparison is done. All Address2 are acknowledged.

Definition at line 226 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK

Own Address2 No mask.

Definition at line 219 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Acknowledge Generation

Defines
Acknowledge Generation
I2C Exported Constants

Defines

#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK

Define Documentation

#define LL_I2C_ACK 0x00000000U

ACK is sent after current received byte.

Definition at line 235 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_NACK I2C_CR2_NACK

NACK is sent after current received byte.

Definition at line 236 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

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STM32G0C1xx HAL User Manual: Slave Address Length

Defines
Slave Address Length
I2C Exported Constants

Defines

#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Slave Address in 10-bit.

Definition at line 245 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U

Slave Address in 7-bit.

Definition at line 244 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Transfer Request Direction

Defines
Transfer Request Direction
I2C Exported Constants

Defines

#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Define Documentation

#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Master request a read transfer.

Definition at line 254 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_REQUEST_WRITE 0x00000000U

Master request a write transfer.

Definition at line 253 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Transfer End Mode

Defines
Transfer End Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Define Documentation

#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND

Enable I2C Automatic end mode with no HW PEC comparison.

Definition at line 263 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD

Enable I2C Reload mode.

Definition at line 262 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 269 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 273 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 267 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 271 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 275 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_MODE_SOFTEND 0x00000000U

Enable I2C Software end mode with no HW PEC comparison.

Definition at line 265 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Start And Stop Generation

Defines
Start And Stop Generation
I2C Exported Constants

Defines

#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_10BIT_READ
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U

Don't Generate Stop and Start condition.

Definition at line 284 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_READ
Value:
(uint32_t)(0x80000000U | I2C_CR2_START | \
                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)

Generate Restart for read request, slave 10Bit address.

Definition at line 296 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 10Bit address.

Definition at line 299 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Restart for read request, slave 7Bit address.

Definition at line 292 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 7Bit address.

Definition at line 294 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Start for read request.

Definition at line 288 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Start for write request.

Definition at line 290 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Generate Stop condition (Size should be set to 0).

Definition at line 286 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Read Write Direction

Defines
Read Write Direction
I2C Exported Constants

Defines

#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR

Define Documentation

#define LL_I2C_DIRECTION_READ I2C_ISR_DIR

Read transfer request by master, slave enters transmitter mode.

Definition at line 310 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_DIRECTION_WRITE 0x00000000U

Write transfer request by master, slave enters receiver mode.

Definition at line 308 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
I2C Exported Constants

Defines

#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 321 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 319 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_DMA_GetRegAddr().

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STM32G0C1xx HAL User Manual: SMBus TimeoutA Mode SCL SDA Timeout

Defines
SMBus TimeoutA Mode SCL SDA Timeout
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

Define Documentation

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U

TimeoutA is used to detect SCL low level timeout.

Definition at line 330 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

TimeoutA is used to detect both SCL and SDA high level timeout.

Definition at line 332 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: SMBus Timeout Selection

Defines
SMBus Timeout Selection
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT

Define Documentation

#define LL_I2C_SMBUS_ALL_TIMEOUT
Value:
(uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
                                                       I2C_TIMEOUTR_TEXTEN)

TimeoutA and TimeoutB (extended clock) enable bits

Definition at line 344 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN

TimeoutA enable bit

Definition at line 341 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN

TimeoutB (extended clock) enable bit

Definition at line 342 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2C Exported Macros

Defines

#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.

Define Documentation

#define LL_I2C_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 379 of file stm32g0xx_ll_i2c.h.

#define LL_I2C_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 371 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Convert SDA SCL timings

Defines
Convert SDA SCL timings
I2C Exported Macros

Defines

#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Define Documentation

#define __LL_I2C_CONVERT_TIMINGS | ( | __PRESCALER__,
 |  | __SETUP_TIME__,
 |  | __HOLD_TIME__,
 |  | __SCLH_PERIOD__,
 |  | __SCLL_PERIOD__
 | ) |
Value:
((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))

Configure the SDA setup, hold time and the SCL high, low period.

Parameters:
__PRESCALER__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF.
__SETUP_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
__HOLD_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
__SCLH_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
__SCLL_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
Return values:
Value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 400 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extended Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_ConfigFilters | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AnalogFilter,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Noise Filters (Analog and Digital).

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. The filters can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_ConfigFilters
CR1 DNF LL_I2C_ConfigFilters
Parameters:
I2Cx | I2C Instance.
AnalogFilter This parameter can be one of the following values:
  • LL_I2C_ANALOGFILTER_ENABLE
  • LL_I2C_ANALOGFILTER_DISABLE
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 475 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA,
 |  | uint32_t | TimeoutAMode,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Clock Timeout.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
TimeoutB
Return values:
None

Definition at line 1123 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_Disable ( I2C_TypeDef * I2Cx )

Disable I2C peripheral (PE = 0).

Note:
When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Disable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 443 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAnalogFilter ( I2C_TypeDef * I2Cx )

Disable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_DisableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 527 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableClockStretching ( I2C_TypeDef * I2Cx )

Disable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_DisableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 656 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_RX ( I2C_TypeDef * I2Cx )

Disable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 593 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_TX ( I2C_TypeDef * I2Cx )

Disable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 560 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableGeneralCall ( I2C_TypeDef * I2Cx )

Disable General Call.

Note:
When disabled the Address 0x00 is NACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_DisableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 764 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableOwnAddress1 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_DisableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 841 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableOwnAddress2 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_DisableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 897 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSlaveByteControl ( I2C_TypeDef * I2Cx )

Disable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_DisableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 689 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusAlert ( I2C_TypeDef * I2Cx )

Disable SMBus alert (Host or Device mode)

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is not drived (can be used as a standard GPIO) and Alert Response Address Header acknowledge is disabled. SMBus Host mode:
  • SMBus Alert pin management is not supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_DisableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1050 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusPEC ( I2C_TypeDef * I2Cx )

Disable SMBus Packet Error Calculation (PEC).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_DisableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1089 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Disable the SMBus Clock Timeout.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1249 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Disable Wakeup from STOP.

Note:
The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_DisableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 727 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_DMA_GetRegAddr
RXDR RXDATA LL_I2C_DMA_GetRegAddr
Parameters:
I2Cx I2C Instance
Direction This parameter can be one of the following values:
  • LL_I2C_DMA_REG_DATA_TRANSMIT
  • LL_I2C_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 619 of file stm32g0xx_ll_i2c.h.

References LL_I2C_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_I2C_Enable ( I2C_TypeDef * I2Cx )

Enable I2C peripheral (PE = 1).

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Enable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 429 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableAnalogFilter ( I2C_TypeDef * I2Cx )

Enable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_EnableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 515 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableClockStretching ( I2C_TypeDef * I2Cx )

Enable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_EnableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 644 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_RX ( I2C_TypeDef * I2Cx )

Enable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 582 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_TX ( I2C_TypeDef * I2Cx )

Enable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 549 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableGeneralCall ( I2C_TypeDef * I2Cx )

Enable General Call.

Note:
When enabled the Address 0x00 is ACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_EnableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 752 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableOwnAddress1 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_EnableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 830 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableOwnAddress2 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_EnableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 886 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSlaveByteControl ( I2C_TypeDef * I2Cx )

Enable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_EnableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 678 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusAlert ( I2C_TypeDef * I2Cx )

Enable SMBus alert (Host or Device mode)

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is drived low and Alert Response Address Header acknowledge is enabled. SMBus Host mode:
  • SMBus Alert pin management is supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_EnableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1032 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPEC ( I2C_TypeDef * I2Cx )

Enable SMBus Packet Error Calculation (PEC).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_EnableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1076 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Enable the SMBus Clock Timeout.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1231 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Enable Wakeup from STOP.

Note:
The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
This bit can only be programmed when Digital Filter is disabled.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_EnableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 714 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod ( I2C_TypeDef * I2Cx )

Get the SCL high period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLH LL_I2C_GetClockHighPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 955 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod ( I2C_TypeDef * I2Cx )

Get the SCL low period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLL LL_I2C_GetClockLowPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 944 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime ( I2C_TypeDef * I2Cx )

Get the SDA hold time.

Reference Manual to LL API cross reference:
TIMINGR SDADEL LL_I2C_GetDataHoldTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 966 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime ( I2C_TypeDef * I2Cx )

Get the SDA setup time.

Reference Manual to LL API cross reference:
TIMINGR SCLDEL LL_I2C_GetDataSetupTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 977 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter ( I2C_TypeDef * I2Cx )

Get the current Digital Noise Filter configuration.

Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_GetDigitalFilter
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 503 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode ( I2C_TypeDef * I2Cx )

Get the Master addressing mode.

Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_GetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT

Definition at line 803 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMode ( I2C_TypeDef * I2Cx )

Get peripheral mode.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_GetMode
CR1 SMBDEN LL_I2C_GetMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP

Definition at line 1014 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA setting.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1153 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA mode.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

Definition at line 1185 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB ( I2C_TypeDef * I2Cx )

Get the SMBus Extended Cumulative Clock TimeoutB setting.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1213 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler ( I2C_TypeDef * I2Cx )

Get the Timing Prescaler setting.

Reference Manual to LL API cross reference:
TIMINGR PRESC LL_I2C_GetTimingPrescaler
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 933 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabled ( I2C_TypeDef * I2Cx )

Check if the I2C peripheral is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_IsEnabled
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 454 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter ( I2C_TypeDef * I2Cx )

Check if Analog Noise Filter is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 538 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching ( I2C_TypeDef * I2Cx )

Check if Clock stretching is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 667 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX ( I2C_TypeDef * I2Cx )

Check if DMA reception requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 604 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX ( I2C_TypeDef * I2Cx )

Check if DMA transmission requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 571 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall ( I2C_TypeDef * I2Cx )

Check if General Call is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_IsEnabledGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 775 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 852 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 908 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl ( I2C_TypeDef * I2Cx )

Check if hardware byte control in slave mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_IsEnabledSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 700 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert ( I2C_TypeDef * I2Cx )

Check if SMBus alert (Host or Device mode) is enabled or disabled.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1063 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC ( I2C_TypeDef * I2Cx )

Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_IsEnabledSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1102 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Check if the SMBus Clock Timeout is enabled or disabled.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
State of bit (1 or 0).

Definition at line 1267 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop ( I2C_TypeDef * I2Cx )

Check if Wakeup from STOP is enabled or disabled.

Note:
The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 740 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetDigitalFilter | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital Noise Filter.

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_SetDigitalFilter
Parameters:
I2Cx | I2C Instance.
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 492 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMasterAddressingMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AddressingMode
 | ) |  |

Configure the Master to operate in 7-bit or 10-bit addressing mode.

Note:
Changing this bit is not allowed, when the START bit is set.
Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_SetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
AddressingMode This parameter can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT
Return values:
None

Definition at line 790 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeripheralMode
 | ) |  |

Configure peripheral mode.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_SetMode
CR1 SMBDEN LL_I2C_SetMode
Parameters:
I2Cx I2C Instance.
PeripheralMode This parameter can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP
Return values:
None

Definition at line 996 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress1 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress1,
 |  | uint32_t | OwnAddrSize
 | ) |  |

Set the Own Address1.

Reference Manual to LL API cross reference:
OAR1 OA1 LL_I2C_SetOwnAddress1
OAR1 OA1MODE LL_I2C_SetOwnAddress1
Parameters:
I2Cx | I2C Instance.
OwnAddress1 | This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
OwnAddrSize This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS1_7BIT
  • LL_I2C_OWNADDRESS1_10BIT
Return values:
None

Definition at line 819 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress2 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress2,
 |  | uint32_t | OwnAddrMask
 | ) |  |

Set the 7bits Own Address2.

Note:
This action has no effect if own address2 is enabled.
Reference Manual to LL API cross reference:
OAR2 OA2 LL_I2C_SetOwnAddress2
OAR2 OA2MSK LL_I2C_SetOwnAddress2
Parameters:
I2Cx | I2C Instance.
OwnAddress2 | Value between Min_Data=0 and Max_Data=0x7F.
OwnAddrMask This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS2_NOMASK
  • LL_I2C_OWNADDRESS2_MASK01
  • LL_I2C_OWNADDRESS2_MASK02
  • LL_I2C_OWNADDRESS2_MASK03
  • LL_I2C_OWNADDRESS2_MASK04
  • LL_I2C_OWNADDRESS2_MASK05
  • LL_I2C_OWNADDRESS2_MASK06
  • LL_I2C_OWNADDRESS2_MASK07
Return values:
None

Definition at line 875 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA
 | ) |  |

Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1140 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutAMode
 | ) |  |

Set the SMBus Clock TimeoutA mode.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This bit can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
Return values:
None

Definition at line 1170 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutB is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
Parameters:
I2Cx | I2C Instance.
TimeoutB | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1200 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTiming | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Timing
 | ) |  |

Configure the SDA setup, hold time and the SCL high, low period.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
TIMINGR TIMINGR LL_I2C_SetTiming
Parameters:
I2Cx | I2C Instance.
Timing | This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
Note:
This parameter is computed with the STM32CubeMX Tool.
Return values:
None

Definition at line 922 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT_Management

Functions
IT_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_DisableIT_ADDR ( I2C_TypeDef * I2Cx )

Disable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_DisableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1364 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_ERR ( I2C_TypeDef * I2Cx )

Disable Error interrupts.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_DisableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1520 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_NACK ( I2C_TypeDef * I2Cx )

Disable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_DisableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1397 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_RX ( I2C_TypeDef * I2Cx )

Disable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_DisableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1331 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_STOP ( I2C_TypeDef * I2Cx )

Disable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_DisableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1430 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TC ( I2C_TypeDef * I2Cx )

Disable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_DisableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1469 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TX ( I2C_TypeDef * I2Cx )

Disable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_DisableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1298 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ADDR ( I2C_TypeDef * I2Cx )

Enable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_EnableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1353 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ERR ( I2C_TypeDef * I2Cx )

Enable Error interrupts.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_EnableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1500 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_NACK ( I2C_TypeDef * I2Cx )

Enable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_EnableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1386 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_RX ( I2C_TypeDef * I2Cx )

Enable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_EnableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1320 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_STOP ( I2C_TypeDef * I2Cx )

Enable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_EnableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1419 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TC ( I2C_TypeDef * I2Cx )

Enable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_EnableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1455 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TX ( I2C_TypeDef * I2Cx )

Enable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_EnableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1287 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR ( I2C_TypeDef * I2Cx )

Check if Address match interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1375 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR ( I2C_TypeDef * I2Cx )

Check if Error interrupts are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_IsEnabledIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1531 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK ( I2C_TypeDef * I2Cx )

Check if Not acknowledge received interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_IsEnabledIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1408 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX ( I2C_TypeDef * I2Cx )

Check if the RXNE Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_IsEnabledIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1342 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP ( I2C_TypeDef * I2Cx )

Check if STOP detection interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_IsEnabledIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1441 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC ( I2C_TypeDef * I2Cx )

Check if Transfer Complete interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_IsEnabledIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1480 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX ( I2C_TypeDef * I2Cx )

Check if the TXIS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_IsEnabledIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1309 of file stm32g0xx_ll_i2c.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG_management

Functions
FLAG_management
I2C Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.

Function Documentation

__STATIC_INLINE void LL_I2C_ClearFlag_ADDR ( I2C_TypeDef * I2Cx )

Clear Address Matched flag.

Reference Manual to LL API cross reference:
ICR ADDRCF LL_I2C_ClearFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1752 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_ARLO ( I2C_TypeDef * I2Cx )

Clear Arbitration lost flag.

Reference Manual to LL API cross reference:
ICR ARLOCF LL_I2C_ClearFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1808 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_BERR ( I2C_TypeDef * I2Cx )

Clear Bus error flag.

Reference Manual to LL API cross reference:
ICR BERRCF LL_I2C_ClearFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1797 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_NACK ( I2C_TypeDef * I2Cx )

Clear Not Acknowledge flag.

Reference Manual to LL API cross reference:
ICR NACKCF LL_I2C_ClearFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1763 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_OVR ( I2C_TypeDef * I2Cx )

Clear Overrun/Underrun flag.

Reference Manual to LL API cross reference:
ICR OVRCF LL_I2C_ClearFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1819 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_STOP ( I2C_TypeDef * I2Cx )

Clear Stop detection flag.

Reference Manual to LL API cross reference:
ICR STOPCF LL_I2C_ClearFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1774 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_TXE ( I2C_TypeDef * I2Cx )

Clear Transmit data register empty flag (TXE).

Note:
This bit can be clear by software in order to flush the transmit data register (TXDR).
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_ClearFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1786 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Clear SMBus Alert flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1858 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Clear SMBus PEC error flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1832 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Clear SMBus Timeout detection flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1845 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR ( I2C_TypeDef * I2Cx )

Indicate the status of Address matched flag (slave mode).

Note:
RESET: Clear default value. SET: When the received slave address matched with one of the enabled slave address.
Reference Manual to LL API cross reference:
ISR ADDR LL_I2C_IsActiveFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1591 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO ( I2C_TypeDef * I2Cx )

Indicate the status of Arbitration lost flag.

Note:
RESET: Clear default value. SET: When arbitration lost.
Reference Manual to LL API cross reference:
ISR ARLO LL_I2C_IsActiveFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1669 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR ( I2C_TypeDef * I2Cx )

Indicate the status of Bus error flag.

Note:
RESET: Clear default value. SET: When a misplaced Start or Stop condition is detected.
Reference Manual to LL API cross reference:
ISR BERR LL_I2C_IsActiveFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1656 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY ( I2C_TypeDef * I2Cx )

Indicate the status of Bus Busy flag.

Note:
RESET: Clear default value. SET: When a Start condition is detected.
Reference Manual to LL API cross reference:
ISR BUSY LL_I2C_IsActiveFlag_BUSY
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1741 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK ( I2C_TypeDef * I2Cx )

Indicate the status of Not Acknowledge received flag.

Note:
RESET: Clear default value. SET: When a NACK is received after a byte transmission.
Reference Manual to LL API cross reference:
ISR NACKF LL_I2C_IsActiveFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1604 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR ( I2C_TypeDef * I2Cx )

Indicate the status of Overrun/Underrun flag (slave mode).

Note:
RESET: Clear default value. SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
Reference Manual to LL API cross reference:
ISR OVR LL_I2C_IsActiveFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1682 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE ( I2C_TypeDef * I2Cx )

Indicate the status of Receive data register not empty flag.

Note:
RESET: When Receive data register is read. SET: When the received data is copied in Receive data register.
Reference Manual to LL API cross reference:
ISR RXNE LL_I2C_IsActiveFlag_RXNE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1578 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP ( I2C_TypeDef * I2Cx )

Indicate the status of Stop detection flag.

Note:
RESET: Clear default value. SET: When a Stop condition is detected.
Reference Manual to LL API cross reference:
ISR STOPF LL_I2C_IsActiveFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1617 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TC LL_I2C_IsActiveFlag_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1630 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=1 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TCR LL_I2C_IsActiveFlag_TCR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1643 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit data register empty flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_IsActiveFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1552 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit interrupt flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXIS LL_I2C_IsActiveFlag_TXIS
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1565 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus alert flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When SMBus host configuration, SMBus alert enabled and a falling edge event occurs on SMBA pin.
Reference Manual to LL API cross reference:
ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1728 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus PEC error flag in reception.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When the received PEC does not match with the PEC register content.
Reference Manual to LL API cross reference:
ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1697 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus Timeout detection flag.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When a timeout or extended clock timeout occurs.
Reference Manual to LL API cross reference:
ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1712 of file stm32g0xx_ll_i2c.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data_Management

Functions
Data_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .

Function Documentation

__STATIC_INLINE void LL_I2C_AcknowledgeNextData | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TypeAcknowledge
 | ) |  |

Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

Note:
Usage in Slave mode only.
Reference Manual to LL API cross reference:
CR2 NACK LL_I2C_AcknowledgeNextData
Parameters:
I2Cx I2C Instance.
TypeAcknowledge This parameter can be one of the following values:
  • LL_I2C_ACK
  • LL_I2C_NACK
Return values:
None

Definition at line 1977 of file stm32g0xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAuto10BitRead ( I2C_TypeDef * I2Cx )

Disable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master only sends the first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_DisableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2027 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableAutoEndMode ( I2C_TypeDef * I2Cx )

Disable automatic STOP condition generation (master mode).

Note:
Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_DisableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1891 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableReloadMode ( I2C_TypeDef * I2Cx )

Disable reload mode (master mode).

Note:
The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_DisableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1926 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAuto10BitRead ( I2C_TypeDef * I2Cx )

Enable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master sends the complete 10bit slave address read sequence : Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_EnableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2015 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAutoEndMode ( I2C_TypeDef * I2Cx )

Enable automatic STOP condition generation (master mode).

Note:
Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. This bit has no effect in slave mode or when RELOAD bit is set.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_EnableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1879 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableReloadMode ( I2C_TypeDef * I2Cx )

Enable reload mode (master mode).

Note:
The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_EnableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1914 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare ( I2C_TypeDef * I2Cx )

Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. This bit has no effect when RELOAD bit is set. This bit has no effect in device mode when SBC bit is not set.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2181 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStartCondition ( I2C_TypeDef * I2Cx )

Generate a START or RESTART condition.

Note:
The START bit can be set even if bus is BUSY or I2C is in slave mode. This action has no effect when RELOAD is set.
Reference Manual to LL API cross reference:
CR2 START LL_I2C_GenerateStartCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1990 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStopCondition ( I2C_TypeDef * I2Cx )

Generate a STOP condition after the current byte transfer (master mode).

Reference Manual to LL API cross reference:
CR2 STOP LL_I2C_GenerateStopCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2001 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode ( I2C_TypeDef * I2Cx )

Return the slave matched address.

Reference Manual to LL API cross reference:
ISR ADDCODE LL_I2C_GetAddressMatchCode
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 2164 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr ( I2C_TypeDef * I2Cx )

Get the slave address programmed for transfer.

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_GetSlaveAddr
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0x3F

Definition at line 2090 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC ( I2C_TypeDef * I2Cx )

Get the SMBus Packet Error byte calculated.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
PECR PEC LL_I2C_GetSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2207 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection ( I2C_TypeDef * I2Cx )

Indicate the value of transfer direction (slave mode).

Note:
RESET: Write transfer, Slave enters in receiver mode. SET: Read transfer, Slave enters in transmitter mode.
Reference Manual to LL API cross reference:
ISR DIR LL_I2C_GetTransferDirection
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_DIRECTION_WRITE
  • LL_I2C_DIRECTION_READ

Definition at line 2153 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest ( I2C_TypeDef * I2Cx )

Get the transfer direction requested (master mode).

Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_GetTransferRequest
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ

Definition at line 2066 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferSize ( I2C_TypeDef * I2Cx )

Get the number of bytes configured for transfer.

Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_GetTransferSize
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xFF

Definition at line 1961 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_HandleTransfer | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr,
 |  | uint32_t | SlaveAddrSize,
 |  | uint32_t | TransferSize,
 |  | uint32_t | EndMode,
 |  | uint32_t | Request
 | ) |  |

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_HandleTransfer
CR2 ADD10 LL_I2C_HandleTransfer
CR2 RD_WRN LL_I2C_HandleTransfer
CR2 START LL_I2C_HandleTransfer
CR2 STOP LL_I2C_HandleTransfer
CR2 RELOAD LL_I2C_HandleTransfer
CR2 NBYTES LL_I2C_HandleTransfer
CR2 AUTOEND LL_I2C_HandleTransfer
CR2 HEAD10R LL_I2C_HandleTransfer
Parameters:
I2Cx | I2C Instance.
SlaveAddr | Specifies the slave address to be programmed.
SlaveAddrSize This parameter can be one of the following values:
  • LL_I2C_ADDRSLAVE_7BIT
  • LL_I2C_ADDRSLAVE_10BIT
TransferSize | Specifies the number of bytes to be programmed. This parameter must be a value between Min_Data=0 and Max_Data=255.
EndMode This parameter can be one of the following values:
  • LL_I2C_MODE_RELOAD
  • LL_I2C_MODE_AUTOEND
  • LL_I2C_MODE_SOFTEND
  • LL_I2C_MODE_SMBUS_RELOAD
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
Request This parameter can be one of the following values:
  • LL_I2C_GENERATE_NOSTARTSTOP
  • LL_I2C_GENERATE_STOP
  • LL_I2C_GENERATE_START_READ
  • LL_I2C_GENERATE_START_WRITE
  • LL_I2C_GENERATE_RESTART_7BIT_READ
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE
  • LL_I2C_GENERATE_RESTART_10BIT_READ
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE
Return values:
None

Definition at line 2133 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead ( I2C_TypeDef * I2Cx )

Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2038 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode ( I2C_TypeDef * I2Cx )

Check if automatic STOP condition is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1902 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode ( I2C_TypeDef * I2Cx )

Check if reload mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_IsEnabledReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1937 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare ( I2C_TypeDef * I2Cx )

Check if the SMBus Packet Error byte internal comparison is requested or not.

Note:
The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2194 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE uint8_t LL_I2C_ReceiveData8 ( I2C_TypeDef * I2Cx )

Read Receive Data register.

Reference Manual to LL API cross reference:
RXDR RXDATA LL_I2C_ReceiveData8
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2218 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSlaveAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr
 | ) |  |

Configure the slave address for transfer (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_SetSlaveAddr
Parameters:
I2Cx | I2C Instance.
SlaveAddr | This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
Return values:
None

Definition at line 2079 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferRequest | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferRequest
 | ) |  |

Configure the transfer direction (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_SetTransferRequest
Parameters:
I2Cx I2C Instance.
TransferRequest This parameter can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ
Return values:
None

Definition at line 2053 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferSize | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferSize
 | ) |  |

Configure the number of bytes for transfer.

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_SetTransferSize
Parameters:
I2Cx | I2C Instance.
TransferSize | This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 1950 of file stm32g0xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_TransmitData8 | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Write in Transmit Data Register .

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_TransmitData8
Parameters:
I2Cx | I2C Instance.
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2230 of file stm32g0xx_ll_i2c.h.

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STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Functions

ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_I2C_DeInit ( I2C_TypeDef * I2Cx )

De-initialize the I2C registers to their default reset values.

Parameters:
I2Cx I2C Instance.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are de-initialized
  • ERROR: I2C registers are not de-initialized

Definition at line 86 of file stm32g0xx_ll_i2c.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_I2C1, LL_APB1_GRP1_PERIPH_I2C2, LL_APB1_GRP1_PERIPH_I2C3, and LL_APB1_GRP1_ReleaseReset().

ErrorStatus LL_I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | LL_I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initialize the I2C registers according to the specified parameters in I2C_InitStruct.

Parameters:
I2Cx | I2C Instance.
I2C_InitStruct | pointer to a LL_I2C_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are initialized
  • ERROR: Not applicable

Definition at line 136 of file stm32g0xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, assert_param, LL_I2C_InitTypeDef::DigitalFilter, IS_LL_I2C_ANALOG_FILTER, IS_LL_I2C_DIGITAL_FILTER, IS_LL_I2C_OWN_ADDRESS1, IS_LL_I2C_OWN_ADDRSIZE, IS_LL_I2C_PERIPHERAL_MODE, IS_LL_I2C_TYPE_ACKNOWLEDGE, LL_I2C_AcknowledgeNextData(), LL_I2C_ConfigFilters(), LL_I2C_Disable(), LL_I2C_DisableOwnAddress1(), LL_I2C_Enable(), LL_I2C_EnableOwnAddress1(), LL_I2C_SetMode(), LL_I2C_SetOwnAddress1(), LL_I2C_SetTiming(), LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

void LL_I2C_StructInit ( LL_I2C_InitTypeDef * I2C_InitStruct )

Set each LL_I2C_InitTypeDef field to default value.

Parameters:
I2C_InitStruct Pointer to a LL_I2C_InitTypeDef structure.
Return values:
None

Definition at line 204 of file stm32g0xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, LL_I2C_InitTypeDef::DigitalFilter, LL_I2C_ANALOGFILTER_ENABLE, LL_I2C_MODE_I2C, LL_I2C_NACK, LL_I2C_OWNADDRESS1_7BIT, LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

Define Documentation

#define LL_IWDG_KEY_ENABLE 0x0000CCCCU

IWDG Peripheral Enable

Definition at line 48 of file stm32g0xx_ll_iwdg.h.

Referenced by LL_IWDG_Enable().

#define LL_IWDG_KEY_RELOAD 0x0000AAAAU

IWDG Reload Counter Enable

Definition at line 47 of file stm32g0xx_ll_iwdg.h.

Referenced by LL_IWDG_ReloadCounter().

#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

IWDG KR Write Access Disable

Definition at line 50 of file stm32g0xx_ll_iwdg.h.

Referenced by LL_IWDG_DisableWriteAccess().

#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U

IWDG KR Write Access Enable

Definition at line 49 of file stm32g0xx_ll_iwdg.h.

Referenced by LL_IWDG_EnableWriteAccess().

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STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
IWDG Exported Constants

Flags defines which can be used with LL_IWDG_ReadReg function. More...

Defines

#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU

Detailed Description

Flags defines which can be used with LL_IWDG_ReadReg function.

Define Documentation

#define LL_IWDG_SR_PVU IWDG_SR_PVU

Watchdog prescaler value update

Definition at line 67 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_SR_RVU IWDG_SR_RVU

Watchdog counter reload value update

Definition at line 68 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_SR_WVU IWDG_SR_WVU

Watchdog counter window value update

Definition at line 69 of file stm32g0xx_ll_iwdg.h.

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STM32G0C1xx HAL User Manual: Prescaler Divider

Defines
Prescaler Divider
IWDG Exported Constants

Defines

#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

Divider by 128

Definition at line 82 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)

Divider by 16

Definition at line 79 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Divider by 256

Definition at line 83 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

Divider by 32

Definition at line 80 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_4 0x00000000U

Divider by 4

Definition at line 77 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)

Divider by 64

Definition at line 81 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)

Divider by 8

Definition at line 78 of file stm32g0xx_ll_iwdg.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
IWDG Exported Macros

Defines

#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Define Documentation

#define LL_IWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 116 of file stm32g0xx_ll_iwdg.h.

#define LL_IWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 108 of file stm32g0xx_ll_iwdg.h.

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STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
IWDG Exported Functions

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.

Function Documentation

__STATIC_INLINE void LL_IWDG_DisableWriteAccess ( IWDG_TypeDef * IWDGx )

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_DisableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 174 of file stm32g0xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_DISABLE.

__STATIC_INLINE void LL_IWDG_Enable ( IWDG_TypeDef * IWDGx )

Start the Independent Watchdog.

Note:
Except if the hardware watchdog option is selected
Reference Manual to LL API cross reference:
KR KEY LL_IWDG_Enable
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 141 of file stm32g0xx_ll_iwdg.h.

References LL_IWDG_KEY_ENABLE.

__STATIC_INLINE void LL_IWDG_EnableWriteAccess ( IWDG_TypeDef * IWDGx )

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_EnableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 163 of file stm32g0xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_ENABLE.

__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler ( IWDG_TypeDef * IWDGx )

Get the selected prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_GetPrescaler
Parameters:
IWDGx IWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256

Definition at line 211 of file stm32g0xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter ( IWDG_TypeDef * IWDGx )

Get the specified IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_GetReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 234 of file stm32g0xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetWindow ( IWDG_TypeDef * IWDGx )

Get the high limit of the window value specified.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_GetWindow
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 257 of file stm32g0xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_ReloadCounter ( IWDG_TypeDef * IWDGx )

Reloads IWDG counter with value defined in the reload register.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_ReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 152 of file stm32g0xx_ll_iwdg.h.

References LL_IWDG_KEY_RELOAD.

__STATIC_INLINE void LL_IWDG_SetPrescaler | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Select the prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_SetPrescaler
Parameters:
IWDGx IWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256
Return values:
None

Definition at line 193 of file stm32g0xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetReloadCounter | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Counter
 | ) |  |

Specify the IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_SetReloadCounter
Parameters:
IWDGx | IWDG Instance
Counter | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 223 of file stm32g0xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetWindow | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Window
 | ) |  |

Specify high limit of the window value to be compared to the down-counter.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_SetWindow
Parameters:
IWDGx | IWDG Instance
Window | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 246 of file stm32g0xx_ll_iwdg.h.

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STM32G0C1xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
IWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Function Documentation

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU ( IWDG_TypeDef * IWDGx )

Check if flag Prescaler Value Update is set or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsActiveFlag_PVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 276 of file stm32g0xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU ( IWDG_TypeDef * IWDGx )

Check if flag Reload Value Update is set or not.

Reference Manual to LL API cross reference:
SR RVU LL_IWDG_IsActiveFlag_RVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 287 of file stm32g0xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU ( IWDG_TypeDef * IWDGx )

Check if flag Window Value Update is set or not.

Reference Manual to LL API cross reference:
SR WVU LL_IWDG_IsActiveFlag_WVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 298 of file stm32g0xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsReady ( IWDG_TypeDef * IWDGx )

Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsReady
SR RVU LL_IWDG_IsReady
SR WVU LL_IWDG_IsReady
Parameters:
IWDGx IWDG Instance
Return values:
State of bits (1 or 0).

Definition at line 311 of file stm32g0xx_ll_iwdg.h.

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STM32G0C1xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LL_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__)

Define Documentation

#define IS_LL_LPTIM_CLOCK_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))

Definition at line 52 of file stm32g0xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_CLOCK_SOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
                                             || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))

Definition at line 49 of file stm32g0xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_OUTPUT_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
                                                || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))

Definition at line 64 of file stm32g0xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_WAVEFORM ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
                                         || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))

Definition at line 61 of file stm32g0xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPTIM_InitTypeDef Struct Reference
LPTIM Exported Init structure

LPTIM Init structure definition. More...

#include <stm32g0xx_ll_lptim.h>

Data Fields

uint32_t | ClockSource
uint32_t | Prescaler
uint32_t | Waveform
uint32_t | Polarity

Detailed Description

LPTIM Init structure definition.

Definition at line 64 of file stm32g0xx_ll_lptim.h.

Field Documentation

uint32_t LL_LPTIM_InitTypeDef::ClockSource

Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of Clock Source.

This feature can be modified afterwards using unitary function LL_LPTIM_SetClockSource().

Definition at line 66 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Polarity

Specifies waveform polarity. This parameter can be a value of Output Polarity.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 84 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Prescaler

Specifies the prescaler division ratio. This parameter can be a value of Prescaler Value.

This feature can be modified afterwards using using unitary function LL_LPTIM_SetPrescaler().

Definition at line 72 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Waveform

Specifies the waveform shape. This parameter can be a value of Output Waveform Type.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 78 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_lptim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPTIM Exported Constants

Flags defines which can be used with LL_LPTIM_ReadReg function. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Detailed Description

Flags defines which can be used with LL_LPTIM_ReadReg function.

Define Documentation

#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM

Autoreload match

Definition at line 107 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK

Autoreload register update OK

Definition at line 109 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM

Compare match

Definition at line 105 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK

Compare register update OK

Definition at line 106 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Counter direction change up to down

Definition at line 111 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG

External trigger edge event

Definition at line 108 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_ISR_UP LPTIM_ISR_UP

Counter direction change down to up

Definition at line 110 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
LPTIM Exported Constants

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions. More...

Defines

#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Detailed Description

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Define Documentation

#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE

Autoreload match

Definition at line 122 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE

Autoreload register update OK

Definition at line 124 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE

Compare match

Definition at line 120 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE

Compare register update OK

Definition at line 121 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Counter direction change up to down

Definition at line 126 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE

External trigger edge event

Definition at line 123 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE

Counter direction change down to up

Definition at line 125 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Operating Mode

Defines
Operating Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

Define Documentation

#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT

LP Timer starts in continuous mode

Definition at line 134 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

LP Tilmer starts in single mode

Definition at line 135 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Update Mode

Defines
Update Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

preload is enabled: registers are updated at the end of the current LPTIM period

Definition at line 144 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U

Preload is disabled: registers are updated after each APB bus write access

Definition at line 143 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Counter Mode

Defines
Counter Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

The counter is incremented following each valid clock pulse on the LPTIM external Input1

Definition at line 153 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U

The counter is incremented following each internal clock pulse

Definition at line 152 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Output Waveform Type

Defines
Output Waveform Type
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

Define Documentation

#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U

LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE

Definition at line 161 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

LPTIM generates a Set Once waveform

Definition at line 162 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Output Polarity

Defines
Output Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

Define Documentation

#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 171 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U

The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 170 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

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STM32G0C1xx HAL User Manual: Prescaler Value

Defines
Prescaler Value
LPTIM Exported Constants

Defines

#define | LL_LPTIM_PRESCALER_DIV1 0x00000000U
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LL_LPTIM_PRESCALER_DIV1 0x00000000U

Prescaler division factor is set to 1

Definition at line 179 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Prescaler division factor is set to 128

Definition at line 186 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Prescaler division factor is set to 16

Definition at line 183 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Prescaler division factor is set to 2

Definition at line 180 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 32

Definition at line 184 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Prescaler division factor is set to 4

Definition at line 181 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)

Prescaler division factor is set to 64

Definition at line 185 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 8

Definition at line 182 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Trigger Source

Defines
Trigger Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL
#define | LL_LPTIM_TRIG_SOURCE_COMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)

Define Documentation

#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)

External input trigger is connected to COMP1 output

Definition at line 202 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL

External input trigger is connected to COMP2 output

Definition at line 203 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_COMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to COMP3 output

Definition at line 205 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U

External input trigger is connected to TIMx_ETR input

Definition at line 194 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0

External input trigger is connected to RTC Alarm A

Definition at line 195 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1

External input trigger is connected to RTC Alarm B

Definition at line 196 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 1

Definition at line 197 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to RTC Tamper 2

Definition at line 198 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 3

Definition at line 200 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Trigger Filter

Defines
Trigger Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_FILTER_NONE 0x00000000U
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Define Documentation

#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0

Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger

Definition at line 215 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1

Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger

Definition at line 216 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

Definition at line 217 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U

Any trigger active level change is considered as a valid trigger

Definition at line 214 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Trigger Polarity

Defines
Trigger Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1

LPTIM counter starts when a falling edge is detected

Definition at line 226 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0

LPTIM counter starts when a rising edge is detected

Definition at line 225 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

LPTIM counter starts when a rising or a falling edge is detected

Definition at line 227 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Clock Source

Defines
Clock Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

Define Documentation

#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

LPTIM is clocked by an external clock source through the LPTIM external Input1

Definition at line 236 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U

LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)

Definition at line 235 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

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STM32G0C1xx HAL User Manual: Clock Filter

Defines
Clock Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

Define Documentation

#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0

External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition

Definition at line 245 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1

External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition

Definition at line 246 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

Definition at line 247 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U

Any external clock signal level change is considered as a valid transition

Definition at line 244 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_POLARITY_RISING 0x00000000U
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 256 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U

The rising edge is the active edge used for counting

Definition at line 255 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 257 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Encoder Mode

Defines
Encoder Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_ENCODER_MODE_RISING 0x00000000U
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 266 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U

The rising edge is the active edge used for counting

Definition at line 265 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 267 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Input1 Source

Defines
Input1 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0
#define | LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1
#define | LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)

Define Documentation

#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0

For LPTIM1 and LPTIM2

Definition at line 276 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)

For LPTIM2

Definition at line 278 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1

For LPTIM2

Definition at line 277 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U

For LPTIM1 and LPTIM2

Definition at line 275 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Input2 Source

Defines
Input2 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0

Define Documentation

#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0

For LPTIM1

Definition at line 287 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U

For LPTIM1

Definition at line 286 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPTIM Exported Macros

Defines

#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in LPTIM register.

Define Documentation

#define LL_LPTIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 320 of file stm32g0xx_ll_lptim.h.

#define LL_LPTIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 312 of file stm32g0xx_ll_lptim.h.

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STM32G0C1xx HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
LPTIM Exported Functions

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Function Documentation

ErrorStatus LL_LPTIM_DeInit ( LPTIM_TypeDef * LPTIMx )

Set LPTIMx registers to their reset values.

Parameters:
LPTIMx LP Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx registers are de-initialized
  • ERROR: invalid LPTIMx instance

Definition at line 95 of file stm32g0xx_ll_lptim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_LPTIM1, LL_APB1_GRP1_PERIPH_LPTIM2, and LL_APB1_GRP1_ReleaseReset().

Referenced by LL_LPTIM_Disable().

void LL_LPTIM_Disable ( LPTIM_TypeDef * LPTIMx )

Disable the LPTIM instance.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Disable
Parameters:
LPTIMx Low-Power Timer instance
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 190 of file stm32g0xx_ll_lptim.c.

References assert_param, LL_LPTIM_ClearFlag_ARROK(), LL_LPTIM_ClearFlag_CMPOK(), LL_LPTIM_DeInit(), LL_LPTIM_IsActiveFlag_ARROK(), LL_LPTIM_IsActiveFlag_CMPOK(), LL_RCC_GetLPTIMClockSource(), LL_RCC_GetSystemClocksFreq(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LPTIM2_CLKSOURCE, LL_RCC_LPTIM2_CLKSOURCE_PCLK1, LL_RCC_SetLPTIMClockSource(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

ErrorStatus LL_LPTIM_Init | ( | LPTIM_TypeDef * | LPTIMx,
 |  | const LL_LPTIM_InitTypeDef * | LPTIM_InitStruct
 | ) |  |

Configure the LPTIMx peripheral according to the specified parameters.

Note:
LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
LPTIMx can be disabled using unitary function LL_LPTIM_Disable().
Parameters:
LPTIMx | LP Timer Instance
LPTIM_InitStruct | pointer to a LL_LPTIM_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx instance has been initialized
  • ERROR: LPTIMx instance hasn't been initialized

Definition at line 147 of file stm32g0xx_ll_lptim.c.

References assert_param, LL_LPTIM_InitTypeDef::ClockSource, IS_LL_LPTIM_CLOCK_PRESCALER, IS_LL_LPTIM_CLOCK_SOURCE, IS_LL_LPTIM_OUTPUT_POLARITY, IS_LL_LPTIM_WAVEFORM, LL_LPTIM_IsEnabled(), LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

void LL_LPTIM_StructInit ( LL_LPTIM_InitTypeDef * LPTIM_InitStruct )

Set each fields of the LPTIM_InitStruct structure to its default value.

Parameters:
LPTIM_InitStruct pointer to a LL_LPTIM_InitTypeDef structure
Return values:
None

Definition at line 128 of file stm32g0xx_ll_lptim.c.

References LL_LPTIM_InitTypeDef::ClockSource, LL_LPTIM_CLK_SOURCE_INTERNAL, LL_LPTIM_OUTPUT_POLARITY_REGULAR, LL_LPTIM_OUTPUT_WAVEFORM_PWM, LL_LPTIM_PRESCALER_DIV1, LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPTIM Configuration

Functions
LPTIM Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (const LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_EnableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Enable reset after read.
__STATIC_INLINE void | LL_LPTIM_DisableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Disable reset after read.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledResetAfterRead (const LPTIM_TypeDef *LPTIMx)
Indicate whether the reset after read feature is enabled.
__STATIC_INLINE void | LL_LPTIM_ResetCounter (LPTIM_TypeDef *LPTIMx)
Reset of the LPTIM_CNT counter register (synchronous).
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (const LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (const LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (const LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (const LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (const LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (const LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (const LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigOutput | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform,
 |  | uint32_t | Polarity
 | ) |  |

Configure the LPTIM instance output (LPTIMx_OUT)

Note:
This function must be called when the LPTIM instance is disabled.
Regarding the LPTIM output polarity the change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled.
Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_ConfigOutput
CFGR WAVPOL LL_LPTIM_ConfigOutput
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 588 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Disable reset after read.

Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_DisableResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 413 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_Enable ( LPTIM_TypeDef * LPTIMx )

Enable the LPTIM instance.

Note:
After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM instance is actually enabled.
Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Enable
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 360 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Enable reset after read.

Note:
After calling this function any read access to LPTIM_CNT register will asynchronously reset the LPTIM_CNT register content.
Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_EnableResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 402 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload ( const LPTIM_TypeDef * LPTIMx )

Get actual auto reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_GetAutoReload
Parameters:
LPTIMx Low-Power Timer instance
Return values:
AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF

Definition at line 496 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCompare ( const LPTIM_TypeDef * LPTIMx )

Get actual compare value.

Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_GetCompare
Parameters:
LPTIMx Low-Power Timer instance
Return values:
CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 523 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounter ( const LPTIM_TypeDef * LPTIMx )

Get actual counter value.

Note:
When the LPTIM instance is running with an asynchronous clock, reading the LPTIMx_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
Reference Manual to LL API cross reference:
CNT CNT LL_LPTIM_GetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Counter value

Definition at line 538 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode ( const LPTIM_TypeDef * LPTIMx )

Get the counter mode.

Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_GetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL

Definition at line 566 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity ( const LPTIM_TypeDef * LPTIMx )

Get actual output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_GetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE

Definition at line 642 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler ( const LPTIM_TypeDef * LPTIMx )

Get actual prescaler division ratio.

Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_GetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128

Definition at line 686 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode ( const LPTIM_TypeDef * LPTIMx )

Get the LPTIM registers update mode.

Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_GetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD

Definition at line 467 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform ( const LPTIM_TypeDef * LPTIMx )

Get actual waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_GetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE

Definition at line 615 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM instance is enabled.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_IsEnabled
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 371 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Init().

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead ( const LPTIM_TypeDef * LPTIMx )

Indicate whether the reset after read feature is enabled.

Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 424 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ResetCounter ( LPTIM_TypeDef * LPTIMx )

Reset of the LPTIM_CNT counter register (synchronous).

Note:
Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTIM core clock cycles (LPTIM core clock may be different from APB clock).
COUNTRST is automatically cleared by hardware
Reference Manual to LL API cross reference:
CR COUNTRST LL_LPTIM_ResetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 439 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetAutoReload | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto reload value.

Note:
The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
After a write to the LPTIMx_ARR register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the ARROK flag is set, will lead to unpredictable results.
autoreload value be strictly greater than the compare value.
Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_SetAutoReload
Parameters:
LPTIMx | Low-Power Timer instance
AutoReload | Value between Min_Data=0x0001 and Max_Data=0xFFFF
Return values:
None

Definition at line 485 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCompare | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set the compare value.

Note:
After a write to the LPTIMx_CMP register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the CMPOK flag is set, will lead to unpredictable results.
Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_SetCompare
Parameters:
LPTIMx | Low-Power Timer instance
CompareValue | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 512 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCounterMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the counter mode (selection of the LPTIM counter clock source).

Note:
The counter mode can be set only when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_SetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
CounterMode This parameter can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL
Return values:
None

Definition at line 553 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput1Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 1 source (default GPIO).

Reference Manual to LL API cross reference:
CFGR2 IN1SEL LL_LPTIM_SetInput1Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT1_SRC_GPIO
  • LL_LPTIM_INPUT1_SRC_COMP1
  • LL_LPTIM_INPUT1_SRC_COMP2
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2
Return values:
None

Definition at line 702 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput2Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 2 source (default GPIO).

Reference Manual to LL API cross reference:
CFGR2 IN2SEL LL_LPTIM_SetInput2Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT2_SRC_GPIO
  • LL_LPTIM_INPUT2_SRC_COMP2
Return values:
None

Definition at line 716 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPolarity | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Polarity
 | ) |  |

Set output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_SetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 629 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPrescaler | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set actual prescaler division ratio.

Note:
This function must be called when the LPTIM instance is disabled.
When the LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated by active edges detected on the LPTIM external Input1, the internal clock provided to the LPTIM must be not be prescaled.
Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_SetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Prescaler This parameter can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128
Return values:
None

Definition at line 667 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetUpdateMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | UpdateMode
 | ) |  |

Set the LPTIM registers update mode (enable/disable register preload)

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_SetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
UpdateMode This parameter can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
Return values:
None

Definition at line 454 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetWaveform | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform
 | ) |  |

Set waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_SetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Return values:
None

Definition at line 602 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_StartCounter | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | OperatingMode
 | ) |  |

Starts the LPTIM counter in the desired mode.

Note:
LPTIM instance must be enabled before starting the counter.
It is possible to change on the fly from One Shot mode to Continuous mode.
Reference Manual to LL API cross reference:
CR CNTSTRT LL_LPTIM_StartCounter
CR SNGSTRT LL_LPTIM_StartCounter
Parameters:
LPTIMx Low-Power Timer instance
OperatingMode This parameter can be one of the following values:
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS
  • LL_LPTIM_OPERATING_MODE_ONESHOT
Return values:
None

Definition at line 389 of file stm32g0xx_ll_lptim.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Trigger Configuration

Functions
Trigger Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (const LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigTrigger | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Source,
 |  | uint32_t | Filter,
 |  | uint32_t | Polarity
 | ) |  |

Configure the external trigger used as a trigger event for the LPTIM.

Note:
This function must be called when the LPTIM instance is disabled.
An internal clock source must be present when a digital filter is required for the trigger.
Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_ConfigTrigger
CFGR TRGFLT LL_LPTIM_ConfigTrigger
CFGR TRIGEN LL_LPTIM_ConfigTrigger
Parameters:
LPTIMx Low-Power Timer instance
Source This parameter can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP1
  • LL_LPTIM_TRIG_SOURCE_COMP2
  • LL_LPTIM_TRIG_SOURCE_COMP3 (*)
(*) Value not defined in all devices.
Filter This parameter can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8
Polarity This parameter can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING
Return values:
None

Definition at line 816 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableTimeout ( LPTIM_TypeDef * LPTIMx )

Disable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
A trigger event arriving when the timer is already started will be ignored.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_DisableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 755 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableTimeout ( LPTIM_TypeDef * LPTIMx )

Enable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart.
The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_EnableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 741 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter ( const LPTIM_TypeDef * LPTIMx )

Get actual external trigger filter.

Reference Manual to LL API cross reference:
CFGR TRGFLT LL_LPTIM_GetTriggerFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8

Definition at line 854 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity ( const LPTIM_TypeDef * LPTIMx )

Get actual external trigger polarity.

Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING

Definition at line 868 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource ( const LPTIM_TypeDef * LPTIMx )

Get actual external trigger source.

Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_GetTriggerSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP1
  • LL_LPTIM_TRIG_SOURCE_COMP2
  • LL_LPTIM_TRIG_SOURCE_COMP3 (*)
(*) Value not defined in all devices.

Definition at line 839 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout ( const LPTIM_TypeDef * LPTIMx )

Indicate whether the timeout function is enabled.

Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 766 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_TrigSw ( LPTIM_TypeDef * LPTIMx )

Start the LPTIM counter.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_TrigSw
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 778 of file stm32g0xx_ll_lptim.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clock Configuration

Functions
Clock Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (const LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (const LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigClock | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockFilter,
 |  | uint32_t | ClockPolarity
 | ) |  |

Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.

Note:
This function must be called when the LPTIM instance is disabled.
When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.
An internal clock source must be present when a digital filter is required for external clock.
Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_ConfigClock
CFGR CKPOL LL_LPTIM_ConfigClock
Parameters:
LPTIMx Low-Power Timer instance
ClockFilter This parameter can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8
ClockPolarity This parameter can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING
Return values:
None

Definition at line 932 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter ( const LPTIM_TypeDef * LPTIMx )

Get actual clock digital filter.

Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_GetClockFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8

Definition at line 961 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity ( const LPTIM_TypeDef * LPTIMx )

Get actual clock polarity.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetClockPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING

Definition at line 946 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource ( const LPTIM_TypeDef * LPTIMx )

Get actual LPTIM instance clock source.

Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_GetClockSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL

Definition at line 904 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetClockSource | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the source of the clock used by the LPTIM instance.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_SetClockSource
Parameters:
LPTIMx Low-Power Timer instance
ClockSource This parameter can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL
Return values:
None

Definition at line 891 of file stm32g0xx_ll_lptim.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Encoder Mode

Functions
Encoder Mode
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (const LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (const LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Disable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_DisableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1027 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Enable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
In this mode the LPTIM instance must be clocked by an internal clock source. Also, the prescaler division ratio must be equal to 1.
LPTIM instance must be configured in continuous mode prior enabling the encoder mode.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_EnableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1015 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode ( const LPTIM_TypeDef * LPTIMx )

Get actual encoder mode.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING

Definition at line 999 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM operates in encoder mode.

Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_IsEnabledEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1038 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetEncoderMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Configure the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_SetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING
Return values:
None

Definition at line 985 of file stm32g0xx_ll_lptim.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG Management

Functions
FLAG Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_ClearFLAG_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (const LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (const LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (const LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (const LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (const LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (const LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (const LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload match flag (ARRMCF)

Reference Manual to LL API cross reference:
ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1079 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload register update interrupt flag (ARROKCF).

Reference Manual to LL API cross reference:
ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1146 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM ( LPTIM_TypeDef * LPTIMx )

Clear the compare match flag (CMPMCF)

Reference Manual to LL API cross reference:
ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1057 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK ( LPTIM_TypeDef * LPTIMx )

Clear the compare register update interrupt flag (CMPOKCF).

Reference Manual to LL API cross reference:
ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1123 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to down interrupt flag (DOWNCF).

Reference Manual to LL API cross reference:
ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1192 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Clear the external trigger valid edge flag(EXTTRIGCF).

Reference Manual to LL API cross reference:
ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1101 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_UP ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to up interrupt flag (UPCF).

Reference Manual to LL API cross reference:
ICR UPCF LL_LPTIM_ClearFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1169 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM ( const LPTIM_TypeDef * LPTIMx )

Inform application whether a autoreload match interrupt has occurred.

Reference Manual to LL API cross reference:
ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1090 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK ( const LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.

If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1158 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM ( const LPTIM_TypeDef * LPTIMx )

Inform application whether a compare match interrupt has occurred.

Reference Manual to LL API cross reference:
ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1068 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK ( const LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.

If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1135 of file stm32g0xx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN ( const LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1204 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG ( const LPTIM_TypeDef * LPTIMx )

Inform application whether a valid edge on the selected external trigger input has occurred.

Reference Manual to LL API cross reference:
ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1112 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP ( const LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR UP LL_LPTIM_IsActiveFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1181 of file stm32g0xx_ll_lptim.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (const LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (const LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (const LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (const LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (const LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (const LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (const LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Disable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_DisableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1267 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Disable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_DisableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1366 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Disable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_DisableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1234 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Disable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1333 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Disable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_DisableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1432 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Disable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1300 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_UP ( LPTIM_TypeDef * LPTIMx )

Disable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_DisableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1399 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Enable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_EnableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1256 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Enable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_EnableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1355 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Enable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_EnableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1223 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Enable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1322 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Enable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_EnableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1421 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Enable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1289 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_UP ( LPTIM_TypeDef * LPTIMx )

Enable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_EnableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1388 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload match interrupt (ARRMIE) is enabled.

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1278 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit(1 or 0).

Definition at line 1377 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the compare match interrupt (CMPMIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1245 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1344 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit(1 or 0).

Definition at line 1443 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG ( const LPTIM_TypeDef * LPTIMx )

Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1311 of file stm32g0xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP ( const LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to up interrupt (UPIE) is enabled.

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_IsEnabledIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit(1 or 0).

Definition at line 1410 of file stm32g0xx_ll_lptim.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPUART Private Variables

Variables
LPUART Private Variables
LPUART

Variables

static const uint16_t LPUART_PRESCALER_TAB []

Variable Documentation

const uint16_t LPUART_PRESCALER_TAB[] [static]
Initial value:
{
  (uint16_t)1,
  (uint16_t)2,
  (uint16_t)4,
  (uint16_t)6,
  (uint16_t)8,
  (uint16_t)10,
  (uint16_t)12,
  (uint16_t)16,
  (uint16_t)32,
  (uint16_t)64,
  (uint16_t)128,
  (uint16_t)256
}

Definition at line 46 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPUART Private Constants

Defines
LPUART Private Constants
LPUART

Defines

#define | LPUART_LPUARTDIV_FREQ_MUL 256U
#define | LPUART_BRR_MASK 0x000FFFFFU
#define | LPUART_BRR_MIN_VALUE 0x00000300U

Define Documentation

#define LPUART_BRR_MASK 0x000FFFFFU

Definition at line 71 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_BRR_MIN_VALUE 0x00000300U

Definition at line 72 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_LPUARTDIV_FREQ_MUL 256U

Definition at line 70 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LPUART Private Macros

Defines
LPUART Private Macros
LPUART

Defines

#define | IS_LL_LPUART_PRESCALER(__VALUE__)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
#define | IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_LPUART_BAUDRATE ( __BAUDRATE__ ) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))

Definition at line 78 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_BRR_MAX ( __VALUE__ ) ((__VALUE__) <= 0x000FFFFFU)

Definition at line 84 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 0x300U)

Definition at line 81 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))

Definition at line 95 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))

Definition at line 86 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))

Definition at line 102 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PARITY_NONE) \
                                        || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
                                        || ((__VALUE__) == LL_LPUART_PARITY_ODD))

Definition at line 91 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))

Definition at line 59 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_STOPBITS_1) \
                                          || ((__VALUE__) == LL_LPUART_STOPBITS_2))

Definition at line 99 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_LPUART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPUART_InitTypeDef Struct Reference
LPUART Exported Init structures

LL LPUART Init Structure definition. More...

#include <stm32g0xx_ll_lpuart.h>

Data Fields

uint32_t | PrescalerValue
uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl

Detailed Description

LL LPUART Init Structure definition.

Definition at line 97 of file stm32g0xx_ll_lpuart.h.

Field Documentation

uint32_t LL_LPUART_InitTypeDef::BaudRate

This field defines expected LPUART communication baud rate.

This feature can be modified afterwards using unitary function LL_LPUART_SetBaudRate().

Definition at line 105 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_LPUART_SetDataWidth().

Definition at line 110 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetHWFlowCtrl().

Definition at line 134 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetParity().

Definition at line 122 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::PrescalerValue

Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of Clock Source Prescaler.

This feature can be modified afterwards using unitary function LL_LPUART_SetPrescaler().

Definition at line 99 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_LPUART_SetStopBitsLength().

Definition at line 116 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Direction.

This feature can be modified afterwards using unitary function LL_LPUART_SetTransferDirection().

Definition at line 128 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_lpuart.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_WriteReg function. More...

Defines

#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NECF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_LPUART_WriteReg function.

Define Documentation

#define LL_LPUART_ICR_CMCF USART_ICR_CMCF

Character match clear flag

Definition at line 163 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF

CTS clear flag

Definition at line 162 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ICR_FECF USART_ICR_FECF

Framing error clear flag

Definition at line 157 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected clear flag

Definition at line 160 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ICR_NCF USART_ICR_NECF

Noise error detected clear flag

Definition at line 158 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ICR_ORECF USART_ICR_ORECF

Overrun error clear flag

Definition at line 159 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ICR_PECF USART_ICR_PECF

Parity error clear flag

Definition at line 156 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ICR_TCCF USART_ICR_TCCF

Transmission complete clear flag

Definition at line 161 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode clear flag

Definition at line 164 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_ReadReg function. More...

Defines

#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_ISR_TXFE USART_ISR_TXFE
#define | LL_LPUART_ISR_RXFF USART_ISR_RXFF
#define | LL_LPUART_ISR_RXFT USART_ISR_RXFT
#define | LL_LPUART_ISR_TXFT USART_ISR_TXFT

Detailed Description

Flags defines which can be used with LL_LPUART_ReadReg function.

Define Documentation

#define LL_LPUART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 183 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 184 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 182 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 181 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 174 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 177 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 175 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 176 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 173 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 189 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 186 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

Definition at line 191 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

Definition at line 192 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

Definition at line 178 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 185 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 179 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 188 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO Not Full flag

Definition at line 180 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

Definition at line 190 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

Definition at line 193 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 187 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
LPUART Exported Constants

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions. More...

Defines

#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

Detailed Description

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

Define Documentation

#define LL_LPUART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 209 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 202 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 208 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

Definition at line 211 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

Definition at line 203 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 205 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

Definition at line 206 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

Definition at line 210 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 213 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 212 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

Definition at line 216 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

Definition at line 215 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 214 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
LPUART Exported Constants

Defines

#define | LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U

Define Documentation

#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

Definition at line 226 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

Definition at line 225 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

Definition at line 224 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

Definition at line 227 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

Definition at line 228 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Definition at line 229 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Direction

Defines
Direction
LPUART Exported Constants

Defines

#define | LL_LPUART_DIRECTION_NONE 0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_LPUART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 237 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 238 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 239 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 240 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

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STM32G0C1xx HAL User Manual: Parity Control

Defines
Parity Control
LPUART Exported Constants

Defines

#define | LL_LPUART_PARITY_NONE 0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_LPUART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 249 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 248 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 250 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Wakeup

Defines
Wakeup
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_IDLELINE 0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

LPUART wake up from Mute mode on Address Mark

Definition at line 259 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U

LPUART wake up from Mute mode on Idle Line

Definition at line 258 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Datawidth

Defines
Datawidth
LPUART Exported Constants

Defines

#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B 0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 267 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 268 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 269 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Clock Source Prescaler

Defines
Clock Source Prescaler
LPUART Exported Constants

Defines

#define | LL_LPUART_PRESCALER_DIV1 0x00000000U
#define | LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV6
#define | LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_LPUART_PRESCALER_DIV10
#define | LL_LPUART_PRESCALER_DIV12
#define | LL_LPUART_PRESCALER_DIV16
#define | LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_LPUART_PRESCALER_DIV64
#define | LL_LPUART_PRESCALER_DIV128
#define | LL_LPUART_PRESCALER_DIV256

Define Documentation

#define LL_LPUART_PRESCALER_DIV1 0x00000000U

Input clock not divided

Definition at line 277 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PRESCALER_DIV10
Value:
(USART_PRESC_PRESCALER_2 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 10

Definition at line 283 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV12
Value:
(USART_PRESC_PRESCALER_2 |\
                                    USART_PRESC_PRESCALER_1)

Input clock divided by 12

Definition at line 285 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV128
Value:
(USART_PRESC_PRESCALER_3 |\
                                    USART_PRESC_PRESCALER_1)

Input clock divided by 128

Definition at line 293 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV16
Value:
(USART_PRESC_PRESCALER_2 |\
                                    USART_PRESC_PRESCALER_1 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 16

Definition at line 287 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock divided by 2

Definition at line 278 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV256
Value:
(USART_PRESC_PRESCALER_3 |\
                                    USART_PRESC_PRESCALER_1 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 256

Definition at line 295 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock divided by 32

Definition at line 290 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock divided by 4

Definition at line 279 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV6
Value:
(USART_PRESC_PRESCALER_1 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 6

Definition at line 280 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV64
Value:
(USART_PRESC_PRESCALER_3 |\
                                    USART_PRESC_PRESCALER_0)

Input clock divided by 64

Definition at line 291 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock divided by 8

Definition at line 282 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Stop Bits

Defines
Stop Bits
LPUART Exported Constants

Defines

#define | LL_LPUART_STOPBITS_1 0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_LPUART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 305 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 306 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
LPUART Exported Constants

Defines

#define | LL_LPUART_TXRX_STANDARD 0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_LPUART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 314 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 315 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 324 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 323 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 333 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 332 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 343 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 341 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Bit Order

Defines
Bit Order
LPUART Exported Constants

Defines

#define | LL_LPUART_BITORDER_LSBFIRST 0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 353 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 355 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Address Length Detection

Defines
Address Length Detection
LPUART Exported Constants

Defines

#define | LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 364 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 365 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Hardware Control

Defines
Hardware Control
LPUART Exported Constants

Defines

#define | LL_LPUART_HWCONTROL_NONE 0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 376 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 373 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 374 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 378 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 386 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 388 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 387 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
LPUART Exported Constants

Defines

#define | LL_LPUART_DE_POLARITY_HIGH 0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 396 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 397 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
LPUART Exported Constants

Defines

#define | LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 406 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 405 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_DMA_GetRegAddr().

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPUART Exported Macros

Defines

#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.

Define Documentation

#define LL_LPUART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 439 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 431 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Helper Macros

Defines
Helper Macros
LPUART Exported Macros

Defines

#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Define Documentation

#define __LL_LPUART_DIV | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
(uint32_t)\
  ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
      * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)

Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for LPUART Instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
__BAUDRATE__ | Baud Rate value to achieve
Return values:
LPUARTDIV value to be used for BRR register filling

Definition at line 468 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_SetBaudRate().

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STM32G0C1xx HAL User Manual: Configuration functions

Functions
Configuration functions
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (const USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_LPUART_DisableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledFIFO (const USART_TypeDef *LPUARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetTXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXFIFOThreshold (const USART_TypeDef *LPUARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_SetRXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXFIFOThreshold (const USART_TypeDef *LPUARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_ConfigFIFOsThreshold (USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (const USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (const USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (const USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (const USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (const USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (const USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetPrescaler (USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_LPUART_GetPrescaler (const USART_TypeDef *LPUARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (const USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (const USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (const USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (const USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (const USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (const USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (const USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (const USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (const USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (const USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (const USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Function Documentation

__STATIC_INLINE void LL_LPUART_ConfigCharacter | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_LPUART_SetDataWidth() function
  • Parity Control and mode configuration using LL_LPUART_SetParity() function
  • Stop bits configuration using LL_LPUART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_ConfigCharacter
CR1 PCE LL_LPUART_ConfigCharacter
CR1 M LL_LPUART_ConfigCharacter
CR2 STOP LL_LPUART_ConfigCharacter
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 996 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TXThreshold,
 |  | uint32_t | RXThreshold
 | ) |  |

Configure TX and RX FIFOs Threshold.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold
CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
Parameters:
LPUARTx LPUART Instance
TXThreshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
RXThreshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 654 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigNodeAddress | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the LPUART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_ConfigNodeAddress
CR2 ADDM7 LL_LPUART_ConfigNodeAddress
Parameters:
LPUARTx | LPUART Instance
AddressLen This parameter can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the LPUART node.
Return values:
None

Definition at line 1168 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Disable ( USART_TypeDef * LPUARTx )

LPUART Disable.

Note:
When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUARTx_ISR are set to their default values.
In order to go into low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit.
Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Disable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 514 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1241 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_DisableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 714 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_DisableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 736 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableFIFO ( USART_TypeDef * LPUARTx )

FIFO Mode Disable.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_DisableFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 547 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableInStopMode ( USART_TypeDef * LPUARTx )

LPUART disabled in STOP Mode.

Note:
When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_DisableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 680 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableMuteMode ( USART_TypeDef * LPUARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_DisableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 882 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableOverrunDetect ( USART_TypeDef * LPUARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_DisableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1296 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1219 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Enable ( USART_TypeDef * LPUARTx )

LPUART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Enable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 495 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1230 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_EnableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 703 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_EnableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 725 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableFIFO ( USART_TypeDef * LPUARTx )

FIFO Mode Enable.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_EnableFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 536 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableInStopMode ( USART_TypeDef * LPUARTx )

LPUART enabled in STOP Mode.

Note:
When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that LPUART clock selection is HSI or LSE in RCC.
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_EnableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 668 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableMuteMode ( USART_TypeDef * LPUARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_EnableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 871 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableOverrunDetect ( USART_TypeDef * LPUARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_EnableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1285 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1208 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate | ( | const USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue
 | ) |  |

Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_GetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
Return values:
Baud Rate

Definition at line 1401 of file stm32g0xx_ll_lpuart.h.

References LPUART_BRR_MASK, LPUART_BRR_MIN_VALUE, and LPUART_LPUARTDIV_FREQ_MUL.

__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic ( const USART_TypeDef * LPUARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_GetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE

Definition at line 1109 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth ( const USART_TypeDef * LPUARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_GetDataWidth
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B

Definition at line 860 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl ( const USART_TypeDef * LPUARTx )

Return HW Flow Control configuration (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_GetHWFlowCtrl
CR3 CTSE LL_LPUART_GetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS

Definition at line 1274 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress ( const USART_TypeDef * LPUARTx )

Return 8 bit Address of the LPUART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_GetNodeAddress
Parameters:
LPUARTx LPUART Instance
Return values:
Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1184 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen ( const USART_TypeDef * LPUARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_LPUART_GetNodeAddressLen
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B

Definition at line 1197 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetParity ( const USART_TypeDef * LPUARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_GetParity
CR1 PCE LL_LPUART_GetParity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD

Definition at line 804 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler ( const USART_TypeDef * LPUARTx )

Retrieve the Clock source prescaler for baudrate generator and oversampling.

Reference Manual to LL API cross reference:
PRESC PRESCALER LL_LPUART_GetPrescaler
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256

Definition at line 940 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold ( const USART_TypeDef * LPUARTx )

Return RX FIFO Threshold Configuration.

Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8

Definition at line 628 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel ( const USART_TypeDef * LPUARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_GetRXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED

Definition at line 1052 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength ( const USART_TypeDef * LPUARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_GetStopBitsLength
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2

Definition at line 967 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder ( const USART_TypeDef * LPUARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST

Definition at line 1140 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection ( const USART_TypeDef * LPUARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_GetTransferDirection
CR1 TE LL_LPUART_GetTransferDirection
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX

Definition at line 770 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold ( const USART_TypeDef * LPUARTx )

Return TX FIFO Threshold Configuration.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8

Definition at line 593 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel ( const USART_TypeDef * LPUARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_GetTXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED

Definition at line 1079 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap ( const USART_TypeDef * LPUARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_GetTXRXSwap
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED

Definition at line 1025 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod ( const USART_TypeDef * LPUARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_GetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK

Definition at line 831 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType ( const USART_TypeDef * LPUARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_GetWKUPType
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE

Definition at line 1336 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabled ( const USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_IsEnabled
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 525 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO ( const USART_TypeDef * LPUARTx )

Indicate if FIFO Mode is enabled.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_IsEnabledFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 558 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode ( const USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_IsEnabledInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 692 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode ( const USART_TypeDef * LPUARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_IsEnabledMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 893 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect ( const USART_TypeDef * LPUARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1307 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetBaudRate | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | BaudRate
 | ) |  |

Configure LPUART BRR register for achieving expected Baud Rate value.

Note:
Compute and set LPUARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock and expected Baud Rate values
Peripheral clock and Baud Rate values provided as function parameters should be valid (Baud rate value != 0).
Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, a care should be taken when generating high baud rates using high PeriphClk values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_SetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
BaudRate | Baud Rate
Return values:
None

Definition at line 1370 of file stm32g0xx_ll_lpuart.h.

References __LL_LPUART_DIV.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_SetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
DataLogic This parameter can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1096 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDataWidth | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_SetDataWidth
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Return values:
None

Definition at line 846 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_SetHWFlowCtrl
CR3 CTSE LL_LPUART_SetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1258 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetParity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled)

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_SetParity
CR1 PCE LL_LPUART_SetParity
Parameters:
LPUARTx LPUART Instance
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
Return values:
None

Definition at line 789 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetPrescaler | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Configure Clock source prescaler for baudrate generator and oversampling.

Reference Manual to LL API cross reference:
PRESC PRESCALER LL_LPUART_SetPrescaler
Parameters:
LPUARTx LPUART Instance
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
Return values:
None

Definition at line 917 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure RX FIFO Threshold.

Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Threshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 611 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetRXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_SetRXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1039 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetStopBitsLength | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_SetStopBitsLength
Parameters:
LPUARTx LPUART Instance
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 954 of file stm32g0xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetTransferBitOrder | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
BitOrder This parameter can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1125 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTransferDirection | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_SetTransferDirection
CR1 TE LL_LPUART_SetTransferDirection
Parameters:
LPUARTx LPUART Instance
TransferDirection This parameter can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX
Return values:
None

Definition at line 754 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure TX FIFO Threshold.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Threshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 576 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_SetTXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1066 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXRXSwap | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_SetTXRXSwap
Parameters:
LPUARTx LPUART Instance
SwapConfig This parameter can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED
Return values:
None

Definition at line 1012 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWakeUpMethod | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_SetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Method This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 818 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWKUPType | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_SetWKUPType
Parameters:
LPUARTx LPUART Instance
Type This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1322 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (const USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableHalfDuplex ( USART_TypeDef * LPUARTx )

Disable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_DisableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1447 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableHalfDuplex ( USART_TypeDef * LPUARTx )

Enable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_EnableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1436 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex ( const USART_TypeDef * LPUARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1458 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (const USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (const USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (const USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (const USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDEMode ( USART_TypeDef * LPUARTx )

Disable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_DisableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1534 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDEMode ( USART_TypeDef * LPUARTx )

Enable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_EnableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1523 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime ( const USART_TypeDef * LPUARTx )

Return DEAT (Driver Enable Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_GetDEAssertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31

Definition at line 1512 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime ( const USART_TypeDef * LPUARTx )

Return DEDT (Driver Enable De-Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_GetDEDeassertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : c

Definition at line 1489 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity ( const USART_TypeDef * LPUARTx )

Return Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_GetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW

Definition at line 1572 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode ( const USART_TypeDef * LPUARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_IsEnabledDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1545 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEAssertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_SetDEAssertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1501 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_SetDEDeassertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1478 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDESignalPolarity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_SetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Polarity This parameter can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW
Return values:
None

Definition at line 1559 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG_Management

Defines | Functions
FLAG_Management
LPUART Exported Functions

Defines

#define | LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
#define | LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF

Functions

__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (const USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (const USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (const USART_TypeDef *LPUARTx)
Check if the LPUART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (const USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (const USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE_RXFNE (const USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE_TXFNF (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (const USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (const USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (const USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (const USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (const USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (const USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFE (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFF (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFT (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFT (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.

Define Documentation

#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE

Definition at line 1641 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF

Definition at line 1666 of file stm32g0xx_ll_lpuart.h.

Function Documentation

__STATIC_INLINE void LL_LPUART_ClearFlag_CM ( USART_TypeDef * LPUARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_LPUART_ClearFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1905 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_FE ( USART_TypeDef * LPUARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_LPUART_ClearFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1839 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE ( USART_TypeDef * LPUARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_LPUART_ClearFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1872 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS ( USART_TypeDef * LPUARTx )

Clear CTS Interrupt Flag.

Reference Manual to LL API cross reference:
ICR CTSCF LL_LPUART_ClearFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1894 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_NE ( USART_TypeDef * LPUARTx )

Clear Noise detected Flag.

Reference Manual to LL API cross reference:
ICR NECF LL_LPUART_ClearFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1850 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_ORE ( USART_TypeDef * LPUARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_LPUART_ClearFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1861 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_PE ( USART_TypeDef * LPUARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_LPUART_ClearFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1828 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_TC ( USART_TypeDef * LPUARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_LPUART_ClearFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1883 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP ( USART_TypeDef * LPUARTx )

Clear Wake Up from stop mode Flag.

Reference Manual to LL API cross reference:
ICR WUCF LL_LPUART_ClearFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1916 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY ( const USART_TypeDef * LPUARTx )

Check if the LPUART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_LPUART_IsActiveFlag_BUSY
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1707 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM ( const USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_LPUART_IsActiveFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1718 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS ( const USART_TypeDef * LPUARTx )

Check if the LPUART CTS Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTS LL_LPUART_IsActiveFlag_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1696 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_LPUART_IsActiveFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1602 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE ( const USART_TypeDef * LPUARTx )

Check if the LPUART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_LPUART_IsActiveFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1635 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS ( const USART_TypeDef * LPUARTx )

Check if the LPUART CTS interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1685 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_LPUART_IsActiveFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1613 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE ( const USART_TypeDef * LPUARTx )

Check if the LPUART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_LPUART_IsActiveFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1624 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_LPUART_IsActiveFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1591 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK ( const USART_TypeDef * LPUARTx )

Check if the LPUART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_LPUART_IsActiveFlag_REACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1773 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU ( const USART_TypeDef * LPUARTx )

Check if the LPUART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_LPUART_IsActiveFlag_RWU
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1740 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF ( const USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Full Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXFF LL_LPUART_IsActiveFlag_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1795 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT ( const USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Threshold Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXFT LL_LPUART_IsActiveFlag_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1817 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1649 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK ( const USART_TypeDef * LPUARTx )

Check if the LPUART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_LPUART_IsActiveFlag_SBK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1729 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC ( const USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_LPUART_IsActiveFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1660 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK ( const USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_LPUART_IsActiveFlag_TEACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1762 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF ( const USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1674 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE ( const USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXFE LL_LPUART_IsActiveFlag_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1784 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT ( const USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Threshold Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXFT LL_LPUART_IsActiveFlag_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1806 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP ( const USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from stop mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR WUF LL_LPUART_IsActiveFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1751 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT_Management

Defines | Functions
IT_Management
LPUART Exported Functions

Defines

#define | LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
#define | LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
#define | LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
#define | LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
#define | LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
#define | LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFE (USART_TypeDef *LPUARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFF (USART_TypeDef *LPUARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFT (USART_TypeDef *LPUARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFT (USART_TypeDef *LPUARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFE (USART_TypeDef *LPUARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFF (USART_TypeDef *LPUARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFT (USART_TypeDef *LPUARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFT (USART_TypeDef *LPUARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (const USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE_RXFNE (const USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE_TXFNF (const USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (const USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (const USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFE (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFF (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (const USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (const USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFT (const USART_TypeDef *LPUARTx)
Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFT (const USART_TypeDef *LPUARTx)
Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.

Define Documentation

#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE

Definition at line 2094 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF

Definition at line 2119 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE

Definition at line 1941 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF

Definition at line 1966 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE

Definition at line 2247 of file stm32g0xx_ll_lpuart.h.

#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Definition at line 2272 of file stm32g0xx_ll_lpuart.h.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableIT_CM ( USART_TypeDef * LPUARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_DisableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2149 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_CTS ( USART_TypeDef * LPUARTx )

Disable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_DisableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2197 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_ERROR ( USART_TypeDef * LPUARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_DisableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2186 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_IDLE ( USART_TypeDef * LPUARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_DisableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2088 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_PE ( USART_TypeDef * LPUARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_DisableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2138 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXFF ( USART_TypeDef * LPUARTx )

Disable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_DisableIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2171 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXFT ( USART_TypeDef * LPUARTx )

Disable RX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_DisableIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2230 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Disable RX Not Empty and RX FIFO Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2102 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TC ( USART_TypeDef * LPUARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_DisableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2113 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Disable TX Empty and TX FIFO Not Full Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2127 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXFE ( USART_TypeDef * LPUARTx )

Disable TX FIFO Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_DisableIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2160 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXFT ( USART_TypeDef * LPUARTx )

Disable TX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_DisableIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2219 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_WKUP ( USART_TypeDef * LPUARTx )

Disable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_DisableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2208 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CM ( USART_TypeDef * LPUARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_EnableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1996 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CTS ( USART_TypeDef * LPUARTx )

Enable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_EnableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2044 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_ERROR ( USART_TypeDef * LPUARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_EnableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2033 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_IDLE ( USART_TypeDef * LPUARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_EnableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1935 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_PE ( USART_TypeDef * LPUARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_EnableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1985 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXFF ( USART_TypeDef * LPUARTx )

Enable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_EnableIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2018 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXFT ( USART_TypeDef * LPUARTx )

Enable RX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_EnableIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2077 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Enable RX Not Empty and RX FIFO Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1949 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TC ( USART_TypeDef * LPUARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_EnableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1960 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Enable TX Empty and TX FIFO Not Full Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1974 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXFE ( USART_TypeDef * LPUARTx )

Enable TX FIFO Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_EnableIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2007 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXFT ( USART_TypeDef * LPUARTx )

Enable TX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_EnableIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2066 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_WKUP ( USART_TypeDef * LPUARTx )

Enable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_EnableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2055 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM ( const USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_IsEnabledIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2302 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS ( const USART_TypeDef * LPUARTx )

Check if the LPUART CTS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2346 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR ( const USART_TypeDef * LPUARTx )

Check if the LPUART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_IsEnabledIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2335 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE ( const USART_TypeDef * LPUARTx )

Check if the LPUART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2241 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE ( const USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_IsEnabledIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2291 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF ( const USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2324 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT ( const USART_TypeDef * LPUARTx )

Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2379 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE ( const USART_TypeDef * LPUARTx )

Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2255 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC ( const USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_IsEnabledIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2266 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF ( const USART_TypeDef * LPUARTx )

Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2280 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE ( const USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2313 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT ( const USART_TypeDef * LPUARTx )

Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2368 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP ( const USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2357 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA_Management

Functions
DMA_Management
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (const USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (const USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (const USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (const USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2475 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_DisableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2409 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_DisableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2442 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr | ( | const USART_TypeDef * | LPUARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the LPUART data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_DMA_GetRegAddr
Parameters:
LPUARTx LPUART Instance
Direction This parameter can be one of the following values:
  • LL_LPUART_DMA_REG_DATA_TRANSMIT
  • LL_LPUART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 2501 of file stm32g0xx_ll_lpuart.h.

References LL_LPUART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2464 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_EnableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2398 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_EnableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2431 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr ( const USART_TypeDef * LPUARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2486 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX ( const USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2420 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX ( const USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2453 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data_Management

Functions
Data_Management
LPUART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (const USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (const USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8 ( const USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData8
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2533 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9 ( const USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData9
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 2544 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData8 | ( | USART_TypeDef * | LPUARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData8
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2556 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData9 | ( | USART_TypeDef * | LPUARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData9
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 2568 of file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Execution

Functions
Execution
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data and FIFO flush.

Function Documentation

__STATIC_INLINE void LL_LPUART_RequestBreakSending ( USART_TypeDef * LPUARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_LPUART_RequestBreakSending
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2587 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode ( USART_TypeDef * LPUARTx )

Put LPUART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_LPUART_RequestEnterMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2598 of file stm32g0xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestRxDataFlush ( USART_TypeDef * LPUARTx )

Request a Receive Data and FIFO flush.

Note:
Allows to discard the received data without reading them, and avoid an overrun condition.
Reference Manual to LL API cross reference:
RQR RXFRQ LL_LPUART_RequestRxDataFlush
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2611 of file stm32g0xx_ll_lpuart.h.

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STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
LPUART Exported Functions

Functions

ErrorStatus | LL_LPUART_DeInit (const USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_LPUART_DeInit ( const USART_TypeDef * LPUARTx )

De-initialize LPUART registers (Registers restored to their default values).

Parameters:
LPUARTx LPUART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are de-initialized
  • ERROR: not applicable

Definition at line 129 of file stm32g0xx_ll_lpuart.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_LPUART1, LL_APB1_GRP1_PERIPH_LPUART2, and LL_APB1_GRP1_ReleaseReset().

ErrorStatus LL_LPUART_Init | ( | USART_TypeDef * | LPUARTx,
 |  | const LL_LPUART_InitTypeDef * | LPUART_InitStruct
 | ) |  |

Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.

Note:
As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0), LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
LPUARTx | LPUART Instance
LPUART_InitStruct | pointer to a LL_LPUART_InitTypeDef structure that contains the configuration information for the specified LPUART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
  • ERROR: Problem occurred during LPUART Registers initialization

Definition at line 177 of file stm32g0xx_ll_lpuart.c.

References assert_param, LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, IS_LL_LPUART_BAUDRATE, IS_LL_LPUART_BRR_MAX, IS_LL_LPUART_BRR_MIN, IS_LL_LPUART_DATAWIDTH, IS_LL_LPUART_DIRECTION, IS_LL_LPUART_HWCONTROL, IS_LL_LPUART_PARITY, IS_LL_LPUART_PRESCALER, IS_LL_LPUART_STOPBITS, LL_LPUART_IsEnabled(), LL_LPUART_SetBaudRate(), LL_LPUART_SetHWFlowCtrl(), LL_LPUART_SetPrescaler(), LL_LPUART_SetStopBitsLength(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_LPUART1_CLKSOURCE, LL_RCC_LPUART2_CLKSOURCE, LL_RCC_PERIPH_FREQUENCY_NO, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::PrescalerValue, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

void LL_LPUART_StructInit ( LL_LPUART_InitTypeDef * LPUART_InitStruct )

Set each LL_LPUART_InitTypeDef field to default value.

Parameters:
LPUART_InitStruct pointer to a LL_LPUART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 281 of file stm32g0xx_ll_lpuart.c.

References LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, LL_LPUART_DATAWIDTH_8B, LL_LPUART_DIRECTION_TX_RX, LL_LPUART_HWCONTROL_NONE, LL_LPUART_PARITY_NONE, LL_LPUART_PRESCALER_DIV1, LL_LPUART_STOPBITS_1, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::PrescalerValue, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

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STM32G0C1xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_WriteReg function. More...

Defines

#define | LL_PWR_SCR_CSBF PWR_SCR_CSBF
#define | LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define | LL_PWR_SCR_CWUF6 PWR_SCR_CWUF6
#define | LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define | LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define | LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define | LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define | LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1

Detailed Description

Flags defines which can be used with LL_PWR_WriteReg function.

Define Documentation

#define LL_PWR_SCR_CSBF PWR_SCR_CSBF

Definition at line 57 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF PWR_SCR_CWUF

Definition at line 58 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1

Definition at line 66 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2

Definition at line 65 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3

Definition at line 63 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4

Definition at line 61 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5

Definition at line 60 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF6 PWR_SCR_CWUF6

Definition at line 59 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_ReadReg function. More...

Defines

#define | LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define | LL_PWR_SR1_SBF PWR_SR1_SBF
#define | LL_PWR_SR1_WUF6 PWR_SR1_WUF6
#define | LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define | LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define | LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define | LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define | LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#define | LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define | LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define | LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define | LL_PWR_SR2_REGLPS PWR_SR2_REGLPS

Detailed Description

Flags defines which can be used with LL_PWR_ReadReg function.

Define Documentation

#define LL_PWR_SR1_SBF PWR_SR1_SBF

Definition at line 76 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1

Definition at line 84 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2

Definition at line 83 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3

Definition at line 81 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4

Definition at line 79 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5

Definition at line 78 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR1_WUF6 PWR_SR1_WUF6

Definition at line 77 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR1_WUFI PWR_SR1_WUFI

Definition at line 75 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR2_PVDO PWR_SR2_PVDO

Definition at line 86 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF

Definition at line 89 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS

Definition at line 90 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_SR2_VOSF PWR_SR2_VOSF

Definition at line 88 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: REGU VOLTAGE

Defines
REGU VOLTAGE
PWR Exported Constants

Defines

#define | LL_PWR_REGU_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Define Documentation

#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_CR1_VOS_0

Definition at line 98 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Definition at line 99 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: MODE PWR

Defines
MODE PWR
PWR Exported Constants

Defines

#define | LL_PWR_MODE_STOP0 (0x00000000UL)
#define | LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
#define | LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)
#define | LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)

Define Documentation

#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)

Definition at line 111 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)

Definition at line 109 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_MODE_STOP0 (0x00000000UL)

Definition at line 107 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)

Definition at line 108 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: PVDLEVEL

Defines
PVDLEVEL
PWR Exported Constants

Defines

#define | LL_PWR_PVDLLEVEL_0 0x000000000u /* VPVD0 > 2.05 V */
#define | LL_PWR_PVDLLEVEL_1 (PWR_CR2_PVDFT_0) /* VPVD0 > 2.2 V */
#define | LL_PWR_PVDLLEVEL_2 (PWR_CR2_PVDFT_1) /* VPVD1 > 2.36 V */
#define | LL_PWR_PVDLLEVEL_3 (PWR_CR2_PVDFT_1 | PWR_CR2_PVDFT_0) /* VPVD2 > 2.52 V */
#define | LL_PWR_PVDLLEVEL_4 (PWR_CR2_PVDFT_2) /* VPVD3 > 2.64 V */
#define | LL_PWR_PVDLLEVEL_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0) /* VPVD4 > 2.81 V */
#define | LL_PWR_PVDLLEVEL_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1) /* VPVD5 > 2.91 V */
#define | LL_PWR_PVDHLEVEL_0 0x00000000u /* VPDD0 > 2.15 V */
#define | LL_PWR_PVDHLEVEL_1 (PWR_CR2_PVDRT_0) /* VPVD1 > 2.3 V */
#define | LL_PWR_PVDHLEVEL_2 (PWR_CR2_PVDRT_1) /* VPVD1 > 2.46 V */
#define | LL_PWR_PVDHLEVEL_3 (PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* VPVD2 > 2.62 V */
#define | LL_PWR_PVDHLEVEL_4 (PWR_CR2_PVDRT_2) /* VPVD3 > 2.74 V */
#define | LL_PWR_PVDHLEVEL_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0) /* VPVD4 > 2.91 V */
#define | LL_PWR_PVDHLEVEL_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1) /* VPVD5 > 3.01 V */
#define | LL_PWR_PVDHLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* External input analog voltage (Compare internally to VREFINT) */

Define Documentation

#define LL_PWR_PVDHLEVEL_0 0x00000000u /* VPDD0 > 2.15 V */

Definition at line 129 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDHLEVEL_1 (PWR_CR2_PVDRT_0) /* VPVD1 > 2.3 V */

Definition at line 130 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDHLEVEL_2 (PWR_CR2_PVDRT_1) /* VPVD1 > 2.46 V */

Definition at line 131 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDHLEVEL_3 (PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* VPVD2 > 2.62 V */

Definition at line 132 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDHLEVEL_4 (PWR_CR2_PVDRT_2) /* VPVD3 > 2.74 V */

Definition at line 133 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDHLEVEL_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0) /* VPVD4 > 2.91 V */

Definition at line 134 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDHLEVEL_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1) /* VPVD5 > 3.01 V */

Definition at line 135 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDHLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* External input analog voltage (Compare internally to VREFINT) */

Definition at line 136 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDLLEVEL_0 0x000000000u /* VPVD0 > 2.05 V */

Definition at line 121 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDLLEVEL_1 (PWR_CR2_PVDFT_0) /* VPVD0 > 2.2 V */

Definition at line 122 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDLLEVEL_2 (PWR_CR2_PVDFT_1) /* VPVD1 > 2.36 V */

Definition at line 123 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDLLEVEL_3 (PWR_CR2_PVDFT_1 | PWR_CR2_PVDFT_0) /* VPVD2 > 2.52 V */

Definition at line 124 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDLLEVEL_4 (PWR_CR2_PVDFT_2) /* VPVD3 > 2.64 V */

Definition at line 125 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDLLEVEL_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0) /* VPVD4 > 2.81 V */

Definition at line 126 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_PVDLLEVEL_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1) /* VPVD5 > 2.91 V */

Definition at line 127 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: PVM_IP

Defines
PVM_IP
PWR Exported Constants

Defines

#define LL_PWR_PVM_USB PWR_CR2_PVMEN_USB

Define Documentation

#define LL_PWR_PVM_USB PWR_CR2_PVMEN_USB

Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2)

Definition at line 146 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: WAKEUP

Defines
WAKEUP
PWR Exported Constants

Defines

#define | LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define | LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define | LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
#define | LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6)

Define Documentation

#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)

Definition at line 155 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)

Definition at line 156 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)

Definition at line 158 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)

Definition at line 160 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)

Definition at line 162 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6)

Definition at line 164 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: BATT CHARG RESISTOR

Defines
BATT CHARG RESISTOR
PWR Exported Constants

Defines

#define | LL_PWR_BATTCHARG_RESISTOR_5K 0x000000000u
#define | LL_PWR_BATTCHARG_RESISTOR_1_5K (PWR_CR4_VBRS)

Define Documentation

#define LL_PWR_BATTCHARG_RESISTOR_1_5K (PWR_CR4_VBRS)

Definition at line 173 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_BATTCHARG_RESISTOR_5K 0x000000000u

Definition at line 172 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: GPIO

Defines
GPIO
PWR Exported Constants

Defines

#define | LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define | LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define | LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define | LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define | LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define | LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))

Define Documentation

#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))

Definition at line 181 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))

Definition at line 182 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))

Definition at line 183 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))

Definition at line 184 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))

Definition at line 186 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))

Definition at line 188 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: GPIO BIT

Defines
GPIO BIT
PWR Exported Constants

Defines

#define | LL_PWR_GPIO_BIT_0 0x00000001u
#define | LL_PWR_GPIO_BIT_1 0x00000002u
#define | LL_PWR_GPIO_BIT_2 0x00000004u
#define | LL_PWR_GPIO_BIT_3 0x00000008u
#define | LL_PWR_GPIO_BIT_4 0x00000010u
#define | LL_PWR_GPIO_BIT_5 0x00000020u
#define | LL_PWR_GPIO_BIT_6 0x00000040u
#define | LL_PWR_GPIO_BIT_7 0x00000080u
#define | LL_PWR_GPIO_BIT_8 0x00000100u
#define | LL_PWR_GPIO_BIT_9 0x00000200u
#define | LL_PWR_GPIO_BIT_10 0x00000400u
#define | LL_PWR_GPIO_BIT_11 0x00000800u
#define | LL_PWR_GPIO_BIT_12 0x00001000u
#define | LL_PWR_GPIO_BIT_13 0x00002000u
#define | LL_PWR_GPIO_BIT_14 0x00004000u
#define | LL_PWR_GPIO_BIT_15 0x00008000u

Define Documentation

#define LL_PWR_GPIO_BIT_0 0x00000001u

Definition at line 196 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_1 0x00000002u

Definition at line 197 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_10 0x00000400u

Definition at line 206 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_11 0x00000800u

Definition at line 207 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_12 0x00001000u

Definition at line 208 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_13 0x00002000u

Definition at line 209 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_14 0x00004000u

Definition at line 210 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_15 0x00008000u

Definition at line 211 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_2 0x00000004u

Definition at line 198 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_3 0x00000008u

Definition at line 199 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_4 0x00000010u

Definition at line 200 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_5 0x00000020u

Definition at line 201 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_6 0x00000040u

Definition at line 202 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_7 0x00000080u

Definition at line 203 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_8 0x00000100u

Definition at line 204 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_9 0x00000200u

Definition at line 205 of file stm32g0xx_ll_pwr.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
PWR Exported Macros

Defines

#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Define Documentation

#define LL_PWR_ReadReg ( __REG__ ) READ_REG(PWR->__REG__)

Read a value in PWR register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 242 of file stm32g0xx_ll_pwr.h.

#define LL_PWR_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(PWR->__REG__, (__VALUE__))

Write a value in PWR register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 235 of file stm32g0xx_ll_pwr.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableLowPowerRunMode (void)
Switch the regulator from main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_DisableLowPowerRunMode (void)
Switch the regulator from low-power mode to main mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledLowPowerRunMode (void)
Check if the regulator is in low-power mode.
__STATIC_INLINE void | LL_PWR_EnterLowPowerRunMode (void)
Switch from run main mode to run low-power mode.
__STATIC_INLINE void | LL_PWR_ExitLowPowerRunMode (void)
Switch from run main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableFlashPowerDownInLPSleep (void)
Enable Flash Power-down mode during low power sleep mode.
__STATIC_INLINE void | LL_PWR_DisableFlashPowerDownInLPSleep (void)
Disable Flash Power-down mode during Low power sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnableFlashPowerDownInLPSleep (void)
Check if flash power-down mode during low power sleep mode domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableFlashPowerDownInLPRun (void)
Enable Flash Power-down mode during low power run mode.
__STATIC_INLINE void | LL_PWR_DisableFlashPowerDownInLPRun (void)
Disable Flash Power-down mode during Low power run mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnableFlashPowerDownInLPRun (void)
Check if flash power-down mode during low power run mode domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableFlashPowerDownInStop (void)
Enable Flash Power-down mode during stop mode.
__STATIC_INLINE void | LL_PWR_DisableFlashPowerDownInStop (void)
Disable Flash Power-down mode during stop mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnableFlashPowerDownInStop (void)
Check if flash power-down mode during stop mode domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableVddIO2 (void)
Enable VDDIO2 supply.
__STATIC_INLINE void | LL_PWR_DisableVddIO2 (void)
Disable VDDIO2 supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddIO2 (void)
Check if VDDIO2 supply is enabled.
__STATIC_INLINE void | LL_PWR_EnableVddUSB (void)
Enable VDDUSB supply.
__STATIC_INLINE void | LL_PWR_DisableVddUSB (void)
Disable VDDUSB supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddUSB (void)
Check if VDDUSB supply is enabled.
__STATIC_INLINE void | LL_PWR_EnablePVM (uint32_t PeriphVoltage)
Enable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE void | LL_PWR_DisablePVM (uint32_t PeriphVoltage)
Disable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVM (uint32_t PeriphVoltage)
Check if Power Voltage Monitoring is enabled on a peripheral.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Low-Power mode.
__STATIC_INLINE void | LL_PWR_SetPVDHighLevel (uint32_t PVDHighLevel)
Configure the high voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDHighLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_SetPVDLowLevel (uint32_t PVDLowLevel)
Configure the low voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLowLevel (void)
Get the low voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableInternWU (void)
Enable Internal Wake-up line.
__STATIC_INLINE void | LL_PWR_DisableInternWU (void)
Disable Internal Wake-up line.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled.
__STATIC_INLINE void | LL_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration.
__STATIC_INLINE void | LL_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRAMRetention (void)
Enable SRAM content retention in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableSRAMRetention (void)
Disable SRAM content retention in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRAMRetention (void)
Check if SRAM content retention in Standby mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableLPMUResetSamplingMode (void)
Enable sampling mode of LPMMU reset block.
__STATIC_INLINE void | LL_PWR_DisableLPMUResetSamplingMode (void)
Disable sampling mode of LPMMU reset block.
__STATIC_INLINE uint32_t | LL_PWR_IsEnableLPMUResetSamplingMode (void)
Check if sampling mode of LPMMU reset block.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-up state is enabled.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-down state is enabled.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableBatteryCharging ( void )

Disable battery charging.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_DisableBatteryCharging
Return values:
None

Definition at line 926 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_DisableBkUpAccess
Return values:
None

Definition at line 350 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPRun ( void )

Disable Flash Power-down mode during Low power run mode.

Reference Manual to LL API cross reference:
CR1 CFIPD_RUN LL_PWR_DisableFlashPowerDownInLPRun
Return values:
None

Definition at line 410 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPSleep ( void )

Disable Flash Power-down mode during Low power sleep mode.

Reference Manual to LL API cross reference:
CR1 CFIPD_SLP LL_PWR_DisableFlashPowerDownInLPSleep
Return values:
None

Definition at line 380 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop ( void )

Disable Flash Power-down mode during stop mode.

Reference Manual to LL API cross reference:
CR1 CFIPD_STOP LL_PWR_DisableFlashPowerDownInStop
Return values:
None

Definition at line 440 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-down state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_DisableGPIOPullDown
PDCRB PD0-15 LL_PWR_DisableGPIOPullDown
PDCRC PD0-15 LL_PWR_DisableGPIOPullDown
PDCRD PD0-15 LL_PWR_DisableGPIOPullDown
PDCRE PD0-15 LL_PWR_DisableGPIOPullDown
PDCRF PD0-13 LL_PWR_DisableGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E (*)
  • LL_PWR_GPIO_F
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1200 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-up state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_DisableGPIOPullUp
PUCRB PU0-15 LL_PWR_DisableGPIOPullUp
PUCRC PU0-15 LL_PWR_DisableGPIOPullUp
PUCRD PU0-15 LL_PWR_DisableGPIOPullUp
PUCRE PU0-15 LL_PWR_DisableGPIOPullUp
PUCRF PU0-13 LL_PWR_DisableGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E (*)
  • LL_PWR_GPIO_F
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1083 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableInternWU ( void )

Disable Internal Wake-up line.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_DisableInternWU
Return values:
None

Definition at line 708 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode ( void )

Switch the regulator from low-power mode to main mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_DisableLowPowerRunMode
Return values:
None

Definition at line 300 of file stm32g0xx_ll_pwr.h.

Referenced by LL_PWR_ExitLowPowerRunMode().

__STATIC_INLINE void LL_PWR_DisableLPMUResetSamplingMode ( void )

Disable sampling mode of LPMMU reset block.

Reference Manual to LL API cross reference:
CR3 ENB_ULP LL_PWR_DisableLPMUResetSamplingMode
Return values:
None

Definition at line 801 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePUPDCfg ( void )

Disable pull-up and pull-down configuration.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_DisablePUPDCfg
Return values:
None

Definition at line 738 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVD ( void )

Disable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_DisablePVD
Return values:
None

Definition at line 677 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVM ( uint32_t PeriphVoltage )

Disable the Power Voltage Monitoring on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVMUSB LL_PWR_DisablePVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_USB (*)
(*) value not defined in all devices
Return values:
None

Definition at line 541 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableSRAMRetention ( void )

Disable SRAM content retention in Standby mode.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_DisableSRAMRetention
Return values:
None

Definition at line 769 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableVddIO2 ( void )

Disable VDDIO2 supply.

Reference Manual to LL API cross reference:
CR2 IOSV LL_PWR_DisableVddIO2
Return values:
None

Definition at line 471 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableVddUSB ( void )

Disable VDDUSB supply.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_DisableVddUSB
Return values:
None

Definition at line 501 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_DisableWakeUpPin
CR3 EWUP2 LL_PWR_DisableWakeUpPin
CR3 EWUP3 LL_PWR_DisableWakeUpPin
CR3 EWUP4 LL_PWR_DisableWakeUpPin
CR3 EWUP5 LL_PWR_DisableWakeUpPin
CR3 EWUP6 LL_PWR_DisableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
  • LL_PWR_WAKEUP_PIN6
Return values:
None
Note:
(*) availability depends on devices

Definition at line 858 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBatteryCharging ( void )

Enable battery charging.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_EnableBatteryCharging
Return values:
None

Definition at line 916 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_EnableBkUpAccess
Return values:
None

Definition at line 340 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPRun ( void )

Enable Flash Power-down mode during low power run mode.

Reference Manual to LL API cross reference:
CR1 CFIPD_RUN LL_PWR_EnableFlashPowerDownInLPRun
Return values:
None

Definition at line 400 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPSleep ( void )

Enable Flash Power-down mode during low power sleep mode.

Reference Manual to LL API cross reference:
CR1 CFIPD_SLP LL_PWR_EnableFlashPowerDownInLPSleep
Return values:
None

Definition at line 370 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop ( void )

Enable Flash Power-down mode during stop mode.

Reference Manual to LL API cross reference:
CR1 CFIPD_STOP LL_PWR_EnableFlashPowerDownInStop
Return values:
None

Definition at line 430 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-down state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_EnableGPIOPullDown
PDCRB PD0-15 LL_PWR_EnableGPIOPullDown
PDCRC PD0-15 LL_PWR_EnableGPIOPullDown
PDCRD PD0-15 LL_PWR_EnableGPIOPullDown
PDCRE PD0-15 LL_PWR_EnableGPIOPullDown
PDCRF PD0-13 LL_PWR_EnableGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E (*)
  • LL_PWR_GPIO_F
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1161 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-up state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_EnableGPIOPullUp
PUCRB PU0-15 LL_PWR_EnableGPIOPullUp
PUCRC PU0-15 LL_PWR_EnableGPIOPullUp
PUCRD PU0-15 LL_PWR_EnableGPIOPullUp
PUCRE PU0-15 LL_PWR_EnableGPIOPullUp
PUCRF PU0-13 LL_PWR_EnableGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E (*)
  • LL_PWR_GPIO_F
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1044 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableInternWU ( void )

Enable Internal Wake-up line.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_EnableInternWU
Return values:
None

Definition at line 698 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode ( void )

Switch the regulator from main mode to low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_EnableLowPowerRunMode
Return values:
None

Definition at line 290 of file stm32g0xx_ll_pwr.h.

Referenced by LL_PWR_EnterLowPowerRunMode().

__STATIC_INLINE void LL_PWR_EnableLPMUResetSamplingMode ( void )

Enable sampling mode of LPMMU reset block.

Reference Manual to LL API cross reference:
CR3 ENB_ULP LL_PWR_EnableLPMUResetSamplingMode
Return values:
None

Definition at line 791 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePUPDCfg ( void )

Enable pull-up and pull-down configuration.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_EnablePUPDCfg
Return values:
None

Definition at line 728 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVD ( void )

Enable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_EnablePVD
Return values:
None

Definition at line 667 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVM ( uint32_t PeriphVoltage )

Enable the Power Voltage Monitoring on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVMUSB LL_PWR_EnablePVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_USB (*)
(*) value not defined in all devices
Return values:
None

Definition at line 527 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableSRAMRetention ( void )

Enable SRAM content retention in Standby mode.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_EnableSRAMRetention
Return values:
None

Definition at line 759 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableVddIO2 ( void )

Enable VDDIO2 supply.

Reference Manual to LL API cross reference:
CR2 IOSV LL_PWR_EnableVddIO2
Return values:
None

Definition at line 461 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableVddUSB ( void )

Enable VDDUSB supply.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_EnableVddUSB
Return values:
None

Definition at line 491 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableWakeUpPin ( uint32_t WakeUpPin )

Enable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_EnableWakeUpPin
CR3 EWUP2 LL_PWR_EnableWakeUpPin
CR3 EWUP3 LL_PWR_EnableWakeUpPin
CR3 EWUP4 LL_PWR_EnableWakeUpPin
CR3 EWUP5 LL_PWR_EnableWakeUpPin
CR3 EWUP6 LL_PWR_EnableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
  • LL_PWR_WAKEUP_PIN6
Return values:
None
Note:
(*) availability depends on devices

Definition at line 835 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode ( void )

Switch from run main mode to run low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_EnterLowPowerRunMode
Return values:
None

Definition at line 320 of file stm32g0xx_ll_pwr.h.

References LL_PWR_EnableLowPowerRunMode().

__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode ( void )

Switch from run main mode to low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_ExitLowPowerRunMode
Return values:
None

Definition at line 330 of file stm32g0xx_ll_pwr.h.

References LL_PWR_DisableLowPowerRunMode().

__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor ( void )

Get the resistor impedance.

Reference Manual to LL API cross reference:
CR4 VBRS LL_PWR_GetBattChargResistor
Return values:
Returned value can be one of the following values:
  • LL_PWR_BATTCHARG_RESISTOR_5K
  • LL_PWR_BATTCHARG_RESISTOR_1_5K

Definition at line 906 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPowerMode ( void )

Get Low-Power mode.

Reference Manual to LL API cross reference:
CR1 LPMS LL_PWR_GetPowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN

Definition at line 585 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPVDHighLevel ( void )

Get the voltage threshold detection.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_GetPVDHighLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_PVDHLEVEL_0
  • LL_PWR_PVDHLEVEL_1
  • LL_PWR_PVDHLEVEL_2
  • LL_PWR_PVDHLEVEL_3
  • LL_PWR_PVDHLEVEL_4
  • LL_PWR_PVDHLEVEL_5
  • LL_PWR_PVDHLEVEL_6
  • LL_PWR_PVDHLEVEL_7

Definition at line 623 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPVDLowLevel ( void )

Get the low voltage threshold detection.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_GetPVDLowLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_PVDLLEVEL_0
  • LL_PWR_PVDLLEVEL_1
  • LL_PWR_PVDLLEVEL_2
  • LL_PWR_PVDLLEVEL_3
  • LL_PWR_PVDLLEVEL_4
  • LL_PWR_PVDLLEVEL_5
  • LL_PWR_PVDLLEVEL_6

Definition at line 657 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling ( void )

Get the main internal regulator output voltage.

Reference Manual to LL API cross reference:
CR1 VOS LL_PWR_GetRegulVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2

Definition at line 280 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging ( void )

Check if battery charging is enabled.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_IsEnabledBatteryCharging
Return values:
State of bit (1 or 0).

Definition at line 936 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess ( void )

Check if the backup domain is enabled.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_IsEnabledBkUpAccess
Return values:
State of bit (1 or 0).

Definition at line 360 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Check if GPIO pull-down state is enabled.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRF PD0-13 LL_PWR_IsEnabledGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E (*)
  • LL_PWR_GPIO_F
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
State of bit (1 or 0).

Definition at line 1239 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Check if GPIO pull-up state is enabled.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRF PU0-13 LL_PWR_IsEnabledGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E (*)
  • LL_PWR_GPIO_F
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
State of bit (1 or 0).

Definition at line 1122 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU ( void )

Check if Internal Wake-up line is enabled.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_IsEnabledInternWU
Return values:
State of bit (1 or 0).

Definition at line 718 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode ( void )

Check if the regulator is in low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
Return values:
State of bit (1 or 0).

Definition at line 310 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg ( void )

Check if pull-up and pull-down configuration is enabled.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_IsEnabledPUPDCfg
Return values:
State of bit (1 or 0).

Definition at line 748 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD ( void )

Check if Power Voltage Detector is enabled.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_IsEnabledPVD
Return values:
State of bit (1 or 0).

Definition at line 687 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM ( uint32_t PeriphVoltage )

Check if Power Voltage Monitoring is enabled on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVMUSB LL_PWR_IsEnabledPVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_USB (*)
(*) value not defined in all devices
Return values:
State of bit (1 or 0).

Definition at line 555 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAMRetention ( void )

Check if SRAM content retention in Standby mode is enabled.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_IsEnabledSRAMRetention
Return values:
State of bit (1 or 0).

Definition at line 779 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2 ( void )

Check if VDDIO2 supply is enabled.

Reference Manual to LL API cross reference:
CR2 IOSV LL_PWR_IsEnabledVddIO2
Return values:
State of bit (1 or 0).

Definition at line 481 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB ( void )

Check if VDDUSB supply is enabled.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_IsEnabledVddUSB
Return values:
State of bit (1 or 0).

Definition at line 511 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin ( uint32_t WakeUpPin )

Check if the WakeUp PINx functionality is enabled.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP6 LL_PWR_IsEnabledWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
  • LL_PWR_WAKEUP_PIN6
Return values:
State of bit (1 or 0).
Note:
(*) availability depends on devices

Definition at line 881 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPRun ( void )

Check if flash power-down mode during low power run mode domain is enabled.

Reference Manual to LL API cross reference:
CR1 CFIPD_RUN LL_PWR_IsEnableFlashPowerDownInLPRun
Return values:
State of bit (1 or 0).

Definition at line 420 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPSleep ( void )

Check if flash power-down mode during low power sleep mode domain is enabled.

Reference Manual to LL API cross reference:
CR1 CFIPD_SLP LL_PWR_IsEnableFlashPowerDownInLPSleep
Return values:
State of bit (1 or 0).

Definition at line 390 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop ( void )

Check if flash power-down mode during stop mode domain is enabled.

Reference Manual to LL API cross reference:
CR1 CFIPD_STOP LL_PWR_IsEnableFlashPowerDownInStop
Return values:
State of bit (1 or 0).

Definition at line 450 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnableLPMUResetSamplingMode ( void )

Check if sampling mode of LPMMU reset block.

Reference Manual to LL API cross reference:
CR3 ENB_ULP LL_PWR_IsEnableLPMUResetSamplingMode
Return values:
State of bit (1 or 0).

Definition at line 811 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Get the Wake-Up pin polarity for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP6 LL_PWR_IsWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
  • LL_PWR_WAKEUP_PIN6
Note:
(*) availability depends on devices
Return values:
State of bit (1 or 0).

Definition at line 1005 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetBattChargResistor ( uint32_t Resistor )

Set the resistor impedance.

Reference Manual to LL API cross reference:
CR4 VBRS LL_PWR_SetBattChargResistor
Parameters:
Resistor This parameter can be one of the following values:
  • LL_PWR_BATTCHARG_RESISTOR_5K
  • LL_PWR_BATTCHARG_RESISTOR_1_5K
Return values:
None

Definition at line 894 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPowerMode ( uint32_t LowPowerMode )

Set Low-Power mode.

Reference Manual to LL API cross reference:
CR1 LPMS LL_PWR_SetPowerMode
Parameters:
LowPowerMode This parameter can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN
Return values:
None

Definition at line 571 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPVDHighLevel ( uint32_t PVDHighLevel )

Configure the high voltage threshold detected by the Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_SetPVDHighLevel
Parameters:
PVDHighLevel This parameter can be one of the following values:
  • LL_PWR_PVDHLEVEL_0
  • LL_PWR_PVDHLEVEL_1
  • LL_PWR_PVDHLEVEL_2
  • LL_PWR_PVDHLEVEL_3
  • LL_PWR_PVDHLEVEL_4
  • LL_PWR_PVDHLEVEL_5
  • LL_PWR_PVDHLEVEL_6
  • LL_PWR_PVDHLEVEL_7
Return values:
None

Definition at line 605 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPVDLowLevel ( uint32_t PVDLowLevel )

Configure the low voltage threshold detected by the Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_SetPVDLowLevel
Parameters:
PVDLowLevel This parameter can be one of the following values:
  • LL_PWR_PVDLLEVEL_0
  • LL_PWR_PVDLLEVEL_1
  • LL_PWR_PVDLLEVEL_2
  • LL_PWR_PVDLLEVEL_3
  • LL_PWR_PVDLLEVEL_4
  • LL_PWR_PVDLLEVEL_5
  • LL_PWR_PVDLLEVEL_6
Return values:
None

Definition at line 640 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling ( uint32_t VoltageScaling )

Set the main internal regulator output voltage.

Reference Manual to LL API cross reference:
CR1 VOS LL_PWR_SetRegulVoltageScaling
Parameters:
VoltageScaling This parameter can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2
Return values:
None

Definition at line 268 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity high for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP6 LL_PWR_SetWakeUpPinPolarityHigh
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
  • LL_PWR_WAKEUP_PIN6
Note:
(*) availability depends on devices
Return values:
None

Definition at line 982 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity low for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP6 LL_PWR_SetWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
  • LL_PWR_WAKEUP_PIN6
Return values:
None
Note:
(*) availability depends on devices

Definition at line 959 of file stm32g0xx_ll_pwr.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
PWR Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_InternWU (void)
Get Internal Wake-up line Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Stand-By Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU6 (void)
Get Wake-up Flag 6.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Stand-By Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU6 (void)
Clear Wake-up Flag 6.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMOUSB (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOS (void)
Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPF (void)
Indicate whether the regulator is ready in main mode or is in low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPS (void)
Indicate whether or not the low-power regulator is ready.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_FLASH_RDY (void)
Indicate whether or not the flash is ready to be accessed.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_SB ( void )

Clear Stand-By Flag.

Reference Manual to LL API cross reference:
SCR CSBF LL_PWR_ClearFlag_SB
Return values:
None

Definition at line 1341 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU ( void )

Clear Wake-up Flags.

Reference Manual to LL API cross reference:
SCR CWUF LL_PWR_ClearFlag_WU
Return values:
None

Definition at line 1351 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU1 ( void )

Clear Wake-up Flag 1.

Reference Manual to LL API cross reference:
SCR CWUF1 LL_PWR_ClearFlag_WU1
Return values:
None

Definition at line 1415 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU2 ( void )

Clear Wake-up Flag 2.

Reference Manual to LL API cross reference:
SCR CWUF2 LL_PWR_ClearFlag_WU2
Return values:
None

Definition at line 1405 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU3 ( void )

Clear Wake-up Flag 3.

Reference Manual to LL API cross reference:
SCR CWUF3 LL_PWR_ClearFlag_WU3
Return values:
None

Definition at line 1394 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU4 ( void )

Clear Wake-up Flag 4.

Reference Manual to LL API cross reference:
SCR CWUF4 LL_PWR_ClearFlag_WU4
Return values:
None

Definition at line 1383 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU5 ( void )

Clear Wake-up Flag 5.

Reference Manual to LL API cross reference:
SCR CWUF5 LL_PWR_ClearFlag_WU5
Return values:
None

Definition at line 1372 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU6 ( void )

Clear Wake-up Flag 6.

Reference Manual to LL API cross reference:
SCR CWUF6 LL_PWR_ClearFlag_WU6
Return values:
None

Definition at line 1361 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY ( void )

Indicate whether or not the flash is ready to be accessed.

Reference Manual to LL API cross reference:
SR2 FLASH_RDY LL_PWR_IsActiveFlag_FLASH_RDY
Return values:
State of bit (1 or 0).

Definition at line 1488 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU ( void )

Get Internal Wake-up line Flag.

Reference Manual to LL API cross reference:
SR1 WUFI LL_PWR_IsActiveFlag_InternWU
Return values:
State of bit (1 or 0).

Definition at line 1257 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO ( void )

Indicate whether VDD voltage is below or above the selected PVD threshold.

Reference Manual to LL API cross reference:
SR2 PVDO LL_PWR_IsActiveFlag_PVDO
Return values:
State of bit (1 or 0).

Definition at line 1440 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB ( void )

Indicate whether VDD voltage is below or above the selected PVD threshold.

Reference Manual to LL API cross reference:
SR2 PVDMO_USB LL_PWR_IsActiveFlag_PVMOUSB
Return values:
State of bit (1 or 0).

Definition at line 1427 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF ( void )

Indicate whether the regulator is ready in main mode or is in low-power mode.

Note:
: Take care, return value "0" means regulator is ready in main mode Return value "1" means regulator is in low-power mode (LPR)
Reference Manual to LL API cross reference:
SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
Return values:
State of bit (1 or 0).

Definition at line 1468 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS ( void )

Indicate whether or not the low-power regulator is ready.

Reference Manual to LL API cross reference:
SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
Return values:
State of bit (1 or 0).

Definition at line 1478 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB ( void )

Get Stand-By Flag.

Reference Manual to LL API cross reference:
SR1 SBF LL_PWR_IsActiveFlag_SB
Return values:
State of bit (1 or 0).

Definition at line 1267 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS ( void )

Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.

Note:
: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
Reference Manual to LL API cross reference:
SR2 VOSF LL_PWR_IsActiveFlag_VOS
Return values:
State of bit (1 or 0).

Definition at line 1455 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1 ( void )

Get Wake-up Flag 1.

Reference Manual to LL API cross reference:
SR1 WUF1 LL_PWR_IsActiveFlag_WU1
Return values:
State of bit (1 or 0).

Definition at line 1331 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2 ( void )

Get Wake-up Flag 2.

Reference Manual to LL API cross reference:
SR1 WUF2 LL_PWR_IsActiveFlag_WU2
Return values:
State of bit (1 or 0).

Definition at line 1321 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3 ( void )

Get Wake-up Flag 3.

Reference Manual to LL API cross reference:
SR1 WUF3 LL_PWR_IsActiveFlag_WU3
Return values:
State of bit (1 or 0).

Definition at line 1310 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4 ( void )

Get Wake-up Flag 4.

Reference Manual to LL API cross reference:
SR1 WUF4 LL_PWR_IsActiveFlag_WU4
Return values:
State of bit (1 or 0).

Definition at line 1299 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5 ( void )

Get Wake-up Flag 5.

Reference Manual to LL API cross reference:
SR1 WUF5 LL_PWR_IsActiveFlag_WU5
Return values:
State of bit (1 or 0).

Definition at line 1288 of file stm32g0xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6 ( void )

Get Wake-up Flag 6.

Reference Manual to LL API cross reference:
SR1 WUF6 LL_PWR_IsActiveFlag_WU6
Return values:
State of bit (1 or 0).

Definition at line 1277 of file stm32g0xx_ll_pwr.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: De-initialization function

Functions
De-initialization function
PWR Exported Functions

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Function Documentation

ErrorStatus LL_PWR_DeInit ( void )

De-initialize the PWR registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PWR registers are de-initialized
  • ERROR: not applicable

Definition at line 55 of file stm32g0xx_ll_pwr.c.

References LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_PWR, and LL_APB1_GRP1_ReleaseReset().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Private functions

Functions
RCC Private functions
RCC

Functions

static uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
static uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
static uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
static uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.
static uint32_t | RCC_PLL_GetFreqDomain_ADC (void)
Return PLL clock frequency used for ADC domain.
static uint32_t | RCC_PLL_GetFreqDomain_I2S1 (void)
Return PLL clock frequency used for I2S1 domain.
static uint32_t | RCC_PLL_GetFreqDomain_I2S2 (void)
Return PLL clock frequency used for I2S2 domain.
static uint32_t | RCC_PLL_GetFreqDomain_USB (void)
Return PLL clock frequency used for USB domain.
static uint32_t | RCC_PLL_GetFreqDomain_FDCAN (void)
Return PLL clock frequency used for FDCAN domain.
static uint32_t | RCC_PLL_GetFreqDomain_RNG (void)
Return PLL clock frequency used for RNG domain.
static uint32_t | RCC_PLL_GetFreqDomain_TIM1 (void)
Return PLL clock frequency used for TIM1 domain.
static uint32_t | RCC_PLL_GetFreqDomain_TIM15 (void)
Return PLL clock frequency used for TIM15 domain.

Function Documentation

static uint32_t RCC_GetHCLKClockFreq ( uint32_t SYSCLK_Frequency ) [static]

Return HCLK clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK clock frequency (in Hz)

Definition at line 1069 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_HCLK_FREQ, and LL_RCC_GetAHBPrescaler().

Referenced by LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetTIMClockFreq(), and LL_RCC_GetUSARTClockFreq().

static uint32_t RCC_GetPCLK1ClockFreq ( uint32_t HCLK_Frequency ) [static]

Return PCLK1 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1080 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK1_FREQ, and LL_RCC_GetAPB1Prescaler().

Referenced by LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetTIMClockFreq(), and LL_RCC_GetUSARTClockFreq().

static uint32_t RCC_GetSystemClockFreq ( void ) [static]

Return SYSTEM clock frequency.

Return values:
SYSTEM clock frequency (in Hz)

Definition at line 1038 of file stm32g0xx_ll_rcc.c.

References HSE_VALUE, HSI_VALUE, LL_RCC_GetSysClkSource(), LL_RCC_SYS_CLKSOURCE_STATUS_HSE, LL_RCC_SYS_CLKSOURCE_STATUS_HSI, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, and RCC_PLL_GetFreqDomain_SYS().

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetTIMClockFreq(), and LL_RCC_GetUSARTClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_ADC ( void ) [static]

Return PLL clock frequency used for ADC domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1120 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_ADC_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetADCClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_FDCAN ( void ) [static]

Return PLL clock frequency used for FDCAN domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1150 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_FDCAN_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetFDCANClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_I2S1 ( void ) [static]

Return PLL clock frequency used for I2S1 domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1181 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_I2S1_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetI2SClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_I2S2 ( void ) [static]

Return PLL clock frequency used for I2S2 domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1211 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_I2S2_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetI2SClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_RNG ( void ) [static]

Return PLL clock frequency used for RNG domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1242 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_RNG_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetRNGClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_SYS ( void ) [static]

Return PLL clock frequency used for system domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1089 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by RCC_GetSystemClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_TIM1 ( void ) [static]

Return PLL clock frequency used for TIM1 domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1306 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_TIM1_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetTIMClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_TIM15 ( void ) [static]

Return PLL clock frequency used for TIM15 domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1338 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_TIM15_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetTIMClockFreq().

static uint32_t RCC_PLL_GetFreqDomain_USB ( void ) [static]

Return PLL clock frequency used for USB domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1274 of file stm32g0xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_USB_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Private Variables

RCC Private Variables
RCC
Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
#define | IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
#define | IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)

Define Documentation

#define IS_LL_RCC_ADC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Definition at line 77 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq().

#define IS_LL_RCC_CEC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))

Definition at line 87 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetCECClockFreq().

#define IS_LL_RCC_FDCAN_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))

Definition at line 95 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetFDCANClockFreq().

#define IS_LL_RCC_I2C_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))

Definition at line 62 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetI2CClockFreq().

#define IS_LL_RCC_I2S_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
                                             || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))

Definition at line 80 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetI2SClockFreq().

#define IS_LL_RCC_LPTIM_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
                                               || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))

Definition at line 69 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define IS_LL_RCC_LPUART_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) \
                                                || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE))

Definition at line 55 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define IS_LL_RCC_RNG_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))

Definition at line 74 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetRNGClockFreq().

#define IS_LL_RCC_TIM_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
                                               || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE))

Definition at line 99 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetTIMClockFreq().

#define IS_LL_RCC_USART_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
                                               || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
                                               || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))

Definition at line 44 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetUSARTClockFreq().

#define IS_LL_RCC_USB_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))

Definition at line 91 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_RCC_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RCC_ClocksTypeDef Struct Reference
Clocks Frequency Structure

RCC Clocks Frequency Structure. More...

#include <stm32g0xx_ll_rcc.h>

Data Fields

uint32_t | SYSCLK_Frequency
uint32_t | HCLK_Frequency
uint32_t | PCLK1_Frequency

Detailed Description

RCC Clocks Frequency Structure.

Definition at line 74 of file stm32g0xx_ll_rcc.h.

Field Documentation

uint32_t LL_RCC_ClocksTypeDef::HCLK_Frequency

HCLK clock frequency

Definition at line 77 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK1_Frequency

PCLK1 clock frequency

Definition at line 78 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq(), and LL_USART_Init().

uint32_t LL_RCC_ClocksTypeDef::SYSCLK_Frequency

SYSCLK clock frequency

Definition at line 76 of file stm32g0xx_ll_rcc.h.

Referenced by LL_I2S_Init(), LL_LPTIM_Disable(), and LL_RCC_GetSystemClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_rcc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Oscillator Values adaptation

Oscillator Values adaptation
RCC Exported Constants

Defines used to adapt values of different oscillators. More...

Defines used to adapt values of different oscillators.

Note:
These values could be modified in the user environment according to HW set-up.
Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_WriteReg function. More...

Defines

#define | LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
#define | LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define | LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define | LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define | LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define | LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define | LL_RCC_CICR_CSSC RCC_CICR_CSSC
#define | LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC

Detailed Description

Flags defines which can be used with LL_RCC_WriteReg function.

Define Documentation

#define LL_RCC_CICR_CSSC RCC_CICR_CSSC

Clock Security System Interrupt Clear

Definition at line 139 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC

HSE Ready Interrupt Clear

Definition at line 136 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC

HSI48 Ready Interrupt Clear

Definition at line 141 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC

HSI Ready Interrupt Clear

Definition at line 135 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC

LSE Clock Security System Interrupt Clear

Definition at line 138 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC

LSE Ready Interrupt Clear

Definition at line 134 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC

LSI Ready Interrupt Clear

Definition at line 133 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC

PLL Ready Interrupt Clear

Definition at line 137 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_ReadReg function. More...

Defines

#define | LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
#define | LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define | LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define | LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF
#define | LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define | LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define | LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define | LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF

Detailed Description

Flags defines which can be used with LL_RCC_ReadReg function.

Define Documentation

#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF

Clock Security System Interrupt flag

Definition at line 160 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF

HSE Ready Interrupt flag

Definition at line 157 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF

HSI48 Ready Interrupt flag

Definition at line 155 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF

HSI Ready Interrupt flag

Definition at line 153 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF

LSE Clock Security System Interrupt flag

Definition at line 159 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF

LSE Ready Interrupt flag

Definition at line 152 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF

LSI Ready Interrupt flag

Definition at line 151 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 158 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF

Independent Watchdog reset flag

Definition at line 165 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF

Low-Power reset flag

Definition at line 161 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF

OBL reset flag

Definition at line 162 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF

PIN reset flag

Definition at line 163 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF

BOR or POR/PDR reset flag

Definition at line 167 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF

Software Reset flag

Definition at line 164 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF

Window watchdog reset flag

Definition at line 166 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
RCC Exported Constants

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions. More...

Defines

#define | LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
#define | LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define | LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define | LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define | LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define | LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE

Detailed Description

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

Define Documentation

#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE

HSE Ready Interrupt Enable

Definition at line 179 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE

HSI48 Ready Interrupt Enable

Definition at line 182 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE

HSI Ready Interrupt Enable

Definition at line 178 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE

LSE Ready Interrupt Enable

Definition at line 177 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE

LSI Ready Interrupt Enable

Definition at line 176 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE

PLL Ready Interrupt Enable

Definition at line 180 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LSE oscillator drive capability

Defines
LSE oscillator drive capability
RCC Exported Constants

Defines

#define | LL_RCC_LSEDRIVE_LOW 0x00000000U
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Xtal mode higher driving capability

Definition at line 194 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_LOW 0x00000000U

Xtal mode lower driving capability

Definition at line 191 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

Xtal mode medium high driving capability

Definition at line 193 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

Xtal mode medium low driving capability

Definition at line 192 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LSCO Selection

Defines
LSCO Selection
RCC Exported Constants

Defines

#define | LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U
#define | LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

Define Documentation

#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

LSE selection for low speed clock

Definition at line 203 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U

LSI selection for low speed clock

Definition at line 202 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: System clock switch

Defines
System clock switch
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1
#define | LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)
#define | LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0

HSE selection as system clock

Definition at line 212 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U

HSI selection as system clock

Definition at line 211 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2

LSE selection used as system clock

Definition at line 215 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)

LSI selection used as system clock

Definition at line 214 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1

PLL selection as system clock

Definition at line 213 of file stm32g0xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: System clock switch status

Defines
System clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1
#define | LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)
#define | LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0

HSE used as system clock

Definition at line 224 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U

HSI used as system clock

Definition at line 223 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2

LSE used as system clock

Definition at line 227 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)

LSI used as system clock

Definition at line 226 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1

PLL used as system clock

Definition at line 225 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: AHB prescaler

Defines
AHB prescaler
RCC Exported Constants

Defines

#define | LL_RCC_SYSCLK_DIV_1 0x00000000U
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3
#define | LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)
#define | LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

Define Documentation

#define LL_RCC_SYSCLK_DIV_1 0x00000000U

SYSCLK not divided

Definition at line 235 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)

SYSCLK divided by 128

Definition at line 241 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

SYSCLK divided by 16

Definition at line 239 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3

SYSCLK divided by 2

Definition at line 236 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)

SYSCLK divided by 256

Definition at line 242 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)

SYSCLK divided by 4

Definition at line 237 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

SYSCLK divided by 512

Definition at line 243 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)

SYSCLK divided by 64

Definition at line 240 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)

SYSCLK divided by 8

Definition at line 238 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: APB low-speed prescaler (APB1)

Defines
APB low-speed prescaler (APB1)
RCC Exported Constants

Defines

#define | LL_RCC_APB1_DIV_1 0x00000000U
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2
#define | LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)
#define | LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)
#define | LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)

Define Documentation

#define LL_RCC_APB1_DIV_1 0x00000000U

HCLK not divided

Definition at line 251 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)

HCLK divided by 16

Definition at line 255 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2

HCLK divided by 2

Definition at line 252 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)

HCLK divided by 4

Definition at line 253 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)

HCLK divided by 8

Definition at line 254 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HSI division factor

Defines
HSI division factor
RCC Exported Constants

Defines

#define | LL_RCC_HSI_DIV_1 0x00000000U
#define | LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0
#define | LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1
#define | LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
#define | LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2
#define | LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0)
#define | LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1)
#define | LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV

Define Documentation

#define LL_RCC_HSI_DIV_1 0x00000000U

HSI not divided

Definition at line 263 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV

HSI divided by 128

Definition at line 270 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2

HSI divided by 16

Definition at line 267 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0

HSI divided by 2

Definition at line 264 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0)

HSI divided by 32

Definition at line 268 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1

HSI divided by 4

Definition at line 265 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1)

HSI divided by 64

Definition at line 269 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)

HSI divided by 8

Definition at line 266 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO1 SOURCE selection

Defines
MCO1 SOURCE selection
RCC Exported Constants

Defines

#define | LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1
#define | LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3
#define | LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)
#define | LL_RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0)

Define Documentation

#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2

HSE selection as MCO1 source

Definition at line 284 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)

HSI16 selection as MCO1 source

Definition at line 283 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1

HSI48 selection as MCO1 source

Definition at line 281 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSE selection as MCO1 source

Definition at line 287 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSI selection as MCO1 source

Definition at line 286 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U

MCO output disabled, no clock on MCO

Definition at line 278 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)

Main PLL selection as MCO1 source

Definition at line 285 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3

PLLPCLK selection as MCO1 source

Definition at line 289 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)

PLLQCLK selection as MCO1 source

Definition at line 290 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0)

RTC_Wakeup selection as MCO1 source

Definition at line 292 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)

RTCCLK selection as MCO1 source

Definition at line 291 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0

SYSCLK selection as MCO1 source

Definition at line 279 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO1 prescaler

Defines
MCO1 prescaler
RCC Exported Constants

Defines

#define | LL_RCC_MCO1_DIV_1 0x00000000U
#define | LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0
#define | LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1
#define | LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2
#define | LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)
#define | LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3
#define | LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)

Define Documentation

#define LL_RCC_MCO1_DIV_1 0x00000000U

MCO1 not divided

Definition at line 301 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)

MCO divided by 1024

Definition at line 312 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)

MCO1 divided by 128

Definition at line 308 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2

MCO1 divided by 16

Definition at line 305 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0

MCO1 divided by 2

Definition at line 302 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3

MCO divided by 256

Definition at line 310 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)

MCO1 divided by 32

Definition at line 306 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1

MCO1 divided by 4

Definition at line 303 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)

MCO divided by 512

Definition at line 311 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)

MCO1 divided by 64

Definition at line 307 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)

MCO1 divided by 8

Definition at line 304 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO2 SOURCE selection

Defines
MCO2 SOURCE selection
RCC Exported Constants

Defines

#define | LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U
#define | LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0
#define | LL_RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1
#define | LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2
#define | LL_RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1)
#define | LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3
#define | LL_RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1)
#define | LL_RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)

Define Documentation

#define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2

HSE selection as MCO2 source

Definition at line 328 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)

HSI16 selection as MCO2 source

Definition at line 327 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1

HSI48 selection as MCO2 source

Definition at line 325 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)

LSE selection as MCO2 source

Definition at line 331 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1)

LSI selection as MCO2 source

Definition at line 330 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U

MCO output disabled, no clock on MCO

Definition at line 322 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0)

Main PLL "R" clock selection as MCO2 source

Definition at line 329 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3

PLL "P" clock selection as MCO2 source

Definition at line 332 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0)

PLL "Q" clock selection as MCO2 source

Definition at line 333 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)

RTC Wakeup timer selection as MCO2 source

Definition at line 335 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1)

RTC Clock selection as MCO2 source

Definition at line 334 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0

SYSCLK selection as MCO2 source

Definition at line 323 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO2 prescaler

Defines
MCO2 prescaler
RCC Exported Constants

Defines

#define | LL_RCC_MCO2_DIV_1 0x00000000U
#define | LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0
#define | LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1
#define | LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2
#define | LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)
#define | LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3
#define | LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)

Define Documentation

#define LL_RCC_MCO2_DIV_1 0x00000000U

MCO2 not divided

Definition at line 343 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)

MCO2 divided by 1024

Definition at line 353 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)

MCO2 divided by 128

Definition at line 350 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2

MCO2 divided by 16

Definition at line 347 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0

MCO2 divided by 2

Definition at line 344 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3

MCO2 divided by 256

Definition at line 351 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)

MCO2 divided by 32

Definition at line 348 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1

MCO2 divided by 4

Definition at line 345 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)

MCO2 divided by 512

Definition at line 352 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)

MCO2 divided by 64

Definition at line 349 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)

MCO2 divided by 8

Definition at line 346 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral clock frequency

Defines
Peripheral clock frequency
RCC Exported Constants

Defines

#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Define Documentation

#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Frequency cannot be provided as external clock

Definition at line 364 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetRTCClockFreq(), and LL_RCC_GetUSBClockFreq().

#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U

No clock enabled for the peripheral

Definition at line 363 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPUART_Init(), LL_RCC_GetADCClockFreq(), LL_RCC_GetCECClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetRTCClockFreq(), LL_RCC_GetTIMClockFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_GetUSBClockFreq(), and LL_USART_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral USART clock source selection

Defines
Peripheral USART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U)
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)
#define | LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)
#define | LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)
#define | LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U)
#define | LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)
#define | LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)
#define | LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)
#define | LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U)
#define | LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0)
#define | LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1)
#define | LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)

Define Documentation

#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)

HSI clock used as USART1 clock source

Definition at line 375 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)

LSE clock used as USART1 clock source

Definition at line 376 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U)

PCLK1 clock used as USART1 clock source

Definition at line 373 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)

SYSCLK clock used as USART1 clock source

Definition at line 374 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)

HSI clock used as USART2 clock source

Definition at line 379 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)

LSE clock used as USART2 clock source

Definition at line 380 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U)

PCLK1 clock used as USART2 clock source

Definition at line 377 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)

SYSCLK clock used as USART2 clock source

Definition at line 378 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1)

HSI clock used as USART3 clock source

Definition at line 384 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)

LSE clock used as USART3 clock source

Definition at line 385 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U)

PCLK1 clock used as USART3 clock source

Definition at line 382 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0)

SYSCLK clock used as USART3 clock source

Definition at line 383 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral LPUART clock source selection

Defines
Peripheral LPUART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U)
#define | LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0)
#define | LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1)
#define | LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL)
#define | LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U)
#define | LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0)
#define | LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1)
#define | LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL)

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1)

HSI clock used as LPUART1 clock source

Definition at line 403 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL)

LSE clock used as LPUART1 clock source

Definition at line 404 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U)

PCLK1 clock used as LPUART1 clock source

Definition at line 401 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0)

SYSCLK clock used as LPUART1 clock source

Definition at line 402 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1)

HSI clock used as LPUART2 clock source

Definition at line 398 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL)

LSE clock used as LPUART2 clock source

Definition at line 399 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U)

PCLK1 clock used as LPUART2 clock source

Definition at line 396 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0)

SYSCLK clock used as LPUART2 clock source

Definition at line 397 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral I2C clock source selection

Defines
Peripheral I2C clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U)
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0)
#define | LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1)
#define | LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U)
#define | LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0)
#define | LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1)

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1)

HSI clock used as I2C1 clock source

Definition at line 415 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U)

PCLK1 clock used as I2C1 clock source

Definition at line 413 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0)

SYSCLK clock used as I2C1 clock source

Definition at line 414 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1)

HSI clock used as I2C2 clock source

Definition at line 419 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U)

PCLK1 clock used as I2C2 clock source

Definition at line 417 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0)

SYSCLK clock used as I2C2 clock source

Definition at line 418 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral I2S clock source selection

Defines
Peripheral I2S clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_I2S1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U)
#define | LL_RCC_I2S1_CLKSOURCE_PLL ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0)
#define | LL_RCC_I2S1_CLKSOURCE_HSI ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1)
#define | LL_RCC_I2S1_CLKSOURCE_PIN ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL)
#define | LL_RCC_I2S2_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U)
#define | LL_RCC_I2S2_CLKSOURCE_PLL ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0)
#define | LL_RCC_I2S2_CLKSOURCE_HSI ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1)
#define | LL_RCC_I2S2_CLKSOURCE_PIN ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL)

Define Documentation

#define LL_RCC_I2S1_CLKSOURCE_HSI ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1)

HSI clock used as I2S1 clock source

Definition at line 431 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S1_CLKSOURCE_PIN ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL)

External clock used as I2S1 clock source

Definition at line 432 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S1_CLKSOURCE_PLL ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0)

PLL clock used as I2S1 clock source

Definition at line 430 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U)

SYSCLK clock used as I2S1 clock source

Definition at line 429 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S2_CLKSOURCE_HSI ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1)

HSI clock used as I2S2 clock source

Definition at line 435 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S2_CLKSOURCE_PIN ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL)

External clock used as I2S2 clock source

Definition at line 436 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S2_CLKSOURCE_PLL ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0)

PLL clock used as I2S2 clock source

Definition at line 434 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S2_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U)

SYSCLK clock used as I2S2 clock source

Definition at line 433 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral TIM clock source selection

Defines
Peripheral TIM clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U))
#define | LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U))
#define | LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U))
#define | LL_RCC_TIM15_CLKSOURCE_PLL (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U))

Define Documentation

#define LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U))

PCLK1 clock used as TIM15 clock source

Definition at line 463 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

#define LL_RCC_TIM15_CLKSOURCE_PLL (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U))

PLL used as TIM15 clock source

Definition at line 464 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

#define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U))

PCLK1 clock used as TIM1 clock source

Definition at line 452 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

#define LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U))

PLL used as TIM1 clock source

Definition at line 453 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral LPTIM clock source selection

Defines
Peripheral LPTIM clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U))
#define | LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U))
#define | LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U))
#define | LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U))

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U))

HSI selected as LPTIM1 clock

Definition at line 476 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U))

LSE selected as LPTIM1 clock

Definition at line 477 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U))

LSI selected as LPTIM1 clock

Definition at line 475 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U))

PCLK1 selected as LPTIM1 clock

Definition at line 474 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U))

HSI selected as LPTIM2 clock

Definition at line 480 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U))

LSE selected as LPTIM2 clock

Definition at line 481 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U))

LSI selected as LPTIM2 clock

Definition at line 479 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U))

PCLK1 selected as LPTIM2 clock

Definition at line 478 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral CEC clock source selection

Defines
Peripheral CEC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U
#define | LL_RCC_CEC_CLKSOURCE_LSE RCC_CCIPR_CECSEL

Define Documentation

#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U

HSI oscillator clock divided by 488 used as CEC clock

Definition at line 491 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CCIPR_CECSEL

LSE oscillator clock used as CEC clock

Definition at line 492 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral FDCAN clock source selection

Defines
Peripheral FDCAN clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_FDCAN_CLKSOURCE_PCLK1 0x00000000U
#define | LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0
#define | LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1

Define Documentation

#define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1

HSE oscillator clock used as FDCAN clock

Definition at line 505 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0x00000000U

PCLK1 oscillator clock used as FDCAN clock

Definition at line 503 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

#define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0

PLL "Q" oscillator clock used as FDCAN clock

Definition at line 504 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral RNG clock source selection

Defines
Peripheral RNG clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RNG_CLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0
#define | LL_RCC_RNG_CLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1
#define | LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_RNGSEL

Define Documentation

#define LL_RCC_RNG_CLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0

HSI oscillator clock divided by 8 used as RNG clock, available on cut2.0

Definition at line 517 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U

No clock used as RNG clock

Definition at line 516 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_RNGSEL

PLL used as RNG clock

Definition at line 519 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1

SYSCLK divided by 1 used as RNG clock

Definition at line 518 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral RNG clock division factor

Defines
Peripheral RNG clock division factor
RCC Exported Constants

Defines

#define | LL_RCC_RNG_CLK_DIV1 0x00000000U
#define | LL_RCC_RNG_CLK_DIV2 RCC_CCIPR_RNGDIV_0
#define | LL_RCC_RNG_CLK_DIV4 RCC_CCIPR_RNGDIV_1
#define | LL_RCC_RNG_CLK_DIV8 RCC_CCIPR_RNGDIV

Define Documentation

#define LL_RCC_RNG_CLK_DIV1 0x00000000U

RNG clock not divided

Definition at line 529 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_RNG_CLK_DIV2 RCC_CCIPR_RNGDIV_0

RNG clock divided by 2

Definition at line 530 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_RNG_CLK_DIV4 RCC_CCIPR_RNGDIV_1

RNG clock divided by 4

Definition at line 531 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_RNG_CLK_DIV8 RCC_CCIPR_RNGDIV

RNG clock divided by 8

Definition at line 532 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: Peripheral USB clock source selection

Defines
Peripheral USB clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U
#define | LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL_0
#define | LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR2_USBSEL_1

Define Documentation

#define LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL_0

PLL clock used as USB clock source

Definition at line 545 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U

HSI48 clock used as USB clock source

Definition at line 543 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR2_USBSEL_1

PLL clock used as USB clock source

Definition at line 546 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral ADC clock source selection

Defines
Peripheral ADC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U
#define | LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_0
#define | LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1

Define Documentation

#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1

HSI used as ADC clock

Definition at line 557 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_0

PLL used as ADC clock

Definition at line 556 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U

SYSCLK used as ADC clock

Definition at line 555 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral USARTx get clock source

Defines
Peripheral USARTx get clock source
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
#define | LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
#define | LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL

Define Documentation

#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL

USART1 Clock source selection

Definition at line 565 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL

USART2 Clock source selection

Definition at line 566 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL

USART3 Clock source selection

Definition at line 568 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

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STM32G0C1xx HAL User Manual: Peripheral LPUART get clock source

Defines
Peripheral LPUART get clock source
RCC Exported Constants

Defines

#define | LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL
#define | LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL

LPUART1 Clock source selection

Definition at line 578 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPUART_Init(), and LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL

LPUART2 Clock source selection

Definition at line 580 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPUART_Init(), and LL_RCC_GetLPUARTClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral I2C get clock source

Defines
Peripheral I2C get clock source
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL
#define | LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL

I2C1 Clock source selection

Definition at line 590 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL

I2C2 Clock source selection

Definition at line 592 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral I2S get clock source

Defines
Peripheral I2S get clock source
RCC Exported Constants

Defines

#define | LL_RCC_I2S1_CLKSOURCE RCC_CCIPR2_I2S1SEL
#define | LL_RCC_I2S2_CLKSOURCE RCC_CCIPR2_I2S2SEL

Define Documentation

#define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR2_I2S1SEL

I2S1 Clock source selection

Definition at line 602 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

#define LL_RCC_I2S2_CLKSOURCE RCC_CCIPR2_I2S2SEL

I2S2 Clock source selection

Definition at line 603 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral TIMx get clock source

Defines
Peripheral TIMx get clock source
RCC Exported Constants

Defines

#define | LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL
#define | LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL

Define Documentation

#define LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL

TIM15 Clock source selection

Definition at line 617 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

#define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL

TIM1 Clock source selection

Definition at line 615 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

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STM32G0C1xx HAL User Manual: Peripheral LPTIM get clock source

Defines
Peripheral LPTIM get clock source
RCC Exported Constants

Defines

#define | LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
#define | LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL

LPTIM2 Clock source selection

Definition at line 628 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL

LPTIM2 Clock source selection

Definition at line 629 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

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STM32G0C1xx HAL User Manual: Peripheral CEC get clock source

Defines
Peripheral CEC get clock source
RCC Exported Constants

Defines

#define LL_RCC_CEC_CLKSOURCE RCC_CCIPR_CECSEL

Define Documentation

#define LL_RCC_CEC_CLKSOURCE RCC_CCIPR_CECSEL

CEC Clock source selection

Definition at line 639 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: Peripheral FDCAN get clock source

Defines
Peripheral FDCAN get clock source
RCC Exported Constants

Defines

#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL

Define Documentation

#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL

FDCAN Clock source selection

Definition at line 649 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: Peripheral USB get clock source

Defines
Peripheral USB get clock source
RCC Exported Constants

Defines

#define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL

Define Documentation

#define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL

USB Clock source selection

Definition at line 659 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: Peripheral RNG get clock source

Defines
Peripheral RNG get clock source
RCC Exported Constants

Defines

#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL

Define Documentation

#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL

RNG Clock source selection

Definition at line 669 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: Peripheral RNG get clock division factor

Defines
Peripheral RNG get clock division factor
RCC Exported Constants

Defines

#define LL_RCC_RNG_CLKDIV RCC_CCIPR_RNGDIV

Define Documentation

#define LL_RCC_RNG_CLKDIV RCC_CCIPR_RNGDIV

RNG Clock division factor

Definition at line 677 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: Peripheral ADC get clock source

Defines
Peripheral ADC get clock source
RCC Exported Constants

Defines

#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL

Define Documentation

#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL

ADC Clock source selection

Definition at line 686 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: RTC clock source selection

Defines
RTC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

Define Documentation

#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 697 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRTCClockFreq().

#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 695 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRTCClockFreq().

#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 696 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRTCClockFreq().

#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U

No clock used as RTC clock

Definition at line 694 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRTCClockFreq().

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STM32G0C1xx HAL User Manual: PLL entry clock source

Defines
PLL entry clock source
RCC Exported Constants

Defines

#define | LL_RCC_PLLSOURCE_NONE 0x00000000U
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Define Documentation

#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

HSE clock selected as PLL entry clock source

Definition at line 708 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_FDCAN(), RCC_PLL_GetFreqDomain_I2S1(), RCC_PLL_GetFreqDomain_I2S2(), RCC_PLL_GetFreqDomain_RNG(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLL_GetFreqDomain_TIM1(), RCC_PLL_GetFreqDomain_TIM15(), and RCC_PLL_GetFreqDomain_USB().

#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

HSI16 clock selected as PLL entry clock source

Definition at line 707 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_FDCAN(), RCC_PLL_GetFreqDomain_I2S1(), RCC_PLL_GetFreqDomain_I2S2(), RCC_PLL_GetFreqDomain_RNG(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLL_GetFreqDomain_TIM1(), RCC_PLL_GetFreqDomain_TIM15(), and RCC_PLL_GetFreqDomain_USB().

#define LL_RCC_PLLSOURCE_NONE 0x00000000U

No clock

Definition at line 706 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: PLL division factor (PLLM)

Defines
PLL division factor (PLLM)
RCC Exported Constants

Defines

#define | LL_RCC_PLLM_DIV_1 0x00000000U
#define | LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
#define | LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)

Define Documentation

#define LL_RCC_PLLM_DIV_1 0x00000000U

PLL division factor by 1

Definition at line 716 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)

PLL division factor by 2

Definition at line 717 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)

PLL division factor by 3

Definition at line 718 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))

PLL division factor by 4

Definition at line 719 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)

PLL division factor by 5

Definition at line 720 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))

PLL division factor by 6

Definition at line 721 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))

PLL division factor by 7

Definition at line 722 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)

PLL division factor by 8

Definition at line 723 of file stm32g0xx_ll_rcc.h.

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STM32G0C1xx HAL User Manual: PLL division factor (PLLR)

Defines
PLL division factor (PLLR)
RCC Exported Constants

Defines

#define | LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2)
#define | LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)

Define Documentation

#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 2

Definition at line 731 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1)

Main PLL division factor for PLLCLK (system clock) by 3

Definition at line 732 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 4

Definition at line 733 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2)

Main PLL division factor for PLLCLK (system clock) by 5

Definition at line 734 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 6

Definition at line 735 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)

Main PLL division factor for PLLCLK (system clock) by 7

Definition at line 736 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)

Main PLL division factor for PLLCLK (system clock) by 8

Definition at line 737 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLL division factor (PLLP)

Defines
PLL division factor (PLLP)
RCC Exported Constants

Defines

#define | LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0)
#define | LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1)
#define | LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)
#define | LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Define Documentation

#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 10

Definition at line 753 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 11

Definition at line 754 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 12

Definition at line 755 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 13

Definition at line 756 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 14

Definition at line 757 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 15

Definition at line 758 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 16

Definition at line 759 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 17

Definition at line 760 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 18

Definition at line 761 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 19

Definition at line 762 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0)

Main PLL division factor for PLLP output by 2

Definition at line 745 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 20

Definition at line 763 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 21

Definition at line 764 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 22

Definition at line 765 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 23

Definition at line 766 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 24

Definition at line 767 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 25

Definition at line 768 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 26

Definition at line 769 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 27

Definition at line 770 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 28

Definition at line 771 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 29

Definition at line 772 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1)

Main PLL division factor for PLLP output by 3

Definition at line 746 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 30

Definition at line 773 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 31

Definition at line 774 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 32

Definition at line 775 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)

Main PLL division factor for PLLP output by 4

Definition at line 747 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2)

Main PLL division factor for PLLP output by 5

Definition at line 748 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)

Main PLL division factor for PLLP output by 6

Definition at line 749 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)

Main PLL division factor for PLLP output by 7

Definition at line 750 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)

Main PLL division factor for PLLP output by 8

Definition at line 751 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 9

Definition at line 752 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLL division factor (PLLQ)

Defines
PLL division factor (PLLQ)
RCC Exported Constants

Defines

#define | LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2)
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)

Define Documentation

#define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0)

Main PLL division factor for PLLQ output by 2

Definition at line 784 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1)

Main PLL division factor for PLLQ output by 3

Definition at line 785 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)

Main PLL division factor for PLLQ output by 4

Definition at line 786 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2)

Main PLL division factor for PLLQ output by 5

Definition at line 787 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)

Main PLL division factor for PLLQ output by 6

Definition at line 788 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)

Main PLL division factor for PLLQ output by 7

Definition at line 789 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)

Main PLL division factor for PLLQ output by 8

Definition at line 790 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RCC Exported Macros

Defines

#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.

Define Documentation

#define LL_RCC_ReadReg ( __REG__ ) READ_REG(RCC->__REG__)

Read a value in RCC register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 822 of file stm32g0xx_ll_rcc.h.

#define LL_RCC_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((RCC->__REG__), (__VALUE__))

Write a value in RCC register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 815 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Calculate frequencies

Defines
Calculate frequencies
RCC Exported Macros

Defines

#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
Helper macro to calculate the PLLCLK frequency on system domain.
#define | __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on I2S domain.
#define | __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on I2S2 domain.
#define | __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on ADC domain.
#define | __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on RNG domain.
#define | __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on TIM1 domain.
#define | __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on TIM15 domain.
#define | __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on FDCAN domain.
#define | __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on USB domain.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU))
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))
Helper macro to calculate the HSISYS frequency.

Define Documentation

#define __LL_RCC_CALC_HCLK_FREQ | ( | __SYSCLKFREQ__,
 |  | __AHBPRESCALER__
 | ) | ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))

Helper macro to calculate the HCLK frequency.

Parameters:
__SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
__AHBPRESCALER__ This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
HCLK clock frequency (in Hz)

Definition at line 1190 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_HSI_FREQ ( __HSIDIV__ ) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))

Helper macro to calculate the HSISYS frequency.

Parameters:
__HSIDIV__ This parameter can be one of the following values:
  • LL_RCC_HSI_DIV_1
  • LL_RCC_HSI_DIV_2
  • LL_RCC_HSI_DIV_4
  • LL_RCC_HSI_DIV_8
  • LL_RCC_HSI_DIV_16
  • LL_RCC_HSI_DIV_32
  • LL_RCC_HSI_DIV_64
  • LL_RCC_HSI_DIV_128
Return values:
HSISYS clock frequency (in Hz)

Definition at line 1220 of file stm32g0xx_ll_rcc.h.

#define __LL_RCC_CALC_PCLK1_FREQ | ( | __HCLKFREQ__,
 |  | __APB1PRESCALER__
 | ) | ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU))

Helper macro to calculate the PCLK1 frequency (ABP1)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB1PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1204 of file stm32g0xx_ll_rcc.h.

Referenced by HAL_RCC_GetPCLK1Freq(), and RCC_GetPCLK1ClockFreq().

#define __LL_RCC_CALC_PLLCLK_ADC_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
   (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))

Helper macro to calculate the PLLPCLK frequency used on ADC domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLP__ This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
PLL clock frequency (in Hz)

Definition at line 1017 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_ADC().

#define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLQ__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /     \
   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))

Helper macro to calculate the PLLQCLK frequency used on FDCAN domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_FDCAN_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLQ__ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 1139 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_FDCAN().

#define __LL_RCC_CALC_PLLCLK_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLR__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
   (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))

Helper macro to calculate the PLLCLK frequency on system domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetR ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLR__ This parameter can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_3
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_5
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_7
  • LL_RCC_PLLR_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 856 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

#define __LL_RCC_CALC_PLLCLK_I2S1_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__
 | ) |
Value:
((__INPUTFREQ__)  * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
   (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))

Helper macro to calculate the PLLPCLK frequency used on I2S domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_I2S1_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLP__ This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
PLL clock frequency (in Hz)

Definition at line 909 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_I2S1().

#define __LL_RCC_CALC_PLLCLK_I2S2_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__
 | ) |
Value:
((__INPUTFREQ__)  * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
   (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))

Helper macro to calculate the PLLPCLK frequency used on I2S2 domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLP__ This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
PLL clock frequency (in Hz)

Definition at line 963 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_I2S2().

#define __LL_RCC_CALC_PLLCLK_RNG_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLQ__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /     \
   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))

Helper macro to calculate the PLLQCLK frequency used on RNG domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLQ__ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 1047 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_RNG().

#define __LL_RCC_CALC_PLLCLK_TIM15_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLQ__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /      \
   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))

Helper macro to calculate the PLLQCLK frequency used on TIM15 domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_TIM15_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLQ__ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 1107 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_TIM15().

#define __LL_RCC_CALC_PLLCLK_TIM1_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLQ__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))

Helper macro to calculate the PLLQCLK frequency used on TIM1 domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_TIM1_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLQ__ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 1078 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_TIM1().

#define __LL_RCC_CALC_PLLCLK_USB_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLQ__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /   \
   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))

Helper macro to calculate the PLLQCLK frequency used on USB domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_USB_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 8 and Max_Data = 86
__PLLQ__ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 1170 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_USB().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HSE

Functions
HSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_HSE_Disable ( void )

Disable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Disable
Return values:
None

Definition at line 1284 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_DisableBypass ( void )

Disable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_DisableBypass
Return values:
None

Definition at line 1264 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_Enable ( void )

Enable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Enable
Return values:
None

Definition at line 1274 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableBypass ( void )

Enable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_EnableBypass
Return values:
None

Definition at line 1254 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableCSS ( void )

Enable the Clock Security System.

Reference Manual to LL API cross reference:
CR CSSON LL_RCC_HSE_EnableCSS
Return values:
None

Definition at line 1244 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady ( void )

Check if HSE oscillator Ready.

Reference Manual to LL API cross reference:
CR HSERDY LL_RCC_HSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1294 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_RCC_DeInit(), LL_RCC_GetFDCANClockFreq(), and LL_RCC_GetUSBClockFreq().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HSI

Functions
HSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI_EnableInStopMode (void)
Enable HSI even in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableInStopMode (void)
Disable HSI in stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsEnabledInStopMode (void)
Check if HSI in stop mode is enabled.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI_Disable ( void )

Disable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Disable
Return values:
None

Definition at line 1353 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode ( void )

Disable HSI in stop mode.

Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_DisableInStopMode
Return values:
None

Definition at line 1323 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_Enable ( void )

Enable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Enable
Return values:
None

Definition at line 1343 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), and LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode ( void )

Enable HSI even in stop mode.

Note:
HSI oscillator is forced ON even in Stop mode
Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_EnableInStopMode
Return values:
None

Definition at line 1313 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration ( void )

Get HSI Calibration value.

Note:
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value
Reference Manual to LL API cross reference:
ICSCR HSICAL LL_RCC_HSI_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 1375 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming ( void )

Get HSI Calibration trimming.

Reference Manual to LL API cross reference:
ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
Return values:
Between Min_Data = 0 and Max_Data = 127

Definition at line 1399 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode ( void )

Check if HSI in stop mode is enabled.

Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
Return values:
State of bit (1 or 0).

Definition at line 1333 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady ( void )

Check if HSI clock is ready.

Reference Manual to LL API cross reference:
CR HSIRDY LL_RCC_HSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1363 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), LL_RCC_DeInit(), LL_RCC_GetCECClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming ( uint32_t Value )

Set HSI Calibration trimming.

Note:
user-programmable trimming value that is added to the HSICAL
Default value is 64, which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 %
Reference Manual to LL API cross reference:
ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
Parameters:
Value Between Min_Data = 0 and Max_Data = 127
Return values:
None

Definition at line 1389 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HSI48

Functions
HSI48
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI48_Enable (void)
Enable HSI48.
__STATIC_INLINE void | LL_RCC_HSI48_Disable (void)
Disable HSI48.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void)
Check if HSI48 oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void)
Get HSI48 Calibration value.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI48_Disable ( void )

Disable HSI48.

Reference Manual to LL API cross reference:
CR HSI48ON LL_RCC_HSI48_Disable
Return values:
None

Definition at line 1428 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI48_Enable ( void )

Enable HSI48.

Reference Manual to LL API cross reference:
CR HSI48ON LL_RCC_HSI48_Enable
Return values:
None

Definition at line 1418 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration ( void )

Get HSI48 Calibration value.

Reference Manual to LL API cross reference:
CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0x1FF

Definition at line 1448 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady ( void )

Check if HSI48 oscillator Ready.

Reference Manual to LL API cross reference:
CR HSI48RDY LL_RCC_HSI48_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1438 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LSE

Functions
LSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable Clock security system on LSE.
__STATIC_INLINE void | LL_RCC_LSE_DisableCSS (void)
Disable Clock security system on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsCSSDetected (void)
Check if CSS on LSE failure Detection.

Function Documentation

__STATIC_INLINE void LL_RCC_LSE_Disable ( void )

Disable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Disable
Return values:
None

Definition at line 1477 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableBypass ( void )

Disable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_DisableBypass
Return values:
None

Definition at line 1497 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableCSS ( void )

Disable Clock security system on LSE.

Note:
Clock security system can be disabled only after a LSE failure detection. In that case it MUST be disabled by software.
Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_DisableCSS
Return values:
None

Definition at line 1549 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_Enable ( void )

Enable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Enable
Return values:
None

Definition at line 1467 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableBypass ( void )

Enable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_EnableBypass
Return values:
None

Definition at line 1487 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableCSS ( void )

Enable Clock security system on LSE.

Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_EnableCSS
Return values:
None

Definition at line 1537 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability ( void )

Get LSE oscillator drive capability.

Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH

Definition at line 1527 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected ( void )

Check if CSS on LSE failure Detection.

Reference Manual to LL API cross reference:
BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
Return values:
State of bit (1 or 0).

Definition at line 1569 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady ( void )

Check if LSE oscillator Ready.

Reference Manual to LL API cross reference:
BDCR LSERDY LL_RCC_LSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1559 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRTCClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability ( uint32_t LSEDrive )

Set LSE oscillator drive capability.

Note:
The oscillator is in Xtal mode when it is not in bypass mode.
Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
Parameters:
LSEDrive This parameter can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH
Return values:
None

Definition at line 1513 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LSI

Functions
LSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSI_Disable ( void )

Disable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Disable
Return values:
None

Definition at line 1597 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSI_Enable ( void )

Enable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Enable
Return values:
None

Definition at line 1587 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady ( void )

Check if LSI is Ready.

Reference Manual to LL API cross reference:
CSR LSIRDY LL_RCC_LSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1607 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq(), and LL_RCC_GetRTCClockFreq().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LSCO

Functions
LSCO
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSCO_Enable (void)
Enable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_Disable (void)
Disable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_SetSource (uint32_t Source)
Configure Low speed clock selection.
__STATIC_INLINE uint32_t | LL_RCC_LSCO_GetSource (void)
Get Low speed clock selection.

Function Documentation

__STATIC_INLINE void LL_RCC_LSCO_Disable ( void )

Disable Low speed clock.

Reference Manual to LL API cross reference:
BDCR LSCOEN LL_RCC_LSCO_Disable
Return values:
None

Definition at line 1635 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSCO_Enable ( void )

Enable Low speed clock.

Reference Manual to LL API cross reference:
BDCR LSCOEN LL_RCC_LSCO_Enable
Return values:
None

Definition at line 1625 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource ( void )

Get Low speed clock selection.

Reference Manual to LL API cross reference:
BDCR LSCOSEL LL_RCC_LSCO_GetSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSCO_CLKSOURCE_LSI
  • LL_RCC_LSCO_CLKSOURCE_LSE

Definition at line 1660 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSCO_SetSource ( uint32_t Source )

Configure Low speed clock selection.

Reference Manual to LL API cross reference:
BDCR LSCOSEL LL_RCC_LSCO_SetSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_LSCO_CLKSOURCE_LSI
  • LL_RCC_LSCO_CLKSOURCE_LSE
Return values:
None

Definition at line 1648 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: System

Functions
System
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetHSIDiv (uint32_t HSIDiv)
Set HSI16 division factor.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetHSIDiv (void)
Get HSI16 Division factor.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler ( void )

Get AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_GetAHBPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 1774 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler ( void )

Get APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE LL_RCC_GetAPB1Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16

Definition at line 1789 of file stm32g0xx_ll_rcc.h.

Referenced by HAL_RCC_GetPCLK1Freq(), and RCC_GetPCLK1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetHSIDiv ( void )

Get HSI16 Division factor.

Reference Manual to LL API cross reference:
CR HSIDIV LL_RCC_GetHSIDiv
Note:
HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as system clock source.
Return values:
Returned value can be one of the following values:
  • LL_RCC_HSI_DIV_1
  • LL_RCC_HSI_DIV_2
  • LL_RCC_HSI_DIV_4
  • LL_RCC_HSI_DIV_8
  • LL_RCC_HSI_DIV_16
  • LL_RCC_HSI_DIV_32
  • LL_RCC_HSI_DIV_64
  • LL_RCC_HSI_DIV_128

Definition at line 1809 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource ( void )

Get the system clock source.

Reference Manual to LL API cross reference:
CFGR SWS LL_RCC_GetSysClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL
  • LL_RCC_SYS_CLKSOURCE_STATUS_LSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_LSE

Definition at line 1699 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAHBPrescaler ( uint32_t Prescaler )

Set AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_SetAHBPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 1719 of file stm32g0xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB1Prescaler ( uint32_t Prescaler )

Set APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE LL_RCC_SetAPB1Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
None

Definition at line 1735 of file stm32g0xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetHSIDiv ( uint32_t HSIDiv )

Set HSI16 division factor.

Reference Manual to LL API cross reference:
CR HSIDIV LL_RCC_SetHSIDiv
Note:
HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as system clock source.
Parameters:
HSIDiv This parameter can be one of the following values:
  • LL_RCC_HSI_DIV_1
  • LL_RCC_HSI_DIV_2
  • LL_RCC_HSI_DIV_4
  • LL_RCC_HSI_DIV_8
  • LL_RCC_HSI_DIV_16
  • LL_RCC_HSI_DIV_32
  • LL_RCC_HSI_DIV_64
  • LL_RCC_HSI_DIV_128
Return values:
None

Definition at line 1756 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSysClkSource ( uint32_t Source )

Configure the system clock source.

Reference Manual to LL API cross reference:
CFGR SW LL_RCC_SetSysClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_HSI
  • LL_RCC_SYS_CLKSOURCE_HSE
  • LL_RCC_SYS_CLKSOURCE_PLL
  • LL_RCC_SYS_CLKSOURCE_LSI
  • LL_RCC_SYS_CLKSOURCE_LSE
Return values:
None

Definition at line 1684 of file stm32g0xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO1

Functions
MCO1
RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigMCO | ( | uint32_t | MCOxSource,
 |  | uint32_t | MCOxPrescaler
 | ) |  |

Configure MCOx.

Reference Manual to LL API cross reference:
CFGR MCOSEL LL_RCC_ConfigMCO
CFGR MCOPRE LL_RCC_ConfigMCO
Parameters:
MCOxSource This parameter can be one of the following values:
  • LL_RCC_MCO1SOURCE_NOCLOCK
  • LL_RCC_MCO1SOURCE_SYSCLK
  • LL_RCC_MCO1SOURCE_HSI
  • LL_RCC_MCO1SOURCE_HSI48 (*)
  • LL_RCC_MCO1SOURCE_HSE
  • LL_RCC_MCO1SOURCE_PLLCLK
  • LL_RCC_MCO1SOURCE_LSI
  • LL_RCC_MCO1SOURCE_LSE
  • LL_RCC_MCO1SOURCE_PLLPCLK (*)
  • LL_RCC_MCO1SOURCE_PLLQCLK (*)
  • LL_RCC_MCO1SOURCE_RTCCLK (*)
  • LL_RCC_MCO1SOURCE_RTC_WKUP (*)
(*) value not defined in all devices.
MCOxPrescaler This parameter can be one of the following values:
  • LL_RCC_MCO1_DIV_1
  • LL_RCC_MCO1_DIV_2
  • LL_RCC_MCO1_DIV_4
  • LL_RCC_MCO1_DIV_8
  • LL_RCC_MCO1_DIV_32
  • LL_RCC_MCO1_DIV_64
  • LL_RCC_MCO1_DIV_128
Return values:
None

Definition at line 1850 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MCO2

Functions
MCO2
RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_ConfigMCO2 (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCO2.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigMCO2 | ( | uint32_t | MCOxSource,
 |  | uint32_t | MCOxPrescaler
 | ) |  |

Configure MCO2.

Reference Manual to LL API cross reference:
CFGR MCO2SEL LL_RCC_ConfigMCO2
CFGR MCO2PRE LL_RCC_ConfigMCO2
Note:
feature not available in all devices.
Parameters:
MCOxSource This parameter can be one of the following values:
  • LL_RCC_MCO2SOURCE_NOCLOCK
  • LL_RCC_MCO2SOURCE_SYSCLK
  • LL_RCC_MCO2SOURCE_HSI
  • LL_RCC_MCO2SOURCE_HSI48
  • LL_RCC_MCO2SOURCE_HSE
  • LL_RCC_MCO2SOURCE_PLLCLK
  • LL_RCC_MCO2SOURCE_LSI
  • LL_RCC_MCO2SOURCE_LSE
  • LL_RCC_MCO2SOURCE_PLLPCLK
  • LL_RCC_MCO2SOURCE_PLLQCLK
  • LL_RCC_MCO2SOURCE_RTCCLK
  • LL_RCC_MCO2SOURCE_RTC_WKUP
MCOxPrescaler This parameter can be one of the following values:
  • LL_RCC_MCO2_DIV_1
  • LL_RCC_MCO2_DIV_2
  • LL_RCC_MCO2_DIV_4
  • LL_RCC_MCO2_DIV_8
  • LL_RCC_MCO2_DIV_16
  • LL_RCC_MCO2_DIV_32
  • LL_RCC_MCO2_DIV_64
  • LL_RCC_MCO2_DIV_128
  • LL_RCC_MCO2_DIV_256
  • LL_RCC_MCO2_DIV_512
  • LL_RCC_MCO2_DIV_1024
Return values:
None

Definition at line 1897 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Peripheral Clock Source

Functions
Peripheral Clock Source
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
Configure LPUARTx clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetTIMClockSource (uint32_t TIMxSource)
Configure TIMx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetCECClockSource (uint32_t CECxSource)
Configure CEC clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockDiv (uint32_t RNGxDiv)
Configure RNG division factor.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetFDCANClockSource (uint32_t FDCANxSource)
Configure FDCAN clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE void | LL_RCC_SetI2SClockSource (uint32_t I2SxSource)
Configure I2Sx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
Get LPUARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetTIMClockSource (uint32_t TIMx)
Get TIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
Get LPTIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCECClockSource (uint32_t CECx)
Get CEC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetFDCANClockSource (uint32_t FDCANx)
Get FDCAN clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t RNGx)
Get RNGx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockDiv (void)
Get RNGx clock division factor.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2SClockSource (uint32_t I2Sx)
Get I2Sx clock source.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource ( uint32_t ADCx )

Get ADCx clock source.

Reference Manual to LL API cross reference:
CCIPR ADCSEL LL_RCC_GetADCClockSource
Parameters:
ADCx This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE_HSI
  • LL_RCC_ADC_CLKSOURCE_PLL
  • LL_RCC_ADC_CLKSOURCE_SYSCLK

Definition at line 2360 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource ( uint32_t CECx )

Get CEC clock source.

Reference Manual to LL API cross reference:
CCIPR CECSEL LL_RCC_GetCECClockSource
Parameters:
CECx This parameter can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE_HSI_DIV488
  • LL_RCC_CEC_CLKSOURCE_LSE

Definition at line 2278 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetCECClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource ( uint32_t FDCANx )

Get FDCAN clock source.

Reference Manual to LL API cross reference:
CCIPR2 FDCANSEL LL_RCC_GetFDCANClockSource
Parameters:
FDCANx This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE_PCLK1
  • LL_RCC_FDCAN_CLKSOURCE_HSE

Definition at line 2294 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource ( uint32_t I2Cx )

Get I2Cx clock source.

Reference Manual to LL API cross reference:
CCIPR I2C1SEL LL_RCC_GetI2CClockSource
CCIPR I2C2SEL LL_RCC_GetI2CClockSource
Parameters:
I2Cx This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C2_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_PCLK1
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C2_CLKSOURCE_PCLK1
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK
  • LL_RCC_I2C2_CLKSOURCE_HSI

Definition at line 2218 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource ( uint32_t I2Sx )

Get I2Sx clock source.

Reference Manual to LL API cross reference:
CCIPR2 I2S1SEL LL_RCC_GetI2SClockSource
CCIPR2 I2S2SEL LL_RCC_GetI2SClockSource
Parameters:
I2Sx This parameter can be one of the following values:
  • LL_RCC_I2S1_CLKSOURCE
  • LL_RCC_I2S2_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_I2S1_CLKSOURCE_PIN
  • LL_RCC_I2S1_CLKSOURCE_SYSCLK
  • LL_RCC_I2S1_CLKSOURCE_HSI
  • LL_RCC_I2S1_CLKSOURCE_PLL
  • LL_RCC_I2S2_CLKSOURCE_PIN
  • LL_RCC_I2S2_CLKSOURCE_SYSCLK
  • LL_RCC_I2S2_CLKSOURCE_HSI
  • LL_RCC_I2S2_CLKSOURCE_PLL

Definition at line 2383 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource ( uint32_t LPTIMx )

Get LPTIMx clock source.

Reference Manual to LL API cross reference:
CCIPR LPTIM1SEL LL_RCC_GetLPTIMClockSource
CCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource
Parameters:
LPTIMx This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_HSI
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_HSI
  • LL_RCC_LPTIM2_CLKSOURCE_LSE

Definition at line 2262 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource ( uint32_t LPUARTx )

Get LPUARTx clock source.

Reference Manual to LL API cross reference:
CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
CCIPR LPUART2SEL LL_RCC_GetLPUARTClockSource
Parameters:
LPUARTx This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
  • LL_RCC_LPUART2_CLKSOURCE (*)
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE
  • LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
  • LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_LPUART2_CLKSOURCE_HSI (*)
  • LL_RCC_LPUART2_CLKSOURCE_LSE (*) (*) feature not available on all devices

Definition at line 2197 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetRNGClockDiv ( void )

Get RNGx clock division factor.

Reference Manual to LL API cross reference:
CCIPR RNGDIV LL_RCC_GetRNGClockDiv
Return values:
Returned value can be one of the following values:
  • LL_RCC_RNG_CLK_DIV1
  • LL_RCC_RNG_CLK_DIV2
  • LL_RCC_RNG_CLK_DIV4
  • LL_RCC_RNG_CLK_DIV8

Definition at line 2328 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource ( uint32_t RNGx )

Get RNGx clock source.

Reference Manual to LL API cross reference:
CCIPR RNGSEL LL_RCC_GetRNGClockSource
Parameters:
RNGx This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_NONE
  • LL_RCC_RNG_CLKSOURCE_HSI_DIV8
  • LL_RCC_RNG_CLKSOURCE_SYSCLK
  • LL_RCC_RNG_CLKSOURCE_PLL

Definition at line 2312 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource ( uint32_t TIMx )

Get TIMx clock source.

Reference Manual to LL API cross reference:
CCIPR TIMxSEL LL_RCC_GetTIMClockSource
Parameters:
TIMx This parameter can be one of the following values:
  • LL_RCC_TIM1_CLKSOURCE
  • LL_RCC_TIM15_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_TIM1_CLKSOURCE_PLL
  • LL_RCC_TIM1_CLKSOURCE_PCLK1

Definition at line 2238 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource ( uint32_t USARTx )

Get USARTx clock source.

Reference Manual to LL API cross reference:
CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
Parameters:
USARTx This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
  • LL_RCC_USART2_CLKSOURCE
  • LL_RCC_USART3_CLKSOURCE (*)
Return values:
Returned value can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK1
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART1_CLKSOURCE_LSE
  • LL_RCC_USART2_CLKSOURCE_PCLK1
  • LL_RCC_USART2_CLKSOURCE_SYSCLK
  • LL_RCC_USART2_CLKSOURCE_HSI
  • LL_RCC_USART2_CLKSOURCE_LSE
  • LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
  • LL_RCC_USART3_CLKSOURCE_HSI (*)
  • LL_RCC_USART3_CLKSOURCE_LSE (*) (*) feature not available on all devices

Definition at line 2173 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource ( uint32_t USBx )

Get USBx clock source.

Reference Manual to LL API cross reference:
CCIPR2 CK48MSEL LL_RCC_GetUSBClockSource
Parameters:
USBx This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_HSI48
  • LL_RCC_USB_CLKSOURCE_PLL

Definition at line 2344 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

__STATIC_INLINE void LL_RCC_SetADCClockSource ( uint32_t ADCxSource )

Configure ADC clock source.

Reference Manual to LL API cross reference:
CCIPR ADCSEL LL_RCC_SetADCClockSource
Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE_PLL
  • LL_RCC_ADC_CLKSOURCE_SYSCLK
  • LL_RCC_ADC_CLKSOURCE_HSI
Return values:
None

Definition at line 2109 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetCECClockSource ( uint32_t CECxSource )

Configure CEC clock source.

Reference Manual to LL API cross reference:
CCIPR CECSEL LL_RCC_SetCECClockSource
Parameters:
CECxSource This parameter can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE_HSI_DIV488
  • LL_RCC_CEC_CLKSOURCE_LSE
Return values:
None

Definition at line 2026 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetFDCANClockSource ( uint32_t FDCANxSource )

Configure FDCAN clock source.

Reference Manual to LL API cross reference:
CCIPR2 FDCANSEL LL_RCC_SetFDCANClockSource
Parameters:
FDCANxSource This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE_HSE
  • LL_RCC_FDCAN_CLKSOURCE_PCLK1
  • LL_RCC_FDCAN_CLKSOURCE_PLL
Return values:
None

Definition at line 2094 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetI2CClockSource ( uint32_t I2CxSource )

Configure I2Cx clock source.

Reference Manual to LL API cross reference:
CCIPR I2C1SEL LL_RCC_SetI2CClockSource
Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_PCLK1
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_I2C2_CLKSOURCE_HSI (*) (*) value not defined in all devices.
Return values:
None

Definition at line 1972 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetI2SClockSource ( uint32_t I2SxSource )

Configure I2Sx clock source.

Reference Manual to LL API cross reference:
CCIPR2 I2SxSEL LL_RCC_SetI2SClockSource
Parameters:
I2SxSource This parameter can be one of the following values:
  • LL_RCC_I2S1_CLKSOURCE_SYSCLK
  • LL_RCC_I2S1_CLKSOURCE_PIN
  • LL_RCC_I2S1_CLKSOURCE_PLL
  • LL_RCC_I2S1_CLKSOURCE_HSI
  • LL_RCC_I2S2_CLKSOURCE_SYSCLK
  • LL_RCC_I2S2_CLKSOURCE_PIN
  • LL_RCC_I2S2_CLKSOURCE_PLL
  • LL_RCC_I2S2_CLKSOURCE_HSI
Return values:
None

Definition at line 2129 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetLPTIMClockSource ( uint32_t LPTIMxSource )

Configure LPTIMx clock source.

Reference Manual to LL API cross reference:
CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_HSI
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_HSI
  • LL_RCC_LPTIM2_CLKSOURCE_LSE
Return values:
None

Definition at line 2011 of file stm32g0xx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_RCC_SetLPUARTClockSource ( uint32_t LPUARTxSource )

Configure LPUARTx clock source.

Reference Manual to LL API cross reference:
CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
Reference Manual to LL API cross reference:
CCIPR LPUART2SEL LL_RCC_SetLPUARTClockSource
Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE
  • LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
  • LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_LPUART2_CLKSOURCE_HSI (*)
  • LL_RCC_LPUART2_CLKSOURCE_LSE (*) (*) feature not available on all devices
Return values:
None

Definition at line 1953 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRNGClockDiv ( uint32_t RNGxDiv )

Configure RNG division factor.

Reference Manual to LL API cross reference:
CCIPR RNGDIV LL_RCC_SetRNGClockDiv
Parameters:
RNGxDiv This parameter can be one of the following values:
  • LL_RCC_RNG_CLK_DIV1
  • LL_RCC_RNG_CLK_DIV2
  • LL_RCC_RNG_CLK_DIV4
  • LL_RCC_RNG_CLK_DIV8
Return values:
None

Definition at line 2043 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRNGClockSource ( uint32_t RNGxSource )

Configure RNG clock source.

Reference Manual to LL API cross reference:
CCIPR RNGSEL LL_RCC_SetRNGClockSource
Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_NONE
  • LL_RCC_RNG_CLKSOURCE_HSI_DIV8
  • LL_RCC_RNG_CLKSOURCE_SYSCLK
  • LL_RCC_RNG_CLKSOURCE_PLL
Return values:
None

Definition at line 2060 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetTIMClockSource ( uint32_t TIMxSource )

Configure TIMx clock source.

Reference Manual to LL API cross reference:
CCIPR TIMxSEL LL_RCC_SetTIMClockSource
Parameters:
TIMxSource This parameter can be one of the following values:
  • LL_RCC_TIM1_CLKSOURCE_PLL
  • LL_RCC_TIM1_CLKSOURCE_PCLK1
Return values:
None

Definition at line 1990 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSARTClockSource ( uint32_t USARTxSource )

Configure USARTx clock source.

Reference Manual to LL API cross reference:
CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK1
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART1_CLKSOURCE_LSE
  • LL_RCC_USART2_CLKSOURCE_PCLK1
  • LL_RCC_USART2_CLKSOURCE_SYSCLK
  • LL_RCC_USART2_CLKSOURCE_HSI
  • LL_RCC_USART2_CLKSOURCE_LSE
  • LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
  • LL_RCC_USART3_CLKSOURCE_HSI (*)
  • LL_RCC_USART3_CLKSOURCE_LSE (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1931 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSBClockSource ( uint32_t USBxSource )

Configure USB clock source.

Reference Manual to LL API cross reference:
CCIPR2 CK48MSEL LL_RCC_SetUSBClockSource
Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_HSI48
  • LL_RCC_USB_CLKSOURCE_HSE
  • LL_RCC_USB_CLKSOURCE_PLL
(*) value not defined in all devices.
Return values:
None

Definition at line 2078 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC

Functions
RTC
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableRTC ( void )

Disable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_DisableRTC
Return values:
None

Definition at line 2459 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableRTC ( void )

Enable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_EnableRTC
Return values:
None

Definition at line 2449 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ForceBackupDomainReset ( void )

Force the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ForceBackupDomainReset
Return values:
None

Definition at line 2479 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource ( void )

Get RTC Clock Source.

Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_GetRTCClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32

Definition at line 2439 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRTCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC ( void )

Check if RTC has been enabled or not.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_IsEnabledRTC
Return values:
State of bit (1 or 0).

Definition at line 2469 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset ( void )

Release the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ReleaseBackupDomainReset
Return values:
None

Definition at line 2489 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRTCClockSource ( uint32_t Source )

Set RTC Clock Source.

Note:
Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_SetRTCClockSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Return values:
None

Definition at line 2425 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PLL

Functions
PLL
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_I2S1 (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for I2S1 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_I2S2 (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for I2S2 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_RNG (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for RNG domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_FDCAN (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for FDCAN domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_USB (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for USB domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_TIM1 (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for TIM1 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_TIM15 (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for TIM15 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void)
Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void)
Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void)
Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void)
Get Main PLL division factor for PLLR.
__STATIC_INLINE void | LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
Configure PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void)
Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_ADC (void)
Enable PLL output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_ADC (void)
Disable PLL output mapped on ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_ADC (void)
Check if PLL output mapped on ADC domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_I2S1 (void)
Enable PLL output mapped on I2S domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_I2S2 (void)
Enable PLL output mapped on I2S2 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_I2S1 (void)
Disable PLL output mapped on I2S1 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_I2S1 (void)
Check if PLL output mapped on I2S1 domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_I2S2 (void)
Disable PLL output mapped on I2S2 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_I2S2 (void)
Check if PLL output mapped on I2S2 domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_RNG (void)
Enable PLL output mapped on RNG domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_RNG (void)
Disable PLL output mapped on RNG domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_RNG (void)
Check if PLL output mapped on RNG domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_FDCAN (void)
Enable PLL output mapped on FDCAN domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_FDCAN (void)
Disable PLL output mapped on FDCAN domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_FDCAN (void)
Check if PLL output mapped on FDCAN domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_USB (void)
Enable PLL output mapped on USB domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_USB (void)
Disable PLL output mapped on USB domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_USB (void)
Check if PLL output mapped on USB domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_TIM1 (void)
Enable PLL output mapped on TIM1 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_TIM1 (void)
Disable PLL output mapped on TIM1 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_TIM1 (void)
Check if PLL output mapped on TIM1 domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_TIM15 (void)
Enable PLL output mapped on TIM15 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_TIM15 (void)
Disable PLL output mapped on TIM15 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_TIM15 (void)
Check if PLL output mapped on TIM15 domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void)
Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void)
Disable PLL output mapped on SYSCLK domain.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_SYS (void)
Check if PLL output mapped on SYSCLK domain clock is enabled.

Function Documentation

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLL used for ADC domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLP can be written only when PLL is disabled
User shall verify whether the PLL configuration is not done through other functions (ex: I2S1)
This can be selected for ADC
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
None

Definition at line 2631 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_FDCAN | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLL used for FDCAN domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLQ can be written only when PLL is disabled
User shall verify whether the PLL configuration is not done through other functions (ex: TIM1, TIM15)
This can be selected for FDCAN
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_FDCAN
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_FDCAN
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_FDCAN
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_FDCAN
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
None

Definition at line 2848 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S1 | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLL used for I2S1 domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLP can be written only when PLL is disabled
User shall verify whether the PLL configuration is not done through other functions (ex: ADC)
This can be selected for I2S1
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S1
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S1
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S1
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S1
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
None

Definition at line 2696 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S2 | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLL used for I2S2 domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLP can be written only when PLL is disabled
User shall verify whether the PLL configuration is not done through other functions (ex: ADC)
This can be selected for I2S2
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S2
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S2
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S2
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S2
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
None

Definition at line 2762 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLL used for RNG domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLQ can be written only when PLL is disabled
User shall verify whether the PLL configuration is not done through other functions (ex: TIM1, TIM15)
This can be selected for RNG
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_RNG
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_RNG
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_RNG
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_RNG
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
None

Definition at line 2805 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLR
 | ) |  |

Configure PLL used for SYSCLK Domain.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLR can be written only when PLL is disabled
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLR This parameter can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_3
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_5
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_7
  • LL_RCC_PLLR_DIV_8
Return values:
None

Definition at line 2566 of file stm32g0xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM1 | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLL used for TIM1 domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLQ can be written only when PLL is disabled
User shall verify whether the PLL configuration is not done through other functions (ex: RNG, TIM15)
This can be selected for TIM1
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM1
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM1
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM1
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM1
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
None

Definition at line 2934 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM15 | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLL used for TIM15 domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLQ can be written only when PLL is disabled
User shall verify whether the PLL configuration is not done through other functions (ex: RNG, TIM1)
This can be selected for TIM15
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM15
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM15
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM15
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM15
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
None

Definition at line 2977 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_USB | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLL used for USB domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled
PLLN/PLLQ can be written only when PLL is disabled
User shall verify whether the PLL configuration is not done through other functions (ex: TIM1, TIM15)
This can be selected for USB
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_USB
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_USB
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_USB
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_USB
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
None

Definition at line 2891 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_Disable ( void )

Disable PLL.

Note:
Cannot be disabled if the PLL clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Disable
Return values:
None

Definition at line 2519 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC ( void )

Disable PLL output mapped on ADC domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
User shall check that PLL is not used by any other peripheral (ex: I2S1)
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
Return values:
None

Definition at line 3140 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_FDCAN ( void )

Disable PLL output mapped on FDCAN domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
User shall check that PLL is not used by any other peripheral (ex: TIM, TIM15)
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_FDCAN
Return values:
None

Definition at line 3295 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S1 ( void )

Disable PLL output mapped on I2S1 domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
User shall check that PLL is not used by any other peripheral (ex: RNG)
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S1
Return values:
None

Definition at line 3191 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S2 ( void )

Disable PLL output mapped on I2S2 domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
User shall check that PLL is not used by any other peripheral (ex: RNG)
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S2
Return values:
None

Definition at line 3217 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG ( void )

Disable PLL output mapped on RNG domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
User shall check that PLL is not used by any other peripheral (ex: TIM, TIM15)
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_RNG
Return values:
None

Definition at line 3256 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS ( void )

Disable PLL output mapped on SYSCLK domain.

Note:
Cannot be disabled if the PLL clock is used as the system clock
In order to save power, when the PLLCLK of the PLL is not used, Main PLL should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
Return values:
None

Definition at line 3446 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM1 ( void )

Disable PLL output mapped on TIM1 domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
User shall check that PLL is not used by any other peripheral (ex: RNG, TIM15)
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM1
Return values:
None

Definition at line 3373 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM15 ( void )

Disable PLL output mapped on TIM15 domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
User shall check that PLL is not used by any other peripheral (ex: RNG, TIM1)
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM15
Return values:
None

Definition at line 3412 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_USB ( void )

Disable PLL output mapped on USB domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
User shall check that PLL is not used by any other peripheral (ex: TIM, TIM15)
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_USB
Return values:
None

Definition at line 3334 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_Enable ( void )

Enable PLL.

Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Enable
Return values:
None

Definition at line 2508 of file stm32g0xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC ( void )

Enable PLL output mapped on ADC domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
Note:
User shall check that PLL enable is not done through other functions (ex: I2S1)
Return values:
None

Definition at line 3125 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_FDCAN ( void )

Enable PLL output mapped on FDCAN domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_FDCAN
Note:
User shall check that PLL enable is not done through other functions (ex: TIM1, TIM15)
Return values:
None

Definition at line 3280 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1 ( void )

Enable PLL output mapped on I2S domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S1
Note:
User shall check that PLL enable is not done through other functions (ex: ADC)
Return values:
None

Definition at line 3162 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S2 ( void )

Enable PLL output mapped on I2S2 domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S2
Note:
User shall check that PLL enable is not done through other functions (ex: ADC)
Return values:
None

Definition at line 3175 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG ( void )

Enable PLL output mapped on RNG domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_RNG
Note:
User shall check that PLL enable is not done through other functions (ex: TIM1, TIM15)
Return values:
None

Definition at line 3241 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS ( void )

Enable PLL output mapped on SYSCLK domain.

Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
Return values:
None

Definition at line 3433 of file stm32g0xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1 ( void )

Enable PLL output mapped on TIM1 domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM1
Note:
User shall check that PLL enable is not done through other functions (ex: RNG, TIM15)
Return values:
None

Definition at line 3358 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15 ( void )

Enable PLL output mapped on TIM15 domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM15
Note:
User shall check that PLL enable is not done through other functions (ex: RNG, TIM1)
Return values:
None

Definition at line 3397 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_USB ( void )

Enable PLL output mapped on USB domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_USB
Note:
User shall check that PLL enable is not done through other functions (ex: TIM1, TIM15)
Return values:
None

Definition at line 3319 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider ( void )

Get Division factor for the main PLL and other PLL.

Reference Manual to LL API cross reference:
PLLCFGR PLLM LL_RCC_PLL_GetDivider
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8

Definition at line 3113 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_FDCAN(), RCC_PLL_GetFreqDomain_I2S1(), RCC_PLL_GetFreqDomain_I2S2(), RCC_PLL_GetFreqDomain_RNG(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLL_GetFreqDomain_TIM1(), RCC_PLL_GetFreqDomain_TIM15(), and RCC_PLL_GetFreqDomain_USB().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource ( void )

Get the oscillator used as PLL clock source.

Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE

Definition at line 3095 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_FDCAN(), RCC_PLL_GetFreqDomain_I2S1(), RCC_PLL_GetFreqDomain_I2S2(), RCC_PLL_GetFreqDomain_RNG(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLL_GetFreqDomain_TIM1(), RCC_PLL_GetFreqDomain_TIM15(), and RCC_PLL_GetFreqDomain_USB().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetN ( void )

Get Main PLL multiplication factor for VCO.

Reference Manual to LL API cross reference:
PLLCFGR PLLN LL_RCC_PLL_GetN
Return values:
Between 8 and 86

Definition at line 2989 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_FDCAN(), RCC_PLL_GetFreqDomain_I2S1(), RCC_PLL_GetFreqDomain_I2S2(), RCC_PLL_GetFreqDomain_RNG(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLL_GetFreqDomain_TIM1(), RCC_PLL_GetFreqDomain_TIM15(), and RCC_PLL_GetFreqDomain_USB().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetP ( void )

Get Main PLL division factor for PLLP.

Note:
used for PLLPCLK (ADC & I2S clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLP LL_RCC_PLL_GetP
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32

Definition at line 3031 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_I2S1(), and RCC_PLL_GetFreqDomain_I2S2().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ ( void )

Get Main PLL division factor for PLLQ.

Note:
used for PLLQCLK selected for RNG, TIM1, TIM15 clock
Reference Manual to LL API cross reference:
PLLCFGR PLLQ LL_RCC_PLL_GetQ
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8

Definition at line 3050 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_FDCAN(), RCC_PLL_GetFreqDomain_RNG(), RCC_PLL_GetFreqDomain_TIM1(), RCC_PLL_GetFreqDomain_TIM15(), and RCC_PLL_GetFreqDomain_USB().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetR ( void )

Get Main PLL division factor for PLLR.

Note:
used for PLLCLK (system clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLR LL_RCC_PLL_GetR
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_3
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_5
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_7
  • LL_RCC_PLLR_DIV_8

Definition at line 3069 of file stm32g0xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC ( void )

Check if PLL output mapped on ADC domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
Return values:
State of bit (1 or 0).

Definition at line 3150 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_FDCAN ( void )

Check if PLL output mapped on FDCAN domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_FDCAN
Return values:
State of bit (1 or 0).

Definition at line 3305 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetFDCANClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S1 ( void )

Check if PLL output mapped on I2S1 domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_I2S1
Return values:
State of bit (1 or 0).

Definition at line 3201 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S2 ( void )

Check if PLL output mapped on I2S2 domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_I2S2
Return values:
State of bit (1 or 0).

Definition at line 3227 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetI2SClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_RNG ( void )

Check if PLL output mapped on RNG domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_RNG
Return values:
State of bit (1 or 0).

Definition at line 3266 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS ( void )

Check if PLL output mapped on SYSCLK domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
Return values:
State of bit (1 or 0).

Definition at line 3456 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_TIM1 ( void )

Check if PLL output mapped on TIM1 domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_TIM1
Return values:
State of bit (1 or 0).

Definition at line 3383 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_TIM15 ( void )

Check if PLL output mapped on TIM15 domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_TIM15
Return values:
State of bit (1 or 0).

Definition at line 3422 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetTIMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_USB ( void )

Check if PLL output mapped on USB domain clock is enabled.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_USB
Return values:
State of bit (1 or 0).

Definition at line 3344 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady ( void )

Check if PLL Ready.

Reference Manual to LL API cross reference:
CR PLLRDY LL_RCC_PLL_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2529 of file stm32g0xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_GetADCClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetTIMClockFreq(), LL_RCC_GetUSBClockFreq(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_PLL_IsBusy().

__STATIC_INLINE void LL_RCC_PLL_SetMainSource ( uint32_t PLLSource )

Configure PLL clock source.

Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
Parameters:
PLLSource This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
Return values:
None

Definition at line 3082 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG Management

Functions
FLAG Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void)
Clear HSI48 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void)
Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag Option byte reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PWRRST (void)
Check if RCC flag BOR or POR/PDR reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.

Function Documentation

__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS ( void )

Clear Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR CSSC LL_RCC_ClearFlag_HSECSS
Return values:
None

Definition at line 3537 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY ( void )

Clear HSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSERDYC LL_RCC_ClearFlag_HSERDY
Return values:
None

Definition at line 3506 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY ( void )

Clear HSI48 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
Return values:
None

Definition at line 3527 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY ( void )

Clear HSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Return values:
None

Definition at line 3496 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS ( void )

Clear LSE Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR LSECSSC LL_RCC_ClearFlag_LSECSS
Return values:
None

Definition at line 3547 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY ( void )

Clear LSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSERDYC LL_RCC_ClearFlag_LSERDY
Return values:
None

Definition at line 3486 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY ( void )

Clear LSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
Return values:
None

Definition at line 3476 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY ( void )

Clear PLL ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
Return values:
None

Definition at line 3516 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearResetFlags ( void )

Set RMVF bit to clear the reset flags.

Reference Manual to LL API cross reference:
CSR RMVF LL_RCC_ClearResetFlags
Return values:
None

Definition at line 3709 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS ( void )

Check if Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
Return values:
State of bit (1 or 0).

Definition at line 3619 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY ( void )

Check if HSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 3587 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY ( void )

Check if HSI48 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
Return values:
State of bit (1 or 0).

Definition at line 3608 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY ( void )

Check if HSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3577 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST ( void )

Check if RCC flag Independent Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
Return values:
State of bit (1 or 0).

Definition at line 3639 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST ( void )

Check if RCC flag Low Power reset is set or not.

Reference Manual to LL API cross reference:
CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
Return values:
State of bit (1 or 0).

Definition at line 3649 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS ( void )

Check if LSE Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 3629 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY ( void )

Check if LSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 3567 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY ( void )

Check if LSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3557 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST ( void )

Check if RCC flag Option byte reset is set or not.

Reference Manual to LL API cross reference:
CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
Return values:
State of bit (1 or 0).

Definition at line 3659 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST ( void )

Check if RCC flag Pin reset is set or not.

Reference Manual to LL API cross reference:
CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Return values:
State of bit (1 or 0).

Definition at line 3669 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY ( void )

Check if PLL ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 3597 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST ( void )

Check if RCC flag BOR or POR/PDR reset is set or not.

Reference Manual to LL API cross reference:
CSR PWRRSTF LL_RCC_IsActiveFlag_PWRRST
Return values:
State of bit (1 or 0).

Definition at line 3699 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST ( void )

Check if RCC flag Software reset is set or not.

Reference Manual to LL API cross reference:
CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
Return values:
State of bit (1 or 0).

Definition at line 3679 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST ( void )

Check if RCC flag Window Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
Return values:
State of bit (1 or 0).

Definition at line 3689 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Management

Functions
IT Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void)
Enable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void)
Disable HSI48 ready interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSI48RDY (void)
Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableIT_HSERDY ( void )

Disable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_DisableIT_HSERDY
Return values:
None

Definition at line 3819 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY ( void )

Disable HSI48 ready interrupt.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
Return values:
None

Definition at line 3840 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY ( void )

Disable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
Return values:
None

Definition at line 3809 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSERDY ( void )

Disable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_DisableIT_LSERDY
Return values:
None

Definition at line 3799 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY ( void )

Disable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
Return values:
None

Definition at line 3789 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY ( void )

Disable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
Return values:
None

Definition at line 3829 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSERDY ( void )

Enable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_EnableIT_HSERDY
Return values:
None

Definition at line 3757 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY ( void )

Enable HSI48 ready interrupt.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
Return values:
None

Definition at line 3778 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY ( void )

Enable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
Return values:
None

Definition at line 3747 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSERDY ( void )

Enable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_EnableIT_LSERDY
Return values:
None

Definition at line 3737 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY ( void )

Enable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
Return values:
None

Definition at line 3727 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY ( void )

Enable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
Return values:
None

Definition at line 3767 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY ( void )

Checks if HSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 3893 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY ( void )

Checks if HSI48 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
Return values:
State of bit (1 or 0).

Definition at line 3882 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY ( void )

Checks if HSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3871 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY ( void )

Checks if LSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 3861 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY ( void )

Checks if LSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3851 of file stm32g0xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY ( void )

Checks if PLL ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 3903 of file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: De-initialization function

Functions
De-initialization function
RCC Exported Functions

Functions

ErrorStatus LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.

Function Documentation

ErrorStatus LL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE and PLL OFF
  • AHB and APB1 prescaler set to 1.
  • CSS, MCO OFF
  • All interrupts disabled
This function does not modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RCC registers are de-initialized
  • ERROR: not applicable

Definition at line 166 of file stm32g0xx_ll_rcc.c.

References LL_RCC_HSE_IsReady(), LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_HSI_SetCalibTrimming(), LL_RCC_PLL_IsReady(), and LL_RCC_WriteReg.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get system and peripherals clocks frequency functions

Functions
Get system and peripherals clocks frequency functions
RCC Exported Functions

Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks and different peripheral clocks available on the device. More...

Functions

void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetI2SClockFreq (uint32_t I2SxSource)
Return I2Sx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetTIMClockFreq (uint32_t TIMxSource)
Return TIMx clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CEC clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCANx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetRTCClockFreq (void)
Return RTC clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.

Detailed Description

Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks and different peripheral clocks available on the device.

Note:
If SYSCLK source is HSI, function returns values based on HSI_VALUE divided by HSI division factor(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) or HSI_VALUE(**) multiplied/divided by the PLL factors.
(**) HSI_VALUE is a constant defined in this file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a constant defined in this file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be incorrect when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.

Function Documentation

uint32_t LL_RCC_GetADCClockFreq ( uint32_t ADCxSource )

Return ADCx clock frequency.

Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
ADC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 894 of file stm32g0xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_ADC_CLKSOURCE, LL_RCC_ADC_CLKSOURCE_HSI, LL_RCC_ADC_CLKSOURCE_PLL, LL_RCC_ADC_CLKSOURCE_SYSCLK, LL_RCC_GetADCClockSource(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_ADC(), LL_RCC_PLL_IsReady(), RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_ADC().

uint32_t LL_RCC_GetCECClockFreq ( uint32_t CECxSource )

Return CEC clock frequency.

Parameters:
CECxSource This parameter can be one of the following values:
  • LL_RCC_CEC_CLKSOURCE
Return values:
CEC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 811 of file stm32g0xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_CEC_CLKSOURCE, LL_RCC_CEC_CLKSOURCE_HSI_DIV488, LL_RCC_CEC_CLKSOURCE_LSE, LL_RCC_GetCECClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, and LSE_VALUE.

uint32_t LL_RCC_GetFDCANClockFreq ( uint32_t FDCANxSource )

Return FDCANx clock frequency.

Parameters:
FDCANxSource This parameter can be one of the following values:
  • LL_RCC_FDCAN_CLKSOURCE
Return values:
FDCANx clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready

Definition at line 849 of file stm32g0xx_ll_rcc.c.

References assert_param, HSE_VALUE, IS_LL_RCC_FDCAN_CLKSOURCE, LL_RCC_FDCAN_CLKSOURCE_HSE, LL_RCC_FDCAN_CLKSOURCE_PCLK1, LL_RCC_FDCAN_CLKSOURCE_PLL, LL_RCC_GetFDCANClockSource(), LL_RCC_HSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_FDCAN(), LL_RCC_PLL_IsReady(), RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_FDCAN().

uint32_t LL_RCC_GetI2CClockFreq ( uint32_t I2CxSource )

Return I2Cx clock frequency.

Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
Return values:
I2C clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready

Definition at line 367 of file stm32g0xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_I2C_CLKSOURCE, LL_RCC_GetI2CClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_I2C1_CLKSOURCE, LL_RCC_I2C1_CLKSOURCE_HSI, LL_RCC_I2C1_CLKSOURCE_PCLK1, LL_RCC_I2C1_CLKSOURCE_SYSCLK, LL_RCC_I2C2_CLKSOURCE, LL_RCC_I2C2_CLKSOURCE_HSI, LL_RCC_I2C2_CLKSOURCE_PCLK1, LL_RCC_I2C2_CLKSOURCE_SYSCLK, LL_RCC_PERIPH_FREQUENCY_NO, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetI2SClockFreq ( uint32_t I2SxSource )

Return I2Sx clock frequency.

Parameters:
I2SxSource This parameter can be one of the following values:
  • LL_RCC_I2S1_CLKSOURCE
Return values:
I2S clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready

Definition at line 435 of file stm32g0xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_I2S_CLKSOURCE, LL_RCC_GetI2SClockSource(), LL_RCC_I2S1_CLKSOURCE, LL_RCC_I2S1_CLKSOURCE_HSI, LL_RCC_I2S1_CLKSOURCE_PIN, LL_RCC_I2S1_CLKSOURCE_PLL, LL_RCC_I2S1_CLKSOURCE_SYSCLK, LL_RCC_I2S2_CLKSOURCE, LL_RCC_I2S2_CLKSOURCE_HSI, LL_RCC_I2S2_CLKSOURCE_PIN, LL_RCC_I2S2_CLKSOURCE_PLL, LL_RCC_I2S2_CLKSOURCE_SYSCLK, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_I2S1(), LL_RCC_PLL_IsEnabledDomain_I2S2(), LL_RCC_PLL_IsReady(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_I2S1(), and RCC_PLL_GetFreqDomain_I2S2().

uint32_t LL_RCC_GetLPTIMClockFreq ( uint32_t LPTIMxSource )

Return LPTIMx clock frequency.

Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
Return values:
LPTIM clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready

Definition at line 603 of file stm32g0xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_LPTIM_CLKSOURCE, LL_RCC_GetLPTIMClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_HSI, LL_RCC_LPTIM1_CLKSOURCE_LSE, LL_RCC_LPTIM1_CLKSOURCE_LSI, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LPTIM2_CLKSOURCE_HSI, LL_RCC_LPTIM2_CLKSOURCE_LSE, LL_RCC_LPTIM2_CLKSOURCE_LSI, LL_RCC_LPTIM2_CLKSOURCE_PCLK1, LL_RCC_LSE_IsReady(), LL_RCC_LSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, LSI_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetLPUARTClockFreq ( uint32_t LPUARTxSource )

Return LPUARTx clock frequency.

Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
  • LL_RCC_LPUART2_CLKSOURCE (*)
Return values:
LPUART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready (*) feature not available on all devices

Definition at line 519 of file stm32g0xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_LPUART_CLKSOURCE, LL_RCC_GetLPUARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LPUART1_CLKSOURCE, LL_RCC_LPUART1_CLKSOURCE_HSI, LL_RCC_LPUART1_CLKSOURCE_LSE, LL_RCC_LPUART1_CLKSOURCE_PCLK1, LL_RCC_LPUART1_CLKSOURCE_SYSCLK, LL_RCC_LPUART2_CLKSOURCE, LL_RCC_LPUART2_CLKSOURCE_HSI, LL_RCC_LPUART2_CLKSOURCE_LSE, LL_RCC_LPUART2_CLKSOURCE_PCLK1, LL_RCC_LPUART2_CLKSOURCE_SYSCLK, LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_LPUART_Init().

uint32_t LL_RCC_GetRNGClockFreq ( uint32_t RNGxSource )

Return RNGx clock frequency.

Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
RNG clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 758 of file stm32g0xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_RNG_CLKSOURCE, LL_RCC_GetRNGClockSource(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_RNG(), LL_RCC_PLL_IsReady(), LL_RCC_RNG_CLKSOURCE_HSI_DIV8, LL_RCC_RNG_CLKSOURCE_NONE, LL_RCC_RNG_CLKSOURCE_PLL, LL_RCC_RNG_CLKSOURCE_SYSCLK, RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_RNG().

uint32_t LL_RCC_GetRTCClockFreq ( void )

Return RTC clock frequency.

Return values:
RTC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 934 of file stm32g0xx_ll_rcc.c.

References HSE_VALUE, LL_RCC_GetRTCClockSource(), LL_RCC_LSE_IsReady(), LL_RCC_LSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_RTC_CLKSOURCE_HSE_DIV32, LL_RCC_RTC_CLKSOURCE_LSE, LL_RCC_RTC_CLKSOURCE_LSI, LL_RCC_RTC_CLKSOURCE_NONE, LSE_VALUE, and LSI_VALUE.

void LL_RCC_GetSystemClocksFreq ( LL_RCC_ClocksTypeDef * RCC_Clocks )

Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks.

Note:
Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function must be called to update structure fields. Otherwise, any configuration based on this function will be incorrect.
Parameters:
RCC_Clocks pointer to a LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
Return values:
None

Definition at line 234 of file stm32g0xx_ll_rcc.c.

References LL_RCC_ClocksTypeDef::HCLK_Frequency, LL_RCC_ClocksTypeDef::PCLK1_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetSystemClockFreq(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by LL_I2S_Init(), LL_LPTIM_Disable(), and LL_USART_Init().

uint32_t LL_RCC_GetTIMClockFreq ( uint32_t TIMxSource )

Return TIMx clock frequency.

Parameters:
TIMxSource This parameter can be one of the following values:
  • LL_RCC_TIM1_CLKSOURCE
Return values:
TIMx clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 690 of file stm32g0xx_ll_rcc.c.

References assert_param, IS_LL_RCC_TIM_CLKSOURCE, LL_RCC_GetTIMClockSource(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_TIM1(), LL_RCC_PLL_IsEnabledDomain_TIM15(), LL_RCC_PLL_IsReady(), LL_RCC_TIM15_CLKSOURCE, LL_RCC_TIM15_CLKSOURCE_PCLK1, LL_RCC_TIM15_CLKSOURCE_PLL, LL_RCC_TIM1_CLKSOURCE, LL_RCC_TIM1_CLKSOURCE_PCLK1, LL_RCC_TIM1_CLKSOURCE_PLL, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_TIM1(), and RCC_PLL_GetFreqDomain_TIM15().

uint32_t LL_RCC_GetUSARTClockFreq ( uint32_t USARTxSource )

Return USARTx clock frequency.

Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
  • LL_RCC_USART2_CLKSOURCE
  • LL_RCC_USART3_CLKSOURCE
Return values:
USART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 255 of file stm32g0xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_USART_CLKSOURCE, LL_RCC_GetUSARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART1_CLKSOURCE_HSI, LL_RCC_USART1_CLKSOURCE_LSE, LL_RCC_USART1_CLKSOURCE_PCLK1, LL_RCC_USART1_CLKSOURCE_SYSCLK, LL_RCC_USART2_CLKSOURCE, LL_RCC_USART2_CLKSOURCE_HSI, LL_RCC_USART2_CLKSOURCE_LSE, LL_RCC_USART2_CLKSOURCE_PCLK1, LL_RCC_USART2_CLKSOURCE_SYSCLK, LL_RCC_USART3_CLKSOURCE, LL_RCC_USART3_CLKSOURCE_HSI, LL_RCC_USART3_CLKSOURCE_LSE, LL_RCC_USART3_CLKSOURCE_PCLK1, LL_RCC_USART3_CLKSOURCE_SYSCLK, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_USART_Init().

uint32_t LL_RCC_GetUSBClockFreq ( uint32_t USBxSource )

Return USBx clock frequency.

Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
USB clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 977 of file stm32g0xx_ll_rcc.c.

References assert_param, HSE_VALUE, HSI48_VALUE, IS_LL_RCC_USB_CLKSOURCE, LL_RCC_GetUSBClockSource(), LL_RCC_HSE_IsReady(), LL_RCC_HSI48_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsEnabledDomain_USB(), LL_RCC_PLL_IsReady(), LL_RCC_USB_CLKSOURCE_HSE, LL_RCC_USB_CLKSOURCE_HSI48, LL_RCC_USB_CLKSOURCE_PLL, and RCC_PLL_GetFreqDomain_USB().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG

Defines

#define IS_LL_RNG_CED(__MODE__)

Define Documentation

#define IS_LL_RNG_CED ( __MODE__ )
Value:
(((__MODE__) == LL_RNG_CED_ENABLE) || \
                                 ((__MODE__) == LL_RNG_CED_DISABLE))

Definition at line 47 of file stm32g0xx_ll_rng.c.

Referenced by LL_RNG_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RNG_InitTypeDef Struct Reference
RNG Exported Init structures

LL RNG Init Structure Definition. More...

#include <stm32g0xx_ll_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

LL RNG Init Structure Definition.

Definition at line 55 of file stm32g0xx_ll_rng.h.

Field Documentation

uint32_t LL_RNG_InitTypeDef::ClockErrorDetection

Clock error detection. This parameter can be one value of Clock Error Detection. This parameter can be modified using unitary functions LL_RNG_EnableClkErrorDetect().

Definition at line 57 of file stm32g0xx_ll_rng.h.

Referenced by LL_RNG_Init(), and LL_RNG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_rng.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clock Error Detection

Defines
Clock Error Detection
RNG Exported Constants

Defines

#define | LL_RNG_CED_ENABLE 0x00000000U
#define | LL_RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define LL_RNG_CED_DISABLE RNG_CR_CED

Clock error detection disabled

Definition at line 76 of file stm32g0xx_ll_rng.h.

#define LL_RNG_CED_ENABLE 0x00000000U

Clock error detection enabled

Definition at line 75 of file stm32g0xx_ll_rng.h.

Referenced by LL_RNG_StructInit().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RNG Exported Constants

Flags defines which can be used with LL_RNG_ReadReg function. More...

Defines

#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS

Detailed Description

Flags defines which can be used with LL_RNG_ReadReg function.

Define Documentation

#define LL_RNG_SR_CECS RNG_SR_CECS

Clock error current status

Definition at line 86 of file stm32g0xx_ll_rng.h.

#define LL_RNG_SR_CEIS RNG_SR_CEIS

Clock error interrupt status

Definition at line 88 of file stm32g0xx_ll_rng.h.

#define LL_RNG_SR_DRDY RNG_SR_DRDY

Register contains valid random data

Definition at line 85 of file stm32g0xx_ll_rng.h.

#define LL_RNG_SR_SECS RNG_SR_SECS

Seed error current status

Definition at line 87 of file stm32g0xx_ll_rng.h.

#define LL_RNG_SR_SEIS RNG_SR_SEIS

Seed error interrupt status

Definition at line 89 of file stm32g0xx_ll_rng.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
RNG Exported Constants

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros. More...

Defines

#define LL_RNG_CR_IE RNG_CR_IE

Detailed Description

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Define Documentation

#define LL_RNG_CR_IE RNG_CR_IE

RNG Interrupt enable

Definition at line 98 of file stm32g0xx_ll_rng.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RNG Exported Macros

Defines

#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Define Documentation

#define LL_RNG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 131 of file stm32g0xx_ll_rng.h.

#define LL_RNG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 123 of file stm32g0xx_ll_rng.h.

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STM32G0C1xx HAL User Manual: RNG Configuration functions

Functions
RNG Configuration functions
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE void | LL_RNG_EnableClkErrorDetect (RNG_TypeDef *RNGx)
Enable Clock Error Detection.
__STATIC_INLINE void | LL_RNG_DisableClkErrorDetect (RNG_TypeDef *RNGx)
Disable RNG Clock Error Detection.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledClkErrorDetect (RNG_TypeDef *RNGx)
Check if RNG Clock Error Detection is enabled.

Function Documentation

__STATIC_INLINE void LL_RNG_Disable ( RNG_TypeDef * RNGx )

Disable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Disable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 166 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_DisableClkErrorDetect ( RNG_TypeDef * RNGx )

Disable RNG Clock Error Detection.

Reference Manual to LL API cross reference:
CR CED LL_RNG_DisableClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 199 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_Enable ( RNG_TypeDef * RNGx )

Enable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Enable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 155 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableClkErrorDetect ( RNG_TypeDef * RNGx )

Enable Clock Error Detection.

Reference Manual to LL API cross reference:
CR CED LL_RNG_EnableClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 188 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabled ( RNG_TypeDef * RNGx )

Check if Random Number Generator is enabled.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_IsEnabled
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 177 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect ( RNG_TypeDef * RNGx )

Check if RNG Clock Error Detection is enabled.

Reference Manual to LL API cross reference:
CR CED LL_RNG_IsEnabledClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 210 of file stm32g0xx_ll_rng.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG Management

Functions
FLAG Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.

Function Documentation

__STATIC_INLINE void LL_RNG_ClearFlag_CEIS ( RNG_TypeDef * RNGx )

Clear Clock Error interrupt Status (CEIS) Flag.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_ClearFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 284 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_ClearFlag_SEIS ( RNG_TypeDef * RNGx )

Clear Seed Error interrupt Status (SEIS) Flag.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_ClearFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 295 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS ( RNG_TypeDef * RNGx )

Indicate if the Clock Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CECS LL_RNG_IsActiveFlag_CECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 240 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS ( RNG_TypeDef * RNGx )

Indicate if the Clock Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_IsActiveFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 262 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY ( RNG_TypeDef * RNGx )

Indicate if the RNG Data ready Flag is set or not.

Reference Manual to LL API cross reference:
SR DRDY LL_RNG_IsActiveFlag_DRDY
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 229 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS ( RNG_TypeDef * RNGx )

Indicate if the Seed Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SECS LL_RNG_IsActiveFlag_SECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 251 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS ( RNG_TypeDef * RNGx )

Indicate if the Seed Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_IsActiveFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 273 of file stm32g0xx_ll_rng.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Management

Functions
IT Management
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Function Documentation

__STATIC_INLINE void LL_RNG_DisableIT ( RNG_TypeDef * RNGx )

Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_DisableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 327 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableIT ( RNG_TypeDef * RNGx )

Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_EnableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 315 of file stm32g0xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT ( RNG_TypeDef * RNGx )

Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_IsEnabledIT
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 339 of file stm32g0xx_ll_rng.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Management

Functions
Data Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 (RNG_TypeDef *RNGx)
Return32-bit Random Number value.

Function Documentation

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 ( RNG_TypeDef * RNGx )

Return32-bit Random Number value.

Reference Manual to LL API cross reference:
DR RNDATA LL_RNG_ReadRandData32
Parameters:
RNGx RNG Instance
Return values:
Generated 32-bit random value

Definition at line 358 of file stm32g0xx_ll_rng.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Functions

ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_RNG_DeInit ( RNG_TypeDef * RNGx )

De-initialize RNG registers (Registers restored to their default values).

Parameters:
RNGx RNG Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are de-initialized
  • ERROR: not applicable

Definition at line 71 of file stm32g0xx_ll_rng.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_RNG, and LL_AHB1_GRP1_ReleaseReset().

ErrorStatus LL_RNG_Init | ( | RNG_TypeDef * | RNGx,
 |  | LL_RNG_InitTypeDef * | RNG_InitStruct
 | ) |  |

Initialize RNG registers according to the specified parameters in RNG_InitStruct.

Parameters:
RNGx | RNG Instance
RNG_InitStruct | pointer to a LL_RNG_InitTypeDef structure that contains the configuration information for the specified RNG peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are initialized according to RNG_InitStruct content
  • ERROR: not applicable

Definition at line 102 of file stm32g0xx_ll_rng.c.

References assert_param, LL_RNG_InitTypeDef::ClockErrorDetection, and IS_LL_RNG_CED.

void LL_RNG_StructInit ( LL_RNG_InitTypeDef * RNG_InitStruct )

Set each LL_RNG_InitTypeDef field to default value.

Parameters:
RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 120 of file stm32g0xx_ll_rng.c.

References LL_RNG_InitTypeDef::ClockErrorDetection, and LL_RNG_CED_ENABLE.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define | RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
#define | RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_LL_INIT_MASK 0xFFFFFFFFU
#define | RTC_LL_RSF_MASK 0xFFFFFF5FU
#define | RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
#define | RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
#define | RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
#define | RTC_OFFSET_WEEKDAY (uint32_t)24U
#define | RTC_OFFSET_DAY (uint32_t)16U
#define | RTC_OFFSET_MONTH (uint32_t)8U
#define | RTC_OFFSET_HOUR (uint32_t)16U
#define | RTC_OFFSET_MINUTE (uint32_t)8U

Define Documentation

#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU

Definition at line 46 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_StructInit().

#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */

Definition at line 50 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_EnterInitMode().

#define RTC_LL_INIT_MASK 0xFFFFFFFFU

Definition at line 47 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_EnableInitMode().

#define RTC_LL_RSF_MASK 0xFFFFFF5FU

Definition at line 48 of file stm32g0xx_ll_rtc.h.

#define RTC_OFFSET_DAY (uint32_t)16U

Definition at line 57 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_HOUR (uint32_t)16U

Definition at line 59 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MINUTE (uint32_t)8U

Definition at line 60 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MONTH (uint32_t)8U

Definition at line 58 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_WEEKDAY (uint32_t)24U

Definition at line 56 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU

Definition at line 47 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_DeInit(), and LL_RTC_StructInit().

#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */

Definition at line 51 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_WaitForSynchro().

#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)

Definition at line 51 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_EnableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)

Definition at line 52 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)

Definition at line 53 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Private Macros

Defines
RTC Private Macros
RTC

Defines

#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define | IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Define Documentation

#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 108 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMA_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))

Definition at line 93 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 111 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ALMB_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))

Definition at line 100 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ASYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FU)

Definition at line 64 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_DAY ( __DAY__ ) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))

Definition at line 87 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_FORMAT_BIN) \
                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))

Definition at line 68 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR12 ( __HOUR__ ) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))

Definition at line 74 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR24 ( __HOUR__ ) ((__HOUR__) <= 23U)

Definition at line 75 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOURFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))

Definition at line 61 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_MINUTES ( __MINUTES__ ) ((__MINUTES__) <= 59U)

Definition at line 76 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_MONTH ( __MONTH__ ) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))

Definition at line 89 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

#define IS_LL_RTC_SECONDS ( __SECONDS__ ) ((__SECONDS__) <= 59U)

Definition at line 77 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_SYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FFFU)

Definition at line 66 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_TIME_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))

Definition at line 71 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_WEEKDAY ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))

Definition at line 79 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_YEAR ( __YEAR__ ) ((__YEAR__) <= 99U)

Definition at line 91 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_InitTypeDef Struct Reference
RTC Exported Init structure

RTC Init structures definition. More...

#include <stm32g0xx_ll_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrescaler
uint32_t | SynchPrescaler

Detailed Description

RTC Init structures definition.

Definition at line 85 of file stm32g0xx_ll_rtc.h.

Field Documentation

uint32_t LL_RTC_InitTypeDef::AsynchPrescaler

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

This feature can be modified afterwards using unitary function LL_RTC_SetAsynchPrescaler().

Definition at line 93 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::HourFormat

Specifies the RTC Hours Format. This parameter can be a value of HOUR FORMAT

This feature can be modified afterwards using unitary function LL_RTC_SetHourFormat().

Definition at line 87 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::SynchPrescaler

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

This feature can be modified afterwards using unitary function LL_RTC_SetSynchPrescaler().

Definition at line 99 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_rtc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_TimeTypeDef Struct Reference
RTC Exported Init structure

RTC Time structure definition. More...

#include <stm32g0xx_ll_rtc.h>

Data Fields

uint32_t | TimeFormat
uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds

Detailed Description

RTC Time structure definition.

Definition at line 109 of file stm32g0xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_TimeTypeDef::Hours

Specifies the RTC Time Hours. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the LL_RTC_TIME_FORMAT_PM is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the LL_RTC_TIME_FORMAT_AM_OR_24 is selected.

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetHour().

Definition at line 116 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetMinute().

Definition at line 122 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetSecond().

Definition at line 127 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint32_t LL_RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of TIME FORMAT

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetFormat().

Definition at line 111 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_rtc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_DateTypeDef Struct Reference
RTC Exported Init structure

RTC Date structure definition. More...

#include <stm32g0xx_ll_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Day
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 136 of file stm32g0xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_DateTypeDef::Day

Specifies the RTC Date Day. This parameter must be a number between Min_Data = 1 and Max_Data = 31

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetDay().

Definition at line 148 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Month

Specifies the RTC Date Month. This parameter can be a value of MONTH

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetMonth().

Definition at line 143 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of WEEK DAY

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetWeekDay().

Definition at line 138 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetYear().

Definition at line 153 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_rtc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_AlarmTypeDef Struct Reference
RTC Exported Init structure

RTC Alarm structure definition. More...

#include <stm32g0xx_ll_rtc.h>

Data Fields

LL_RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay

Detailed Description

RTC Alarm structure definition.

Definition at line 162 of file stm32g0xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Day/WeekDay. If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetDay() for ALARM A or LL_RTC_ALMB_SetDay() for ALARM B.

If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of WEEK DAY.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetWeekDay() for ALARM A or LL_RTC_ALMB_SetWeekDay() for ALARM B.

Definition at line 180 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on day or WeekDay. This parameter can be a value of RTC Alarm A Date WeekDay for ALARM A or RTC Alarm B Date WeekDay for ALARM B

This feature can be modified afterwards using unitary function LL_RTC_ALMA_EnableWeekday() or LL_RTC_ALMA_DisableWeekday() for ALARM A or LL_RTC_ALMB_EnableWeekday() or LL_RTC_ALMB_DisableWeekday() for ALARM B

Definition at line 173 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of ALARMA MASK for ALARM A or ALARMB MASK for ALARM B.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetMask() for ALARM A or LL_RTC_ALMB_SetMask() for ALARM B

Definition at line 166 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

LL_RTC_TimeTypeDef LL_RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members.

Definition at line 164 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_rtc.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FORMAT

Defines
FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_FORMAT_BIN 0x00000000U
#define | LL_RTC_FORMAT_BCD 0x00000001U

Define Documentation

#define LL_RTC_FORMAT_BCD 0x00000001U

BCD data format

Definition at line 208 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_FORMAT_BIN 0x00000000U

Binary data format

Definition at line 207 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Alarm A Date WeekDay

Defines
RTC Alarm A Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm A Date is selected

Definition at line 216 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), and LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Alarm A WeekDay is selected

Definition at line 217 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Alarm B Date WeekDay

Defines
RTC Alarm B Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Define Documentation

#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm B Date is selected

Definition at line 225 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Alarm B WeekDay is selected

Definition at line 226 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RTC Exported Constants

Flags defines which can be used with LL_RTC_ReadReg function. More...

Defines

#define | LL_RTC_SCR_ITSF RTC_SCR_CITSF
#define | LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
#define | LL_RTC_SCR_TSF RTC_SCR_CTSF
#define | LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define | LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define | LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
#define | LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define | LL_RTC_ICSR_INITF RTC_ICSR_INITF
#define | LL_RTC_ICSR_RSF RTC_ICSR_RSF
#define | LL_RTC_ICSR_INITS RTC_ICSR_INITS
#define | LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
#define | LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
#define | LL_RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF
#define | LL_RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF

Detailed Description

Flags defines which can be used with LL_RTC_ReadReg function.

Define Documentation

#define LL_RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF

Definition at line 251 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF

Definition at line 250 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ICSR_INITF RTC_ICSR_INITF

Definition at line 245 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ICSR_INITS RTC_ICSR_INITS

Definition at line 247 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF

Definition at line 244 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ICSR_RSF RTC_ICSR_RSF

Definition at line 246 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF

Definition at line 248 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF

Definition at line 249 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF

Definition at line 242 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF

Definition at line 241 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_SCR_ITSF RTC_SCR_CITSF

Definition at line 237 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_SCR_TSF RTC_SCR_CTSF

Definition at line 239 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF

Definition at line 238 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF

Definition at line 240 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
RTC Exported Constants

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions. More...

Defines

#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Detailed Description

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

Define Documentation

#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Definition at line 263 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE

Definition at line 262 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_CR_TSIE RTC_CR_TSIE

Definition at line 260 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_CR_WUTIE RTC_CR_WUTIE

Definition at line 261 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: WEEK DAY

Defines
WEEK DAY
RTC Exported Constants

Defines

#define | LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Define Documentation

#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)

Friday

Definition at line 275 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)

Monday

Definition at line 271 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)

Saturday

Definition at line 276 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Sunday

Definition at line 277 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)

Thursday

Definition at line 274 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)

Tuesday

Definition at line 272 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)

Wednesday

Definition at line 273 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: MONTH

Defines
MONTH
RTC Exported Constants

Defines

#define | LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | LL_RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | LL_RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | LL_RTC_MONTH_MAY ((uint8_t)0x05U)
#define | LL_RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | LL_RTC_MONTH_JULY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Define Documentation

#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U)

April

Definition at line 288 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)

August

Definition at line 292 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)

December

Definition at line 296 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)

February

Definition at line 286 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)

January

Definition at line 285 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_MONTH_JULY ((uint8_t)0x07U)

July

Definition at line 291 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U)

June

Definition at line 290 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U)

March

Definition at line 287 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_MAY ((uint8_t)0x05U)

May

Definition at line 289 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)

November

Definition at line 295 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)

October

Definition at line 294 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)

September

Definition at line 293 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HOUR FORMAT

Defines
HOUR FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

Define Documentation

#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U

24 hour/day format

Definition at line 304 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_StructInit(), and LL_RTC_TIME_Init().

#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

AM/PM hour format

Definition at line 305 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ALARM OUTPUT

Defines
ALARM OUTPUT
RTC Exported Constants

Defines

#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Define Documentation

#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0

Alarm A output enabled

Definition at line 314 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1

Alarm B output enabled

Definition at line 315 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_DISABLE 0x00000000U

Output disabled

Definition at line 313 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Wakeup output enabled

Definition at line 316 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ALARM OUTPUT TYPE

Defines
ALARM OUTPUT TYPE
RTC Exported Constants

Defines

#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U

Define Documentation

#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE

RTC_ALARM is open-drain output

Definition at line 324 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U

RTC_ALARM is push-pull output

Definition at line 325 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: OUTPUT POLARITY PIN

Defines
OUTPUT POLARITY PIN
RTC Exported Constants

Defines

#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Define Documentation

#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U

Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 333 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 334 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIME FORMAT

Defines
TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM

Define Documentation

#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U

AM or 24-hour format

Definition at line 342 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_TIME_StructInit().

#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM

PM

Definition at line 343 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SHIFT SECOND

Defines
SHIFT SECOND
RTC Exported Constants

Defines

#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Define Documentation

#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Definition at line 352 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */

Definition at line 351 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ALARMA MASK

Defines
ALARMA MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Define Documentation

#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Masks all

Definition at line 365 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Date/day do not care in Alarm A comparison

Definition at line 361 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3

Hours do not care in Alarm A comparison

Definition at line 362 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2

Minutes do not care in Alarm A comparison

Definition at line 363 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_NONE 0x00000000U

No masks applied on Alarm A

Definition at line 360 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1

Seconds do not care in Alarm A comparison

Definition at line 364 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: ALARMA TIME FORMAT

Defines
ALARMA TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

Define Documentation

#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 373 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

PM

Definition at line 374 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: ALARMB MASK

Defines
ALARMB MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Define Documentation

#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Masks all

Definition at line 387 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4

Date/day do not care in Alarm B comparison

Definition at line 383 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3

Hours do not care in Alarm B comparison

Definition at line 384 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2

Minutes do not care in Alarm B comparison

Definition at line 385 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_NONE 0x00000000U

No masks applied on Alarm B

Definition at line 382 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1

Seconds do not care in Alarm B comparison

Definition at line 386 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: ALARMB TIME FORMAT

Defines
ALARMB TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

Define Documentation

#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 395 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

PM

Definition at line 396 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TIMESTAMP EDGE

Defines
TIMESTAMP EDGE
RTC Exported Constants

Defines

#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

RTC_TS input falling edge generates a time-stamp even

Definition at line 405 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U

RTC_TS input rising edge generates a time-stamp event

Definition at line 404 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TIMESTAMP TIME FORMAT

Defines
TIMESTAMP TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

Define Documentation

#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 413 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

PM

Definition at line 414 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TAMPER

Defines
TAMPER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E

Define Documentation

#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E

Tamper 1 input detection

Definition at line 422 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E

Tamper 2 input detection

Definition at line 423 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E

Tamper 3 input detection

Definition at line 425 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TAMPER MASK

Defines
TAMPER MASK
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK
#define | LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK
#define | LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK

Define Documentation

#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK

Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased

Definition at line 434 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK

Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 435 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK

Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 437 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TAMPER NO ERASE

Defines
TAMPER NO ERASE
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE

Define Documentation

#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE

Tamper 1 event does not erase the backup registers.

Definition at line 446 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE

Tamper 2 event does not erase the backup registers.

Definition at line 447 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE

Tamper 3 event does not erase the backup registers.

Definition at line 449 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TAMPER DURATION

Defines
TAMPER DURATION
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH

Define Documentation

#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 458 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 459 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 460 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 461 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TAMPER FILTER

Defines
TAMPER FILTER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Define Documentation

#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 470 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 471 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 472 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 469 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TAMPER SAMPLING FREQUENCY DIVIDER

Defines
TAMPER SAMPLING FREQUENCY DIVIDER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ

Define Documentation

#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 485 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 481 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 484 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 487 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 480 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 483 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 486 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 482 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: TAMPER ACTIVE LEVEL

Defines
TAMPER ACTIVE LEVEL
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG

Define Documentation

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG

Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 495 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG

Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 496 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG

Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 498 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: INTERNAL TAMPER

Defines
INTERNAL TAMPER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E
#define | LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E
#define | LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E
#define | LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E

Define Documentation

#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E

Internal tamper 3: LSE monitoring

Definition at line 508 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E

Internal tamper 4: HSE monitoring

Definition at line 509 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E

Internal tamper 5: RTC calendar overflow

Definition at line 510 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E

Internal tamper 6: Test mode entry

Definition at line 511 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: BACKUP

Defines
BACKUP
RTC Exported Constants

Defines

#define | LL_RTC_BKP_DR0 0x00000000U
#define | LL_RTC_BKP_DR1 0x00000001U
#define | LL_RTC_BKP_DR2 0x00000002U
#define | LL_RTC_BKP_DR3 0x00000003U
#define | LL_RTC_BKP_DR4 0x00000004U

Define Documentation

#define LL_RTC_BKP_DR0 0x00000000U

Definition at line 519 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_BKP_DR1 0x00000001U

Definition at line 520 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_BKP_DR2 0x00000002U

Definition at line 521 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_BKP_DR3 0x00000003U

Definition at line 522 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_BKP_DR4 0x00000004U

Definition at line 523 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: WAKEUP CLOCK DIV

Defines
WAKEUP CLOCK DIV
RTC Exported Constants

Defines

#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
#define | LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

Define Documentation

#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2

ck_spre (usually 1 Hz) clock is selected

Definition at line 535 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value

Definition at line 536 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U

RTC/16 clock is selected

Definition at line 531 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)

RTC/2 clock is selected

Definition at line 534 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1

RTC/4 clock is selected

Definition at line 533 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0

RTC/8 clock is selected

Definition at line 532 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: Calibration output

Defines
Calibration output
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE

Define Documentation

#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)

Calibration output is 1 Hz

Definition at line 545 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE

Calibration output is 512 Hz

Definition at line 546 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U

Calibration output disabled

Definition at line 544 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: Calibration pulse insertion

Defines
Calibration pulse insertion
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

Define Documentation

#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U

No RTCCLK pulses are added

Definition at line 554 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm)

Definition at line 555 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Calibration period

Defines
Calibration period
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16

Use a 16-second calibration cycle period

Definition at line 564 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U

Use a 32-second calibration cycle period

Definition at line 563 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Use a 8-second calibration cycle period

Definition at line 565 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RTC Exported Macros

Defines

#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RTC register.

Define Documentation

#define LL_RTC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 598 of file stm32g0xx_ll_rtc.h.

#define LL_RTC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 590 of file stm32g0xx_ll_rtc.h.

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STM32G0C1xx HAL User Manual: Convert helper Macros

Defines
Convert helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))
Helper macro to convert a value from BCD format to 2 digit decimal format.

Define Documentation

#define __LL_RTC_CONVERT_BCD2BIN ( __VALUE__ ) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))

Helper macro to convert a value from BCD format to 2 digit decimal format.

Parameters:
__VALUE__ BCD value to be converted
Return values:
Converted byte

Definition at line 619 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define __LL_RTC_CONVERT_BIN2BCD ( __VALUE__ ) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))

Helper macro to convert a value from 2 digit decimal format to BCD format.

Parameters:
__VALUE__ Byte to be converted
Return values:
Converted byte

Definition at line 612 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Date helper Macros

Defines
Date helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.

Define Documentation

#define __LL_RTC_GET_DAY ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)

Helper macro to retrieve Day in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Day in BCD format (0x01 . . . 0x31)

Definition at line 674 of file stm32g0xx_ll_rtc.h.

#define __LL_RTC_GET_MONTH ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)

Helper macro to retrieve Month in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 667 of file stm32g0xx_ll_rtc.h.

#define __LL_RTC_GET_WEEKDAY ( __RTC_DATE__ ) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)

Helper macro to retrieve weekday.

Parameters:
__RTC_DATE__ Date returned by LL_RTC_DATE_Get function.
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 641 of file stm32g0xx_ll_rtc.h.

#define __LL_RTC_GET_YEAR ( __RTC_DATE__ ) ((__RTC_DATE__) & 0x000000FFU)

Helper macro to retrieve Year in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Year in BCD format (0x00 . . . 0x99)

Definition at line 648 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Time helper Macros

Defines
Time helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Define Documentation

#define __LL_RTC_GET_HOUR ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)

Helper macro to retrieve hour in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)

Definition at line 689 of file stm32g0xx_ll_rtc.h.

#define __LL_RTC_GET_MINUTE ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)

Helper macro to retrieve minute in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Minutes in BCD format (0x00. . .0x59)

Definition at line 696 of file stm32g0xx_ll_rtc.h.

#define __LL_RTC_GET_SECOND ( __RTC_TIME__ ) ((__RTC_TIME__) & 0x000000FFU)

Helper macro to retrieve second in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Seconds in format (0x00. . .0x59)

Definition at line 703 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableTamperOutput (RTC_TypeDef *RTCx)
Enable tamper output.
__STATIC_INLINE void | LL_RTC_DisableTamperOutput (RTC_TypeDef *RTCx)
Disable tamper output.
__STATIC_INLINE uint32_t | LL_RTC_IsTamperOutputEnabled (RTC_TypeDef *RTCx)
Check if tamper output is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableAlarmPullUp (RTC_TypeDef *RTCx)
Enable internal pull-up in output mode.
__STATIC_INLINE void | LL_RTC_DisableAlarmPullUp (RTC_TypeDef *RTCx)
Disable internal pull-up in output mode.
__STATIC_INLINE uint32_t | LL_RTC_IsAlarmPullUpEnabled (RTC_TypeDef *RTCx)
Check if internal pull-up in output mode is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableOutput2 (RTC_TypeDef *RTCx)
Enable RTC_OUT2 output.
__STATIC_INLINE void | LL_RTC_DisableOutput2 (RTC_TypeDef *RTCx)
Disable RTC_OUT2 output.
__STATIC_INLINE uint32_t | LL_RTC_IsOutput2Enabled (RTC_TypeDef *RTCx)
Check if RTC_OUT2 output is enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableAlarmPullUp ( RTC_TypeDef * RTCx )

Disable internal pull-up in output mode.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1046 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableInitMode ( RTC_TypeDef * RTCx )

Disable initialization mode (Free running mode)

Reference Manual to LL API cross reference:
RTC_ICSR INIT LL_RTC_DisableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 831 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_ExitInitMode(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_DisableOutput2 ( RTC_TypeDef * RTCx )

Disable RTC_OUT2 output.

Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_DisableOutput2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1082 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableRefClock ( RTC_TypeDef * RTCx )

Disable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR REFCKON LL_RTC_DisableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 920 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableShadowRegBypass ( RTC_TypeDef * RTCx )

Disable Bypass the shadow registers.

Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 883 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableTamperOutput ( RTC_TypeDef * RTCx )

Disable tamper output.

Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_DisableTamperOutput
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1013 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableWriteProtection ( RTC_TypeDef * RTCx )

Disable the write protection for RTC registers.

Reference Manual to LL API cross reference:
RTC_WPR KEY LL_RTC_DisableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 988 of file stm32g0xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_ENABLE_1, and RTC_WRITE_PROTECTION_ENABLE_2.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_EnableAlarmPullUp ( RTC_TypeDef * RTCx )

Enable internal pull-up in output mode.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1035 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableInitMode ( RTC_TypeDef * RTCx )

Enable initialization mode.

Note:
Initialization mode is used to program time and date register (RTC_TR and RTC_DR) and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Reference Manual to LL API cross reference:
RTC_ICSR INIT LL_RTC_EnableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 819 of file stm32g0xx_ll_rtc.h.

References RTC_LL_INIT_MASK.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE void LL_RTC_EnableOutput2 ( RTC_TypeDef * RTCx )

Enable RTC_OUT2 output.

Note:
RTC_OUT2 mapping depends on both OSEL (LL_RTC_SetAlarmOutEvent) and COE (LL_RTC_CAL_SetOutputFreq) settings.
RTC_OUT2 is not available ins VBAT mode.
Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_EnableOutput2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1071 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableRefClock ( RTC_TypeDef * RTCx )

Enable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR REFCKON LL_RTC_EnableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 907 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableShadowRegBypass ( RTC_TypeDef * RTCx )

Enable Bypass the shadow registers.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 872 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableTamperOutput ( RTC_TypeDef * RTCx )

Enable tamper output.

Note:
When the tamper output is enabled, all external and internal tamper flags are ORed and routed to the TAMPALRM output.
Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_EnableTamperOutput
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1002 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableWriteProtection ( RTC_TypeDef * RTCx )

Enable the write protection for RTC registers.

Reference Manual to LL API cross reference:
RTC_WPR KEY LL_RTC_EnableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 977 of file stm32g0xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_DISABLE.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent ( RTC_TypeDef * RTCx )

Get the flag to be routed to RTC_ALARM output.

Reference Manual to LL API cross reference:
RTC_CR OSEL LL_RTC_GetAlarmOutEvent
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP

Definition at line 778 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType ( RTC_TypeDef * RTCx )

Get RTC_ALARM output type (ALARM in push-pull or open-drain output)

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

Definition at line 805 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler ( RTC_TypeDef * RTCx )

Get Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7F

Definition at line 955 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetHourFormat ( RTC_TypeDef * RTCx )

Get Hours format (24 hour/day or AM/PM hour format)

Reference Manual to LL API cross reference:
RTC_CR FMT LL_RTC_GetHourFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM

Definition at line 746 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity ( RTC_TypeDef * RTCx )

Get Output polarity.

Reference Manual to LL API cross reference:
RTC_CR POL LL_RTC_GetOutputPolarity
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW

Definition at line 860 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler ( RTC_TypeDef * RTCx )

Get Synchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7FFF

Definition at line 966 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled ( RTC_TypeDef * RTCx )

Check if internal pull-up in output mode is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1057 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled ( RTC_TypeDef * RTCx )

Check if RTC_OUT2 output is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR OUT2EN LL_RTC_IsOutput2Enabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1093 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled ( RTC_TypeDef * RTCx )

Check if Shadow registers bypass is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 894 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled ( RTC_TypeDef * RTCx )

Check if tamper output is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1024 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutEvent | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AlarmOutput
 | ) |  |

Select the flag to be routed to RTC_ALARM output.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR OSEL LL_RTC_SetAlarmOutEvent
Parameters:
RTCx RTC Instance
AlarmOutput This parameter can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP
Return values:
None

Definition at line 763 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutputType | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Output
 | ) |  |

Set RTC_ALARM output type (ALARM in push-pull or open-drain output)

Reference Manual to LL API cross reference:
RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Output This parameter can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
Return values:
None

Definition at line 792 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAsynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AsynchPrescaler
 | ) |  |

Set Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler
Parameters:
RTCx | RTC Instance
AsynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7F
Return values:
None

Definition at line 932 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetHourFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | HourFormat
 | ) |  |

Set Hours format (24 hour/day or AM/PM hour format)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_CR FMT LL_RTC_SetHourFormat
Parameters:
RTCx RTC Instance
HourFormat This parameter can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM
Return values:
None

Definition at line 733 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetOutputPolarity | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Polarity
 | ) |  |

Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR POL LL_RTC_SetOutputPolarity
Parameters:
RTCx RTC Instance
Polarity This parameter can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW
Return values:
None

Definition at line 847 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetSynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SynchPrescaler
 | ) |  |

Set Synchronous prescaler factor.

Reference Manual to LL API cross reference:
RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler
Parameters:
RTCx | RTC Instance
SynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7FFF
Return values:
None

Definition at line 944 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Time

Functions
Time
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.

Function Documentation

__STATIC_INLINE void LL_RTC_TIME_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set time (hour, minute and second) in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
TimeFormat and Hours should follow the same format
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_Config
RTC_TR HT LL_RTC_TIME_Config
RTC_TR HU LL_RTC_TIME_Config
RTC_TR MNT LL_RTC_TIME_Config
RTC_TR MNU LL_RTC_TIME_Config
RTC_TR ST LL_RTC_TIME_Config
RTC_TR SU LL_RTC_TIME_Config
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1265 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_TIME_DecHour ( RTC_TypeDef * RTCx )

Subtract 1 hour (winter time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR SUB1H LL_RTC_TIME_DecHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1345 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore ( RTC_TypeDef * RTCx )

Disable memorization whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_DisableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1322 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore ( RTC_TypeDef * RTCx )

Memorize whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_EnableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1310 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_Get ( RTC_TypeDef * RTCx )

Get time (hour, minute and second) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_Get
RTC_TR HU LL_RTC_TIME_Get
RTC_TR MNT LL_RTC_TIME_Get
RTC_TR MNU LL_RTC_TIME_Get
RTC_TR ST LL_RTC_TIME_Get
RTC_TR SU LL_RTC_TIME_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds (Format: 0x00HHMMSS).

Definition at line 1293 of file stm32g0xx_ll_rtc.h.

References RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat ( RTC_TypeDef * RTCx )

Get time format (AM or PM notation)

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_GetFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM

Definition at line 1134 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour ( RTC_TypeDef * RTCx )

Get Hours in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_GetHour
RTC_TR HU LL_RTC_TIME_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1169 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute ( RTC_TypeDef * RTCx )

Get Minutes in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR MNT LL_RTC_TIME_GetMinute
RTC_TR MNU LL_RTC_TIME_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1204 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond ( RTC_TypeDef * RTCx )

Get Seconds in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TR ST LL_RTC_TIME_GetSecond
RTC_TR SU LL_RTC_TIME_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1239 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond ( RTC_TypeDef * RTCx )

Get Sub second value in the synchronous prescaler counter.

Note:
You can use both SubSeconds value and SecondFraction (PREDIV_S through LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar SubSeconds value in second fraction ratio with time unit following generic formula: ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS.
Reference Manual to LL API cross reference:
RTC_SSR SS LL_RTC_TIME_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Sub second value (number between 0 and 65535)

Definition at line 1375 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_IncHour ( RTC_TypeDef * RTCx )

Add 1 hour (summer time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ADD1H LL_RTC_TIME_IncHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1357 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled ( RTC_TypeDef * RTCx )

Check if RTC Day Light Saving stored operation has been enabled or not.

Reference Manual to LL API cross reference:
RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1333 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set time format (AM/24-hour or PM notation)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
RTC_TR PM LL_RTC_TIME_SetFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Return values:
None

Definition at line 1117 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set Hours in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR HT LL_RTC_TIME_SetHour
RTC_TR HU LL_RTC_TIME_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1150 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set Minutes in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR MNT LL_RTC_TIME_SetMinute
RTC_TR MNU LL_RTC_TIME_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1185 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set Seconds in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_TR ST LL_RTC_TIME_SetSecond
RTC_TR SU LL_RTC_TIME_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1220 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_Synchronize | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | ShiftSecond,
 |  | uint32_t | Fraction
 | ) |  |

Synchronize to a remote clock with a high degree of precision.

Note:
This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
When REFCKON is set, firmware must not write to Shift control register.
Reference Manual to LL API cross reference:
RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize
RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize
Parameters:
RTCx | RTC Instance
ShiftSecond This parameter can be one of the following values:
  • LL_RTC_SHIFT_SECOND_DELAY
  • LL_RTC_SHIFT_SECOND_ADVANCE
Fraction | Number of Seconds Fractions (any value from 0 to 0x7FFF)
Return values:
None

Definition at line 1394 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Date

Functions
Date
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.

Function Documentation

__STATIC_INLINE void LL_RTC_DATE_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay,
 |  | uint32_t | Day,
 |  | uint32_t | Month,
 |  | uint32_t | Year
 | ) |  |

Set date (WeekDay, Day, Month and Year) in BCD format.

Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_Config
RTC_DR MT LL_RTC_DATE_Config
RTC_DR MU LL_RTC_DATE_Config
RTC_DR DT LL_RTC_DATE_Config
RTC_DR DU LL_RTC_DATE_Config
RTC_DR YT LL_RTC_DATE_Config
RTC_DR YU LL_RTC_DATE_Config
Parameters:
RTCx | RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Day | Value between Min_Data=0x01 and Max_Data=0x31
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1595 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init().

__STATIC_INLINE uint32_t LL_RTC_DATE_Get ( RTC_TypeDef * RTCx )

Get date (WeekDay, Day, Month and Year) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_Get
RTC_DR MT LL_RTC_DATE_Get
RTC_DR MU LL_RTC_DATE_Get
RTC_DR DT LL_RTC_DATE_Get
RTC_DR DU LL_RTC_DATE_Get
RTC_DR YT LL_RTC_DATE_Get
RTC_DR YU LL_RTC_DATE_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).

Definition at line 1623 of file stm32g0xx_ll_rtc.h.

References RTC_OFFSET_DAY, RTC_OFFSET_MONTH, and RTC_OFFSET_WEEKDAY.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay ( RTC_TypeDef * RTCx )

Get Day in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR DT LL_RTC_DATE_GetDay
RTC_DR DU LL_RTC_DATE_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1555 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth ( RTC_TypeDef * RTCx )

Get Month in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR MT LL_RTC_DATE_GetMonth
RTC_DR MU LL_RTC_DATE_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 1525 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay ( RTC_TypeDef * RTCx )

Get Week day.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1471 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear ( RTC_TypeDef * RTCx )

Get Year in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_DR YT LL_RTC_DATE_GetYear
RTC_DR YU LL_RTC_DATE_GetYear
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x99

Definition at line 1432 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR DT LL_RTC_DATE_SetDay
RTC_DR DU LL_RTC_DATE_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1539 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetMonth | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Month
 | ) |  |

Set Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR MT LL_RTC_DATE_SetMonth
RTC_DR MU LL_RTC_DATE_SetMonth
Parameters:
RTCx RTC Instance
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Return values:
None

Definition at line 1497 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set Week day.

Reference Manual to LL API cross reference:
RTC_DR WDU LL_RTC_DATE_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1451 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetYear | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Year
 | ) |  |

Set Year in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
Reference Manual to LL API cross reference:
RTC_DR YT LL_RTC_DATE_SetYear
RTC_DR YU LL_RTC_DATE_SetYear
Parameters:
RTCx | RTC Instance
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1416 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ALARMA

Functions
ALARMA
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMA_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm A Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime
RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime
RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime
RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime
RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime
RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime
RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1923 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Disable ( RTC_TypeDef * RTCx )

Disable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAE LL_RTC_ALMA_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1661 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmA Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1724 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Enable ( RTC_TypeDef * RTCx )

Enable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAE LL_RTC_ALMA_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1649 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmA Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1713 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay ( RTC_TypeDef * RTCx )

Get ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR DT LL_RTC_ALMA_GetDay
RTC_ALRMAR DU LL_RTC_ALMA_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1752 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour ( RTC_TypeDef * RTCx )

Get ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_GetHour
RTC_ALRMAR HU LL_RTC_ALMA_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1844 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm A masks.

Reference Manual to LL API cross reference:
RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask
RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask
RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask
RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL

Definition at line 1702 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute
RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1872 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMAR ST LL_RTC_ALMA_GetSecond
RTC_ALRMAR SU LL_RTC_ALMA_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1900 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 1995 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm A Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 1972 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_GetTime
RTC_ALRMAR HU LL_RTC_ALMA_GetTime
RTC_ALRMAR MNT LL_RTC_ALMA_GetTime
RTC_ALRMAR MNU LL_RTC_ALMA_GetTime
RTC_ALRMAR ST LL_RTC_ALMA_GetTime
RTC_ALRMAR SU LL_RTC_ALMA_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 1947 of file stm32g0xx_ll_rtc.h.

References LL_RTC_ALMA_GetHour(), LL_RTC_ALMA_GetMinute(), LL_RTC_ALMA_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Alarm A time format (AM or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM

Definition at line 1816 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM A Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1789 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR DT LL_RTC_ALMA_SetDay
RTC_ALRMAR DU LL_RTC_ALMA_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1738 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR HT LL_RTC_ALMA_SetHour
RTC_ALRMAR HU LL_RTC_ALMA_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1830 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm A masks.

Reference Manual to LL API cross reference:
RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask
RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask
RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask
RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL
Return values:
None

Definition at line 1682 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute
RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1858 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMAR ST LL_RTC_ALMA_SetSecond
RTC_ALRMAR SU LL_RTC_ALMA_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1886 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 1984 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm A Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 1961 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set Alarm A time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Return values:
None

Definition at line 1803 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM A Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1771 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ALARMB

Functions
ALARMB
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMB_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm B Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime
RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime
RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime
RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime
RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime
RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime
RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2289 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Disable ( RTC_TypeDef * RTCx )

Disable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBE LL_RTC_ALMB_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2027 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmB Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2090 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Enable ( RTC_TypeDef * RTCx )

Enable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBE LL_RTC_ALMB_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2015 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmB Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2079 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay ( RTC_TypeDef * RTCx )

Get ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR DT LL_RTC_ALMB_GetDay
RTC_ALRMBR DU LL_RTC_ALMB_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2118 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour ( RTC_TypeDef * RTCx )

Get ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_GetHour
RTC_ALRMBR HU LL_RTC_ALMB_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2210 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm B masks.

Reference Manual to LL API cross reference:
RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask
RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask
RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask
RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL

Definition at line 2068 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute
RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2238 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_ALRMBR ST LL_RTC_ALMB_GetSecond
RTC_ALRMBR SU LL_RTC_ALMB_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2266 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2361 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm B Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2338 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_GetTime
RTC_ALRMBR HU LL_RTC_ALMB_GetTime
RTC_ALRMBR MNT LL_RTC_ALMB_GetTime
RTC_ALRMBR MNU LL_RTC_ALMB_GetTime
RTC_ALRMBR ST LL_RTC_ALMB_GetTime
RTC_ALRMBR SU LL_RTC_ALMB_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2313 of file stm32g0xx_ll_rtc.h.

References LL_RTC_ALMB_GetHour(), LL_RTC_ALMB_GetMinute(), LL_RTC_ALMB_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat ( RTC_TypeDef * RTCx )

Get ALARM B time format (AM or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM

Definition at line 2182 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM B Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2155 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR DT LL_RTC_ALMB_SetDay
RTC_ALRMBR DU LL_RTC_ALMB_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 2104 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR HT LL_RTC_ALMB_SetHour
RTC_ALRMBR HU LL_RTC_ALMB_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 2196 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm B masks.

Reference Manual to LL API cross reference:
RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask
RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask
RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask
RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL
Return values:
None

Definition at line 2048 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute
RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2224 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
RTC_ALRMBR ST LL_RTC_ALMB_SetSecond
RTC_ALRMBR SU LL_RTC_ALMB_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2252 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2350 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm B Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2327 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set ALARM B time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Return values:
None

Definition at line 2169 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM B Weekday.

Reference Manual to LL API cross reference:
RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 2137 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Timestamp

Functions
Timestamp
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.

Function Documentation

__STATIC_INLINE void LL_RTC_TS_Disable ( RTC_TypeDef * RTCx )

Disable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSE LL_RTC_TS_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2417 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent ( RTC_TypeDef * RTCx )

Disable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSE LL_RTC_TS_DisableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2393 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableOnTamper ( RTC_TypeDef * RTCx )

Disable timestamp on tamper detection event.

Reference Manual to LL API cross reference:
RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2624 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_Enable ( RTC_TypeDef * RTCx )

Enable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSE LL_RTC_TS_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2405 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent ( RTC_TypeDef * RTCx )

Enable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ITSE LL_RTC_TS_EnableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2381 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableOnTamper ( RTC_TypeDef * RTCx )

Activate timestamp on tamper detection event.

Reference Manual to LL API cross reference:
RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2613 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge ( RTC_TypeDef * RTCx )

Get Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING

Definition at line 2447 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDate ( RTC_TypeDef * RTCx )

Get Timestamp date (WeekDay, Day and Month) in BCD format.

Note:
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TSDR WDU LL_RTC_TS_GetDate
RTC_TSDR MT LL_RTC_TS_GetDate
RTC_TSDR MU LL_RTC_TS_GetDate
RTC_TSDR DT LL_RTC_TS_GetDate
RTC_TSDR DU LL_RTC_TS_GetDate
Parameters:
RTCx RTC Instance
Return values:
Combination of Weekday, Day and Month

Definition at line 2591 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDay ( RTC_TypeDef * RTCx )

Get Timestamp Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSDR DT LL_RTC_TS_GetDay
RTC_TSDR DU LL_RTC_TS_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2574 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetHour ( RTC_TypeDef * RTCx )

Get Timestamp Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR HT LL_RTC_TS_GetHour
RTC_TSTR HU LL_RTC_TS_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2473 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute ( RTC_TypeDef * RTCx )

Get Timestamp Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR MNT LL_RTC_TS_GetMinute
RTC_TSTR MNU LL_RTC_TS_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2486 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth ( RTC_TypeDef * RTCx )

Get Timestamp Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSDR MT LL_RTC_TS_GetMonth
RTC_TSDR MU LL_RTC_TS_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 2561 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond ( RTC_TypeDef * RTCx )

Get Timestamp Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
RTC_TSTR ST LL_RTC_TS_GetSecond
RTC_TSTR SU LL_RTC_TS_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2499 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond ( RTC_TypeDef * RTCx )

Get time-stamp sub second value.

Reference Manual to LL API cross reference:
RTC_TSSSR SS LL_RTC_TS_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 2602 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTime ( RTC_TypeDef * RTCx )

Get Timestamp time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
RTC_TSTR HT LL_RTC_TS_GetTime
RTC_TSTR HU LL_RTC_TS_GetTime
RTC_TSTR MNT LL_RTC_TS_GetTime
RTC_TSTR MNU LL_RTC_TS_GetTime
RTC_TSTR ST LL_RTC_TS_GetTime
RTC_TSTR SU LL_RTC_TS_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2517 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Timestamp AM/PM notation (AM or 24-hour format)

Reference Manual to LL API cross reference:
RTC_TSTR PM LL_RTC_TS_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TS_TIME_FORMAT_AM
  • LL_RTC_TS_TIME_FORMAT_PM

Definition at line 2460 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay ( RTC_TypeDef * RTCx )

Get Timestamp Week day.

Reference Manual to LL API cross reference:
RTC_TSDR WDU LL_RTC_TS_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2536 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_SetActiveEdge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Edge
 | ) |  |

Set Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
Reference Manual to LL API cross reference:
RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge
Parameters:
RTCx RTC Instance
Edge This parameter can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING
Return values:
None

Definition at line 2433 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Tamper

Functions
Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_Enable (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Clear TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (TAMP_TypeDef *TAMPx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (TAMP_TypeDef *TAMPx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (TAMP_TypeDef *TAMPx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (TAMP_TypeDef *TAMPx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (TAMP_TypeDef *TAMPx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (TAMP_TypeDef *TAMPx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (TAMP_TypeDef *TAMPx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (TAMP_TypeDef *TAMPx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (TAMP_TypeDef *TAMPx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Disable Active level for Tamper input.

Function Documentation

__STATIC_INLINE void LL_RTC_TAMPER_Disable | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Clear TAMPx input detection.

Reference Manual to LL API cross reference:
TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable
TAMP_CR1 TAMP2E LL_RTC_TAMPER_Disable
TAMP_CR1 TAMP3E LL_RTC_TAMPER_Disable
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_2 (*)
Return values:
None

Definition at line 2669 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Disable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel
TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel
TAMP_CR2 TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
Return values:
None

Definition at line 2901 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Disable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP
TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP
TAMP_CR2 TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1
  • LL_RTC_TAMPER_NOERASE_TAMPER2
  • LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
Return values:
None

Definition at line 2742 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableMask | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Mask
 | ) |  |

Disable Tamper mask flag.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask
TAMP_CR2 TAMP2MF LL_RTC_TAMPER_DisableMask
TAMP_CR2 TAMP3MF LL_RTC_TAMPER_DisableMask
Parameters:
TAMPx TAMP Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1
  • LL_RTC_TAMPER_MASK_TAMPER2
  • LL_RTC_TAMPER_MASK_TAMPER3 (*)
Return values:
None

Definition at line 2706 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp ( TAMP_TypeDef * TAMPx )

Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 2753 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_Enable | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Enable TAMPx input detection.

Reference Manual to LL API cross reference:
TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable
TAMP_CR1 TAMP2E LL_RTC_TAMPER_Enable
TAMP_CR1 TAMP3E LL_RTC_TAMPER_Enable
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3 (*)
Return values:
None

Definition at line 2651 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Enable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel
TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel
TAMP_CR2 TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
Return values:
None

Definition at line 2883 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Tamper
 | ) |  |

Enable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP
TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP
TAMP_CR2 TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP
Parameters:
TAMPx TAMP Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1
  • LL_RTC_TAMPER_NOERASE_TAMPER2
  • LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
Return values:
None

Definition at line 2724 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableMask | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Mask
 | ) |  |

Enable Tamper mask flag.

Note:
Associated Tamper IT must not enabled when tamper mask is set.
Reference Manual to LL API cross reference:
TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask
TAMP_CR2 TAMP2MF LL_RTC_TAMPER_EnableMask
TAMP_CR2 TAMP3MF LL_RTC_TAMPER_EnableMask
Parameters:
TAMPx TAMP Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1
  • LL_RTC_TAMPER_MASK_TAMPER2
  • LL_RTC_TAMPER_MASK_TAMPER3 (*)
Return values:
None

Definition at line 2688 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp ( TAMP_TypeDef * TAMPx )

Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 2764 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount ( TAMP_TypeDef * TAMPx )

Get RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
Parameters:
TAMPx TAMP Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE

Definition at line 2826 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge ( TAMP_TypeDef * TAMPx )

Get RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
Parameters:
TAMPx TAMP Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK

Definition at line 2795 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq ( TAMP_TypeDef * TAMPx )

Get Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
Parameters:
TAMPx TAMP Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256

Definition at line 2865 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | FilterCount
 | ) |  |

Set RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
Parameters:
TAMPx TAMP Instance
FilterCount This parameter can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE
Return values:
None

Definition at line 2811 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | Duration
 | ) |  |

Set RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
Parameters:
TAMPx TAMP Instance
Duration This parameter can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK
Return values:
None

Definition at line 2780 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | SamplingFreq
 | ) |  |

Set Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
Parameters:
TAMPx TAMP Instance
SamplingFreq This parameter can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256
Return values:
None

Definition at line 2846 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Internal Tamper

Functions
Internal Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_ITAMP_Enable (TAMP_TypeDef *TAMPx, uint32_t InternalTamper)
Enable internal tamper detection.
__STATIC_INLINE void | LL_RTC_TAMPER_ITAMP_Disable (TAMP_TypeDef *TAMPx, uint32_t InternalTamper)
Disable internal tamper detection.

Function Documentation

__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | InternalTamper
 | ) |  |

Disable internal tamper detection.

Reference Manual to LL API cross reference:
TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Disable
TAMP_CR1 ITAMP4E LL_RTC_TAMPER_ITAMP_Disable
TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Disable
TAMP_CR1 ITAMP6E LL_RTC_TAMPER_ITAMP_Disable
Parameters:
TAMPx TAMP Instance
InternalTamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ITAMP3
  • LL_RTC_TAMPER_ITAMP4
  • LL_RTC_TAMPER_ITAMP5
  • LL_RTC_TAMPER_ITAMP6
Return values:
None

Definition at line 2949 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | InternalTamper
 | ) |  |

Enable internal tamper detection.

Reference Manual to LL API cross reference:
TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Enable
TAMP_CR1 ITAMP4E LL_RTC_TAMPER_ITAMP_Enable
TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Enable
TAMP_CR1 ITAMP6E LL_RTC_TAMPER_ITAMP_Enable
Parameters:
TAMPx TAMP Instance
InternalTamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ITAMP3
  • LL_RTC_TAMPER_ITAMP4
  • LL_RTC_TAMPER_ITAMP5
  • LL_RTC_TAMPER_ITAMP6
Return values:
None

Definition at line 2929 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Wakeup

Functions
Wakeup
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.

Function Documentation

__STATIC_INLINE void LL_RTC_WAKEUP_Disable ( RTC_TypeDef * RTCx )

Disable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2982 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_Enable ( RTC_TypeDef * RTCx )

Enable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2970 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload ( RTC_TypeDef * RTCx )

Get Wakeup auto-reload value.

Reference Manual to LL API cross reference:
RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 3054 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock ( RTC_TypeDef * RTCx )

Get Wakeup clock.

Reference Manual to LL API cross reference:
RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT

Definition at line 3030 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled ( RTC_TypeDef * RTCx )

Check if Wakeup timer is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 2993 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Value
 | ) |  |

Set Wakeup auto-reload value.

Note:
Bit can be written only when WUTWF is set to 1
Reference Manual to LL API cross reference:
RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload
Parameters:
RTCx | RTC Instance
Value | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 3043 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetClock | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WakeupClock
 | ) |  |

Select Wakeup clock.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when WUTE bit = 0 and WUTWF bit = 1
Reference Manual to LL API cross reference:
RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock
Parameters:
RTCx RTC Instance
WakeupClock This parameter can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
Return values:
None

Definition at line 3013 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Backup_Registers

Functions
Backup_Registers
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_BKP_SetRegister (TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BKP_GetRegister (TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Reference Manual to LL API cross reference:
TAMP_BKPxR BKP LL_RTC_BKP_GetRegister
Parameters:
TAMPx RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3
  • LL_RTC_BKP_DR4
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

Definition at line 3102 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_BKP_SetRegister | ( | TAMP_TypeDef * | TAMPx,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified Backup data register.

Reference Manual to LL API cross reference:
TAMP_BKPxR BKP LL_RTC_BKP_SetRegister
Parameters:
TAMPx | RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3
  • LL_RTC_BKP_DR4
Data | Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 3080 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Calibration

Functions
Calibration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus ( RTC_TypeDef * RTCx )

Get Calibration minus.

Reference Manual to LL API cross reference:
RTC_CALR CALM LL_RTC_CAL_GetMinus
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data= 0x1FF

Definition at line 3232 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq ( RTC_TypeDef * RTCx )

Get Calibration output frequency (1 Hz or 512 Hz)

Reference Manual to LL API cross reference:
RTC_CR COE LL_RTC_CAL_GetOutputFreq
RTC_CR COSEL LL_RTC_CAL_GetOutputFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ

Definition at line 3147 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod ( RTC_TypeDef * RTCx )

Get the calibration cycle period.

Reference Manual to LL API cross reference:
RTC_CALR CALW8 LL_RTC_CAL_GetPeriod
RTC_CALR CALW16 LL_RTC_CAL_GetPeriod
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC

Definition at line 3207 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted ( RTC_TypeDef * RTCx )

Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)

Reference Manual to LL API cross reference:
RTC_CALR CALP LL_RTC_CAL_IsPulseInserted
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3174 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetMinus | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | CalibMinus
 | ) |  |

Set Calibration minus.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0
Reference Manual to LL API cross reference:
RTC_CALR CALM LL_RTC_CAL_SetMinus
Parameters:
RTCx | RTC Instance
CalibMinus | Value between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 3221 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Frequency
 | ) |  |

Set Calibration output frequency (1 Hz or 512 Hz)

Note:
Bits are write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR COE LL_RTC_CAL_SetOutputFreq
RTC_CR COSEL LL_RTC_CAL_SetOutputFreq
Parameters:
RTCx RTC Instance
Frequency This parameter can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ
Return values:
None

Definition at line 3132 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPeriod | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Period
 | ) |  |

Set the calibration cycle period.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0
Reference Manual to LL API cross reference:
RTC_CALR CALW8 LL_RTC_CAL_SetPeriod
RTC_CALR CALW16 LL_RTC_CAL_SetPeriod
Parameters:
RTCx RTC Instance
Period This parameter can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC
Return values:
None

Definition at line 3192 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPulse | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Pulse
 | ) |  |

Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0
Reference Manual to LL API cross reference:
RTC_CALR CALP LL_RTC_CAL_SetPulse
Parameters:
RTCx RTC Instance
Pulse This parameter can be one of the following values:
  • LL_RTC_CALIB_INSERTPULSE_NONE
  • LL_RTC_CALIB_INSERTPULSE_SET
Return values:
None

Definition at line 3163 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
RTC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAM (RTC_TypeDef *RTCx)
Get Alarm A masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBM (RTC_TypeDef *RTCx)
Get Alarm B masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTM (RTC_TypeDef *RTCx)
Get Wakeup timer masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSM (RTC_TypeDef *RTCx)
Get Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOVM (RTC_TypeDef *RTCx)
Get Time-stamp overflow masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITSM (RTC_TypeDef *RTCx)
Get Internal Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (TAMP_TypeDef *TAMPx)
Get tamper 1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (TAMP_TypeDef *TAMPx)
Get tamper 2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (TAMP_TypeDef *TAMPx)
Get tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP3 (TAMP_TypeDef *TAMPx)
Get internal tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP4 (TAMP_TypeDef *TAMPx)
Get internal tamper 4 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP5 (TAMP_TypeDef *TAMPx)
Get internal tamper 5 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP6 (TAMP_TypeDef *TAMPx)
Get internal tamper 6 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1M (TAMP_TypeDef *TAMPx)
Get tamper 1 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2M (TAMP_TypeDef *TAMPx)
Get tamper 2 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3M (TAMP_TypeDef *TAMPx)
Get tamper 3 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP3M (TAMP_TypeDef *TAMPx)
Get internal tamper 3 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP4M (TAMP_TypeDef *TAMPx)
Get internal tamper 4 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP5M (TAMP_TypeDef *TAMPx)
Get internal tamper 5 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP6M (TAMP_TypeDef *TAMPx)
Get internal tamper 6 interrupt masked flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (TAMP_TypeDef *TAMPx)
Clear tamper 1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (TAMP_TypeDef *TAMPx)
Clear tamper 2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (TAMP_TypeDef *TAMPx)
Clear tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP3 (TAMP_TypeDef *TAMPx)
Clear internal tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP4 (TAMP_TypeDef *TAMPx)
Clear internal tamper 4 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP5 (TAMP_TypeDef *TAMPx)
Clear internal tamper 5 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP6 (TAMP_TypeDef *TAMPx)
Clear internal tamper 6 detection flag.

Function Documentation

__STATIC_INLINE void LL_RTC_ClearFlag_ALRA ( RTC_TypeDef * RTCx )

Clear Alarm A flag.

Reference Manual to LL API cross reference:
RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3383 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ALRB ( RTC_TypeDef * RTCx )

Clear Alarm B flag.

Reference Manual to LL API cross reference:
RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3372 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3 ( TAMP_TypeDef * TAMPx )

Clear internal tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3742 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4 ( TAMP_TypeDef * TAMPx )

Clear internal tamper 4 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CITAMP4F LL_RTC_ClearFlag_ITAMP4
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3753 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5 ( TAMP_TypeDef * TAMPx )

Clear internal tamper 5 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3764 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6 ( TAMP_TypeDef * TAMPx )

Clear internal tamper 6 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CITAMP6F LL_RTC_ClearFlag_ITAMP6
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3775 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITS ( RTC_TypeDef * RTCx )

Clear Internal Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SCR CITSF LL_RTC_ClearFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3328 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_RS ( RTC_TypeDef * RTCx )

Clear Registers synchronization flag.

Reference Manual to LL API cross reference:
RTC_ICSR RSF LL_RTC_ClearFlag_RS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3416 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1 ( TAMP_TypeDef * TAMPx )

Clear tamper 1 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3707 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2 ( TAMP_TypeDef * TAMPx )

Clear tamper 2 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3718 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3 ( TAMP_TypeDef * TAMPx )

Clear tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3730 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TS ( RTC_TypeDef * RTCx )

Clear Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SCR CTSF LL_RTC_ClearFlag_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3350 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TSOV ( RTC_TypeDef * RTCx )

Clear Time-stamp overflow flag.

Reference Manual to LL API cross reference:
RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3339 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_WUT ( RTC_TypeDef * RTCx )

Clear Wakeup timer flag.

Reference Manual to LL API cross reference:
RTC_SCR CWUTF LL_RTC_ClearFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3361 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA ( RTC_TypeDef * RTCx )

Get Alarm A flag.

Reference Manual to LL API cross reference:
RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3317 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM ( RTC_TypeDef * RTCx )

Get Alarm A masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3482 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW ( RTC_TypeDef * RTCx )

Get Alarm A write flag.

Reference Manual to LL API cross reference:
RTC_ICSR ALRAWF LL_RTC_IsActiveFlag_ALRAW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3471 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB ( RTC_TypeDef * RTCx )

Get Alarm B flag.

Reference Manual to LL API cross reference:
RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3306 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM ( RTC_TypeDef * RTCx )

Get Alarm B masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3493 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW ( RTC_TypeDef * RTCx )

Get Alarm B write flag.

Reference Manual to LL API cross reference:
RTC_ICSR ALRBWF LL_RTC_IsActiveFlag_ALRBW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3460 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT ( RTC_TypeDef * RTCx )

Get Initialization flag.

Reference Manual to LL API cross reference:
RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3394 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS ( RTC_TypeDef * RTCx )

Get Initialization status flag.

Reference Manual to LL API cross reference:
RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3427 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3 ( TAMP_TypeDef * TAMPx )

Get internal tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3582 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M ( TAMP_TypeDef * TAMPx )

Get internal tamper 3 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3662 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4 ( TAMP_TypeDef * TAMPx )

Get internal tamper 4 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP4
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3593 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M ( TAMP_TypeDef * TAMPx )

Get internal tamper 4 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR ITAMP4MF LL_RTC_IsActiveFlag_ITAMP4M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3673 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5 ( TAMP_TypeDef * TAMPx )

Get internal tamper 5 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3604 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M ( TAMP_TypeDef * TAMPx )

Get internal tamper 5 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3684 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6 ( TAMP_TypeDef * TAMPx )

Get internal tamper 6 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR ITAMP6F LL_RTC_IsActiveFlag_ITAMP6
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3615 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M ( TAMP_TypeDef * TAMPx )

Get internal tamper 6 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR ITAMP6MF LL_RTC_IsActiveFlag_ITAMP6M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3695 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS ( RTC_TypeDef * RTCx )

Get Internal Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SR ITSF LL_RTC_IsActiveFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3251 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM ( RTC_TypeDef * RTCx )

Get Internal Time-stamp masked flag.

Reference Manual to LL API cross reference:
RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3537 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP ( RTC_TypeDef * RTCx )

Get Recalibration pending Flag.

Reference Manual to LL API cross reference:
RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3262 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS ( RTC_TypeDef * RTCx )

Get Registers synchronization flag.

Reference Manual to LL API cross reference:
RTC_ICSR RSF LL_RTC_IsActiveFlag_RS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3405 of file stm32g0xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP ( RTC_TypeDef * RTCx )

Get Shift operation pending flag.

Reference Manual to LL API cross reference:
RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3438 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1 ( TAMP_TypeDef * TAMPx )

Get tamper 1 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3548 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M ( TAMP_TypeDef * TAMPx )

Get tamper 1 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3627 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2 ( TAMP_TypeDef * TAMPx )

Get tamper 2 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3559 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M ( TAMP_TypeDef * TAMPx )

Get tamper 2 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3638 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3 ( TAMP_TypeDef * TAMPx )

Get tamper 3 detection flag.

Reference Manual to LL API cross reference:
TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3571 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M ( TAMP_TypeDef * TAMPx )

Get tamper 3 interrupt masked flag.

Reference Manual to LL API cross reference:
TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 3650 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS ( RTC_TypeDef * RTCx )

Get Time-stamp flag.

Reference Manual to LL API cross reference:
RTC_SR TSF LL_RTC_IsActiveFlag_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3284 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM ( RTC_TypeDef * RTCx )

Get Time-stamp masked flag.

Reference Manual to LL API cross reference:
RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3515 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV ( RTC_TypeDef * RTCx )

Get Time-stamp overflow flag.

Reference Manual to LL API cross reference:
RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3273 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM ( RTC_TypeDef * RTCx )

Get Time-stamp overflow masked flag.

Reference Manual to LL API cross reference:
RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3526 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT ( RTC_TypeDef * RTCx )

Get Wakeup timer flag.

Reference Manual to LL API cross reference:
RTC_SR WUTF LL_RTC_IsActiveFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3295 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM ( RTC_TypeDef * RTCx )

Get Wakeup timer masked flag.

Reference Manual to LL API cross reference:
RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3504 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW ( RTC_TypeDef * RTCx )

Get Wakeup timer write flag.

Reference Manual to LL API cross reference:
RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3449 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT_Management

Functions
IT_Management
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (TAMP_TypeDef *TAMPx)
Enable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (TAMP_TypeDef *TAMPx)
Disable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (TAMP_TypeDef *TAMPx)
Enable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (TAMP_TypeDef *TAMPx)
Disable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (TAMP_TypeDef *TAMPx)
Enable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (TAMP_TypeDef *TAMPx)
Disable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP3 (TAMP_TypeDef *TAMPx)
Enable internal tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP3 (TAMP_TypeDef *TAMPx)
Disable internal tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP4 (TAMP_TypeDef *TAMPx)
Enable internal tamper 4 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP4 (TAMP_TypeDef *TAMPx)
Disable internal tamper 4 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP5 (TAMP_TypeDef *TAMPx)
Enable internal tamper 5 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP5 (TAMP_TypeDef *TAMPx)
Disable internal tamper 5 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP6 (TAMP_TypeDef *TAMPx)
Enable internal tamper 6 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP6 (TAMP_TypeDef *TAMPx)
Disable internal tamper 6 interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (TAMP_TypeDef *TAMPx)
Check if tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (TAMP_TypeDef *TAMPx)
Check if tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (TAMP_TypeDef *TAMPx)
Check if tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP3 (TAMP_TypeDef *TAMPx)
Check if internal tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP4 (TAMP_TypeDef *TAMPx)
Check if internal tamper 4 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP5 (TAMP_TypeDef *TAMPx)
Check if internal tamper 5 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP6 (TAMP_TypeDef *TAMPx)
Check if internal tamper 6 interrupt is enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableIT_ALRA ( RTC_TypeDef * RTCx )

Disable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAIE LL_RTC_DisableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3880 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ALRB ( RTC_TypeDef * RTCx )

Disable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBIE LL_RTC_DisableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3856 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3 ( TAMP_TypeDef * TAMPx )

Disable internal tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP3IE LL_RTC_DisableIT_ITAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4014 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ITAMP4 ( TAMP_TypeDef * TAMPx )

Disable internal tamper 4 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP4IE LL_RTC_DisableIT_ITAMP4
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4036 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5 ( TAMP_TypeDef * TAMPx )

Disable internal tamper 5 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP5IE LL_RTC_DisableIT_ITAMP5
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4058 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6 ( TAMP_TypeDef * TAMPx )

Disable internal tamper 6 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP6IE LL_RTC_DisableIT_ITAMP6
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4080 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP1 ( TAMP_TypeDef * TAMPx )

Disable tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3946 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP2 ( TAMP_TypeDef * TAMPx )

Disable tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3968 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP3 ( TAMP_TypeDef * TAMPx )

Disable tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3991 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TS ( RTC_TypeDef * RTCx )

Disable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSIE LL_RTC_DisableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3808 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_WUT ( RTC_TypeDef * RTCx )

Disable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTIE LL_RTC_DisableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3832 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRA ( RTC_TypeDef * RTCx )

Enable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRAIE LL_RTC_EnableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3868 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRB ( RTC_TypeDef * RTCx )

Enable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR ALRBIE LL_RTC_EnableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3844 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3 ( TAMP_TypeDef * TAMPx )

Enable internal tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4003 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ITAMP4 ( TAMP_TypeDef * TAMPx )

Enable internal tamper 4 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP4IE LL_RTC_EnableIT_ITAMP4
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4025 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5 ( TAMP_TypeDef * TAMPx )

Enable internal tamper 5 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4047 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6 ( TAMP_TypeDef * TAMPx )

Enable internal tamper 6 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP6IE LL_RTC_EnableIT_ITAMP6
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 4069 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP1 ( TAMP_TypeDef * TAMPx )

Enable tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3935 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP2 ( TAMP_TypeDef * TAMPx )

Enable tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3957 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP3 ( TAMP_TypeDef * TAMPx )

Enable tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
None

Definition at line 3980 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TS ( RTC_TypeDef * RTCx )

Enable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR TSIE LL_RTC_EnableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3796 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_WUT ( RTC_TypeDef * RTCx )

Enable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
RTC_CR WUTIE LL_RTC_EnableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3820 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA ( RTC_TypeDef * RTCx )

Check if Alarm A interrupt is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3924 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB ( RTC_TypeDef * RTCx )

Check if Alarm B interrupt is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3913 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3 ( TAMP_TypeDef * TAMPx )

Check if internal tamper 3 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4127 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4 ( TAMP_TypeDef * TAMPx )

Check if internal tamper 4 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP4IE LL_RTC_IsEnabledIT_ITAMP4
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4138 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5 ( TAMP_TypeDef * TAMPx )

Check if internal tamper 5 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4149 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6 ( TAMP_TypeDef * TAMPx )

Check if internal tamper 6 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER ITAMP6IE LL_RTC_IsEnabledIT_ITAMP6
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4160 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1 ( TAMP_TypeDef * TAMPx )

Check if tamper 1 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4092 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2 ( TAMP_TypeDef * TAMPx )

Check if tamper 2 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4103 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3 ( TAMP_TypeDef * TAMPx )

Check if tamper 3 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3
Parameters:
TAMPx TAMP Instance
Return values:
State of bit (1 or 0).

Definition at line 4115 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS ( RTC_TypeDef * RTCx )

Check if Time-stamp interrupt is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR TSIE LL_RTC_IsEnabledIT_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3891 of file stm32g0xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT ( RTC_TypeDef * RTCx )

Check if Wakeup timer interrupt is enabled or not.

Reference Manual to LL API cross reference:
RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3902 of file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Function Documentation

ErrorStatus LL_RTC_ALMA_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm A.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use LL_RTC_ALMA_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMA registers are configured
  • ERROR: ALARMA registers are not configured

Definition at line 447 of file stm32g0xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMA_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_DisableWeekday(), LL_RTC_ALMA_EnableWeekday(), LL_RTC_ALMA_SetDay(), LL_RTC_ALMA_SetMask(), LL_RTC_ALMA_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMA_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 675 of file stm32g0xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_MASK_NONE, LL_RTC_ALMA_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_ALMB_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm B.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (LL_RTC_ALMB_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMB registers are configured
  • ERROR: ALARMB registers are not configured

Definition at line 565 of file stm32g0xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMB_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_DisableWeekday(), LL_RTC_ALMB_EnableWeekday(), LL_RTC_ALMB_SetDay(), LL_RTC_ALMB_SetMask(), LL_RTC_ALMB_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMB_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 697 of file stm32g0xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_MASK_NONE, LL_RTC_ALMB_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_DATE_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Set the RTC current date.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_DateStruct | pointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Day register is configured
  • ERROR: RTC Day register is not configured

Definition at line 357 of file stm32g0xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_DateTypeDef::Day, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_MONTH, IS_LL_RTC_WEEKDAY, IS_LL_RTC_YEAR, LL_RTC_DATE_Config(), LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_WaitForSynchro(), LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

void LL_RTC_DATE_StructInit ( LL_RTC_DateTypeDef * RTC_DateStruct )

Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)

Parameters:
RTC_DateStruct pointer to a LL_RTC_DateTypeDef structure which will be initialized.
Return values:
None

Definition at line 424 of file stm32g0xx_ll_rtc.c.

References LL_RTC_DateTypeDef::Day, LL_RTC_MONTH_JANUARY, LL_RTC_WEEKDAY_MONDAY, LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

ErrorStatus LL_RTC_DeInit ( RTC_TypeDef * RTCx )

De-Initializes the RTC registers to their default reset values.

Note:
This function does not reset the RTC Clock source and RTC Backup Data registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are de-initialized
  • ERROR: RTC registers are not de-initialized

Definition at line 137 of file stm32g0xx_ll_rtc.c.

References assert_param, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_WaitForSynchro(), and RTC_SYNCH_PRESC_DEFAULT.

ErrorStatus LL_RTC_EnterInitMode ( RTC_TypeDef * RTCx )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC is in Init mode
  • ERROR: RTC is not in Init mode

Definition at line 722 of file stm32g0xx_ll_rtc.c.

References assert_param, LL_RTC_EnableInitMode(), LL_RTC_IsActiveFlag_INIT(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_INITMODE_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

ErrorStatus LL_RTC_ExitInitMode ( RTC_TypeDef * RTCx )

Exit the RTC Initialization mode.

Note:
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC exited from in Init mode
  • ERROR: Not applicable

Definition at line 766 of file stm32g0xx_ll_rtc.c.

References assert_param, and LL_RTC_DisableInitMode().

ErrorStatus LL_RTC_Init | ( | RTC_TypeDef * | RTCx,
 |  | LL_RTC_InitTypeDef * | RTC_InitStruct
 | ) |  |

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

Parameters:
RTCx | RTC Instance
RTC_InitStruct | pointer to a LL_RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
Note:
The RTC Prescaler register is write protected and can be written in initialization mode only.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are initialized
  • ERROR: RTC registers are not initialized

Definition at line 195 of file stm32g0xx_ll_rtc.c.

References assert_param, LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, IS_LL_RTC_ASYNCH_PREDIV, IS_LL_RTC_HOURFORMAT, IS_LL_RTC_SYNCH_PREDIV, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_SetAsynchPrescaler(), LL_RTC_SetHourFormat(), LL_RTC_SetSynchPrescaler(), and LL_RTC_InitTypeDef::SynchPrescaler.

void LL_RTC_StructInit ( LL_RTC_InitTypeDef * RTC_InitStruct )

Set each LL_RTC_InitTypeDef field to default value.

Parameters:
RTC_InitStruct pointer to a LL_RTC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 234 of file stm32g0xx_ll_rtc.c.

References LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, LL_RTC_HOURFORMAT_24HOUR, RTC_ASYNCH_PRESC_DEFAULT, RTC_SYNCH_PRESC_DEFAULT, and LL_RTC_InitTypeDef::SynchPrescaler.

ErrorStatus LL_RTC_TIME_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Set the RTC current time.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_TimeStruct | pointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Time register is configured
  • ERROR: RTC Time register is not configured

Definition at line 254 of file stm32g0xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_TIME_Config(), LL_RTC_WaitForSynchro(), LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_TIME_StructInit ( LL_RTC_TimeTypeDef * RTC_TimeStruct )

Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).

Parameters:
RTC_TimeStruct pointer to a LL_RTC_TimeTypeDef structure which will be initialized.
Return values:
None

Definition at line 336 of file stm32g0xx_ll_rtc.c.

References LL_RTC_TimeTypeDef::Hours, LL_RTC_TIME_FORMAT_AM_OR_24, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_WaitForSynchro ( RTC_TypeDef * RTCx )

Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are synchronised
  • ERROR: RTC registers are not synchronised

Definition at line 793 of file stm32g0xx_ll_rtc.c.

References assert_param, LL_RTC_ClearFlag_RS(), LL_RTC_IsActiveFlag_RS(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_SYNCHRO_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), and LL_RTC_TIME_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_CR1_CLEAR_MASK

Define Documentation

#define SPI_CR1_CLEAR_MASK
Value:
(SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
                                            SPI_CR1_BIDIMODE)

Definition at line 49 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Define Documentation

#define IS_LL_SPI_BAUDRATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))

Definition at line 94 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_BITORDER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_LSB_FIRST) \
                                       || ((__VALUE__) == LL_SPI_MSB_FIRST))

Definition at line 103 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRC_POLYNOMIAL ( __VALUE__ ) ((__VALUE__) >= 0x1U)

Definition at line 109 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRCCALCULATION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
                                             || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))

Definition at line 106 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))

Definition at line 70 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_MODE_MASTER) \
                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))

Definition at line 67 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_NSS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_NSS_SOFT)          \
                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))

Definition at line 90 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_PHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_PHASE_1EDGE) \
                                    || ((__VALUE__) == LL_SPI_PHASE_2EDGE))

Definition at line 87 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_POLARITY_LOW) \
                                       || ((__VALUE__) == LL_SPI_POLARITY_HIGH))

Definition at line 84 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_TRANSFER_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
                                                 || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))

Definition at line 62 of file stm32g0xx_ll_spi.c.

Referenced by LL_SPI_Init().

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STM32G0C1xx HAL User Manual: LL_SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SPI_InitTypeDef Struct Reference
SPI Exported Init structure

SPI Init structures definition. More...

#include <stm32g0xx_ll_spi.h>

Data Fields

uint32_t | TransferDirection
uint32_t | Mode
uint32_t | DataWidth
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | NSS
uint32_t | BaudRate
uint32_t | BitOrder
uint32_t | CRCCalculation
uint32_t | CRCPoly

Detailed Description

SPI Init structures definition.

Definition at line 53 of file stm32g0xx_ll_spi.h.

Field Documentation

uint32_t LL_SPI_InitTypeDef::BaudRate

Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of Baud Rate Prescaler.

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

This feature can be modified afterwards using unitary function LL_SPI_SetBaudRatePrescaler().

Definition at line 85 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::BitOrder

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of Transmission Bit Order.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferBitOrder().

Definition at line 91 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of Clock Phase.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPhase().

Definition at line 75 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPolarity

Specifies the serial clock steady state. This parameter can be a value of Clock Polarity.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPolarity().

Definition at line 70 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of CRC Calculation.

This feature can be modified afterwards using unitary functions LL_SPI_EnableCRC() and LL_SPI_DisableCRC().

Definition at line 96 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCPoly

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_SPI_SetCRCPolynomial().

Definition at line 101 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::DataWidth

Specifies the SPI data width. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_SPI_SetDataWidth().

Definition at line 65 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::Mode

Specifies the SPI mode (Master/Slave). This parameter can be a value of Operation Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetMode().

Definition at line 60 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of Slave Select Pin Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetNSSMode().

Definition at line 80 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::TransferDirection

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of Transfer Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferDirection().

Definition at line 55 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_spi.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SPI Exported Constants

Flags defines which can be used with LL_SPI_ReadReg function. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_SPI_ReadReg function.

Define Documentation

#define LL_SPI_SR_BSY SPI_SR_BSY

Busy flag

Definition at line 124 of file stm32g0xx_ll_spi.h.

#define LL_SPI_SR_CRCERR SPI_SR_CRCERR

CRC error flag

Definition at line 125 of file stm32g0xx_ll_spi.h.

#define LL_SPI_SR_FRE SPI_SR_FRE

TI mode frame format error flag

Definition at line 128 of file stm32g0xx_ll_spi.h.

#define LL_SPI_SR_MODF SPI_SR_MODF

Mode fault flag

Definition at line 126 of file stm32g0xx_ll_spi.h.

#define LL_SPI_SR_OVR SPI_SR_OVR

Overrun flag

Definition at line 127 of file stm32g0xx_ll_spi.h.

#define LL_SPI_SR_RXNE SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 122 of file stm32g0xx_ll_spi.h.

#define LL_SPI_SR_TXE SPI_SR_TXE

Tx buffer empty flag

Definition at line 123 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
SPI Exported Constants | I2S Exported Constants

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions. More...

Defines

#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
#define | LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
#define | LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE

Detailed Description

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Define Documentation

#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE

Error interrupt enable

Definition at line 1495 of file stm32g0xx_ll_spi.h.

#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 1493 of file stm32g0xx_ll_spi.h.

#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 1494 of file stm32g0xx_ll_spi.h.

#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Error interrupt enable

Definition at line 139 of file stm32g0xx_ll_spi.h.

#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 137 of file stm32g0xx_ll_spi.h.

#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 138 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Operation Mode

Defines
Operation Mode
SPI Exported Constants

Defines

#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U

Define Documentation

#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Master configuration

Definition at line 147 of file stm32g0xx_ll_spi.h.

#define LL_SPI_MODE_SLAVE 0x00000000U

Slave configuration

Definition at line 148 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Serial Protocol

Defines
Serial Protocol
SPI Exported Constants

Defines

#define | LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

Define Documentation

#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U

Motorola mode. Used as default value

Definition at line 156 of file stm32g0xx_ll_spi.h.

#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

TI mode

Definition at line 157 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Clock Phase

Defines
Clock Phase
SPI Exported Constants

Defines

#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Define Documentation

#define LL_SPI_PHASE_1EDGE 0x00000000U

First clock transition is the first data capture edge

Definition at line 165 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Second clock transition is the first data capture edge

Definition at line 166 of file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
SPI Exported Constants

Defines

#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Define Documentation

#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Clock to 1 when idle

Definition at line 175 of file stm32g0xx_ll_spi.h.

#define LL_SPI_POLARITY_LOW 0x00000000U

Clock to 0 when idle

Definition at line 174 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Baud Rate Prescaler

Defines
Baud Rate Prescaler
SPI Exported Constants

Defines

#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

BaudRate control equal to fPCLK/128

Definition at line 189 of file stm32g0xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/16

Definition at line 186 of file stm32g0xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U

BaudRate control equal to fPCLK/2

Definition at line 183 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/256

Definition at line 190 of file stm32g0xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)

BaudRate control equal to fPCLK/32

Definition at line 187 of file stm32g0xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)

BaudRate control equal to fPCLK/4

Definition at line 184 of file stm32g0xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/64

Definition at line 188 of file stm32g0xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)

BaudRate control equal to fPCLK/8

Definition at line 185 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Transmission Bit Order

Defines
Transmission Bit Order
SPI Exported Constants

Defines

#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U

Define Documentation

#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)

Data is transmitted/received with the LSB first

Definition at line 198 of file stm32g0xx_ll_spi.h.

#define LL_SPI_MSB_FIRST 0x00000000U

Data is transmitted/received with the MSB first

Definition at line 199 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Transfer Mode

Defines
Transfer Mode
SPI Exported Constants

Defines

#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Define Documentation

#define LL_SPI_FULL_DUPLEX 0x00000000U

Full-Duplex mode. Rx and Tx transfer on 2 lines

Definition at line 207 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)

Half-Duplex Rx mode. Rx transfer on 1 line

Definition at line 209 of file stm32g0xx_ll_spi.h.

#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Half-Duplex Tx mode. Tx transfer on 1 line

Definition at line 210 of file stm32g0xx_ll_spi.h.

#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)

Simplex Rx mode. Rx transfer only on 1 line

Definition at line 208 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Slave Select Pin Mode

Defines
Slave Select Pin Mode
SPI Exported Constants

Defines

#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

Define Documentation

#define LL_SPI_NSS_HARD_INPUT 0x00000000U

NSS pin used in Input. Only used in Master mode

Definition at line 219 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

NSS pin used in Output. Only used in Slave mode as chip select

Definition at line 220 of file stm32g0xx_ll_spi.h.

#define LL_SPI_NSS_SOFT (SPI_CR1_SSM)

NSS managed internally. NSS pin not used and free

Definition at line 218 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Datawidth

Defines
Datawidth
SPI Exported Constants

Defines

#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Define Documentation

#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)

Data length for SPI transfer: 10 bits

Definition at line 234 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)

Data length for SPI transfer: 11 bits

Definition at line 235 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 12 bits

Definition at line 236 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)

Data length for SPI transfer: 13 bits

Definition at line 237 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 14 bits

Definition at line 238 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 15 bits

Definition at line 239 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 16 bits

Definition at line 240 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)

Data length for SPI transfer: 4 bits

Definition at line 228 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)

Data length for SPI transfer: 5 bits

Definition at line 229 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 6 bits

Definition at line 230 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 7 bits

Definition at line 231 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 8 bits

Definition at line 232 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)

Data length for SPI transfer: 9 bits

Definition at line 233 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC Calculation

Defines
CRC Calculation
SPI Exported Constants

Defines

#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

Define Documentation

#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U

CRC calculation disabled

Definition at line 249 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

CRC calculation enabled

Definition at line 250 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC Length

Defines
CRC Length
SPI Exported Constants

Defines

#define | LL_SPI_CRC_8BIT 0x00000000U
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

Define Documentation

#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

16-bit CRC length

Definition at line 260 of file stm32g0xx_ll_spi.h.

#define LL_SPI_CRC_8BIT 0x00000000U

8-bit CRC length

Definition at line 259 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: RX FIFO Threshold

Defines
RX FIFO Threshold
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_TH_HALF 0x00000000U
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

Define Documentation

#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U

RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit)

Definition at line 268 of file stm32g0xx_ll_spi.h.

#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)

Definition at line 269 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RX FIFO Level

Defines
RX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

Define Documentation

#define LL_SPI_RX_FIFO_EMPTY 0x00000000U

FIFO reception empty

Definition at line 277 of file stm32g0xx_ll_spi.h.

#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

FIFO reception full

Definition at line 280 of file stm32g0xx_ll_spi.h.

#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)

FIFO reception 1/2

Definition at line 279 of file stm32g0xx_ll_spi.h.

#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)

FIFO reception 1/4

Definition at line 278 of file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TX FIFO Level

Defines
TX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_TX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

Define Documentation

#define LL_SPI_TX_FIFO_EMPTY 0x00000000U

FIFO transmission empty

Definition at line 288 of file stm32g0xx_ll_spi.h.

#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

FIFO transmission full

Definition at line 291 of file stm32g0xx_ll_spi.h.

#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)

FIFO transmission 1/2

Definition at line 290 of file stm32g0xx_ll_spi.h.

#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)

FIFO transmission 1/4

Definition at line 289 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: DMA Parity

Defines
DMA Parity
SPI Exported Constants

Defines

#define | LL_SPI_DMA_PARITY_EVEN 0x00000000U
#define | LL_SPI_DMA_PARITY_ODD 0x00000001U

Define Documentation

#define LL_SPI_DMA_PARITY_EVEN 0x00000000U

Select DMA parity Even

Definition at line 299 of file stm32g0xx_ll_spi.h.

#define LL_SPI_DMA_PARITY_ODD 0x00000001U

Select DMA parity Odd

Definition at line 300 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SPI Exported Macros

Defines

#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Define Documentation

#define LL_SPI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 334 of file stm32g0xx_ll_spi.h.

#define LL_SPI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 326 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.

Function Documentation

__STATIC_INLINE void LL_SPI_Disable ( SPI_TypeDef * SPIx )

Disable SPI peripheral.

Note:
When disabling the SPI, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 370 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_Enable ( SPI_TypeDef * SPIx )

Enable SPI peripheral.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 358 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler ( SPI_TypeDef * SPIx )

Get baud rate prescaler.

Reference Manual to LL API cross reference:
CR1 BR LL_SPI_GetBaudRatePrescaler
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256

Definition at line 537 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPhase ( SPI_TypeDef * SPIx )

Get clock phase.

Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_GetClockPhase
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE

Definition at line 468 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity ( SPI_TypeDef * SPIx )

Get clock polarity.

Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH

Definition at line 497 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDataWidth ( SPI_TypeDef * SPIx )

Get frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_GetDataWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT

Definition at line 651 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetMode ( SPI_TypeDef * SPIx )

Get SPI operation mode (Master or Slave)

Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_GetMode
CR1 SSI LL_SPI_GetMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE

Definition at line 411 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold ( SPI_TypeDef * SPIx )

Get threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_GetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER

Definition at line 678 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetStandard ( SPI_TypeDef * SPIx )

Get serial protocol used.

Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI

Definition at line 439 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder ( SPI_TypeDef * SPIx )

Get transfer bit order.

Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_GetTransferBitOrder
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST

Definition at line 565 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection ( SPI_TypeDef * SPIx )

Get transfer direction mode.

Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_GetTransferDirection
CR1 BIDIMODE LL_SPI_GetTransferDirection
CR1 BIDIOE LL_SPI_GetTransferDirection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX

Definition at line 602 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabled ( SPI_TypeDef * SPIx )

Check if SPI peripheral is enabled.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 381 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BaudRate
 | ) |  |

Set baud rate prescaler.

Note:
These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
Reference Manual to LL API cross reference:
CR1 BR LL_SPI_SetBaudRatePrescaler
Parameters:
SPIx SPI Instance
BaudRate This parameter can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256
Return values:
None

Definition at line 518 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPhase | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPhase
 | ) |  |

Set clock phase.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_SetClockPhase
Parameters:
SPIx SPI Instance
ClockPhase This parameter can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE
Return values:
None

Definition at line 455 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set clock polarity.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH
Return values:
None

Definition at line 484 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDataWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataWidth
 | ) |  |

Set frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_SetDataWidth
Parameters:
SPIx SPI Instance
DataWidth This parameter can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT
Return values:
None

Definition at line 627 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set SPI operation mode to Master or Slave.

Note:
This bit should not be changed when communication is ongoing.
Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_SetMode
CR1 SSI LL_SPI_SetMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE
Return values:
None

Definition at line 397 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Threshold
 | ) |  |

Set threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_SetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Threshold This parameter can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER
Return values:
None

Definition at line 665 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set serial protocol used.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI
Return values:
None

Definition at line 426 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferBitOrder | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BitOrder
 | ) |  |

Set transfer bit order.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_SetTransferBitOrder
Parameters:
SPIx SPI Instance
BitOrder This parameter can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST
Return values:
None

Definition at line 552 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferDirection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TransferDirection
 | ) |  |

Set transfer direction mode.

Note:
For Half-Duplex mode, Rx Direction is set by default. In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_SetTransferDirection
CR1 BIDIMODE LL_SPI_SetTransferDirection
CR1 BIDIOE LL_SPI_SetTransferDirection
Parameters:
SPIx SPI Instance
TransferDirection This parameter can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX
Return values:
None

Definition at line 585 of file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC Management

Functions
CRC Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableCRC ( SPI_TypeDef * SPIx )

Disable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_DisableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 710 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableCRC ( SPI_TypeDef * SPIx )

Enable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_EnableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 698 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Get polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 785 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth ( SPI_TypeDef * SPIx )

Get CRC Length.

Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_GetCRCWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT

Definition at line 750 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxCRC ( SPI_TypeDef * SPIx )

Get Rx CRC.

Reference Manual to LL API cross reference:
RXCRCR RXCRC LL_SPI_GetRxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 796 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxCRC ( SPI_TypeDef * SPIx )

Get Tx CRC.

Reference Manual to LL API cross reference:
TXCRCR TXCRC LL_SPI_GetTxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 807 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC ( SPI_TypeDef * SPIx )

Check if CRC is enabled.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_IsEnabledCRC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 722 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCNext ( SPI_TypeDef * SPIx )

Set CRCNext to transfer CRC on the line.

Note:
This bit has to be written as soon as the last data is written in the SPIx_DR register.
Reference Manual to LL API cross reference:
CR1 CRCNEXT LL_SPI_SetCRCNext
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 762 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCPolynomial | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCPoly
 | ) |  |

Set polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
Parameters:
SPIx | SPI Instance
CRCPoly | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
Return values:
None

Definition at line 774 of file stm32g0xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetCRCWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCLength
 | ) |  |

Set CRC Length.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_SetCRCWidth
Parameters:
SPIx SPI Instance
CRCLength This parameter can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT
Return values:
None

Definition at line 737 of file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Slave Select Pin Management

Functions
Slave Select Pin Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt ( SPI_TypeDef * SPIx )

Disable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_DisableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 874 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt ( SPI_TypeDef * SPIx )

Enable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_EnableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 862 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetNSSMode ( SPI_TypeDef * SPIx )

Get NSS mode.

Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_GetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_GetNSSMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT

Definition at line 848 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse ( SPI_TypeDef * SPIx )

Check if NSS pulse is enabled.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_IsEnabledNSSPulse
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 886 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetNSSMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | NSS
 | ) |  |

Set NSS mode.

Note:
LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_SetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_SetNSSMode
Parameters:
SPIx SPI Instance
NSS This parameter can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT
Return values:
None

Definition at line 832 of file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG Management

Functions
FLAG Management
SPI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR ( SPI_TypeDef * SPIx )

Clear CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_ClearFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1019 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Note:
Clearing this flag is done by reading SPIx_SR register
Reference Manual to LL API cross reference:
SR FRE LL_SPI_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1064 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_FRE().

__STATIC_INLINE void LL_SPI_ClearFlag_MODF ( SPI_TypeDef * SPIx )

Clear mode fault error flag.

Note:
Clearing this flag is done by a read access to the SPIx_SR register followed by a write access to the SPIx_CR1 register
Reference Manual to LL API cross reference:
SR MODF LL_SPI_ClearFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1032 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Note:
Clearing this flag is done by a read access to the SPIx_DR register followed by a read access to the SPIx_SR register
Reference Manual to LL API cross reference:
SR OVR LL_SPI_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1048 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO reception Level.

Reference Manual to LL API cross reference:
SR FRLVL LL_SPI_GetRxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_EMPTY
  • LL_SPI_RX_FIFO_QUARTER_FULL
  • LL_SPI_RX_FIFO_HALF_FULL
  • LL_SPI_RX_FIFO_FULL

Definition at line 993 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO Transmission Level.

Reference Manual to LL API cross reference:
SR FTLVL LL_SPI_GetTxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_TX_FIFO_EMPTY
  • LL_SPI_TX_FIFO_QUARTER_FULL
  • LL_SPI_TX_FIFO_HALF_FULL
  • LL_SPI_TX_FIFO_FULL

Definition at line 1008 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Note:
The BSY flag is cleared under any one of the following conditions: -When the SPI is correctly disabled -When a fault is detected in Master mode (MODF bit set to 1) -In Master mode, when it finishes a data transmission and no new data is ready to be sent -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between each data transfer.
Reference Manual to LL API cross reference:
SR BSY LL_SPI_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 967 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_BSY().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR ( SPI_TypeDef * SPIx )

Get CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_IsActiveFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 927 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_SPI_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 978 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_FRE().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF ( SPI_TypeDef * SPIx )

Get mode fault error flag.

Reference Manual to LL API cross reference:
SR MODF LL_SPI_IsActiveFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 938 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_SPI_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 949 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_SPI_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 905 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_RXNE().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_SPI_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 916 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_TXE().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1120 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_ERR().

__STATIC_INLINE void LL_SPI_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1131 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_RXNE().

__STATIC_INLINE void LL_SPI_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1142 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_TXE().

__STATIC_INLINE void LL_SPI_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1086 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_ERR().

__STATIC_INLINE void LL_SPI_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1097 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_RXNE().

__STATIC_INLINE void LL_SPI_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1108 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_TXE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if error interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1153 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_ERR().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer not empty interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1164 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_RXNE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1175 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_TXE().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Management

Functions
DMA Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1205 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_RX().

__STATIC_INLINE void LL_SPI_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1238 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr ( SPI_TypeDef * SPIx )

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
DR DR LL_SPI_DMA_GetRegAddr
Parameters:
SPIx SPI Instance
Return values:
Address of data register

Definition at line 1314 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1194 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_RX().

__STATIC_INLINE void LL_SPI_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1227 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_GetDMAParity_RX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1276 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_GetDMAParity_TX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1303 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1216 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1249 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_TX().

__STATIC_INLINE void LL_SPI_SetDMAParity_RX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_SetDMAParity_RX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1263 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDMAParity_TX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_SetDMAParity_TX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1290 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: DATA Management

Functions
DATA Management
SPI Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.

Function Documentation

__STATIC_INLINE uint16_t LL_SPI_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1344 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_ReceiveData16().

__STATIC_INLINE uint8_t LL_SPI_ReceiveData8 ( SPI_TypeDef * SPIx )

Read 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData8
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1333 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 1373 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_TransmitData16().

__STATIC_INLINE void LL_SPI_TransmitData8 | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | TxData
 | ) |  |

Write 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData8
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1356 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_SPI_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 133 of file stm32g0xx_ll_spi.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_SPI2, LL_APB1_GRP1_PERIPH_SPI3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_SPI1, and LL_APB2_GRP1_ReleaseReset().

Referenced by LL_I2S_DeInit().

ErrorStatus LL_SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initialize the SPI registers according to the specified parameters in SPI_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
SPI_InitStruct | pointer to a LL_SPI_InitTypeDef structure
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 188 of file stm32g0xx_ll_spi.c.

References assert_param, LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, IS_LL_SPI_BAUDRATE, IS_LL_SPI_BITORDER, IS_LL_SPI_CRC_POLYNOMIAL, IS_LL_SPI_CRCCALCULATION, IS_LL_SPI_DATAWIDTH, IS_LL_SPI_MODE, IS_LL_SPI_NSS, IS_LL_SPI_PHASE, IS_LL_SPI_POLARITY, IS_LL_SPI_TRANSFER_DIRECTION, LL_SPI_CRCCALCULATION_ENABLE, LL_SPI_DATAWIDTH_9BIT, LL_SPI_IsEnabled(), LL_SPI_RX_FIFO_TH_QUARTER, LL_SPI_SetCRCPolynomial(), LL_SPI_SetRxFIFOThreshold(), LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, SPI_CR1_CLEAR_MASK, and LL_SPI_InitTypeDef::TransferDirection.

void LL_SPI_StructInit ( LL_SPI_InitTypeDef * SPI_InitStruct )

Set each LL_SPI_InitTypeDef field to default value.

Parameters:
SPI_InitStruct pointer to a LL_SPI_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 266 of file stm32g0xx_ll_spi.c.

References LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, LL_SPI_BAUDRATEPRESCALER_DIV2, LL_SPI_CRCCALCULATION_DISABLE, LL_SPI_DATAWIDTH_8BIT, LL_SPI_FULL_DUPLEX, LL_SPI_MODE_SLAVE, LL_SPI_MSB_FIRST, LL_SPI_NSS_HARD_INPUT, LL_SPI_PHASE_1EDGE, LL_SPI_POLARITY_LOW, LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, and LL_SPI_InitTypeDef::TransferDirection.

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STM32G0C1xx HAL User Manual: I2S Private Constants

Defines
I2S Private Constants
I2S

Defines

#define | I2S_I2SCFGR_CLEAR_MASK
#define | I2S_I2SPR_CLEAR_MASK 0x0002U

Define Documentation

#define I2S_I2SCFGR_CLEAR_MASK
Value:
(SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )

Definition at line 305 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define I2S_I2SPR_CLEAR_MASK 0x0002U

Definition at line 309 of file stm32g0xx_ll_spi.c.

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STM32G0C1xx HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)

Define Documentation

#define IS_LL_I2S_AUDIO_FREQ ( __VALUE__ )
Value:
((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
                                          && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
                                         || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))

Definition at line 340 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_CPOL ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_POLARITY_LOW)  \
                                          || ((__VALUE__) == LL_I2S_POLARITY_HIGH))

Definition at line 323 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_DATAFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))

Definition at line 318 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MCLK_OUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
                                          || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))

Definition at line 337 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
                                          || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))

Definition at line 332 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_PRESCALER_LINEAR ( __VALUE__ ) ((__VALUE__) >= 0x2U)

Definition at line 344 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_PRESCALER_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
                                               || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))

Definition at line 346 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_STANDARD ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
                                          || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
                                          || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))

Definition at line 326 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_Init().

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STM32G0C1xx HAL User Manual: LL_I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2S_InitTypeDef Struct Reference
I2S Exported Init structure

I2S Init structure definition. More...

#include <stm32g0xx_ll_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | ClockPolarity

Detailed Description

I2S Init structure definition.

Definition at line 1426 of file stm32g0xx_ll_spi.h.

Field Documentation

uint32_t LL_I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of Audio Frequency

Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity and unitary functions LL_I2S_SetPrescalerLinear() and LL_I2S_SetPrescalerParity() to set it.

Definition at line 1451 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::ClockPolarity

Specifies the idle state of the I2S clock. This parameter can be a value of Clock Polarity

This feature can be modified afterwards using unitary function LL_I2S_SetClockPolarity().

Definition at line 1458 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of Data format

This feature can be modified afterwards using unitary function LL_I2S_SetDataFormat().

Definition at line 1439 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of MCLK Output

This feature can be modified afterwards using unitary functions LL_I2S_EnableMasterClock() or LL_I2S_DisableMasterClock.

Definition at line 1445 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of Operation Mode

This feature can be modified afterwards using unitary function LL_I2S_SetTransferMode().

Definition at line 1428 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2s Standard

This feature can be modified afterwards using unitary function LL_I2S_SetStandard().

Definition at line 1433 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_spi.h
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STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2S Exported Constants

Flags defines which can be used with LL_I2S_ReadReg function. More...

Defines

#define | LL_I2S_SR_RXNE LL_SPI_SR_RXNE
#define | LL_I2S_SR_TXE LL_SPI_SR_TXE
#define | LL_I2S_SR_BSY LL_SPI_SR_BSY
#define | LL_I2S_SR_UDR SPI_SR_UDR
#define | LL_I2S_SR_OVR LL_SPI_SR_OVR
#define | LL_I2S_SR_FRE LL_SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_I2S_ReadReg function.

Define Documentation

#define LL_I2S_SR_BSY LL_SPI_SR_BSY

Busy flag

Definition at line 1481 of file stm32g0xx_ll_spi.h.

#define LL_I2S_SR_FRE LL_SPI_SR_FRE

TI mode frame format error flag

Definition at line 1484 of file stm32g0xx_ll_spi.h.

#define LL_I2S_SR_OVR LL_SPI_SR_OVR

Overrun flag

Definition at line 1483 of file stm32g0xx_ll_spi.h.

#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 1479 of file stm32g0xx_ll_spi.h.

#define LL_I2S_SR_TXE LL_SPI_SR_TXE

Tx buffer empty flag

Definition at line 1480 of file stm32g0xx_ll_spi.h.

#define LL_I2S_SR_UDR SPI_SR_UDR

Underrun flag

Definition at line 1482 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Data format

Defines
Data format
I2S Exported Constants

Defines

#define | LL_I2S_DATAFORMAT_16B 0x00000000U
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Define Documentation

#define LL_I2S_DATAFORMAT_16B 0x00000000U

Data length 16 bits, Channel length 16bit

Definition at line 1503 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)

Data length 16 bits, Channel length 32bit

Definition at line 1504 of file stm32g0xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)

Data length 24 bits, Channel length 32bit

Definition at line 1505 of file stm32g0xx_ll_spi.h.

#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Data length 16 bits, Channel length 32bit

Definition at line 1506 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
I2S Exported Constants

Defines

#define | LL_I2S_POLARITY_LOW 0x00000000U
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Define Documentation

#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Clock steady state is high level

Definition at line 1515 of file stm32g0xx_ll_spi.h.

#define LL_I2S_POLARITY_LOW 0x00000000U

Clock steady state is low level

Definition at line 1514 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

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STM32G0C1xx HAL User Manual: I2s Standard

Defines
I2s Standard
I2S Exported Constants

Defines

#define | LL_I2S_STANDARD_PHILIPS 0x00000000U
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

Define Documentation

#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)

LSB justified standard (right justified)

Definition at line 1525 of file stm32g0xx_ll_spi.h.

#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)

MSB justified standard (left justified)

Definition at line 1524 of file stm32g0xx_ll_spi.h.

#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

PCM standard, long frame synchronization

Definition at line 1527 of file stm32g0xx_ll_spi.h.

#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)

PCM standard, short frame synchronization

Definition at line 1526 of file stm32g0xx_ll_spi.h.

#define LL_I2S_STANDARD_PHILIPS 0x00000000U

I2S standard philips

Definition at line 1523 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

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STM32G0C1xx HAL User Manual: Operation Mode

Defines
Operation Mode
I2S Exported Constants

Defines

#define | LL_I2S_MODE_SLAVE_TX 0x00000000U
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Define Documentation

#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Master Rx configuration

Definition at line 1538 of file stm32g0xx_ll_spi.h.

#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)

Master Tx configuration

Definition at line 1537 of file stm32g0xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)

Slave Rx configuration

Definition at line 1536 of file stm32g0xx_ll_spi.h.

#define LL_I2S_MODE_SLAVE_TX 0x00000000U

Slave Tx configuration

Definition at line 1535 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

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STM32G0C1xx HAL User Manual: Prescaler Factor

Defines
Prescaler Factor
I2S Exported Constants

Defines

#define | LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
#define | LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)

Define Documentation

#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U

Odd factor: Real divider value is = I2SDIV * 2

Definition at line 1546 of file stm32g0xx_ll_spi.h.

#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)

Odd factor: Real divider value is = (I2SDIV * 2)+1

Definition at line 1547 of file stm32g0xx_ll_spi.h.

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STM32G0C1xx HAL User Manual: MCLK Output

Defines
MCLK Output
I2S Exported Constants

Defines

#define | LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Define Documentation

#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U

Master clock output is disabled

Definition at line 1557 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_StructInit().

#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Master clock output is enabled

Definition at line 1558 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Audio Frequency

Defines
Audio Frequency
I2S Exported Constants

Defines

#define | LL_I2S_AUDIOFREQ_192K 192000U
#define | LL_I2S_AUDIOFREQ_96K 96000U
#define | LL_I2S_AUDIOFREQ_48K 48000U
#define | LL_I2S_AUDIOFREQ_44K 44100U
#define | LL_I2S_AUDIOFREQ_32K 32000U
#define | LL_I2S_AUDIOFREQ_22K 22050U
#define | LL_I2S_AUDIOFREQ_16K 16000U
#define | LL_I2S_AUDIOFREQ_11K 11025U
#define | LL_I2S_AUDIOFREQ_8K 8000U
#define | LL_I2S_AUDIOFREQ_DEFAULT 2U

Define Documentation

#define LL_I2S_AUDIOFREQ_11K 11025U

Audio Frequency configuration 11025 Hz

Definition at line 1574 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_16K 16000U

Audio Frequency configuration 16000 Hz

Definition at line 1573 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_192K 192000U

Audio Frequency configuration 192000 Hz

Definition at line 1567 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_22K 22050U

Audio Frequency configuration 22050 Hz

Definition at line 1572 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_32K 32000U

Audio Frequency configuration 32000 Hz

Definition at line 1571 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_44K 44100U

Audio Frequency configuration 44100 Hz

Definition at line 1570 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_48K 48000U

Audio Frequency configuration 48000 Hz

Definition at line 1569 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_8K 8000U

Audio Frequency configuration 8000 Hz

Definition at line 1575 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_96K 96000U

Audio Frequency configuration 96000 Hz

Definition at line 1568 of file stm32g0xx_ll_spi.h.

#define LL_I2S_AUDIOFREQ_DEFAULT 2U

Audio Freq not specified. Register I2SDIV = 2

Definition at line 1576 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2S Exported Macros

Defines

#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Define Documentation

#define LL_I2S_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1610 of file stm32g0xx_ll_spi.h.

#define LL_I2S_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1602 of file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabled (SPI_TypeDef *SPIx)
Check if I2S peripheral is enabled.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataFormat)
Set I2S data frame length.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S data frame length.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set I2S clock polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get I2S clock polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard protocol.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard protocol.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set I2S transfer mode.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S transfer mode.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the master clock output (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the master clock output (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock output (Pin MCK) is enabled.
__STATIC_INLINE void | LL_I2S_EnableAsyncStart (SPI_TypeDef *SPIx)
Enable asynchronous start.
__STATIC_INLINE void | LL_I2S_DisableAsyncStart (SPI_TypeDef *SPIx)
Disable asynchronous start.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledAsyncStart (SPI_TypeDef *SPIx)
Check if asynchronous start is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_Disable ( SPI_TypeDef * SPIx )

Disable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SE LL_I2S_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1648 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_DisableAsyncStart ( SPI_TypeDef * SPIx )

Disable asynchronous start.

Reference Manual to LL API cross reference:
I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1891 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_DisableMasterClock ( SPI_TypeDef * SPIx )

Disable the master clock output (Pin MCK)

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_DisableMasterClock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1857 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_Enable ( SPI_TypeDef * SPIx )

Select I2S mode and Enable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SMOD LL_I2S_Enable
I2SCFGR I2SE LL_I2S_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1637 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_EnableAsyncStart ( SPI_TypeDef * SPIx )

Enable asynchronous start.

Reference Manual to LL API cross reference:
I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1880 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_EnableMasterClock ( SPI_TypeDef * SPIx )

Enable the master clock output (Pin MCK)

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_EnableMasterClock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1846 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity ( SPI_TypeDef * SPIx )

Get I2S clock polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH

Definition at line 1719 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetDataFormat ( SPI_TypeDef * SPIx )

Get I2S data frame length.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_GetDataFormat
I2SCFGR CHLEN LL_I2S_GetDataFormat
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_32B

Definition at line 1692 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear ( SPI_TypeDef * SPIx )

Get I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SPR I2SDIV LL_I2S_GetPrescalerLinear
Parameters:
SPIx SPI Instance
Return values:
PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF

Definition at line 1808 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity ( SPI_TypeDef * SPIx )

Get I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SPR ODD LL_I2S_GetPrescalerParity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD

Definition at line 1835 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetStandard ( SPI_TypeDef * SPIx )

Get I2S standard protocol.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_GetStandard
I2SCFGR PCMSYNC LL_I2S_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG

Definition at line 1754 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_GetTransferMode ( SPI_TypeDef * SPIx )

Get I2S transfer mode.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_GetTransferMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX

Definition at line 1785 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsEnabled ( SPI_TypeDef * SPIx )

Check if I2S peripheral is enabled.

Reference Manual to LL API cross reference:
I2SCFGR I2SE LL_I2S_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1659 of file stm32g0xx_ll_spi.h.

Referenced by LL_I2S_Init().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart ( SPI_TypeDef * SPIx )

Check if asynchronous start is enabled.

Reference Manual to LL API cross reference:
I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1902 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock ( SPI_TypeDef * SPIx )

Check if the master clock output (Pin MCK) is enabled.

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_IsEnabledMasterClock
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1868 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set I2S clock polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH
Return values:
None

Definition at line 1706 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetDataFormat | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataFormat
 | ) |  |

Set I2S data frame length.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_SetDataFormat
I2SCFGR CHLEN LL_I2S_SetDataFormat
Parameters:
SPIx SPI Instance
DataFormat This parameter can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_32B
Return values:
None

Definition at line 1676 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetPrescalerLinear | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | PrescalerLinear
 | ) |  |

Set I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SPR I2SDIV LL_I2S_SetPrescalerLinear
Parameters:
SPIx | SPI Instance
PrescalerLinear | Value between Min_Data=0x02 and Max_Data=0xFF
Return values:
None

Definition at line 1797 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetPrescalerParity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SPR ODD LL_I2S_SetPrescalerParity
Parameters:
SPIx SPI Instance
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 1822 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set I2S standard protocol.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_SetStandard
I2SCFGR PCMSYNC LL_I2S_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG
Return values:
None

Definition at line 1737 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE void LL_I2S_SetTransferMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set I2S transfer mode.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_SetTransferMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX
Return values:
None

Definition at line 1770 of file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG Management

Functions
FLAG Management
I2S Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_CHSIDE (SPI_TypeDef *SPIx)
Get channel side flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_I2S_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_I2S_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2026 of file stm32g0xx_ll_spi.h.

References LL_SPI_ClearFlag_FRE().

__STATIC_INLINE void LL_I2S_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2002 of file stm32g0xx_ll_spi.h.

References LL_SPI_ClearFlag_OVR().

__STATIC_INLINE void LL_I2S_ClearFlag_UDR ( SPI_TypeDef * SPIx )

Clear underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_ClearFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2013 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Reference Manual to LL API cross reference:
SR BSY LL_I2S_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1944 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsActiveFlag_BSY().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE ( SPI_TypeDef * SPIx )

Get channel side flag.

Note:
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
It has no significance in PCM mode.
Reference Manual to LL API cross reference:
SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1991 of file stm32g0xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_I2S_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1977 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsActiveFlag_FRE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1955 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_I2S_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1922 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsActiveFlag_RXNE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_I2S_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1933 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsActiveFlag_TXE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR ( SPI_TypeDef * SPIx )

Get underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_IsActiveFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1966 of file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error IT.
__STATIC_INLINE void | LL_I2S_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if ERR IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if RXNE IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if TXE IT is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error IT.

Note:
This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2080 of file stm32g0xx_ll_spi.h.

References LL_SPI_DisableIT_ERR().

__STATIC_INLINE void LL_I2S_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty IT.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2091 of file stm32g0xx_ll_spi.h.

References LL_SPI_DisableIT_RXNE().

__STATIC_INLINE void LL_I2S_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty IT.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2102 of file stm32g0xx_ll_spi.h.

References LL_SPI_DisableIT_TXE().

__STATIC_INLINE void LL_I2S_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error IT.

Note:
This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2046 of file stm32g0xx_ll_spi.h.

References LL_SPI_EnableIT_ERR().

__STATIC_INLINE void LL_I2S_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty IT.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2057 of file stm32g0xx_ll_spi.h.

References LL_SPI_EnableIT_RXNE().

__STATIC_INLINE void LL_I2S_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty IT.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2068 of file stm32g0xx_ll_spi.h.

References LL_SPI_EnableIT_TXE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if ERR IT is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2113 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsEnabledIT_ERR().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if RXNE IT is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2124 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsEnabledIT_RXNE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if TXE IT is enabled.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2135 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsEnabledIT_TXE().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Management

Functions
DMA Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2165 of file stm32g0xx_ll_spi.h.

References LL_SPI_DisableDMAReq_RX().

__STATIC_INLINE void LL_I2S_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2198 of file stm32g0xx_ll_spi.h.

References LL_SPI_DisableDMAReq_TX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2154 of file stm32g0xx_ll_spi.h.

References LL_SPI_EnableDMAReq_RX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 2187 of file stm32g0xx_ll_spi.h.

References LL_SPI_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2176 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 2209 of file stm32g0xx_ll_spi.h.

References LL_SPI_IsEnabledDMAReq_TX().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DATA Management

Functions
DATA Management
I2S Exported Functions

Functions

__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in data register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in data register.

Function Documentation

__STATIC_INLINE uint16_t LL_I2S_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in data register.

Reference Manual to LL API cross reference:
DR DR LL_I2S_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF

Definition at line 2228 of file stm32g0xx_ll_spi.h.

References LL_SPI_ReceiveData16().

__STATIC_INLINE void LL_I2S_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in data register.

Reference Manual to LL API cross reference:
DR DR LL_I2S_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x0000 and Max_Data=0xFFFF
Return values:
None

Definition at line 2240 of file stm32g0xx_ll_spi.h.

References LL_SPI_TransmitData16().

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STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Functions

ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Function Documentation

void LL_I2S_ConfigPrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerLinear,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set linear and parity prescaler.

Note:
To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)
Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
Parameters:
SPIx | SPI Instance
PrescalerLinear | value Min_Data=0x02 and Max_Data=0xFF.
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 516 of file stm32g0xx_ll_spi.c.

References assert_param, IS_LL_I2S_PRESCALER_LINEAR, and IS_LL_I2S_PRESCALER_PARITY.

ErrorStatus LL_I2S_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI/I2S registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 370 of file stm32g0xx_ll_spi.c.

References LL_SPI_DeInit().

ErrorStatus LL_I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
I2S_InitStruct | pointer to a LL_I2S_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are Initialized
  • ERROR: SPI registers are not Initialized

Definition at line 385 of file stm32g0xx_ll_spi.c.

References assert_param, LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, I2S_I2SCFGR_CLEAR_MASK, IS_LL_I2S_AUDIO_FREQ, IS_LL_I2S_CPOL, IS_LL_I2S_DATAFORMAT, IS_LL_I2S_MCLK_OUTPUT, IS_LL_I2S_MODE, IS_LL_I2S_STANDARD, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_IsEnabled(), LL_I2S_MCLK_OUTPUT_ENABLE, LL_RCC_GetSystemClocksFreq(), LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, LL_I2S_InitTypeDef::Standard, and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

void LL_I2S_StructInit ( LL_I2S_InitTypeDef * I2S_InitStruct )

Set each LL_I2S_InitTypeDef field to default value.

Parameters:
I2S_InitStruct pointer to a LL_I2S_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 494 of file stm32g0xx_ll_spi.c.

References LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_MCLK_OUTPUT_DISABLE, LL_I2S_MODE_SLAVE_TX, LL_I2S_POLARITY_LOW, LL_I2S_STANDARD_PHILIPS, LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

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STM32G0C1xx HAL User Manual: SYSTEM Private Constants

SYSTEM Private Constants
SYSTEM
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSCFG REMAP

Defines
SYSCFG REMAP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_REMAP_FLASH 0x00000000U
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)

Define Documentation

#define LL_SYSCFG_REMAP_FLASH 0x00000000U

Main Flash memory mapped at 0x00000000

Definition at line 78 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)

Embedded SRAM mapped at 0x00000000

Definition at line 80 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0

System Flash memory mapped at 0x00000000

Definition at line 79 of file stm32g0xx_ll_system.h.

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STM32G0C1xx HAL User Manual: SYSCFG PIN RMP

Defines
SYSCFG PIN RMP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_PIN_RMP_PA11 SYSCFG_CFGR1_PA11_RMP
#define | LL_SYSCFG_PIN_RMP_PA12 SYSCFG_CFGR1_PA12_RMP

Define Documentation

#define LL_SYSCFG_PIN_RMP_PA11 SYSCFG_CFGR1_PA11_RMP

PA11 pad behaves as PA9 pin

Definition at line 88 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_PIN_RMP_PA12 SYSCFG_CFGR1_PA12_RMP

PA12 pad behaves as PA10 pin

Definition at line 89 of file stm32g0xx_ll_system.h.

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STM32G0C1xx HAL User Manual: SYSCFG IR Modulation

Defines
SYSCFG IR Modulation
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)
#define | LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0)
#define | LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1)

Define Documentation

#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)

00: Timer16 is selected as IRDA Modulation enveloppe source

Definition at line 99 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0)

01: USART1 is selected as IRDA Modulation enveloppe source

Definition at line 100 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1)

10: USART4 is selected as IRDA Modulation enveloppe source

Definition at line 102 of file stm32g0xx_ll_system.h.

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STM32G0C1xx HAL User Manual: SYSCFG IR Polarity

Defines
SYSCFG IR Polarity
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_IR_POL_NOT_INVERTED 0x00000000U
#define | LL_SYSCFG_IR_POL_INVERTED (SYSCFG_CFGR1_IR_POL)

Define Documentation

#define LL_SYSCFG_IR_POL_INVERTED (SYSCFG_CFGR1_IR_POL)

1: Output of IRDA (IROut) inverted

Definition at line 113 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_IR_POL_NOT_INVERTED 0x00000000U

0: Output of IRDA (IROut) not inverted

Definition at line 112 of file stm32g0xx_ll_system.h.

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STM32G0C1xx HAL User Manual: SYSCFG I/O analog switch voltage booster enable

Defines
SYSCFG I/O analog switch voltage booster enable
SYSTEM Exported Constants

Defines

#define LL_SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN

Define Documentation

#define LL_SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN

I/O analog switch voltage booster enable

Definition at line 123 of file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSCFG UCPD Dead Battery feature Disable

Defines
SYSCFG UCPD Dead Battery feature Disable
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE
#define | LL_SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE

Define Documentation

#define LL_SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE

UCPD1 STROBE sw configuration

Definition at line 133 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE

UCPD2 STROBE sw configuration

Definition at line 134 of file stm32g0xx_ll_system.h.

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STM32G0C1xx HAL User Manual: SYSCFG I2C FASTMODEPLUS

Defines
SYSCFG I2C FASTMODEPLUS
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable I2C1 Fast mode Plus

Definition at line 148 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable I2C2 Fast mode plus

Definition at line 151 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable I2C3 Fast mode plus

Definition at line 161 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP

Enable Fast Mode Plus on PA10

Definition at line 157 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP

Enable Fast Mode Plus on PA9

Definition at line 154 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

I2C PB6 Fast mode plus

Definition at line 143 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

I2C PB7 Fast mode plus

Definition at line 144 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

I2C PB8 Fast mode plus

Definition at line 145 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

I2C PB9 Fast mode plus

Definition at line 146 of file stm32g0xx_ll_system.h.

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STM32G0C1xx HAL User Manual: SYSCFG TIMER BREAK

Defines
SYSCFG TIMER BREAK
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL
#define | LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/15/16/17

Definition at line 171 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIM1/15/16/17

Definition at line 180 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 174 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL

Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17

Definition at line 178 of file stm32g0xx_ll_system.h.

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STM32G0C1xx HAL User Manual: SYSCFG CLAMPING DIODE

Defines
SYSCFG CLAMPING DIODE
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN
#define | LL_SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN
#define | LL_SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN
#define | LL_SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN
#define | LL_SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN
#define | LL_SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN
#define | LL_SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN
#define | LL_SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN

Define Documentation

#define LL_SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN

Enables Clamping diode of PA13

Definition at line 194 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN

Enables Clamping diode of PA1

Definition at line 190 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN

Enables Clamping diode of PA3

Definition at line 191 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN

Enables Clamping diode of PA5

Definition at line 192 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN

Enables Clamping diode of PA6

Definition at line 193 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN

Enables Clamping diode of PB0

Definition at line 195 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN

Enables Clamping diode of PB1

Definition at line 196 of file stm32g0xx_ll_system.h.

#define LL_SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN

Enables Clamping diode of PB2

Definition at line 197 of file stm32g0xx_ll_system.h.

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STM32G0C1xx HAL User Manual: DBGMCU APB1 GRP1 STOP IP

Defines
DBGMCU APB1 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBG_APB_FZ1_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBG_APB_FZ1_DBG_TIM6_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBG_APB_FZ1_DBG_TIM7_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM2_STOP DBG_APB_FZ1_DBG_LPTIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBG_APB_FZ1_DBG_LPTIM1_STOP

Define Documentation

#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP

I2C1 SMBUS timeout mode stopped when Core is halted

Definition at line 222 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP

I2C2 SMBUS timeout mode stopped when Core is halted

Definition at line 224 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP

Debug Independent Watchdog stopped when Core is halted

Definition at line 221 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBG_APB_FZ1_DBG_LPTIM1_STOP

LPTIM1 counter stopped when Core is halted

Definition at line 230 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_LPTIM2_STOP DBG_APB_FZ1_DBG_LPTIM2_STOP

LPTIM2 counter stopped when Core is halted

Definition at line 227 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP

RTC Calendar frozen when core is halted

Definition at line 219 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP

TIM2 counter stopped when core is halted

Definition at line 207 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP

TIM3 counter stopped when core is halted

Definition at line 209 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBG_APB_FZ1_DBG_TIM4_STOP

TIM4 counter stopped when core is halted

Definition at line 211 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBG_APB_FZ1_DBG_TIM6_STOP

TIM6 counter stopped when core is halted

Definition at line 214 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBG_APB_FZ1_DBG_TIM7_STOP

TIM7 counter stopped when core is halted

Definition at line 217 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP

Debug Window Watchdog stopped when Core is halted

Definition at line 220 of file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DBGMCU APB2 GRP1 STOP IP

Defines
DBGMCU APB2 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP

Define Documentation

#define LL_DBGMCU_APB2_GRP1_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP

TIM14 counter stopped when core is halted

Definition at line 241 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP

TIM15 counter stopped when core is halted

Definition at line 244 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP

TIM16 counter stopped when core is halted

Definition at line 246 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP

TIM17 counter stopped when core is halted

Definition at line 247 of file stm32g0xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP

TIM1 counter stopped when core is halted

Definition at line 239 of file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: VREFBUF VOLTAGE

Defines
VREFBUF VOLTAGE
SYSTEM Exported Constants

Defines

#define | LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U
#define | LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Define Documentation

#define LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U

Voltage reference scale 0 (VREF_OUT1)

Definition at line 257 of file stm32g0xx_ll_system.h.

#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Voltage reference scale 1 (VREF_OUT2)

Definition at line 258 of file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH LATENCY

Defines
FLASH LATENCY
SYSTEM Exported Constants

Defines

#define | LL_FLASH_LATENCY_0 0x00000000U
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1
#define | LL_FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)

Define Documentation

#define LL_FLASH_LATENCY_0 0x00000000U

FLASH Zero Latency cycle

Definition at line 267 of file stm32g0xx_ll_system.h.

Referenced by LL_SetFlashLatency().

#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0

FLASH One Latency cycle

Definition at line 268 of file stm32g0xx_ll_system.h.

Referenced by LL_SetFlashLatency().

#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

FLASH Two wait states

Definition at line 269 of file stm32g0xx_ll_system.h.

Referenced by LL_SetFlashLatency().

#define LL_FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)

FLASH Three wait states

Definition at line 270 of file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSCFG

Functions
SYSCFG
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_EnablePinRemap (uint32_t PinRemap)
Enable remap of a pin on different pad.
__STATIC_INLINE void | LL_SYSCFG_DisablePinRemap (uint32_t PinRemap)
Enable remap of a pin on different pad.
__STATIC_INLINE void | LL_SYSCFG_SetIRModEnvelopeSignal (uint32_t Source)
Set IR Modulation Envelope signal source.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetIRModEnvelopeSignal (void)
Get IR Modulation Envelope signal source.
__STATIC_INLINE void | LL_SYSCFG_SetIRPolarity (uint32_t Polarity)
Set IR Output polarity.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetIRPolarity (void)
Get IR Output polarity.
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void)
Enable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void)
Disable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableDBATT (uint32_t ConfigDeadBattery)
Disable dead battery behavior.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_WWDG (void)
Check if Window watchdog interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_PVDOUT (void)
Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_PVMOUT (void)
Check if VDDUSB supply monitoring interrupt occurred or not (EXTI line 34).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_RTC_WAKEUP (void)
Check if RTC Wake Up interrupt occurred or not (EXTI line 19).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TAMPER (void)
Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 21).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FLASH_ITF (void)
Check if Flash interface interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FLASH_ECC (void)
Check if Flash interface interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CLK_CTRL (void)
Check if Reset and clock control interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CRS (void)
Check if Reset and clock control interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI0 (void)
Check if EXTI line 0 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI1 (void)
Check if EXTI line 1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI2 (void)
Check if EXTI line 2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI3 (void)
Check if EXTI line 3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI4 (void)
Check if EXTI line 4 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI5 (void)
Check if EXTI line 5 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI6 (void)
Check if EXTI line 6 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI7 (void)
Check if EXTI line 7 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI8 (void)
Check if EXTI line 8 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI9 (void)
Check if EXTI line 9 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI10 (void)
Check if EXTI line 10 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI11 (void)
Check if EXTI line 11 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI12 (void)
Check if EXTI line 12 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI13 (void)
Check if EXTI line 13 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI14 (void)
Check if EXTI line 14 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI15 (void)
Check if EXTI line 15 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_UCPD1 (void)
Check if UCPD1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_UCPD2 (void)
Check if UCPD2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USB (void)
Check if USB interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH1 (void)
Check if DMA1 channel 1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH2 (void)
Check if DMA1 channel 2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH3 (void)
Check if DMA1 channel 3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH4 (void)
Check if DMA1 channel 4 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH5 (void)
Check if DMA1 channel 5 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH6 (void)
Check if DMA1 channel 6 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH7 (void)
Check if DMA1 channel 7 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMAMUX (void)
Check if DMAMUX interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH1 (void)
Check if DMA2_CH1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH2 (void)
Check if DMA2_CH2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH3 (void)
Check if DMA2_CH3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH4 (void)
Check if DMA2_CH4 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH5 (void)
Check if DMA2_CH5 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_ADC (void)
Check if ADC interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_COMP1 (void)
Check if Comparator 1 interrupt occurred or not (EXTI line 21).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_COMP2 (void)
Check if Comparator 2 interrupt occurred or not (EXTI line 22).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_COMP3 (void)
Check if Comparator 3 interrupt occurred or not (EXTI line 20).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_BRK (void)
Check if Timer 1 break interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_UPD (void)
Check if Timer 1 update interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_TRG (void)
Check if Timer 1 trigger interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_CCU (void)
Check if Timer 1 commutation interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_CC (void)
Check if Timer 1 capture compare interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM2 (void)
Check if Timer 2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM3 (void)
Check if Timer 3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM4 (void)
Check if Timer 3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DAC (void)
Check if DAC underrun interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM6 (void)
Check if Timer 6 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_LPTIM1 (void)
Check if LPTIM1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM7 (void)
Check if Timer 7 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_LPTIM2 (void)
Check if LPTIM2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM14 (void)
Check if Timer 14 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM15 (void)
Check if Timer 15 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM16 (void)
Check if Timer 16 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FDCAN1_IT0 (void)
Check if FDCAN1_IT0 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FDCAN2_IT0 (void)
Check if FDCAN2_IT0 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM17 (void)
Check if Timer 17 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FDCAN1_IT1 (void)
Check if FDCAN1_IT1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FDCAN2_IT1 (void)
Check if FDCAN2_IT1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_I2C1 (void)
Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_I2C2 (void)
Check if I2C2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_I2C3 (void)
Check if I2C3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SPI1 (void)
Check if SPI1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SPI2 (void)
Check if SPI2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SPI3 (void)
Check if SPI3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART1 (void)
Check if USART1 interrupt occurred or not, combined with EXTI line 25.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART2 (void)
Check if USART2 interrupt occurred or not, combined with EXTI line 26.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_LPUART2 (void)
Check if LPUART2 interrupt occurred or not, combined with EXTI line 26.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART3 (void)
Check if USART3 interrupt occurred or not, combined with EXTI line 28.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART4 (void)
Check if USART4 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_LPUART1 (void)
Check if LPUART1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART5 (void)
Check if USART5 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART6 (void)
Check if USART6 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CEC (void)
Check if CEC interrupt occurred or not, combined with EXTI line 27.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_AES (void)
Check if AES interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_RNG (void)
Check if RNG interrupt occurred or not, combined with EXTI line 31.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM parity error flag.
__STATIC_INLINE void | LL_SYSCFG_EnableClampingDiode (uint32_t ConfigClampingDiode)
Enable Clamping Diode on specific pin.
__STATIC_INLINE void | LL_SYSCFG_DisableClampingDiode (uint32_t ConfigClampingDiode)
Disable Clamping Diode on specific pin.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledClampingDiode (uint32_t ConfigClampingDiode)
Indicates whether clamping diode(s) is(are) enabled.

Function Documentation

__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP ( void )

Clear SRAM parity error flag.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
Return values:
None

Definition at line 1575 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster ( void )

Disable I/O analog switch voltage booster.

Note:
When voltage booster is enabled, I/O analog switches are supplied by a dedicated voltage booster, from VDD power domain. This is the recommended configuration with low VDDA voltage operation.
The I/O analog switch voltage booster is relevant for peripherals using I/O in analog input: ADC, COMP. However, COMP and OPAMP inputs have a high impedance and voltage booster do not impact performance significantly. Therefore, the voltage booster is mainly intended for usage with ADC.
Reference Manual to LL API cross reference:
SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
Return values:
None

Definition at line 433 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableClampingDiode ( uint32_t ConfigClampingDiode )

Disable Clamping Diode on specific pin.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_DisableClampingDiode
SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_DisableClampingDiode
SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_DisableClampingDiode
SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_DisableClampingDiode
SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_DisableClampingDiode
SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_DisableClampingDiode
SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_DisableClampingDiode
SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_DisableClampingDiode
Parameters:
ConfigClampingDiode This parameter can be a combination of the following values:
  • LL_SYSCFG_CFGR2_PA1_CDEN
  • LL_SYSCFG_CFGR2_PA3_CDEN
  • LL_SYSCFG_CFGR2_PA5_CDEN
  • LL_SYSCFG_CFGR2_PA6_CDEN
  • LL_SYSCFG_CFGR2_PA13_CDEN
  • LL_SYSCFG_CFGR2_PB0_CDEN
  • LL_SYSCFG_CFGR2_PB1_CDEN
  • LL_SYSCFG_CFGR2_PB2_CDEN
Return values:
None

Definition at line 1628 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableDBATT ( uint32_t ConfigDeadBattery )

Disable dead battery behavior.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 UCPD1_STROBE LL_SYSCFG_DisableDBATT
SYSCFG_CFGR1 UCPD2_STROBE LL_SYSCFG_DisableDBATT
Parameters:
ConfigDeadBattery This parameter can be a combination of the following values:
  • LL_SYSCFG_UCPD1_STROBE
  • LL_SYSCFG_UCPD2_STROBE (*) value not defined in all devices
Return values:
None

Definition at line 510 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_FMP_I2C3 LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 494 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisablePinRemap ( uint32_t PinRemap )

Enable remap of a pin on different pad.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_DisablePinRemap
SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_DisablePinRemap
Parameters:
PinRemap This parameter can be a combination of the following values:
  • LL_SYSCFG_PIN_RMP_PA11
  • LL_SYSCFG_PIN_RMP_PA12
Return values:
None

Definition at line 340 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster ( void )

Enable I/O analog switch voltage booster.

Note:
When voltage booster is enabled, I/O analog switches are supplied by a dedicated voltage booster, from VDD power domain. This is the recommended configuration with low VDDA voltage operation.
The I/O analog switch voltage booster is relevant for peripherals using I/O in analog input: ADC, COMP. However, COMP and OPAMP inputs have a high impedance and voltage booster do not impact performance significantly. Therefore, the voltage booster is mainly intended for usage with ADC.
Reference Manual to LL API cross reference:
SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
Return values:
None

Definition at line 414 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableClampingDiode ( uint32_t ConfigClampingDiode )

Enable Clamping Diode on specific pin.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_EnableClampingDiode
SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_EnableClampingDiode
SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_EnableClampingDiode
SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_EnableClampingDiode
SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_EnableClampingDiode
SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_EnableClampingDiode
SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_EnableClampingDiode
SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_EnableClampingDiode
Parameters:
ConfigClampingDiode This parameter can be a combination of the following values:
  • LL_SYSCFG_CFGR2_PA1_CDEN
  • LL_SYSCFG_CFGR2_PA3_CDEN
  • LL_SYSCFG_CFGR2_PA5_CDEN
  • LL_SYSCFG_CFGR2_PA6_CDEN
  • LL_SYSCFG_CFGR2_PA13_CDEN
  • LL_SYSCFG_CFGR2_PB0_CDEN
  • LL_SYSCFG_CFGR2_PB1_CDEN
  • LL_SYSCFG_CFGR2_PB2_CDEN
Return values:
None

Definition at line 1602 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_FMP_I2C3 LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 464 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnablePinRemap ( uint32_t PinRemap )

Enable remap of a pin on different pad.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_EnablePinRemap
SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_EnablePinRemap
Parameters:
PinRemap This parameter can be a combination of the following values:
  • LL_SYSCFG_PIN_RMP_PA11
  • LL_SYSCFG_PIN_RMP_PA12
Return values:
None

Definition at line 326 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal ( void )

Get IR Modulation Envelope signal source.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_IR_MOD_TIM16
  • LL_SYSCFG_IR_MOD_USART1
  • LL_SYSCFG_IR_MOD_USART4

Definition at line 368 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetIRPolarity ( void )

Get IR Output polarity.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 IR_POL LL_SYSCFG_GetIRPolarity
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_IR_POL_INVERTED
  • LL_SYSCFG_IR_POL_NOT_INVERTED

Definition at line 393 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory ( void )

Get memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM

Definition at line 312 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs ( void )

Get connections to TIM1/15/16/17 Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
Return values:
Returned value can be can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_PVD (*)
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY
  • LL_SYSCFG_TIMBREAK_LOCKUP
  • LL_SYSCFG_TIMBREAK_ECC
(*) value not defined in all devices

Definition at line 1551 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC ( void )

Check if ADC interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
Return values:
State of bit (1 or 0).

Definition at line 1013 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_AES ( void )

Check if AES interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE31 SR_AES LL_SYSCFG_IsActiveFlag_AES
Return values:
State of bit (1 or 0).

Definition at line 1491 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC ( void )

Check if CEC interrupt occurred or not, combined with EXTI line 27.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC
Return values:
State of bit (1 or 0).

Definition at line 1479 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL ( void )

Check if Reset and clock control interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
Return values:
State of bit (1 or 0).

Definition at line 606 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1 ( void )

Check if Comparator 1 interrupt occurred or not (EXTI line 21).

Reference Manual to LL API cross reference:
SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
Return values:
State of bit (1 or 0).

Definition at line 1025 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2 ( void )

Check if Comparator 2 interrupt occurred or not (EXTI line 22).

Reference Manual to LL API cross reference:
SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
Return values:
State of bit (1 or 0).

Definition at line 1037 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP3 ( void )

Check if Comparator 3 interrupt occurred or not (EXTI line 20).

Reference Manual to LL API cross reference:
SYSCFG_ITLINE12 SR_COMP3 LL_SYSCFG_IsActiveFlag_COMP3
Return values:
State of bit (1 or 0).

Definition at line 1049 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS ( void )

Check if Reset and clock control interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
Return values:
State of bit (1 or 0).

Definition at line 618 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC ( void )

Check if DAC underrun interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
Return values:
State of bit (1 or 0).

Definition at line 1157 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1 ( void )

Check if DMA1 channel 1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
Return values:
State of bit (1 or 0).

Definition at line 857 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2 ( void )

Check if DMA1 channel 2 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
Return values:
State of bit (1 or 0).

Definition at line 869 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3 ( void )

Check if DMA1 channel 3 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
Return values:
State of bit (1 or 0).

Definition at line 881 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4 ( void )

Check if DMA1 channel 4 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
Return values:
State of bit (1 or 0).

Definition at line 893 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5 ( void )

Check if DMA1 channel 5 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
Return values:
State of bit (1 or 0).

Definition at line 905 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6 ( void )

Check if DMA1 channel 6 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
Return values:
State of bit (1 or 0).

Definition at line 917 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7 ( void )

Check if DMA1 channel 7 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
Return values:
State of bit (1 or 0).

Definition at line 929 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1 ( void )

Check if DMA2_CH1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
Return values:
State of bit (1 or 0).

Definition at line 953 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2 ( void )

Check if DMA2_CH2 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
Return values:
State of bit (1 or 0).

Definition at line 965 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3 ( void )

Check if DMA2_CH3 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
Return values:
State of bit (1 or 0).

Definition at line 977 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4 ( void )

Check if DMA2_CH4 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
Return values:
State of bit (1 or 0).

Definition at line 989 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5 ( void )

Check if DMA2_CH5 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
Return values:
State of bit (1 or 0).

Definition at line 1001 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMAMUX ( void )

Check if DMAMUX interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE11 SR_DMAMUX1 LL_SYSCFG_IsActiveFlag_DMAMUX
Return values:
State of bit (1 or 0).

Definition at line 941 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0 ( void )

Check if EXTI line 0 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
Return values:
State of bit (1 or 0).

Definition at line 629 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1 ( void )

Check if EXTI line 1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
Return values:
State of bit (1 or 0).

Definition at line 641 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10 ( void )

Check if EXTI line 10 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
Return values:
State of bit (1 or 0).

Definition at line 749 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11 ( void )

Check if EXTI line 11 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
Return values:
State of bit (1 or 0).

Definition at line 761 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12 ( void )

Check if EXTI line 12 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
Return values:
State of bit (1 or 0).

Definition at line 773 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13 ( void )

Check if EXTI line 13 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
Return values:
State of bit (1 or 0).

Definition at line 785 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14 ( void )

Check if EXTI line 14 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
Return values:
State of bit (1 or 0).

Definition at line 797 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15 ( void )

Check if EXTI line 15 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
Return values:
State of bit (1 or 0).

Definition at line 809 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2 ( void )

Check if EXTI line 2 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
Return values:
State of bit (1 or 0).

Definition at line 653 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3 ( void )

Check if EXTI line 3 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
Return values:
State of bit (1 or 0).

Definition at line 665 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4 ( void )

Check if EXTI line 4 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
Return values:
State of bit (1 or 0).

Definition at line 677 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5 ( void )

Check if EXTI line 5 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
Return values:
State of bit (1 or 0).

Definition at line 689 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6 ( void )

Check if EXTI line 6 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
Return values:
State of bit (1 or 0).

Definition at line 701 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7 ( void )

Check if EXTI line 7 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
Return values:
State of bit (1 or 0).

Definition at line 713 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8 ( void )

Check if EXTI line 8 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
Return values:
State of bit (1 or 0).

Definition at line 725 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9 ( void )

Check if EXTI line 9 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
Return values:
State of bit (1 or 0).

Definition at line 737 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT0 ( void )

Check if FDCAN1_IT0 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE21 SR_FDCAN1_IT0 LL_SYSCFG_IsActiveFlag_FDCAN1_IT0
Return values:
State of bit (1 or 0).

Definition at line 1253 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT1 ( void )

Check if FDCAN1_IT1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE22 SR_FDCAN1_IT1 LL_SYSCFG_IsActiveFlag_FDCAN1_IT1
Return values:
State of bit (1 or 0).

Definition at line 1288 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN2_IT0 ( void )

Check if FDCAN2_IT0 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE21 SR_FDCAN2_IT0 LL_SYSCFG_IsActiveFlag_FDCAN2_IT0
Return values:
State of bit (1 or 0).

Definition at line 1264 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN2_IT1 ( void )

Check if FDCAN2_IT1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE22 SR_FDCAN2_IT1 LL_SYSCFG_IsActiveFlag_FDCAN2_IT1
Return values:
State of bit (1 or 0).

Definition at line 1299 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ECC ( void )

Check if Flash interface interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE3 SR_FLASH_ECC LL_SYSCFG_IsActiveFlag_FLASH_ECC
Return values:
State of bit (1 or 0).

Definition at line 594 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF ( void )

Check if Flash interface interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
Return values:
State of bit (1 or 0).

Definition at line 582 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1 ( void )

Check if I2C1 interrupt occurred or not, combined with EXTI line 23.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
Return values:
State of bit (1 or 0).

Definition at line 1311 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2 ( void )

Check if I2C2 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
Return values:
State of bit (1 or 0).

Definition at line 1323 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C3 ( void )

Check if I2C3 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE24 SR_I2C3_GLB LL_SYSCFG_IsActiveFlag_I2C3
Return values:
State of bit (1 or 0).

Definition at line 1335 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM1 ( void )

Check if LPTIM1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE17 SR_LPTIM1_GLB LL_SYSCFG_IsActiveFlag_LPTIM1
Return values:
State of bit (1 or 0).

Definition at line 1181 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM2 ( void )

Check if LPTIM2 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE18 SR_LPTIM2_GLB LL_SYSCFG_IsActiveFlag_LPTIM2
Return values:
State of bit (1 or 0).

Definition at line 1205 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART1 ( void )

Check if LPUART1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE29 SR_LPUART1_GLB LL_SYSCFG_IsActiveFlag_LPUART1
Return values:
State of bit (1 or 0).

Definition at line 1443 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART2 ( void )

Check if LPUART2 interrupt occurred or not, combined with EXTI line 26.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE28 SR_LPUART2_GLB LL_SYSCFG_IsActiveFlag_LPUART2
Return values:
State of bit (1 or 0).

Definition at line 1407 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT ( void )

Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).

Reference Manual to LL API cross reference:
SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
Return values:
State of bit (1 or 0).

Definition at line 534 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVMOUT ( void )

Check if VDDUSB supply monitoring interrupt occurred or not (EXTI line 34).

Reference Manual to LL API cross reference:
SYSCFG_ITLINE1 SR_PVMOUT LL_SYSCFG_IsActiveFlag_PVMOUT
Return values:
State of bit (1 or 0).

Definition at line 546 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RNG ( void )

Check if RNG interrupt occurred or not, combined with EXTI line 31.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE31 SR_RNG LL_SYSCFG_IsActiveFlag_RNG
Return values:
State of bit (1 or 0).

Definition at line 1503 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP ( void )

Check if RTC Wake Up interrupt occurred or not (EXTI line 19).

Reference Manual to LL API cross reference:
SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
Return values:
State of bit (1 or 0).

Definition at line 558 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP ( void )

Check if SRAM parity error detected.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
Return values:
State of bit (1 or 0).

Definition at line 1565 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1 ( void )

Check if SPI1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
Return values:
State of bit (1 or 0).

Definition at line 1347 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2 ( void )

Check if SPI2 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
Return values:
State of bit (1 or 0).

Definition at line 1359 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI3 ( void )

Check if SPI3 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE26 SR_SPI3 LL_SYSCFG_IsActiveFlag_SPI3
Return values:
State of bit (1 or 0).

Definition at line 1371 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TAMPER ( void )

Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 21).

Reference Manual to LL API cross reference:
SYSCFG_ITLINE2 SR_TAMPER LL_SYSCFG_IsActiveFlag_TAMPER
Return values:
State of bit (1 or 0).

Definition at line 570 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14 ( void )

Check if Timer 14 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
Return values:
State of bit (1 or 0).

Definition at line 1217 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15 ( void )

Check if Timer 15 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
Return values:
State of bit (1 or 0).

Definition at line 1229 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16 ( void )

Check if Timer 16 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
Return values:
State of bit (1 or 0).

Definition at line 1241 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17 ( void )

Check if Timer 17 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
Return values:
State of bit (1 or 0).

Definition at line 1276 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK ( void )

Check if Timer 1 break interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
Return values:
State of bit (1 or 0).

Definition at line 1061 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC ( void )

Check if Timer 1 capture compare interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
Return values:
State of bit (1 or 0).

Definition at line 1109 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU ( void )

Check if Timer 1 commutation interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
Return values:
State of bit (1 or 0).

Definition at line 1097 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG ( void )

Check if Timer 1 trigger interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
Return values:
State of bit (1 or 0).

Definition at line 1085 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD ( void )

Check if Timer 1 update interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
Return values:
State of bit (1 or 0).

Definition at line 1073 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2 ( void )

Check if Timer 2 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
Return values:
State of bit (1 or 0).

Definition at line 1121 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3 ( void )

Check if Timer 3 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
Return values:
State of bit (1 or 0).

Definition at line 1133 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM4 ( void )

Check if Timer 3 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE16 SR_TIM4_GLB LL_SYSCFG_IsActiveFlag_TIM4
Return values:
State of bit (1 or 0).

Definition at line 1145 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6 ( void )

Check if Timer 6 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
Return values:
State of bit (1 or 0).

Definition at line 1169 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7 ( void )

Check if Timer 7 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
Return values:
State of bit (1 or 0).

Definition at line 1193 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_UCPD1 ( void )

Check if UCPD1 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE8 SR_UCPD1 LL_SYSCFG_IsActiveFlag_UCPD1
Return values:
State of bit (1 or 0).

Definition at line 821 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_UCPD2 ( void )

Check if UCPD2 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE8 SR_UCPD2 LL_SYSCFG_IsActiveFlag_UCPD2
Return values:
State of bit (1 or 0).

Definition at line 833 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1 ( void )

Check if USART1 interrupt occurred or not, combined with EXTI line 25.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
Return values:
State of bit (1 or 0).

Definition at line 1383 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2 ( void )

Check if USART2 interrupt occurred or not, combined with EXTI line 26.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
Return values:
State of bit (1 or 0).

Definition at line 1395 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3 ( void )

Check if USART3 interrupt occurred or not, combined with EXTI line 28.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
Return values:
State of bit (1 or 0).

Definition at line 1419 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4 ( void )

Check if USART4 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4
Return values:
State of bit (1 or 0).

Definition at line 1431 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5 ( void )

Check if USART5 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5
Return values:
State of bit (1 or 0).

Definition at line 1455 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6 ( void )

Check if USART6 interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6
Return values:
State of bit (1 or 0).

Definition at line 1467 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USB ( void )

Check if USB interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE8 SR_USB LL_SYSCFG_IsActiveFlag_USB
Return values:
State of bit (1 or 0).

Definition at line 845 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG ( void )

Check if Window watchdog interrupt occurred or not.

Reference Manual to LL API cross reference:
SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
Return values:
State of bit (1 or 0).

Definition at line 522 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledClampingDiode ( uint32_t ConfigClampingDiode )

Indicates whether clamping diode(s) is(are) enabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_IsEnabledClampingDiode
SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_IsEnabledClampingDiode
SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_IsEnabledClampingDiode
SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_IsEnabledClampingDiode
SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_IsEnabledClampingDiode
SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_IsEnabledClampingDiode
SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_IsEnabledClampingDiode
SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_IsEnabledClampingDiode
Parameters:
ConfigClampingDiode This parameter can be a combination of the following values:
  • LL_SYSCFG_CFGR2_PA1_CDEN
  • LL_SYSCFG_CFGR2_PA3_CDEN
  • LL_SYSCFG_CFGR2_PA5_CDEN
  • LL_SYSCFG_CFGR2_PA6_CDEN
  • LL_SYSCFG_CFGR2_PA13_CDEN
  • LL_SYSCFG_CFGR2_PB0_CDEN
  • LL_SYSCFG_CFGR2_PB1_CDEN
  • LL_SYSCFG_CFGR2_PB2_CDEN
Return values:
None

Definition at line 1653 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal ( uint32_t Source )

Set IR Modulation Envelope signal source.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
Parameters:
Source This parameter can be one of the following values:
  • LL_SYSCFG_IR_MOD_TIM16
  • LL_SYSCFG_IR_MOD_USART1
  • LL_SYSCFG_IR_MOD_USART4
Return values:
None

Definition at line 355 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetIRPolarity ( uint32_t Polarity )

Set IR Output polarity.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 IR_POL LL_SYSCFG_SetIRPolarity
Parameters:
Polarity This parameter can be one of the following values:
  • LL_SYSCFG_IR_POL_INVERTED
  • LL_SYSCFG_IR_POL_NOT_INVERTED
Return values:
None

Definition at line 381 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetRemapMemory ( uint32_t Memory )

Set memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
Parameters:
Memory This parameter can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
Return values:
None

Definition at line 299 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs ( uint32_t Break )

Set connections to TIM1/15/16/17 Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
Parameters:
Break This parameter can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_PVD (*)
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY
  • LL_SYSCFG_TIMBREAK_LOCKUP
  • LL_SYSCFG_TIMBREAK_ECC
(*) value not defined in all devices
Return values:
None

Definition at line 1526 of file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DBGMCU

Functions
DBGMCU
SYSTEM Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.

Function Documentation

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBG_APB_FZ1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_LPTIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBG_APB_FZ1 DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_LPTIM2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP (*)
(*) value not defined in all devices
Return values:
None

Definition at line 1760 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBG_APB_FZ1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_LPTIM2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBG_APB_FZ1 DBG_LPTIM1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_LPTIM2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP (*)
(*) value not defined in all devices
Return values:
None

Definition at line 1796 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBG_APB_FZ2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM14_STOP
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
(*) value not defined in all devices
Return values:
None

Definition at line 1818 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
DBG_APB_FZ2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM14_STOP
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
(*) value not defined in all devices
Return values:
None

Definition at line 1840 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBG_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
Return values:
None

Definition at line 1724 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBG_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
Return values:
None

Definition at line 1704 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBG_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
Return values:
None

Definition at line 1714 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBG_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
Return values:
None

Definition at line 1694 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID ( void )

Return the device identifier.

Note:
For STM32G081xx devices, the device ID is 0x460
Reference Manual to LL API cross reference:
DBG_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFF

Definition at line 1673 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID ( void )

Return the device revision identifier.

Note:
This field indicates the revision of the device.
Reference Manual to LL API cross reference:
DBG_IDCODE REV_ID LL_DBGMCU_GetRevisionID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1684 of file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: VREFBUF

Functions
VREFBUF
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_VREFBUF_Enable (void)
Enable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_Disable (void)
Disable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_EnableHIZ (void)
Enable high impedance (VREF+pin is high impedance)
__STATIC_INLINE void | LL_VREFBUF_DisableHIZ (void)
Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
__STATIC_INLINE void | LL_VREFBUF_SetVoltageScaling (uint32_t Scale)
Set the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetVoltageScaling (void)
Get the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_IsVREFReady (void)
Check if Voltage reference buffer is ready.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetTrimming (void)
Get the trimming code for VREFBUF calibration.
__STATIC_INLINE void | LL_VREFBUF_SetTrimming (uint32_t Value)
Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)

Function Documentation

__STATIC_INLINE void LL_VREFBUF_Disable ( void )

Disable Internal voltage reference.

Reference Manual to LL API cross reference:
VREFBUF_CSR VREFBUF_CSR_ENVR LL_VREFBUF_Disable
Return values:
None

Definition at line 1868 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_DisableHIZ ( void )

Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)

Reference Manual to LL API cross reference:
VREFBUF_CSR VREFBUF_CSR_HIZ LL_VREFBUF_DisableHIZ
Return values:
None

Definition at line 1888 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_Enable ( void )

Enable Internal voltage reference.

Reference Manual to LL API cross reference:
VREFBUF_CSR VREFBUF_CSR_ENVR LL_VREFBUF_Enable
Return values:
None

Definition at line 1858 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_EnableHIZ ( void )

Enable high impedance (VREF+pin is high impedance)

Reference Manual to LL API cross reference:
VREFBUF_CSR VREFBUF_CSR_HIZ LL_VREFBUF_EnableHIZ
Return values:
None

Definition at line 1878 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming ( void )

Get the trimming code for VREFBUF calibration.

Reference Manual to LL API cross reference:
VREFBUF_CCR VREFBUF_CCR_TRIM LL_VREFBUF_GetTrimming
Return values:
Between 0 and 0x3F

Definition at line 1933 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling ( void )

Get the Voltage reference scale.

Reference Manual to LL API cross reference:
VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_GetVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_VREFBUF_VOLTAGE_SCALE0
  • LL_VREFBUF_VOLTAGE_SCALE1

Definition at line 1913 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady ( void )

Check if Voltage reference buffer is ready.

Reference Manual to LL API cross reference:
VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_IsVREFReady
Return values:
State of bit (1 or 0).

Definition at line 1923 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_SetTrimming ( uint32_t Value )

Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)

Note:
VrefBuf voltage scale is calibrated in production for each device, using voltage scale 1. This calibration value is loaded as default trimming value at device power up. This trimming value can be fine tuned for voltage scales 0 and 1 using this function.
Reference Manual to LL API cross reference:
VREFBUF_CCR VREFBUF_CCR_TRIM LL_VREFBUF_SetTrimming
Parameters:
Value Between 0 and 0x3F
Return values:
None

Definition at line 1949 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling ( uint32_t Scale )

Set the Voltage reference scale.

Reference Manual to LL API cross reference:
VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_SetVoltageScaling
Parameters:
Scale This parameter can be one of the following values:
  • LL_VREFBUF_VOLTAGE_SCALE0
  • LL_VREFBUF_VOLTAGE_SCALE1
Return values:
None

Definition at line 1901 of file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLASH

Functions
FLASH
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableInstCache (void)
Enable Instruction cache.
__STATIC_INLINE void | LL_FLASH_DisableInstCache (void)
Disable Instruction cache.
__STATIC_INLINE void | LL_FLASH_EnableInstCacheReset (void)
Enable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_DisableInstCacheReset (void)
Disable Instruction cache reset.

Function Documentation

__STATIC_INLINE void LL_FLASH_DisableInstCache ( void )

Disable Instruction cache.

Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_ICEN LL_FLASH_DisableInstCache
Return values:
None

Definition at line 2035 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableInstCacheReset ( void )

Disable Instruction cache reset.

Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_ICRST LL_FLASH_DisableInstCacheReset
Return values:
None

Definition at line 2056 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisablePrefetch ( void )

Disable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_DisablePrefetch
Return values:
None

Definition at line 2005 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableInstCache ( void )

Enable Instruction cache.

Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_ICEN LL_FLASH_EnableInstCache
Return values:
None

Definition at line 2025 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableInstCacheReset ( void )

Enable Instruction cache reset.

Note:
bit can be written only when the instruction cache is disabled
Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_ICRST LL_FLASH_EnableInstCacheReset
Return values:
None

Definition at line 2046 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnablePrefetch ( void )

Enable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_EnablePrefetch
Return values:
None

Definition at line 1995 of file stm32g0xx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetLatency ( void )

Get FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_GetLatency
Return values:
Returned value can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2

Definition at line 1985 of file stm32g0xx_ll_system.h.

Referenced by LL_SetFlashLatency().

__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled ( void )

Check if Prefetch buffer is enabled.

Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_IsPrefetchEnabled
Return values:
State of bit (1 or 0).

Definition at line 2015 of file stm32g0xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_SetLatency ( uint32_t Latency )

Set FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_SetLatency
Parameters:
Latency This parameter can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
Return values:
None

Definition at line 1972 of file stm32g0xx_ll_system.h.

Referenced by LL_SetFlashLatency().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Private functions. More...

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.

Detailed Description

Private functions.

Function Documentation

static ErrorStatus IC1Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 1.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1229 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC2Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 2.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1262 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC3Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 3.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1295 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC4Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 4.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1328 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus OC1Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 1.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 801 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH1(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC2Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 2.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 880 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH2(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC3Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 3.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 959 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH3(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC4Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 4.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1038 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH4(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC5Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 5.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 5 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1108 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH5(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC6Config | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 6.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 6 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1169 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH6(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Private Variables

Variables
TIM Private Variables
TIM

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Variable Documentation

const uint8_t OFFSET_TAB_CCMRx[] [static]
Initial value:
{
  0x00U,
  0x00U,
  0x00U,
  0x00U,
  0x04U,
  0x04U,
  0x04U,
  0x3CU,
  0x3CU
}

Definition at line 45 of file stm32g0xx_ll_tim.h.

const uint8_t SHIFT_TAB_CCxP[] [static]
Initial value:
{
  0U,
  2U,
  4U,
  6U,
  8U,
  10U,
  12U,
  16U,
  20U
}

Definition at line 84 of file stm32g0xx_ll_tim.h.

const uint8_t SHIFT_TAB_ICxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  0U
}

Definition at line 71 of file stm32g0xx_ll_tim.h.

const uint8_t SHIFT_TAB_OCxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  8U
}

Definition at line 58 of file stm32g0xx_ll_tim.h.

const uint8_t SHIFT_TAB_OISx[] [static]
Initial value:
{
  0U,
  1U,
  2U,
  3U,
  4U,
  5U,
  6U,
  8U,
  10U
}

Definition at line 97 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIM_POSITION_BRK_SOURCE
#define | TIMx_AF1_BKINP TIM1_AF1_BKINP
#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | DT_DELAY_1 ((uint8_t)0x7F)
#define | DT_DELAY_2 ((uint8_t)0x3F)
#define | DT_DELAY_3 ((uint8_t)0x1F)
#define | DT_DELAY_4 ((uint8_t)0x1F)
#define | DT_RANGE_1 ((uint8_t)0x00)
#define | DT_RANGE_2 ((uint8_t)0x80)
#define | DT_RANGE_3 ((uint8_t)0xC0)
#define | DT_RANGE_4 ((uint8_t)0xE0)
#define | OCREF_CLEAR_SELECT_Pos (16U)
Legacy definitions for compatibility purpose.
#define | OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)

Define Documentation

#define DT_DELAY_1 ((uint8_t)0x7F)

Definition at line 134 of file stm32g0xx_ll_tim.h.

#define DT_DELAY_2 ((uint8_t)0x3F)

Definition at line 135 of file stm32g0xx_ll_tim.h.

#define DT_DELAY_3 ((uint8_t)0x1F)

Definition at line 136 of file stm32g0xx_ll_tim.h.

#define DT_DELAY_4 ((uint8_t)0x1F)

Definition at line 137 of file stm32g0xx_ll_tim.h.

#define DT_RANGE_1 ((uint8_t)0x00)

Definition at line 140 of file stm32g0xx_ll_tim.h.

#define DT_RANGE_2 ((uint8_t)0x80)

Definition at line 141 of file stm32g0xx_ll_tim.h.

#define DT_RANGE_3 ((uint8_t)0xC0)

Definition at line 142 of file stm32g0xx_ll_tim.h.

#define DT_RANGE_4 ((uint8_t)0xE0)

Definition at line 143 of file stm32g0xx_ll_tim.h.

#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)

0x00010000

Definition at line 153 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_SetOCRefClearInputSource().

#define OCREF_CLEAR_SELECT_Pos (16U)

Legacy definitions for compatibility purpose.

Definition at line 152 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_SetOCRefClearInputSource().

#define TIM_POSITION_BRK_SOURCE
Value:
((Source == LL_TIM_BKIN_SOURCE_BKIN)    ? 0U :\
   (Source == LL_TIM_BKIN_SOURCE_BKCOMP1) ? 1U :\
   (Source == LL_TIM_BKIN_SOURCE_BKCOMP2) ? 2U :3U)

Definition at line 120 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_AF1_BKINP TIM1_AF1_BKINP

BRK BKIN input polarity

Definition at line 129 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL

TIMx ETR source selection

Definition at line 130 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_SetETRSource().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK_AFMODE(__VALUE__)
#define | IS_LL_TIM_BREAK2_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK2_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK2_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK2_AFMODE(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).

Define Documentation

#define IS_LL_TIM_ACTIVEINPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))

Definition at line 81 of file stm32g0xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))

Definition at line 181 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_AFMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
                                            || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))

Definition at line 178 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))

Definition at line 161 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
                                              || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))

Definition at line 158 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
                                           || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))

Definition at line 155 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_AFMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
                                           || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))

Definition at line 152 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))

Definition at line 135 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))

Definition at line 132 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_DISABLE) \
                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))

Definition at line 129 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_CLOCKDIVISION ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))

Definition at line 53 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_COUNTERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))

Definition at line 47 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_ENCODERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))

Definition at line 111 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init().

#define IS_LL_TIM_IC_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))

Definition at line 90 of file stm32g0xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_IC_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))

Definition at line 107 of file stm32g0xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), and IC4Config().

#define IS_LL_TIM_IC_POLARITY_ENCODER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))

Definition at line 115 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_ICPSC ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ICPSC_DIV1) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))

Definition at line 85 of file stm32g0xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_LOCK_LEVEL ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))

Definition at line 124 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OCIDLESTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))

Definition at line 78 of file stm32g0xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 57 of file stm32g0xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))

Definition at line 75 of file stm32g0xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCSTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))

Definition at line 72 of file stm32g0xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OSSI_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSI_DISABLE) \
                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))

Definition at line 121 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OSSR_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSR_DISABLE) \
                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))

Definition at line 118 of file stm32g0xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define TIM_CALC_DTS | ( | __TIMCLK__,
 |  | __CKD__
 | ) |
Value:
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))

Calculate the deadtime sampling period(in ps).

Parameters:
__TIMCLK__ timer input clock frequency (in Hz).
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
none

Definition at line 193 of file stm32g0xx_ll_tim.h.

#define TIM_GET_CHANNEL_INDEX ( __CHANNEL__ )
Value:
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)

Convert channel id into channel index.

Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
none

Definition at line 175 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_IC_Config(), LL_TIM_IC_GetActiveInput(), LL_TIM_IC_GetFilter(), LL_TIM_IC_GetPolarity(), LL_TIM_IC_GetPrescaler(), LL_TIM_IC_SetActiveInput(), LL_TIM_IC_SetFilter(), LL_TIM_IC_SetPolarity(), LL_TIM_IC_SetPrescaler(), LL_TIM_OC_ConfigOutput(), LL_TIM_OC_DisableClear(), LL_TIM_OC_DisableFast(), LL_TIM_OC_DisablePreload(), LL_TIM_OC_EnableClear(), LL_TIM_OC_EnableFast(), LL_TIM_OC_EnablePreload(), LL_TIM_OC_GetIdleState(), LL_TIM_OC_GetMode(), LL_TIM_OC_GetPolarity(), LL_TIM_OC_IsEnabledClear(), LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload(), LL_TIM_OC_SetIdleState(), LL_TIM_OC_SetMode(), and LL_TIM_OC_SetPolarity().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_TIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Time Base configuration structure definition. More...

#include <stm32g0xx_ll_tim.h>

Data Fields

uint16_t | Prescaler
uint32_t | CounterMode
uint32_t | Autoreload
uint32_t | ClockDivision
uint32_t | RepetitionCounter

Detailed Description

TIM Time Base configuration structure definition.

Definition at line 211 of file stm32g0xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_InitTypeDef::Autoreload

Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetAutoReload().

Definition at line 225 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of Clock Division.

This feature can be modified afterwards using unitary function LL_TIM_SetClockDivision().

Definition at line 234 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of Counter Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetCounterMode().

Definition at line 219 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint16_t LL_TIM_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetPrescaler().

Definition at line 213 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetRepetitionCounter().

Definition at line 240 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_tim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_OC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Output Compare configuration structure definition. More...

#include <stm32g0xx_ll_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | OCState
uint32_t | OCNState
uint32_t | CompareValue
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare configuration structure definition.

Definition at line 258 of file stm32g0xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_OC_InitTypeDef::CompareValue

Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).

Definition at line 278 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 297 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCMode

Specifies the output mode. This parameter can be a value of Output Configuration Mode.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetMode().

Definition at line 260 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 303 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 290 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNState

Specifies the TIM complementary Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 272 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 284 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCState

Specifies the TIM Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 266 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_tim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_IC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Input Capture configuration structure definition. More...

#include <stm32g0xx_ll_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICActiveInput
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture configuration structure definition.

Definition at line 314 of file stm32g0xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_IC_InitTypeDef::ICActiveInput

Specifies the input. This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 323 of file stm32g0xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 335 of file stm32g0xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 317 of file stm32g0xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 329 of file stm32g0xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_tim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_TIM_ENCODER_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_ENCODER_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Encoder interface configuration structure definition. More...

#include <stm32g0xx_ll_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1ActiveInput
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2ActiveInput
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder interface configuration structure definition.

Definition at line 346 of file stm32g0xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_ENCODER_InitTypeDef::EncoderMode

Specifies the encoder resolution (x2 or x4). This parameter can be a value of Encoder Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetEncoderMode().

Definition at line 348 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput

Specifies the TI1 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 360 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 372 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 354 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 366 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput

Specifies the TI2 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 384 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Filter

Specifies the TI2 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 396 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Polarity

Specifies the active edge of TI2 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 378 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Prescaler

Specifies the TI2 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 390 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_tim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_TIM_HALLSENSOR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_HALLSENSOR_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Hall sensor interface configuration structure definition. More...

#include <stm32g0xx_ll_tim.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | CommutationDelay

Detailed Description

TIM Hall sensor interface configuration structure definition.

Definition at line 407 of file stm32g0xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay

Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCH2().

Definition at line 431 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 424 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 410 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 416 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_tim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_TIM_BDTR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_BDTR_InitTypeDef Struct Reference
TIM Exported Init structure

BDTR (Break and Dead Time) structure definition. More...

#include <stm32g0xx_ll_tim.h>

Data Fields

uint32_t | OSSRState
uint32_t | OSSIState
uint32_t | LockLevel
uint8_t | DeadTime
uint16_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | BreakAFMode
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | Break2AFMode
uint32_t | AutomaticOutput

Detailed Description

BDTR (Break and Dead Time) structure definition.

Definition at line 443 of file stm32g0xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_BDTR_InitTypeDef::AutomaticOutput

Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of Automatic output enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableAutomaticOutput() or LL_TIM_DisableAutomaticOutput()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 555 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2AFMode

Specifies the alternate function mode of the break2 input. This parameter can be a value of BREAK2 AF MODE

This feature can be modified afterwards using unitary functions LL_TIM_ConfigBRK2()

Note:
Bidirectional break input is only supported by advanced timers instances.
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 544 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2Filter

Specifies the TIM Break2 Filter. This parameter can be a value of BREAK2 FILTER

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 535 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2Polarity

Specifies the TIM Break2 Input pin polarity. This parameter can be a value of BREAK2 POLARITY

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 526 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2State

Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of Break2 Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK2() or LL_TIM_DisableBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 517 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakAFMode

Specifies the alternate function mode of the break input. This parameter can be a value of BREAK AF MODE

This feature can be modified afterwards using unitary functions LL_TIM_ConfigBRK()

Note:
Bidirectional break input is only supported by advanced timers instances.
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 506 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakFilter

Specifies the TIM Break Filter. This parameter can be a value of break filter

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 497 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakPolarity

Specifies the TIM Break Input pin polarity. This parameter can be a value of break polarity

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 488 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint16_t LL_TIM_BDTR_InitTypeDef::BreakState

Specifies whether the TIM Break input is enabled or not. This parameter can be a value of Break Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK() or LL_TIM_DisableBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 479 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint8_t LL_TIM_BDTR_InitTypeDef::DeadTime

Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetDeadTime()

Note:
This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed.

Definition at line 469 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::LockLevel

Specifies the LOCK level parameters. This parameter can be a value of Lock Level

Note:
The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Definition at line 463 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSIState

Specifies the Off-State used in Idle state. This parameter can be a value of OSSI

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 454 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSRState

Specifies the Off-State selection used in Run mode. This parameter can be a value of OSSR

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 445 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_tim.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
TIM Exported Constants

Flags defines which can be used with LL_TIM_ReadReg function. More...

Defines

#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF

Detailed Description

Flags defines which can be used with LL_TIM_ReadReg function.

Define Documentation

#define LL_TIM_SR_B2IF TIM_SR_B2IF

Second break interrupt flag

Definition at line 589 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_BIF TIM_SR_BIF

Break interrupt flag

Definition at line 588 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC1IF TIM_SR_CC1IF

Capture/compare 1 interrupt flag

Definition at line 580 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC1OF TIM_SR_CC1OF

Capture/Compare 1 overcapture flag

Definition at line 590 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC2IF TIM_SR_CC2IF

Capture/compare 2 interrupt flag

Definition at line 581 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC2OF TIM_SR_CC2OF

Capture/Compare 2 overcapture flag

Definition at line 591 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC3IF TIM_SR_CC3IF

Capture/compare 3 interrupt flag

Definition at line 582 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC3OF TIM_SR_CC3OF

Capture/Compare 3 overcapture flag

Definition at line 592 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC4IF TIM_SR_CC4IF

Capture/compare 4 interrupt flag

Definition at line 583 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC4OF TIM_SR_CC4OF

Capture/Compare 4 overcapture flag

Definition at line 593 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC5IF TIM_SR_CC5IF

Capture/compare 5 interrupt flag

Definition at line 584 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_CC6IF TIM_SR_CC6IF

Capture/compare 6 interrupt flag

Definition at line 585 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_COMIF TIM_SR_COMIF

COM interrupt flag

Definition at line 586 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_SBIF TIM_SR_SBIF

System Break interrupt flag

Definition at line 594 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_TIF TIM_SR_TIF

Trigger interrupt flag

Definition at line 587 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SR_UIF TIM_SR_UIF

Update interrupt flag

Definition at line 579 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Break Enable

Defines
Break Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Define Documentation

#define LL_TIM_BREAK_DISABLE 0x00000000U

Break function disabled

Definition at line 603 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Break function enabled

Definition at line 604 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Break2 Enable

Defines
Break2 Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_DISABLE 0x00000000U
#define | LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Define Documentation

#define LL_TIM_BREAK2_DISABLE 0x00000000U

Break2 function disabled

Definition at line 612 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Break2 function enabled

Definition at line 613 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Automatic output enable

Defines
Automatic output enable
TIM Exported Constants

Defines

#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 621 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event

Definition at line 622 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
TIM Exported Constants

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. More...

Defines

#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE

Detailed Description

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Define Documentation

#define LL_TIM_DIER_BIE TIM_DIER_BIE

Break interrupt enable

Definition at line 639 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE

Capture/compare 1 interrupt enable

Definition at line 633 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE

Capture/compare 2 interrupt enable

Definition at line 634 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE

Capture/compare 3 interrupt enable

Definition at line 635 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE

Capture/compare 4 interrupt enable

Definition at line 636 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DIER_COMIE TIM_DIER_COMIE

COM interrupt enable

Definition at line 637 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DIER_TIE TIM_DIER_TIE

Trigger interrupt enable

Definition at line 638 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DIER_UIE TIM_DIER_UIE

Update interrupt enable

Definition at line 632 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Update Source

Defines
Update Source
TIM Exported Constants

Defines

#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Define Documentation

#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Only counter overflow/underflow generates an update request

Definition at line 648 of file stm32g0xx_ll_tim.h.

#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U

Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request

Definition at line 647 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: One Pulse Mode

Defines
One Pulse Mode
TIM Exported Constants

Defines

#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Define Documentation

#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Counter is not stopped at update event

Definition at line 657 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM

Counter stops counting at the next update event

Definition at line 656 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Counter Mode

Defines
Counter Mode
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

Define Documentation

#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down.

Definition at line 667 of file stm32g0xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up

Definition at line 668 of file stm32g0xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down.

Definition at line 669 of file stm32g0xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as downcounter

Definition at line 666 of file stm32g0xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_UP 0x00000000U

Counter used as upcounter

Definition at line 665 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

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STM32G0C1xx HAL User Manual: Clock Division

Defines
Clock Division
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U

tDTS=tCK_INT

Definition at line 677 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

tDTS=2*tCK_INT

Definition at line 678 of file stm32g0xx_ll_tim.h.

#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

tDTS=4*tCK_INT

Definition at line 679 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Counter Direction

Defines
Counter Direction
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Define Documentation

#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Timer counter counts down

Definition at line 688 of file stm32g0xx_ll_tim.h.

#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U

Timer counter counts up

Definition at line 687 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Capture Compare Update Source

Defines
Capture Compare Update Source
TIM Exported Constants

Defines

#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Define Documentation

#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI)

Definition at line 697 of file stm32g0xx_ll_tim.h.

#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U

Capture/compare control bits are updated by setting the COMG bit only

Definition at line 696 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Capture Compare DMA Request

Defines
Capture Compare DMA Request
TIM Exported Constants

Defines

#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define LL_TIM_CCDMAREQUEST_CC 0x00000000U

CCx DMA request sent when CCx event occurs

Definition at line 705 of file stm32g0xx_ll_tim.h.

#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 706 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Lock Level

Defines
Lock Level
TIM Exported Constants

Defines

#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 715 of file stm32g0xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 716 of file stm32g0xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 717 of file stm32g0xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF - No bit is write protected

Definition at line 714 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32G0C1xx HAL User Manual: Channel

Defines
Channel
TIM Exported Constants

Defines

#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Define Documentation

#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E

Timer input/output channel 1

Definition at line 725 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE

Timer complementary output channel 1

Definition at line 726 of file stm32g0xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E

Timer input/output channel 2

Definition at line 727 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE

Timer complementary output channel 2

Definition at line 728 of file stm32g0xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E

Timer input/output channel 3

Definition at line 729 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE

Timer complementary output channel 3

Definition at line 730 of file stm32g0xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Timer input/output channel 4

Definition at line 731 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E

Timer output channel 5

Definition at line 732 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Timer output channel 6

Definition at line 733 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

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STM32G0C1xx HAL User Manual: Output Configuration State

Defines
Output Configuration State
TIM Exported Constants

Defines

#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define LL_TIM_OCSTATE_DISABLE 0x00000000U

OCx is not active

Definition at line 742 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

OCx signal is output on the corresponding output pin

Definition at line 743 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Output Configuration Mode

Defines
Output Configuration Mode
TIM Exported Constants

Defines

#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Define Documentation

#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

OCyREF is forced high on compare match

Definition at line 753 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 764 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Asymmetric PWM mode 2

Definition at line 765 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 762 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 763 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

OCyREF is forced high

Definition at line 757 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

OCyREF is forced low

Definition at line 756 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_FROZEN 0x00000000U

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level

Definition at line 752 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

OCyREF is forced low on compare match

Definition at line 754 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.

Definition at line 758 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive

Definition at line 759 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 760 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 761 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

OCyREF toggles on compare match

Definition at line 755 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Output Configuration Polarity

Defines
Output Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define LL_TIM_OCPOLARITY_HIGH 0x00000000U

OCxactive high

Definition at line 773 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

OCxactive low

Definition at line 774 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Output Configuration Idle State

Defines
Output Configuration Idle State
TIM Exported Constants

Defines

#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

Define Documentation

#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

OCx=1 (after a dead-time if OC is implemented) when MOE=0

Definition at line 783 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCIDLESTATE_LOW 0x00000000U

OCx=0 (after a dead-time if OC is implemented) when MOE=0

Definition at line 782 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

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STM32G0C1xx HAL User Manual: GROUPCH5

Defines
GROUPCH5
TIM Exported Constants

Defines

#define | LL_TIM_GROUPCH5_NONE 0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

Define Documentation

#define LL_TIM_GROUPCH5_NONE 0x00000000U

No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC

Definition at line 791 of file stm32g0xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1

OC1REFC is the logical AND of OC1REFC and OC5REF

Definition at line 792 of file stm32g0xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2

OC2REFC is the logical AND of OC2REFC and OC5REF

Definition at line 793 of file stm32g0xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

OC3REFC is the logical AND of OC3REFC and OC5REF

Definition at line 794 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Active Input Selection

Defines
Active Input Selection
TIM Exported Constants

Defines

#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

Define Documentation

#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)

ICx is mapped on TIx

Definition at line 802 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)

ICx is mapped on TIy

Definition at line 803 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

ICx is mapped on TRC

Definition at line 804 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

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STM32G0C1xx HAL User Manual: Input Configuration Prescaler

Defines
Input Configuration Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Define Documentation

#define LL_TIM_ICPSC_DIV1 0x00000000U

No prescaler, capture is done each time an edge is detected on the capture input

Definition at line 812 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)

Capture is done once every 2 events

Definition at line 813 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)

Capture is done once every 4 events

Definition at line 814 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Capture is done once every 8 events

Definition at line 815 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Input Configuration Filter

Defines
Input Configuration Filter
TIM Exported Constants

Defines

#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

Define Documentation

#define LL_TIM_IC_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 823 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/16, N=5

Definition at line 833 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/16, N=6

Definition at line 834 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)

fSAMPLING=fDTS/16, N=8

Definition at line 835 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)

fSAMPLING=fCK_INT, N=2

Definition at line 824 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)

fSAMPLING=fCK_INT, N=4

Definition at line 825 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fCK_INT, N=8

Definition at line 826 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)

fSAMPLING=fDTS/2, N=6

Definition at line 827 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/2, N=8

Definition at line 828 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/32, N=5

Definition at line 836 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/32, N=6

Definition at line 837 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

fSAMPLING=fDTS/32, N=8

Definition at line 838 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/4, N=6

Definition at line 829 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/4, N=8

Definition at line 830 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)

fSAMPLING=fDTS/8, N=6

Definition at line 831 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/8, N=8

Definition at line 832 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Input Configuration Polarity

Defines
Input Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted

Definition at line 848 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P

The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

Definition at line 847 of file stm32g0xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_RISING 0x00000000U

The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

Definition at line 846 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clock Source

Defines
Clock Source
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Define Documentation

#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Counter counts at each rising or falling edge on a selected input

Definition at line 857 of file stm32g0xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Counter counts at each rising or falling edge on the external trigger input ETR

Definition at line 858 of file stm32g0xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U

The timer is clocked by the internal clock provided from the RCC

Definition at line 856 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Encoder Mode

Defines
Encoder Mode
TIM Exported Constants

Defines

#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0

Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 866 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit().

#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1

Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level

Definition at line 867 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input

Definition at line 868 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Trigger Output

Defines
Trigger Output
TIM Exported Constants

Defines

#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

CC1 capture or a compare match is used as trigger output

Definition at line 879 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0

Counter Enable signal (CNT_EN) is used as trigger output

Definition at line 877 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output

Definition at line 880 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output

Definition at line 881 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output

Definition at line 882 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output

Definition at line 883 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output

Definition at line 876 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output

Definition at line 878 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Trigger Output 2

Defines
Trigger Output 2
TIM Exported Constants

Defines

#define | LL_TIM_TRGO2_RESET 0x00000000U
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

CC1 capture or a compare match is used as trigger output 2

Definition at line 894 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

Counter Enable signal (CNT_EN) is used as trigger output 2

Definition at line 892 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2

OC1REF signal is used as trigger output 2

Definition at line 895 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output 2

Definition at line 896 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output 2

Definition at line 897 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output 2

Definition at line 898 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 904 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges are used as trigger output 2

Definition at line 903 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges are used as trigger output 2

Definition at line 901 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3

OC5REF signal is used as trigger output 2

Definition at line 899 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 906 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges are used as trigger output 2

Definition at line 905 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output 2

Definition at line 900 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges are used as trigger output 2

Definition at line 902 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output 2

Definition at line 891 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output 2

Definition at line 893 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Slave Mode

Defines
Slave Mode
TIM Exported Constants

Defines

#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Define Documentation

#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter

Definition at line 918 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U

Slave mode disabled

Definition at line 914 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high

Definition at line 916 of file stm32g0xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

Definition at line 915 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode - The counter starts at a rising edge of the trigger TRGI

Definition at line 917 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: Trigger Selection

Defines
Trigger Selection
TIM Exported Constants

Defines

#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Define Documentation

#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Filtered external Trigger (ETRF) is used as trigger input

Definition at line 936 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0) is used as trigger input

Definition at line 926 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1) is used as trigger input

Definition at line 927 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2) is used as trigger input

Definition at line 928 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3) is used as trigger input

Definition at line 929 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Internal Trigger 7 (ITR7) is used as trigger input

Definition at line 931 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED) is used as trigger input

Definition at line 933 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)

Filtered Timer Input 1 (TI1FP1) is used as trigger input

Definition at line 934 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)

Filtered Timer Input 2 (TI12P2) is used as trigger input

Definition at line 935 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: External Trigger Polarity

Defines
External Trigger Polarity
TIM Exported Constants

Defines

#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

Define Documentation

#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

ETR is inverted, active at low level or falling edge

Definition at line 945 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U

ETR is non-inverted, active at high level or rising edge

Definition at line 944 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: External Trigger Prescaler

Defines
External Trigger Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U

ETR prescaler OFF

Definition at line 953 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR frequency is divided by 2

Definition at line 954 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR frequency is divided by 4

Definition at line 955 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

ETR frequency is divided by 8

Definition at line 956 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: External Trigger Filter

Defines
External Trigger Filter
TIM Exported Constants

Defines

#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

Define Documentation

#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 964 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/16, N=6

Definition at line 974 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=8

Definition at line 975 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)

fSAMPLING=fDTS/16, N=5

Definition at line 976 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0

fSAMPLING=fCK_INT, N=2

Definition at line 965 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1

fSAMPLING=fCK_INT, N=4

Definition at line 966 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fCK_INT, N=8

Definition at line 967 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2

fSAMPLING=fDTS/2, N=6

Definition at line 968 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/2, N=8

Definition at line 969 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/32, N=5

Definition at line 977 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/32, N=6

Definition at line 978 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

fSAMPLING=fDTS/32, N=8

Definition at line 979 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/4, N=6

Definition at line 970 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/4, N=8

Definition at line 971 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3

fSAMPLING=fDTS/8, N=8

Definition at line 972 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=5

Definition at line 973 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: External Trigger Source

Defines
External Trigger Source
TIM Exported Constants

Defines

#define | LL_TIM_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)
#define | LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2
#define | LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_ETRSOURCE_MCO TIM1_AF1_ETRSEL_2
#define | LL_TIM_ETRSOURCE_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)

Define Documentation

#define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to ADC1 analog watchdog 1

Definition at line 995 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2

ETR input is connected to ADC1 analog watchdog 2

Definition at line 996 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)

ETR input is connected to ADC1 analog watchdog 3

Definition at line 997 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 989 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 990 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)

ETR input is connected to COMP3_OUT

Definition at line 993 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_SetETRSource().

#define LL_TIM_ETRSOURCE_GPIO 0x00000000U

ETR input is connected to GPIO

Definition at line 987 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

ETR input is connected to LSE

Definition at line 998 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_MCO TIM1_AF1_ETRSEL_2

ETR input is connected to MCO

Definition at line 999 of file stm32g0xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)

ETR input is connected to MCO2

Definition at line 1000 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: break polarity

Defines
break polarity
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 1009 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 1008 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32G0C1xx HAL User Manual: break filter

Defines
break filter
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U

Define Documentation

#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U

No filter, BRK acts asynchronously

Definition at line 1017 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U

fSAMPLING=fDTS/16, N=5

Definition at line 1027 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U

fSAMPLING=fDTS/16, N=6

Definition at line 1028 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U

fSAMPLING=fDTS/16, N=8

Definition at line 1029 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U

fSAMPLING=fCK_INT, N=2

Definition at line 1018 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U

fSAMPLING=fCK_INT, N=4

Definition at line 1019 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U

fSAMPLING=fCK_INT, N=8

Definition at line 1020 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U

fSAMPLING=fDTS/2, N=6

Definition at line 1021 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U

fSAMPLING=fDTS/2, N=8

Definition at line 1022 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U

fSAMPLING=fDTS/32, N=5

Definition at line 1030 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U

fSAMPLING=fDTS/32, N=6

Definition at line 1031 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U

fSAMPLING=fDTS/32, N=8

Definition at line 1032 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U

fSAMPLING=fDTS/4, N=6

Definition at line 1023 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U

fSAMPLING=fDTS/4, N=8

Definition at line 1024 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U

fSAMPLING=fDTS/8, N=6

Definition at line 1025 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U

fSAMPLING=fDTS/8, N=8

Definition at line 1026 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: BREAK2 POLARITY

Defines
BREAK2 POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 1041 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U

Break input BRK2 is active low

Definition at line 1040 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32G0C1xx HAL User Manual: BREAK2 FILTER

Defines
BREAK2 FILTER
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U

Define Documentation

#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U

No filter, BRK acts asynchronously

Definition at line 1049 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U

fSAMPLING=fDTS/16, N=5

Definition at line 1059 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U

fSAMPLING=fDTS/16, N=6

Definition at line 1060 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U

fSAMPLING=fDTS/16, N=8

Definition at line 1061 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U

fSAMPLING=fCK_INT, N=2

Definition at line 1050 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U

fSAMPLING=fCK_INT, N=4

Definition at line 1051 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U

fSAMPLING=fCK_INT, N=8

Definition at line 1052 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U

fSAMPLING=fDTS/2, N=6

Definition at line 1053 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U

fSAMPLING=fDTS/2, N=8

Definition at line 1054 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U

fSAMPLING=fDTS/32, N=5

Definition at line 1062 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U

fSAMPLING=fDTS/32, N=6

Definition at line 1063 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U

fSAMPLING=fDTS/32, N=8

Definition at line 1064 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U

fSAMPLING=fDTS/4, N=6

Definition at line 1055 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U

fSAMPLING=fDTS/4, N=8

Definition at line 1056 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U

fSAMPLING=fDTS/8, N=6

Definition at line 1057 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U

fSAMPLING=fDTS/8, N=8

Definition at line 1058 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: OSSI

Defines
OSSI
TIM Exported Constants

Defines

#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

Define Documentation

#define LL_TIM_OSSI_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1072 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime

Definition at line 1073 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: OSSR

Defines
OSSR
TIM Exported Constants

Defines

#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

Define Documentation

#define LL_TIM_OSSR_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1081 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1

Definition at line 1082 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: BREAK INPUT

Defines
BREAK INPUT
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_INPUT_BKIN 0x00000000U
#define | LL_TIM_BREAK_INPUT_BKIN2 0x00000004U

Define Documentation

#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U

TIMx_BKIN input

Definition at line 1090 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U

TIMx_BKIN2 input

Definition at line 1091 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: BKIN SOURCE

Defines
BKIN SOURCE
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E
#define | LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E

Define Documentation

#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E

internal signal: COMP1 output

Definition at line 1101 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E

internal signal: COMP2 output

Definition at line 1102 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E

internal signal: COMP3 output

Definition at line 1105 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE

BKIN input from AF controller

Definition at line 1099 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: BKIN POLARITY

Defines
BKIN POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP
#define | LL_TIM_BKIN_POLARITY_HIGH 0x00000000U

Define Documentation

#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U

BRK BKIN input is active high

Definition at line 1115 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP

BRK BKIN input is active low

Definition at line 1114 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: BREAK AF MODE

Defines
BREAK AF MODE
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_AFMODE_INPUT 0x00000000U
#define | LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID

Define Documentation

#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID

Break input BRK in bidirectional mode

Definition at line 1124 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U

Break input BRK in input mode

Definition at line 1123 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: BREAK2 AF MODE

Defines
BREAK2 AF MODE
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U
#define | LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID

Define Documentation

#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID

Break2 input BRK2 in bidirectional mode

Definition at line 1133 of file stm32g0xx_ll_tim.h.

#define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U

Break2 input BRK2 in input mode

Definition at line 1132 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32G0C1xx HAL User Manual: DMA Burst Base Address

Defines
DMA Burst Base Address
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)
#define | LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

Define Documentation

#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)

TIMx_AF1 register is the DMA base address for DMA burst

Definition at line 1163 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_AF2 register is the DMA base address for DMA burst

Definition at line 1164 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_ARR register is the DMA base address for DMA burst

Definition at line 1152 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)

TIMx_BDTR register is the DMA base address for DMA burst

Definition at line 1158 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3

TIMx_CCER register is the DMA base address for DMA burst

Definition at line 1149 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCMR1 register is the DMA base address for DMA burst

Definition at line 1147 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCMR2 register is the DMA base address for DMA burst

Definition at line 1148 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCMR3 register is the DMA base address for DMA burst

Definition at line 1160 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCR1 register is the DMA base address for DMA burst

Definition at line 1154 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR2 register is the DMA base address for DMA burst

Definition at line 1155 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR3 register is the DMA base address for DMA burst

Definition at line 1156 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4

TIMx_CCR4 register is the DMA base address for DMA burst

Definition at line 1157 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR5 register is the DMA base address for DMA burst

Definition at line 1161 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR6 register is the DMA base address for DMA burst

Definition at line 1162 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_CNT register is the DMA base address for DMA burst

Definition at line 1150 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U

TIMx_CR1 register is the DMA base address for DMA burst

Definition at line 1141 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0

TIMx_CR2 register is the DMA base address for DMA burst

Definition at line 1142 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_DIER register is the DMA base address for DMA burst

Definition at line 1144 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_EGR register is the DMA base address for DMA burst

Definition at line 1146 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)

TIMx_OR1 register is the DMA base address for DMA burst

Definition at line 1159 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_PSC register is the DMA base address for DMA burst

Definition at line 1151 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)

TIMx_RCR register is the DMA base address for DMA burst

Definition at line 1153 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1

TIMx_SMCR register is the DMA base address for DMA burst

Definition at line 1143 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2

TIMx_SR register is the DMA base address for DMA burst

Definition at line 1145 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_TISEL register is the DMA base address for DMA burst

Definition at line 1165 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: DMA Burst Length

Defines
DMA Burst Length
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Define Documentation

#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Transfer is done to 10 registers starting from the DMA burst base address

Definition at line 1182 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)

Transfer is done to 11 registers starting from the DMA burst base address

Definition at line 1183 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 12 registers starting from the DMA burst base address

Definition at line 1184 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)

Transfer is done to 13 registers starting from the DMA burst base address

Definition at line 1185 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 14 registers starting from the DMA burst base address

Definition at line 1186 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 15 registers starting from the DMA burst base address

Definition at line 1187 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 16 registers starting from the DMA burst base address

Definition at line 1188 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4

Transfer is done to 17 registers starting from the DMA burst base address

Definition at line 1189 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Transfer is done to 18 registers starting from the DMA burst base address

Definition at line 1190 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U

Transfer is done to 1 register starting from the DMA burst base address

Definition at line 1173 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0

Transfer is done to 2 registers starting from the DMA burst base address

Definition at line 1174 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1

Transfer is done to 3 registers starting from the DMA burst base address

Definition at line 1175 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 4 registers starting from the DMA burst base address

Definition at line 1176 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2

Transfer is done to 5 registers starting from the DMA burst base address

Definition at line 1177 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 6 registers starting from the DMA burst base address

Definition at line 1178 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 7 registers starting from the DMA burst base address

Definition at line 1179 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 1 registers starting from the DMA burst base address

Definition at line 1180 of file stm32g0xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3

Transfer is done to 9 registers starting from the DMA burst base address

Definition at line 1181 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM1 Timer Input Ch1 Remap

Defines
TIM1 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

Define Documentation

#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM1 input 1 is connected to COMP1_OUT

Definition at line 1200 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U

TIM1 input 1 is connected to GPIO

Definition at line 1198 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM1 Timer Input Ch2 Remap

Defines
TIM1 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM1_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

Define Documentation

#define LL_TIM_TIM1_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

TIM1 input 2 is connected to COMP2_OUT

Definition at line 1211 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U

TIM1 input 2 is connected to GPIO

Definition at line 1209 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM1 Timer Input Ch3 Remap

Defines
TIM1 Timer Input Ch3 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM1_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

Define Documentation

#define LL_TIM_TIM1_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

TIM1 input 3 is connected to COMP3_OUT

Definition at line 1222 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM1_TI3_RMP_GPIO 0x00000000U

TIM1 input 3 is connected to GPIO

Definition at line 1220 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM2 Timer Input Ch1 Remap

Defines
TIM2 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

Define Documentation

#define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM2 input 1 is connected to COMP1_OUT

Definition at line 1233 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U

TIM2 input 1 is connected to GPIO

Definition at line 1232 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM2 Timer Input Ch2 Remap

Defines
TIM2 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

Define Documentation

#define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

TIM2 input 2 is connected to COMP2_OUT

Definition at line 1242 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U

TIM2 input 2 is connected to GPIO

Definition at line 1241 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM2 Timer Input Ch3 Remap

Defines
TIM2 Timer Input Ch3 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

Define Documentation

#define LL_TIM_TIM2_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

TIM2 input 3 is connected to COMP3_OUT

Definition at line 1252 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U

TIM2 input 3 is connected to GPIO

Definition at line 1250 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM3 Timer Input Ch1 Remap

Defines
TIM3 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

Define Documentation

#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM3 input 1 is connected to COMP1_OUT

Definition at line 1264 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U

TIM3 input 1 is connected to GPIO

Definition at line 1262 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM3 Timer Input Ch2 Remap

Defines
TIM3 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

Define Documentation

#define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

TIM3 input 2 is connected to COMP2_OUT

Definition at line 1275 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U

TIM3 input 2 is connected to GPIO

Definition at line 1273 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM3 Timer Input Ch3 Remap

Defines
TIM3 Timer Input Ch3 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

Define Documentation

#define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

TIM3 input 3 is connected to COMP3_OUT

Definition at line 1286 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U

TIM3 input 3 is connected to GPIO

Definition at line 1284 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM4 Timer Input Ch1 Remap

Defines
TIM4 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

Define Documentation

#define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0

TIM4 input 1 is connected to COMP1_OUT

Definition at line 1298 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U

TIM4 input 1 is connected to GPIO

Definition at line 1296 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM4 Timer Input Ch2 Remap

Defines
TIM4 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

Define Documentation

#define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0

TIM4 input 2 is connected to COMP2_OUT

Definition at line 1309 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U

TIM4 input 2 is connected to GPIO

Definition at line 1307 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM4 Timer Input Ch3 Remap

Defines
TIM4 Timer Input Ch3 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

Define Documentation

#define LL_TIM_TIM4_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0

TIM4 input 3 is connected to COMP3_OUT

Definition at line 1320 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U

TIM4 input 3 is connected to GPIO

Definition at line 1318 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM14 Timer Input Ch1 Remap

Defines
TIM14 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
#define | LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2

Define Documentation

#define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U

TIM14 input 1 is connected to GPIO

Definition at line 1330 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1

TIM14 input 1 is connected to HSE/32 clock

Definition at line 1332 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)

TIM14 input 1 is connected to MCO

Definition at line 1333 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2

TIM14 input 1 is connected to MCO2

Definition at line 1334 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0

TIM14 input 1 is connected to RTC clock

Definition at line 1331 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM15 Timer Input Ch1 Remap

Defines
TIM15 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1

Define Documentation

#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U

TIM15 input 1 is connected to GPIO

Definition at line 1343 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0

TIM15 input 1 is connected to TIM2 input 1

Definition at line 1345 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1

TIM15 input 1 is connected to TIM3 input 1

Definition at line 1348 of file stm32g0xx_ll_tim.h.

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STM32G0C1xx HAL User Manual: TIM15 Timer Input Ch2 Remap

Defines
TIM15 Timer Input Ch2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1

Define Documentation

#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U

TIM15 input 2 is connected to GPIO

Definition at line 1359 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0

TIM15 input 2 is connected to TIM2 input 2

Definition at line 1361 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1

TIM15 input 2 is connected to TIM3 input 2

Definition at line 1364 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM16 Timer Input Ch1 Remap

Defines
TIM16 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM16_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
#define | LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2

Define Documentation

#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U

TIM16 input 1 is connected to GPIO

Definition at line 1374 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1

TIM16 input 1 is connected to LSE

Definition at line 1376 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0

TIM16 input 1 is connected to LSI

Definition at line 1375 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2

TIM16 input 1 is connected to MCO2

Definition at line 1378 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)

TIM16 input 1 is connected to RTC_WAKEUP

Definition at line 1377 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM17 Timer Input Ch1 Remap

Defines
TIM17 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM17_TI1_RMP_HSI48 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
#define | LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2

Define Documentation

#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U

TIM17 input 1 is connected to GPIO

Definition at line 1386 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1

TIM17 input 1 is connected to HSE/32 clock

Definition at line 1388 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_HSI48 TIM_TISEL_TI1SEL_0

TIM17 input 1 is connected to HSI48/256

Definition at line 1387 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)

TIM17 input 1 is connected to MCO

Definition at line 1389 of file stm32g0xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2

TIM17 input 1 is connected to MCO2

Definition at line 1390 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: OCREF clear input selection

Defines
OCREF clear input selection
TIM Exported Constants

Defines

#define | LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk
#define | LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U
#define | LL_TIM_OCREF_CLR_INT_COMP2 TIM1_OR1_OCREF_CLR_0
#define | LL_TIM_OCREF_CLR_INT_COMP3 TIM1_OR1_OCREF_CLR_1

Define Documentation

#define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U

OCREF clear input is connected to COMP1_OUT

Definition at line 1400 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_OR1_OCREF_CLR_0

OCREF clear input is connected to COMP2_OUT

Definition at line 1402 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_COMP3 TIM1_OR1_OCREF_CLR_1

OCREF clear input is connected to COMP3_OUT

Definition at line 1403 of file stm32g0xx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk

OCREF_CLR_INT is connected to ETRF

Definition at line 1398 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
TIM Exported Macros

Defines

#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in TIM register.

Define Documentation

#define LL_TIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1446 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define LL_TIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1438 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Exported_Macros

Defines
Exported_Macros
TIM Exported Macros

Defines

#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Define Documentation

#define __LL_TIM_CALC_ARR | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) | ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)

HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

Note:
ex: __LL_TIM_CALC_ARR (1000000, LL_TIM_GetPrescaler (), 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1509 of file stm32g0xx_ll_tim.h.

#define __LL_TIM_CALC_DEADTIME | ( | __TIMCLK__,
 |  | __CKD__,
 |  | __DT__
 | ) |
Value:
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
    0U)

HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.

Note:
ex: __LL_TIM_CALC_DEADTIME (80000000, LL_TIM_GetClockDivision (), 120);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
__DT__ | deadtime duration (in ns)
Return values:
DTG[0:7]

Definition at line 1477 of file stm32g0xx_ll_tim.h.

#define __LL_TIM_CALC_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

Note:
ex: __LL_TIM_CALC_DELAY (1000000, LL_TIM_GetPrescaler (), 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 1521 of file stm32g0xx_ll_tim.h.

#define __LL_TIM_CALC_PSC | ( | __TIMCLK__,
 |  | __CNTCLK__
 | ) | (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)

HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

Note:
ex: __LL_TIM_CALC_PSC (80000000, 1000000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CNTCLK__ | counter clock frequency (in Hz)
Return values:
Prescaler value (between Min_Data=0 and Max_Data=65535)

Definition at line 1498 of file stm32g0xx_ll_tim.h.

#define __LL_TIM_CALC_PULSE | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __LL_TIM_CALC_PULSE (1000000, LL_TIM_GetPrescaler (), 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1535 of file stm32g0xx_ll_tim.h.

#define __LL_TIM_GET_ICPSC_RATIO ( __ICPSC__ ) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))

HELPER macro retrieving the ratio of the input capture prescaler.

Note:
ex: __LL_TIM_GET_ICPSC_RATIO (LL_TIM_IC_GetPrescaler ());
Parameters:
__ICPSC__ This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
Input capture prescaler ratio (1, 2, 4 or 8)

Definition at line 1549 of file stm32g0xx_ll_tim.h.

#define __LL_TIM_GETFLAG_UIFCPY ( __CNT__ ) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)

HELPER macro retrieving the UIFCPY flag from the counter value.

Note:
ex: __LL_TIM_GETFLAG_UIFCPY (LL_TIM_GetCounter ());
Relevant only if UIF flag remapping has been enabled (UIF status bit is copied to TIMx_CNT register bit 31)
Parameters:
__CNT__ Counter value
Return values:
UIF status bit

Definition at line 1463 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Time Base configuration

Functions
Time Base configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (const TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (const TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (const TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (const TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (const TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (const TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (const TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (const TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (const TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (const TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (const TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (const TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.
__STATIC_INLINE uint32_t | LL_TIM_IsActiveUIFCPY (const uint32_t Counter)
Indicate whether update interrupt flag (UIF) copy is set.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableARRPreload ( TIM_TypeDef * TIMx )

Disable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_DisableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1767 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableCounter ( TIM_TypeDef * TIMx )

Disable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_DisableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1587 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUIFRemap ( TIM_TypeDef * TIMx )

Disable update interrupt flag (UIF) remapping.

Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_DisableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1963 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUpdateEvent ( TIM_TypeDef * TIMx )

Disable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_DisableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1620 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableARRPreload ( TIM_TypeDef * TIMx )

Enable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_EnableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1756 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableCounter ( TIM_TypeDef * TIMx )

Enable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_EnableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1576 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUIFRemap ( TIM_TypeDef * TIMx )

Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

Note:
This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_EnableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1952 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUpdateEvent ( TIM_TypeDef * TIMx )

Enable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_EnableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1609 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetAutoReload ( const TIM_TypeDef * TIMx )

Get the auto-reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_TIM_GetAutoReload
Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Parameters:
TIMx Timer instance
Return values:
Auto-reload value

Definition at line 1911 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetClockDivision ( const TIM_TypeDef * TIMx )

Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_GetClockDivision
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4

Definition at line 1815 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounter ( const TIM_TypeDef * TIMx )

Get the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_GetCounter
Parameters:
TIMx Timer instance
Return values:
Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)

Definition at line 1842 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounterMode ( const TIM_TypeDef * TIMx )

Get actual counter mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetCounterMode
CR1 CMS LL_TIM_GetCounterMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN

Definition at line 1736 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetDirection ( const TIM_TypeDef * TIMx )

Get the current direction of the counter.

Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetDirection
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERDIRECTION_UP
  • LL_TIM_COUNTERDIRECTION_DOWN

Definition at line 1855 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode ( const TIM_TypeDef * TIMx )

Get actual one pulse mode.

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_GetOnePulseMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE

Definition at line 1692 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetPrescaler ( const TIM_TypeDef * TIMx )

Get the prescaler value.

Reference Manual to LL API cross reference:
PSC PSC LL_TIM_GetPrescaler
Parameters:
TIMx Timer instance
Return values:
Prescaler value between Min_Data=0 and Max_Data=65535

Definition at line 1882 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter ( const TIM_TypeDef * TIMx )

Get the repetition counter value.

Note:
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_GetRepetitionCounter
Parameters:
TIMx Timer instance
Return values:
Repetition counter value

Definition at line 1939 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource ( const TIM_TypeDef * TIMx )

Get actual event update source.

Reference Manual to LL API cross reference:
CR1 URS LL_TIM_GetUpdateSource
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER

Definition at line 1665 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY ( const uint32_t Counter )

Indicate whether update interrupt flag (UIF) copy is set.

Parameters:
Counter Counter value
Return values:
State of bit (1 or 0).

Definition at line 1973 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload ( const TIM_TypeDef * TIMx )

Indicates whether auto-reload (ARR) preload is enabled.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_IsEnabledARRPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1778 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter ( const TIM_TypeDef * TIMx )

Indicates whether the timer counter is enabled.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_IsEnabledCounter
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1598 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent ( const TIM_TypeDef * TIMx )

Indicates whether update event generation is enabled.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_IsEnabledUpdateEvent
Parameters:
TIMx Timer instance
Return values:
Inverted state of bit (0 or 1).

Definition at line 1631 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetAutoReload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto-reload value.

Note:
The counter is blocked while the auto-reload value is null.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Helper macro __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
Reference Manual to LL API cross reference:
ARR ARR LL_TIM_SetAutoReload
Parameters:
TIMx | Timer instance
AutoReload | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1898 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockDivision
 | ) |  |

Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_SetClockDivision
Parameters:
TIMx Timer instance
ClockDivision This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1797 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Set the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_SetCounter
Parameters:
TIMx | Timer instance
Counter | Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
Return values:
None

Definition at line 1829 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounterMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the timer counter counting mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_SetCounterMode
CR1 CMS LL_TIM_SetCounterMode
Parameters:
TIMx Timer instance
CounterMode This parameter can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN
Return values:
None

Definition at line 1716 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OnePulseMode
 | ) |  |

Set one pulse mode (one shot v.s.

repetitive).

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_SetOnePulseMode
Parameters:
TIMx Timer instance
OnePulseMode This parameter can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE
Return values:
None

Definition at line 1679 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the prescaler value.

Note:
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
The prescaler can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Helper macro __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
Reference Manual to LL API cross reference:
PSC PSC LL_TIM_SetPrescaler
Parameters:
TIMx | Timer instance
Prescaler | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1871 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetRepetitionCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | RepetitionCounter
 | ) |  |

Set the repetition counter value.

Note:
For advanced timer instances RepetitionCounter can be up to 65535.
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_SetRepetitionCounter
Parameters:
TIMx | Timer instance
RepetitionCounter | between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
Return values:
None

Definition at line 1926 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetUpdateSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | UpdateSource
 | ) |  |

Set update event source.

Note:
Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events generate an update interrupt or DMA request if enabled:
  • Counter overflow/underflow
  • Setting the UG bit
  • Update generation through the slave mode controller
Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Reference Manual to LL API cross reference:
CR1 URS LL_TIM_SetUpdateSource
Parameters:
TIMx Timer instance
UpdateSource This parameter can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER
Return values:
None

Definition at line 1652 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Capture Compare configuration

Functions
Capture Compare configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (const TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_CC_DisableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Disable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_DisableChannel
CCER CC1NE LL_TIM_CC_DisableChannel
CCER CC2E LL_TIM_CC_DisableChannel
CCER CC2NE LL_TIM_CC_DisableChannel
CCER CC3E LL_TIM_CC_DisableChannel
CCER CC3NE LL_TIM_CC_DisableChannel
CCER CC4E LL_TIM_CC_DisableChannel
CCER CC5E LL_TIM_CC_DisableChannel
CCER CC6E LL_TIM_CC_DisableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2129 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_DisablePreload ( TIM_TypeDef * TIMx )

Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_DisablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2009 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Enable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_EnableChannel
CCER CC1NE LL_TIM_CC_EnableChannel
CCER CC2E LL_TIM_CC_EnableChannel
CCER CC2NE LL_TIM_CC_EnableChannel
CCER CC3E LL_TIM_CC_EnableChannel
CCER CC3NE LL_TIM_CC_EnableChannel
CCER CC4E LL_TIM_CC_EnableChannel
CCER CC5E LL_TIM_CC_EnableChannel
CCER CC6E LL_TIM_CC_EnableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2100 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnablePreload ( TIM_TypeDef * TIMx )

Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs.
Only on channels that have a complementary output.
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_EnablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1996 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger ( const TIM_TypeDef * TIMx )

Get actual trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE

Definition at line 2052 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Indicate whether channel(s) is(are) enabled.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_IsEnabledChannel
CCER CC1NE LL_TIM_CC_IsEnabledChannel
CCER CC2E LL_TIM_CC_IsEnabledChannel
CCER CC2NE LL_TIM_CC_IsEnabledChannel
CCER CC3E LL_TIM_CC_IsEnabledChannel
CCER CC3NE LL_TIM_CC_IsEnabledChannel
CCER CC4E LL_TIM_CC_IsEnabledChannel
CCER CC5E LL_TIM_CC_IsEnabledChannel
CCER CC6E LL_TIM_CC_IsEnabledChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2158 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMAReqTrigger
 | ) |  |

Set the trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
Parameters:
TIMx Timer instance
DMAReqTrigger This parameter can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE
Return values:
None

Definition at line 2039 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetLockLevel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | LockLevel
 | ) |  |

Set the lock level to freeze the configuration of several capture/compare parameters.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not the lock mechanism is supported by a timer instance.
Reference Manual to LL API cross reference:
BDTR LOCK LL_TIM_CC_SetLockLevel
Parameters:
TIMx Timer instance
LockLevel This parameter can be one of the following values:
  • LL_TIM_LOCKLEVEL_OFF
  • LL_TIM_LOCKLEVEL_1
  • LL_TIM_LOCKLEVEL_2
  • LL_TIM_LOCKLEVEL_3
Return values:
None

Definition at line 2071 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetUpdate | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CCUpdateSource
 | ) |  |

Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCUS LL_TIM_CC_SetUpdate
Parameters:
TIMx Timer instance
CCUpdateSource This parameter can be one of the following values:
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
Return values:
None

Definition at line 2025 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Output channel configuration

Functions
Output channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.

Function Documentation

__STATIC_INLINE void LL_TIM_OC_ConfigOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure an output channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_OC_ConfigOutput
CCMR1 CC2S LL_TIM_OC_ConfigOutput
CCMR2 CC3S LL_TIM_OC_ConfigOutput
CCMR2 CC4S LL_TIM_OC_ConfigOutput
CCMR3 CC5S LL_TIM_OC_ConfigOutput
CCMR3 CC6S LL_TIM_OC_ConfigOutput
CCER CC1P LL_TIM_OC_ConfigOutput
CCER CC2P LL_TIM_OC_ConfigOutput
CCER CC3P LL_TIM_OC_ConfigOutput
CCER CC4P LL_TIM_OC_ConfigOutput
CCER CC5P LL_TIM_OC_ConfigOutput
CCER CC6P LL_TIM_OC_ConfigOutput
CR2 OIS1 LL_TIM_OC_ConfigOutput
CR2 OIS2 LL_TIM_OC_ConfigOutput
CR2 OIS3 LL_TIM_OC_ConfigOutput
CR2 OIS4 LL_TIM_OC_ConfigOutput
CR2 OIS5 LL_TIM_OC_ConfigOutput
CR2 OIS6 LL_TIM_OC_ConfigOutput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_OCPOLARITY_HIGH or LL_TIM_OCPOLARITY_LOW
  • LL_TIM_OCIDLESTATE_LOW or LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 2203 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable clearing the output channel on an external event.

Note:
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_DisableClear
CCMR1 OC2CE LL_TIM_OC_DisableClear
CCMR2 OC3CE LL_TIM_OC_DisableClear
CCMR2 OC4CE LL_TIM_OC_DisableClear
CCMR3 OC5CE LL_TIM_OC_DisableClear
CCMR3 OC6CE LL_TIM_OC_DisableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2631 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable fast mode for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_DisableFast
CCMR1 OC2FE LL_TIM_OC_DisableFast
CCMR2 OC3FE LL_TIM_OC_DisableFast
CCMR2 OC4FE LL_TIM_OC_DisableFast
CCMR3 OC5FE LL_TIM_OC_DisableFast
CCMR3 OC6FE LL_TIM_OC_DisableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2473 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_DisablePreload
CCMR1 OC2PE LL_TIM_OC_DisablePreload
CCMR2 OC3PE LL_TIM_OC_DisablePreload
CCMR2 OC4PE LL_TIM_OC_DisablePreload
CCMR3 OC5PE LL_TIM_OC_DisablePreload
CCMR3 OC6PE LL_TIM_OC_DisablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2550 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable clearing the output channel on an external event.

Note:
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_EnableClear
CCMR1 OC2CE LL_TIM_OC_EnableClear
CCMR2 OC3CE LL_TIM_OC_EnableClear
CCMR2 OC4CE LL_TIM_OC_EnableClear
CCMR3 OC5CE LL_TIM_OC_EnableClear
CCMR3 OC6CE LL_TIM_OC_EnableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2604 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable fast mode for the output channel.

Note:
Acts only if the channel is configured in PWM1 or PWM2 mode.
Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_EnableFast
CCMR1 OC2FE LL_TIM_OC_EnableFast
CCMR2 OC3FE LL_TIM_OC_EnableFast
CCMR2 OC4FE LL_TIM_OC_EnableFast
CCMR3 OC5FE LL_TIM_OC_EnableFast
CCMR3 OC6FE LL_TIM_OC_EnableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2447 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_EnablePreload
CCMR1 OC2PE LL_TIM_OC_EnablePreload
CCMR2 OC3PE LL_TIM_OC_EnablePreload
CCMR2 OC4PE LL_TIM_OC_EnablePreload
CCMR3 OC5PE LL_TIM_OC_EnablePreload
CCMR3 OC6PE LL_TIM_OC_EnablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2525 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR1) set for output channel 1.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_GetCompareCH1
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2791 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR2) set for output channel 2.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_GetCompareCH2
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2807 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR3) set for output channel 3.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_GetCompareCH3
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2823 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR4) set for output channel 4.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_GetCompareCH4
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2839 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR5) set for output channel 5.

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_GetCompareCH5
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2852 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6 ( const TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR6) set for output channel 6.

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_GetCompareCH6
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2865 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the IDLE state of an output channel.

Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS2 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS3 LL_TIM_OC_GetIdleState
CR2 OIS3N LL_TIM_OC_GetIdleState
CR2 OIS4 LL_TIM_OC_GetIdleState
CR2 OIS5 LL_TIM_OC_GetIdleState
CR2 OIS6 LL_TIM_OC_GetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH

Definition at line 2422 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetMode | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the output compare mode of an output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_GetMode
CCMR1 OC2M LL_TIM_OC_GetMode
CCMR2 OC3M LL_TIM_OC_GetMode
CCMR2 OC4M LL_TIM_OC_GetMode
CCMR3 OC5M LL_TIM_OC_GetMode
CCMR3 OC6M LL_TIM_OC_GetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2

Definition at line 2287 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_GetPolarity
CCER CC1NP LL_TIM_OC_GetPolarity
CCER CC2P LL_TIM_OC_GetPolarity
CCER CC2NP LL_TIM_OC_GetPolarity
CCER CC3P LL_TIM_OC_GetPolarity
CCER CC3NP LL_TIM_OC_GetPolarity
CCER CC4P LL_TIM_OC_GetPolarity
CCER CC5P LL_TIM_OC_GetPolarity
CCER CC6P LL_TIM_OC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW

Definition at line 2353 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates clearing the output channel on an external event is enabled for the output channel.

Note:
This function enables clearing the output channel on an external event.
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_IsEnabledClear
CCMR1 OC2CE LL_TIM_OC_IsEnabledClear
CCMR2 OC3CE LL_TIM_OC_IsEnabledClear
CCMR2 OC4CE LL_TIM_OC_IsEnabledClear
CCMR3 OC5CE LL_TIM_OC_IsEnabledClear
CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2660 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether fast mode is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_IsEnabledFast
CCMR1 OC2FE LL_TIM_OC_IsEnabledFast
CCMR2 OC3FE LL_TIM_OC_IsEnabledFast
CCMR2 OC4FE LL_TIM_OC_IsEnabledFast
CCMR3 OC5FE LL_TIM_OC_IsEnabledFast
CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2499 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload
CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2575 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetCompareCH1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 1 (TIMx_CCR1).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_SetCompareCH1
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2696 of file stm32g0xx_ll_tim.h.

Referenced by OC1Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 2 (TIMx_CCR2).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_SetCompareCH2
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2713 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and OC2Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 3 (TIMx_CCR3).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_SetCompareCH3
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2730 of file stm32g0xx_ll_tim.h.

Referenced by OC3Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 4 (TIMx_CCR4).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_SetCompareCH4
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2747 of file stm32g0xx_ll_tim.h.

Referenced by OC4Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH5 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 5 (TIMx_CCR5).

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_SetCompareCH5
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2761 of file stm32g0xx_ll_tim.h.

Referenced by OC5Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH6 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 6 (TIMx_CCR6).

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_SetCompareCH6
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2775 of file stm32g0xx_ll_tim.h.

Referenced by OC6Config().

__STATIC_INLINE void LL_TIM_OC_SetDeadTime | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DeadTime
 | ) |  |

Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not dead-time insertion feature is supported by a timer instance.
Helper macro __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
Reference Manual to LL API cross reference:
BDTR DTG LL_TIM_OC_SetDeadTime
Parameters:
TIMx | Timer instance
DeadTime | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 2679 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_OC_SetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | IdleState
 | ) |  |

Set the IDLE state of an output channel.

Note:
This function is significant only for the timer instances supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS2 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS3 LL_TIM_OC_SetIdleState
CR2 OIS3N LL_TIM_OC_SetIdleState
CR2 OIS4 LL_TIM_OC_SetIdleState
CR2 OIS5 LL_TIM_OC_SetIdleState
CR2 OIS6 LL_TIM_OC_SetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
IdleState This parameter can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 2390 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_SetMode
CCMR1 OC2M LL_TIM_OC_SetMode
CCMR2 OC3M LL_TIM_OC_SetMode
CCMR2 OC4M LL_TIM_OC_SetMode
CCMR3 OC5M LL_TIM_OC_SetMode
CCMR3 OC6M LL_TIM_OC_SetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Mode This parameter can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2
Return values:
None

Definition at line 2248 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_SetPolarity
CCER CC1NP LL_TIM_OC_SetPolarity
CCER CC2P LL_TIM_OC_SetPolarity
CCER CC2NP LL_TIM_OC_SetPolarity
CCER CC3P LL_TIM_OC_SetPolarity
CCER CC3NP LL_TIM_OC_SetPolarity
CCER CC4P LL_TIM_OC_SetPolarity
CCER CC5P LL_TIM_OC_SetPolarity
CCER CC6P LL_TIM_OC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Polarity This parameter can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW
Return values:
None

Definition at line 2321 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | GroupCH5
 | ) |  |

Select on which reference signal the OC5REF is combined to.

Note:
Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the combined 3-phase PWM mode.
Reference Manual to LL API cross reference:
CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
Parameters:
TIMx Timer instance
GroupCH5 This parameter can be a combination of the following values:
  • LL_TIM_GROUPCH5_NONE
  • LL_TIM_GROUPCH5_OC1REFC
  • LL_TIM_GROUPCH5_OC2REFC
  • LL_TIM_GROUPCH5_OC3REFC
Return values:
None

Definition at line 2885 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Input channel configuration

Functions
Input channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (const TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (const TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (const TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (const TIM_TypeDef *TIMx)
Get captured value for input channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_IC_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure input channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_Config
CCMR1 IC1PSC LL_TIM_IC_Config
CCMR1 IC1F LL_TIM_IC_Config
CCMR1 CC2S LL_TIM_IC_Config
CCMR1 IC2PSC LL_TIM_IC_Config
CCMR1 IC2F LL_TIM_IC_Config
CCMR2 CC3S LL_TIM_IC_Config
CCMR2 IC3PSC LL_TIM_IC_Config
CCMR2 IC3F LL_TIM_IC_Config
CCMR2 CC4S LL_TIM_IC_Config
CCMR2 IC4PSC LL_TIM_IC_Config
CCMR2 IC4F LL_TIM_IC_Config
CCER CC1P LL_TIM_IC_Config
CCER CC1NP LL_TIM_IC_Config
CCER CC2P LL_TIM_IC_Config
CCER CC2NP LL_TIM_IC_Config
CCER CC3P LL_TIM_IC_Config
CCER CC3NP LL_TIM_IC_Config
CCER CC4P LL_TIM_IC_Config
CCER CC4NP LL_TIM_IC_Config
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI or LL_TIM_ACTIVEINPUT_INDIRECTTI or LL_TIM_ACTIVEINPUT_TRC
  • LL_TIM_ICPSC_DIV1 or ... or LL_TIM_ICPSC_DIV8
  • LL_TIM_IC_FILTER_FDIV1 or ... or LL_TIM_IC_FILTER_FDIV32_N8
  • LL_TIM_IC_POLARITY_RISING or LL_TIM_IC_POLARITY_FALLING or LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 2932 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_DisableXORCombination ( TIM_TypeDef * TIMx )

Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_DisableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3196 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_EnableXORCombination ( TIM_TypeDef * TIMx )

Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_EnableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3183 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_GetActiveInput
CCMR1 CC2S LL_TIM_IC_GetActiveInput
CCMR2 CC3S LL_TIM_IC_GetActiveInput
CCMR2 CC4S LL_TIM_IC_GetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC

Definition at line 2985 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1 ( const TIM_TypeDef * TIMx )

Get captured value for input channel 1.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not input channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3225 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2 ( const TIM_TypeDef * TIMx )

Get captured value for input channel 2.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not input channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3241 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3 ( const TIM_TypeDef * TIMx )

Get captured value for input channel 3.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not input channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3257 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4 ( const TIM_TypeDef * TIMx )

Get captured value for input channel 4.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not input channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3273 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_GetFilter
CCMR1 IC2F LL_TIM_IC_GetFilter
CCMR2 IC3F LL_TIM_IC_GetFilter
CCMR2 IC4F LL_TIM_IC_GetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8

Definition at line 3111 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_GetPolarity
CCER CC1NP LL_TIM_IC_GetPolarity
CCER CC2P LL_TIM_IC_GetPolarity
CCER CC2NP LL_TIM_IC_GetPolarity
CCER CC3P LL_TIM_IC_GetPolarity
CCER CC3NP LL_TIM_IC_GetPolarity
CCER CC4P LL_TIM_IC_GetPolarity
CCER CC4NP LL_TIM_IC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE

Definition at line 3168 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler | ( | const TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current prescaler value acting on an input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_GetPrescaler
CCMR1 IC2PSC LL_TIM_IC_GetPrescaler
CCMR2 IC3PSC LL_TIM_IC_GetPrescaler
CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8

Definition at line 3036 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination ( TIM_TypeDef * TIMx )

Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3209 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_SetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICActiveInput
 | ) |  |

Set the active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_SetActiveInput
CCMR1 CC2S LL_TIM_IC_SetActiveInput
CCMR2 CC3S LL_TIM_IC_SetActiveInput
CCMR2 CC4S LL_TIM_IC_SetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICActiveInput This parameter can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC
Return values:
None

Definition at line 2961 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICFilter
 | ) |  |

Set the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_SetFilter
CCMR1 IC2F LL_TIM_IC_SetFilter
CCMR2 IC3F LL_TIM_IC_SetFilter
CCMR2 IC4F LL_TIM_IC_SetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICFilter This parameter can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8
Return values:
None

Definition at line 3074 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPolarity
 | ) |  |

Set the input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_SetPolarity
CCER CC1NP LL_TIM_IC_SetPolarity
CCER CC2P LL_TIM_IC_SetPolarity
CCER CC2NP LL_TIM_IC_SetPolarity
CCER CC3P LL_TIM_IC_SetPolarity
CCER CC3NP LL_TIM_IC_SetPolarity
CCER CC4P LL_TIM_IC_SetPolarity
CCER CC4NP LL_TIM_IC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPolarity This parameter can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 3140 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPrescaler
 | ) |  |

Set the prescaler of input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_SetPrescaler
CCMR1 IC2PSC LL_TIM_IC_SetPrescaler
CCMR2 IC3PSC LL_TIM_IC_SetPrescaler
CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPrescaler This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
None

Definition at line 3011 of file stm32g0xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Counter clock selection

Functions
Counter clock selection
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (const TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableExternalClock ( TIM_TypeDef * TIMx )

Disable external clock mode 2.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_DisableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3307 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableExternalClock ( TIM_TypeDef * TIMx )

Enable external clock mode 2.

Note:
When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_EnableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3294 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock ( const TIM_TypeDef * TIMx )

Indicate whether external clock mode 2 is enabled.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_IsEnabledExternalClock
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3320 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetClockSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the clock source of the counter clock.

Note:
when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode1.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetClockSource
SMCR ECE LL_TIM_SetClockSource
Parameters:
TIMx Timer instance
ClockSource This parameter can be one of the following values:
  • LL_TIM_CLOCKSOURCE_INTERNAL
  • LL_TIM_CLOCKSOURCE_EXT_MODE1
  • LL_TIM_CLOCKSOURCE_EXT_MODE2
Return values:
None

Definition at line 3344 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetEncoderMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Set the encoder interface mode.

Note:
Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the encoder mode.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetEncoderMode
Parameters:
TIMx Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_TIM_ENCODERMODE_X2_TI1
  • LL_TIM_ENCODERMODE_X2_TI2
  • LL_TIM_ENCODERMODE_X4_TI12
Return values:
None

Definition at line 3361 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init().

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Timer synchronisation configuration

Functions
Timer synchronisation configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (const TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigETR | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRPolarity,
 |  | uint32_t | ETRPrescaler,
 |  | uint32_t | ETRFilter
 | ) |  |

Configure the external trigger (ETR) input.

Note:
Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an external trigger input.
Reference Manual to LL API cross reference:
SMCR ETP LL_TIM_ConfigETR
SMCR ETPS LL_TIM_ConfigETR
SMCR ETF LL_TIM_ConfigETR
Parameters:
TIMx Timer instance
ETRPolarity This parameter can be one of the following values:
  • LL_TIM_ETR_POLARITY_NONINVERTED
  • LL_TIM_ETR_POLARITY_INVERTED
ETRPrescaler This parameter can be one of the following values:
  • LL_TIM_ETR_PRESCALER_DIV1
  • LL_TIM_ETR_PRESCALER_DIV2
  • LL_TIM_ETR_PRESCALER_DIV4
  • LL_TIM_ETR_PRESCALER_DIV8
ETRFilter This parameter can be one of the following values:
  • LL_TIM_ETR_FILTER_FDIV1
  • LL_TIM_ETR_FILTER_FDIV1_N2
  • LL_TIM_ETR_FILTER_FDIV1_N4
  • LL_TIM_ETR_FILTER_FDIV1_N8
  • LL_TIM_ETR_FILTER_FDIV2_N6
  • LL_TIM_ETR_FILTER_FDIV2_N8
  • LL_TIM_ETR_FILTER_FDIV4_N6
  • LL_TIM_ETR_FILTER_FDIV4_N8
  • LL_TIM_ETR_FILTER_FDIV8_N6
  • LL_TIM_ETR_FILTER_FDIV8_N8
  • LL_TIM_ETR_FILTER_FDIV16_N5
  • LL_TIM_ETR_FILTER_FDIV16_N6
  • LL_TIM_ETR_FILTER_FDIV16_N8
  • LL_TIM_ETR_FILTER_FDIV32_N5
  • LL_TIM_ETR_FILTER_FDIV32_N6
  • LL_TIM_ETR_FILTER_FDIV32_N8
Return values:
None

Definition at line 3543 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode ( TIM_TypeDef * TIMx )

Disable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_DisableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3490 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode ( TIM_TypeDef * TIMx )

Enable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_EnableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3477 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode ( const TIM_TypeDef * TIMx )

Indicates whether the Master/Slave mode is enabled.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3503 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetETRSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRSource
 | ) |  |

Select the external trigger (ETR) input source.

Note:
Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or not a timer instance supports ETR source selection.
Reference Manual to LL API cross reference:
AF1 ETRSEL LL_TIM_SetETRSource
Parameters:
TIMx | Timer instance
ETRSource | This parameter can be one of the following values: TIM1
  • LL_TIM_ETRSOURCE_GPIO
  • LL_TIM_ETRSOURCE_COMP1 (**)
  • LL_TIM_ETRSOURCE_COMP2 (**)
  • LL_TIM_ETRSOURCE_COMP3 (**)
  • LL_TIM_ETRSOURCE_ADC1_AWD1
  • LL_TIM_ETRSOURCE_ADC1_AWD2
  • LL_TIM_ETRSOURCE_ADC1_AWD3

TIM2 (*)

  • LL_TIM_ETRSOURCE_GPIO
  • LL_TIM_ETRSOURCE_COMP1
  • LL_TIM_ETRSOURCE_COMP2
  • LL_TIM_ETRSOURCE_COMP3 (**)
  • LL_TIM_ETRSOURCE_LSE
  • LL_TIM_ETRSOURCE_MCO (**)
  • LL_TIM_ETRSOURCE_MCO2 (**)

TIM3

  • LL_TIM_ETRSOURCE_GPIO
  • LL_TIM_ETRSOURCE_COMP1 (**)
  • LL_TIM_ETRSOURCE_COMP2 (**)
  • LL_TIM_ETRSOURCE_COMP3 (**)

TIM4 (*)

  • LL_TIM_ETRSOURCE_GPIO
  • LL_TIM_ETRSOURCE_COMP1
  • LL_TIM_ETRSOURCE_COMP2
  • LL_TIM_ETRSOURCE_COMP3 (**)

(*) Timer instance not available on all devices
(**) Value not defined in all devices.

Return values:
None

Definition at line 3595 of file stm32g0xx_ll_tim.h.

References LL_TIM_ETRSOURCE_COMP3, and TIMx_AF1_ETRSEL.

__STATIC_INLINE void LL_TIM_SetSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | SlaveMode
 | ) |  |

Set the synchronization mode of a slave timer.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetSlaveMode
Parameters:
TIMx Timer instance
SlaveMode This parameter can be one of the following values:
  • LL_TIM_SLAVEMODE_DISABLED
  • LL_TIM_SLAVEMODE_RESET
  • LL_TIM_SLAVEMODE_GATED
  • LL_TIM_SLAVEMODE_TRIGGER
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
Return values:
None

Definition at line 3439 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TriggerInput
 | ) |  |

Set the selects the trigger input to be used to synchronize the counter.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR TS LL_TIM_SetTriggerInput
Parameters:
TIMx Timer instance
TriggerInput This parameter can be one of the following values:
  • LL_TIM_TS_ITR0
  • LL_TIM_TS_ITR1
  • LL_TIM_TS_ITR2
  • LL_TIM_TS_ITR3
  • LL_TIM_TS_ITR7 (*)
  • LL_TIM_TS_TI1F_ED
  • LL_TIM_TS_TI1FP1
  • LL_TIM_TS_TI2FP2
  • LL_TIM_TS_ETRF
(*) Value not defined in all devices.
Return values:
None

Definition at line 3464 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TimerSynchronization
 | ) |  |

Set the trigger output (TRGO) used for timer synchronization .

Note:
Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a master timer.
Reference Manual to LL API cross reference:
CR2 MMS LL_TIM_SetTriggerOutput
Parameters:
TIMx Timer instance
TimerSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO_RESET
  • LL_TIM_TRGO_ENABLE
  • LL_TIM_TRGO_UPDATE
  • LL_TIM_TRGO_CC1IF
  • LL_TIM_TRGO_OC1REF
  • LL_TIM_TRGO_OC2REF
  • LL_TIM_TRGO_OC3REF
  • LL_TIM_TRGO_OC4REF
Return values:
None

Definition at line 3390 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ADCSynchronization
 | ) |  |

Set the trigger output 2 (TRGO2) used for ADC synchronization .

Note:
Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check whether or not a timer instance can be used for ADC synchronization.
Reference Manual to LL API cross reference:
CR2 MMS2 LL_TIM_SetTriggerOutput2
Parameters:
TIMx Timer Instance
ADCSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO2_RESET
  • LL_TIM_TRGO2_ENABLE
  • LL_TIM_TRGO2_UPDATE
  • LL_TIM_TRGO2_CC1F
  • LL_TIM_TRGO2_OC1
  • LL_TIM_TRGO2_OC2
  • LL_TIM_TRGO2_OC3
  • LL_TIM_TRGO2_OC4
  • LL_TIM_TRGO2_OC5
  • LL_TIM_TRGO2_OC6
  • LL_TIM_TRGO2_OC4_RISINGFALLING
  • LL_TIM_TRGO2_OC6_RISINGFALLING
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
Return values:
None

Definition at line 3420 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Break function configuration

Functions
Break function configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, uint32_t BreakAFMode)
Configure the break input.
__STATIC_INLINE void | LL_TIM_DisarmBRK (TIM_TypeDef *TIMx)
Disarm the break input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_ReArmBRK (TIM_TypeDef *TIMx)
Re-arm the break input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, uint32_t Break2AFMode)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_DisarmBRK2 (TIM_TypeDef *TIMx)
Disarm the break 2 input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_ReArmBRK2 (TIM_TypeDef *TIMx)
Re-arm the break 2 input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (const TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (const TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigBRK | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakPolarity,
 |  | uint32_t | BreakFilter,
 |  | uint32_t | BreakAFMode
 | ) |  |

Configure the break input.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Bidirectional mode is only supported by advanced timer instances. Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not a timer instance is an advanced-control timer.
In bidirectional mode (BKBID bit set), the Break input is configured both in input mode and in open drain output mode. Any active Break event will assert a low logic level on the Break input to indicate an internal break event to external devices.
When bidirectional mode isn't supported, BreakAFMode must be set to LL_TIM_BREAK_AFMODE_INPUT.
Reference Manual to LL API cross reference:
BDTR BKP LL_TIM_ConfigBRK
BDTR BKF LL_TIM_ConfigBRK
BDTR BKBID LL_TIM_ConfigBRK
Parameters:
TIMx Timer instance
BreakPolarity This parameter can be one of the following values:
  • LL_TIM_BREAK_POLARITY_LOW
  • LL_TIM_BREAK_POLARITY_HIGH
BreakFilter This parameter can be one of the following values:
  • LL_TIM_BREAK_FILTER_FDIV1
  • LL_TIM_BREAK_FILTER_FDIV1_N2
  • LL_TIM_BREAK_FILTER_FDIV1_N4
  • LL_TIM_BREAK_FILTER_FDIV1_N8
  • LL_TIM_BREAK_FILTER_FDIV2_N6
  • LL_TIM_BREAK_FILTER_FDIV2_N8
  • LL_TIM_BREAK_FILTER_FDIV4_N6
  • LL_TIM_BREAK_FILTER_FDIV4_N8
  • LL_TIM_BREAK_FILTER_FDIV8_N6
  • LL_TIM_BREAK_FILTER_FDIV8_N8
  • LL_TIM_BREAK_FILTER_FDIV16_N5
  • LL_TIM_BREAK_FILTER_FDIV16_N6
  • LL_TIM_BREAK_FILTER_FDIV16_N8
  • LL_TIM_BREAK_FILTER_FDIV32_N5
  • LL_TIM_BREAK_FILTER_FDIV32_N6
  • LL_TIM_BREAK_FILTER_FDIV32_N8
BreakAFMode This parameter can be one of the following values:
  • LL_TIM_BREAK_AFMODE_INPUT
  • LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
Return values:
None

Definition at line 3687 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ConfigBRK2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Break2Polarity,
 |  | uint32_t | Break2Filter,
 |  | uint32_t | Break2AFMode
 | ) |  |

Configure the break 2 input.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Bidirectional mode is only supported by advanced timer instances. Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not a timer instance is an advanced-control timer.
In bidirectional mode (BK2BID bit set), the Break 2 input is configured both in input mode and in open drain output mode. Any active Break event will assert a low logic level on the Break 2 input to indicate an internal break event to external devices.
When bidirectional mode isn't supported, Break2AFMode must be set to LL_TIM_BREAK2_AFMODE_INPUT.
Reference Manual to LL API cross reference:
BDTR BK2P LL_TIM_ConfigBRK2
BDTR BK2F LL_TIM_ConfigBRK2
BDTR BK2BID LL_TIM_ConfigBRK2
Parameters:
TIMx Timer instance
Break2Polarity This parameter can be one of the following values:
  • LL_TIM_BREAK2_POLARITY_LOW
  • LL_TIM_BREAK2_POLARITY_HIGH
Break2Filter This parameter can be one of the following values:
  • LL_TIM_BREAK2_FILTER_FDIV1
  • LL_TIM_BREAK2_FILTER_FDIV1_N2
  • LL_TIM_BREAK2_FILTER_FDIV1_N4
  • LL_TIM_BREAK2_FILTER_FDIV1_N8
  • LL_TIM_BREAK2_FILTER_FDIV2_N6
  • LL_TIM_BREAK2_FILTER_FDIV2_N8
  • LL_TIM_BREAK2_FILTER_FDIV4_N6
  • LL_TIM_BREAK2_FILTER_FDIV4_N8
  • LL_TIM_BREAK2_FILTER_FDIV8_N6
  • LL_TIM_BREAK2_FILTER_FDIV8_N8
  • LL_TIM_BREAK2_FILTER_FDIV16_N5
  • LL_TIM_BREAK2_FILTER_FDIV16_N6
  • LL_TIM_BREAK2_FILTER_FDIV16_N8
  • LL_TIM_BREAK2_FILTER_FDIV32_N5
  • LL_TIM_BREAK2_FILTER_FDIV32_N6
  • LL_TIM_BREAK2_FILTER_FDIV32_N8
Break2AFMode This parameter can be one of the following values:
  • LL_TIM_BREAK2_AFMODE_INPUT
  • LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
Return values:
None

Definition at line 3788 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAllOutputs ( TIM_TypeDef * TIMx )

Disable the outputs (reset the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_DisableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3905 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAutomaticOutput ( TIM_TypeDef * TIMx )

Disable automatic output (MOE can be set only by software).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_DisableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3862 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Disable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINE LL_TIM_DisableBreakInputSource
AF1 BKCMP1E LL_TIM_DisableBreakInputSource
AF1 BKCMP2E LL_TIM_DisableBreakInputSource
AF1 BKCMP3E LL_TIM_DisableBreakInputSource
AF2 BK2INE LL_TIM_DisableBreakInputSource
AF2 BK2CMP1E LL_TIM_DisableBreakInputSource
AF2 BK2CMP2E LL_TIM_DisableBreakInputSource
AF2 BK2CMP3E LL_TIM_DisableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 3981 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK ( TIM_TypeDef * TIMx )

Disable the break function.

Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_DisableBRK
Parameters:
TIMx Timer instance
Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Return values:
None

Definition at line 3640 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK2 ( TIM_TypeDef * TIMx )

Disable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_DisableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3741 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisarmBRK ( TIM_TypeDef * TIMx )

Disarm the break input (when it operates in bidirectional mode).

Note:
The break input can be disarmed only when it is configured in bidirectional mode and when when MOE is reset.
Purpose is to be able to have the input voltage back to high-state, whatever the time constant on the output .
Reference Manual to LL API cross reference:
BDTR BKDSRM LL_TIM_DisarmBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3703 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisarmBRK2 ( TIM_TypeDef * TIMx )

Disarm the break 2 input (when it operates in bidirectional mode).

Note:
The break 2 input can be disarmed only when it is configured in bidirectional mode and when when MOE is reset.
Purpose is to be able to have the input voltage back to high-state, whatever the time constant on the output.
Reference Manual to LL API cross reference:
BDTR BK2DSRM LL_TIM_DisarmBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3804 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAllOutputs ( TIM_TypeDef * TIMx )

Enable the outputs (set the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_EnableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3890 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAutomaticOutput ( TIM_TypeDef * TIMx )

Enable automatic output (MOE can be set by software or automatically when a break input is active).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_EnableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3849 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Enable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINE LL_TIM_EnableBreakInputSource
AF1 BKCMP1E LL_TIM_EnableBreakInputSource
AF1 BKCMP2E LL_TIM_EnableBreakInputSource
AF1 BKCMP3E LL_TIM_EnableBreakInputSource
AF2 BK2INE LL_TIM_EnableBreakInputSource
AF2 BK2CMP1E LL_TIM_EnableBreakInputSource
AF2 BK2CMP2E LL_TIM_EnableBreakInputSource
AF2 BK2CMP3E LL_TIM_EnableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 3949 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK ( TIM_TypeDef * TIMx )

Enable the break function.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_EnableBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3627 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK2 ( TIM_TypeDef * TIMx )

Enable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_EnableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3728 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs ( const TIM_TypeDef * TIMx )

Indicates whether outputs are enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_IsEnabledAllOutputs
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3918 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput ( const TIM_TypeDef * TIMx )

Indicate whether automatic output is enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_IsEnabledAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3875 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ReArmBRK ( TIM_TypeDef * TIMx )

Re-arm the break input (when it operates in bidirectional mode).

Note:
The Break input is automatically armed as soon as MOE bit is set.
Reference Manual to LL API cross reference:
BDTR BKDSRM LL_TIM_ReArmBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3715 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ReArmBRK2 ( TIM_TypeDef * TIMx )

Re-arm the break 2 input (when it operates in bidirectional mode).

Note:
The Break 2 input is automatically armed as soon as MOE bit is set.
Reference Manual to LL API cross reference:
BDTR BK2DSRM LL_TIM_ReArmBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3816 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the break signal for the timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINP LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
Polarity This parameter can be one of the following values:
  • LL_TIM_BKIN_POLARITY_LOW
  • LL_TIM_BKIN_POLARITY_HIGH
(*) Value not defined in all devices.
Return values:
None

Definition at line 4016 of file stm32g0xx_ll_tim.h.

References TIM_POSITION_BRK_SOURCE, and TIMx_AF1_BKINP.

__STATIC_INLINE void LL_TIM_SetOffStates | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OffStateIdle,
 |  | uint32_t | OffStateRun
 | ) |  |

Select the outputs off state (enabled v.s.

disabled) in Idle and Run modes.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR OSSI LL_TIM_SetOffStates
BDTR OSSR LL_TIM_SetOffStates
Parameters:
TIMx Timer instance
OffStateIdle This parameter can be one of the following values:
  • LL_TIM_OSSI_DISABLE
  • LL_TIM_OSSI_ENABLE
OffStateRun This parameter can be one of the following values:
  • LL_TIM_OSSR_DISABLE
  • LL_TIM_OSSR_ENABLE
Return values:
None

Definition at line 3836 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA burst mode configuration

Functions
DMA burst mode configuration
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigDMABurst | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMABurstBaseAddress,
 |  | uint32_t | DMABurstLength
 | ) |  |

Configures the timer DMA burst feature.

Note:
Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the DMA burst mode.
Reference Manual to LL API cross reference:
DCR DBL LL_TIM_ConfigDMABurst
DCR DBA LL_TIM_ConfigDMABurst
Parameters:
TIMx Timer instance
DMABurstBaseAddress This parameter can be one of the following values:
  • LL_TIM_DMABURST_BASEADDR_CR1
  • LL_TIM_DMABURST_BASEADDR_CR2
  • LL_TIM_DMABURST_BASEADDR_SMCR
  • LL_TIM_DMABURST_BASEADDR_DIER
  • LL_TIM_DMABURST_BASEADDR_SR
  • LL_TIM_DMABURST_BASEADDR_EGR
  • LL_TIM_DMABURST_BASEADDR_CCMR1
  • LL_TIM_DMABURST_BASEADDR_CCMR2
  • LL_TIM_DMABURST_BASEADDR_CCER
  • LL_TIM_DMABURST_BASEADDR_CNT
  • LL_TIM_DMABURST_BASEADDR_PSC
  • LL_TIM_DMABURST_BASEADDR_ARR
  • LL_TIM_DMABURST_BASEADDR_RCR
  • LL_TIM_DMABURST_BASEADDR_CCR1
  • LL_TIM_DMABURST_BASEADDR_CCR2
  • LL_TIM_DMABURST_BASEADDR_CCR3
  • LL_TIM_DMABURST_BASEADDR_CCR4
  • LL_TIM_DMABURST_BASEADDR_BDTR
  • LL_TIM_DMABURST_BASEADDR_OR1
  • LL_TIM_DMABURST_BASEADDR_CCMR3
  • LL_TIM_DMABURST_BASEADDR_CCR5
  • LL_TIM_DMABURST_BASEADDR_CCR6
  • LL_TIM_DMABURST_BASEADDR_AF1
  • LL_TIM_DMABURST_BASEADDR_AF2
  • LL_TIM_DMABURST_BASEADDR_TISEL
DMABurstLength This parameter can be one of the following values:
  • LL_TIM_DMABURST_LENGTH_1TRANSFER
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS
Return values:
None

Definition at line 4083 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Timer input remapping

Functions
Timer input remapping
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).

Function Documentation

__STATIC_INLINE void LL_TIM_SetRemap | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Remap
 | ) |  |

Remap TIM inputs (input channel, internal/external triggers).

Note:
Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not a some timer inputs can be remapped.
Reference Manual to LL API cross reference:
TIM1_TISEL TI1SEL LL_TIM_SetRemap
TIM1_TISEL TI2SEL LL_TIM_SetRemap
TIM2_TISEL TI1SEL LL_TIM_SetRemap
TIM2_TISEL TI2SEL LL_TIM_SetRemap
TIM3_TISEL TI1SEL LL_TIM_SetRemap
TIM3_TISEL TI2SEL LL_TIM_SetRemap
TIM4_TISEL TI1SEL LL_TIM_SetRemap
TIM4_TISEL TI2SEL LL_TIM_SetRemap
TIM4_TISEL TI3SEL LL_TIM_SetRemap
TIM14_TISEL TI1SEL LL_TIM_SetRemap
TIM15_TISEL TI1SEL LL_TIM_SetRemap
TIM15_TISEL TI2SEL LL_TIM_SetRemap
TIM16_TISEL TI1SEL LL_TIM_SetRemap
TIM17_TISEL TI1SEL LL_TIM_SetRemap
Parameters:
TIMx | Timer instance
Remap | Remap param depends on the TIMx. Description available only in CHM version of the User Manual (not in .pdf). Otherwise see Reference Manual description of TISEL registers.

Below description summarizes "Timer Instance" and "Remap" param combinations:

TIM1: any combination of TI1_RMP and TI2_RMP where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM1_TI1_RMP_GPIO
  • LL_TIM_TIM1_TI1_RMP_COMP1 (**)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM1_TI2_RMP_GPIO
  • LL_TIM_TIM1_TI2_RMP_COMP2 (**)

. . TI3_RMP can be one of the following values

  • LL_TIM_TIM1_TI3_RMP_GPIO
  • LL_TIM_TIM1_TI3_RMP_COMP3 (**)

TIM2: any combination of TI1_RMP and TI2_RMP where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM2_TI1_RMP_GPIO
  • LL_TIM_TIM2_TI1_RMP_COMP1 (**)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM2_TI2_RMP_GPIO
  • LL_TIM_TIM2_TI2_RMP_COMP2 (**)

. . TI3_RMP can be one of the following values

  • LL_TIM_TIM2_TI3_RMP_GPIO
  • LL_TIM_TIM2_TI3_RMP_COMP3 (**)

TIM3: any combination of TI1_RMP and TI2_RMP where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM3_TI1_RMP_GPIO
  • LL_TIM_TIM3_TI1_RMP_COMP1 (**)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM3_TI2_RMP_GPIO
  • LL_TIM_TIM3_TI2_RMP_COMP2 (**)

. . TI3_RMP can be one of the following values

  • LL_TIM_TIM3_TI3_RMP_GPIO
  • LL_TIM_TIM3_TI3_RMP_COMP3 (**)

TIM4: any combination of TI1_RMP, TI2_RMP and TI3_RMP where (*)

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM4_TI1_RMP_GPIO
  • LL_TIM_TIM4_TI1_RMP_COMP1 (**)

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM4_TI2_RMP_GPIO
  • LL_TIM_TIM4_TI2_RMP_COMP2 (**)

. . TI3_RMP can be one of the following values

  • LL_TIM_TIM4_TI3_RMP_GPIO
  • LL_TIM_TIM4_TI3_RMP_COMP3 (**)

TIM14: one of the following values

  • LL_TIM_TIM14_TI1_RMP_GPIO
  • LL_TIM_TIM14_TI1_RMP_RTC_CLK
  • LL_TIM_TIM14_TI1_RMP_HSE_32
  • LL_TIM_TIM14_TI1_RMP_MCO
  • LL_TIM_TIM14_TI1_RMP_MCO2 (**)

TIM15: any combination of TI1_RMP and TI2_RMP where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM15_TI1_RMP_GPIO
  • LL_TIM_TIM15_TI1_RMP_TIM2_IC1
  • LL_TIM_TIM15_TI1_RMP_TIM3_IC1

. . TI2_RMP can be one of the following values

  • LL_TIM_TIM15_TI2_RMP_GPIO
  • LL_TIM_TIM15_TI2_RMP_TIM2_IC2
  • LL_TIM_TIM15_TI2_RMP_TIM3_IC2

TIM16: one of the following values

  • LL_TIM_TIM16_TI1_RMP_GPIO
  • LL_TIM_TIM16_TI1_RMP_LSI
  • LL_TIM_TIM16_TI1_RMP_LSE
  • LL_TIM_TIM16_TI1_RMP_RTC_WK
  • LL_TIM_TIM16_TI1_RMP_MCO2(**)

TIM17: one of the following values

  • LL_TIM_TIM17_TI1_RMP_GPIO
  • LL_TIM_TIM17_TI1_RMP_HSE_32
  • LL_TIM_TIM17_TI1_RMP_MCO
  • LL_TIM_TIM17_TI1_RMP_HSI48 (**)
  • LL_TIM_TIM17_TI1_RMP_MCO2(**)

(*) Timer instance not available on all devices
(**) Value not defined in all devices.

Return values:
None

Definition at line 4217 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: OCREF_Clear_Management

Functions
OCREF_Clear_Management
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource (TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
Set the OCREF clear input source.

Function Documentation

__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OCRefClearInputSource
 | ) |  |

Set the OCREF clear input source.

Note:
The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
This function can only be used in Output compare and PWM modes.
Reference Manual to LL API cross reference:
SMCR OCCS LL_TIM_SetOCRefClearInputSource
Reference Manual to LL API cross reference:
OR1 OCREF_CLR LL_TIM_SetOCRefClearInputSource
Parameters:
TIMx Timer instance
OCRefClearInputSource This parameter can be one of the following values:
  • LL_TIM_OCREF_CLR_INT_ETR
  • LL_TIM_OCREF_CLR_INT_COMP1 (*)
  • LL_TIM_OCREF_CLR_INT_COMP2 (*)
  • LL_TIM_OCREF_CLR_INT_COMP3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 4246 of file stm32g0xx_ll_tim.h.

References OCREF_CLEAR_SELECT_Msk, and OCREF_CLEAR_SELECT_Pos.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG-Management

Functions
FLAG-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (const TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (const TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (const TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (const TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (const TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (const TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Function Documentation

__STATIC_INLINE void LL_TIM_ClearFlag_BRK ( TIM_TypeDef * TIMx )

Clear the break interrupt flag (BIF).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_ClearFlag_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4463 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_BRK2 ( TIM_TypeDef * TIMx )

Clear the break 2 interrupt flag (B2IF).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_ClearFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4485 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 interrupt flag (CC1F).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_ClearFlag_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4287 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_ClearFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4507 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 interrupt flag (CC2F).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_ClearFlag_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4309 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_ClearFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4530 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 interrupt flag (CC3F).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_ClearFlag_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4331 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_ClearFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4553 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 interrupt flag (CC4F).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_ClearFlag_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4353 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_ClearFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4576 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC5 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 5 interrupt flag (CC5F).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_ClearFlag_CC5
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4375 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC6 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 6 interrupt flag (CC6F).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_ClearFlag_CC6
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4397 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_COM ( TIM_TypeDef * TIMx )

Clear the commutation interrupt flag (COMIF).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_ClearFlag_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4419 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK ( TIM_TypeDef * TIMx )

Clear the system break interrupt flag (SBIF).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_ClearFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4599 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_TRIG ( TIM_TypeDef * TIMx )

Clear the trigger interrupt flag (TIF).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_ClearFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4441 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE ( TIM_TypeDef * TIMx )

Clear the update interrupt flag (UIF).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_ClearFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4265 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK ( const TIM_TypeDef * TIMx )

Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_IsActiveFlag_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4474 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2 ( const TIM_TypeDef * TIMx )

Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_IsActiveFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4496 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_IsActiveFlag_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4298 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4519 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_IsActiveFlag_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4320 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4542 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_IsActiveFlag_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4342 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4565 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_IsActiveFlag_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4364 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4588 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_IsActiveFlag_CC5
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4386 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6 ( const TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_IsActiveFlag_CC6
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4408 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM ( const TIM_TypeDef * TIMx )

Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_IsActiveFlag_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4430 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK ( const TIM_TypeDef * TIMx )

Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_IsActiveFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4610 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG ( const TIM_TypeDef * TIMx )

Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_IsActiveFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4452 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE ( const TIM_TypeDef * TIMx )

Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_IsActiveFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4276 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT-Management

Functions
IT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (const TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (const TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (const TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (const TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableIT_BRK ( TIM_TypeDef * TIMx )

Disable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_DisableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4870 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_DisableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4672 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_DisableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4705 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_DisableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4738 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_DisableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4771 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_COM ( TIM_TypeDef * TIMx )

Disable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_DisableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4804 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_DisableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4837 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_UPDATE ( TIM_TypeDef * TIMx )

Disable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_DisableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4639 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_BRK ( TIM_TypeDef * TIMx )

Enable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_EnableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4859 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_EnableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4661 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_EnableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4694 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_EnableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4727 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_EnableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4760 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_COM ( TIM_TypeDef * TIMx )

Enable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_EnableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4793 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_EnableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4826 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_UPDATE ( TIM_TypeDef * TIMx )

Enable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_EnableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4628 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK ( const TIM_TypeDef * TIMx )

Indicates whether the break interrupt (BIE) is enabled.

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_IsEnabledIT_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4881 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_IsEnabledIT_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4683 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_IsEnabledIT_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4716 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_IsEnabledIT_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4749 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_IsEnabledIT_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4782 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM ( const TIM_TypeDef * TIMx )

Indicates whether the commutation interrupt (COMIE) is enabled.

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_IsEnabledIT_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4815 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG ( const TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TIE) is enabled.

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_IsEnabledIT_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4848 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE ( const TIM_TypeDef * TIMx )

Indicates whether the update interrupt (UIE) is enabled.

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_IsEnabledIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4650 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Management

Functions
DMA Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (const TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (const TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (const TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_DisableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4943 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_DisableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4976 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_DisableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5009 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_DisableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5042 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_COM ( TIM_TypeDef * TIMx )

Disable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_DisableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5075 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_DisableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5108 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Disable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_DisableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4910 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_EnableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4932 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_EnableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4965 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_EnableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4998 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_EnableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5031 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_COM ( TIM_TypeDef * TIMx )

Enable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_EnableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5064 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_EnableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5097 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Enable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_EnableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4899 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4954 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4987 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5020 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4 ( const TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5053 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM ( const TIM_TypeDef * TIMx )

Indicates whether the commutation DMA request (COMDE) is enabled.

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_IsEnabledDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5086 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG ( const TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TDE) is enabled.

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 5119 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE ( const TIM_TypeDef * TIMx )

Indicates whether the update DMA request (UDE) is enabled.

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4921 of file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: EVENT-Management

Functions
EVENT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.

Function Documentation

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK ( TIM_TypeDef * TIMx )

Generate break event.

Reference Manual to LL API cross reference:
EGR BG LL_TIM_GenerateEvent_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5214 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2 ( TIM_TypeDef * TIMx )

Generate break 2 event.

Reference Manual to LL API cross reference:
EGR B2G LL_TIM_GenerateEvent_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5225 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC1 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 1 event.

Reference Manual to LL API cross reference:
EGR CC1G LL_TIM_GenerateEvent_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5148 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC2 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 2 event.

Reference Manual to LL API cross reference:
EGR CC2G LL_TIM_GenerateEvent_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5159 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC3 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 3 event.

Reference Manual to LL API cross reference:
EGR CC3G LL_TIM_GenerateEvent_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5170 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC4 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 4 event.

Reference Manual to LL API cross reference:
EGR CC4G LL_TIM_GenerateEvent_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5181 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_COM ( TIM_TypeDef * TIMx )

Generate commutation event.

Reference Manual to LL API cross reference:
EGR COMG LL_TIM_GenerateEvent_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5192 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG ( TIM_TypeDef * TIMx )

Generate trigger event.

Reference Manual to LL API cross reference:
EGR TG LL_TIM_GenerateEvent_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5203 of file stm32g0xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE ( TIM_TypeDef * TIMx )

Generate an update event.

Reference Manual to LL API cross reference:
EGR UG LL_TIM_GenerateEvent_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 5137 of file stm32g0xx_ll_tim.h.

Referenced by LL_TIM_Init().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
TIM Exported Functions

Functions

ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Function Documentation

ErrorStatus LL_TIM_BDTR_Init | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_BDTR_InitTypeDef * | TIM_BDTRInitStruct
 | ) |  |

Configure the Break and Dead Time feature of the timer instance.

Note:
As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Parameters:
TIMx | Timer Instance
TIM_BDTRInitStruct | pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Break and Dead Time is initialized
  • ERROR: not applicable

Definition at line 729 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::Break2AFMode, LL_TIM_BDTR_InitTypeDef::Break2Filter, LL_TIM_BDTR_InitTypeDef::Break2Polarity, LL_TIM_BDTR_InitTypeDef::Break2State, LL_TIM_BDTR_InitTypeDef::BreakAFMode, LL_TIM_BDTR_InitTypeDef::BreakFilter, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, IS_LL_TIM_AUTOMATIC_OUTPUT_STATE, IS_LL_TIM_BREAK2_AFMODE, IS_LL_TIM_BREAK2_FILTER, IS_LL_TIM_BREAK2_POLARITY, IS_LL_TIM_BREAK2_STATE, IS_LL_TIM_BREAK_AFMODE, IS_LL_TIM_BREAK_FILTER, IS_LL_TIM_BREAK_POLARITY, IS_LL_TIM_BREAK_STATE, IS_LL_TIM_LOCK_LEVEL, IS_LL_TIM_OSSI_STATE, IS_LL_TIM_OSSR_STATE, LL_TIM_WriteReg, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

void LL_TIM_BDTR_StructInit ( LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct )

Set the fields of the Break and Dead Time configuration data structure to their default values.

Parameters:
TIM_BDTRInitStruct pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
None

Definition at line 694 of file stm32g0xx_ll_tim.c.

References LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::Break2AFMode, LL_TIM_BDTR_InitTypeDef::Break2Filter, LL_TIM_BDTR_InitTypeDef::Break2Polarity, LL_TIM_BDTR_InitTypeDef::Break2State, LL_TIM_BDTR_InitTypeDef::BreakAFMode, LL_TIM_BDTR_InitTypeDef::BreakFilter, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, LL_TIM_AUTOMATICOUTPUT_DISABLE, LL_TIM_BREAK2_AFMODE_INPUT, LL_TIM_BREAK2_DISABLE, LL_TIM_BREAK2_FILTER_FDIV1, LL_TIM_BREAK2_POLARITY_LOW, LL_TIM_BREAK_AFMODE_INPUT, LL_TIM_BREAK_DISABLE, LL_TIM_BREAK_FILTER_FDIV1, LL_TIM_BREAK_POLARITY_LOW, LL_TIM_LOCKLEVEL_OFF, LL_TIM_OSSI_DISABLE, LL_TIM_OSSR_DISABLE, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

ErrorStatus LL_TIM_DeInit ( TIM_TypeDef * TIMx )

Set TIMx registers to their reset values.

Parameters:
TIMx Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: invalid TIMx instance

Definition at line 222 of file stm32g0xx_ll_tim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_TIM2, LL_APB1_GRP1_PERIPH_TIM3, LL_APB1_GRP1_PERIPH_TIM4, LL_APB1_GRP1_PERIPH_TIM6, LL_APB1_GRP1_PERIPH_TIM7, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_TIM1, LL_APB2_GRP1_PERIPH_TIM14, LL_APB2_GRP1_PERIPH_TIM15, LL_APB2_GRP1_PERIPH_TIM16, LL_APB2_GRP1_PERIPH_TIM17, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_TIM_ENCODER_Init | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_ENCODER_InitTypeDef * | TIM_EncoderInitStruct
 | ) |  |

Configure the encoder interface of the timer instance.

Parameters:
TIMx | Timer Instance
TIM_EncoderInitStruct | pointer to a LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 522 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_ENCODERMODE, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ReadReg, LL_TIM_SetEncoderMode(), and LL_TIM_WriteReg.

void LL_TIM_ENCODER_StructInit ( LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct )

Fills each TIM_EncoderInitStruct field with its default value.

Parameters:
TIM_EncoderInitStruct pointer to a LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
Return values:
None

Definition at line 499 of file stm32g0xx_ll_tim.c.

References LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_ENCODERMODE_X2_TI1, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_HALLSENSOR_Init | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_HALLSENSOR_InitTypeDef * | TIM_HallSensorInitStruct
 | ) |  |

Configure the Hall sensor interface of the timer instance.

Note:
TIMx CH1, CH2 and CH3 inputs connected through a XOR to the TI1 input channel
TIMx slave mode controller is configured in reset mode. Selected internal trigger is TI1F_ED.
Channel 1 is configured as input, IC1 is mapped on TRC.
Captured value stored in TIMx_CCR1 correspond to the time elapsed between 2 changes on the inputs. It gives information about motor speed.
Channel 2 is configured in output PWM 2 mode.
Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
OC2REF is selected as trigger output on TRGO.
LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used when TIMx operates in Hall sensor interface mode.
Parameters:
TIMx | Timer Instance
TIM_HallSensorInitStruct | pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 615 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ACTIVEINPUT_TRC, LL_TIM_OC_SetCompareCH2(), LL_TIM_OCMODE_PWM2, LL_TIM_ReadReg, LL_TIM_SLAVEMODE_RESET, LL_TIM_TRGO_OC2REF, LL_TIM_TS_TI1F_ED, and LL_TIM_WriteReg.

void LL_TIM_HALLSENSOR_StructInit ( LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct )

Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.

Parameters:
TIM_HallSensorInitStruct pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
Return values:
None

Definition at line 585 of file stm32g0xx_ll_tim.c.

References LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_IC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | const LL_TIM_IC_InitTypeDef * | TIM_IC_InitStruct
 | ) |  |

Configure the TIMx input channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
TIM_IC_InitStruct | pointer to a LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 468 of file stm32g0xx_ll_tim.c.

References IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, and LL_TIM_CHANNEL_CH4.

void LL_TIM_IC_StructInit ( LL_TIM_IC_InitTypeDef * TIM_ICInitStruct )

Set the fields of the TIMx input channel configuration data structure to their default values.

Parameters:
TIM_ICInitStruct pointer to a LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
Return values:
None

Definition at line 445 of file stm32g0xx_ll_tim.c.

References LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_Init | ( | TIM_TypeDef * | TIMx,
 |  | const LL_TIM_InitTypeDef * | TIM_InitStruct
 | ) |  |

Configure the TIMx time base unit.

Parameters:
TIMx | Timer Instance
TIM_InitStruct | pointer to a LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 326 of file stm32g0xx_ll_tim.c.

References assert_param, LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, IS_LL_TIM_CLOCKDIVISION, IS_LL_TIM_COUNTERMODE, LL_TIM_GenerateEvent_UPDATE(), LL_TIM_ReadReg, LL_TIM_SetAutoReload(), LL_TIM_SetPrescaler(), LL_TIM_SetRepetitionCounter(), LL_TIM_WriteReg, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

ErrorStatus LL_TIM_OC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | const LL_TIM_OC_InitTypeDef * | TIM_OC_InitStruct
 | ) |  |

Configure the TIMx output channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
TIM_OC_InitStruct | pointer to a LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 407 of file stm32g0xx_ll_tim.c.

References LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4, LL_TIM_CHANNEL_CH5, LL_TIM_CHANNEL_CH6, OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

void LL_TIM_OC_StructInit ( LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct )

Set the fields of the TIMx output channel configuration data structure to their default values.

Parameters:
TIM_OC_InitStruct pointer to a LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
Return values:
None

Definition at line 378 of file stm32g0xx_ll_tim.c.

References LL_TIM_OC_InitTypeDef::CompareValue, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCMODE_FROZEN, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCSTATE_DISABLE, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

void LL_TIM_StructInit ( LL_TIM_InitTypeDef * TIM_InitStruct )

Set the fields of the time base unit configuration data structure to their default values.

Parameters:
TIM_InitStruct pointer to a LL_TIM_InitTypeDef structure (time base unit configuration data structure)
Return values:
None

Definition at line 307 of file stm32g0xx_ll_tim.c.

References LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, LL_TIM_CLOCKDIVISION_DIV1, LL_TIM_COUNTERMODE_UP, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UCPD Private Constants

UCPD Private Constants
UCPD
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UCPD Private Macros

UCPD Private Macros
UCPD
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_UCPD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UCPD_InitTypeDef Struct Reference
UCPD Exported Init structure

UCPD Init structures definition. More...

#include <stm32g0xx_ll_ucpd.h>

Data Fields

uint32_t | psc_ucpdclk
uint32_t | transwin
uint32_t | IfrGap
uint32_t | HbitClockDiv

Detailed Description

UCPD Init structures definition.

Definition at line 53 of file stm32g0xx_ll_ucpd.h.

Field Documentation

uint32_t LL_UCPD_InitTypeDef::HbitClockDiv

Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock : "UCPD1_CLK". This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F. This feature can be modified using function LL_UCPD_SetHbitClockDiv().

Definition at line 73 of file stm32g0xx_ll_ucpd.h.

Referenced by LL_UCPD_Init(), and LL_UCPD_StructInit().

uint32_t LL_UCPD_InitTypeDef::IfrGap

Specify the definition of the clock divider (minus 1) in order to generate tInterframeGap from the peripheral clock. This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F This feature can be modified afterwards using function LL_UCPD_SetIfrGap().

Definition at line 67 of file stm32g0xx_ll_ucpd.h.

Referenced by LL_UCPD_Init(), and LL_UCPD_StructInit().

uint32_t LL_UCPD_InitTypeDef::psc_ucpdclk

Specify the prescaler for the UCPD clock. This parameter can be a value of prescaler for UCPDCLK. This feature can be modified afterwards using function LL_UCPD_SetPSCClk().

Definition at line 55 of file stm32g0xx_ll_ucpd.h.

Referenced by LL_UCPD_Init(), and LL_UCPD_StructInit().

uint32_t LL_UCPD_InitTypeDef::transwin

Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal tTransitionWindow (set according to peripheral clock to define an interval of between 12 and 20 us). This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F This value can be modified afterwards using function LL_UCPD_SetTransWin().

Definition at line 60 of file stm32g0xx_ll_ucpd.h.

Referenced by LL_UCPD_Init(), and LL_UCPD_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_ucpd.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
UCPD Exported Constants

Flags defines which can be used with LL_ucpd_ReadReg function. More...

Defines

#define | LL_UCPD_SR_TXIS UCPD_SR_TXIS
#define | LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC
#define | LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT
#define | LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT
#define | LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC
#define | LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT
#define | LL_UCPD_SR_TXUND UCPD_SR_TXUND
#define | LL_UCPD_SR_RXNE UCPD_SR_RXNE
#define | LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET
#define | LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET
#define | LL_UCPD_SR_RXOVR UCPD_SR_RXOVR
#define | LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND
#define | LL_UCPD_SR_RXERR UCPD_SR_RXERR
#define | LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1
#define | LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2
#define | LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1
#define | LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2
#define | LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT

Detailed Description

Flags defines which can be used with LL_ucpd_ReadReg function.

Define Documentation

#define LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT

Fast Role Swap detection event

Definition at line 113 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC

HRST discarded interrupt

Definition at line 100 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT

HRST sent interrupt

Definition at line 101 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_RXERR UCPD_SR_RXERR

Rx error

Definition at line 108 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET

Rx Hard Reset detect interrupt

Definition at line 105 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND

Rx message received

Definition at line 107 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_RXNE UCPD_SR_RXNE

Receive data register not empty interrupt

Definition at line 103 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET

Rx ordered set (4 K-codes) detected interrupt

Definition at line 104 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR

Rx data overflow interrupt

Definition at line 106 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TXIS UCPD_SR_TXIS

Transmit interrupt status

Definition at line 96 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT

Transmit message abort interrupt

Definition at line 99 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC

Transmit message discarded interrupt

Definition at line 97 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT

Transmit message sent interrupt

Definition at line 98 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TXUND UCPD_SR_TXUND

Tx data underrun condition interrupt

Definition at line 102 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1

Status of DC level on CC1 pin

Definition at line 111 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2

Status of DC level on CC2 pin

Definition at line 112 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1

Type C voltage level event on CC1

Definition at line 109 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2

Type C voltage level event on CC2

Definition at line 110 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
UCPD Exported Constants

IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions. More...

Defines

#define | LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE
#define | LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE
#define | LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE
#define | LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE
#define | LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE
#define | LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE
#define | LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE
#define | LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE
#define | LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE
#define | LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE
#define | LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE
#define | LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE
#define | LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE
#define | LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE
#define | LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE

Detailed Description

IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions.

Define Documentation

#define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE

Enable fast Role Swap detection event

Definition at line 137 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE

Enable HRST discarded interrupt

Definition at line 127 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE

Enable HRST sent interrupt

Definition at line 128 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE

Enable Rx Hard Reset detect interrupt

Definition at line 132 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE

Enable Rx message received

Definition at line 134 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE

Enable Receive data register not empty interrupt

Definition at line 130 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE

Enable Rx ordered set (4 K-codes) detected interrupt

Definition at line 131 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE

Enable Rx data overflow interrupt

Definition at line 133 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE

Enable transmit interrupt status

Definition at line 123 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE

Enable transmit message abort interrupt

Definition at line 126 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE

Enable transmit message discarded interrupt

Definition at line 124 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE

Enable transmit message sent interrupt

Definition at line 125 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE

Enable tx data underrun condition interrupt

Definition at line 129 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE

Enable Type C voltage level event on CC1

Definition at line 135 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE

Enable Type C voltage level event on CC2

Definition at line 136 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Ordered sets value

Defines
Ordered sets value
UCPD Exported Constants

definition of the usual Ordered sets More...

Defines

#define | LL_UCPD_SYNC1 0x18u
#define | LL_UCPD_SYNC2 0x11u
#define | LL_UCPD_SYNC3 0x06u
#define | LL_UCPD_RST1 0x07u
#define | LL_UCPD_RST2 0x19u
#define | LL_UCPD_EOP 0x0Du
#define | LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u))
#define | LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u ))
#define | LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u))

Detailed Description

definition of the usual Ordered sets

Define Documentation

#define LL_UCPD_EOP 0x0Du

K-code for EOP End of Packet

Definition at line 152 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u))

Cable Reset Ordered set coding

Definition at line 158 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u ))

Hard Reset Ordered set coding

Definition at line 157 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u))

SOP Ordered set coding

Definition at line 154 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u))

SOP' Ordered set coding

Definition at line 155 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u))

SOP' Debug Ordered set coding

Definition at line 159 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u))

SOP'' Ordered set coding

Definition at line 156 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u))

SOP'' Debug Ordered set coding

Definition at line 160 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RST1 0x07u

K-code for Hard Reset #1

Definition at line 150 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RST2 0x19u

K-code for Hard Reset #2

Definition at line 151 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SYNC1 0x18u

K-code for Startsynch #1

Definition at line 147 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SYNC2 0x11u

K-code for Startsynch #2

Definition at line 148 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SYNC3 0x06u

K-code for Startsynch #3

Definition at line 149 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Role Mode

Defines
Role Mode
UCPD Exported Constants

Defines

#define | LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE
#define | LL_UCPD_ROLE_SRC 0x0U

Define Documentation

#define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE

Mode SNK Rd

Definition at line 168 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ROLE_SRC 0x0U

Mode SRC Rp

Definition at line 169 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Resistor value

Defines
Resistor value
UCPD Exported Constants

Defines

#define | LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0
#define | LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1
#define | LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE
#define | LL_UCPD_RESISTOR_NONE 0x0U

Define Documentation

#define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1

Rp 1.5 A

Definition at line 178 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE

Rp 3.0 A

Definition at line 179 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0

Rp default

Definition at line 177 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RESISTOR_NONE 0x0U

No resistor

Definition at line 180 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ordered set configuration

Defines
ordered set configuration
UCPD Exported Constants

Defines

#define | LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0
#define | LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1
#define | LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2
#define | LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3
#define | LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4
#define | LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5
#define | LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6
#define | LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7
#define | LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8

Define Documentation

#define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4

Cable Reset Ordered set detection enabled

Definition at line 192 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3

Hard Reset Ordered set detection enabled

Definition at line 191 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0

SOP Ordered set detection enabled

Definition at line 188 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1

SOP' Ordered set detection enabled

Definition at line 189 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5

SOP' Debug Ordered set detection enabled

Definition at line 193 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2

SOP'' Ordered set detection enabled

Definition at line 190 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6

SOP'' Debug Ordered set detection enabled

Definition at line 194 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7

SOP extension#1 Ordered set detection enabled

Definition at line 195 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8

SOP extension#2 Ordered set detection enabled

Definition at line 196 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CCx event

Defines
CCx event
UCPD Exported Constants

Defines

#define | LL_UCPD_SNK_CC1_VOPEN 0x00u
#define | LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0
#define | LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1
#define | LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)
#define | LL_UCPD_SNK_CC2_VOPEN 0x00u
#define | LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0
#define | LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1
#define | LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)
#define | LL_UCPD_SRC_CC1_VRA 0x0U
#define | LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0
#define | LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1
#define | LL_UCPD_SRC_CC2_VRA 0x0U
#define | LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0
#define | LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1

Define Documentation

#define LL_UCPD_SNK_CC1_VOPEN 0x00u

CC1 Sink Open state

Definition at line 204 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0

CC1 Sink vRP default state

Definition at line 205 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1

CC1 Sink vRP 1.5A state

Definition at line 206 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)

CC1 Sink vRP 3.0A state

Definition at line 207 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC2_VOPEN 0x00u

CC2 Sink Open state

Definition at line 209 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0

CC2 Sink vRP default state

Definition at line 210 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1

CC2 Sink vRP 1.5A state

Definition at line 211 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)

CC2 Sink vRP 3.0A state

Definition at line 212 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1

CC1 Source Open state

Definition at line 216 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC1_VRA 0x0U

CC1 Source vRA state

Definition at line 214 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0

CC1 Source vRD state

Definition at line 215 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1

CC2 Source Open state

Definition at line 220 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC2_VRA 0x0U

CC2 Source vRA state

Definition at line 218 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0

CC2 Source vRD state

Definition at line 219 of file stm32g0xx_ll_ucpd.h.

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STM32G0C1xx HAL User Manual: prescaler for UCPDCLK

Defines
prescaler for UCPDCLK
UCPD Exported Constants

Defines

#define | LL_UCPD_PSC_DIV1 0x0u
#define | LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0
#define | LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1
#define | LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)
#define | LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2

Define Documentation

#define LL_UCPD_PSC_DIV1 0x0u

Bypass pre-scaling / divide by 1

Definition at line 228 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2

Pre-scale clock by dividing by 16

Definition at line 232 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0

Pre-scale clock by dividing by 2

Definition at line 229 of file stm32g0xx_ll_ucpd.h.

Referenced by LL_UCPD_StructInit().

#define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1

Pre-scale clock by dividing by 4

Definition at line 230 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)

Pre-scale clock by dividing by 8

Definition at line 231 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CC pin enable

Defines
CC pin enable
UCPD Exported Constants

Defines

#define | LL_UCPD_CCENABLE_NONE 0x0U
#define | LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0
#define | LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1
#define | LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)

Define Documentation

#define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0

Controls apply to only CC1

Definition at line 241 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)

Controls apply to both CC1 and CC2 (normal usage for sink/source)

Definition at line 243 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1

Controls apply to only CC1

Definition at line 242 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_CCENABLE_NONE 0x0U

Neither PHY is activated (e.g. disabled state of source)

Definition at line 240 of file stm32g0xx_ll_ucpd.h.

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STM32G0C1xx HAL User Manual: CC pin selection

Defines
CC pin selection
UCPD Exported Constants

Defines

#define | LL_UCPD_CCPIN_CC1 0x0U
#define | LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL

Define Documentation

#define LL_UCPD_CCPIN_CC1 0x0U

Use CC1 IO for power delivery communication

Definition at line 251 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL

Use CC2 IO for power delivery communication

Definition at line 252 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Receiver mode

Defines
Receiver mode
UCPD Exported Constants

Defines

#define | LL_UCPD_RXMODE_NORMAL 0x0U
#define | LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE

Define Documentation

#define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE

BIST receive mode (BIST Test Data Mode)

Definition at line 261 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RXMODE_NORMAL 0x0U

Normal receive mode

Definition at line 260 of file stm32g0xx_ll_ucpd.h.

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STM32G0C1xx HAL User Manual: Type of Tx packet

Defines
Type of Tx packet
UCPD Exported Constants

Defines

#define | LL_UCPD_TXMODE_NORMAL 0x0U
#define | LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0
#define | LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1

Define Documentation

#define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1

Trigger a BIST test sequence send (BIST Carrier Mode 2)

Definition at line 271 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0

Trigger a the transfer of a Cable Reset sequence

Definition at line 270 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_TXMODE_NORMAL 0x0U

Initiate the transfer of a Tx message

Definition at line 269 of file stm32g0xx_ll_ucpd.h.

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STM32G0C1xx HAL User Manual: Rx ordered set code detected

Defines
Rx ordered set code detected
UCPD Exported Constants

Defines

#define | LL_UCPD_RXORDSET_SOP 0x0U
#define | LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0
#define | LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1
#define | LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)
#define | LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2
#define | LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)
#define | LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)
#define | LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)

Define Documentation

#define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)

Cable Reset code detected in receiver

Definition at line 284 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP 0x0U

SOP code detected in receiver

Definition at line 279 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0

SOP' code detected in receiver

Definition at line 280 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)

SOP' Debug code detected in receiver

Definition at line 282 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1

SOP'' code detected in receiver

Definition at line 281 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2

SOP'' Debug code detected in receiver

Definition at line 283 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)

SOP extension#1 code detected in receiver

Definition at line 285 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)

SOP extension#2 code detected in receiver

Definition at line 286 of file stm32g0xx_ll_ucpd.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
UCPD Exported Macros

Defines

#define | LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in UCPD register.
#define | LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in UCPD register.

Define Documentation

#define LL_UCPD_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in UCPD register.

Parameters:
__INSTANCE__ | UCPD Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 319 of file stm32g0xx_ll_ucpd.h.

#define LL_UCPD_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in UCPD register.

Parameters:
__INSTANCE__ | UCPD Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 311 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CFG1 register

Functions
CFG1 register
Configuration

Functions

__STATIC_INLINE void | LL_UCPD_Enable (UCPD_TypeDef *UCPDx)
Enable UCPD peripheral.
__STATIC_INLINE void | LL_UCPD_Disable (UCPD_TypeDef *UCPDx)
Disable UCPD peripheral.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabled (UCPD_TypeDef const *const UCPDx)
Check if UCPD peripheral is enabled.
__STATIC_INLINE void | LL_UCPD_SetRxOrderSet (UCPD_TypeDef *UCPDx, uint32_t OrderSet)
Set the receiver ordered set detection enable.
__STATIC_INLINE void | LL_UCPD_SetPSCClk (UCPD_TypeDef *UCPDx, uint32_t Psc)
Set the prescaler for ucpd clock.
__STATIC_INLINE void | LL_UCPD_SetTransWin (UCPD_TypeDef *UCPDx, uint32_t TransWin)
Set the number of cycles (minus 1) of the half bit clock.
__STATIC_INLINE void | LL_UCPD_SetIfrGap (UCPD_TypeDef *UCPDx, uint32_t IfrGap)
Set the clock divider value to generate an interframe gap.
__STATIC_INLINE void | LL_UCPD_SetHbitClockDiv (UCPD_TypeDef *UCPDx, uint32_t HbitClock)
Set the clock divider value to generate an interframe gap.

Function Documentation

__STATIC_INLINE void LL_UCPD_Disable ( UCPD_TypeDef * UCPDx )

Disable UCPD peripheral.

Note:
When disabling the UCPD, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CFG1 UCPDEN LL_UCPD_Disable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 358 of file stm32g0xx_ll_ucpd.h.

Referenced by LL_UCPD_DeInit(), and LL_UCPD_Init().

__STATIC_INLINE void LL_UCPD_Enable ( UCPD_TypeDef * UCPDx )

Enable UCPD peripheral.

Reference Manual to LL API cross reference:
CFG1 UCPDEN LL_UCPD_Enable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 346 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnabled ( UCPD_TypeDef const *const UCPDx )

Check if UCPD peripheral is enabled.

Reference Manual to LL API cross reference:
CFG1 UCPDEN LL_UCPD_IsEnabled
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 369 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetHbitClockDiv | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | HbitClock
 | ) |  |

Set the clock divider value to generate an interframe gap.

Reference Manual to LL API cross reference:
CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
Parameters:
UCPDx | UCPD Instance
HbitClock | a value between Min_Data=0x0 and Max_Data=0x3F
Return values:
None

Definition at line 443 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetIfrGap | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | IfrGap
 | ) |  |

Set the clock divider value to generate an interframe gap.

Reference Manual to LL API cross reference:
CFG1 IFRGAP LL_UCPD_SetIfrGap
Parameters:
UCPDx | UCPD Instance
IfrGap | a value between Min_Data=0x1 and Max_Data=0x1F
Return values:
None

Definition at line 431 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetPSCClk | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | Psc
 | ) |  |

Set the prescaler for ucpd clock.

Reference Manual to LL API cross reference:
CFG1 UCPDCLK LL_UCPD_SetPSCClk
Parameters:
UCPDx UCPD Instance
Psc This parameter can be one of the following values:
  • LL_UCPD_PSC_DIV1
  • LL_UCPD_PSC_DIV2
  • LL_UCPD_PSC_DIV4
  • LL_UCPD_PSC_DIV8
  • LL_UCPD_PSC_DIV16
Return values:
None

Definition at line 407 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRxOrderSet | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | OrderSet
 | ) |  |

Set the receiver ordered set detection enable.

Reference Manual to LL API cross reference:
CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
Parameters:
UCPDx UCPD Instance
OrderSet This parameter can be combination of the following values:
  • LL_UCPD_ORDERSET_SOP
  • LL_UCPD_ORDERSET_SOP1
  • LL_UCPD_ORDERSET_SOP2
  • LL_UCPD_ORDERSET_HARDRST
  • LL_UCPD_ORDERSET_CABLERST
  • LL_UCPD_ORDERSET_SOP1_DEBUG
  • LL_UCPD_ORDERSET_SOP2_DEBUG
  • LL_UCPD_ORDERSET_SOP_EXT1
  • LL_UCPD_ORDERSET_SOP_EXT2
Return values:
None

Definition at line 390 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetTransWin | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | TransWin
 | ) |  |

Set the number of cycles (minus 1) of the half bit clock.

Reference Manual to LL API cross reference:
CFG1 TRANSWIN LL_UCPD_SetTransWin
Parameters:
UCPDx | UCPD Instance
TransWin | a value between Min_Data=0x1 and Max_Data=0x1F
Return values:
None

Definition at line 419 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CFG2 register

Functions
CFG2 register
Configuration

Functions

__STATIC_INLINE void | LL_UCPD_WakeUpEnable (UCPD_TypeDef *UCPDx)
Enable the wakeup mode.
__STATIC_INLINE void | LL_UCPD_WakeUpDisable (UCPD_TypeDef *UCPDx)
Disable the wakeup mode.
__STATIC_INLINE void | LL_UCPD_ForceClockEnable (UCPD_TypeDef *UCPDx)
Force clock enable.
__STATIC_INLINE void | LL_UCPD_ForceClockDisable (UCPD_TypeDef *UCPDx)
Force clock disable.
__STATIC_INLINE void | LL_UCPD_RxFilterEnable (UCPD_TypeDef *UCPDx)
RxFilter enable.
__STATIC_INLINE void | LL_UCPD_RxFilterDisable (UCPD_TypeDef *UCPDx)
RxFilter disable.

Function Documentation

__STATIC_INLINE void LL_UCPD_ForceClockDisable ( UCPD_TypeDef * UCPDx )

Force clock disable.

Reference Manual to LL API cross reference:
CFG2 FORCECLK LL_UCPD_ForceClockDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 495 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ForceClockEnable ( UCPD_TypeDef * UCPDx )

Force clock enable.

Reference Manual to LL API cross reference:
CFG2 FORCECLK LL_UCPD_ForceClockEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 484 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxFilterDisable ( UCPD_TypeDef * UCPDx )

RxFilter disable.

Reference Manual to LL API cross reference:
CFG2 RXFILTDIS LL_UCPD_RxFilterDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 517 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxFilterEnable ( UCPD_TypeDef * UCPDx )

RxFilter enable.

Reference Manual to LL API cross reference:
CFG2 RXFILTDIS LL_UCPD_RxFilterEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 506 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WakeUpDisable ( UCPD_TypeDef * UCPDx )

Disable the wakeup mode.

Reference Manual to LL API cross reference:
CFG2 WUPEN LL_UCPD_WakeUpDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 473 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WakeUpEnable ( UCPD_TypeDef * UCPDx )

Enable the wakeup mode.

Reference Manual to LL API cross reference:
CFG2 WUPEN LL_UCPD_WakeUpEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 462 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CR register

Functions
CR register
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC2Enable (UCPD_TypeDef *UCPDx)
Type C detector for CC2 enable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC2Disable (UCPD_TypeDef *UCPDx)
Type C detector for CC2 disable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC1Enable (UCPD_TypeDef *UCPDx)
Type C detector for CC1 enable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC1Disable (UCPD_TypeDef *UCPDx)
Type C detector for CC1 disable.
__STATIC_INLINE void | LL_UCPD_VconnDischargeEnable (UCPD_TypeDef *UCPDx)
Source Vconn discharge enable.
__STATIC_INLINE void | LL_UCPD_VconnDischargeDisable (UCPD_TypeDef *UCPDx)
Source Vconn discharge disable.
__STATIC_INLINE void | LL_UCPD_SignalFRSTX (UCPD_TypeDef *UCPDx)
Signal Fast Role Swap request.
__STATIC_INLINE void | LL_UCPD_FRSDetectionEnable (UCPD_TypeDef *UCPDx)
Fast Role swap RX detection enable.
__STATIC_INLINE void | LL_UCPD_FRSDetectionDisable (UCPD_TypeDef *UCPDx)
Fast Role swap RX detection disable.
__STATIC_INLINE void | LL_UCPD_SetccEnable (UCPD_TypeDef *UCPDx, uint32_t CCEnable)
Set cc enable.
__STATIC_INLINE void | LL_UCPD_SetSNKRole (UCPD_TypeDef *UCPDx)
Set UCPD SNK role.
__STATIC_INLINE void | LL_UCPD_SetSRCRole (UCPD_TypeDef *UCPDx)
Set UCPD SRC role.
__STATIC_INLINE uint32_t | LL_UCPD_GetRole (UCPD_TypeDef const *const UCPDx)
Get UCPD Role.
__STATIC_INLINE void | LL_UCPD_SetRpResistor (UCPD_TypeDef *UCPDx, uint32_t Resistor)
Set Rp resistor.
__STATIC_INLINE void | LL_UCPD_SetCCPin (UCPD_TypeDef *UCPDx, uint32_t CCPin)
Set CC pin.
__STATIC_INLINE void | LL_UCPD_RxEnable (UCPD_TypeDef *UCPDx)
Rx enable.
__STATIC_INLINE void | LL_UCPD_RxDisable (UCPD_TypeDef *UCPDx)
Rx disable.
__STATIC_INLINE void | LL_UCPD_SetRxMode (UCPD_TypeDef *UCPDx, uint32_t RxMode)
Set Rx mode.
__STATIC_INLINE void | LL_UCPD_SendHardReset (UCPD_TypeDef *UCPDx)
Send Hard Reset.
__STATIC_INLINE void | LL_UCPD_SendMessage (UCPD_TypeDef *UCPDx)
Send message.
__STATIC_INLINE void | LL_UCPD_SetTxMode (UCPD_TypeDef *UCPDx, uint32_t TxMode)
Set Tx mode.

Function Documentation

__STATIC_INLINE void LL_UCPD_FRSDetectionDisable ( UCPD_TypeDef * UCPDx )

Fast Role swap RX detection disable.

Reference Manual to LL API cross reference:
CR FRSRXEN LL_UCPD_FRSDetectionDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 627 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_FRSDetectionEnable ( UCPD_TypeDef * UCPDx )

Fast Role swap RX detection enable.

Reference Manual to LL API cross reference:
CR FRSRXEN LL_UCPD_FRSDetectionEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 616 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_GetRole ( UCPD_TypeDef const *const UCPDx )

Get UCPD Role.

Reference Manual to LL API cross reference:
CR ANAMODE LL_UCPD_GetRole
Parameters:
UCPDx UCPD Instance
Return values:
Returned value can be one of the following values:
  • LL_UCPD_ROLE_SNK
  • LL_UCPD_ROLE_SRC

Definition at line 678 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxDisable ( UCPD_TypeDef * UCPDx )

Rx disable.

Reference Manual to LL API cross reference:
CR PHYRXEN LL_UCPD_RxDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 730 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxEnable ( UCPD_TypeDef * UCPDx )

Rx enable.

Reference Manual to LL API cross reference:
CR PHYRXEN LL_UCPD_RxEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 719 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SendHardReset ( UCPD_TypeDef * UCPDx )

Send Hard Reset.

Reference Manual to LL API cross reference:
CR TXHRST LL_UCPD_SendHardReset
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 755 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SendMessage ( UCPD_TypeDef * UCPDx )

Send message.

Reference Manual to LL API cross reference:
CR TXSEND LL_UCPD_SendMessage
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 766 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetccEnable | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | CCEnable
 | ) |  |

Set cc enable.

Reference Manual to LL API cross reference:
CR CC1VCONNEN LL_UCPD_SetccEnable
Parameters:
UCPDx UCPD Instance
CCEnable This parameter can be one of the following values:
  • LL_UCPD_CCENABLE_NONE
  • LL_UCPD_CCENABLE_CC1
  • LL_UCPD_CCENABLE_CC2
  • LL_UCPD_CCENABLE_CC1CC2
Return values:
None

Definition at line 643 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetCCPin | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | CCPin
 | ) |  |

Set CC pin.

Reference Manual to LL API cross reference:
CR PHYCCSEL LL_UCPD_SetCCPin
Parameters:
UCPDx UCPD Instance
CCPin This parameter can be one of the following values:
  • LL_UCPD_CCPIN_CC1
  • LL_UCPD_CCPIN_CC2
Return values:
None

Definition at line 708 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRpResistor | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | Resistor
 | ) |  |

Set Rp resistor.

Reference Manual to LL API cross reference:
CR ANASUBMODE LL_UCPD_SetRpResistor
Parameters:
UCPDx UCPD Instance
Resistor This parameter can be one of the following values:
  • LL_UCPD_RESISTOR_DEFAULT
  • LL_UCPD_RESISTOR_1_5A
  • LL_UCPD_RESISTOR_3_0A
  • LL_UCPD_RESISTOR_NONE
Return values:
None

Definition at line 694 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRxMode | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | RxMode
 | ) |  |

Set Rx mode.

Reference Manual to LL API cross reference:
CR RXMODE LL_UCPD_SetRxMode
Parameters:
UCPDx UCPD Instance
RxMode This parameter can be one of the following values:
  • LL_UCPD_RXMODE_NORMAL
  • LL_UCPD_RXMODE_BIST_TEST_DATA
Return values:
None

Definition at line 744 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetSNKRole ( UCPD_TypeDef * UCPDx )

Set UCPD SNK role.

Reference Manual to LL API cross reference:
CR ANAMODE LL_UCPD_SetSNKRole
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 654 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetSRCRole ( UCPD_TypeDef * UCPDx )

Set UCPD SRC role.

Reference Manual to LL API cross reference:
CR ANAMODE LL_UCPD_SetSRCRole
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 665 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetTxMode | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | TxMode
 | ) |  |

Set Tx mode.

Reference Manual to LL API cross reference:
CR TXMODE LL_UCPD_SetTxMode
Parameters:
UCPDx UCPD Instance
TxMode This parameter can be one of the following values:
  • LL_UCPD_TXMODE_NORMAL
  • LL_UCPD_TXMODE_CABLE_RESET
  • LL_UCPD_TXMODE_BIST_CARRIER2
Return values:
None

Definition at line 781 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SignalFRSTX ( UCPD_TypeDef * UCPDx )

Signal Fast Role Swap request.

Reference Manual to LL API cross reference:
CR FRSTX LL_UCPD_VconnDischargeDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 605 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable ( UCPD_TypeDef * UCPDx )

Type C detector for CC1 disable.

Reference Manual to LL API cross reference:
CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 572 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable ( UCPD_TypeDef * UCPDx )

Type C detector for CC1 enable.

Reference Manual to LL API cross reference:
CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 561 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable ( UCPD_TypeDef * UCPDx )

Type C detector for CC2 disable.

Reference Manual to LL API cross reference:
CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 550 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable ( UCPD_TypeDef * UCPDx )

Type C detector for CC2 enable.

Reference Manual to LL API cross reference:
CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 539 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_VconnDischargeDisable ( UCPD_TypeDef * UCPDx )

Source Vconn discharge disable.

Reference Manual to LL API cross reference:
CR RDCH LL_UCPD_VconnDischargeDisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 594 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_VconnDischargeEnable ( UCPD_TypeDef * UCPDx )

Source Vconn discharge enable.

Reference Manual to LL API cross reference:
CR RDCH LL_UCPD_VconnDischargeEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 583 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_EnableIT_FRS (UCPD_TypeDef *UCPDx)
Enable FRS interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Enable type c event on CC2.
__STATIC_INLINE void | LL_UCPD_EnableIT_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Enable type c event on CC1.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxMsgEnd (UCPD_TypeDef *UCPDx)
Enable Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxOvr (UCPD_TypeDef *UCPDx)
Enable Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxHRST (UCPD_TypeDef *UCPDx)
Enable Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxOrderSet (UCPD_TypeDef *UCPDx)
Enable Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxNE (UCPD_TypeDef *UCPDx)
Enable Rx non empty interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxUND (UCPD_TypeDef *UCPDx)
Enable TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Enable hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Enable hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGABT (UCPD_TypeDef *UCPDx)
Enable Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGSENT (UCPD_TypeDef *UCPDx)
Enable Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGDISC (UCPD_TypeDef *UCPDx)
Enable Tx message discarded interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxIS (UCPD_TypeDef *UCPDx)
Enable Tx data receive interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_FRS (UCPD_TypeDef *UCPDx)
Disable FRS interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Disable type c event on CC2.
__STATIC_INLINE void | LL_UCPD_DisableIT_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Disable type c event on CC1.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxMsgEnd (UCPD_TypeDef *UCPDx)
Disable Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxOvr (UCPD_TypeDef *UCPDx)
Disable Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxHRST (UCPD_TypeDef *UCPDx)
Disable Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxOrderSet (UCPD_TypeDef *UCPDx)
Disable Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxNE (UCPD_TypeDef *UCPDx)
Disable Rx non empty interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxUND (UCPD_TypeDef *UCPDx)
Disable TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Disable hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Disable hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGABT (UCPD_TypeDef *UCPDx)
Disable Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGSENT (UCPD_TypeDef *UCPDx)
Disable Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGDISC (UCPD_TypeDef *UCPDx)
Disable Tx message discarded interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxIS (UCPD_TypeDef *UCPDx)
Disable Tx data receive interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_FRS (UCPD_TypeDef const *const UCPDx)
Check if FRS interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TypeCEventCC2 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC2 enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TypeCEventCC1 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC1 enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxMsgEnd (UCPD_TypeDef const *const UCPDx)
Check if Rx message end interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxOvr (UCPD_TypeDef const *const UCPDx)
Check if Rx overrun interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxHRST (UCPD_TypeDef const *const UCPDx)
Check if Rx hard resrt interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxOrderSet (UCPD_TypeDef const *const UCPDx)
Check if Rx orderset interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxNE (UCPD_TypeDef const *const UCPDx)
Check if Rx non empty interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxUND (UCPD_TypeDef const *const UCPDx)
Check if TX underrun interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxHRSTSENT (UCPD_TypeDef const *const UCPDx)
Check if hard reset sent interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxHRSTDISC (UCPD_TypeDef const *const UCPDx)
Check if hard reset discard interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGABT (UCPD_TypeDef const *const UCPDx)
Check if Tx message abort interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGSENT (UCPD_TypeDef const *const UCPDx)
Check if Tx message sent interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGDISC (UCPD_TypeDef const *const UCPDx)
Check if Tx message discarded interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxIS (UCPD_TypeDef const *const UCPDx)
Check if Tx data receive interrupt enabled.

Function Documentation

__STATIC_INLINE void LL_UCPD_DisableIT_FRS ( UCPD_TypeDef * UCPDx )

Disable FRS interrupt.

Reference Manual to LL API cross reference:
IMR FRSEVTIE LL_UCPD_DisableIT_FRS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 965 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST ( UCPD_TypeDef * UCPDx )

Disable Rx hard resrt interrupt.

Reference Manual to LL API cross reference:
IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1020 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd ( UCPD_TypeDef * UCPDx )

Disable Rx message end interrupt.

Reference Manual to LL API cross reference:
IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 998 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxNE ( UCPD_TypeDef * UCPDx )

Disable Rx non empty interrupt.

Reference Manual to LL API cross reference:
IMR RXNEIE LL_UCPD_DisableIT_RxNE
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1042 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet ( UCPD_TypeDef * UCPDx )

Disable Rx orderset interrupt.

Reference Manual to LL API cross reference:
IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1031 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr ( UCPD_TypeDef * UCPDx )

Disable Rx overrun interrupt.

Reference Manual to LL API cross reference:
IMR RXOVRIE LL_UCPD_DisableIT_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1009 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC ( UCPD_TypeDef * UCPDx )

Disable hard reset discard interrupt.

Reference Manual to LL API cross reference:
IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1075 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT ( UCPD_TypeDef * UCPDx )

Disable hard reset sent interrupt.

Reference Manual to LL API cross reference:
IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1064 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxIS ( UCPD_TypeDef * UCPDx )

Disable Tx data receive interrupt.

Reference Manual to LL API cross reference:
IMR TXISIE LL_UCPD_DisableIT_TxIS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1119 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT ( UCPD_TypeDef * UCPDx )

Disable Tx message abort interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1086 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC ( UCPD_TypeDef * UCPDx )

Disable Tx message discarded interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1108 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT ( UCPD_TypeDef * UCPDx )

Disable Tx message sent interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1097 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TxUND ( UCPD_TypeDef * UCPDx )

Disable TX underrun interrupt.

Reference Manual to LL API cross reference:
IMR TXUNDIE LL_UCPD_DisableIT_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1053 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1 ( UCPD_TypeDef * UCPDx )

Disable type c event on CC1.

Reference Manual to LL API cross reference:
IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 987 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2 ( UCPD_TypeDef * UCPDx )

Disable type c event on CC2.

Reference Manual to LL API cross reference:
IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 976 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_FRS ( UCPD_TypeDef * UCPDx )

Enable FRS interrupt.

Reference Manual to LL API cross reference:
IMR FRSEVTIE LL_UCPD_EnableIT_FRS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 800 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST ( UCPD_TypeDef * UCPDx )

Enable Rx hard resrt interrupt.

Reference Manual to LL API cross reference:
IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 855 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd ( UCPD_TypeDef * UCPDx )

Enable Rx message end interrupt.

Reference Manual to LL API cross reference:
IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 833 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxNE ( UCPD_TypeDef * UCPDx )

Enable Rx non empty interrupt.

Reference Manual to LL API cross reference:
IMR RXNEIE LL_UCPD_EnableIT_RxNE
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 877 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet ( UCPD_TypeDef * UCPDx )

Enable Rx orderset interrupt.

Reference Manual to LL API cross reference:
IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 866 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr ( UCPD_TypeDef * UCPDx )

Enable Rx overrun interrupt.

Reference Manual to LL API cross reference:
IMR RXOVRIE LL_UCPD_EnableIT_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 844 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC ( UCPD_TypeDef * UCPDx )

Enable hard reset discard interrupt.

Reference Manual to LL API cross reference:
IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 910 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT ( UCPD_TypeDef * UCPDx )

Enable hard reset sent interrupt.

Reference Manual to LL API cross reference:
IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 899 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxIS ( UCPD_TypeDef * UCPDx )

Enable Tx data receive interrupt.

Reference Manual to LL API cross reference:
IMR TXISIE LL_UCPD_EnableIT_TxIS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 954 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT ( UCPD_TypeDef * UCPDx )

Enable Tx message abort interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 921 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC ( UCPD_TypeDef * UCPDx )

Enable Tx message discarded interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 943 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT ( UCPD_TypeDef * UCPDx )

Enable Tx message sent interrupt.

Reference Manual to LL API cross reference:
IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 932 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TxUND ( UCPD_TypeDef * UCPDx )

Enable TX underrun interrupt.

Reference Manual to LL API cross reference:
IMR TXUNDIE LL_UCPD_EnableIT_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 888 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1 ( UCPD_TypeDef * UCPDx )

Enable type c event on CC1.

Reference Manual to LL API cross reference:
IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 822 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2 ( UCPD_TypeDef * UCPDx )

Enable type c event on CC2.

Reference Manual to LL API cross reference:
IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 811 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS ( UCPD_TypeDef const *const UCPDx )

Check if FRS interrupt enabled.

Reference Manual to LL API cross reference:
IMR FRSEVTIE LL_UCPD_DisableIT_FRS
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1130 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST ( UCPD_TypeDef const *const UCPDx )

Check if Rx hard resrt interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1185 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd ( UCPD_TypeDef const *const UCPDx )

Check if Rx message end interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1163 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE ( UCPD_TypeDef const *const UCPDx )

Check if Rx non empty interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXNEIE LL_UCPD_IsEnableIT_RxNE
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1207 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet ( UCPD_TypeDef const *const UCPDx )

Check if Rx orderset interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1196 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr ( UCPD_TypeDef const *const UCPDx )

Check if Rx overrun interrupt enabled.

Reference Manual to LL API cross reference:
IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1174 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC ( UCPD_TypeDef const *const UCPDx )

Check if hard reset discard interrupt enabled.

Reference Manual to LL API cross reference:
IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1240 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT ( UCPD_TypeDef const *const UCPDx )

Check if hard reset sent interrupt enabled.

Reference Manual to LL API cross reference:
IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1229 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS ( UCPD_TypeDef const *const UCPDx )

Check if Tx data receive interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXISIE LL_UCPD_IsEnableIT_TxIS
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1284 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT ( UCPD_TypeDef const *const UCPDx )

Check if Tx message abort interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1251 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC ( UCPD_TypeDef const *const UCPDx )

Check if Tx message discarded interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1273 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT ( UCPD_TypeDef const *const UCPDx )

Check if Tx message sent interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1262 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND ( UCPD_TypeDef const *const UCPDx )

Check if TX underrun interrupt enabled.

Reference Manual to LL API cross reference:
IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1218 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1 ( UCPD_TypeDef const *const UCPDx )

Check if type c event on CC1 enabled.

Reference Manual to LL API cross reference:
IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1152 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2 ( UCPD_TypeDef const *const UCPDx )

Check if type c event on CC2 enabled.

Reference Manual to LL API cross reference:
IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1141 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Interrupt Clear

Functions
Interrupt Clear
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_ClearFlag_FRS (UCPD_TypeDef *UCPDx)
Clear FRS interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Clear type c event on CC2.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Clear type c event on CC1.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxMsgEnd (UCPD_TypeDef *UCPDx)
Clear Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxOvr (UCPD_TypeDef *UCPDx)
Clear Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxHRST (UCPD_TypeDef *UCPDx)
Clear Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxOrderSet (UCPD_TypeDef *UCPDx)
Clear Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxUND (UCPD_TypeDef *UCPDx)
Clear TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Clear hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Clear hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGABT (UCPD_TypeDef *UCPDx)
Clear Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGSENT (UCPD_TypeDef *UCPDx)
Clear Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGDISC (UCPD_TypeDef *UCPDx)
Clear Tx message discarded interrupt.

Function Documentation

__STATIC_INLINE void LL_UCPD_ClearFlag_FRS ( UCPD_TypeDef * UCPDx )

Clear FRS interrupt.

Reference Manual to LL API cross reference:
ICR FRSEVTIE LL_UCPD_ClearFlag_FRS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1303 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST ( UCPD_TypeDef * UCPDx )

Clear Rx hard resrt interrupt.

Reference Manual to LL API cross reference:
ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1358 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd ( UCPD_TypeDef * UCPDx )

Clear Rx message end interrupt.

Reference Manual to LL API cross reference:
ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1336 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet ( UCPD_TypeDef * UCPDx )

Clear Rx orderset interrupt.

Reference Manual to LL API cross reference:
ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1369 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr ( UCPD_TypeDef * UCPDx )

Clear Rx overrun interrupt.

Reference Manual to LL API cross reference:
ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1347 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC ( UCPD_TypeDef * UCPDx )

Clear hard reset discard interrupt.

Reference Manual to LL API cross reference:
ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1402 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT ( UCPD_TypeDef * UCPDx )

Clear hard reset sent interrupt.

Reference Manual to LL API cross reference:
ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1391 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT ( UCPD_TypeDef * UCPDx )

Clear Tx message abort interrupt.

Reference Manual to LL API cross reference:
ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1413 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC ( UCPD_TypeDef * UCPDx )

Clear Tx message discarded interrupt.

Reference Manual to LL API cross reference:
ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1435 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT ( UCPD_TypeDef * UCPDx )

Clear Tx message sent interrupt.

Reference Manual to LL API cross reference:
ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1424 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND ( UCPD_TypeDef * UCPDx )

Clear TX underrun interrupt.

Reference Manual to LL API cross reference:
ICR TXUNDIE LL_UCPD_ClearFlag_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1380 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1 ( UCPD_TypeDef * UCPDx )

Clear type c event on CC1.

Reference Manual to LL API cross reference:
IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1325 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2 ( UCPD_TypeDef * UCPDx )

Clear type c event on CC2.

Reference Manual to LL API cross reference:
IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1314 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG Management

Functions
FLAG Management
UCPD Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_FRS (UCPD_TypeDef const *const UCPDx)
Check if FRS interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TypeCEventCC2 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC2.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TypeCEventCC1 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC1.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxMsgEnd (UCPD_TypeDef const *const UCPDx)
Check if Rx message end interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxOvr (UCPD_TypeDef const *const UCPDx)
Check if Rx overrun interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxHRST (UCPD_TypeDef const *const UCPDx)
Check if Rx hard resrt interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxOrderSet (UCPD_TypeDef const *const UCPDx)
Check if Rx orderset interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxNE (UCPD_TypeDef const *const UCPDx)
Check if Rx non empty interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxUND (UCPD_TypeDef const *const UCPDx)
Check if TX underrun interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxHRSTSENT (UCPD_TypeDef const *const UCPDx)
Check if hard reset sent interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxHRSTDISC (UCPD_TypeDef const *const UCPDx)
Check if hard reset discard interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGABT (UCPD_TypeDef const *const UCPDx)
Check if Tx message abort interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGSENT (UCPD_TypeDef const *const UCPDx)
Check if Tx message sent interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGDISC (UCPD_TypeDef const *const UCPDx)
Check if Tx message discarded interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxIS (UCPD_TypeDef const *const UCPDx)
Check if Tx data receive interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_GetTypeCVstateCC2 (UCPD_TypeDef const *const UCPDx)
return the vstate value for CC2
__STATIC_INLINE uint32_t | LL_UCPD_GetTypeCVstateCC1 (UCPD_TypeDef const *const UCPDx)
return the vstate value for CC1

Function Documentation

__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1 ( UCPD_TypeDef const *const UCPDx )

return the vstate value for CC1

Reference Manual to LL API cross reference:
SR TXIS LL_UCPD_GetTypeCVstateCC1
Parameters:
UCPDx UCPD Instance
Return values:
val

Definition at line 1630 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2 ( UCPD_TypeDef const *const UCPDx )

return the vstate value for CC2

Reference Manual to LL API cross reference:
SR TXIS LL_UCPD_GetTypeCVstateCC2
Parameters:
UCPDx UCPD Instance
Return values:
val

Definition at line 1619 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS ( UCPD_TypeDef const *const UCPDx )

Check if FRS interrupt.

Reference Manual to LL API cross reference:
SR FRSEVT LL_UCPD_IsActiveFlag_FRS
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1454 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST ( UCPD_TypeDef const *const UCPDx )

Check if Rx hard resrt interrupt.

Reference Manual to LL API cross reference:
SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1509 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd ( UCPD_TypeDef const *const UCPDx )

Check if Rx message end interrupt.

Reference Manual to LL API cross reference:
SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1487 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE ( UCPD_TypeDef const *const UCPDx )

Check if Rx non empty interrupt.

Reference Manual to LL API cross reference:
SR RXNE LL_UCPD_IsActiveFlag_RxNE
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1531 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet ( UCPD_TypeDef const *const UCPDx )

Check if Rx orderset interrupt.

Reference Manual to LL API cross reference:
SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1520 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr ( UCPD_TypeDef const *const UCPDx )

Check if Rx overrun interrupt.

Reference Manual to LL API cross reference:
SR RXOVR LL_UCPD_IsActiveFlag_RxOvr
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1498 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC ( UCPD_TypeDef const *const UCPDx )

Check if hard reset discard interrupt.

Reference Manual to LL API cross reference:
SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1564 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT ( UCPD_TypeDef const *const UCPDx )

Check if hard reset sent interrupt.

Reference Manual to LL API cross reference:
SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1553 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS ( UCPD_TypeDef const *const UCPDx )

Check if Tx data receive interrupt.

Reference Manual to LL API cross reference:
SR TXIS LL_UCPD_IsActiveFlag_TxIS
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1608 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT ( UCPD_TypeDef const *const UCPDx )

Check if Tx message abort interrupt.

Reference Manual to LL API cross reference:
SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1575 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC ( UCPD_TypeDef const *const UCPDx )

Check if Tx message discarded interrupt.

Reference Manual to LL API cross reference:
SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1597 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT ( UCPD_TypeDef const *const UCPDx )

Check if Tx message sent interrupt.

Reference Manual to LL API cross reference:
SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1586 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND ( UCPD_TypeDef const *const UCPDx )

Check if TX underrun interrupt.

Reference Manual to LL API cross reference:
SR TXUND LL_UCPD_IsActiveFlag_TxUND
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1542 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1 ( UCPD_TypeDef const *const UCPDx )

Check if type c event on CC1.

Reference Manual to LL API cross reference:
SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1476 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2 ( UCPD_TypeDef const *const UCPDx )

Check if type c event on CC2.

Reference Manual to LL API cross reference:
SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1465 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Management

Functions
DMA Management
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_RxDMAEnable (UCPD_TypeDef *UCPDx)
Rx DMA Enable.
__STATIC_INLINE void | LL_UCPD_RxDMADisable (UCPD_TypeDef *UCPDx)
Rx DMA Disable.
__STATIC_INLINE void | LL_UCPD_TxDMAEnable (UCPD_TypeDef *UCPDx)
Tx DMA Enable.
__STATIC_INLINE void | LL_UCPD_TxDMADisable (UCPD_TypeDef *UCPDx)
Tx DMA Disable.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabledTxDMA (UCPD_TypeDef const *const UCPDx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabledRxDMA (UCPD_TypeDef const *const UCPDx)
Check if DMA Rx is enabled.

Function Documentation

__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA ( UCPD_TypeDef const *const UCPDx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1705 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA ( UCPD_TypeDef const *const UCPDx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA
Parameters:
UCPDx UCPD Instance
Return values:
State of bit (1 or 0).

Definition at line 1694 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxDMADisable ( UCPD_TypeDef * UCPDx )

Rx DMA Disable.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_UCPD_RxDMADisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1661 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_RxDMAEnable ( UCPD_TypeDef * UCPDx )

Rx DMA Enable.

Reference Manual to LL API cross reference:
CFG1 RXDMAEN LL_UCPD_RxDMAEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1650 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TxDMADisable ( UCPD_TypeDef * UCPDx )

Tx DMA Disable.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_UCPD_TxDMADisable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1683 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_TxDMAEnable ( UCPD_TypeDef * UCPDx )

Tx DMA Enable.

Reference Manual to LL API cross reference:
CFG1 TXDMAEN LL_UCPD_TxDMAEnable
Parameters:
UCPDx UCPD Instance
Return values:
None

Definition at line 1672 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DATA Management

Functions
DATA Management
UCPD Exported Functions

Functions

__STATIC_INLINE void | LL_UCPD_WriteTxOrderSet (UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
write the orderset for Tx message
__STATIC_INLINE void | LL_UCPD_WriteTxPaySize (UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
write the Tx paysize
__STATIC_INLINE void | LL_UCPD_WriteData (UCPD_TypeDef *UCPDx, uint8_t Data)
Write data.
__STATIC_INLINE uint32_t | LL_UCPD_ReadRxOrderSet (UCPD_TypeDef const *const UCPDx)
read RX the orderset
__STATIC_INLINE uint32_t | LL_UCPD_ReadRxPaySize (UCPD_TypeDef const *const UCPDx)
Read the Rx paysize.
__STATIC_INLINE uint32_t | LL_UCPD_ReadData (UCPD_TypeDef const *const UCPDx)
Read data.
__STATIC_INLINE void | LL_UCPD_SetRxOrdExt1 (UCPD_TypeDef *UCPDx, uint32_t SOPExt)
Set Rx OrderSet Ext1.
__STATIC_INLINE void | LL_UCPD_SetRxOrdExt2 (UCPD_TypeDef *UCPDx, uint32_t SOPExt)
Set Rx OrderSet Ext2.

Function Documentation

__STATIC_INLINE uint32_t LL_UCPD_ReadData ( UCPD_TypeDef const *const UCPDx )

Read data.

Reference Manual to LL API cross reference:
RXDR RXDATA LL_UCPD_ReadData
Parameters:
UCPDx UCPD Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1797 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet ( UCPD_TypeDef const *const UCPDx )

read RX the orderset

Reference Manual to LL API cross reference:
RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet
Parameters:
UCPDx UCPD Instance
Return values:
RxOrderSet one of the following value
  • LL_UCPD_RXORDSET_SOP
  • LL_UCPD_RXORDSET_SOP1
  • LL_UCPD_RXORDSET_SOP2
  • LL_UCPD_RXORDSET_SOP1_DEBUG
  • LL_UCPD_RXORDSET_SOP2_DEBUG
  • LL_UCPD_RXORDSET_CABLE_RESET
  • LL_UCPD_RXORDSET_SOPEXT1
  • LL_UCPD_RXORDSET_SOPEXT2

Definition at line 1775 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize ( UCPD_TypeDef const *const UCPDx )

Read the Rx paysize.

Reference Manual to LL API cross reference:
RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize
Parameters:
UCPDx UCPD Instance
Return values:
RXPaysize.

Definition at line 1786 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRxOrdExt1 | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | SOPExt
 | ) |  |

Set Rx OrderSet Ext1.

Reference Manual to LL API cross reference:
RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1
Parameters:
UCPDx | UCPD Instance
SOPExt | Value between Min_Data=0x00000 and Max_Data=0xFFFFF
Return values:
None

Definition at line 1809 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_SetRxOrdExt2 | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | SOPExt
 | ) |  |

Set Rx OrderSet Ext2.

Reference Manual to LL API cross reference:
RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2
Parameters:
UCPDx | UCPD Instance
SOPExt | Value between Min_Data=0x00000 and Max_Data=0xFFFFF
Return values:
None

Definition at line 1821 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WriteData | ( | UCPD_TypeDef * | UCPDx,
 |  | uint8_t | Data
 | ) |  |

Write data.

Reference Manual to LL API cross reference:
TXDR DR LL_UCPD_WriteData
Parameters:
UCPDx | UCPD Instance
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None.

Definition at line 1756 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WriteTxOrderSet | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | TxOrderSet
 | ) |  |

write the orderset for Tx message

Reference Manual to LL API cross reference:
TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet
Parameters:
UCPDx UCPD Instance
TxOrderSet one of the following value
  • LL_UCPD_ORDERED_SET_SOP
  • LL_UCPD_ORDERED_SET_SOP1
  • LL_UCPD_ORDERED_SET_SOP2
  • LL_UCPD_ORDERED_SET_HARD_RESET
  • LL_UCPD_ORDERED_SET_CABLE_RESET
  • LL_UCPD_ORDERED_SET_SOP1_DEBUG
  • LL_UCPD_ORDERED_SET_SOP2_DEBUG
Return values:
None

Definition at line 1732 of file stm32g0xx_ll_ucpd.h.

__STATIC_INLINE void LL_UCPD_WriteTxPaySize | ( | UCPD_TypeDef * | UCPDx,
 |  | uint32_t | TxPaySize
 | ) |  |

write the Tx paysize

Reference Manual to LL API cross reference:
TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize
Parameters:
UCPDx UCPD Instance
TxPaySize
Return values:
None.

Definition at line 1744 of file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UCPD Exported Functions

Functions

ErrorStatus | LL_UCPD_DeInit (UCPD_TypeDef *UCPDx)
De-initialize the UCPD registers to their default reset values.
ErrorStatus | LL_UCPD_Init (UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
void | LL_UCPD_StructInit (LL_UCPD_InitTypeDef *UCPD_InitStruct)
Set each LL_UCPD_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_UCPD_DeInit ( UCPD_TypeDef * UCPDx )

De-initialize the UCPD registers to their default reset values.

Parameters:
UCPDx ucpd Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ucpd registers are de-initialized
  • ERROR: ucpd registers are not de-initialized

Definition at line 79 of file stm32g0xx_ll_ucpd.c.

References assert_param, LL_APB1_GRP1_DisableClock(), LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_UCPD1, LL_APB1_GRP1_PERIPH_UCPD2, LL_APB1_GRP1_ReleaseReset(), and LL_UCPD_Disable().

ErrorStatus LL_UCPD_Init | ( | UCPD_TypeDef * | UCPDx,
 |  | LL_UCPD_InitTypeDef * | UCPD_InitStruct
 | ) |  |

Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.

Note:
As some bits in ucpd configuration registers can only be written when the ucpd is disabled (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
UCPDx | UCPD Instance
UCPD_InitStruct | pointer to a LL_UCPD_InitTypeDef structure that contains the configuration information for the UCPD peripheral.
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 128 of file stm32g0xx_ll_ucpd.c.

References assert_param, LL_UCPD_InitTypeDef::HbitClockDiv, LL_UCPD_InitTypeDef::IfrGap, LL_APB1_GRP1_EnableClock(), LL_APB1_GRP1_PERIPH_UCPD1, LL_APB1_GRP1_PERIPH_UCPD2, LL_UCPD_Disable(), LL_UCPD_InitTypeDef::psc_ucpdclk, and LL_UCPD_InitTypeDef::transwin.

void LL_UCPD_StructInit ( LL_UCPD_InitTypeDef * UCPD_InitStruct )

Set each LL_UCPD_InitTypeDef field to default value.

Parameters:
UCPD_InitStruct pointer to a LL_UCPD_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 160 of file stm32g0xx_ll_ucpd.c.

References LL_UCPD_InitTypeDef::HbitClockDiv, LL_UCPD_InitTypeDef::IfrGap, LL_UCPD_PSC_DIV2, LL_UCPD_InitTypeDef::psc_ucpdclk, and LL_UCPD_InitTypeDef::transwin.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Private Variables

Variables
USART Private Variables
USART

Variables

static const uint32_t USART_PRESCALER_TAB []

Variable Documentation

const uint32_t USART_PRESCALER_TAB[] [static]
Initial value:
{
  1UL,
  2UL,
  4UL,
  6UL,
  8UL,
  10UL,
  12UL,
  16UL,
  32UL,
  64UL,
  128UL,
  256UL
}

Definition at line 46 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_LL_USART_PRESCALER(__VALUE__)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 8000000U)

Definition at line 63 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 16U)

Definition at line 66 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_CLOCKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_CLOCK_DISABLE) \
                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))

Definition at line 93 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PHASE_1EDGE) \
                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))

Definition at line 87 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_POLARITY_LOW) \
                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))

Definition at line 90 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DATAWIDTH_7B) \
                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))

Definition at line 77 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DIRECTION_NONE) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))

Definition at line 68 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_HWCONTROL_NONE) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))

Definition at line 101 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_LASTBITCLKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))

Definition at line 84 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_OVERSAMPLING ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_OVERSAMPLING_16) \
                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))

Definition at line 81 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PARITY_NONE) \
                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
                                       || ((__VALUE__) == LL_USART_PARITY_ODD))

Definition at line 73 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PRESCALER_DIV1) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV256))

Definition at line 48 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_STOPBITS_0_5) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
                                         || ((__VALUE__) == LL_USART_STOPBITS_2))

Definition at line 96 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_Init().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_InitTypeDef Struct Reference
USART Exported Init structures

LL USART Init Structure definition. More...

#include <stm32g0xx_ll_usart.h>

Data Fields

uint32_t | PrescalerValue
uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl
uint32_t | OverSampling

Detailed Description

LL USART Init Structure definition.

Definition at line 85 of file stm32g0xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_InitTypeDef::BaudRate

This field defines expected Usart communication baud rate.

This feature can be modified afterwards using unitary function LL_USART_SetBaudRate().

Definition at line 93 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_USART_SetDataWidth().

Definition at line 98 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_USART_SetHWFlowCtrl().

Definition at line 122 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::OverSampling

Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of Oversampling.

This feature can be modified afterwards using unitary function LL_USART_SetOverSampling().

Definition at line 128 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_USART_SetParity().

Definition at line 110 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::PrescalerValue

Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of Clock Source Prescaler.

This feature can be modified afterwards using unitary function LL_USART_SetPrescaler().

Definition at line 87 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_USART_SetStopBitsLength().

Definition at line 104 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Communication Direction.

This feature can be modified afterwards using unitary function LL_USART_SetTransferDirection().

Definition at line 116 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_usart.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_USART_ClockInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_ClockInitTypeDef Struct Reference
USART Exported Init structures

LL USART Clock Init Structure definition. More...

#include <stm32g0xx_ll_usart.h>

Data Fields

uint32_t | ClockOutput
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | LastBitClockPulse

Detailed Description

LL USART Clock Init Structure definition.

Definition at line 139 of file stm32g0xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_ClockInitTypeDef::ClockOutput

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of Clock Signal.

USART HW configuration can be modified afterwards using unitary functions LL_USART_EnableSCLKOutput() or LL_USART_DisableSCLKOutput(). For more details, refer to description of this function.

Definition at line 141 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of Clock Phase.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPhase(). For more details, refer to description of this function.

Definition at line 155 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPolarity

Specifies the steady state of the serial clock. This parameter can be a value of Clock Polarity.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPolarity(). For more details, refer to description of this function.

Definition at line 148 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::LastBitClockPulse

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of Last Clock Pulse.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function.

Definition at line 162 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_usart.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_WriteReg function. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NECF USART_ICR_NECF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_UDRCF USART_ICR_UDRCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_USART_WriteReg function.

Define Documentation

#define LL_USART_ICR_CMCF USART_ICR_CMCF

Character match clear flag

Definition at line 199 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_CTSCF USART_ICR_CTSCF

CTS clear flag

Definition at line 195 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_EOBCF USART_ICR_EOBCF

End of block clear flag

Definition at line 197 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_FECF USART_ICR_FECF

Framing error clear flag

Definition at line 187 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected clear flag

Definition at line 190 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_LBDCF USART_ICR_LBDCF

LIN break detection clear flag

Definition at line 194 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_NECF USART_ICR_NECF

Noise error detected clear flag

Definition at line 188 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_ORECF USART_ICR_ORECF

Overrun error clear flag

Definition at line 189 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_PECF USART_ICR_PECF

Parity error clear flag

Definition at line 186 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_RTOCF USART_ICR_RTOCF

Receiver timeout clear flag

Definition at line 196 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF

Transmission completed before guard time clear flag

Definition at line 193 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_TCCF USART_ICR_TCCF

Transmission complete clear flag

Definition at line 192 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_TXFECF USART_ICR_TXFECF

TX FIFO Empty clear flag

Definition at line 191 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_UDRCF USART_ICR_UDRCF

SPI Slave Underrun clear flag

Definition at line 198 of file stm32g0xx_ll_usart.h.

#define LL_USART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode clear flag

Definition at line 200 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_ReadReg function. More...

Defines

#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_UDR USART_ISR_UDR
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_ISR_TXFE USART_ISR_TXFE
#define | LL_USART_ISR_RXFF USART_ISR_RXFF
#define | LL_USART_ISR_TCBGT USART_ISR_TCBGT
#define | LL_USART_ISR_RXFT USART_ISR_RXFT
#define | LL_USART_ISR_TXFT USART_ISR_TXFT

Detailed Description

Flags defines which can be used with LL_USART_ReadReg function.

Define Documentation

#define LL_USART_ISR_ABRE USART_ISR_ABRE

Auto baud rate error flag

Definition at line 223 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_ABRF USART_ISR_ABRF

Auto baud rate flag

Definition at line 224 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 225 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 226 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 219 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 218 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_EOBF USART_ISR_EOBF

End of block flag

Definition at line 221 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 210 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 213 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_LBDF USART_ISR_LBDF

LIN break detection flag

Definition at line 217 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 211 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 212 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 209 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 231 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_RTOF USART_ISR_RTOF

Receiver timeout flag

Definition at line 220 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 228 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

Definition at line 233 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

Definition at line 235 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

Definition at line 214 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 227 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 215 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_TCBGT USART_ISR_TCBGT

Transmission complete before guard time completion flag

Definition at line 234 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 230 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO Not Full flag

Definition at line 216 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

Definition at line 232 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

Definition at line 236 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_UDR USART_ISR_UDR

SPI Slave underrun error flag

Definition at line 222 of file stm32g0xx_ll_usart.h.

#define LL_USART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 229 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
USART Exported Constants

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions. More...

Defines

#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
#define | LL_USART_CR3_RXFTIE USART_CR3_RXFTIE

Detailed Description

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Define Documentation

#define LL_USART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 250 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_EOBIE USART_CR1_EOBIE

End of Block interrupt enable

Definition at line 252 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 245 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 249 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_RTOIE USART_CR1_RTOIE

Receiver timeout interrupt enable

Definition at line 251 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

Definition at line 254 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

Definition at line 246 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 247 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

Definition at line 248 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

Definition at line 253 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR2_LBDIE USART_CR2_LBDIE

LIN break detection interrupt enable

Definition at line 255 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 257 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 256 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

Definition at line 261 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE

Transmission complete before guard time interrupt enable

Definition at line 260 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

Definition at line 259 of file stm32g0xx_ll_usart.h.

#define LL_USART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 258 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
USART Exported Constants

Defines

#define | LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_USART_FIFOTHRESHOLD_8_8 0x00000005U

Define Documentation

#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

Definition at line 271 of file stm32g0xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

Definition at line 270 of file stm32g0xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

Definition at line 269 of file stm32g0xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

Definition at line 272 of file stm32g0xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

Definition at line 273 of file stm32g0xx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Definition at line 274 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Communication Direction

Defines
Communication Direction
USART Exported Constants

Defines

#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_USART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 282 of file stm32g0xx_ll_usart.h.

#define LL_USART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 283 of file stm32g0xx_ll_usart.h.

#define LL_USART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 284 of file stm32g0xx_ll_usart.h.

#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 285 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_StructInit().

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STM32G0C1xx HAL User Manual: Parity Control

Defines
Parity Control
USART Exported Constants

Defines

#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_USART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 294 of file stm32g0xx_ll_usart.h.

#define LL_USART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 293 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 295 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Wakeup

Defines
Wakeup
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

USART wake up from Mute mode on Address Mark

Definition at line 304 of file stm32g0xx_ll_usart.h.

#define LL_USART_WAKEUP_IDLELINE 0x00000000U

USART wake up from Mute mode on Idle Line

Definition at line 303 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Datawidth

Defines
Datawidth
USART Exported Constants

Defines

#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_USART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 312 of file stm32g0xx_ll_usart.h.

#define LL_USART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 313 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 314 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Oversampling

Defines
Oversampling
USART Exported Constants

Defines

#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define LL_USART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 322 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 323 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_GetBaudRate(), and LL_USART_SetBaudRate().

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STM32G0C1xx HAL User Manual: Clock Signal

Defines
Clock Signal
USART Exported Constants

Defines

#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define LL_USART_CLOCK_DISABLE 0x00000000U

Clock signal not provided

Definition at line 333 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Clock signal provided

Definition at line 334 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Last Clock Pulse

Defines
Last Clock Pulse
USART Exported Constants

Defines

#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

Define Documentation

#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U

The clock pulse of the last data bit is not output to the SCLK pin

Definition at line 343 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

The clock pulse of the last data bit is output to the SCLK pin

Definition at line 344 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Clock Phase

Defines
Clock Phase
USART Exported Constants

Defines

#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define LL_USART_PHASE_1EDGE 0x00000000U

The first clock transition is the first data capture edge

Definition at line 352 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_PHASE_2EDGE USART_CR2_CPHA

The second clock transition is the first data capture edge

Definition at line 353 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
USART Exported Constants

Defines

#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define LL_USART_POLARITY_HIGH USART_CR2_CPOL

Steady high value on SCLK pin outside transmission window

Definition at line 362 of file stm32g0xx_ll_usart.h.

#define LL_USART_POLARITY_LOW 0x00000000U

Steady low value on SCLK pin outside transmission window

Definition at line 361 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

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STM32G0C1xx HAL User Manual: Clock Source Prescaler

Defines
Clock Source Prescaler
USART Exported Constants

Defines

#define | LL_USART_PRESCALER_DIV1 0x00000000U
#define | LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Define Documentation

#define LL_USART_PRESCALER_DIV1 0x00000000U

Input clock not divided

Definition at line 370 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)

Input clock divided by 10

Definition at line 375 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)

Input clock divided by 12

Definition at line 376 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)

Input clock divided by 128

Definition at line 380 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock divided by 16

Definition at line 377 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock divided by 2

Definition at line 371 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock divided by 256

Definition at line 381 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock divided by 32

Definition at line 378 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock divided by 4

Definition at line 372 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock divided by 6

Definition at line 373 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)

Input clock divided by 64

Definition at line 379 of file stm32g0xx_ll_usart.h.

#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock divided by 8

Definition at line 374 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Stop Bits

Defines
Stop Bits
USART Exported Constants

Defines

#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0

0.5 stop bit

Definition at line 389 of file stm32g0xx_ll_usart.h.

#define LL_USART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 390 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

1.5 stop bits

Definition at line 391 of file stm32g0xx_ll_usart.h.

#define LL_USART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 392 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
USART Exported Constants

Defines

#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_USART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 400 of file stm32g0xx_ll_usart.h.

#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 401 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 410 of file stm32g0xx_ll_usart.h.

#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 409 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 419 of file stm32g0xx_ll_usart.h.

#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 418 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
USART Exported Constants

Defines

#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 428 of file stm32g0xx_ll_usart.h.

#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 427 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Bit Order

Defines
Bit Order
USART Exported Constants

Defines

#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_USART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 436 of file stm32g0xx_ll_usart.h.

#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 437 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Autobaud Detection

Defines
Autobaud Detection
USART Exported Constants

Defines

#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

Define Documentation

#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

0x55 frame detection

Definition at line 448 of file stm32g0xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1

0x7F frame detection

Definition at line 447 of file stm32g0xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0

Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

Definition at line 446 of file stm32g0xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U

Measurement of the start bit is used to detect the baud rate

Definition at line 445 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Address Length Detection

Defines
Address Length Detection
USART Exported Constants

Defines

#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_USART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 456 of file stm32g0xx_ll_usart.h.

#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 457 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Hardware Control

Defines
Hardware Control
USART Exported Constants

Defines

#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 467 of file stm32g0xx_ll_usart.h.

#define LL_USART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 465 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 466 of file stm32g0xx_ll_usart.h.

#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 468 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 476 of file stm32g0xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 478 of file stm32g0xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 477 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: IrDA Power

Defines
IrDA Power
USART Exported Constants

Defines

#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

Define Documentation

#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

IrDA low power mode

Definition at line 487 of file stm32g0xx_ll_usart.h.

#define LL_USART_IRDA_POWER_NORMAL 0x00000000U

IrDA normal power mode

Definition at line 486 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: LIN Break Detection Length

Defines
LIN Break Detection Length
USART Exported Constants

Defines

#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

Define Documentation

#define LL_USART_LINBREAK_DETECT_10B 0x00000000U

10-bit break detection method selected

Definition at line 495 of file stm32g0xx_ll_usart.h.

#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

11-bit break detection method selected

Definition at line 496 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
USART Exported Constants

Defines

#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_USART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 504 of file stm32g0xx_ll_usart.h.

#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 505 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
USART Exported Constants

Defines

#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 514 of file stm32g0xx_ll_usart.h.

#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 513 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_DMA_GetRegAddr().

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STM32G0C1xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
USART Exported Macros

Defines

#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.

Define Documentation

#define LL_USART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 547 of file stm32g0xx_ll_usart.h.

#define LL_USART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 539 of file stm32g0xx_ll_usart.h.

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STM32G0C1xx HAL User Manual: Exported_Macros_Helper

Defines
Exported_Macros_Helper
USART Exported Macros

Defines

#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Define Documentation

#define __LL_USART_DIV_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_16 case

Definition at line 600 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define __LL_USART_DIV_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
(((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_8 case

Definition at line 576 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

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STM32G0C1xx HAL User Manual: Configuration functions

Functions
Configuration functions
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (const USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableFIFO (USART_TypeDef *USARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_USART_DisableFIFO (USART_TypeDef *USARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledFIFO (const USART_TypeDef *USARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_USART_SetTXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetTXFIFOThreshold (const USART_TypeDef *USARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_SetRXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetRXFIFOThreshold (const USART_TypeDef *USARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_ConfigFIFOsThreshold (USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (const USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (const USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (const USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (const USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (const USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (const USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (const USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (const USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (const USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (const USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_SetPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_USART_GetPrescaler (const USART_TypeDef *USARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (const USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (const USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (const USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (const USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (const USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (const USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (const USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (const USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (const USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (const USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (const USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (const USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (const USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (const USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (const USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (const USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (const USART_TypeDef *USARTx)
Get Block Length value in reception.

Function Documentation

__STATIC_INLINE void LL_USART_ConfigCharacter | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_USART_SetDataWidth() function
  • Parity Control and mode configuration using LL_USART_SetParity() function
  • Stop bits configuration using LL_USART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_USART_ConfigCharacter
CR1 PCE LL_USART_ConfigCharacter
CR1 M0 LL_USART_ConfigCharacter
CR1 M1 LL_USART_ConfigCharacter
CR2 STOP LL_USART_ConfigCharacter
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1346 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigClock | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Phase,
 |  | uint32_t | Polarity,
 |  | uint32_t | LBCPOutput
 | ) |  |

Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clock Phase configuration using LL_USART_SetClockPhase() function
  • Clock Polarity configuration using LL_USART_SetClockPolarity() function
  • Output of Last bit Clock pulse configuration using LL_USART_SetLastClkPulseOutput() function
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_ConfigClock
CR2 CPOL LL_USART_ConfigClock
CR2 LBCL LL_USART_ConfigClock
Parameters:
USARTx USART Instance
Phase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Polarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
LBCPOutput This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 1193 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TXThreshold,
 |  | uint32_t | RXThreshold
 | ) |  |

Configure TX and RX FIFOs Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold
CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
Parameters:
USARTx USART Instance
TXThreshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
RXThreshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 798 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigNodeAddress | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the USART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_ConfigNodeAddress
CR2 ADDM7 LL_USART_ConfigNodeAddress
Parameters:
USARTx | USART Instance
AddressLen This parameter can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the USART node.
Return values:
None

Definition at line 1624 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_Disable ( USART_TypeDef * USARTx )

USART Disable (all USART prescalers and outputs are disabled)

Note:
When USART is disabled, USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USARTx_ISR are set to their default values.
Reference Manual to LL API cross reference:
CR1 UE LL_USART_Disable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 642 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableAutoBaudRate ( USART_TypeDef * USARTx )

Disable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_DisableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1515 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1705 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionRx ( USART_TypeDef * USARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_DisableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 863 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_DisableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 885 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableFIFO ( USART_TypeDef * USARTx )

FIFO Mode Disable.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_DisableFIFO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 679 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableInStopMode ( USART_TypeDef * USARTx )

USART disabled in STOP Mode.

Note:
When this function is disabled, USART is not able to wake up the MCU from Stop mode
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_DisableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 828 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableMuteMode ( USART_TypeDef * USARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_DisableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1033 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOneBitSamp ( USART_TypeDef * USARTx )

Disable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_DisableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1764 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOverrunDetect ( USART_TypeDef * USARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_DisableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1797 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1679 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRxTimeout ( USART_TypeDef * USARTx )

Disable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_DisableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1585 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSCLKOutput ( USART_TypeDef * USARTx )

Disable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_DisableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1270 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_Enable ( USART_TypeDef * USARTx )

USART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_Enable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 628 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableAutoBaudRate ( USART_TypeDef * USARTx )

Enable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_EnableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1502 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1692 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionRx ( USART_TypeDef * USARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_USART_EnableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 852 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_EnableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 874 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableFIFO ( USART_TypeDef * USARTx )

FIFO Mode Enable.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_EnableFIFO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 666 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableInStopMode ( USART_TypeDef * USARTx )

USART enabled in STOP Mode.

Note:
When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that USART clock selection is HSI or LSE in RCC.
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_EnableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 814 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableMuteMode ( USART_TypeDef * USARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_EnableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1022 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOneBitSamp ( USART_TypeDef * USARTx )

Enable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_EnableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1753 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOverrunDetect ( USART_TypeDef * USARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_EnableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1786 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1666 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRxTimeout ( USART_TypeDef * USARTx )

Enable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_EnableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1574 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSCLKOutput ( USART_TypeDef * USARTx )

Enable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_EnableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1257 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode ( USART_TypeDef * USARTx )

Return Auto Baud-Rate mode.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_GetAutoBaudRateMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME

Definition at line 1563 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBaudRate | ( | const USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | OverSampling
 | ) |  |

Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_GetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
Baud Rate

Definition at line 1929 of file stm32g0xx_ll_usart.h.

References LL_USART_OVERSAMPLING_8.

__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic ( const USART_TypeDef * USARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_GetBinaryDataLogic
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE

Definition at line 1458 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBlockLength ( const USART_TypeDef * USARTx )

Get Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_GetBlockLength
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2001 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPhase ( const USART_TypeDef * USARTx )

Return phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_GetClockPhase
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE

Definition at line 1134 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPolarity ( const USART_TypeDef * USARTx )

Return polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_GetClockPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH

Definition at line 1165 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDataWidth ( const USART_TypeDef * USARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_GetDataWidth
CR1 M1 LL_USART_GetDataWidth
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B

Definition at line 1011 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl ( const USART_TypeDef * USARTx )

Return HW Flow Control configuration (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_GetHWFlowCtrl
CR3 CTSE LL_USART_GetHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS

Definition at line 1742 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput ( const USART_TypeDef * USARTx )

Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_GetLastClkPulseOutput
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT

Definition at line 1103 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddress ( const USART_TypeDef * USARTx )

Return 8 bit Address of the USART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_GetNodeAddress
Parameters:
USARTx USART Instance
Return values:
Address of the USART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1640 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen ( const USART_TypeDef * USARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_USART_GetNodeAddressLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B

Definition at line 1653 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetOverSampling ( const USART_TypeDef * USARTx )

Return Oversampling mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_GetOverSampling
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8

Definition at line 1071 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetParity ( const USART_TypeDef * USARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_USART_GetParity
CR1 PCE LL_USART_GetParity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD

Definition at line 953 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetPrescaler ( const USART_TypeDef * USARTx )

Retrieve the Clock source prescaler for baudrate generator and oversampling.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
PRESC PRESCALER LL_USART_GetPrescaler
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256

Definition at line 1244 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold ( const USART_TypeDef * USARTx )

Return RX FIFO Threshold Configuration.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8

Definition at line 770 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel ( const USART_TypeDef * USARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_GetRXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED

Definition at line 1402 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRxTimeout ( const USART_TypeDef * USARTx )

Get Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_GetRxTimeout
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x00FFFFFF

Definition at line 1978 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength ( const USART_TypeDef * USARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_GetStopBitsLength
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2

Definition at line 1314 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder ( const USART_TypeDef * USARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_GetTransferBitOrder
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST

Definition at line 1489 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferDirection ( const USART_TypeDef * USARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_GetTransferDirection
CR1 TE LL_USART_GetTransferDirection
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX

Definition at line 919 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold ( const USART_TypeDef * USARTx )

Return TX FIFO Threshold Configuration.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8

Definition at line 731 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel ( const USART_TypeDef * USARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_GetTXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED

Definition at line 1429 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap ( const USART_TypeDef * USARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_GetTXRXSwap
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED

Definition at line 1375 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod ( const USART_TypeDef * USARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_GetWakeUpMethod
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK

Definition at line 980 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWKUPType ( const USART_TypeDef * USARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_GetWKUPType
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE

Definition at line 1841 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabled ( const USART_TypeDef * USARTx )

Indicate if USART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_IsEnabled
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 653 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_Init().

__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud ( const USART_TypeDef * USARTx )

Indicate if Auto Baud-Rate Detection mechanism is enabled.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_IsEnabledAutoBaud
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1528 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO ( const USART_TypeDef * USARTx )

Indicate if FIFO Mode is enabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_IsEnabledFIFO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 692 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode ( const USART_TypeDef * USARTx )

Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_IsEnabledInStopMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 841 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode ( const USART_TypeDef * USARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_IsEnabledMuteMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1044 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp ( const USART_TypeDef * USARTx )

Indicate if One bit sampling method is enabled.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1775 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect ( const USART_TypeDef * USARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1808 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout ( const USART_TypeDef * USARTx )

Indicate if Receiver Timeout feature is enabled.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_IsEnabledRxTimeout
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1596 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput ( const USART_TypeDef * USARTx )

Indicate if Clock output on SCLK pin is enabled.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_IsEnabledSCLKOutput
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1283 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetAutoBaudRateMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoBaudRateMode
 | ) |  |

Set Auto Baud-Rate mode bits.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_SetAutoBaudRateMode
Parameters:
USARTx USART Instance
AutoBaudRateMode This parameter can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
Return values:
None

Definition at line 1546 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | OverSampling,
 |  | uint32_t | BaudRate
 | ) |  |

Configure USART BRR register for achieving expected Baud Rate value.

Note:
Compute and set USARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
Peripheral clock and Baud rate values provided as function parameters should be valid (Baud rate value != 0)
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_SetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
BaudRate | Baud Rate
Return values:
None

Definition at line 1875 of file stm32g0xx_ll_usart.h.

References __LL_USART_DIV_SAMPLING16, __LL_USART_DIV_SAMPLING8, LL_USART_OVERSAMPLING_8, and LL_USART_PRESCALER_DIV256.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetBinaryDataLogic | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_SetBinaryDataLogic
Parameters:
USARTx USART Instance
DataLogic This parameter can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1445 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBlockLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BlockLength
 | ) |  |

Set Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_SetBlockLength
Parameters:
USARTx | USART Instance
BlockLength | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1990 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPhase | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPhase
 | ) |  |

Select the phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_SetClockPhase
Parameters:
USARTx USART Instance
ClockPhase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Return values:
None

Definition at line 1119 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Select the polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_SetClockPolarity
Parameters:
USARTx USART Instance
ClockPolarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
Return values:
None

Definition at line 1150 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDataWidth | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_SetDataWidth
CR1 M1 LL_USART_SetDataWidth
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Return values:
None

Definition at line 996 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetHWFlowCtrl | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_SetHWFlowCtrl
CR3 CTSE LL_USART_SetHWFlowCtrl
Parameters:
USARTx USART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1724 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetLastClkPulseOutput | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LastBitClockPulse
 | ) |  |

Configure if Clock pulse of the last data bit is output to the SCLK pin or not.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_SetLastClkPulseOutput
Parameters:
USARTx USART Instance
LastBitClockPulse This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 1087 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetOverSampling | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | OverSampling
 | ) |  |

Set Oversampling to 8-bit or 16-bit mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_SetOverSampling
Parameters:
USARTx USART Instance
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
None

Definition at line 1058 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetParity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled).

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (9th or 8th bit depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_USART_SetParity
CR1 PCE LL_USART_SetParity
Parameters:
USARTx USART Instance
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
Return values:
None

Definition at line 938 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Configure Clock source prescaler for baudrate generator and oversampling.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
PRESC PRESCALER LL_USART_SetPrescaler
Parameters:
USARTx USART Instance
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
Return values:
None

Definition at line 1219 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetRXFIFOThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure RX FIFO Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
Parameters:
USARTx USART Instance
Threshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 751 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_SetRXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1389 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRxTimeout | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Timeout
 | ) |  |

Set Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_SetRxTimeout
Parameters:
USARTx | USART Instance
Timeout | Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
Return values:
None

Definition at line 1967 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetStopBitsLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_SetStopBitsLength
Parameters:
USARTx USART Instance
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1299 of file stm32g0xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetTransferBitOrder | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_SetTransferBitOrder
Parameters:
USARTx USART Instance
BitOrder This parameter can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1474 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTransferDirection | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_SetTransferDirection
CR1 TE LL_USART_SetTransferDirection
Parameters:
USARTx USART Instance
TransferDirection This parameter can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX
Return values:
None

Definition at line 903 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXFIFOThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure TX FIFO Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
Parameters:
USARTx USART Instance
Threshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 712 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_SetTXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1416 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXRXSwap | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_SetTXRXSwap
Parameters:
USARTx USART Instance
SwapConfig This parameter can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED
Return values:
None

Definition at line 1362 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWakeUpMethod | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_SetWakeUpMethod
Parameters:
USARTx USART Instance
Method This parameter can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 967 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWKUPType | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_SetWKUPType
Parameters:
USARTx USART Instance
Type This parameter can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1825 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions related to Irda feature

Functions
Configuration functions related to Irda feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (const USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (const USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (const USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableIrda ( USART_TypeDef * USARTx )

Disable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_DisableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2035 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIrda ( USART_TypeDef * USARTx )

Enable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_EnableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2022 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode ( const USART_TypeDef * USARTx )

Retrieve IrDA Power Mode configuration (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_GetIrdaPowerMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_PHASE_2EDGE

Definition at line 2079 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler ( const USART_TypeDef * USARTx )

Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetIrdaPrescaler
Parameters:
USARTx USART Instance
Return values:
Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 2108 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda ( const USART_TypeDef * USARTx )

Indicate if IrDA mode is enabled.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_IsEnabledIrda
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2048 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPowerMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PowerMode
 | ) |  |

Configure IrDA Power Mode (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_SetIrdaPowerMode
Parameters:
USARTx USART Instance
PowerMode This parameter can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_IRDA_POWER_LOW
Return values:
None

Definition at line 2064 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetIrdaPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2094 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions related to Smartcard feature

Functions
Configuration functions related to Smartcard feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (const USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (const USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (const USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (const USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (const USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableSmartcard ( USART_TypeDef * USARTx )

Disable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_DisableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2181 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSmartcardNACK ( USART_TypeDef * USARTx )

Disable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_DisableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2142 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcard ( USART_TypeDef * USARTx )

Enable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_EnableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2168 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcardNACK ( USART_TypeDef * USARTx )

Enable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_EnableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2129 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount ( const USART_TypeDef * USARTx )

Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
Parameters:
USARTx USART Instance
Return values:
Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)

Definition at line 2226 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime ( const USART_TypeDef * USARTx )

Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_GetSmartcardGuardTime
Parameters:
USARTx USART Instance
Return values:
Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 2284 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler ( const USART_TypeDef * USARTx )

Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetSmartcardPrescaler
Parameters:
USARTx USART Instance
Return values:
Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)

Definition at line 2255 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard ( const USART_TypeDef * USARTx )

Indicate if Smartcard mode is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_IsEnabledSmartcard
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2194 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK ( const USART_TypeDef * USARTx )

Indicate if Smartcard NACK transmission is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_IsEnabledSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2155 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoRetryCount
 | ) |  |

Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE and PE bits set)
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
Parameters:
USARTx | USART Instance
AutoRetryCount | Value between Min_Data=0 and Max_Data=7
Return values:
None

Definition at line 2213 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | GuardTime
 | ) |  |

Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_SetSmartcardGuardTime
Parameters:
USARTx | USART Instance
GuardTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2270 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetSmartcardPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2241 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (const USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableHalfDuplex ( USART_TypeDef * USARTx )

Disable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_DisableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2318 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableHalfDuplex ( USART_TypeDef * USARTx )

Enable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_EnableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2305 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex ( const USART_TypeDef * USARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_IsEnabledHalfDuplex
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2331 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions related to SPI Slave feature

Functions
Configuration functions related to SPI Slave feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSPISlave (USART_TypeDef *USARTx)
Enable SPI Synchronous Slave mode.
__STATIC_INLINE void | LL_USART_DisableSPISlave (USART_TypeDef *USARTx)
Disable SPI Synchronous Slave mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlave (const USART_TypeDef *USARTx)
Indicate if SPI Synchronous Slave mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlaveSelect (USART_TypeDef *USARTx)
Enable SPI Slave Selection using NSS input pin.
__STATIC_INLINE void | LL_USART_DisableSPISlaveSelect (USART_TypeDef *USARTx)
Disable SPI Slave Selection using NSS input pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlaveSelect (const USART_TypeDef *USARTx)
Indicate if SPI Slave Selection depends on NSS input pin.

Function Documentation

__STATIC_INLINE void LL_USART_DisableSPISlave ( USART_TypeDef * USARTx )

Disable SPI Synchronous Slave mode.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_DisableSPISlave
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2364 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSPISlaveSelect ( USART_TypeDef * USARTx )

Disable SPI Slave Selection using NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
SPI Slave will be always selected and NSS input pin will be ignored.
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2406 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSPISlave ( USART_TypeDef * USARTx )

Enable SPI Synchronous Slave mode.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_EnableSPISlave
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2351 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSPISlaveSelect ( USART_TypeDef * USARTx )

Enable SPI Slave Selection using NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
SPI Slave Selection depends on NSS input pin (The slave is selected when NSS is low and deselected when NSS is high).
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2392 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave ( const USART_TypeDef * USARTx )

Indicate if SPI Synchronous Slave mode is enabled.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_IsEnabledSPISlave
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2377 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect ( const USART_TypeDef * USARTx )

Indicate if SPI Slave Selection depends on NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2419 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions related to LIN feature

Functions
Configuration functions related to LIN feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (const USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (const USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableLIN ( USART_TypeDef * USARTx )

Disable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_DisableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2484 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableLIN ( USART_TypeDef * USARTx )

Enable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_EnableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2471 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen ( const USART_TypeDef * USARTx )

Return LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_GetLINBrkDetectionLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B

Definition at line 2458 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN ( const USART_TypeDef * USARTx )

Indicate if LIN mode is enabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_IsEnabledLIN
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2497 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LINBDLength
 | ) |  |

Set LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_SetLINBrkDetectionLen
Parameters:
USARTx USART Instance
LINBDLength This parameter can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B
Return values:
None

Definition at line 2443 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (const USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (const USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (const USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (const USART_TypeDef *USARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDEMode ( USART_TypeDef * USARTx )

Disable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_DisableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2585 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDEMode ( USART_TypeDef * USARTx )

Enable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_EnableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2572 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime ( const USART_TypeDef * USARTx )

Return DEAT (Driver Enable Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_GetDEAssertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2559 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime ( const USART_TypeDef * USARTx )

Return DEDT (Driver Enable De-Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_GetDEDeassertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2532 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity ( const USART_TypeDef * USARTx )

Return Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_GetDESignalPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW

Definition at line 2629 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode ( const USART_TypeDef * USARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_IsEnabledDEMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2598 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEAssertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_SetDEAssertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2546 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEDeassertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_SetDEDeassertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2519 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDESignalPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_SetDESignalPolarity
Parameters:
USARTx USART Instance
Polarity This parameter can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW
Return values:
None

Definition at line 2614 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Advanced Configurations services

Functions
Advanced Configurations services
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Function Documentation

__STATIC_INLINE void LL_USART_ConfigAsyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)

Note:
In UART mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Asynchronous Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigAsyncMode
CR2 CLKEN LL_USART_ConfigAsyncMode
CR3 SCEN LL_USART_ConfigAsyncMode
CR3 IREN LL_USART_ConfigAsyncMode
CR3 HDSEL LL_USART_ConfigAsyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2667 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Half Duplex Mode.

Note:
In Half Duplex mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register, This function also sets the UART/USART in Half Duplex mode.
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Set HDSEL in CR3 using LL_USART_EnableHalfDuplex() function
Other remaining configurations items related to Half Duplex Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigHalfDuplexMode
CR2 CLKEN LL_USART_ConfigHalfDuplexMode
CR3 HDSEL LL_USART_ConfigHalfDuplexMode
CR3 SCEN LL_USART_ConfigHalfDuplexMode
CR3 IREN LL_USART_ConfigHalfDuplexMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2784 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigIrdaMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Irda Mode.

Note:
In IRDA mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the UART/USART in IRDA mode (IREN bit).
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set IREN in CR3 using LL_USART_EnableIrda() function
Other remaining configurations items related to Irda Mode (as Baud Rate, Word length, Power mode, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigIrdaMode
CR2 CLKEN LL_USART_ConfigIrdaMode
CR2 STOP LL_USART_ConfigIrdaMode
CR3 SCEN LL_USART_ConfigIrdaMode
CR3 HDSEL LL_USART_ConfigIrdaMode
CR3 IREN LL_USART_ConfigIrdaMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2869 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigLINMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in LIN Mode.

Note:
In LIN mode, the following bits must be kept cleared:
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also set the UART/USART in LIN mode.
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set LINEN in CR2 using LL_USART_EnableLIN() function
Other remaining configurations items related to LIN Mode (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_ConfigLINMode
CR2 STOP LL_USART_ConfigLINMode
CR2 LINEN LL_USART_ConfigLINMode
CR3 IREN LL_USART_ConfigLINMode
CR3 SCEN LL_USART_ConfigLINMode
CR3 HDSEL LL_USART_ConfigLINMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2745 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigMultiProcessMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Note:
In MultiProcessor mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Multi processor Mode (as Baud Rate, Wake Up Method, Node address, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigMultiProcessMode
CR2 CLKEN LL_USART_ConfigMultiProcessMode
CR3 SCEN LL_USART_ConfigMultiProcessMode
CR3 HDSEL LL_USART_ConfigMultiProcessMode
CR3 IREN LL_USART_ConfigMultiProcessMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2908 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSmartcardMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Smartcard Mode.

Note:
In Smartcard mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also configures Stop bits to 1.5 bits and sets the USART in Smartcard mode (SCEN bit). Clock Output is also enabled (CLKEN).
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
  • Set SCEN in CR3 using LL_USART_EnableSmartcard() function
Other remaining configurations items related to Smartcard Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSmartcardMode
CR2 STOP LL_USART_ConfigSmartcardMode
CR2 CLKEN LL_USART_ConfigSmartcardMode
CR3 HDSEL LL_USART_ConfigSmartcardMode
CR3 SCEN LL_USART_ConfigSmartcardMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2825 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Synchronous Mode.

Note:
In Synchronous mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the USART in Synchronous mode.
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
Other remaining configurations items related to Synchronous Mode (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSyncMode
CR2 CLKEN LL_USART_ConfigSyncMode
CR3 SCEN LL_USART_ConfigSyncMode
CR3 IREN LL_USART_ConfigSyncMode
CR3 HDSEL LL_USART_ConfigSyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2704 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: FLAG_Management

Defines | Functions
FLAG_Management
USART Exported Functions

Defines

#define | LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
#define | LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF

Functions

__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (const USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (const USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (const USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (const USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (const USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE_RXFNE (const USART_TypeDef *USARTx)
Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (const USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE_TXFNF (const USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (const USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (const USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (const USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (const USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (const USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_UDR (const USART_TypeDef *USARTx)
Check if the SPI Slave Underrun error flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (const USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (const USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (const USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (const USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (const USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (const USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (const USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (const USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (const USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFE (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFF (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TCBGT (const USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFT (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFT (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise Error detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TXFE (USART_TypeDef *USARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TCBGT (USART_TypeDef *USARTx)
Clear Smartcard Transmission Complete Before Guard Time Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_UDR (USART_TypeDef *USARTx)
Clear SPI Slave Underrun Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.

Define Documentation

#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE

Definition at line 2982 of file stm32g0xx_ll_usart.h.

#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF

Definition at line 3009 of file stm32g0xx_ll_usart.h.

Function Documentation

__STATIC_INLINE void LL_USART_ClearFlag_CM ( USART_TypeDef * USARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_USART_ClearFlag_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3427 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_EOB ( USART_TypeDef * USARTx )

Clear End Of Block Flag.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR EOBCF LL_USART_ClearFlag_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3403 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_FE ( USART_TypeDef * USARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_USART_ClearFlag_FE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3285 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_IDLE ( USART_TypeDef * USARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_USART_ClearFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3318 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_LBD ( USART_TypeDef * USARTx )

Clear LIN Break Detection Flag.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR LBDCF LL_USART_ClearFlag_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3366 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_nCTS ( USART_TypeDef * USARTx )

Clear CTS Interrupt Flag.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR CTSCF LL_USART_ClearFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3379 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_NE ( USART_TypeDef * USARTx )

Clear Noise Error detected Flag.

Reference Manual to LL API cross reference:
ICR NECF LL_USART_ClearFlag_NE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3296 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_ORE ( USART_TypeDef * USARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_USART_ClearFlag_ORE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3307 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_PE ( USART_TypeDef * USARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_USART_ClearFlag_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3274 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_RTO ( USART_TypeDef * USARTx )

Clear Receiver Time Out Flag.

Reference Manual to LL API cross reference:
ICR RTOCF LL_USART_ClearFlag_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3390 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TC ( USART_TypeDef * USARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_USART_ClearFlag_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3342 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TCBGT ( USART_TypeDef * USARTx )

Clear Smartcard Transmission Complete Before Guard Time Flag.

Reference Manual to LL API cross reference:
ICR TCBGTCF LL_USART_ClearFlag_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3353 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TXFE ( USART_TypeDef * USARTx )

Clear TX FIFO Empty Flag.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR TXFECF LL_USART_ClearFlag_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3331 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_UDR ( USART_TypeDef * USARTx )

Clear SPI Slave Underrun Flag.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR UDRCF LL_USART_ClearFlag_UDR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3416 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_WKUP ( USART_TypeDef * USARTx )

Clear Wake Up from stop mode Flag.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR WUCF LL_USART_ClearFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3440 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR ( const USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRF LL_USART_IsActiveFlag_ABR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3121 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE ( const USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Error Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRE LL_USART_IsActiveFlag_ABRE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3108 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY ( const USART_TypeDef * USARTx )

Check if the USART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_USART_IsActiveFlag_BUSY
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3132 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM ( const USART_TypeDef * USARTx )

Check if the USART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_USART_IsActiveFlag_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3143 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS ( const USART_TypeDef * USARTx )

Check if the USART CTS Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTS LL_USART_IsActiveFlag_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3058 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB ( const USART_TypeDef * USARTx )

Check if the USART End Of Block Flag is set or not.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR EOBF LL_USART_IsActiveFlag_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3082 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE ( const USART_TypeDef * USARTx )

Check if the USART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_USART_IsActiveFlag_FE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2943 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE ( const USART_TypeDef * USARTx )

Check if the USART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_USART_IsActiveFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2976 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD ( const USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Flag is set or not.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR LBDF LL_USART_IsActiveFlag_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3032 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS ( const USART_TypeDef * USARTx )

Check if the USART CTS interrupt Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTSIF LL_USART_IsActiveFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3045 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE ( const USART_TypeDef * USARTx )

Check if the USART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_USART_IsActiveFlag_NE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2954 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE ( const USART_TypeDef * USARTx )

Check if the USART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_USART_IsActiveFlag_ORE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2965 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE ( const USART_TypeDef * USARTx )

Check if the USART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_USART_IsActiveFlag_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2932 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK ( const USART_TypeDef * USARTx )

Check if the USART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_USART_IsActiveFlag_REACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3200 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO ( const USART_TypeDef * USARTx )

Check if the USART Receiver Time Out Flag is set or not.

Reference Manual to LL API cross reference:
ISR RTOF LL_USART_IsActiveFlag_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3069 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU ( const USART_TypeDef * USARTx )

Check if the USART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_USART_IsActiveFlag_RWU
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3165 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF ( const USART_TypeDef * USARTx )

Check if the USART RX FIFO Full Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXFF LL_USART_IsActiveFlag_RXFF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3226 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT ( const USART_TypeDef * USARTx )

Check if the USART RX FIFO Threshold Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXFT LL_USART_IsActiveFlag_RXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3263 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE ( const USART_TypeDef * USARTx )

Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2992 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK ( const USART_TypeDef * USARTx )

Check if the USART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_USART_IsActiveFlag_SBK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3154 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC ( const USART_TypeDef * USARTx )

Check if the USART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_USART_IsActiveFlag_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3003 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT ( const USART_TypeDef * USARTx )

Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.

Reference Manual to LL API cross reference:
ISR TCBGT LL_USART_IsActiveFlag_TCBGT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3237 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK ( const USART_TypeDef * USARTx )

Check if the USART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_USART_IsActiveFlag_TEACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3189 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF ( const USART_TypeDef * USARTx )

Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3019 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE ( const USART_TypeDef * USARTx )

Check if the USART TX FIFO Empty Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXFE LL_USART_IsActiveFlag_TXFE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3213 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT ( const USART_TypeDef * USARTx )

Check if the USART TX FIFO Threshold Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXFT LL_USART_IsActiveFlag_TXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3250 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR ( const USART_TypeDef * USARTx )

Check if the SPI Slave Underrun error flag is set or not.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR UDR LL_USART_IsActiveFlag_UDR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3095 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP ( const USART_TypeDef * USARTx )

Check if the USART Wake Up from stop mode Flag is set or not.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR WUF LL_USART_IsActiveFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3178 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT_Management

Defines | Functions
IT_Management
USART Exported Functions

Defines

#define | LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
#define | LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
#define | LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
#define | LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
#define | LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
#define | LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFE (USART_TypeDef *USARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFF (USART_TypeDef *USARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFT (USART_TypeDef *USARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TCBGT (USART_TypeDef *USARTx)
Enable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFT (USART_TypeDef *USARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFE (USART_TypeDef *USARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFF (USART_TypeDef *USARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFT (USART_TypeDef *USARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TCBGT (USART_TypeDef *USARTx)
Disable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFT (USART_TypeDef *USARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (const USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE_RXFNE (const USART_TypeDef *USARTx)
Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (const USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE_TXFNF (const USART_TypeDef *USARTx)
Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (const USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (const USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (const USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (const USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFE (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFF (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (const USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (const USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (const USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (const USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFT (const USART_TypeDef *USARTx)
Check if USART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TCBGT (const USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFT (const USART_TypeDef *USARTx)
Check if USART RX FIFO Threshold Interrupt is enabled or disabled.

Define Documentation

#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE

Definition at line 3682 of file stm32g0xx_ll_usart.h.

#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF

Definition at line 3709 of file stm32g0xx_ll_usart.h.

#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE

Definition at line 3465 of file stm32g0xx_ll_usart.h.

#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF

Definition at line 3492 of file stm32g0xx_ll_usart.h.

#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE

Definition at line 3901 of file stm32g0xx_ll_usart.h.

#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Definition at line 3928 of file stm32g0xx_ll_usart.h.

Function Documentation

__STATIC_INLINE void LL_USART_DisableIT_CM ( USART_TypeDef * USARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_DisableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3741 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_CTS ( USART_TypeDef * USARTx )

Disable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_DisableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3832 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_EOB ( USART_TypeDef * USARTx )

Disable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_DisableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3765 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_ERROR ( USART_TypeDef * USARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_DisableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3819 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_IDLE ( USART_TypeDef * USARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_DisableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3676 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_LBD ( USART_TypeDef * USARTx )

Disable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_DisableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3804 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_PE ( USART_TypeDef * USARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_DisableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3730 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RTO ( USART_TypeDef * USARTx )

Disable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_DisableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3752 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXFF ( USART_TypeDef * USARTx )

Disable RX FIFO Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_DisableIT_RXFF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3791 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXFT ( USART_TypeDef * USARTx )

Disable RX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_DisableIT_RXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3884 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Disable RX Not Empty and RX FIFO Not Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3692 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TC ( USART_TypeDef * USARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_DisableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3703 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TCBGT ( USART_TypeDef * USARTx )

Disable Smartcard Transmission Complete Before Guard Time Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_DisableIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3871 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Disable TX Empty and TX FIFO Not Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3719 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXFE ( USART_TypeDef * USARTx )

Disable TX FIFO Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_DisableIT_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3778 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXFT ( USART_TypeDef * USARTx )

Disable TX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_DisableIT_TXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3858 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_WKUP ( USART_TypeDef * USARTx )

Disable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_DisableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3845 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CM ( USART_TypeDef * USARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_EnableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3524 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CTS ( USART_TypeDef * USARTx )

Enable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_EnableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3613 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_EOB ( USART_TypeDef * USARTx )

Enable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_EnableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3548 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_ERROR ( USART_TypeDef * USARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_EnableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3600 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_IDLE ( USART_TypeDef * USARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_EnableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3459 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_LBD ( USART_TypeDef * USARTx )

Enable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_EnableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3585 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_PE ( USART_TypeDef * USARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_EnableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3513 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RTO ( USART_TypeDef * USARTx )

Enable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_EnableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3535 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXFF ( USART_TypeDef * USARTx )

Enable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_EnableIT_RXFF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3572 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXFT ( USART_TypeDef * USARTx )

Enable RX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_EnableIT_RXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3665 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Enable RX Not Empty and RX FIFO Not Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3475 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TC ( USART_TypeDef * USARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_EnableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3486 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TCBGT ( USART_TypeDef * USARTx )

Enable Smartcard Transmission Complete Before Guard Time Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_EnableIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3652 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Enable TX Empty and TX FIFO Not Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3502 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXFE ( USART_TypeDef * USARTx )

Enable TX FIFO Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_EnableIT_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3561 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXFT ( USART_TypeDef * USARTx )

Enable TX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_EnableIT_TXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3639 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_WKUP ( USART_TypeDef * USARTx )

Enable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_EnableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3626 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM ( const USART_TypeDef * USARTx )

Check if the USART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_IsEnabledIT_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3960 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS ( const USART_TypeDef * USARTx )

Check if the USART CTS Interrupt is enabled or disabled.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_IsEnabledIT_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4047 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB ( const USART_TypeDef * USARTx )

Check if the USART End Of Block Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_IsEnabledIT_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3984 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR ( const USART_TypeDef * USARTx )

Check if the USART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_USART_IsEnabledIT_ERROR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4034 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE ( const USART_TypeDef * USARTx )

Check if the USART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3895 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD ( const USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Interrupt is enabled or disabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_IsEnabledIT_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4023 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE ( const USART_TypeDef * USARTx )

Check if the USART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_IsEnabledIT_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3949 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO ( const USART_TypeDef * USARTx )

Check if the USART Receiver Timeout Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_IsEnabledIT_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3971 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF ( const USART_TypeDef * USARTx )

Check if the USART RX FIFO Full Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4010 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT ( const USART_TypeDef * USARTx )

Check if USART RX FIFO Threshold Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4099 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE ( const USART_TypeDef * USARTx )

Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3911 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC ( const USART_TypeDef * USARTx )

Check if the USART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_IsEnabledIT_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3922 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT ( const USART_TypeDef * USARTx )

Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4086 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF ( const USART_TypeDef * USARTx )

Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3938 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE ( const USART_TypeDef * USARTx )

Check if the USART TX FIFO Empty Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3997 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT ( const USART_TypeDef * USARTx )

Check if USART TX FIFO Threshold Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4073 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP ( const USART_TypeDef * USARTx )

Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_IsEnabledIT_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4060 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA_Management

Functions
DMA_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (const USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (const USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (const USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (const USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_DisableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4195 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_RX ( USART_TypeDef * USARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_DisableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4129 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_TX ( USART_TypeDef * USARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_DisableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4162 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr | ( | const USART_TypeDef * | USARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_USART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_USART_DMA_GetRegAddr
Parameters:
USARTx USART Instance
Direction This parameter can be one of the following values:
  • LL_USART_DMA_REG_DATA_TRANSMIT
  • LL_USART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 4221 of file stm32g0xx_ll_usart.h.

References LL_USART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_EnableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4184 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_RX ( USART_TypeDef * USARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_EnableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4118 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_TX ( USART_TypeDef * USARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_EnableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4151 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr ( const USART_TypeDef * USARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4206 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX ( const USART_TypeDef * USARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_IsEnabledDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4140 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX ( const USART_TypeDef * USARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_IsEnabledDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4173 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data_Management

Functions
Data_Management
USART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (const USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (const USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_USART_ReceiveData8 ( const USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData8
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 4253 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE uint16_t LL_USART_ReceiveData9 ( const USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData9
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 4264 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData8 | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData8
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 4276 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData9 | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData9
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 4288 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Execution

Functions
Execution
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data and FIFO flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data and FIFO flush.

Function Documentation

__STATIC_INLINE void LL_USART_RequestAutoBaudRate ( USART_TypeDef * USARTx )

Request an Automatic Baud Rate measurement on next received data frame.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR ABRRQ LL_USART_RequestAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4309 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestBreakSending ( USART_TypeDef * USARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_USART_RequestBreakSending
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4320 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestEnterMuteMode ( USART_TypeDef * USARTx )

Put USART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_USART_RequestEnterMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4331 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestRxDataFlush ( USART_TypeDef * USARTx )

Request a Receive Data and FIFO flush.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Allows to discard the received data without reading them, and avoid an overrun condition.
Reference Manual to LL API cross reference:
RQR RXFRQ LL_USART_RequestRxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4346 of file stm32g0xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestTxDataFlush ( USART_TypeDef * USARTx )

Request a Transmit data and FIFO flush.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR TXFRQ LL_USART_RequestTxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4359 of file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Functions

ErrorStatus | LL_USART_DeInit (const USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Function Documentation

ErrorStatus LL_USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | const LL_USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
USARTx | USART Instance
USART_ClockInitStruct | pointer to a LL_USART_ClockInitTypeDef structure that contains the Clock configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 389 of file stm32g0xx_ll_usart.c.

References assert_param, LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, IS_LL_USART_CLOCKOUTPUT, IS_LL_USART_CLOCKPHASE, IS_LL_USART_CLOCKPOLARITY, IS_LL_USART_LASTBITCLKOUTPUT, LL_USART_ClockInitTypeDef::LastBitClockPulse, and LL_USART_IsEnabled().

void LL_USART_ClockStructInit ( LL_USART_ClockInitTypeDef * USART_ClockInitStruct )

Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Parameters:
USART_ClockInitStruct pointer to a LL_USART_ClockInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 436 of file stm32g0xx_ll_usart.c.

References LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_LASTCLKPULSE_NO_OUTPUT, LL_USART_PHASE_1EDGE, and LL_USART_POLARITY_LOW.

ErrorStatus LL_USART_DeInit ( const USART_TypeDef * USARTx )

De-initialize USART registers (Registers restored to their default values).

Parameters:
USARTx USART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are de-initialized
  • ERROR: USART registers are not de-initialized

Definition at line 128 of file stm32g0xx_ll_usart.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_USART2, LL_APB1_GRP1_PERIPH_USART3, LL_APB1_GRP1_PERIPH_USART4, LL_APB1_GRP1_PERIPH_USART5, LL_APB1_GRP1_PERIPH_USART6, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_USART1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_USART_Init | ( | USART_TypeDef * | USARTx,
 |  | const LL_USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initialize USART registers according to the specified parameters in USART_InitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
USARTx | USART Instance
USART_InitStruct | pointer to a LL_USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are initialized according to USART_InitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 213 of file stm32g0xx_ll_usart.c.

References assert_param, LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, IS_LL_USART_BAUDRATE, IS_LL_USART_BRR_MIN, IS_LL_USART_DATAWIDTH, IS_LL_USART_DIRECTION, IS_LL_USART_HWCONTROL, IS_LL_USART_OVERSAMPLING, IS_LL_USART_PARITY, IS_LL_USART_PRESCALER, IS_LL_USART_STOPBITS, LL_RCC_GetSystemClocksFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART2_CLKSOURCE, LL_RCC_USART3_CLKSOURCE, LL_USART_IsEnabled(), LL_USART_SetBaudRate(), LL_USART_SetHWFlowCtrl(), LL_USART_SetPrescaler(), LL_USART_SetStopBitsLength(), LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_USART_InitTypeDef::PrescalerValue, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

void LL_USART_StructInit ( LL_USART_InitTypeDef * USART_InitStruct )

Set each LL_USART_InitTypeDef field to default value.

Parameters:
USART_InitStruct pointer to a LL_USART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 362 of file stm32g0xx_ll_usart.c.

References LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, LL_USART_DATAWIDTH_8B, LL_USART_DIRECTION_TX_RX, LL_USART_HWCONTROL_NONE, LL_USART_OVERSAMPLING_16, LL_USART_PARITY_NONE, LL_USART_PRESCALER_DIV1, LL_USART_STOPBITS_1, LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::PrescalerValue, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UTILS Private functions

Functions
UTILS Private functions
UTILS

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.

Function Documentation

static ErrorStatus UTILS_EnablePLLAndSwitchSystem | ( | uint32_t | SYSCLK_Frequency,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  | [static]

Function to enable PLL and switch system clock to PLL.

Parameters:
SYSCLK_Frequency | SYSCLK frequency
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: No problem to switch system to PLL
  • ERROR: Problem to switch system to PLL

Definition at line 507 of file stm32g0xx_ll_utils.c.

References __LL_RCC_CALC_HCLK_FREQ, LL_UTILS_ClkInitTypeDef::AHBCLKDivider, LL_UTILS_ClkInitTypeDef::APB1CLKDivider, assert_param, IS_LL_UTILS_APB1_DIV, IS_LL_UTILS_SYSCLK_DIV, LL_RCC_GetSysClkSource(), LL_RCC_PLL_Enable(), LL_RCC_PLL_EnableDomain_SYS(), LL_RCC_PLL_IsReady(), LL_RCC_SetAHBPrescaler(), LL_RCC_SetAPB1Prescaler(), LL_RCC_SetSysClkSource(), LL_RCC_SYS_CLKSOURCE_PLL, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, LL_SetFlashLatency(), and LL_SetSystemCoreClock().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static uint32_t UTILS_GetPLLOutputFrequency | ( | uint32_t | PLL_InputFrequency,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct
 | ) |  | [static]

Function to check that PLL can be modified.

Parameters:
PLL_InputFrequency | PLL input frequency (in Hz)
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
Return values:
PLL output frequency (in Hz)

Definition at line 453 of file stm32g0xx_ll_utils.c.

References assert_param, IS_LL_UTILS_PLL_FREQUENCY, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLR_VALUE, IS_LL_UTILS_PLLVCO_INPUT, IS_LL_UTILS_PLLVCO_OUTPUT, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, and LL_UTILS_PLLInitTypeDef::PLLR.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static ErrorStatus UTILS_PLL_IsBusy ( void ) [static]

Function to check that PLL can be modified.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PLL modification can be done
  • ERROR: PLL is busy

Definition at line 484 of file stm32g0xx_ll_utils.c.

References LL_RCC_PLL_IsReady().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UTILS Private Constants

Defines
UTILS Private Constants
UTILS

Defines

#define | UTILS_MAX_FREQUENCY 64000000U
#define | UTILS_PLLVCO_INPUT_MIN 4000000U
#define | UTILS_PLLVCO_INPUT_MAX 8000000U
#define | UTILS_PLLVCO_OUTPUT_MIN 64000000U
#define | UTILS_PLLVCO_OUTPUT_MAX 344000000U
#define | UTILS_HSE_FREQUENCY_MIN 4000000U
#define | UTILS_HSE_FREQUENCY_MAX 48000000U
#define | UTILS_SCALE1_LATENCY1_FREQ 24000000U
#define | UTILS_SCALE1_LATENCY2_FREQ 48000000U
#define | UTILS_SCALE1_LATENCY3_FREQ 64000000U
#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.

Define Documentation

#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE

Flash size data register base address.

Definition at line 70 of file stm32g0xx_ll_utils.h.

Referenced by LL_GetFlashSize().

#define LL_MAX_DELAY 0xFFFFFFFFU

Definition at line 60 of file stm32g0xx_ll_utils.h.

Referenced by LL_mDelay().

#define PACKAGE_BASE_ADDRESS PACKAGE_BASE

Package data register base address.

Definition at line 75 of file stm32g0xx_ll_utils.h.

Referenced by LL_GetPackageType().

#define UID_BASE_ADDRESS UID_BASE

Unique device ID register base address.

Definition at line 65 of file stm32g0xx_ll_utils.h.

Referenced by LL_GetUID_Word0(), LL_GetUID_Word1(), and LL_GetUID_Word2().

#define UTILS_HSE_FREQUENCY_MAX 48000000U

Frequency max for HSE frequency, in Hz

Definition at line 53 of file stm32g0xx_ll_utils.c.

#define UTILS_HSE_FREQUENCY_MIN 4000000U

Frequency min for HSE frequency, in Hz

Definition at line 52 of file stm32g0xx_ll_utils.c.

#define UTILS_MAX_FREQUENCY 64000000U

Maximum frequency for system clock, in Hz

Definition at line 43 of file stm32g0xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MAX 8000000U

Frequency max for PLLVCO input, in Hz

Definition at line 47 of file stm32g0xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MIN 4000000U

Frequency min for PLLVCO input, in Hz

Definition at line 46 of file stm32g0xx_ll_utils.c.

#define UTILS_PLLVCO_OUTPUT_MAX 344000000U

Frequency max for PLLVCO output, in Hz

Definition at line 49 of file stm32g0xx_ll_utils.c.

#define UTILS_PLLVCO_OUTPUT_MIN 64000000U

Frequency min for PLLVCO output, in Hz

Definition at line 48 of file stm32g0xx_ll_utils.c.

#define UTILS_SCALE1_LATENCY1_FREQ 24000000U

HCLK frequency to set FLASH latency 1 in power scale 1

Definition at line 56 of file stm32g0xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY2_FREQ 48000000U

HCLK frequency to set FLASH latency 2 in power scale 1

Definition at line 57 of file stm32g0xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

#define UTILS_SCALE1_LATENCY3_FREQ 64000000U

HCLK frequency to set FLASH latency 3 in power scale 1

Definition at line 58 of file stm32g0xx_ll_utils.c.

Referenced by LL_SetFlashLatency().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UTILS Private Macros

Defines
UTILS Private Macros
UTILS

Defines

#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_HSI_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_LL_UTILS_PLLR_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Define Documentation

#define IS_LL_UTILS_APB1_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB1_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))

Definition at line 77 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_HSE_BYPASS ( __STATE__ )
Value:
(((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))

Definition at line 117 of file stm32g0xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_HSE_FREQUENCY ( __FREQUENCY__ ) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Definition at line 120 of file stm32g0xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_HSI_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_HSI_DIV_1)  \
                                      || ((__VALUE__) == LL_RCC_HSI_DIV_2)  \
                                      || ((__VALUE__) == LL_RCC_HSI_DIV_4)  \
                                      || ((__VALUE__) == LL_RCC_HSI_DIV_8)  \
                                      || ((__VALUE__) == LL_RCC_HSI_DIV_16) \
                                      || ((__VALUE__) == LL_RCC_HSI_DIV_32) \
                                      || ((__VALUE__) == LL_RCC_HSI_DIV_64) \
                                      || ((__VALUE__) == LL_RCC_HSI_DIV_128))

Definition at line 83 of file stm32g0xx_ll_utils.c.

#define IS_LL_UTILS_PLL_FREQUENCY ( __VALUE__ ) ((__VALUE__) <= UTILS_MAX_FREQUENCY)

Definition at line 115 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLM_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLLM_DIV_1) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8))

Definition at line 92 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLN_VALUE ( __VALUE__ ) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))

Definition at line 101 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLR_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLLR_DIV_2) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_8))

Definition at line 103 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_INPUT ( __VALUE__ ) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))

Definition at line 111 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_OUTPUT ( __VALUE__ ) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))

Definition at line 113 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_SYSCLK_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))

Definition at line 67 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_UTILS_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_PLLInitTypeDef Struct Reference
UTILS Exported structures

UTILS PLL structure definition. More...

#include <stm32g0xx_ll_utils.h>

Data Fields

uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLR

Detailed Description

UTILS PLL structure definition.

Definition at line 95 of file stm32g0xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_PLLInitTypeDef::PLLM

Division factor for PLL VCO input clock. This parameter can be a value of PLL division factor (PLLM)

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 97 of file stm32g0xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLN

Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 103 of file stm32g0xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLR

Division for the main system clock. This parameter can be a value of PLL division factor (PLLR)

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 109 of file stm32g0xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_utils.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: LL_UTILS_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_ClkInitTypeDef Struct Reference
UTILS Exported structures

UTILS System, AHB and APB buses clock configuration structure definition. More...

#include <stm32g0xx_ll_utils.h>

Data Fields

uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider

Detailed Description

UTILS System, AHB and APB buses clock configuration structure definition.

Definition at line 119 of file stm32g0xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetAHBPrescaler().

Definition at line 121 of file stm32g0xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB1)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB1Prescaler().

Definition at line 127 of file stm32g0xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

The documentation for this struct was generated from the following file:
  • stm32g0xx_ll_utils.h
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: HSE Bypass activation

Defines
HSE Bypass activation
UTILS Exported Constants

Defines

#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U

Define Documentation

#define LL_UTILS_HSEBYPASS_OFF 0x00000000U

HSE Bypass is not enabled

Definition at line 146 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_HSEBYPASS_ON 0x00000001U

HSE Bypass is enabled

Definition at line 147 of file stm32g0xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PACKAGE TYPE

Defines
PACKAGE TYPE
UTILS Exported Constants

Defines

#define | LL_UTILS_PACKAGETYPE_QFP100 0x00000000U
#define | LL_UTILS_PACKAGETYPE_QFN32_GP 0x00000001U
#define | LL_UTILS_PACKAGETYPE_QFN32_N 0x00000002U
#define | LL_UTILS_PACKAGETYPE_QFN48_GP 0x00000004U
#define | LL_UTILS_PACKAGETYPE_QFN48_N 0x00000005U
#define | LL_UTILS_PACKAGETYPE_WLCSP52 0x00000006U
#define | LL_UTILS_PACKAGETYPE_QFN64_GP 0x00000007U
#define | LL_UTILS_PACKAGETYPE_QFN64_N 0x00000008U
#define | LL_UTILS_PACKAGETYPE_BGA64_N 0x0000000AU
#define | LL_UTILS_PACKAGETYPE_QFP80 0x0000000BU
#define | LL_UTILS_PACKAGETYPE_BGA100 0x0000000CU

Define Documentation

#define LL_UTILS_PACKAGETYPE_BGA100 0x0000000CU

UBGA100 package type

Definition at line 166 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_BGA64_N 0x0000000AU

UFBGA64 N-version

Definition at line 164 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN32_GP 0x00000001U

LQFP32/UFQFPN32 General purpose (GP)

Definition at line 157 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN32_N 0x00000002U

LQFP32/UFQFPN32 N-version

Definition at line 158 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN48_GP 0x00000004U

LQFP48/UFQPN48 General purpose (GP)

Definition at line 159 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN48_N 0x00000005U

LQFP48/UFQPN48 N-version

Definition at line 160 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN64_GP 0x00000007U

LQFP64 General purpose (GP)

Definition at line 162 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN64_N 0x00000008U

LQFP64 N-version

Definition at line 163 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFP100 0x00000000U

LQFP100 package type

Definition at line 156 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFP80 0x0000000BU

LQFP80 package type

Definition at line 165 of file stm32g0xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_WLCSP52 0x00000006U

WLCSP52

Definition at line 161 of file stm32g0xx_ll_utils.h.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DEVICE ELECTRONIC SIGNATURE

Functions
DEVICE ELECTRONIC SIGNATURE
UTILS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.

Function Documentation

__STATIC_INLINE uint32_t LL_GetFlashSize ( void )

Get Flash memory size.

Note:
This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
Return values:
FLASH_SIZE[15:0],: Flash memory size

Definition at line 234 of file stm32g0xx_ll_utils.h.

References FLASHSIZE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetPackageType ( void )

Get Package type.

Return values:
PKG[3:0],: Package type - This parameter can be a value of PACKAGE TYPE

Definition at line 271 of file stm32g0xx_ll_utils.h.

References PACKAGE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word0 ( void )

Get Word0 of the unique device identifier (UID based on 96 bits)

Return values:
UID[31:0],: X and Y coordinates on the wafer expressed in BCD format

Definition at line 205 of file stm32g0xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word1 ( void )

Get Word1 of the unique device identifier (UID based on 96 bits)

Return values:
UID[63:32],: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])

Definition at line 214 of file stm32g0xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word2 ( void )

Get Word2 of the unique device identifier (UID based on 96 bits)

Return values:
UID[95:64],: Lot number (ASCII encoded) - LOT_NUM[55:24]

Definition at line 223 of file stm32g0xx_ll_utils.h.

References UID_BASE_ADDRESS.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DELAY

Functions
DELAY
UTILS Exported Functions

Functions

void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.

Function Documentation

void LL_Init1msTick ( uint32_t HCLKFrequency )

This function configures the Cortex-M SysTick source to have 1ms time base.

Note:
When a RTOS is used, it is recommended to avoid changing the Systick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
HCLKFrequency HCLK frequency in Hz
Note:
HCLK frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq
Return values:
None

Definition at line 153 of file stm32g0xx_ll_utils.c.

References LL_InitTick().

__STATIC_INLINE void LL_InitTick | ( | uint32_t | HCLKFrequency,
 |  | uint32_t | Ticks
 | ) |  |

This function configures the Cortex-M SysTick source of the time base.

Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Note:
When a RTOS is used, it is recommended to avoid changing the SysTick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
Ticks Number of ticks
Return values:
None

Definition at line 296 of file stm32g0xx_ll_utils.h.

Referenced by LL_Init1msTick().

void LL_mDelay ( uint32_t Delay )

This function provides accurate delay (in milliseconds) based on SysTick counter flag.

Note:
When a RTOS is used, it is recommended to avoid using blocking delay and use rather osDelay service.
To respect 1ms timebase, user should call LL_Init1msTick function which will configure Systick to 1ms
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 169 of file stm32g0xx_ll_utils.c.

References LL_MAX_DELAY.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSTEM

Functions
SYSTEM
UTILS Exported Functions

System Configuration functions. More...

Functions

void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.
ErrorStatus | LL_SetFlashLatency (uint32_t HCLKFrequency)
Update number of Flash wait states in line with new frequency and current voltage range.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 64000000 Hz.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE | ( | uint32_t | HSEFrequency,
 |  | uint32_t | HSEBypass,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSE as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
Parameters:
HSEFrequency | Value between Min_Data = 4000000 and Max_Data = 48000000
HSEBypass This parameter can be one of the following values:
  • LL_UTILS_HSEBYPASS_ON
  • LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 315 of file stm32g0xx_ll_utils.c.

References assert_param, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSE, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_HSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 64000000 Hz is reach (PLLVCO_output / PLLR)
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 257 of file stm32g0xx_ll_utils.c.

References HSI_VALUE, LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_SetFlashLatency ( uint32_t HCLKFrequency )

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters:
HCLKFrequency HCLK frequency
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 376 of file stm32g0xx_ll_utils.c.

References LL_FLASH_GetLatency(), LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_SetLatency(), UTILS_SCALE1_LATENCY1_FREQ, UTILS_SCALE1_LATENCY2_FREQ, and UTILS_SCALE1_LATENCY3_FREQ.

Referenced by UTILS_EnablePLLAndSwitchSystem().

void LL_SetSystemCoreClock ( uint32_t HCLKFrequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:
Variable can be calculated also through SystemCoreClockUpdate function.
Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Return values:
None

Definition at line 235 of file stm32g0xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: IT Defines

Defines
IT Defines
WWDG Exported Constants

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions. More...

Defines

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Detailed Description

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

Define Documentation

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Definition at line 54 of file stm32g0xx_ll_wwdg.h.

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STM32G0C1xx HAL User Manual: PRESCALER

Defines
PRESCALER
WWDG Exported Constants

Defines

#define | LL_WWDG_PRESCALER_1 0x00000000u
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

Define Documentation

#define LL_WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 62 of file stm32g0xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/128

Definition at line 69 of file stm32g0xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2

WWDG counter clock = (PCLK1/4096)/16

Definition at line 66 of file stm32g0xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 63 of file stm32g0xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/32

Definition at line 67 of file stm32g0xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 64 of file stm32g0xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/64

Definition at line 68 of file stm32g0xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 65 of file stm32g0xx_ll_wwdg.h.

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STM32G0C1xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
WWDG Exported Macros

Defines

#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Define Documentation

#define LL_WWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 100 of file stm32g0xx_ll_wwdg.h.

#define LL_WWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 92 of file stm32g0xx_ll_wwdg.h.

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STM32G0C1xx HAL User Manual: Configuration

Functions
Configuration
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)

Function Documentation

__STATIC_INLINE void LL_WWDG_Enable ( WWDG_TypeDef * WWDGx )

Enable Window Watchdog.

The watchdog is always disabled after a reset.

Note:
It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_Enable
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 127 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetCounter ( WWDG_TypeDef * WWDGx )

Return current Watchdog Counter Value (7 bits counter value)

Reference Manual to LL API cross reference:
CR T LL_WWDG_GetCounter
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Counter value

Definition at line 165 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler ( WWDG_TypeDef * WWDGx )

Return current Watchdog Prescaler Value.

Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_GetPrescaler
Parameters:
WWDGx WWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
  • LL_WWDG_PRESCALER_16
  • LL_WWDG_PRESCALER_32
  • LL_WWDG_PRESCALER_64
  • LL_WWDG_PRESCALER_128

Definition at line 206 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetWindow ( WWDG_TypeDef * WWDGx )

Return current Watchdog Window Value (7 bits value)

Reference Manual to LL API cross reference:
CFR W LL_WWDG_GetWindow
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Window value

Definition at line 238 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabled ( WWDG_TypeDef * WWDGx )

Checks if Window Watchdog is enabled.

Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_IsEnabled
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 138 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetCounter | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Counter
 | ) |  |

Set the Watchdog counter value to provided value (7-bits T[6:0])

Note:
When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset This counter is decremented every (4096 x 2expWDGTB) PCLK cycles A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
Reference Manual to LL API cross reference:
CR T LL_WWDG_SetCounter
Parameters:
WWDGx | WWDG Instance
Counter | 0..0x7F (7 bit counter value)
Return values:
None

Definition at line 154 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetPrescaler | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the time base of the prescaler (WDGTB).

Note:
Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter is decremented every (4096 x 2expWDGTB) PCLK cycles
Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_SetPrescaler
Parameters:
WWDGx WWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
  • LL_WWDG_PRESCALER_16
  • LL_WWDG_PRESCALER_32
  • LL_WWDG_PRESCALER_64
  • LL_WWDG_PRESCALER_128
Return values:
None

Definition at line 187 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetWindow | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Window
 | ) |  |

Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

Note:
This window value defines when write in the WWDG_CR register to program Watchdog counter is allowed. Watchdog counter value update must occur only when the counter value is lower than the Watchdog window register value. Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value (in the control register) is refreshed before the downcounter has reached the watchdog window register value. Physically is possible to set the Window lower then 0x40 but it is not recommended. To generate an immediate reset, it is possible to set the Counter lower than 0x40.
Reference Manual to LL API cross reference:
CFR W LL_WWDG_SetWindow
Parameters:
WWDGx | WWDG Instance
Window | 0x00..0x7F (7 bit Window value)
Return values:
None

Definition at line 227 of file stm32g0xx_ll_wwdg.h.

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STM32G0C1xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
WWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Function Documentation

__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_ClearFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 270 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.

Note:
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_IsActiveFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 259 of file stm32g0xx_ll_wwdg.h.

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STM32G0C1xx HAL User Manual: IT_Management

Functions
IT_Management
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP ( WWDG_TypeDef * WWDGx )

Enable the Early Wakeup Interrupt.

Note:
When set, an interrupt occurs whenever the counter reaches value 0x40. This interrupt is only cleared by hardware after a reset
Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_EnableIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 290 of file stm32g0xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP ( WWDG_TypeDef * WWDGx )

Check if Early Wakeup Interrupt is enabled.

Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_IsEnabledIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 301 of file stm32g0xx_ll_wwdg.h.

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STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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  • t
  • u
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  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • AbortCpltCallback : __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef
  • AbortReceiveCpltCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef
  • AbortTransmitCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • Activity : FDCAN_ProtocolStatusTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • ADCGroupRegularSequencerRanks : __ADC_HandleTypeDef
  • AddrCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Address : FLASH_ProcessTypeDef , UART_WakeUpTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmAEventCallback : __RTC_HandleTypeDef
  • AlarmBEventCallback : __RTC_HandleTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • Algorithm : CRYP_ConfigTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AnalogFilter : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • APB1CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFreq : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoKeyDerivation : __CRYP_HandleTypeDef
  • AutoKeyDerivation_saved : __CRYP_HandleTypeDef
  • AutomaticOutput : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadMatchCallback : __LPTIM_HandleTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoReloadWriteCallback : __LPTIM_HandleTypeDef
  • AutoRetransmission : FDCAN_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • B0 : CRYP_ConfigTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_ProcessTypeDef
  • Base_MspDeInitCallback : __TIM_HandleTypeDef
  • Base_MspInitCallback : __TIM_HandleTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • battery_charging_active : __PCD_HandleTypeDef
  • BaudRate : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BCDCallback : __PCD_HandleTypeDef
  • BESL : __PCD_HandleTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BitRateSwitch : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BootEntryPoint : FLASH_OBProgramInitTypeDef
  • Break2AFMode : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Callback : __TIM_HandleTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Polarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakAFMode : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakCallback : __TIM_HandleTypeDef
  • BreakFilter : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • BusOff : FDCAN_ProtocolStatusTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • Channel : ADC_ChannelConfTypeDef , __TIM_HandleTypeDef , ADC_AnalogWDGConfTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelNState : __TIM_HandleTypeDef
  • ChannelState : __TIM_HandleTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SPI_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef , LL_ADC_InitTypeDef
  • ClockDivider : FDCAN_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockErrorDetection : RNG_InitTypeDef , LL_RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , TIM_ClockConfigTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationCallback : __TIM_HandleTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CommutationHalfCpltCallback : __TIM_HandleTypeDef
  • CompareMatchCallback : __LPTIM_HandleTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • CompareWriteCallback : __LPTIM_HandleTypeDef
  • ConnectCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • ConvCpltCallback : __ADC_HandleTypeDef
  • ConvCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvCpltCallbackCh2 : __DAC_HandleTypeDef
  • ConvHalfCpltCallback : __ADC_HandleTypeDef
  • ConvHalfCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvHalfCpltCallbackCh2 : __DAC_HandleTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : LL_TIM_InitTypeDef , TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CR_saved : __CRYP_HandleTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CrypHeaderCount : __CRYP_HandleTypeDef
  • CrypHeaderCount_saved : __CRYP_HandleTypeDef
  • CrypInCount : __CRYP_HandleTypeDef
  • CrypInCount_saved : __CRYP_HandleTypeDef
  • CrypOutCount : __CRYP_HandleTypeDef
  • CrypOutCount_saved : __CRYP_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • a
  • b
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  • n
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  • t
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  • x
  • y
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DataFormat : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • DataInStageCallback : __PCD_HandleTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataLastErrorCode : FDCAN_ProtocolStatusTypeDef
  • DataLength : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • DataOutStageCallback : __PCD_HandleTypeDef
  • DataPrescaler : FDCAN_InitTypeDef
  • DataSize : SPI_InitTypeDef
  • DataSyncJumpWidth : FDCAN_InitTypeDef
  • DataTimeSeg1 : FDCAN_InitTypeDef
  • DataTimeSeg2 : FDCAN_InitTypeDef
  • DataType : CRYP_ConfigTypeDef
  • DataWidth : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • DataWidthUnit : CRYP_ConfigTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • Devaddress : __I2C_HandleTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : DMA_InitTypeDef , LL_DMA_InitTypeDef , SPI_InitTypeDef
  • DirectionDownCallback : __LPTIM_HandleTypeDef
  • DirectionUpCallback : __LPTIM_HandleTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DisconnectCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DMA_Handle : __ADC_HandleTypeDef
  • DMA_Handle1 : __DAC_HandleTypeDef
  • DMA_Handle2 : __DAC_HandleTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMABurstState : __TIM_HandleTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DMAUnderrunCallbackCh1 : __DAC_HandleTypeDef
  • DMAUnderrunCallbackCh2 : __DAC_HandleTypeDef
  • DualAddressMode : SMBUS_InitTypeDef , I2C_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Encoder_MspDeInitCallback : __TIM_HandleTypeDef
  • Encoder_MspInitCallback : __TIM_HandleTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • EndOfSamplingCallback : __ADC_HandleTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ep0_PmaAllocState : __HCD_HandleTypeDef
  • ErrorCallback : __IRDA_HandleTypeDef , __RNG_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __ADC_HandleTypeDef , __SPI_HandleTypeDef , __TIM_HandleTypeDef , __CEC_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __CRYP_HandleTypeDef , __FDCAN_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef
  • ErrorCallbackCh1 : __DAC_HandleTypeDef
  • ErrorCallbackCh2 : __DAC_HandleTypeDef
  • ErrorCode : __FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __DMA_HandleTypeDef , __I2S_HandleTypeDef , __CRYP_HandleTypeDef , __IRDA_HandleTypeDef , __PCD_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __ADC_HandleTypeDef , __CEC_HandleTypeDef , __RNG_HandleTypeDef , __COMP_HandleTypeDef , __DAC_HandleTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • ErrorLogging : FDCAN_ErrorCountersTypeDef
  • ErrorPassive : FDCAN_ProtocolStatusTypeDef
  • ErrorStateIndicator : FDCAN_RxHeaderTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • ErrorStatusCallback : __FDCAN_HandleTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EventType : FDCAN_TxEventFifoTypeDef
  • EwiCallback : __WWDG_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExtendedFilterSA : FDCAN_MsgRamAddressTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExtFiltersNbr : FDCAN_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FallingCallback : EXTI_HandleTypeDef
  • FdcanClockSelection : RCC_PeriphCLKInitTypeDef
  • FDFormat : FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef , FDCAN_TxHeaderTypeDef
  • FifoMode : __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • Filter : RTC_TamperTypeDef
  • FilterConfig : FDCAN_FilterTypeDef
  • FilterID1 : FDCAN_FilterTypeDef
  • FilterID2 : FDCAN_FilterTypeDef
  • FilterIndex : FDCAN_FilterTypeDef , FDCAN_HpMsgStatusTypeDef , FDCAN_RxHeaderTypeDef
  • FilterList : FDCAN_HpMsgStatusTypeDef
  • FilterType : FDCAN_FilterTypeDef
  • FirstBit : SPI_InitTypeDef
  • FrameFormat : FDCAN_InitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GPIOSel : EXTI_ConfigTypeDef
  • gState : __SMARTCARD_HandleTypeDef , __CEC_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HallSensor_MspDeInitCallback : __TIM_HandleTypeDef
  • HallSensor_MspInitCallback : __TIM_HandleTypeDef
  • HardwareFlowControl : LL_USART_InitTypeDef , LL_LPUART_InitTypeDef
  • HbitClockDiv : LL_UCPD_InitTypeDef
  • hc : __HCD_HandleTypeDef
  • HC_NotifyURBChangeCallback : __HCD_HandleTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : __TIM_HandleTypeDef
  • hdmain : __CRYP_HandleTypeDef
  • hdmaout : __CRYP_HandleTypeDef
  • hdmarx : __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • hdmatx : __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • Header : CRYP_ConfigTypeDef
  • HeaderSize : CRYP_ConfigTypeDef
  • HeaderWidthUnit : CRYP_ConfigTypeDef
  • HighPriorityMessageCallback : __FDCAN_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HostState : __HCD_HandleTypeDef
  • HourFormat : RTC_InitTypeDef , LL_RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIDiv : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2s1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2s2ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • IC_CaptureCallback : __TIM_HandleTypeDef
  • IC_CaptureHalfCpltCallback : __TIM_HandleTypeDef
  • IC_MspDeInitCallback : __TIM_HandleTypeDef
  • IC_MspInitCallback : __TIM_HandleTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • Identifier : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IdType : FDCAN_FilterTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IfrGap : LL_UCPD_InitTypeDef
  • IN_ep : __PCD_HandleTypeDef
  • InCpltCallback : __CRYP_HandleTypeDef
  • Init : __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __TIM_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , IWDG_HandleTypeDef , __WWDG_HandleTypeDef , __ADC_HandleTypeDef , __CEC_HandleTypeDef , __HCD_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef
  • Init_saved : __CRYP_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputMinus : COMP_InitTypeDef , LL_COMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef , COMP_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : __DAC_HandleTypeDef , __TIM_HandleTypeDef , __ADC_HandleTypeDef , __DMA_HandleTypeDef , __RNG_HandleTypeDef , __UART_HandleTypeDef , __CRYP_HandleTypeDef , __I2S_HandleTypeDef , __SPI_HandleTypeDef , __RTC_HandleTypeDef , CRC_HandleTypeDef , __PCD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __COMP_HandleTypeDef , __I2C_HandleTypeDef , __CEC_HandleTypeDef , __SMBUS_HandleTypeDef , __LPTIM_HandleTypeDef , __FDCAN_HandleTypeDef , IWDG_HandleTypeDef , __USART_HandleTypeDef , __HCD_HandleTypeDef , __IRDA_HandleTypeDef , __WWDG_HandleTypeDef
  • InternalTamper3EventCallback : __RTC_HandleTypeDef
  • InternalTamper4EventCallback : __RTC_HandleTypeDef
  • InternalTamper5EventCallback : __RTC_HandleTypeDef
  • InternalTamper6EventCallback : __RTC_HandleTypeDef
  • IntTamper : RTC_InternalTamperTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsFilterMatchingFrame : FDCAN_RxHeaderTypeDef
  • ISOINIncompleteCallback : __PCD_HandleTypeDef
  • ISOOUTIncompleteCallback : __PCD_HandleTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
  • IV_saved : __CRYP_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • Key_saved : __CRYP_HandleTypeDef
  • KeyIVConfig : __CRYP_HandleTypeDef
  • KeyIVConfigSkip : CRYP_ConfigTypeDef
  • KeySize : CRYP_ConfigTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LastErrorCode : FDCAN_ProtocolStatusTypeDef
  • LatestTxFifoQRequest : __FDCAN_HandleTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • LevelOutOfWindow2Callback : __ADC_HandleTypeDef
  • LevelOutOfWindow3Callback : __ADC_HandleTypeDef
  • LevelOutOfWindowCallback : __ADC_HandleTypeDef
  • Line : EXTI_HandleTypeDef , EXTI_ConfigTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • ListenCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : __ADC_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __RTC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __CEC_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __RNG_HandleTypeDef , __COMP_HandleTypeDef , __TIM_HandleTypeDef , CRC_HandleTypeDef , __I2S_HandleTypeDef , __CRYP_HandleTypeDef , __DAC_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • LowPowerAutoPowerOff : ADC_InitTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_active : __PCD_HandleTypeDef
  • LPM_State : __PCD_HandleTypeDef
  • LPMCallback : __PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • Mask : __IRDA_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterRxCpltCallback : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • MCLKOutput : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • Memaddress : __I2C_HandleTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • MemRxCpltCallback : __I2C_HandleTypeDef
  • MemTxCpltCallback : __I2C_HandleTypeDef
  • MessageIndex : FDCAN_HpMsgStatusTypeDef
  • MessageMarker : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • MessageStorage : FDCAN_HpMsgStatusTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Mode : GPIO_InitTypeDef , __I2C_HandleTypeDef , I2S_InitTypeDef , IRDA_InitTypeDef , PWR_PVMTypeDef , PWR_PVDTypeDef , SMARTCARD_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_DMA_InitTypeDef , LL_EXTI_InitTypeDef , LL_GPIO_InitTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , COMP_InitTypeDef , DMA_InitTypeDef , EXTI_ConfigTypeDef , FDCAN_InitTypeDef
  • Month : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • MSBFirst : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • msgRam : __FDCAN_HandleTypeDef
  • MspDeInitCallback : __PCD_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __I2C_HandleTypeDef , __LPTIM_HandleTypeDef , __IRDA_HandleTypeDef , __CRYP_HandleTypeDef , __USART_HandleTypeDef , __HCD_HandleTypeDef , __CEC_HandleTypeDef , __SMBUS_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __DAC_HandleTypeDef , __FDCAN_HandleTypeDef , __I2S_HandleTypeDef
  • MspInitCallback : __SMBUS_HandleTypeDef , __ADC_HandleTypeDef , __I2S_HandleTypeDef , __SPI_HandleTypeDef , __FDCAN_HandleTypeDef , __UART_HandleTypeDef , __LPTIM_HandleTypeDef , __CEC_HandleTypeDef , __PCD_HandleTypeDef , __RNG_HandleTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __WWDG_HandleTypeDef , __DAC_HandleTypeDef , __IRDA_HandleTypeDef , __CRYP_HandleTypeDef , __USART_HandleTypeDef , __COMP_HandleTypeDef , __SMARTCARD_HandleTypeDef , __RTC_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NbData : LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbPagesToErase : FLASH_ProcessTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbRxDataToProcess : __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • NbTxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NoErase : RTC_TamperTypeDef
  • NominalPrescaler : FDCAN_InitTypeDef
  • NominalSyncJumpWidth : FDCAN_InitTypeDef
  • NominalTimeSeg1 : FDCAN_InitTypeDef
  • NominalTimeSeg2 : FDCAN_InitTypeDef
  • NoStretchMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • NSS : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
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  • a
  • b
  • c
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  • f
  • g
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  • i
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OC_DelayElapsedCallback : __TIM_HandleTypeDef
  • OC_MspDeInitCallback : __TIM_HandleTypeDef
  • OC_MspInitCallback : __TIM_HandleTypeDef
  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OnePulse_MspDeInitCallback : __TIM_HandleTypeDef
  • OnePulse_MspInitCallback : __TIM_HandleTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : __PCD_HandleTypeDef
  • OutCpltCallback : __CRYP_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputConnection : LL_DAC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputMode : LL_DAC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef , LL_COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutPullUp : RTC_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • Overrun : ADC_InitTypeDef , LL_ADC_REG_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • OverSampling : LL_USART_InitTypeDef , UART_InitTypeDef
  • Oversampling : ADC_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : LL_I2C_InitTypeDef , I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2 : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2Masks : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : FLASH_EraseInitTypeDef , FLASH_ProcessTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : USART_InitTypeDef , LL_LPUART_InitTypeDef , IRDA_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCROP1AEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP1AStartAddr : FLASH_OBProgramInitTypeDef
  • PCROP1BEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP1BStartAddr : FLASH_OBProgramInitTypeDef
  • PCROP2AEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP2AStartAddr : FLASH_OBProgramInitTypeDef
  • PCROP2BEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP2BStartAddr : FLASH_OBProgramInitTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : __CRYP_HandleTypeDef
  • pCrypInBuffPtr_saved : __CRYP_HandleTypeDef
  • pCrypOutBuffPtr : __CRYP_HandleTypeDef
  • pCrypOutBuffPtr_saved : __CRYP_HandleTypeDef
  • pData : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriodElapsedCallback : __TIM_HandleTypeDef
  • PeriodElapsedHalfCpltCallback : __TIM_HandleTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • PeriphRequest : LL_DMA_InitTypeDef
  • Phase : __CRYP_HandleTypeDef
  • Phase_saved : __CRYP_HandleTypeDef
  • phy_chin_state : __HCD_HandleTypeDef
  • phy_chout_state : __HCD_HandleTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInitVect : CRYP_ConfigTypeDef
  • pKey : CRYP_ConfigTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • PMALookupTable : __HCD_HandleTypeDef
  • Polarity : TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef , RCC_CRSInitTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef , LPTIM_ULPClockConfigTypeDef
  • PortDisabledCallback : __HCD_HandleTypeDef
  • PortEnabledCallback : __HCD_HandleTypeDef
  • PowerMode : IRDA_InitTypeDef , LL_COMP_InitTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : WWDG_InitTypeDef , IWDG_InitTypeDef , LPTIM_ClockConfigTypeDef , RCC_CRSInitTypeDef , LL_LPTIM_InitTypeDef , TIM_Base_InitTypeDef , LL_TIM_InitTypeDef , SMARTCARD_InitTypeDef , IRDA_InitTypeDef
  • PrescalerValue : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • PreviousState : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Priority : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • ProtocolException : FDCAN_ProtocolStatusTypeDef , FDCAN_InitTypeDef
  • pRxBuffPtr : __SPI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __I2S_HandleTypeDef
  • psc_ucpdclk : LL_UCPD_InitTypeDef
  • pTxBuffPtr : __I2S_HandleTypeDef , __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __CEC_HandleTypeDef , __SPI_HandleTypeDef
  • Pull : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PVMType : PWR_PVMTypeDef
  • PWM_MspDeInitCallback : __TIM_HandleTypeDef
  • PWM_MspInitCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedHalfCpltCallback : __TIM_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RandomNumber : __RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_OversamplingTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • ReadyDataCallback : __RNG_HandleTypeDef
  • ReceptionType : __UART_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • ResetCallback : __PCD_HandleTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • ResumeCallback : __PCD_HandleTypeDef
  • ResumingFlag : __CRYP_HandleTypeDef
  • RightBitShift : ADC_OversamplingTypeDef
  • RisingCallback : EXTI_HandleTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxBRSflag : FDCAN_ProtocolStatusTypeDef
  • RxBuffer : CEC_InitTypeDef
  • RxCpltCallback : __USART_HandleTypeDef , __CEC_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • RxErrorCnt : FDCAN_ErrorCountersTypeDef
  • RxErrorPassive : FDCAN_ErrorCountersTypeDef
  • RxESIflag : FDCAN_ProtocolStatusTypeDef
  • RxEventCallback : __UART_HandleTypeDef
  • RxEventType : __UART_HandleTypeDef
  • RxFDFflag : FDCAN_ProtocolStatusTypeDef
  • RxFifo0Callback : __FDCAN_HandleTypeDef
  • RxFIFO0SA : FDCAN_MsgRamAddressTypeDef
  • RxFifo1Callback : __FDCAN_HandleTypeDef
  • RxFIFO1SA : FDCAN_MsgRamAddressTypeDef
  • RxFifoFullCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxFrameType : FDCAN_RxHeaderTypeDef
  • RxHalfCpltCallback : __USART_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __I2S_HandleTypeDef
  • RxISR : __UART_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __UART_HandleTypeDef , __CEC_HandleTypeDef
  • RxTimestamp : FDCAN_RxHeaderTypeDef
  • RxXferCount : __USART_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __I2S_HandleTypeDef , __SPI_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • RxXferSize : __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __CEC_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • SamplingTimeCommon1 : ADC_InitTypeDef
  • SamplingTimeCommon2 : ADC_InitTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • SecSize : FLASH_OBProgramInitTypeDef
  • SecSize2 : FLASH_OBProgramInitTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef
  • Setup : __PCD_HandleTypeDef
  • SetupStageCallback : __PCD_HandleTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • Size : MPU_Region_InitTypeDef , __CRYP_HandleTypeDef
  • Size_saved : __CRYP_HandleTypeDef
  • SizesSum : __CRYP_HandleTypeDef
  • SizesSum_saved : __CRYP_HandleTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , __USART_HandleTypeDef
  • SlaveRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlaveTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • SOFCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Standard : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • StandardFilterSA : FDCAN_MsgRamAddressTypeDef
  • State : __DAC_HandleTypeDef , __I2C_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __TIM_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __HCD_HandleTypeDef , __I2S_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __SPI_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMBUS_HandleTypeDef , __USART_HandleTypeDef
  • State_saved : __CRYP_HandleTypeDef
  • Status : __LPTIM_HandleTypeDef
  • StdFiltersNbr : FDCAN_InitTypeDef
  • StopBits : LL_LPUART_InitTypeDef , SMARTCARD_InitTypeDef , USART_InitTypeDef , LL_USART_InitTypeDef , UART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendCallback : __PCD_HandleTypeDef
  • SuspendRequest : __CRYP_HandleTypeDef
  • SUSPxR_saved : __CRYP_HandleTypeDef
  • Swap : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • Tamper : RTC_TamperTypeDef
  • Tamper1EventCallback : __RTC_HandleTypeDef
  • Tamper2EventCallback : __RTC_HandleTypeDef
  • Tamper3EventCallback : __RTC_HandleTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TampOffset : __RTC_HandleTypeDef
  • TDCvalue : FDCAN_ProtocolStatusTypeDef
  • Tim15ClockSelection : RCC_PeriphCLKInitTypeDef
  • Tim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • TimeFormat : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeoutOccurredCallback : __FDCAN_HandleTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampEventCallback : __RTC_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef , RTC_InternalTamperTypeDef
  • TimestampWraparoundCallback : __FDCAN_HandleTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • Tolerance : CEC_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TransmitPause : FDCAN_InitTypeDef
  • transwin : LL_UCPD_InitTypeDef
  • Trigger : LL_EXTI_InitTypeDef , EXTI_ConfigTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef
  • TriggerCallback : __COMP_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerFrequencyMode : ADC_InitTypeDef
  • TriggerHalfCpltCallback : __TIM_HandleTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_DAC_InitTypeDef
  • TxBufferAbortCallback : __FDCAN_HandleTypeDef
  • TxBufferCompleteCallback : __FDCAN_HandleTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCpltCallback : __CEC_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxErrorCnt : FDCAN_ErrorCountersTypeDef
  • TxEventFifoCallback : __FDCAN_HandleTypeDef
  • TxEventFifoControl : FDCAN_TxHeaderTypeDef
  • TxEventFIFOSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoEmptyCallback : __FDCAN_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxFIFOQSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoQueueMode : FDCAN_InitTypeDef
  • TxFrameType : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • TxHalfCpltCallback : __SPI_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef
  • TxISR : __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxRxCpltCallback : __USART_HandleTypeDef , __SPI_HandleTypeDef
  • TxRxHalfCpltCallback : __SPI_HandleTypeDef
  • TxTimestamp : FDCAN_TxEventFifoTypeDef
  • TxXferCount : __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __CEC_HandleTypeDef , __I2S_HandleTypeDef
  • TxXferSize : __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : __PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WakeupCallback : __UART_HandleTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeUpTimerEventCallback : __RTC_HandleTypeDef
  • Warning : FDCAN_ProtocolStatusTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WindowOutput : COMP_InitTypeDef
  • WordLength : USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • WRPArea : FLASH_OBProgramInitTypeDef
  • WRPEndOffset : FLASH_OBProgramInitTypeDef
  • WRPStartOffset : FLASH_OBProgramInitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • XferSize : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- a -

  • AbortCpltCallback : __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef
  • AbortReceiveCpltCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef
  • AbortTransmitCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • Activity : FDCAN_ProtocolStatusTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • ADCGroupRegularSequencerRanks : __ADC_HandleTypeDef
  • AddrCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Address : FLASH_ProcessTypeDef , UART_WakeUpTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmAEventCallback : __RTC_HandleTypeDef
  • AlarmBEventCallback : __RTC_HandleTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • Algorithm : CRYP_ConfigTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AnalogFilter : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • APB1CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFreq : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoKeyDerivation : __CRYP_HandleTypeDef
  • AutoKeyDerivation_saved : __CRYP_HandleTypeDef
  • AutomaticOutput : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadMatchCallback : __LPTIM_HandleTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoReloadWriteCallback : __LPTIM_HandleTypeDef
  • AutoRetransmission : FDCAN_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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- b -

  • B0 : CRYP_ConfigTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_ProcessTypeDef
  • Base_MspDeInitCallback : __TIM_HandleTypeDef
  • Base_MspInitCallback : __TIM_HandleTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • battery_charging_active : __PCD_HandleTypeDef
  • BaudRate : IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BCDCallback : __PCD_HandleTypeDef
  • BESL : __PCD_HandleTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BitRateSwitch : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BootEntryPoint : FLASH_OBProgramInitTypeDef
  • Break2AFMode : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Callback : __TIM_HandleTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Polarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakAFMode : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakCallback : __TIM_HandleTypeDef
  • BreakFilter : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BREErrorBitGen : CEC_InitTypeDef
  • BRERxStop : CEC_InitTypeDef
  • BroadcastMsgNoErrorBitGen : CEC_InitTypeDef
  • BusOff : FDCAN_ProtocolStatusTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • CecClockSelection : RCC_PeriphCLKInitTypeDef
  • Channel : ADC_ChannelConfTypeDef , __TIM_HandleTypeDef , ADC_AnalogWDGConfTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelNState : __TIM_HandleTypeDef
  • ChannelState : __TIM_HandleTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SPI_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef , LL_ADC_InitTypeDef
  • ClockDivider : FDCAN_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockErrorDetection : RNG_InitTypeDef , LL_RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , TIM_ClockConfigTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationCallback : __TIM_HandleTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CommutationHalfCpltCallback : __TIM_HandleTypeDef
  • CompareMatchCallback : __LPTIM_HandleTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • CompareWriteCallback : __LPTIM_HandleTypeDef
  • ConnectCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • ConvCpltCallback : __ADC_HandleTypeDef
  • ConvCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvCpltCallbackCh2 : __DAC_HandleTypeDef
  • ConvHalfCpltCallback : __ADC_HandleTypeDef
  • ConvHalfCpltCallbackCh1 : __DAC_HandleTypeDef
  • ConvHalfCpltCallbackCh2 : __DAC_HandleTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : LL_TIM_InitTypeDef , TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CR_saved : __CRYP_HandleTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CrypHeaderCount : __CRYP_HandleTypeDef
  • CrypHeaderCount_saved : __CRYP_HandleTypeDef
  • CrypInCount : __CRYP_HandleTypeDef
  • CrypInCount_saved : __CRYP_HandleTypeDef
  • CrypOutCount : __CRYP_HandleTypeDef
  • CrypOutCount_saved : __CRYP_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DataFormat : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • DataInStageCallback : __PCD_HandleTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataLastErrorCode : FDCAN_ProtocolStatusTypeDef
  • DataLength : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • DataOutStageCallback : __PCD_HandleTypeDef
  • DataPrescaler : FDCAN_InitTypeDef
  • DataSize : SPI_InitTypeDef
  • DataSyncJumpWidth : FDCAN_InitTypeDef
  • DataTimeSeg1 : FDCAN_InitTypeDef
  • DataTimeSeg2 : FDCAN_InitTypeDef
  • DataType : CRYP_ConfigTypeDef
  • DataWidth : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • DataWidthUnit : CRYP_ConfigTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • Devaddress : __I2C_HandleTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : DMA_InitTypeDef , LL_DMA_InitTypeDef , SPI_InitTypeDef
  • DirectionDownCallback : __LPTIM_HandleTypeDef
  • DirectionUpCallback : __LPTIM_HandleTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DisconnectCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DMA_Handle : __ADC_HandleTypeDef
  • DMA_Handle1 : __DAC_HandleTypeDef
  • DMA_Handle2 : __DAC_HandleTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMABurstState : __TIM_HandleTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DMAUnderrunCallbackCh1 : __DAC_HandleTypeDef
  • DMAUnderrunCallbackCh2 : __DAC_HandleTypeDef
  • DualAddressMode : SMBUS_InitTypeDef , I2C_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Encoder_MspDeInitCallback : __TIM_HandleTypeDef
  • Encoder_MspInitCallback : __TIM_HandleTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • EndOfSamplingCallback : __ADC_HandleTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ep0_PmaAllocState : __HCD_HandleTypeDef
  • ErrorCallback : __IRDA_HandleTypeDef , __RNG_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __ADC_HandleTypeDef , __SPI_HandleTypeDef , __TIM_HandleTypeDef , __CEC_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __CRYP_HandleTypeDef , __FDCAN_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef
  • ErrorCallbackCh1 : __DAC_HandleTypeDef
  • ErrorCallbackCh2 : __DAC_HandleTypeDef
  • ErrorCode : __FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __DMA_HandleTypeDef , __I2S_HandleTypeDef , __CRYP_HandleTypeDef , __IRDA_HandleTypeDef , __PCD_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __ADC_HandleTypeDef , __CEC_HandleTypeDef , __RNG_HandleTypeDef , __COMP_HandleTypeDef , __DAC_HandleTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • ErrorLogging : FDCAN_ErrorCountersTypeDef
  • ErrorPassive : FDCAN_ProtocolStatusTypeDef
  • ErrorStateIndicator : FDCAN_RxHeaderTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • ErrorStatusCallback : __FDCAN_HandleTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EventType : FDCAN_TxEventFifoTypeDef
  • EwiCallback : __WWDG_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExtendedFilterSA : FDCAN_MsgRamAddressTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExtFiltersNbr : FDCAN_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • FallingCallback : EXTI_HandleTypeDef
  • FdcanClockSelection : RCC_PeriphCLKInitTypeDef
  • FDFormat : FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef , FDCAN_TxHeaderTypeDef
  • FifoMode : __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • Filter : RTC_TamperTypeDef
  • FilterConfig : FDCAN_FilterTypeDef
  • FilterID1 : FDCAN_FilterTypeDef
  • FilterID2 : FDCAN_FilterTypeDef
  • FilterIndex : FDCAN_FilterTypeDef , FDCAN_HpMsgStatusTypeDef , FDCAN_RxHeaderTypeDef
  • FilterList : FDCAN_HpMsgStatusTypeDef
  • FilterType : FDCAN_FilterTypeDef
  • FirstBit : SPI_InitTypeDef
  • FrameFormat : FDCAN_InitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GPIOSel : EXTI_ConfigTypeDef
  • gState : __SMARTCARD_HandleTypeDef , __CEC_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- h -

  • HallSensor_MspDeInitCallback : __TIM_HandleTypeDef
  • HallSensor_MspInitCallback : __TIM_HandleTypeDef
  • HardwareFlowControl : LL_USART_InitTypeDef , LL_LPUART_InitTypeDef
  • HbitClockDiv : LL_UCPD_InitTypeDef
  • hc : __HCD_HandleTypeDef
  • HC_NotifyURBChangeCallback : __HCD_HandleTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : __TIM_HandleTypeDef
  • hdmain : __CRYP_HandleTypeDef
  • hdmaout : __CRYP_HandleTypeDef
  • hdmarx : __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • hdmatx : __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • Header : CRYP_ConfigTypeDef
  • HeaderSize : CRYP_ConfigTypeDef
  • HeaderWidthUnit : CRYP_ConfigTypeDef
  • HighPriorityMessageCallback : __FDCAN_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HostState : __HCD_HandleTypeDef
  • HourFormat : RTC_InitTypeDef , LL_RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIDiv : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2s1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2s2ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • IC_CaptureCallback : __TIM_HandleTypeDef
  • IC_CaptureHalfCpltCallback : __TIM_HandleTypeDef
  • IC_MspDeInitCallback : __TIM_HandleTypeDef
  • IC_MspInitCallback : __TIM_HandleTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • Identifier : FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IdType : FDCAN_FilterTypeDef , FDCAN_TxHeaderTypeDef , FDCAN_RxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • IfrGap : LL_UCPD_InitTypeDef
  • IN_ep : __PCD_HandleTypeDef
  • InCpltCallback : __CRYP_HandleTypeDef
  • Init : __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __TIM_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , IWDG_HandleTypeDef , __WWDG_HandleTypeDef , __ADC_HandleTypeDef , __CEC_HandleTypeDef , __HCD_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __I2C_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef
  • Init_saved : __CRYP_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputMinus : COMP_InitTypeDef , LL_COMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef , COMP_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : __DAC_HandleTypeDef , __TIM_HandleTypeDef , __ADC_HandleTypeDef , __DMA_HandleTypeDef , __RNG_HandleTypeDef , __UART_HandleTypeDef , __CRYP_HandleTypeDef , __I2S_HandleTypeDef , __SPI_HandleTypeDef , __RTC_HandleTypeDef , CRC_HandleTypeDef , __PCD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __COMP_HandleTypeDef , __I2C_HandleTypeDef , __CEC_HandleTypeDef , __SMBUS_HandleTypeDef , __LPTIM_HandleTypeDef , __FDCAN_HandleTypeDef , IWDG_HandleTypeDef , __USART_HandleTypeDef , __HCD_HandleTypeDef , __IRDA_HandleTypeDef , __WWDG_HandleTypeDef
  • InternalTamper3EventCallback : __RTC_HandleTypeDef
  • InternalTamper4EventCallback : __RTC_HandleTypeDef
  • InternalTamper5EventCallback : __RTC_HandleTypeDef
  • InternalTamper6EventCallback : __RTC_HandleTypeDef
  • IntTamper : RTC_InternalTamperTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsFilterMatchingFrame : FDCAN_RxHeaderTypeDef
  • ISOINIncompleteCallback : __PCD_HandleTypeDef
  • ISOOUTIncompleteCallback : __PCD_HandleTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
  • IV_saved : __CRYP_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- k -

  • Key_saved : __CRYP_HandleTypeDef
  • KeyIVConfig : __CRYP_HandleTypeDef
  • KeyIVConfigSkip : CRYP_ConfigTypeDef
  • KeySize : CRYP_ConfigTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LastErrorCode : FDCAN_ProtocolStatusTypeDef
  • LatestTxFifoQRequest : __FDCAN_HandleTypeDef
  • LBPEErrorBitGen : CEC_InitTypeDef
  • LevelOutOfWindow2Callback : __ADC_HandleTypeDef
  • LevelOutOfWindow3Callback : __ADC_HandleTypeDef
  • LevelOutOfWindowCallback : __ADC_HandleTypeDef
  • Line : EXTI_HandleTypeDef , EXTI_ConfigTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • ListenCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • ListenMode : CEC_InitTypeDef
  • Lock : __ADC_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __RTC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __CEC_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __RNG_HandleTypeDef , __COMP_HandleTypeDef , __TIM_HandleTypeDef , CRC_HandleTypeDef , __I2S_HandleTypeDef , __CRYP_HandleTypeDef , __DAC_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , FLASH_ProcessTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • LowPowerAutoPowerOff : ADC_InitTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_active : __PCD_HandleTypeDef
  • LPM_State : __PCD_HandleTypeDef
  • LPMCallback : __PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- m -

  • Mask : __IRDA_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterRxCpltCallback : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • MCLKOutput : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • Memaddress : __I2C_HandleTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • MemRxCpltCallback : __I2C_HandleTypeDef
  • MemTxCpltCallback : __I2C_HandleTypeDef
  • MessageIndex : FDCAN_HpMsgStatusTypeDef
  • MessageMarker : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • MessageStorage : FDCAN_HpMsgStatusTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Mode : GPIO_InitTypeDef , __I2C_HandleTypeDef , I2S_InitTypeDef , IRDA_InitTypeDef , PWR_PVMTypeDef , PWR_PVDTypeDef , SMARTCARD_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_DMA_InitTypeDef , LL_EXTI_InitTypeDef , LL_GPIO_InitTypeDef , LL_SPI_InitTypeDef , LL_I2S_InitTypeDef , COMP_InitTypeDef , DMA_InitTypeDef , EXTI_ConfigTypeDef , FDCAN_InitTypeDef
  • Month : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • MSBFirst : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • msgRam : __FDCAN_HandleTypeDef
  • MspDeInitCallback : __PCD_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __I2C_HandleTypeDef , __LPTIM_HandleTypeDef , __IRDA_HandleTypeDef , __CRYP_HandleTypeDef , __USART_HandleTypeDef , __HCD_HandleTypeDef , __CEC_HandleTypeDef , __SMBUS_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __DAC_HandleTypeDef , __FDCAN_HandleTypeDef , __I2S_HandleTypeDef
  • MspInitCallback : __SMBUS_HandleTypeDef , __ADC_HandleTypeDef , __I2S_HandleTypeDef , __SPI_HandleTypeDef , __FDCAN_HandleTypeDef , __UART_HandleTypeDef , __LPTIM_HandleTypeDef , __CEC_HandleTypeDef , __PCD_HandleTypeDef , __RNG_HandleTypeDef , __HCD_HandleTypeDef , __I2C_HandleTypeDef , __WWDG_HandleTypeDef , __DAC_HandleTypeDef , __IRDA_HandleTypeDef , __CRYP_HandleTypeDef , __USART_HandleTypeDef , __COMP_HandleTypeDef , __SMARTCARD_HandleTypeDef , __RTC_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • NACKEnable : SMARTCARD_InitTypeDef
  • NbData : LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbPagesToErase : FLASH_ProcessTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbRxDataToProcess : __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • NbTxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NoErase : RTC_TamperTypeDef
  • NominalPrescaler : FDCAN_InitTypeDef
  • NominalSyncJumpWidth : FDCAN_InitTypeDef
  • NominalTimeSeg1 : FDCAN_InitTypeDef
  • NominalTimeSeg2 : FDCAN_InitTypeDef
  • NoStretchMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • NSS : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • OC_DelayElapsedCallback : __TIM_HandleTypeDef
  • OC_MspDeInitCallback : __TIM_HandleTypeDef
  • OC_MspInitCallback : __TIM_HandleTypeDef
  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OnePulse_MspDeInitCallback : __TIM_HandleTypeDef
  • OnePulse_MspInitCallback : __TIM_HandleTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : __PCD_HandleTypeDef
  • OutCpltCallback : __CRYP_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputConnection : LL_DAC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputMode : LL_DAC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef , LL_COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutPullUp : RTC_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • Overrun : ADC_InitTypeDef , LL_ADC_REG_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • OverSampling : LL_USART_InitTypeDef , UART_InitTypeDef
  • Oversampling : ADC_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OwnAddress : CEC_InitTypeDef
  • OwnAddress1 : LL_I2C_InitTypeDef , I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2 : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2Masks : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : FLASH_EraseInitTypeDef , FLASH_ProcessTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : USART_InitTypeDef , LL_LPUART_InitTypeDef , IRDA_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCROP1AEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP1AStartAddr : FLASH_OBProgramInitTypeDef
  • PCROP1BEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP1BStartAddr : FLASH_OBProgramInitTypeDef
  • PCROP2AEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP2AStartAddr : FLASH_OBProgramInitTypeDef
  • PCROP2BEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP2BStartAddr : FLASH_OBProgramInitTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : __CRYP_HandleTypeDef
  • pCrypInBuffPtr_saved : __CRYP_HandleTypeDef
  • pCrypOutBuffPtr : __CRYP_HandleTypeDef
  • pCrypOutBuffPtr_saved : __CRYP_HandleTypeDef
  • pData : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriodElapsedCallback : __TIM_HandleTypeDef
  • PeriodElapsedHalfCpltCallback : __TIM_HandleTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • PeriphRequest : LL_DMA_InitTypeDef
  • Phase : __CRYP_HandleTypeDef
  • Phase_saved : __CRYP_HandleTypeDef
  • phy_chin_state : __HCD_HandleTypeDef
  • phy_chout_state : __HCD_HandleTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInitVect : CRYP_ConfigTypeDef
  • pKey : CRYP_ConfigTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • PMALookupTable : __HCD_HandleTypeDef
  • Polarity : TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef , RCC_CRSInitTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef , LPTIM_ULPClockConfigTypeDef
  • PortDisabledCallback : __HCD_HandleTypeDef
  • PortEnabledCallback : __HCD_HandleTypeDef
  • PowerMode : IRDA_InitTypeDef , LL_COMP_InitTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : WWDG_InitTypeDef , IWDG_InitTypeDef , LPTIM_ClockConfigTypeDef , RCC_CRSInitTypeDef , LL_LPTIM_InitTypeDef , TIM_Base_InitTypeDef , LL_TIM_InitTypeDef , SMARTCARD_InitTypeDef , IRDA_InitTypeDef
  • PrescalerValue : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • PreviousState : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Priority : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • ProtocolException : FDCAN_ProtocolStatusTypeDef , FDCAN_InitTypeDef
  • pRxBuffPtr : __SPI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __I2S_HandleTypeDef
  • psc_ucpdclk : LL_UCPD_InitTypeDef
  • pTxBuffPtr : __I2S_HandleTypeDef , __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __CEC_HandleTypeDef , __SPI_HandleTypeDef
  • Pull : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PVMType : PWR_PVMTypeDef
  • PWM_MspDeInitCallback : __TIM_HandleTypeDef
  • PWM_MspInitCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedHalfCpltCallback : __TIM_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • RandomNumber : __RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_OversamplingTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • ReadyDataCallback : __RNG_HandleTypeDef
  • ReceptionType : __UART_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • ResetCallback : __PCD_HandleTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • ResumeCallback : __PCD_HandleTypeDef
  • ResumingFlag : __CRYP_HandleTypeDef
  • RightBitShift : ADC_OversamplingTypeDef
  • RisingCallback : EXTI_HandleTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxBRSflag : FDCAN_ProtocolStatusTypeDef
  • RxBuffer : CEC_InitTypeDef
  • RxCpltCallback : __USART_HandleTypeDef , __CEC_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • RxErrorCnt : FDCAN_ErrorCountersTypeDef
  • RxErrorPassive : FDCAN_ErrorCountersTypeDef
  • RxESIflag : FDCAN_ProtocolStatusTypeDef
  • RxEventCallback : __UART_HandleTypeDef
  • RxEventType : __UART_HandleTypeDef
  • RxFDFflag : FDCAN_ProtocolStatusTypeDef
  • RxFifo0Callback : __FDCAN_HandleTypeDef
  • RxFIFO0SA : FDCAN_MsgRamAddressTypeDef
  • RxFifo1Callback : __FDCAN_HandleTypeDef
  • RxFIFO1SA : FDCAN_MsgRamAddressTypeDef
  • RxFifoFullCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxFrameType : FDCAN_RxHeaderTypeDef
  • RxHalfCpltCallback : __USART_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __I2S_HandleTypeDef
  • RxISR : __UART_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __UART_HandleTypeDef , __CEC_HandleTypeDef
  • RxTimestamp : FDCAN_RxHeaderTypeDef
  • RxXferCount : __USART_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __I2S_HandleTypeDef , __SPI_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • RxXferSize : __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __CEC_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __I2S_HandleTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • SamplingTimeCommon1 : ADC_InitTypeDef
  • SamplingTimeCommon2 : ADC_InitTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • SecSize : FLASH_OBProgramInitTypeDef
  • SecSize2 : FLASH_OBProgramInitTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef
  • Setup : __PCD_HandleTypeDef
  • SetupStageCallback : __PCD_HandleTypeDef
  • SignalFreeTime : CEC_InitTypeDef
  • SignalFreeTimeOption : CEC_InitTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • Size : MPU_Region_InitTypeDef , __CRYP_HandleTypeDef
  • Size_saved : __CRYP_HandleTypeDef
  • SizesSum : __CRYP_HandleTypeDef
  • SizesSum_saved : __CRYP_HandleTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , __USART_HandleTypeDef
  • SlaveRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlaveTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • SOFCallback : __HCD_HandleTypeDef , __PCD_HandleTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Standard : I2S_InitTypeDef , LL_I2S_InitTypeDef
  • StandardFilterSA : FDCAN_MsgRamAddressTypeDef
  • State : __DAC_HandleTypeDef , __I2C_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __TIM_HandleTypeDef , __DMA_HandleTypeDef , __FDCAN_HandleTypeDef , __HCD_HandleTypeDef , __I2S_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __SPI_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SMBUS_HandleTypeDef , __USART_HandleTypeDef
  • State_saved : __CRYP_HandleTypeDef
  • Status : __LPTIM_HandleTypeDef
  • StdFiltersNbr : FDCAN_InitTypeDef
  • StopBits : LL_LPUART_InitTypeDef , SMARTCARD_InitTypeDef , USART_InitTypeDef , LL_USART_InitTypeDef , UART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendCallback : __PCD_HandleTypeDef
  • SuspendRequest : __CRYP_HandleTypeDef
  • SUSPxR_saved : __CRYP_HandleTypeDef
  • Swap : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • Tamper : RTC_TamperTypeDef
  • Tamper1EventCallback : __RTC_HandleTypeDef
  • Tamper2EventCallback : __RTC_HandleTypeDef
  • Tamper3EventCallback : __RTC_HandleTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TampOffset : __RTC_HandleTypeDef
  • TDCvalue : FDCAN_ProtocolStatusTypeDef
  • Tim15ClockSelection : RCC_PeriphCLKInitTypeDef
  • Tim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • TimeFormat : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeoutOccurredCallback : __FDCAN_HandleTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampEventCallback : __RTC_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef , RTC_InternalTamperTypeDef
  • TimestampWraparoundCallback : __FDCAN_HandleTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • Tolerance : CEC_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TransmitPause : FDCAN_InitTypeDef
  • transwin : LL_UCPD_InitTypeDef
  • Trigger : LL_EXTI_InitTypeDef , EXTI_ConfigTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef
  • TriggerCallback : __COMP_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerFrequencyMode : ADC_InitTypeDef
  • TriggerHalfCpltCallback : __TIM_HandleTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_DAC_InitTypeDef
  • TxBufferAbortCallback : __FDCAN_HandleTypeDef
  • TxBufferCompleteCallback : __FDCAN_HandleTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCpltCallback : __CEC_HandleTypeDef , __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxErrorCnt : FDCAN_ErrorCountersTypeDef
  • TxEventFifoCallback : __FDCAN_HandleTypeDef
  • TxEventFifoControl : FDCAN_TxHeaderTypeDef
  • TxEventFIFOSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoEmptyCallback : __FDCAN_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxFIFOQSA : FDCAN_MsgRamAddressTypeDef
  • TxFifoQueueMode : FDCAN_InitTypeDef
  • TxFrameType : FDCAN_TxHeaderTypeDef , FDCAN_TxEventFifoTypeDef
  • TxHalfCpltCallback : __SPI_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef , __I2S_HandleTypeDef
  • TxISR : __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxRxCpltCallback : __USART_HandleTypeDef , __SPI_HandleTypeDef
  • TxRxHalfCpltCallback : __SPI_HandleTypeDef
  • TxTimestamp : FDCAN_TxEventFifoTypeDef
  • TxXferCount : __SMARTCARD_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __CEC_HandleTypeDef , __I2S_HandleTypeDef
  • TxXferSize : __I2S_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

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  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : __PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • WakeupCallback : __UART_HandleTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeUpTimerEventCallback : __RTC_HandleTypeDef
  • Warning : FDCAN_ProtocolStatusTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WindowOutput : COMP_InitTypeDef
  • WordLength : USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • WRPArea : FLASH_OBProgramInitTypeDef
  • WRPEndOffset : FLASH_OBProgramInitTypeDef
  • WRPStartOffset : FLASH_OBProgramInitTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
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STM32G0C1xx HAL User Manual: Data Fields - Variables

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  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_conf.h File Reference

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Defines
stm32g0xx_hal_conf.h File Reference

HAL configuration template file. This file should be copied to the application folder and renamed to stm32g0xx_hal_conf.h. More...

#include "stm32g0xx_hal_rcc.h"
#include "stm32g0xx_hal_gpio.h"
#include "stm32g0xx_hal_dma.h"
#include "stm32g0xx_hal_cortex.h"
#include "stm32g0xx_hal_adc.h"
#include "stm32g0xx_hal_adc_ex.h"
#include "stm32g0xx_hal_cec.h"
#include "stm32g0xx_hal_comp.h"
#include "stm32g0xx_hal_crc.h"
#include "stm32g0xx_hal_cryp.h"
#include "stm32g0xx_hal_dac.h"
#include "stm32g0xx_hal_exti.h"
#include "stm32g0xx_hal_fdcan.h"
#include "stm32g0xx_hal_flash.h"
#include "stm32g0xx_hal_i2c.h"
#include "stm32g0xx_hal_i2s.h"
#include "stm32g0xx_hal_irda.h"
#include "stm32g0xx_hal_iwdg.h"
#include "stm32g0xx_hal_lptim.h"
#include "stm32g0xx_hal_pcd.h"
#include "stm32g0xx_hal_hcd.h"
#include "stm32g0xx_hal_pwr.h"
#include "stm32g0xx_hal_rng.h"
#include "stm32g0xx_hal_rtc.h"
#include "stm32g0xx_hal_smartcard.h"
#include "stm32g0xx_hal_smbus.h"
#include "stm32g0xx_hal_spi.h"
#include "stm32g0xx_hal_tim.h"
#include "stm32g0xx_hal_uart.h"
#include "stm32g0xx_hal_usart.h"
#include "stm32g0xx_hal_wwdg.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_CEC_MODULE_ENABLED
#define | HAL_COMP_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_CRYP_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_EXTI_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_FDCAN_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_I2S_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_LPTIM_MODULE_ENABLED
#define | HAL_HCD_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RNG_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_SMBUS_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | USE_HAL_ADC_REGISTER_CALLBACKS 1u
This is the list of modules where register callback can be used.
#define | USE_HAL_CEC_REGISTER_CALLBACKS 1u
#define | USE_HAL_COMP_REGISTER_CALLBACKS 1u
#define | USE_HAL_CRYP_REGISTER_CALLBACKS 1u
#define | USE_HAL_DAC_REGISTER_CALLBACKS 1u
#define | USE_HAL_FDCAN_REGISTER_CALLBACKS 1u
#define | USE_HAL_I2C_REGISTER_CALLBACKS 1u
#define | USE_HAL_I2S_REGISTER_CALLBACKS 1u
#define | USE_HAL_IRDA_REGISTER_CALLBACKS 1u
#define | USE_HAL_LPTIM_REGISTER_CALLBACKS 1u
#define | USE_HAL_HCD_REGISTER_CALLBACKS 1u
#define | USE_HAL_PCD_REGISTER_CALLBACKS 1u
#define | USE_HAL_RNG_REGISTER_CALLBACKS 1u
#define | USE_HAL_RTC_REGISTER_CALLBACKS 1u
#define | USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1u
#define | USE_HAL_SMBUS_REGISTER_CALLBACKS 1u
#define | USE_HAL_SPI_REGISTER_CALLBACKS 1u
#define | USE_HAL_TIM_REGISTER_CALLBACKS 1u
#define | USE_HAL_UART_REGISTER_CALLBACKS 1u
#define | USE_HAL_USART_REGISTER_CALLBACKS 1u
#define | USE_HAL_WWDG_REGISTER_CALLBACKS 1u
#define | HSE_VALUE (8000000UL)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT (100UL)
#define | HSI_VALUE (16000000UL)
Internal High Speed oscillator (HSI) value.
#define | HSI48_VALUE 48000000U
Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
#define | LSI_VALUE (32000UL)
Internal Low Speed oscillator (LSI) value.
#define | LSE_VALUE (32768UL)
External Low Speed oscillator (LSE) value.
#define | LSE_STARTUP_TIMEOUT (5000UL)
#define | EXTERNAL_I2S1_CLOCK_VALUE (48000UL)
External clock source for I2S1 peripheral This value is used by the RCC HAL module to compute the I2S1 clock source frequency.
#define | EXTERNAL_I2S2_CLOCK_VALUE 48000U
External clock source for I2S2 peripheral This value is used by the RCC HAL module to compute the I2S2 clock source frequency.
#define | VDD_VALUE (3300UL)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL)
#define | USE_RTOS 0U
#define | PREFETCH_ENABLE 1U
#define | INSTRUCTION_CACHE_ENABLE 1U
#define | USE_SPI_CRC 1U
#define | USE_HAL_CRYP_SUSPEND_RESUME 1U
#define | assert_param(expr) ((void)0U)
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Detailed Description

HAL configuration template file. This file should be copied to the application folder and renamed to stm32g0xx_hal_conf.h.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Include modules header file

Definition at line 345 of file stm32g0xx_hal_conf.h.

Referenced by ADC_ConversionStop(), FLASH_MassErase(), FLASH_OB_GetWRP(), FLASH_OB_OptrConfig(), FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), FLASH_OB_PCROP2AConfig(), FLASH_OB_PCROP2BConfig(), FLASH_OB_SecMemConfig(), FLASH_OB_WRPConfig(), FLASH_PageErase(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableVoltageRegulator(), HAL_CEC_DeInit(), HAL_CEC_Init(), HAL_CEC_SetDeviceAddress(), HAL_CEC_Transmit_IT(), HAL_COMP_DeInit(), HAL_COMP_GetError(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Stop(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), HAL_CRCEx_Polynomial_Set(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualSetValue(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), HAL_DACEx_TriangleWaveGenerate(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), HAL_EXTI_SetConfigLine(), HAL_FDCAN_AbortTxRequest(), HAL_FDCAN_ActivateNotification(), HAL_FDCAN_AddMessageToTxFifoQ(), HAL_FDCAN_ConfigExtendedIdMask(), HAL_FDCAN_ConfigFilter(), HAL_FDCAN_ConfigGlobalFilter(), HAL_FDCAN_ConfigInterruptLines(), HAL_FDCAN_ConfigRamWatchdog(), HAL_FDCAN_ConfigRxFifoOverwrite(), HAL_FDCAN_ConfigTimeoutCounter(), HAL_FDCAN_ConfigTimestampCounter(), HAL_FDCAN_ConfigTxDelayCompensation(), HAL_FDCAN_DeactivateNotification(), HAL_FDCAN_DeInit(), HAL_FDCAN_EnableTimestampCounter(), HAL_FDCAN_GetRxFifoFillLevel(), HAL_FDCAN_GetRxMessage(), HAL_FDCAN_Init(), HAL_FDCAN_IsTxBufferMessagePending(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_EnableSecMemProtection(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_ForceFlashEmpty(), HAL_FLASHEx_OBProgram(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HalfDuplex_Init(), HAL_HCD_Init(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableFastModePlus(), HAL_I2CEx_EnableWakeUp(), HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetPendingIRQ(), HAL_NVIC_SetPendingIRQ(), HAL_NVIC_SetPriority(), HAL_PCD_Init(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_ConfigPVD(), HAL_PWREx_ConfigPVM(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableFlashPowerDown(), HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableBatteryCharging(), HAL_PWREx_EnableFlashPowerDown(), HAL_PWREx_EnableGPIOPullDown(), HAL_PWREx_EnableGPIOPullUp(), HAL_RCC_ClockConfig(), HAL_RCC_GetClockConfig(), HAL_RCC_GetOscConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSConfig(), HAL_RCCEx_CRSGetSynchronizationInfo(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_Init(), HAL_RS485Ex_Init(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateInternalTamper(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForInternalTamperEvent(), HAL_RTCEx_PollForTamperEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTamper(), HAL_RTCEx_SetInternalTamper_IT(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SetTickFreq(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_TimeOut_Config(), HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUSEx_DisableFastModePlus(), HAL_SMBUSEx_DisableWakeUp(), HAL_SMBUSEx_EnableFastModePlus(), HAL_SMBUSEx_EnableWakeUp(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SYSCFG_DisableClampingDiode(), HAL_SYSCFG_DisableRemap(), HAL_SYSCFG_EnableClampingDiode(), HAL_SYSCFG_EnableRemap(), HAL_SYSCFG_StrobeDBattpinsConfig(), HAL_SYSCFG_VREFBUF_HighImpedanceConfig(), HAL_SYSCFG_VREFBUF_TrimmingConfig(), HAL_SYSCFG_VREFBUF_VoltageScalingConfig(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_MultiReadStart(), HAL_TIM_DMABurst_MultiWriteStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_DMABurstState(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_GetChannelState(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_DisarmBreakInput(), HAL_TIMEx_GetChannelNState(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_ReArmBreakInput(), HAL_TIMEx_RemapConfig(), HAL_TIMEx_TISelection(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_ReceiverTimeout_Config(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), HAL_WWDG_Init(), I2C_TransferConfig(), IRDA_SetConfig(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_SetConfig(), SMBUS_TransferConfig(), TIM_CCxChannelCmd(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_AdvFeatureConfig(), UART_SetConfig(), UARTEx_Wakeup_AddressConfig(), and USART_SetConfig().

#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL)

External clock source for I2S1 peripheral This value is used by the RCC HAL module to compute the I2S1 clock source frequency.

Value of the I2S1 External clock source in Hz

Definition at line 157 of file stm32g0xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define EXTERNAL_I2S2_CLOCK_VALUE 48000U

External clock source for I2S2 peripheral This value is used by the RCC HAL module to compute the I2S2 clock source frequency.

Value of the I2S2 External clock source in Hz

Definition at line 167 of file stm32g0xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define HAL_ADC_MODULE_ENABLED

Definition at line 37 of file stm32g0xx_hal_conf.h.

#define HAL_CEC_MODULE_ENABLED

Definition at line 38 of file stm32g0xx_hal_conf.h.

#define HAL_COMP_MODULE_ENABLED

Definition at line 39 of file stm32g0xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 40 of file stm32g0xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 41 of file stm32g0xx_hal_conf.h.

#define HAL_CRYP_MODULE_ENABLED

Definition at line 42 of file stm32g0xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 43 of file stm32g0xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 44 of file stm32g0xx_hal_conf.h.

#define HAL_EXTI_MODULE_ENABLED

Definition at line 45 of file stm32g0xx_hal_conf.h.

#define HAL_FDCAN_MODULE_ENABLED

Definition at line 47 of file stm32g0xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 46 of file stm32g0xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 48 of file stm32g0xx_hal_conf.h.

#define HAL_HCD_MODULE_ENABLED

Definition at line 54 of file stm32g0xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 49 of file stm32g0xx_hal_conf.h.

#define HAL_I2S_MODULE_ENABLED

Definition at line 50 of file stm32g0xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 51 of file stm32g0xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 52 of file stm32g0xx_hal_conf.h.

#define HAL_LPTIM_MODULE_ENABLED

Definition at line 53 of file stm32g0xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 36 of file stm32g0xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 55 of file stm32g0xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 56 of file stm32g0xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 57 of file stm32g0xx_hal_conf.h.

#define HAL_RNG_MODULE_ENABLED

Definition at line 58 of file stm32g0xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 59 of file stm32g0xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 60 of file stm32g0xx_hal_conf.h.

#define HAL_SMBUS_MODULE_ENABLED

Definition at line 61 of file stm32g0xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 62 of file stm32g0xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 63 of file stm32g0xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 64 of file stm32g0xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 65 of file stm32g0xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 66 of file stm32g0xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT (100UL)

Time out for HSE start up, in ms

Definition at line 105 of file stm32g0xx_hal_conf.h.

#define HSE_VALUE (8000000UL)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 101 of file stm32g0xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetRTCClockFreq(), LL_RCC_GetUSBClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_FDCAN(), RCC_PLL_GetFreqDomain_I2S1(), RCC_PLL_GetFreqDomain_I2S2(), RCC_PLL_GetFreqDomain_RNG(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLL_GetFreqDomain_TIM1(), RCC_PLL_GetFreqDomain_TIM15(), and RCC_PLL_GetFreqDomain_USB().

#define HSI48_VALUE 48000000U

Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.

This internal oscillator is mainly dedicated to provide a high precision clock to the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. When the CRS is not used, the HSI48 RC oscillator runs on it default frequency which is subject to manufacturing process variations. Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.

Definition at line 126 of file stm32g0xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetUSBClockFreq().

#define HSI_VALUE (16000000UL)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 114 of file stm32g0xx_hal_conf.h.

Referenced by HAL_RCC_DeInit(), HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetADCClockFreq(), LL_RCC_GetCECClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetUSARTClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_FDCAN(), RCC_PLL_GetFreqDomain_I2S1(), RCC_PLL_GetFreqDomain_I2S2(), RCC_PLL_GetFreqDomain_RNG(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLL_GetFreqDomain_TIM1(), RCC_PLL_GetFreqDomain_TIM15(), RCC_PLL_GetFreqDomain_USB(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define INSTRUCTION_CACHE_ENABLE 1U

Definition at line 182 of file stm32g0xx_hal_conf.h.

#define LSE_STARTUP_TIMEOUT (5000UL)

Time out for LSE start up, in ms

Definition at line 148 of file stm32g0xx_hal_conf.h.

#define LSE_VALUE (32768UL)

External Low Speed oscillator (LSE) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. This value is used by the UART, RTC HAL module to compute the system frequency Value of the External oscillator in Hz

Definition at line 144 of file stm32g0xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_RCC_GetCECClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRTCClockFreq(), LL_RCC_GetUSARTClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSI_VALUE (32000UL)

Internal Low Speed oscillator (LSI) value.

LSI Typical Value in Hz

Definition at line 135 of file stm32g0xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_GetLPTIMClockFreq(), and LL_RCC_GetRTCClockFreq().

#define PREFETCH_ENABLE 1U

Definition at line 181 of file stm32g0xx_hal_conf.h.

#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL)

tick interrupt priority

Definition at line 179 of file stm32g0xx_hal_conf.h.

Referenced by HAL_Init().

#define USE_HAL_ADC_REGISTER_CALLBACKS 1u

This is the list of modules where register callback can be used.

Definition at line 72 of file stm32g0xx_hal_conf.h.

#define USE_HAL_CEC_REGISTER_CALLBACKS 1u

Definition at line 73 of file stm32g0xx_hal_conf.h.

#define USE_HAL_COMP_REGISTER_CALLBACKS 1u

Definition at line 74 of file stm32g0xx_hal_conf.h.

#define USE_HAL_CRYP_REGISTER_CALLBACKS 1u

Definition at line 75 of file stm32g0xx_hal_conf.h.

#define USE_HAL_CRYP_SUSPEND_RESUME 1U

Definition at line 195 of file stm32g0xx_hal_conf.h.

#define USE_HAL_DAC_REGISTER_CALLBACKS 1u

Definition at line 76 of file stm32g0xx_hal_conf.h.

#define USE_HAL_FDCAN_REGISTER_CALLBACKS 1u

Definition at line 77 of file stm32g0xx_hal_conf.h.

#define USE_HAL_HCD_REGISTER_CALLBACKS 1u

Definition at line 82 of file stm32g0xx_hal_conf.h.

#define USE_HAL_I2C_REGISTER_CALLBACKS 1u

Definition at line 78 of file stm32g0xx_hal_conf.h.

#define USE_HAL_I2S_REGISTER_CALLBACKS 1u

Definition at line 79 of file stm32g0xx_hal_conf.h.

#define USE_HAL_IRDA_REGISTER_CALLBACKS 1u

Definition at line 80 of file stm32g0xx_hal_conf.h.

#define USE_HAL_LPTIM_REGISTER_CALLBACKS 1u

Definition at line 81 of file stm32g0xx_hal_conf.h.

#define USE_HAL_PCD_REGISTER_CALLBACKS 1u

Definition at line 83 of file stm32g0xx_hal_conf.h.

#define USE_HAL_RNG_REGISTER_CALLBACKS 1u

Definition at line 84 of file stm32g0xx_hal_conf.h.

#define USE_HAL_RTC_REGISTER_CALLBACKS 1u

Definition at line 85 of file stm32g0xx_hal_conf.h.

#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1u

Definition at line 86 of file stm32g0xx_hal_conf.h.

#define USE_HAL_SMBUS_REGISTER_CALLBACKS 1u

Definition at line 87 of file stm32g0xx_hal_conf.h.

#define USE_HAL_SPI_REGISTER_CALLBACKS 1u

Definition at line 88 of file stm32g0xx_hal_conf.h.

#define USE_HAL_TIM_REGISTER_CALLBACKS 1u

Definition at line 89 of file stm32g0xx_hal_conf.h.

#define USE_HAL_UART_REGISTER_CALLBACKS 1u

Definition at line 90 of file stm32g0xx_hal_conf.h.

#define USE_HAL_USART_REGISTER_CALLBACKS 1u

Definition at line 91 of file stm32g0xx_hal_conf.h.

#define USE_HAL_WWDG_REGISTER_CALLBACKS 1u

Definition at line 92 of file stm32g0xx_hal_conf.h.

#define USE_RTOS 0U

Definition at line 180 of file stm32g0xx_hal_conf.h.

#define USE_SPI_CRC 1U

Definition at line 191 of file stm32g0xx_hal_conf.h.

#define VDD_VALUE (3300UL)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 178 of file stm32g0xx_hal_conf.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_adc.c File Reference

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stm32g0xx_ll_adc.c File Reference

ADC LL module driver. More...

#include "stm32g0xx_ll_adc.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__)
#define | IS_LL_ADC_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *pADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.

Detailed Description

ADC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_adc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g0xx_ll_adc.c.

Referenced by LL_ADC_CommonDeInit(), LL_ADC_CommonInit(), LL_ADC_DeInit(), LL_ADC_Init(), and LL_ADC_REG_Init().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_comp.c File Reference

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stm32g0xx_ll_comp.c File Reference

COMP LL module driver. More...

#include "stm32g0xx_ll_comp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

COMP LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_comp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g0xx_ll_comp.c.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_crc.c File Reference

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stm32g0xx_ll_crc.c File Reference

CRC LL module driver. More...

#include "stm32g0xx_ll_crc.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

CRC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_crc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g0xx_ll_crc.c.

Referenced by LL_CRC_DeInit().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dac.c File Reference

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stm32g0xx_ll_dac.c File Reference

DAC LL module driver. More...

#include "stm32g0xx_ll_dac.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)
#define | IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)

Functions

ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

DAC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_dac.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g0xx_ll_dac.c.

Referenced by LL_DAC_DeInit(), and LL_DAC_Init().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dma.c File Reference

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stm32g0xx_ll_dma.c File Reference

DMA LL module driver. More...

#include "stm32g0xx_ll_dma.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_MAX_REQ)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Functions

ErrorStatus | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
ErrorStatus | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Detailed Description

DMA LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_dma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g0xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_exti.c File Reference

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Defines | Functions
stm32g0xx_ll_exti.c File Reference

EXTI LL module driver. More...

#include "stm32g0xx_ll_exti.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

EXTI LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_exti.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 25 of file stm32g0xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_gpio.c File Reference

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stm32g0xx_ll_gpio.c File Reference

GPIO LL module driver. More...

#include "stm32g0xx_ll_gpio.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

GPIO LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_gpio.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g0xx_ll_gpio.c.

Referenced by LL_GPIO_DeInit(), and LL_GPIO_Init().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_i2c.c File Reference

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Defines | Functions
stm32g0xx_ll_i2c.c File Reference

I2C LL module driver. More...

#include "stm32g0xx_ll_i2c.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Functions

ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

I2C LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_i2c.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g0xx_ll_i2c.c.

Referenced by LL_I2C_DeInit(), and LL_I2C_Init().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_lptim.c File Reference

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Defines | Functions
stm32g0xx_ll_lptim.c File Reference

LPTIM LL module driver. More...

#include "stm32g0xx_ll_lptim.h"
#include "stm32g0xx_ll_bus.h"
#include "stm32g0xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LL_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__)

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Detailed Description

LPTIM LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_lptim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 29 of file stm32g0xx_ll_lptim.c.

Referenced by LL_LPTIM_DeInit(), LL_LPTIM_Disable(), and LL_LPTIM_Init().

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_lpuart.c File Reference

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Defines | Functions
stm32g0xx_ll_lpuart.c File Reference

LPUART LL module driver. More...

#include "stm32g0xx_ll_lpuart.h"
#include "stm32g0xx_ll_rcc.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_LPUART_PRESCALER(__VALUE__)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
#define | IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_LPUART_DeInit (const USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Detailed Description

LPUART LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_lpuart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g0xx_ll_lpuart.c.

Referenced by LL_LPUART_DeInit(), and LL_LPUART_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rcc.c File Reference

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Defines | Functions
stm32g0xx_ll_rcc.c File Reference

RCC LL module driver. More...

#include "stm32g0xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
#define | IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
#define | IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)

Functions

static uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
static uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
static uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
static uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.
static uint32_t | RCC_PLL_GetFreqDomain_ADC (void)
Return PLL clock frequency used for ADC domain.
static uint32_t | RCC_PLL_GetFreqDomain_I2S1 (void)
Return PLL clock frequency used for I2S1 domain.
static uint32_t | RCC_PLL_GetFreqDomain_I2S2 (void)
Return PLL clock frequency used for I2S2 domain.
static uint32_t | RCC_PLL_GetFreqDomain_USB (void)
Return PLL clock frequency used for USB domain.
static uint32_t | RCC_PLL_GetFreqDomain_FDCAN (void)
Return PLL clock frequency used for FDCAN domain.
static uint32_t | RCC_PLL_GetFreqDomain_RNG (void)
Return PLL clock frequency used for RNG domain.
static uint32_t | RCC_PLL_GetFreqDomain_TIM1 (void)
Return PLL clock frequency used for TIM1 domain.
static uint32_t | RCC_PLL_GetFreqDomain_TIM15 (void)
Return PLL clock frequency used for TIM15 domain.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetI2SClockFreq (uint32_t I2SxSource)
Return I2Sx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetTIMClockFreq (uint32_t TIMxSource)
Return TIMx clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CEC clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCANx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetRTCClockFreq (void)
Return RTC clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.

Detailed Description

RCC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_rcc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 24 of file stm32g0xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetCECClockFreq(), LL_RCC_GetFDCANClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetI2SClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetTIMClockFreq(), LL_RCC_GetUSARTClockFreq(), and LL_RCC_GetUSBClockFreq().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rng.c File Reference

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Defines | Functions
stm32g0xx_ll_rng.c File Reference

RNG LL module driver. More...

#include "stm32g0xx_ll_rng.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RNG_CED(__MODE__)

Functions

ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.

Detailed Description

RNG LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_rng.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g0xx_ll_rng.c.

Referenced by LL_RNG_DeInit(), and LL_RNG_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rtc.c File Reference

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Defines | Functions
stm32g0xx_ll_rtc.c File Reference

RTC LL module driver. More...

#include "stm32g0xx_ll_rtc.h"
#include "stm32g0xx_ll_cortex.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define | RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
#define | RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define | IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

RTC LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_rtc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g0xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_EnterInitMode(), LL_RTC_ExitInitMode(), LL_RTC_Init(), LL_RTC_TIME_Init(), and LL_RTC_WaitForSynchro().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_spi.c File Reference

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Defines | Functions
stm32g0xx_ll_spi.c File Reference

SPI LL module driver. More...

#include "stm32g0xx_ll_spi.h"
#include "stm32g0xx_ll_bus.h"
#include "stm32g0xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | SPI_CR1_CLEAR_MASK
#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
#define | I2S_I2SCFGR_CLEAR_MASK
#define | I2S_I2SPR_CLEAR_MASK 0x0002U
#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Detailed Description

SPI LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_spi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32g0xx_ll_spi.c.

Referenced by LL_I2S_ConfigPrescaler(), LL_I2S_Init(), LL_SPI_DeInit(), and LL_SPI_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_tim.c File Reference

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stm32g0xx_ll_tim.c File Reference

TIM LL module driver. More...

#include "stm32g0xx_ll_tim.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK_AFMODE(__VALUE__)
#define | IS_LL_TIM_BREAK2_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK2_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK2_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK2_AFMODE(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Detailed Description

TIM LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_tim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g0xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_BDTR_Init(), LL_TIM_DeInit(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_ucpd.c File Reference

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Defines | Functions
stm32g0xx_ll_ucpd.c File Reference

UCPD LL module driver. More...

#include "stm32g0xx_ll_ucpd.h"
#include "stm32g0xx_ll_bus.h"
#include "stm32g0xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_UCPD_DeInit (UCPD_TypeDef *UCPDx)
De-initialize the UCPD registers to their default reset values.
ErrorStatus | LL_UCPD_Init (UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
void | LL_UCPD_StructInit (LL_UCPD_InitTypeDef *UCPD_InitStruct)
Set each LL_UCPD_InitTypeDef field to default value.

Detailed Description

UCPD LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_ucpd.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32g0xx_ll_ucpd.c.

Referenced by LL_UCPD_DeInit(), and LL_UCPD_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_usart.c File Reference

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  • STM32G0xx_HAL_Driver
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Defines | Functions
stm32g0xx_ll_usart.c File Reference

USART LL module driver. More...

#include "stm32g0xx_ll_usart.h"
#include "stm32g0xx_ll_rcc.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_USART_PRESCALER(__VALUE__)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_USART_DeInit (const USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

USART LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_usart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32g0xx_ll_usart.c.

Referenced by LL_USART_ClockInit(), LL_USART_DeInit(), and LL_USART_Init().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_utils.c File Reference

  • File List
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  • STM32G0xx_HAL_Driver
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Defines | Functions
stm32g0xx_ll_utils.c File Reference

UTILS LL module driver. More...

#include "stm32g0xx_ll_utils.h"
#include "stm32g0xx_ll_rcc.h"
#include "stm32g0xx_ll_system.h"
#include "stm32g0xx_ll_pwr.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | UTILS_MAX_FREQUENCY 64000000U
#define | UTILS_PLLVCO_INPUT_MIN 4000000U
#define | UTILS_PLLVCO_INPUT_MAX 8000000U
#define | UTILS_PLLVCO_OUTPUT_MIN 64000000U
#define | UTILS_PLLVCO_OUTPUT_MAX 344000000U
#define | UTILS_HSE_FREQUENCY_MIN 4000000U
#define | UTILS_HSE_FREQUENCY_MAX 48000000U
#define | UTILS_SCALE1_LATENCY1_FREQ 24000000U
#define | UTILS_SCALE1_LATENCY2_FREQ 48000000U
#define | UTILS_SCALE1_LATENCY3_FREQ 64000000U
#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_HSI_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_LL_UTILS_PLLR_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.
ErrorStatus | LL_SetFlashLatency (uint32_t HCLKFrequency)
Update number of Flash wait states in line with new frequency and current voltage range.

Detailed Description

UTILS LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_utils.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32g0xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_GetPLLOutputFrequency().

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __ADC_PTR_REG_OFFSET : stm32g0xx_ll_adc.h
  • __COMP_PTR_REG_OFFSET : stm32g0xx_ll_comp.h
  • __DAC_PTR_REG_OFFSET : stm32g0xx_ll_dac.h
  • __HAL_ADC_CALC_DATA_TO_VOLTAGE : stm32g0xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE : stm32g0xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32g0xx_hal_adc.h
  • __HAL_ADC_CALC_VREFANALOG_VOLTAGE : stm32g0xx_hal_adc.h
  • __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32g0xx_hal_adc.h
  • __HAL_ADC_CHANNEL_TO_DECIMAL_NB : stm32g0xx_hal_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32g0xx_hal_adc.h
  • __HAL_ADC_COMMON_INSTANCE : stm32g0xx_hal_adc.h
  • __HAL_ADC_CONVERT_DATA_RESOLUTION : stm32g0xx_hal_adc.h
  • __HAL_ADC_DECIMAL_NB_TO_CHANNEL : stm32g0xx_hal_adc.h
  • __HAL_ADC_DIGITAL_SCALE : stm32g0xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32g0xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32g0xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32g0xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32g0xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL : stm32g0xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32g0xx_hal_adc.h
  • __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32g0xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32g0xx_hal_adc.h
  • __HAL_CEC_CLEAR_FLAG : stm32g0xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32g0xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32g0xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32g0xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32g0xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32g0xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32g0xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32g0xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32g0xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32g0xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32g0xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32g0xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32g0xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32g0xx_hal_cec.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GENERATE_SWIT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GET_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32g0xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32g0xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32g0xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32g0xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32g0xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32g0xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32g0xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32g0xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32g0xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32g0xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32g0xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32g0xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32g0xx_hal_crc.h
  • __HAL_CRYP_CLEAR_FLAG : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_DISABLE : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_GET_IT_SOURCE : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_RESET_HANDLE_STATE : stm32g0xx_hal_cryp.h
  • __HAL_DAC_CLEAR_FLAG : stm32g0xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32g0xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32g0xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32g0xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32g0xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32g0xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32g0xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32g0xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM2 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM14 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM15 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32g0xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32g0xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32g0xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32g0xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32g0xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32g0xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32g0xx_hal_dma.h
  • __HAL_FDCAN_CLEAR_FLAG : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_CLEAR_IT : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_DISABLE_IT : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_ENABLE_IT : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_GET_FLAG : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT_SOURCE : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_RESET_HANDLE_STATE : stm32g0xx_hal_fdcan.h
  • __HAL_FLASH_CLEAR_FLAG : stm32g0xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32g0xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32g0xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32g0xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32g0xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32g0xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32g0xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32g0xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32g0xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32g0xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32g0xx_hal_flash.h
  • __HAL_GET_PENDING_IT : stm32g0xx_hal.h
  • __HAL_GPIO_EXTI_CLEAR_FALLING_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_RISING_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FALLING_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_RISING_IT : stm32g0xx_hal_gpio.h
  • __HAL_HCD_CLEAR_FLAG : stm32g0xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32g0xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32g0xx_hal_hcd.h
  • __HAL_HCD_GET_CHDIR : stm32g0xx_hal_hcd.h
  • __HAL_HCD_GET_CHNUM : stm32g0xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32g0xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32g0xx_hal_hcd.h
  • __HAL_I2C_CLEAR_FLAG : stm32g0xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32g0xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32g0xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32g0xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32g0xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32g0xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32g0xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32g0xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32g0xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32g0xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32g0xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32g0xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32g0xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32g0xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32g0xx_hal_i2s.h
  • __HAL_I2S_FLUSH_RX_DR : stm32g0xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32g0xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32g0xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32g0xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32g0xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32g0xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32g0xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32g0xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32g0xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32g0xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32g0xx_hal_iwdg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT : stm32g0xx_hal_lptim.c
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT : stm32g0xx_hal_lptim.c
  • __HAL_PCD_CLEAR_FLAG : stm32g0xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32g0xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32g0xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32g0xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32g0xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32g0xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GET_RISING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_EVENT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_IT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_EVENT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_IT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_GENERATE_SWIT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_GET_RISING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_RCC_ADC_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AHB_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AHB_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_DAC1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_FDCAN_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FDCAN_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2S1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2S2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_PLLCLKOUT_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_RNG_DIV : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_TIM15_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_TIM1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2S1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_I2S2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_IOP_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_IOP_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_MCO2_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNGDIV_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_RTC_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SRAM_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SRAM_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32g0xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32g0xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32g0xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32g0xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32g0xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32g0xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32g0xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32g0xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32g0xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H : stm32g0xx_hal_rtc.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H : stm32g0xx_hal_rtc.h
  • __HAL_RTC_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_IS_CALENDAR_INITIALIZED : stm32g0xx_hal_rtc.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32g0xx_hal_rtc.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32g0xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32g0xx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32g0xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32g0xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32g0xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32g0xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32g0xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32g0xx_hal_spi.h
  • __HAL_SYSCFG_BREAK_DISABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_ECC_LOCK : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_ENABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK : stm32g0xx_hal.h
  • __HAL_SYSCFG_CLAMPINGDIODE_DISABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_CLAMPINGDIODE_ENABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_CLEAR_FLAG : stm32g0xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_GET_BOOT_MODE : stm32g0xx_hal.h
  • __HAL_SYSCFG_GET_IRDA_ENV_SELECTION : stm32g0xx_hal.h
  • __HAL_SYSCFG_GET_PENDING_IT : stm32g0xx_hal.h
  • __HAL_SYSCFG_GET_POLARITY : stm32g0xx_hal.h
  • __HAL_SYSCFG_IRDA_ENV_SELECTION : stm32g0xx_hal.h
  • __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION : stm32g0xx_hal.h
  • __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32g0xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32g0xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32g0xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32g0xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxFAST : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxFAST : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_UIFCPY : stm32g0xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32g0xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32g0xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32g0xx_hal_tim.h
  • __HAL_TIM_SELECT_CCDMAREQUEST : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32g0xx_hal_tim.h
  • __HAL_TIM_UIFREMAP_DISABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_UIFREMAP_ENABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32g0xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32g0xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32g0xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32g0xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32g0xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32g0xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32g0xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32g0xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32g0xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32g0xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32g0xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32g0xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32g0xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32g0xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32g0xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32g0xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32g0xx_hal_usart.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32g0xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32g0xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32g0xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32g0xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32g0xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32g0xx_ll_adc.h
  • __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW : stm32g0xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32g0xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32g0xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32g0xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32g0xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32g0xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32g0xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32g0xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32g0xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32g0xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32g0xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32g0xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32g0xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32g0xx_ll_adc.h
  • __LL_COMP_COMMON_INSTANCE : stm32g0xx_ll_comp.h
  • __LL_CRS_CALC_CALCULATE_RELOADVALUE : stm32g0xx_ll_crs.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32g0xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32g0xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32g0xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32g0xx_ll_dac.h
  • __LL_DMA_GET_CHANNEL : stm32g0xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32g0xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32g0xx_ll_dma.h
  • __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL : stm32g0xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32g0xx_ll_i2c.h
  • __LL_LPUART_DIV : stm32g0xx_ll_lpuart.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_HSI_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_ADC_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FDCAN_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_I2S1_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_I2S2_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_RNG_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_TIM15_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_TIM1_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_USB_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32g0xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32g0xx_ll_rtc.h
  • __LL_TIM_CALC_ARR : stm32g0xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32g0xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32g0xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32g0xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32g0xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32g0xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32g0xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32g0xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32g0xx_ll_usart.h
  • __STM32G0xx_HAL_VERSION : stm32g0xx_hal.c
  • __STM32G0xx_HAL_VERSION_MAIN : stm32g0xx_hal.c
  • __STM32G0xx_HAL_VERSION_RC : stm32g0xx_hal.c
  • __STM32G0xx_HAL_VERSION_SUB1 : stm32g0xx_hal.c
  • __STM32G0xx_HAL_VERSION_SUB2 : stm32g0xx_hal.c
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC_ANALOGWATCHDOG_1 : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_2 : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_3 : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32g0xx_hal_adc.h
  • ADC_AWD1_EVENT : stm32g0xx_hal_adc.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32g0xx_hal_adc.h
  • ADC_AWD2_EVENT : stm32g0xx_hal_adc.h
  • ADC_AWD3_EVENT : stm32g0xx_hal_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32g0xx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_AWD_EVENT : stm32g0xx_hal_adc.h
  • ADC_AWD_TR1_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_POS : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_SHIFT4 : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CALIBRATION_TIMEOUT : stm32g0xx_hal_adc_ex.c
  • ADC_CFGR1_AUTOOFF : stm32g0xx_hal_adc.h
  • ADC_CFGR1_AUTOWAIT : stm32g0xx_hal_adc.h
  • ADC_CFGR1_AWDSGL_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CFGR1_CONTINUOUS : stm32g0xx_hal_adc.h
  • ADC_CFGR1_DMACONTREQ : stm32g0xx_hal_adc.h
  • ADC_CFGR1_OVERRUN : stm32g0xx_hal_adc.h
  • ADC_CFGR1_REG_DISCCONTINUOUS : stm32g0xx_hal_adc.h
  • ADC_CFGR1_RES_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_0 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_CONF_RDY_TIMEOUT : stm32g0xx_hal_adc.c
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_SEQ : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32g0xx_hal_adc.h
  • ADC_CHSELR_CHSEL0_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL10_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL11_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL12_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL13_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL14_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL15_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL16_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL17_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL18_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL1_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL2_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL3_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL4_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL5_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL6_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL7_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL8_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL9_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_SQ2_TO_SQ8 : stm32g0xx_hal_adc.c
  • ADC_CLEAR_ERRORCODE : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32g0xx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32g0xx_hal_adc.h
  • ADC_ConversionStop() : stm32g0xx_hal_adc.c , stm32g0xx_hal_adc.h
  • ADC_CR_BITS_PROPERTY_RS : stm32g0xx_ll_adc.h
  • ADC_DATAALIGN_LEFT : stm32g0xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32g0xx_hal_adc.h
  • ADC_Disable() : stm32g0xx_hal_adc.c , stm32g0xx_hal_adc.h
  • ADC_DISABLE_TIMEOUT : stm32g0xx_hal_adc_ex.c , stm32g0xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32g0xx_hal_adc.c
  • ADC_DMAError() : stm32g0xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32g0xx_hal_adc.c
  • ADC_Enable() : stm32g0xx_hal_adc.c , stm32g0xx_hal_adc.h
  • ADC_ENABLE_TIMEOUT : stm32g0xx_hal_adc.c
  • ADC_EOC_SEQ_CONV : stm32g0xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32g0xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC4 : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32g0xx_hal_adc.h
  • ADC_FLAG_AWD1 : stm32g0xx_hal_adc.h
  • ADC_FLAG_AWD2 : stm32g0xx_hal_adc.h
  • ADC_FLAG_AWD3 : stm32g0xx_hal_adc.h
  • ADC_FLAG_CCRDY : stm32g0xx_hal_adc.h
  • ADC_FLAG_EOC : stm32g0xx_hal_adc.h
  • ADC_FLAG_EOS : stm32g0xx_hal_adc.h
  • ADC_FLAG_EOSMP : stm32g0xx_hal_adc.h
  • ADC_FLAG_OVR : stm32g0xx_hal_adc.h
  • ADC_FLAG_POSTCONV_ALL : stm32g0xx_hal_adc.h
  • ADC_FLAG_RDY : stm32g0xx_hal_adc.h
  • ADC_GET_RESOLUTION : stm32g0xx_hal_adc.h
  • ADC_HandleTypeDef : stm32g0xx_hal_adc.h
  • ADC_IS_INDEPENDENT : stm32g0xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32g0xx_hal_adc.h
  • ADC_IT_AWD1 : stm32g0xx_hal_adc.h
  • ADC_IT_AWD2 : stm32g0xx_hal_adc.h
  • ADC_IT_AWD3 : stm32g0xx_hal_adc.h
  • ADC_IT_CCRDY : stm32g0xx_hal_adc.h
  • ADC_IT_EOC : stm32g0xx_hal_adc.h
  • ADC_IT_EOS : stm32g0xx_hal_adc.h
  • ADC_IT_EOSMP : stm32g0xx_hal_adc.h
  • ADC_IT_OVR : stm32g0xx_hal_adc.h
  • ADC_IT_RDY : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_128 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_16 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_2 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_256 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_32 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_4 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_64 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_8 : stm32g0xx_hal_adc.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32g0xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32g0xx_hal_adc.h
  • ADC_OVR_EVENT : stm32g0xx_hal_adc.h
  • ADC_RANK_CHANNEL_NUMBER : stm32g0xx_hal_adc.h
  • ADC_RANK_NONE : stm32g0xx_hal_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32g0xx_ll_adc.h
  • ADC_REGULAR_GROUP : stm32g0xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32g0xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32g0xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32g0xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32g0xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_2 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_3 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_4 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_5 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_6 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_7 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_8 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_NONE : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_12CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_160CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_19CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_39CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_3CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_79CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_7CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLING_TIME_CH_MASK : stm32g0xx_ll_adc.h
  • ADC_SAMPLING_TIME_SMP_MASK : stm32g0xx_ll_adc.h
  • ADC_SAMPLING_TIME_SMP_SHIFT_MASK : stm32g0xx_ll_adc.h
  • ADC_SAMPLINGTIME_COMMON_1 : stm32g0xx_hal_adc.h
  • ADC_SAMPLINGTIME_COMMON_2 : stm32g0xx_hal_adc.h
  • ADC_SCAN_DIRECTION_BACKWARD : stm32g0xx_hal_adc.h
  • ADC_SCAN_DIRECTION_FORWARD : stm32g0xx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32g0xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32g0xx_hal_adc.h
  • ADC_SCAN_SEQ_FIXED : stm32g0xx_hal_adc.h
  • ADC_SCAN_SEQ_FIXED_BACKWARD : stm32g0xx_hal_adc.h
  • ADC_SCAN_SEQ_FIXED_INT : stm32g0xx_hal_adc.h
  • ADC_SCAN_SEQ_MODE : stm32g0xx_hal_adc.h
  • ADC_SMPR_SMP1_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_SMPR_SMP2_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_SMPR_SMPSEL0_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32g0xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32g0xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32g0xx_hal_adc.c
  • ADC_TIMEOUT_CCRDY_CPU_CYCLES : stm32g0xx_ll_adc.c
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32g0xx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32g0xx_ll_adc.c
  • ADC_TR1_HT1_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_TRIGGER_FREQ_HIGH : stm32g0xx_hal_adc.h
  • ADC_TRIGGER_FREQ_LOW : stm32g0xx_hal_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32g0xx_hal_adc.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32g0xx_hal_adc.h
  • assert_param : stm32g0xx_ll_lptim.c , stm32g0xx_ll_rng.c , stm32g0xx_ll_adc.c , stm32g0xx_ll_comp.c , stm32g0xx_ll_i2c.c , stm32g0xx_ll_gpio.c , stm32g0xx_ll_rtc.c , stm32g0xx_ll_crc.c , stm32g0xx_ll_ucpd.c , stm32g0xx_ll_dac.c , stm32g0xx_hal_conf.h , stm32g0xx_ll_exti.c , stm32g0xx_ll_rcc.c , stm32g0xx_ll_utils.c , stm32g0xx_ll_spi.c , stm32g0xx_ll_lpuart.c , stm32g0xx_ll_dma.c , stm32g0xx_ll_usart.c , stm32g0xx_ll_tim.c
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDCR_REG_INDEX : stm32g0xx_hal_rcc.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CEC_0_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32g0xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • CEC_CFGR_OAR_LSB_POS : stm32g0xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32g0xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32g0xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32g0xx_hal_cec.h
  • CEC_FLAG_BRE : stm32g0xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32g0xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32g0xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32g0xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32g0xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32g0xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32g0xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32g0xx_hal_cec.h
  • CEC_HandleTypeDef : stm32g0xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32g0xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32g0xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32g0xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32g0xx_hal_cec.h
  • CEC_IT_ARBLST : stm32g0xx_hal_cec.h
  • CEC_IT_BRE : stm32g0xx_hal_cec.h
  • CEC_IT_LBPE : stm32g0xx_hal_cec.h
  • CEC_IT_RXACKE : stm32g0xx_hal_cec.h
  • CEC_IT_RXBR : stm32g0xx_hal_cec.h
  • CEC_IT_RXEND : stm32g0xx_hal_cec.h
  • CEC_IT_RXOVR : stm32g0xx_hal_cec.h
  • CEC_IT_SBPE : stm32g0xx_hal_cec.h
  • CEC_IT_TXACKE : stm32g0xx_hal_cec.h
  • CEC_IT_TXBR : stm32g0xx_hal_cec.h
  • CEC_IT_TXEND : stm32g0xx_hal_cec.h
  • CEC_IT_TXERR : stm32g0xx_hal_cec.h
  • CEC_IT_TXUDR : stm32g0xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32g0xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_0 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_1 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_10 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_11 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_12 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_13 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_14 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_2 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_3 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_4 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_5 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_6 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_7 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_8 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_9 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_NONE : stm32g0xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32g0xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32g0xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32g0xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32g0xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32g0xx_hal_cec.h
  • CHANNEL_OFFSET_TAB : stm32g0xx_ll_dma.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • COMP_BLANKINGSRC_NONE : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC2 : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC4 : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5 : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3 : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3 : stm32g0xx_hal_comp.h
  • COMP_CLEAR_ERRORCODE : stm32g0xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32g0xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32g0xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32g0xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32g0xx_hal_comp.h
  • COMP_EXTI_IT : stm32g0xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32g0xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32g0xx_hal_comp.h
  • COMP_EXTI_LINE_COMP3 : stm32g0xx_hal_comp.h
  • COMP_EXTI_RISING : stm32g0xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32g0xx_hal_comp.h
  • COMP_HandleTypeDef : stm32g0xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32g0xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32g0xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32g0xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_IO3 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32g0xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32g0xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32g0xx_hal_comp.h
  • COMP_INPUT_PLUS_IO3 : stm32g0xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32g0xx_hal_comp.c
  • COMP_OUTPUT_LEVEL_HIGH : stm32g0xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32g0xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32g0xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32g0xx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32g0xx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32g0xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32g0xx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32g0xx_hal_comp.h
  • COMP_WINDOWMODE_COMP2 : stm32g0xx_hal_comp.h
  • COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON : stm32g0xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_BOTH : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_COMP1 : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_COMP2 : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_COMP3 : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_EACH_COMP : stm32g0xx_hal_comp.h
  • CR_REG_INDEX : stm32g0xx_hal_rcc.h
  • CRC_Handle_16() : stm32g0xx_hal_crc.c
  • CRC_Handle_8() : stm32g0xx_hal_crc.c
  • CRC_INPUTDATA_FORMAT_BYTES : stm32g0xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32g0xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32g0xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32g0xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32g0xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32g0xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32g0xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32g0xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32g0xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32g0xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32g0xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32g0xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32g0xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32g0xx_hal_crc.h
  • CRRCR_REG_INDEX : stm32g0xx_hal_rcc.h
  • CRYP_AES_CBC : stm32g0xx_hal_cryp.h
  • CRYP_AES_CCM : stm32g0xx_hal_cryp.h
  • CRYP_AES_CTR : stm32g0xx_hal_cryp.h
  • CRYP_AES_Decrypt() : stm32g0xx_hal_cryp.c
  • CRYP_AES_Decrypt_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_AES_Decrypt_IT() : stm32g0xx_hal_cryp.c
  • CRYP_AES_ECB : stm32g0xx_hal_cryp.h
  • CRYP_AES_Encrypt() : stm32g0xx_hal_cryp.c
  • CRYP_AES_Encrypt_IT() : stm32g0xx_hal_cryp.c
  • CRYP_AES_GCM_GMAC : stm32g0xx_hal_cryp.h
  • CRYP_AES_IT() : stm32g0xx_hal_cryp.c
  • CRYP_AES_ProcessData() : stm32g0xx_hal_cryp.c
  • CRYP_AESCCM_Process() : stm32g0xx_hal_cryp.c
  • CRYP_AESCCM_Process_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_AESCCM_Process_IT() : stm32g0xx_hal_cryp.c
  • CRYP_AESGCM_Process() : stm32g0xx_hal_cryp.c
  • CRYP_AESGCM_Process_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_AESGCM_Process_IT() : stm32g0xx_hal_cryp.c
  • CRYP_CCF_CLEAR : stm32g0xx_hal_cryp.h
  • CRYP_CCM_CTR0_0 : stm32g0xx_hal_cryp_ex.c
  • CRYP_CCM_CTR0_3 : stm32g0xx_hal_cryp_ex.c
  • CRYP_CCM_CTR1_0 : stm32g0xx_hal_cryp.c
  • CRYP_CCM_CTR1_1 : stm32g0xx_hal_cryp.c
  • CRYP_CCM_CTR1_2 : stm32g0xx_hal_cryp.c
  • CRYP_ClearCCFlagWhenHigh() : stm32g0xx_hal_cryp.c
  • CRYP_DATATYPE_16B : stm32g0xx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32g0xx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32g0xx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32g0xx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_BYTE : stm32g0xx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_WORD : stm32g0xx_hal_cryp.h
  • CRYP_DMAError() : stm32g0xx_hal_cryp.c
  • CRYP_DMAInCplt() : stm32g0xx_hal_cryp.c
  • CRYP_DMAOutCplt() : stm32g0xx_hal_cryp.c
  • CRYP_ERR_CLEAR : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_BUSY : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_CCF : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_MASK : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_RDERR : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_WRERR : stm32g0xx_hal_cryp.h
  • CRYP_GCMCCM_SetHeaderPhase() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_IT() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_IT() : stm32g0xx_hal_cryp.c
  • CRYP_HandleTypeDef : stm32g0xx_hal_cryp.h
  • CRYP_HEADERWIDTHUNIT_BYTE : stm32g0xx_hal_cryp.h
  • CRYP_HEADERWIDTHUNIT_WORD : stm32g0xx_hal_cryp.h
  • CRYP_IT_CCF : stm32g0xx_hal_cryp.h
  • CRYP_IT_CCFIE : stm32g0xx_hal_cryp.h
  • CRYP_IT_ERRIE : stm32g0xx_hal_cryp.h
  • CRYP_IT_RDERR : stm32g0xx_hal_cryp.h
  • CRYP_IT_WRERR : stm32g0xx_hal_cryp.h
  • CRYP_KEYIVCONFIG_ALWAYS : stm32g0xx_hal_cryp.h
  • CRYP_KEYIVCONFIG_ONCE : stm32g0xx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32g0xx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32g0xx_hal_cryp.h
  • CRYP_OPERATINGMODE_DECRYPT : stm32g0xx_hal_cryp_ex.c , stm32g0xx_hal_cryp.c
  • CRYP_OPERATINGMODE_ENCRYPT : stm32g0xx_hal_cryp_ex.c , stm32g0xx_hal_cryp.c
  • CRYP_OPERATINGMODE_KEYDERIVATION : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_PHASE_FINAL : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_PHASE_HEADER : stm32g0xx_hal_cryp_ex.c , stm32g0xx_hal_cryp.c
  • CRYP_PHASE_HEADER_DMA_FEED : stm32g0xx_hal_cryp.c
  • CRYP_PHASE_HEADER_SUSPENDED : stm32g0xx_hal_cryp.c
  • CRYP_PHASE_INIT : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_PHASE_PAYLOAD : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_PHASE_PAYLOAD_SUSPENDED : stm32g0xx_hal_cryp.c
  • CRYP_PHASE_PROCESS : stm32g0xx_hal_cryp.c
  • CRYP_PHASE_READY : stm32g0xx_hal_cryp.c
  • CRYP_PhaseProcessingResume() : stm32g0xx_hal_cryp.c
  • CRYP_Read_IVRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_Read_KeyRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_Read_SuspendRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_SET_PHASE : stm32g0xx_hal_cryp.c
  • CRYP_SetDMAConfig() : stm32g0xx_hal_cryp.c
  • CRYP_SetHeaderDMAConfig() : stm32g0xx_hal_cryp.c
  • CRYP_SetKey() : stm32g0xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMHEADERPHASE : stm32g0xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMINITPHASE : stm32g0xx_hal_cryp.c
  • CRYP_TIMEOUT_KEYPREPARATION : stm32g0xx_hal_cryp.c
  • CRYP_WaitOnCCFlag() : stm32g0xx_hal_cryp.c
  • CRYP_Write_IVRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_Write_KeyRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_Write_SuspendRegisters() : stm32g0xx_hal_cryp.c
  • CRYPEx_PHASE_FINAL : stm32g0xx_hal_cryp_ex.c
  • CRYPEx_PHASE_PROCESS : stm32g0xx_hal_cryp_ex.c
  • CSR_REG_INDEX : stm32g0xx_hal_rcc.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC_ALIGN_12B_L : stm32g0xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32g0xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32g0xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32g0xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32g0xx_hal_dac.h
  • DAC_CHIPCONNECT_DISABLE : stm32g0xx_hal_dac.h
  • DAC_CHIPCONNECT_ENABLE : stm32g0xx_hal_dac.h
  • DAC_CR_CH1_BITOFFSET : stm32g0xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32g0xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32g0xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32g0xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32g0xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32g0xx_ll_dac.h
  • DAC_DMAConvCpltCh1() : stm32g0xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32g0xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32g0xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32g0xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32g0xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32g0xx_hal_dac_ex.c
  • DAC_FLAG_DMAUDR1 : stm32g0xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32g0xx_hal_dac.h
  • DAC_HandleTypeDef : stm32g0xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32g0xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32g0xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32g0xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32g0xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32g0xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 : stm32g0xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 : stm32g0xx_ll_dac.h
  • DAC_REG_SHSR1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_SHSR2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 : stm32g0xx_ll_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32g0xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32g0xx_hal_dac.h
  • DAC_SWTR_CH1 : stm32g0xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32g0xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32g0xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_LPTIM1_OUT : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_LPTIM2_OUT : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T15_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T1_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T3_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32g0xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32g0xx_hal_dac.h
  • DEFAULT_CRC32_POLY : stm32g0xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32g0xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32g0xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32g0xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32g0xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32g0xx_hal_crc.h
  • DLCtoBytes : stm32g0xx_hal_fdcan.c
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32g0xx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32g0xx_hal_dma.c
  • DMA_CIRCULAR : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI1 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI2 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI3 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI4 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI5 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI6 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI7 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT7 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC7 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE7 : stm32g0xx_hal_dma.h
  • DMA_HandleTypeDef : stm32g0xx_hal_dma.h
  • DMA_IT_HT : stm32g0xx_hal_dma.h
  • DMA_IT_TC : stm32g0xx_hal_dma.h
  • DMA_IT_TE : stm32g0xx_hal_dma.h
  • DMA_MAX_REQUEST : stm32g0xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32g0xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32g0xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32g0xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32g0xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32g0xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32g0xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32g0xx_hal_dma.h
  • DMA_NORMAL : stm32g0xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32g0xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32g0xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32g0xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32g0xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32g0xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32g0xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32g0xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32g0xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32g0xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32g0xx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_AES_IN : stm32g0xx_hal_dma.h
  • DMA_REQUEST_AES_OUT : stm32g0xx_hal_dma.h
  • DMA_REQUEST_DAC1_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_DAC1_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_LPUART1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_LPUART1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_LPUART2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_LPUART2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI3_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI3_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM15_TRIG_COM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM15_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM16_COM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM17_COM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG_COM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_TRIG : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH4 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_TRIG : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH4 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_TRIG : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM6_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM7_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_UCPD1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_UCPD1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_UCPD2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_UCPD2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART3_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART3_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART4_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART4_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART5_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART5_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART6_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART6_TX : stm32g0xx_hal_dma.h
  • DMA_SetConfig() : stm32g0xx_hal_dma.c
  • DMAMUX_CCR_SIZE : stm32g0xx_ll_dmamux.h
  • DMAMUX_RGCR_SIZE : stm32g0xx_ll_dmamux.h
  • DT_DELAY_1 : stm32g0xx_ll_tim.h
  • DT_DELAY_2 : stm32g0xx_ll_tim.h
  • DT_DELAY_3 : stm32g0xx_ll_tim.h
  • DT_DELAY_4 : stm32g0xx_ll_tim.h
  • DT_RANGE_1 : stm32g0xx_ll_tim.h
  • DT_RANGE_2 : stm32g0xx_ll_tim.h
  • DT_RANGE_3 : stm32g0xx_ll_tim.h
  • DT_RANGE_4 : stm32g0xx_ll_tim.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
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  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • EXTERNAL_I2S1_CLOCK_VALUE : stm32g0xx_hal_conf.h
  • EXTERNAL_I2S2_CLOCK_VALUE : stm32g0xx_hal_conf.h
  • EXTI_CallbackIDTypeDef : stm32g0xx_hal_exti.h
  • EXTI_CONFIG : stm32g0xx_hal_exti.h
  • EXTI_CONFIG_OFFSET : stm32g0xx_hal_exti.c
  • EXTI_DIRECT : stm32g0xx_hal_exti.h
  • EXTI_EVT : stm32g0xx_hal_gpio.h
  • EXTI_GPIO : stm32g0xx_hal_exti.h
  • EXTI_GPIOA : stm32g0xx_hal_exti.h
  • EXTI_GPIOB : stm32g0xx_hal_exti.h
  • EXTI_GPIOC : stm32g0xx_hal_exti.h
  • EXTI_GPIOD : stm32g0xx_hal_exti.h
  • EXTI_GPIOE : stm32g0xx_hal_exti.h
  • EXTI_GPIOF : stm32g0xx_hal_exti.h
  • EXTI_IT : stm32g0xx_hal_gpio.h
  • EXTI_LINE_0 : stm32g0xx_hal_exti.h
  • EXTI_LINE_1 : stm32g0xx_hal_exti.h
  • EXTI_LINE_10 : stm32g0xx_hal_exti.h
  • EXTI_LINE_11 : stm32g0xx_hal_exti.h
  • EXTI_LINE_12 : stm32g0xx_hal_exti.h
  • EXTI_LINE_13 : stm32g0xx_hal_exti.h
  • EXTI_LINE_14 : stm32g0xx_hal_exti.h
  • EXTI_LINE_15 : stm32g0xx_hal_exti.h
  • EXTI_LINE_16 : stm32g0xx_hal_exti.h
  • EXTI_LINE_17 : stm32g0xx_hal_exti.h
  • EXTI_LINE_18 : stm32g0xx_hal_exti.h
  • EXTI_LINE_19 : stm32g0xx_hal_exti.h
  • EXTI_LINE_2 : stm32g0xx_hal_exti.h
  • EXTI_LINE_20 : stm32g0xx_hal_exti.h
  • EXTI_LINE_21 : stm32g0xx_hal_exti.h
  • EXTI_LINE_22 : stm32g0xx_hal_exti.h
  • EXTI_LINE_23 : stm32g0xx_hal_exti.h
  • EXTI_LINE_24 : stm32g0xx_hal_exti.h
  • EXTI_LINE_25 : stm32g0xx_hal_exti.h
  • EXTI_LINE_26 : stm32g0xx_hal_exti.h
  • EXTI_LINE_27 : stm32g0xx_hal_exti.h
  • EXTI_LINE_28 : stm32g0xx_hal_exti.h
  • EXTI_LINE_29 : stm32g0xx_hal_exti.h
  • EXTI_LINE_3 : stm32g0xx_hal_exti.h
  • EXTI_LINE_30 : stm32g0xx_hal_exti.h
  • EXTI_LINE_31 : stm32g0xx_hal_exti.h
  • EXTI_LINE_32 : stm32g0xx_hal_exti.h
  • EXTI_LINE_33 : stm32g0xx_hal_exti.h
  • EXTI_LINE_34 : stm32g0xx_hal_exti.h
  • EXTI_LINE_35 : stm32g0xx_hal_exti.h
  • EXTI_LINE_36 : stm32g0xx_hal_exti.h
  • EXTI_LINE_4 : stm32g0xx_hal_exti.h
  • EXTI_LINE_5 : stm32g0xx_hal_exti.h
  • EXTI_LINE_6 : stm32g0xx_hal_exti.h
  • EXTI_LINE_7 : stm32g0xx_hal_exti.h
  • EXTI_LINE_8 : stm32g0xx_hal_exti.h
  • EXTI_LINE_9 : stm32g0xx_hal_exti.h
  • EXTI_LINE_NB : stm32g0xx_hal_exti.h
  • EXTI_MODE : stm32g0xx_hal_gpio.h
  • EXTI_MODE_EVENT : stm32g0xx_hal_exti.h
  • EXTI_MODE_INTERRUPT : stm32g0xx_hal_exti.h
  • EXTI_MODE_MASK : stm32g0xx_hal_exti.h
  • EXTI_MODE_NONE : stm32g0xx_hal_exti.h
  • EXTI_MODE_OFFSET : stm32g0xx_hal_exti.c
  • EXTI_MODE_Pos : stm32g0xx_hal_gpio.h
  • EXTI_PIN_MASK : stm32g0xx_hal_exti.h
  • EXTI_PROPERTY_MASK : stm32g0xx_hal_exti.h
  • EXTI_PROPERTY_SHIFT : stm32g0xx_hal_exti.h
  • EXTI_REG1 : stm32g0xx_hal_exti.h
  • EXTI_REG2 : stm32g0xx_hal_exti.h
  • EXTI_REG_MASK : stm32g0xx_hal_exti.h
  • EXTI_REG_SHIFT : stm32g0xx_hal_exti.h
  • EXTI_RESERVED : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_FALLING : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_MASK : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_NONE : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_RISING : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_RISING_FALLING : stm32g0xx_hal_exti.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FDCAN_ACCEPT_IN_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_ACCEPT_IN_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_BRS_OFF : stm32g0xx_hal_fdcan.h
  • FDCAN_BRS_ON : stm32g0xx_hal_fdcan.h
  • FDCAN_CalcultateRamBlockAddresses() : stm32g0xx_hal_fdcan.c
  • FDCAN_CHECK_FLAG : stm32g0xx_hal_fdcan.h
  • FDCAN_CHECK_IT_SOURCE : stm32g0xx_hal_fdcan.h
  • FDCAN_CLASSIC_CAN : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV1 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV10 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV12 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV14 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV16 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV18 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV2 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV20 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV22 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV24 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV26 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV28 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV30 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV4 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV6 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV8 : stm32g0xx_hal_fdcan.h
  • FDCAN_COM_STATE_IDLE : stm32g0xx_hal_fdcan.h
  • FDCAN_COM_STATE_RX : stm32g0xx_hal_fdcan.h
  • FDCAN_COM_STATE_SYNC : stm32g0xx_hal_fdcan.h
  • FDCAN_COM_STATE_TX : stm32g0xx_hal_fdcan.h
  • FDCAN_CopyMessageToRAM() : stm32g0xx_hal_fdcan.c
  • FDCAN_DATA_FRAME : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_0 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_1 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_12 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_16 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_2 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_20 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_24 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_3 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_32 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_4 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_48 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_5 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_6 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_64 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_7 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_8 : stm32g0xx_hal_fdcan.h
  • FDCAN_ELEMENT_MASK_ANMF : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_BRS : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_DLC : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EFC : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ESI : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ET : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EXTID : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FDF : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FIDX : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_MM : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_RTR : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_STDID : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_TS : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_XTD : stm32g0xx_hal_fdcan.c
  • FDCAN_ERROR_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_ERROR_STATUS_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_ESI_ACTIVE : stm32g0xx_hal_fdcan.h
  • FDCAN_ESI_PASSIVE : stm32g0xx_hal_fdcan.h
  • FDCAN_EXTENDED_ID : stm32g0xx_hal_fdcan.h
  • FDCAN_FD_CAN : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_DISABLE : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_DUAL : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_HP : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_MASK : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE_NO_EIDM : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_REJECT : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_REMOTE : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0_HP : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1_HP : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_ARB_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_BUS_OFF : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_DATA_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_LOGGING_OVERFLOW : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_PASSIVE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_WARNING : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_ACCESS_FAILURE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_WATCHDOG : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RESERVED_ADDRESS_ACCESS : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_HIGH_PRIORITY_MSG : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TIMEOUT_OCCURRED : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TIMESTAMP_WRAPAROUND : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_ABORT_COMPLETE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_COMPLETE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_FIFO_EMPTY : stm32g0xx_hal_fdcan.h
  • FDCAN_FRAME_CLASSIC : stm32g0xx_hal_fdcan.h
  • FDCAN_FRAME_FD_BRS : stm32g0xx_hal_fdcan.h
  • FDCAN_FRAME_FD_NO_BRS : stm32g0xx_hal_fdcan.h
  • FDCAN_HandleTypeDef : stm32g0xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_MSG_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_NO_FIFO : stm32g0xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_ILS_MASK : stm32g0xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE0 : stm32g0xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE1 : stm32g0xx_hal_fdcan.h
  • FDCAN_IR_MASK : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_ARB_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_BUS_OFF : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_DATA_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_ERROR_LOGGING_OVERFLOW : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_ERROR_PASSIVE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_ERROR_WARNING : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_BIT_LINE_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_MISC : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_SMSG : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_TX_FIFO_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_BIT_LINE_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_MISC : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_SMSG : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_TX_FIFO_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RAM_ACCESS_FAILURE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RAM_WATCHDOG : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RESERVED_ADDRESS_ACCESS : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_MESSAGE_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_NEW_MESSAGE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_MESSAGE_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_NEW_MESSAGE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_HIGH_PRIORITY_MSG : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TIMEOUT_OCCURRED : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TIMESTAMP_WRAPAROUND : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_ABORT_COMPLETE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_COMPLETE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_ELT_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_NEW_DATA : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_FIFO_EMPTY : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_BUS_MONITORING : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_EXTERNAL_LOOPBACK : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_INTERNAL_LOOPBACK : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_NORMAL : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_RESTRICTED_OPERATION : stm32g0xx_hal_fdcan.h
  • FDCAN_NO_TX_EVENTS : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_ACK : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT0 : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT1 : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_CRC : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_FORM : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NO_CHANGE : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NONE : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_STUFF : stm32g0xx_hal_fdcan.h
  • FDCAN_REJECT : stm32g0xx_hal_fdcan.h
  • FDCAN_REJECT_REMOTE : stm32g0xx_hal_fdcan.h
  • FDCAN_REMOTE_FRAME : stm32g0xx_hal_fdcan.h
  • FDCAN_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_RX_FIFO0_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_RX_FIFO1_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_RX_FIFO_BLOCKING : stm32g0xx_hal_fdcan.h
  • FDCAN_RX_FIFO_OVERWRITE : stm32g0xx_hal_fdcan.h
  • FDCAN_STANDARD_ID : stm32g0xx_hal_fdcan.h
  • FDCAN_STORE_TX_EVENTS : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_CONTINUOUS : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_TX_EVENT_FIFO : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_VALUE : stm32g0xx_hal_fdcan.c
  • FDCAN_TIMESTAMP_EXTERNAL : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_INTERNAL : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_1 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_10 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_11 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_12 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_13 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_14 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_15 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_16 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_2 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_3 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_4 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_5 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_6 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_7 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_8 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_9 : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_BUFFER0 : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_BUFFER1 : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_BUFFER2 : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_EVENT : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_EVENT_FIFO_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_TX_FIFO_OPERATION : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_IN_SPITE_OF_ABORT : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_QUEUE_OPERATION : stm32g0xx_hal_fdcan.h
  • FLASH_BANK_1 : stm32g0xx_hal_flash.h
  • FLASH_BANK_2 : stm32g0xx_hal_flash.h
  • FLASH_BANK_NB : stm32g0xx_hal_flash.h
  • FLASH_BANK_SIZE : stm32g0xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32g0xx_hal_flash.h
  • FLASH_FLAG_BSY1 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_BSY2 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_CFGBSY : stm32g0xx_hal_flash.h
  • FLASH_FLAG_CR_ID : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCC : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCC1 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCC2 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCD : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCD1 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCD2 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCR1_ID : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCR2_ID : stm32g0xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32g0xx_hal_flash.h
  • FLASH_FLAG_FASTERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_MISERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_OPTVERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_PESD : stm32g0xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_PROGERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_REG_POS : stm32g0xx_hal_flash.h
  • FLASH_FLAG_SIZERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_SR_ID : stm32g0xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32g0xx_hal_flash.h
  • FLASH_FlushCaches() : stm32g0xx_hal_flash_ex.c
  • FLASH_IT_ECCC : stm32g0xx_hal_flash.h
  • FLASH_IT_ECCC1 : stm32g0xx_hal_flash.h
  • FLASH_IT_ECCC2 : stm32g0xx_hal_flash.h
  • FLASH_IT_EOP : stm32g0xx_hal_flash.h
  • FLASH_IT_OPERR : stm32g0xx_hal_flash.h
  • FLASH_IT_RDERR : stm32g0xx_hal_flash.h
  • FLASH_KEY1 : stm32g0xx_hal_flash.h
  • FLASH_KEY2 : stm32g0xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32g0xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32g0xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32g0xx_hal_flash.h
  • FLASH_MassErase() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP1A() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP1B() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP2A() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP2B() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetSecMem() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_OptrConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_PCROP1AConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_PCROP1BConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_PCROP2AConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_PCROP2BConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_SecMemConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_WRPConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OPTKEY1 : stm32g0xx_hal_flash.h
  • FLASH_OPTKEY2 : stm32g0xx_hal_flash.h
  • FLASH_PAGE_NB : stm32g0xx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32g0xx_hal_flash.h
  • FLASH_PageErase() : stm32g0xx_hal_flash_ex.c , stm32g0xx_hal_flash_ex.h
  • FLASH_PCROP_GRANULARITY : stm32g0xx_hal_flash_ex.h
  • FLASH_PCROP_GRANULARITY_OFFSET : stm32g0xx_hal_flash_ex.h
  • FLASH_PROG_EMPTY : stm32g0xx_hal_flash_ex.h
  • FLASH_PROG_NOT_EMPTY : stm32g0xx_hal_flash_ex.h
  • FLASH_Program_DoubleWord() : stm32g0xx_hal_flash.c
  • FLASH_Program_Fast() : stm32g0xx_hal_flash.c
  • FLASH_SALES_TYPE : stm32g0xx_hal_flash.h
  • FLASH_SALES_TYPE_0 : stm32g0xx_hal_flash.h
  • FLASH_SALES_TYPE_1 : stm32g0xx_hal_flash.h
  • FLASH_SALES_TYPE_Pos : stm32g0xx_hal_flash.h
  • FLASH_SALES_VALUE : stm32g0xx_hal_flash.h
  • FLASH_SIZE_DATA_REGISTER : stm32g0xx_hal_flash.h
  • FLASH_SR_CLEAR : stm32g0xx_hal_flash.h
  • FLASH_SR_ERRORS : stm32g0xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32g0xx_hal_flash.h
  • FLASH_TYPEERASE_MASS : stm32g0xx_hal_flash.h
  • FLASH_TYPEERASE_PAGES : stm32g0xx_hal_flash.h
  • FLASH_TYPENONE : stm32g0xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32g0xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST : stm32g0xx_hal_flash.h
  • FLASH_WaitForLastOperation() : stm32g0xx_hal_flash.c , stm32g0xx_hal_flash.h
  • FLASHSIZE_BASE_ADDRESS : stm32g0xx_ll_utils.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_AF0_CEC : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_CRS : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_EVENTOUT : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_IR : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_LPTIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_OSC : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_OSC32 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_SPI1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_SPI2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_TIM14 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_TIM15 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_TIM16 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_TIM17 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_UCPD1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_UCPD2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_USART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_USART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_USART3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_USART4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF10_LPUART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_CEC : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_EVENTOUT : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_IR : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_LPUART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_LPUART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_OSC : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_SPI1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_SPI2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_TIM3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_UCPD1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_UCPD2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_USART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_USART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_USART4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_LPTIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_LPTIM2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM14 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM16 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM17 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_USB : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_FDCAN1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_FDCAN2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_LPUART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_MCO2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_USART5 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_USART6 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_CRS : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_SPI2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_SPI3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_TIM14 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_TIM15 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_UCPD1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_UCPD2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_USART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_USART3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_USART4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_USART6 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_LPTIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_LPTIM2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_TIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_TIM15 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_TIM16 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_TIM17 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_USART3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_I2C1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_I2C2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_I2C3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_LPUART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_UCPD1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_UCPD2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_USB : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF7_COMP1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF7_COMP2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF7_COMP3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF7_EVENTOUT : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF8_I2C2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF8_USART5 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF8_USART6 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF9_I2C3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF9_SPI3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF9_TIM4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32g0xx_hal_gpio_ex.h
  • GPIO_MODE : stm32g0xx_hal_gpio.h
  • GPIO_MODE_AF_OD : stm32g0xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32g0xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32g0xx_hal_gpio.h
  • GPIO_MODE_EVT_FALLING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32g0xx_hal_gpio.h
  • GPIO_MODE_IT_FALLING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32g0xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32g0xx_hal_gpio.h
  • GPIO_MODE_Pos : stm32g0xx_hal_gpio.h
  • GPIO_NOPULL : stm32g0xx_hal_gpio.h
  • GPIO_NUMBER : stm32g0xx_hal_gpio.c
  • GPIO_PIN_0 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_1 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_10 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_11 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_12 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_13 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_14 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_15 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_2 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_3 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_4 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_5 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_6 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_7 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_8 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_9 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_All : stm32g0xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32g0xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32g0xx_hal_gpio.h
  • GPIO_PIN_SET : stm32g0xx_hal_gpio.h
  • GPIO_PinState : stm32g0xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32g0xx_hal_gpio.h
  • GPIO_PULLUP : stm32g0xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32g0xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32g0xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32g0xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32g0xx_hal_gpio.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAC_SET_CH_TX_SETUP : stm32g0xx_hal_hcd.h
  • HAL_ADC_AnalogWDGConfig() : stm32g0xx_hal_adc.c
  • HAL_ADC_CallbackIDTypeDef : stm32g0xx_hal_adc.h
  • HAL_ADC_ConfigChannel() : stm32g0xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_CONVERSION_HALF_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_ConvHalfCpltCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32g0xx_hal_adc.c
  • HAL_ADC_END_OF_SAMPLING_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_DMA : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_INVALID_CALLBACK : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32g0xx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_GetError() : stm32g0xx_hal_adc.c
  • HAL_ADC_GetState() : stm32g0xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32g0xx_hal_adc.c
  • HAL_ADC_Init() : stm32g0xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32g0xx_hal_adc.c
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_LevelOutOfWindowCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32g0xx_hal_adc.c
  • HAL_ADC_MSPDEINIT_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_MspInit() : stm32g0xx_hal_adc.c
  • HAL_ADC_MSPINIT_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_PollForConversion() : stm32g0xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32g0xx_hal_adc.c
  • HAL_ADC_RegisterCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_Start() : stm32g0xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32g0xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32g0xx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32g0xx_hal_adc.h
  • HAL_ADC_Stop() : stm32g0xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32g0xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32g0xx_hal_adc.c
  • HAL_ADC_UnRegisterCallback() : stm32g0xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_ChannelConfigReadyCallback() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32g0xx_hal_adc_ex.c , stm32g0xx_hal_adc_ex.h
  • HAL_ADCEx_EndOfSamplingCallback() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32g0xx_hal_adc_ex.c
  • HAL_CEC_CallbackIDTypeDef : stm32g0xx_hal_cec.h
  • HAL_CEC_ChangeRxBuffer() : stm32g0xx_hal_cec.c
  • HAL_CEC_DeInit() : stm32g0xx_hal_cec.c
  • HAL_CEC_ERROR_ARBLST : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_INVALID_CALLBACK : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32g0xx_hal_cec.h
  • HAL_CEC_ErrorCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_GetError() : stm32g0xx_hal_cec.c
  • HAL_CEC_GetLastReceivedFrameSize() : stm32g0xx_hal_cec.c
  • HAL_CEC_GetState() : stm32g0xx_hal_cec.c
  • HAL_CEC_Init() : stm32g0xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32g0xx_hal_cec.c
  • HAL_CEC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_CEC_MspDeInit() : stm32g0xx_hal_cec.c
  • HAL_CEC_MSPDEINIT_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_MspInit() : stm32g0xx_hal_cec.c
  • HAL_CEC_MSPINIT_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_RegisterCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_RegisterRxCpltCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_RX_CPLT_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_RxCpltCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_SetDeviceAddress() : stm32g0xx_hal_cec.c
  • HAL_CEC_STATE_BUSY : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX_TX : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32g0xx_hal_cec.h
  • HAL_CEC_StateTypeDef : stm32g0xx_hal_cec.h
  • HAL_CEC_Transmit_IT() : stm32g0xx_hal_cec.c
  • HAL_CEC_TX_CPLT_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_TxCpltCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_UnRegisterCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_UnRegisterRxCpltCallback() : stm32g0xx_hal_cec.c
  • HAL_COMP_CallbackIDTypeDef : stm32g0xx_hal_comp.h
  • HAL_COMP_DeInit() : stm32g0xx_hal_comp.c
  • HAL_COMP_ERROR_INVALID_CALLBACK : stm32g0xx_hal_comp.h
  • HAL_COMP_ERROR_NONE : stm32g0xx_hal_comp.h
  • HAL_COMP_GetError() : stm32g0xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32g0xx_hal_comp.c
  • HAL_COMP_GetState() : stm32g0xx_hal_comp.c
  • HAL_COMP_Init() : stm32g0xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32g0xx_hal_comp.c
  • HAL_COMP_Lock() : stm32g0xx_hal_comp.c
  • HAL_COMP_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_COMP_MspDeInit() : stm32g0xx_hal_comp.c
  • HAL_COMP_MSPDEINIT_CB_ID : stm32g0xx_hal_comp.h
  • HAL_COMP_MspInit() : stm32g0xx_hal_comp.c
  • HAL_COMP_MSPINIT_CB_ID : stm32g0xx_hal_comp.h
  • HAL_COMP_RegisterCallback() : stm32g0xx_hal_comp.c
  • HAL_COMP_Start() : stm32g0xx_hal_comp.c
  • HAL_COMP_STATE_BUSY : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32g0xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32g0xx_hal_comp.h
  • HAL_COMP_Stop() : stm32g0xx_hal_comp.c
  • HAL_COMP_TRIGGER_CB_ID : stm32g0xx_hal_comp.h
  • HAL_COMP_TriggerCallback() : stm32g0xx_hal_comp.c
  • HAL_COMP_UnRegisterCallback() : stm32g0xx_hal_comp.c
  • HAL_CORTEX_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32g0xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32g0xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32g0xx_hal_crc.c
  • HAL_CRC_GetState() : stm32g0xx_hal_crc.c
  • HAL_CRC_Init() : stm32g0xx_hal_crc.c
  • HAL_CRC_LENGTH_16B : stm32g0xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32g0xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32g0xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32g0xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32g0xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32g0xx_hal_crc.c
  • HAL_CRC_STATE_BUSY : stm32g0xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32g0xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32g0xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32g0xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32g0xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32g0xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32g0xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32g0xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32g0xx_hal_crc_ex.c
  • HAL_CRYP_CallbackIDTypeDef : stm32g0xx_hal_cryp.h
  • HAL_CRYP_Decrypt() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Decrypt_DMA() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Decrypt_IT() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Encrypt() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Encrypt_DMA() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Encrypt_IT() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_BUSY : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_DMA : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_INVALID_CALLBACK : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_NOT_SUPPORTED : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_READ : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_TIMEOUT : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_WRITE : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ErrorCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_GetConfig() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Init() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_INPUT_COMPLETE_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_IRQHandler() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_CRYP_MspDeInit() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_MSPDEINIT_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_MspInit() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_MSPINIT_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_OutCpltCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ProcessSuspend() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_RegisterCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Resume() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_SetConfig() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_STATE_BUSY : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATE_SUSPENDED : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATETypeDef : stm32g0xx_hal_cryp.h
  • HAL_CRYP_SUSPEND : stm32g0xx_hal_cryp.h
  • HAL_CRYP_Suspend() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_SUSPEND_NONE : stm32g0xx_hal_cryp.h
  • HAL_CRYP_UnRegisterCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYPEx_AESCCM_GenerateAuthTAG() : stm32g0xx_hal_cryp_ex.c
  • HAL_CRYPEx_AESGCM_GenerateAuthTAG() : stm32g0xx_hal_cryp_ex.c
  • HAL_CRYPEx_DisableAutoKeyDerivation() : stm32g0xx_hal_cryp_ex.c
  • HAL_CRYPEx_EnableAutoKeyDerivation() : stm32g0xx_hal_cryp_ex.c
  • HAL_DAC_ALL_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CallbackIDTypeDef : stm32g0xx_hal_dac.h
  • HAL_DAC_CH1_COMPLETE_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH1_ERROR_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH1_UNDERRUN_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH2_COMPLETE_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH2_ERROR_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH2_UNDERRUN_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_ConfigChannel() : stm32g0xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32g0xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32g0xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32g0xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32g0xx_hal_dac.c
  • HAL_DAC_ERROR_DMA : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_INVALID_CALLBACK : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32g0xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32g0xx_hal_dac.c
  • HAL_DAC_GetError() : stm32g0xx_hal_dac.c
  • HAL_DAC_GetState() : stm32g0xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32g0xx_hal_dac.c
  • HAL_DAC_Init() : stm32g0xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32g0xx_hal_dac.c
  • HAL_DAC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_DAC_MspDeInit() : stm32g0xx_hal_dac.c
  • HAL_DAC_MSPDEINIT_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_MspInit() : stm32g0xx_hal_dac.c
  • HAL_DAC_MSPINIT_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_RegisterCallback() : stm32g0xx_hal_dac.c , stm32g0xx_hal_dac.h
  • HAL_DAC_SetValue() : stm32g0xx_hal_dac.c
  • HAL_DAC_Start() : stm32g0xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32g0xx_hal_dac.c
  • HAL_DAC_STATE_BUSY : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32g0xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32g0xx_hal_dac.h
  • HAL_DAC_Stop() : stm32g0xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32g0xx_hal_dac.c
  • HAL_DAC_UnRegisterCallback() : stm32g0xx_hal_dac.c , stm32g0xx_hal_dac.h
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32g0xx_hal_dac_ex.c , stm32g0xx_hal_dac_ex.h
  • HAL_DACEx_DualSetValue() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_DualStart() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_DualStop() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32g0xx_hal_dac_ex.c , stm32g0xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32g0xx_hal_dac_ex.c , stm32g0xx_hal_dac_ex.h
  • HAL_DACEx_SetUserTrimming() : stm32g0xx_hal_dac_ex.c , stm32g0xx_hal_dac_ex.h
  • HAL_DACEx_TriangleWaveGenerate() : stm32g0xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32g0xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32g0xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32g0xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32g0xx_hal.c
  • HAL_DeInit() : stm32g0xx_hal.c
  • HAL_Delay() : stm32g0xx_hal.c
  • HAL_DMA_Abort() : stm32g0xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32g0xx_hal_dma.c
  • HAL_DMA_BURST_STATE_BUSY : stm32g0xx_hal_tim.h
  • HAL_DMA_BURST_STATE_READY : stm32g0xx_hal_tim.h
  • HAL_DMA_BURST_STATE_RESET : stm32g0xx_hal_tim.h
  • HAL_DMA_CallbackIDTypeDef : stm32g0xx_hal_dma.h
  • HAL_DMA_DeInit() : stm32g0xx_hal_dma.c
  • HAL_DMA_ERROR_BUSY : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_NO_XFER : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_PARAM : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32g0xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32g0xx_hal_dma.h
  • HAL_DMA_GetError() : stm32g0xx_hal_dma.c
  • HAL_DMA_GetState() : stm32g0xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32g0xx_hal_dma.h
  • HAL_DMA_Init() : stm32g0xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32g0xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32g0xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32g0xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32g0xx_hal_dma.c
  • HAL_DMA_Start() : stm32g0xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32g0xx_hal_dma.c
  • HAL_DMA_STATE_BUSY : stm32g0xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32g0xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32g0xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32g0xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32g0xx_hal_dma.h
  • HAL_DMA_UnRegisterCallback() : stm32g0xx_hal_dma.c
  • HAL_DMA_XFER_ABORT_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAMUX1_MAX_REQ_GEN : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_MAX_SYNC : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI0 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI1 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI10 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI11 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI12 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI13 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI14 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI15 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI2 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI3 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI4 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI5 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI6 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI7 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI8 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI9 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_TIM14_OC : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI1 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI10 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI11 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI12 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI13 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI14 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI15 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI2 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI3 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI4 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI5 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI6 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI7 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI8 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI9 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM2_OUT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_TIM14_OC : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_FALLING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_NO_EVENT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING_FALLING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32g0xx_hal_dma_ex.h
  • HAL_EXTI_ClearConfigLine() : stm32g0xx_hal_exti.c
  • HAL_EXTI_ClearPending() : stm32g0xx_hal_exti.c
  • HAL_EXTI_COMMON_CB_ID : stm32g0xx_hal_exti.h
  • HAL_EXTI_FALLING_CB_ID : stm32g0xx_hal_exti.h
  • HAL_EXTI_GenerateSWI() : stm32g0xx_hal_exti.c
  • HAL_EXTI_GetConfigLine() : stm32g0xx_hal_exti.c
  • HAL_EXTI_GetHandle() : stm32g0xx_hal_exti.c
  • HAL_EXTI_GetPending() : stm32g0xx_hal_exti.c
  • HAL_EXTI_IRQHandler() : stm32g0xx_hal_exti.c
  • HAL_EXTI_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_EXTI_RegisterCallback() : stm32g0xx_hal_exti.c
  • HAL_EXTI_RISING_CB_ID : stm32g0xx_hal_exti.h
  • HAL_EXTI_SetConfigLine() : stm32g0xx_hal_exti.c
  • HAL_FDCAN_AbortTxRequest() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ActivateNotification() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxFifoQ() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_CallbackIDTypeDef : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ConfigExtendedIdMask() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFilter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigGlobalFilter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigInterruptLines() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRamWatchdog() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRxFifoOverwrite() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTxDelayCompensation() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DeactivateNotification() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DeInit() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableEdgeFiltering() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableISOMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableTxDelayCompensation() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableEdgeFiltering() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableISOMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxDelayCompensation() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnterPowerDownMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_EMPTY : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_FULL : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_INVALID_CALLBACK : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_LOG_OVERFLOW : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NONE : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_INITIALIZED : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_READY : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_STARTED : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_SUPPORTED : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PARAM : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PENDING : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_ARBT : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_DATA : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_ACCESS : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_WDG : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RESERVED_AREA : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TIMEOUT : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ErrorCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ErrorStatusCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ExitPowerDownMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ExitRestrictedOperationMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetError() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetErrorCounters() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetHighPriorityMessageStatus() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetLatestTxFifoQRequestBuffer() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetProtocolStatus() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetRxFifoFillLevel() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetRxMessage() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetState() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetTxEvent() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetTxFifoFreeLevel() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_HighPriorityMessageCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_Init() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_IRQHandler() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_IsRestrictedOperationMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_IsTxBufferMessagePending() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_FDCAN_MspDeInit() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_MSPDEINIT_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_MspInit() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_MSPINIT_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_RegisterCallback() : stm32g0xx_hal_fdcan.c , stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_RegisterErrorStatusCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo0Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo1Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferAbortCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferCompleteCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxEventFifoCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo0Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo1Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_Start() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_STATE_BUSY : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_STATE_ERROR : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_STATE_READY : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_STATE_RESET : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_StateTypeDef : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_Stop() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_TimeoutOccurredCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_TimestampWraparoundCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_TxBufferAbortCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferCompleteCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TxEventFifoCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TxFifoEmptyCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterErrorStatusCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo0Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo1Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferAbortCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferCompleteCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxEventFifoCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FLASH_EndOfOperationCallback() : stm32g0xx_hal_flash.c
  • HAL_FLASH_ERROR_ECCD : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_FAST : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_MIS : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_OP : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_SIZ : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32g0xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32g0xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32g0xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32g0xx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32g0xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32g0xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32g0xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32g0xx_hal_flash.c
  • HAL_FLASH_Program() : stm32g0xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32g0xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32g0xx_hal_flash.c
  • HAL_FLASHEx_DisableDebugger() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_EnableDebugger() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_EnableSecMemProtection() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_FlashEmptyCheck() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_ForceFlashEmpty() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32g0xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32g0xx_hal.c
  • HAL_GetHalVersion() : stm32g0xx_hal.c
  • HAL_GetREVID() : stm32g0xx_hal.c
  • HAL_GetTick() : stm32g0xx_hal.c
  • HAL_GetTickFreq() : stm32g0xx_hal.c
  • HAL_GetTickPrio() : stm32g0xx_hal.c
  • HAL_GetUIDw0() : stm32g0xx_hal.c
  • HAL_GetUIDw1() : stm32g0xx_hal.c
  • HAL_GetUIDw2() : stm32g0xx_hal.c
  • HAL_GPIO_DeInit() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_EXTI_Falling_Callback() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_EXTI_Rising_Callback() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32g0xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32g0xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32g0xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32g0xx_hal_uart.c
  • HAL_HCD_CallbackIDTypeDef : stm32g0xx_hal_hcd.h
  • HAL_HCD_Check_usedChannel() : stm32g0xx_hal_hcd.c
  • HAL_HCD_ClearPhyChannel() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Connect_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_CONNECT_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_DeInit() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_DISCONNECT_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_ERROR_INVALID_CALLBACK : stm32g0xx_hal_hcd.h
  • HAL_HCD_Get_FreePhyChannel() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetFreePMA() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetLogical_Channel() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_Close() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Init() : stm32g0xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32g0xx_hal_hcd.c
  • HAL_HCD_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_HCD_MspDeInit() : stm32g0xx_hal_hcd.c
  • HAL_HCD_MSPDEINIT_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_MspInit() : stm32g0xx_hal_hcd.c
  • HAL_HCD_MSPINIT_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_PMADeAlloc() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_PMAFree() : stm32g0xx_hal_hcd.c
  • HAL_HCD_PMAlloc() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_PMAReset() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_PORT_DISABLED_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_PORT_ENABLED_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_PortDisabled_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_PortEnabled_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_RegisterCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_RegisterHC_NotifyURBChangeCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_ResetPort() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Resume() : stm32g0xx_hal_hcd.c
  • HAL_HCD_ResumeCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_ResumePort() : stm32g0xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_SOF_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_Start() : stm32g0xx_hal_hcd.c
  • HAL_HCD_STATE_BUSY : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32g0xx_hal_hcd.h
  • HAL_HCD_Stop() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Suspend() : stm32g0xx_hal_hcd.c
  • HAL_HCD_SuspendCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_UnRegisterCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_UnRegisterHC_NotifyURBChangeCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_I2C_ABORT_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_AbortCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_CallbackIDTypeDef : stm32g0xx_hal_i2c.h
  • HAL_I2C_DeInit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32g0xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA_PARAM : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_CALLBACK : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_PARAM : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32g0xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32g0xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32g0xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32g0xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Init() : stm32g0xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32g0xx_hal_i2c.c
  • HAL_I2C_LISTEN_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_ListenCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_Master_Seq_Receive_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MasterRxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_Mem_Write() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32g0xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MSPDEINIT_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MspInit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MSPINIT_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_RegisterAddrCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_RegisterCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_Slave_Seq_Receive_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_SlaveRxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_STATE_ABORT : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32g0xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32g0xx_hal_i2c.h
  • HAL_I2C_UnRegisterAddrCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_UnRegisterCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2S_CallbackIDTypeDef : stm32g0xx_hal_i2s.h
  • HAL_I2S_DeInit() : stm32g0xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32g0xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32g0xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32g0xx_hal_i2s.c
  • HAL_I2S_ERROR_BUSY_LINE_RX : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_DMA : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_INVALID_CALLBACK : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_PRESCALER : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32g0xx_hal_i2s.h
  • HAL_I2S_ErrorCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32g0xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Init() : stm32g0xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32g0xx_hal_i2s.c
  • HAL_I2S_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_I2S_MspDeInit() : stm32g0xx_hal_i2s.c
  • HAL_I2S_MSPDEINIT_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_MspInit() : stm32g0xx_hal_i2s.c
  • HAL_I2S_MSPINIT_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_Receive() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32g0xx_hal_i2s.c
  • HAL_I2S_RegisterCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_RX_COMPLETE_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_RX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_RxCpltCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_STATE_BUSY : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32g0xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32g0xx_hal_i2s.h
  • HAL_I2S_Transmit() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32g0xx_hal_i2s.c
  • HAL_I2S_TX_COMPLETE_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_TX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_TxCpltCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_UnRegisterCallback() : stm32g0xx_hal_i2s.c
  • HAL_IncTick() : stm32g0xx_hal.c
  • HAL_Init() : stm32g0xx_hal.c
  • HAL_InitTick() : stm32g0xx_hal.c
  • HAL_IRDA_Abort() : stm32g0xx_hal_irda.c
  • HAL_IRDA_ABORT_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_Abort_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_AbortCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_CallbackIDTypeDef : stm32g0xx_hal_irda.h
  • HAL_IRDA_DeInit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32g0xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32g0xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32g0xx_hal_irda.c
  • HAL_IRDA_ERROR_BUSY : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_INVALID_CALLBACK : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32g0xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Init() : stm32g0xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32g0xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_MSPDEINIT_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_MspInit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_MSPINIT_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_Receive() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_RegisterCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_RX_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_RxCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32g0xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32g0xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_TX_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_TxCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_UnRegisterCallback() : stm32g0xx_hal_irda.c
  • HAL_ITLINE_ADC : stm32g0xx_hal.h
  • HAL_ITLINE_AES : stm32g0xx_hal.h
  • HAL_ITLINE_CEC : stm32g0xx_hal.h
  • HAL_ITLINE_CLK_CTRL : stm32g0xx_hal.h
  • HAL_ITLINE_COMP1 : stm32g0xx_hal.h
  • HAL_ITLINE_COMP2 : stm32g0xx_hal.h
  • HAL_ITLINE_COMP3 : stm32g0xx_hal.h
  • HAL_ITLINE_CRS : stm32g0xx_hal.h
  • HAL_ITLINE_DAC : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH1 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH2 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH3 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH4 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH5 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH6 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH7 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH1 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH2 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH3 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH4 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH5 : stm32g0xx_hal.h
  • HAL_ITLINE_DMAMUX1 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI0 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI1 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI10 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI11 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI12 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI13 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI14 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI15 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI2 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI3 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI4 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI5 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI6 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI7 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI8 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI9 : stm32g0xx_hal.h
  • HAL_ITLINE_FDCAN1_IT0 : stm32g0xx_hal.h
  • HAL_ITLINE_FDCAN1_IT1 : stm32g0xx_hal.h
  • HAL_ITLINE_FDCAN2_IT0 : stm32g0xx_hal.h
  • HAL_ITLINE_FDCAN2_IT1 : stm32g0xx_hal.h
  • HAL_ITLINE_FLASH_ECC : stm32g0xx_hal.h
  • HAL_ITLINE_FLASH_ITF : stm32g0xx_hal.h
  • HAL_ITLINE_I2C1 : stm32g0xx_hal.h
  • HAL_ITLINE_I2C2 : stm32g0xx_hal.h
  • HAL_ITLINE_I2C3 : stm32g0xx_hal.h
  • HAL_ITLINE_LPTIM1 : stm32g0xx_hal.h
  • HAL_ITLINE_LPTIM2 : stm32g0xx_hal.h
  • HAL_ITLINE_LPUART1 : stm32g0xx_hal.h
  • HAL_ITLINE_LPUART2 : stm32g0xx_hal.h
  • HAL_ITLINE_PVDOUT : stm32g0xx_hal.h
  • HAL_ITLINE_PVMOUT : stm32g0xx_hal.h
  • HAL_ITLINE_RNG : stm32g0xx_hal.h
  • HAL_ITLINE_RTC : stm32g0xx_hal.h
  • HAL_ITLINE_SPI1 : stm32g0xx_hal.h
  • HAL_ITLINE_SPI2 : stm32g0xx_hal.h
  • HAL_ITLINE_SPI3 : stm32g0xx_hal.h
  • HAL_ITLINE_TAMPER : stm32g0xx_hal.h
  • HAL_ITLINE_TIM14 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM15 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM16 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM17 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_BRK : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_CC : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_CCU : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_TRG : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_UPD : stm32g0xx_hal.h
  • HAL_ITLINE_TIM2 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM3 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM4 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM6 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM7 : stm32g0xx_hal.h
  • HAL_ITLINE_UCPD1 : stm32g0xx_hal.h
  • HAL_ITLINE_UCPD2 : stm32g0xx_hal.h
  • HAL_ITLINE_USART1 : stm32g0xx_hal.h
  • HAL_ITLINE_USART2 : stm32g0xx_hal.h
  • HAL_ITLINE_USART3 : stm32g0xx_hal.h
  • HAL_ITLINE_USART4 : stm32g0xx_hal.h
  • HAL_ITLINE_USART5 : stm32g0xx_hal.h
  • HAL_ITLINE_USART6 : stm32g0xx_hal.h
  • HAL_ITLINE_USB : stm32g0xx_hal.h
  • HAL_ITLINE_WWDG : stm32g0xx_hal.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32g0xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32g0xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_IWDG_Refresh() : stm32g0xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32g0xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32g0xx_hal_uart.c
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_CallbackIDTypeDef : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_MATCH_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_WRITE_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_CompareWriteCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_DeInit() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_UP_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_DirectionUpCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_GetState() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Init() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_IRQHandler() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_LPTIM_MspDeInit() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_MSPDEINIT_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_MSPINIT_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_ReadAutoReload() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_ReadCompare() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_ReadCounter() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_RegisterCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_STATE_BUSY : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TRIGGER_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_UnRegisterCallback() : stm32g0xx_hal_lptim.c
  • HAL_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32g0xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32g0xx_hal_cortex.c
  • HAL_MPU_Enable() : stm32g0xx_hal_cortex.c
  • HAL_MspDeInit() : stm32g0xx_hal.c
  • HAL_MspInit() : stm32g0xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32g0xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32g0xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32g0xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32g0xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32g0xx_hal_uart_ex.c
  • HAL_NVIC_ClearPendingIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32g0xx_hal_cortex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32g0xx_hal_pcd.c
  • HAL_PCD_CallbackIDTypeDef : stm32g0xx_hal_pcd.h
  • HAL_PCD_CONNECT_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_ConnectCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DISCONNECT_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_DisconnectCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Abort() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_DB_Receive() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_DB_Transmit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_ERROR_INVALID_CALLBACK : stm32g0xx_hal_pcd.h
  • HAL_PCD_GetState() : stm32g0xx_hal_pcd.c
  • HAL_PCD_Init() : stm32g0xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32g0xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_MSPDEINIT_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_MspInit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_MSPINIT_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_RegisterBcdCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterDataInStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterDataOutStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterIsoInIncpltCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterIsoOutIncpltCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterLpmCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RESET_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_ResetCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RESUME_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_ResumeCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32g0xx_hal_pcd.c
  • HAL_PCD_SETUPSTAGE_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_SetupStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_SOF_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_SOFCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_Start() : stm32g0xx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32g0xx_hal_pcd.h
  • HAL_PCD_Stop() : stm32g0xx_hal_pcd.c
  • HAL_PCD_SUSPEND_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_SuspendCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterBcdCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataInStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataOutStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoInIncpltCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoOutIncpltCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterLpmCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_PMAConfig() : stm32g0xx_hal_pcd_ex.c
  • HAL_PWR_DeInit() : stm32g0xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32g0xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32g0xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32g0xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32g0xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_PWREx_ConfigPVD() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigPVM() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullDown() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullUp() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableInternalWakeUpLine() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowPowerRunMode() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePORMonitorSampling() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePullUpPullDownConfig() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVD() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVMUSB() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableSRAMRetention() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddIO2() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddUSB() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullDown() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullUp() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableInternalWakeUpLine() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowPowerRunMode() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePORMonitorSampling() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePullUpPullDownConfig() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVD() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVMUSB() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableSRAMRetention() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddIO2() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddUSB() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSHUTDOWNMode() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_Falling_Callback() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_IRQHandler() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_Rising_Callback() : stm32g0xx_hal_pwr_ex.c
  • HAL_RCC_ClockConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32g0xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32g0xx_hal_rcc.c
  • HAL_RCC_DisableLSECSS() : stm32g0xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32g0xx_hal_rcc.c
  • HAL_RCC_EnableLSECSS() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetResetSource() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32g0xx_hal_rcc.c
  • HAL_RCC_LSECSSCallback() : stm32g0xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32g0xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSCO() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSCO() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32g0xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32g0xx_hal.c
  • HAL_RNG_CallbackIDTypeDef : stm32g0xx_hal_rng.h
  • HAL_RNG_DeInit() : stm32g0xx_hal_rng.c
  • HAL_RNG_ERROR_BUSY : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_CB_ID : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_CLOCK : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_INVALID_CALLBACK : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_NONE : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_SEED : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_TIMEOUT : stm32g0xx_hal_rng.h
  • HAL_RNG_ErrorCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32g0xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32g0xx_hal_rng.c
  • HAL_RNG_GetError() : stm32g0xx_hal_rng.c
  • HAL_RNG_GetState() : stm32g0xx_hal_rng.c
  • HAL_RNG_Init() : stm32g0xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32g0xx_hal_rng.c
  • HAL_RNG_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_RNG_MspDeInit() : stm32g0xx_hal_rng.c
  • HAL_RNG_MSPDEINIT_CB_ID : stm32g0xx_hal_rng.h
  • HAL_RNG_MspInit() : stm32g0xx_hal_rng.c
  • HAL_RNG_MSPINIT_CB_ID : stm32g0xx_hal_rng.h
  • HAL_RNG_ReadLastRandomNumber() : stm32g0xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_RegisterCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_RegisterReadyDataCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_STATE_BUSY : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32g0xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32g0xx_hal_rng.h
  • HAL_RNG_UnRegisterCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_UnRegisterReadyDataCallback() : stm32g0xx_hal_rng.c
  • HAL_RS485Ex_Init() : stm32g0xx_hal_uart_ex.c
  • HAL_RTC_ALARM_A_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_ALARM_B_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_AlarmAEventCallback() : stm32g0xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32g0xx_hal_rtc.c
  • HAL_RTC_CallbackIDTypeDef : stm32g0xx_hal_rtc.h
  • HAL_RTC_DeactivateAlarm() : stm32g0xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32g0xx_hal_rtc.c
  • HAL_RTC_DST_Add1Hour() : stm32g0xx_hal_rtc.c , stm32g0xx_hal_rtc.h
  • HAL_RTC_DST_ClearStoreOperation() : stm32g0xx_hal_rtc.c , stm32g0xx_hal_rtc.h
  • HAL_RTC_DST_ReadStoreOperation() : stm32g0xx_hal_rtc.c , stm32g0xx_hal_rtc.h
  • HAL_RTC_DST_SetStoreOperation() : stm32g0xx_hal_rtc.c , stm32g0xx_hal_rtc.h
  • HAL_RTC_DST_Sub1Hour() : stm32g0xx_hal_rtc.c , stm32g0xx_hal_rtc.h
  • HAL_RTC_GetAlarm() : stm32g0xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32g0xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32g0xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32g0xx_hal_rtc.c
  • HAL_RTC_Init() : stm32g0xx_hal_rtc.c
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32g0xx_hal_rtc.c
  • HAL_RTC_MSPDEINIT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_MspInit() : stm32g0xx_hal_rtc.c
  • HAL_RTC_MSPINIT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_PollForAlarmAEvent() : stm32g0xx_hal_rtc.c
  • HAL_RTC_RegisterCallback() : stm32g0xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32g0xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32g0xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32g0xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32g0xx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32g0xx_hal_rtc.h
  • HAL_RTC_TAMPER1_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_TAMPER2_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_TAMPER3_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_UnRegisterCallback() : stm32g0xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32g0xx_hal_rtc.c
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTCEx_AlarmBEventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTamper() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper3EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper4EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper5EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper6EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForInternalTamperEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamperEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper_IT() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperIRQHandler() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampIRQHandler() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCStateTypeDef : stm32g0xx_hal_rtc.h
  • HAL_SetTickFreq() : stm32g0xx_hal.c
  • HAL_SMARTCARD_Abort() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_Abort_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_AbortCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_CallbackIDTypeDef : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_DeInit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_DMA : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_INVALID_CALLBACK : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_MSPDEINIT_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_MspInit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_MSPINIT_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_Receive() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_RegisterCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_RxCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_TxCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_UnRegisterCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableFifoMode() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableFifoMode() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_RxFifoFullCallback() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetRxFifoThreshold() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetTxFifoThreshold() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TxFifoEmptyCallback() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_CallbackIDTypeDef : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ConfigAnalogFilter() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_DisableListen_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_EnableListen_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_ER_IRQHandler() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_ERROR_ACKF : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_CALLBACK : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_PARAM : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ErrorCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ListenCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_SMBUS_MspDeInit() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_MSPDEINIT_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MspInit() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_MSPINIT_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_RegisterAddrCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_RegisterCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_STATE_BUSY : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_UnRegisterAddrCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUSEx_DisableFastModePlus() : stm32g0xx_hal_smbus_ex.c
  • HAL_SMBUSEx_DisableWakeUp() : stm32g0xx_hal_smbus_ex.c
  • HAL_SMBUSEx_EnableFastModePlus() : stm32g0xx_hal_smbus_ex.c
  • HAL_SMBUSEx_EnableWakeUp() : stm32g0xx_hal_smbus_ex.c
  • HAL_SPI_Abort() : stm32g0xx_hal_spi.c
  • HAL_SPI_ABORT_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_Abort_IT() : stm32g0xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_CallbackIDTypeDef : stm32g0xx_hal_spi.h
  • HAL_SPI_DeInit() : stm32g0xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32g0xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32g0xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32g0xx_hal_spi.c
  • HAL_SPI_ERROR_ABORT : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_INVALID_CALLBACK : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32g0xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_GetError() : stm32g0xx_hal_spi.c
  • HAL_SPI_GetState() : stm32g0xx_hal_spi.c
  • HAL_SPI_Init() : stm32g0xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32g0xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32g0xx_hal_spi.c
  • HAL_SPI_MSPDEINIT_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_MspInit() : stm32g0xx_hal_spi.c
  • HAL_SPI_MSPINIT_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_Receive() : stm32g0xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32g0xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32g0xx_hal_spi.c
  • HAL_SPI_RegisterCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_RX_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_RX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_RxCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_STATE_ABORT : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32g0xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32g0xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32g0xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32g0xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32g0xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32g0xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32g0xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32g0xx_hal_spi.c
  • HAL_SPI_TX_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_TX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_TX_RX_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_TxCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_UnRegisterCallback() : stm32g0xx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32g0xx_hal_spi_ex.c
  • HAL_SuspendTick() : stm32g0xx_hal.c
  • HAL_SuspendTypeDef : stm32g0xx_hal_cryp.h
  • HAL_SYSCFG_DisableClampingDiode() : stm32g0xx_hal.c
  • HAL_SYSCFG_DisableIOAnalogSwitchBooster() : stm32g0xx_hal.c
  • HAL_SYSCFG_DisableRemap() : stm32g0xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32g0xx_hal.c
  • HAL_SYSCFG_EnableClampingDiode() : stm32g0xx_hal.c
  • HAL_SYSCFG_EnableIOAnalogSwitchBooster() : stm32g0xx_hal.c
  • HAL_SYSCFG_EnableRemap() : stm32g0xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32g0xx_hal.c
  • HAL_SYSCFG_IRDA_ENV_SEL_TIM16 : stm32g0xx_hal.h
  • HAL_SYSCFG_IRDA_ENV_SEL_USART1 : stm32g0xx_hal.h
  • HAL_SYSCFG_IRDA_ENV_SEL_USART4 : stm32g0xx_hal.h
  • HAL_SYSCFG_IRDA_POLARITY_INVERTED : stm32g0xx_hal.h
  • HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE0 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE1 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE10 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE11 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE12 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE13 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE14 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE15 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE16 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE17 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE18 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE19 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE2 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE20 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE21 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE22 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE23 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE24 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE25 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE26 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE27 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE28 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE29 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE3 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE30 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE31 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE4 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE5 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE6 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE7 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE8 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE9 : stm32g0xx_hal.h
  • HAL_SYSCFG_StrobeDBattpinsConfig() : stm32g0xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32g0xx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32g0xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32g0xx_hal.c
  • HAL_SYSTICK_Callback() : stm32g0xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32g0xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32g0xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32g0xx_hal_cortex.c
  • HAL_TICK_FREQ_100HZ : stm32g0xx_hal.h
  • HAL_TICK_FREQ_10HZ : stm32g0xx_hal.h
  • HAL_TICK_FREQ_1KHZ : stm32g0xx_hal.h
  • HAL_TICK_FREQ_DEFAULT : stm32g0xx_hal.h
  • HAL_TickFreqTypeDef : stm32g0xx_hal.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32g0xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32g0xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_BASE_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_Base_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_BASE_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_Base_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_BREAK2_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_BREAK_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_CallbackIDTypeDef : stm32g0xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_BUSY : stm32g0xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_READY : stm32g0xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_RESET : stm32g0xx_hal_tim.h
  • HAL_TIM_ChannelStateTypeDef : stm32g0xx_hal_tim.h
  • HAL_TIM_COMMUTATION_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_COMMUTATION_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_ConfigClockSource() : stm32g0xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32g0xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiReadStart() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiWriteStart() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurstState() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurstStateTypeDef : stm32g0xx_hal_tim.h
  • HAL_TIM_Encoder_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_Encoder_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_ENCODER_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_Encoder_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_ERROR_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_ErrorCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32g0xx_hal_tim.c
  • HAL_TIM_GetActiveChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_GetChannelState() : stm32g0xx_hal_tim.c
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_CaptureCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_CaptureHalfCpltCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32g0xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_OC_DelayElapsedCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_OC_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_OC_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_OnePulse_ConfigChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_PERIOD_ELAPSED_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PeriodElapsedCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_PeriodElapsedHalfCpltCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PWM_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedHalfCpltCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32g0xx_hal_tim.c
  • HAL_TIM_RegisterCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro() : stm32g0xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32g0xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32g0xx_hal_tim.h
  • HAL_TIM_TRIGGER_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_TRIGGER_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_TriggerHalfCpltCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_UnRegisterCallback() : stm32g0xx_hal_tim.c
  • HAL_TIMEOUT_ADDR : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32g0xx_hal_smbus.c
  • HAL_TIMEx_Break2Callback() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_CommutCallback() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_CommutHalfCpltCallback() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_DisarmBreakInput() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_GetChannelNState() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ReArmBreakInput() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_TISelection() : stm32g0xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32g0xx_hal_uart.c
  • HAL_UART_ABORT_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_Abort_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_AbortCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_CallbackIDTypeDef : stm32g0xx_hal_uart.h
  • HAL_UART_DeInit() : stm32g0xx_hal_uart.c
  • HAL_UART_DisableReceiverTimeout() : stm32g0xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32g0xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32g0xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32g0xx_hal_uart.c
  • HAL_UART_EnableReceiverTimeout() : stm32g0xx_hal_uart.c
  • HAL_UART_ERROR_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_DMA : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_INVALID_CALLBACK : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_RTO : stm32g0xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_GetError() : stm32g0xx_hal_uart.c
  • HAL_UART_GetState() : stm32g0xx_hal_uart.c
  • HAL_UART_Init() : stm32g0xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32g0xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32g0xx_hal_uart.c
  • HAL_UART_MSPDEINIT_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_MspInit() : stm32g0xx_hal_uart.c
  • HAL_UART_MSPINIT_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_Receive() : stm32g0xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32g0xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_ReceiverTimeout_Config() : stm32g0xx_hal_uart.c
  • HAL_UART_RECEPTION_STANDARD : stm32g0xx_hal_uart.h
  • HAL_UART_RECEPTION_TOCHARMATCH : stm32g0xx_hal_uart.h
  • HAL_UART_RECEPTION_TOIDLE : stm32g0xx_hal_uart.h
  • HAL_UART_RECEPTION_TORTO : stm32g0xx_hal_uart.h
  • HAL_UART_RegisterCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_RegisterRxEventCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_RX_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_RX_FIFO_FULL_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_RX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_RxCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_RXEVENT_HT : stm32g0xx_hal_uart.h
  • HAL_UART_RXEVENT_IDLE : stm32g0xx_hal_uart.h
  • HAL_UART_RXEVENT_TC : stm32g0xx_hal_uart.h
  • HAL_UART_RxEventTypeTypeDef : stm32g0xx_hal_uart.h
  • HAL_UART_RxHalfCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_RxTypeTypeDef : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_BUSY : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32g0xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32g0xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32g0xx_hal_uart.h
  • HAL_UART_Transmit() : stm32g0xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32g0xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_TX_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_TX_FIFO_EMPTY_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_TX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_TxCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_UnRegisterCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_UnRegisterRxEventCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_WAKEUP_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UARTEx_DisableFifoMode() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_DisableStopMode() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_EnableFifoMode() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_GetRxEventType() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle_DMA() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle_IT() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_RxEventCallback() : stm32g0xx_hal_uart.c
  • HAL_UARTEx_RxFifoFullCallback() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_SetRxFifoThreshold() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_SetTxFifoThreshold() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_TxFifoEmptyCallback() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32g0xx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32g0xx_hal_usart.c
  • HAL_USART_ABORT_COMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_Abort_IT() : stm32g0xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_CallbackIDTypeDef : stm32g0xx_hal_usart.h
  • HAL_USART_DeInit() : stm32g0xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32g0xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32g0xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32g0xx_hal_usart.c
  • HAL_USART_ERROR_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_DMA : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_INVALID_CALLBACK : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_RTO : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32g0xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_GetError() : stm32g0xx_hal_usart.c
  • HAL_USART_GetState() : stm32g0xx_hal_usart.c
  • HAL_USART_Init() : stm32g0xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32g0xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32g0xx_hal_usart.c
  • HAL_USART_MSPDEINIT_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_MspInit() : stm32g0xx_hal_usart.c
  • HAL_USART_MSPINIT_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_Receive() : stm32g0xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32g0xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32g0xx_hal_usart.c
  • HAL_USART_RegisterCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_RX_COMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_RX_FIFO_FULL_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_RX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_RxCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32g0xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32g0xx_hal_usart.h
  • HAL_USART_Transmit() : stm32g0xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32g0xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32g0xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32g0xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32g0xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32g0xx_hal_usart.c
  • HAL_USART_TX_COMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_TX_FIFO_EMPTY_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_TX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_TX_RX_COMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_TxCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_UnRegisterCallback() : stm32g0xx_hal_usart.c
  • HAL_USARTEx_ConfigNSS() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_DisableFifoMode() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_DisableSlaveMode() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_EnableFifoMode() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_EnableSlaveMode() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_RxFifoFullCallback() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_SetRxFifoThreshold() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_SetTxFifoThreshold() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_TxFifoEmptyCallback() : stm32g0xx_hal_usart_ex.c
  • HAL_WWDG_CallbackIDTypeDef : stm32g0xx_hal_wwdg.h
  • HAL_WWDG_EarlyWakeupCallback() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_EWI_CB_ID : stm32g0xx_hal_wwdg.h
  • HAL_WWDG_Init() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_WWDG_MspInit() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_MSPINIT_CB_ID : stm32g0xx_hal_wwdg.h
  • HAL_WWDG_Refresh() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_RegisterCallback() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_UnRegisterCallback() : stm32g0xx_hal_wwdg.c
  • HCD_CLEAR_BULK_CH_DBUF : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_CH_KIND : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_RX_CH_CTR : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_RX_CH_ERR : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_RX_DTOG : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_TX_CH_CTR : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_TX_CH_ERR : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_TX_DTOG : stm32g0xx_hal_hcd.h
  • HCD_DBL_BUF : stm32g0xx_hal_hcd.h
  • HCD_DEVICE_SPEED_FULL : stm32g0xx_hal_hcd.h
  • HCD_DEVICE_SPEED_HIGH : stm32g0xx_hal_hcd.h
  • HCD_DEVICE_SPEED_LOW : stm32g0xx_hal_hcd.h
  • HCD_FREE_CH_NOT_FOUND : stm32g0xx_hal_hcd.h
  • HCD_FREE_USER_BUFFER : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_DBUF0_CNT() : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_DBUF1_CNT() : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_RX_CNT() : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_RX_STATUS : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_TX_CNT : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_TX_STATUS : stm32g0xx_hal_hcd.h
  • HCD_GET_CHANNEL : stm32g0xx_hal_hcd.h
  • HCD_HandleTypeDef : stm32g0xx_hal_hcd.h
  • HCD_HC_IN_BulkDb() : stm32g0xx_hal_hcd.c
  • HCD_HC_IN_IRQHandler() : stm32g0xx_hal_hcd.c
  • HCD_HC_IN_ISO() : stm32g0xx_hal_hcd.c
  • HCD_HC_OUT_BulkDb() : stm32g0xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32g0xx_hal_hcd.c
  • HCD_HCD_STATE_CONNECTED : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_DISCONNECTED : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_RESETED : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_RESUME : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_RUN : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_SUSPEND : stm32g0xx_hal_hcd.h
  • HCD_HCStateTypeDef : stm32g0xx_hal_hcd.h
  • HCD_HCTypeDef : stm32g0xx_hal_hcd.h
  • HCD_HostStateTypeDef : stm32g0xx_hal_hcd.h
  • HCD_InitTypeDef : stm32g0xx_hal_hcd.h
  • HCD_LOGICAL_CH_NOT_OPENED : stm32g0xx_hal_hcd.h
  • HCD_PHY_EMBEDDED : stm32g0xx_hal_hcd.h
  • HCD_PHY_ULPI : stm32g0xx_hal_hcd.h
  • HCD_Port_IRQHandler() : stm32g0xx_hal_hcd.c
  • HCD_RX_DTOG : stm32g0xx_hal_hcd.h
  • HCD_SET_BULK_CH_DBUF : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_DBUF0_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_DBUF1_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_DBUF_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_KIND : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_RX_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_RX_STATUS : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_TX_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_TX_STATUS : stm32g0xx_hal_hcd.h
  • HCD_SET_CHANNEL : stm32g0xx_hal_hcd.h
  • HCD_SNG_BUF : stm32g0xx_hal_hcd.h
  • HCD_SPEED_FULL : stm32g0xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32g0xx_hal_hcd.h
  • HCD_StateTypeDef : stm32g0xx_hal_hcd.h
  • HCD_TX_DTOG : stm32g0xx_hal_hcd.h
  • HCD_TypeDef : stm32g0xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32g0xx_hal_hcd.h
  • HSE_STARTUP_TIMEOUT : stm32g0xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • HSE_VALUE : stm32g0xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • HSI48_VALUE : stm32g0xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • HSI_VALUE : stm32g0xx_hal_conf.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32g0xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32g0xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32g0xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32g0xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32g0xx_hal_i2c.h
  • I2C_CHECK_FLAG : stm32g0xx_hal_i2c.h
  • I2C_CHECK_IT_SOURCE : stm32g0xx_hal_i2c.h
  • I2C_ConvertOtherXferOptions() : stm32g0xx_hal_i2c.c
  • I2C_DIRECTION_RECEIVE : stm32g0xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32g0xx_hal_i2c.h
  • I2C_Disable_IRQ() : stm32g0xx_hal_i2c.c
  • I2C_DMAAbort() : stm32g0xx_hal_i2c.c
  • I2C_DMAError() : stm32g0xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32g0xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32g0xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32g0xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32g0xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32g0xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32g0xx_hal_i2c.h
  • I2C_Enable_IRQ() : stm32g0xx_hal_i2c.c
  • I2C_FASTMODEPLUS_I2C1 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PA10 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PA9 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32g0xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32g0xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32g0xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32g0xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_AF : stm32g0xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32g0xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32g0xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32g0xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32g0xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32g0xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TC : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32g0xx_hal_i2c.h
  • I2C_Flush_TXDR() : stm32g0xx_hal_i2c.c
  • I2C_FMP_NOT_SUPPORTED : stm32g0xx_hal_i2c_ex.h
  • I2C_GENERALCALL_DISABLE : stm32g0xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32g0xx_hal_i2c.h
  • I2C_GENERATE_START : stm32g0xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32g0xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32g0xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32g0xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32g0xx_hal_i2c.h
  • I2C_GET_DIR : stm32g0xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32g0xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32g0xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32g0xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32g0xx_hal_i2c.h
  • I2C_HandleTypeDef : stm32g0xx_hal_i2c.h
  • I2C_IsErrorOccurred() : stm32g0xx_hal_i2c.c
  • I2C_IT_ADDRI : stm32g0xx_hal_i2c.h
  • I2C_IT_ERRI : stm32g0xx_hal_i2c.h
  • I2C_IT_NACKI : stm32g0xx_hal_i2c.h
  • I2C_IT_RXI : stm32g0xx_hal_i2c.h
  • I2C_IT_STOPI : stm32g0xx_hal_i2c.h
  • I2C_IT_TCI : stm32g0xx_hal_i2c.h
  • I2C_IT_TXI : stm32g0xx_hal_i2c.h
  • I2C_ITAddrCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITError() : stm32g0xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITMasterSeqCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITSlaveSeqCplt() : stm32g0xx_hal_i2c.c
  • I2C_LAST_FRAME : stm32g0xx_hal_i2c.h
  • I2C_LAST_FRAME_NO_STOP : stm32g0xx_hal_i2c.h
  • I2C_Master_ISR_DMA() : stm32g0xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32g0xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32g0xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32g0xx_hal_i2c.h
  • I2C_Mem_ISR_DMA() : stm32g0xx_hal_i2c.c
  • I2C_Mem_ISR_IT() : stm32g0xx_hal_i2c.c
  • I2C_MEMADD_SIZE_16BIT : stm32g0xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32g0xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32g0xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32g0xx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32g0xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32g0xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32g0xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32g0xx_hal_i2c.h
  • I2C_OTHER_AND_LAST_FRAME : stm32g0xx_hal_i2c.h
  • I2C_OTHER_FRAME : stm32g0xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32g0xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32g0xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32g0xx_hal_i2c.c
  • I2C_RESET_CR2 : stm32g0xx_hal_i2c.h
  • I2C_Slave_ISR_DMA() : stm32g0xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32g0xx_hal_i2c.c
  • I2C_SOFTEND_MODE : stm32g0xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32g0xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32g0xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32g0xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32g0xx_hal_i2c.c
  • I2C_STATE_MSK : stm32g0xx_hal_i2c.c
  • I2C_STATE_NONE : stm32g0xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32g0xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32g0xx_hal_i2c.c
  • I2C_TransferConfig() : stm32g0xx_hal_i2c.c
  • I2C_TreatErrorCallback() : stm32g0xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32g0xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32g0xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32g0xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32g0xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32g0xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32g0xx_hal_i2s.h
  • I2S_CHECK_FLAG : stm32g0xx_hal_i2s.h
  • I2S_CHECK_IT_SOURCE : stm32g0xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32g0xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32g0xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32g0xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32g0xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32g0xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32g0xx_hal_i2s.h
  • I2S_DMAError() : stm32g0xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32g0xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32g0xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32g0xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32g0xx_hal_i2s.c
  • I2S_FLAG_BSY : stm32g0xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32g0xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32g0xx_hal_i2s.h
  • I2S_FLAG_MASK : stm32g0xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32g0xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32g0xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32g0xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32g0xx_hal_i2s.h
  • I2S_HandleTypeDef : stm32g0xx_hal_i2s.h
  • I2S_I2SCFGR_CLEAR_MASK : stm32g0xx_ll_spi.c
  • I2S_I2SPR_CLEAR_MASK : stm32g0xx_ll_spi.c
  • I2S_IT_ERR : stm32g0xx_hal_i2s.h
  • I2S_IT_RXNE : stm32g0xx_hal_i2s.h
  • I2S_IT_TXE : stm32g0xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32g0xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32g0xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32g0xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32g0xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32g0xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32g0xx_hal_i2s.h
  • I2S_Receive_IT() : stm32g0xx_hal_i2s.c
  • I2S_STANDARD_LSB : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32g0xx_hal_i2s.h
  • I2S_TIMEOUT_FLAG : stm32g0xx_hal_i2s.c
  • I2S_Transmit_IT() : stm32g0xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32g0xx_hal_i2s.c
  • IC1Config() : stm32g0xx_ll_tim.c
  • IC2Config() : stm32g0xx_ll_tim.c
  • IC3Config() : stm32g0xx_ll_tim.c
  • IC4Config() : stm32g0xx_ll_tim.c
  • INSTRUCTION_CACHE_ENABLE : stm32g0xx_hal_conf.h
  • IRDA_AUTOBAUD_REQUEST : stm32g0xx_hal_irda.h
  • IRDA_CheckIdleState() : stm32g0xx_hal_irda.c
  • IRDA_CLEAR_FEF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32g0xx_hal_irda.h
  • IRDA_ClockSourceTypeDef : stm32g0xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32g0xx_hal_irda.c
  • IRDA_CR_MASK : stm32g0xx_hal_irda.h
  • IRDA_CR_POS : stm32g0xx_hal_irda.h
  • IRDA_DIV_SAMPLING16 : stm32g0xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_DMAAbortOnError() : stm32g0xx_hal_irda.c
  • IRDA_DMAError() : stm32g0xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32g0xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32g0xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32g0xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32g0xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32g0xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32g0xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32g0xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32g0xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32g0xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32g0xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32g0xx_hal_irda.c
  • IRDA_FLAG_ABRE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32g0xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32g0xx_hal_irda.h
  • IRDA_FLAG_FE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_NE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_PE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32g0xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_TC : stm32g0xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32g0xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32g0xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32g0xx_hal_irda_ex.h
  • IRDA_HandleTypeDef : stm32g0xx_hal_irda.h
  • IRDA_InitCallbacksToDefault() : stm32g0xx_hal_irda.c
  • IRDA_ISR_MASK : stm32g0xx_hal_irda.h
  • IRDA_ISR_POS : stm32g0xx_hal_irda.h
  • IRDA_IT_ERR : stm32g0xx_hal_irda.h
  • IRDA_IT_FE : stm32g0xx_hal_irda.h
  • IRDA_IT_IDLE : stm32g0xx_hal_irda.h
  • IRDA_IT_MASK : stm32g0xx_hal_irda.h
  • IRDA_IT_NE : stm32g0xx_hal_irda.h
  • IRDA_IT_ORE : stm32g0xx_hal_irda.h
  • IRDA_IT_PE : stm32g0xx_hal_irda.h
  • IRDA_IT_RXNE : stm32g0xx_hal_irda.h
  • IRDA_IT_TC : stm32g0xx_hal_irda.h
  • IRDA_IT_TXE : stm32g0xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32g0xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_MODE_RX : stm32g0xx_hal_irda.h
  • IRDA_MODE_TX : stm32g0xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32g0xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32g0xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32g0xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32g0xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32g0xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV1 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV10 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV12 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV128 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV16 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV2 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV256 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV32 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV4 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV6 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV64 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV8 : stm32g0xx_hal_irda.h
  • IRDA_Receive_IT() : stm32g0xx_hal_irda.c
  • IRDA_RXDATA_FLUSH_REQUEST : stm32g0xx_hal_irda.h
  • IRDA_SetConfig() : stm32g0xx_hal_irda.c
  • IRDA_STATE_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32g0xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32g0xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32g0xx_hal_irda.h
  • IRDA_WaitOnFlagUntilTimeout() : stm32g0xx_hal_irda.c
  • IRDA_WORDLENGTH_7B : stm32g0xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_8B : stm32g0xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32g0xx_hal_irda_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32g0xx_hal_adc.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32g0xx_hal_adc.h
  • IS_ADC_CALFACT : stm32g0xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32g0xx_hal_adc.h
  • IS_ADC_CLOCKPRESCALER : stm32g0xx_hal_adc.h
  • IS_ADC_DATA_ALIGN : stm32g0xx_hal_adc.h
  • IS_ADC_EOC_SELECTION : stm32g0xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32g0xx_hal_adc.h
  • IS_ADC_EXTTRIG : stm32g0xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32g0xx_hal_adc.h
  • IS_ADC_OVERRUN : stm32g0xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32g0xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32g0xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32g0xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32g0xx_hal_adc.h
  • IS_ADC_REGULAR_RANK_SEQ_FIXED : stm32g0xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32g0xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32g0xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32g0xx_hal_adc.h
  • IS_ADC_SAMPLING_TIME_COMMON : stm32g0xx_hal_adc.h
  • IS_ADC_SCAN_MODE : stm32g0xx_hal_adc.h
  • IS_ADC_TRIGGER_FREQ : stm32g0xx_hal_adc.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32g0xx_hal_adc_ex.h
  • IS_CEC_ADDRESS : stm32g0xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32g0xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32g0xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32g0xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32g0xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32g0xx_hal_cec.h
  • IS_CEC_OWN_ADDRESS : stm32g0xx_hal_cec.h
  • IS_CEC_SFTOP : stm32g0xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32g0xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32g0xx_hal_cec.h
  • IS_COMP_BLANKINGSRC_INSTANCE : stm32g0xx_hal_comp.h
  • IS_COMP_BLANKINGSRCE : stm32g0xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32g0xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32g0xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32g0xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32g0xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32g0xx_hal_comp.h
  • IS_COMP_POWERMODE : stm32g0xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32g0xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32g0xx_hal_comp.h
  • IS_COMP_WINDOWOUTPUT : stm32g0xx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32g0xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32g0xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32g0xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32g0xx_hal_crc.h
  • IS_CRYP_ALGORITHM : stm32g0xx_hal_cryp.h
  • IS_CRYP_BUFFERSIZE : stm32g0xx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32g0xx_hal_cryp.h
  • IS_CRYP_INIT : stm32g0xx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32g0xx_hal_cryp.h
  • IS_DAC_ALIGN : stm32g0xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32g0xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32g0xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32g0xx_hal_dac.h
  • IS_DAC_HOLDTIME : stm32g0xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32g0xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32g0xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32g0xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32g0xx_hal_dac.h
  • IS_DAC_SAMPLEANDHOLD : stm32g0xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32g0xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32g0xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32g0xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32g0xx_hal_dac_ex.h
  • IS_DEFAULT_INIT_VALUE : stm32g0xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32g0xx_hal_crc.h
  • IS_DMA_ALL_REQUEST : stm32g0xx_hal_dma.h
  • IS_DMA_BUFFER_SIZE : stm32g0xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32g0xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32g0xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32g0xx_hal_dma.h
  • IS_DMA_MODE : stm32g0xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32g0xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32g0xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32g0xx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_SIGNAL_ID : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32g0xx_hal_dma_ex.h
  • IS_EXTI_CONFIG_LINE : stm32g0xx_hal_exti.h
  • IS_EXTI_GPIO_PIN : stm32g0xx_hal_exti.h
  • IS_EXTI_GPIO_PORT : stm32g0xx_hal_exti.h
  • IS_EXTI_LINE : stm32g0xx_hal_exti.h
  • IS_EXTI_MODE : stm32g0xx_hal_exti.h
  • IS_EXTI_PENDING_EDGE : stm32g0xx_hal_exti.h
  • IS_EXTI_TRIGGER : stm32g0xx_hal_exti.h
  • IS_FDCAN_BRS : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_CKDIV : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DATA_PRESCALER : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DATA_SJW : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG1 : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG2 : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DLC : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_EFC : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_ESI : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_EXT_FILTER_TYPE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_FDF : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_FILTER_CFG : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_FRAME_FORMAT : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_FRAME_TYPE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_ID_TYPE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_IT : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_IT_GROUP : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_IT_LINE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_MAX_VALUE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_MIN_VALUE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_MODE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_PRESCALER : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_SJW : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG1 : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG2 : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NON_MATCHING : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_REJECT_REMOTE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO_MODE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_STD_FILTER_TYPE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TIMEOUT : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP_PRESCALER : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TX_FIFO_QUEUE_MODE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION_LIST : stm32g0xx_hal_fdcan.h
  • IS_FLASH_BANK : stm32g0xx_hal_flash.h
  • IS_FLASH_EMPTY_CHECK : stm32g0xx_hal_flash_ex.h
  • IS_FLASH_FAST_PROGRAM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32g0xx_hal_flash.h
  • IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_MAIN_MEM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_PAGE : stm32g0xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_PROGRAM_OTP_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_TYPEERASE : stm32g0xx_hal_flash.h
  • IS_FLASH_TYPEPROGRAM : stm32g0xx_hal_flash.h
  • IS_GPIO_AF : stm32g0xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32g0xx_hal_gpio.h
  • IS_GPIO_PIN : stm32g0xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32g0xx_hal_gpio.h
  • IS_GPIO_PULL : stm32g0xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32g0xx_hal_gpio.h
  • IS_HAL_REMAP_PIN : stm32g0xx_hal.h
  • IS_HAL_SYSCFG_IRDA_ENV_SEL : stm32g0xx_hal.h
  • IS_HAL_SYSCFG_IRDA_POL_SEL : stm32g0xx_hal.h
  • IS_I2C_ADDRESSING_MODE : stm32g0xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32g0xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32g0xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32g0xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32g0xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32g0xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32g0xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32g0xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32g0xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32g0xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32g0xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32g0xx_hal_i2c.h
  • IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST : stm32g0xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32g0xx_hal_i2s.h
  • IS_I2S_CPOL : stm32g0xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32g0xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32g0xx_hal_i2s.h
  • IS_I2S_MODE : stm32g0xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32g0xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32g0xx_hal_irda.h
  • IS_IRDA_CLOCKPRESCALER : stm32g0xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32g0xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32g0xx_hal_irda.h
  • IS_IRDA_MODE : stm32g0xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32g0xx_hal_irda.h
  • IS_IRDA_PARITY : stm32g0xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32g0xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32g0xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32g0xx_hal_irda.h
  • IS_IRDA_STATE : stm32g0xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32g0xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32g0xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32g0xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32g0xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32g0xx_hal_iwdg.h
  • IS_LL_ADC_CLOCK : stm32g0xx_ll_adc.c
  • IS_LL_ADC_CLOCK_FREQ_MODE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_COMMON_CLOCK : stm32g0xx_ll_adc.c
  • IS_LL_ADC_DATA_ALIGN : stm32g0xx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_MODE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32g0xx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32g0xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32g0xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32g0xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32g0xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32g0xx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32g0xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32g0xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32g0xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_CONNECTION : stm32g0xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_MODE : stm32g0xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32g0xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32g0xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32g0xx_ll_dac.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32g0xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32g0xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_PERIPHREQUEST : stm32g0xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32g0xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32g0xx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32g0xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32g0xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32g0xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32g0xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32g0xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32g0xx_ll_spi.c
  • IS_LL_I2S_CPOL : stm32g0xx_ll_spi.c
  • IS_LL_I2S_DATAFORMAT : stm32g0xx_ll_spi.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32g0xx_ll_spi.c
  • IS_LL_I2S_MODE : stm32g0xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32g0xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32g0xx_ll_spi.c
  • IS_LL_I2S_STANDARD : stm32g0xx_ll_spi.c
  • IS_LL_LPTIM_CLOCK_PRESCALER : stm32g0xx_ll_lptim.c
  • IS_LL_LPTIM_CLOCK_SOURCE : stm32g0xx_ll_lptim.c
  • IS_LL_LPTIM_OUTPUT_POLARITY : stm32g0xx_ll_lptim.c
  • IS_LL_LPTIM_WAVEFORM : stm32g0xx_ll_lptim.c
  • IS_LL_LPUART_BAUDRATE : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MAX : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MIN : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_PRESCALER : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32g0xx_ll_lpuart.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_CEC_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_FDCAN_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_I2S_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_LPUART_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_RNG_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_TIM_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RNG_CED : stm32g0xx_ll_rng.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32g0xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32g0xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32g0xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32g0xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32g0xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32g0xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32g0xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32g0xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32g0xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32g0xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32g0xx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32g0xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK2_AFMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK2_FILTER : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK2_POLARITY : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK2_STATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK_AFMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK_FILTER : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32g0xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32g0xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32g0xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32g0xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32g0xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32g0xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32g0xx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32g0xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32g0xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32g0xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32g0xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32g0xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32g0xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32g0xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32g0xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32g0xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32g0xx_ll_usart.c
  • IS_LL_USART_PRESCALER : stm32g0xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32g0xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_HSI_DIV : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLR_VALUE : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32g0xx_ll_utils.c
  • IS_LPTIM_AUTORELOAD : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32g0xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32g0xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32g0xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32g0xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32g0xx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32g0xx_hal_uart.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32g0xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32g0xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32g0xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32g0xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32g0xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32g0xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32g0xx_hal_cortex.h
  • IS_OB_PCROP_CONFIG : stm32g0xx_hal_flash.h
  • IS_OB_RDP_LEVEL : stm32g0xx_hal_flash.h
  • IS_OB_SEC_BOOT_LOCK : stm32g0xx_hal_flash.h
  • IS_OB_SEC_SIZE : stm32g0xx_hal_flash.h
  • IS_OB_USER_CONFIG : stm32g0xx_hal_flash.h
  • IS_OB_USER_TYPE : stm32g0xx_hal_flash.h
  • IS_OB_WRPAREA : stm32g0xx_hal_flash.h
  • IS_OPTIONBYTE : stm32g0xx_hal_flash.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_FLASH_POWERDOWN : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_GPIO : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_GPIO_BIT_NUMBER : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_PVD_MODE : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_PVM_MODE : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_PVM_TYPE : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32g0xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32g0xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32g0xx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32g0xx_hal_pwr.h
  • IS_RCC_ADCCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CECCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32g0xx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_FDCANCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32g0xx_hal_rcc.h
  • IS_RCC_HSE : stm32g0xx_hal_rcc.h
  • IS_RCC_HSI : stm32g0xx_hal_rcc.h
  • IS_RCC_HSI48 : stm32g0xx_hal_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_HSIDIV : stm32g0xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_I2S1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_I2S2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LPUART2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LSCOSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32g0xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32g0xx_hal_rcc.h
  • IS_RCC_LSI : stm32g0xx_hal_rcc.h
  • IS_RCC_MCO : stm32g0xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_MCO2DIV : stm32g0xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32g0xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32g0xx_hal_rcc.h
  • IS_RCC_PCLK : stm32g0xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_RNGCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_RNGDIV : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_TIM15CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_TIM1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RNG_CED : stm32g0xx_hal_rng.h
  • IS_RNG_FLAG : stm32g0xx_hal_rng.h
  • IS_RNG_IT : stm32g0xx_hal_rng.h
  • IS_RTC_ALARM : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32g0xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32g0xx_hal_rtc.h
  • IS_RTC_BKP : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32g0xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32g0xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32g0xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32g0xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32g0xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32g0xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32g0xx_hal_rtc.h
  • IS_RTC_INTERNAL_TAMPER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_MINUTES : stm32g0xx_hal_rtc.h
  • IS_RTC_MONTH : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT_POL : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT_PULLUP : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32g0xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32g0xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32g0xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32g0xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMPONTAMPER_DETECTION : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32g0xx_hal_rtc.h
  • IS_RTC_YEAR : stm32g0xx_hal_rtc.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_CLOCKPRESCALER : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_FIFOMODE_STATE : stm32g0xx_hal_smartcard_ex.h
  • IS_SMARTCARD_LASTBIT : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32g0xx_hal_smartcard_ex.h
  • IS_SMARTCARD_STOPBITS : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32g0xx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32g0xx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32g0xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32g0xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32g0xx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32g0xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32g0xx_hal_smbus.h
  • IS_SMBUS_FASTMODEPLUS : stm32g0xx_hal_smbus_ex.h
  • IS_SMBUS_GENERAL_CALL : stm32g0xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32g0xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32g0xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32g0xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32g0xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32g0xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32g0xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32g0xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32g0xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32g0xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32g0xx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32g0xx_hal_spi.h
  • IS_SPI_CPHA : stm32g0xx_hal_spi.h
  • IS_SPI_CPOL : stm32g0xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32g0xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32g0xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32g0xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32g0xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32g0xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32g0xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32g0xx_hal_spi.h
  • IS_SPI_DMA_HANDLE : stm32g0xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32g0xx_hal_spi.h
  • IS_SPI_MODE : stm32g0xx_hal_spi.h
  • IS_SPI_NSS : stm32g0xx_hal_spi.h
  • IS_SPI_NSSP : stm32g0xx_hal_spi.h
  • IS_SPI_TIMODE : stm32g0xx_hal_spi.h
  • IS_SYSCFG_BREAK_CONFIG : stm32g0xx_hal.h
  • IS_SYSCFG_CLAMPINGDIODE : stm32g0xx_hal.h
  • IS_SYSCFG_DBATT_CONFIG : stm32g0xx_hal.h
  • IS_SYSCFG_FASTMODEPLUS : stm32g0xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32g0xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32g0xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32g0xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32g0xx_hal_cortex.h
  • IS_TICKFREQ : stm32g0xx_hal.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK2_AFMODE : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_AFMODE : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32g0xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32g0xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32g0xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32g0xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32g0xx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32g0xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32g0xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32g0xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32g0xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32g0xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32g0xx_hal_tim.h
  • IS_TIM_DMA_DATA_LENGTH : stm32g0xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32g0xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_ENCODERINPUT_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32g0xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32g0xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32g0xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32g0xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32g0xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32g0xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32g0xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_PERIOD : stm32g0xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_REMAP : stm32g0xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_SLAVEMODE_TRIGGER_ENABLED : stm32g0xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32g0xx_hal_tim.h
  • IS_TIM_TISEL : stm32g0xx_hal_tim_ex.h
  • IS_TIM_TRGO2_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32g0xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32g0xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32g0xx_hal_tim.h
  • IS_TIM_UIFREMAP_MODE : stm32g0xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32g0xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32g0xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32g0xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32g0xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32g0xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32g0xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32g0xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32g0xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32g0xx_hal_uart.h
  • IS_UART_DMA_RX : stm32g0xx_hal_uart.h
  • IS_UART_DMA_TX : stm32g0xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32g0xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32g0xx_hal_uart.h
  • IS_UART_LIN : stm32g0xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32g0xx_hal_uart.h
  • IS_UART_MODE : stm32g0xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32g0xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32g0xx_hal_uart.h
  • IS_UART_OVERRUN : stm32g0xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32g0xx_hal_uart.h
  • IS_UART_PARITY : stm32g0xx_hal_uart.h
  • IS_UART_PRESCALER : stm32g0xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32g0xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT_VALUE : stm32g0xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32g0xx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32g0xx_hal_uart_ex.h
  • IS_UART_STATE : stm32g0xx_hal_uart.h
  • IS_UART_STOPBITS : stm32g0xx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32g0xx_hal_uart_ex.h
  • IS_UART_WAKEUP_SELECTION : stm32g0xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32g0xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32g0xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32g0xx_hal_usart.h
  • IS_USART_CLOCK : stm32g0xx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32g0xx_hal_usart_ex.h
  • IS_USART_LASTBIT : stm32g0xx_hal_usart.h
  • IS_USART_MODE : stm32g0xx_hal_usart.h
  • IS_USART_NSS : stm32g0xx_hal_usart_ex.h
  • IS_USART_PARITY : stm32g0xx_hal_usart.h
  • IS_USART_PHASE : stm32g0xx_hal_usart.h
  • IS_USART_POLARITY : stm32g0xx_hal_usart.h
  • IS_USART_PRESCALER : stm32g0xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32g0xx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32g0xx_hal_usart_ex.h
  • IS_USART_SLAVEMODE : stm32g0xx_hal_usart_ex.h
  • IS_USART_STOPBITS : stm32g0xx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32g0xx_hal_usart_ex.h
  • IS_USART_WORD_LENGTH : stm32g0xx_hal_usart_ex.h
  • IS_WWDG_COUNTER : stm32g0xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32g0xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32g0xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32g0xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32g0xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32g0xx_hal_iwdg.h
  • IWDG_KERNEL_UPDATE_FLAGS : stm32g0xx_hal_iwdg.c
  • IWDG_KEY_ENABLE : stm32g0xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32g0xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32g0xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32g0xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32g0xx_hal_iwdg.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
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  • Typedefs
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LL_ADC_AWD1 : stm32g0xx_ll_adc.h
  • LL_ADC_AWD2 : stm32g0xx_ll_adc.h
  • LL_ADC_AWD3 : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_FREQ_MODE_HIGH : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_FREQ_MODE_LOW : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32g0xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32g0xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32g0xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32g0xx_ll_adc.c
  • LL_ADC_ConfigAnalogWDThresholds() : stm32g0xx_ll_adc.h
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32g0xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32g0xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32g0xx_ll_adc.h
  • LL_ADC_DeInit() : stm32g0xx_ll_adc.c
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32g0xx_ll_adc.h
  • LL_ADC_Disable() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32g0xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32g0xx_ll_adc.h
  • LL_ADC_Enable() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_CCRDY : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_EOCAL : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32g0xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32g0xx_ll_adc.h
  • LL_ADC_GetCalibrationFactor() : stm32g0xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32g0xx_ll_adc.h
  • LL_ADC_GetClock() : stm32g0xx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32g0xx_ll_adc.h
  • LL_ADC_GetCommonFrequencyMode() : stm32g0xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32g0xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32g0xx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32g0xx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32g0xx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32g0xx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32g0xx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32g0xx_ll_adc.h
  • LL_ADC_GetResolution() : stm32g0xx_ll_adc.h
  • LL_ADC_GetSamplingTimeCommonChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_GetTriggerFrequencyMode() : stm32g0xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32g0xx_ll_adc.h
  • LL_ADC_Init() : stm32g0xx_ll_adc.c
  • LL_ADC_IsActiveFlag_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32g0xx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32g0xx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32g0xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32g0xx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32g0xx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32g0xx_ll_adc.h
  • LL_ADC_IT_CCRDY : stm32g0xx_ll_adc.h
  • LL_ADC_IT_EOC : stm32g0xx_ll_adc.h
  • LL_ADC_IT_EOCAL : stm32g0xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32g0xx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32g0xx_ll_adc.h
  • LL_ADC_IT_OVR : stm32g0xx_ll_adc.h
  • LL_ADC_LP_AUTOPOWEROFF : stm32g0xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32g0xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF : stm32g0xx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_128 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_16 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_2 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_256 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_32 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_4 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_64 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_8 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32g0xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32g0xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32g0xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32g0xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32g0xx_ll_adc.h
  • LL_ADC_ReadReg : stm32g0xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32g0xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerConfigurable() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerScanDirection() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32g0xx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32g0xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData6() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_CONFIGURABLE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_FIXED : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DIR_FORWARD : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerChAdd() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerChRem() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerConfigurable() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerScanDirection() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32g0xx_ll_adc.c
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH4 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32g0xx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32g0xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32g0xx_ll_adc.h
  • LL_ADC_RESOLUTION_6B : stm32g0xx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_12CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_160CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_19CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_1CYCLE_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_39CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_3CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_79CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_7CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_COMMON_1 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_COMMON_2 : stm32g0xx_ll_adc.h
  • LL_ADC_SetAnalogWDMonitChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCalibrationFactor() : stm32g0xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32g0xx_ll_adc.h
  • LL_ADC_SetClock() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonFrequencyMode() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalChAdd() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalChRem() : stm32g0xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32g0xx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32g0xx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32g0xx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32g0xx_ll_adc.h
  • LL_ADC_SetResolution() : stm32g0xx_ll_adc.h
  • LL_ADC_SetSamplingTimeCommonChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_SetTriggerFrequencyMode() : stm32g0xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32g0xx_ll_adc.h
  • LL_ADC_StructInit() : stm32g0xx_ll_adc.c
  • LL_ADC_TEMPERATURE_CALC_ERROR : stm32g0xx_ll_adc.h
  • LL_ADC_TRIGGER_FREQ_HIGH : stm32g0xx_ll_adc.h
  • LL_ADC_TRIGGER_FREQ_LOW : stm32g0xx_ll_adc.h
  • LL_ADC_WriteReg : stm32g0xx_ll_adc.h
  • LL_AHB1_GRP1_DisableClock() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRYP : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_RNG : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_DisableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_EnableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CEC : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CRS : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DBGMCU : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_FDCAN : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPUART1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPUART2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_RTC : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UCPD1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UCPD2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART4 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART5 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART6 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_DisableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_EnableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ADC : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SYSCFG : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM14 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32g0xx_ll_bus.h
  • LL_COMP_BLANKINGSRC_NONE : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC2 : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC4 : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5 : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3 : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3 : stm32g0xx_ll_comp.h
  • LL_COMP_ConfigInputs() : stm32g0xx_ll_comp.h
  • LL_COMP_DeInit() : stm32g0xx_ll_comp.c
  • LL_COMP_DELAY_STARTUP_US : stm32g0xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32g0xx_ll_comp.h
  • LL_COMP_Disable() : stm32g0xx_ll_comp.h
  • LL_COMP_Enable() : stm32g0xx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32g0xx_ll_comp.h
  • LL_COMP_GetCommonWindowOutput() : stm32g0xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32g0xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32g0xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32g0xx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32g0xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32g0xx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32g0xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32g0xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32g0xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32g0xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32g0xx_ll_comp.h
  • LL_COMP_Init() : stm32g0xx_ll_comp.c
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO3 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO3 : stm32g0xx_ll_comp.h
  • LL_COMP_IsEnabled() : stm32g0xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32g0xx_ll_comp.h
  • LL_COMP_Lock() : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32g0xx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32g0xx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32g0xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32g0xx_ll_comp.h
  • LL_COMP_ReadReg : stm32g0xx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32g0xx_ll_comp.h
  • LL_COMP_SetCommonWindowOutput() : stm32g0xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32g0xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32g0xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32g0xx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32g0xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32g0xx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32g0xx_ll_comp.h
  • LL_COMP_StructInit() : stm32g0xx_ll_comp.c
  • LL_COMP_WINDOWMODE_BITOFFSET_POS : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMPX_SETTING_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_BOTH : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_COMP1 : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_COMP2 : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_COMP3 : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_EACH_COMP : stm32g0xx_ll_comp.h
  • LL_COMP_WriteReg : stm32g0xx_ll_comp.h
  • LL_CPUID_GetArchitecture() : stm32g0xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32g0xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32g0xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32g0xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32g0xx_ll_cortex.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32g0xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32g0xx_ll_crc.h
  • LL_CRC_DeInit() : stm32g0xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32g0xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32g0xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32g0xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32g0xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32g0xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32g0xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32g0xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32g0xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32g0xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32g0xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32g0xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32g0xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32g0xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32g0xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32g0xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32g0xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32g0xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32g0xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadReg : stm32g0xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32g0xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32g0xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32g0xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32g0xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32g0xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32g0xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32g0xx_ll_crc.h
  • LL_CRC_WriteReg : stm32g0xx_ll_crc.h
  • LL_CRS_ClearFlag_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_ClearFlag_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_ConfigSynchronization() : stm32g0xx_ll_crs.h
  • LL_CRS_CR_ERRIE : stm32g0xx_ll_crs.h
  • LL_CRS_CR_ESYNCIE : stm32g0xx_ll_crs.h
  • LL_CRS_CR_SYNCOKIE : stm32g0xx_ll_crs.h
  • LL_CRS_CR_SYNCWARNIE : stm32g0xx_ll_crs.h
  • LL_CRS_DeInit() : stm32g0xx_ll_crs.c
  • LL_CRS_DisableAutoTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableFreqErrorCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableIT_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableIT_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableAutoTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableFreqErrorCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableIT_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableIT_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_ERRORLIMIT_DEFAULT : stm32g0xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_DOWN : stm32g0xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_UP : stm32g0xx_ll_crs.h
  • LL_CRS_GenerateEvent_SWSYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_GetFreqErrorCapture() : stm32g0xx_ll_crs.h
  • LL_CRS_GetFreqErrorDirection() : stm32g0xx_ll_crs.h
  • LL_CRS_GetFreqErrorLimit() : stm32g0xx_ll_crs.h
  • LL_CRS_GetHSI48SmoothTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_GetReloadCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_GetSyncDivider() : stm32g0xx_ll_crs.h
  • LL_CRS_GetSyncPolarity() : stm32g0xx_ll_crs.h
  • LL_CRS_GetSyncSignalSource() : stm32g0xx_ll_crs.h
  • LL_CRS_HSI48CALIBRATION_DEFAULT : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCERR() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCMISS() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_TRIMOVF() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledAutoTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledFreqErrorCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_ERRF : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_ESYNCF : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_SYNCERR : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_SYNCMISS : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_SYNCOKF : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_SYNCWARNF : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_TRIMOVF : stm32g0xx_ll_crs.h
  • LL_CRS_ReadReg : stm32g0xx_ll_crs.h
  • LL_CRS_RELOADVALUE_DEFAULT : stm32g0xx_ll_crs.h
  • LL_CRS_SetFreqErrorLimit() : stm32g0xx_ll_crs.h
  • LL_CRS_SetHSI48SmoothTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_SetReloadCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_SetSyncDivider() : stm32g0xx_ll_crs.h
  • LL_CRS_SetSyncPolarity() : stm32g0xx_ll_crs.h
  • LL_CRS_SetSyncSignalSource() : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_1 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_128 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_16 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_2 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_32 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_4 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_64 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_8 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_FALLING : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_RISING : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_GPIO : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_LSE : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_USB : stm32g0xx_ll_crs.h
  • LL_CRS_WriteReg : stm32g0xx_ll_crs.h
  • LL_DAC_CHANNEL_1 : stm32g0xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32g0xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_ConfigOutput() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_DeInit() : stm32g0xx_ll_dac.c
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32g0xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32g0xx_ll_dac.h
  • LL_DAC_Disable() : stm32g0xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32g0xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32g0xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32g0xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32g0xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32g0xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32g0xx_ll_dac.h
  • LL_DAC_Enable() : stm32g0xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32g0xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_BWST1 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_BWST2 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_CAL1 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_CAL2 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32g0xx_ll_dac.h
  • LL_DAC_GetMode() : stm32g0xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32g0xx_ll_dac.h
  • LL_DAC_GetOutputConnection() : stm32g0xx_ll_dac.h
  • LL_DAC_GetOutputMode() : stm32g0xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldHoldTime() : stm32g0xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldRefreshTime() : stm32g0xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldSampleTime() : stm32g0xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32g0xx_ll_dac.h
  • LL_DAC_GetTrimmingValue() : stm32g0xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32g0xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32g0xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32g0xx_ll_dac.h
  • LL_DAC_Init() : stm32g0xx_ll_dac.c
  • LL_DAC_IsActiveFlag_BWST1() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_BWST2() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL1() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL2() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32g0xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32g0xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32g0xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32g0xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32g0xx_ll_dac.h
  • LL_DAC_MODE_CALIBRATION : stm32g0xx_ll_dac.h
  • LL_DAC_MODE_NORMAL_OPERATION : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_GPIO : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_INTERNAL : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_NORMAL : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD : stm32g0xx_ll_dac.h
  • LL_DAC_ReadReg : stm32g0xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32g0xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32g0xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32g0xx_ll_dac.h
  • LL_DAC_SetMode() : stm32g0xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32g0xx_ll_dac.h
  • LL_DAC_SetOutputConnection() : stm32g0xx_ll_dac.h
  • LL_DAC_SetOutputMode() : stm32g0xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldHoldTime() : stm32g0xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldRefreshTime() : stm32g0xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldSampleTime() : stm32g0xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32g0xx_ll_dac.h
  • LL_DAC_SetTrimmingValue() : stm32g0xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32g0xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32g0xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32g0xx_ll_dac.h
  • LL_DAC_StructInit() : stm32g0xx_ll_dac.c
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM1_OUT : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM2_OUT : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM15_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM1_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM3_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32g0xx_ll_dac.h
  • LL_DAC_TrigSWConversion() : stm32g0xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32g0xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32g0xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32g0xx_ll_dac.h
  • LL_DAC_WriteReg : stm32g0xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM2_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM14_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32g0xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32g0xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32g0xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32g0xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32g0xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32g0xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32g0xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32g0xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32g0xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI1() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32g0xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32g0xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32g0xx_ll_dma.h
  • LL_DMA_DeInit() : stm32g0xx_ll_dma.c
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32g0xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32g0xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32g0xx_ll_dma.h
  • LL_DMA_DisableChannel() : stm32g0xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32g0xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32g0xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32g0xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32g0xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32g0xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32g0xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32g0xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32g0xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32g0xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32g0xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32g0xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32g0xx_ll_dma.h
  • LL_DMA_GetMode() : stm32g0xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32g0xx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32g0xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_Init() : stm32g0xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32g0xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32g0xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32g0xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32g0xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32g0xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32g0xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32g0xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32g0xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32g0xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32g0xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32g0xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32g0xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32g0xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32g0xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32g0xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32g0xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32g0xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32g0xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32g0xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32g0xx_ll_dma.h
  • LL_DMA_ReadReg : stm32g0xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32g0xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32g0xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32g0xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32g0xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32g0xx_ll_dma.h
  • LL_DMA_SetMode() : stm32g0xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32g0xx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32g0xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32g0xx_ll_dma.h
  • LL_DMA_StructInit() : stm32g0xx_ll_dma.c
  • LL_DMA_WriteReg : stm32g0xx_ll_dma.h
  • LL_DMAMUX_CCR_SOIE : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO0() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO1() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO2() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO3() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO0() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO1() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO10() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO11() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO2() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO3() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO4() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO5() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO6() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO7() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO8() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO9() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableEventGeneration() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_RGO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_SO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableRequestGen() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableSync() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableEventGeneration() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_RGO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_SO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableRequestGen() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableSync() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetGenRequestNb() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestGenPolarity() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestSignalID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncPolarity() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncRequestNb() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO0() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO1() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO2() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO3() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO0() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO1() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO10() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO11() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO2() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO3() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO4() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO5() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO6() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO7() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO8() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO9() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledEventGeneration() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_RGO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_SO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledRequestGen() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledSync() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_MAX_REQ : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ReadReg : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES_IN : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC1_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC1_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM2_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_NO_EVENT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_FALLING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_TIM14_OC : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_MEM2MEM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI3_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI3_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_TRIG_COM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_COM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_COM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_TRIG_COM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_TRIG : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_TRIG : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_TRIG : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM6_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM7_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART3_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART3_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART4_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART4_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART5_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART5_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART6_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART6_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCR_RGOIE : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetGenRequestNb() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestGenPolarity() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestSignalID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncPolarity() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncRequestNb() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE12 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE13 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE14 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE15 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM1_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM2_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_NO_EVENT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_FALLING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING_FALLING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_TIM14_OC : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_WriteReg : stm32g0xx_ll_dmamux.h
  • LL_EXTI_ClearFallingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_ClearFallingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_ClearRisingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_ClearRisingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE0 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE1 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE10 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE11 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE12 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE13 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE14 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE15 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE2 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE3 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE4 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE5 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE6 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE7 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE8 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE9 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTA : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTB : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTC : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTD : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTE : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTF : stm32g0xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32g0xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_GetEXTISource() : stm32g0xx_ll_exti.h
  • LL_EXTI_Init() : stm32g0xx_ll_exti.c
  • LL_EXTI_IsActiveFallingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsActiveFallingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsActiveRisingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsActiveRisingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_31 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_32 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_33 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_34 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_35 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32g0xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32g0xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32g0xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadFallingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadFallingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadRisingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadRisingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_REGISTER_PINPOS_SHFT : stm32g0xx_ll_exti.h
  • LL_EXTI_SetEXTISource() : stm32g0xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32g0xx_ll_exti.c
  • LL_EXTI_TRIGGER_FALLING : stm32g0xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32g0xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32g0xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32g0xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32g0xx_ll_exti.h
  • LL_FLASH_DisableInstCache() : stm32g0xx_ll_system.h
  • LL_FLASH_DisableInstCacheReset() : stm32g0xx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32g0xx_ll_system.h
  • LL_FLASH_EnableInstCache() : stm32g0xx_ll_system.h
  • LL_FLASH_EnableInstCacheReset() : stm32g0xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32g0xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32g0xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32g0xx_ll_system.h
  • LL_FLASH_LATENCY_0 : stm32g0xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32g0xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32g0xx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32g0xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32g0xx_ll_system.h
  • LL_GetFlashSize() : stm32g0xx_ll_utils.h
  • LL_GetPackageType() : stm32g0xx_ll_utils.h
  • LL_GetUID_Word0() : stm32g0xx_ll_utils.h
  • LL_GetUID_Word1() : stm32g0xx_ll_utils.h
  • LL_GetUID_Word2() : stm32g0xx_ll_utils.h
  • LL_GPIO_AF_0 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32g0xx_ll_gpio.h
  • LL_GPIO_DeInit() : stm32g0xx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32g0xx_ll_gpio.h
  • LL_GPIO_Init() : stm32g0xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32g0xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32g0xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32g0xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32g0xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32g0xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32g0xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32g0xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32g0xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32g0xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32g0xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32g0xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32g0xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32g0xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32g0xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32g0xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32g0xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32g0xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FAST : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_HIGH : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_LOW : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_MEDIUM : stm32g0xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32g0xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32g0xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32g0xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32g0xx_ll_gpio.h
  • LL_I2C_ACK : stm32g0xx_ll_i2c.h
  • LL_I2C_AcknowledgeNextData() : stm32g0xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32g0xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32g0xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32g0xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32g0xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32g0xx_ll_i2c.c
  • LL_I2C_DIRECTION_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_Disable() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32g0xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32g0xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32g0xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32g0xx_ll_i2c.h
  • LL_I2C_Enable() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32g0xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32g0xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32g0xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32g0xx_ll_i2c.h
  • LL_I2C_Init() : stm32g0xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32g0xx_ll_i2c.h
  • LL_I2C_NACK : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32g0xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32g0xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32g0xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32g0xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32g0xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32g0xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32g0xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_16K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_192K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_22K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_32K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_44K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_48K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_8K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_96K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32g0xx_ll_spi.h
  • LL_I2S_ClearFlag_FRE() : stm32g0xx_ll_spi.h
  • LL_I2S_ClearFlag_OVR() : stm32g0xx_ll_spi.h
  • LL_I2S_ClearFlag_UDR() : stm32g0xx_ll_spi.h
  • LL_I2S_ConfigPrescaler() : stm32g0xx_ll_spi.c
  • LL_I2S_CR2_ERRIE : stm32g0xx_ll_spi.h
  • LL_I2S_CR2_RXNEIE : stm32g0xx_ll_spi.h
  • LL_I2S_CR2_TXEIE : stm32g0xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B : stm32g0xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32g0xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B : stm32g0xx_ll_spi.h
  • LL_I2S_DATAFORMAT_32B : stm32g0xx_ll_spi.h
  • LL_I2S_DeInit() : stm32g0xx_ll_spi.c
  • LL_I2S_Disable() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableAsyncStart() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableIT_ERR() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableIT_TXE() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableMasterClock() : stm32g0xx_ll_spi.h
  • LL_I2S_Enable() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableAsyncStart() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableIT_ERR() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableIT_TXE() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableMasterClock() : stm32g0xx_ll_spi.h
  • LL_I2S_GetClockPolarity() : stm32g0xx_ll_spi.h
  • LL_I2S_GetDataFormat() : stm32g0xx_ll_spi.h
  • LL_I2S_GetPrescalerLinear() : stm32g0xx_ll_spi.h
  • LL_I2S_GetPrescalerParity() : stm32g0xx_ll_spi.h
  • LL_I2S_GetStandard() : stm32g0xx_ll_spi.h
  • LL_I2S_GetTransferMode() : stm32g0xx_ll_spi.h
  • LL_I2S_Init() : stm32g0xx_ll_spi.c
  • LL_I2S_IsActiveFlag_BSY() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_CHSIDE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_FRE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_OVR() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_RXNE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_TXE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_UDR() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabled() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledAsyncStart() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledIT_ERR() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledIT_TXE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledMasterClock() : stm32g0xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32g0xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32g0xx_ll_spi.h
  • LL_I2S_MODE_MASTER_RX : stm32g0xx_ll_spi.h
  • LL_I2S_MODE_MASTER_TX : stm32g0xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_RX : stm32g0xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_TX : stm32g0xx_ll_spi.h
  • LL_I2S_POLARITY_HIGH : stm32g0xx_ll_spi.h
  • LL_I2S_POLARITY_LOW : stm32g0xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32g0xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32g0xx_ll_spi.h
  • LL_I2S_ReadReg : stm32g0xx_ll_spi.h
  • LL_I2S_ReceiveData16() : stm32g0xx_ll_spi.h
  • LL_I2S_SetClockPolarity() : stm32g0xx_ll_spi.h
  • LL_I2S_SetDataFormat() : stm32g0xx_ll_spi.h
  • LL_I2S_SetPrescalerLinear() : stm32g0xx_ll_spi.h
  • LL_I2S_SetPrescalerParity() : stm32g0xx_ll_spi.h
  • LL_I2S_SetStandard() : stm32g0xx_ll_spi.h
  • LL_I2S_SetTransferMode() : stm32g0xx_ll_spi.h
  • LL_I2S_SR_BSY : stm32g0xx_ll_spi.h
  • LL_I2S_SR_FRE : stm32g0xx_ll_spi.h
  • LL_I2S_SR_OVR : stm32g0xx_ll_spi.h
  • LL_I2S_SR_RXNE : stm32g0xx_ll_spi.h
  • LL_I2S_SR_TXE : stm32g0xx_ll_spi.h
  • LL_I2S_SR_UDR : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_LSB : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_MSB : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_LONG : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_PHILIPS : stm32g0xx_ll_spi.h
  • LL_I2S_StructInit() : stm32g0xx_ll_spi.c
  • LL_I2S_TransmitData16() : stm32g0xx_ll_spi.h
  • LL_I2S_WriteReg : stm32g0xx_ll_spi.h
  • LL_Init1msTick() : stm32g0xx_ll_utils.c
  • LL_InitTick() : stm32g0xx_ll_utils.h
  • LL_IOP_GRP1_DisableClock() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_DisableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_EnableClock() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_EnableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_ForceReset() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_IsEnabledClock() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_ALL : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOA : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOB : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOC : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOD : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOE : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOF : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_ReleaseReset() : stm32g0xx_ll_bus.h
  • LL_IWDG_DisableWriteAccess() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_KEY_ENABLE : stm32g0xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32g0xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32g0xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32g0xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32g0xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32g0xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32g0xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32g0xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32g0xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32g0xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32g0xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32g0xx_ll_cortex.h
  • LL_LPTIM_ClearFLAG_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFLAG_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32g0xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32g0xx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32g0xx_ll_lptim.c
  • LL_LPTIM_DisableEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableResetAfterRead() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableResetAfterRead() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_Init() : stm32g0xx_ll_lptim.c
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledResetAfterRead() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ResetCounter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32g0xx_ll_lptim.c
  • LL_LPTIM_TRIG_FILTER_2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP3 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TrigSw() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32g0xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32g0xx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32g0xx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ConfigFIFOsThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_RXFFIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE_RXFNEIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE_TXFNFIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_TXFEIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_RXFTIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_TXFTIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32g0xx_ll_lpuart.c
  • LL_LPUART_DIRECTION_NONE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32g0xx_ll_lpuart.h
  • LL_LPUART_Disable() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableFIFO() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE_RXFNE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE_TXFNF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32g0xx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableFIFO() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE_RXFNE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE_TXFNF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_2 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_4 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_8 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_3_4 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_7_8 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_8_8 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetPrescaler() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetRXFIFOThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTXFIFOThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_Init() : stm32g0xx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE_RXFNE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE_TXFNF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledFIFO() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE_RXFNE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE_TXFNF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFT : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE_RXFNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TXE_TXFNF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFT : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV1 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV10 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV12 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV128 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV16 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV2 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV256 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV32 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV4 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV6 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV64 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV8 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetPrescaler() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetRXFIFOThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTXFIFOThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32g0xx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32g0xx_ll_lpuart.h
  • LL_MAX_DELAY : stm32g0xx_ll_utils.h
  • LL_mDelay() : stm32g0xx_ll_utils.c
  • LL_MPU_ACCESS_BUFFERABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ConfigRegion() : stm32g0xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32g0xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32g0xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32g0xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32g0xx_ll_cortex.h
  • LL_MPU_Disable() : stm32g0xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32g0xx_ll_cortex.h
  • LL_MPU_Enable() : stm32g0xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32g0xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32g0xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32g0xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32g0xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32g0xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32g0xx_ll_cortex.h
  • LL_PLL_ConfigSystemClock_HSE() : stm32g0xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32g0xx_ll_utils.c
  • LL_PWR_BATTCHARG_RESISTOR_1_5K : stm32g0xx_ll_pwr.h
  • LL_PWR_BATTCHARG_RESISTOR_5K : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_SB() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU6() : stm32g0xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32g0xx_ll_pwr.c
  • LL_PWR_DisableBatteryCharging() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableFlashPowerDownInLPRun() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableFlashPowerDownInLPSleep() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableFlashPowerDownInStop() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullDown() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullUp() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableInternWU() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableLPMUResetSamplingMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisablePUPDCfg() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisablePVM() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableSRAMRetention() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableVddIO2() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableVddUSB() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableFlashPowerDownInLPRun() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableFlashPowerDownInLPSleep() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableFlashPowerDownInStop() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullDown() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullUp() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableInternWU() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableLPMUResetSamplingMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnablePUPDCfg() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnablePVM() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableSRAMRetention() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableVddIO2() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableVddUSB() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnterLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_ExitLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetPVDHighLevel() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetPVDLowLevel() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_A : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_B : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_0 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_1 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_10 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_11 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_12 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_13 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_14 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_15 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_2 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_3 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_4 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_5 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_6 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_7 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_8 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_9 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_C : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_D : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_E : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_F : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_FLASH_RDY() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_InternWU() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMOUSB() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPF() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPS() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOS() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU6() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullDown() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullUp() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledInternWU() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledPUPDCfg() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledPVM() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledSRAMRetention() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledVddIO2() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledVddUSB() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnableFlashPowerDownInLPRun() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnableFlashPowerDownInLPSleep() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnableFlashPowerDownInStop() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnableLPMUResetSamplingMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32g0xx_ll_pwr.h
  • LL_PWR_MODE_SHUTDOWN : stm32g0xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32g0xx_ll_pwr.h
  • LL_PWR_MODE_STOP0 : stm32g0xx_ll_pwr.h
  • LL_PWR_MODE_STOP1 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_0 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_1 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_2 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_3 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_4 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_5 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_6 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_7 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_0 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_1 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_2 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_3 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_4 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_5 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_6 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVM_USB : stm32g0xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32g0xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32g0xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CSBF : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF1 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF2 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF3 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF4 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF5 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF6 : stm32g0xx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetPVDHighLevel() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetPVDLowLevel() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_SBF : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF1 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF2 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF3 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF4 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF5 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF6 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUFI : stm32g0xx_ll_pwr.h
  • LL_PWR_SR2_PVDO : stm32g0xx_ll_pwr.h
  • LL_PWR_SR2_REGLPF : stm32g0xx_ll_pwr.h
  • LL_PWR_SR2_REGLPS : stm32g0xx_ll_pwr.h
  • LL_PWR_SR2_VOSF : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN6 : stm32g0xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32g0xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_HSI_DIV488 : stm32g0xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_CSSC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_HSERDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_HSI48RDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_HSIRDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_LSECSSC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_LSERDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_LSIRDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_PLLRDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_HSERDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_HSI48RDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_HSIRDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_LSERDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_LSIRDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_PLLRDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_CSSF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_HSERDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_HSI48RDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_HSIRDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_LSECSSF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_LSERDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_LSIRDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_PLLRDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSECSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32g0xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32g0xx_ll_rcc.h
  • LL_RCC_ConfigMCO2() : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_PWRRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32g0xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32g0xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetCECClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetCECClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetFDCANClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetFDCANClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetHSIDiv() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetI2SClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetI2SClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetRNGClockDiv() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetRNGClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetRTCClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetRTCClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetTIMClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetTIMClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetUSARTClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI48_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI48_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI48_GetCalibration() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI48_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DisableInStopMode() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_128 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_32 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_64 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_EnableInStopMode() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_IsEnabledInStopMode() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE_PIN : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE_PIN : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PWRRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_GetSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_SetSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_DisableCSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_IsCSSDetected() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32g0xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32g0xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32g0xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32g0xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1024 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_128 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_256 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_32 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_512 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_64 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI48 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLPCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLQCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_RTC_WKUP : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_RTCCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_1024 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_128 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_256 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_32 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_512 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_64 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_HSI48 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_NOCLOCK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLLCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLLPCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLLQCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_RTC_WKUP : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_RTCCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32g0xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_ADC() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_FDCAN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_I2S1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_I2S2() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_RNG() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_TIM1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_TIM15() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_USB() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_ADC() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_FDCAN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_I2S1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_I2S2() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_RNG() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SYS() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_TIM1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_TIM15() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_USB() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_ADC() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_FDCAN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_I2S1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_I2S2() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_RNG() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SYS() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_TIM1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_TIM15() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_USB() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetDivider() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetP() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetQ() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetR() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_ADC() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_FDCAN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_I2S1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_I2S2() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_RNG() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_SYS() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_TIM1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_TIM15() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_USB() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_SetMainSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_3 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_5 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_6 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_7 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_10 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_11 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_12 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_13 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_14 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_15 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_17 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_18 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_19 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_20 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_21 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_22 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_23 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_24 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_25 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_26 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_27 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_28 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_29 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_3 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_30 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_31 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_32 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_5 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_6 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_7 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_9 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_3 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_5 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_6 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_7 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_3 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_5 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_6 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_7 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32g0xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32g0xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLK_DIV1 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLK_DIV2 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLK_DIV4 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLK_DIV8 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKDIV : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_HSI_DIV8 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_NONE : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32g0xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32g0xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetCECClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetFDCANClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetHSIDiv() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetI2SClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetRNGClockDiv() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetTIMClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM15_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM15_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM15_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM1_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSI48 : stm32g0xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32g0xx_ll_rcc.h
  • LL_RNG_CED_DISABLE : stm32g0xx_ll_rng.h
  • LL_RNG_CED_ENABLE : stm32g0xx_ll_rng.h
  • LL_RNG_ClearFlag_CEIS() : stm32g0xx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32g0xx_ll_rng.h
  • LL_RNG_CR_IE : stm32g0xx_ll_rng.h
  • LL_RNG_DeInit() : stm32g0xx_ll_rng.c
  • LL_RNG_Disable() : stm32g0xx_ll_rng.h
  • LL_RNG_DisableClkErrorDetect() : stm32g0xx_ll_rng.h
  • LL_RNG_DisableIT() : stm32g0xx_ll_rng.h
  • LL_RNG_Enable() : stm32g0xx_ll_rng.h
  • LL_RNG_EnableClkErrorDetect() : stm32g0xx_ll_rng.h
  • LL_RNG_EnableIT() : stm32g0xx_ll_rng.h
  • LL_RNG_Init() : stm32g0xx_ll_rng.c
  • LL_RNG_IsActiveFlag_CECS() : stm32g0xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32g0xx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32g0xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32g0xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32g0xx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32g0xx_ll_rng.h
  • LL_RNG_IsEnabledClkErrorDetect() : stm32g0xx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32g0xx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32g0xx_ll_rng.h
  • LL_RNG_ReadReg : stm32g0xx_ll_rng.h
  • LL_RNG_SR_CECS : stm32g0xx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32g0xx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32g0xx_ll_rng.h
  • LL_RNG_SR_SECS : stm32g0xx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32g0xx_ll_rng.h
  • LL_RNG_StructInit() : stm32g0xx_ll_rng.c
  • LL_RNG_WriteReg : stm32g0xx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_ConfigTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_ALMA_MASK_ALL : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_ConfigTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_ALMB_MASK_ALL : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_GetRegister() : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_SetRegister() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32g0xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32g0xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32g0xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_DisableAlarmPullUp() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableInitMode() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableOutput2() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableTamperOutput() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableAlarmPullUp() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableOutput2() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableTamperOutput() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32g0xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32g0xx_ll_rtc.c
  • LL_RTC_FORMAT_BCD : stm32g0xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32g0xx_ll_rtc.h
  • LL_RTC_GetAlarmOutEvent() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32g0xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32g0xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_ALRAWF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_ALRBWF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_INITF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_INITS : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_RECALPF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_RSF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_SHPF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_WUTWF : stm32g0xx_ll_rtc.h
  • LL_RTC_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP3M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP4M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP5M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP6M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITSM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOVM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsAlarmPullUpEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsOutput2Enabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsTamperOutputEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32g0xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32g0xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32g0xx_ll_rtc.h
  • LL_RTC_ReadReg : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_ALRAF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_ALRBF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_ITSF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_TSF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_TSOVF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_WUTF : stm32g0xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32g0xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32g0xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32g0xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_TAMPER_1 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP4 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP5 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP6 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32g0xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32g0xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32g0xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WriteReg : stm32g0xx_ll_rtc.h
  • LL_SetFlashLatency() : stm32g0xx_ll_utils.c
  • LL_SetSystemCoreClock() : stm32g0xx_ll_utils.c
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32g0xx_ll_spi.h
  • LL_SPI_ClearFlag_CRCERR() : stm32g0xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32g0xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32g0xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32g0xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32g0xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32g0xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32g0xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32g0xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32g0xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32g0xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DeInit() : stm32g0xx_ll_spi.c
  • LL_SPI_Disable() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32g0xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32g0xx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32g0xx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32g0xx_ll_spi.h
  • LL_SPI_Enable() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32g0xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32g0xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32g0xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32g0xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32g0xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32g0xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32g0xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32g0xx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_GetMode() : stm32g0xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32g0xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32g0xx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32g0xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32g0xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32g0xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32g0xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32g0xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32g0xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32g0xx_ll_spi.h
  • LL_SPI_Init() : stm32g0xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32g0xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32g0xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32g0xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32g0xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32g0xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32g0xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32g0xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32g0xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32g0xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32g0xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32g0xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32g0xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32g0xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32g0xx_ll_spi.h
  • LL_SPI_ReadReg : stm32g0xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32g0xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32g0xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32g0xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32g0xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32g0xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32g0xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32g0xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32g0xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32g0xx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_SetMode() : stm32g0xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32g0xx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32g0xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32g0xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32g0xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32g0xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32g0xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32g0xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32g0xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32g0xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32g0xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32g0xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32g0xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32g0xx_ll_spi.h
  • LL_SPI_StructInit() : stm32g0xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32g0xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32g0xx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32g0xx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_WriteReg : stm32g0xx_ll_spi.h
  • LL_SYSCFG_CFGR1_BOOSTEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA13_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA1_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA3_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA5_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA6_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PB0_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PB1_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PB2_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_ClearFlag_SP() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisableAnalogBooster() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisableClampingDiode() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisableDBATT() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisablePinRemap() : stm32g0xx_ll_system.h
  • LL_SYSCFG_EnableAnalogBooster() : stm32g0xx_ll_system.h
  • LL_SYSCFG_EnableClampingDiode() : stm32g0xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32g0xx_ll_system.h
  • LL_SYSCFG_EnablePinRemap() : stm32g0xx_ll_system.h
  • LL_SYSCFG_GetIRModEnvelopeSignal() : stm32g0xx_ll_system.h
  • LL_SYSCFG_GetIRPolarity() : stm32g0xx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32g0xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PA10 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PA9 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_MOD_TIM16 : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_MOD_USART1 : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_MOD_USART4 : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_POL_INVERTED : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_POL_NOT_INVERTED : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_ADC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_AES() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_CEC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_CLK_CTRL() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_COMP1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_COMP2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_COMP3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_CRS() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DAC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH5() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH6() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH7() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH5() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMAMUX() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI0() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI10() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI11() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI12() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI13() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI14() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI15() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI5() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI6() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI7() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI8() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI9() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FDCAN1_IT0() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FDCAN1_IT1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FDCAN2_IT0() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FDCAN2_IT1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FLASH_ECC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FLASH_ITF() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_I2C1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_I2C2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_I2C3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_LPTIM1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_LPTIM2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_LPUART1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_LPUART2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_PVDOUT() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_PVMOUT() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_RNG() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_RTC_WAKEUP() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SPI1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SPI2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SPI3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TAMPER() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM14() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM15() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM16() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM17() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_BRK() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_CC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_CCU() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_TRG() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_UPD() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM6() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM7() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_UCPD1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_UCPD2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART5() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART6() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USB() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_WWDG() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsEnabledClampingDiode() : stm32g0xx_ll_system.h
  • LL_SYSCFG_PIN_RMP_PA11 : stm32g0xx_ll_system.h
  • LL_SYSCFG_PIN_RMP_PA12 : stm32g0xx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32g0xx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32g0xx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32g0xx_ll_system.h
  • LL_SYSCFG_SetIRModEnvelopeSignal() : stm32g0xx_ll_system.h
  • LL_SYSCFG_SetIRPolarity() : stm32g0xx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32g0xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32g0xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ECC : stm32g0xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32g0xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32g0xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY : stm32g0xx_ll_system.h
  • LL_SYSCFG_UCPD1_STROBE : stm32g0xx_ll_system.h
  • LL_SYSCFG_UCPD2_STROBE : stm32g0xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_DisableIT() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32g0xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32g0xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32g0xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32g0xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BDTR_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_BKIN_POLARITY_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_AFMODE_INPUT : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_AFMODE_BIDIRECTIONAL : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_AFMODE_INPUT : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_CC_DisableChannel() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32g0xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32g0xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32g0xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32g0xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32g0xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32g0xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32g0xx_ll_tim.h
  • LL_TIM_DeInit() : stm32g0xx_ll_tim.c
  • LL_TIM_DIER_BIE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32g0xx_ll_tim.h
  • LL_TIM_DisableAllOutputs() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32g0xx_ll_tim.h
  • LL_TIM_DisarmBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_DisarmBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF2 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_TISEL : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32g0xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32g0xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32g0xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD1 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD2 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD3 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_LSE : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_MCO : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_MCO2 : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32g0xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32g0xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32g0xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32g0xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32g0xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32g0xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32g0xx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32g0xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32g0xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32g0xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32g0xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32g0xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32g0xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32g0xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_ICPSC_DIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32g0xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32g0xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32g0xx_ll_tim.h
  • LL_TIM_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveUIFCPY() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32g0xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32g0xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32g0xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32g0xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32g0xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_OCIDLESTATE_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32g0xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_ETR : stm32g0xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32g0xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32g0xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_ReadReg : stm32g0xx_ll_tim.h
  • LL_TIM_ReArmBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_ReArmBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_SetAutoReload() : stm32g0xx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32g0xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32g0xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32g0xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32g0xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32g0xx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32g0xx_ll_tim.h
  • LL_TIM_SetOCRefClearInputSource() : stm32g0xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32g0xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32g0xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32g0xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32g0xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32g0xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32g0xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32g0xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32g0xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32g0xx_ll_tim.h
  • LL_TIM_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_TIM14_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_HSE_32 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_MCO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_MCO2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_RTC_CLK : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_TIM2_IC1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_TIM3_IC1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_TIM2_IC2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_TIM3_IC2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSE : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSI : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_MCO2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC_WK : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSE_32 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSI48 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI2_RMP_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI3_RMP_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI3_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI3_RMP_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI3_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI3_RMP_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI3_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI3_RMP_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI3_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR7 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32g0xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32g0xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32g0xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32g0xx_ll_tim.h
  • LL_TIM_WriteReg : stm32g0xx_ll_tim.h
  • LL_UCPD_CCENABLE_CC1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_CC1CC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_CC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_NONE : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCPIN_CC1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCPIN_CC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DeInit() : stm32g0xx_ll_ucpd.c
  • LL_UCPD_Disable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxNE() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxIS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_Enable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxNE() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxIS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EOP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ForceClockDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ForceClockEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_FRSDetectionDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_FRSDetectionEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_GetRole() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_GetTypeCVstateCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_GetTypeCVstateCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_FRSEVT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_HRSTDISC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_HRSTSENT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXHRSTDET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXMSGEND : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXNE : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXORDDET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXOVR : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXIS : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGABT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGDISC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGSENT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXUND : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TYPECEVT1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TYPECEVT2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_Init() : stm32g0xx_ll_ucpd.c
  • LL_UCPD_IsActiveFlag_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxNE() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxIS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnabled() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnabledRxDMA() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnabledTxDMA() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxNE() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxIS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_CABLE_RESET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_HARD_RESET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP1_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP2_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_CABLERST : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_HARDRST : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP1_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP2_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP_EXT1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP_EXT2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV16 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV4 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV8 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ReadData() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ReadReg : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ReadRxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ReadRxPaySize() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_1_5A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_3_0A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_DEFAULT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_NONE : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ROLE_SNK : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ROLE_SRC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RST1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RST2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxDMADisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxDMAEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxFilterDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxFilterEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXMODE_BIST_TEST_DATA : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXMODE_NORMAL : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_CABLE_RESET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP1_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP2_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOPEXT1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOPEXT2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SendHardReset() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SendMessage() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetccEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetCCPin() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetHbitClockDiv() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetIfrGap() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetPSCClk() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRpResistor() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRxMode() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRxOrdExt1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRxOrdExt2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetSNKRole() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetSRCRole() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetTransWin() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetTxMode() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SignalFRSTX() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VOPEN : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP15A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP30A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VOPEN : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP15A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP30A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_FRSEVT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_HRSTDISC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_HRSTSENT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXERR : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXHRSTDET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXMSGEND : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXNE : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXORDDET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXOVR : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXIS : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGABT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGDISC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGSENT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXUND : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TYPEC_VSTATE_CC1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TYPEC_VSTATE_CC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TYPECEVT1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TYPECEVT2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_OPEN : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_VRA : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_VRD : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_OPEN : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_VRA : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_VRD : stm32g0xx_ll_ucpd.h
  • LL_UCPD_StructInit() : stm32g0xx_ll_ucpd.c
  • LL_UCPD_SYNC1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SYNC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SYNC3 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TxDMADisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TxDMAEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TXMODE_BIST_CARRIER2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TXMODE_CABLE_RESET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TXMODE_NORMAL : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC1Disable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC1Enable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC2Disable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC2Enable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_VconnDischargeDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_VconnDischargeEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WakeUpDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WakeUpEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WriteData() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WriteReg : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WriteTxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WriteTxPaySize() : stm32g0xx_ll_ucpd.h
  • LL_USART_ADDRESS_DETECT_4B : stm32g0xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32g0xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32g0xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32g0xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32g0xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32g0xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32g0xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32g0xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32g0xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_CM() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_UDR() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32g0xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32g0xx_ll_usart.h
  • LL_USART_ClockInit() : stm32g0xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32g0xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigFIFOsThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32g0xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_RXFFIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_RXNEIE_RXFNEIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_TXEIE_TXFNFIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_TXFEIE : stm32g0xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_RXFTIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_TCBGTIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_TXFTIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32g0xx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32g0xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32g0xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32g0xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32g0xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32g0xx_ll_usart.h
  • LL_USART_DeInit() : stm32g0xx_ll_usart.c
  • LL_USART_DIRECTION_NONE : stm32g0xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32g0xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32g0xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32g0xx_ll_usart.h
  • LL_USART_Disable() : stm32g0xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32g0xx_ll_usart.h
  • LL_USART_DisableFIFO() : stm32g0xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32g0xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RXFF() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RXFT() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RXNE_RXFNE() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TXE : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TXE_TXFNF() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TXFT() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32g0xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32g0xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32g0xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32g0xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSPISlave() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSPISlaveSelect() : stm32g0xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32g0xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32g0xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32g0xx_ll_usart.h
  • LL_USART_Enable() : stm32g0xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32g0xx_ll_usart.h
  • LL_USART_EnableFIFO() : stm32g0xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32g0xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RXFF() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RXFT() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RXNE_RXFNE() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TXE : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TXE_TXFNF() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TXFT() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32g0xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32g0xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32g0xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32g0xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSPISlave() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSPISlaveSelect() : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_2 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_4 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_8 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_3_4 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_7_8 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_8_8 : stm32g0xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32g0xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32g0xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32g0xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32g0xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32g0xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32g0xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32g0xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32g0xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32g0xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32g0xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32g0xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32g0xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32g0xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32g0xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32g0xx_ll_usart.h
  • LL_USART_GetParity() : stm32g0xx_ll_usart.h
  • LL_USART_GetPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_GetRXFIFOThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32g0xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32g0xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32g0xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32g0xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32g0xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32g0xx_ll_usart.h
  • LL_USART_GetTXFIFOThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32g0xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32g0xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32g0xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32g0xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32g0xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32g0xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32g0xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32g0xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_NECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_TCBGTCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_TXFECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_UDRCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32g0xx_ll_usart.h
  • LL_USART_Init() : stm32g0xx_ll_usart.c
  • LL_USART_IRDA_POWER_LOW : stm32g0xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABR() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFF() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFT() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE_RXFNE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE_TXFNF() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFT() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_UDR() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledFIFO() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFF() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFT() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE_RXFNE() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE_TXFNF() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFT() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSPISlave() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSPISlaveSelect() : stm32g0xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32g0xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32g0xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_FE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_NE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_PE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RXFF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RXFT : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RXNE_RXFNE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TC : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TCBGT : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TXE_TXFNF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TXFE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TXFT : stm32g0xx_ll_usart.h
  • LL_USART_ISR_UDR : stm32g0xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32g0xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32g0xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32g0xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32g0xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32g0xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32g0xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32g0xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32g0xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32g0xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32g0xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32g0xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32g0xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32g0xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV1 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV10 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV12 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV128 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV16 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV2 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV256 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV32 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV4 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV6 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV64 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV8 : stm32g0xx_ll_usart.h
  • LL_USART_ReadReg : stm32g0xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32g0xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32g0xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32g0xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32g0xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32g0xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32g0xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32g0xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32g0xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32g0xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32g0xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32g0xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32g0xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32g0xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32g0xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32g0xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32g0xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32g0xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32g0xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32g0xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32g0xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32g0xx_ll_usart.h
  • LL_USART_SetParity() : stm32g0xx_ll_usart.h
  • LL_USART_SetPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_SetRXFIFOThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32g0xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32g0xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32g0xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32g0xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32g0xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32g0xx_ll_usart.h
  • LL_USART_SetTXFIFOThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32g0xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32g0xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32g0xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32g0xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32g0xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32g0xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32g0xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32g0xx_ll_usart.h
  • LL_USART_StructInit() : stm32g0xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32g0xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32g0xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32g0xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32g0xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32g0xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32g0xx_ll_usart.h
  • LL_USART_WriteReg : stm32g0xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32g0xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_BGA100 : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_BGA64_N : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN32_GP : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN32_N : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN48_GP : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN48_N : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN64_GP : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN64_N : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFP100 : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFP80 : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP52 : stm32g0xx_ll_utils.h
  • LL_VREFBUF_Disable() : stm32g0xx_ll_system.h
  • LL_VREFBUF_DisableHIZ() : stm32g0xx_ll_system.h
  • LL_VREFBUF_Enable() : stm32g0xx_ll_system.h
  • LL_VREFBUF_EnableHIZ() : stm32g0xx_ll_system.h
  • LL_VREFBUF_GetTrimming() : stm32g0xx_ll_system.h
  • LL_VREFBUF_GetVoltageScaling() : stm32g0xx_ll_system.h
  • LL_VREFBUF_IsVREFReady() : stm32g0xx_ll_system.h
  • LL_VREFBUF_SetTrimming() : stm32g0xx_ll_system.h
  • LL_VREFBUF_SetVoltageScaling() : stm32g0xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE0 : stm32g0xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE1 : stm32g0xx_ll_system.h
  • LL_WWDG_CFR_EWI : stm32g0xx_ll_wwdg.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_128 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_16 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_32 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_64 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32g0xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32g0xx_ll_wwdg.h
  • LPM_L0 : stm32g0xx_hal_pcd.h
  • LPM_L1 : stm32g0xx_hal_pcd.h
  • LPM_L2 : stm32g0xx_hal_pcd.h
  • LPM_L3 : stm32g0xx_hal_pcd.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32g0xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32g0xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32g0xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32g0xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32g0xx_hal_lptim.h
  • LPTIM_Disable() : stm32g0xx_hal_lptim.c
  • LPTIM_EXTI_LINE_LPTIM1 : stm32g0xx_hal_lptim.h
  • LPTIM_EXTI_LINE_LPTIM2 : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32g0xx_hal_lptim.h
  • LPTIM_HandleTypeDef : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32g0xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32g0xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32g0xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32g0xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32g0xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32g0xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32g0xx_hal_lptim.h
  • LPTIM_IT_UP : stm32g0xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32g0xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32g0xx_hal_lptim.h
  • LPTIM_ResetCallback() : stm32g0xx_hal_lptim.c
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32g0xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32g0xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32g0xx_hal_lptim.h
  • LPTIM_WaitForFlag() : stm32g0xx_hal_lptim.c
  • LPUART_BRR_MASK : stm32g0xx_ll_lpuart.h
  • LPUART_BRR_MAX : stm32g0xx_hal_uart.c
  • LPUART_BRR_MIN : stm32g0xx_hal_uart.c
  • LPUART_BRR_MIN_VALUE : stm32g0xx_ll_lpuart.h
  • LPUART_LPUARTDIV_FREQ_MUL : stm32g0xx_ll_lpuart.h
  • LPUART_PRESCALER_TAB : stm32g0xx_ll_lpuart.h
  • LSCO_CLK_ENABLE : stm32g0xx_hal_rcc_ex.c
  • LSCO_GPIO_PORT : stm32g0xx_hal_rcc_ex.c
  • LSCO_PIN : stm32g0xx_hal_rcc_ex.c
  • LSE_STARTUP_TIMEOUT : stm32g0xx_hal_conf.h
  • LSE_VALUE : stm32g0xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • LSI_VALUE : stm32g0xx_hal_conf.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_NBYTE_SIZE : stm32g0xx_hal_i2c.c , stm32g0xx_hal_smbus.c
  • MCO1_CLK_ENABLE : stm32g0xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32g0xx_hal_rcc.c
  • MCO1_PIN : stm32g0xx_hal_rcc.c
  • MCO2_CLK_ENABLE : stm32g0xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32g0xx_hal_rcc.c
  • MCO2_PIN : stm32g0xx_hal_rcc.c
  • MODE_AF : stm32g0xx_hal_gpio.h
  • MODE_ANALOG : stm32g0xx_hal_gpio.h
  • MODE_INPUT : stm32g0xx_hal_gpio.h
  • MODE_OUTPUT : stm32g0xx_hal_gpio.h
  • MPU_ACCESS_BUFFERABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32g0xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32g0xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32g0xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32g0xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32g0xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32g0xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32g0xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32g0xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32g0xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32g0xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32g0xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32g0xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32g0xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32g0xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32g0xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32g0xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32g0xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32g0xx_hal_cortex.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_BOOT0_FROM_OB : stm32g0xx_hal_flash.h
  • OB_BOOT0_FROM_PIN : stm32g0xx_hal_flash.h
  • OB_BOOT1_SRAM : stm32g0xx_hal_flash.h
  • OB_BOOT1_SYSTEM : stm32g0xx_hal_flash.h
  • OB_BOOT_ENTRY_FORCED_FLASH : stm32g0xx_hal_flash.h
  • OB_BOOT_ENTRY_FORCED_NONE : stm32g0xx_hal_flash.h
  • OB_BOR_DISABLE : stm32g0xx_hal_flash.h
  • OB_BOR_ENABLE : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_FALLING_0 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_FALLING_1 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_FALLING_2 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_FALLING_3 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_RISING_0 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_RISING_1 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_RISING_2 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_RISING_3 : stm32g0xx_hal_flash.h
  • OB_DUAL_BANK_BASE : stm32g0xx_hal_flash.h
  • OB_DUAL_BANK_VALUE : stm32g0xx_hal_flash.h
  • OB_IRH_DISABLE : stm32g0xx_hal_flash.h
  • OB_IRH_ENABLE : stm32g0xx_hal_flash.h
  • OB_IWDG_HW : stm32g0xx_hal_flash.h
  • OB_IWDG_STDBY_FREEZE : stm32g0xx_hal_flash.h
  • OB_IWDG_STDBY_RUN : stm32g0xx_hal_flash.h
  • OB_IWDG_STOP_FREEZE : stm32g0xx_hal_flash.h
  • OB_IWDG_STOP_RUN : stm32g0xx_hal_flash.h
  • OB_IWDG_SW : stm32g0xx_hal_flash.h
  • OB_nBOOT0_RESET : stm32g0xx_hal_flash.h
  • OB_nBOOT0_SET : stm32g0xx_hal_flash.h
  • OB_PCROP_RDP_ERASE : stm32g0xx_hal_flash.h
  • OB_PCROP_RDP_NOT_ERASE : stm32g0xx_hal_flash.h
  • OB_PCROP_ZONE2_A : stm32g0xx_hal_flash.h
  • OB_PCROP_ZONE2_B : stm32g0xx_hal_flash.h
  • OB_PCROP_ZONE_A : stm32g0xx_hal_flash.h
  • OB_PCROP_ZONE_B : stm32g0xx_hal_flash.h
  • OB_RDP_LEVEL_0 : stm32g0xx_hal_flash.h
  • OB_RDP_LEVEL_1 : stm32g0xx_hal_flash.h
  • OB_RDP_LEVEL_2 : stm32g0xx_hal_flash.h
  • OB_RESET_MODE_GPIO : stm32g0xx_hal_flash.h
  • OB_RESET_MODE_INPUT_ONLY : stm32g0xx_hal_flash.h
  • OB_RESET_MODE_INPUT_OUTPUT : stm32g0xx_hal_flash.h
  • OB_SHUTDOWN_NORST : stm32g0xx_hal_flash.h
  • OB_SHUTDOWN_RST : stm32g0xx_hal_flash.h
  • OB_SRAM_PARITY_DISABLE : stm32g0xx_hal_flash.h
  • OB_SRAM_PARITY_ENABLE : stm32g0xx_hal_flash.h
  • OB_STANDBY_NORST : stm32g0xx_hal_flash.h
  • OB_STANDBY_RST : stm32g0xx_hal_flash.h
  • OB_STOP_NORST : stm32g0xx_hal_flash.h
  • OB_STOP_RST : stm32g0xx_hal_flash.h
  • OB_USER_ALL : stm32g0xx_hal_flash.h
  • OB_USER_BANK_SWAP : stm32g0xx_hal_flash.h
  • OB_USER_BOR_EN : stm32g0xx_hal_flash.h
  • OB_USER_BOR_LEV : stm32g0xx_hal_flash.h
  • OB_USER_DUAL_BANK : stm32g0xx_hal_flash.h
  • OB_USER_DUALBANK_DISABLE : stm32g0xx_hal_flash.h
  • OB_USER_DUALBANK_ENABLE : stm32g0xx_hal_flash.h
  • OB_USER_DUALBANK_SWAP_DISABLE : stm32g0xx_hal_flash.h
  • OB_USER_DUALBANK_SWAP_ENABLE : stm32g0xx_hal_flash.h
  • OB_USER_INPUT_RESET_HOLDER : stm32g0xx_hal_flash.h
  • OB_USER_IWDG_STDBY : stm32g0xx_hal_flash.h
  • OB_USER_IWDG_STOP : stm32g0xx_hal_flash.h
  • OB_USER_IWDG_SW : stm32g0xx_hal_flash.h
  • OB_USER_nBOOT0 : stm32g0xx_hal_flash.h
  • OB_USER_nBOOT1 : stm32g0xx_hal_flash.h
  • OB_USER_nBOOT_SEL : stm32g0xx_hal_flash.h
  • OB_USER_NRST_MODE : stm32g0xx_hal_flash.h
  • OB_USER_nRST_SHDW : stm32g0xx_hal_flash.h
  • OB_USER_nRST_STDBY : stm32g0xx_hal_flash.h
  • OB_USER_nRST_STOP : stm32g0xx_hal_flash.h
  • OB_USER_RAM_PARITY_CHECK : stm32g0xx_hal_flash.h
  • OB_USER_WWDG_SW : stm32g0xx_hal_flash.h
  • OB_WRPAREA_ZONE2_A : stm32g0xx_hal_flash.h
  • OB_WRPAREA_ZONE2_B : stm32g0xx_hal_flash.h
  • OB_WRPAREA_ZONE_A : stm32g0xx_hal_flash.h
  • OB_WRPAREA_ZONE_B : stm32g0xx_hal_flash.h
  • OB_WWDG_HW : stm32g0xx_hal_flash.h
  • OB_WWDG_SW : stm32g0xx_hal_flash.h
  • OC1Config() : stm32g0xx_ll_tim.c
  • OC2Config() : stm32g0xx_ll_tim.c
  • OC3Config() : stm32g0xx_ll_tim.c
  • OC4Config() : stm32g0xx_ll_tim.c
  • OC5Config() : stm32g0xx_ll_tim.c
  • OC6Config() : stm32g0xx_ll_tim.c
  • OCREF_CLEAR_SELECT_Msk : stm32g0xx_ll_tim.h
  • OCREF_CLEAR_SELECT_Pos : stm32g0xx_ll_tim.h
  • OFFSET_TAB_CCMRx : stm32g0xx_ll_tim.h
  • OPTIONBYTE_ALL : stm32g0xx_hal_flash.h
  • OPTIONBYTE_PCROP : stm32g0xx_hal_flash.h
  • OPTIONBYTE_RDP : stm32g0xx_hal_flash.h
  • OPTIONBYTE_SEC : stm32g0xx_hal_flash.h
  • OPTIONBYTE_USER : stm32g0xx_hal_flash.h
  • OPTIONBYTE_WRP : stm32g0xx_hal_flash.h
  • OUTPUT_OD : stm32g0xx_hal_gpio.h
  • OUTPUT_PP : stm32g0xx_hal_gpio.h
  • OUTPUT_TYPE : stm32g0xx_hal_gpio.h
  • OUTPUT_TYPE_Pos : stm32g0xx_hal_gpio.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PACKAGE_BASE_ADDRESS : stm32g0xx_ll_utils.h
  • pADC_CallbackTypeDef : stm32g0xx_hal_adc.h
  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32g0xx_hal_pcd.h
  • PCD_BCD_CONTACT_DETECTION : stm32g0xx_hal_pcd.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32g0xx_hal_pcd.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32g0xx_hal_pcd.h
  • PCD_BCD_ERROR : stm32g0xx_hal_pcd.h
  • PCD_BCD_MsgTypeDef : stm32g0xx_hal_pcd.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_BULK_EP_DBUF : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32g0xx_hal_pcd.h
  • PCD_DBL_BUF : stm32g0xx_hal_pcd.h
  • PCD_ENDP0 : stm32g0xx_hal_pcd.h
  • PCD_ENDP1 : stm32g0xx_hal_pcd.h
  • PCD_ENDP2 : stm32g0xx_hal_pcd.h
  • PCD_ENDP3 : stm32g0xx_hal_pcd.h
  • PCD_ENDP4 : stm32g0xx_hal_pcd.h
  • PCD_ENDP5 : stm32g0xx_hal_pcd.h
  • PCD_ENDP6 : stm32g0xx_hal_pcd.h
  • PCD_ENDP7 : stm32g0xx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32g0xx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32g0xx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32g0xx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32g0xx_hal_pcd.h
  • PCD_EP_ISR_Handler() : stm32g0xx_hal_pcd.c
  • PCD_EPTypeDef : stm32g0xx_hal_pcd.h
  • PCD_FREE_USER_BUFFER : stm32g0xx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32g0xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT() : stm32g0xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT() : stm32g0xx_hal_pcd.h
  • PCD_GET_EP_RX_CNT() : stm32g0xx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32g0xx_hal_pcd.h
  • PCD_HandleTypeDef : stm32g0xx_hal_pcd.h
  • PCD_InitTypeDef : stm32g0xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32g0xx_hal_pcd.h
  • PCD_LPM_L1_ACTIVE : stm32g0xx_hal_pcd.h
  • PCD_LPM_MsgTypeDef : stm32g0xx_hal_pcd.h
  • PCD_LPM_StateTypeDef : stm32g0xx_hal_pcd.h
  • PCD_MAX : stm32g0xx_hal_pcd.c
  • PCD_MIN : stm32g0xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32g0xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32g0xx_hal_pcd.h
  • PCD_PHY_UTMI : stm32g0xx_hal_pcd.h
  • PCD_RX_DTOG : stm32g0xx_hal_pcd.h
  • PCD_SET_BULK_EP_DBUF : stm32g0xx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32g0xx_hal_pcd.h
  • PCD_SNG_BUF : stm32g0xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32g0xx_hal_pcd.h
  • PCD_StateTypeDef : stm32g0xx_hal_pcd.h
  • PCD_TX_DTOG : stm32g0xx_hal_pcd.h
  • PCD_TypeDef : stm32g0xx_hal_pcd.h
  • pCEC_CallbackTypeDef : stm32g0xx_hal_cec.h
  • pCEC_RxCallbackTypeDef : stm32g0xx_hal_cec.h
  • pCOMP_CallbackTypeDef : stm32g0xx_hal_comp.h
  • pCRYP_CallbackTypeDef : stm32g0xx_hal_cryp.h
  • pDAC_CallbackTypeDef : stm32g0xx_hal_dac.h
  • pFDCAN_CallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_ErrorStatusCallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_RxFifo0CallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_RxFifo1CallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_TxBufferAbortCallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_TxBufferCompleteCallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_TxEventFifoCallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFlash : stm32g0xx_hal_flash.c , stm32g0xx_hal_flash.h
  • pHCD_CallbackTypeDef : stm32g0xx_hal_hcd.h
  • pHCD_HC_NotifyURBChangeCallbackTypeDef : stm32g0xx_hal_hcd.h
  • pI2C_AddrCallbackTypeDef : stm32g0xx_hal_i2c.h
  • pI2C_CallbackTypeDef : stm32g0xx_hal_i2c.h
  • pI2S_CallbackTypeDef : stm32g0xx_hal_i2s.h
  • pIRDA_CallbackTypeDef : stm32g0xx_hal_irda.h
  • PLL_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c , stm32g0xx_hal_rcc_ex.c
  • PLLSOURCE_NONE : stm32g0xx_hal_rcc.c
  • pLPTIM_CallbackTypeDef : stm32g0xx_hal_lptim.h
  • PMA_BLOCKS : stm32g0xx_hal_hcd.h
  • pPCD_BcdCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_CallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_DataInStageCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_DataOutStageCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_IsoInIncpltCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_IsoOutIncpltCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_LpmCallbackTypeDef : stm32g0xx_hal_pcd.h
  • PREFETCH_ENABLE : stm32g0xx_hal_conf.h
  • pRNG_CallbackTypeDef : stm32g0xx_hal_rng.h
  • pRNG_ReadyDataCallbackTypeDef : stm32g0xx_hal_rng.h
  • pRTC_CallbackTypeDef : stm32g0xx_hal_rtc.h
  • pSMARTCARD_CallbackTypeDef : stm32g0xx_hal_smartcard.h
  • pSMBUS_AddrCallbackTypeDef : stm32g0xx_hal_smbus.h
  • pSMBUS_CallbackTypeDef : stm32g0xx_hal_smbus.h
  • pSPI_CallbackTypeDef : stm32g0xx_hal_spi.h
  • pTIM_CallbackTypeDef : stm32g0xx_hal_tim.h
  • pUART_CallbackTypeDef : stm32g0xx_hal_uart.h
  • pUART_RxEventCallbackTypeDef : stm32g0xx_hal_uart.h
  • pUSART_CallbackTypeDef : stm32g0xx_hal_usart.h
  • PVD_FALLING_EDGE : stm32g0xx_hal_pwr_ex.c
  • PVD_MODE_EVT : stm32g0xx_hal_pwr_ex.c
  • PVD_MODE_IT : stm32g0xx_hal_pwr_ex.c
  • PVD_RISING_EDGE : stm32g0xx_hal_pwr_ex.c
  • PVM_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • PVM_MODE_EVT : stm32g0xx_hal_pwr_ex.h
  • PVM_MODE_IT : stm32g0xx_hal_pwr_ex.h
  • PVM_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVD : stm32g0xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM : stm32g0xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32g0xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM : stm32g0xx_hal_pwr_ex.h
  • PWR_FLAG_FLASH_READY : stm32g0xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32g0xx_hal_pwr.h
  • PWR_FLAG_PVMO_USB : stm32g0xx_hal_pwr.h
  • PWR_FLAG_PVMOUSB : stm32g0xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPF : stm32g0xx_hal_pwr.h
  • PWR_FLAG_REGLPS : stm32g0xx_hal_pwr.h
  • PWR_FLAG_SB : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF1 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF2 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF3 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF4 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF5 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF6 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUFI : stm32g0xx_hal_pwr.h
  • PWR_FLASHPD_LPRUN : stm32g0xx_hal_pwr_ex.h
  • PWR_FLASHPD_LPSLEEP : stm32g0xx_hal_pwr_ex.h
  • PWR_FLASHPD_STOP : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_A : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_B : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_0 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_1 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_10 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_11 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_12 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_13 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_14 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_15 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_2 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_3 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_4 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_6 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_7 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_8 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_9 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_C : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_D : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_E : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_F : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_PIN_NB : stm32g0xx_hal_pwr_ex.c
  • PWR_LOWPOWERMODE_SHUTDOWN : stm32g0xx_hal_pwr.h
  • PWR_LOWPOWERMODE_STANDBY : stm32g0xx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP0 : stm32g0xx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP1 : stm32g0xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32g0xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32g0xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_RISING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_RISING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_NORMAL : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_0 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_1 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_2 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_3 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_4 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_6 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_7 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_0 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_1 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_2 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_3 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_4 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_6 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_0 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_1 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_2 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_3 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_4 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_6 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_NORMAL : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_USB : stm32g0xx_hal_pwr_ex.h
  • PWR_REGLPF_SETTING_DELAY_6_US : stm32g0xx_hal_pwr_ex.c
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32g0xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32g0xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32g0xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32g0xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32g0xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32g0xx_hal_pwr.h
  • PWR_VOSF_SETTING_DELAY_6_US : stm32g0xx_hal_pwr_ex.c
  • PWR_WAKEUP_PIN1 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN1_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN1_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN2 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN2_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN2_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN3 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN3_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN3_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN4 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN4_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN4_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN5 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN5_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN5_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN6 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN6_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN6_LOW : stm32g0xx_hal_pwr.h
  • PWR_WUP_POLARITY_SHIFT : stm32g0xx_hal_pwr.h
  • pWWDG_CallbackTypeDef : stm32g0xx_hal_wwdg.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_ADCCLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLLADC : stm32g0xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_HSI_DIV488 : stm32g0xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_ALL : stm32g0xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32g0xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32g0xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32g0xx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_GPIO : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32g0xx_hal_rcc_ex.h
  • RCC_DBP_TIMEOUT_VALUE : stm32g0xx_hal_rcc.h
  • RCC_FDCANCLKSOURCE_HSE : stm32g0xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_FLAG_HSERDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_LSECSSD : stm32g0xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32g0xx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_PWRRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32g0xx_hal_rcc.h
  • RCC_GetHCLKClockFreq() : stm32g0xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32g0xx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32g0xx_ll_rcc.c
  • RCC_HCLK_DIV1 : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32g0xx_hal_rcc.h
  • RCC_HSE_OFF : stm32g0xx_hal_rcc.h
  • RCC_HSE_ON : stm32g0xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32g0xx_hal_rcc.h
  • RCC_HSI48_ON : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV1 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV128 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV16 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV32 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV64 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_HSI_OFF : stm32g0xx_hal_rcc.h
  • RCC_HSI_ON : stm32g0xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32g0xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S1CLKSOURCE_EXT : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S1CLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S1CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S2CLKSOURCE_EXT : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S2CLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S2CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32g0xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32g0xx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32g0xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32g0xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32g0xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32g0xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32g0xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32g0xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART2CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART2CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART2CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32g0xx_hal_rcc.h
  • RCC_LSE_OFF : stm32g0xx_hal_rcc.h
  • RCC_LSE_ON : stm32g0xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32g0xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32g0xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32g0xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32g0xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32g0xx_hal_rcc.h
  • RCC_LSI_OFF : stm32g0xx_hal_rcc.h
  • RCC_LSI_ON : stm32g0xx_hal_rcc.h
  • RCC_MCO : stm32g0xx_hal_rcc.h
  • RCC_MCO1 : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLPCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLQCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_RTC_WKUP : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_RTCCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_SYSCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_1 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_1024 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_128 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_16 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_2 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_256 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_32 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_4 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_512 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_64 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_8 : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSE : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSI : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSI48 : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_LSE : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_LSI : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_NOCLOCK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLPCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLQCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_RTC_WKUP : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_RTCCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_SYSCLK : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_1024 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_128 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_16 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_256 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_32 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_512 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_64 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32g0xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CEC : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FDCAN : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM15 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32g0xx_hal_rcc_ex.h
  • RCC_PLL_GetFreqDomain_ADC() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_FDCAN() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_I2S1() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_I2S2() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_RNG() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_TIM1() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_TIM15() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_USB() : stm32g0xx_ll_rcc.c
  • RCC_PLL_NONE : stm32g0xx_hal_rcc.h
  • RCC_PLL_OFF : stm32g0xx_hal_rcc.h
  • RCC_PLL_ON : stm32g0xx_hal_rcc.h
  • RCC_PLL_OSCSOURCE_CONFIG : stm32g0xx_hal_rcc.c
  • RCC_PLLM_DIV1 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV3 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV5 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV6 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV7 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV10 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV11 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV12 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV13 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV14 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV15 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV16 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV17 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV18 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV19 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV20 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV21 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV22 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV23 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV24 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV25 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV26 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV27 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV28 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV29 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV3 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV30 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV31 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV32 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV5 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV7 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV9 : stm32g0xx_hal_rcc.h
  • RCC_PLLPCLK : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV3 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV5 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV6 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV7 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_PLLQCLK : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV3 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV5 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV6 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV7 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_PLLRCLK : stm32g0xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32g0xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32g0xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_ALL : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_IWDG : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_LPWR : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_OBL : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_PIN : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_PWR : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_SW : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_WWDG : stm32g0xx_hal_rcc.h
  • RCC_RNGCLK_DIV1 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLK_DIV2 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLK_DIV4 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLK_DIV8 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_HSI_DIV8 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_NONE : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32g0xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32g0xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32g0xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NONE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV1 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_LSE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_LSI : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_LSE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_LSI : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32g0xx_hal_rcc.h
  • RCC_TIM15CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_TIM15CLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_TIM1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_TIM1CLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSE : stm32g0xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32g0xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RNG_CED_DISABLE : stm32g0xx_hal_rng.h
  • RNG_CED_ENABLE : stm32g0xx_hal_rng.h
  • RNG_FLAG_CECS : stm32g0xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32g0xx_hal_rng.h
  • RNG_FLAG_SECS : stm32g0xx_hal_rng.h
  • RNG_HandleTypeDef : stm32g0xx_hal_rng.h
  • RNG_IT_CEI : stm32g0xx_hal_rng.h
  • RNG_IT_DRDY : stm32g0xx_hal_rng.h
  • RNG_IT_SEI : stm32g0xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32g0xx_hal_rng.c
  • RTC_ALARM_A : stm32g0xx_hal_rtc.h
  • RTC_ALARM_B : stm32g0xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32g0xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32g0xx_hal_rtc.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32g0xx_ll_rtc.c
  • RTC_Bcd2ToByte() : stm32g0xx_hal_rtc.c
  • RTC_BKP_DR0 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_NUMBER : stm32g0xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32g0xx_hal_rtc.c
  • RTC_CALIBOUTPUT_1HZ : stm32g0xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32g0xx_hal_rtc_ex.h
  • RTC_CLEAR_ALRAF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_ALRBF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_ITSF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_TSF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_TSOVF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_WUTF : stm32g0xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32g0xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32g0xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32g0xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32g0xx_hal_rtc.h
  • RTC_EnterInitMode() : stm32g0xx_hal_rtc.c
  • RTC_ExitInitMode() : stm32g0xx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32g0xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_EVENT : stm32g0xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_TIMESTAMP_EVENT : stm32g0xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32g0xx_hal_rtc.h
  • RTC_FLAG_INT_TAMP3 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP4 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP5 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP6 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMPALL : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_ITSF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_MASK : stm32g0xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_TAMP1 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP2 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP3 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_TAMPALL : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_TSF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32g0xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32g0xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32g0xx_hal_rtc.h
  • RTC_HandleTypeDef : stm32g0xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32g0xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32g0xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32g0xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32g0xx_hal_rtc.h
  • RTC_INIT_MASK : stm32g0xx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32g0xx_ll_rtc.c
  • RTC_INT_TAMPER_3 : stm32g0xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_4 : stm32g0xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_5 : stm32g0xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_6 : stm32g0xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_ALL : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_ALRA : stm32g0xx_hal_rtc.h
  • RTC_IT_ALRB : stm32g0xx_hal_rtc.h
  • RTC_IT_INT_TAMP3 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP4 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP5 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP6 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMPALL : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TAMP1 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TAMP2 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TAMP3 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TAMPALL : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TS : stm32g0xx_hal_rtc.h
  • RTC_IT_WUT : stm32g0xx_hal_rtc.h
  • RTC_LL_INIT_MASK : stm32g0xx_ll_rtc.h
  • RTC_LL_RSF_MASK : stm32g0xx_ll_rtc.h
  • RTC_MONTH_APRIL : stm32g0xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32g0xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32g0xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32g0xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32g0xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32g0xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32g0xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32g0xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32g0xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32g0xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32g0xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32g0xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32g0xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32g0xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32g0xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32g0xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32g0xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_ALARMB : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_DISABLE : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_NONE : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_ON : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_TAMPER : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32g0xx_hal_rtc.h
  • RTC_RSF_MASK : stm32g0xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32g0xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32g0xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32g0xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32g0xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32g0xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32g0xx_ll_rtc.c
  • RTC_TAMPER_1 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_ALL : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32g0xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32g0xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32g0xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32g0xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32g0xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32g0xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32g0xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32g0xx_ll_rtc.h
  • RX_FIFO_DEPTH : stm32g0xx_hal_uart_ex.c , stm32g0xx_hal_usart_ex.c , stm32g0xx_hal_smartcard_ex.c
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SHIFT_TAB_CCxP : stm32g0xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32g0xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32g0xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32g0xx_ll_tim.h
  • SLAVE_ADDR_MSK : stm32g0xx_hal_i2c.c
  • SLAVE_ADDR_SHIFT : stm32g0xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_AdvFeatureConfig() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_CLEAR_EOBF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ClockSourceTypeDef : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CR_MASK : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CR_POS : stm32g0xx_hal_smartcard.h
  • SMARTCARD_DMAAbortOnError() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_FIFOMODE_DISABLE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_BUSY : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFNE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFNF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_HandleTypeDef : stm32g0xx_hal_smartcard.h
  • SMARTCARD_InitCallbacksToDefault() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_ISR_MASK : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ISR_POS : stm32g0xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32g0xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFNE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFNF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32g0xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32g0xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32g0xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32g0xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV1 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV10 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV12 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV128 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV16 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV2 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV256 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV32 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV4 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV6 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV64 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV8 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32g0xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RxISR() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_RxISR_FIFOEN() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_TC : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32g0xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32g0xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TxISR() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_TxISR_FIFOEN() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32g0xx_hal_smartcard.h
  • SMARTCARDEx_SetNbDataToProcess() : stm32g0xx_hal_smartcard_ex.c
  • SMBUS_ADDRESSINGMODE_10BIT : stm32g0xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32g0xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32g0xx_hal_smbus.h
  • SMBUS_CHECK_IT_SOURCE : stm32g0xx_hal_smbus.h
  • SMBUS_ConvertOtherXferOptions() : stm32g0xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32g0xx_hal_smbus.c
  • SMBUS_DUALADDRESS_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_Enable_IRQ() : stm32g0xx_hal_smbus.c
  • SMBUS_FASTMODEPLUS_I2C1 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C2 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C3 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PA10 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PA9 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB6 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB7 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB8 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB9 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32g0xx_hal_smbus.h
  • SMBUS_FIRST_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32g0xx_hal_smbus.h
  • SMBUS_Flush_TXDR() : stm32g0xx_hal_smbus.c
  • SMBUS_FMP_NOT_SUPPORTED : stm32g0xx_hal_smbus_ex.h
  • SMBUS_GENERALCALL_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32g0xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32g0xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32g0xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32g0xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32g0xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32g0xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32g0xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_HandleTypeDef : stm32g0xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32g0xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32g0xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_RX : stm32g0xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_TX : stm32g0xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32g0xx_hal_smbus.h
  • SMBUS_ITErrorHandler() : stm32g0xx_hal_smbus.c
  • SMBUS_LAST_FRAME_NO_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_Master_ISR() : stm32g0xx_hal_smbus.c
  • SMBUS_NEXT_FRAME : stm32g0xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32g0xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32g0xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32g0xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32g0xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32g0xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32g0xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32g0xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_Slave_ISR() : stm32g0xx_hal_smbus.c
  • SMBUS_SOFTEND_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_TransferConfig() : stm32g0xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32g0xx_hal_smbus.c
  • SPI_1LINE_RX : stm32g0xx_hal_spi.h
  • SPI_1LINE_TX : stm32g0xx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32g0xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32g0xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32g0xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32g0xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32g0xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32g0xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32g0xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32g0xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32g0xx_hal_spi.h
  • SPI_CHECK_FLAG : stm32g0xx_hal_spi.h
  • SPI_CHECK_IT_SOURCE : stm32g0xx_hal_spi.h
  • SPI_CloseRx_ISR() : stm32g0xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32g0xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32g0xx_hal_spi.c
  • SPI_CR1_CLEAR_MASK : stm32g0xx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32g0xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32g0xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32g0xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32g0xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32g0xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32g0xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32g0xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32g0xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32g0xx_hal_spi.h
  • SPI_DMAAbortOnError() : stm32g0xx_hal_spi.c
  • SPI_DMAError() : stm32g0xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32g0xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32g0xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32g0xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32g0xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32g0xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32g0xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32g0xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32g0xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32g0xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32g0xx_hal_spi.c
  • SPI_FIFO_SIZE : stm32g0xx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32g0xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32g0xx_hal_spi.h
  • SPI_FLAG_BSY : stm32g0xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32g0xx_hal_spi.h
  • SPI_FLAG_FRE : stm32g0xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32g0xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32g0xx_hal_spi.h
  • SPI_FLAG_MASK : stm32g0xx_hal_spi.h
  • SPI_FLAG_MODF : stm32g0xx_hal_spi.h
  • SPI_FLAG_OVR : stm32g0xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32g0xx_hal_spi.h
  • SPI_FLAG_TXE : stm32g0xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32g0xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32g0xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32g0xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32g0xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32g0xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32g0xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32g0xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32g0xx_hal_spi.h
  • SPI_HandleTypeDef : stm32g0xx_hal_spi.h
  • SPI_IT_ERR : stm32g0xx_hal_spi.h
  • SPI_IT_RXNE : stm32g0xx_hal_spi.h
  • SPI_IT_TXE : stm32g0xx_hal_spi.h
  • SPI_MODE_MASTER : stm32g0xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32g0xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32g0xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32g0xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32g0xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32g0xx_hal_spi.h
  • SPI_NSS_SOFT : stm32g0xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32g0xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32g0xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32g0xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32g0xx_hal_spi.h
  • SPI_RESET_CRC : stm32g0xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32g0xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32g0xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32g0xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32g0xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32g0xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32g0xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32g0xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32g0xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32g0xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32g0xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32g0xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32g0xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32g0xx_hal_spi.c
  • SRAMCAN_FLE_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLE_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLESA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLS_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLS_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLSSA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF0_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF0_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF0SA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF1_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF1_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF1SA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TEF_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TEF_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TEFSA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TFQ_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TFQ_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TFQSA : stm32g0xx_hal_fdcan.c
  • SYSCFG_BOOT_MAINFLASH : stm32g0xx_hal.h
  • SYSCFG_BOOT_SRAM : stm32g0xx_hal.h
  • SYSCFG_BOOT_SYSTEMFLASH : stm32g0xx_hal.h
  • SYSCFG_BREAK_ECC : stm32g0xx_hal.h
  • SYSCFG_BREAK_LOCKUP : stm32g0xx_hal.h
  • SYSCFG_BREAK_PVD : stm32g0xx_hal.h
  • SYSCFG_BREAK_SP : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA1 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA13 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA3 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA5 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA6 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PB0 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PB1 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PB2 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_I2C1 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_I2C2 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_I2C3 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PA10 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PA9 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32g0xx_hal.h
  • SYSCFG_REMAP_PA11 : stm32g0xx_hal.h
  • SYSCFG_REMAP_PA12 : stm32g0xx_hal.h
  • SYSCFG_UCPD1_STROBE : stm32g0xx_hal.h
  • SYSCFG_UCPD2_STROBE : stm32g0xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32g0xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32g0xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32g0xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32g0xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32g0xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32g0xx_hal_cortex.h
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
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  • Variables
  • Typedefs
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TEMPSENSOR_CAL1_ADDR : stm32g0xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32g0xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32g0xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32g0xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32g0xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32g0xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32g0xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32g0xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32g0xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32g0xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_BREAK2_AFMODE_BIDIRECTIONAL : stm32g0xx_hal_tim.h
  • TIM_BREAK2_AFMODE_INPUT : stm32g0xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32g0xx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32g0xx_hal_tim.h
  • TIM_BREAK_AFMODE_BIDIRECTIONAL : stm32g0xx_hal_tim.h
  • TIM_BREAK_AFMODE_INPUT : stm32g0xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32g0xx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32g0xx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32g0xx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR : stm32g0xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUT_REARM_TIMEOUT : stm32g0xx_hal_tim_ex.c
  • TIM_BREAKINPUTSOURCE_BKIN : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32g0xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32g0xx_hal_tim.h
  • TIM_CALC_DTS : stm32g0xx_ll_tim.h
  • TIM_CCDMAREQUEST_CC : stm32g0xx_hal_tim.h
  • TIM_CCDMAREQUEST_UPDATE : stm32g0xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32g0xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32g0xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32g0xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32g0xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32g0xx_hal_tim.c
  • TIM_CCxN_DISABLE : stm32g0xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32g0xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32g0xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_5 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_6 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_GET : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_SET : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_SET_ALL : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_STATE_GET : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_STATE_SET : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_STATE_SET_ALL : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP1 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP2 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP3 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32g0xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32g0xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32g0xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32g0xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR7 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32g0xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32g0xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32g0xx_hal_tim.h
  • TIM_DMA_CC1 : stm32g0xx_hal_tim.h
  • TIM_DMA_CC2 : stm32g0xx_hal_tim.h
  • TIM_DMA_CC3 : stm32g0xx_hal_tim.h
  • TIM_DMA_CC4 : stm32g0xx_hal_tim.h
  • TIM_DMA_COM : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32g0xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32g0xx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_AF2 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32g0xx_hal_tim.h
  • TIM_DMABASE_DMAR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_OR1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32g0xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_SR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_TISEL : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMACaptureCplt() : stm32g0xx_hal_tim.c
  • TIM_DMACaptureHalfCplt() : stm32g0xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32g0xx_hal_tim.c
  • TIM_DMADelayPulseHalfCplt() : stm32g0xx_hal_tim.c
  • TIM_DMADelayPulseNCplt() : stm32g0xx_hal_tim_ex.c
  • TIM_DMAError() : stm32g0xx_hal_tim.c
  • TIM_DMAErrorCCxN() : stm32g0xx_hal_tim_ex.c
  • TIM_DMAPeriodElapsedCplt() : stm32g0xx_hal_tim.c
  • TIM_DMAPeriodElapsedHalfCplt() : stm32g0xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32g0xx_hal_tim.c
  • TIM_DMATriggerHalfCplt() : stm32g0xx_hal_tim.c
  • TIM_ENCODERINPUTPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32g0xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32g0xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32g0xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_ETRPOLARITY_INVERTED : stm32g0xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32g0xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32g0xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32g0xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32g0xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32g0xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32g0xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32g0xx_hal_tim.h
  • TIM_FLAG_COM : stm32g0xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32g0xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32g0xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32g0xx_ll_tim.h
  • TIM_GROUPCH5_NONE : stm32g0xx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32g0xx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32g0xx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32g0xx_hal_tim.h
  • TIM_HandleTypeDef : stm32g0xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32g0xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32g0xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32g0xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32g0xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32g0xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32g0xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32g0xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32g0xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32g0xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_IT_BREAK : stm32g0xx_hal_tim.h
  • TIM_IT_CC1 : stm32g0xx_hal_tim.h
  • TIM_IT_CC2 : stm32g0xx_hal_tim.h
  • TIM_IT_CC3 : stm32g0xx_hal_tim.h
  • TIM_IT_CC4 : stm32g0xx_hal_tim.h
  • TIM_IT_COM : stm32g0xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_IT_UPDATE : stm32g0xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32g0xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32g0xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32g0xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32g0xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32g0xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32g0xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32g0xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32g0xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32g0xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32g0xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32g0xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32g0xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32g0xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32g0xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32g0xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32g0xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32g0xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32g0xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32g0xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32g0xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32g0xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32g0xx_hal_tim.h
  • TIM_POSITION_BRK_SOURCE : stm32g0xx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32g0xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32g0xx_hal_tim.h
  • TIM_ResetCallback() : stm32g0xx_hal_tim.c
  • TIM_SET_CAPTUREPOLARITY : stm32g0xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_SlaveTimer_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32g0xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TI1SELECTION_CH1 : stm32g0xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32g0xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32g0xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TIM14_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM14_TI1_HSE_32 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM14_TI1_MCO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM14_TI1_MCO2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM14_TI1_RTC : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM2_CH1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM3_CH1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM2_CH2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM3_CH2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSE : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSI : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_MCO2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RTC_WAKEUP : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSE_32 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSI48 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI2_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI3_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI3_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_LSE : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_MCO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_MCO2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI3_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI3_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI3_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI3_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_ETR_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI3_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI3_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32g0xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32g0xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32g0xx_hal_tim.h
  • TIM_TRGO_RESET : stm32g0xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32g0xx_hal_tim.h
  • TIM_TS_ETRF : stm32g0xx_hal_tim.h
  • TIM_TS_ITR0 : stm32g0xx_hal_tim.h
  • TIM_TS_ITR1 : stm32g0xx_hal_tim.h
  • TIM_TS_ITR2 : stm32g0xx_hal_tim.h
  • TIM_TS_ITR3 : stm32g0xx_hal_tim.h
  • TIM_TS_ITR7 : stm32g0xx_hal_tim.h
  • TIM_TS_NONE : stm32g0xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32g0xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32g0xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32g0xx_hal_tim.h
  • TIM_UIFREMAP_DISABLE : stm32g0xx_hal_tim.h
  • TIM_UIFREMAP_ENABLE : stm32g0xx_hal_tim.h
  • TIMEOUT : stm32g0xx_hal_lptim.c
  • TIMEOUT_DAC_CALIBCONFIG : stm32g0xx_hal_dac.c
  • TIMEx_DMACommutationCplt() : stm32g0xx_hal_tim_ex.c
  • TIMEx_DMACommutationHalfCplt() : stm32g0xx_hal_tim_ex.c
  • TIMING_CLEAR_MASK : stm32g0xx_hal_i2c.c , stm32g0xx_hal_smbus.c
  • TIMx_AF1_BKINP : stm32g0xx_ll_tim.h
  • TIMx_AF1_ETRSEL : stm32g0xx_ll_tim.h
  • TIMx_OR1_OCREF_CLR : stm32g0xx_hal_tim.c
  • TRIGGER_FALLING : stm32g0xx_hal_gpio.h
  • TRIGGER_MODE : stm32g0xx_hal_gpio.h
  • TRIGGER_MODE_Pos : stm32g0xx_hal_gpio.h
  • TRIGGER_RISING : stm32g0xx_hal_gpio.h
  • TX_FIFO_DEPTH : stm32g0xx_hal_smartcard_ex.c , stm32g0xx_hal_usart_ex.c , stm32g0xx_hal_uart_ex.c
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ADDRESS_DETECT_4B : stm32g0xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32g0xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32g0xx_hal_uart.h
  • UART_AdvFeatureConfig() : stm32g0xx_hal_uart.c
  • UART_AUTOBAUD_REQUEST : stm32g0xx_hal_uart.h
  • UART_BRR_MAX : stm32g0xx_hal_uart.c
  • UART_BRR_MIN : stm32g0xx_hal_uart.c
  • UART_CheckIdleState() : stm32g0xx_hal_uart.c
  • UART_CLEAR_CMF : stm32g0xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32g0xx_hal_uart.h
  • UART_CLEAR_FEF : stm32g0xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32g0xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32g0xx_hal_uart.h
  • UART_CLEAR_NEF : stm32g0xx_hal_uart.h
  • UART_CLEAR_OREF : stm32g0xx_hal_uart.h
  • UART_CLEAR_PEF : stm32g0xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32g0xx_hal_uart.h
  • UART_CLEAR_TCF : stm32g0xx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32g0xx_hal_uart.h
  • UART_CLEAR_WUF : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32g0xx_hal_uart.h
  • UART_ClockSourceTypeDef : stm32g0xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32g0xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32g0xx_hal_uart.h
  • UART_CR2_ADDRESS_LSB_POS : stm32g0xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32g0xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32g0xx_hal_uart.h
  • UART_DIV_LPUART : stm32g0xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32g0xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32g0xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32g0xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32g0xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32g0xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32g0xx_hal_uart.h
  • UART_DMAAbortOnError() : stm32g0xx_hal_uart.c
  • UART_DMAError() : stm32g0xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32g0xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32g0xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32g0xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32g0xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32g0xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32g0xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32g0xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32g0xx_hal_uart.c
  • UART_EndRxTransfer() : stm32g0xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32g0xx_hal_uart.c
  • UART_EndTxTransfer() : stm32g0xx_hal_uart.c
  • UART_FIFOMODE_DISABLE : stm32g0xx_hal_uart_ex.h
  • UART_FIFOMODE_ENABLE : stm32g0xx_hal_uart_ex.h
  • UART_FLAG_ABRE : stm32g0xx_hal_uart.h
  • UART_FLAG_ABRF : stm32g0xx_hal_uart.h
  • UART_FLAG_BUSY : stm32g0xx_hal_uart.h
  • UART_FLAG_CMF : stm32g0xx_hal_uart.h
  • UART_FLAG_CTS : stm32g0xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32g0xx_hal_uart.h
  • UART_FLAG_FE : stm32g0xx_hal_uart.h
  • UART_FLAG_IDLE : stm32g0xx_hal_uart.h
  • UART_FLAG_LBDF : stm32g0xx_hal_uart.h
  • UART_FLAG_NE : stm32g0xx_hal_uart.h
  • UART_FLAG_ORE : stm32g0xx_hal_uart.h
  • UART_FLAG_PE : stm32g0xx_hal_uart.h
  • UART_FLAG_REACK : stm32g0xx_hal_uart.h
  • UART_FLAG_RTOF : stm32g0xx_hal_uart.h
  • UART_FLAG_RWU : stm32g0xx_hal_uart.h
  • UART_FLAG_RXFF : stm32g0xx_hal_uart.h
  • UART_FLAG_RXFNE : stm32g0xx_hal_uart.h
  • UART_FLAG_RXFT : stm32g0xx_hal_uart.h
  • UART_FLAG_RXNE : stm32g0xx_hal_uart.h
  • UART_FLAG_SBKF : stm32g0xx_hal_uart.h
  • UART_FLAG_TC : stm32g0xx_hal_uart.h
  • UART_FLAG_TEACK : stm32g0xx_hal_uart.h
  • UART_FLAG_TXE : stm32g0xx_hal_uart.h
  • UART_FLAG_TXFE : stm32g0xx_hal_uart.h
  • UART_FLAG_TXFNF : stm32g0xx_hal_uart.h
  • UART_FLAG_TXFT : stm32g0xx_hal_uart.h
  • UART_FLAG_WUF : stm32g0xx_hal_uart.h
  • UART_GET_DIV_FACTOR : stm32g0xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32g0xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32g0xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32g0xx_hal_uart.h
  • UART_HandleTypeDef : stm32g0xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32g0xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32g0xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32g0xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32g0xx_hal_uart.h
  • UART_InitCallbacksToDefault() : stm32g0xx_hal_uart.c
  • UART_INSTANCE_LOWPOWER : stm32g0xx_hal_uart.h
  • UART_IT_CM : stm32g0xx_hal_uart.h
  • UART_IT_CTS : stm32g0xx_hal_uart.h
  • UART_IT_ERR : stm32g0xx_hal_uart.h
  • UART_IT_FE : stm32g0xx_hal_uart.h
  • UART_IT_IDLE : stm32g0xx_hal_uart.h
  • UART_IT_LBD : stm32g0xx_hal_uart.h
  • UART_IT_MASK : stm32g0xx_hal_uart.h
  • UART_IT_NE : stm32g0xx_hal_uart.h
  • UART_IT_ORE : stm32g0xx_hal_uart.h
  • UART_IT_PE : stm32g0xx_hal_uart.h
  • UART_IT_RTO : stm32g0xx_hal_uart.h
  • UART_IT_RXFF : stm32g0xx_hal_uart.h
  • UART_IT_RXFNE : stm32g0xx_hal_uart.h
  • UART_IT_RXFT : stm32g0xx_hal_uart.h
  • UART_IT_RXNE : stm32g0xx_hal_uart.h
  • UART_IT_TC : stm32g0xx_hal_uart.h
  • UART_IT_TXE : stm32g0xx_hal_uart.h
  • UART_IT_TXFE : stm32g0xx_hal_uart.h
  • UART_IT_TXFNF : stm32g0xx_hal_uart.h
  • UART_IT_TXFT : stm32g0xx_hal_uart.h
  • UART_IT_WUF : stm32g0xx_hal_uart.h
  • UART_LIN_DISABLE : stm32g0xx_hal_uart.h
  • UART_LIN_ENABLE : stm32g0xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32g0xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32g0xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32g0xx_hal_uart_ex.h
  • UART_MODE_RX : stm32g0xx_hal_uart.h
  • UART_MODE_TX : stm32g0xx_hal_uart.h
  • UART_MODE_TX_RX : stm32g0xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32g0xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32g0xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32g0xx_hal_uart.h
  • UART_PARITY_EVEN : stm32g0xx_hal_uart.h
  • UART_PARITY_NONE : stm32g0xx_hal_uart.h
  • UART_PARITY_ODD : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32g0xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32g0xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32g0xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32g0xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_uart_ex.h
  • UART_RxISR_16BIT() : stm32g0xx_hal_uart.c
  • UART_RxISR_16BIT_FIFOEN() : stm32g0xx_hal_uart.c
  • UART_RxISR_8BIT() : stm32g0xx_hal_uart.c
  • UART_RxISR_8BIT_FIFOEN() : stm32g0xx_hal_uart.c
  • UART_SENDBREAK_REQUEST : stm32g0xx_hal_uart.h
  • UART_SetConfig() : stm32g0xx_hal_uart.c
  • UART_Start_Receive_DMA() : stm32g0xx_hal_uart.c
  • UART_Start_Receive_IT() : stm32g0xx_hal_uart.c
  • UART_STATE_DISABLE : stm32g0xx_hal_uart.h
  • UART_STATE_ENABLE : stm32g0xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32g0xx_hal_uart.h
  • UART_STOPBITS_1 : stm32g0xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32g0xx_hal_uart.h
  • UART_STOPBITS_2 : stm32g0xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32g0xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_uart_ex.h
  • UART_TxISR_16BIT() : stm32g0xx_hal_uart.c
  • UART_TxISR_16BIT_FIFOEN() : stm32g0xx_hal_uart.c
  • UART_TxISR_8BIT() : stm32g0xx_hal_uart.c
  • UART_TxISR_8BIT_FIFOEN() : stm32g0xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32g0xx_hal_uart.c
  • UART_WAKEUP_ON_ADDRESS : stm32g0xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32g0xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32g0xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32g0xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32g0xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32g0xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32g0xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32g0xx_hal_uart_ex.h
  • UARTEx_SetNbDataToProcess() : stm32g0xx_hal_uart_ex.c
  • UARTEx_Wakeup_AddressConfig() : stm32g0xx_hal_uart_ex.c
  • UARTPrescTable : stm32g0xx_hal_uart.h , stm32g0xx_hal_uart.c
  • UID_BASE_ADDRESS : stm32g0xx_ll_utils.h
  • USART_BRR_MAX : stm32g0xx_hal_usart.c , stm32g0xx_hal_irda.c , stm32g0xx_hal_smartcard.c
  • USART_BRR_MIN : stm32g0xx_hal_irda.c , stm32g0xx_hal_smartcard.c , stm32g0xx_hal_usart.c
  • USART_CheckIdleState() : stm32g0xx_hal_usart.c
  • USART_CLEAR_FEF : stm32g0xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32g0xx_hal_usart.h
  • USART_CLEAR_NEF : stm32g0xx_hal_usart.h
  • USART_CLEAR_OREF : stm32g0xx_hal_usart.h
  • USART_CLEAR_PEF : stm32g0xx_hal_usart.h
  • USART_CLEAR_RTOF : stm32g0xx_hal_usart.h
  • USART_CLEAR_TCF : stm32g0xx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32g0xx_hal_usart.h
  • USART_CLEAR_UDRF : stm32g0xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32g0xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32g0xx_hal_usart.h
  • USART_ClockSourceTypeDef : stm32g0xx_hal_usart.h
  • USART_CR1_FIELDS : stm32g0xx_hal_usart.c , stm32g0xx_hal_smartcard.c , stm32g0xx_hal_uart.c
  • USART_CR2_CLK_FIELDS : stm32g0xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32g0xx_hal_smartcard.c , stm32g0xx_hal_usart.c
  • USART_CR3_FIELDS : stm32g0xx_hal_smartcard.c , stm32g0xx_hal_uart.c , stm32g0xx_hal_usart.c
  • USART_CR_MASK : stm32g0xx_hal_usart.h
  • USART_CR_POS : stm32g0xx_hal_usart.h
  • USART_DIV_SAMPLING8 : stm32g0xx_hal_usart.h
  • USART_DMAAbortOnError() : stm32g0xx_hal_usart.c
  • USART_DMAError() : stm32g0xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32g0xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32g0xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32g0xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32g0xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32g0xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32g0xx_hal_usart.c
  • USART_DUMMY_DATA : stm32g0xx_hal_usart.c
  • USART_EndTransfer() : stm32g0xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32g0xx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32g0xx_hal_usart_ex.h
  • USART_FIFOMODE_ENABLE : stm32g0xx_hal_usart_ex.h
  • USART_FLAG_BUSY : stm32g0xx_hal_usart.h
  • USART_FLAG_FE : stm32g0xx_hal_usart.h
  • USART_FLAG_IDLE : stm32g0xx_hal_usart.h
  • USART_FLAG_NE : stm32g0xx_hal_usart.h
  • USART_FLAG_ORE : stm32g0xx_hal_usart.h
  • USART_FLAG_PE : stm32g0xx_hal_usart.h
  • USART_FLAG_REACK : stm32g0xx_hal_usart.h
  • USART_FLAG_RTOF : stm32g0xx_hal_usart.h
  • USART_FLAG_RXFF : stm32g0xx_hal_usart.h
  • USART_FLAG_RXFNE : stm32g0xx_hal_usart.h
  • USART_FLAG_RXFT : stm32g0xx_hal_usart.h
  • USART_FLAG_RXNE : stm32g0xx_hal_usart.h
  • USART_FLAG_TC : stm32g0xx_hal_usart.h
  • USART_FLAG_TEACK : stm32g0xx_hal_usart.h
  • USART_FLAG_TXE : stm32g0xx_hal_usart.h
  • USART_FLAG_TXFE : stm32g0xx_hal_usart.h
  • USART_FLAG_TXFNF : stm32g0xx_hal_usart.h
  • USART_FLAG_TXFT : stm32g0xx_hal_usart.h
  • USART_FLAG_UDR : stm32g0xx_hal_usart.h
  • USART_GET_DIV_FACTOR : stm32g0xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32g0xx_hal_usart_ex.h
  • USART_HandleTypeDef : stm32g0xx_hal_usart.h
  • USART_InitCallbacksToDefault() : stm32g0xx_hal_usart.c
  • USART_ISR_MASK : stm32g0xx_hal_usart.h
  • USART_ISR_POS : stm32g0xx_hal_usart.h
  • USART_IT_ERR : stm32g0xx_hal_usart.h
  • USART_IT_FE : stm32g0xx_hal_usart.h
  • USART_IT_IDLE : stm32g0xx_hal_usart.h
  • USART_IT_MASK : stm32g0xx_hal_usart.h
  • USART_IT_NE : stm32g0xx_hal_usart.h
  • USART_IT_ORE : stm32g0xx_hal_usart.h
  • USART_IT_PE : stm32g0xx_hal_usart.h
  • USART_IT_RXFF : stm32g0xx_hal_usart.h
  • USART_IT_RXFNE : stm32g0xx_hal_usart.h
  • USART_IT_RXFT : stm32g0xx_hal_usart.h
  • USART_IT_RXNE : stm32g0xx_hal_usart.h
  • USART_IT_TC : stm32g0xx_hal_usart.h
  • USART_IT_TXE : stm32g0xx_hal_usart.h
  • USART_IT_TXFE : stm32g0xx_hal_usart.h
  • USART_IT_TXFNF : stm32g0xx_hal_usart.h
  • USART_IT_TXFT : stm32g0xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32g0xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32g0xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32g0xx_hal_usart_ex.h
  • USART_MODE_RX : stm32g0xx_hal_usart.h
  • USART_MODE_TX : stm32g0xx_hal_usart.h
  • USART_MODE_TX_RX : stm32g0xx_hal_usart.h
  • USART_NSS_HARD : stm32g0xx_hal_usart_ex.h
  • USART_NSS_SOFT : stm32g0xx_hal_usart_ex.h
  • USART_PARITY_EVEN : stm32g0xx_hal_usart.h
  • USART_PARITY_NONE : stm32g0xx_hal_usart.h
  • USART_PARITY_ODD : stm32g0xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32g0xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32g0xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32g0xx_hal_usart.h
  • USART_POLARITY_LOW : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_TAB : stm32g0xx_ll_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32g0xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_usart_ex.h
  • USART_RxISR_16BIT() : stm32g0xx_hal_usart.c
  • USART_RxISR_16BIT_FIFOEN() : stm32g0xx_hal_usart.c
  • USART_RxISR_8BIT() : stm32g0xx_hal_usart.c
  • USART_RxISR_8BIT_FIFOEN() : stm32g0xx_hal_usart.c
  • USART_SetConfig() : stm32g0xx_hal_usart.c
  • USART_SLAVEMODE_DISABLE : stm32g0xx_hal_usart_ex.h
  • USART_SLAVEMODE_ENABLE : stm32g0xx_hal_usart_ex.h
  • USART_STOPBITS_0_5 : stm32g0xx_hal_usart.h
  • USART_STOPBITS_1 : stm32g0xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32g0xx_hal_usart.h
  • USART_STOPBITS_2 : stm32g0xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32g0xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32g0xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_usart_ex.h
  • USART_TxISR_16BIT() : stm32g0xx_hal_usart.c
  • USART_TxISR_16BIT_FIFOEN() : stm32g0xx_hal_usart.c
  • USART_TxISR_8BIT() : stm32g0xx_hal_usart.c
  • USART_TxISR_8BIT_FIFOEN() : stm32g0xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32g0xx_hal_usart.c
  • USART_WORDLENGTH_7B : stm32g0xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32g0xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32g0xx_hal_usart_ex.h
  • USARTEx_SetNbDataToProcess() : stm32g0xx_hal_usart_ex.c
  • USB_EP0StartXfer : stm32g0xx_hal_pcd.h
  • USB_WAKEUP_EXTI_LINE : stm32g0xx_hal_pcd.h
  • USE_HAL_ADC_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_CEC_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_COMP_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_CRYP_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_CRYP_SUSPEND_RESUME : stm32g0xx_hal_conf.h
  • USE_HAL_DAC_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_FDCAN_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_HCD_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_I2C_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_I2S_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_IRDA_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_LPTIM_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_PCD_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_RNG_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_RTC_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_SMARTCARD_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_SMBUS_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_SPI_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_TIM_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_UART_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_USART_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_WWDG_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_RTOS : stm32g0xx_hal_conf.h
  • USE_SPI_CRC : stm32g0xx_hal_conf.h
  • UTILS_EnablePLLAndSwitchSystem() : stm32g0xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32g0xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MAX : stm32g0xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32g0xx_ll_utils.c
  • UTILS_MAX_FREQUENCY : stm32g0xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32g0xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX : stm32g0xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN : stm32g0xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MAX : stm32g0xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MIN : stm32g0xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_FREQ : stm32g0xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_FREQ : stm32g0xx_ll_utils.c
  • UTILS_SCALE1_LATENCY3_FREQ : stm32g0xx_ll_utils.c
  • uwTick : stm32g0xx_hal.c , stm32g0xx_hal.h
  • uwTickFreq : stm32g0xx_hal.c , stm32g0xx_hal.h
  • uwTickPrio : stm32g0xx_hal.h , stm32g0xx_hal.c
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VDD_VALUE : stm32g0xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32g0xx_hal.c
  • VREFINT_CAL_ADDR : stm32g0xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32g0xx_ll_adc.h
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STM32G0C1xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_EWI_DISABLE : stm32g0xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32g0xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32g0xx_hal_wwdg.h
  • WWDG_HandleTypeDef : stm32g0xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32g0xx_hal_wwdg.h
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STM32G0C1xx HAL User Manual: Globals

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- a -

  • ADC_ConversionStop() : stm32g0xx_hal_adc.c , stm32g0xx_hal_adc.h
  • ADC_Disable() : stm32g0xx_hal_adc.h , stm32g0xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32g0xx_hal_adc.c
  • ADC_DMAError() : stm32g0xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32g0xx_hal_adc.c
  • ADC_Enable() : stm32g0xx_hal_adc.c , stm32g0xx_hal_adc.h
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STM32G0C1xx HAL User Manual: Globals

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- c -

  • CRC_Handle_16() : stm32g0xx_hal_crc.c
  • CRC_Handle_8() : stm32g0xx_hal_crc.c
  • CRYP_AES_Decrypt() : stm32g0xx_hal_cryp.c
  • CRYP_AES_Decrypt_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_AES_Decrypt_IT() : stm32g0xx_hal_cryp.c
  • CRYP_AES_Encrypt() : stm32g0xx_hal_cryp.c
  • CRYP_AES_Encrypt_IT() : stm32g0xx_hal_cryp.c
  • CRYP_AES_IT() : stm32g0xx_hal_cryp.c
  • CRYP_AES_ProcessData() : stm32g0xx_hal_cryp.c
  • CRYP_AESCCM_Process() : stm32g0xx_hal_cryp.c
  • CRYP_AESCCM_Process_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_AESCCM_Process_IT() : stm32g0xx_hal_cryp.c
  • CRYP_AESGCM_Process() : stm32g0xx_hal_cryp.c
  • CRYP_AESGCM_Process_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_AESGCM_Process_IT() : stm32g0xx_hal_cryp.c
  • CRYP_ClearCCFlagWhenHigh() : stm32g0xx_hal_cryp.c
  • CRYP_DMAError() : stm32g0xx_hal_cryp.c
  • CRYP_DMAInCplt() : stm32g0xx_hal_cryp.c
  • CRYP_DMAOutCplt() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_IT() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_DMA() : stm32g0xx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_IT() : stm32g0xx_hal_cryp.c
  • CRYP_PhaseProcessingResume() : stm32g0xx_hal_cryp.c
  • CRYP_Read_IVRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_Read_KeyRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_Read_SuspendRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_SetDMAConfig() : stm32g0xx_hal_cryp.c
  • CRYP_SetHeaderDMAConfig() : stm32g0xx_hal_cryp.c
  • CRYP_SetKey() : stm32g0xx_hal_cryp.c
  • CRYP_WaitOnCCFlag() : stm32g0xx_hal_cryp.c
  • CRYP_Write_IVRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_Write_KeyRegisters() : stm32g0xx_hal_cryp.c
  • CRYP_Write_SuspendRegisters() : stm32g0xx_hal_cryp.c
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STM32G0C1xx HAL User Manual: Globals

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- d -

  • DAC_DMAConvCpltCh1() : stm32g0xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32g0xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32g0xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32g0xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32g0xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32g0xx_hal_dac_ex.c
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32g0xx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32g0xx_hal_dma.c
  • DMA_SetConfig() : stm32g0xx_hal_dma.c
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STM32G0C1xx HAL User Manual: Globals

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- f -

  • FDCAN_CalcultateRamBlockAddresses() : stm32g0xx_hal_fdcan.c
  • FDCAN_CopyMessageToRAM() : stm32g0xx_hal_fdcan.c
  • FLASH_FlushCaches() : stm32g0xx_hal_flash_ex.c
  • FLASH_MassErase() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP1A() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP1B() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP2A() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP2B() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetSecMem() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_OptrConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_PCROP1AConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_PCROP1BConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_PCROP2AConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_PCROP2BConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_SecMemConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_OB_WRPConfig() : stm32g0xx_hal_flash_ex.c
  • FLASH_PageErase() : stm32g0xx_hal_flash_ex.c , stm32g0xx_hal_flash_ex.h
  • FLASH_Program_DoubleWord() : stm32g0xx_hal_flash.c
  • FLASH_Program_Fast() : stm32g0xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32g0xx_hal_flash.h , stm32g0xx_hal_flash.c
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STM32G0C1xx HAL User Manual: Globals

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- h -

  • HAL_ADC_AnalogWDGConfig() : stm32g0xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32g0xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32g0xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_GetError() : stm32g0xx_hal_adc.c
  • HAL_ADC_GetState() : stm32g0xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32g0xx_hal_adc.c
  • HAL_ADC_Init() : stm32g0xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32g0xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32g0xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32g0xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32g0xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32g0xx_hal_adc.c
  • HAL_ADC_RegisterCallback() : stm32g0xx_hal_adc.c
  • HAL_ADC_Start() : stm32g0xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32g0xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32g0xx_hal_adc.c
  • HAL_ADC_Stop() : stm32g0xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32g0xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32g0xx_hal_adc.c
  • HAL_ADC_UnRegisterCallback() : stm32g0xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_ChannelConfigReadyCallback() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32g0xx_hal_adc_ex.c , stm32g0xx_hal_adc_ex.h
  • HAL_ADCEx_EndOfSamplingCallback() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32g0xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32g0xx_hal_adc_ex.c
  • HAL_CEC_ChangeRxBuffer() : stm32g0xx_hal_cec.c
  • HAL_CEC_DeInit() : stm32g0xx_hal_cec.c
  • HAL_CEC_ErrorCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_GetError() : stm32g0xx_hal_cec.c
  • HAL_CEC_GetLastReceivedFrameSize() : stm32g0xx_hal_cec.c
  • HAL_CEC_GetState() : stm32g0xx_hal_cec.c
  • HAL_CEC_Init() : stm32g0xx_hal_cec.c
  • HAL_CEC_IRQHandler() : stm32g0xx_hal_cec.c
  • HAL_CEC_MspDeInit() : stm32g0xx_hal_cec.c
  • HAL_CEC_MspInit() : stm32g0xx_hal_cec.c
  • HAL_CEC_RegisterCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_RegisterRxCpltCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_RxCpltCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_SetDeviceAddress() : stm32g0xx_hal_cec.c
  • HAL_CEC_Transmit_IT() : stm32g0xx_hal_cec.c
  • HAL_CEC_TxCpltCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_UnRegisterCallback() : stm32g0xx_hal_cec.c
  • HAL_CEC_UnRegisterRxCpltCallback() : stm32g0xx_hal_cec.c
  • HAL_COMP_DeInit() : stm32g0xx_hal_comp.c
  • HAL_COMP_GetError() : stm32g0xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32g0xx_hal_comp.c
  • HAL_COMP_GetState() : stm32g0xx_hal_comp.c
  • HAL_COMP_Init() : stm32g0xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32g0xx_hal_comp.c
  • HAL_COMP_Lock() : stm32g0xx_hal_comp.c
  • HAL_COMP_MspDeInit() : stm32g0xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32g0xx_hal_comp.c
  • HAL_COMP_RegisterCallback() : stm32g0xx_hal_comp.c
  • HAL_COMP_Start() : stm32g0xx_hal_comp.c
  • HAL_COMP_Stop() : stm32g0xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32g0xx_hal_comp.c
  • HAL_COMP_UnRegisterCallback() : stm32g0xx_hal_comp.c
  • HAL_CRC_Accumulate() : stm32g0xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32g0xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32g0xx_hal_crc.c
  • HAL_CRC_GetState() : stm32g0xx_hal_crc.c
  • HAL_CRC_Init() : stm32g0xx_hal_crc.c
  • HAL_CRC_MspDeInit() : stm32g0xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32g0xx_hal_crc.c
  • HAL_CRCEx_Input_Data_Reverse() : stm32g0xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32g0xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32g0xx_hal_crc_ex.c
  • HAL_CRYP_Decrypt() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Decrypt_DMA() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Decrypt_IT() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Encrypt() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Encrypt_DMA() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Encrypt_IT() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_ErrorCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_GetConfig() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Init() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_IRQHandler() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_MspDeInit() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_MspInit() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_OutCpltCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_ProcessSuspend() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_RegisterCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Resume() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_SetConfig() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_Suspend() : stm32g0xx_hal_cryp.c
  • HAL_CRYP_UnRegisterCallback() : stm32g0xx_hal_cryp.c
  • HAL_CRYPEx_AESCCM_GenerateAuthTAG() : stm32g0xx_hal_cryp_ex.c
  • HAL_CRYPEx_AESGCM_GenerateAuthTAG() : stm32g0xx_hal_cryp_ex.c
  • HAL_CRYPEx_DisableAutoKeyDerivation() : stm32g0xx_hal_cryp_ex.c
  • HAL_CRYPEx_EnableAutoKeyDerivation() : stm32g0xx_hal_cryp_ex.c
  • HAL_DAC_ConfigChannel() : stm32g0xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32g0xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32g0xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32g0xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32g0xx_hal_dac.c
  • HAL_DAC_ErrorCallbackCh1() : stm32g0xx_hal_dac.c
  • HAL_DAC_GetError() : stm32g0xx_hal_dac.c
  • HAL_DAC_GetState() : stm32g0xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32g0xx_hal_dac.c
  • HAL_DAC_Init() : stm32g0xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32g0xx_hal_dac.c
  • HAL_DAC_MspDeInit() : stm32g0xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32g0xx_hal_dac.c
  • HAL_DAC_RegisterCallback() : stm32g0xx_hal_dac.c , stm32g0xx_hal_dac.h
  • HAL_DAC_SetValue() : stm32g0xx_hal_dac.c
  • HAL_DAC_Start() : stm32g0xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32g0xx_hal_dac.c
  • HAL_DAC_Stop() : stm32g0xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32g0xx_hal_dac.c
  • HAL_DAC_UnRegisterCallback() : stm32g0xx_hal_dac.c , stm32g0xx_hal_dac.h
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32g0xx_hal_dac_ex.c , stm32g0xx_hal_dac_ex.h
  • HAL_DACEx_DualSetValue() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_DualStart() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_DualStop() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32g0xx_hal_dac_ex.c , stm32g0xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32g0xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32g0xx_hal_dac_ex.c , stm32g0xx_hal_dac_ex.h
  • HAL_DACEx_SetUserTrimming() : stm32g0xx_hal_dac_ex.c , stm32g0xx_hal_dac_ex.h
  • HAL_DACEx_TriangleWaveGenerate() : stm32g0xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32g0xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32g0xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32g0xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32g0xx_hal.c
  • HAL_DeInit() : stm32g0xx_hal.c
  • HAL_Delay() : stm32g0xx_hal.c
  • HAL_DMA_Abort() : stm32g0xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32g0xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32g0xx_hal_dma.c
  • HAL_DMA_GetError() : stm32g0xx_hal_dma.c
  • HAL_DMA_GetState() : stm32g0xx_hal_dma.c
  • HAL_DMA_Init() : stm32g0xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32g0xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32g0xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32g0xx_hal_dma.c
  • HAL_DMA_Start() : stm32g0xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32g0xx_hal_dma.c
  • HAL_DMA_UnRegisterCallback() : stm32g0xx_hal_dma.c
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32g0xx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32g0xx_hal_dma_ex.c
  • HAL_EXTI_ClearConfigLine() : stm32g0xx_hal_exti.c
  • HAL_EXTI_ClearPending() : stm32g0xx_hal_exti.c
  • HAL_EXTI_GenerateSWI() : stm32g0xx_hal_exti.c
  • HAL_EXTI_GetConfigLine() : stm32g0xx_hal_exti.c
  • HAL_EXTI_GetHandle() : stm32g0xx_hal_exti.c
  • HAL_EXTI_GetPending() : stm32g0xx_hal_exti.c
  • HAL_EXTI_IRQHandler() : stm32g0xx_hal_exti.c
  • HAL_EXTI_RegisterCallback() : stm32g0xx_hal_exti.c
  • HAL_EXTI_SetConfigLine() : stm32g0xx_hal_exti.c
  • HAL_FDCAN_AbortTxRequest() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ActivateNotification() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_AddMessageToTxFifoQ() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigExtendedIdMask() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigFilter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigGlobalFilter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigInterruptLines() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRamWatchdog() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigRxFifoOverwrite() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ConfigTxDelayCompensation() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DeactivateNotification() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DeInit() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableEdgeFiltering() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableISOMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_DisableTxDelayCompensation() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableEdgeFiltering() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableISOMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnableTxDelayCompensation() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_EnterPowerDownMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ErrorCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ErrorStatusCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ExitPowerDownMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ExitRestrictedOperationMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetError() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetErrorCounters() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetHighPriorityMessageStatus() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetLatestTxFifoQRequestBuffer() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetProtocolStatus() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetRxFifoFillLevel() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetRxMessage() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetState() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetTxEvent() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_GetTxFifoFreeLevel() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_HighPriorityMessageCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_Init() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_IRQHandler() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_IsRestrictedOperationMode() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_IsTxBufferMessagePending() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_MspDeInit() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_MspInit() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterCallback() : stm32g0xx_hal_fdcan.c , stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_RegisterErrorStatusCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo0Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterRxFifo1Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferAbortCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxBufferCompleteCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RegisterTxEventFifoCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimeoutCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_ResetTimestampCounter() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo0Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_RxFifo1Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_Start() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_Stop() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TimeoutOccurredCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TimestampWraparoundCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferAbortCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TxBufferCompleteCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TxEventFifoCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_TxFifoEmptyCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterErrorStatusCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo0Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterRxFifo1Callback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferAbortCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxBufferCompleteCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FDCAN_UnRegisterTxEventFifoCallback() : stm32g0xx_hal_fdcan.c
  • HAL_FLASH_EndOfOperationCallback() : stm32g0xx_hal_flash.c
  • HAL_FLASH_GetError() : stm32g0xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32g0xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32g0xx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32g0xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32g0xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32g0xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32g0xx_hal_flash.c
  • HAL_FLASH_Program() : stm32g0xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32g0xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32g0xx_hal_flash.c
  • HAL_FLASHEx_DisableDebugger() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_EnableDebugger() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_EnableSecMemProtection() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_FlashEmptyCheck() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_ForceFlashEmpty() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32g0xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32g0xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32g0xx_hal.c
  • HAL_GetHalVersion() : stm32g0xx_hal.c
  • HAL_GetREVID() : stm32g0xx_hal.c
  • HAL_GetTick() : stm32g0xx_hal.c
  • HAL_GetTickFreq() : stm32g0xx_hal.c
  • HAL_GetTickPrio() : stm32g0xx_hal.c
  • HAL_GetUIDw0() : stm32g0xx_hal.c
  • HAL_GetUIDw1() : stm32g0xx_hal.c
  • HAL_GetUIDw2() : stm32g0xx_hal.c
  • HAL_GPIO_DeInit() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_EXTI_Falling_Callback() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_EXTI_Rising_Callback() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32g0xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32g0xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32g0xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32g0xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32g0xx_hal_uart.c
  • HAL_HCD_Check_usedChannel() : stm32g0xx_hal_hcd.c
  • HAL_HCD_ClearPhyChannel() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Connect_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_DeInit() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Get_FreePhyChannel() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetFreePMA() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetLogical_Channel() : stm32g0xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_Close() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Init() : stm32g0xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32g0xx_hal_hcd.c
  • HAL_HCD_MspDeInit() : stm32g0xx_hal_hcd.c
  • HAL_HCD_MspInit() : stm32g0xx_hal_hcd.c
  • HAL_HCD_PMADeAlloc() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_PMAFree() : stm32g0xx_hal_hcd.c
  • HAL_HCD_PMAlloc() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_PMAReset() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_PortDisabled_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_PortEnabled_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_RegisterCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_RegisterHC_NotifyURBChangeCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_ResetPort() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Resume() : stm32g0xx_hal_hcd.c
  • HAL_HCD_ResumeCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_ResumePort() : stm32g0xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Start() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Stop() : stm32g0xx_hal_hcd.c
  • HAL_HCD_Suspend() : stm32g0xx_hal_hcd.c
  • HAL_HCD_SuspendCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_UnRegisterCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_HCD_UnRegisterHC_NotifyURBChangeCallback() : stm32g0xx_hal_hcd.c , stm32g0xx_hal_hcd.h
  • HAL_I2C_AbortCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32g0xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32g0xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32g0xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32g0xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Init() : stm32g0xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32g0xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_RegisterAddrCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_RegisterCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32g0xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32g0xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_UnRegisterAddrCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2C_UnRegisterCallback() : stm32g0xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32g0xx_hal_i2c_ex.c
  • HAL_I2S_DeInit() : stm32g0xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32g0xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32g0xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32g0xx_hal_i2s.c
  • HAL_I2S_ErrorCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32g0xx_hal_i2s.c
  • HAL_I2S_GetState() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Init() : stm32g0xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32g0xx_hal_i2s.c
  • HAL_I2S_MspDeInit() : stm32g0xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32g0xx_hal_i2s.c
  • HAL_I2S_RegisterCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Transmit() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32g0xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32g0xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32g0xx_hal_i2s.c
  • HAL_I2S_UnRegisterCallback() : stm32g0xx_hal_i2s.c
  • HAL_IncTick() : stm32g0xx_hal.c
  • HAL_Init() : stm32g0xx_hal.c
  • HAL_InitTick() : stm32g0xx_hal.c
  • HAL_IRDA_Abort() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32g0xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32g0xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32g0xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32g0xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Init() : stm32g0xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32g0xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_RegisterCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32g0xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32g0xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32g0xx_hal_irda.c
  • HAL_IRDA_UnRegisterCallback() : stm32g0xx_hal_irda.c
  • HAL_IWDG_Init() : stm32g0xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32g0xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32g0xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32g0xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_CompareMatchCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_CompareWriteCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Counter_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Counter_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_DeInit() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_DirectionDownCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_DirectionUpCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Encoder_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_GetState() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_Init() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_IRQHandler() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_MspDeInit() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_MspInit() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_PWM_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_PWM_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_ReadAutoReload() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_ReadCompare() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_ReadCounter() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_RegisterCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Start_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_TriggerCallback() : stm32g0xx_hal_lptim.c
  • HAL_LPTIM_UnRegisterCallback() : stm32g0xx_hal_lptim.c
  • HAL_MPU_ConfigRegion() : stm32g0xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32g0xx_hal_cortex.c
  • HAL_MPU_Enable() : stm32g0xx_hal_cortex.c
  • HAL_MspDeInit() : stm32g0xx_hal.c
  • HAL_MspInit() : stm32g0xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32g0xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32g0xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32g0xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32g0xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32g0xx_hal_uart_ex.c
  • HAL_NVIC_ClearPendingIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32g0xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32g0xx_hal_cortex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32g0xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32g0xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Abort() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_DB_Receive() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_DB_Transmit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32g0xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32g0xx_hal_pcd.c
  • HAL_PCD_Init() : stm32g0xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32g0xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterBcdCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterDataInStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterDataOutStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterIsoInIncpltCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterIsoOutIncpltCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_RegisterLpmCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32g0xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_Start() : stm32g0xx_hal_pcd.c
  • HAL_PCD_Stop() : stm32g0xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterBcdCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataInStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterDataOutStageCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoInIncpltCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoOutIncpltCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCD_UnRegisterLpmCallback() : stm32g0xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32g0xx_hal_pcd_ex.c
  • HAL_PCDEx_PMAConfig() : stm32g0xx_hal_pcd_ex.c
  • HAL_PWR_DeInit() : stm32g0xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32g0xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32g0xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32g0xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32g0xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32g0xx_hal_pwr.c
  • HAL_PWREx_ConfigPVD() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_ConfigPVM() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullDown() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullUp() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableInternalWakeUpLine() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowPowerRunMode() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePORMonitorSampling() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePullUpPullDownConfig() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVD() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVMUSB() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableSRAMRetention() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddIO2() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddUSB() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullDown() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullUp() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableInternalWakeUpLine() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowPowerRunMode() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePORMonitorSampling() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePullUpPullDownConfig() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVD() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVMUSB() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableSRAMRetention() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddIO2() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddUSB() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSHUTDOWNMode() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_Falling_Callback() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_IRQHandler() : stm32g0xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_Rising_Callback() : stm32g0xx_hal_pwr_ex.c
  • HAL_RCC_ClockConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32g0xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32g0xx_hal_rcc.c
  • HAL_RCC_DisableLSECSS() : stm32g0xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32g0xx_hal_rcc.c
  • HAL_RCC_EnableLSECSS() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetResetSource() : stm32g0xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32g0xx_hal_rcc.c
  • HAL_RCC_LSECSSCallback() : stm32g0xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32g0xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32g0xx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSCO() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSCO() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32g0xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32g0xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32g0xx_hal.c
  • HAL_RNG_DeInit() : stm32g0xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32g0xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32g0xx_hal_rng.c
  • HAL_RNG_GetError() : stm32g0xx_hal_rng.c
  • HAL_RNG_GetState() : stm32g0xx_hal_rng.c
  • HAL_RNG_Init() : stm32g0xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32g0xx_hal_rng.c
  • HAL_RNG_MspDeInit() : stm32g0xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32g0xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32g0xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_RegisterCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_RegisterReadyDataCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_UnRegisterCallback() : stm32g0xx_hal_rng.c
  • HAL_RNG_UnRegisterReadyDataCallback() : stm32g0xx_hal_rng.c
  • HAL_RS485Ex_Init() : stm32g0xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32g0xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32g0xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32g0xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32g0xx_hal_rtc.c
  • HAL_RTC_DST_Add1Hour() : stm32g0xx_hal_rtc.c , stm32g0xx_hal_rtc.h
  • HAL_RTC_DST_ClearStoreOperation() : stm32g0xx_hal_rtc.h , stm32g0xx_hal_rtc.c
  • HAL_RTC_DST_ReadStoreOperation() : stm32g0xx_hal_rtc.c , stm32g0xx_hal_rtc.h
  • HAL_RTC_DST_SetStoreOperation() : stm32g0xx_hal_rtc.h , stm32g0xx_hal_rtc.c
  • HAL_RTC_DST_Sub1Hour() : stm32g0xx_hal_rtc.c , stm32g0xx_hal_rtc.h
  • HAL_RTC_GetAlarm() : stm32g0xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32g0xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32g0xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32g0xx_hal_rtc.c
  • HAL_RTC_Init() : stm32g0xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32g0xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32g0xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32g0xx_hal_rtc.c
  • HAL_RTC_RegisterCallback() : stm32g0xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32g0xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32g0xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32g0xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32g0xx_hal_rtc.c
  • HAL_RTC_UnRegisterCallback() : stm32g0xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32g0xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTamper() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper3EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper4EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper5EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_InternalTamper6EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForInternalTamperEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamperEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTamper_IT() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperIRQHandler() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampIRQHandler() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32g0xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32g0xx_hal_rtc_ex.c
  • HAL_SetTickFreq() : stm32g0xx_hal.c
  • HAL_SMARTCARD_Abort() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_RegisterCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARD_UnRegisterCallback() : stm32g0xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableFifoMode() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableFifoMode() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_RxFifoFullCallback() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetRxFifoThreshold() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetTxFifoThreshold() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TxFifoEmptyCallback() : stm32g0xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_ConfigAnalogFilter() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_DisableListen_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_EnableListen_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ER_IRQHandler() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_ErrorCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_ListenCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32g0xx_hal_smbus.h , stm32g0xx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_MspDeInit() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_RegisterAddrCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_RegisterCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32g0xx_hal_smbus.c , stm32g0xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterAddrCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUS_UnRegisterCallback() : stm32g0xx_hal_smbus.c
  • HAL_SMBUSEx_DisableFastModePlus() : stm32g0xx_hal_smbus_ex.c
  • HAL_SMBUSEx_DisableWakeUp() : stm32g0xx_hal_smbus_ex.c
  • HAL_SMBUSEx_EnableFastModePlus() : stm32g0xx_hal_smbus_ex.c
  • HAL_SMBUSEx_EnableWakeUp() : stm32g0xx_hal_smbus_ex.c
  • HAL_SPI_Abort() : stm32g0xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32g0xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32g0xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32g0xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32g0xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32g0xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_GetError() : stm32g0xx_hal_spi.c
  • HAL_SPI_GetState() : stm32g0xx_hal_spi.c
  • HAL_SPI_Init() : stm32g0xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32g0xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32g0xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32g0xx_hal_spi.c
  • HAL_SPI_Receive() : stm32g0xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32g0xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32g0xx_hal_spi.c
  • HAL_SPI_RegisterCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32g0xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32g0xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32g0xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32g0xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32g0xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32g0xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32g0xx_hal_spi.c
  • HAL_SPI_UnRegisterCallback() : stm32g0xx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32g0xx_hal_spi_ex.c
  • HAL_SuspendTick() : stm32g0xx_hal.c
  • HAL_SYSCFG_DisableClampingDiode() : stm32g0xx_hal.c
  • HAL_SYSCFG_DisableIOAnalogSwitchBooster() : stm32g0xx_hal.c
  • HAL_SYSCFG_DisableRemap() : stm32g0xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32g0xx_hal.c
  • HAL_SYSCFG_EnableClampingDiode() : stm32g0xx_hal.c
  • HAL_SYSCFG_EnableIOAnalogSwitchBooster() : stm32g0xx_hal.c
  • HAL_SYSCFG_EnableRemap() : stm32g0xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32g0xx_hal.c
  • HAL_SYSCFG_StrobeDBattpinsConfig() : stm32g0xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32g0xx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32g0xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32g0xx_hal.c
  • HAL_SYSTICK_Callback() : stm32g0xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32g0xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32g0xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32g0xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32g0xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32g0xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiReadStart() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_MultiWriteStart() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32g0xx_hal_tim.c
  • HAL_TIM_DMABurstState() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32g0xx_hal_tim.c
  • HAL_TIM_GetActiveChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_GetChannelState() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_CaptureHalfCpltCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_PeriodElapsedHalfCpltCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedHalfCpltCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32g0xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32g0xx_hal_tim.c
  • HAL_TIM_RegisterCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro() : stm32g0xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro_IT() : stm32g0xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_TriggerHalfCpltCallback() : stm32g0xx_hal_tim.c
  • HAL_TIM_UnRegisterCallback() : stm32g0xx_hal_tim.c
  • HAL_TIMEx_Break2Callback() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_CommutCallback() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_CommutHalfCpltCallback() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_DisarmBreakInput() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_GetChannelNState() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_ReArmBreakInput() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32g0xx_hal_tim_ex.c
  • HAL_TIMEx_TISelection() : stm32g0xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32g0xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_DeInit() : stm32g0xx_hal_uart.c
  • HAL_UART_DisableReceiverTimeout() : stm32g0xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32g0xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32g0xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32g0xx_hal_uart.c
  • HAL_UART_EnableReceiverTimeout() : stm32g0xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_GetError() : stm32g0xx_hal_uart.c
  • HAL_UART_GetState() : stm32g0xx_hal_uart.c
  • HAL_UART_Init() : stm32g0xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32g0xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32g0xx_hal_uart.c
  • HAL_UART_MspInit() : stm32g0xx_hal_uart.c
  • HAL_UART_Receive() : stm32g0xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32g0xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_ReceiverTimeout_Config() : stm32g0xx_hal_uart.c
  • HAL_UART_RegisterCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_RegisterRxEventCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_Transmit() : stm32g0xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32g0xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32g0xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_UnRegisterCallback() : stm32g0xx_hal_uart.c
  • HAL_UART_UnRegisterRxEventCallback() : stm32g0xx_hal_uart.c
  • HAL_UARTEx_DisableFifoMode() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_DisableStopMode() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_EnableFifoMode() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_GetRxEventType() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle_DMA() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_ReceiveToIdle_IT() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_RxEventCallback() : stm32g0xx_hal_uart.c
  • HAL_UARTEx_RxFifoFullCallback() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_SetRxFifoThreshold() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_SetTxFifoThreshold() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_TxFifoEmptyCallback() : stm32g0xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32g0xx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32g0xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32g0xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_DeInit() : stm32g0xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32g0xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32g0xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32g0xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_GetError() : stm32g0xx_hal_usart.c
  • HAL_USART_GetState() : stm32g0xx_hal_usart.c
  • HAL_USART_Init() : stm32g0xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32g0xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32g0xx_hal_usart.c
  • HAL_USART_MspInit() : stm32g0xx_hal_usart.c
  • HAL_USART_Receive() : stm32g0xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32g0xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32g0xx_hal_usart.c
  • HAL_USART_RegisterCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_Transmit() : stm32g0xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32g0xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32g0xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32g0xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32g0xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32g0xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32g0xx_hal_usart.c
  • HAL_USART_UnRegisterCallback() : stm32g0xx_hal_usart.c
  • HAL_USARTEx_ConfigNSS() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_DisableFifoMode() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_DisableSlaveMode() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_EnableFifoMode() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_EnableSlaveMode() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_RxFifoFullCallback() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_SetRxFifoThreshold() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_SetTxFifoThreshold() : stm32g0xx_hal_usart_ex.c
  • HAL_USARTEx_TxFifoEmptyCallback() : stm32g0xx_hal_usart_ex.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_RegisterCallback() : stm32g0xx_hal_wwdg.c
  • HAL_WWDG_UnRegisterCallback() : stm32g0xx_hal_wwdg.c
  • HCD_GET_CH_DBUF0_CNT() : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_DBUF1_CNT() : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_RX_CNT() : stm32g0xx_hal_hcd.h
  • HCD_HC_IN_BulkDb() : stm32g0xx_hal_hcd.c
  • HCD_HC_IN_IRQHandler() : stm32g0xx_hal_hcd.c
  • HCD_HC_IN_ISO() : stm32g0xx_hal_hcd.c
  • HCD_HC_OUT_BulkDb() : stm32g0xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32g0xx_hal_hcd.c
  • HCD_Port_IRQHandler() : stm32g0xx_hal_hcd.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- i -

  • I2C_ConvertOtherXferOptions() : stm32g0xx_hal_i2c.c
  • I2C_Disable_IRQ() : stm32g0xx_hal_i2c.c
  • I2C_DMAAbort() : stm32g0xx_hal_i2c.c
  • I2C_DMAError() : stm32g0xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32g0xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32g0xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32g0xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32g0xx_hal_i2c.c
  • I2C_Enable_IRQ() : stm32g0xx_hal_i2c.c
  • I2C_Flush_TXDR() : stm32g0xx_hal_i2c.c
  • I2C_IsErrorOccurred() : stm32g0xx_hal_i2c.c
  • I2C_ITAddrCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITError() : stm32g0xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITMasterSeqCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32g0xx_hal_i2c.c
  • I2C_ITSlaveSeqCplt() : stm32g0xx_hal_i2c.c
  • I2C_Master_ISR_DMA() : stm32g0xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32g0xx_hal_i2c.c
  • I2C_Mem_ISR_DMA() : stm32g0xx_hal_i2c.c
  • I2C_Mem_ISR_IT() : stm32g0xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32g0xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32g0xx_hal_i2c.c
  • I2C_Slave_ISR_DMA() : stm32g0xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32g0xx_hal_i2c.c
  • I2C_TransferConfig() : stm32g0xx_hal_i2c.c
  • I2C_TreatErrorCallback() : stm32g0xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32g0xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32g0xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32g0xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32g0xx_hal_i2c.c
  • I2S_DMAError() : stm32g0xx_hal_i2s.c
  • I2S_DMARxCplt() : stm32g0xx_hal_i2s.c
  • I2S_DMARxHalfCplt() : stm32g0xx_hal_i2s.c
  • I2S_DMATxCplt() : stm32g0xx_hal_i2s.c
  • I2S_DMATxHalfCplt() : stm32g0xx_hal_i2s.c
  • I2S_Receive_IT() : stm32g0xx_hal_i2s.c
  • I2S_Transmit_IT() : stm32g0xx_hal_i2s.c
  • I2S_WaitFlagStateUntilTimeout() : stm32g0xx_hal_i2s.c
  • IC1Config() : stm32g0xx_ll_tim.c
  • IC2Config() : stm32g0xx_ll_tim.c
  • IC3Config() : stm32g0xx_ll_tim.c
  • IC4Config() : stm32g0xx_ll_tim.c
  • IRDA_CheckIdleState() : stm32g0xx_hal_irda.c
  • IRDA_DMAAbortOnError() : stm32g0xx_hal_irda.c
  • IRDA_DMAError() : stm32g0xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32g0xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32g0xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32g0xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32g0xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32g0xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32g0xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32g0xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32g0xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32g0xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32g0xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32g0xx_hal_irda.c
  • IRDA_InitCallbacksToDefault() : stm32g0xx_hal_irda.c
  • IRDA_Receive_IT() : stm32g0xx_hal_irda.c
  • IRDA_SetConfig() : stm32g0xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32g0xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32g0xx_hal_irda.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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  • Globals
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- l -

  • LL_ADC_ClearFlag_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32g0xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32g0xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32g0xx_ll_adc.c
  • LL_ADC_ConfigAnalogWDThresholds() : stm32g0xx_ll_adc.h
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32g0xx_ll_adc.h
  • LL_ADC_DeInit() : stm32g0xx_ll_adc.c
  • LL_ADC_Disable() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32g0xx_ll_adc.h
  • LL_ADC_Enable() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32g0xx_ll_adc.h
  • LL_ADC_GetCalibrationFactor() : stm32g0xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32g0xx_ll_adc.h
  • LL_ADC_GetClock() : stm32g0xx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32g0xx_ll_adc.h
  • LL_ADC_GetCommonFrequencyMode() : stm32g0xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32g0xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32g0xx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32g0xx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32g0xx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32g0xx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32g0xx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32g0xx_ll_adc.h
  • LL_ADC_GetResolution() : stm32g0xx_ll_adc.h
  • LL_ADC_GetSamplingTimeCommonChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_GetTriggerFrequencyMode() : stm32g0xx_ll_adc.h
  • LL_ADC_Init() : stm32g0xx_ll_adc.c
  • LL_ADC_IsActiveFlag_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32g0xx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_CCRDY() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOCAL() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32g0xx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32g0xx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerConfigurable() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetSequencerScanDirection() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32g0xx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData6() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerChAdd() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerChRem() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerConfigurable() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetSequencerScanDirection() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32g0xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32g0xx_ll_adc.c
  • LL_ADC_SetAnalogWDMonitChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCalibrationFactor() : stm32g0xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32g0xx_ll_adc.h
  • LL_ADC_SetClock() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonFrequencyMode() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalChAdd() : stm32g0xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalChRem() : stm32g0xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32g0xx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32g0xx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32g0xx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32g0xx_ll_adc.h
  • LL_ADC_SetResolution() : stm32g0xx_ll_adc.h
  • LL_ADC_SetSamplingTimeCommonChannels() : stm32g0xx_ll_adc.h
  • LL_ADC_SetTriggerFrequencyMode() : stm32g0xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32g0xx_ll_adc.h
  • LL_ADC_StructInit() : stm32g0xx_ll_adc.c
  • LL_AHB1_GRP1_DisableClock() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_DisableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_EnableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_DisableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_EnableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32g0xx_ll_bus.h
  • LL_COMP_ConfigInputs() : stm32g0xx_ll_comp.h
  • LL_COMP_DeInit() : stm32g0xx_ll_comp.c
  • LL_COMP_Disable() : stm32g0xx_ll_comp.h
  • LL_COMP_Enable() : stm32g0xx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32g0xx_ll_comp.h
  • LL_COMP_GetCommonWindowOutput() : stm32g0xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32g0xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32g0xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32g0xx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32g0xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32g0xx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32g0xx_ll_comp.h
  • LL_COMP_Init() : stm32g0xx_ll_comp.c
  • LL_COMP_IsEnabled() : stm32g0xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32g0xx_ll_comp.h
  • LL_COMP_Lock() : stm32g0xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32g0xx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32g0xx_ll_comp.h
  • LL_COMP_SetCommonWindowOutput() : stm32g0xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32g0xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32g0xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32g0xx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32g0xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32g0xx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32g0xx_ll_comp.h
  • LL_COMP_StructInit() : stm32g0xx_ll_comp.c
  • LL_CPUID_GetArchitecture() : stm32g0xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32g0xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32g0xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32g0xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32g0xx_ll_cortex.h
  • LL_CRC_DeInit() : stm32g0xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32g0xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32g0xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32g0xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32g0xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32g0xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32g0xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32g0xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32g0xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32g0xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32g0xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32g0xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32g0xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32g0xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32g0xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32g0xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32g0xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32g0xx_ll_crc.h
  • LL_CRS_ClearFlag_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_ClearFlag_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_ConfigSynchronization() : stm32g0xx_ll_crs.h
  • LL_CRS_DeInit() : stm32g0xx_ll_crs.c
  • LL_CRS_DisableAutoTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableFreqErrorCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableIT_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableIT_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_DisableIT_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableAutoTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableFreqErrorCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableIT_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableIT_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_EnableIT_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_GenerateEvent_SWSYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_GetFreqErrorCapture() : stm32g0xx_ll_crs.h
  • LL_CRS_GetFreqErrorDirection() : stm32g0xx_ll_crs.h
  • LL_CRS_GetFreqErrorLimit() : stm32g0xx_ll_crs.h
  • LL_CRS_GetHSI48SmoothTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_GetReloadCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_GetSyncDivider() : stm32g0xx_ll_crs.h
  • LL_CRS_GetSyncPolarity() : stm32g0xx_ll_crs.h
  • LL_CRS_GetSyncSignalSource() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCERR() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCMISS() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_IsActiveFlag_TRIMOVF() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledAutoTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledFreqErrorCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ERR() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledIT_ESYNC() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCOK() : stm32g0xx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCWARN() : stm32g0xx_ll_crs.h
  • LL_CRS_SetFreqErrorLimit() : stm32g0xx_ll_crs.h
  • LL_CRS_SetHSI48SmoothTrimming() : stm32g0xx_ll_crs.h
  • LL_CRS_SetReloadCounter() : stm32g0xx_ll_crs.h
  • LL_CRS_SetSyncDivider() : stm32g0xx_ll_crs.h
  • LL_CRS_SetSyncPolarity() : stm32g0xx_ll_crs.h
  • LL_CRS_SetSyncSignalSource() : stm32g0xx_ll_crs.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_ConfigOutput() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32g0xx_ll_dac.h
  • LL_DAC_DeInit() : stm32g0xx_ll_dac.c
  • LL_DAC_Disable() : stm32g0xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32g0xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32g0xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32g0xx_ll_dac.h
  • LL_DAC_Enable() : stm32g0xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32g0xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32g0xx_ll_dac.h
  • LL_DAC_GetMode() : stm32g0xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32g0xx_ll_dac.h
  • LL_DAC_GetOutputConnection() : stm32g0xx_ll_dac.h
  • LL_DAC_GetOutputMode() : stm32g0xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldHoldTime() : stm32g0xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldRefreshTime() : stm32g0xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldSampleTime() : stm32g0xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32g0xx_ll_dac.h
  • LL_DAC_GetTrimmingValue() : stm32g0xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32g0xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32g0xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32g0xx_ll_dac.h
  • LL_DAC_Init() : stm32g0xx_ll_dac.c
  • LL_DAC_IsActiveFlag_BWST1() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_BWST2() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL1() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL2() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32g0xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32g0xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32g0xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32g0xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32g0xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32g0xx_ll_dac.h
  • LL_DAC_SetMode() : stm32g0xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32g0xx_ll_dac.h
  • LL_DAC_SetOutputConnection() : stm32g0xx_ll_dac.h
  • LL_DAC_SetOutputMode() : stm32g0xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldHoldTime() : stm32g0xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldRefreshTime() : stm32g0xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldSampleTime() : stm32g0xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32g0xx_ll_dac.h
  • LL_DAC_SetTrimmingValue() : stm32g0xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32g0xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32g0xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32g0xx_ll_dac.h
  • LL_DAC_StructInit() : stm32g0xx_ll_dac.c
  • LL_DAC_TrigSWConversion() : stm32g0xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32g0xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32g0xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32g0xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32g0xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32g0xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32g0xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32g0xx_ll_system.h
  • LL_DMA_ClearFlag_GI1() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32g0xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32g0xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32g0xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32g0xx_ll_dma.h
  • LL_DMA_DeInit() : stm32g0xx_ll_dma.c
  • LL_DMA_DisableChannel() : stm32g0xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32g0xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32g0xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32g0xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32g0xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32g0xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32g0xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32g0xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32g0xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32g0xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32g0xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32g0xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32g0xx_ll_dma.h
  • LL_DMA_GetMode() : stm32g0xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32g0xx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32g0xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32g0xx_ll_dma.h
  • LL_DMA_Init() : stm32g0xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32g0xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32g0xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32g0xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32g0xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32g0xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32g0xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32g0xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32g0xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32g0xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32g0xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32g0xx_ll_dma.h
  • LL_DMA_SetMode() : stm32g0xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32g0xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32g0xx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32g0xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32g0xx_ll_dma.h
  • LL_DMA_StructInit() : stm32g0xx_ll_dma.c
  • LL_DMAMUX_ClearFlag_RGO0() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO1() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO2() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO3() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO0() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO1() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO10() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO11() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO2() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO3() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO4() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO5() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO6() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO7() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO8() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO9() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableEventGeneration() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_RGO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_SO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableRequestGen() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_DisableSync() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableEventGeneration() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_RGO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_SO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableRequestGen() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_EnableSync() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetGenRequestNb() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestGenPolarity() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetRequestSignalID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncPolarity() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_GetSyncRequestNb() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO0() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO1() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO2() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO3() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO0() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO1() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO10() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO11() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO2() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO3() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO4() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO5() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO6() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO7() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO8() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO9() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledEventGeneration() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_RGO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_SO() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledRequestGen() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledSync() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetGenRequestNb() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestGenPolarity() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetRequestSignalID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncID() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncPolarity() : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SetSyncRequestNb() : stm32g0xx_ll_dmamux.h
  • LL_EXTI_ClearFallingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_ClearFallingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_ClearRisingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_ClearRisingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32g0xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_GetEXTISource() : stm32g0xx_ll_exti.h
  • LL_EXTI_Init() : stm32g0xx_ll_exti.c
  • LL_EXTI_IsActiveFallingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsActiveFallingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsActiveRisingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsActiveRisingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadFallingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadFallingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadRisingFlag_0_31() : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadRisingFlag_32_63() : stm32g0xx_ll_exti.h
  • LL_EXTI_SetEXTISource() : stm32g0xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32g0xx_ll_exti.c
  • LL_FLASH_DisableInstCache() : stm32g0xx_ll_system.h
  • LL_FLASH_DisableInstCacheReset() : stm32g0xx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32g0xx_ll_system.h
  • LL_FLASH_EnableInstCache() : stm32g0xx_ll_system.h
  • LL_FLASH_EnableInstCacheReset() : stm32g0xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32g0xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32g0xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32g0xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32g0xx_ll_system.h
  • LL_GetFlashSize() : stm32g0xx_ll_utils.h
  • LL_GetPackageType() : stm32g0xx_ll_utils.h
  • LL_GetUID_Word0() : stm32g0xx_ll_utils.h
  • LL_GetUID_Word1() : stm32g0xx_ll_utils.h
  • LL_GetUID_Word2() : stm32g0xx_ll_utils.h
  • LL_GPIO_DeInit() : stm32g0xx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32g0xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32g0xx_ll_gpio.h
  • LL_GPIO_Init() : stm32g0xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32g0xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32g0xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32g0xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32g0xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32g0xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32g0xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32g0xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32g0xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32g0xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32g0xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32g0xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32g0xx_ll_gpio.h
  • LL_I2C_AcknowledgeNextData() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32g0xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32g0xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32g0xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32g0xx_ll_i2c.c
  • LL_I2C_Disable() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32g0xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32g0xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32g0xx_ll_i2c.h
  • LL_I2C_Enable() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32g0xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32g0xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32g0xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32g0xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32g0xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32g0xx_ll_i2c.h
  • LL_I2C_Init() : stm32g0xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32g0xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32g0xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32g0xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32g0xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32g0xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32g0xx_ll_i2c.h
  • LL_I2S_ClearFlag_FRE() : stm32g0xx_ll_spi.h
  • LL_I2S_ClearFlag_OVR() : stm32g0xx_ll_spi.h
  • LL_I2S_ClearFlag_UDR() : stm32g0xx_ll_spi.h
  • LL_I2S_ConfigPrescaler() : stm32g0xx_ll_spi.c
  • LL_I2S_DeInit() : stm32g0xx_ll_spi.c
  • LL_I2S_Disable() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableAsyncStart() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableIT_ERR() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableIT_TXE() : stm32g0xx_ll_spi.h
  • LL_I2S_DisableMasterClock() : stm32g0xx_ll_spi.h
  • LL_I2S_Enable() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableAsyncStart() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableIT_ERR() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableIT_TXE() : stm32g0xx_ll_spi.h
  • LL_I2S_EnableMasterClock() : stm32g0xx_ll_spi.h
  • LL_I2S_GetClockPolarity() : stm32g0xx_ll_spi.h
  • LL_I2S_GetDataFormat() : stm32g0xx_ll_spi.h
  • LL_I2S_GetPrescalerLinear() : stm32g0xx_ll_spi.h
  • LL_I2S_GetPrescalerParity() : stm32g0xx_ll_spi.h
  • LL_I2S_GetStandard() : stm32g0xx_ll_spi.h
  • LL_I2S_GetTransferMode() : stm32g0xx_ll_spi.h
  • LL_I2S_Init() : stm32g0xx_ll_spi.c
  • LL_I2S_IsActiveFlag_BSY() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_CHSIDE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_FRE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_OVR() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_RXNE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_TXE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsActiveFlag_UDR() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabled() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledAsyncStart() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledIT_ERR() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledIT_TXE() : stm32g0xx_ll_spi.h
  • LL_I2S_IsEnabledMasterClock() : stm32g0xx_ll_spi.h
  • LL_I2S_ReceiveData16() : stm32g0xx_ll_spi.h
  • LL_I2S_SetClockPolarity() : stm32g0xx_ll_spi.h
  • LL_I2S_SetDataFormat() : stm32g0xx_ll_spi.h
  • LL_I2S_SetPrescalerLinear() : stm32g0xx_ll_spi.h
  • LL_I2S_SetPrescalerParity() : stm32g0xx_ll_spi.h
  • LL_I2S_SetStandard() : stm32g0xx_ll_spi.h
  • LL_I2S_SetTransferMode() : stm32g0xx_ll_spi.h
  • LL_I2S_StructInit() : stm32g0xx_ll_spi.c
  • LL_I2S_TransmitData16() : stm32g0xx_ll_spi.h
  • LL_Init1msTick() : stm32g0xx_ll_utils.c
  • LL_InitTick() : stm32g0xx_ll_utils.h
  • LL_IOP_GRP1_DisableClock() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_DisableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_EnableClock() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_EnableClockStopSleep() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_ForceReset() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_IsEnabledClock() : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_ReleaseReset() : stm32g0xx_ll_bus.h
  • LL_IWDG_DisableWriteAccess() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32g0xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32g0xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32g0xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32g0xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32g0xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32g0xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32g0xx_ll_cortex.h
  • LL_LPTIM_ClearFLAG_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFLAG_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32g0xx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32g0xx_ll_lptim.c
  • LL_LPTIM_DisableEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableResetAfterRead() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableResetAfterRead() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_Init() : stm32g0xx_ll_lptim.c
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledResetAfterRead() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ResetCounter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32g0xx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32g0xx_ll_lptim.c
  • LL_LPTIM_TrigSw() : stm32g0xx_ll_lptim.h
  • LL_LPUART_ClearFlag_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ConfigFIFOsThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32g0xx_ll_lpuart.c
  • LL_LPUART_Disable() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableFIFO() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE_RXFNE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE_TXFNF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableFIFO() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE_RXFNE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE_TXFNF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetPrescaler() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetRXFIFOThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTXFIFOThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_Init() : stm32g0xx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE_RXFNE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE_TXFNF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledFIFO() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE_RXFNE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE_TXFNF() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFE() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFT() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetPrescaler() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetRXFIFOThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTXFIFOThreshold() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32g0xx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32g0xx_ll_lpuart.h
  • LL_mDelay() : stm32g0xx_ll_utils.c
  • LL_MPU_ConfigRegion() : stm32g0xx_ll_cortex.h
  • LL_MPU_Disable() : stm32g0xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32g0xx_ll_cortex.h
  • LL_MPU_Enable() : stm32g0xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32g0xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32g0xx_ll_cortex.h
  • LL_PLL_ConfigSystemClock_HSE() : stm32g0xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32g0xx_ll_utils.c
  • LL_PWR_ClearFlag_SB() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32g0xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU6() : stm32g0xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32g0xx_ll_pwr.c
  • LL_PWR_DisableBatteryCharging() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableFlashPowerDownInLPRun() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableFlashPowerDownInLPSleep() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableFlashPowerDownInStop() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullDown() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullUp() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableInternWU() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableLPMUResetSamplingMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisablePUPDCfg() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisablePVM() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableSRAMRetention() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableVddIO2() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableVddUSB() : stm32g0xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableFlashPowerDownInLPRun() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableFlashPowerDownInLPSleep() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableFlashPowerDownInStop() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullDown() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullUp() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableInternWU() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableLPMUResetSamplingMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnablePUPDCfg() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnablePVM() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableSRAMRetention() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableVddIO2() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableVddUSB() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32g0xx_ll_pwr.h
  • LL_PWR_EnterLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_ExitLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetPVDHighLevel() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetPVDLowLevel() : stm32g0xx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_FLASH_RDY() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_InternWU() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMOUSB() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPF() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPS() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOS() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU6() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullDown() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullUp() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledInternWU() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledLowPowerRunMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledPUPDCfg() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledPVM() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledSRAMRetention() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledVddIO2() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledVddUSB() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnableFlashPowerDownInLPRun() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnableFlashPowerDownInLPSleep() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnableFlashPowerDownInStop() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsEnableLPMUResetSamplingMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetPVDHighLevel() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetPVDLowLevel() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32g0xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32g0xx_ll_pwr.h
  • LL_RCC_ClearFlag_HSECSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32g0xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32g0xx_ll_rcc.h
  • LL_RCC_ConfigMCO2() : stm32g0xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32g0xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32g0xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetCECClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetCECClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetFDCANClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetFDCANClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetHSIDiv() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetI2SClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetI2SClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetRNGClockDiv() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetRNGClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetRTCClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetRTCClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetTIMClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetTIMClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetUSARTClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32g0xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI48_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI48_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI48_GetCalibration() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI48_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DisableInStopMode() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_EnableInStopMode() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_IsEnabledInStopMode() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PWRRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSI48RDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32g0xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_GetSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_SetSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_DisableCSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_IsCSSDetected() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_ADC() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_FDCAN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_I2S1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_I2S2() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_RNG() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_TIM1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_TIM15() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_USB() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_ADC() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_FDCAN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_I2S1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_I2S2() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_RNG() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SYS() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_TIM1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_TIM15() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_USB() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_ADC() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_FDCAN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_I2S1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_I2S2() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_RNG() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SYS() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_TIM1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_TIM15() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_USB() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetDivider() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetP() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetQ() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_GetR() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_ADC() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_FDCAN() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_I2S1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_I2S2() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_RNG() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_SYS() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_TIM1() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_TIM15() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsEnabledDomain_USB() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32g0xx_ll_rcc.h
  • LL_RCC_PLL_SetMainSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetCECClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetFDCANClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetHSIDiv() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetI2SClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetRNGClockDiv() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetTIMClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32g0xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32g0xx_ll_rcc.h
  • LL_RNG_ClearFlag_CEIS() : stm32g0xx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32g0xx_ll_rng.h
  • LL_RNG_DeInit() : stm32g0xx_ll_rng.c
  • LL_RNG_Disable() : stm32g0xx_ll_rng.h
  • LL_RNG_DisableClkErrorDetect() : stm32g0xx_ll_rng.h
  • LL_RNG_DisableIT() : stm32g0xx_ll_rng.h
  • LL_RNG_Enable() : stm32g0xx_ll_rng.h
  • LL_RNG_EnableClkErrorDetect() : stm32g0xx_ll_rng.h
  • LL_RNG_EnableIT() : stm32g0xx_ll_rng.h
  • LL_RNG_Init() : stm32g0xx_ll_rng.c
  • LL_RNG_IsActiveFlag_CECS() : stm32g0xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32g0xx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32g0xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32g0xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32g0xx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32g0xx_ll_rng.h
  • LL_RNG_IsEnabledClkErrorDetect() : stm32g0xx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32g0xx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32g0xx_ll_rng.h
  • LL_RNG_StructInit() : stm32g0xx_ll_rng.c
  • LL_RTC_ALMA_ConfigTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_ALMA_SetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_ALMB_ConfigTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_ALMB_SetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_BKP_GetRegister() : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_SetRegister() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32g0xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32g0xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32g0xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_DisableAlarmPullUp() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableInitMode() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableOutput2() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableTamperOutput() : stm32g0xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableAlarmPullUp() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableOutput2() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableTamperOutput() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32g0xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32g0xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32g0xx_ll_rtc.c
  • LL_RTC_GetAlarmOutEvent() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32g0xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32g0xx_ll_rtc.h
  • LL_RTC_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP3M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP4M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP5M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITAMP6M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITSM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3M() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOVM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTM() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsAlarmPullUpEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP4() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP5() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ITAMP6() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsOutput2Enabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_IsTamperOutputEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32g0xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32g0xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_TAMPER_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32g0xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32g0xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32g0xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32g0xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32g0xx_ll_rtc.h
  • LL_SetFlashLatency() : stm32g0xx_ll_utils.c
  • LL_SetSystemCoreClock() : stm32g0xx_ll_utils.c
  • LL_SPI_ClearFlag_CRCERR() : stm32g0xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32g0xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32g0xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32g0xx_ll_spi.h
  • LL_SPI_DeInit() : stm32g0xx_ll_spi.c
  • LL_SPI_Disable() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32g0xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32g0xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32g0xx_ll_spi.h
  • LL_SPI_Enable() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32g0xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32g0xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32g0xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32g0xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32g0xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32g0xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32g0xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32g0xx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_GetMode() : stm32g0xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32g0xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32g0xx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32g0xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32g0xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32g0xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32g0xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32g0xx_ll_spi.h
  • LL_SPI_Init() : stm32g0xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32g0xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32g0xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32g0xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32g0xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32g0xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32g0xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32g0xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32g0xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32g0xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32g0xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32g0xx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32g0xx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32g0xx_ll_spi.h
  • LL_SPI_SetMode() : stm32g0xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32g0xx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32g0xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32g0xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32g0xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32g0xx_ll_spi.h
  • LL_SPI_StructInit() : stm32g0xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32g0xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32g0xx_ll_spi.h
  • LL_SYSCFG_ClearFlag_SP() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisableAnalogBooster() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisableClampingDiode() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisableDBATT() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32g0xx_ll_system.h
  • LL_SYSCFG_DisablePinRemap() : stm32g0xx_ll_system.h
  • LL_SYSCFG_EnableAnalogBooster() : stm32g0xx_ll_system.h
  • LL_SYSCFG_EnableClampingDiode() : stm32g0xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32g0xx_ll_system.h
  • LL_SYSCFG_EnablePinRemap() : stm32g0xx_ll_system.h
  • LL_SYSCFG_GetIRModEnvelopeSignal() : stm32g0xx_ll_system.h
  • LL_SYSCFG_GetIRPolarity() : stm32g0xx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32g0xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_ADC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_AES() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_CEC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_CLK_CTRL() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_COMP1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_COMP2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_COMP3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_CRS() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DAC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH5() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH6() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA1_CH7() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMA2_CH5() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_DMAMUX() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI0() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI10() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI11() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI12() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI13() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI14() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI15() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI5() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI6() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI7() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI8() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_EXTI9() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FDCAN1_IT0() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FDCAN1_IT1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FDCAN2_IT0() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FDCAN2_IT1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FLASH_ECC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_FLASH_ITF() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_I2C1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_I2C2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_I2C3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_LPTIM1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_LPTIM2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_LPUART1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_LPUART2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_PVDOUT() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_PVMOUT() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_RNG() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_RTC_WAKEUP() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SPI1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SPI2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SPI3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TAMPER() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM14() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM15() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM16() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM17() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_BRK() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_CC() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_CCU() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_TRG() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM1_UPD() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM6() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_TIM7() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_UCPD1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_UCPD2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART1() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART2() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART3() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART4() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART5() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USART6() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_USB() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_WWDG() : stm32g0xx_ll_system.h
  • LL_SYSCFG_IsEnabledClampingDiode() : stm32g0xx_ll_system.h
  • LL_SYSCFG_SetIRModEnvelopeSignal() : stm32g0xx_ll_system.h
  • LL_SYSCFG_SetIRPolarity() : stm32g0xx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32g0xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32g0xx_ll_system.h
  • LL_SYSTICK_DisableIT() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32g0xx_ll_cortex.h
  • LL_TIM_BDTR_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_CC_DisableChannel() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32g0xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32g0xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32g0xx_ll_tim.h
  • LL_TIM_DeInit() : stm32g0xx_ll_tim.c
  • LL_TIM_DisableAllOutputs() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32g0xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32g0xx_ll_tim.h
  • LL_TIM_DisarmBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_DisarmBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32g0xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32g0xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_GenerateEvent_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32g0xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32g0xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32g0xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32g0xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32g0xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32g0xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32g0xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32g0xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_IsActiveUIFCPY() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32g0xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32g0xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32g0xx_ll_tim.c
  • LL_TIM_ReArmBRK() : stm32g0xx_ll_tim.h
  • LL_TIM_ReArmBRK2() : stm32g0xx_ll_tim.h
  • LL_TIM_SetAutoReload() : stm32g0xx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32g0xx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32g0xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32g0xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32g0xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32g0xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32g0xx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32g0xx_ll_tim.h
  • LL_TIM_SetOCRefClearInputSource() : stm32g0xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32g0xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32g0xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32g0xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32g0xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32g0xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32g0xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32g0xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32g0xx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32g0xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32g0xx_ll_tim.h
  • LL_TIM_StructInit() : stm32g0xx_ll_tim.c
  • LL_UCPD_ClearFlag_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ClearFlag_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DeInit() : stm32g0xx_ll_ucpd.c
  • LL_UCPD_Disable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxNE() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxIS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_DisableIT_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_Enable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxNE() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxIS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EnableIT_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ForceClockDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ForceClockEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_FRSDetectionDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_FRSDetectionEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_GetRole() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_GetTypeCVstateCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_GetTypeCVstateCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_Init() : stm32g0xx_ll_ucpd.c
  • LL_UCPD_IsActiveFlag_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxNE() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxIS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsActiveFlag_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnabled() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnabledRxDMA() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnabledTxDMA() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_FRS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxHRST() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxMsgEnd() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxNE() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_RxOvr() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxHRSTDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxHRSTSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxIS() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGABT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGDISC() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxMSGSENT() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TxUND() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TypeCEventCC1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IsEnableIT_TypeCEventCC2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ReadData() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ReadRxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ReadRxPaySize() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxDMADisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxDMAEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxFilterDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RxFilterEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SendHardReset() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SendMessage() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetccEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetCCPin() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetHbitClockDiv() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetIfrGap() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetPSCClk() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRpResistor() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRxMode() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRxOrdExt1() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetRxOrdExt2() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetSNKRole() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetSRCRole() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetTransWin() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SetTxMode() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SignalFRSTX() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_StructInit() : stm32g0xx_ll_ucpd.c
  • LL_UCPD_TxDMADisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TxDMAEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC1Disable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC1Enable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC2Disable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TypeCDetectionCC2Enable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_VconnDischargeDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_VconnDischargeEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WakeUpDisable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WakeUpEnable() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WriteData() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WriteTxOrderSet() : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WriteTxPaySize() : stm32g0xx_ll_ucpd.h
  • LL_USART_ClearFlag_CM() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_UDR() : stm32g0xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_ClockInit() : stm32g0xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32g0xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigFIFOsThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32g0xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32g0xx_ll_usart.h
  • LL_USART_DeInit() : stm32g0xx_ll_usart.c
  • LL_USART_Disable() : stm32g0xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32g0xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32g0xx_ll_usart.h
  • LL_USART_DisableFIFO() : stm32g0xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32g0xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RXFF() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RXFT() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RXNE_RXFNE() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TXE_TXFNF() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TXFT() : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32g0xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32g0xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32g0xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32g0xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSPISlave() : stm32g0xx_ll_usart.h
  • LL_USART_DisableSPISlaveSelect() : stm32g0xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32g0xx_ll_usart.h
  • LL_USART_Enable() : stm32g0xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32g0xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32g0xx_ll_usart.h
  • LL_USART_EnableFIFO() : stm32g0xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32g0xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RXFF() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RXFT() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RXNE_RXFNE() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TXE_TXFNF() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TXFT() : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32g0xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32g0xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32g0xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32g0xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSPISlave() : stm32g0xx_ll_usart.h
  • LL_USART_EnableSPISlaveSelect() : stm32g0xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32g0xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32g0xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32g0xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32g0xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32g0xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32g0xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32g0xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32g0xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32g0xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32g0xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32g0xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32g0xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32g0xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32g0xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32g0xx_ll_usart.h
  • LL_USART_GetParity() : stm32g0xx_ll_usart.h
  • LL_USART_GetPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_GetRXFIFOThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32g0xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32g0xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32g0xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32g0xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32g0xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32g0xx_ll_usart.h
  • LL_USART_GetTXFIFOThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32g0xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32g0xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32g0xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32g0xx_ll_usart.h
  • LL_USART_Init() : stm32g0xx_ll_usart.c
  • LL_USART_IsActiveFlag_ABR() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFF() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFT() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE_RXFNE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE_TXFNF() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFT() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_UDR() : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledFIFO() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFF() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFT() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE_RXFNE() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TCBGT() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE_TXFNF() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFE() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFT() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSPISlave() : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledSPISlaveSelect() : stm32g0xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32g0xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32g0xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32g0xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32g0xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32g0xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32g0xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32g0xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32g0xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32g0xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32g0xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32g0xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32g0xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32g0xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32g0xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32g0xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32g0xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32g0xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32g0xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32g0xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32g0xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32g0xx_ll_usart.h
  • LL_USART_SetParity() : stm32g0xx_ll_usart.h
  • LL_USART_SetPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_SetRXFIFOThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32g0xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32g0xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32g0xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32g0xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32g0xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32g0xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32g0xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32g0xx_ll_usart.h
  • LL_USART_SetTXFIFOThreshold() : stm32g0xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32g0xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32g0xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32g0xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32g0xx_ll_usart.h
  • LL_USART_StructInit() : stm32g0xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32g0xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32g0xx_ll_usart.h
  • LL_VREFBUF_Disable() : stm32g0xx_ll_system.h
  • LL_VREFBUF_DisableHIZ() : stm32g0xx_ll_system.h
  • LL_VREFBUF_Enable() : stm32g0xx_ll_system.h
  • LL_VREFBUF_EnableHIZ() : stm32g0xx_ll_system.h
  • LL_VREFBUF_GetTrimming() : stm32g0xx_ll_system.h
  • LL_VREFBUF_GetVoltageScaling() : stm32g0xx_ll_system.h
  • LL_VREFBUF_IsVREFReady() : stm32g0xx_ll_system.h
  • LL_VREFBUF_SetTrimming() : stm32g0xx_ll_system.h
  • LL_VREFBUF_SetVoltageScaling() : stm32g0xx_ll_system.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32g0xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32g0xx_ll_wwdg.h
  • LPTIM_Disable() : stm32g0xx_hal_lptim.c
  • LPTIM_ResetCallback() : stm32g0xx_hal_lptim.c
  • LPTIM_WaitForFlag() : stm32g0xx_hal_lptim.c
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STM32G0C1xx HAL User Manual: Globals

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- o -

  • OC1Config() : stm32g0xx_ll_tim.c
  • OC2Config() : stm32g0xx_ll_tim.c
  • OC3Config() : stm32g0xx_ll_tim.c
  • OC4Config() : stm32g0xx_ll_tim.c
  • OC5Config() : stm32g0xx_ll_tim.c
  • OC6Config() : stm32g0xx_ll_tim.c
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STM32G0C1xx HAL User Manual: Globals

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- p -

  • PCD_EP_ISR_Handler() : stm32g0xx_hal_pcd.c
  • PCD_GET_EP_DBUF0_CNT() : stm32g0xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT() : stm32g0xx_hal_pcd.h
  • PCD_GET_EP_RX_CNT() : stm32g0xx_hal_pcd.h
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STM32G0C1xx HAL User Manual: Globals

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- r -

  • RCC_GetHCLKClockFreq() : stm32g0xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32g0xx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_ADC() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_FDCAN() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_I2S1() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_I2S2() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_RNG() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_TIM1() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_TIM15() : stm32g0xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_USB() : stm32g0xx_ll_rcc.c
  • RTC_Bcd2ToByte() : stm32g0xx_hal_rtc.c
  • RTC_ByteToBcd2() : stm32g0xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32g0xx_hal_rtc.c
  • RTC_ExitInitMode() : stm32g0xx_hal_rtc.c
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STM32G0C1xx HAL User Manual: Globals

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- s -

  • SMARTCARD_AdvFeatureConfig() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMAAbortOnError() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_InitCallbacksToDefault() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_RxISR() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_RxISR_FIFOEN() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_TxISR() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_TxISR_FIFOEN() : stm32g0xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32g0xx_hal_smartcard.c
  • SMARTCARDEx_SetNbDataToProcess() : stm32g0xx_hal_smartcard_ex.c
  • SMBUS_ConvertOtherXferOptions() : stm32g0xx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32g0xx_hal_smbus.c
  • SMBUS_Enable_IRQ() : stm32g0xx_hal_smbus.c
  • SMBUS_Flush_TXDR() : stm32g0xx_hal_smbus.c
  • SMBUS_ITErrorHandler() : stm32g0xx_hal_smbus.c
  • SMBUS_Master_ISR() : stm32g0xx_hal_smbus.c
  • SMBUS_Slave_ISR() : stm32g0xx_hal_smbus.c
  • SMBUS_TransferConfig() : stm32g0xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32g0xx_hal_smbus.c
  • SPI_2linesRxISR_16BIT() : stm32g0xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32g0xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32g0xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32g0xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32g0xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32g0xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32g0xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32g0xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32g0xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32g0xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32g0xx_hal_spi.c
  • SPI_DMAAbortOnError() : stm32g0xx_hal_spi.c
  • SPI_DMAError() : stm32g0xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32g0xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32g0xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32g0xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32g0xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32g0xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32g0xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32g0xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32g0xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32g0xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32g0xx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32g0xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32g0xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32g0xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32g0xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32g0xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32g0xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32g0xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32g0xx_hal_spi.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- t -

  • TIM_Base_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_CCxChannelCmd() : stm32g0xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32g0xx_hal_tim_ex.c
  • TIM_DMACaptureCplt() : stm32g0xx_hal_tim.c
  • TIM_DMACaptureHalfCplt() : stm32g0xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32g0xx_hal_tim.c
  • TIM_DMADelayPulseHalfCplt() : stm32g0xx_hal_tim.c
  • TIM_DMADelayPulseNCplt() : stm32g0xx_hal_tim_ex.c
  • TIM_DMAError() : stm32g0xx_hal_tim.c
  • TIM_DMAErrorCCxN() : stm32g0xx_hal_tim_ex.c
  • TIM_DMAPeriodElapsedCplt() : stm32g0xx_hal_tim.c
  • TIM_DMAPeriodElapsedHalfCplt() : stm32g0xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32g0xx_hal_tim.c
  • TIM_DMATriggerHalfCplt() : stm32g0xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_ITRx_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_ResetCallback() : stm32g0xx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32g0xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TI2_ConfigInputStage() : stm32g0xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32g0xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32g0xx_hal_tim.c
  • TIMEx_DMACommutationCplt() : stm32g0xx_hal_tim_ex.c
  • TIMEx_DMACommutationHalfCplt() : stm32g0xx_hal_tim_ex.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- u -

  • UART_AdvFeatureConfig() : stm32g0xx_hal_uart.c
  • UART_CheckIdleState() : stm32g0xx_hal_uart.c
  • UART_DMAAbortOnError() : stm32g0xx_hal_uart.c
  • UART_DMAError() : stm32g0xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32g0xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32g0xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32g0xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32g0xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32g0xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32g0xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32g0xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32g0xx_hal_uart.c
  • UART_EndRxTransfer() : stm32g0xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32g0xx_hal_uart.c
  • UART_EndTxTransfer() : stm32g0xx_hal_uart.c
  • UART_InitCallbacksToDefault() : stm32g0xx_hal_uart.c
  • UART_RxISR_16BIT() : stm32g0xx_hal_uart.c
  • UART_RxISR_16BIT_FIFOEN() : stm32g0xx_hal_uart.c
  • UART_RxISR_8BIT() : stm32g0xx_hal_uart.c
  • UART_RxISR_8BIT_FIFOEN() : stm32g0xx_hal_uart.c
  • UART_SetConfig() : stm32g0xx_hal_uart.c
  • UART_Start_Receive_DMA() : stm32g0xx_hal_uart.c
  • UART_Start_Receive_IT() : stm32g0xx_hal_uart.c
  • UART_TxISR_16BIT() : stm32g0xx_hal_uart.c
  • UART_TxISR_16BIT_FIFOEN() : stm32g0xx_hal_uart.c
  • UART_TxISR_8BIT() : stm32g0xx_hal_uart.c
  • UART_TxISR_8BIT_FIFOEN() : stm32g0xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32g0xx_hal_uart.c
  • UARTEx_SetNbDataToProcess() : stm32g0xx_hal_uart_ex.c
  • UARTEx_Wakeup_AddressConfig() : stm32g0xx_hal_uart_ex.c
  • USART_CheckIdleState() : stm32g0xx_hal_usart.c
  • USART_DMAAbortOnError() : stm32g0xx_hal_usart.c
  • USART_DMAError() : stm32g0xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32g0xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32g0xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32g0xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32g0xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32g0xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32g0xx_hal_usart.c
  • USART_EndTransfer() : stm32g0xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32g0xx_hal_usart.c
  • USART_InitCallbacksToDefault() : stm32g0xx_hal_usart.c
  • USART_RxISR_16BIT() : stm32g0xx_hal_usart.c
  • USART_RxISR_16BIT_FIFOEN() : stm32g0xx_hal_usart.c
  • USART_RxISR_8BIT() : stm32g0xx_hal_usart.c
  • USART_RxISR_8BIT_FIFOEN() : stm32g0xx_hal_usart.c
  • USART_SetConfig() : stm32g0xx_hal_usart.c
  • USART_TxISR_16BIT() : stm32g0xx_hal_usart.c
  • USART_TxISR_16BIT_FIFOEN() : stm32g0xx_hal_usart.c
  • USART_TxISR_8BIT() : stm32g0xx_hal_usart.c
  • USART_TxISR_8BIT_FIFOEN() : stm32g0xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32g0xx_hal_usart.c
  • USARTEx_SetNbDataToProcess() : stm32g0xx_hal_usart_ex.c
  • UTILS_EnablePLLAndSwitchSystem() : stm32g0xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32g0xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32g0xx_ll_utils.c
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STM32G0C1xx HAL User Manual: Globals

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  • CHANNEL_OFFSET_TAB : stm32g0xx_ll_dma.h
  • DLCtoBytes : stm32g0xx_hal_fdcan.c
  • LPUART_PRESCALER_TAB : stm32g0xx_ll_lpuart.h
  • OFFSET_TAB_CCMRx : stm32g0xx_ll_tim.h
  • pFlash : stm32g0xx_hal_flash.c , stm32g0xx_hal_flash.h
  • SHIFT_TAB_CCxP : stm32g0xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32g0xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32g0xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32g0xx_ll_tim.h
  • UARTPrescTable : stm32g0xx_hal_uart.c , stm32g0xx_hal_uart.h
  • USART_PRESCALER_TAB : stm32g0xx_ll_usart.h
  • uwTick : stm32g0xx_hal.c , stm32g0xx_hal.h
  • uwTickFreq : stm32g0xx_hal.h , stm32g0xx_hal.c
  • uwTickPrio : stm32g0xx_hal.h , stm32g0xx_hal.c
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STM32G0C1xx HAL User Manual: Globals

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- a -

  • ADC_HandleTypeDef : stm32g0xx_hal_adc.h

- c -

  • CEC_HandleTypeDef : stm32g0xx_hal_cec.h
  • COMP_HandleTypeDef : stm32g0xx_hal_comp.h
  • CRYP_HandleTypeDef : stm32g0xx_hal_cryp.h

- d -

  • DAC_HandleTypeDef : stm32g0xx_hal_dac.h
  • DMA_HandleTypeDef : stm32g0xx_hal_dma.h

- f -

  • FDCAN_HandleTypeDef : stm32g0xx_hal_fdcan.h

- h -

  • HAL_CEC_StateTypeDef : stm32g0xx_hal_cec.h
  • HAL_IRDA_StateTypeDef : stm32g0xx_hal_irda.h
  • HAL_SMARTCARD_StateTypeDef : stm32g0xx_hal_smartcard.h
  • HAL_UART_RxEventTypeTypeDef : stm32g0xx_hal_uart.h
  • HAL_UART_RxTypeTypeDef : stm32g0xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32g0xx_hal_uart.h
  • HCD_HandleTypeDef : stm32g0xx_hal_hcd.h
  • HCD_HCStateTypeDef : stm32g0xx_hal_hcd.h
  • HCD_HCTypeDef : stm32g0xx_hal_hcd.h
  • HCD_InitTypeDef : stm32g0xx_hal_hcd.h
  • HCD_TypeDef : stm32g0xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32g0xx_hal_hcd.h

- i -

  • I2C_HandleTypeDef : stm32g0xx_hal_i2c.h
  • I2S_HandleTypeDef : stm32g0xx_hal_i2s.h
  • IRDA_HandleTypeDef : stm32g0xx_hal_irda.h

- l -

  • LPTIM_HandleTypeDef : stm32g0xx_hal_lptim.h

- p -

  • pADC_CallbackTypeDef : stm32g0xx_hal_adc.h
  • PCD_EPTypeDef : stm32g0xx_hal_pcd.h
  • PCD_HandleTypeDef : stm32g0xx_hal_pcd.h
  • PCD_InitTypeDef : stm32g0xx_hal_pcd.h
  • PCD_TypeDef : stm32g0xx_hal_pcd.h
  • pCEC_CallbackTypeDef : stm32g0xx_hal_cec.h
  • pCEC_RxCallbackTypeDef : stm32g0xx_hal_cec.h
  • pCOMP_CallbackTypeDef : stm32g0xx_hal_comp.h
  • pCRYP_CallbackTypeDef : stm32g0xx_hal_cryp.h
  • pDAC_CallbackTypeDef : stm32g0xx_hal_dac.h
  • pFDCAN_CallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_ErrorStatusCallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_RxFifo0CallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_RxFifo1CallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_TxBufferAbortCallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_TxBufferCompleteCallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pFDCAN_TxEventFifoCallbackTypeDef : stm32g0xx_hal_fdcan.h
  • pHCD_CallbackTypeDef : stm32g0xx_hal_hcd.h
  • pHCD_HC_NotifyURBChangeCallbackTypeDef : stm32g0xx_hal_hcd.h
  • pI2C_AddrCallbackTypeDef : stm32g0xx_hal_i2c.h
  • pI2C_CallbackTypeDef : stm32g0xx_hal_i2c.h
  • pI2S_CallbackTypeDef : stm32g0xx_hal_i2s.h
  • pIRDA_CallbackTypeDef : stm32g0xx_hal_irda.h
  • pLPTIM_CallbackTypeDef : stm32g0xx_hal_lptim.h
  • pPCD_BcdCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_CallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_DataInStageCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_DataOutStageCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_IsoInIncpltCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_IsoOutIncpltCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pPCD_LpmCallbackTypeDef : stm32g0xx_hal_pcd.h
  • pRNG_CallbackTypeDef : stm32g0xx_hal_rng.h
  • pRNG_ReadyDataCallbackTypeDef : stm32g0xx_hal_rng.h
  • pRTC_CallbackTypeDef : stm32g0xx_hal_rtc.h
  • pSMARTCARD_CallbackTypeDef : stm32g0xx_hal_smartcard.h
  • pSMBUS_AddrCallbackTypeDef : stm32g0xx_hal_smbus.h
  • pSMBUS_CallbackTypeDef : stm32g0xx_hal_smbus.h
  • pSPI_CallbackTypeDef : stm32g0xx_hal_spi.h
  • pTIM_CallbackTypeDef : stm32g0xx_hal_tim.h
  • pUART_CallbackTypeDef : stm32g0xx_hal_uart.h
  • pUART_RxEventCallbackTypeDef : stm32g0xx_hal_uart.h
  • pUSART_CallbackTypeDef : stm32g0xx_hal_usart.h
  • pWWDG_CallbackTypeDef : stm32g0xx_hal_wwdg.h

- r -

  • RNG_HandleTypeDef : stm32g0xx_hal_rng.h
  • RTC_HandleTypeDef : stm32g0xx_hal_rtc.h

- s -

  • SMARTCARD_HandleTypeDef : stm32g0xx_hal_smartcard.h
  • SMBUS_HandleTypeDef : stm32g0xx_hal_smbus.h
  • SPI_HandleTypeDef : stm32g0xx_hal_spi.h

- t -

  • TIM_HandleTypeDef : stm32g0xx_hal_tim.h

- u -

  • UART_HandleTypeDef : stm32g0xx_hal_uart.h
  • USART_HandleTypeDef : stm32g0xx_hal_usart.h

- w -

  • WWDG_HandleTypeDef : stm32g0xx_hal_wwdg.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • e
  • g
  • h
  • i
  • p
  • s
  • u

- e -

  • EXTI_CallbackIDTypeDef : stm32g0xx_hal_exti.h

- g -

  • GPIO_PinState : stm32g0xx_hal_gpio.h

- h -

  • HAL_ADC_CallbackIDTypeDef : stm32g0xx_hal_adc.h
  • HAL_CEC_CallbackIDTypeDef : stm32g0xx_hal_cec.h
  • HAL_COMP_CallbackIDTypeDef : stm32g0xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32g0xx_hal_comp.h
  • HAL_CRC_StateTypeDef : stm32g0xx_hal_crc.h
  • HAL_CRYP_CallbackIDTypeDef : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATETypeDef : stm32g0xx_hal_cryp.h
  • HAL_DAC_CallbackIDTypeDef : stm32g0xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32g0xx_hal_dac.h
  • HAL_DMA_CallbackIDTypeDef : stm32g0xx_hal_dma.h
  • HAL_DMA_LevelCompleteTypeDef : stm32g0xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32g0xx_hal_dma.h
  • HAL_FDCAN_CallbackIDTypeDef : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_StateTypeDef : stm32g0xx_hal_fdcan.h
  • HAL_HCD_CallbackIDTypeDef : stm32g0xx_hal_hcd.h
  • HAL_I2C_CallbackIDTypeDef : stm32g0xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32g0xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32g0xx_hal_i2c.h
  • HAL_I2S_CallbackIDTypeDef : stm32g0xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32g0xx_hal_i2s.h
  • HAL_IRDA_CallbackIDTypeDef : stm32g0xx_hal_irda.h
  • HAL_LPTIM_CallbackIDTypeDef : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32g0xx_hal_lptim.h
  • HAL_PCD_CallbackIDTypeDef : stm32g0xx_hal_pcd.h
  • HAL_RNG_CallbackIDTypeDef : stm32g0xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32g0xx_hal_rng.h
  • HAL_RTC_CallbackIDTypeDef : stm32g0xx_hal_rtc.h
  • HAL_RTCStateTypeDef : stm32g0xx_hal_rtc.h
  • HAL_SMARTCARD_CallbackIDTypeDef : stm32g0xx_hal_smartcard.h
  • HAL_SMBUS_CallbackIDTypeDef : stm32g0xx_hal_smbus.h
  • HAL_SPI_CallbackIDTypeDef : stm32g0xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32g0xx_hal_spi.h
  • HAL_SuspendTypeDef : stm32g0xx_hal_cryp.h
  • HAL_TickFreqTypeDef : stm32g0xx_hal.h
  • HAL_TIM_ActiveChannel : stm32g0xx_hal_tim.h
  • HAL_TIM_CallbackIDTypeDef : stm32g0xx_hal_tim.h
  • HAL_TIM_ChannelStateTypeDef : stm32g0xx_hal_tim.h
  • HAL_TIM_DMABurstStateTypeDef : stm32g0xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32g0xx_hal_tim.h
  • HAL_UART_CallbackIDTypeDef : stm32g0xx_hal_uart.h
  • HAL_USART_CallbackIDTypeDef : stm32g0xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32g0xx_hal_usart.h
  • HAL_WWDG_CallbackIDTypeDef : stm32g0xx_hal_wwdg.h
  • HCD_HostStateTypeDef : stm32g0xx_hal_hcd.h
  • HCD_StateTypeDef : stm32g0xx_hal_hcd.h

- i -

  • IRDA_ClockSourceTypeDef : stm32g0xx_hal_irda.h

- p -

  • PCD_BCD_MsgTypeDef : stm32g0xx_hal_pcd.h
  • PCD_LPM_MsgTypeDef : stm32g0xx_hal_pcd.h
  • PCD_LPM_StateTypeDef : stm32g0xx_hal_pcd.h
  • PCD_StateTypeDef : stm32g0xx_hal_pcd.h

- s -

  • SMARTCARD_ClockSourceTypeDef : stm32g0xx_hal_smartcard.h

- u -

  • UART_ClockSourceTypeDef : stm32g0xx_hal_uart.h
  • USART_ClockSourceTypeDef : stm32g0xx_hal_usart.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- g -

  • GPIO_PIN_RESET : stm32g0xx_hal_gpio.h
  • GPIO_PIN_SET : stm32g0xx_hal_gpio.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • g
  • h
  • i
  • l
  • p
  • s
  • u

- h -

  • HAL_ADC_CONVERSION_COMPLETE_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_CONVERSION_HALF_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_END_OF_SAMPLING_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_MSPDEINIT_CB_ID : stm32g0xx_hal_adc.h
  • HAL_ADC_MSPINIT_CB_ID : stm32g0xx_hal_adc.h
  • HAL_CEC_ERROR_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_MSPDEINIT_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_MSPINIT_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_RX_CPLT_CB_ID : stm32g0xx_hal_cec.h
  • HAL_CEC_TX_CPLT_CB_ID : stm32g0xx_hal_cec.h
  • HAL_COMP_MSPDEINIT_CB_ID : stm32g0xx_hal_comp.h
  • HAL_COMP_MSPINIT_CB_ID : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_BUSY : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32g0xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32g0xx_hal_comp.h
  • HAL_COMP_TRIGGER_CB_ID : stm32g0xx_hal_comp.h
  • HAL_CRC_STATE_BUSY : stm32g0xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32g0xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32g0xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32g0xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32g0xx_hal_crc.h
  • HAL_CRYP_ERROR_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_INPUT_COMPLETE_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_MSPDEINIT_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_MSPINIT_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATE_BUSY : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32g0xx_hal_cryp.h
  • HAL_CRYP_STATE_SUSPENDED : stm32g0xx_hal_cryp.h
  • HAL_CRYP_SUSPEND : stm32g0xx_hal_cryp.h
  • HAL_CRYP_SUSPEND_NONE : stm32g0xx_hal_cryp.h
  • HAL_DAC_ALL_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH1_COMPLETE_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH1_ERROR_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH1_HALF_COMPLETE_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH1_UNDERRUN_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH2_COMPLETE_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH2_ERROR_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH2_HALF_COMPLETE_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_CH2_UNDERRUN_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_MSPDEINIT_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_MSPINIT_CB_ID : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_BUSY : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32g0xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32g0xx_hal_dac.h
  • HAL_DMA_BURST_STATE_BUSY : stm32g0xx_hal_tim.h
  • HAL_DMA_BURST_STATE_READY : stm32g0xx_hal_tim.h
  • HAL_DMA_BURST_STATE_RESET : stm32g0xx_hal_tim.h
  • HAL_DMA_FULL_TRANSFER : stm32g0xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32g0xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32g0xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32g0xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32g0xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_ABORT_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32g0xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32g0xx_hal_dma.h
  • HAL_EXTI_COMMON_CB_ID : stm32g0xx_hal_exti.h
  • HAL_EXTI_FALLING_CB_ID : stm32g0xx_hal_exti.h
  • HAL_EXTI_RISING_CB_ID : stm32g0xx_hal_exti.h
  • HAL_FDCAN_ERROR_CALLBACK_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_MSPDEINIT_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_MSPINIT_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_STATE_BUSY : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_STATE_ERROR : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_STATE_READY : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_STATE_RESET : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : stm32g0xx_hal_fdcan.h
  • HAL_HCD_CONNECT_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_DISCONNECT_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_MSPDEINIT_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_MSPINIT_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_PORT_DISABLED_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_PORT_ENABLED_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_SOF_CB_ID : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_BUSY : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32g0xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32g0xx_hal_hcd.h
  • HAL_I2C_ABORT_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_LISTEN_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODE_MASTER : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32g0xx_hal_i2c.h
  • HAL_I2C_MSPDEINIT_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_MSPINIT_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_ABORT : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32g0xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32g0xx_hal_i2c.h
  • HAL_I2S_ERROR_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_MSPDEINIT_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_MSPINIT_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_RX_COMPLETE_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_RX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32g0xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32g0xx_hal_i2s.h
  • HAL_I2S_TX_COMPLETE_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_I2S_TX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_i2s.h
  • HAL_IRDA_ABORT_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_MSPDEINIT_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_MSPINIT_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_RX_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_TX_COMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_irda.h
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_MATCH_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_COMPARE_WRITE_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_UP_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_MSPDEINIT_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_MSPINIT_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32g0xx_hal_lptim.h
  • HAL_LPTIM_TRIGGER_CB_ID : stm32g0xx_hal_lptim.h
  • HAL_PCD_CONNECT_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_DISCONNECT_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_MSPDEINIT_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_MSPINIT_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_RESET_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_RESUME_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_SETUPSTAGE_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_SOF_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_BUSY : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32g0xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32g0xx_hal_pcd.h
  • HAL_PCD_SUSPEND_CB_ID : stm32g0xx_hal_pcd.h
  • HAL_RNG_ERROR_CB_ID : stm32g0xx_hal_rng.h
  • HAL_RNG_MSPDEINIT_CB_ID : stm32g0xx_hal_rng.h
  • HAL_RNG_MSPINIT_CB_ID : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_BUSY : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32g0xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32g0xx_hal_rng.h
  • HAL_RTC_ALARM_A_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_ALARM_B_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_MSPDEINIT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_MSPINIT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_BUSY : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32g0xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32g0xx_hal_rtc.h
  • HAL_RTC_TAMPER1_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_TAMPER2_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_TAMPER3_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : stm32g0xx_hal_rtc.h
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_MSPDEINIT_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_MSPINIT_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : stm32g0xx_hal_smartcard.h
  • HAL_SMBUS_ERROR_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MSPDEINIT_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MSPINIT_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : stm32g0xx_hal_smbus.h
  • HAL_SPI_ABORT_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_MSPDEINIT_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_MSPINIT_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_RX_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_RX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_ABORT : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32g0xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32g0xx_hal_spi.h
  • HAL_SPI_TX_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_TX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_TX_RX_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : stm32g0xx_hal_spi.h
  • HAL_TICK_FREQ_100HZ : stm32g0xx_hal.h
  • HAL_TICK_FREQ_10HZ : stm32g0xx_hal.h
  • HAL_TICK_FREQ_1KHZ : stm32g0xx_hal.h
  • HAL_TICK_FREQ_DEFAULT : stm32g0xx_hal.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32g0xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32g0xx_hal_tim.h
  • HAL_TIM_BASE_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_BASE_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_BREAK2_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_BREAK_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_BUSY : stm32g0xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_READY : stm32g0xx_hal_tim.h
  • HAL_TIM_CHANNEL_STATE_RESET : stm32g0xx_hal_tim.h
  • HAL_TIM_COMMUTATION_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_COMMUTATION_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_ENCODER_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_ERROR_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_IC_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_OC_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_OC_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PWM_MSPDEINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PWM_MSPINIT_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32g0xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32g0xx_hal_tim.h
  • HAL_TIM_TRIGGER_CB_ID : stm32g0xx_hal_tim.h
  • HAL_TIM_TRIGGER_HALF_CB_ID : stm32g0xx_hal_tim.h
  • HAL_UART_ABORT_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_MSPDEINIT_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_MSPINIT_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_RX_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_RX_FIFO_FULL_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_RX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_TX_COMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_TX_FIFO_EMPTY_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_TX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_uart.h
  • HAL_UART_WAKEUP_CB_ID : stm32g0xx_hal_uart.h
  • HAL_USART_ABORT_COMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_MSPDEINIT_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_MSPINIT_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_RX_COMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_RX_FIFO_FULL_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_RX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_BUSY : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32g0xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32g0xx_hal_usart.h
  • HAL_USART_TX_COMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_TX_FIFO_EMPTY_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_TX_HALFCOMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_USART_TX_RX_COMPLETE_CB_ID : stm32g0xx_hal_usart.h
  • HAL_WWDG_EWI_CB_ID : stm32g0xx_hal_wwdg.h
  • HAL_WWDG_MSPINIT_CB_ID : stm32g0xx_hal_wwdg.h
  • HCD_HCD_STATE_CONNECTED : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_DISCONNECTED : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_RESETED : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_RESUME : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_RUN : stm32g0xx_hal_hcd.h
  • HCD_HCD_STATE_SUSPEND : stm32g0xx_hal_hcd.h
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STM32G0C1xx HAL User Manual: Globals

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- i -

  • IRDA_CLOCKSOURCE_HSI : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32g0xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32g0xx_hal_irda.h
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STM32G0C1xx HAL User Manual: Globals

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- l -

  • LPM_L0 : stm32g0xx_hal_pcd.h
  • LPM_L1 : stm32g0xx_hal_pcd.h
  • LPM_L2 : stm32g0xx_hal_pcd.h
  • LPM_L3 : stm32g0xx_hal_pcd.h
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STM32G0C1xx HAL User Manual: Globals

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- p -

  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32g0xx_hal_pcd.h
  • PCD_BCD_CONTACT_DETECTION : stm32g0xx_hal_pcd.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32g0xx_hal_pcd.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32g0xx_hal_pcd.h
  • PCD_BCD_ERROR : stm32g0xx_hal_pcd.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32g0xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32g0xx_hal_pcd.h
  • PCD_LPM_L1_ACTIVE : stm32g0xx_hal_pcd.h
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STM32G0C1xx HAL User Manual: Globals

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- s -

  • SMARTCARD_CLOCKSOURCE_HSI : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32g0xx_hal_smartcard.h
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STM32G0C1xx HAL User Manual: Globals

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- u -

  • UART_CLOCKSOURCE_HSI : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32g0xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32g0xx_hal_uart.h
  • USART_CLOCKSOURCE_HSI : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32g0xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32g0xx_hal_usart.h
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STM32G0C1xx HAL User Manual: Globals

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- _ -

  • __ADC_PTR_REG_OFFSET : stm32g0xx_ll_adc.h
  • __COMP_PTR_REG_OFFSET : stm32g0xx_ll_comp.h
  • __DAC_PTR_REG_OFFSET : stm32g0xx_ll_dac.h
  • __HAL_ADC_CALC_DATA_TO_VOLTAGE : stm32g0xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE : stm32g0xx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32g0xx_hal_adc.h
  • __HAL_ADC_CALC_VREFANALOG_VOLTAGE : stm32g0xx_hal_adc.h
  • __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32g0xx_hal_adc.h
  • __HAL_ADC_CHANNEL_TO_DECIMAL_NB : stm32g0xx_hal_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32g0xx_hal_adc.h
  • __HAL_ADC_COMMON_INSTANCE : stm32g0xx_hal_adc.h
  • __HAL_ADC_CONVERT_DATA_RESOLUTION : stm32g0xx_hal_adc.h
  • __HAL_ADC_DECIMAL_NB_TO_CHANNEL : stm32g0xx_hal_adc.h
  • __HAL_ADC_DIGITAL_SCALE : stm32g0xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32g0xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32g0xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32g0xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32g0xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL : stm32g0xx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32g0xx_hal_adc.h
  • __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32g0xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32g0xx_hal_adc.h
  • __HAL_CEC_CLEAR_FLAG : stm32g0xx_hal_cec.h
  • __HAL_CEC_CLEAR_OAR : stm32g0xx_hal_cec.h
  • __HAL_CEC_DISABLE : stm32g0xx_hal_cec.h
  • __HAL_CEC_DISABLE_IT : stm32g0xx_hal_cec.h
  • __HAL_CEC_ENABLE : stm32g0xx_hal_cec.h
  • __HAL_CEC_ENABLE_IT : stm32g0xx_hal_cec.h
  • __HAL_CEC_FIRST_BYTE_TX_SET : stm32g0xx_hal_cec.h
  • __HAL_CEC_GET_FLAG : stm32g0xx_hal_cec.h
  • __HAL_CEC_GET_IT_SOURCE : stm32g0xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_END_FLAG : stm32g0xx_hal_cec.h
  • __HAL_CEC_GET_TRANSMISSION_START_FLAG : stm32g0xx_hal_cec.h
  • __HAL_CEC_LAST_BYTE_TX_SET : stm32g0xx_hal_cec.h
  • __HAL_CEC_RESET_HANDLE_STATE : stm32g0xx_hal_cec.h
  • __HAL_CEC_SET_OAR : stm32g0xx_hal_cec.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_EVENT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_IT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GENERATE_SWIT : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_COMP3_EXTI_GET_RISING_FLAG : stm32g0xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32g0xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32g0xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32g0xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32g0xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32g0xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32g0xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32g0xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32g0xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32g0xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32g0xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32g0xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32g0xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32g0xx_hal_crc.h
  • __HAL_CRYP_CLEAR_FLAG : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_DISABLE : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_GET_IT_SOURCE : stm32g0xx_hal_cryp.h
  • __HAL_CRYP_RESET_HANDLE_STATE : stm32g0xx_hal_cryp.h
  • __HAL_DAC_CLEAR_FLAG : stm32g0xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32g0xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32g0xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32g0xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32g0xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32g0xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32g0xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32g0xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32g0xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM2 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM14 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM15 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32g0xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32g0xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32g0xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32g0xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32g0xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32g0xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32g0xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32g0xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32g0xx_hal_dma.h
  • __HAL_FDCAN_CLEAR_FLAG : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_CLEAR_IT : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_DISABLE_IT : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_ENABLE_IT : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_GET_FLAG : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_GET_IT_SOURCE : stm32g0xx_hal_fdcan.h
  • __HAL_FDCAN_RESET_HANDLE_STATE : stm32g0xx_hal_fdcan.h
  • __HAL_FLASH_CLEAR_FLAG : stm32g0xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32g0xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32g0xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32g0xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32g0xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32g0xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32g0xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32g0xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32g0xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32g0xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32g0xx_hal_flash.h
  • __HAL_GET_PENDING_IT : stm32g0xx_hal.h
  • __HAL_GPIO_EXTI_CLEAR_FALLING_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_RISING_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FALLING_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32g0xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_RISING_IT : stm32g0xx_hal_gpio.h
  • __HAL_HCD_CLEAR_FLAG : stm32g0xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32g0xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32g0xx_hal_hcd.h
  • __HAL_HCD_GET_CHDIR : stm32g0xx_hal_hcd.h
  • __HAL_HCD_GET_CHNUM : stm32g0xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32g0xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32g0xx_hal_hcd.h
  • __HAL_I2C_CLEAR_FLAG : stm32g0xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32g0xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32g0xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32g0xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32g0xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32g0xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32g0xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32g0xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32g0xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32g0xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32g0xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32g0xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32g0xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32g0xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32g0xx_hal_i2s.h
  • __HAL_I2S_FLUSH_RX_DR : stm32g0xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32g0xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32g0xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32g0xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32g0xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32g0xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32g0xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32g0xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32g0xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32g0xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32g0xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32g0xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32g0xx_hal_iwdg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32g0xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT : stm32g0xx_hal_lptim.c
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT : stm32g0xx_hal_lptim.c
  • __HAL_PCD_CLEAR_FLAG : stm32g0xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32g0xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32g0xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32g0xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32g0xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32g0xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVD_EXTI_GET_RISING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_EVENT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_IT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_EVENT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_IT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_GENERATE_SWIT : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_PWR_PVM_EXTI_GET_RISING_FLAG : stm32g0xx_hal_pwr_ex.h
  • __HAL_RCC_ADC_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AES_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AHB_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_AHB_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CEC_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CEC_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_CRS_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_DAC1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DAC1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DBGMCU_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_FDCAN_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FDCAN_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_FLASH_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_CEC_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FDCAN_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2S1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2S2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_PLLCLKOUT_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_RNG_DIV : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GET_TIM15_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_TIM1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_I2S1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_I2S2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_IOP_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_IOP_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LPUART2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_MCO2_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RNGDIV_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_RTC_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SRAM_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SRAM_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM14_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_UCPD2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART4_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART5_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32g0xx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32g0xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32g0xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32g0xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32g0xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32g0xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32g0xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32g0xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32g0xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32g0xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32g0xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32g0xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H : stm32g0xx_hal_rtc.h
  • __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H : stm32g0xx_hal_rtc.h
  • __HAL_RTC_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_IS_CALENDAR_INITIALIZED : stm32g0xx_hal_rtc.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_EXTI_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPOE_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPTS_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32g0xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32g0xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32g0xx_hal_rtc.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32g0xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32g0xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32g0xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32g0xx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32g0xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32g0xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32g0xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32g0xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32g0xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32g0xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32g0xx_hal_spi.h
  • __HAL_SYSCFG_BREAK_DISABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_ECC_LOCK : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_ENABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32g0xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK : stm32g0xx_hal.h
  • __HAL_SYSCFG_CLAMPINGDIODE_DISABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_CLAMPINGDIODE_ENABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_CLEAR_FLAG : stm32g0xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_GET_BOOT_MODE : stm32g0xx_hal.h
  • __HAL_SYSCFG_GET_IRDA_ENV_SELECTION : stm32g0xx_hal.h
  • __HAL_SYSCFG_GET_PENDING_IT : stm32g0xx_hal.h
  • __HAL_SYSCFG_GET_POLARITY : stm32g0xx_hal.h
  • __HAL_SYSCFG_IRDA_ENV_SELECTION : stm32g0xx_hal.h
  • __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION : stm32g0xx_hal.h
  • __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE : stm32g0xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32g0xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32g0xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32g0xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32g0xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxFAST : stm32g0xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxFAST : stm32g0xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32g0xx_hal_tim.h
  • __HAL_TIM_GET_UIFCPY : stm32g0xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32g0xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32g0xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32g0xx_hal_tim.h
  • __HAL_TIM_SELECT_CCDMAREQUEST : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32g0xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32g0xx_hal_tim.h
  • __HAL_TIM_UIFREMAP_DISABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_UIFREMAP_ENABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32g0xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32g0xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32g0xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32g0xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32g0xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32g0xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32g0xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32g0xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32g0xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32g0xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32g0xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32g0xx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32g0xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32g0xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32g0xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32g0xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32g0xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32g0xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32g0xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32g0xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32g0xx_hal_usart.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32g0xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32g0xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32g0xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32g0xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32g0xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32g0xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32g0xx_ll_adc.h
  • __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW : stm32g0xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32g0xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32g0xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32g0xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32g0xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32g0xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32g0xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32g0xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32g0xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32g0xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32g0xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32g0xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32g0xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32g0xx_ll_adc.h
  • __LL_COMP_COMMON_INSTANCE : stm32g0xx_ll_comp.h
  • __LL_CRS_CALC_CALCULATE_RELOADVALUE : stm32g0xx_ll_crs.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32g0xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32g0xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32g0xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32g0xx_ll_dac.h
  • __LL_DMA_GET_CHANNEL : stm32g0xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32g0xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32g0xx_ll_dma.h
  • __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL : stm32g0xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32g0xx_ll_i2c.h
  • __LL_LPUART_DIV : stm32g0xx_ll_lpuart.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_HSI_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_ADC_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FDCAN_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_I2S1_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_I2S2_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_RNG_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_TIM15_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_TIM1_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_USB_FREQ : stm32g0xx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32g0xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32g0xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32g0xx_ll_rtc.h
  • __LL_TIM_CALC_ARR : stm32g0xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32g0xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32g0xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32g0xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32g0xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32g0xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32g0xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32g0xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32g0xx_ll_usart.h
  • __STM32G0xx_HAL_VERSION : stm32g0xx_hal.c
  • __STM32G0xx_HAL_VERSION_MAIN : stm32g0xx_hal.c
  • __STM32G0xx_HAL_VERSION_RC : stm32g0xx_hal.c
  • __STM32G0xx_HAL_VERSION_SUB1 : stm32g0xx_hal.c
  • __STM32G0xx_HAL_VERSION_SUB2 : stm32g0xx_hal.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- a -

  • ADC_ANALOGWATCHDOG_1 : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_2 : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_3 : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32g0xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32g0xx_hal_adc.h
  • ADC_AWD1_EVENT : stm32g0xx_hal_adc.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32g0xx_hal_adc.h
  • ADC_AWD2_EVENT : stm32g0xx_hal_adc.h
  • ADC_AWD3_EVENT : stm32g0xx_hal_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32g0xx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_AWD_EVENT : stm32g0xx_hal_adc.h
  • ADC_AWD_TR1_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_POS : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_SHIFT4 : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32g0xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CALIBRATION_TIMEOUT : stm32g0xx_hal_adc_ex.c
  • ADC_CFGR1_AUTOOFF : stm32g0xx_hal_adc.h
  • ADC_CFGR1_AUTOWAIT : stm32g0xx_hal_adc.h
  • ADC_CFGR1_AWDSGL_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CFGR1_CONTINUOUS : stm32g0xx_hal_adc.h
  • ADC_CFGR1_DMACONTREQ : stm32g0xx_hal_adc.h
  • ADC_CFGR1_OVERRUN : stm32g0xx_hal_adc.h
  • ADC_CFGR1_REG_DISCCONTINUOUS : stm32g0xx_hal_adc.h
  • ADC_CFGR1_RES_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_0 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_CONF_RDY_TIMEOUT : stm32g0xx_hal_adc.c
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_SEQ : stm32g0xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32g0xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32g0xx_hal_adc.h
  • ADC_CHSELR_CHSEL0_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL10_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL11_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL12_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL13_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL14_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL15_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL16_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL17_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL18_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL1_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL2_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL3_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL4_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL5_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL6_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL7_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL8_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_CHSEL9_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_CHSELR_SQ2_TO_SQ8 : stm32g0xx_hal_adc.c
  • ADC_CLEAR_ERRORCODE : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32g0xx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32g0xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32g0xx_hal_adc.h
  • ADC_CR_BITS_PROPERTY_RS : stm32g0xx_ll_adc.h
  • ADC_DATAALIGN_LEFT : stm32g0xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32g0xx_hal_adc.h
  • ADC_DISABLE_TIMEOUT : stm32g0xx_hal_adc_ex.c , stm32g0xx_hal_adc.c
  • ADC_ENABLE_TIMEOUT : stm32g0xx_hal_adc.c
  • ADC_EOC_SEQ_CONV : stm32g0xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32g0xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC4 : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32g0xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32g0xx_hal_adc.h
  • ADC_FLAG_AWD1 : stm32g0xx_hal_adc.h
  • ADC_FLAG_AWD2 : stm32g0xx_hal_adc.h
  • ADC_FLAG_AWD3 : stm32g0xx_hal_adc.h
  • ADC_FLAG_CCRDY : stm32g0xx_hal_adc.h
  • ADC_FLAG_EOC : stm32g0xx_hal_adc.h
  • ADC_FLAG_EOS : stm32g0xx_hal_adc.h
  • ADC_FLAG_EOSMP : stm32g0xx_hal_adc.h
  • ADC_FLAG_OVR : stm32g0xx_hal_adc.h
  • ADC_FLAG_POSTCONV_ALL : stm32g0xx_hal_adc.h
  • ADC_FLAG_RDY : stm32g0xx_hal_adc.h
  • ADC_GET_RESOLUTION : stm32g0xx_hal_adc.h
  • ADC_IS_INDEPENDENT : stm32g0xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32g0xx_hal_adc.h
  • ADC_IT_AWD1 : stm32g0xx_hal_adc.h
  • ADC_IT_AWD2 : stm32g0xx_hal_adc.h
  • ADC_IT_AWD3 : stm32g0xx_hal_adc.h
  • ADC_IT_CCRDY : stm32g0xx_hal_adc.h
  • ADC_IT_EOC : stm32g0xx_hal_adc.h
  • ADC_IT_EOS : stm32g0xx_hal_adc.h
  • ADC_IT_EOSMP : stm32g0xx_hal_adc.h
  • ADC_IT_OVR : stm32g0xx_hal_adc.h
  • ADC_IT_RDY : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_128 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_16 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_2 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_256 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_32 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_4 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_64 : stm32g0xx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_8 : stm32g0xx_hal_adc.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32g0xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32g0xx_hal_adc.h
  • ADC_OVR_EVENT : stm32g0xx_hal_adc.h
  • ADC_RANK_CHANNEL_NUMBER : stm32g0xx_hal_adc.h
  • ADC_RANK_NONE : stm32g0xx_hal_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32g0xx_ll_adc.h
  • ADC_REGULAR_GROUP : stm32g0xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32g0xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32g0xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32g0xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32g0xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32g0xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_2 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_3 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_4 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_5 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_6 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_7 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_8 : stm32g0xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_NONE : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_12CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_160CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_19CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_39CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_3CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_79CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLETIME_7CYCLES_5 : stm32g0xx_hal_adc.h
  • ADC_SAMPLING_TIME_CH_MASK : stm32g0xx_ll_adc.h
  • ADC_SAMPLING_TIME_SMP_MASK : stm32g0xx_ll_adc.h
  • ADC_SAMPLING_TIME_SMP_SHIFT_MASK : stm32g0xx_ll_adc.h
  • ADC_SAMPLINGTIME_COMMON_1 : stm32g0xx_hal_adc.h
  • ADC_SAMPLINGTIME_COMMON_2 : stm32g0xx_hal_adc.h
  • ADC_SCAN_DIRECTION_BACKWARD : stm32g0xx_hal_adc.h
  • ADC_SCAN_DIRECTION_FORWARD : stm32g0xx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32g0xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32g0xx_hal_adc.h
  • ADC_SCAN_SEQ_FIXED : stm32g0xx_hal_adc.h
  • ADC_SCAN_SEQ_FIXED_BACKWARD : stm32g0xx_hal_adc.h
  • ADC_SCAN_SEQ_FIXED_INT : stm32g0xx_hal_adc.h
  • ADC_SCAN_SEQ_MODE : stm32g0xx_hal_adc.h
  • ADC_SMPR_SMP1_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_SMPR_SMP2_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_SMPR_SMPSEL0_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32g0xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32g0xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32g0xx_hal_adc.c
  • ADC_TIMEOUT_CCRDY_CPU_CYCLES : stm32g0xx_ll_adc.c
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32g0xx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32g0xx_ll_adc.c
  • ADC_TR1_HT1_BITOFFSET_POS : stm32g0xx_ll_adc.h
  • ADC_TRIGGER_FREQ_HIGH : stm32g0xx_hal_adc.h
  • ADC_TRIGGER_FREQ_LOW : stm32g0xx_hal_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32g0xx_hal_adc.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32g0xx_hal_adc.h
  • assert_param : stm32g0xx_ll_spi.c , stm32g0xx_ll_rtc.c , stm32g0xx_ll_comp.c , stm32g0xx_ll_lpuart.c , stm32g0xx_ll_tim.c , stm32g0xx_ll_dac.c , stm32g0xx_ll_adc.c , stm32g0xx_ll_lptim.c , stm32g0xx_hal_conf.h , stm32g0xx_ll_usart.c , stm32g0xx_ll_utils.c , stm32g0xx_ll_ucpd.c , stm32g0xx_ll_rcc.c , stm32g0xx_ll_rng.c , stm32g0xx_ll_exti.c , stm32g0xx_ll_dma.c , stm32g0xx_ll_crc.c , stm32g0xx_ll_gpio.c , stm32g0xx_ll_i2c.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- b -

  • BDCR_REG_INDEX : stm32g0xx_hal_rcc.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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- c -

  • CEC_0_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_1_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_2_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_3_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_4_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_5_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_6_5_BITPERIOD_SFT : stm32g0xx_hal_cec.h
  • CEC_BRE_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • CEC_BRE_ERRORBIT_NO_GENERATION : stm32g0xx_hal_cec.h
  • CEC_BROADCASTERROR_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • CEC_CFGR_OAR_LSB_POS : stm32g0xx_hal_cec.h
  • CEC_DEFAULT_SFT : stm32g0xx_hal_cec.h
  • CEC_EXTENDED_TOLERANCE : stm32g0xx_hal_cec.h
  • CEC_FLAG_ARBLST : stm32g0xx_hal_cec.h
  • CEC_FLAG_BRE : stm32g0xx_hal_cec.h
  • CEC_FLAG_LBPE : stm32g0xx_hal_cec.h
  • CEC_FLAG_RXACKE : stm32g0xx_hal_cec.h
  • CEC_FLAG_RXBR : stm32g0xx_hal_cec.h
  • CEC_FLAG_RXEND : stm32g0xx_hal_cec.h
  • CEC_FLAG_RXOVR : stm32g0xx_hal_cec.h
  • CEC_FLAG_SBPE : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXACKE : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXBR : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXEND : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXERR : stm32g0xx_hal_cec.h
  • CEC_FLAG_TXUDR : stm32g0xx_hal_cec.h
  • CEC_FULL_LISTENING_MODE : stm32g0xx_hal_cec.h
  • CEC_IER_RX_ALL_ERR : stm32g0xx_hal_cec.h
  • CEC_IER_TX_ALL_ERR : stm32g0xx_hal_cec.h
  • CEC_INITIATOR_LSB_POS : stm32g0xx_hal_cec.h
  • CEC_ISR_ALL_ERROR : stm32g0xx_hal_cec.h
  • CEC_IT_ARBLST : stm32g0xx_hal_cec.h
  • CEC_IT_BRE : stm32g0xx_hal_cec.h
  • CEC_IT_LBPE : stm32g0xx_hal_cec.h
  • CEC_IT_RXACKE : stm32g0xx_hal_cec.h
  • CEC_IT_RXBR : stm32g0xx_hal_cec.h
  • CEC_IT_RXEND : stm32g0xx_hal_cec.h
  • CEC_IT_RXOVR : stm32g0xx_hal_cec.h
  • CEC_IT_SBPE : stm32g0xx_hal_cec.h
  • CEC_IT_TXACKE : stm32g0xx_hal_cec.h
  • CEC_IT_TXBR : stm32g0xx_hal_cec.h
  • CEC_IT_TXEND : stm32g0xx_hal_cec.h
  • CEC_IT_TXERR : stm32g0xx_hal_cec.h
  • CEC_IT_TXUDR : stm32g0xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • CEC_LBPE_ERRORBIT_NO_GENERATION : stm32g0xx_hal_cec.h
  • CEC_NO_RX_STOP_ON_BRE : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_0 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_1 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_10 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_11 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_12 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_13 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_14 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_2 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_3 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_4 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_5 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_6 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_7 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_8 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_9 : stm32g0xx_hal_cec.h
  • CEC_OWN_ADDRESS_NONE : stm32g0xx_hal_cec.h
  • CEC_REDUCED_LISTENING_MODE : stm32g0xx_hal_cec.h
  • CEC_RX_STOP_ON_BRE : stm32g0xx_hal_cec.h
  • CEC_SFT_START_ON_TX_RX_END : stm32g0xx_hal_cec.h
  • CEC_SFT_START_ON_TXSOM : stm32g0xx_hal_cec.h
  • CEC_STANDARD_TOLERANCE : stm32g0xx_hal_cec.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • COMP_BLANKINGSRC_NONE : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC2 : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC4 : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5 : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3 : stm32g0xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3 : stm32g0xx_hal_comp.h
  • COMP_CLEAR_ERRORCODE : stm32g0xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32g0xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32g0xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32g0xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32g0xx_hal_comp.h
  • COMP_EXTI_IT : stm32g0xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32g0xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32g0xx_hal_comp.h
  • COMP_EXTI_LINE_COMP3 : stm32g0xx_hal_comp.h
  • COMP_EXTI_RISING : stm32g0xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32g0xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32g0xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32g0xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32g0xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_IO3 : stm32g0xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32g0xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32g0xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32g0xx_hal_comp.h
  • COMP_INPUT_PLUS_IO3 : stm32g0xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32g0xx_hal_comp.c
  • COMP_OUTPUT_LEVEL_HIGH : stm32g0xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32g0xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32g0xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32g0xx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32g0xx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32g0xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32g0xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32g0xx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32g0xx_hal_comp.h
  • COMP_WINDOWMODE_COMP2 : stm32g0xx_hal_comp.h
  • COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON : stm32g0xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_BOTH : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_COMP1 : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_COMP2 : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_COMP3 : stm32g0xx_hal_comp.h
  • COMP_WINDOWOUTPUT_EACH_COMP : stm32g0xx_hal_comp.h
  • CR_REG_INDEX : stm32g0xx_hal_rcc.h
  • CRC_INPUTDATA_FORMAT_BYTES : stm32g0xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32g0xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32g0xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32g0xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32g0xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32g0xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32g0xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32g0xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32g0xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32g0xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32g0xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32g0xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32g0xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32g0xx_hal_crc.h
  • CRRCR_REG_INDEX : stm32g0xx_hal_rcc.h
  • CRYP_AES_CBC : stm32g0xx_hal_cryp.h
  • CRYP_AES_CCM : stm32g0xx_hal_cryp.h
  • CRYP_AES_CTR : stm32g0xx_hal_cryp.h
  • CRYP_AES_ECB : stm32g0xx_hal_cryp.h
  • CRYP_AES_GCM_GMAC : stm32g0xx_hal_cryp.h
  • CRYP_CCF_CLEAR : stm32g0xx_hal_cryp.h
  • CRYP_CCM_CTR0_0 : stm32g0xx_hal_cryp_ex.c
  • CRYP_CCM_CTR0_3 : stm32g0xx_hal_cryp_ex.c
  • CRYP_CCM_CTR1_0 : stm32g0xx_hal_cryp.c
  • CRYP_CCM_CTR1_1 : stm32g0xx_hal_cryp.c
  • CRYP_CCM_CTR1_2 : stm32g0xx_hal_cryp.c
  • CRYP_DATATYPE_16B : stm32g0xx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32g0xx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32g0xx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32g0xx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_BYTE : stm32g0xx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_WORD : stm32g0xx_hal_cryp.h
  • CRYP_ERR_CLEAR : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_BUSY : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_CCF : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_MASK : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_RDERR : stm32g0xx_hal_cryp.h
  • CRYP_FLAG_WRERR : stm32g0xx_hal_cryp.h
  • CRYP_HEADERWIDTHUNIT_BYTE : stm32g0xx_hal_cryp.h
  • CRYP_HEADERWIDTHUNIT_WORD : stm32g0xx_hal_cryp.h
  • CRYP_IT_CCF : stm32g0xx_hal_cryp.h
  • CRYP_IT_CCFIE : stm32g0xx_hal_cryp.h
  • CRYP_IT_ERRIE : stm32g0xx_hal_cryp.h
  • CRYP_IT_RDERR : stm32g0xx_hal_cryp.h
  • CRYP_IT_WRERR : stm32g0xx_hal_cryp.h
  • CRYP_KEYIVCONFIG_ALWAYS : stm32g0xx_hal_cryp.h
  • CRYP_KEYIVCONFIG_ONCE : stm32g0xx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32g0xx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32g0xx_hal_cryp.h
  • CRYP_OPERATINGMODE_DECRYPT : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_OPERATINGMODE_ENCRYPT : stm32g0xx_hal_cryp_ex.c , stm32g0xx_hal_cryp.c
  • CRYP_OPERATINGMODE_KEYDERIVATION : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT : stm32g0xx_hal_cryp_ex.c , stm32g0xx_hal_cryp.c
  • CRYP_PHASE_FINAL : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_PHASE_HEADER : stm32g0xx_hal_cryp_ex.c , stm32g0xx_hal_cryp.c
  • CRYP_PHASE_HEADER_DMA_FEED : stm32g0xx_hal_cryp.c
  • CRYP_PHASE_HEADER_SUSPENDED : stm32g0xx_hal_cryp.c
  • CRYP_PHASE_INIT : stm32g0xx_hal_cryp_ex.c , stm32g0xx_hal_cryp.c
  • CRYP_PHASE_PAYLOAD : stm32g0xx_hal_cryp.c , stm32g0xx_hal_cryp_ex.c
  • CRYP_PHASE_PAYLOAD_SUSPENDED : stm32g0xx_hal_cryp.c
  • CRYP_PHASE_PROCESS : stm32g0xx_hal_cryp.c
  • CRYP_PHASE_READY : stm32g0xx_hal_cryp.c
  • CRYP_SET_PHASE : stm32g0xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMHEADERPHASE : stm32g0xx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMINITPHASE : stm32g0xx_hal_cryp.c
  • CRYP_TIMEOUT_KEYPREPARATION : stm32g0xx_hal_cryp.c
  • CRYPEx_PHASE_FINAL : stm32g0xx_hal_cryp_ex.c
  • CRYPEx_PHASE_PROCESS : stm32g0xx_hal_cryp_ex.c
  • CSR_REG_INDEX : stm32g0xx_hal_rcc.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • s
  • t
  • u
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- d -

  • DAC_ALIGN_12B_L : stm32g0xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32g0xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32g0xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32g0xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32g0xx_hal_dac.h
  • DAC_CHIPCONNECT_DISABLE : stm32g0xx_hal_dac.h
  • DAC_CHIPCONNECT_ENABLE : stm32g0xx_hal_dac.h
  • DAC_CR_CH1_BITOFFSET : stm32g0xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32g0xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32g0xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32g0xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32g0xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32g0xx_ll_dac.h
  • DAC_FLAG_DMAUDR1 : stm32g0xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32g0xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32g0xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32g0xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32g0xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32g0xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32g0xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32g0xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 : stm32g0xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 : stm32g0xx_ll_dac.h
  • DAC_REG_SHSR1_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_SHSR2_REGOFFSET : stm32g0xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS : stm32g0xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK : stm32g0xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 : stm32g0xx_ll_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32g0xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32g0xx_hal_dac.h
  • DAC_SWTR_CH1 : stm32g0xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32g0xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32g0xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32g0xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_LPTIM1_OUT : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_LPTIM2_OUT : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T15_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T1_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T3_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32g0xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32g0xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32g0xx_hal_dac.h
  • DEFAULT_CRC32_POLY : stm32g0xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32g0xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32g0xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32g0xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32g0xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32g0xx_hal_crc.h
  • DMA_CIRCULAR : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI1 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI2 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI3 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI4 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI5 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI6 : stm32g0xx_hal_dma.h
  • DMA_FLAG_GI7 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32g0xx_hal_dma.h
  • DMA_FLAG_HT7 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TC7 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32g0xx_hal_dma.h
  • DMA_FLAG_TE7 : stm32g0xx_hal_dma.h
  • DMA_IT_HT : stm32g0xx_hal_dma.h
  • DMA_IT_TC : stm32g0xx_hal_dma.h
  • DMA_IT_TE : stm32g0xx_hal_dma.h
  • DMA_MAX_REQUEST : stm32g0xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32g0xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32g0xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32g0xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32g0xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32g0xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32g0xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32g0xx_hal_dma.h
  • DMA_NORMAL : stm32g0xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32g0xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32g0xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32g0xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32g0xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32g0xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32g0xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32g0xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32g0xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32g0xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32g0xx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_AES_IN : stm32g0xx_hal_dma.h
  • DMA_REQUEST_AES_OUT : stm32g0xx_hal_dma.h
  • DMA_REQUEST_DAC1_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_DAC1_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_LPUART1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_LPUART1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_LPUART2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_LPUART2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI3_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_SPI3_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM15_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM15_TRIG_COM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM15_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM16_COM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM17_COM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG_COM : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_TRIG : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_CH4 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_TRIG : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM3_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH1 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH2 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH3 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_CH4 : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_TRIG : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM4_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM6_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_TIM7_UP : stm32g0xx_hal_dma.h
  • DMA_REQUEST_UCPD1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_UCPD1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_UCPD2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_UCPD2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART2_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART2_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART3_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART3_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART4_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART4_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART5_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART5_TX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART6_RX : stm32g0xx_hal_dma.h
  • DMA_REQUEST_USART6_TX : stm32g0xx_hal_dma.h
  • DMAMUX_CCR_SIZE : stm32g0xx_ll_dmamux.h
  • DMAMUX_RGCR_SIZE : stm32g0xx_ll_dmamux.h
  • DT_DELAY_1 : stm32g0xx_ll_tim.h
  • DT_DELAY_2 : stm32g0xx_ll_tim.h
  • DT_DELAY_3 : stm32g0xx_ll_tim.h
  • DT_DELAY_4 : stm32g0xx_ll_tim.h
  • DT_RANGE_1 : stm32g0xx_ll_tim.h
  • DT_RANGE_2 : stm32g0xx_ll_tim.h
  • DT_RANGE_3 : stm32g0xx_ll_tim.h
  • DT_RANGE_4 : stm32g0xx_ll_tim.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
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  • s
  • t
  • u
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  • w

- e -

  • EXTERNAL_I2S1_CLOCK_VALUE : stm32g0xx_hal_conf.h
  • EXTERNAL_I2S2_CLOCK_VALUE : stm32g0xx_hal_conf.h
  • EXTI_CONFIG : stm32g0xx_hal_exti.h
  • EXTI_CONFIG_OFFSET : stm32g0xx_hal_exti.c
  • EXTI_DIRECT : stm32g0xx_hal_exti.h
  • EXTI_EVT : stm32g0xx_hal_gpio.h
  • EXTI_GPIO : stm32g0xx_hal_exti.h
  • EXTI_GPIOA : stm32g0xx_hal_exti.h
  • EXTI_GPIOB : stm32g0xx_hal_exti.h
  • EXTI_GPIOC : stm32g0xx_hal_exti.h
  • EXTI_GPIOD : stm32g0xx_hal_exti.h
  • EXTI_GPIOE : stm32g0xx_hal_exti.h
  • EXTI_GPIOF : stm32g0xx_hal_exti.h
  • EXTI_IT : stm32g0xx_hal_gpio.h
  • EXTI_LINE_0 : stm32g0xx_hal_exti.h
  • EXTI_LINE_1 : stm32g0xx_hal_exti.h
  • EXTI_LINE_10 : stm32g0xx_hal_exti.h
  • EXTI_LINE_11 : stm32g0xx_hal_exti.h
  • EXTI_LINE_12 : stm32g0xx_hal_exti.h
  • EXTI_LINE_13 : stm32g0xx_hal_exti.h
  • EXTI_LINE_14 : stm32g0xx_hal_exti.h
  • EXTI_LINE_15 : stm32g0xx_hal_exti.h
  • EXTI_LINE_16 : stm32g0xx_hal_exti.h
  • EXTI_LINE_17 : stm32g0xx_hal_exti.h
  • EXTI_LINE_18 : stm32g0xx_hal_exti.h
  • EXTI_LINE_19 : stm32g0xx_hal_exti.h
  • EXTI_LINE_2 : stm32g0xx_hal_exti.h
  • EXTI_LINE_20 : stm32g0xx_hal_exti.h
  • EXTI_LINE_21 : stm32g0xx_hal_exti.h
  • EXTI_LINE_22 : stm32g0xx_hal_exti.h
  • EXTI_LINE_23 : stm32g0xx_hal_exti.h
  • EXTI_LINE_24 : stm32g0xx_hal_exti.h
  • EXTI_LINE_25 : stm32g0xx_hal_exti.h
  • EXTI_LINE_26 : stm32g0xx_hal_exti.h
  • EXTI_LINE_27 : stm32g0xx_hal_exti.h
  • EXTI_LINE_28 : stm32g0xx_hal_exti.h
  • EXTI_LINE_29 : stm32g0xx_hal_exti.h
  • EXTI_LINE_3 : stm32g0xx_hal_exti.h
  • EXTI_LINE_30 : stm32g0xx_hal_exti.h
  • EXTI_LINE_31 : stm32g0xx_hal_exti.h
  • EXTI_LINE_32 : stm32g0xx_hal_exti.h
  • EXTI_LINE_33 : stm32g0xx_hal_exti.h
  • EXTI_LINE_34 : stm32g0xx_hal_exti.h
  • EXTI_LINE_35 : stm32g0xx_hal_exti.h
  • EXTI_LINE_36 : stm32g0xx_hal_exti.h
  • EXTI_LINE_4 : stm32g0xx_hal_exti.h
  • EXTI_LINE_5 : stm32g0xx_hal_exti.h
  • EXTI_LINE_6 : stm32g0xx_hal_exti.h
  • EXTI_LINE_7 : stm32g0xx_hal_exti.h
  • EXTI_LINE_8 : stm32g0xx_hal_exti.h
  • EXTI_LINE_9 : stm32g0xx_hal_exti.h
  • EXTI_LINE_NB : stm32g0xx_hal_exti.h
  • EXTI_MODE : stm32g0xx_hal_gpio.h
  • EXTI_MODE_EVENT : stm32g0xx_hal_exti.h
  • EXTI_MODE_INTERRUPT : stm32g0xx_hal_exti.h
  • EXTI_MODE_MASK : stm32g0xx_hal_exti.h
  • EXTI_MODE_NONE : stm32g0xx_hal_exti.h
  • EXTI_MODE_OFFSET : stm32g0xx_hal_exti.c
  • EXTI_MODE_Pos : stm32g0xx_hal_gpio.h
  • EXTI_PIN_MASK : stm32g0xx_hal_exti.h
  • EXTI_PROPERTY_MASK : stm32g0xx_hal_exti.h
  • EXTI_PROPERTY_SHIFT : stm32g0xx_hal_exti.h
  • EXTI_REG1 : stm32g0xx_hal_exti.h
  • EXTI_REG2 : stm32g0xx_hal_exti.h
  • EXTI_REG_MASK : stm32g0xx_hal_exti.h
  • EXTI_REG_SHIFT : stm32g0xx_hal_exti.h
  • EXTI_RESERVED : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_FALLING : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_MASK : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_NONE : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_RISING : stm32g0xx_hal_exti.h
  • EXTI_TRIGGER_RISING_FALLING : stm32g0xx_hal_exti.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- f -

  • FDCAN_ACCEPT_IN_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_ACCEPT_IN_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_BRS_OFF : stm32g0xx_hal_fdcan.h
  • FDCAN_BRS_ON : stm32g0xx_hal_fdcan.h
  • FDCAN_CHECK_FLAG : stm32g0xx_hal_fdcan.h
  • FDCAN_CHECK_IT_SOURCE : stm32g0xx_hal_fdcan.h
  • FDCAN_CLASSIC_CAN : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV1 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV10 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV12 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV14 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV16 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV18 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV2 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV20 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV22 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV24 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV26 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV28 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV30 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV4 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV6 : stm32g0xx_hal_fdcan.h
  • FDCAN_CLOCK_DIV8 : stm32g0xx_hal_fdcan.h
  • FDCAN_COM_STATE_IDLE : stm32g0xx_hal_fdcan.h
  • FDCAN_COM_STATE_RX : stm32g0xx_hal_fdcan.h
  • FDCAN_COM_STATE_SYNC : stm32g0xx_hal_fdcan.h
  • FDCAN_COM_STATE_TX : stm32g0xx_hal_fdcan.h
  • FDCAN_DATA_FRAME : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_0 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_1 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_12 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_16 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_2 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_20 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_24 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_3 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_32 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_4 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_48 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_5 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_6 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_64 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_7 : stm32g0xx_hal_fdcan.h
  • FDCAN_DLC_BYTES_8 : stm32g0xx_hal_fdcan.h
  • FDCAN_ELEMENT_MASK_ANMF : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_BRS : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_DLC : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EFC : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ESI : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_ET : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_EXTID : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FDF : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_FIDX : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_MM : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_RTR : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_STDID : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_TS : stm32g0xx_hal_fdcan.c
  • FDCAN_ELEMENT_MASK_XTD : stm32g0xx_hal_fdcan.c
  • FDCAN_ERROR_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_ERROR_STATUS_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_ESI_ACTIVE : stm32g0xx_hal_fdcan.h
  • FDCAN_ESI_PASSIVE : stm32g0xx_hal_fdcan.h
  • FDCAN_EXTENDED_ID : stm32g0xx_hal_fdcan.h
  • FDCAN_FD_CAN : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_DISABLE : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_DUAL : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_HP : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_MASK : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_RANGE_NO_EIDM : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_REJECT : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_REMOTE : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO0_HP : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_FILTER_TO_RXFIFO1_HP : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_ARB_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_BUS_OFF : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_DATA_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_LOGGING_OVERFLOW : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_PASSIVE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_ERROR_WARNING : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_ACCESS_FAILURE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RAM_WATCHDOG : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RESERVED_ADDRESS_ACCESS : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_RX_HIGH_PRIORITY_MSG : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TIMEOUT_OCCURRED : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TIMESTAMP_WRAPAROUND : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_ABORT_COMPLETE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_COMPLETE : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA : stm32g0xx_hal_fdcan.h
  • FDCAN_FLAG_TX_FIFO_EMPTY : stm32g0xx_hal_fdcan.h
  • FDCAN_FRAME_CLASSIC : stm32g0xx_hal_fdcan.h
  • FDCAN_FRAME_FD_BRS : stm32g0xx_hal_fdcan.h
  • FDCAN_FRAME_FD_NO_BRS : stm32g0xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_MSG_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_NO_FIFO : stm32g0xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_HP_STORAGE_RXFIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_ILS_MASK : stm32g0xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE0 : stm32g0xx_hal_fdcan.h
  • FDCAN_INTERRUPT_LINE1 : stm32g0xx_hal_fdcan.h
  • FDCAN_IR_MASK : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_ARB_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_BUS_OFF : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_DATA_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_ERROR_LOGGING_OVERFLOW : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_ERROR_PASSIVE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_ERROR_WARNING : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_BIT_LINE_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_MISC : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_SMSG : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_GROUP_TX_FIFO_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_BIT_LINE_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_MISC : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_PROTOCOL_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_SMSG : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_LIST_TX_FIFO_ERROR : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RAM_ACCESS_FAILURE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RAM_WATCHDOG : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RESERVED_ADDRESS_ACCESS : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_MESSAGE_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO0_NEW_MESSAGE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_MESSAGE_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_FIFO1_NEW_MESSAGE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_RX_HIGH_PRIORITY_MSG : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TIMEOUT_OCCURRED : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TIMESTAMP_WRAPAROUND : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_ABORT_COMPLETE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_COMPLETE : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_ELT_LOST : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_FULL : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_EVT_FIFO_NEW_DATA : stm32g0xx_hal_fdcan.h
  • FDCAN_IT_TX_FIFO_EMPTY : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_BUS_MONITORING : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_EXTERNAL_LOOPBACK : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_INTERNAL_LOOPBACK : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_NORMAL : stm32g0xx_hal_fdcan.h
  • FDCAN_MODE_RESTRICTED_OPERATION : stm32g0xx_hal_fdcan.h
  • FDCAN_NO_TX_EVENTS : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_ACK : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT0 : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_BIT1 : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_CRC : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_FORM : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NO_CHANGE : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_NONE : stm32g0xx_hal_fdcan.h
  • FDCAN_PROTOCOL_ERROR_STUFF : stm32g0xx_hal_fdcan.h
  • FDCAN_REJECT : stm32g0xx_hal_fdcan.h
  • FDCAN_REJECT_REMOTE : stm32g0xx_hal_fdcan.h
  • FDCAN_REMOTE_FRAME : stm32g0xx_hal_fdcan.h
  • FDCAN_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_RX_FIFO0_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_RX_FIFO1_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_RX_FIFO_BLOCKING : stm32g0xx_hal_fdcan.h
  • FDCAN_RX_FIFO_OVERWRITE : stm32g0xx_hal_fdcan.h
  • FDCAN_STANDARD_ID : stm32g0xx_hal_fdcan.h
  • FDCAN_STORE_TX_EVENTS : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_CONTINUOUS : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO0 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_RX_FIFO1 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_TX_EVENT_FIFO : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMEOUT_VALUE : stm32g0xx_hal_fdcan.c
  • FDCAN_TIMESTAMP_EXTERNAL : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_INTERNAL : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_1 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_10 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_11 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_12 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_13 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_14 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_15 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_16 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_2 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_3 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_4 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_5 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_6 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_7 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_8 : stm32g0xx_hal_fdcan.h
  • FDCAN_TIMESTAMP_PRESC_9 : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_BUFFER0 : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_BUFFER1 : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_BUFFER2 : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_EVENT : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_EVENT_FIFO_MASK : stm32g0xx_hal_fdcan.c
  • FDCAN_TX_FIFO_OPERATION : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_IN_SPITE_OF_ABORT : stm32g0xx_hal_fdcan.h
  • FDCAN_TX_QUEUE_OPERATION : stm32g0xx_hal_fdcan.h
  • FLASH_BANK_1 : stm32g0xx_hal_flash.h
  • FLASH_BANK_2 : stm32g0xx_hal_flash.h
  • FLASH_BANK_NB : stm32g0xx_hal_flash.h
  • FLASH_BANK_SIZE : stm32g0xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32g0xx_hal_flash.h
  • FLASH_FLAG_BSY1 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_BSY2 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_CFGBSY : stm32g0xx_hal_flash.h
  • FLASH_FLAG_CR_ID : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCC : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCC1 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCC2 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCD : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCD1 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCD2 : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCR1_ID : stm32g0xx_hal_flash.h
  • FLASH_FLAG_ECCR2_ID : stm32g0xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32g0xx_hal_flash.h
  • FLASH_FLAG_FASTERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_MISERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_OPTVERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_PESD : stm32g0xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_PROGERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_REG_POS : stm32g0xx_hal_flash.h
  • FLASH_FLAG_SIZERR : stm32g0xx_hal_flash.h
  • FLASH_FLAG_SR_ID : stm32g0xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32g0xx_hal_flash.h
  • FLASH_IT_ECCC : stm32g0xx_hal_flash.h
  • FLASH_IT_ECCC1 : stm32g0xx_hal_flash.h
  • FLASH_IT_ECCC2 : stm32g0xx_hal_flash.h
  • FLASH_IT_EOP : stm32g0xx_hal_flash.h
  • FLASH_IT_OPERR : stm32g0xx_hal_flash.h
  • FLASH_IT_RDERR : stm32g0xx_hal_flash.h
  • FLASH_KEY1 : stm32g0xx_hal_flash.h
  • FLASH_KEY2 : stm32g0xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32g0xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32g0xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32g0xx_hal_flash.h
  • FLASH_OPTKEY1 : stm32g0xx_hal_flash.h
  • FLASH_OPTKEY2 : stm32g0xx_hal_flash.h
  • FLASH_PAGE_NB : stm32g0xx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32g0xx_hal_flash.h
  • FLASH_PCROP_GRANULARITY : stm32g0xx_hal_flash_ex.h
  • FLASH_PCROP_GRANULARITY_OFFSET : stm32g0xx_hal_flash_ex.h
  • FLASH_PROG_EMPTY : stm32g0xx_hal_flash_ex.h
  • FLASH_PROG_NOT_EMPTY : stm32g0xx_hal_flash_ex.h
  • FLASH_SALES_TYPE : stm32g0xx_hal_flash.h
  • FLASH_SALES_TYPE_0 : stm32g0xx_hal_flash.h
  • FLASH_SALES_TYPE_1 : stm32g0xx_hal_flash.h
  • FLASH_SALES_TYPE_Pos : stm32g0xx_hal_flash.h
  • FLASH_SALES_VALUE : stm32g0xx_hal_flash.h
  • FLASH_SIZE_DATA_REGISTER : stm32g0xx_hal_flash.h
  • FLASH_SR_CLEAR : stm32g0xx_hal_flash.h
  • FLASH_SR_ERRORS : stm32g0xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32g0xx_hal_flash.h
  • FLASH_TYPEERASE_MASS : stm32g0xx_hal_flash.h
  • FLASH_TYPEERASE_PAGES : stm32g0xx_hal_flash.h
  • FLASH_TYPENONE : stm32g0xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32g0xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST : stm32g0xx_hal_flash.h
  • FLASHSIZE_BASE_ADDRESS : stm32g0xx_ll_utils.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
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- g -

  • GPIO_AF0_CEC : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_CRS : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_EVENTOUT : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_IR : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_LPTIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_OSC : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_OSC32 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_SPI1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_SPI2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_TIM14 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_TIM15 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_TIM16 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_TIM17 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_UCPD1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_UCPD2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_USART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_USART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_USART3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF0_USART4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF10_LPUART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_CEC : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_EVENTOUT : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_IR : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_LPUART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_LPUART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_OSC : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_SPI1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_SPI2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_TIM3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_UCPD1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_UCPD2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_USART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_USART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF1_USART4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_LPTIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_LPTIM2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM14 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM15 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM16 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM17 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF2_USB : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_FDCAN1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_FDCAN2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_LPUART2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_MCO2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_USART5 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF3_USART6 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_CRS : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_SPI2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_SPI3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_TIM14 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_TIM15 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_UCPD1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_UCPD2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_USART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_USART3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_USART4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF4_USART6 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_LPTIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_LPTIM2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_TIM1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_TIM15 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_TIM16 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_TIM17 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF5_USART3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_I2C1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_I2C2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_I2C3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_LPUART1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_UCPD1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_UCPD2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF6_USB : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF7_COMP1 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF7_COMP2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF7_COMP3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF7_EVENTOUT : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF8_I2C2 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF8_USART5 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF8_USART6 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF9_I2C3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF9_SPI3 : stm32g0xx_hal_gpio_ex.h
  • GPIO_AF9_TIM4 : stm32g0xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32g0xx_hal_gpio_ex.h
  • GPIO_MODE : stm32g0xx_hal_gpio.h
  • GPIO_MODE_AF_OD : stm32g0xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32g0xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32g0xx_hal_gpio.h
  • GPIO_MODE_EVT_FALLING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32g0xx_hal_gpio.h
  • GPIO_MODE_IT_FALLING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32g0xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32g0xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32g0xx_hal_gpio.h
  • GPIO_MODE_Pos : stm32g0xx_hal_gpio.h
  • GPIO_NOPULL : stm32g0xx_hal_gpio.h
  • GPIO_NUMBER : stm32g0xx_hal_gpio.c
  • GPIO_PIN_0 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_1 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_10 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_11 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_12 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_13 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_14 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_15 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_2 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_3 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_4 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_5 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_6 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_7 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_8 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_9 : stm32g0xx_hal_gpio.h
  • GPIO_PIN_All : stm32g0xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32g0xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32g0xx_hal_gpio.h
  • GPIO_PULLUP : stm32g0xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32g0xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32g0xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32g0xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32g0xx_hal_gpio.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- h -

  • HAC_SET_CH_TX_SETUP : stm32g0xx_hal_hcd.h
  • HAL_ADC_ERROR_DMA : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_INVALID_CALLBACK : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32g0xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32g0xx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32g0xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32g0xx_hal_adc.h
  • HAL_CEC_ERROR_ARBLST : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_BRE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_INVALID_CALLBACK : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_LBPE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_NONE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_RXACKE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_RXOVR : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_SBPE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_TXACKE : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_TXERR : stm32g0xx_hal_cec.h
  • HAL_CEC_ERROR_TXUDR : stm32g0xx_hal_cec.h
  • HAL_CEC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_CEC_STATE_BUSY : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_RX_TX : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_BUSY_TX : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_ERROR : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_READY : stm32g0xx_hal_cec.h
  • HAL_CEC_STATE_RESET : stm32g0xx_hal_cec.h
  • HAL_COMP_ERROR_INVALID_CALLBACK : stm32g0xx_hal_comp.h
  • HAL_COMP_ERROR_NONE : stm32g0xx_hal_comp.h
  • HAL_COMP_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_CRC_LENGTH_16B : stm32g0xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32g0xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32g0xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32g0xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_BUSY : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_DMA : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_INVALID_CALLBACK : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_NOT_SUPPORTED : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_READ : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_TIMEOUT : stm32g0xx_hal_cryp.h
  • HAL_CRYP_ERROR_WRITE : stm32g0xx_hal_cryp.h
  • HAL_CRYP_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_DAC_ERROR_DMA : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_INVALID_CALLBACK : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32g0xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32g0xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_DMA_ERROR_BUSY : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_NO_XFER : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_PARAM : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32g0xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32g0xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_DMAMUX1_MAX_REQ_GEN : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_MAX_SYNC : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI0 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI1 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI10 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI11 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI12 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI13 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI14 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI15 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI2 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI3 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI4 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI5 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI6 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI7 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI8 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI9 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_TIM14_OC : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI1 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI10 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI11 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI12 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI13 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI14 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI15 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI2 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI3 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI4 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI5 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI6 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI7 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI8 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI9 : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM2_OUT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_TIM14_OC : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_FALLING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_NO_EVENT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING_FALLING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32g0xx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32g0xx_hal_dma_ex.h
  • HAL_EXTI_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_FDCAN_ERROR_FIFO_EMPTY : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_FIFO_FULL : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_INVALID_CALLBACK : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_LOG_OVERFLOW : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NONE : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_INITIALIZED : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_READY : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_STARTED : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_NOT_SUPPORTED : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PARAM : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PENDING : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_ARBT : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_PROTOCOL_DATA : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_ACCESS : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RAM_WDG : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_RESERVED_AREA : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_ERROR_TIMEOUT : stm32g0xx_hal_fdcan.h
  • HAL_FDCAN_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_FLASH_ERROR_ECCD : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_FAST : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_MIS : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_OP : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_SIZ : stm32g0xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32g0xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_HCD_ERROR_INVALID_CALLBACK : stm32g0xx_hal_hcd.h
  • HAL_HCD_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA_PARAM : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_CALLBACK : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_PARAM : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32g0xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32g0xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_I2S_ERROR_BUSY_LINE_RX : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_DMA : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_INVALID_CALLBACK : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_PRESCALER : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_TIMEOUT : stm32g0xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32g0xx_hal_i2s.h
  • HAL_I2S_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_IRDA_ERROR_BUSY : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_INVALID_CALLBACK : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32g0xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32g0xx_hal_irda.h
  • HAL_IRDA_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_IRDA_STATE_BUSY : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32g0xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32g0xx_hal_irda.h
  • HAL_ITLINE_ADC : stm32g0xx_hal.h
  • HAL_ITLINE_AES : stm32g0xx_hal.h
  • HAL_ITLINE_CEC : stm32g0xx_hal.h
  • HAL_ITLINE_CLK_CTRL : stm32g0xx_hal.h
  • HAL_ITLINE_COMP1 : stm32g0xx_hal.h
  • HAL_ITLINE_COMP2 : stm32g0xx_hal.h
  • HAL_ITLINE_COMP3 : stm32g0xx_hal.h
  • HAL_ITLINE_CRS : stm32g0xx_hal.h
  • HAL_ITLINE_DAC : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH1 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH2 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH3 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH4 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH5 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH6 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA1_CH7 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH1 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH2 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH3 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH4 : stm32g0xx_hal.h
  • HAL_ITLINE_DMA2_CH5 : stm32g0xx_hal.h
  • HAL_ITLINE_DMAMUX1 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI0 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI1 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI10 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI11 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI12 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI13 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI14 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI15 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI2 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI3 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI4 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI5 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI6 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI7 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI8 : stm32g0xx_hal.h
  • HAL_ITLINE_EXTI9 : stm32g0xx_hal.h
  • HAL_ITLINE_FDCAN1_IT0 : stm32g0xx_hal.h
  • HAL_ITLINE_FDCAN1_IT1 : stm32g0xx_hal.h
  • HAL_ITLINE_FDCAN2_IT0 : stm32g0xx_hal.h
  • HAL_ITLINE_FDCAN2_IT1 : stm32g0xx_hal.h
  • HAL_ITLINE_FLASH_ECC : stm32g0xx_hal.h
  • HAL_ITLINE_FLASH_ITF : stm32g0xx_hal.h
  • HAL_ITLINE_I2C1 : stm32g0xx_hal.h
  • HAL_ITLINE_I2C2 : stm32g0xx_hal.h
  • HAL_ITLINE_I2C3 : stm32g0xx_hal.h
  • HAL_ITLINE_LPTIM1 : stm32g0xx_hal.h
  • HAL_ITLINE_LPTIM2 : stm32g0xx_hal.h
  • HAL_ITLINE_LPUART1 : stm32g0xx_hal.h
  • HAL_ITLINE_LPUART2 : stm32g0xx_hal.h
  • HAL_ITLINE_PVDOUT : stm32g0xx_hal.h
  • HAL_ITLINE_PVMOUT : stm32g0xx_hal.h
  • HAL_ITLINE_RNG : stm32g0xx_hal.h
  • HAL_ITLINE_RTC : stm32g0xx_hal.h
  • HAL_ITLINE_SPI1 : stm32g0xx_hal.h
  • HAL_ITLINE_SPI2 : stm32g0xx_hal.h
  • HAL_ITLINE_SPI3 : stm32g0xx_hal.h
  • HAL_ITLINE_TAMPER : stm32g0xx_hal.h
  • HAL_ITLINE_TIM14 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM15 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM16 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM17 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_BRK : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_CC : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_CCU : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_TRG : stm32g0xx_hal.h
  • HAL_ITLINE_TIM1_UPD : stm32g0xx_hal.h
  • HAL_ITLINE_TIM2 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM3 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM4 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM6 : stm32g0xx_hal.h
  • HAL_ITLINE_TIM7 : stm32g0xx_hal.h
  • HAL_ITLINE_UCPD1 : stm32g0xx_hal.h
  • HAL_ITLINE_UCPD2 : stm32g0xx_hal.h
  • HAL_ITLINE_USART1 : stm32g0xx_hal.h
  • HAL_ITLINE_USART2 : stm32g0xx_hal.h
  • HAL_ITLINE_USART3 : stm32g0xx_hal.h
  • HAL_ITLINE_USART4 : stm32g0xx_hal.h
  • HAL_ITLINE_USART5 : stm32g0xx_hal.h
  • HAL_ITLINE_USART6 : stm32g0xx_hal.h
  • HAL_ITLINE_USB : stm32g0xx_hal.h
  • HAL_ITLINE_WWDG : stm32g0xx_hal.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32g0xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_LPTIM_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_PCD_ERROR_INVALID_CALLBACK : stm32g0xx_hal_pcd.h
  • HAL_PCD_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_RNG_ERROR_BUSY : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_CLOCK : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_INVALID_CALLBACK : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_NONE : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_SEED : stm32g0xx_hal_rng.h
  • HAL_RNG_ERROR_TIMEOUT : stm32g0xx_hal_rng.h
  • HAL_RNG_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_SMARTCARD_ERROR_DMA : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_INVALID_CALLBACK : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_SMARTCARD_STATE_BUSY : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32g0xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32g0xx_hal_smartcard.h
  • HAL_SMBUS_ERROR_ACKF : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_CALLBACK : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_PARAM : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_SMBUS_STATE_BUSY : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32g0xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32g0xx_hal_smbus.h
  • HAL_SPI_ERROR_ABORT : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_INVALID_CALLBACK : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32g0xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32g0xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_SYSCFG_IRDA_ENV_SEL_TIM16 : stm32g0xx_hal.h
  • HAL_SYSCFG_IRDA_ENV_SEL_USART1 : stm32g0xx_hal.h
  • HAL_SYSCFG_IRDA_ENV_SEL_USART4 : stm32g0xx_hal.h
  • HAL_SYSCFG_IRDA_POLARITY_INVERTED : stm32g0xx_hal.h
  • HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE0 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE1 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE10 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE11 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE12 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE13 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE14 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE15 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE16 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE17 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE18 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE19 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE2 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE20 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE21 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE22 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE23 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE24 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE25 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE26 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE27 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE28 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE29 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE3 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE30 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE31 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE4 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE5 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE6 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE7 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE8 : stm32g0xx_hal.h
  • HAL_SYSCFG_ITLINE9 : stm32g0xx_hal.h
  • HAL_TIM_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_TIMEOUT_ADDR : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32g0xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32g0xx_hal_smbus.c
  • HAL_UART_ERROR_DMA : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_INVALID_CALLBACK : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32g0xx_hal_uart.h
  • HAL_UART_ERROR_RTO : stm32g0xx_hal_uart.h
  • HAL_UART_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_UART_RECEPTION_STANDARD : stm32g0xx_hal_uart.h
  • HAL_UART_RECEPTION_TOCHARMATCH : stm32g0xx_hal_uart.h
  • HAL_UART_RECEPTION_TOIDLE : stm32g0xx_hal_uart.h
  • HAL_UART_RECEPTION_TORTO : stm32g0xx_hal_uart.h
  • HAL_UART_RXEVENT_HT : stm32g0xx_hal_uart.h
  • HAL_UART_RXEVENT_IDLE : stm32g0xx_hal_uart.h
  • HAL_UART_RXEVENT_TC : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_BUSY : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32g0xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32g0xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32g0xx_hal_uart.h
  • HAL_USART_ERROR_DMA : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_INVALID_CALLBACK : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_RTO : stm32g0xx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32g0xx_hal_usart.h
  • HAL_USART_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32g0xx_hal_conf.h
  • HCD_CLEAR_BULK_CH_DBUF : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_CH_KIND : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_RX_CH_CTR : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_RX_CH_ERR : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_RX_DTOG : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_TX_CH_CTR : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_TX_CH_ERR : stm32g0xx_hal_hcd.h
  • HCD_CLEAR_TX_DTOG : stm32g0xx_hal_hcd.h
  • HCD_DBL_BUF : stm32g0xx_hal_hcd.h
  • HCD_DEVICE_SPEED_FULL : stm32g0xx_hal_hcd.h
  • HCD_DEVICE_SPEED_HIGH : stm32g0xx_hal_hcd.h
  • HCD_DEVICE_SPEED_LOW : stm32g0xx_hal_hcd.h
  • HCD_FREE_CH_NOT_FOUND : stm32g0xx_hal_hcd.h
  • HCD_FREE_USER_BUFFER : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_RX_STATUS : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_TX_CNT : stm32g0xx_hal_hcd.h
  • HCD_GET_CH_TX_STATUS : stm32g0xx_hal_hcd.h
  • HCD_GET_CHANNEL : stm32g0xx_hal_hcd.h
  • HCD_LOGICAL_CH_NOT_OPENED : stm32g0xx_hal_hcd.h
  • HCD_PHY_EMBEDDED : stm32g0xx_hal_hcd.h
  • HCD_PHY_ULPI : stm32g0xx_hal_hcd.h
  • HCD_RX_DTOG : stm32g0xx_hal_hcd.h
  • HCD_SET_BULK_CH_DBUF : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_DBUF0_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_DBUF1_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_DBUF_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_KIND : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_RX_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_RX_STATUS : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_TX_CNT : stm32g0xx_hal_hcd.h
  • HCD_SET_CH_TX_STATUS : stm32g0xx_hal_hcd.h
  • HCD_SET_CHANNEL : stm32g0xx_hal_hcd.h
  • HCD_SNG_BUF : stm32g0xx_hal_hcd.h
  • HCD_SPEED_FULL : stm32g0xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32g0xx_hal_hcd.h
  • HCD_TX_DTOG : stm32g0xx_hal_hcd.h
  • HSE_STARTUP_TIMEOUT : stm32g0xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • HSE_VALUE : stm32g0xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • HSI48_VALUE : stm32g0xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • HSI_VALUE : stm32g0xx_hal_conf.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32g0xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32g0xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32g0xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32g0xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32g0xx_hal_i2c.h
  • I2C_CHECK_FLAG : stm32g0xx_hal_i2c.h
  • I2C_CHECK_IT_SOURCE : stm32g0xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32g0xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32g0xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32g0xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32g0xx_hal_i2c.h
  • I2C_FASTMODEPLUS_I2C1 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PA10 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PA9 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32g0xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32g0xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32g0xx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32g0xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32g0xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_AF : stm32g0xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32g0xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32g0xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32g0xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32g0xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32g0xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TC : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32g0xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32g0xx_hal_i2c.h
  • I2C_FMP_NOT_SUPPORTED : stm32g0xx_hal_i2c_ex.h
  • I2C_GENERALCALL_DISABLE : stm32g0xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32g0xx_hal_i2c.h
  • I2C_GENERATE_START : stm32g0xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32g0xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32g0xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32g0xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32g0xx_hal_i2c.h
  • I2C_GET_DIR : stm32g0xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32g0xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32g0xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32g0xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32g0xx_hal_i2c.h
  • I2C_IT_ADDRI : stm32g0xx_hal_i2c.h
  • I2C_IT_ERRI : stm32g0xx_hal_i2c.h
  • I2C_IT_NACKI : stm32g0xx_hal_i2c.h
  • I2C_IT_RXI : stm32g0xx_hal_i2c.h
  • I2C_IT_STOPI : stm32g0xx_hal_i2c.h
  • I2C_IT_TCI : stm32g0xx_hal_i2c.h
  • I2C_IT_TXI : stm32g0xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32g0xx_hal_i2c.h
  • I2C_LAST_FRAME_NO_STOP : stm32g0xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32g0xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32g0xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32g0xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32g0xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32g0xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32g0xx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32g0xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32g0xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32g0xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32g0xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32g0xx_hal_i2c.h
  • I2C_OTHER_AND_LAST_FRAME : stm32g0xx_hal_i2c.h
  • I2C_OTHER_FRAME : stm32g0xx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32g0xx_hal_i2c.h
  • I2C_RESET_CR2 : stm32g0xx_hal_i2c.h
  • I2C_SOFTEND_MODE : stm32g0xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32g0xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32g0xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32g0xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32g0xx_hal_i2c.c
  • I2C_STATE_MSK : stm32g0xx_hal_i2c.c
  • I2C_STATE_NONE : stm32g0xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32g0xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32g0xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32g0xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32g0xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32g0xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32g0xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32g0xx_hal_i2s.h
  • I2S_CHECK_FLAG : stm32g0xx_hal_i2s.h
  • I2S_CHECK_IT_SOURCE : stm32g0xx_hal_i2s.h
  • I2S_CPOL_HIGH : stm32g0xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32g0xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32g0xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32g0xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32g0xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32g0xx_hal_i2s.h
  • I2S_FLAG_BSY : stm32g0xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32g0xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32g0xx_hal_i2s.h
  • I2S_FLAG_MASK : stm32g0xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32g0xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32g0xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32g0xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32g0xx_hal_i2s.h
  • I2S_I2SCFGR_CLEAR_MASK : stm32g0xx_ll_spi.c
  • I2S_I2SPR_CLEAR_MASK : stm32g0xx_ll_spi.c
  • I2S_IT_ERR : stm32g0xx_hal_i2s.h
  • I2S_IT_RXNE : stm32g0xx_hal_i2s.h
  • I2S_IT_TXE : stm32g0xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32g0xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32g0xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32g0xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32g0xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32g0xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32g0xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32g0xx_hal_i2s.h
  • I2S_TIMEOUT_FLAG : stm32g0xx_hal_i2s.c
  • INSTRUCTION_CACHE_ENABLE : stm32g0xx_hal_conf.h
  • IRDA_AUTOBAUD_REQUEST : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_FEF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32g0xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32g0xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32g0xx_hal_irda.c
  • IRDA_CR_MASK : stm32g0xx_hal_irda.h
  • IRDA_CR_POS : stm32g0xx_hal_irda.h
  • IRDA_DIV_SAMPLING16 : stm32g0xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_ABRE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32g0xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32g0xx_hal_irda.h
  • IRDA_FLAG_FE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_NE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_PE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32g0xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32g0xx_hal_irda.h
  • IRDA_FLAG_TC : stm32g0xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32g0xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32g0xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32g0xx_hal_irda_ex.h
  • IRDA_ISR_MASK : stm32g0xx_hal_irda.h
  • IRDA_ISR_POS : stm32g0xx_hal_irda.h
  • IRDA_IT_ERR : stm32g0xx_hal_irda.h
  • IRDA_IT_FE : stm32g0xx_hal_irda.h
  • IRDA_IT_IDLE : stm32g0xx_hal_irda.h
  • IRDA_IT_MASK : stm32g0xx_hal_irda.h
  • IRDA_IT_NE : stm32g0xx_hal_irda.h
  • IRDA_IT_ORE : stm32g0xx_hal_irda.h
  • IRDA_IT_PE : stm32g0xx_hal_irda.h
  • IRDA_IT_RXNE : stm32g0xx_hal_irda.h
  • IRDA_IT_TC : stm32g0xx_hal_irda.h
  • IRDA_IT_TXE : stm32g0xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32g0xx_hal_irda_ex.h
  • IRDA_MODE_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_MODE_RX : stm32g0xx_hal_irda.h
  • IRDA_MODE_TX : stm32g0xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32g0xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32g0xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32g0xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32g0xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32g0xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV1 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV10 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV12 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV128 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV16 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV2 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV256 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV32 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV4 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV6 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV64 : stm32g0xx_hal_irda.h
  • IRDA_PRESCALER_DIV8 : stm32g0xx_hal_irda.h
  • IRDA_RXDATA_FLUSH_REQUEST : stm32g0xx_hal_irda.h
  • IRDA_STATE_DISABLE : stm32g0xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32g0xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32g0xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32g0xx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32g0xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_8B : stm32g0xx_hal_irda_ex.h
  • IRDA_WORDLENGTH_9B : stm32g0xx_hal_irda_ex.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32g0xx_hal_adc.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32g0xx_hal_adc.h
  • IS_ADC_CALFACT : stm32g0xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32g0xx_hal_adc.h
  • IS_ADC_CLOCKPRESCALER : stm32g0xx_hal_adc.h
  • IS_ADC_DATA_ALIGN : stm32g0xx_hal_adc.h
  • IS_ADC_EOC_SELECTION : stm32g0xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32g0xx_hal_adc.h
  • IS_ADC_EXTTRIG : stm32g0xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32g0xx_hal_adc.h
  • IS_ADC_OVERRUN : stm32g0xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32g0xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32g0xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32g0xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32g0xx_hal_adc.h
  • IS_ADC_REGULAR_RANK_SEQ_FIXED : stm32g0xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32g0xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32g0xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32g0xx_hal_adc.h
  • IS_ADC_SAMPLING_TIME_COMMON : stm32g0xx_hal_adc.h
  • IS_ADC_SCAN_MODE : stm32g0xx_hal_adc.h
  • IS_ADC_TRIGGER_FREQ : stm32g0xx_hal_adc.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32g0xx_hal_adc_ex.h
  • IS_CEC_ADDRESS : stm32g0xx_hal_cec.h
  • IS_CEC_BREERRORBITGEN : stm32g0xx_hal_cec.h
  • IS_CEC_BRERXSTOP : stm32g0xx_hal_cec.h
  • IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION : stm32g0xx_hal_cec.h
  • IS_CEC_LBPEERRORBITGEN : stm32g0xx_hal_cec.h
  • IS_CEC_LISTENING_MODE : stm32g0xx_hal_cec.h
  • IS_CEC_MSGSIZE : stm32g0xx_hal_cec.h
  • IS_CEC_OWN_ADDRESS : stm32g0xx_hal_cec.h
  • IS_CEC_SFTOP : stm32g0xx_hal_cec.h
  • IS_CEC_SIGNALFREETIME : stm32g0xx_hal_cec.h
  • IS_CEC_TOLERANCE : stm32g0xx_hal_cec.h
  • IS_COMP_BLANKINGSRC_INSTANCE : stm32g0xx_hal_comp.h
  • IS_COMP_BLANKINGSRCE : stm32g0xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32g0xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32g0xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32g0xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32g0xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32g0xx_hal_comp.h
  • IS_COMP_POWERMODE : stm32g0xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32g0xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32g0xx_hal_comp.h
  • IS_COMP_WINDOWOUTPUT : stm32g0xx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32g0xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32g0xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32g0xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32g0xx_hal_crc.h
  • IS_CRYP_ALGORITHM : stm32g0xx_hal_cryp.h
  • IS_CRYP_BUFFERSIZE : stm32g0xx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32g0xx_hal_cryp.h
  • IS_CRYP_INIT : stm32g0xx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32g0xx_hal_cryp.h
  • IS_DAC_ALIGN : stm32g0xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32g0xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32g0xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32g0xx_hal_dac.h
  • IS_DAC_HOLDTIME : stm32g0xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32g0xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32g0xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32g0xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32g0xx_hal_dac.h
  • IS_DAC_SAMPLEANDHOLD : stm32g0xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32g0xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32g0xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32g0xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32g0xx_hal_dac_ex.h
  • IS_DEFAULT_INIT_VALUE : stm32g0xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32g0xx_hal_crc.h
  • IS_DMA_ALL_REQUEST : stm32g0xx_hal_dma.h
  • IS_DMA_BUFFER_SIZE : stm32g0xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32g0xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32g0xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32g0xx_hal_dma.h
  • IS_DMA_MODE : stm32g0xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32g0xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32g0xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32g0xx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_SIGNAL_ID : stm32g0xx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32g0xx_hal_dma_ex.h
  • IS_EXTI_CONFIG_LINE : stm32g0xx_hal_exti.h
  • IS_EXTI_GPIO_PIN : stm32g0xx_hal_exti.h
  • IS_EXTI_GPIO_PORT : stm32g0xx_hal_exti.h
  • IS_EXTI_LINE : stm32g0xx_hal_exti.h
  • IS_EXTI_MODE : stm32g0xx_hal_exti.h
  • IS_EXTI_PENDING_EDGE : stm32g0xx_hal_exti.h
  • IS_EXTI_TRIGGER : stm32g0xx_hal_exti.h
  • IS_FDCAN_BRS : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_CKDIV : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DATA_PRESCALER : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DATA_SJW : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG1 : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DATA_TSEG2 : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_DLC : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_EFC : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_ESI : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_EXT_FILTER_TYPE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_FDF : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_FILTER_CFG : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_FRAME_FORMAT : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_FRAME_TYPE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_ID_TYPE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_IT : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_IT_GROUP : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_IT_LINE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_MAX_VALUE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_MIN_VALUE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_MODE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_PRESCALER : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_SJW : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG1 : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NOMINAL_TSEG2 : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_NON_MATCHING : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_REJECT_REMOTE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_RX_FIFO_MODE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_STD_FILTER_TYPE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TIMEOUT : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TIMESTAMP_PRESCALER : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TX_FIFO_QUEUE_MODE : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION : stm32g0xx_hal_fdcan.h
  • IS_FDCAN_TX_LOCATION_LIST : stm32g0xx_hal_fdcan.h
  • IS_FLASH_BANK : stm32g0xx_hal_flash.h
  • IS_FLASH_EMPTY_CHECK : stm32g0xx_hal_flash_ex.h
  • IS_FLASH_FAST_PROGRAM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32g0xx_hal_flash.h
  • IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_MAIN_MEM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_PAGE : stm32g0xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_PROGRAM_OTP_ADDRESS : stm32g0xx_hal_flash.h
  • IS_FLASH_TYPEERASE : stm32g0xx_hal_flash.h
  • IS_FLASH_TYPEPROGRAM : stm32g0xx_hal_flash.h
  • IS_GPIO_AF : stm32g0xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32g0xx_hal_gpio.h
  • IS_GPIO_PIN : stm32g0xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32g0xx_hal_gpio.h
  • IS_GPIO_PULL : stm32g0xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32g0xx_hal_gpio.h
  • IS_HAL_REMAP_PIN : stm32g0xx_hal.h
  • IS_HAL_SYSCFG_IRDA_ENV_SEL : stm32g0xx_hal.h
  • IS_HAL_SYSCFG_IRDA_POL_SEL : stm32g0xx_hal.h
  • IS_I2C_ADDRESSING_MODE : stm32g0xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32g0xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32g0xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32g0xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32g0xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32g0xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32g0xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32g0xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32g0xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32g0xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32g0xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32g0xx_hal_i2c.h
  • IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST : stm32g0xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32g0xx_hal_i2s.h
  • IS_I2S_CPOL : stm32g0xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32g0xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32g0xx_hal_i2s.h
  • IS_I2S_MODE : stm32g0xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32g0xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32g0xx_hal_irda.h
  • IS_IRDA_CLOCKPRESCALER : stm32g0xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32g0xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32g0xx_hal_irda.h
  • IS_IRDA_MODE : stm32g0xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32g0xx_hal_irda.h
  • IS_IRDA_PARITY : stm32g0xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32g0xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32g0xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32g0xx_hal_irda.h
  • IS_IRDA_STATE : stm32g0xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32g0xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32g0xx_hal_irda_ex.h
  • IS_IWDG_PRESCALER : stm32g0xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32g0xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32g0xx_hal_iwdg.h
  • IS_LL_ADC_CLOCK : stm32g0xx_ll_adc.c
  • IS_LL_ADC_CLOCK_FREQ_MODE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_COMMON_CLOCK : stm32g0xx_ll_adc.c
  • IS_LL_ADC_DATA_ALIGN : stm32g0xx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_MODE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32g0xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32g0xx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32g0xx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32g0xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32g0xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32g0xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32g0xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32g0xx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32g0xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32g0xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32g0xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_CONNECTION : stm32g0xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_MODE : stm32g0xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32g0xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32g0xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32g0xx_ll_dac.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32g0xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32g0xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32g0xx_ll_dma.c
  • IS_LL_DMA_PERIPHREQUEST : stm32g0xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32g0xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32g0xx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32g0xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32g0xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32g0xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32g0xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32g0xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32g0xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32g0xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32g0xx_ll_spi.c
  • IS_LL_I2S_CPOL : stm32g0xx_ll_spi.c
  • IS_LL_I2S_DATAFORMAT : stm32g0xx_ll_spi.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32g0xx_ll_spi.c
  • IS_LL_I2S_MODE : stm32g0xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32g0xx_ll_spi.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32g0xx_ll_spi.c
  • IS_LL_I2S_STANDARD : stm32g0xx_ll_spi.c
  • IS_LL_LPTIM_CLOCK_PRESCALER : stm32g0xx_ll_lptim.c
  • IS_LL_LPTIM_CLOCK_SOURCE : stm32g0xx_ll_lptim.c
  • IS_LL_LPTIM_OUTPUT_POLARITY : stm32g0xx_ll_lptim.c
  • IS_LL_LPTIM_WAVEFORM : stm32g0xx_ll_lptim.c
  • IS_LL_LPUART_BAUDRATE : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MAX : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MIN : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_PRESCALER : stm32g0xx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32g0xx_ll_lpuart.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_CEC_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_FDCAN_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_I2S_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_LPUART_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_RNG_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_TIM_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32g0xx_ll_rcc.c
  • IS_LL_RNG_CED : stm32g0xx_ll_rng.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32g0xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32g0xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32g0xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32g0xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32g0xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32g0xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32g0xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32g0xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32g0xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32g0xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32g0xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32g0xx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32g0xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK2_AFMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK2_FILTER : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK2_POLARITY : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK2_STATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK_AFMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK_FILTER : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32g0xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32g0xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32g0xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32g0xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32g0xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32g0xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32g0xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32g0xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32g0xx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32g0xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32g0xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32g0xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32g0xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32g0xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32g0xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32g0xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32g0xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32g0xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32g0xx_ll_usart.c
  • IS_LL_USART_PRESCALER : stm32g0xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32g0xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_HSI_DIV : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLR_VALUE : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32g0xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32g0xx_ll_utils.c
  • IS_LPTIM_AUTORELOAD : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32g0xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32g0xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32g0xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32g0xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32g0xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32g0xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32g0xx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32g0xx_hal_uart.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32g0xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32g0xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32g0xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32g0xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32g0xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32g0xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32g0xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32g0xx_hal_cortex.h
  • IS_OB_PCROP_CONFIG : stm32g0xx_hal_flash.h
  • IS_OB_RDP_LEVEL : stm32g0xx_hal_flash.h
  • IS_OB_SEC_BOOT_LOCK : stm32g0xx_hal_flash.h
  • IS_OB_SEC_SIZE : stm32g0xx_hal_flash.h
  • IS_OB_USER_CONFIG : stm32g0xx_hal_flash.h
  • IS_OB_USER_TYPE : stm32g0xx_hal_flash.h
  • IS_OB_WRPAREA : stm32g0xx_hal_flash.h
  • IS_OPTIONBYTE : stm32g0xx_hal_flash.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_FLASH_POWERDOWN : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_GPIO : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_GPIO_BIT_NUMBER : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_PVD_MODE : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_PVM_MODE : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_PVM_TYPE : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32g0xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32g0xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32g0xx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32g0xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32g0xx_hal_pwr.h
  • IS_RCC_ADCCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CECCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32g0xx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_FDCANCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32g0xx_hal_rcc.h
  • IS_RCC_HSE : stm32g0xx_hal_rcc.h
  • IS_RCC_HSI : stm32g0xx_hal_rcc.h
  • IS_RCC_HSI48 : stm32g0xx_hal_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_HSIDIV : stm32g0xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_I2S1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_I2S2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LPUART2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LSCOSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32g0xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32g0xx_hal_rcc.h
  • IS_RCC_LSI : stm32g0xx_hal_rcc.h
  • IS_RCC_MCO : stm32g0xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_MCO2DIV : stm32g0xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32g0xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32g0xx_hal_rcc.h
  • IS_RCC_PCLK : stm32g0xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32g0xx_hal_rcc.h
  • IS_RCC_PLLSOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_RNGCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_RNGDIV : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32g0xx_hal_rcc.h
  • IS_RCC_TIM15CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_TIM1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32g0xx_hal_rcc_ex.h
  • IS_RNG_CED : stm32g0xx_hal_rng.h
  • IS_RNG_FLAG : stm32g0xx_hal_rng.h
  • IS_RNG_IT : stm32g0xx_hal_rng.h
  • IS_RTC_ALARM : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32g0xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32g0xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32g0xx_hal_rtc.h
  • IS_RTC_BKP : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32g0xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32g0xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32g0xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32g0xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32g0xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32g0xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32g0xx_hal_rtc.h
  • IS_RTC_INTERNAL_TAMPER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_MINUTES : stm32g0xx_hal_rtc.h
  • IS_RTC_MONTH : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT_POL : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT_PULLUP : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32g0xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32g0xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32g0xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32g0xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32g0xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMPONTAMPER_DETECTION : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32g0xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32g0xx_hal_rtc.h
  • IS_RTC_YEAR : stm32g0xx_hal_rtc.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_CLOCKPRESCALER : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_FIFOMODE_STATE : stm32g0xx_hal_smartcard_ex.h
  • IS_SMARTCARD_LASTBIT : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32g0xx_hal_smartcard_ex.h
  • IS_SMARTCARD_STOPBITS : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32g0xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32g0xx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32g0xx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32g0xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32g0xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32g0xx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32g0xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32g0xx_hal_smbus.h
  • IS_SMBUS_FASTMODEPLUS : stm32g0xx_hal_smbus_ex.h
  • IS_SMBUS_GENERAL_CALL : stm32g0xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32g0xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32g0xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32g0xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32g0xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32g0xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32g0xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32g0xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32g0xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32g0xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32g0xx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32g0xx_hal_spi.h
  • IS_SPI_CPHA : stm32g0xx_hal_spi.h
  • IS_SPI_CPOL : stm32g0xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32g0xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32g0xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32g0xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32g0xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32g0xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32g0xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32g0xx_hal_spi.h
  • IS_SPI_DMA_HANDLE : stm32g0xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32g0xx_hal_spi.h
  • IS_SPI_MODE : stm32g0xx_hal_spi.h
  • IS_SPI_NSS : stm32g0xx_hal_spi.h
  • IS_SPI_NSSP : stm32g0xx_hal_spi.h
  • IS_SPI_TIMODE : stm32g0xx_hal_spi.h
  • IS_SYSCFG_BREAK_CONFIG : stm32g0xx_hal.h
  • IS_SYSCFG_CLAMPINGDIODE : stm32g0xx_hal.h
  • IS_SYSCFG_DBATT_CONFIG : stm32g0xx_hal.h
  • IS_SYSCFG_FASTMODEPLUS : stm32g0xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32g0xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32g0xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32g0xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32g0xx_hal_cortex.h
  • IS_TICKFREQ : stm32g0xx_hal.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK2_AFMODE : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_AFMODE : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32g0xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32g0xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32g0xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32g0xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32g0xx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32g0xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32g0xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32g0xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32g0xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32g0xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32g0xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32g0xx_hal_tim.h
  • IS_TIM_DMA_DATA_LENGTH : stm32g0xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32g0xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_ENCODERINPUT_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32g0xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32g0xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32g0xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32g0xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32g0xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32g0xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32g0xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32g0xx_hal_tim.h
  • IS_TIM_PERIOD : stm32g0xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_REMAP : stm32g0xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32g0xx_hal_tim.h
  • IS_TIM_SLAVEMODE_TRIGGER_ENABLED : stm32g0xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32g0xx_hal_tim.h
  • IS_TIM_TISEL : stm32g0xx_hal_tim_ex.h
  • IS_TIM_TRGO2_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32g0xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32g0xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32g0xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32g0xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32g0xx_hal_tim.h
  • IS_TIM_UIFREMAP_MODE : stm32g0xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32g0xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32g0xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32g0xx_hal_i2c.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32g0xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32g0xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32g0xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32g0xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32g0xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32g0xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32g0xx_hal_uart.h
  • IS_UART_DMA_RX : stm32g0xx_hal_uart.h
  • IS_UART_DMA_TX : stm32g0xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32g0xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32g0xx_hal_uart.h
  • IS_UART_LIN : stm32g0xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32g0xx_hal_uart.h
  • IS_UART_MODE : stm32g0xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32g0xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32g0xx_hal_uart.h
  • IS_UART_OVERRUN : stm32g0xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32g0xx_hal_uart.h
  • IS_UART_PARITY : stm32g0xx_hal_uart.h
  • IS_UART_PRESCALER : stm32g0xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32g0xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT_VALUE : stm32g0xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32g0xx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32g0xx_hal_uart_ex.h
  • IS_UART_STATE : stm32g0xx_hal_uart.h
  • IS_UART_STOPBITS : stm32g0xx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32g0xx_hal_uart_ex.h
  • IS_UART_WAKEUP_SELECTION : stm32g0xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32g0xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32g0xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32g0xx_hal_usart.h
  • IS_USART_CLOCK : stm32g0xx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32g0xx_hal_usart_ex.h
  • IS_USART_LASTBIT : stm32g0xx_hal_usart.h
  • IS_USART_MODE : stm32g0xx_hal_usart.h
  • IS_USART_NSS : stm32g0xx_hal_usart_ex.h
  • IS_USART_PARITY : stm32g0xx_hal_usart.h
  • IS_USART_PHASE : stm32g0xx_hal_usart.h
  • IS_USART_POLARITY : stm32g0xx_hal_usart.h
  • IS_USART_PRESCALER : stm32g0xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32g0xx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32g0xx_hal_usart_ex.h
  • IS_USART_SLAVEMODE : stm32g0xx_hal_usart_ex.h
  • IS_USART_STOPBITS : stm32g0xx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32g0xx_hal_usart_ex.h
  • IS_USART_WORD_LENGTH : stm32g0xx_hal_usart_ex.h
  • IS_WWDG_COUNTER : stm32g0xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32g0xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32g0xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32g0xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32g0xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32g0xx_hal_iwdg.h
  • IWDG_KERNEL_UPDATE_FLAGS : stm32g0xx_hal_iwdg.c
  • IWDG_KEY_ENABLE : stm32g0xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32g0xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32g0xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32g0xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32g0xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32g0xx_hal_iwdg.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- l -

  • LL_ADC_AWD1 : stm32g0xx_ll_adc.h
  • LL_ADC_AWD2 : stm32g0xx_ll_adc.h
  • LL_ADC_AWD3 : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32g0xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32g0xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_FREQ_MODE_HIGH : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_FREQ_MODE_LOW : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32g0xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32g0xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32g0xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32g0xx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32g0xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_CCRDY : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_EOCAL : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32g0xx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32g0xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32g0xx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32g0xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32g0xx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32g0xx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32g0xx_ll_adc.h
  • LL_ADC_IT_CCRDY : stm32g0xx_ll_adc.h
  • LL_ADC_IT_EOC : stm32g0xx_ll_adc.h
  • LL_ADC_IT_EOCAL : stm32g0xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32g0xx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32g0xx_ll_adc.h
  • LL_ADC_IT_OVR : stm32g0xx_ll_adc.h
  • LL_ADC_LP_AUTOPOWEROFF : stm32g0xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32g0xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF : stm32g0xx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_128 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_16 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_2 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_256 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_32 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_4 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_64 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_RATIO_8 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32g0xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32g0xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32g0xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32g0xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32g0xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32g0xx_ll_adc.h
  • LL_ADC_ReadReg : stm32g0xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32g0xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32g0xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32g0xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_CONFIGURABLE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_FIXED : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DIR_FORWARD : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH4 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO : stm32g0xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32g0xx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32g0xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32g0xx_ll_adc.h
  • LL_ADC_RESOLUTION_6B : stm32g0xx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_12CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_160CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_19CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_1CYCLE_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_39CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_3CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_79CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_7CYCLES_5 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_COMMON_1 : stm32g0xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_COMMON_2 : stm32g0xx_ll_adc.h
  • LL_ADC_TEMPERATURE_CALC_ERROR : stm32g0xx_ll_adc.h
  • LL_ADC_TRIGGER_FREQ_HIGH : stm32g0xx_ll_adc.h
  • LL_ADC_TRIGGER_FREQ_LOW : stm32g0xx_ll_adc.h
  • LL_ADC_WriteReg : stm32g0xx_ll_adc.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRYP : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_RNG : stm32g0xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CEC : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CRS : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DBGMCU : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_FDCAN : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPUART1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPUART2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_RTC : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UCPD1 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UCPD2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART4 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART5 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART6 : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32g0xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ADC : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SYSCFG : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM14 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32g0xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32g0xx_ll_bus.h
  • LL_COMP_BLANKINGSRC_NONE : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC2 : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC4 : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5 : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3 : stm32g0xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3 : stm32g0xx_ll_comp.h
  • LL_COMP_DELAY_STARTUP_US : stm32g0xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32g0xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32g0xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32g0xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32g0xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO3 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32g0xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO3 : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32g0xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32g0xx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32g0xx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32g0xx_ll_comp.h
  • LL_COMP_ReadReg : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_BITOFFSET_POS : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMPX_SETTING_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_BOTH : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_COMP1 : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_COMP2 : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_COMP3 : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK : stm32g0xx_ll_comp.h
  • LL_COMP_WINDOWOUTPUT_EACH_COMP : stm32g0xx_ll_comp.h
  • LL_COMP_WriteReg : stm32g0xx_ll_comp.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32g0xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32g0xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32g0xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32g0xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32g0xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32g0xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32g0xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32g0xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32g0xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32g0xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32g0xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32g0xx_ll_crc.h
  • LL_CRC_ReadReg : stm32g0xx_ll_crc.h
  • LL_CRC_WriteReg : stm32g0xx_ll_crc.h
  • LL_CRS_CR_ERRIE : stm32g0xx_ll_crs.h
  • LL_CRS_CR_ESYNCIE : stm32g0xx_ll_crs.h
  • LL_CRS_CR_SYNCOKIE : stm32g0xx_ll_crs.h
  • LL_CRS_CR_SYNCWARNIE : stm32g0xx_ll_crs.h
  • LL_CRS_ERRORLIMIT_DEFAULT : stm32g0xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_DOWN : stm32g0xx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_UP : stm32g0xx_ll_crs.h
  • LL_CRS_HSI48CALIBRATION_DEFAULT : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_ERRF : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_ESYNCF : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_SYNCERR : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_SYNCMISS : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_SYNCOKF : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_SYNCWARNF : stm32g0xx_ll_crs.h
  • LL_CRS_ISR_TRIMOVF : stm32g0xx_ll_crs.h
  • LL_CRS_ReadReg : stm32g0xx_ll_crs.h
  • LL_CRS_RELOADVALUE_DEFAULT : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_1 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_128 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_16 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_2 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_32 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_4 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_64 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_DIV_8 : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_FALLING : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_RISING : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_GPIO : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_LSE : stm32g0xx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_USB : stm32g0xx_ll_crs.h
  • LL_CRS_WriteReg : stm32g0xx_ll_crs.h
  • LL_DAC_CHANNEL_1 : stm32g0xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32g0xx_ll_dac.h
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32g0xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32g0xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32g0xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32g0xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_BWST1 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_BWST2 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_CAL1 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_CAL2 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32g0xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32g0xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32g0xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32g0xx_ll_dac.h
  • LL_DAC_MODE_CALIBRATION : stm32g0xx_ll_dac.h
  • LL_DAC_MODE_NORMAL_OPERATION : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32g0xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_GPIO : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_INTERNAL : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_NORMAL : stm32g0xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD : stm32g0xx_ll_dac.h
  • LL_DAC_ReadReg : stm32g0xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32g0xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM1_OUT : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_LPTIM2_OUT : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM15_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM1_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM3_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32g0xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32g0xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32g0xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32g0xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32g0xx_ll_dac.h
  • LL_DAC_WriteReg : stm32g0xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM2_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM14_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32g0xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32g0xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32g0xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32g0xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32g0xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32g0xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32g0xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32g0xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32g0xx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32g0xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32g0xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32g0xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32g0xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32g0xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32g0xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32g0xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32g0xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32g0xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32g0xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32g0xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32g0xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32g0xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32g0xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32g0xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32g0xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32g0xx_ll_dma.h
  • LL_DMA_ReadReg : stm32g0xx_ll_dma.h
  • LL_DMA_WriteReg : stm32g0xx_ll_dma.h
  • LL_DMAMUX_CCR_SOIE : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_MAX_REQ : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_ReadReg : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES_IN : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC1_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_DAC1_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM2_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_NO_EVENT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_FALLING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_TIM14_OC : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_MEM2MEM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI3_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI3_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_TRIG_COM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM15_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_COM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_COM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_TRIG_COM : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_TRIG : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_CH4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_TRIG : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM3_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_CH4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_TRIG : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM4_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM6_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM7_UP : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_UCPD2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART2_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART2_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART3_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART3_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART4_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART4_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART5_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART5_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART6_RX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART6_TX : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGCR_RGOIE : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE0 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE1 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE10 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE11 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE12 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE13 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE14 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE15 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE2 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE3 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE4 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE5 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE6 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE7 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE8 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE9 : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM1_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM2_OUT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_NO_EVENT : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_FALLING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING_FALLING : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_SYNC_TIM14_OC : stm32g0xx_ll_dmamux.h
  • LL_DMAMUX_WriteReg : stm32g0xx_ll_dmamux.h
  • LL_EXTI_CONFIG_LINE0 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE1 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE10 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE11 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE12 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE13 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE14 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE15 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE2 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE3 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE4 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE5 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE6 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE7 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE8 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_LINE9 : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTA : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTB : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTC : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTD : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTE : stm32g0xx_ll_exti.h
  • LL_EXTI_CONFIG_PORTF : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_31 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_32 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_33 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_34 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_35 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32g0xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32g0xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32g0xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32g0xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32g0xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32g0xx_ll_exti.h
  • LL_EXTI_REGISTER_PINPOS_SHFT : stm32g0xx_ll_exti.h
  • LL_EXTI_TRIGGER_FALLING : stm32g0xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32g0xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32g0xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32g0xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32g0xx_ll_exti.h
  • LL_FLASH_LATENCY_0 : stm32g0xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32g0xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32g0xx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32g0xx_ll_system.h
  • LL_GPIO_AF_0 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32g0xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32g0xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32g0xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32g0xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32g0xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32g0xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32g0xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32g0xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32g0xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32g0xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32g0xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32g0xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FAST : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_HIGH : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_LOW : stm32g0xx_ll_gpio.h
  • LL_GPIO_SPEED_MEDIUM : stm32g0xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32g0xx_ll_gpio.h
  • LL_I2C_ACK : stm32g0xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32g0xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32g0xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32g0xx_ll_i2c.h
  • LL_I2C_DIRECTION_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32g0xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32g0xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32g0xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32g0xx_ll_i2c.h
  • LL_I2C_NACK : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32g0xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32g0xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32g0xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32g0xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32g0xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32g0xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32g0xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_16K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_192K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_22K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_32K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_44K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_48K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_8K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_96K : stm32g0xx_ll_spi.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32g0xx_ll_spi.h
  • LL_I2S_CR2_ERRIE : stm32g0xx_ll_spi.h
  • LL_I2S_CR2_RXNEIE : stm32g0xx_ll_spi.h
  • LL_I2S_CR2_TXEIE : stm32g0xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B : stm32g0xx_ll_spi.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32g0xx_ll_spi.h
  • LL_I2S_DATAFORMAT_24B : stm32g0xx_ll_spi.h
  • LL_I2S_DATAFORMAT_32B : stm32g0xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32g0xx_ll_spi.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32g0xx_ll_spi.h
  • LL_I2S_MODE_MASTER_RX : stm32g0xx_ll_spi.h
  • LL_I2S_MODE_MASTER_TX : stm32g0xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_RX : stm32g0xx_ll_spi.h
  • LL_I2S_MODE_SLAVE_TX : stm32g0xx_ll_spi.h
  • LL_I2S_POLARITY_HIGH : stm32g0xx_ll_spi.h
  • LL_I2S_POLARITY_LOW : stm32g0xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32g0xx_ll_spi.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32g0xx_ll_spi.h
  • LL_I2S_ReadReg : stm32g0xx_ll_spi.h
  • LL_I2S_SR_BSY : stm32g0xx_ll_spi.h
  • LL_I2S_SR_FRE : stm32g0xx_ll_spi.h
  • LL_I2S_SR_OVR : stm32g0xx_ll_spi.h
  • LL_I2S_SR_RXNE : stm32g0xx_ll_spi.h
  • LL_I2S_SR_TXE : stm32g0xx_ll_spi.h
  • LL_I2S_SR_UDR : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_LSB : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_MSB : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_LONG : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32g0xx_ll_spi.h
  • LL_I2S_STANDARD_PHILIPS : stm32g0xx_ll_spi.h
  • LL_I2S_WriteReg : stm32g0xx_ll_spi.h
  • LL_IOP_GRP1_PERIPH_ALL : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOA : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOB : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOC : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOD : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOE : stm32g0xx_ll_bus.h
  • LL_IOP_GRP1_PERIPH_GPIOF : stm32g0xx_ll_bus.h
  • LL_IWDG_KEY_ENABLE : stm32g0xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32g0xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32g0xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32g0xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32g0xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32g0xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32g0xx_ll_iwdg.h
  • LL_LPTIM_CLK_FILTER_2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32g0xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32g0xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32g0xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32g0xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP3 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32g0xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32g0xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32g0xx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32g0xx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32g0xx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_RXFFIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE_RXFNEIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE_TXFNFIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR1_TXFEIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_RXFTIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_TXFTIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_NONE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_2 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_4 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_8 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_3_4 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_7_8 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_8_8 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_RXFT : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE_RXFNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TXE_TXFNF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_TXFT : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV1 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV10 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV12 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV128 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV16 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV2 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV256 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV32 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV4 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV6 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV64 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV8 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32g0xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32g0xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32g0xx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32g0xx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32g0xx_ll_lpuart.h
  • LL_MAX_DELAY : stm32g0xx_ll_utils.h
  • LL_MPU_ACCESS_BUFFERABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32g0xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32g0xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32g0xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32g0xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32g0xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32g0xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32g0xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32g0xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32g0xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32g0xx_ll_cortex.h
  • LL_PWR_BATTCHARG_RESISTOR_1_5K : stm32g0xx_ll_pwr.h
  • LL_PWR_BATTCHARG_RESISTOR_5K : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_A : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_B : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_0 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_1 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_10 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_11 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_12 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_13 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_14 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_15 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_2 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_3 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_4 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_5 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_6 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_7 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_8 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_9 : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_C : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_D : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_E : stm32g0xx_ll_pwr.h
  • LL_PWR_GPIO_F : stm32g0xx_ll_pwr.h
  • LL_PWR_MODE_SHUTDOWN : stm32g0xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32g0xx_ll_pwr.h
  • LL_PWR_MODE_STOP0 : stm32g0xx_ll_pwr.h
  • LL_PWR_MODE_STOP1 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_0 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_1 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_2 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_3 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_4 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_5 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_6 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDHLEVEL_7 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_0 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_1 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_2 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_3 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_4 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_5 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVDLLEVEL_6 : stm32g0xx_ll_pwr.h
  • LL_PWR_PVM_USB : stm32g0xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32g0xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32g0xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CSBF : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF1 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF2 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF3 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF4 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF5 : stm32g0xx_ll_pwr.h
  • LL_PWR_SCR_CWUF6 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_SBF : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF1 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF2 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF3 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF4 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF5 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUF6 : stm32g0xx_ll_pwr.h
  • LL_PWR_SR1_WUFI : stm32g0xx_ll_pwr.h
  • LL_PWR_SR2_PVDO : stm32g0xx_ll_pwr.h
  • LL_PWR_SR2_REGLPF : stm32g0xx_ll_pwr.h
  • LL_PWR_SR2_REGLPS : stm32g0xx_ll_pwr.h
  • LL_PWR_SR2_VOSF : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32g0xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN6 : stm32g0xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32g0xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_HSI_DIV488 : stm32g0xx_ll_rcc.h
  • LL_RCC_CEC_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_CSSC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_HSERDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_HSI48RDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_HSIRDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_LSECSSC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_LSERDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_LSIRDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CICR_PLLRDYC : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_HSERDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_HSI48RDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_HSIRDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_LSERDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_LSIRDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIER_PLLRDYIE : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_CSSF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_HSERDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_HSI48RDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_HSIRDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_LSECSSF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_LSERDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_LSIRDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CIFR_PLLRDYF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_PWRRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32g0xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_FDCAN_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_128 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_32 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_64 : stm32g0xx_ll_rcc.h
  • LL_RCC_HSI_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE_PIN : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S1_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE_PIN : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_I2S2_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_LPUART2_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32g0xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32g0xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32g0xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1024 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_128 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_256 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_32 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_512 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_64 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI48 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLPCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLQCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_RTC_WKUP : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_RTCCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_1024 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_128 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_256 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_32 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_512 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_64 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_HSI48 : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_NOCLOCK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLLCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLLPCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_PLLQCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_RTC_WKUP : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_RTCCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_MCO2SOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32g0xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_3 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_5 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_6 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_7 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_10 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_11 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_12 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_13 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_14 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_15 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_17 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_18 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_19 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_20 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_21 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_22 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_23 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_24 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_25 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_26 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_27 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_28 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_29 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_3 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_30 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_31 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_32 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_5 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_6 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_7 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_9 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_3 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_5 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_6 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_7 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_3 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_5 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_6 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_7 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32g0xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLK_DIV1 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLK_DIV2 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLK_DIV4 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLK_DIV8 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKDIV : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_HSI_DIV8 : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_NONE : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32g0xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_LSI : stm32g0xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32g0xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM15_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM15_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM15_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_TIM1_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_HSI : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_LSE : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_PCLK1 : stm32g0xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_SYSCLK : stm32g0xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32g0xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSE : stm32g0xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSI48 : stm32g0xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32g0xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32g0xx_ll_rcc.h
  • LL_RNG_CED_DISABLE : stm32g0xx_ll_rng.h
  • LL_RNG_CED_ENABLE : stm32g0xx_ll_rng.h
  • LL_RNG_CR_IE : stm32g0xx_ll_rng.h
  • LL_RNG_ReadReg : stm32g0xx_ll_rng.h
  • LL_RNG_SR_CECS : stm32g0xx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32g0xx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32g0xx_ll_rng.h
  • LL_RNG_SR_SECS : stm32g0xx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32g0xx_ll_rng.h
  • LL_RNG_WriteReg : stm32g0xx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_ALL : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_ALL : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32g0xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32g0xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32g0xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32g0xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32g0xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32g0xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32g0xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32g0xx_ll_rtc.h
  • LL_RTC_FORMAT_BCD : stm32g0xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32g0xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32g0xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_ALRAWF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_ALRBWF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_INITF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_INITS : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_RECALPF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_RSF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_SHPF : stm32g0xx_ll_rtc.h
  • LL_RTC_ICSR_WUTWF : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32g0xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32g0xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32g0xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32g0xx_ll_rtc.h
  • LL_RTC_ReadReg : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_ALRAF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_ALRBF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_ITSF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_TSF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_TSOVF : stm32g0xx_ll_rtc.h
  • LL_RTC_SCR_WUTF : stm32g0xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32g0xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP4 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP5 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_ITAMP6 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32g0xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32g0xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32g0xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32g0xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32g0xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32g0xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32g0xx_ll_rtc.h
  • LL_RTC_WriteReg : stm32g0xx_ll_rtc.h
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32g0xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32g0xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32g0xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32g0xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32g0xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32g0xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32g0xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32g0xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32g0xx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32g0xx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32g0xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32g0xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32g0xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32g0xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32g0xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32g0xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32g0xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32g0xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32g0xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32g0xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32g0xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32g0xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32g0xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32g0xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32g0xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32g0xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32g0xx_ll_spi.h
  • LL_SPI_ReadReg : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32g0xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32g0xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32g0xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32g0xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32g0xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32g0xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32g0xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32g0xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32g0xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32g0xx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32g0xx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32g0xx_ll_spi.h
  • LL_SPI_WriteReg : stm32g0xx_ll_spi.h
  • LL_SYSCFG_CFGR1_BOOSTEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA13_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA1_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA3_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA5_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PA6_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PB0_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PB1_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_CFGR2_PB2_CDEN : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PA10 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PA9 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32g0xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_MOD_TIM16 : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_MOD_USART1 : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_MOD_USART4 : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_POL_INVERTED : stm32g0xx_ll_system.h
  • LL_SYSCFG_IR_POL_NOT_INVERTED : stm32g0xx_ll_system.h
  • LL_SYSCFG_PIN_RMP_PA11 : stm32g0xx_ll_system.h
  • LL_SYSCFG_PIN_RMP_PA12 : stm32g0xx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32g0xx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32g0xx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32g0xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ECC : stm32g0xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32g0xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32g0xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM_PARITY : stm32g0xx_ll_system.h
  • LL_SYSCFG_UCPD1_STROBE : stm32g0xx_ll_system.h
  • LL_SYSCFG_UCPD2_STROBE : stm32g0xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32g0xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32g0xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32g0xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32g0xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32g0xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_AFMODE_INPUT : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_AFMODE_BIDIRECTIONAL : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_AFMODE_INPUT : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32g0xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32g0xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32g0xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32g0xx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32g0xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32g0xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_BIE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32g0xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF2 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR1 : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_TISEL : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32g0xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32g0xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32g0xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32g0xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD1 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD2 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD3 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_LSE : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_MCO : stm32g0xx_ll_tim.h
  • LL_TIM_ETRSOURCE_MCO2 : stm32g0xx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32g0xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32g0xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32g0xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32g0xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32g0xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32g0xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32g0xx_ll_tim.h
  • LL_TIM_ICPSC_DIV1 : stm32g0xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32g0xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32g0xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32g0xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32g0xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32g0xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32g0xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32g0xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32g0xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32g0xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32g0xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_ETR : stm32g0xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32g0xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32g0xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32g0xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_ReadReg : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32g0xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32g0xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32g0xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_HSE_32 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_MCO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_MCO2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM14_TI1_RMP_RTC_CLK : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_TIM2_IC1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_TIM3_IC1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_TIM2_IC2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM15_TI2_RMP_TIM3_IC2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSE : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSI : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_MCO2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC_WK : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSE_32 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSI48 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI2_RMP_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI3_RMP_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM1_TI3_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI3_RMP_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM2_TI3_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI3_RMP_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM3_TI3_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_COMP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI1_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_COMP2 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI2_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI3_RMP_COMP3 : stm32g0xx_ll_tim.h
  • LL_TIM_TIM4_TI3_RMP_GPIO : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32g0xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_ITR7 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32g0xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32g0xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32g0xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32g0xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32g0xx_ll_tim.h
  • LL_TIM_WriteReg : stm32g0xx_ll_tim.h
  • LL_UCPD_CCENABLE_CC1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_CC1CC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_CC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCENABLE_NONE : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCPIN_CC1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_CCPIN_CC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_EOP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_FRSEVT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_HRSTDISC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_HRSTSENT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXHRSTDET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXMSGEND : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXNE : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXORDDET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_RXOVR : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXIS : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGABT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGDISC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXMSGSENT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TXUND : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TYPECEVT1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_IMR_TYPECEVT2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_CABLE_RESET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_HARD_RESET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP1_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERED_SET_SOP2_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_CABLERST : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_HARDRST : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP1_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP2_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP_EXT1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ORDERSET_SOP_EXT2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV16 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV4 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_PSC_DIV8 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ReadReg : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_1_5A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_3_0A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_DEFAULT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RESISTOR_NONE : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ROLE_SNK : stm32g0xx_ll_ucpd.h
  • LL_UCPD_ROLE_SRC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RST1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RST2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXMODE_BIST_TEST_DATA : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXMODE_NORMAL : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_CABLE_RESET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP1_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOP2_DEBUG : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOPEXT1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_RXORDSET_SOPEXT2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VOPEN : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP15A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC1_VRP30A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VOPEN : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP15A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SNK_CC2_VRP30A : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_FRSEVT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_HRSTDISC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_HRSTSENT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXERR : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXHRSTDET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXMSGEND : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXNE : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXORDDET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_RXOVR : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXIS : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGABT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGDISC : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXMSGSENT : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TXUND : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TYPEC_VSTATE_CC1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TYPEC_VSTATE_CC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TYPECEVT1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SR_TYPECEVT2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_OPEN : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_VRA : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC1_VRD : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_OPEN : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_VRA : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SRC_CC2_VRD : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SYNC1 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SYNC2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_SYNC3 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TXMODE_BIST_CARRIER2 : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TXMODE_CABLE_RESET : stm32g0xx_ll_ucpd.h
  • LL_UCPD_TXMODE_NORMAL : stm32g0xx_ll_ucpd.h
  • LL_UCPD_WriteReg : stm32g0xx_ll_ucpd.h
  • LL_USART_ADDRESS_DETECT_4B : stm32g0xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32g0xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32g0xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32g0xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32g0xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32g0xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32g0xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32g0xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32g0xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32g0xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32g0xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_RXFFIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_RXNEIE_RXFNEIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_TXEIE_TXFNFIE : stm32g0xx_ll_usart.h
  • LL_USART_CR1_TXFEIE : stm32g0xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_RXFTIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_TCBGTIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_TXFTIE : stm32g0xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32g0xx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32g0xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32g0xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32g0xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32g0xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32g0xx_ll_usart.h
  • LL_USART_DIRECTION_NONE : stm32g0xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32g0xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32g0xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_DisableIT_TXE : stm32g0xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32g0xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_EnableIT_TXE : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_2 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_4 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_8 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_3_4 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_7_8 : stm32g0xx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_8_8 : stm32g0xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32g0xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32g0xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32g0xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32g0xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_NECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_TCBGTCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_TXFECF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_UDRCF : stm32g0xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32g0xx_ll_usart.h
  • LL_USART_IRDA_POWER_LOW : stm32g0xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32g0xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32g0xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_FE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_NE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_PE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RXFF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RXFT : stm32g0xx_ll_usart.h
  • LL_USART_ISR_RXNE_RXFNE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TC : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TCBGT : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TXE_TXFNF : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TXFE : stm32g0xx_ll_usart.h
  • LL_USART_ISR_TXFT : stm32g0xx_ll_usart.h
  • LL_USART_ISR_UDR : stm32g0xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32g0xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32g0xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32g0xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32g0xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32g0xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32g0xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32g0xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32g0xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32g0xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32g0xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32g0xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32g0xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32g0xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV1 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV10 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV12 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV128 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV16 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV2 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV256 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV32 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV4 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV6 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV64 : stm32g0xx_ll_usart.h
  • LL_USART_PRESCALER_DIV8 : stm32g0xx_ll_usart.h
  • LL_USART_ReadReg : stm32g0xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32g0xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32g0xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32g0xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32g0xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32g0xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32g0xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32g0xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32g0xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32g0xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32g0xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32g0xx_ll_usart.h
  • LL_USART_WriteReg : stm32g0xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32g0xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_BGA100 : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_BGA64_N : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN32_GP : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN32_N : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN48_GP : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN48_N : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN64_GP : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN64_N : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFP100 : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFP80 : stm32g0xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP52 : stm32g0xx_ll_utils.h
  • LL_VREFBUF_VOLTAGE_SCALE0 : stm32g0xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE1 : stm32g0xx_ll_system.h
  • LL_WWDG_CFR_EWI : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_128 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_16 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_32 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_64 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32g0xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32g0xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32g0xx_ll_wwdg.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32g0xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32g0xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32g0xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32g0xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32g0xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32g0xx_hal_lptim.h
  • LPTIM_EXTI_LINE_LPTIM1 : stm32g0xx_hal_lptim.h
  • LPTIM_EXTI_LINE_LPTIM2 : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32g0xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32g0xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32g0xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32g0xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32g0xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32g0xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32g0xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32g0xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32g0xx_hal_lptim.h
  • LPTIM_IT_UP : stm32g0xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32g0xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32g0xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32g0xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32g0xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32g0xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32g0xx_hal_lptim.h
  • LPUART_BRR_MASK : stm32g0xx_ll_lpuart.h
  • LPUART_BRR_MAX : stm32g0xx_hal_uart.c
  • LPUART_BRR_MIN : stm32g0xx_hal_uart.c
  • LPUART_BRR_MIN_VALUE : stm32g0xx_ll_lpuart.h
  • LPUART_LPUARTDIV_FREQ_MUL : stm32g0xx_ll_lpuart.h
  • LSCO_CLK_ENABLE : stm32g0xx_hal_rcc_ex.c
  • LSCO_GPIO_PORT : stm32g0xx_hal_rcc_ex.c
  • LSCO_PIN : stm32g0xx_hal_rcc_ex.c
  • LSE_STARTUP_TIMEOUT : stm32g0xx_hal_conf.h
  • LSE_VALUE : stm32g0xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c
  • LSI_VALUE : stm32g0xx_hal_conf.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- m -

  • MAX_NBYTE_SIZE : stm32g0xx_hal_i2c.c , stm32g0xx_hal_smbus.c
  • MCO1_CLK_ENABLE : stm32g0xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32g0xx_hal_rcc.c
  • MCO1_PIN : stm32g0xx_hal_rcc.c
  • MCO2_CLK_ENABLE : stm32g0xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32g0xx_hal_rcc.c
  • MCO2_PIN : stm32g0xx_hal_rcc.c
  • MODE_AF : stm32g0xx_hal_gpio.h
  • MODE_ANALOG : stm32g0xx_hal_gpio.h
  • MODE_INPUT : stm32g0xx_hal_gpio.h
  • MODE_OUTPUT : stm32g0xx_hal_gpio.h
  • MPU_ACCESS_BUFFERABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32g0xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32g0xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32g0xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32g0xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32g0xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32g0xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32g0xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32g0xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32g0xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32g0xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32g0xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32g0xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32g0xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32g0xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32g0xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32g0xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32g0xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32g0xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32g0xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32g0xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32g0xx_hal_cortex.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- o -

  • OB_BOOT0_FROM_OB : stm32g0xx_hal_flash.h
  • OB_BOOT0_FROM_PIN : stm32g0xx_hal_flash.h
  • OB_BOOT1_SRAM : stm32g0xx_hal_flash.h
  • OB_BOOT1_SYSTEM : stm32g0xx_hal_flash.h
  • OB_BOOT_ENTRY_FORCED_FLASH : stm32g0xx_hal_flash.h
  • OB_BOOT_ENTRY_FORCED_NONE : stm32g0xx_hal_flash.h
  • OB_BOR_DISABLE : stm32g0xx_hal_flash.h
  • OB_BOR_ENABLE : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_FALLING_0 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_FALLING_1 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_FALLING_2 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_FALLING_3 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_RISING_0 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_RISING_1 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_RISING_2 : stm32g0xx_hal_flash.h
  • OB_BOR_LEVEL_RISING_3 : stm32g0xx_hal_flash.h
  • OB_DUAL_BANK_BASE : stm32g0xx_hal_flash.h
  • OB_DUAL_BANK_VALUE : stm32g0xx_hal_flash.h
  • OB_IRH_DISABLE : stm32g0xx_hal_flash.h
  • OB_IRH_ENABLE : stm32g0xx_hal_flash.h
  • OB_IWDG_HW : stm32g0xx_hal_flash.h
  • OB_IWDG_STDBY_FREEZE : stm32g0xx_hal_flash.h
  • OB_IWDG_STDBY_RUN : stm32g0xx_hal_flash.h
  • OB_IWDG_STOP_FREEZE : stm32g0xx_hal_flash.h
  • OB_IWDG_STOP_RUN : stm32g0xx_hal_flash.h
  • OB_IWDG_SW : stm32g0xx_hal_flash.h
  • OB_nBOOT0_RESET : stm32g0xx_hal_flash.h
  • OB_nBOOT0_SET : stm32g0xx_hal_flash.h
  • OB_PCROP_RDP_ERASE : stm32g0xx_hal_flash.h
  • OB_PCROP_RDP_NOT_ERASE : stm32g0xx_hal_flash.h
  • OB_PCROP_ZONE2_A : stm32g0xx_hal_flash.h
  • OB_PCROP_ZONE2_B : stm32g0xx_hal_flash.h
  • OB_PCROP_ZONE_A : stm32g0xx_hal_flash.h
  • OB_PCROP_ZONE_B : stm32g0xx_hal_flash.h
  • OB_RDP_LEVEL_0 : stm32g0xx_hal_flash.h
  • OB_RDP_LEVEL_1 : stm32g0xx_hal_flash.h
  • OB_RDP_LEVEL_2 : stm32g0xx_hal_flash.h
  • OB_RESET_MODE_GPIO : stm32g0xx_hal_flash.h
  • OB_RESET_MODE_INPUT_ONLY : stm32g0xx_hal_flash.h
  • OB_RESET_MODE_INPUT_OUTPUT : stm32g0xx_hal_flash.h
  • OB_SHUTDOWN_NORST : stm32g0xx_hal_flash.h
  • OB_SHUTDOWN_RST : stm32g0xx_hal_flash.h
  • OB_SRAM_PARITY_DISABLE : stm32g0xx_hal_flash.h
  • OB_SRAM_PARITY_ENABLE : stm32g0xx_hal_flash.h
  • OB_STANDBY_NORST : stm32g0xx_hal_flash.h
  • OB_STANDBY_RST : stm32g0xx_hal_flash.h
  • OB_STOP_NORST : stm32g0xx_hal_flash.h
  • OB_STOP_RST : stm32g0xx_hal_flash.h
  • OB_USER_ALL : stm32g0xx_hal_flash.h
  • OB_USER_BANK_SWAP : stm32g0xx_hal_flash.h
  • OB_USER_BOR_EN : stm32g0xx_hal_flash.h
  • OB_USER_BOR_LEV : stm32g0xx_hal_flash.h
  • OB_USER_DUAL_BANK : stm32g0xx_hal_flash.h
  • OB_USER_DUALBANK_DISABLE : stm32g0xx_hal_flash.h
  • OB_USER_DUALBANK_ENABLE : stm32g0xx_hal_flash.h
  • OB_USER_DUALBANK_SWAP_DISABLE : stm32g0xx_hal_flash.h
  • OB_USER_DUALBANK_SWAP_ENABLE : stm32g0xx_hal_flash.h
  • OB_USER_INPUT_RESET_HOLDER : stm32g0xx_hal_flash.h
  • OB_USER_IWDG_STDBY : stm32g0xx_hal_flash.h
  • OB_USER_IWDG_STOP : stm32g0xx_hal_flash.h
  • OB_USER_IWDG_SW : stm32g0xx_hal_flash.h
  • OB_USER_nBOOT0 : stm32g0xx_hal_flash.h
  • OB_USER_nBOOT1 : stm32g0xx_hal_flash.h
  • OB_USER_nBOOT_SEL : stm32g0xx_hal_flash.h
  • OB_USER_NRST_MODE : stm32g0xx_hal_flash.h
  • OB_USER_nRST_SHDW : stm32g0xx_hal_flash.h
  • OB_USER_nRST_STDBY : stm32g0xx_hal_flash.h
  • OB_USER_nRST_STOP : stm32g0xx_hal_flash.h
  • OB_USER_RAM_PARITY_CHECK : stm32g0xx_hal_flash.h
  • OB_USER_WWDG_SW : stm32g0xx_hal_flash.h
  • OB_WRPAREA_ZONE2_A : stm32g0xx_hal_flash.h
  • OB_WRPAREA_ZONE2_B : stm32g0xx_hal_flash.h
  • OB_WRPAREA_ZONE_A : stm32g0xx_hal_flash.h
  • OB_WRPAREA_ZONE_B : stm32g0xx_hal_flash.h
  • OB_WWDG_HW : stm32g0xx_hal_flash.h
  • OB_WWDG_SW : stm32g0xx_hal_flash.h
  • OCREF_CLEAR_SELECT_Msk : stm32g0xx_ll_tim.h
  • OCREF_CLEAR_SELECT_Pos : stm32g0xx_ll_tim.h
  • OPTIONBYTE_ALL : stm32g0xx_hal_flash.h
  • OPTIONBYTE_PCROP : stm32g0xx_hal_flash.h
  • OPTIONBYTE_RDP : stm32g0xx_hal_flash.h
  • OPTIONBYTE_SEC : stm32g0xx_hal_flash.h
  • OPTIONBYTE_USER : stm32g0xx_hal_flash.h
  • OPTIONBYTE_WRP : stm32g0xx_hal_flash.h
  • OUTPUT_OD : stm32g0xx_hal_gpio.h
  • OUTPUT_PP : stm32g0xx_hal_gpio.h
  • OUTPUT_TYPE : stm32g0xx_hal_gpio.h
  • OUTPUT_TYPE_Pos : stm32g0xx_hal_gpio.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- p -

  • PACKAGE_BASE_ADDRESS : stm32g0xx_ll_utils.h
  • PCD_CLEAR_BULK_EP_DBUF : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32g0xx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32g0xx_hal_pcd.h
  • PCD_DBL_BUF : stm32g0xx_hal_pcd.h
  • PCD_ENDP0 : stm32g0xx_hal_pcd.h
  • PCD_ENDP1 : stm32g0xx_hal_pcd.h
  • PCD_ENDP2 : stm32g0xx_hal_pcd.h
  • PCD_ENDP3 : stm32g0xx_hal_pcd.h
  • PCD_ENDP4 : stm32g0xx_hal_pcd.h
  • PCD_ENDP5 : stm32g0xx_hal_pcd.h
  • PCD_ENDP6 : stm32g0xx_hal_pcd.h
  • PCD_ENDP7 : stm32g0xx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32g0xx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32g0xx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32g0xx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32g0xx_hal_pcd.h
  • PCD_FREE_USER_BUFFER : stm32g0xx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32g0xx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32g0xx_hal_pcd.h
  • PCD_MAX : stm32g0xx_hal_pcd.c
  • PCD_MIN : stm32g0xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32g0xx_hal_pcd.h
  • PCD_PHY_ULPI : stm32g0xx_hal_pcd.h
  • PCD_PHY_UTMI : stm32g0xx_hal_pcd.h
  • PCD_RX_DTOG : stm32g0xx_hal_pcd.h
  • PCD_SET_BULK_EP_DBUF : stm32g0xx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32g0xx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32g0xx_hal_pcd.h
  • PCD_SNG_BUF : stm32g0xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32g0xx_hal_pcd.h
  • PCD_TX_DTOG : stm32g0xx_hal_pcd.h
  • PLL_TIMEOUT_VALUE : stm32g0xx_hal_rcc.c , stm32g0xx_hal_rcc_ex.c
  • PLLSOURCE_NONE : stm32g0xx_hal_rcc.c
  • PMA_BLOCKS : stm32g0xx_hal_hcd.h
  • PREFETCH_ENABLE : stm32g0xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32g0xx_hal_pwr_ex.c
  • PVD_MODE_EVT : stm32g0xx_hal_pwr_ex.c
  • PVD_MODE_IT : stm32g0xx_hal_pwr_ex.c
  • PVD_RISING_EDGE : stm32g0xx_hal_pwr_ex.c
  • PVM_FALLING_EDGE : stm32g0xx_hal_pwr_ex.h
  • PVM_MODE_EVT : stm32g0xx_hal_pwr_ex.h
  • PVM_MODE_IT : stm32g0xx_hal_pwr_ex.h
  • PVM_RISING_EDGE : stm32g0xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVD : stm32g0xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM : stm32g0xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32g0xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM : stm32g0xx_hal_pwr_ex.h
  • PWR_FLAG_FLASH_READY : stm32g0xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32g0xx_hal_pwr.h
  • PWR_FLAG_PVMO_USB : stm32g0xx_hal_pwr.h
  • PWR_FLAG_PVMOUSB : stm32g0xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPF : stm32g0xx_hal_pwr.h
  • PWR_FLAG_REGLPS : stm32g0xx_hal_pwr.h
  • PWR_FLAG_SB : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF1 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF2 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF3 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF4 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF5 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUF6 : stm32g0xx_hal_pwr.h
  • PWR_FLAG_WUFI : stm32g0xx_hal_pwr.h
  • PWR_FLASHPD_LPRUN : stm32g0xx_hal_pwr_ex.h
  • PWR_FLASHPD_LPSLEEP : stm32g0xx_hal_pwr_ex.h
  • PWR_FLASHPD_STOP : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_A : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_B : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_0 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_1 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_10 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_11 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_12 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_13 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_14 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_15 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_2 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_3 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_4 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_6 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_7 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_8 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_9 : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_C : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_D : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_E : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_F : stm32g0xx_hal_pwr_ex.h
  • PWR_GPIO_PIN_NB : stm32g0xx_hal_pwr_ex.c
  • PWR_LOWPOWERMODE_SHUTDOWN : stm32g0xx_hal_pwr.h
  • PWR_LOWPOWERMODE_STANDBY : stm32g0xx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP0 : stm32g0xx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP1 : stm32g0xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32g0xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32g0xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_RISING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_RISING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVD_MODE_NORMAL : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_0 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_1 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_2 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_3 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_4 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_6 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_7 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_0 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_1 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_2 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_3 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_4 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_FALLING_6 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_0 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_1 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_2 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_3 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_4 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_5 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVDLEVEL_RISING_6 : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING_FALLING : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_MODE_NORMAL : stm32g0xx_hal_pwr_ex.h
  • PWR_PVM_USB : stm32g0xx_hal_pwr_ex.h
  • PWR_REGLPF_SETTING_DELAY_6_US : stm32g0xx_hal_pwr_ex.c
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32g0xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32g0xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32g0xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32g0xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32g0xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32g0xx_hal_pwr.h
  • PWR_VOSF_SETTING_DELAY_6_US : stm32g0xx_hal_pwr_ex.c
  • PWR_WAKEUP_PIN1 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN1_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN1_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN2 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN2_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN2_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN3 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN3_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN3_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN4 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN4_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN4_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN5 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN5_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN5_LOW : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN6 : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN6_HIGH : stm32g0xx_hal_pwr.h
  • PWR_WAKEUP_PIN6_LOW : stm32g0xx_hal_pwr.h
  • PWR_WUP_POLARITY_SHIFT : stm32g0xx_hal_pwr.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- r -

  • RCC_ADCCLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLLADC : stm32g0xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_HSI_DIV488 : stm32g0xx_hal_rcc_ex.h
  • RCC_CECCLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_ALL : stm32g0xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32g0xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32g0xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32g0xx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_GPIO : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32g0xx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32g0xx_hal_rcc_ex.h
  • RCC_DBP_TIMEOUT_VALUE : stm32g0xx_hal_rcc.h
  • RCC_FDCANCLKSOURCE_HSE : stm32g0xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_FDCANCLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_FLAG_HSERDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_LSECSSD : stm32g0xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32g0xx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32g0xx_hal_rcc.h
  • RCC_FLAG_PWRRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32g0xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32g0xx_hal_rcc.h
  • RCC_HSE_OFF : stm32g0xx_hal_rcc.h
  • RCC_HSE_ON : stm32g0xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32g0xx_hal_rcc.h
  • RCC_HSI48_ON : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV1 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV128 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV16 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV32 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV64 : stm32g0xx_hal_rcc.h
  • RCC_HSI_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_HSI_OFF : stm32g0xx_hal_rcc.h
  • RCC_HSI_ON : stm32g0xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32g0xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S1CLKSOURCE_EXT : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S1CLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S1CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S2CLKSOURCE_EXT : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S2CLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_I2S2CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32g0xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32g0xx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32g0xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32g0xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32g0xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32g0xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32g0xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32g0xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART2CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART2CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_LPUART2CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSI : stm32g0xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32g0xx_hal_rcc.h
  • RCC_LSE_OFF : stm32g0xx_hal_rcc.h
  • RCC_LSE_ON : stm32g0xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32g0xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32g0xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32g0xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32g0xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32g0xx_hal_rcc.h
  • RCC_LSI_OFF : stm32g0xx_hal_rcc.h
  • RCC_LSI_ON : stm32g0xx_hal_rcc.h
  • RCC_MCO : stm32g0xx_hal_rcc.h
  • RCC_MCO1 : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLPCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLQCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_RTC_WKUP : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_RTCCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO1SOURCE_SYSCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_1 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_1024 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_128 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_16 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_2 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_256 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_32 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_4 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_512 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_64 : stm32g0xx_hal_rcc.h
  • RCC_MCO2DIV_8 : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSE : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSI : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_HSI48 : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_LSE : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_LSI : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_NOCLOCK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLPCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_PLLQCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_RTC_WKUP : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_RTCCLK : stm32g0xx_hal_rcc.h
  • RCC_MCO2SOURCE_SYSCLK : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_1024 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_128 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_16 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_256 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_32 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_512 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_64 : stm32g0xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32g0xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32g0xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CEC : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_FDCAN : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM15 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32g0xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32g0xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32g0xx_hal_rcc.h
  • RCC_PLL_OFF : stm32g0xx_hal_rcc.h
  • RCC_PLL_ON : stm32g0xx_hal_rcc.h
  • RCC_PLL_OSCSOURCE_CONFIG : stm32g0xx_hal_rcc.c
  • RCC_PLLM_DIV1 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV3 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV5 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV6 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV7 : stm32g0xx_hal_rcc.h
  • RCC_PLLM_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV10 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV11 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV12 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV13 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV14 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV15 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV16 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV17 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV18 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV19 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV20 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV21 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV22 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV23 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV24 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV25 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV26 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV27 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV28 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV29 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV3 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV30 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV31 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV32 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV5 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV7 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_PLLP_DIV9 : stm32g0xx_hal_rcc.h
  • RCC_PLLPCLK : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV3 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV5 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV6 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV7 : stm32g0xx_hal_rcc.h
  • RCC_PLLQ_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_PLLQCLK : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV3 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV5 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV6 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV7 : stm32g0xx_hal_rcc.h
  • RCC_PLLR_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_PLLRCLK : stm32g0xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32g0xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32g0xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_ALL : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_IWDG : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_LPWR : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_OBL : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_PIN : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_PWR : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_SW : stm32g0xx_hal_rcc.h
  • RCC_RESET_FLAG_WWDG : stm32g0xx_hal_rcc.h
  • RCC_RNGCLK_DIV1 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLK_DIV2 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLK_DIV4 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLK_DIV8 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_HSI_DIV8 : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_NONE : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32g0xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32g0xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32g0xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NONE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV1 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_LSE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_LSI : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_LSE : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_LSI : stm32g0xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32g0xx_hal_rcc.h
  • RCC_TIM15CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_TIM15CLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_TIM1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_TIM1CLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32g0xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32g0xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32g0xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32g0xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSE : stm32g0xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32g0xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32g0xx_hal_rcc_ex.h
  • RNG_CED_DISABLE : stm32g0xx_hal_rng.h
  • RNG_CED_ENABLE : stm32g0xx_hal_rng.h
  • RNG_FLAG_CECS : stm32g0xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32g0xx_hal_rng.h
  • RNG_FLAG_SECS : stm32g0xx_hal_rng.h
  • RNG_IT_CEI : stm32g0xx_hal_rng.h
  • RNG_IT_DRDY : stm32g0xx_hal_rng.h
  • RNG_IT_SEI : stm32g0xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32g0xx_hal_rng.c
  • RTC_ALARM_A : stm32g0xx_hal_rtc.h
  • RTC_ALARM_B : stm32g0xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32g0xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32g0xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32g0xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32g0xx_hal_rtc.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32g0xx_ll_rtc.c
  • RTC_BKP_DR0 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32g0xx_hal_rtc_ex.h
  • RTC_BKP_NUMBER : stm32g0xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32g0xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32g0xx_hal_rtc_ex.h
  • RTC_CLEAR_ALRAF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_ALRBF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_ITSF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_TSF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_TSOVF : stm32g0xx_hal_rtc.h
  • RTC_CLEAR_WUTF : stm32g0xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32g0xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32g0xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32g0xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32g0xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32g0xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_EVENT : stm32g0xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_TIMESTAMP_EVENT : stm32g0xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32g0xx_hal_rtc.h
  • RTC_FLAG_INT_TAMP3 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP4 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP5 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMP6 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_INT_TAMPALL : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_ITSF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_MASK : stm32g0xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_TAMP1 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP2 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_TAMP3 : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_TAMPALL : stm32g0xx_hal_rtc_ex.h
  • RTC_FLAG_TSF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32g0xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32g0xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32g0xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32g0xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32g0xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32g0xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32g0xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32g0xx_hal_rtc.h
  • RTC_INIT_MASK : stm32g0xx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32g0xx_ll_rtc.c
  • RTC_INT_TAMPER_3 : stm32g0xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_4 : stm32g0xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_5 : stm32g0xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_6 : stm32g0xx_hal_rtc_ex.h
  • RTC_INT_TAMPER_ALL : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_ALRA : stm32g0xx_hal_rtc.h
  • RTC_IT_ALRB : stm32g0xx_hal_rtc.h
  • RTC_IT_INT_TAMP3 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP4 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP5 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMP6 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_INT_TAMPALL : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TAMP1 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TAMP2 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TAMP3 : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TAMPALL : stm32g0xx_hal_rtc_ex.h
  • RTC_IT_TS : stm32g0xx_hal_rtc.h
  • RTC_IT_WUT : stm32g0xx_hal_rtc.h
  • RTC_LL_INIT_MASK : stm32g0xx_ll_rtc.h
  • RTC_LL_RSF_MASK : stm32g0xx_ll_rtc.h
  • RTC_MONTH_APRIL : stm32g0xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32g0xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32g0xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32g0xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32g0xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32g0xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32g0xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32g0xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32g0xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32g0xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32g0xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32g0xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32g0xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32g0xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32g0xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32g0xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32g0xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_ALARMB : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_DISABLE : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_NONE : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_PULLUP_ON : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_TAMPER : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32g0xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32g0xx_hal_rtc.h
  • RTC_RSF_MASK : stm32g0xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32g0xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32g0xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32g0xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32g0xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32g0xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32g0xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32g0xx_ll_rtc.c
  • RTC_TAMPER_1 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_ALL : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32g0xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32g0xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32g0xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32g0xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32g0xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32g0xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32g0xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32g0xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32g0xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32g0xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32g0xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32g0xx_ll_rtc.h
  • RX_FIFO_DEPTH : stm32g0xx_hal_uart_ex.c , stm32g0xx_hal_usart_ex.c , stm32g0xx_hal_smartcard_ex.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- s -

  • SLAVE_ADDR_MSK : stm32g0xx_hal_i2c.c
  • SLAVE_ADDR_SHIFT : stm32g0xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_EOBF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_CR_MASK : stm32g0xx_hal_smartcard.h
  • SMARTCARD_CR_POS : stm32g0xx_hal_smartcard.h
  • SMARTCARD_FIFOMODE_DISABLE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_BUSY : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFNE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFNF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_ISR_MASK : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ISR_POS : stm32g0xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32g0xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFNE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFNF : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32g0xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32g0xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32g0xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32g0xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV1 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV10 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV12 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV128 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV16 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV2 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV256 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV32 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV4 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV6 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV64 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV8 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32g0xx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_STOPBITS_0_5 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32g0xx_hal_smartcard.h
  • SMARTCARD_TC : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32g0xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32g0xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32g0xx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_smartcard_ex.h
  • SMARTCARD_WORDLENGTH_9B : stm32g0xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32g0xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32g0xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32g0xx_hal_smbus.h
  • SMBUS_CHECK_IT_SOURCE : stm32g0xx_hal_smbus.h
  • SMBUS_DUALADDRESS_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_FASTMODEPLUS_I2C1 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C2 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_I2C3 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PA10 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PA9 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB6 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB7 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB8 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FASTMODEPLUS_PB9 : stm32g0xx_hal_smbus_ex.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32g0xx_hal_smbus.h
  • SMBUS_FIRST_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32g0xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32g0xx_hal_smbus.h
  • SMBUS_FMP_NOT_SUPPORTED : stm32g0xx_hal_smbus_ex.h
  • SMBUS_GENERALCALL_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32g0xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32g0xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32g0xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32g0xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32g0xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32g0xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32g0xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32g0xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32g0xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_RX : stm32g0xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32g0xx_hal_smbus.h
  • SMBUS_IT_TX : stm32g0xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32g0xx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_NEXT_FRAME : stm32g0xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32g0xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32g0xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32g0xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32g0xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32g0xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32g0xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32g0xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32g0xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32g0xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32g0xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32g0xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32g0xx_hal_smbus.h
  • SMBUS_SOFTEND_MODE : stm32g0xx_hal_smbus.h
  • SPI_1LINE_RX : stm32g0xx_hal_spi.h
  • SPI_1LINE_TX : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32g0xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32g0xx_hal_spi.h
  • SPI_CHECK_FLAG : stm32g0xx_hal_spi.h
  • SPI_CHECK_IT_SOURCE : stm32g0xx_hal_spi.h
  • SPI_CR1_CLEAR_MASK : stm32g0xx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32g0xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32g0xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32g0xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32g0xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32g0xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32g0xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32g0xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32g0xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32g0xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32g0xx_hal_spi.h
  • SPI_FIFO_SIZE : stm32g0xx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32g0xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32g0xx_hal_spi.h
  • SPI_FLAG_BSY : stm32g0xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32g0xx_hal_spi.h
  • SPI_FLAG_FRE : stm32g0xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32g0xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32g0xx_hal_spi.h
  • SPI_FLAG_MASK : stm32g0xx_hal_spi.h
  • SPI_FLAG_MODF : stm32g0xx_hal_spi.h
  • SPI_FLAG_OVR : stm32g0xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32g0xx_hal_spi.h
  • SPI_FLAG_TXE : stm32g0xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32g0xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32g0xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32g0xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32g0xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32g0xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32g0xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32g0xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32g0xx_hal_spi.h
  • SPI_IT_ERR : stm32g0xx_hal_spi.h
  • SPI_IT_RXNE : stm32g0xx_hal_spi.h
  • SPI_IT_TXE : stm32g0xx_hal_spi.h
  • SPI_MODE_MASTER : stm32g0xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32g0xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32g0xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32g0xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32g0xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32g0xx_hal_spi.h
  • SPI_NSS_SOFT : stm32g0xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32g0xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32g0xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32g0xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32g0xx_hal_spi.h
  • SPI_RESET_CRC : stm32g0xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32g0xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32g0xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32g0xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32g0xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32g0xx_hal_spi.h
  • SRAMCAN_FLE_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLE_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLESA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLS_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLS_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_FLSSA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF0_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF0_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF0SA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF1_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF1_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_RF1SA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TEF_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TEF_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TEFSA : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TFQ_NBR : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TFQ_SIZE : stm32g0xx_hal_fdcan.c
  • SRAMCAN_TFQSA : stm32g0xx_hal_fdcan.c
  • SYSCFG_BOOT_MAINFLASH : stm32g0xx_hal.h
  • SYSCFG_BOOT_SRAM : stm32g0xx_hal.h
  • SYSCFG_BOOT_SYSTEMFLASH : stm32g0xx_hal.h
  • SYSCFG_BREAK_ECC : stm32g0xx_hal.h
  • SYSCFG_BREAK_LOCKUP : stm32g0xx_hal.h
  • SYSCFG_BREAK_PVD : stm32g0xx_hal.h
  • SYSCFG_BREAK_SP : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA1 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA13 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA3 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA5 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PA6 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PB0 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PB1 : stm32g0xx_hal.h
  • SYSCFG_CDEN_PB2 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_I2C1 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_I2C2 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_I2C3 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PA10 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PA9 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32g0xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32g0xx_hal.h
  • SYSCFG_REMAP_PA11 : stm32g0xx_hal.h
  • SYSCFG_REMAP_PA12 : stm32g0xx_hal.h
  • SYSCFG_UCPD1_STROBE : stm32g0xx_hal.h
  • SYSCFG_UCPD2_STROBE : stm32g0xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32g0xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32g0xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32g0xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32g0xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32g0xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32g0xx_hal_cortex.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- t -

  • TEMPSENSOR_CAL1_ADDR : stm32g0xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32g0xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32g0xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32g0xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32g0xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32g0xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32g0xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32g0xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32g0xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK2_AFMODE_BIDIRECTIONAL : stm32g0xx_hal_tim.h
  • TIM_BREAK2_AFMODE_INPUT : stm32g0xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32g0xx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32g0xx_hal_tim.h
  • TIM_BREAK_AFMODE_BIDIRECTIONAL : stm32g0xx_hal_tim.h
  • TIM_BREAK_AFMODE_INPUT : stm32g0xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32g0xx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32g0xx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32g0xx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32g0xx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR : stm32g0xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUT_REARM_TIMEOUT : stm32g0xx_hal_tim_ex.c
  • TIM_BREAKINPUTSOURCE_BKIN : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32g0xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32g0xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32g0xx_hal_tim.h
  • TIM_CALC_DTS : stm32g0xx_ll_tim.h
  • TIM_CCDMAREQUEST_CC : stm32g0xx_hal_tim.h
  • TIM_CCDMAREQUEST_UPDATE : stm32g0xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32g0xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32g0xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32g0xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32g0xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32g0xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_5 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_6 : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_GET : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_SET : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_N_STATE_SET_ALL : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_STATE_GET : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_STATE_SET : stm32g0xx_hal_tim.h
  • TIM_CHANNEL_STATE_SET_ALL : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP1 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP2 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP3 : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32g0xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32g0xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32g0xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32g0xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32g0xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32g0xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR7 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32g0xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32g0xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32g0xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32g0xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32g0xx_hal_tim.h
  • TIM_DMA_CC1 : stm32g0xx_hal_tim.h
  • TIM_DMA_CC2 : stm32g0xx_hal_tim.h
  • TIM_DMA_CC3 : stm32g0xx_hal_tim.h
  • TIM_DMA_CC4 : stm32g0xx_hal_tim.h
  • TIM_DMA_COM : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32g0xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32g0xx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_AF2 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32g0xx_hal_tim.h
  • TIM_DMABASE_DMAR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_OR1 : stm32g0xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32g0xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_SR : stm32g0xx_hal_tim.h
  • TIM_DMABASE_TISEL : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32g0xx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32g0xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32g0xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32g0xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32g0xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32g0xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32g0xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32g0xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32g0xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32g0xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32g0xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32g0xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32g0xx_hal_tim.h
  • TIM_FLAG_COM : stm32g0xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32g0xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32g0xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32g0xx_ll_tim.h
  • TIM_GROUPCH5_NONE : stm32g0xx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32g0xx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32g0xx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32g0xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32g0xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32g0xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32g0xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32g0xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32g0xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32g0xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32g0xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32g0xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32g0xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_IT_BREAK : stm32g0xx_hal_tim.h
  • TIM_IT_CC1 : stm32g0xx_hal_tim.h
  • TIM_IT_CC2 : stm32g0xx_hal_tim.h
  • TIM_IT_CC3 : stm32g0xx_hal_tim.h
  • TIM_IT_CC4 : stm32g0xx_hal_tim.h
  • TIM_IT_COM : stm32g0xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_IT_UPDATE : stm32g0xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32g0xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32g0xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32g0xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32g0xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32g0xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32g0xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32g0xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32g0xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32g0xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32g0xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32g0xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32g0xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32g0xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32g0xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32g0xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32g0xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32g0xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32g0xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32g0xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32g0xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32g0xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32g0xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32g0xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32g0xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32g0xx_hal_tim.h
  • TIM_POSITION_BRK_SOURCE : stm32g0xx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32g0xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32g0xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32g0xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32g0xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32g0xx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32g0xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32g0xx_hal_tim.h
  • TIM_TIM14_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM14_TI1_HSE_32 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM14_TI1_MCO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM14_TI1_MCO2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM14_TI1_RTC : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM2_CH1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI1_TIM3_CH1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM2_CH2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM15_TI2_TIM3_CH2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSE : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSI : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_MCO2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RTC_WAKEUP : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSE_32 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSI48 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI2_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI3_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM1_TI3_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_LSE : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_MCO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_ETR_MCO2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI1_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI2_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI3_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM2_TI3_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI2_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI3_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM3_TI3_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_ETR_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_ETR_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI1_COMP1 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI1_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI2_COMP2 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI2_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI3_COMP3 : stm32g0xx_hal_tim_ex.h
  • TIM_TIM4_TI3_GPIO : stm32g0xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32g0xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32g0xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32g0xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32g0xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32g0xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32g0xx_hal_tim.h
  • TIM_TRGO_RESET : stm32g0xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32g0xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32g0xx_hal_tim.h
  • TIM_TS_ETRF : stm32g0xx_hal_tim.h
  • TIM_TS_ITR0 : stm32g0xx_hal_tim.h
  • TIM_TS_ITR1 : stm32g0xx_hal_tim.h
  • TIM_TS_ITR2 : stm32g0xx_hal_tim.h
  • TIM_TS_ITR3 : stm32g0xx_hal_tim.h
  • TIM_TS_ITR7 : stm32g0xx_hal_tim.h
  • TIM_TS_NONE : stm32g0xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32g0xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32g0xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32g0xx_hal_tim.h
  • TIM_UIFREMAP_DISABLE : stm32g0xx_hal_tim.h
  • TIM_UIFREMAP_ENABLE : stm32g0xx_hal_tim.h
  • TIMEOUT : stm32g0xx_hal_lptim.c
  • TIMEOUT_DAC_CALIBCONFIG : stm32g0xx_hal_dac.c
  • TIMING_CLEAR_MASK : stm32g0xx_hal_i2c.c , stm32g0xx_hal_smbus.c
  • TIMx_AF1_BKINP : stm32g0xx_ll_tim.h
  • TIMx_AF1_ETRSEL : stm32g0xx_ll_tim.h
  • TIMx_OR1_OCREF_CLR : stm32g0xx_hal_tim.c
  • TRIGGER_FALLING : stm32g0xx_hal_gpio.h
  • TRIGGER_MODE : stm32g0xx_hal_gpio.h
  • TRIGGER_MODE_Pos : stm32g0xx_hal_gpio.h
  • TRIGGER_RISING : stm32g0xx_hal_gpio.h
  • TX_FIFO_DEPTH : stm32g0xx_hal_usart_ex.c , stm32g0xx_hal_uart_ex.c , stm32g0xx_hal_smartcard_ex.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- u -

  • UART_ADDRESS_DETECT_4B : stm32g0xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32g0xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32g0xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32g0xx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32g0xx_hal_uart.h
  • UART_BRR_MAX : stm32g0xx_hal_uart.c
  • UART_BRR_MIN : stm32g0xx_hal_uart.c
  • UART_CLEAR_CMF : stm32g0xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32g0xx_hal_uart.h
  • UART_CLEAR_FEF : stm32g0xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32g0xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32g0xx_hal_uart.h
  • UART_CLEAR_NEF : stm32g0xx_hal_uart.h
  • UART_CLEAR_OREF : stm32g0xx_hal_uart.h
  • UART_CLEAR_PEF : stm32g0xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32g0xx_hal_uart.h
  • UART_CLEAR_TCF : stm32g0xx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32g0xx_hal_uart.h
  • UART_CLEAR_WUF : stm32g0xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32g0xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32g0xx_hal_uart.h
  • UART_CR2_ADDRESS_LSB_POS : stm32g0xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32g0xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32g0xx_hal_uart.h
  • UART_DIV_LPUART : stm32g0xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32g0xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32g0xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32g0xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32g0xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32g0xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32g0xx_hal_uart.h
  • UART_FIFOMODE_DISABLE : stm32g0xx_hal_uart_ex.h
  • UART_FIFOMODE_ENABLE : stm32g0xx_hal_uart_ex.h
  • UART_FLAG_ABRE : stm32g0xx_hal_uart.h
  • UART_FLAG_ABRF : stm32g0xx_hal_uart.h
  • UART_FLAG_BUSY : stm32g0xx_hal_uart.h
  • UART_FLAG_CMF : stm32g0xx_hal_uart.h
  • UART_FLAG_CTS : stm32g0xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32g0xx_hal_uart.h
  • UART_FLAG_FE : stm32g0xx_hal_uart.h
  • UART_FLAG_IDLE : stm32g0xx_hal_uart.h
  • UART_FLAG_LBDF : stm32g0xx_hal_uart.h
  • UART_FLAG_NE : stm32g0xx_hal_uart.h
  • UART_FLAG_ORE : stm32g0xx_hal_uart.h
  • UART_FLAG_PE : stm32g0xx_hal_uart.h
  • UART_FLAG_REACK : stm32g0xx_hal_uart.h
  • UART_FLAG_RTOF : stm32g0xx_hal_uart.h
  • UART_FLAG_RWU : stm32g0xx_hal_uart.h
  • UART_FLAG_RXFF : stm32g0xx_hal_uart.h
  • UART_FLAG_RXFNE : stm32g0xx_hal_uart.h
  • UART_FLAG_RXFT : stm32g0xx_hal_uart.h
  • UART_FLAG_RXNE : stm32g0xx_hal_uart.h
  • UART_FLAG_SBKF : stm32g0xx_hal_uart.h
  • UART_FLAG_TC : stm32g0xx_hal_uart.h
  • UART_FLAG_TEACK : stm32g0xx_hal_uart.h
  • UART_FLAG_TXE : stm32g0xx_hal_uart.h
  • UART_FLAG_TXFE : stm32g0xx_hal_uart.h
  • UART_FLAG_TXFNF : stm32g0xx_hal_uart.h
  • UART_FLAG_TXFT : stm32g0xx_hal_uart.h
  • UART_FLAG_WUF : stm32g0xx_hal_uart.h
  • UART_GET_DIV_FACTOR : stm32g0xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32g0xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32g0xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32g0xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32g0xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32g0xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32g0xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32g0xx_hal_uart.h
  • UART_INSTANCE_LOWPOWER : stm32g0xx_hal_uart.h
  • UART_IT_CM : stm32g0xx_hal_uart.h
  • UART_IT_CTS : stm32g0xx_hal_uart.h
  • UART_IT_ERR : stm32g0xx_hal_uart.h
  • UART_IT_FE : stm32g0xx_hal_uart.h
  • UART_IT_IDLE : stm32g0xx_hal_uart.h
  • UART_IT_LBD : stm32g0xx_hal_uart.h
  • UART_IT_MASK : stm32g0xx_hal_uart.h
  • UART_IT_NE : stm32g0xx_hal_uart.h
  • UART_IT_ORE : stm32g0xx_hal_uart.h
  • UART_IT_PE : stm32g0xx_hal_uart.h
  • UART_IT_RTO : stm32g0xx_hal_uart.h
  • UART_IT_RXFF : stm32g0xx_hal_uart.h
  • UART_IT_RXFNE : stm32g0xx_hal_uart.h
  • UART_IT_RXFT : stm32g0xx_hal_uart.h
  • UART_IT_RXNE : stm32g0xx_hal_uart.h
  • UART_IT_TC : stm32g0xx_hal_uart.h
  • UART_IT_TXE : stm32g0xx_hal_uart.h
  • UART_IT_TXFE : stm32g0xx_hal_uart.h
  • UART_IT_TXFNF : stm32g0xx_hal_uart.h
  • UART_IT_TXFT : stm32g0xx_hal_uart.h
  • UART_IT_WUF : stm32g0xx_hal_uart.h
  • UART_LIN_DISABLE : stm32g0xx_hal_uart.h
  • UART_LIN_ENABLE : stm32g0xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32g0xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32g0xx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32g0xx_hal_uart_ex.h
  • UART_MODE_RX : stm32g0xx_hal_uart.h
  • UART_MODE_TX : stm32g0xx_hal_uart.h
  • UART_MODE_TX_RX : stm32g0xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32g0xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32g0xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32g0xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32g0xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32g0xx_hal_uart.h
  • UART_PARITY_EVEN : stm32g0xx_hal_uart.h
  • UART_PARITY_NONE : stm32g0xx_hal_uart.h
  • UART_PARITY_ODD : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32g0xx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32g0xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32g0xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32g0xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32g0xx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_uart_ex.h
  • UART_SENDBREAK_REQUEST : stm32g0xx_hal_uart.h
  • UART_STATE_DISABLE : stm32g0xx_hal_uart.h
  • UART_STATE_ENABLE : stm32g0xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32g0xx_hal_uart.h
  • UART_STOPBITS_1 : stm32g0xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32g0xx_hal_uart.h
  • UART_STOPBITS_2 : stm32g0xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32g0xx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_uart_ex.h
  • UART_WAKEUP_ON_ADDRESS : stm32g0xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32g0xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32g0xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32g0xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32g0xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32g0xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32g0xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32g0xx_hal_uart_ex.h
  • UID_BASE_ADDRESS : stm32g0xx_ll_utils.h
  • USART_BRR_MAX : stm32g0xx_hal_smartcard.c , stm32g0xx_hal_irda.c , stm32g0xx_hal_usart.c
  • USART_BRR_MIN : stm32g0xx_hal_usart.c , stm32g0xx_hal_irda.c , stm32g0xx_hal_smartcard.c
  • USART_CLEAR_FEF : stm32g0xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32g0xx_hal_usart.h
  • USART_CLEAR_NEF : stm32g0xx_hal_usart.h
  • USART_CLEAR_OREF : stm32g0xx_hal_usart.h
  • USART_CLEAR_PEF : stm32g0xx_hal_usart.h
  • USART_CLEAR_RTOF : stm32g0xx_hal_usart.h
  • USART_CLEAR_TCF : stm32g0xx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32g0xx_hal_usart.h
  • USART_CLEAR_UDRF : stm32g0xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32g0xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32g0xx_hal_usart.h
  • USART_CR1_FIELDS : stm32g0xx_hal_smartcard.c , stm32g0xx_hal_uart.c , stm32g0xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32g0xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32g0xx_hal_smartcard.c , stm32g0xx_hal_usart.c
  • USART_CR3_FIELDS : stm32g0xx_hal_usart.c , stm32g0xx_hal_smartcard.c , stm32g0xx_hal_uart.c
  • USART_CR_MASK : stm32g0xx_hal_usart.h
  • USART_CR_POS : stm32g0xx_hal_usart.h
  • USART_DIV_SAMPLING8 : stm32g0xx_hal_usart.h
  • USART_DUMMY_DATA : stm32g0xx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32g0xx_hal_usart_ex.h
  • USART_FIFOMODE_ENABLE : stm32g0xx_hal_usart_ex.h
  • USART_FLAG_BUSY : stm32g0xx_hal_usart.h
  • USART_FLAG_FE : stm32g0xx_hal_usart.h
  • USART_FLAG_IDLE : stm32g0xx_hal_usart.h
  • USART_FLAG_NE : stm32g0xx_hal_usart.h
  • USART_FLAG_ORE : stm32g0xx_hal_usart.h
  • USART_FLAG_PE : stm32g0xx_hal_usart.h
  • USART_FLAG_REACK : stm32g0xx_hal_usart.h
  • USART_FLAG_RTOF : stm32g0xx_hal_usart.h
  • USART_FLAG_RXFF : stm32g0xx_hal_usart.h
  • USART_FLAG_RXFNE : stm32g0xx_hal_usart.h
  • USART_FLAG_RXFT : stm32g0xx_hal_usart.h
  • USART_FLAG_RXNE : stm32g0xx_hal_usart.h
  • USART_FLAG_TC : stm32g0xx_hal_usart.h
  • USART_FLAG_TEACK : stm32g0xx_hal_usart.h
  • USART_FLAG_TXE : stm32g0xx_hal_usart.h
  • USART_FLAG_TXFE : stm32g0xx_hal_usart.h
  • USART_FLAG_TXFNF : stm32g0xx_hal_usart.h
  • USART_FLAG_TXFT : stm32g0xx_hal_usart.h
  • USART_FLAG_UDR : stm32g0xx_hal_usart.h
  • USART_GET_DIV_FACTOR : stm32g0xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32g0xx_hal_usart_ex.h
  • USART_ISR_MASK : stm32g0xx_hal_usart.h
  • USART_ISR_POS : stm32g0xx_hal_usart.h
  • USART_IT_ERR : stm32g0xx_hal_usart.h
  • USART_IT_FE : stm32g0xx_hal_usart.h
  • USART_IT_IDLE : stm32g0xx_hal_usart.h
  • USART_IT_MASK : stm32g0xx_hal_usart.h
  • USART_IT_NE : stm32g0xx_hal_usart.h
  • USART_IT_ORE : stm32g0xx_hal_usart.h
  • USART_IT_PE : stm32g0xx_hal_usart.h
  • USART_IT_RXFF : stm32g0xx_hal_usart.h
  • USART_IT_RXFNE : stm32g0xx_hal_usart.h
  • USART_IT_RXFT : stm32g0xx_hal_usart.h
  • USART_IT_RXNE : stm32g0xx_hal_usart.h
  • USART_IT_TC : stm32g0xx_hal_usart.h
  • USART_IT_TXE : stm32g0xx_hal_usart.h
  • USART_IT_TXFE : stm32g0xx_hal_usart.h
  • USART_IT_TXFNF : stm32g0xx_hal_usart.h
  • USART_IT_TXFT : stm32g0xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32g0xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32g0xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32g0xx_hal_usart_ex.h
  • USART_MODE_RX : stm32g0xx_hal_usart.h
  • USART_MODE_TX : stm32g0xx_hal_usart.h
  • USART_MODE_TX_RX : stm32g0xx_hal_usart.h
  • USART_NSS_HARD : stm32g0xx_hal_usart_ex.h
  • USART_NSS_SOFT : stm32g0xx_hal_usart_ex.h
  • USART_PARITY_EVEN : stm32g0xx_hal_usart.h
  • USART_PARITY_NONE : stm32g0xx_hal_usart.h
  • USART_PARITY_ODD : stm32g0xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32g0xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32g0xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32g0xx_hal_usart.h
  • USART_POLARITY_LOW : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32g0xx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32g0xx_hal_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32g0xx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_usart_ex.h
  • USART_SLAVEMODE_DISABLE : stm32g0xx_hal_usart_ex.h
  • USART_SLAVEMODE_ENABLE : stm32g0xx_hal_usart_ex.h
  • USART_STOPBITS_0_5 : stm32g0xx_hal_usart.h
  • USART_STOPBITS_1 : stm32g0xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32g0xx_hal_usart.h
  • USART_STOPBITS_2 : stm32g0xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32g0xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32g0xx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32g0xx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32g0xx_hal_usart_ex.h
  • USART_WORDLENGTH_7B : stm32g0xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32g0xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32g0xx_hal_usart_ex.h
  • USB_EP0StartXfer : stm32g0xx_hal_pcd.h
  • USB_WAKEUP_EXTI_LINE : stm32g0xx_hal_pcd.h
  • USE_HAL_ADC_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_CEC_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_COMP_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_CRYP_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_CRYP_SUSPEND_RESUME : stm32g0xx_hal_conf.h
  • USE_HAL_DAC_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_FDCAN_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_HCD_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_I2C_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_I2S_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_IRDA_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_LPTIM_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_PCD_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_RNG_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_RTC_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_SMARTCARD_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_SMBUS_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_SPI_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_TIM_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_UART_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_USART_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_HAL_WWDG_REGISTER_CALLBACKS : stm32g0xx_hal_conf.h
  • USE_RTOS : stm32g0xx_hal_conf.h
  • USE_SPI_CRC : stm32g0xx_hal_conf.h
  • UTILS_HSE_FREQUENCY_MAX : stm32g0xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32g0xx_ll_utils.c
  • UTILS_MAX_FREQUENCY : stm32g0xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX : stm32g0xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN : stm32g0xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MAX : stm32g0xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MIN : stm32g0xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_FREQ : stm32g0xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_FREQ : stm32g0xx_ll_utils.c
  • UTILS_SCALE1_LATENCY3_FREQ : stm32g0xx_ll_utils.c
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- v -

  • VDD_VALUE : stm32g0xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32g0xx_hal.c
  • VREFINT_CAL_ADDR : stm32g0xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32g0xx_ll_adc.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Globals

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- w -

  • WWDG_EWI_DISABLE : stm32g0xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32g0xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32g0xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32g0xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32g0xx_hal_wwdg.h
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal.h File Reference

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stm32g0xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32g0xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | SYSCFG_BOOT_MAINFLASH 0x00000000U
#define | SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0
#define | SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)
#define | SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL
#define | SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL
#define | SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL
#define | SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL
#define | SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN
#define | SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN
#define | SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN
#define | SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN
#define | SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN
#define | SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN
#define | SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN
#define | SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN
#define | SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP
#define | SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP
#define | HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)
#define | HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0)
#define | HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1)
#define | HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U
#define | HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ
#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
Fast mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP
#define | SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP
#define | SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
Fast mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | SYSCFG_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE
#define | SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE
#define | HAL_SYSCFG_ITLINE0 0x00000000U
#define | HAL_SYSCFG_ITLINE1 0x00000001U
#define | HAL_SYSCFG_ITLINE2 0x00000002U
#define | HAL_SYSCFG_ITLINE3 0x00000003U
#define | HAL_SYSCFG_ITLINE4 0x00000004U
#define | HAL_SYSCFG_ITLINE5 0x00000005U
#define | HAL_SYSCFG_ITLINE6 0x00000006U
#define | HAL_SYSCFG_ITLINE7 0x00000007U
#define | HAL_SYSCFG_ITLINE8 0x00000008U
#define | HAL_SYSCFG_ITLINE9 0x00000009U
#define | HAL_SYSCFG_ITLINE10 0x0000000AU
#define | HAL_SYSCFG_ITLINE11 0x0000000BU
#define | HAL_SYSCFG_ITLINE12 0x0000000CU
#define | HAL_SYSCFG_ITLINE13 0x0000000DU
#define | HAL_SYSCFG_ITLINE14 0x0000000EU
#define | HAL_SYSCFG_ITLINE15 0x0000000FU
#define | HAL_SYSCFG_ITLINE16 0x00000010U
#define | HAL_SYSCFG_ITLINE17 0x00000011U
#define | HAL_SYSCFG_ITLINE18 0x00000012U
#define | HAL_SYSCFG_ITLINE19 0x00000013U
#define | HAL_SYSCFG_ITLINE20 0x00000014U
#define | HAL_SYSCFG_ITLINE21 0x00000015U
#define | HAL_SYSCFG_ITLINE22 0x00000016U
#define | HAL_SYSCFG_ITLINE23 0x00000017U
#define | HAL_SYSCFG_ITLINE24 0x00000018U
#define | HAL_SYSCFG_ITLINE25 0x00000019U
#define | HAL_SYSCFG_ITLINE26 0x0000001AU
#define | HAL_SYSCFG_ITLINE27 0x0000001BU
#define | HAL_SYSCFG_ITLINE28 0x0000001CU
#define | HAL_SYSCFG_ITLINE29 0x0000001DU
#define | HAL_SYSCFG_ITLINE30 0x0000001EU
#define | HAL_SYSCFG_ITLINE31 0x0000001FU
#define | HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)
#define | HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)
#define | HAL_ITLINE_PVMOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT)
#define | HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC)
#define | HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER)
#define | HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC)
#define | HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)
#define | HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)
#define | HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)
#define | HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)
#define | HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)
#define | HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)
#define | HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)
#define | HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)
#define | HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)
#define | HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)
#define | HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)
#define | HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)
#define | HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)
#define | HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)
#define | HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)
#define | HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)
#define | HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)
#define | HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)
#define | HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)
#define | HAL_ITLINE_UCPD1 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1)
#define | HAL_ITLINE_UCPD2 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2)
#define | HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB)
#define | HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)
#define | HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)
#define | HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)
#define | HAL_ITLINE_DMAMUX1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1)
#define | HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)
#define | HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)
#define | HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)
#define | HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)
#define | HAL_ITLINE_DMA2_CH1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1)
#define | HAL_ITLINE_DMA2_CH2 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2)
#define | HAL_ITLINE_DMA2_CH3 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)
#define | HAL_ITLINE_DMA2_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)
#define | HAL_ITLINE_DMA2_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)
#define | HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)
#define | HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)
#define | HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)
#define | HAL_ITLINE_COMP3 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3)
#define | HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)
#define | HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)
#define | HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)
#define | HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)
#define | HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)
#define | HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)
#define | HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)
#define | HAL_ITLINE_TIM4 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB)
#define | HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)
#define | HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)
#define | HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB)
#define | HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)
#define | HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB)
#define | HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)
#define | HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)
#define | HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)
#define | HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0)
#define | HAL_ITLINE_FDCAN2_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0)
#define | HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)
#define | HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1)
#define | HAL_ITLINE_FDCAN2_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1)
#define | HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)
#define | HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)
#define | HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB)
#define | HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)
#define | HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)
#define | HAL_ITLINE_SPI3 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3)
#define | HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)
#define | HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)
#define | HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB)
#define | HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)
#define | HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)
#define | HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB)
#define | HAL_ITLINE_USART5 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)
#define | HAL_ITLINE_USART6 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)
#define | HAL_ITLINE_CEC ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)
#define | HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG)
#define | HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES)
#define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
Freeze and Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
#define | __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
ISR wrapper check.
#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
Return the boot mode as configured by user.
#define | __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
SYSCFG Break ECC lock.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
SYSCFG Break Cortex-M0+ Lockup lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
SYSCFG Break SRAM PARITY lock Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17.
#define | __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
Parity check on RAM disable macro.
#define | __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
Set the PEF bit to clear the SRAM Parity Error Flag.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)
#define | __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__)
Clamping Diode on specific pins enable/disable macros.
#define | __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__)
#define | __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU))
ISR wrapper check.
#define | __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)
selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
#define | __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U)
#define | __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__)
IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register.
#define | __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
Return the IROut Polarity mode as configured by user.
#define | __HAL_SYSCFG_BREAK_ENABLE(__BREAK__)
Break input to TIM1/15/16/17 capability enable/disable macros.
#define | __HAL_SYSCFG_BREAK_DISABLE(__BREAK__)
#define | IS_SYSCFG_BREAK_CONFIG(__CONFIG__)
#define | IS_SYSCFG_CLAMPINGDIODE(__PIN__)
#define | IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)
#define | IS_HAL_SYSCFG_IRDA_POL_SEL(SEL)
#define | IS_SYSCFG_DBATT_CONFIG(__CONFIG__)
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)
#define | IS_HAL_REMAP_PIN(RMP)
#define | IS_TICKFREQ(FREQ)

Enumerations

enum | HAL_TickFreqTypeDef { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ }

Functions

HAL_StatusTypeDef | HAL_Init (void)
Configure the Flash prefetch and the Instruction cache, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32g0xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (HAL_TickFreqTypeDef Freq)
Set new tick Freq.
HAL_TickFreqTypeDef | HAL_GetTickFreq (void)
return tick frequency.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Returns first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Returns second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Returns third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOAnalogSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOAnalogSwitchBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableRemap (uint32_t PinRemap)
Enable the remap on PA11_PA12.
void | HAL_SYSCFG_DisableRemap (uint32_t PinRemap)
Disable the remap on PA11_PA12.
void | HAL_SYSCFG_EnableClampingDiode (uint32_t PinConfig)
Enable Clamping Diode on specified IO.
void | HAL_SYSCFG_DisableClampingDiode (uint32_t PinConfig)
Disable Clamping Diode on specified IO.
void | HAL_SYSCFG_StrobeDBattpinsConfig (uint32_t ConfigDeadBattery)
Strobe configuration of GPIO depending on UCPDx dead battery settings.

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio
HAL_TickFreqTypeDef uwTickFreq

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_adc.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_adc.h File Reference

Header file of ADC HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_ll_adc.h"
#include "stm32g0xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_OversamplingTypeDef
ADC group regular oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...
struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET (0x00000000UL)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001UL)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004UL)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100UL)
#define | HAL_ADC_STATE_REG_EOC (0x00000200UL)
#define | HAL_ADC_STATE_REG_OVR (0x00000400UL)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000UL)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
#define | HAL_ADC_STATE_AWD1 (0x00010000UL)
#define | HAL_ADC_STATE_AWD2 (0x00020000UL)
#define | HAL_ADC_STATE_AWD3 (0x00040000UL)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)
#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)
#define | ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define | ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
#define | ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
#define | ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
#define | ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
#define | ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
#define | ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
#define | ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
#define | ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
#define | ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
#define | ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
#define | ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
#define | ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)
#define | ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
#define | ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
#define | ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
#define | ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)
#define | ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)
#define | ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)
#define | ADC_SCAN_DISABLE (0x00000000UL)
#define | ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD)
#define | ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT)
#define | ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR)
#define | ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */
#define | ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */
#define | ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4)
#define | ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
#define | ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
#define | ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
#define | ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
#define | ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)
#define | ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV (ADC_ISR_EOS)
#define | ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
#define | ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)
#define | ADC_RANK_CHANNEL_NUMBER (0x00000001U)
#define | ADC_RANK_NONE (0x00000002U)
#define | ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
#define | ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
#define | ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
#define | ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
#define | ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
#define | ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
#define | ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
#define | ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
#define | ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1)
#define | ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2)
#define | ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5)
#define | ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5)
#define | ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5)
#define | ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)
#define | ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5)
#define | ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5)
#define | ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5)
#define | ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5)
#define | ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
#define | ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
#define | ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
#define | ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
#define | ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
#define | ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
#define | ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
#define | ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
#define | ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
#define | ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
#define | ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
#define | ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
#define | ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
#define | ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
#define | ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
#define | ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
#define | ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
#define | ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
#define | ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
#define | ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
#define | ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)
#define | ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)
#define | ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
#define | ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
#define | ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)
#define | ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN)
#define | ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)
#define | ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)
#define | ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)
#define | ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)
#define | ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)
#define | ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)
#define | ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)
#define | ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)
#define | ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)
#define | ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH)
#define | ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW)
#define | ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT (ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT (ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT (ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT (ADC_FLAG_OVR)
#define | ADC_AWD_EVENT ADC_AWD1_EVENT
#define | ADC_IT_RDY ADC_IER_ADRDYIE
#define | ADC_IT_CCRDY ADC_IER_CCRDYIE
#define | ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | ADC_IT_EOC ADC_IER_EOCIE
#define | ADC_IT_EOS ADC_IER_EOSIE
#define | ADC_IT_OVR ADC_IER_OVRIE
#define | ADC_IT_AWD1 ADC_IER_AWD1IE
#define | ADC_IT_AWD2 ADC_IER_AWD2IE
#define | ADC_IT_AWD3 ADC_IER_AWD3IE
#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_CCRDY ADC_ISR_CCRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_GET_RESOLUTION(__HANDLE__) (LL_ADC_GetResolution((__HANDLE__)->Instance))
Return resolution bits in CFGR1 register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U)
Enable ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR1_AUTOOFF(_AUTOOFF_) ((_AUTOOFF_) << 15U)
Enable the ADC auto off mode.
#define | ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U)
Enable the ADC auto delay mode.
#define | ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
Enable ADC continuous conversion mode.
#define | ADC_CFGR1_OVERRUN(_OVERRUN_MODE_)
Enable ADC overrun mode.
#define | ADC_SCAN_SEQ_MODE(_SCAN_MODE_)
Set ADC scan mode with differentiation of sequencer setting fixed or configurable.
#define | ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U)
Enable the ADC DMA continuous request.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
Shift the AWD threshold in function of the selected ADC resolution.
#define | IS_ADC_CLOCKPRESCALER(ADC_CLOCK)
#define | IS_ADC_RESOLUTION(RESOLUTION)
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
#define | IS_ADC_EXTTRIG_EDGE(EDGE)
#define | IS_ADC_EXTTRIG(REGTRIG)
#define | IS_ADC_EOC_SELECTION(EOC_SELECTION)
#define | IS_ADC_OVERRUN(OVR)
#define | IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK)
#define | IS_ADC_REGULAR_RANK(RANK)
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG)
#define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
#define | IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ)
#define | IS_ADC_EVENT_TYPE(EVENT)
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))
#define | ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
#define | ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable ADC interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear the specified ADC flag.
#define | __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define | __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define | __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define | __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.
typedef void(* | pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.

Enumerations

enum HAL_ADC_CallbackIDTypeDef {
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U,
HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, HAL_ADC_MSPINIT_CB_ID = 0x09U,
HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
}
HAL ADC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.

Detailed Description

Header file of ADC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_adc.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_adc_ex.h File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_adc_ex.h File Reference

Header file of ADC HAL extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
#define | ADC_IS_INDEPENDENT(__HANDLE__) (SET)
Check whether or not ADC is independent.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_OVERSAMPLING_RATIO(__RATIO__)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
__weak void | HAL_ADCEx_ChannelConfigReadyCallback (ADC_HandleTypeDef *hadc)
ADC channel configuration ready callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.

Detailed Description

Header file of ADC HAL extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_adc_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cec.h File Reference

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stm32g0xx_hal_cec.h File Reference

Header file of CEC HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CEC_InitTypeDef
CEC Init Structure definition. More...
struct | __CEC_HandleTypeDef
CEC handle Structure definition. More...

Defines

#define | HAL_CEC_STATE_RESET ((uint32_t)0x00000000)
#define | HAL_CEC_STATE_READY ((uint32_t)0x00000020)
#define | HAL_CEC_STATE_BUSY ((uint32_t)0x00000024)
#define | HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022)
#define | HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021)
#define | HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)
#define | HAL_CEC_STATE_ERROR ((uint32_t)0x00000050)
#define | HAL_CEC_ERROR_NONE (uint32_t) 0x0000U
#define | HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
#define | HAL_CEC_ERROR_BRE CEC_ISR_BRE
#define | HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
#define | HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
#define | HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
#define | HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
#define | HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
#define | HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
#define | HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
#define | HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U)
#define | CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define | CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define | CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define | CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define | CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define | CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define | CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define | CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
#define | CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define | CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
#define | CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define | CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
#define | CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
#define | CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define | CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
#define | CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define | CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
#define | CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define | CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
#define | CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define | CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
#define | CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
#define | CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
#define | CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define | CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define | CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define | CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define | CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define | CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define | CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define | CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define | CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define | CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define | CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define | CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define | CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define | CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define | CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define | CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
#define | CEC_IT_TXACKE CEC_IER_TXACKEIE
#define | CEC_IT_TXERR CEC_IER_TXERRIE
#define | CEC_IT_TXUDR CEC_IER_TXUDRIE
#define | CEC_IT_TXEND CEC_IER_TXENDIE
#define | CEC_IT_TXBR CEC_IER_TXBRIE
#define | CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define | CEC_IT_RXACKE CEC_IER_RXACKEIE
#define | CEC_IT_LBPE CEC_IER_LBPEIE
#define | CEC_IT_SBPE CEC_IER_SBPEIE
#define | CEC_IT_BRE CEC_IER_BREIE
#define | CEC_IT_RXOVR CEC_IER_RXOVRIE
#define | CEC_IT_RXEND CEC_IER_RXENDIE
#define | CEC_IT_RXBR CEC_IER_RXBRIE
#define | CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define | CEC_FLAG_TXERR CEC_ISR_TXERR
#define | CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define | CEC_FLAG_TXEND CEC_ISR_TXEND
#define | CEC_FLAG_TXBR CEC_ISR_TXBR
#define | CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define | CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define | CEC_FLAG_LBPE CEC_ISR_LBPE
#define | CEC_FLAG_SBPE CEC_ISR_SBPE
#define | CEC_FLAG_BRE CEC_ISR_BRE
#define | CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define | CEC_FLAG_RXEND CEC_ISR_RXEND
#define | CEC_FLAG_RXBR CEC_ISR_RXBR
#define | CEC_ISR_ALL_ERROR
#define | CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
#define | CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
#define | __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__)
Reset CEC handle gstate & RxState.
#define | __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
Checks whether or not the specified CEC interrupt flag is set.
#define | __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
Clears the interrupt or status flag when raised (write at 1)
#define | __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enables the specified CEC interrupt.
#define | __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disables the specified CEC interrupt.
#define | __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
Checks whether or not the specified CEC interrupt is enabled.
#define | __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
Enables the CEC device.
#define | __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
Disables the CEC device.
#define | __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
Set Transmission Start flag.
#define | __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
Set Transmission End flag.
#define | __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
Get Transmission Start flag.
#define | __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
Get Transmission End flag.
#define | __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
Clear OAR register.
#define | __HAL_CEC_SET_OAR(__HANDLE__, __ADDRESS__)
Set OAR register (without resetting previously set address in case of multi-address mode) To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.
#define | IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define | IS_CEC_TOLERANCE(__RXTOL__)
#define | IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define | IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define | IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define | IS_CEC_SFTOP(__SFTOP__)
#define | IS_CEC_LISTENING_MODE(__MODE__)
#define | IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
Check CEC message size.
#define | IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
Check CEC device Own Address Register (OAR) setting.
#define | IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
Check CEC initiator or destination logical address setting.

Typedefs

typedef uint32_t | HAL_CEC_StateTypeDef
HAL CEC State definition.
typedef struct __CEC_HandleTypeDef | CEC_HandleTypeDef
CEC handle Structure definition.
typedef void(* | pCEC_CallbackTypeDef )(CEC_HandleTypeDef *hcec)
HAL CEC Callback pointer definition.
typedef void(* | pCEC_RxCallbackTypeDef )(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)

Enumerations

enum HAL_CEC_CallbackIDTypeDef {
HAL_CEC_TX_CPLT_CB_ID = 0x00U, HAL_CEC_RX_CPLT_CB_ID = 0x01U, HAL_CEC_ERROR_CB_ID = 0x02U, HAL_CEC_MSPINIT_CB_ID = 0x03U,
HAL_CEC_MSPDEINIT_CB_ID = 0x04U
}
HAL CEC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_RegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback)
Register a User CEC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
Unregister an CEC Callback CEC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_RegisterRxCpltCallback (CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
Register CEC RX complete Callback To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterRxCpltCallback (CEC_HandleTypeDef *hcec)
UnRegister CEC RX complete Callback CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, const uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (const CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (const CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (const CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

Header file of CEC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_cec.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_comp.h File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_comp.h File Reference

Header file of COMP HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_ll_exti.h"

Go to the source code of this file.

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | __COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK (0x10U)
HAL COMP state machine: HAL COMP states definition.
#define | HAL_COMP_ERROR_NONE (0x00UL)
#define | HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)
#define | COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)
#define | COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2)
#define | COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL)
#define | COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT)
#define | COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2)
#define | COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT)
#define | COMP_WINDOWOUTPUT_BOTH (0x00000001UL)
#define | COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)
#define | COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO3 (COMP_CSR_INMSEL_3 )
#define | COMP_HYSTERESIS_NONE (0x00000000UL)
#define | COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)
#define | COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | COMP_BLANKINGSRC_TIM1_OC4 (COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_2)
#define | COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKING_3)
#define | COMP_BLANKINGSRC_TIM15_OC2 (COMP_CSR_BLANKING_4)
#define | COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
#define | COMP_TRIGGERMODE_NONE (0x00000000UL)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)
Reset COMP handle state.
#define | COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
Check whether the specified comparator is locked.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line rising flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI rising flag.
#define | __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line falling flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI falling flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line rising flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI rising flag.
#define | __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line falling flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI falling flag.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP3 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP3 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
Generate a software interrupt on the COMP3 EXTI line.
#define | __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
Enable the COMP3 EXTI line in event mode.
#define | __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
Disable the COMP3 EXTI line in event mode.
#define | __HAL_COMP_COMP3_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP3)
Check whether the COMP3 EXTI line rising flag is set.
#define | __HAL_COMP_COMP3_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP3)
Clear the COMP3 EXTI rising flag.
#define | __HAL_COMP_COMP3_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP3)
Check whether the COMP3 EXTI line falling flag is set.
#define | __HAL_COMP_COMP3_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP3)
Clear the COMP3 EXTI falling flag.
#define | COMP_WINDOWMODE_COMP2 0x00001000U
#define | COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17)
#define | COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18)
#define | COMP_EXTI_LINE_COMP3 (EXTI_IMR1_IM20)
#define | COMP_EXTI_IT (0x00000001UL)
#define | COMP_EXTI_EVENT (0x00000002UL)
#define | COMP_EXTI_RISING (0x00000010UL)
#define | COMP_EXTI_FALLING (0x00000020UL)
#define | COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.
#define | IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__)
#define | IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)
#define | IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Typedefs

typedef struct __COMP_HandleTypeDef | COMP_HandleTypeDef
COMP Handle Structure definition.
typedef void(* | pCOMP_CallbackTypeDef )(COMP_HandleTypeDef *hcomp)
HAL COMP Callback pointer definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00U, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01U, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02U, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}
enum | HAL_COMP_CallbackIDTypeDef { HAL_COMP_TRIGGER_CB_ID = 0x00U, HAL_COMP_MSPINIT_CB_ID = 0x01U, HAL_COMP_MSPDEINIT_CB_ID = 0x02U }
HAL COMP Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

Header file of COMP HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_comp.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cortex.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32g0xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | SYSTICK_CLKSOURCE_HCLK 0x00000004U
#define | MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define | MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define | MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)

Functions

void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
uint32_t | HAL_NVIC_GetPriority (IRQn_Type IRQn)
Get the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_Disable (void)
Disable the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_cortex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_crc.h File Reference

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stm32g0xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_crc_ex.h"

Go to the source code of this file.

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Defines

#define | DEFAULT_CRC32_POLY 0x04C11DB7U
#define | DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
#define | CRC_POLYLENGTH_32B 0x00000000U
#define | CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | CRC_POLYLENGTH_7B CRC_CR_POLYSIZE
#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U
#define | CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U
#define | CRC_INPUTDATA_FORMAT_BYTES 0x00000001U
#define | CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U
#define | CRC_INPUTDATA_FORMAT_WORDS 0x00000003U
#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store data in the Independent Data (ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the data stored in the Independent Data (ID) register.
#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_crc.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_crc_ex.h File Reference

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stm32g0xx_hal_crc_ex.h File Reference

Header file of CRC HAL extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | CRC_INPUTDATA_INVERSION_NONE 0x00000000U
#define | CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0
#define | CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1
#define | CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN
#define | CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U
#define | CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT
#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.
#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Header file of CRC HAL extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_crc_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cryp.h File Reference

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stm32g0xx_hal_cryp.h File Reference

Header file of CRYP HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_cryp_ex.h"

Go to the source code of this file.

Data Structures

struct | CRYP_ConfigTypeDef
CRYP Init Structure definition. More...
struct | __CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Defines

#define | HAL_CRYP_ERROR_NONE 0x00000000U
#define | HAL_CRYP_ERROR_WRITE 0x00000001U
#define | HAL_CRYP_ERROR_READ 0x00000002U
#define | HAL_CRYP_ERROR_DMA 0x00000004U
#define | HAL_CRYP_ERROR_BUSY 0x00000008U
#define | HAL_CRYP_ERROR_TIMEOUT 0x00000010U
#define | HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U
#define | HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U
#define | HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)
#define | CRYP_DATAWIDTHUNIT_WORD 0x00000000U
#define | CRYP_DATAWIDTHUNIT_BYTE 0x00000001U
#define | CRYP_HEADERWIDTHUNIT_WORD 0x00000000U
#define | CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U
#define | CRYP_AES_ECB 0x00000000U
#define | CRYP_AES_CBC AES_CR_CHMOD_0
#define | CRYP_AES_CTR AES_CR_CHMOD_1
#define | CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)
#define | CRYP_AES_CCM AES_CR_CHMOD_2
#define | CRYP_KEYSIZE_128B 0x00000000U
#define | CRYP_KEYSIZE_256B AES_CR_KEYSIZE
#define | CRYP_DATATYPE_32B 0x00000000U
#define | CRYP_DATATYPE_16B AES_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B AES_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B AES_CR_DATATYPE
#define | CRYP_IT_CCFIE AES_CR_CCFIE
#define | CRYP_IT_ERRIE AES_CR_ERRIE
#define | CRYP_IT_WRERR AES_SR_WRERR
#define | CRYP_IT_RDERR AES_SR_RDERR
#define | CRYP_IT_CCF AES_SR_CCF
#define | CRYP_FLAG_BUSY AES_SR_BUSY
#define | CRYP_FLAG_WRERR AES_SR_WRERR
#define | CRYP_FLAG_RDERR AES_SR_RDERR
#define | CRYP_FLAG_CCF AES_SR_CCF
#define | CRYP_CCF_CLEAR AES_CR_CCFC
#define | CRYP_ERR_CLEAR AES_CR_ERRC
#define | CRYP_KEYIVCONFIG_ALWAYS 0x00000000U
#define | CRYP_KEYIVCONFIG_ONCE 0x00000001U
#define | __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__)
Reset CRYP handle state.
#define | __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
Enable/Disable the CRYP peripheral.
#define | __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
#define | CRYP_FLAG_MASK 0x0000001FU
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#define | __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
Clear the CRYP pending status flag.
#define | __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt source is enabled or not.
#define | __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.
#define | IS_CRYP_ALGORITHM(ALGORITHM)
#define | IS_CRYP_KEYSIZE(KEYSIZE)
#define | IS_CRYP_DATATYPE(DATATYPE)
#define | IS_CRYP_INIT(CONFIG)
#define | IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)

Typedefs

typedef struct __CRYP_HandleTypeDef | CRYP_HandleTypeDef
CRYP handle Structure definition.
typedef void(* | pCRYP_CallbackTypeDef )(CRYP_HandleTypeDef *hcryp)

Enumerations

enum | HAL_CRYP_STATETypeDef { HAL_CRYP_STATE_RESET = 0x00U, HAL_CRYP_STATE_READY = 0x01U, HAL_CRYP_STATE_BUSY = 0x02U, HAL_CRYP_STATE_SUSPENDED = 0x03U }
CRYP State Structure definition. More...
enum | HAL_SuspendTypeDef { HAL_CRYP_SUSPEND_NONE = 0x00U, HAL_CRYP_SUSPEND = 0x01U }
HAL CRYP mode suspend definitions. More...
enum HAL_CRYP_CallbackIDTypeDef {
HAL_CRYP_MSPINIT_CB_ID = 0x00U, HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U,
HAL_CRYP_ERROR_CB_ID = 0x04U
}

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callback is redirected to the weak predefined callback.
void | HAL_CRYP_ProcessSuspend (CRYP_HandleTypeDef *hcryp)
Request CRYP processing suspension when in interruption mode.
HAL_StatusTypeDef | HAL_CRYP_Suspend (CRYP_HandleTypeDef *hcryp)
CRYP processing suspension and peripheral internal parameters storage.
HAL_StatusTypeDef | HAL_CRYP_Resume (CRYP_HandleTypeDef *hcryp)
CRYP processing resumption.
HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.

Detailed Description

Header file of CRYP HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_cryp.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cryp_ex.h File Reference

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Functions
stm32g0xx_hal_cryp_ex.h File Reference

Header file of CRYPEx HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.
void | HAL_CRYPEx_EnableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES enable key derivation functions.
void | HAL_CRYPEx_DisableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES disable key derivation functions.

Detailed Description

Header file of CRYPEx HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_cryp_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dac.h File Reference

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stm32g0xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_dac_ex.h"

Go to the source code of this file.

Data Structures

struct | __DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Defines

#define | HAL_DAC_ERROR_NONE 0x00U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
#define | HAL_DAC_ERROR_DMA 0x04U
#define | HAL_DAC_ERROR_TIMEOUT 0x08U
#define | HAL_DAC_ERROR_INVALID_CALLBACK 0x10U
#define | DAC_TRIGGER_NONE 0x00000000UL
#define | DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1)
#define | DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
#define | DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
#define | DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
#define | DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define | DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
#define | DAC_CHANNEL_1 0x00000000U
#define | DAC_CHANNEL_2 0x00000010U
#define | DAC_ALIGN_12B_R 0x00000000U
#define | DAC_ALIGN_12B_L 0x00000004U
#define | DAC_ALIGN_8B_R 0x00000008U
#define | DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
#define | DAC_CHIPCONNECT_DISABLE (0x00000000UL)
#define | DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0)
#define | DAC_TRIMMING_FACTORY (0x00000000UL)
#define | DAC_TRIMMING_USER (0x00000001UL)
#define | DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define | DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)

Typedefs

typedef struct __DAC_HandleTypeDef | DAC_HandleTypeDef
DAC handle Structure definition.
typedef void(* | pDAC_CallbackTypeDef )(DAC_HandleTypeDef *hdac)
HAL DAC Callback pointer definition.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_DAC_CallbackIDTypeDef {
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, HAL_DAC_CH1_ERROR_ID = 0x02U, HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U,
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, HAL_DAC_CH2_ERROR_ID = 0x06U, HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U,
HAL_DAC_MSPINIT_CB_ID = 0x08U, HAL_DAC_MSPDEINIT_CB_ID = 0x09U, HAL_DAC_ALL_CB_ID = 0x0AU
}
HAL DAC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Detailed Description

Header file of DAC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_dac.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dac_ex.h File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_dac_ex.h File Reference

Header file of DAC HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DAC_LFSRUNMASK_BIT0 0x00000000UL
#define | DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 0x00000000UL
#define | DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Detailed Description

Header file of DAC HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_dac_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dma.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_ll_dma.h"
#include "stm32g0xx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE 0x00000000U
#define | HAL_DMA_ERROR_TE 0x00000001U
#define | HAL_DMA_ERROR_NO_XFER 0x00000004U
#define | HAL_DMA_ERROR_TIMEOUT 0x00000020U
#define | HAL_DMA_ERROR_PARAM 0x00000040U
#define | HAL_DMA_ERROR_BUSY 0x00000080U
#define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
#define | HAL_DMA_ERROR_SYNC 0x00000200U
#define | HAL_DMA_ERROR_REQGEN 0x00000400U
#define | DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM
#define | DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0
#define | DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1
#define | DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2
#define | DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3
#define | DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1
#define | DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN
#define | DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT
#define | DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1
#define | DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2
#define | DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX
#define | DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX
#define | DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX
#define | DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX
#define | DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX
#define | DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX
#define | DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX
#define | DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX
#define | DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX
#define | DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX
#define | DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1
#define | DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2
#define | DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3
#define | DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4
#define | DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM
#define | DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP
#define | DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1
#define | DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2
#define | DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3
#define | DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4
#define | DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG
#define | DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP
#define | DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1
#define | DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2
#define | DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3
#define | DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4
#define | DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG
#define | DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP
#define | DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP
#define | DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP
#define | DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1
#define | DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2
#define | DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM
#define | DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP
#define | DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1
#define | DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM
#define | DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP
#define | DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1
#define | DMA_REQUEST_TIM17_COM LL_DMAMUX_REQ_TIM17_COM
#define | DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP
#define | DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX
#define | DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX
#define | DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX
#define | DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX
#define | DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX
#define | DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX
#define | DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX
#define | DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX
#define | DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX
#define | DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX
#define | DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX
#define | DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX
#define | DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX
#define | DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX
#define | DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX
#define | DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX
#define | DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX
#define | DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX
#define | DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1
#define | DMA_REQUEST_TIM4_CH2 LL_DMAMUX_REQ_TIM4_CH2
#define | DMA_REQUEST_TIM4_CH3 LL_DMAMUX_REQ_TIM4_CH3
#define | DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4
#define | DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG
#define | DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP
#define | DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX
#define | DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX
#define | DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX
#define | DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX
#define | DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ
#define | DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY
#define | DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH
#define | DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY
#define | DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT
#define | DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT
#define | DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT
#define | DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT
#define | DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE
#define | DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD
#define | DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD
#define | DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE
#define | DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD
#define | DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD
#define | DMA_NORMAL LL_DMA_MODE_NORMAL
#define | DMA_CIRCULAR LL_DMA_MODE_CIRCULAR
#define | DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW
#define | DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM
#define | DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH
#define | DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH
#define | DMA_IT_TC DMA_CCR_TCIE
#define | DMA_IT_HT DMA_CCR_HTIE
#define | DMA_IT_TE DMA_CCR_TEIE
#define | DMA_FLAG_GI1 DMA_ISR_GIF1
#define | DMA_FLAG_TC1 DMA_ISR_TCIF1
#define | DMA_FLAG_HT1 DMA_ISR_HTIF1
#define | DMA_FLAG_TE1 DMA_ISR_TEIF1
#define | DMA_FLAG_GI2 DMA_ISR_GIF2
#define | DMA_FLAG_TC2 DMA_ISR_TCIF2
#define | DMA_FLAG_HT2 DMA_ISR_HTIF2
#define | DMA_FLAG_TE2 DMA_ISR_TEIF2
#define | DMA_FLAG_GI3 DMA_ISR_GIF3
#define | DMA_FLAG_TC3 DMA_ISR_TCIF3
#define | DMA_FLAG_HT3 DMA_ISR_HTIF3
#define | DMA_FLAG_TE3 DMA_ISR_TEIF3
#define | DMA_FLAG_GI4 DMA_ISR_GIF4
#define | DMA_FLAG_TC4 DMA_ISR_TCIF4
#define | DMA_FLAG_HT4 DMA_ISR_HTIF4
#define | DMA_FLAG_TE4 DMA_ISR_TEIF4
#define | DMA_FLAG_GI5 DMA_ISR_GIF5
#define | DMA_FLAG_TC5 DMA_ISR_TCIF5
#define | DMA_FLAG_HT5 DMA_ISR_HTIF5
#define | DMA_FLAG_TE5 DMA_ISR_TEIF5
#define | DMA_FLAG_GI6 DMA_ISR_GIF6
#define | DMA_FLAG_TC6 DMA_ISR_TCIF6
#define | DMA_FLAG_HT6 DMA_ISR_HTIF6
#define | DMA_FLAG_TE6 DMA_ISR_TEIF6
#define | DMA_FLAG_GI7 DMA_ISR_GIF7
#define | DMA_FLAG_TC7 DMA_ISR_TCIF7
#define | DMA_FLAG_HT7 DMA_ISR_HTIF7
#define | DMA_FLAG_TE7 DMA_ISR_TEIF7
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Channel pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enable the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Check whether the specified DMA Channel interrupt is enabled or disabled.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Returns the number of remaining data units in the current DMA Channel transfer.
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04U
}
HAL DMA Callback ID structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA handle state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_dma.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dma_ex.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32g0xx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_ll_dmamux.h"

Go to the source code of this file.

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMAMUX Synchronization configuration structure definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...

Defines

#define | HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0
#define | HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1
#define | HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2
#define | HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3
#define | HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4
#define | HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5
#define | HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6
#define | HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7
#define | HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8
#define | HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9
#define | HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10
#define | HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11
#define | HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12
#define | HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13
#define | HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14
#define | HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT LL_DMAMUX_SYNC_DMAMUX_CH2
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT
#define | HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT
#define | HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC
#define | HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC
#define | HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT
#define | HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING
#define | HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING
#define | HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING
#define | HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0
#define | HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1
#define | HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2
#define | HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3
#define | HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4
#define | HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5
#define | HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6
#define | HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7
#define | HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8
#define | HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9
#define | HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10
#define | HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11
#define | HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12
#define | HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13
#define | HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14
#define | HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH2
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3
#define | HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT
#define | HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT
#define | HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC
#define | HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC
#define | HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT
#define | HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING
#define | HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING
#define | HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
#define | IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_dma_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_exti.h File Reference

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stm32g0xx_hal_exti.h File Reference

Header file of EXTI HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | EXTI_HandleTypeDef
EXTI Handle structure definition. More...
struct | EXTI_ConfigTypeDef
EXTI Configuration structure definition. More...

Defines

#define | EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
#define | EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
#define | EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
#define | EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
#define | EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
#define | EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
#define | EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
#define | EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
#define | EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
#define | EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
#define | EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
#define | EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
#define | EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
#define | EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
#define | EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
#define | EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
#define | EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
#define | EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
#define | EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u)
#define | EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13u)
#define | EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
#define | EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u)
#define | EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
#define | EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#define | EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#define | EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#define | EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
#define | EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
#define | EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#define | EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
#define | EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
#define | EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu)
#define | EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u)
#define | EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u)
#define | EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u)
#define | EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
#define | EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
#define | EXTI_MODE_NONE 0x00000000u
#define | EXTI_MODE_INTERRUPT 0x00000001u
#define | EXTI_MODE_EVENT 0x00000002u
#define | EXTI_TRIGGER_NONE 0x00000000u
#define | EXTI_TRIGGER_RISING 0x00000001u
#define | EXTI_TRIGGER_FALLING 0x00000002u
#define | EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
#define | EXTI_GPIOA 0x00000000u
#define | EXTI_GPIOB 0x00000001u
#define | EXTI_GPIOC 0x00000002u
#define | EXTI_GPIOD 0x00000003u
#define | EXTI_GPIOE 0x00000004u
#define | EXTI_GPIOF 0x00000005u
#define | EXTI_PROPERTY_SHIFT 24u
EXTI Line property definition.
#define | EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define | EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
#define | EXTI_REG_SHIFT 16u
EXTI Register and bit usage.
#define | EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define | EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define | EXTI_PIN_MASK 0x0000001Fu
#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
EXTI Mask for interrupt & event mode.
#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
EXTI Mask for trigger possibilities.
#define | EXTI_LINE_NB 37uL
EXTI Line number.
#define | IS_EXTI_LINE(__EXTI_LINE__)
#define | IS_EXTI_MODE(__MODE__)
#define | IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define | IS_EXTI_PENDING_EDGE(__EXTI_LINE__)
#define | IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#define | IS_EXTI_GPIO_PORT(__PORT__)
#define | IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)

Enumerations

enum | EXTI_CallbackIDTypeDef { HAL_EXTI_COMMON_CB_ID = 0x00U, HAL_EXTI_RISING_CB_ID = 0x01U, HAL_EXTI_FALLING_CB_ID = 0x02U }

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicaated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.
void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

Header file of EXTI HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_exti.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_fdcan.h File Reference

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  • STM32G0xx_HAL_Driver
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stm32g0xx_hal_fdcan.h File Reference

Header file of FDCAN HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FDCAN_InitTypeDef
FDCAN Init structure definition. More...
struct | FDCAN_FilterTypeDef
FDCAN filter structure definition. More...
struct | FDCAN_TxHeaderTypeDef
FDCAN Tx header structure definition. More...
struct | FDCAN_RxHeaderTypeDef
FDCAN Rx header structure definition. More...
struct | FDCAN_TxEventFifoTypeDef
FDCAN Tx event FIFO structure definition. More...
struct | FDCAN_HpMsgStatusTypeDef
FDCAN High Priority Message Status structure definition. More...
struct | FDCAN_ProtocolStatusTypeDef
FDCAN Protocol Status structure definition. More...
struct | FDCAN_ErrorCountersTypeDef
FDCAN Error Counters structure definition. More...
struct | FDCAN_MsgRamAddressTypeDef
FDCAN Message RAM blocks. More...
struct | __FDCAN_HandleTypeDef
FDCAN handle structure definition. More...

Defines

#define | HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U)
#define | HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U)
#define | HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U)
#define | HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U)
#define | HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U)
#define | HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U)
#define | HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U)
#define | HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U)
#define | HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U)
#define | HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U)
#define | HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO
#define | HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI
#define | HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA
#define | HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED
#define | HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA
#define | HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)
#define | FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U)
#define | FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)
#define | FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE))
#define | FDCAN_MODE_NORMAL ((uint32_t)0x00000000U)
#define | FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U)
#define | FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U)
#define | FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U)
#define | FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U)
#define | FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U)
#define | FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U)
#define | FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U)
#define | FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U)
#define | FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U)
#define | FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U)
#define | FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U)
#define | FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U)
#define | FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U)
#define | FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U)
#define | FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU)
#define | FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU)
#define | FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU)
#define | FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU)
#define | FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU)
#define | FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU)
#define | FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U)
#define | FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM)
#define | FDCAN_STANDARD_ID ((uint32_t)0x00000000U)
#define | FDCAN_EXTENDED_ID ((uint32_t)0x40000000U)
#define | FDCAN_DATA_FRAME ((uint32_t)0x00000000U)
#define | FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)
#define | FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U)
#define | FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U)
#define | FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U)
#define | FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U)
#define | FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U)
#define | FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U)
#define | FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U)
#define | FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U)
#define | FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U)
#define | FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U)
#define | FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U)
#define | FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U)
#define | FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U)
#define | FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U)
#define | FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U)
#define | FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U)
#define | FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U)
#define | FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U)
#define | FDCAN_BRS_OFF ((uint32_t)0x00000000U)
#define | FDCAN_BRS_ON ((uint32_t)0x00100000U)
#define | FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U)
#define | FDCAN_FD_CAN ((uint32_t)0x00200000U)
#define | FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U)
#define | FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U)
#define | FDCAN_FILTER_RANGE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_DUAL ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_MASK ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U)
#define | FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REJECT ((uint32_t)0x00000003U)
#define | FDCAN_FILTER_HP ((uint32_t)0x00000004U)
#define | FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U)
#define | FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U)
#define | FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U)
#define | FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U)
#define | FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U)
#define | FDCAN_RX_FIFO0 ((uint32_t)0x00000040U)
#define | FDCAN_RX_FIFO1 ((uint32_t)0x00000041U)
#define | FDCAN_TX_EVENT ((uint32_t)0x00400000U)
#define | FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U)
#define | FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U)
#define | FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U)
#define | FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U)
#define | FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U)
#define | FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U)
#define | FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U)
#define | FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U)
#define | FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U)
#define | FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U)
#define | FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U)
#define | FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U)
#define | FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U)
#define | FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U)
#define | FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U)
#define | FDCAN_COM_STATE_RX ((uint32_t)0x00000010U)
#define | FDCAN_COM_STATE_TX ((uint32_t)0x00000018U)
#define | FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U)
#define | FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U)
#define | FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U)
#define | FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U)
#define | FDCAN_REJECT ((uint32_t)0x00000002U)
#define | FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U)
#define | FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U)
#define | FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U)
#define | FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U)
#define | FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U)
#define | FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U)
#define | FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U)
#define | FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U)
#define | FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U)
#define | FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U)
#define | FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U)
#define | FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U)
#define | FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U)
#define | FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U)
#define | FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U)
#define | FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U)
#define | FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U)
#define | FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U)
#define | FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U)
#define | FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U)
#define | FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U)
#define | FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U)
#define | FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U)
#define | FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U)
#define | FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U)
#define | FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU)
#define | FDCAN_ILS_MASK ((uint32_t)0x0000007FU)
#define | FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC
#define | FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF
#define | FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE
#define | FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM
#define | FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL
#define | FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF
#define | FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN
#define | FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L
#define | FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F
#define | FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N
#define | FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L
#define | FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F
#define | FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N
#define | FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF
#define | FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO
#define | FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP
#define | FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW
#define | FDCAN_FLAG_BUS_OFF FDCAN_IR_BO
#define | FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI
#define | FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA
#define | FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED
#define | FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA
#define | FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW
#define | FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO
#define | FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE
#define | FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE
#define | FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE
#define | FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME
#define | FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE
#define | FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE
#define | FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE
#define | FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE
#define | FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE
#define | FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE
#define | FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE
#define | FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE
#define | FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE
#define | FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE
#define | FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE
#define | FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE
#define | FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE
#define | FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE
#define | FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE
#define | FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE
#define | FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE
#define | FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE
#define | FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE
#define | FDCAN_IT_BUS_OFF FDCAN_IE_BOE
#define | FDCAN_IT_LIST_RX_FIFO0
#define | FDCAN_IT_LIST_RX_FIFO1
#define | FDCAN_IT_LIST_SMSG
#define | FDCAN_IT_LIST_TX_FIFO_ERROR
#define | FDCAN_IT_LIST_MISC
#define | FDCAN_IT_LIST_BIT_LINE_ERROR
#define | FDCAN_IT_LIST_PROTOCOL_ERROR
#define | FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0
#define | FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1
#define | FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG
#define | FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR
#define | FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC
#define | FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR
#define | FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR
#define | __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__)
Reset FDCAN handle state.
#define | __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
Enable the specified FDCAN interrupts.
#define | __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
Disable the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
Check whether the specified FDCAN interrupt is set or not.
#define | __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
Clear the specified FDCAN interrupts.
#define | __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
Check whether the specified FDCAN flag is set or not.
#define | __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR) = (__FLAG__)
Clear the specified FDCAN flags.
#define | __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
Check if the specified FDCAN interrupt source is enabled or disabled.
#define | IS_FDCAN_FRAME_FORMAT(FORMAT)
#define | IS_FDCAN_MODE(MODE)
#define | IS_FDCAN_CKDIV(CKDIV)
#define | IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
#define | IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
#define | IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
#define | IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
#define | IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
#define | IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
#define | IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
#define | IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
#define | IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
#define | IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
#define | IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE)
#define | IS_FDCAN_ID_TYPE(ID_TYPE)
#define | IS_FDCAN_FILTER_CFG(CONFIG)
#define | IS_FDCAN_TX_LOCATION(LOCATION)
#define | IS_FDCAN_TX_LOCATION_LIST(LOCATION)
#define | IS_FDCAN_RX_FIFO(FIFO)
#define | IS_FDCAN_RX_FIFO_MODE(MODE)
#define | IS_FDCAN_STD_FILTER_TYPE(TYPE)
#define | IS_FDCAN_EXT_FILTER_TYPE(TYPE)
#define | IS_FDCAN_FRAME_TYPE(TYPE)
#define | IS_FDCAN_DLC(DLC)
#define | IS_FDCAN_ESI(ESI)
#define | IS_FDCAN_BRS(BRS)
#define | IS_FDCAN_FDF(FDF)
#define | IS_FDCAN_EFC(EFC)
#define | IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
#define | IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
#define | IS_FDCAN_NON_MATCHING(DESTINATION)
#define | IS_FDCAN_REJECT_REMOTE(DESTINATION)
#define | IS_FDCAN_IT_LINE(IT_LINE)
#define | IS_FDCAN_TIMESTAMP(OPERATION)
#define | IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER)
#define | IS_FDCAN_TIMEOUT(OPERATION)
#define | FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Typedefs

typedef struct
__FDCAN_HandleTypeDef 		FDCAN_HandleTypeDef
FDCAN handle structure definition.
typedef void(* | pFDCAN_CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan)
HAL FDCAN Callback pointer definition.
typedef void(* | pFDCAN_TxEventFifoCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
typedef void(* | pFDCAN_RxFifo0CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
typedef void(* | pFDCAN_RxFifo1CallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
typedef void(* | pFDCAN_TxBufferCompleteCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_TxBufferAbortCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
typedef void(* | pFDCAN_ErrorStatusCallbackTypeDef )(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)

Enumerations

enum | HAL_FDCAN_StateTypeDef { HAL_FDCAN_STATE_RESET = 0x00U, HAL_FDCAN_STATE_READY = 0x01U, HAL_FDCAN_STATE_BUSY = 0x02U, HAL_FDCAN_STATE_ERROR = 0x03U }
HAL State structures definition. More...
enum HAL_FDCAN_CallbackIDTypeDef {
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U,
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, HAL_FDCAN_MSPINIT_CB_ID = 0x05U, HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U
}
HAL FDCAN common Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback)
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.
HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.

Detailed Description

Header file of FDCAN HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_fdcan.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_flash.h File Reference

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Data Structures | Defines | Functions | Variables
stm32g0xx_hal_flash.h File Reference

Header file of FLASH HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_flash_ex.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | FLASH_KEY1 0x45670123U
#define | FLASH_KEY2 0xCDEF89ABU
#define | FLASH_OPTKEY1 0x08192A3BU
#define | FLASH_OPTKEY2 0x4C5D6E7FU
#define | FLASH_LATENCY_0 0x00000000UL
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_1
#define | FLASH_FLAG_EOP ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_EOP_Pos)
#define | FLASH_FLAG_OPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPERR_Pos)
#define | FLASH_FLAG_PROGERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PROGERR_Pos)
#define | FLASH_FLAG_WRPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_WRPERR_Pos)
#define | FLASH_FLAG_PGAERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGAERR_Pos)
#define | FLASH_FLAG_SIZERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_SIZERR_Pos)
#define | FLASH_FLAG_PGSERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGSERR_Pos)
#define | FLASH_FLAG_MISERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_MISERR_Pos)
#define | FLASH_FLAG_FASTERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_FASTERR_Pos)
#define | FLASH_FLAG_RDERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_RDERR_Pos)
#define | FLASH_FLAG_OPTVERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPTVERR_Pos)
#define | FLASH_FLAG_BSY1 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY1_Pos)
#define | FLASH_FLAG_BSY2 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY2_Pos)
#define | FLASH_FLAG_BSY FLASH_FLAG_BSY1
#define | FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos)
#define | FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos)
#define | FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos)
#define | FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos)
#define | FLASH_FLAG_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCC_Pos)
#define | FLASH_FLAG_ECCD2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCD_Pos)
#define | FLASH_FLAG_ECCC FLASH_FLAG_ECCC1
#define | FLASH_FLAG_ECCD FLASH_FLAG_ECCD1
#define | FLASH_IT_EOP ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_EOPIE_Pos)
#define | FLASH_IT_OPERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_ERRIE_Pos)
#define | FLASH_IT_RDERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_RDERRIE_Pos)
#define | FLASH_IT_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCCIE_Pos)
#define | FLASH_IT_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCCIE_Pos)
#define | FLASH_IT_ECCC FLASH_IT_ECCC1
#define | HAL_FLASH_ERROR_NONE 0x00000000U
#define | HAL_FLASH_ERROR_OP FLASH_SR_OPERR
#define | HAL_FLASH_ERROR_PROG FLASH_SR_PROGERR
#define | HAL_FLASH_ERROR_WRP FLASH_SR_WRPERR
#define | HAL_FLASH_ERROR_PGA FLASH_SR_PGAERR
#define | HAL_FLASH_ERROR_SIZ FLASH_SR_SIZERR
#define | HAL_FLASH_ERROR_PGS FLASH_SR_PGSERR
#define | HAL_FLASH_ERROR_MIS FLASH_SR_MISERR
#define | HAL_FLASH_ERROR_FAST FLASH_SR_FASTERR
#define | HAL_FLASH_ERROR_RD FLASH_SR_RDERR
#define | HAL_FLASH_ERROR_OPTV FLASH_SR_OPTVERR
#define | HAL_FLASH_ERROR_ECCD FLASH_ECCR_ECCD
#define | FLASH_TYPEERASE_PAGES FLASH_CR_PER
#define | FLASH_TYPEERASE_MASS FLASH_CR_MER1
#define | FLASH_BANK_1 FLASH_CR_MER1
#define | FLASH_BANK_2 FLASH_CR_MER2
#define | FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG
#define | FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG
#define | OPTIONBYTE_WRP 0x00000001U
#define | OPTIONBYTE_RDP 0x00000002U
#define | OPTIONBYTE_USER 0x00000004U
#define | OPTIONBYTE_PCROP 0x00000008U
#define | OPTIONBYTE_SEC 0x00000010U
#define | OPTIONBYTE_ALL
#define | OB_WRPAREA_ZONE_A 0x00000001U
#define | OB_WRPAREA_ZONE_B 0x00000002U
#define | OB_WRPAREA_ZONE2_A 0x00000004U
#define | OB_WRPAREA_ZONE2_B 0x00000008U
#define | OB_RDP_LEVEL_0 0x000000AAU
#define | OB_RDP_LEVEL_1 0x000000BBU
#define | OB_RDP_LEVEL_2 0x000000CCU
#define | OB_USER_BOR_EN FLASH_OPTR_BOR_EN
#define | OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV)
#define | OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP
#define | OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY
#define | OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW
#define | OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW
#define | OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP
#define | OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY
#define | OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW
#define | OB_USER_BANK_SWAP FLASH_OPTR_nSWAP_BANK
#define | OB_USER_DUAL_BANK FLASH_OPTR_DUAL_BANK
#define | OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK
#define | OB_USER_nBOOT_SEL FLASH_OPTR_nBOOT_SEL
#define | OB_USER_nBOOT1 FLASH_OPTR_nBOOT1
#define | OB_USER_nBOOT0 FLASH_OPTR_nBOOT0
#define | OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE
#define | OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN
#define | OB_USER_ALL
#define | OB_BOR_DISABLE 0x00000000U
#define | OB_BOR_ENABLE FLASH_OPTR_BOR_EN
#define | OB_BOR_LEVEL_FALLING_0 0x00000000U
#define | OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0
#define | OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1
#define | OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1)
#define | OB_BOR_LEVEL_RISING_0 0x00000000U
#define | OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0
#define | OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1
#define | OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1)
#define | OB_STOP_RST 0x00000000U
#define | OB_STOP_NORST FLASH_OPTR_nRST_STOP
#define | OB_STANDBY_RST 0x00000000U
#define | OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY
#define | OB_SHUTDOWN_RST 0x00000000U
#define | OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW
#define | OB_IWDG_HW 0x00000000U
#define | OB_IWDG_SW FLASH_OPTR_IWDG_SW
#define | OB_IWDG_STOP_FREEZE 0x00000000U
#define | OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP
#define | OB_IWDG_STDBY_FREEZE 0x00000000U
#define | OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY
#define | OB_WWDG_HW 0x00000000U
#define | OB_WWDG_SW FLASH_OPTR_WWDG_SW
#define | OB_USER_DUALBANK_SWAP_ENABLE 0x00000000U
#define | OB_USER_DUALBANK_SWAP_DISABLE FLASH_OPTR_nSWAP_BANK
#define | OB_USER_DUALBANK_DISABLE 0x00000000U
#define | OB_USER_DUALBANK_ENABLE FLASH_OPTR_DUAL_BANK
#define | OB_SRAM_PARITY_ENABLE 0x00000000U
#define | OB_SRAM_PARITY_DISABLE FLASH_OPTR_RAM_PARITY_CHECK
#define | OB_BOOT0_FROM_PIN 0x00000000U
#define | OB_BOOT0_FROM_OB FLASH_OPTR_nBOOT_SEL
#define | OB_BOOT1_SRAM 0x00000000U
#define | OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1
#define | OB_nBOOT0_RESET 0x00000000U
#define | OB_nBOOT0_SET FLASH_OPTR_nBOOT0
#define | OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0
#define | OB_RESET_MODE_GPIO FLASH_OPTR_NRST_MODE_1
#define | OB_RESET_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE
#define | OB_IRH_ENABLE 0x00000000U
#define | OB_IRH_DISABLE FLASH_OPTR_IRHEN
#define | OB_PCROP_ZONE_A 0x00000001U
#define | OB_PCROP_ZONE_B 0x00000002U
#define | OB_PCROP_ZONE2_A 0x00000004U
#define | OB_PCROP_ZONE2_B 0x00000008U
#define | OB_PCROP_RDP_NOT_ERASE 0x00000000U
#define | OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP
#define | OB_BOOT_ENTRY_FORCED_NONE 0x00000000U
#define | OB_BOOT_ENTRY_FORCED_FLASH FLASH_SECR_BOOT_LOCK
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Disable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Reset the FLASH instruction Cache.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Check whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the FLASH pending flags.
#define | FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
#define | OB_DUAL_BANK_BASE (FLASH_R_BASE + 0x20U)
#define | FLASH_SALES_TYPE_Pos (24U)
#define | FLASH_SALES_TYPE (0x3UL << FLASH_SALES_TYPE_Pos)
#define | FLASH_SALES_TYPE_0 (0x1UL << FLASH_SALES_TYPE_Pos)
#define | FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos)
#define | FLASH_SALES_VALUE ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE))
#define | OB_DUAL_BANK_VALUE ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK))
#define | FLASH_BANK_NB
#define | FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U))
#define | FLASH_PAGE_SIZE 0x00000800U
#define | FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of pages per bank */
#define | FLASH_TIMEOUT_VALUE 1000U
#define | FLASH_TYPENONE 0x00000000U
#define | FLASH_SR_ERRORS
#define | FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD)
#define | FLASH_FLAG_REG_POS 16u
#define | FLASH_FLAG_SR_ID 1u
#define | FLASH_FLAG_CR_ID 2u
#define | FLASH_FLAG_ECCR1_ID 4u
#define | FLASH_FLAG_ECCR2_ID 8u
#define | IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__)
#define | IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__)
#define | IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB)
#define | IS_FLASH_BANK(__BANK__)
#define | IS_FLASH_TYPEERASE(__VALUE__)
#define | IS_FLASH_TYPEPROGRAM(__VALUE__)
#define | IS_OPTIONBYTE(__VALUE__)
#define | IS_OB_WRPAREA(__VALUE__)
#define | IS_OB_RDP_LEVEL(__LEVEL__)
#define | IS_OB_USER_TYPE(__TYPE__)
#define | IS_OB_USER_CONFIG(__TYPE__, __CONFIG__) ((~(__TYPE__) & (__CONFIG__)) == 0x00U)
#define | IS_OB_PCROP_CONFIG(__CONFIG__)
#define | IS_OB_SEC_BOOT_LOCK(__VALUE__)
#define | IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U))
#define | IS_FLASH_LATENCY(__LATENCY__)

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_flash.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_flash_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
  • Inc
Defines | Functions
stm32g0xx_hal_flash_ex.h File Reference

Header file of FLASH HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | FLASH_PROG_NOT_EMPTY 0x00000000u
#define | FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY
#define | FLASH_PCROP_GRANULARITY_OFFSET 9u
#define | FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)
#define | IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
void | HAL_FLASHEx_EnableDebugger (void)
Enable Debugger.
void | HAL_FLASHEx_DisableDebugger (void)
Disable Debugger.
uint32_t | HAL_FLASHEx_FlashEmptyCheck (void)
Flash Empty check.
void | HAL_FLASHEx_ForceFlashEmpty (uint32_t FlashEmpty)
Force Empty check value.
void | HAL_FLASHEx_EnableSecMemProtection (uint32_t Banks)
Securable memory area protection enable.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
void | FLASH_PageErase (uint32_t Banks, uint32_t Page)
Erase the specified FLASH memory page.

Detailed Description

Header file of FLASH HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_flash_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_gpio.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32g0xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT MODE_INPUT
#define | GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)
#define | GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)
#define | GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)
#define | GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)
#define | GPIO_MODE_ANALOG MODE_ANALOG
#define | GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)
#define | GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)
#define | GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)
#define | GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)
#define | GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)
#define | GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)
#define | GPIO_SPEED_FREQ_LOW 0x00000000u
#define | GPIO_SPEED_FREQ_MEDIUM 0x00000001u
#define | GPIO_SPEED_FREQ_HIGH 0x00000002u
#define | GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u
#define | GPIO_NOPULL 0x00000000u
#define | GPIO_PULLUP 0x00000001u
#define | GPIO_PULLDOWN 0x00000002u
#define | __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is rising edge asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__))
Clear the EXTI line rising pending bits.
#define | __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is falling edge asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__))
Clear the EXTI line falling pending bits.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
Clear the EXTI line pending flags.
#define | GPIO_MODE_Pos 0u
#define | GPIO_MODE (0x3uL << GPIO_MODE_Pos)
#define | MODE_INPUT (0x0uL << GPIO_MODE_Pos)
#define | MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
#define | MODE_AF (0x2uL << GPIO_MODE_Pos)
#define | MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
#define | OUTPUT_TYPE_Pos 4u
#define | OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
#define | OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
#define | OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
#define | EXTI_MODE_Pos 16u
#define | EXTI_MODE (0x3uL << EXTI_MODE_Pos)
#define | EXTI_IT (0x1uL << EXTI_MODE_Pos)
#define | EXTI_EVT (0x2uL << EXTI_MODE_Pos)
#define | TRIGGER_MODE_Pos 20u
#define | TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
#define | TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
#define | TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Rising_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.
__weak void | HAL_GPIO_EXTI_Falling_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_gpio.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_gpio_ex.h File Reference

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Defines
stm32g0xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_CEC ((uint8_t)0x00)
AF 0 selection.
#define | GPIO_AF0_CRS ((uint8_t)0x00)
#define | GPIO_AF0_EVENTOUT ((uint8_t)0x00)
#define | GPIO_AF0_IR ((uint8_t)0x00)
#define | GPIO_AF0_LPTIM1 ((uint8_t)0x00)
#define | GPIO_AF0_MCO ((uint8_t)0x00)
#define | GPIO_AF0_OSC ((uint8_t)0x00)
#define | GPIO_AF0_OSC32 ((uint8_t)0x00)
#define | GPIO_AF0_SWJ ((uint8_t)0x00)
#define | GPIO_AF0_SPI1 ((uint8_t)0x00)
#define | GPIO_AF0_SPI2 ((uint8_t)0x00)
#define | GPIO_AF0_TIM14 ((uint8_t)0x00)
#define | GPIO_AF0_TIM15 ((uint8_t)0x00)
#define | GPIO_AF0_TIM16 ((uint8_t)0x00)
#define | GPIO_AF0_TIM17 ((uint8_t)0x00)
#define | GPIO_AF0_USART1 ((uint8_t)0x00)
#define | GPIO_AF0_USART2 ((uint8_t)0x00)
#define | GPIO_AF0_USART3 ((uint8_t)0x00)
#define | GPIO_AF0_USART4 ((uint8_t)0x00)
#define | GPIO_AF0_UCPD1 ((uint8_t)0x00)
#define | GPIO_AF0_UCPD2 ((uint8_t)0x00)
#define | GPIO_AF1_CEC ((uint8_t)0x01)
AF 1 selection.
#define | GPIO_AF1_EVENTOUT ((uint8_t)0x01)
#define | GPIO_AF1_IR ((uint8_t)0x01)
#define | GPIO_AF1_LPTIM2 ((uint8_t)0x01)
#define | GPIO_AF1_LPUART1 ((uint8_t)0x01)
#define | GPIO_AF1_LPUART2 ((uint8_t)0x01)
#define | GPIO_AF1_OSC ((uint8_t)0x01)
#define | GPIO_AF1_SPI1 ((uint8_t)0x01)
#define | GPIO_AF1_SPI2 ((uint8_t)0x01)
#define | GPIO_AF1_TIM1 ((uint8_t)0x01)
#define | GPIO_AF1_TIM3 ((uint8_t)0x01)
#define | GPIO_AF1_USART1 ((uint8_t)0x01)
#define | GPIO_AF1_USART2 ((uint8_t)0x01)
#define | GPIO_AF1_USART4 ((uint8_t)0x01)
#define | GPIO_AF1_UCPD1 ((uint8_t)0x01)
#define | GPIO_AF1_UCPD2 ((uint8_t)0x01)
#define | GPIO_AF2_LPTIM1 ((uint8_t)0x02)
AF 2 selection.
#define | GPIO_AF2_LPTIM2 ((uint8_t)0x02)
#define | GPIO_AF2_TIM1 ((uint8_t)0x02)
#define | GPIO_AF2_TIM2 ((uint8_t)0x02)
#define | GPIO_AF2_TIM4 ((uint8_t)0x02)
#define | GPIO_AF2_TIM14 ((uint8_t)0x02)
#define | GPIO_AF2_TIM15 ((uint8_t)0x02)
#define | GPIO_AF2_TIM16 ((uint8_t)0x02)
#define | GPIO_AF2_TIM17 ((uint8_t)0x02)
#define | GPIO_AF2_USB ((uint8_t)0x02)
#define | GPIO_AF3_FDCAN1 ((uint8_t)0x03)
AF 3 selection.
#define | GPIO_AF3_FDCAN2 ((uint8_t)0x03)
#define | GPIO_AF3_LPUART2 ((uint8_t)0x03)
#define | GPIO_AF3_USART5 ((uint8_t)0x03)
#define | GPIO_AF3_USART6 ((uint8_t)0x03)
#define | GPIO_AF3_MCO2 ((uint8_t)0x03)
#define | GPIO_AF4_CRS ((uint8_t)0x04)
AF 4 selection.
#define | GPIO_AF4_SPI2 ((uint8_t)0x04)
#define | GPIO_AF4_SPI3 ((uint8_t)0x04)
#define | GPIO_AF4_TIM14 ((uint8_t)0x04)
#define | GPIO_AF4_TIM15 ((uint8_t)0x04)
#define | GPIO_AF4_USART1 ((uint8_t)0x04)
#define | GPIO_AF4_USART3 ((uint8_t)0x04)
#define | GPIO_AF4_USART4 ((uint8_t)0x04)
#define | GPIO_AF4_USART6 ((uint8_t)0x04)
#define | GPIO_AF4_UCPD1 ((uint8_t)0x04)
#define | GPIO_AF4_UCPD2 ((uint8_t)0x04)
#define | GPIO_AF5_LPTIM1 ((uint8_t)0x05)
AF 5 selection.
#define | GPIO_AF5_LPTIM2 ((uint8_t)0x05)
#define | GPIO_AF5_SPI1 ((uint8_t)0x05)
#define | GPIO_AF5_SPI2 ((uint8_t)0x05)
#define | GPIO_AF5_TIM1 ((uint8_t)0x05)
#define | GPIO_AF5_TIM15 ((uint8_t)0x05)
#define | GPIO_AF5_TIM16 ((uint8_t)0x05)
#define | GPIO_AF5_TIM17 ((uint8_t)0x05)
#define | GPIO_AF5_USART3 ((uint8_t)0x05)
#define | GPIO_AF6_I2C1 ((uint8_t)0x06)
AF 6 selection.
#define | GPIO_AF6_I2C2 ((uint8_t)0x06)
#define | GPIO_AF6_I2C3 ((uint8_t)0x06)
#define | GPIO_AF6_LPUART1 ((uint8_t)0x06)
#define | GPIO_AF6_UCPD1 ((uint8_t)0x06)
#define | GPIO_AF6_UCPD2 ((uint8_t)0x06)
#define | GPIO_AF6_USB ((uint8_t)0x06)
#define | GPIO_AF7_COMP1 ((uint8_t)0x07)
AF 7 selection.
#define | GPIO_AF7_COMP2 ((uint8_t)0x07)
#define | GPIO_AF7_COMP3 ((uint8_t)0x07)
#define | GPIO_AF7_EVENTOUT ((uint8_t)0x07)
#define | GPIO_AF8_I2C2 ((uint8_t)0x08)
AF 8 selection.
#define | GPIO_AF8_USART5 ((uint8_t)0x08)
#define | GPIO_AF8_USART6 ((uint8_t)0x08)
#define | GPIO_AF9_I2C3 ((uint8_t)0x09)
AF 9 selection.
#define | GPIO_AF9_SPI3 ((uint8_t)0x09)
#define | GPIO_AF9_TIM4 ((uint8_t)0x09)
#define | GPIO_AF10_LPUART2 ((uint8_t)0x0A)
AF 10 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0A)
#define | GPIO_GET_INDEX(__GPIOx__)

Detailed Description

Header file of GPIO HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_gpio_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_hcd.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_hcd.h File Reference

Header file of HCD HAL module. More...

#include "stm32g0xx_ll_usb.h"

Go to the source code of this file.

Data Structures

struct | __HCD_HandleTypeDef

Defines

#define | PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U))
#define | HCD_SPEED_FULL USBH_FSLS_SPEED
#define | HCD_SPEED_LOW USBH_FSLS_SPEED
#define | HCD_DEVICE_SPEED_HIGH 0U
#define | HCD_DEVICE_SPEED_FULL 1U
#define | HCD_DEVICE_SPEED_LOW 2U
#define | HCD_PHY_ULPI 1U
#define | HCD_PHY_EMBEDDED 2U
#define | HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U)
#define | __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define | __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)
#define | __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)
#define | HCD_LOGICAL_CH_NOT_OPENED 0xFFU
#define | HCD_FREE_CH_NOT_FOUND 0xFFU
#define | HCD_SNG_BUF 0U
#define | HCD_DBL_BUF 1U
#define | HCD_SET_CHANNEL USB_DRD_SET_CHEP
#define | HCD_GET_CHANNEL USB_DRD_GET_CHEP
#define | HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP
Set the Setup bit in the corresponding channel, when a Setup transaction is needed.
#define | HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
sets the status for rx transfer (bits STAT_TX[1:0])
#define | HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS
#define | HCD_SET_CH_KIND USB_DRD_SET_CH_KIND
Sets/clears CH_KIND bit in the Channel register.
#define | HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND
#define | HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND
#define | HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND
#define | HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR
Clears bit ERR_RX in the Channel register.
#define | HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR
Clears bit ERR_TX in the Channel register.
#define | HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR
#define | HCD_RX_DTOG USB_DRD_RX_DTOG
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | HCD_TX_DTOG USB_DRD_TX_DTOG
#define | HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
#define | HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT
sets counter for the tx/rx buffer.
#define | HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT
#define | HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT
gets counter of the tx buffer.
#define | HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
Gets buffer 0/1 address of a double buffer endpoint.
#define | HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
#define | HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT

Typedefs

typedef USB_DRD_TypeDef | HCD_TypeDef
typedef USB_DRD_CfgTypeDef | HCD_InitTypeDef
typedef USB_DRD_HCTypeDef | HCD_HCTypeDef
typedef USB_DRD_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_DRD_HCStateTypeDef | HCD_HCStateTypeDef
typedef struct __HCD_HandleTypeDef | HCD_HandleTypeDef
typedef void(* | pHCD_CallbackTypeDef )(HCD_HandleTypeDef *hhcd)
typedef void(* | pHCD_HC_NotifyURBChangeCallbackTypeDef )(HCD_HandleTypeDef *hhcd, uint8_t epnum, HCD_URBStateTypeDef urb_state)

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}
enum HCD_HostStateTypeDef {
HCD_HCD_STATE_DISCONNECTED = 0x00U, HCD_HCD_STATE_CONNECTED = 0x01U, HCD_HCD_STATE_RESETED = 0x02U, HCD_HCD_STATE_RUN = 0x03U,
HCD_HCD_STATE_SUSPEND = 0x04U, HCD_HCD_STATE_RESUME = 0x05U
}
enum HAL_HCD_CallbackIDTypeDef {
HAL_HCD_SOF_CB_ID = 0x01, HAL_HCD_CONNECT_CB_ID = 0x02, HAL_HCD_DISCONNECT_CB_ID = 0x03, HAL_HCD_PORT_ENABLED_CB_ID = 0x04,
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, HAL_HCD_MSPINIT_CB_ID = 0x06, HAL_HCD_MSPDEINIT_CB_ID = 0x07
}

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Close (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
HAL_HCD_HC_Close Pipe.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
HAL_StatusTypeDef | HAL_HCD_RegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
Register a User USB HCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
Unregister an USB HCD Callback USB HCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_RegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd)
Unregister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_PortEnabled_Callback (HCD_HandleTypeDef *hhcd)
Port Enabled Event callback.
__weak void | HAL_HCD_PortDisabled_Callback (HCD_HandleTypeDef *hhcd)
Port Disabled Event callback.
void | HAL_HCD_SuspendCallback (HCD_HandleTypeDef *hhcd)
void | HAL_HCD_ResumeCallback (HCD_HandleTypeDef *hhcd)
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_Suspend (HCD_HandleTypeDef *hhcd)
Put the Device in suspend mode.
HAL_StatusTypeDef | HAL_HCD_Resume (HCD_HandleTypeDef *hhcd)
Resume host port.
HAL_StatusTypeDef | HAL_HCD_ResumePort (HCD_HandleTypeDef *hhcd)
Resme the host port.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.
HAL_StatusTypeDef | HAL_HCD_PMAlloc (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint16_t ch_kind, uint16_t mps)
Allocate PMA buffer for Channel This API will fetch a free space.
HAL_StatusTypeDef | HAL_HCD_PMADeAlloc (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable.
HAL_StatusTypeDef | HAL_HCD_PMAReset (HCD_HandleTypeDef *hhcd)
PMA Reset.
__STATIC_INLINE uint16_t | HCD_GET_CH_RX_CNT (const HCD_TypeDef *Instance, uint16_t bChNum)
gets counter of the rx buffer.
__STATIC_INLINE uint16_t | HCD_GET_CH_DBUF0_CNT (const HCD_TypeDef *Instance, uint16_t bChNum)
gets counter of the rx buffer0.
__STATIC_INLINE uint16_t | HCD_GET_CH_DBUF1_CNT (const HCD_TypeDef *Instance, uint16_t bChNum)
gets counter of the rx buffer1.

Detailed Description

Header file of HCD HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_hcd.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2c.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
struct | __I2C_HandleTypeDef

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
#define | HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_OTHER_FRAME (0x000000AAU)
#define | I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)
#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)
#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)
#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)
#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)
#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE
#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified I2C interrupt source is enabled or not.
#define | I2C_FLAG_MASK (0x0001FFFFU)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__)
#define | I2C_GET_ADDR_MATCH(__HANDLE__)
#define | I2C_GET_DIR(__HANDLE__)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__)
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | I2C_CHECK_FLAG(__ISR__, __FLAG__)
#define | I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef
typedef void(* | pI2C_CallbackTypeDef )(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
typedef void(* | pI2C_AddrCallbackTypeDef )(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }
enum HAL_I2C_CallbackIDTypeDef {
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, HAL_I2C_ERROR_CB_ID = 0x07U,
HAL_I2C_ABORT_CB_ID = 0x08U, HAL_I2C_MSPINIT_CB_ID = 0x09U, HAL_I2C_MSPDEINIT_CB_ID = 0x0AU
}
HAL I2C Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_i2c.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2c_ex.h File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP
#define | I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Header file of I2C HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_i2c_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2s.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_i2s.h File Reference

Header file of I2S HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | __I2S_HandleTypeDef
I2S handle Structure definition. More...

Defines

#define | HAL_I2S_ERROR_NONE (0x00000000U)
#define | HAL_I2S_ERROR_TIMEOUT (0x00000001U)
#define | HAL_I2S_ERROR_OVR (0x00000002U)
#define | HAL_I2S_ERROR_UDR (0x00000004U)
#define | HAL_I2S_ERROR_DMA (0x00000008U)
#define | HAL_I2S_ERROR_PRESCALER (0x00000010U)
#define | HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U)
#define | HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U)
#define | I2S_MODE_SLAVE_TX (0x00000000U)
#define | I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
#define | I2S_STANDARD_PHILIPS (0x00000000U)
#define | I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
#define | I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
#define | I2S_DATAFORMAT_16B (0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define | I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
#define | I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE (0x00000000U)
#define | I2S_AUDIOFREQ_192K (192000U)
#define | I2S_AUDIOFREQ_96K (96000U)
#define | I2S_AUDIOFREQ_48K (48000U)
#define | I2S_AUDIOFREQ_44K (44100U)
#define | I2S_AUDIOFREQ_32K (32000U)
#define | I2S_AUDIOFREQ_22K (22050U)
#define | I2S_AUDIOFREQ_16K (16000U)
#define | I2S_AUDIOFREQ_11K (11025U)
#define | I2S_AUDIOFREQ_8K (8000U)
#define | I2S_AUDIOFREQ_DEFAULT (2U)
#define | I2S_CPOL_LOW (0x00000000U)
#define | I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE
#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY
#define | I2S_FLAG_MASK
#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
Enable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
Disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
Enable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
Disable the specified I2S interrupts.
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.
#define | __HAL_I2S_FLUSH_RX_DR(__HANDLE__)
Flush the I2S DR Register.
#define | I2S_CHECK_FLAG(__SR__, __FLAG__)
Check whether the specified SPI flag is set or not.
#define | I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)
Check whether the specified SPI Interrupt is set or not.
#define | IS_I2S_MODE(__MODE__)
Checks if I2S Mode parameter is in allowed range.
#define | IS_I2S_STANDARD(__STANDARD__)
#define | IS_I2S_DATA_FORMAT(__FORMAT__)
#define | IS_I2S_MCLK_OUTPUT(__OUTPUT__)
#define | IS_I2S_AUDIO_FREQ(__FREQ__)
#define | IS_I2S_CPOL(__CPOL__)
Checks if I2S Serial clock steady state parameter is in allowed range.

Typedefs

typedef struct __I2S_HandleTypeDef | I2S_HandleTypeDef
I2S handle Structure definition.
typedef void(* | pI2S_CallbackTypeDef )(I2S_HandleTypeDef *hi2s)
HAL I2S Callback pointer definition.

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x03U,
HAL_I2S_STATE_BUSY_RX = 0x04U, HAL_I2S_STATE_TIMEOUT = 0x06U, HAL_I2S_STATE_ERROR = 0x07U
}
HAL State structures definition. More...
enum HAL_I2S_CallbackIDTypeDef {
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U,
HAL_I2S_ERROR_CB_ID = 0x06U, HAL_I2S_MSPINIT_CB_ID = 0x07U, HAL_I2S_MSPDEINIT_CB_ID = 0x08U
}
HAL I2S Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_i2s.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_irda.h File Reference

  • File List
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stm32g0xx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_irda_ex.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | __IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | HAL_IRDA_STATE_RESET 0x00000000U
#define | HAL_IRDA_STATE_READY 0x00000020U
#define | HAL_IRDA_STATE_BUSY 0x00000024U
#define | HAL_IRDA_STATE_BUSY_TX 0x00000021U
#define | HAL_IRDA_STATE_BUSY_RX 0x00000022U
#define | HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_IRDA_STATE_TIMEOUT 0x000000A0U
#define | HAL_IRDA_STATE_ERROR 0x000000E0U
#define | HAL_IRDA_ERROR_NONE (0x00000000U)
#define | HAL_IRDA_ERROR_PE (0x00000001U)
#define | HAL_IRDA_ERROR_NE (0x00000002U)
#define | HAL_IRDA_ERROR_FE (0x00000004U)
#define | HAL_IRDA_ERROR_ORE (0x00000008U)
#define | HAL_IRDA_ERROR_DMA (0x00000010U)
#define | HAL_IRDA_ERROR_BUSY (0x00000020U)
#define | HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U)
#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN USART_CR1_PCE
#define | IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | IRDA_MODE_RX USART_CR1_RE
#define | IRDA_MODE_TX USART_CR1_TE
#define | IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP
#define | IRDA_PRESCALER_DIV1 0x00000000U
#define | IRDA_PRESCALER_DIV2 0x00000001U
#define | IRDA_PRESCALER_DIV4 0x00000002U
#define | IRDA_PRESCALER_DIV6 0x00000003U
#define | IRDA_PRESCALER_DIV8 0x00000004U
#define | IRDA_PRESCALER_DIV10 0x00000005U
#define | IRDA_PRESCALER_DIV12 0x00000006U
#define | IRDA_PRESCALER_DIV16 0x00000007U
#define | IRDA_PRESCALER_DIV32 0x00000008U
#define | IRDA_PRESCALER_DIV64 0x00000009U
#define | IRDA_PRESCALER_DIV128 0x0000000AU
#define | IRDA_PRESCALER_DIV256 0x0000000BU
#define | IRDA_STATE_DISABLE 0x00000000U
#define | IRDA_STATE_ENABLE USART_CR1_UE
#define | IRDA_MODE_DISABLE 0x00000000U
#define | IRDA_MODE_ENABLE USART_CR3_IREN
#define | IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | IRDA_DMA_TX_DISABLE 0x00000000U
#define | IRDA_DMA_TX_ENABLE USART_CR3_DMAT
#define | IRDA_DMA_RX_DISABLE 0x00000000U
#define | IRDA_DMA_RX_ENABLE USART_CR3_DMAR
#define | IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | IRDA_FLAG_REACK USART_ISR_REACK
#define | IRDA_FLAG_TEACK USART_ISR_TEACK
#define | IRDA_FLAG_BUSY USART_ISR_BUSY
#define | IRDA_FLAG_ABRF USART_ISR_ABRF
#define | IRDA_FLAG_ABRE USART_ISR_ABRE
#define | IRDA_FLAG_TXE USART_ISR_TXE_TXFNF
#define | IRDA_FLAG_TC USART_ISR_TC
#define | IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | IRDA_FLAG_ORE USART_ISR_ORE
#define | IRDA_FLAG_NE USART_ISR_NE
#define | IRDA_FLAG_FE USART_ISR_FE
#define | IRDA_FLAG_PE USART_ISR_PE
#define | IRDA_IT_PE 0x0028U
#define | IRDA_IT_TXE 0x0727U
#define | IRDA_IT_TC 0x0626U
#define | IRDA_IT_RXNE 0x0525U
#define | IRDA_IT_IDLE 0x0424U
#define | IRDA_IT_ERR 0x0060U
#define | IRDA_IT_ORE 0x0300U
#define | IRDA_IT_NE 0x0200U
#define | IRDA_IT_FE 0x0100U
#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NECF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF
#define | IRDA_IT_MASK 0x001FU
#define | IRDA_CR_MASK 0x00E0U
#define | IRDA_CR_POS 5U
#define | IRDA_ISR_MASK 0x1F00U
#define | IRDA_ISR_POS 8U
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__)
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that IRDA clock Prescaler is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Typedefs

typedef uint32_t | HAL_IRDA_StateTypeDef
HAL IRDA State definition.
typedef struct __IRDA_HandleTypeDef | IRDA_HandleTypeDef
IRDA handle Structure definition.
typedef void(* | pIRDA_CallbackTypeDef )(IRDA_HandleTypeDef *hirda)
HAL IRDA Callback pointer definition.

Enumerations

enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_SYSCLK = 0x04U, IRDA_CLOCKSOURCE_LSE = 0x10U,
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U
}
IRDA clock sources definition. More...
enum HAL_IRDA_CallbackIDTypeDef {
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U,
HAL_IRDA_ERROR_CB_ID = 0x04U, HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_IRDA_MSPINIT_CB_ID = 0x08U, HAL_IRDA_MSPDEINIT_CB_ID = 0x09U
}
HAL IRDA Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_irda.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_irda_ex.h File Reference

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Defines
stm32g0xx_hal_irda_ex.h File Reference

Header file of IRDA HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | IRDA_WORDLENGTH_7B USART_CR1_M1
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B USART_CR1_M0
#define | IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.

Detailed Description

Header file of IRDA HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_irda_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_iwdg.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | IWDG_WINDOW_DISABLE IWDG_WINR_WIN
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_iwdg.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_lptim.h File Reference

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stm32g0xx_hal_lptim.h File Reference

Header file of LPTIM HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | __LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29
#define | LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30
#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
#define | LPTIM_PRESCALER_DIV1 0x00000000U
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define | LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define | LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define | LPTIM_TRIGSOURCE_0 0x00000000U
#define | LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
#define | LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1SEL_1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)
#define | LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0
#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE
#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified LPTIM interrupt source is enabled or not.
#define | __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
Enable the LPTIM1 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()
Disable the LPTIM1 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)
Enable the LPTIM1 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT()
Disable the LPTIM1 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
Enable the LPTIM2 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()
Disable the LPTIM2 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)
Enable the LPTIM2 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT()
Disable the LPTIM2 EXTI line in event mode.
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PERIOD(__PERIOD__)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Typedefs

typedef struct
__LPTIM_HandleTypeDef 		LPTIM_HandleTypeDef
LPTIM handle Structure definition.
typedef void(* | pLPTIM_CallbackTypeDef )(LPTIM_HandleTypeDef *hlptim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...
enum HAL_LPTIM_CallbackIDTypeDef {
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U,
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U
}
HAL LPTIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (const LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (const LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (const LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.
void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.

Detailed Description

Header file of LPTIM HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_lptim.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pcd.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32g0xx_ll_usb.h"
#include "stm32g0xx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | __PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_FULL USBD_FS_SPEED
#define | PCD_PHY_ULPI 1U
#define | PCD_PHY_EMBEDDED 2U
#define | PCD_PHY_UTMI 3U
#define | HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)
#define | __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE)
#define | USB_WAKEUP_EXTI_LINE (0x1U << 4)
#define | PCD_EP0MPS_64 EP_MPS_64
#define | PCD_EP0MPS_32 EP_MPS_32
#define | PCD_EP0MPS_16 EP_MPS_16
#define | PCD_EP0MPS_08 EP_MPS_8
#define | PCD_ENDP0 0U
#define | PCD_ENDP1 1U
#define | PCD_ENDP2 2U
#define | PCD_ENDP3 3U
#define | PCD_ENDP4 4U
#define | PCD_ENDP5 5U
#define | PCD_ENDP6 6U
#define | PCD_ENDP7 7U
#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U
#define | PCD_SET_ENDPOINT USB_DRD_SET_CHEP
#define | PCD_GET_ENDPOINT USB_DRD_GET_CHEP
#define | USB_EP0StartXfer USB_EPStartXfer
#define | PCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_SET_EP_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_KIND USB_DRD_SET_CHEP_KIND
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_EP_KIND USB_DRD_CLEAR_CHEP_KIND
#define | PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND
#define | PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND
#define | PCD_CLEAR_RX_EP_CTR USB_DRD_CLEAR_RX_CHEP_CTR
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR USB_DRD_CLEAR_TX_CHEP_CTR
#define | PCD_RX_DTOG USB_DRD_RX_DTOG
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG USB_DRD_TX_DTOG
#define | PCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
#define | PCD_SET_EP_ADDRESS USB_DRD_SET_CHEP_ADDRESS
Sets address in an endpoint register.
#define | PCD_SET_EP_TX_ADDRESS USB_DRD_SET_CHEP_TX_ADDRESS
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS USB_DRD_SET_CHEP_RX_ADDRESS
#define | PCD_SET_EP_TX_CNT USB_DRD_SET_CHEP_TX_CNT
sets counter for the tx/rx buffer.
#define | PCD_SET_EP_RX_CNT USB_DRD_SET_CHEP_RX_CNT
#define | PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT
gets counter of the tx buffer.
#define | PCD_SET_EP_DBUF_ADDR USB_DRD_SET_CHEP_DBUF_ADDR
Sets addresses in a double buffer endpoint.
#define | PCD_SET_EP_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
#define | PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT

Typedefs

typedef USB_DRD_TypeDef | PCD_TypeDef
typedef USB_DRD_CfgTypeDef | PCD_InitTypeDef
typedef USB_DRD_EPTypeDef | PCD_EPTypeDef
typedef struct __PCD_HandleTypeDef | PCD_HandleTypeDef
PCD Handle Structure definition.
typedef void(* | pPCD_CallbackTypeDef )(PCD_HandleTypeDef *hpcd)
typedef void(* | pPCD_DataOutStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_DataInStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoOutIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoInIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_LpmCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
typedef void(* | pPCD_BcdCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }
enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}
enum HAL_PCD_CallbackIDTypeDef {
HAL_PCD_SOF_CB_ID = 0x01, HAL_PCD_SETUPSTAGE_CB_ID = 0x02, HAL_PCD_RESET_CB_ID = 0x03, HAL_PCD_SUSPEND_CB_ID = 0x04,
HAL_PCD_RESUME_CB_ID = 0x05, HAL_PCD_CONNECT_CB_ID = 0x06, HAL_PCD_DISCONNECT_CB_ID = 0x07, HAL_PCD_MSPINIT_CB_ID = 0x08,
HAL_PCD_MSPDEINIT_CB_ID = 0x09
}

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Abort (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Abort an USB EP transaction.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.
__STATIC_INLINE uint16_t | PCD_GET_EP_RX_CNT (const PCD_TypeDef *Instance, uint16_t bEpNum)
gets counter of the rx buffer.
__STATIC_INLINE uint16_t | PCD_GET_EP_DBUF0_CNT (const PCD_TypeDef *Instance, uint16_t bEpNum)
gets counter of the rx buffer0.
__STATIC_INLINE uint16_t | PCD_GET_EP_DBUF1_CNT (const PCD_TypeDef *Instance, uint16_t bEpNum)
gets counter of the rx buffer1.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_pcd.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pcd_ex.h File Reference

  • File List
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Functions
stm32g0xx_hal_pcd_ex.h File Reference

Header file of PCD HAL Extension module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

Header file of PCD HAL Extension module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_pcd_ex.h.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pwr.h File Reference

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stm32g0xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_pwr_ex.h"

Go to the source code of this file.

Defines

#define | PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN6 PWR_CR3_EWUP6
#define | PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN6_HIGH PWR_CR3_EWUP6
#define | PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)
#define | PWR_WAKEUP_PIN6_LOW ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6)
#define | PWR_LOWPOWERMODE_STOP0 (0x00000000u)
#define | PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0)
#define | PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
#define | PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2)
#define | PWR_MAINREGULATOR_ON (0x00000000u)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01u)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02u)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01u)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02u)
#define | PWR_FLAG_WUF1 (0x00010000u | PWR_SR1_WUF1)
#define | PWR_FLAG_WUF2 (0x00010000u | PWR_SR1_WUF2)
#define | PWR_FLAG_WUF3 (0x00010000u | PWR_SR1_WUF3)
#define | PWR_FLAG_WUF4 (0x00010000u | PWR_SR1_WUF4)
#define | PWR_FLAG_WUF5 (0x00010000u | PWR_SR1_WUF5)
#define | PWR_FLAG_WUF6 (0x00010000u | PWR_SR1_WUF6)
#define | PWR_FLAG_WUF (0x00010000u | PWR_SR1_WUF)
#define | PWR_FLAG_SB (0x00010000u | PWR_SR1_SBF)
#define | PWR_FLAG_WUFI (0x00010000u | PWR_SR1_WUFI)
#define | PWR_FLAG_FLASH_READY (0x00020000u | PWR_SR2_FLASH_RDY)
#define | PWR_FLAG_REGLPS (0x00020000u | PWR_SR2_REGLPS)
#define | PWR_FLAG_REGLPF (0x00020000u | PWR_SR2_REGLPF)
#define | PWR_FLAG_PVDO (0x00020000u | PWR_SR2_PVDO)
#define | PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_USB)
#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check whether or not a specific PWR flag is set.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->SCR = (__FLAG__))
Clear a specific PWR flag.
#define | PWR_WUP_POLARITY_SHIFT 0x08u
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY)
#define | IS_PWR_STOP_ENTRY(ENTRY)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC & TAMP registers, backup registers, RCC BDCR register).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Enable Sleep-On-Exit Cortex feature.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit Cortex feature.
void | HAL_PWR_EnableSEVOnPend (void)
Enable Cortex Sev On Pending feature.
void | HAL_PWR_DisableSEVOnPend (void)
Disable Cortex Sev On Pending feature.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_pwr.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pwr_ex.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32g0xx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVMTypeDef
PWR PVM configuration structure definition. More...
struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_PVDLEVEL_RISING_0 (0x00000000u)
#define | PWR_PVDLEVEL_RISING_1 (PWR_CR2_PVDRT_0)
#define | PWR_PVDLEVEL_RISING_2 (PWR_CR2_PVDRT_1)
#define | PWR_PVDLEVEL_RISING_3 (PWR_CR2_PVDRT_0 | PWR_CR2_PVDRT_1)
#define | PWR_PVDLEVEL_RISING_4 (PWR_CR2_PVDRT_2)
#define | PWR_PVDLEVEL_RISING_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0)
#define | PWR_PVDLEVEL_RISING_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1)
#define | PWR_PVDLEVEL_FALLING_0 (0x00000000u)
#define | PWR_PVDLEVEL_FALLING_1 (PWR_CR2_PVDFT_0)
#define | PWR_PVDLEVEL_FALLING_2 (PWR_CR2_PVDFT_1)
#define | PWR_PVDLEVEL_FALLING_3 (PWR_CR2_PVDFT_0 | PWR_CR2_PVDFT_1)
#define | PWR_PVDLEVEL_FALLING_4 (PWR_CR2_PVDFT_2)
#define | PWR_PVDLEVEL_FALLING_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0)
#define | PWR_PVDLEVEL_FALLING_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1)
#define | PWR_PVDLEVEL_0 (PWR_PVDLEVEL_RISING_0 | PWR_PVDLEVEL_FALLING_0)
#define | PWR_PVDLEVEL_1 (PWR_PVDLEVEL_RISING_1 | PWR_PVDLEVEL_FALLING_1)
#define | PWR_PVDLEVEL_2 (PWR_PVDLEVEL_RISING_2 | PWR_PVDLEVEL_FALLING_2)
#define | PWR_PVDLEVEL_3 (PWR_PVDLEVEL_RISING_3 | PWR_PVDLEVEL_FALLING_3)
#define | PWR_PVDLEVEL_4 (PWR_PVDLEVEL_RISING_4 | PWR_PVDLEVEL_FALLING_4)
#define | PWR_PVDLEVEL_5 (PWR_PVDLEVEL_RISING_5 | PWR_PVDLEVEL_FALLING_5)
#define | PWR_PVDLEVEL_6 (PWR_PVDLEVEL_RISING_6 | PWR_PVDLEVEL_FALLING_6)
#define | PWR_PVDLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)
#define | PWR_PVD_MODE_NORMAL (0x00000000u)
#define | PWR_PVD_MODE_IT_RISING (0x00010001u)
#define | PWR_PVD_MODE_IT_FALLING (0x00010002u)
#define | PWR_PVD_MODE_IT_RISING_FALLING (0x00010003u)
#define | PWR_PVD_MODE_EVENT_RISING (0x00020001u)
#define | PWR_PVD_MODE_EVENT_FALLING (0x00020002u)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003u)
#define | PWR_EXTI_LINE_PVD (EXTI_IMR1_IM16)
#define | PWR_EVENT_LINE_PVD (EXTI_EMR1_EM16)
#define | PWR_PVM_USB PWR_CR2_PVMEN_USB
#define | PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)
#define | PWR_EXTI_LINE_PVM (EXTI_IMR2_IM34)
#define | PWR_EVENT_LINE_PVM (EXTI_EMR2_EM34)
#define | PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000u)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS
#define | PWR_GPIO_BIT_0 PWR_PUCRB_PU0
#define | PWR_GPIO_BIT_1 PWR_PUCRB_PU1
#define | PWR_GPIO_BIT_2 PWR_PUCRB_PU2
#define | PWR_GPIO_BIT_3 PWR_PUCRB_PU3
#define | PWR_GPIO_BIT_4 PWR_PUCRB_PU4
#define | PWR_GPIO_BIT_5 PWR_PUCRB_PU5
#define | PWR_GPIO_BIT_6 PWR_PUCRB_PU6
#define | PWR_GPIO_BIT_7 PWR_PUCRB_PU7
#define | PWR_GPIO_BIT_8 PWR_PUCRB_PU8
#define | PWR_GPIO_BIT_9 PWR_PUCRB_PU9
#define | PWR_GPIO_BIT_10 PWR_PUCRB_PU10
#define | PWR_GPIO_BIT_11 PWR_PUCRB_PU11
#define | PWR_GPIO_BIT_12 PWR_PUCRB_PU12
#define | PWR_GPIO_BIT_13 PWR_PUCRB_PU13
#define | PWR_GPIO_BIT_14 PWR_PUCRB_PU14
#define | PWR_GPIO_BIT_15 PWR_PUCRB_PU15
#define | PWR_GPIO_A (0x00000000u)
#define | PWR_GPIO_B (0x00000001u)
#define | PWR_GPIO_C (0x00000002u)
#define | PWR_GPIO_D (0x00000003u)
#define | PWR_GPIO_E (0x00000004u)
#define | PWR_GPIO_F (0x00000005u)
#define | PWR_FLASHPD_LPRUN PWR_CR1_FPD_LPRUN
#define | PWR_FLASHPD_LPSLEEP PWR_CR1_FPD_LPSLP
#define | PWR_FLASHPD_STOP PWR_CR1_FPD_STOP
#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1
#define | PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB)
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Enable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Disable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() (EXTI->RPR1 & PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt Rising flag is set.
#define | __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() (EXTI->FPR1 & PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt Falling flag is set.
#define | __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt Rising flag.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt Falling flag.
#define | __HAL_PWR_PVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)
Enable the PVM Extended Interrupt Line.
#define | __HAL_PWR_PVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)
Disable the PVM Extended Interrupt Line.
#define | __HAL_PWR_PVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)
Enable the PVM Event Line.
#define | __HAL_PWR_PVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)
Disable the PVM Event Line.
#define | __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)
Enable the PVM Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)
Disable the PVM Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)
Enable the PVM Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)
Disable the PVM Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVM Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM_EXTI_GET_RISING_FLAG() (EXTI->RPR2 & PWR_EXTI_LINE_PVM)
Check whether or not the PVM EXTI interrupt Rising flag is set.
#define | __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() (EXTI->FPR2 & PWR_EXTI_LINE_PVM)
Check whether or not the PVM EXTI interrupt Falling flag is set.
#define | __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM)
Clear the PVM EXTI interrupt Rising flag.
#define | __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM)
Clear the PVM EXTI interrupt Falling flag.
#define | PVM_MODE_IT ((uint32_t)0x00010000)
#define | PVM_MODE_EVT ((uint32_t)0x00020000)
#define | PVM_RISING_EDGE ((uint32_t)0x00000001)
#define | PVM_FALLING_EDGE ((uint32_t)0x00000002)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__)
#define | IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__)
#define | IS_PWR_GPIO(__GPIO__)
#define | IS_PWR_FLASH_POWERDOWN(__MODE__)
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) & ~(PWR_CR2_PVDRT | PWR_CR2_PVDFT)) == 0x00000000u)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB)
#define | IS_PWR_PVM_MODE(MODE)

Functions

void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnablePORMonitorSampling (void)
Enable POR Monitor sampling mode.
void | HAL_PWREx_DisablePORMonitorSampling (void)
Disable POR Monitor sampling mode.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAMRetention (void)
Enable SRAM content retention in Standby mode.
void | HAL_PWREx_DisableSRAMRetention (void)
Disable SRAM content retention in Standby mode.
void | HAL_PWREx_EnableFlashPowerDown (uint32_t PowerMode)
Enable Flash Power Down.
void | HAL_PWREx_DisableFlashPowerDown (uint32_t PowerMode)
Disable Flash Power Down.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main regulator output voltage.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the Power Voltage Detector (PVD).
void | HAL_PWREx_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWREx_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWREx_EnableVddIO2 (void)
Enable VDDIO2 supply.
void | HAL_PWREx_DisableVddIO2 (void)
Disable VDDIO2 supply.
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnablePVMUSB (void)
Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)
void | HAL_PWREx_DisablePVMUSB (void)
Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWREx_PVD_PVM_Rising_Callback (void)
PWR PVD interrupt rising callback.
__weak void | HAL_PWREx_PVD_PVM_Falling_Callback (void)
PWR PVD interrupt Falling callback.

Detailed Description

Header file of PWR HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_pwr_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rcc.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_ll_rcc.h"
#include "stm32g0xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | CR_REG_INDEX 1U
#define | BDCR_REG_INDEX 2U
#define | CSR_REG_INDEX 3U
#define | CRRCR_REG_INDEX 4U
#define | RCC_FLAG_MASK 0x1FU
#define | RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1)
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
#define | IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U)
#define | IS_RCC_HSIDIV(__DIV__)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_PLLM_VALUE(__VALUE__)
#define | IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
#define | IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
#define | IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
#define | IS_RCC_CLOCKTYPE(__CLK__)
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) )
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_MCODIV(__DIV__)
#define | IS_RCC_MCO2SOURCE(__SOURCE__)
#define | IS_RCC_MCO2DIV(__DIV__)
#define | IS_RCC_LSE_DRIVE(__DRIVE__)
#define | RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */
#define | RCC_OSCILLATORTYPE_NONE 0x00000000U
#define | RCC_OSCILLATORTYPE_HSE 0x00000001U
#define | RCC_OSCILLATORTYPE_HSI 0x00000002U
#define | RCC_OSCILLATORTYPE_LSE 0x00000004U
#define | RCC_OSCILLATORTYPE_LSI 0x00000008U
#define | RCC_OSCILLATORTYPE_HSI48 0x00000020U
#define | RCC_HSE_OFF 0x00000000U
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON)
#define | RCC_LSE_OFF 0x00000000U
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)
#define | RCC_HSI_OFF 0x00000000U
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT 64U
#define | RCC_HSI_DIV1 0x00000000U
#define | RCC_HSI_DIV2 RCC_CR_HSIDIV_0
#define | RCC_HSI_DIV4 RCC_CR_HSIDIV_1
#define | RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)
#define | RCC_HSI_DIV16 RCC_CR_HSIDIV_2
#define | RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0)
#define | RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1)
#define | RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)
#define | RCC_LSI_OFF 0x00000000U
#define | RCC_LSI_ON RCC_CSR_LSION
#define | RCC_HSI48_OFF 0x00000000U
#define | RCC_HSI48_ON RCC_CR_HSI48ON
#define | RCC_PLL_NONE 0x00000000U
#define | RCC_PLL_OFF 0x00000001U
#define | RCC_PLL_ON 0x00000002U
#define | RCC_PLLM_DIV1 0x00000000U
#define | RCC_PLLM_DIV2 RCC_PLLCFGR_PLLM_0
#define | RCC_PLLM_DIV3 RCC_PLLCFGR_PLLM_1
#define | RCC_PLLM_DIV4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
#define | RCC_PLLM_DIV5 RCC_PLLCFGR_PLLM_2
#define | RCC_PLLM_DIV6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
#define | RCC_PLLM_DIV7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
#define | RCC_PLLM_DIV8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0)
#define | RCC_PLLP_DIV2 RCC_PLLCFGR_PLLP_0
#define | RCC_PLLP_DIV3 RCC_PLLCFGR_PLLP_1
#define | RCC_PLLP_DIV4 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV5 RCC_PLLCFGR_PLLP_2
#define | RCC_PLLP_DIV6 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV7 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV8 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV9 RCC_PLLCFGR_PLLP_3
#define | RCC_PLLP_DIV10 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV11 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV12 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV13 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2)
#define | RCC_PLLP_DIV14 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV15 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV16 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV17 RCC_PLLCFGR_PLLP_4
#define | RCC_PLLP_DIV18 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV19 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV20 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV21 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2)
#define | RCC_PLLP_DIV22 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV23 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV24 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV25 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3)
#define | RCC_PLLP_DIV26 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV27 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV28 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV29 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2)
#define | RCC_PLLP_DIV30 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLP_DIV31 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)
#define | RCC_PLLP_DIV32 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
#define | RCC_PLLQ_DIV2 RCC_PLLCFGR_PLLQ_0
#define | RCC_PLLQ_DIV3 RCC_PLLCFGR_PLLQ_1
#define | RCC_PLLQ_DIV4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0)
#define | RCC_PLLQ_DIV5 RCC_PLLCFGR_PLLQ_2
#define | RCC_PLLQ_DIV6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0)
#define | RCC_PLLQ_DIV7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1)
#define | RCC_PLLQ_DIV8 (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0)
#define | RCC_PLLR_DIV2 RCC_PLLCFGR_PLLR_0
#define | RCC_PLLR_DIV3 RCC_PLLCFGR_PLLR_1
#define | RCC_PLLR_DIV4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0)
#define | RCC_PLLR_DIV5 RCC_PLLCFGR_PLLR_2
#define | RCC_PLLR_DIV6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0)
#define | RCC_PLLR_DIV7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1)
#define | RCC_PLLR_DIV8 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0)
#define | RCC_PLLSOURCE_NONE 0x00000000U
#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define | RCC_PLLPCLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLLQCLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLLRCLK RCC_PLLCFGR_PLLREN
#define | RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define | RCC_CLOCKTYPE_HCLK 0x00000002U
#define | RCC_CLOCKTYPE_PCLK1 0x00000004U
#define | RCC_SYSCLKSOURCE_HSI 0x00000000U
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_1
#define | RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)
#define | RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2
#define | RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_1
#define | RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)
#define | RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2
#define | RCC_SYSCLK_DIV1 0x00000000U
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3
#define | RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)
#define | RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)
#define | RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)
#define | RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)
#define | RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)
#define | RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | RCC_HCLK_DIV1 0x00000000U
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE_2
#define | RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)
#define | RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)
#define | RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)
#define | RCC_RTCCLKSOURCE_NONE 0x00000000U
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define | RCC_MCO1 0x00000000U
#define | RCC_MCO2 0x00000001U
#define | RCC_MCO RCC_MCO1
#define | RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1
#define | RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3
#define | RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)
#define | RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)
#define | RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0)
#define | RCC_MCODIV_1 0x00000000U
#define | RCC_MCODIV_2 RCC_CFGR_MCOPRE_0
#define | RCC_MCODIV_4 RCC_CFGR_MCOPRE_1
#define | RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | RCC_MCODIV_16 RCC_CFGR_MCOPRE_2
#define | RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)
#define | RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)
#define | RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | RCC_MCODIV_256 RCC_CFGR_MCOPRE_3
#define | RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)
#define | RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)
#define | RCC_MCO2SOURCE_NOCLOCK 0x00000000U
#define | RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0
#define | RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1
#define | RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1| RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2
#define | RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1)
#define | RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3
#define | RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1)
#define | RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0)
#define | RCC_MCO2DIV_1 0x00000000U
#define | RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0
#define | RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1
#define | RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#define | RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2
#define | RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)
#define | RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)
#define | RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#define | RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3
#define | RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)
#define | RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)
#define | RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
#define | RCC_IT_LSERDY RCC_CIFR_LSERDYF
#define | RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
#define | RCC_IT_HSERDY RCC_CIFR_HSERDYF
#define | RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
#define | RCC_IT_CSS RCC_CIFR_CSSF
#define | RCC_IT_LSECSS RCC_CIFR_LSECSSF
#define | RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
#define | RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)
#define | RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)
#define | RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)
#define | RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)
#define | RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)
#define | RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)
#define | RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)
#define | RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)
#define | RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)
#define | RCC_FLAG_PWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos)
#define | RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)
#define | RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)
#define | RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)
#define | RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)
#define | RCC_LSEDRIVE_LOW 0x00000000U
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF
#define | RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF
#define | RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF
#define | RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF
#define | RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF
#define | RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF
#define | RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF
#define | RCC_RESET_FLAG_ALL
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_FLASH_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_AES_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
#define | __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)
#define | __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN)
#define | __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
#define | __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN)
#define | __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN)
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN)
#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_CRS_CLK_ENABLE()
#define | __HAL_RCC_RTCAPB_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_USART4_CLK_ENABLE()
#define | __HAL_RCC_USART5_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_LPUART2_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_CEC_CLK_ENABLE()
#define | __HAL_RCC_UCPD1_CLK_ENABLE()
#define | __HAL_RCC_UCPD2_CLK_ENABLE()
#define | __HAL_RCC_USB_CLK_ENABLE()
#define | __HAL_RCC_FDCAN_CLK_ENABLE()
#define | __HAL_RCC_DBGMCU_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_DAC1_CLK_ENABLE()
#define | __HAL_RCC_LPTIM2_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_TIM14_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_ADC_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN)
#define | __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN);
#define | __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN)
#define | __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN)
#define | __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN)
#define | __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN)
#define | __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN)
#define | __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)
#define | __HAL_RCC_LPUART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN)
#define | __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN)
#define | __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN)
#define | __HAL_RCC_UCPD2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN)
#define | __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN)
#define | __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN)
#define | __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)
#define | __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)
#define | __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN)
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN)
#define | __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN)
#define | __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN)
#define | __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET)
#define | __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET)
#define | __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) != 0U)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U)
#define | __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) != 0U)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U)
#define | __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U)
#define | __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U)
#define | __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U)
#define | __HAL_RCC_LPUART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U)
#define | __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) != 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) != 0U)
#define | __HAL_RCC_UCPD2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) != 0U)
#define | __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U)
#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) == 0U)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U)
#define | __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U)
#define | __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U)
#define | __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) == 0U)
#define | __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U)
#define | __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U)
#define | __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U)
#define | __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U)
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U)
#define | __HAL_RCC_LPUART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U)
#define | __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) == 0U)
#define | __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) == 0U)
#define | __HAL_RCC_UCPD2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) == 0U)
#define | __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U)
#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U)
#define | __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U)
#define | __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U)
#define | __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U)
#define | __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U)
#define | __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U)
#define | __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)
#define | __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)
#define | __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
#define | __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
#define | __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)
#define | __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)
#define | __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U)
#define | __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)
#define | __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)
#define | __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
#define | __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
#define | __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)
#define | __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)
#define | __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)
#define | __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)
#define | __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)
#define | __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)
#define | __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)
#define | __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)
#define | __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)
#define | __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)
#define | __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)
#define | __HAL_RCC_LPUART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)
#define | __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)
#define | __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)
#define | __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)
#define | __HAL_RCC_UCPD2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)
#define | __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)
#define | __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)
#define | __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
#define | __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
#define | __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)
#define | __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)
#define | __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)
#define | __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)
#define | __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)
#define | __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)
#define | __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)
#define | __HAL_RCC_LPUART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)
#define | __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)
#define | __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)
#define | __HAL_RCC_UCPD2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)
#define | __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)
#define | __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)
#define | __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
#define | __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
#define | __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)
#define | __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
#define | __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
#define | __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
#define | __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)
#define | __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
#define | __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
#define | __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
#define | __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)
#define | __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
#define | __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
#define | __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)
#define | __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)
#define | __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)
#define | __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)
#define | __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)
#define | __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)
#define | __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)
#define | __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)
#define | __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)
#define | __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)
#define | __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)
#define | __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)
#define | __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)
#define | __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)
#define | __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
#define | __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)
#define | __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)
#define | __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)
#define | __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)
#define | __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET)
#define | __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET)
#define | __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET)
#define | __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET)
#define | __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)!= RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) != RESET)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET)
#define | __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET)
#define | __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) != RESET)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) != RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)!= RESET)
#define | __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)!= RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) != RESET)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) != RESET)
#define | __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) != RESET)
#define | __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) != RESET)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) != RESET)
#define | __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) != RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) == RESET)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET)
#define | __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET)
#define | __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) == RESET)
#define | __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) == RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)== RESET)
#define | __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)== RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) == RESET)
#define | __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) == RESET)
#define | __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) == RESET)
#define | __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) == RESET)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET)
#define | __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) == RESET)
#define | __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) == RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) == RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET)
#define | __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET)
#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Macros to disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_HSI_CONFIG(__HSIDIV__) MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__))
Macro to configure the HSISYS clock.
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON)
Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON)
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Macro to get the RTC clock source.
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Macro to configure the PLL multiplication factor.
#define | __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
#define | __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the Microcontroller output clock.
#define | __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the Microcontroller output clock 2.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear RCC interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the RCC interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check whether the selected RCC flag is set or not.

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PA10)(*).
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCC_DisableLSECSS (void)
Disable the LSE Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCC_GetResetSource (void)
Get and clear reset flags.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
Handle the RCC HSE Clock Security System interrupt callback.
__weak void | HAL_RCC_LSECSSCallback (void)
RCC LSE Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_rcc.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...

Defines

#define | RCC_LSCOSOURCE_LSI 0x00000000U
#define | RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL
#define | RCC_PERIPHCLK_USART1 0x00000001U
#define | RCC_PERIPHCLK_USART2 0x00000002U
#define | RCC_PERIPHCLK_USART3 0x00000004U
#define | RCC_PERIPHCLK_LPUART1 0x00000010U
#define | RCC_PERIPHCLK_I2C1 0x00000020U
#define | RCC_PERIPHCLK_I2C2 0x00000040U
#define | RCC_PERIPHCLK_LPTIM1 0x00000200U
#define | RCC_PERIPHCLK_LPTIM2 0x00000400U
#define | RCC_PERIPHCLK_I2S1 0x00000800U
#define | RCC_PERIPHCLK_LPUART2 0x00001000U
#define | RCC_PERIPHCLK_I2S2 0x00002000U
#define | RCC_PERIPHCLK_ADC 0x00004000U
#define | RCC_PERIPHCLK_RTC 0x00020000U
#define | RCC_PERIPHCLK_RNG 0x00040000U
#define | RCC_PERIPHCLK_CEC 0x00080000U
#define | RCC_PERIPHCLK_TIM1 0x00200000U
#define | RCC_PERIPHCLK_TIM15 0x00400000U
#define | RCC_PERIPHCLK_USB 0x01000000U
#define | RCC_PERIPHCLK_FDCAN 0x02000000U
#define | RCC_USART1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define | RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define | RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
#define | RCC_USART2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define | RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define | RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
#define | RCC_USART3CLKSOURCE_PCLK1 0x00000000U
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define | RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define | RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
#define | RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
#define | RCC_LPUART2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPUART2CLKSOURCE_SYSCLK RCC_CCIPR_LPUART2SEL_0
#define | RCC_LPUART2CLKSOURCE_HSI RCC_CCIPR_LPUART2SEL_1
#define | RCC_LPUART2CLKSOURCE_LSE (RCC_CCIPR_LPUART2SEL_0 | RCC_CCIPR_LPUART2SEL_1)
#define | RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
#define | RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
#define | RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U
#define | RCC_I2S1CLKSOURCE_PLL RCC_CCIPR2_I2S1SEL_0
#define | RCC_I2S1CLKSOURCE_HSI RCC_CCIPR2_I2S1SEL_1
#define | RCC_I2S1CLKSOURCE_EXT RCC_CCIPR2_I2S1SEL
#define | RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
#define | RCC_I2S2CLKSOURCE_PLL RCC_CCIPR2_I2S2SEL_0
#define | RCC_I2S2CLKSOURCE_HSI RCC_CCIPR2_I2S2SEL_1
#define | RCC_I2S2CLKSOURCE_EXT RCC_CCIPR2_I2S2SEL
#define | RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
#define | RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U
#define | RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
#define | RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
#define | RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
#define | RCC_RNGCLKSOURCE_NONE 0x00000000U
#define | RCC_RNGCLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0
#define | RCC_RNGCLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1
#define | RCC_RNGCLKSOURCE_PLL (RCC_CCIPR_RNGSEL_0|RCC_CCIPR_RNGSEL_1)
#define | RCC_RNGCLK_DIV1 0x00000000U
#define | RCC_RNGCLK_DIV2 RCC_CCIPR_RNGDIV_0
#define | RCC_RNGCLK_DIV4 RCC_CCIPR_RNGDIV_1
#define | RCC_RNGCLK_DIV8 (RCC_CCIPR_RNGDIV_0|RCC_CCIPR_RNGDIV_1)
#define | RCC_FDCANCLKSOURCE_PCLK1 0x00000000U
#define | RCC_FDCANCLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0
#define | RCC_FDCANCLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1
#define | RCC_USBCLKSOURCE_HSI48 0x00000000U
#define | RCC_USBCLKSOURCE_HSE RCC_CCIPR2_USBSEL_0
#define | RCC_USBCLKSOURCE_PLL RCC_CCIPR2_USBSEL_1
#define | RCC_ADCCLKSOURCE_SYSCLK 0x00000000U
#define | RCC_ADCCLKSOURCE_PLLADC RCC_CCIPR_ADCSEL_0
#define | RCC_ADCCLKSOURCE_HSI RCC_CCIPR_ADCSEL_1
#define | RCC_CECCLKSOURCE_HSI_DIV488 0x00000000U
#define | RCC_CECCLKSOURCE_LSE RCC_CCIPR_CECSEL
#define | RCC_TIM1CLKSOURCE_PCLK1 0x00000000U
#define | RCC_TIM1CLKSOURCE_PLL RCC_CCIPR_TIM1SEL
#define | RCC_TIM15CLKSOURCE_PCLK1 0x00000000U
#define | RCC_TIM15CLKSOURCE_PLL RCC_CCIPR_TIM15SEL
#define | RCC_CRS_NONE 0x00000000U
#define | RCC_CRS_TIMEOUT 0x00000001U
#define | RCC_CRS_SYNCOK 0x00000002U
#define | RCC_CRS_SYNCWARN 0x00000004U
#define | RCC_CRS_SYNCERR 0x00000008U
#define | RCC_CRS_SYNCMISS 0x00000010U
#define | RCC_CRS_TRIMOVF 0x00000020U
#define | RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1
#define | RCC_CRS_SYNC_DIV1 0x00000000U
#define | RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
#define | RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
#define | RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
#define | RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV
#define | RCC_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
#define | RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
#define | RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U
#define | RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
#define | RCC_CRS_FREQERRORDIR_UP 0x00000000U
#define | RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR
#define | RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE
#define | RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))
Macro to configure the I2S1 clock (I2S1CLK).
#define | __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL)))
Macro to get the I2S1 clock source.
#define | __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__))
Macro to configure the I2S2 clock (I2S2CLK).
#define | __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL)))
Macro to get the I2S2 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
Macro to get the USART3 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
Macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
Macro to get the LPUART1 clock source.
#define | __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__))
Macro to configure the LPUART2 clock (LPUART2CLK).
#define | __HAL_RCC_GET_LPUART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART2SEL)))
Macro to get the LPUART2 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
Macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
Macro to configure the LPTIM2 clock (LPTIM2CLK).
#define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
Macro to get the LPTIM2 clock source.
#define | __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
Macro to configure the CEC clock (CECCLK).
#define | __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CECSEL)))
Macro to get the CEC clock source.
#define | __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__))
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL)))
Macro to get the RNG clock.
#define | __HAL_RCC_RNGDIV_CONFIG(__RNG_CLKDIV__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__))
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_DIV() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)))
Macro to get the RNG clock division factor.
#define | __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
Macro to configure the ADC interface clock.
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
Macro to get the ADC clock source.
#define | __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__))
Macro to configure the TIM1 interface clock.
#define | __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL)))
Macro to get the TIM1 clock source.
#define | __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__))
Macro to configure the TIM15 interface clock.
#define | __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL)))
Macro to get the TIM15 clock source.
#define | __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__))
Macro to configure the USB interface clock.
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL)))
Macro to get the USB clock source.
#define | __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
Macro to configure the FDCAN interface clock.
#define | __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL)))
Macro to get the FDCAN clock source.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Enable or disable the automatic hardware adjustment of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.
#define | IS_RCC_LSCOSOURCE(__SOURCE__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C2CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2S1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2S2CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPTIM1CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPTIM2CLKSOURCE(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(__SOURCE__)
#define | IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define | IS_RCC_RNGDIV(__DIV__)
#define | IS_RCC_CECCLKSOURCE(__SOURCE__)
#define | IS_RCC_FDCANCLKSOURCE(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(__SOURCE__)
#define | IS_RCC_TIM1CLKSOURCE(__SOURCE__)
#define | IS_RCC_TIM15CLKSOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLL.
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Header file of RCC HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_rcc_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rng.h File Reference

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stm32g0xx_hal_rng.h File Reference

Header file of RNG HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RNG_InitTypeDef
struct | __RNG_HandleTypeDef

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS
#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS
#define | RNG_CED_ENABLE 0x00000000U
#define | RNG_CED_DISABLE RNG_CR_CED
#define | HAL_RNG_ERROR_NONE 0x00000000U
#define | HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U
#define | HAL_RNG_ERROR_TIMEOUT 0x00000002U
#define | HAL_RNG_ERROR_BUSY 0x00000004U
#define | HAL_RNG_ERROR_SEED 0x00000008U
#define | HAL_RNG_ERROR_CLOCK 0x00000010U
#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.
#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(__MODE__)
Verify the RNG Clock Error Detection mode.

Typedefs

typedef struct __RNG_HandleTypeDef | RNG_HandleTypeDef
typedef void(* | pRNG_CallbackTypeDef )(RNG_HandleTypeDef *hrng)
HAL RNG Callback pointer definition.
typedef void(* | pRNG_ReadyDataCallbackTypeDef )(RNG_HandleTypeDef *hrng, uint32_t random32bit)

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}
enum | HAL_RNG_CallbackIDTypeDef { HAL_RNG_ERROR_CB_ID = 0x00U, HAL_RNG_MSPINIT_CB_ID = 0x01U, HAL_RNG_MSPDEINIT_CB_ID = 0x02U }
HAL RNG Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

Header file of RNG HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_rng.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rtc.h File Reference

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stm32g0xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | __RTC_HandleTypeDef
RTC Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 0x00000000u
#define | RTC_HOURFORMAT_12 RTC_CR_FMT
#define | RTC_OUTPUT_DISABLE 0x00000000u
#define | RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define | RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define | RTC_OUTPUT_WAKEUP RTC_CR_OSEL
#define | RTC_OUTPUT_TAMPER RTC_CR_TAMPOE
#define | RTC_OUTPUT_POLARITY_HIGH 0x00000000u
#define | RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
#define | RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u
#define | RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | RTC_OUTPUT_PULLUP_NONE 0x00000000u
#define | RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU
#define | RTC_OUTPUT_REMAP_NONE 0x00000000u
#define | RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN
#define | RTC_HOURFORMAT12_AM 0x0u
#define | RTC_HOURFORMAT12_PM 0x1u
#define | RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define | RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define | RTC_DAYLIGHTSAVING_NONE 0x00000000u
#define | RTC_STOREOPERATION_RESET 0x00000000u
#define | RTC_STOREOPERATION_SET RTC_CR_BKP
#define | RTC_FORMAT_BIN 0x00000000u
#define | RTC_FORMAT_BCD 0x00000001u
#define | RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | RTC_MONTH_MAY ((uint8_t)0x05U)
#define | RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | RTC_MONTH_JULY ((uint8_t)0x07U)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | RTC_ALARMMASK_NONE 0x00000000u
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL 0x00000000u
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
#define | RTC_IT_TS RTC_CR_TSIE
#define | RTC_IT_WUT RTC_CR_WUTIE
#define | RTC_IT_ALRA RTC_CR_ALRAIE
#define | RTC_IT_ALRB RTC_CR_ALRBIE
#define | RTC_FLAG_MASK 0x001Fu
#define | RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos)
#define | RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos)
#define | RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos)
#define | RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos)
#define | RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos)
#define | RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos)
#define | RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos)
#define | RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos)
#define | RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos)
#define | RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos)
#define | RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos)
#define | RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos)
#define | RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos)
#define | RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos)
#define | RTC_CLEAR_ITSF RTC_SCR_CITSF
#define | RTC_CLEAR_TSOVF RTC_SCR_CTSOVF
#define | RTC_CLEAR_TSF RTC_SCR_CTSF
#define | RTC_CLEAR_WUTF RTC_SCR_CWUTF
#define | RTC_CLEAR_ALRBF RTC_SCR_CALRBF
#define | RTC_CLEAR_ALRAF RTC_SCR_CALRAF
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
Check whether the RTC Calendar is initialized.
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)
Add 1 hour (summer time change).
#define | __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)
Subtract 1 hour (winter time change).
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR)& ((__INTERRUPT__)>> 12U)) != 0U)? 1U : 0U)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC Alarms flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the RTC Alarms pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK
#define | RTC_DR_RESERVED_MASK
#define | RTC_INIT_MASK 0xFFFFFFFFu
#define | RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#define | RTC_TIMEOUT_VALUE 1000u
#define | RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM19
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_PULLUP(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT)
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)
#define | IS_RTC_ALARM(ALARM)
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7Fu)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFu)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)

Typedefs

typedef struct __RTC_HandleTypeDef | RTC_HandleTypeDef
RTC Handle Structure definition.
typedef void(* | pRTC_CallbackTypeDef )(RTC_HandleTypeDef *hrtc)
HAL RTC Callback pointer definition.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_RTC_CallbackIDTypeDef {
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U,
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 0x09U,
HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 0x0AU, HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 0x0BU, HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 0x0CU, HAL_RTC_MSPINIT_CB_ID = 0x0EU,
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU
}
HAL RTC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
void | HAL_RTC_DST_Add1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_Sub1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_SetStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Set the store operation bit.
void | HAL_RTC_DST_ClearStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Clear the store operation bit.
uint32_t | HAL_RTC_DST_ReadStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Read the store operation bit.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
HAL_StatusTypeDef | RTC_ExitInitMode (RTC_HandleTypeDef *hrtc)
Exit the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_rtc.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
struct | RTC_InternalTamperTypeDef

Defines

#define | RTC_TIMESTAMPEDGE_RISING 0x00000000u
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
#define | RTC_TIMESTAMPPIN_DEFAULT 0x00000000u
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
#define | RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u
#define | RTC_CALIBOUTPUT_512HZ 0x00000000u
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
#define | RTC_SHIFTADD1S_RESET 0x00000000u
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
#define | RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)
#define | RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
#define | RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E
#define | RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
#define | RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
#define | RTC_INT_TAMPER_ALL
#define | RTC_TAMPERTRIGGER_RISINGEDGE 0x00u
#define | RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
#define | RTC_TAMPERMASK_FLAG_DISABLE 0x00u
#define | RTC_TAMPERMASK_FLAG_ENABLE 0x01u
#define | RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u
#define | RTC_TAMPERFILTER_DISABLE 0x00000000U
#define | RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)
#define | RTC_TAMPER_PULLUP_ENABLE 0x00000000u
#define | RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS
#define | RTC_IT_TAMP1 TAMP_IER_TAMP1IE
#define | RTC_IT_TAMP2 TAMP_IER_TAMP2IE
#define | RTC_IT_TAMP3 TAMP_IER_TAMP3IE
#define | RTC_IT_TAMPALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE)
#define | RTC_IT_INT_TAMP3 TAMP_IER_ITAMP3IE
#define | RTC_IT_INT_TAMP4 TAMP_IER_ITAMP4IE
#define | RTC_IT_INT_TAMP5 TAMP_IER_ITAMP5IE
#define | RTC_IT_INT_TAMP6 TAMP_IER_ITAMP6IE
#define | RTC_IT_INT_TAMPALL
#define | RTC_FLAG_TAMP1 TAMP_SR_TAMP1F
#define | RTC_FLAG_TAMP2 TAMP_SR_TAMP2F
#define | RTC_FLAG_TAMP3 TAMP_SR_TAMP3F
#define | RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3)
#define | RTC_FLAG_INT_TAMP3 TAMP_SR_ITAMP3F
#define | RTC_FLAG_INT_TAMP4 TAMP_SR_ITAMP4F
#define | RTC_FLAG_INT_TAMP5 TAMP_SR_ITAMP5F
#define | RTC_FLAG_INT_TAMP6 TAMP_SR_ITAMP6F
#define | RTC_FLAG_INT_TAMPALL
#define | RTC_BKP_NUMBER 0x00000005u
#define | RTC_BKP_DR0 0x00000000u
#define | RTC_BKP_DR1 0x00000001u
#define | RTC_BKP_DR2 0x00000002u
#define | RTC_BKP_DR3 0x00000003u
#define | RTC_BKP_DR4 0x00000004u
#define | __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= (__FLAG__))
Clear the specified RTC pending flag.
#define | __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified RTC flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC WakeUpTimers flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
Clear the RTC Wake Up timers pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
Get the selected RTC TimeStamps flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
Clear the RTC Time Stamps pending flags.
#define | __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
Enable interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
Disable interrupt on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
Enable event on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
Disable event on the RTC Timestamp associated Exti line.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
Get the selected RTC Internal Time Stamps flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
Clear the RTC Internal Time Stamps pending flags.
#define | __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))
Enable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))
Disable the RTC TimeStamp on Tamper detection.
#define | __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
Enable the RTC Tamper detection output.
#define | __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
Disable the RTC Tamper detection output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
Get the selected RTC shift operations flag status.
#define | __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 |= (__TAMPER__))
Enable the TAMP Tamper input detection.
#define | __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 &= ~(__TAMPER__))
Disable the TAMP Tamper input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER |= (__INTERRUPT__))
Enable the TAMP Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER &= ~(__INTERRUPT__))
Disable the TAMP Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified TAMP Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified TAMP Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__FLAG__)) != 0U)
Get the selected TAMP Tampers flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SCR) |= (__FLAG__))
Clear the TAMP Tampers pending flags.
#define | __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable interrupt on the TAMP associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
Disable interrupt on the TAMP associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
Enable event on the TAMP associated Exti line.
#define | __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
Disable event on the TAMP associated Exti line.
#define | RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM19
#define | RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM21
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_TAMPER(__TAMPER__)
#define | IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_TAMPER_ERASE_MODE(__MODE__)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)
#define | IS_RTC_TAMPER_FILTER(__FILTER__)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)
#define | IS_RTC_TAMPER_PULLUP_STATE(__STATE__)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
void | HAL_RTCEx_TimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper in IT mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
Tamper event polling.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.

Detailed Description

Header file of RTC HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_rtc_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smartcard.h File Reference

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stm32g0xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_smartcard_ex.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initialization structure definition. More...
struct | __SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | HAL_SMARTCARD_STATE_RESET 0x00000000U
#define | HAL_SMARTCARD_STATE_READY 0x00000020U
#define | HAL_SMARTCARD_STATE_BUSY 0x00000024U
#define | HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U
#define | HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U
#define | HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U
#define | HAL_SMARTCARD_STATE_ERROR 0x000000E0U
#define | HAL_SMARTCARD_ERROR_NONE (0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE (0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE (0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE (0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE (0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA (0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO (0x00000020U)
#define | HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)
#define | SMARTCARD_WORDLENGTH_9B USART_CR1_M0
#define | SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0
#define | SMARTCARD_STOPBITS_1_5 USART_CR2_STOP
#define | SMARTCARD_PARITY_EVEN USART_CR1_PCE
#define | SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | SMARTCARD_MODE_RX USART_CR1_RE
#define | SMARTCARD_MODE_TX USART_CR1_TE
#define | SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH USART_CR2_CPOL
#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE USART_CR2_CPHA
#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL
#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_NACK_ENABLE USART_CR3_NACK
#define | SMARTCARD_TIMEOUT_DISABLE 0x00000000U
#define | SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN
#define | SMARTCARD_PRESCALER_DIV1 0x00000000U
#define | SMARTCARD_PRESCALER_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_DIV16 0x00000007U
#define | SMARTCARD_PRESCALER_DIV32 0x00000008U
#define | SMARTCARD_PRESCALER_DIV64 0x00000009U
#define | SMARTCARD_PRESCALER_DIV128 0x0000000AU
#define | SMARTCARD_PRESCALER_DIV256 0x0000000BU
#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
#define | SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | SMARTCARD_IT_MASK 0x001FU
#define | SMARTCARD_CR_MASK 0x00E0U
#define | SMARTCARD_CR_POS 5U
#define | SMARTCARD_ISR_MASK 0x1F00U
#define | SMARTCARD_ISR_POS 8U
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__)
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__)
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that SMARTCARD clock Prescaler is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Typedefs

typedef uint32_t | HAL_SMARTCARD_StateTypeDef
HAL SMARTCARD State definition.
typedef struct
__SMARTCARD_HandleTypeDef 		SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition.
typedef void(* | pSMARTCARD_CallbackTypeDef )(SMARTCARD_HandleTypeDef *hsmartcard)
HAL SMARTCARD Callback pointer definition.

Enumerations

enum HAL_SMARTCARD_CallbackIDTypeDef {
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, HAL_SMARTCARD_ERROR_CB_ID = 0x02U, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U,
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U,
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U
}
HAL SMARTCARD Callback ID enumeration definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, SMARTCARD_CLOCKSOURCE_HSI = 0x02U, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, SMARTCARD_CLOCKSOURCE_LSE = 0x08U,
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U
}
SMARTCARD clock sources. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_smartcard.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smartcard_ex.h File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_smartcard_ex.h File Reference

Header file of SMARTCARD HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC
#define | SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U
#define | SMARTCARD_FIFOMODE_DISABLE 0x00000000U
#define | SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT
#define | SMARTCARD_IT_PE 0x0028U
#define | SMARTCARD_IT_TXE 0x0727U
#define | SMARTCARD_IT_TXFNF 0x0727U
#define | SMARTCARD_IT_TC 0x0626U
#define | SMARTCARD_IT_RXNE 0x0525U
#define | SMARTCARD_IT_RXFNE 0x0525U
#define | SMARTCARD_IT_IDLE 0x0424U
#define | SMARTCARD_IT_ERR 0x0060U
#define | SMARTCARD_IT_ORE 0x0300U
#define | SMARTCARD_IT_NE 0x0200U
#define | SMARTCARD_IT_FE 0x0100U
#define | SMARTCARD_IT_EOB 0x0C3BU
#define | SMARTCARD_IT_RTO 0x0B3AU
#define | SMARTCARD_IT_TCBGT 0x1978U
#define | SMARTCARD_IT_RXFF 0x183FU
#define | SMARTCARD_IT_TXFE 0x173EU
#define | SMARTCARD_IT_RXFT 0x1A7CU
#define | SMARTCARD_IT_TXFT 0x1B77U
#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NECF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.
#define | IS_SMARTCARD_FIFOMODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.
__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of SMARTCARD HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_smartcard_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smbus.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_smbus.h File Reference

Header file of SMBUS HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_smbus_ex.h"

Go to the source code of this file.

Data Structures

struct | SMBUS_InitTypeDef
struct | __SMBUS_HandleTypeDef

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)
#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)
#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)
#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX
#define | SMBUS_IT_RX
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR
#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__)
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__)
#define | SMBUS_RESET_CR2(__HANDLE__)
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__)
#define | SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Typedefs

typedef struct
__SMBUS_HandleTypeDef 		SMBUS_HandleTypeDef
typedef void(* | pSMBUS_CallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus)
HAL SMBUS Callback pointer definition.
typedef void(* | pSMBUS_AddrCallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_SMBUS_CallbackIDTypeDef {
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_SMBUS_ERROR_CB_ID = 0x05U, HAL_SMBUS_MSPINIT_CB_ID = 0x06U, HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
}
HAL SMBUS Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Header file of SMBUS HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_smbus.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smbus_ex.h File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_smbus_ex.h File Reference

Header file of SMBUS HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | SMBUS_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP
#define | SMBUS_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP
#define | SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | IS_SMBUS_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_SMBUSEx_EnableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Enable SMBUS wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_SMBUSEx_DisableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Disable SMBUS wakeup from Stop mode(s).
void | HAL_SMBUSEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the SMBUS fast mode plus driving capability.
void | HAL_SMBUSEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the SMBUS fast mode plus driving capability.

Detailed Description

Header file of SMBUS HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_smbus_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_spi.h File Reference

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stm32g0xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_spi_ex.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)
#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define | SPI_DATASIZE_4BIT (0x00000300U)
#define | SPI_DATASIZE_5BIT (0x00000400U)
#define | SPI_DATASIZE_6BIT (0x00000500U)
#define | SPI_DATASIZE_7BIT (0x00000600U)
#define | SPI_DATASIZE_8BIT (0x00000700U)
#define | SPI_DATASIZE_9BIT (0x00000800U)
#define | SPI_DATASIZE_10BIT (0x00000900U)
#define | SPI_DATASIZE_11BIT (0x00000A00U)
#define | SPI_DATASIZE_12BIT (0x00000B00U)
#define | SPI_DATASIZE_13BIT (0x00000C00U)
#define | SPI_DATASIZE_14BIT (0x00000D00U)
#define | SPI_DATASIZE_15BIT (0x00000E00U)
#define | SPI_DATASIZE_16BIT (0x00000F00U)
#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL
#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA
#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define | SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF
#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_8BIT (0x00000001U)
#define | SPI_CRC_LENGTH_16BIT (0x00000002U)
#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FLAG_MASK
#define | SPI_FTLVL_EMPTY (0x00000000U)
#define | SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define | SPI_FTLVL_HALF_FULL (0x00001000U)
#define | SPI_FTLVL_FULL (0x00001800U)
#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define | SPI_FRLVL_HALF_FULL (0x00000400U)
#define | SPI_FRLVL_FULL (0x00000600U)
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the SPI peripheral.
#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | SPI_CHECK_FLAG(__SR__, __FLAG__)
Check whether the specified SPI flag is set or not.
#define | SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)
Check whether the specified SPI Interrupt is set or not.
#define | IS_SPI_MODE(__MODE__)
Checks if SPI Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION(__MODE__)
Checks if SPI Direction Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
Checks if SPI Direction Mode parameter is 2 lines.
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__)
Checks if SPI Direction Mode parameter is 1 or 2 lines.
#define | IS_SPI_DATASIZE(__DATASIZE__)
Checks if SPI Data Size parameter is in allowed range.
#define | IS_SPI_CPOL(__CPOL__)
Checks if SPI Serial clock steady state parameter is in allowed range.
#define | IS_SPI_CPHA(__CPHA__)
Checks if SPI Clock Phase parameter is in allowed range.
#define | IS_SPI_NSS(__NSS__)
Checks if SPI Slave Select parameter is in allowed range.
#define | IS_SPI_NSSP(__NSSP__)
Checks if SPI NSS Pulse parameter is in allowed range.
#define | IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__)
Checks if SPI Baudrate prescaler parameter is in allowed range.
#define | IS_SPI_FIRST_BIT(__BIT__)
Checks if SPI MSB LSB transmission parameter is in allowed range.
#define | IS_SPI_TIMODE(__MODE__)
Checks if SPI TI mode parameter is in allowed range.
#define | IS_SPI_CRC_CALCULATION(__CALCULATION__)
Checks if SPI CRC calculation enabled state is in allowed range.
#define | IS_SPI_CRC_LENGTH(__LENGTH__)
Checks if SPI CRC length is in allowed range.
#define | IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__)
Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
#define | IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
Checks if DMA handle is valid.

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.
typedef void(* | pSPI_CallbackTypeDef )(SPI_HandleTypeDef *hspi)
HAL SPI Callback pointer definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...
enum HAL_SPI_CallbackIDTypeDef {
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U,
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, HAL_SPI_ERROR_CB_ID = 0x06U, HAL_SPI_ABORT_CB_ID = 0x07U,
HAL_SPI_MSPINIT_CB_ID = 0x08U, HAL_SPI_MSPDEINIT_CB_ID = 0x09U
}
HAL SPI Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_spi.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_spi_ex.h File Reference

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Functions
stm32g0xx_hal_spi_ex.h File Reference

Header file of SPI HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Header file of SPI HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_spi_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_tim.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | __TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_CLEARINPUTSOURCE_NONE 0x10000000U
#define | TIM_CLEARINPUTSOURCE_ETR 0x20000000U
#define | TIM_CLEARINPUTSOURCE_COMP1 0x00000000U
#define | TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR_0
#define | TIM_CLEARINPUTSOURCE_COMP3 TIM1_OR1_OCREF_CLR_1
#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_DCR 0x00000012U
#define | TIM_DMABASE_DMAR 0x00000013U
#define | TIM_DMABASE_OR1 0x00000014U
#define | TIM_DMABASE_CCMR3 0x00000015U
#define | TIM_DMABASE_CCR5 0x00000016U
#define | TIM_DMABASE_CCR6 0x00000017U
#define | TIM_DMABASE_AF1 0x00000018U
#define | TIM_DMABASE_AF2 0x00000019U
#define | TIM_DMABASE_TISEL 0x0000001AU
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U
#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_UIFREMAP_DISABLE 0x00000000U
#define | TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP
#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
#define | TIM_OCIDLESTATE_SET TIM_CR2_OIS1
#define | TIM_OCIDLESTATE_RESET 0x00000000U
#define | TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
#define | TIM_OCNIDLESTATE_RESET 0x00000000U
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
#define | TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
#define | TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
#define | TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
#define | TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
#define | TIM_OPMODE_SINGLE TIM_CR1_OPM
#define | TIM_OPMODE_REPETITIVE 0x00000000U
#define | TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
#define | TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE TIM_DIER_UIE
#define | TIM_IT_CC1 TIM_DIER_CC1IE
#define | TIM_IT_CC2 TIM_DIER_CC2IE
#define | TIM_IT_CC3 TIM_DIER_CC3IE
#define | TIM_IT_CC4 TIM_DIER_CC4IE
#define | TIM_IT_COM TIM_DIER_COMIE
#define | TIM_IT_TRIGGER TIM_DIER_TIE
#define | TIM_IT_BREAK TIM_DIER_BIE
#define | TIM_COMMUTATION_TRGI TIM_CR2_CCUS
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U
#define | TIM_DMA_UPDATE TIM_DIER_UDE
#define | TIM_DMA_CC1 TIM_DIER_CC1DE
#define | TIM_DMA_CC2 TIM_DIER_CC2DE
#define | TIM_DMA_CC3 TIM_DIER_CC3DE
#define | TIM_DMA_CC4 TIM_DIER_CC4DE
#define | TIM_DMA_COM TIM_DIER_COMDE
#define | TIM_DMA_TRIGGER TIM_DIER_TDE
#define | TIM_CCDMAREQUEST_CC 0x00000000U
#define | TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | TIM_FLAG_UPDATE TIM_SR_UIF
#define | TIM_FLAG_CC1 TIM_SR_CC1IF
#define | TIM_FLAG_CC2 TIM_SR_CC2IF
#define | TIM_FLAG_CC3 TIM_SR_CC3IF
#define | TIM_FLAG_CC4 TIM_SR_CC4IF
#define | TIM_FLAG_CC5 TIM_SR_CC5IF
#define | TIM_FLAG_CC6 TIM_SR_CC6IF
#define | TIM_FLAG_COM TIM_SR_COMIF
#define | TIM_FLAG_TRIGGER TIM_SR_TIF
#define | TIM_FLAG_BREAK TIM_SR_BIF
#define | TIM_FLAG_BREAK2 TIM_SR_B2IF
#define | TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
#define | TIM_FLAG_CC1OF TIM_SR_CC1OF
#define | TIM_FLAG_CC2OF TIM_SR_CC2OF
#define | TIM_FLAG_CC3OF TIM_SR_CC3OF
#define | TIM_FLAG_CC4OF TIM_SR_CC4OF
#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_5 0x00000010U
#define | TIM_CHANNEL_6 0x00000014U
#define | TIM_CHANNEL_ALL 0x0000003CU
#define | TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
#define | TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
#define | TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
#define | TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
#define | TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
#define | TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
#define | TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
#define | TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
#define | TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
#define | TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
#define | TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | TIM_OSSR_DISABLE 0x00000000U
#define | TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | TIM_OSSI_DISABLE 0x00000000U
#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | TIM_BREAK_DISABLE 0x00000000U
#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
#define | TIM_BREAK_AFMODE_INPUT 0x00000000U
#define | TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID
#define | TIM_BREAK2_DISABLE 0x00000000U
#define | TIM_BREAK2_ENABLE TIM_BDTR_BK2E
#define | TIM_BREAK2POLARITY_LOW 0x00000000U
#define | TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P
#define | TIM_BREAK2_AFMODE_INPUT 0x00000000U
#define | TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID
#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | TIM_GROUPCH5_NONE 0x00000000U
#define | TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO2_RESET 0x00000000U
#define | TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
#define | TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
#define | TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M
#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 TIM_SMCR_TS_0
#define | TIM_TS_ITR2 TIM_SMCR_TS_1
#define | TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
#define | TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_NONE 0x0000FFFFU
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U
#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
#define | __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
Disable update interrupt flag (UIF) remapping.
#define | __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
Get update interrupt flag (UIF) copy status.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Set the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Reset the TIM Output compare preload.
#define | __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Enable fast mode for a given channel.
#define | __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Disable fast mode for a given channel.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
Select the Capture/compare DMA request source.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_UIFREMAP_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK_AFMODE(__AFMODE__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_AFMODE(__AFMODE__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define | TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__)
#define | TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)
#define | TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define | TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,__CHANNEL_STATE__)

Typedefs

typedef struct __TIM_HandleTypeDef | TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
typedef void(* | pTIM_CallbackTypeDef )(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum | HAL_TIM_ChannelStateTypeDef { HAL_TIM_CHANNEL_STATE_RESET = 0x00U, HAL_TIM_CHANNEL_STATE_READY = 0x01U, HAL_TIM_CHANNEL_STATE_BUSY = 0x02U }
TIM Channel States definition. More...
enum | HAL_TIM_DMABurstStateTypeDef { HAL_DMA_BURST_STATE_RESET = 0x00U, HAL_DMA_BURST_STATE_READY = 0x01U, HAL_DMA_BURST_STATE_BUSY = 0x02U }
DMA Burst States definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...
enum HAL_TIM_CallbackIDTypeDef {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U,
HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U,
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU,
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU,
HAL_TIM_TRIGGER_CB_ID = 0x10U, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U,
HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U, HAL_TIM_ERROR_CB_ID = 0x17U,
HAL_TIM_COMMUTATION_CB_ID = 0x18U, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U, HAL_TIM_BREAK_CB_ID = 0x1AU, HAL_TIM_BREAK2_CB_ID = 0x1BU
}
HAL TIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (const TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (const TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (const TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ActiveChannel | HAL_TIM_GetActiveChannel (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIM_GetChannelState (const TIM_HandleTypeDef *htim, uint32_t Channel)
Return actual state of the TIM channel.
HAL_TIM_DMABurstStateTypeDef | HAL_TIM_DMABurstState (const TIM_HandleTypeDef *htim)
Return actual state of a DMA burst operation.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_tim.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_tim_ex.h File Reference

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stm32g0xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...

Defines

#define | TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
#define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
#define | TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to COMP3 output */
#define | TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define | TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
#define | TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
#define | TIM_TIM2_ETR_LSE (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to LSE */
#define | TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to MCO */
#define | TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to MCO2 */
#define | TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP3 output */
#define | TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define | TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */
#define | TIM_TIM3_ETR_COMP2 TIM3_AF1_ETRSEL_1 /* !< TIM3_ETR is connected to COMP2 output */
#define | TIM_TIM3_ETR_COMP3 (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0) /* !< TIM3_ETR is connected to COMP3 output */
#define | TIM_TIM4_ETR_GPIO 0x00000000U /* !< TIM4_ETR is connected to GPIO */
#define | TIM_TIM4_ETR_COMP1 TIM4_AF1_ETRSEL_0 /* !< TIM4_ETR is connected to COMP1 output */
#define | TIM_TIM4_ETR_COMP2 TIM4_AF1_ETRSEL_1 /* !< TIM4_ETR is connected to COMP2 output */
#define | TIM_TIM4_ETR_COMP3 (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0) /* !< TIM4_ETR is connected to COMP3 output */
#define | TIM_BREAKINPUT_BRK 0x00000001U
#define | TIM_BREAKINPUT_BRK2 0x00000002U
#define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U
#define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U
#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U
#define | TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */
#define | TIM_TIM1_TI1_COMP1 0x00000001U /* !< TIM1_TI1 is connected to COMP1 OUT */
#define | TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */
#define | TIM_TIM1_TI2_COMP2 0x00000100U /* !< TIM1_TI2 is connected to COMP2 OUT */
#define | TIM_TIM1_TI3_GPIO 0x00000000U /* !< TIM1_TI3 is connected to GPIO */
#define | TIM_TIM1_TI3_COMP3 0x00010000U /* !< TIM1_TI3 is connected to COMP3 OUT */
#define | TIM_TIM2_TI1_GPIO 0x00000000U /* !< TIM2_TI1 is connected to GPIO */
#define | TIM_TIM2_TI1_COMP1 0x00000001U /* !< TIM2_TI1 is connected to COMP1 OUT */
#define | TIM_TIM2_TI2_GPIO 0x00000000U /* !< TIM2_TI2 is connected to GPIO */
#define | TIM_TIM2_TI2_COMP2 0x00000100U /* !< TIM2_TI2 is connected to COMP2 OUT */
#define | TIM_TIM2_TI3_GPIO 0x00000000U /* !< TIM2_TI3 is connected to GPIO */
#define | TIM_TIM2_TI3_COMP3 0x00010000U /* !< TIM2_TI3 is connected to COMP3 OUT */
#define | TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */
#define | TIM_TIM3_TI1_COMP1 0x00000001U /* !< TIM3_TI1 is connected to COMP1 OUT */
#define | TIM_TIM3_TI2_GPIO 0x00000000U /* !< TIM3_TI2 is connected to GPIO */
#define | TIM_TIM3_TI2_COMP2 0x00000100U /* !< TIM3_TI2 is connected to COMP2 OUT */
#define | TIM_TIM3_TI3_GPIO 0x00000000U /* !< TIM3_TI3 is connected to GPIO */
#define | TIM_TIM3_TI3_COMP3 0x00010000U /* !< TIM3_TI3 is connected to COMP3 OUT */
#define | TIM_TIM4_TI1_GPIO 0x00000000U /* !< TIM4_TI1 is connected to GPIO */
#define | TIM_TIM4_TI1_COMP1 0x00000001U /* !< TIM4_TI1 is connected to COMP1 OUT */
#define | TIM_TIM4_TI2_GPIO 0x00000000U /* !< TIM4_TI2 is connected to GPIO */
#define | TIM_TIM4_TI2_COMP2 0x00000100U /* !< TIM4_TI2 is connected to COMP2 OUT */
#define | TIM_TIM4_TI3_GPIO 0x00000000U /* !< TIM4_TI3 is connected to GPIO */
#define | TIM_TIM4_TI3_COMP3 0x00010000U /* !< TIM4_TI3 is connected to COMP3 OUT */
#define | TIM_TIM14_TI1_GPIO 0x00000000U /* !< TIM14_TI1 is connected to GPIO */
#define | TIM_TIM14_TI1_RTC 0x00000001U /* !< TIM14_TI1 is connected to RTC clock */
#define | TIM_TIM14_TI1_HSE_32 0x00000002U /* !< TIM14_TI1 is connected to HSE div 32 */
#define | TIM_TIM14_TI1_MCO 0x00000003U /* !< TIM14_TI1 is connected to MCO */
#define | TIM_TIM14_TI1_MCO2 0x00000004U /* !< TIM14_TI1 is connected to MCO2 */
#define | TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
#define | TIM_TIM15_TI1_TIM2_CH1 0x00000001U /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define | TIM_TIM15_TI1_TIM3_CH1 0x00000002U /* !< TIM15_TI1 is connected to TIM3 CH1 */
#define | TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */
#define | TIM_TIM15_TI2_TIM2_CH2 0x00000100U /* !< TIM15_TI2 is connected to TIM2 CH2 */
#define | TIM_TIM15_TI2_TIM3_CH2 0x00000200U /* !< TIM15_TI2 is connected to TIM3 CH2 */
#define | TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to GPIO */
#define | TIM_TIM16_TI1_LSI 0x00000001U /* !< TIM16_TI1 is connected to LSI */
#define | TIM_TIM16_TI1_LSE 0x00000002U /* !< TIM16_TI1 is connected to LSE */
#define | TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /* !< TIM16_TI1 is connected to TRC wakeup interrupt */
#define | TIM_TIM16_TI1_MCO2 0x00000004U /* !< TIM16_TI1 is connected to MCO2 */
#define | TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to GPIO */
#define | TIM_TIM17_TI1_HSI48 0x00000001U /* !< TIM17_TI1 is connected to HSI48/256 */
#define | TIM_TIM17_TI1_HSE_32 0x00000002U /* !< TIM17_TI1 is connected to HSE div 32 */
#define | TIM_TIM17_TI1_MCO 0x00000003U /* !< TIM17_TI1 is connected to MCO */
#define | TIM_TIM17_TI1_MCO2 0x00000004U /* !< TIM17_TI1 is connected to MCO2 */
#define | IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)
#define | IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
HAL_StatusTypeDef | HAL_TIMEx_DisarmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Disarm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_ReArmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Arm the designated break input (when it operates in bidirectional mode).
__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIMEx_GetChannelNState (const TIM_HandleTypeDef *htim, uint32_t ChannelN)
Return actual state of the TIM complementary channel.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.

Detailed Description

Header file of TIM HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_tim_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_uart.h File Reference

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stm32g0xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_uart_ex.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | __UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_UART_STATE_RESET 0x00000000U
#define | HAL_UART_STATE_READY 0x00000020U
#define | HAL_UART_STATE_BUSY 0x00000024U
#define | HAL_UART_STATE_BUSY_TX 0x00000021U
#define | HAL_UART_STATE_BUSY_RX 0x00000022U
#define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_UART_STATE_TIMEOUT 0x000000A0U
#define | HAL_UART_STATE_ERROR 0x000000E0U
#define | HAL_UART_ERROR_NONE (0x00000000U)
#define | HAL_UART_ERROR_PE (0x00000001U)
#define | HAL_UART_ERROR_NE (0x00000002U)
#define | HAL_UART_ERROR_FE (0x00000004U)
#define | HAL_UART_ERROR_ORE (0x00000008U)
#define | HAL_UART_ERROR_DMA (0x00000010U)
#define | HAL_UART_ERROR_RTO (0x00000020U)
#define | HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)
#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1
#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN USART_CR1_PCE
#define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS USART_CR3_RTSE
#define | UART_HWCONTROL_CTS USART_CR3_CTSE
#define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | UART_MODE_RX USART_CR1_RE
#define | UART_MODE_TX USART_CR1_TE
#define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE USART_CR1_UE
#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_OVERSAMPLING_8 USART_CR1_OVER8
#define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | UART_PRESCALER_DIV1 0x00000000U
#define | UART_PRESCALER_DIV2 0x00000001U
#define | UART_PRESCALER_DIV4 0x00000002U
#define | UART_PRESCALER_DIV6 0x00000003U
#define | UART_PRESCALER_DIV8 0x00000004U
#define | UART_PRESCALER_DIV10 0x00000005U
#define | UART_PRESCALER_DIV12 0x00000006U
#define | UART_PRESCALER_DIV16 0x00000007U
#define | UART_PRESCALER_DIV32 0x00000008U
#define | UART_PRESCALER_DIV64 0x00000009U
#define | UART_PRESCALER_DIV128 0x0000000AU
#define | UART_PRESCALER_DIV256 0x0000000BU
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE
#define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
#define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN
#define | UART_LIN_DISABLE 0x00000000U
#define | UART_LIN_ENABLE USART_CR2_LINEN
#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL
#define | UART_DMA_TX_DISABLE 0x00000000U
#define | UART_DMA_TX_ENABLE USART_CR3_DMAT
#define | UART_DMA_RX_DISABLE 0x00000000U
#define | UART_DMA_RX_ENABLE USART_CR3_DMAR
#define | UART_HALF_DUPLEX_DISABLE 0x00000000U
#define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL
#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE
#define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
#define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
#define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | UART_ADVFEATURE_NO_INIT 0x00000000U
#define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | UART_ADVFEATURE_SWAP_INIT 0x00000008U
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
#define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
#define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
#define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
#define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
#define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN
#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
#define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
#define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM
#define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME
#define | UART_CR2_ADDRESS_LSB_POS 24U
#define | UART_WAKEUP_ON_ADDRESS 0x00000000U
#define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS
#define | UART_DE_POLARITY_HIGH 0x00000000U
#define | UART_DE_POLARITY_LOW USART_CR3_DEP
#define | UART_CR1_DEAT_ADDRESS_LSB_POS 21U
#define | UART_CR1_DEDT_ADDRESS_LSB_POS 16U
#define | UART_IT_MASK 0x001FU
#define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE
#define | UART_IT_PE 0x0028U
#define | UART_IT_TXE 0x0727U
#define | UART_IT_TXFNF 0x0727U
#define | UART_IT_TC 0x0626U
#define | UART_IT_RXNE 0x0525U
#define | UART_IT_RXFNE 0x0525U
#define | UART_IT_IDLE 0x0424U
#define | UART_IT_LBD 0x0846U
#define | UART_IT_CTS 0x096AU
#define | UART_IT_CM 0x112EU
#define | UART_IT_WUF 0x1476U
#define | UART_IT_RXFF 0x183FU
#define | UART_IT_TXFE 0x173EU
#define | UART_IT_RXFT 0x1A7CU
#define | UART_IT_TXFT 0x1B77U
#define | UART_IT_RTO 0x0B3AU
#define | UART_IT_ERR 0x0060U
#define | UART_IT_ORE 0x0300U
#define | UART_IT_NE 0x0200U
#define | UART_IT_FE 0x0100U
#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NECF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | HAL_UART_RECEPTION_STANDARD (0x00000000U)
#define | HAL_UART_RECEPTION_TOIDLE (0x00000001U)
#define | HAL_UART_RECEPTION_TORTO (0x00000002U)
#define | HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U)
#define | HAL_UART_RXEVENT_TC (0x00000000U)
#define | HAL_UART_RXEVENT_HT (0x00000001U)
#define | HAL_UART_RXEVENT_IDLE (0x00000002U)
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.
#define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get UART clok division factor from clock prescaler value.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__CLOCKPRESCALER__)
Ensure that UART Prescaler is valid.

Typedefs

typedef uint32_t | HAL_UART_StateTypeDef
HAL UART State definition.
typedef uint32_t | HAL_UART_RxTypeTypeDef
HAL UART Reception type definition.
typedef uint32_t | HAL_UART_RxEventTypeTypeDef
HAL UART Rx Event type definition.
typedef struct __UART_HandleTypeDef | UART_HandleTypeDef
UART handle Structure definition.
typedef void(* | pUART_CallbackTypeDef )(UART_HandleTypeDef *huart)
HAL UART Callback pointer definition.
typedef void(* | pUART_RxEventCallbackTypeDef )(struct __UART_HandleTypeDef *huart, uint16_t Pos)

Enumerations

enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00U, UART_CLOCKSOURCE_HSI = 0x02U, UART_CLOCKSOURCE_SYSCLK = 0x04U, UART_CLOCKSOURCE_LSE = 0x08U,
UART_CLOCKSOURCE_UNDEFINED = 0x10U
}
UART clock sources definition. More...
enum HAL_UART_CallbackIDTypeDef {
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_UART_TX_COMPLETE_CB_ID = 0x01U, HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_UART_RX_COMPLETE_CB_ID = 0x03U,
HAL_UART_ERROR_CB_ID = 0x04U, HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_UART_WAKEUP_CB_ID = 0x08U, HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, HAL_UART_MSPINIT_CB_ID = 0x0BU,
HAL_UART_MSPDEINIT_CB_ID = 0x0CU
}
HAL UART Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_RegisterRxEventCallback (UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
Register a User UART Rx Event Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterRxEventCallback (UART_HandleTypeDef *huart)
UnRegister the UART Rx Event Callback UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
__weak void | HAL_UARTEx_RxEventCallback (UART_HandleTypeDef *huart, uint16_t Size)
Reception Event Callback (Rx event notification called after use of advanced reception service).
void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (const UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (const UART_HandleTypeDef *huart)
Return the UART handle error code.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles UART Communication Timeout.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_Start_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in interrupt mode.
HAL_StatusTypeDef | UART_Start_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in DMA mode.

Variables

const uint16_t | UARTPrescTable [12]

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_uart.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_uart_ex.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_hal_uart_ex.h File Reference

Header file of UART HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...

Defines

#define | UART_WORDLENGTH_7B USART_CR1_M1
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B USART_CR1_M0
#define | UART_ADDRESS_DETECT_4B 0x00000000U
#define | UART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | UART_FIFOMODE_DISABLE 0x00000000U
#define | UART_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | UART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | UART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Functions

HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
HAL_UART_RxEventTypeTypeDef | HAL_UARTEx_GetRxEventType (UART_HandleTypeDef *huart)
Provide Rx Event type that has lead to RxEvent callback execution.

Detailed Description

Header file of UART HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_uart_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_usart.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32g0xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_hal_usart_ex.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | __USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | HAL_USART_ERROR_NONE (0x00000000U)
#define | HAL_USART_ERROR_PE (0x00000001U)
#define | HAL_USART_ERROR_NE (0x00000002U)
#define | HAL_USART_ERROR_FE (0x00000004U)
#define | HAL_USART_ERROR_ORE (0x00000008U)
#define | HAL_USART_ERROR_DMA (0x00000010U)
#define | HAL_USART_ERROR_UDR (0x00000020U)
#define | HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)
#define | HAL_USART_ERROR_RTO (0x00000080U)
#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1
#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN USART_CR1_PCE
#define | USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | USART_MODE_RX USART_CR1_RE
#define | USART_MODE_TX USART_CR1_TE
#define | USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH USART_CR2_CPOL
#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE USART_CR2_CPHA
#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE USART_CR2_LBCL
#define | USART_PRESCALER_DIV1 0x00000000U
#define | USART_PRESCALER_DIV2 0x00000001U
#define | USART_PRESCALER_DIV4 0x00000002U
#define | USART_PRESCALER_DIV6 0x00000003U
#define | USART_PRESCALER_DIV8 0x00000004U
#define | USART_PRESCALER_DIV10 0x00000005U
#define | USART_PRESCALER_DIV12 0x00000006U
#define | USART_PRESCALER_DIV16 0x00000007U
#define | USART_PRESCALER_DIV32 0x00000008U
#define | USART_PRESCALER_DIV64 0x00000009U
#define | USART_PRESCALER_DIV128 0x0000000AU
#define | USART_PRESCALER_DIV256 0x0000000BU
#define | USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | USART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | USART_FLAG_RTOF USART_ISR_RTOF
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE
#define | USART_IT_PE 0x0028U
#define | USART_IT_TXE 0x0727U
#define | USART_IT_TXFNF 0x0727U
#define | USART_IT_TC 0x0626U
#define | USART_IT_RXNE 0x0525U
#define | USART_IT_RXFNE 0x0525U
#define | USART_IT_IDLE 0x0424U
#define | USART_IT_ERR 0x0060U
#define | USART_IT_ORE 0x0300U
#define | USART_IT_NE 0x0200U
#define | USART_IT_FE 0x0100U
#define | USART_IT_RXFF 0x183FU
#define | USART_IT_TXFE 0x173EU
#define | USART_IT_RXFT 0x1A7CU
#define | USART_IT_TXFT 0x1B77U
#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NECF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF
#define | USART_CLEAR_RTOF USART_ICR_RTOCF
#define | USART_IT_MASK 0x001FU
#define | USART_CR_MASK 0x00E0U
#define | USART_CR_POS 5U
#define | USART_ISR_MASK 0x1F00U
#define | USART_ISR_POS 8U
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
Clear SPI slave underrun error flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | USART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get USART clock division factor from clock prescaler value.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__CLOCKPRESCALER__)
Ensure that USART Prescaler is valid.

Typedefs

typedef struct
__USART_HandleTypeDef 		USART_HandleTypeDef
USART handle Structure definition.
typedef void(* | pUSART_CallbackTypeDef )(USART_HandleTypeDef *husart)
HAL USART Callback pointer definition.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00U, USART_CLOCKSOURCE_HSI = 0x02U, USART_CLOCKSOURCE_SYSCLK = 0x04U, USART_CLOCKSOURCE_LSE = 0x08U,
USART_CLOCKSOURCE_UNDEFINED = 0x10U
}
USART clock sources definitions. More...
enum HAL_USART_CallbackIDTypeDef {
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_USART_TX_COMPLETE_CB_ID = 0x01U, HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_USART_RX_COMPLETE_CB_ID = 0x03U,
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, HAL_USART_ERROR_CB_ID = 0x05U, HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U,
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, HAL_USART_MSPINIT_CB_ID = 0x09U, HAL_USART_MSPDEINIT_CB_ID = 0x0AU
}
HAL USART Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an USART Callback USART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (const USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (const USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_usart.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_usart_ex.h File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_usart_ex.h File Reference

Header file of USART HAL Extended module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Defines

#define | USART_WORDLENGTH_7B (USART_CR1_M1)
#define | USART_WORDLENGTH_8B (0x00000000U)
#define | USART_WORDLENGTH_9B (USART_CR1_M0)
#define | USART_NSS_HARD 0x00000000U
#define | USART_NSS_SOFT USART_CR2_DIS_NSS
#define | USART_SLAVEMODE_DISABLE 0x00000000U
#define | USART_SLAVEMODE_ENABLE USART_CR2_SLVEN
#define | USART_FIFOMODE_DISABLE 0x00000000U
#define | USART_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | USART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | USART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.
#define | IS_USART_NSS(__NSS__)
Ensure that USART Negative Slave Select (NSS) pin management is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.

Functions

__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of USART HAL Extended module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_usart_ex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_wwdg.h File Reference

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stm32g0xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32g0xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | __WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB
#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified WWDG interrupt source is enabled or not.

Typedefs

typedef struct __WWDG_HandleTypeDef | WWDG_HandleTypeDef
WWDG handle Structure definition.
typedef void(* | pWWDG_CallbackTypeDef )(WWDG_HandleTypeDef *hppp)
HAL WWDG Callback pointer definition.

Enumerations

enum | HAL_WWDG_CallbackIDTypeDef { HAL_WWDG_EWI_CB_ID = 0x00U, HAL_WWDG_MSPINIT_CB_ID = 0x01U }
HAL WWDG common Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_wwdg.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_adc.h File Reference

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stm32g0xx_ll_adc.h File Reference

Header file of ADC LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...

Defines

#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
#define | ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
#define | ADC_CHANNEL_ID_MASK
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
#define | ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
#define | ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define | ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
#define | ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
#define | ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
#define | ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_15_NUMBER
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
#define | ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
#define | ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
#define | ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
#define | ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
#define | ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define | ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define | ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define | ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define | ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
#define | ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
#define | ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
#define | ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */
#define | ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
#define | ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
#define | ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
#define | ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
#define | ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
#define | ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
#define | ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
#define | ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
#define | ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
#define | ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
#define | ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
#define | ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
#define | ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
#define | ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
#define | ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
#define | ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
#define | ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
#define | ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
#define | ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
#define | ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
#define | ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
#define | ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
#define | ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
#define | ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
#define | ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define | VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL
#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_CCRDY ADC_IER_CCRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE
#define | LL_ADC_IT_EOCAL ADC_IER_EOCALIE
#define | LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL)
#define | LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN)
#define | LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC (0x00000000UL)
#define | LL_ADC_RESOLUTION_12B (0x00000000UL)
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 )
#define | LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)
#define | LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN)
#define | LL_ADC_LP_MODE_NONE (0x00000000UL)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT)
#define | LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF)
#define | LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)
#define | LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL)
#define | LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG)
#define | LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS)
#define | LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK)
#define | LL_ADC_GROUP_REGULAR (0x00000001UL)
#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD )
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD )
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD )
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD )
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD )
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD )
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD )
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD )
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD )
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD )
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD)
#define | LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 )
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0)
#define | LL_ADC_REG_CONV_SINGLE (0x00000000UL)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT)
#define | LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
#define | LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD)
#define | LL_ADC_REG_SEQ_FIXED (0x00000000UL)
#define | LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD)
#define | LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR)
#define | LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN)
#define | LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0)
#define | LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1)
#define | LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0)
#define | LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2)
#define | LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0)
#define | LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1)
#define | LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0)
#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define | LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)
#define | LL_ADC_AWD_DISABLE (0x00000000UL)
#define | LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR1_AWD1EN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 )
#define | LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1)
#define | LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1)
#define | LL_ADC_OVS_DISABLE (0x00000000UL)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE)
#define | LL_ADC_OVS_REG_CONT (0x00000000UL)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS)
#define | LL_ADC_OVS_RATIO_2 (0x00000000UL)
#define | LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )
#define | LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define | LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
#define | LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */
#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)
#define | LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)
#define | LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL)
#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.
#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC1_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) LL_ADC_IsEnabled(ADC1)
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Functions

__STATIC_INLINE uint32_t | LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonFrequencyMode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonFrequencyMode)
Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonFrequencyMode (ADC_Common_TypeDef *ADCxy_COMMON)
Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalChAdd (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalChRem (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetClock (ADC_TypeDef *ADCx, uint32_t ClockSource)
Set ADC instance clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetClock (ADC_TypeDef *ADCx)
Get ADC instance clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationFactor (ADC_TypeDef *ADCx)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetTriggerFrequencyMode (ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
Set ADC trigger frequency mode.
__STATIC_INLINE uint32_t | LL_ADC_GetTriggerFrequencyMode (ADC_TypeDef *ADCx)
Get ADC trigger frequency mode.
__STATIC_INLINE void | LL_ADC_SetSamplingTimeCommonChannels (ADC_TypeDef *ADCx, uint32_t SamplingTimeY, uint32_t SamplingTime)
Set sampling time common to a group of channels.
__STATIC_INLINE uint32_t | LL_ADC_GetSamplingTimeCommonChannels (ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
Get sampling time common to a group of channels.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerConfigurable (ADC_TypeDef *ADCx, uint32_t Configurability)
Set ADC group regular sequencer configuration flexibility.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerConfigurable (ADC_TypeDef *ADCx)
Get ADC group regular sequencer configuration flexibility.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerScanDirection (ADC_TypeDef *ADCx, uint32_t ScanDirection)
Set ADC group regular sequencer scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerScanDirection (ADC_TypeDef *ADCx)
Get ADC group regular sequencer scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerChannels (ADC_TypeDef *ADCx, uint32_t Channel)
Set ADC group regular sequence: channel on rank corresponding to channel number.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerChAdd (ADC_TypeDef *ADCx, uint32_t Channel)
Add channel to ADC group regular sequence: channel on rank corresponding to channel number.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerChRem (ADC_TypeDef *ADCx, uint32_t Channel)
Remove channel to ADC group regular sequence: channel on rank corresponding to channel number.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerChannels (ADC_TypeDef *ADCx)
Get ADC group regular sequence: channel on rank corresponding to channel number.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
Get ADC oversampling scope.
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
Get ADC oversampling ratio.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
Get ADC oversampling shift.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.
__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData6 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_CCRDY (ADC_TypeDef *ADCx)
Get flag ADC channel configuration ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOCAL (ADC_TypeDef *ADCx)
Get flag ADC end of calibration.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_CCRDY (ADC_TypeDef *ADCx)
Clear flag ADC channel configuration ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOCAL (ADC_TypeDef *ADCx)
Clear flag ADC end of calibration.
__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_CCRDY (ADC_TypeDef *ADCx)
Enable interruption ADC channel configuration ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_EnableIT_EOCAL (ADC_TypeDef *ADCx)
Enable interruption ADC end of calibration.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_CCRDY (ADC_TypeDef *ADCx)
Disable interruption ADC channel configuration ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_EOCAL (ADC_TypeDef *ADCx)
Disable interruption ADC end of calibration.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_CCRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC channel configuration ready.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOCAL (ADC_TypeDef *ADCx)
Get state of interruption ADC end of calibration (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *pADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_adc.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_bus.h File Reference

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Defines | Functions
stm32g0xx_ll_bus.h File Reference

Header file of BUS LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
#define | LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
#define | LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN
#define | LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APBENR1_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APBENR1_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APBENR1_TIM7EN
#define | LL_APB1_GRP1_PERIPH_LPUART2 RCC_APBENR1_LPUART2EN
#define | LL_APB1_GRP1_PERIPH_USART5 RCC_APBENR1_USART5EN
#define | LL_APB1_GRP1_PERIPH_USART6 RCC_APBENR1_USART6EN
#define | LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
#define | LL_APB1_GRP1_PERIPH_FDCAN RCC_APBENR1_FDCANEN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APBENR1_SPI3EN
#define | LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN
#define | LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN
#define | LL_APB1_GRP1_PERIPH_LPUART1 RCC_APBENR1_LPUART1EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APBENR1_I2C3EN
#define | LL_APB1_GRP1_PERIPH_CEC RCC_APBENR1_CECEN
#define | LL_APB1_GRP1_PERIPH_UCPD1 RCC_APBENR1_UCPD1EN
#define | LL_APB1_GRP1_PERIPH_UCPD2 RCC_APBENR1_UCPD2EN
#define | LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
#define | LL_APB1_GRP1_PERIPH_DAC1 RCC_APBENR1_DAC1EN
#define | LL_APB1_GRP1_PERIPH_LPTIM2 RCC_APBENR1_LPTIM2EN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIM1EN
#define | LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APBENR2_TIM1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APBENR2_SPI1EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APBENR2_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM14 RCC_APBENR2_TIM14EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APBENR2_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APBENR2_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APBENR2_TIM17EN
#define | LL_APB2_GRP1_PERIPH_ADC RCC_APBENR2_ADCEN
#define | LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define | LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
#define | LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
#define | LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN
#define | LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN
#define | LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN
#define | LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_IOP_GRP1_EnableClock (uint32_t Periphs)
Enable IOP peripherals clock.
__STATIC_INLINE uint32_t | LL_IOP_GRP1_IsEnabledClock (uint32_t Periphs)
Check if IOP peripheral clock is enabled or not.
__STATIC_INLINE void | LL_IOP_GRP1_DisableClock (uint32_t Periphs)
Disable IOP peripherals clock.
__STATIC_INLINE void | LL_IOP_GRP1_ForceReset (uint32_t Periphs)
Disable IOP peripherals clock.
__STATIC_INLINE void | LL_IOP_GRP1_ReleaseReset (uint32_t Periphs)
Release IOP peripherals reset.
__STATIC_INLINE void | LL_IOP_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable IOP peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_IOP_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable IOP peripheral clocks in Sleep and Stop modes.

Detailed Description

Header file of BUS LL module.

Author:
MCD Application Team
                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_bus.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_comp.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32g0xx_ll_comp.h File Reference

Header file of COMP LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...

Defines

#define | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...) defined as reference register */
#define | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) offset vs register of COMP instance odd */
#define | LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
#define | LL_COMP_WINDOWMODE_COMPX_SETTING_MASK (COMP_CSR_WINMODE)
#define | LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK (COMP_CSR_WINOUT)
#define | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK (COMP_CSR_WINOUT << 1UL)
#define | LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW (1UL)
#define | LL_COMP_WINDOWMODE_BITOFFSET_POS (11UL) /* Value equivalent to POSITION_VAL(COMP_CSR_WINMODE) */
#define | LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
#define | __COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
#define | LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)
#define | LL_COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL)
#define | LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)
#define | LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
#define | LL_COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)
#define | LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK)
#define | LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)
#define | LL_COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_INMSEL_3 )
#define | LL_COMP_HYSTERESIS_NONE (0x00000000UL)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)
#define | LL_COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | LL_COMP_BLANKINGSRC_TIM1_OC4 (COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_2)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKING_3)
#define | LL_COMP_BLANKINGSRC_TIM15_OC2 (COMP_CSR_BLANKING_4)
#define | LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
#define | LL_COMP_DELAY_STARTUP_US ( 80UL)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)
#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in COMP register.
#define | __LL_COMP_COMMON_INSTANCE(__COMPx__)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).
__STATIC_INLINE void | LL_COMP_SetCommonWindowOutput (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput)
Set window output of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowOutput (COMP_Common_TypeDef *COMPxy_COMMON)
Get window output of a pair of comparators instances (2 consecutive COMP instances COMP<x> and COMP<x+1>).
__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.
__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.
__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (COMP_TypeDef *COMPx)
Get comparator instance blanking source.
__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.
ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

Header file of COMP LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_comp.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_cortex.h File Reference

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Defines | Functions
stm32g0xx_ll_cortex.h File Reference

Header file of CORTEX LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | LL_MPU_REGION_NUMBER0 0x00U
#define | LL_MPU_REGION_NUMBER1 0x01U
#define | LL_MPU_REGION_NUMBER2 0x02U
#define | LL_MPU_REGION_NUMBER3 0x03U
#define | LL_MPU_REGION_NUMBER4 0x04U
#define | LL_MPU_REGION_NUMBER5 0x05U
#define | LL_MPU_REGION_NUMBER6 0x06U
#define | LL_MPU_REGION_NUMBER7 0x07U
#define | LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)
#define | LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)
#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00U
#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00U
#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetArchitecture (void)
Get Architecture number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Detailed Description

Header file of CORTEX LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL CORTEX driver contains a set of generic APIs that can be
    used by user:
      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
          functions
      (+) Low power mode configuration (SCB register of Cortex-MCU)
      (+) MPU API to configure and enable regions
      (+) API to access to MCU info (CPUID register)
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_cortex.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_crc.h File Reference

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Defines | Functions
stm32g0xx_ll_crc.h File Reference

Header file of CRC LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)
#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)
#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT
#define | LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U
#define | LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.
__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.
ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

Header file of CRC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_crc.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_crs.h File Reference

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stm32g0xx_ll_crs.h File Reference

CRS LL module driver. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define | LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define | LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define | LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define | LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define | LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define | LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
#define | LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define | LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define | LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define | LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
#define | LL_CRS_SYNC_DIV_1 0x00000000U
#define | LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0
#define | LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1
#define | LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2
#define | LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV
#define | LL_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1
#define | LL_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
#define | LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U
#define | LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR
#define | LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
Reset value of the RELOAD field.
#define | LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
Reset value of Frequency error limit.
#define | LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
Reset value of the HSI48 Calibration field.
#define | LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRS register.
#define | LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRS register.
#define | __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Functions

__STATIC_INLINE void | LL_CRS_EnableFreqErrorCounter (void)
Enable Frequency error counter.
__STATIC_INLINE void | LL_CRS_DisableFreqErrorCounter (void)
Disable Frequency error counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledFreqErrorCounter (void)
Check if Frequency error counter is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableAutoTrimming (void)
Enable Automatic trimming counter.
__STATIC_INLINE void | LL_CRS_DisableAutoTrimming (void)
Disable Automatic trimming counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledAutoTrimming (void)
Check if Automatic trimming is enabled or not.
__STATIC_INLINE void | LL_CRS_SetHSI48SmoothTrimming (uint32_t Value)
Set HSI48 oscillator smooth trimming.
__STATIC_INLINE uint32_t | LL_CRS_GetHSI48SmoothTrimming (void)
Get HSI48 oscillator smooth trimming.
__STATIC_INLINE void | LL_CRS_SetReloadCounter (uint32_t Value)
Set counter reload value.
__STATIC_INLINE uint32_t | LL_CRS_GetReloadCounter (void)
Get counter reload value.
__STATIC_INLINE void | LL_CRS_SetFreqErrorLimit (uint32_t Value)
Set frequency error limit.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorLimit (void)
Get frequency error limit.
__STATIC_INLINE void | LL_CRS_SetSyncDivider (uint32_t Divider)
Set division factor for SYNC signal.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncDivider (void)
Get division factor for SYNC signal.
__STATIC_INLINE void | LL_CRS_SetSyncSignalSource (uint32_t Source)
Set SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncSignalSource (void)
Get SYNC signal source.
__STATIC_INLINE void | LL_CRS_SetSyncPolarity (uint32_t Polarity)
Set input polarity for the SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncPolarity (void)
Get input polarity for the SYNC signal source.
__STATIC_INLINE void | LL_CRS_ConfigSynchronization (uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
Configure CRS for the synchronization.
__STATIC_INLINE void | LL_CRS_GenerateEvent_SWSYNC (void)
Generate software SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorDirection (void)
Get the frequency error direction latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorCapture (void)
Get the frequency error counter value latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCOK (void)
Check if SYNC event OK signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCWARN (void)
Check if SYNC warning signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ERR (void)
Check if Synchronization or trimming error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ESYNC (void)
Check if Expected SYNC signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCERR (void)
Check if SYNC error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCMISS (void)
Check if SYNC missed error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_TRIMOVF (void)
Check if Trimming overflow or underflow occurred or not.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCOK (void)
Clear the SYNC event OK flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCWARN (void)
Clear the SYNC warning flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ERR (void)
Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ESYNC (void)
Clear Expected SYNC flag.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCOK (void)
Enable SYNC event OK interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCOK (void)
Disable SYNC event OK interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCOK (void)
Check if SYNC event OK interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCWARN (void)
Enable SYNC warning interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCWARN (void)
Disable SYNC warning interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCWARN (void)
Check if SYNC warning interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ERR (void)
Enable Synchronization or trimming error interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ERR (void)
Disable Synchronization or trimming error interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ERR (void)
Check if Synchronization or trimming error interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ESYNC (void)
Enable Expected SYNC interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ESYNC (void)
Disable Expected SYNC interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ESYNC (void)
Check if Expected SYNC interrupt is enabled or not.
ErrorStatus | LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.

Detailed Description

CRS LL module driver.

Header file of CRS LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_crs.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dac.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_ll_dac.h File Reference

Header file of DAC LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...

Defines

#define | DAC_CR_CH1_BITOFFSET
#define | DAC_CR_CH2_BITOFFSET
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET
#define | DAC_REG_DHR8R1_REGOFFSET
#define | DAC_REG_DHR12R2_REGOFFSET
#define | DAC_REG_DHR12L2_REGOFFSET
#define | DAC_REG_DHR8R2_REGOFFSET
#define | DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define | DAC_REG_DHRX_REGOFFSET_MASK
#define | DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define | DAC_REG_SHSR2_REGOFFSET
#define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define | DAC_REG_DHR_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_DORX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0
#define | DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_DORX_REGOFFSET_BITOFFSET_POS
#define | DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
#define | DAC_DIGITAL_SCALE_12BITS
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
#define | LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
#define | LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)
#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)
#define | LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)
#define | LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL
#define | LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)
#define | LL_DAC_TRIG_SOFTWARE 0x00000000UL
#define | LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 )
#define | LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL
#define | LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)
#define | LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)
#define | LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL
#define | LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)
#define | LL_DAC_RESOLUTION_12B 0x00000000UL
#define | LL_DAC_RESOLUTION_8B 0x00000002UL
#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL
#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.
#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Functions

__STATIC_INLINE void | LL_DAC_SetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
Set the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE uint32_t | LL_DAC_GetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE void | LL_DAC_SetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
Set the offset trimming value for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the offset trimming value for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_ConfigOutput (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
Set the output for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
Set the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
Set the output connection for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output connection for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
Set the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
Set the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
Set the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL1 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL2 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST1 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST2 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.
ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC channel.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

Header file of DAC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_dac.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dma.h File Reference

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stm32g0xx_ll_dma.h File Reference

Header file of DMA LL module. More...

#include "stm32g0xx.h"
#include "stm32g0xx_ll_dmamux.h"

Go to the source code of this file.

Data Structures

struct | LL_DMA_InitTypeDef

Defines

#define | __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
Helper macro to convert DMA Instance DMAx into DMAMUX channel.
#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7
#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7
#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE
#define | LL_DMA_CHANNEL_1 0x00000000U
#define | LL_DMA_CHANNEL_2 0x00000001U
#define | LL_DMA_CHANNEL_3 0x00000002U
#define | LL_DMA_CHANNEL_4 0x00000003U
#define | LL_DMA_CHANNEL_5 0x00000004U
#define | LL_DMA_CHANNEL_6 0x00000005U
#define | LL_DMA_CHANNEL_7 0x00000006U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U
#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC
#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U
#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U
#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL
#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.
#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
Set DMA request for DMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA request for DMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.
ErrorStatus | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
ErrorStatus | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Variables

static const uint8_t | CHANNEL_OFFSET_TAB []

Detailed Description

Header file of DMA LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_dma.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dmamux.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
  • Inc
Defines | Functions
stm32g0xx_ll_dmamux.h File Reference

Header file of DMAMUX LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | DMAMUX_CCR_SIZE 0x00000004UL
#define | DMAMUX_RGCR_SIZE 0x00000004UL
#define | LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0
#define | LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1
#define | LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2
#define | LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3
#define | LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4
#define | LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5
#define | LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6
#define | LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7
#define | LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8
#define | LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9
#define | LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10
#define | LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11
#define | LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0
#define | LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1
#define | LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2
#define | LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3
#define | LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0
#define | LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1
#define | LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2
#define | LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3
#define | LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4
#define | LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5
#define | LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6
#define | LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7
#define | LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8
#define | LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9
#define | LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10
#define | LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11
#define | LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0
#define | LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1
#define | LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2
#define | LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3
#define | LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE
#define | LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE
#define | LL_DMAMUX_REQ_MEM2MEM 0x00000000U
#define | LL_DMAMUX_REQ_GENERATOR0 0x00000001U
#define | LL_DMAMUX_REQ_GENERATOR1 0x00000002U
#define | LL_DMAMUX_REQ_GENERATOR2 0x00000003U
#define | LL_DMAMUX_REQ_GENERATOR3 0x00000004U
#define | LL_DMAMUX_REQ_ADC1 0x00000005U
#define | LL_DMAMUX_REQ_AES_IN 0x00000006U
#define | LL_DMAMUX_REQ_AES_OUT 0x00000007U
#define | LL_DMAMUX_REQ_DAC1_CH1 0x00000008U
#define | LL_DMAMUX_REQ_DAC1_CH2 0x00000009U
#define | LL_DMAMUX_REQ_I2C1_RX 0x0000000AU
#define | LL_DMAMUX_REQ_I2C1_TX 0x0000000BU
#define | LL_DMAMUX_REQ_I2C2_RX 0x0000000CU
#define | LL_DMAMUX_REQ_I2C2_TX 0x0000000DU
#define | LL_DMAMUX_REQ_LPUART1_RX 0x0000000EU
#define | LL_DMAMUX_REQ_LPUART1_TX 0x0000000FU
#define | LL_DMAMUX_REQ_SPI1_RX 0x00000010U
#define | LL_DMAMUX_REQ_SPI1_TX 0x00000011U
#define | LL_DMAMUX_REQ_SPI2_RX 0x00000012U
#define | LL_DMAMUX_REQ_SPI2_TX 0x00000013U
#define | LL_DMAMUX_REQ_TIM1_CH1 0x00000014U
#define | LL_DMAMUX_REQ_TIM1_CH2 0x00000015U
#define | LL_DMAMUX_REQ_TIM1_CH3 0x00000016U
#define | LL_DMAMUX_REQ_TIM1_CH4 0x00000017U
#define | LL_DMAMUX_REQ_TIM1_TRIG_COM 0x00000018U
#define | LL_DMAMUX_REQ_TIM1_UP 0x00000019U
#define | LL_DMAMUX_REQ_TIM2_CH1 0x0000001AU
#define | LL_DMAMUX_REQ_TIM2_CH2 0x0000001BU
#define | LL_DMAMUX_REQ_TIM2_CH3 0x0000001CU
#define | LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU
#define | LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU
#define | LL_DMAMUX_REQ_TIM2_UP 0x0000001FU
#define | LL_DMAMUX_REQ_TIM3_CH1 0x00000020U
#define | LL_DMAMUX_REQ_TIM3_CH2 0x00000021U
#define | LL_DMAMUX_REQ_TIM3_CH3 0x00000022U
#define | LL_DMAMUX_REQ_TIM3_CH4 0x00000023U
#define | LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U
#define | LL_DMAMUX_REQ_TIM3_UP 0x00000025U
#define | LL_DMAMUX_REQ_TIM6_UP 0x00000026U
#define | LL_DMAMUX_REQ_TIM7_UP 0x00000027U
#define | LL_DMAMUX_REQ_TIM15_CH1 0x00000028U
#define | LL_DMAMUX_REQ_TIM15_CH2 0x00000029U
#define | LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU
#define | LL_DMAMUX_REQ_TIM15_UP 0x0000002BU
#define | LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU
#define | LL_DMAMUX_REQ_TIM16_COM 0x0000002DU
#define | LL_DMAMUX_REQ_TIM16_UP 0x0000002EU
#define | LL_DMAMUX_REQ_TIM17_CH1 0x0000002FU
#define | LL_DMAMUX_REQ_TIM17_COM 0x00000030U
#define | LL_DMAMUX_REQ_TIM17_UP 0x00000031U
#define | LL_DMAMUX_REQ_USART1_RX 0x00000032U
#define | LL_DMAMUX_REQ_USART1_TX 0x00000033U
#define | LL_DMAMUX_REQ_USART2_RX 0x00000034U
#define | LL_DMAMUX_REQ_USART2_TX 0x00000035U
#define | LL_DMAMUX_REQ_USART3_RX 0x00000036U
#define | LL_DMAMUX_REQ_USART3_TX 0x00000037U
#define | LL_DMAMUX_REQ_USART4_RX 0x00000038U
#define | LL_DMAMUX_REQ_USART4_TX 0x00000039U
#define | LL_DMAMUX_REQ_UCPD1_RX 0x0000003AU
#define | LL_DMAMUX_REQ_UCPD1_TX 0x0000003BU
#define | LL_DMAMUX_REQ_UCPD2_RX 0x0000003CU
#define | LL_DMAMUX_REQ_UCPD2_TX 0x0000003DU
#define | LL_DMAMUX_REQ_I2C3_RX 0x0000003EU
#define | LL_DMAMUX_REQ_I2C3_TX 0x0000003FU
#define | LL_DMAMUX_REQ_LPUART2_RX 0x00000040U
#define | LL_DMAMUX_REQ_LPUART2_TX 0x00000041U
#define | LL_DMAMUX_REQ_SPI3_RX 0x00000042U
#define | LL_DMAMUX_REQ_SPI3_TX 0x00000043U
#define | LL_DMAMUX_REQ_TIM4_CH1 0x00000044U
#define | LL_DMAMUX_REQ_TIM4_CH2 0x00000045U
#define | LL_DMAMUX_REQ_TIM4_CH3 0x00000046U
#define | LL_DMAMUX_REQ_TIM4_CH4 0x00000047U
#define | LL_DMAMUX_REQ_TIM4_TRIG 0x00000048U
#define | LL_DMAMUX_REQ_TIM4_UP 0x00000049U
#define | LL_DMAMUX_REQ_USART5_RX 0x0000004AU
#define | LL_DMAMUX_REQ_USART5_TX 0x0000004BU
#define | LL_DMAMUX_REQ_USART6_RX 0x0000004CU
#define | LL_DMAMUX_REQ_USART6_TX 0x0000004DU
#define | LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX
#define | LL_DMAMUX_CHANNEL_0 0x00000000U
#define | LL_DMAMUX_CHANNEL_1 0x00000001U
#define | LL_DMAMUX_CHANNEL_2 0x00000002U
#define | LL_DMAMUX_CHANNEL_3 0x00000003U
#define | LL_DMAMUX_CHANNEL_4 0x00000004U
#define | LL_DMAMUX_CHANNEL_5 0x00000005U
#define | LL_DMAMUX_CHANNEL_6 0x00000006U
#define | LL_DMAMUX_CHANNEL_7 0x00000007U
#define | LL_DMAMUX_CHANNEL_8 0x00000008U
#define | LL_DMAMUX_CHANNEL_9 0x00000009U
#define | LL_DMAMUX_CHANNEL_10 0x0000000AU
#define | LL_DMAMUX_CHANNEL_11 0x0000000BU
#define | LL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0
#define | LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1
#define | LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0
#define | LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1
#define | LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2
#define | LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3
#define | LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4
#define | LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_REQ_GEN_0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_1 0x00000001U
#define | LL_DMAMUX_REQ_GEN_2 0x00000002U
#define | LL_DMAMUX_REQ_GEN_3 0x00000003U
#define | LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0
#define | LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1
#define | LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMAMUX register.
#define | LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMAMUX register.

Functions

__STATIC_INLINE void | LL_DMAMUX_SetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
Set DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_SetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE void | LL_DMAMUX_SetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE void | LL_DMAMUX_EnableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Event Generation on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Event Generation on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Event Generation on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the synchronization mode.
__STATIC_INLINE void | LL_DMAMUX_DisableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the synchronization mode.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the synchronization mode is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
Set DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_EnableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generator.
__STATIC_INLINE void | LL_DMAMUX_DisableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generator.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generator is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE void | LL_DMAMUX_SetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE void | LL_DMAMUX_SetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Detailed Description

Header file of DMAMUX LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_dmamux.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_exti.h File Reference

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stm32g0xx_ll_exti.h File Reference

Header file of EXTI LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_EXTI_InitTypeDef

Defines

#define | LL_EXTI_REGISTER_PINPOS_SHFT 16u
#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR1_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR1_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_31 EXTI_IMR1_IM31
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM
#define | LL_EXTI_LINE_32 EXTI_IMR2_IM32
#define | LL_EXTI_LINE_33 EXTI_IMR2_IM33
#define | LL_EXTI_LINE_34 EXTI_IMR2_IM34
#define | LL_EXTI_LINE_35 EXTI_IMR2_IM35
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM
#define | LL_EXTI_LINE_ALL 0xFFFFFFFFU
#define | LL_EXTI_LINE_NONE 0x00000000U
#define | LL_EXTI_CONFIG_PORTA 0U
#define | LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0
#define | LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1
#define | LL_EXTI_CONFIG_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0)
#define | LL_EXTI_CONFIG_PORTE EXTI_EXTICR1_EXTI0_2
#define | LL_EXTI_CONFIG_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0)
#define | LL_EXTI_CONFIG_LINE0 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)
#define | LL_EXTI_CONFIG_LINE1 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)
#define | LL_EXTI_CONFIG_LINE2 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)
#define | LL_EXTI_CONFIG_LINE3 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)
#define | LL_EXTI_CONFIG_LINE4 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)
#define | LL_EXTI_CONFIG_LINE5 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)
#define | LL_EXTI_CONFIG_LINE6 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)
#define | LL_EXTI_CONFIG_LINE7 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)
#define | LL_EXTI_CONFIG_LINE8 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)
#define | LL_EXTI_CONFIG_LINE9 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)
#define | LL_EXTI_CONFIG_LINE10 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)
#define | LL_EXTI_CONFIG_LINE11 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)
#define | LL_EXTI_CONFIG_LINE12 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)
#define | LL_EXTI_CONFIG_LINE13 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)
#define | LL_EXTI_CONFIG_LINE14 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)
#define | LL_EXTI_CONFIG_LINE15 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)
#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)
#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFallingFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFallingFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFallingFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Falling Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFallingFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Falling Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFallingFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Falling Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFallingFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Falling Flags for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveRisingFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveRisingFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadRisingFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Rising Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadRisingFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Rising Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearRisingFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Rising Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearRisingFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Rising Flags for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_EXTI_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

Header file of EXTI LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_exti.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_gpio.h File Reference

  • File List
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stm32g0xx_ll_gpio.h File Reference

Header file of GPIO LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL
#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0
#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0
#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0
#define | LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define | LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define | LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define | LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1
#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.
__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.
ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

Header file of GPIO LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_gpio.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_i2c.h File Reference

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stm32g0xx_ll_i2c.h File Reference

Header file of I2C LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_I2C_InitTypeDef

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF
#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY
#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE
#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN
#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10
#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE
#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07
#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK
#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10
#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN
#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_10BIT_READ
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR
#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE
#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT
#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.
#define | __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extended Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.
__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

Header file of I2C LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_i2c.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_iwdg.h File Reference

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Defines | Functions
stm32g0xx_ll_iwdg.h File Reference

Header file of IWDG LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U
#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU
#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Detailed Description

Header file of IWDG LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_iwdg.h.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_lptim.h File Reference

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stm32g0xx_ll_lptim.h File Reference

Header file of LPTIM LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN
#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE
#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT
#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE
#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL
#define | LL_LPTIM_PRESCALER_DIV1 0x00000000U
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL
#define | LL_LPTIM_TRIG_SOURCE_COMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_FILTER_NONE 0x00000000U
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT
#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL
#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT
#define | LL_LPTIM_CLK_POLARITY_RISING 0x00000000U
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_ENCODER_MODE_RISING 0x00000000U
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0
#define | LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1
#define | LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)
#define | LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0
#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in LPTIM register.

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.
__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (const LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_EnableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Enable reset after read.
__STATIC_INLINE void | LL_LPTIM_DisableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Disable reset after read.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledResetAfterRead (const LPTIM_TypeDef *LPTIMx)
Indicate whether the reset after read feature is enabled.
__STATIC_INLINE void | LL_LPTIM_ResetCounter (LPTIM_TypeDef *LPTIMx)
Reset of the LPTIM_CNT counter register (synchronous).
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (const LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (const LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (const LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (const LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (const LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (const LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (const LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (const LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.
__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (const LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (const LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (const LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.
__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (const LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (const LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (const LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (const LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (const LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (const LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (const LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (const LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (const LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (const LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (const LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (const LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (const LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (const LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (const LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (const LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Detailed Description

Header file of LPTIM LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_lptim.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_lpuart.h File Reference

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stm32g0xx_ll_lpuart.h File Reference

Header file of LPUART LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...

Defines

#define | LPUART_LPUARTDIV_FREQ_MUL 256U
#define | LPUART_BRR_MASK 0x000FFFFFU
#define | LPUART_BRR_MIN_VALUE 0x00000300U
#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NECF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF
#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_ISR_TXFE USART_ISR_TXFE
#define | LL_LPUART_ISR_RXFF USART_ISR_RXFF
#define | LL_LPUART_ISR_RXFT USART_ISR_RXFT
#define | LL_LPUART_ISR_TXFT USART_ISR_TXFT
#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE
#define | LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U
#define | LL_LPUART_DIRECTION_NONE 0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_LPUART_PARITY_NONE 0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_LPUART_WAKEUP_IDLELINE 0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B 0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0
#define | LL_LPUART_PRESCALER_DIV1 0x00000000U
#define | LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV6
#define | LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_LPUART_PRESCALER_DIV10
#define | LL_LPUART_PRESCALER_DIV12
#define | LL_LPUART_PRESCALER_DIV16
#define | LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_LPUART_PRESCALER_DIV64
#define | LL_LPUART_PRESCALER_DIV128
#define | LL_LPUART_PRESCALER_DIV256
#define | LL_LPUART_STOPBITS_1 0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_LPUART_TXRX_STANDARD 0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_LPUART_BITORDER_LSBFIRST 0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_LPUART_HWCONTROL_NONE 0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_LPUART_DE_POLARITY_HIGH 0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.
#define | __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)
#define | LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
#define | LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
#define | LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
#define | LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
#define | LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
#define | LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
#define | LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
#define | LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (const USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_LPUART_DisableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledFIFO (const USART_TypeDef *LPUARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetTXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXFIFOThreshold (const USART_TypeDef *LPUARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_SetRXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXFIFOThreshold (const USART_TypeDef *LPUARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_ConfigFIFOsThreshold (USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (const USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (const USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (const USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (const USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (const USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (const USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetPrescaler (USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_LPUART_GetPrescaler (const USART_TypeDef *LPUARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (const USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (const USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (const USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (const USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (const USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (const USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (const USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (const USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (const USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (const USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (const USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.
__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (const USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (const USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (const USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (const USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (const USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (const USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (const USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (const USART_TypeDef *LPUARTx)
Check if the LPUART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (const USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (const USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE_RXFNE (const USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE_TXFNF (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (const USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (const USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (const USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (const USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (const USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (const USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFE (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFF (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFT (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFT (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFE (USART_TypeDef *LPUARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFF (USART_TypeDef *LPUARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFT (USART_TypeDef *LPUARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFT (USART_TypeDef *LPUARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFE (USART_TypeDef *LPUARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFF (USART_TypeDef *LPUARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFT (USART_TypeDef *LPUARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFT (USART_TypeDef *LPUARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (const USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE_RXFNE (const USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (const USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE_TXFNF (const USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (const USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (const USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFE (const USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFF (const USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (const USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (const USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (const USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFT (const USART_TypeDef *LPUARTx)
Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFT (const USART_TypeDef *LPUARTx)
Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (const USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (const USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (const USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (const USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (const USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (const USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data and FIFO flush.
ErrorStatus | LL_LPUART_DeInit (const USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Variables

static const uint16_t | LPUART_PRESCALER_TAB []

Detailed Description

Header file of LPUART LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_lpuart.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_pwr.h File Reference

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Defines | Functions
stm32g0xx_ll_pwr.h File Reference

Header file of PWR LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | LL_PWR_SCR_CSBF PWR_SCR_CSBF
#define | LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define | LL_PWR_SCR_CWUF6 PWR_SCR_CWUF6
#define | LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define | LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define | LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define | LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define | LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
#define | LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define | LL_PWR_SR1_SBF PWR_SR1_SBF
#define | LL_PWR_SR1_WUF6 PWR_SR1_WUF6
#define | LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define | LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define | LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define | LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define | LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#define | LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define | LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define | LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define | LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
#define | LL_PWR_REGU_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1
#define | LL_PWR_MODE_STOP0 (0x00000000UL)
#define | LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
#define | LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)
#define | LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
#define | LL_PWR_PVDLLEVEL_0 0x000000000u /* VPVD0 > 2.05 V */
#define | LL_PWR_PVDLLEVEL_1 (PWR_CR2_PVDFT_0) /* VPVD0 > 2.2 V */
#define | LL_PWR_PVDLLEVEL_2 (PWR_CR2_PVDFT_1) /* VPVD1 > 2.36 V */
#define | LL_PWR_PVDLLEVEL_3 (PWR_CR2_PVDFT_1 | PWR_CR2_PVDFT_0) /* VPVD2 > 2.52 V */
#define | LL_PWR_PVDLLEVEL_4 (PWR_CR2_PVDFT_2) /* VPVD3 > 2.64 V */
#define | LL_PWR_PVDLLEVEL_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0) /* VPVD4 > 2.81 V */
#define | LL_PWR_PVDLLEVEL_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1) /* VPVD5 > 2.91 V */
#define | LL_PWR_PVDHLEVEL_0 0x00000000u /* VPDD0 > 2.15 V */
#define | LL_PWR_PVDHLEVEL_1 (PWR_CR2_PVDRT_0) /* VPVD1 > 2.3 V */
#define | LL_PWR_PVDHLEVEL_2 (PWR_CR2_PVDRT_1) /* VPVD1 > 2.46 V */
#define | LL_PWR_PVDHLEVEL_3 (PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* VPVD2 > 2.62 V */
#define | LL_PWR_PVDHLEVEL_4 (PWR_CR2_PVDRT_2) /* VPVD3 > 2.74 V */
#define | LL_PWR_PVDHLEVEL_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0) /* VPVD4 > 2.91 V */
#define | LL_PWR_PVDHLEVEL_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1) /* VPVD5 > 3.01 V */
#define | LL_PWR_PVDHLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* External input analog voltage (Compare internally to VREFINT) */
#define | LL_PWR_PVM_USB PWR_CR2_PVMEN_USB
#define | LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define | LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define | LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
#define | LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6)
#define | LL_PWR_BATTCHARG_RESISTOR_5K 0x000000000u
#define | LL_PWR_BATTCHARG_RESISTOR_1_5K (PWR_CR4_VBRS)
#define | LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define | LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define | LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define | LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define | LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define | LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
#define | LL_PWR_GPIO_BIT_0 0x00000001u
#define | LL_PWR_GPIO_BIT_1 0x00000002u
#define | LL_PWR_GPIO_BIT_2 0x00000004u
#define | LL_PWR_GPIO_BIT_3 0x00000008u
#define | LL_PWR_GPIO_BIT_4 0x00000010u
#define | LL_PWR_GPIO_BIT_5 0x00000020u
#define | LL_PWR_GPIO_BIT_6 0x00000040u
#define | LL_PWR_GPIO_BIT_7 0x00000080u
#define | LL_PWR_GPIO_BIT_8 0x00000100u
#define | LL_PWR_GPIO_BIT_9 0x00000200u
#define | LL_PWR_GPIO_BIT_10 0x00000400u
#define | LL_PWR_GPIO_BIT_11 0x00000800u
#define | LL_PWR_GPIO_BIT_12 0x00001000u
#define | LL_PWR_GPIO_BIT_13 0x00002000u
#define | LL_PWR_GPIO_BIT_14 0x00004000u
#define | LL_PWR_GPIO_BIT_15 0x00008000u
#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Functions

__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableLowPowerRunMode (void)
Switch the regulator from main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_DisableLowPowerRunMode (void)
Switch the regulator from low-power mode to main mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledLowPowerRunMode (void)
Check if the regulator is in low-power mode.
__STATIC_INLINE void | LL_PWR_EnterLowPowerRunMode (void)
Switch from run main mode to run low-power mode.
__STATIC_INLINE void | LL_PWR_ExitLowPowerRunMode (void)
Switch from run main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableFlashPowerDownInLPSleep (void)
Enable Flash Power-down mode during low power sleep mode.
__STATIC_INLINE void | LL_PWR_DisableFlashPowerDownInLPSleep (void)
Disable Flash Power-down mode during Low power sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnableFlashPowerDownInLPSleep (void)
Check if flash power-down mode during low power sleep mode domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableFlashPowerDownInLPRun (void)
Enable Flash Power-down mode during low power run mode.
__STATIC_INLINE void | LL_PWR_DisableFlashPowerDownInLPRun (void)
Disable Flash Power-down mode during Low power run mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnableFlashPowerDownInLPRun (void)
Check if flash power-down mode during low power run mode domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableFlashPowerDownInStop (void)
Enable Flash Power-down mode during stop mode.
__STATIC_INLINE void | LL_PWR_DisableFlashPowerDownInStop (void)
Disable Flash Power-down mode during stop mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnableFlashPowerDownInStop (void)
Check if flash power-down mode during stop mode domain is enabled.
__STATIC_INLINE void | LL_PWR_EnableVddIO2 (void)
Enable VDDIO2 supply.
__STATIC_INLINE void | LL_PWR_DisableVddIO2 (void)
Disable VDDIO2 supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddIO2 (void)
Check if VDDIO2 supply is enabled.
__STATIC_INLINE void | LL_PWR_EnableVddUSB (void)
Enable VDDUSB supply.
__STATIC_INLINE void | LL_PWR_DisableVddUSB (void)
Disable VDDUSB supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddUSB (void)
Check if VDDUSB supply is enabled.
__STATIC_INLINE void | LL_PWR_EnablePVM (uint32_t PeriphVoltage)
Enable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE void | LL_PWR_DisablePVM (uint32_t PeriphVoltage)
Disable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVM (uint32_t PeriphVoltage)
Check if Power Voltage Monitoring is enabled on a peripheral.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Low-Power mode.
__STATIC_INLINE void | LL_PWR_SetPVDHighLevel (uint32_t PVDHighLevel)
Configure the high voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDHighLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_SetPVDLowLevel (uint32_t PVDLowLevel)
Configure the low voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLowLevel (void)
Get the low voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableInternWU (void)
Enable Internal Wake-up line.
__STATIC_INLINE void | LL_PWR_DisableInternWU (void)
Disable Internal Wake-up line.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled.
__STATIC_INLINE void | LL_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration.
__STATIC_INLINE void | LL_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRAMRetention (void)
Enable SRAM content retention in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableSRAMRetention (void)
Disable SRAM content retention in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRAMRetention (void)
Check if SRAM content retention in Standby mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableLPMUResetSamplingMode (void)
Enable sampling mode of LPMMU reset block.
__STATIC_INLINE void | LL_PWR_DisableLPMUResetSamplingMode (void)
Disable sampling mode of LPMMU reset block.
__STATIC_INLINE uint32_t | LL_PWR_IsEnableLPMUResetSamplingMode (void)
Check if sampling mode of LPMMU reset block.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-up state is enabled.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-down state is enabled.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_InternWU (void)
Get Internal Wake-up line Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Stand-By Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU6 (void)
Get Wake-up Flag 6.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Stand-By Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU6 (void)
Clear Wake-up Flag 6.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMOUSB (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOS (void)
Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPF (void)
Indicate whether the regulator is ready in main mode or is in low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPS (void)
Indicate whether or not the low-power regulator is ready.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_FLASH_RDY (void)
Indicate whether or not the flash is ready to be accessed.
ErrorStatus | LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

Header file of PWR LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_pwr.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rcc.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_ll_rcc.h File Reference

Header file of RCC LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...

Defines

#define | LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
#define | LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define | LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define | LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define | LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define | LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define | LL_RCC_CICR_CSSC RCC_CICR_CSSC
#define | LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC
#define | LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
#define | LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define | LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define | LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF
#define | LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define | LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define | LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define | LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF
#define | LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
#define | LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define | LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define | LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define | LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define | LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE
#define | LL_RCC_LSEDRIVE_LOW 0x00000000U
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U
#define | LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL
#define | LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1
#define | LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)
#define | LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1
#define | LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)
#define | LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2
#define | LL_RCC_SYSCLK_DIV_1 0x00000000U
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3
#define | LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)
#define | LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | LL_RCC_APB1_DIV_1 0x00000000U
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2
#define | LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)
#define | LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)
#define | LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)
#define | LL_RCC_HSI_DIV_1 0x00000000U
#define | LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0
#define | LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1
#define | LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
#define | LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2
#define | LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0)
#define | LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1)
#define | LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV
#define | LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1
#define | LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3
#define | LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)
#define | LL_RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0)
#define | LL_RCC_MCO1_DIV_1 0x00000000U
#define | LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0
#define | LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1
#define | LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2
#define | LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)
#define | LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3
#define | LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)
#define | LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U
#define | LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0
#define | LL_RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1
#define | LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2
#define | LL_RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1)
#define | LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3
#define | LL_RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1)
#define | LL_RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)
#define | LL_RCC_MCO2_DIV_1 0x00000000U
#define | LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0
#define | LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1
#define | LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2
#define | LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)
#define | LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3
#define | LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)
#define | LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)
#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
#define | LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U)
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)
#define | LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)
#define | LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)
#define | LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U)
#define | LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)
#define | LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)
#define | LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)
#define | LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U)
#define | LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0)
#define | LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1)
#define | LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)
#define | LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U)
#define | LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0)
#define | LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1)
#define | LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL)
#define | LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U)
#define | LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0)
#define | LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1)
#define | LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL)
#define | LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U)
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0)
#define | LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1)
#define | LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U)
#define | LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0)
#define | LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1)
#define | LL_RCC_I2S1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U)
#define | LL_RCC_I2S1_CLKSOURCE_PLL ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0)
#define | LL_RCC_I2S1_CLKSOURCE_HSI ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1)
#define | LL_RCC_I2S1_CLKSOURCE_PIN ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL)
#define | LL_RCC_I2S2_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U)
#define | LL_RCC_I2S2_CLKSOURCE_PLL ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0)
#define | LL_RCC_I2S2_CLKSOURCE_HSI ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1)
#define | LL_RCC_I2S2_CLKSOURCE_PIN ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL)
#define | LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U))
#define | LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U))
#define | LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U))
#define | LL_RCC_TIM15_CLKSOURCE_PLL (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U))
#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U))
#define | LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U))
#define | LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U))
#define | LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U))
#define | LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U
#define | LL_RCC_CEC_CLKSOURCE_LSE RCC_CCIPR_CECSEL
#define | LL_RCC_FDCAN_CLKSOURCE_PCLK1 0x00000000U
#define | LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0
#define | LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1
#define | LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RNG_CLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0
#define | LL_RCC_RNG_CLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1
#define | LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_RNGSEL
#define | LL_RCC_RNG_CLK_DIV1 0x00000000U
#define | LL_RCC_RNG_CLK_DIV2 RCC_CCIPR_RNGDIV_0
#define | LL_RCC_RNG_CLK_DIV4 RCC_CCIPR_RNGDIV_1
#define | LL_RCC_RNG_CLK_DIV8 RCC_CCIPR_RNGDIV
#define | LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U
#define | LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL_0
#define | LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR2_USBSEL_1
#define | LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U
#define | LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_0
#define | LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1
#define | LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
#define | LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
#define | LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL
#define | LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL
#define | LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL
#define | LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL
#define | LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL
#define | LL_RCC_I2S1_CLKSOURCE RCC_CCIPR2_I2S1SEL
#define | LL_RCC_I2S2_CLKSOURCE RCC_CCIPR2_I2S2SEL
#define | LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL
#define | LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL
#define | LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
#define | LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL
#define | LL_RCC_CEC_CLKSOURCE RCC_CCIPR_CECSEL
#define | LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL
#define | LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL
#define | LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL
#define | LL_RCC_RNG_CLKDIV RCC_CCIPR_RNGDIV
#define | LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL
#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define | LL_RCC_PLLSOURCE_NONE 0x00000000U
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define | LL_RCC_PLLM_DIV_1 0x00000000U
#define | LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
#define | LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)
#define | LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2)
#define | LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)
#define | LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0)
#define | LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1)
#define | LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)
#define | LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2)
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)
#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.
#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
Helper macro to calculate the PLLCLK frequency on system domain.
#define | __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on I2S domain.
#define | __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on I2S2 domain.
#define | __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on ADC domain.
#define | __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on RNG domain.
#define | __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on TIM1 domain.
#define | __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on TIM15 domain.
#define | __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on FDCAN domain.
#define | __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on USB domain.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU))
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))
Helper macro to calculate the HSISYS frequency.

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_HSI_EnableInStopMode (void)
Enable HSI even in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableInStopMode (void)
Disable HSI in stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsEnabledInStopMode (void)
Check if HSI in stop mode is enabled.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_HSI48_Enable (void)
Enable HSI48.
__STATIC_INLINE void | LL_RCC_HSI48_Disable (void)
Disable HSI48.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void)
Check if HSI48 oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void)
Get HSI48 Calibration value.
__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable Clock security system on LSE.
__STATIC_INLINE void | LL_RCC_LSE_DisableCSS (void)
Disable Clock security system on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsCSSDetected (void)
Check if CSS on LSE failure Detection.
__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.
__STATIC_INLINE void | LL_RCC_LSCO_Enable (void)
Enable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_Disable (void)
Disable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_SetSource (uint32_t Source)
Configure Low speed clock selection.
__STATIC_INLINE uint32_t | LL_RCC_LSCO_GetSource (void)
Get Low speed clock selection.
__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetHSIDiv (uint32_t HSIDiv)
Set HSI16 division factor.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetHSIDiv (void)
Get HSI16 Division factor.
__STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.
__STATIC_INLINE void | LL_RCC_ConfigMCO2 (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCO2.
__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
Configure LPUARTx clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetTIMClockSource (uint32_t TIMxSource)
Configure TIMx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetCECClockSource (uint32_t CECxSource)
Configure CEC clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockDiv (uint32_t RNGxDiv)
Configure RNG division factor.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetFDCANClockSource (uint32_t FDCANxSource)
Configure FDCAN clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE void | LL_RCC_SetI2SClockSource (uint32_t I2SxSource)
Configure I2Sx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
Get LPUARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetTIMClockSource (uint32_t TIMx)
Get TIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
Get LPTIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCECClockSource (uint32_t CECx)
Get CEC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetFDCANClockSource (uint32_t FDCANx)
Get FDCAN clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t RNGx)
Get RNGx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockDiv (void)
Get RNGx clock division factor.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2SClockSource (uint32_t I2Sx)
Get I2Sx clock source.
__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.
__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_I2S1 (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for I2S1 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_I2S2 (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for I2S2 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_RNG (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for RNG domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_FDCAN (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for FDCAN domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_USB (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for USB domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_TIM1 (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for TIM1 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_TIM15 (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for TIM15 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void)
Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void)
Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void)
Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void)
Get Main PLL division factor for PLLR.
__STATIC_INLINE void | LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
Configure PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void)
Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_ADC (void)
Enable PLL output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_ADC (void)
Disable PLL output mapped on ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_ADC (void)
Check if PLL output mapped on ADC domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_I2S1 (void)
Enable PLL output mapped on I2S domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_I2S2 (void)
Enable PLL output mapped on I2S2 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_I2S1 (void)
Disable PLL output mapped on I2S1 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_I2S1 (void)
Check if PLL output mapped on I2S1 domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_I2S2 (void)
Disable PLL output mapped on I2S2 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_I2S2 (void)
Check if PLL output mapped on I2S2 domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_RNG (void)
Enable PLL output mapped on RNG domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_RNG (void)
Disable PLL output mapped on RNG domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_RNG (void)
Check if PLL output mapped on RNG domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_FDCAN (void)
Enable PLL output mapped on FDCAN domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_FDCAN (void)
Disable PLL output mapped on FDCAN domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_FDCAN (void)
Check if PLL output mapped on FDCAN domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_USB (void)
Enable PLL output mapped on USB domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_USB (void)
Disable PLL output mapped on USB domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_USB (void)
Check if PLL output mapped on USB domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_TIM1 (void)
Enable PLL output mapped on TIM1 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_TIM1 (void)
Disable PLL output mapped on TIM1 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_TIM1 (void)
Check if PLL output mapped on TIM1 domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_TIM15 (void)
Enable PLL output mapped on TIM15 domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_TIM15 (void)
Disable PLL output mapped on TIM15 domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_TIM15 (void)
Check if PLL output mapped on TIM15 domain clock is enabled.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void)
Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void)
Disable PLL output mapped on SYSCLK domain.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsEnabledDomain_SYS (void)
Check if PLL output mapped on SYSCLK domain clock is enabled.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void)
Clear HSI48 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void)
Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag Option byte reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PWRRST (void)
Check if RCC flag BOR or POR/PDR reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.
__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void)
Enable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void)
Disable HSI48 ready interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSI48RDY (void)
Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetI2SClockFreq (uint32_t I2SxSource)
Return I2Sx clock frequency.
uint32_t | LL_RCC_GetCECClockFreq (uint32_t CECxSource)
Return CEC clock frequency.
uint32_t | LL_RCC_GetFDCANClockFreq (uint32_t FDCANxSource)
Return FDCANx clock frequency.
uint32_t | LL_RCC_GetTIMClockFreq (uint32_t TIMxSource)
Return TIMx clock frequency.
uint32_t | LL_RCC_GetRTCClockFreq (void)
Return RTC clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.

Detailed Description

Header file of RCC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_rcc.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rng.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_ll_rng.h File Reference

Header file of RNG LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RNG_InitTypeDef
LL RNG Init Structure Definition. More...

Defines

#define | LL_RNG_CED_ENABLE 0x00000000U
#define | LL_RNG_CED_DISABLE RNG_CR_CED
#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS
#define | LL_RNG_CR_IE RNG_CR_IE
#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE void | LL_RNG_EnableClkErrorDetect (RNG_TypeDef *RNGx)
Enable Clock Error Detection.
__STATIC_INLINE void | LL_RNG_DisableClkErrorDetect (RNG_TypeDef *RNGx)
Disable RNG Clock Error Detection.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledClkErrorDetect (RNG_TypeDef *RNGx)
Check if RNG Clock Error Detection is enabled.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.
__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_ReadRandData32 (RNG_TypeDef *RNGx)
Return32-bit Random Number value.
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.
ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).

Detailed Description

Header file of RNG LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_rng.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rtc.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_ll_rtc.h File Reference

Header file of RTC LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...

Defines

#define | RTC_LL_INIT_MASK 0xFFFFFFFFU
#define | RTC_LL_RSF_MASK 0xFFFFFF5FU
#define | RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
#define | RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
#define | RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
#define | RTC_OFFSET_WEEKDAY (uint32_t)24U
#define | RTC_OFFSET_DAY (uint32_t)16U
#define | RTC_OFFSET_MONTH (uint32_t)8U
#define | RTC_OFFSET_HOUR (uint32_t)16U
#define | RTC_OFFSET_MINUTE (uint32_t)8U
#define | LL_RTC_FORMAT_BIN 0x00000000U
#define | LL_RTC_FORMAT_BCD 0x00000001U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
#define | LL_RTC_SCR_ITSF RTC_SCR_CITSF
#define | LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
#define | LL_RTC_SCR_TSF RTC_SCR_CTSF
#define | LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define | LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define | LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
#define | LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define | LL_RTC_ICSR_INITF RTC_ICSR_INITF
#define | LL_RTC_ICSR_RSF RTC_ICSR_RSF
#define | LL_RTC_ICSR_INITS RTC_ICSR_INITS
#define | LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
#define | LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
#define | LL_RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF
#define | LL_RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF
#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | LL_RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | LL_RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | LL_RTC_MONTH_MAY ((uint8_t)0x05U)
#define | LL_RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | LL_RTC_MONTH_JULY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM
#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
#define | LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define | LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
#define | LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define | LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK
#define | LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK
#define | LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK
#define | LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE
#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH
#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG
#define | LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E
#define | LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E
#define | LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E
#define | LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E
#define | LL_RTC_BKP_DR0 0x00000000U
#define | LL_RTC_BKP_DR1 0x00000001U
#define | LL_RTC_BKP_DR2 0x00000002U
#define | LL_RTC_BKP_DR3 0x00000003U
#define | LL_RTC_BKP_DR4 0x00000004U
#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
#define | LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE
#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RTC register.
#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))
Helper macro to convert a value from BCD format to 2 digit decimal format.
#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.
#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableTamperOutput (RTC_TypeDef *RTCx)
Enable tamper output.
__STATIC_INLINE void | LL_RTC_DisableTamperOutput (RTC_TypeDef *RTCx)
Disable tamper output.
__STATIC_INLINE uint32_t | LL_RTC_IsTamperOutputEnabled (RTC_TypeDef *RTCx)
Check if tamper output is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableAlarmPullUp (RTC_TypeDef *RTCx)
Enable internal pull-up in output mode.
__STATIC_INLINE void | LL_RTC_DisableAlarmPullUp (RTC_TypeDef *RTCx)
Disable internal pull-up in output mode.
__STATIC_INLINE uint32_t | LL_RTC_IsAlarmPullUpEnabled (RTC_TypeDef *RTCx)
Check if internal pull-up in output mode is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableOutput2 (RTC_TypeDef *RTCx)
Enable RTC_OUT2 output.
__STATIC_INLINE void | LL_RTC_DisableOutput2 (RTC_TypeDef *RTCx)
Disable RTC_OUT2 output.
__STATIC_INLINE uint32_t | LL_RTC_IsOutput2Enabled (RTC_TypeDef *RTCx)
Check if RTC_OUT2 output is enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.
__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.
__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.
__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TAMPER_Enable (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Clear TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (TAMP_TypeDef *TAMPx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (TAMP_TypeDef *TAMPx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (TAMP_TypeDef *TAMPx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (TAMP_TypeDef *TAMPx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (TAMP_TypeDef *TAMPx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (TAMP_TypeDef *TAMPx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (TAMP_TypeDef *TAMPx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (TAMP_TypeDef *TAMPx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (TAMP_TypeDef *TAMPx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (TAMP_TypeDef *TAMPx, uint32_t Tamper)
Disable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_ITAMP_Enable (TAMP_TypeDef *TAMPx, uint32_t InternalTamper)
Enable internal tamper detection.
__STATIC_INLINE void | LL_RTC_TAMPER_ITAMP_Disable (TAMP_TypeDef *TAMPx, uint32_t InternalTamper)
Disable internal tamper detection.
__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.
__STATIC_INLINE void | LL_RTC_BKP_SetRegister (TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BKP_GetRegister (TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAM (RTC_TypeDef *RTCx)
Get Alarm A masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBM (RTC_TypeDef *RTCx)
Get Alarm B masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTM (RTC_TypeDef *RTCx)
Get Wakeup timer masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSM (RTC_TypeDef *RTCx)
Get Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOVM (RTC_TypeDef *RTCx)
Get Time-stamp overflow masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITSM (RTC_TypeDef *RTCx)
Get Internal Time-stamp masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (TAMP_TypeDef *TAMPx)
Get tamper 1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (TAMP_TypeDef *TAMPx)
Get tamper 2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (TAMP_TypeDef *TAMPx)
Get tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP3 (TAMP_TypeDef *TAMPx)
Get internal tamper 3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP4 (TAMP_TypeDef *TAMPx)
Get internal tamper 4 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP5 (TAMP_TypeDef *TAMPx)
Get internal tamper 5 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP6 (TAMP_TypeDef *TAMPx)
Get internal tamper 6 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1M (TAMP_TypeDef *TAMPx)
Get tamper 1 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2M (TAMP_TypeDef *TAMPx)
Get tamper 2 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3M (TAMP_TypeDef *TAMPx)
Get tamper 3 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP3M (TAMP_TypeDef *TAMPx)
Get internal tamper 3 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP4M (TAMP_TypeDef *TAMPx)
Get internal tamper 4 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP5M (TAMP_TypeDef *TAMPx)
Get internal tamper 5 interrupt masked flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITAMP6M (TAMP_TypeDef *TAMPx)
Get internal tamper 6 interrupt masked flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (TAMP_TypeDef *TAMPx)
Clear tamper 1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (TAMP_TypeDef *TAMPx)
Clear tamper 2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (TAMP_TypeDef *TAMPx)
Clear tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP3 (TAMP_TypeDef *TAMPx)
Clear internal tamper 3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP4 (TAMP_TypeDef *TAMPx)
Clear internal tamper 4 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP5 (TAMP_TypeDef *TAMPx)
Clear internal tamper 5 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITAMP6 (TAMP_TypeDef *TAMPx)
Clear internal tamper 6 detection flag.
__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (TAMP_TypeDef *TAMPx)
Enable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (TAMP_TypeDef *TAMPx)
Disable tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (TAMP_TypeDef *TAMPx)
Enable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (TAMP_TypeDef *TAMPx)
Disable tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (TAMP_TypeDef *TAMPx)
Enable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (TAMP_TypeDef *TAMPx)
Disable tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP3 (TAMP_TypeDef *TAMPx)
Enable internal tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP3 (TAMP_TypeDef *TAMPx)
Disable internal tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP4 (TAMP_TypeDef *TAMPx)
Enable internal tamper 4 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP4 (TAMP_TypeDef *TAMPx)
Disable internal tamper 4 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP5 (TAMP_TypeDef *TAMPx)
Enable internal tamper 5 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP5 (TAMP_TypeDef *TAMPx)
Disable internal tamper 5 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ITAMP6 (TAMP_TypeDef *TAMPx)
Enable internal tamper 6 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ITAMP6 (TAMP_TypeDef *TAMPx)
Disable internal tamper 6 interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (TAMP_TypeDef *TAMPx)
Check if tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (TAMP_TypeDef *TAMPx)
Check if tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (TAMP_TypeDef *TAMPx)
Check if tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP3 (TAMP_TypeDef *TAMPx)
Check if internal tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP4 (TAMP_TypeDef *TAMPx)
Check if internal tamper 4 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP5 (TAMP_TypeDef *TAMPx)
Check if internal tamper 5 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ITAMP6 (TAMP_TypeDef *TAMPx)
Check if internal tamper 6 interrupt is enabled or not.
ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Header file of RTC LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_rtc.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


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Data Structures | Defines | Functions
stm32g0xx_ll_spi.h File Reference

Header file of SPI LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_SPI_InitTypeDef
SPI Init structures definition. More...
struct | LL_I2S_InitTypeDef
I2S Init structure definition. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE
#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U
#define | LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)
#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)
#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)
#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U
#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)
#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))
#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)
#define | LL_SPI_CRC_8BIT 0x00000000U
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)
#define | LL_SPI_RX_FIFO_TH_HALF 0x00000000U
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)
#define | LL_SPI_RX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)
#define | LL_SPI_TX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)
#define | LL_SPI_DMA_PARITY_EVEN 0x00000000U
#define | LL_SPI_DMA_PARITY_ODD 0x00000001U
#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.
#define | LL_I2S_SR_RXNE LL_SPI_SR_RXNE
#define | LL_I2S_SR_TXE LL_SPI_SR_TXE
#define | LL_I2S_SR_BSY LL_SPI_SR_BSY
#define | LL_I2S_SR_UDR SPI_SR_UDR
#define | LL_I2S_SR_OVR LL_SPI_SR_OVR
#define | LL_I2S_SR_FRE LL_SPI_SR_FRE
#define | LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
#define | LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
#define | LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE
#define | LL_I2S_DATAFORMAT_16B 0x00000000U
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
#define | LL_I2S_POLARITY_LOW 0x00000000U
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
#define | LL_I2S_STANDARD_PHILIPS 0x00000000U
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
#define | LL_I2S_MODE_SLAVE_TX 0x00000000U
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
#define | LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)
#define | LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define | LL_I2S_AUDIOFREQ_192K 192000U
#define | LL_I2S_AUDIOFREQ_96K 96000U
#define | LL_I2S_AUDIOFREQ_48K 48000U
#define | LL_I2S_AUDIOFREQ_44K 44100U
#define | LL_I2S_AUDIOFREQ_32K 32000U
#define | LL_I2S_AUDIOFREQ_22K 22050U
#define | LL_I2S_AUDIOFREQ_16K 16000U
#define | LL_I2S_AUDIOFREQ_11K 11025U
#define | LL_I2S_AUDIOFREQ_8K 8000U
#define | LL_I2S_AUDIOFREQ_DEFAULT 2U
#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.
__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.
ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.
__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabled (SPI_TypeDef *SPIx)
Check if I2S peripheral is enabled.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataFormat)
Set I2S data frame length.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S data frame length.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set I2S clock polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get I2S clock polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard protocol.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard protocol.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set I2S transfer mode.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S transfer mode.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the master clock output (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the master clock output (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock output (Pin MCK) is enabled.
__STATIC_INLINE void | LL_I2S_EnableAsyncStart (SPI_TypeDef *SPIx)
Enable asynchronous start.
__STATIC_INLINE void | LL_I2S_DisableAsyncStart (SPI_TypeDef *SPIx)
Disable asynchronous start.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledAsyncStart (SPI_TypeDef *SPIx)
Check if asynchronous start is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_CHSIDE (SPI_TypeDef *SPIx)
Get channel side flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_I2S_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error IT.
__STATIC_INLINE void | LL_I2S_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if ERR IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if RXNE IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if TXE IT is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in data register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in data register.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Detailed Description

Header file of SPI LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_spi.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_system.h File Reference

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Defines | Functions
stm32g0xx_ll_system.h File Reference

Header file of SYSTEM LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | LL_SYSCFG_REMAP_FLASH 0x00000000U
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)
#define | LL_SYSCFG_PIN_RMP_PA11 SYSCFG_CFGR1_PA11_RMP
#define | LL_SYSCFG_PIN_RMP_PA12 SYSCFG_CFGR1_PA12_RMP
#define | LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)
#define | LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0)
#define | LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1)
#define | LL_SYSCFG_IR_POL_NOT_INVERTED 0x00000000U
#define | LL_SYSCFG_IR_POL_INVERTED (SYSCFG_CFGR1_IR_POL)
#define | LL_SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN
#define | LL_SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE
#define | LL_SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL
#define | LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL
#define | LL_SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN
#define | LL_SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN
#define | LL_SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN
#define | LL_SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN
#define | LL_SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN
#define | LL_SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN
#define | LL_SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN
#define | LL_SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN
#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBG_APB_FZ1_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBG_APB_FZ1_DBG_TIM6_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBG_APB_FZ1_DBG_TIM7_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM2_STOP DBG_APB_FZ1_DBG_LPTIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBG_APB_FZ1_DBG_LPTIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP
#define | LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U
#define | LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS
#define | LL_FLASH_LATENCY_0 0x00000000U
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1
#define | LL_FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_EnablePinRemap (uint32_t PinRemap)
Enable remap of a pin on different pad.
__STATIC_INLINE void | LL_SYSCFG_DisablePinRemap (uint32_t PinRemap)
Enable remap of a pin on different pad.
__STATIC_INLINE void | LL_SYSCFG_SetIRModEnvelopeSignal (uint32_t Source)
Set IR Modulation Envelope signal source.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetIRModEnvelopeSignal (void)
Get IR Modulation Envelope signal source.
__STATIC_INLINE void | LL_SYSCFG_SetIRPolarity (uint32_t Polarity)
Set IR Output polarity.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetIRPolarity (void)
Get IR Output polarity.
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void)
Enable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void)
Disable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableDBATT (uint32_t ConfigDeadBattery)
Disable dead battery behavior.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_WWDG (void)
Check if Window watchdog interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_PVDOUT (void)
Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_PVMOUT (void)
Check if VDDUSB supply monitoring interrupt occurred or not (EXTI line 34).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_RTC_WAKEUP (void)
Check if RTC Wake Up interrupt occurred or not (EXTI line 19).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TAMPER (void)
Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 21).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FLASH_ITF (void)
Check if Flash interface interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FLASH_ECC (void)
Check if Flash interface interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CLK_CTRL (void)
Check if Reset and clock control interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CRS (void)
Check if Reset and clock control interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI0 (void)
Check if EXTI line 0 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI1 (void)
Check if EXTI line 1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI2 (void)
Check if EXTI line 2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI3 (void)
Check if EXTI line 3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI4 (void)
Check if EXTI line 4 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI5 (void)
Check if EXTI line 5 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI6 (void)
Check if EXTI line 6 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI7 (void)
Check if EXTI line 7 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI8 (void)
Check if EXTI line 8 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI9 (void)
Check if EXTI line 9 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI10 (void)
Check if EXTI line 10 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI11 (void)
Check if EXTI line 11 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI12 (void)
Check if EXTI line 12 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI13 (void)
Check if EXTI line 13 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI14 (void)
Check if EXTI line 14 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_EXTI15 (void)
Check if EXTI line 15 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_UCPD1 (void)
Check if UCPD1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_UCPD2 (void)
Check if UCPD2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USB (void)
Check if USB interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH1 (void)
Check if DMA1 channel 1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH2 (void)
Check if DMA1 channel 2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH3 (void)
Check if DMA1 channel 3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH4 (void)
Check if DMA1 channel 4 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH5 (void)
Check if DMA1 channel 5 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH6 (void)
Check if DMA1 channel 6 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA1_CH7 (void)
Check if DMA1 channel 7 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMAMUX (void)
Check if DMAMUX interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH1 (void)
Check if DMA2_CH1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH2 (void)
Check if DMA2_CH2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH3 (void)
Check if DMA2_CH3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH4 (void)
Check if DMA2_CH4 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DMA2_CH5 (void)
Check if DMA2_CH5 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_ADC (void)
Check if ADC interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_COMP1 (void)
Check if Comparator 1 interrupt occurred or not (EXTI line 21).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_COMP2 (void)
Check if Comparator 2 interrupt occurred or not (EXTI line 22).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_COMP3 (void)
Check if Comparator 3 interrupt occurred or not (EXTI line 20).
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_BRK (void)
Check if Timer 1 break interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_UPD (void)
Check if Timer 1 update interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_TRG (void)
Check if Timer 1 trigger interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_CCU (void)
Check if Timer 1 commutation interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM1_CC (void)
Check if Timer 1 capture compare interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM2 (void)
Check if Timer 2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM3 (void)
Check if Timer 3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM4 (void)
Check if Timer 3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_DAC (void)
Check if DAC underrun interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM6 (void)
Check if Timer 6 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_LPTIM1 (void)
Check if LPTIM1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM7 (void)
Check if Timer 7 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_LPTIM2 (void)
Check if LPTIM2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM14 (void)
Check if Timer 14 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM15 (void)
Check if Timer 15 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM16 (void)
Check if Timer 16 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FDCAN1_IT0 (void)
Check if FDCAN1_IT0 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FDCAN2_IT0 (void)
Check if FDCAN2_IT0 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_TIM17 (void)
Check if Timer 17 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FDCAN1_IT1 (void)
Check if FDCAN1_IT1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_FDCAN2_IT1 (void)
Check if FDCAN2_IT1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_I2C1 (void)
Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_I2C2 (void)
Check if I2C2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_I2C3 (void)
Check if I2C3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SPI1 (void)
Check if SPI1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SPI2 (void)
Check if SPI2 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SPI3 (void)
Check if SPI3 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART1 (void)
Check if USART1 interrupt occurred or not, combined with EXTI line 25.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART2 (void)
Check if USART2 interrupt occurred or not, combined with EXTI line 26.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_LPUART2 (void)
Check if LPUART2 interrupt occurred or not, combined with EXTI line 26.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART3 (void)
Check if USART3 interrupt occurred or not, combined with EXTI line 28.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART4 (void)
Check if USART4 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_LPUART1 (void)
Check if LPUART1 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART5 (void)
Check if USART5 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_USART6 (void)
Check if USART6 interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_CEC (void)
Check if CEC interrupt occurred or not, combined with EXTI line 27.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_AES (void)
Check if AES interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_RNG (void)
Check if RNG interrupt occurred or not, combined with EXTI line 31.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM parity error flag.
__STATIC_INLINE void | LL_SYSCFG_EnableClampingDiode (uint32_t ConfigClampingDiode)
Enable Clamping Diode on specific pin.
__STATIC_INLINE void | LL_SYSCFG_DisableClampingDiode (uint32_t ConfigClampingDiode)
Disable Clamping Diode on specific pin.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledClampingDiode (uint32_t ConfigClampingDiode)
Indicates whether clamping diode(s) is(are) enabled.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.
__STATIC_INLINE void | LL_VREFBUF_Enable (void)
Enable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_Disable (void)
Disable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_EnableHIZ (void)
Enable high impedance (VREF+pin is high impedance)
__STATIC_INLINE void | LL_VREFBUF_DisableHIZ (void)
Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
__STATIC_INLINE void | LL_VREFBUF_SetVoltageScaling (uint32_t Scale)
Set the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetVoltageScaling (void)
Get the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_IsVREFReady (void)
Check if Voltage reference buffer is ready.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetTrimming (void)
Get the trimming code for VREFBUF calibration.
__STATIC_INLINE void | LL_VREFBUF_SetTrimming (uint32_t Value)
Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableInstCache (void)
Enable Instruction cache.
__STATIC_INLINE void | LL_FLASH_DisableInstCache (void)
Disable Instruction cache.
__STATIC_INLINE void | LL_FLASH_EnableInstCacheReset (void)
Enable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_DisableInstCacheReset (void)
Disable Instruction cache reset.

Detailed Description

Header file of SYSTEM LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL SYSTEM driver contains a set of generic APIs that can be
    used by user:
      (+) Some of the FLASH features need to be handled in the SYSTEM file.
      (+) Access to DBG registers
      (+) Access to SYSCFG registers
      (+) Access to VREFBUF registers

Definition in file stm32g0xx_ll_system.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_tim.h File Reference

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Data Structures | Defines | Functions | Variables
stm32g0xx_ll_tim.h File Reference

Header file of TIM LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...

Defines

#define | TIM_POSITION_BRK_SOURCE
#define | TIMx_AF1_BKINP TIM1_AF1_BKINP
#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | DT_DELAY_1 ((uint8_t)0x7F)
#define | DT_DELAY_2 ((uint8_t)0x3F)
#define | DT_DELAY_3 ((uint8_t)0x1F)
#define | DT_DELAY_4 ((uint8_t)0x1F)
#define | DT_RANGE_1 ((uint8_t)0x00)
#define | DT_RANGE_2 ((uint8_t)0x80)
#define | DT_RANGE_3 ((uint8_t)0xC0)
#define | DT_RANGE_4 ((uint8_t)0xE0)
#define | OCREF_CLEAR_SELECT_Pos (16U)
Legacy definitions for compatibility purpose.
#define | OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).
#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF
#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | LL_TIM_BREAK2_DISABLE 0x00000000U
#define | LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E
#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE
#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS
#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U
#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS
#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR
#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS
#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E
#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E
#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1
#define | LL_TIM_GROUPCH5_NONE 0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)
#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)
#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)
#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE
#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO2_RESET 0x00000000U
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP
#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS
#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF
#define | LL_TIM_ETRSOURCE_GPIO 0x00000000U
#define | LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)
#define | LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2
#define | LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_ETRSOURCE_MCO TIM1_AF1_ETRSEL_2
#define | LL_TIM_ETRSOURCE_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)
#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP
#define | LL_TIM_BREAK_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U
#define | LL_TIM_BREAK2_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P
#define | LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U
#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | LL_TIM_BREAK_INPUT_BKIN 0x00000000U
#define | LL_TIM_BREAK_INPUT_BKIN2 0x00000004U
#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E
#define | LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E
#define | LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP
#define | LL_TIM_BKIN_POLARITY_HIGH 0x00000000U
#define | LL_TIM_BREAK_AFMODE_INPUT 0x00000000U
#define | LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID
#define | LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U
#define | LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID
#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)
#define | LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
#define | LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM1_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM1_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM1_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0
#define | LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM2_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0
#define | LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0
#define | LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM4_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0
#define | LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
#define | LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0
#define | LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM16_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
#define | LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2
#define | LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U
#define | LL_TIM_TIM17_TI1_RMP_HSI48 TIM_TISEL_TI1SEL_0
#define | LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1
#define | LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)
#define | LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2
#define | LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk
#define | LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U
#define | LL_TIM_OCREF_CLR_INT_COMP2 TIM1_OR1_OCREF_CLR_0
#define | LL_TIM_OCREF_CLR_INT_COMP3 TIM1_OR1_OCREF_CLR_1
#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in TIM register.
#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (const TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (const TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (const TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (const TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (const TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (const TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (const TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (const TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (const TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (const TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (const TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (const TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.
__STATIC_INLINE uint32_t | LL_TIM_IsActiveUIFCPY (const uint32_t Counter)
Indicate whether update interrupt flag (UIF) copy is set.
__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (const TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.
__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (const TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.
__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (const TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (const TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (const TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (const TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (const TIM_TypeDef *TIMx)
Get captured value for input channel 4.
__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (const TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.
__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (const TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.
__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, uint32_t BreakAFMode)
Configure the break input.
__STATIC_INLINE void | LL_TIM_DisarmBRK (TIM_TypeDef *TIMx)
Disarm the break input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_ReArmBRK (TIM_TypeDef *TIMx)
Re-arm the break input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, uint32_t Break2AFMode)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_DisarmBRK2 (TIM_TypeDef *TIMx)
Disarm the break 2 input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_ReArmBRK2 (TIM_TypeDef *TIMx)
Re-arm the break 2 input (when it operates in bidirectional mode).
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (const TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (const TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.
__STATIC_INLINE void | LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.
__STATIC_INLINE void | LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).
__STATIC_INLINE void | LL_TIM_SetOCRefClearInputSource (TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
Set the OCREF clear input source.
__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (const TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (const TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (const TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (const TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (const TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (const TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (const TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (const TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (const TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (const TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (const TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (const TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (const TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (const TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (const TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.
__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Detailed Description

Header file of TIM LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_tim.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_ucpd.h File Reference

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Data Structures | Defines | Functions
stm32g0xx_ll_ucpd.h File Reference

Header file of UCPD LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_UCPD_InitTypeDef
UCPD Init structures definition. More...

Defines

#define | LL_UCPD_SR_TXIS UCPD_SR_TXIS
#define | LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC
#define | LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT
#define | LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT
#define | LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC
#define | LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT
#define | LL_UCPD_SR_TXUND UCPD_SR_TXUND
#define | LL_UCPD_SR_RXNE UCPD_SR_RXNE
#define | LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET
#define | LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET
#define | LL_UCPD_SR_RXOVR UCPD_SR_RXOVR
#define | LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND
#define | LL_UCPD_SR_RXERR UCPD_SR_RXERR
#define | LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1
#define | LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2
#define | LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1
#define | LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2
#define | LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT
#define | LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE
#define | LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE
#define | LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE
#define | LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE
#define | LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE
#define | LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE
#define | LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE
#define | LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE
#define | LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE
#define | LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE
#define | LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE
#define | LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE
#define | LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE
#define | LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE
#define | LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE
#define | LL_UCPD_SYNC1 0x18u
#define | LL_UCPD_SYNC2 0x11u
#define | LL_UCPD_SYNC3 0x06u
#define | LL_UCPD_RST1 0x07u
#define | LL_UCPD_RST2 0x19u
#define | LL_UCPD_EOP 0x0Du
#define | LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u))
#define | LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u ))
#define | LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u))
#define | LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u))
#define | LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE
#define | LL_UCPD_ROLE_SRC 0x0U
#define | LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0
#define | LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1
#define | LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE
#define | LL_UCPD_RESISTOR_NONE 0x0U
#define | LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0
#define | LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1
#define | LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2
#define | LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3
#define | LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4
#define | LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5
#define | LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6
#define | LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7
#define | LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8
#define | LL_UCPD_SNK_CC1_VOPEN 0x00u
#define | LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0
#define | LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1
#define | LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)
#define | LL_UCPD_SNK_CC2_VOPEN 0x00u
#define | LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0
#define | LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1
#define | LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)
#define | LL_UCPD_SRC_CC1_VRA 0x0U
#define | LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0
#define | LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1
#define | LL_UCPD_SRC_CC2_VRA 0x0U
#define | LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0
#define | LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1
#define | LL_UCPD_PSC_DIV1 0x0u
#define | LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0
#define | LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1
#define | LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)
#define | LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2
#define | LL_UCPD_CCENABLE_NONE 0x0U
#define | LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0
#define | LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1
#define | LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)
#define | LL_UCPD_CCPIN_CC1 0x0U
#define | LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL
#define | LL_UCPD_RXMODE_NORMAL 0x0U
#define | LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE
#define | LL_UCPD_TXMODE_NORMAL 0x0U
#define | LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0
#define | LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1
#define | LL_UCPD_RXORDSET_SOP 0x0U
#define | LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0
#define | LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1
#define | LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)
#define | LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2
#define | LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)
#define | LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)
#define | LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)
#define | LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in UCPD register.
#define | LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in UCPD register.

Functions

__STATIC_INLINE void | LL_UCPD_Enable (UCPD_TypeDef *UCPDx)
Enable UCPD peripheral.
__STATIC_INLINE void | LL_UCPD_Disable (UCPD_TypeDef *UCPDx)
Disable UCPD peripheral.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabled (UCPD_TypeDef const *const UCPDx)
Check if UCPD peripheral is enabled.
__STATIC_INLINE void | LL_UCPD_SetRxOrderSet (UCPD_TypeDef *UCPDx, uint32_t OrderSet)
Set the receiver ordered set detection enable.
__STATIC_INLINE void | LL_UCPD_SetPSCClk (UCPD_TypeDef *UCPDx, uint32_t Psc)
Set the prescaler for ucpd clock.
__STATIC_INLINE void | LL_UCPD_SetTransWin (UCPD_TypeDef *UCPDx, uint32_t TransWin)
Set the number of cycles (minus 1) of the half bit clock.
__STATIC_INLINE void | LL_UCPD_SetIfrGap (UCPD_TypeDef *UCPDx, uint32_t IfrGap)
Set the clock divider value to generate an interframe gap.
__STATIC_INLINE void | LL_UCPD_SetHbitClockDiv (UCPD_TypeDef *UCPDx, uint32_t HbitClock)
Set the clock divider value to generate an interframe gap.
__STATIC_INLINE void | LL_UCPD_WakeUpEnable (UCPD_TypeDef *UCPDx)
Enable the wakeup mode.
__STATIC_INLINE void | LL_UCPD_WakeUpDisable (UCPD_TypeDef *UCPDx)
Disable the wakeup mode.
__STATIC_INLINE void | LL_UCPD_ForceClockEnable (UCPD_TypeDef *UCPDx)
Force clock enable.
__STATIC_INLINE void | LL_UCPD_ForceClockDisable (UCPD_TypeDef *UCPDx)
Force clock disable.
__STATIC_INLINE void | LL_UCPD_RxFilterEnable (UCPD_TypeDef *UCPDx)
RxFilter enable.
__STATIC_INLINE void | LL_UCPD_RxFilterDisable (UCPD_TypeDef *UCPDx)
RxFilter disable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC2Enable (UCPD_TypeDef *UCPDx)
Type C detector for CC2 enable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC2Disable (UCPD_TypeDef *UCPDx)
Type C detector for CC2 disable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC1Enable (UCPD_TypeDef *UCPDx)
Type C detector for CC1 enable.
__STATIC_INLINE void | LL_UCPD_TypeCDetectionCC1Disable (UCPD_TypeDef *UCPDx)
Type C detector for CC1 disable.
__STATIC_INLINE void | LL_UCPD_VconnDischargeEnable (UCPD_TypeDef *UCPDx)
Source Vconn discharge enable.
__STATIC_INLINE void | LL_UCPD_VconnDischargeDisable (UCPD_TypeDef *UCPDx)
Source Vconn discharge disable.
__STATIC_INLINE void | LL_UCPD_SignalFRSTX (UCPD_TypeDef *UCPDx)
Signal Fast Role Swap request.
__STATIC_INLINE void | LL_UCPD_FRSDetectionEnable (UCPD_TypeDef *UCPDx)
Fast Role swap RX detection enable.
__STATIC_INLINE void | LL_UCPD_FRSDetectionDisable (UCPD_TypeDef *UCPDx)
Fast Role swap RX detection disable.
__STATIC_INLINE void | LL_UCPD_SetccEnable (UCPD_TypeDef *UCPDx, uint32_t CCEnable)
Set cc enable.
__STATIC_INLINE void | LL_UCPD_SetSNKRole (UCPD_TypeDef *UCPDx)
Set UCPD SNK role.
__STATIC_INLINE void | LL_UCPD_SetSRCRole (UCPD_TypeDef *UCPDx)
Set UCPD SRC role.
__STATIC_INLINE uint32_t | LL_UCPD_GetRole (UCPD_TypeDef const *const UCPDx)
Get UCPD Role.
__STATIC_INLINE void | LL_UCPD_SetRpResistor (UCPD_TypeDef *UCPDx, uint32_t Resistor)
Set Rp resistor.
__STATIC_INLINE void | LL_UCPD_SetCCPin (UCPD_TypeDef *UCPDx, uint32_t CCPin)
Set CC pin.
__STATIC_INLINE void | LL_UCPD_RxEnable (UCPD_TypeDef *UCPDx)
Rx enable.
__STATIC_INLINE void | LL_UCPD_RxDisable (UCPD_TypeDef *UCPDx)
Rx disable.
__STATIC_INLINE void | LL_UCPD_SetRxMode (UCPD_TypeDef *UCPDx, uint32_t RxMode)
Set Rx mode.
__STATIC_INLINE void | LL_UCPD_SendHardReset (UCPD_TypeDef *UCPDx)
Send Hard Reset.
__STATIC_INLINE void | LL_UCPD_SendMessage (UCPD_TypeDef *UCPDx)
Send message.
__STATIC_INLINE void | LL_UCPD_SetTxMode (UCPD_TypeDef *UCPDx, uint32_t TxMode)
Set Tx mode.
__STATIC_INLINE void | LL_UCPD_EnableIT_FRS (UCPD_TypeDef *UCPDx)
Enable FRS interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Enable type c event on CC2.
__STATIC_INLINE void | LL_UCPD_EnableIT_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Enable type c event on CC1.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxMsgEnd (UCPD_TypeDef *UCPDx)
Enable Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxOvr (UCPD_TypeDef *UCPDx)
Enable Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxHRST (UCPD_TypeDef *UCPDx)
Enable Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxOrderSet (UCPD_TypeDef *UCPDx)
Enable Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_RxNE (UCPD_TypeDef *UCPDx)
Enable Rx non empty interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxUND (UCPD_TypeDef *UCPDx)
Enable TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Enable hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Enable hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGABT (UCPD_TypeDef *UCPDx)
Enable Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGSENT (UCPD_TypeDef *UCPDx)
Enable Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxMSGDISC (UCPD_TypeDef *UCPDx)
Enable Tx message discarded interrupt.
__STATIC_INLINE void | LL_UCPD_EnableIT_TxIS (UCPD_TypeDef *UCPDx)
Enable Tx data receive interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_FRS (UCPD_TypeDef *UCPDx)
Disable FRS interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Disable type c event on CC2.
__STATIC_INLINE void | LL_UCPD_DisableIT_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Disable type c event on CC1.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxMsgEnd (UCPD_TypeDef *UCPDx)
Disable Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxOvr (UCPD_TypeDef *UCPDx)
Disable Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxHRST (UCPD_TypeDef *UCPDx)
Disable Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxOrderSet (UCPD_TypeDef *UCPDx)
Disable Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_RxNE (UCPD_TypeDef *UCPDx)
Disable Rx non empty interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxUND (UCPD_TypeDef *UCPDx)
Disable TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Disable hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Disable hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGABT (UCPD_TypeDef *UCPDx)
Disable Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGSENT (UCPD_TypeDef *UCPDx)
Disable Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxMSGDISC (UCPD_TypeDef *UCPDx)
Disable Tx message discarded interrupt.
__STATIC_INLINE void | LL_UCPD_DisableIT_TxIS (UCPD_TypeDef *UCPDx)
Disable Tx data receive interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_FRS (UCPD_TypeDef const *const UCPDx)
Check if FRS interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TypeCEventCC2 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC2 enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TypeCEventCC1 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC1 enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxMsgEnd (UCPD_TypeDef const *const UCPDx)
Check if Rx message end interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxOvr (UCPD_TypeDef const *const UCPDx)
Check if Rx overrun interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxHRST (UCPD_TypeDef const *const UCPDx)
Check if Rx hard resrt interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxOrderSet (UCPD_TypeDef const *const UCPDx)
Check if Rx orderset interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_RxNE (UCPD_TypeDef const *const UCPDx)
Check if Rx non empty interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxUND (UCPD_TypeDef const *const UCPDx)
Check if TX underrun interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxHRSTSENT (UCPD_TypeDef const *const UCPDx)
Check if hard reset sent interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxHRSTDISC (UCPD_TypeDef const *const UCPDx)
Check if hard reset discard interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGABT (UCPD_TypeDef const *const UCPDx)
Check if Tx message abort interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGSENT (UCPD_TypeDef const *const UCPDx)
Check if Tx message sent interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxMSGDISC (UCPD_TypeDef const *const UCPDx)
Check if Tx message discarded interrupt enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnableIT_TxIS (UCPD_TypeDef const *const UCPDx)
Check if Tx data receive interrupt enabled.
__STATIC_INLINE void | LL_UCPD_ClearFlag_FRS (UCPD_TypeDef *UCPDx)
Clear FRS interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TypeCEventCC2 (UCPD_TypeDef *UCPDx)
Clear type c event on CC2.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TypeCEventCC1 (UCPD_TypeDef *UCPDx)
Clear type c event on CC1.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxMsgEnd (UCPD_TypeDef *UCPDx)
Clear Rx message end interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxOvr (UCPD_TypeDef *UCPDx)
Clear Rx overrun interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxHRST (UCPD_TypeDef *UCPDx)
Clear Rx hard resrt interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_RxOrderSet (UCPD_TypeDef *UCPDx)
Clear Rx orderset interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxUND (UCPD_TypeDef *UCPDx)
Clear TX underrun interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxHRSTSENT (UCPD_TypeDef *UCPDx)
Clear hard reset sent interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxHRSTDISC (UCPD_TypeDef *UCPDx)
Clear hard reset discard interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGABT (UCPD_TypeDef *UCPDx)
Clear Tx message abort interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGSENT (UCPD_TypeDef *UCPDx)
Clear Tx message sent interrupt.
__STATIC_INLINE void | LL_UCPD_ClearFlag_TxMSGDISC (UCPD_TypeDef *UCPDx)
Clear Tx message discarded interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_FRS (UCPD_TypeDef const *const UCPDx)
Check if FRS interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TypeCEventCC2 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC2.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TypeCEventCC1 (UCPD_TypeDef const *const UCPDx)
Check if type c event on CC1.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxMsgEnd (UCPD_TypeDef const *const UCPDx)
Check if Rx message end interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxOvr (UCPD_TypeDef const *const UCPDx)
Check if Rx overrun interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxHRST (UCPD_TypeDef const *const UCPDx)
Check if Rx hard resrt interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxOrderSet (UCPD_TypeDef const *const UCPDx)
Check if Rx orderset interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_RxNE (UCPD_TypeDef const *const UCPDx)
Check if Rx non empty interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxUND (UCPD_TypeDef const *const UCPDx)
Check if TX underrun interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxHRSTSENT (UCPD_TypeDef const *const UCPDx)
Check if hard reset sent interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxHRSTDISC (UCPD_TypeDef const *const UCPDx)
Check if hard reset discard interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGABT (UCPD_TypeDef const *const UCPDx)
Check if Tx message abort interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGSENT (UCPD_TypeDef const *const UCPDx)
Check if Tx message sent interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxMSGDISC (UCPD_TypeDef const *const UCPDx)
Check if Tx message discarded interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_IsActiveFlag_TxIS (UCPD_TypeDef const *const UCPDx)
Check if Tx data receive interrupt.
__STATIC_INLINE uint32_t | LL_UCPD_GetTypeCVstateCC2 (UCPD_TypeDef const *const UCPDx)
return the vstate value for CC2
__STATIC_INLINE uint32_t | LL_UCPD_GetTypeCVstateCC1 (UCPD_TypeDef const *const UCPDx)
return the vstate value for CC1
__STATIC_INLINE void | LL_UCPD_RxDMAEnable (UCPD_TypeDef *UCPDx)
Rx DMA Enable.
__STATIC_INLINE void | LL_UCPD_RxDMADisable (UCPD_TypeDef *UCPDx)
Rx DMA Disable.
__STATIC_INLINE void | LL_UCPD_TxDMAEnable (UCPD_TypeDef *UCPDx)
Tx DMA Enable.
__STATIC_INLINE void | LL_UCPD_TxDMADisable (UCPD_TypeDef *UCPDx)
Tx DMA Disable.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabledTxDMA (UCPD_TypeDef const *const UCPDx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint32_t | LL_UCPD_IsEnabledRxDMA (UCPD_TypeDef const *const UCPDx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_UCPD_WriteTxOrderSet (UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
write the orderset for Tx message
__STATIC_INLINE void | LL_UCPD_WriteTxPaySize (UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
write the Tx paysize
__STATIC_INLINE void | LL_UCPD_WriteData (UCPD_TypeDef *UCPDx, uint8_t Data)
Write data.
__STATIC_INLINE uint32_t | LL_UCPD_ReadRxOrderSet (UCPD_TypeDef const *const UCPDx)
read RX the orderset
__STATIC_INLINE uint32_t | LL_UCPD_ReadRxPaySize (UCPD_TypeDef const *const UCPDx)
Read the Rx paysize.
__STATIC_INLINE uint32_t | LL_UCPD_ReadData (UCPD_TypeDef const *const UCPDx)
Read data.
__STATIC_INLINE void | LL_UCPD_SetRxOrdExt1 (UCPD_TypeDef *UCPDx, uint32_t SOPExt)
Set Rx OrderSet Ext1.
__STATIC_INLINE void | LL_UCPD_SetRxOrdExt2 (UCPD_TypeDef *UCPDx, uint32_t SOPExt)
Set Rx OrderSet Ext2.
ErrorStatus | LL_UCPD_DeInit (UCPD_TypeDef *UCPDx)
De-initialize the UCPD registers to their default reset values.
ErrorStatus | LL_UCPD_Init (UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
void | LL_UCPD_StructInit (LL_UCPD_InitTypeDef *UCPD_InitStruct)
Set each LL_UCPD_InitTypeDef field to default value.

Detailed Description

Header file of UCPD LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_ucpd.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_usart.h File Reference

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stm32g0xx_ll_usart.h File Reference

Header file of USART LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NECF USART_ICR_NECF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_UDRCF USART_ICR_UDRCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF
#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_UDR USART_ISR_UDR
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_ISR_TXFE USART_ISR_TXFE
#define | LL_USART_ISR_RXFF USART_ISR_RXFF
#define | LL_USART_ISR_TCBGT USART_ISR_TCBGT
#define | LL_USART_ISR_RXFT USART_ISR_RXFT
#define | LL_USART_ISR_TXFT USART_ISR_TXFT
#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
#define | LL_USART_CR3_RXFTIE USART_CR3_RXFTIE
#define | LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_USART_FIFOTHRESHOLD_8_8 0x00000005U
#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0
#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8
#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA
#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL
#define | LL_USART_PRESCALER_DIV1 0x00000000U
#define | LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)
#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.
#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
#define | LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
#define | LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
#define | LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
#define | LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
#define | LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
#define | LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
#define | LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
#define | LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (const USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableFIFO (USART_TypeDef *USARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_USART_DisableFIFO (USART_TypeDef *USARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledFIFO (const USART_TypeDef *USARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_USART_SetTXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetTXFIFOThreshold (const USART_TypeDef *USARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_SetRXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetRXFIFOThreshold (const USART_TypeDef *USARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_ConfigFIFOsThreshold (USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (const USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (const USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (const USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (const USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (const USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (const USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (const USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (const USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (const USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (const USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_SetPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_USART_GetPrescaler (const USART_TypeDef *USARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (const USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (const USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (const USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (const USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (const USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (const USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (const USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (const USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (const USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (const USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (const USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (const USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (const USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (const USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (const USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (const USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (const USART_TypeDef *USARTx)
Get Block Length value in reception.
__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (const USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (const USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (const USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (const USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (const USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (const USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (const USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (const USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (const USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlave (USART_TypeDef *USARTx)
Enable SPI Synchronous Slave mode.
__STATIC_INLINE void | LL_USART_DisableSPISlave (USART_TypeDef *USARTx)
Disable SPI Synchronous Slave mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlave (const USART_TypeDef *USARTx)
Indicate if SPI Synchronous Slave mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlaveSelect (USART_TypeDef *USARTx)
Enable SPI Slave Selection using NSS input pin.
__STATIC_INLINE void | LL_USART_DisableSPISlaveSelect (USART_TypeDef *USARTx)
Disable SPI Slave Selection using NSS input pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlaveSelect (const USART_TypeDef *USARTx)
Indicate if SPI Slave Selection depends on NSS input pin.
__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (const USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (const USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.
__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (const USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (const USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (const USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (const USART_TypeDef *USARTx)
Return Driver Enable Polarity.
__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (const USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (const USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (const USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (const USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (const USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE_RXFNE (const USART_TypeDef *USARTx)
Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (const USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE_TXFNF (const USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (const USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (const USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (const USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (const USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (const USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_UDR (const USART_TypeDef *USARTx)
Check if the SPI Slave Underrun error flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (const USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (const USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (const USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (const USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (const USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (const USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (const USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (const USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (const USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFE (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFF (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TCBGT (const USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFT (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFT (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise Error detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TXFE (USART_TypeDef *USARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TCBGT (USART_TypeDef *USARTx)
Clear Smartcard Transmission Complete Before Guard Time Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_UDR (USART_TypeDef *USARTx)
Clear SPI Slave Underrun Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFE (USART_TypeDef *USARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFF (USART_TypeDef *USARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFT (USART_TypeDef *USARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TCBGT (USART_TypeDef *USARTx)
Enable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFT (USART_TypeDef *USARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFE (USART_TypeDef *USARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFF (USART_TypeDef *USARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFT (USART_TypeDef *USARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TCBGT (USART_TypeDef *USARTx)
Disable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFT (USART_TypeDef *USARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (const USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE_RXFNE (const USART_TypeDef *USARTx)
Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (const USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE_TXFNF (const USART_TypeDef *USARTx)
Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (const USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (const USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (const USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (const USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFE (const USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFF (const USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (const USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (const USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (const USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (const USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFT (const USART_TypeDef *USARTx)
Check if USART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TCBGT (const USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFT (const USART_TypeDef *USARTx)
Check if USART RX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (const USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (const USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (const USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (const USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (const USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (const USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data and FIFO flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data and FIFO flush.
ErrorStatus | LL_USART_DeInit (const USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Variables

static const uint32_t | USART_PRESCALER_TAB []

Detailed Description

Header file of USART LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_usart.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_utils.h File Reference

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stm32g0xx_ll_utils.h File Reference

Header file of UTILS LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.
#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U
#define | LL_UTILS_PACKAGETYPE_QFP100 0x00000000U
#define | LL_UTILS_PACKAGETYPE_QFN32_GP 0x00000001U
#define | LL_UTILS_PACKAGETYPE_QFN32_N 0x00000002U
#define | LL_UTILS_PACKAGETYPE_QFN48_GP 0x00000004U
#define | LL_UTILS_PACKAGETYPE_QFN48_N 0x00000005U
#define | LL_UTILS_PACKAGETYPE_WLCSP52 0x00000006U
#define | LL_UTILS_PACKAGETYPE_QFN64_GP 0x00000007U
#define | LL_UTILS_PACKAGETYPE_QFN64_N 0x00000008U
#define | LL_UTILS_PACKAGETYPE_BGA64_N 0x0000000AU
#define | LL_UTILS_PACKAGETYPE_QFP80 0x0000000BU
#define | LL_UTILS_PACKAGETYPE_BGA100 0x0000000CU

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.
ErrorStatus | LL_SetFlashLatency (uint32_t HCLKFrequency)
Update number of Flash wait states in line with new frequency and current voltage range.

Detailed Description

Header file of UTILS LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL UTILS driver contains a set of generic APIs that can be
    used by user:
      (+) Device electronic signature
      (+) Timing functions
      (+) PLL configuration functions

Definition in file stm32g0xx_ll_utils.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_wwdg.h File Reference

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stm32g0xx_ll_wwdg.h File Reference

Header file of WWDG LL module. More...

#include "stm32g0xx.h"

Go to the source code of this file.

Defines

#define | LL_WWDG_CFR_EWI WWDG_CFR_EWI
#define | LL_WWDG_PRESCALER_1 0x00000000u
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)
__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)
__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Detailed Description

Header file of WWDG LL module.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_wwdg.h.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal.c File Reference

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  • STM32G0xx_HAL_Driver
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Defines | Functions | Variables
stm32g0xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32G0xx_HAL_VERSION_MAIN (0x01U)
STM32G0xx HAL Driver version number.
#define | __STM32G0xx_HAL_VERSION_SUB1 (0x04U)
#define | __STM32G0xx_HAL_VERSION_SUB2 (0x05U)
#define | __STM32G0xx_HAL_VERSION_RC (0x00U)
#define | __STM32G0xx_HAL_VERSION
#define | VREFBUF_TIMEOUT_VALUE 10U

Functions

HAL_StatusTypeDef | HAL_Init (void)
Configure the Flash prefetch and the Instruction cache, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32g0xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (HAL_TickFreqTypeDef Freq)
Set new tick Freq.
HAL_TickFreqTypeDef | HAL_GetTickFreq (void)
return tick frequency.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Returns first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Returns second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Returns third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOAnalogSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOAnalogSwitchBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableRemap (uint32_t PinRemap)
Enable the remap on PA11_PA12.
void | HAL_SYSCFG_DisableRemap (uint32_t PinRemap)
Disable the remap on PA11_PA12.
void | HAL_SYSCFG_EnableClampingDiode (uint32_t PinConfig)
Enable Clamping Diode on specified IO.
void | HAL_SYSCFG_DisableClampingDiode (uint32_t PinConfig)
Disable Clamping Diode on specified IO.
void | HAL_SYSCFG_StrobeDBattpinsConfig (uint32_t ConfigDeadBattery)
Strobe configuration of GPIO depending on UCPDx dead battery settings.

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio = (1UL << __NVIC_PRIO_BITS)
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs categories:
         (+) Common HAL APIs
         (+) Services HAL APIs

Definition in file stm32g0xx_hal.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_adc.c File Reference

  • File List
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  • Firmware
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  • STM32G0xx_HAL_Driver
  • Src
Defines | Functions
stm32g0xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions Other functions (extended functions) are available in file "stm32g0xx_hal_adc_ex.c". More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_ENABLE_TIMEOUT (2UL)
#define | ADC_DISABLE_TIMEOUT (2UL)
#define | ADC_STOP_CONVERSION_TIMEOUT (2UL)
#define | ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL)
#define | ADC_CHSELR_SQ2_TO_SQ8

Functions

static void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions Other functions (extended functions) are available in file "stm32g0xx_hal_adc_ex.c".

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### ADC peripheral features #####
  ==============================================================================
  [..]
  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.

  (+) Interrupt generation at the end of regular conversion and in case of
      analog watchdog or overrun events.

  (+) Single and continuous conversion modes.

  (+) Scan mode for conversion of several channels sequentially.

  (+) Data alignment with in-built data coherency.

  (+) Programmable sampling time (common to group of channels)

  (+) External trigger (timer or EXTI) with configurable polarity

  (+) DMA request generation for transfer of conversions data of regular group.

  (+) ADC calibration

  (+) ADC conversion of regular group.

  (+) ADC supply requirements: 1.62 V to 3.6 V.

  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).

                     ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Configuration of top level parameters related to ADC ***
     ============================================================
     [..]

    (#) Enable the ADC interface
        (++) As prerequisite, ADC clock must be configured at RCC top level.
             Caution: On STM32G0, ADC clock frequency max is 35MHz (refer
                      to device datasheet).
                      Therefore, ADC clock source from RCC and ADC clock
                      prescaler must be configured to remain below
                      this maximum frequency.

        (++) Two clock settings are mandatory:
             (+++) ADC clock (core clock, also possibly conversion clock).

             (+++) ADC clock (conversions clock).
                   Four possible clock sources: synchronous clock from APB clock (same as ADC core clock)
                   or asynchronous clock from RCC level: SYSCLK, HSI16, PLLPCLK.

             (+++) Example:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory: core clock)

        (++) ADC clock source and clock prescaler are configured at ADC level with
             parameter "ClockPrescaler" using function HAL_ADC_Init().

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
         (++) Configure these ADC pins in analog mode
              using function HAL_GPIO_Init()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Configure the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding ADC interruption vector
              ADCx_IRQHandler().

    (#) Optionally, in case of usage of DMA:
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
              using function HAL_DMA_Init().
         (++) Configure the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding DMA interruption vector
              DMAx_Channelx_IRQHandler().

     *** Configuration of ADC, group regular, channels parameters ***
     ================================================================
     [..]

    (#) Configure the ADC parameters (resolution, data alignment, ...)
        and regular group parameters (conversion trigger, sequencer, ...)
        using function HAL_ADC_Init().

    (#) Configure the channels for regular group parameters (channel number,
        channel rank into sequencer, ..., into regular group)
        using function HAL_ADC_ConfigChannel().

    (#) Optionally, configure the analog watchdog parameters (channels
        monitored, thresholds, ...)
        using function HAL_ADC_AnalogWDGConfig().

     *** Execution of ADC conversions ***
     ====================================
     [..]

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy
        using function HAL_ADCEx_Calibration_Start().

    (#) ADC driver can be used among three modes: polling, interruption,
        transfer by DMA.

        (++) ADC conversion by polling:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start()
          (+++) Wait for ADC conversion completion
                using function HAL_ADC_PollForConversion()
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop()

        (++) ADC conversion by interruption:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_IT()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback()
                (this function must be implemented in user program)
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_IT()

        (++) ADC conversion with transfer by DMA:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_DMA()

     [..]

    (@) Callback functions must be implemented in user program:
      (+@) HAL_ADC_ErrorCallback()
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
      (+@) HAL_ADC_ConvCpltCallback()
      (+@) HAL_ADC_ConvHalfCpltCallback

     *** Deinitialization of ADC ***
     ============================================================
     [..]

    (#) Disable the ADC interface
      (++) ADC clock can be hard reset and disabled at RCC top level.
        (++) Hard reset of ADC peripherals
             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
        (++) ADC clock disable
             using the equivalent macro/functions as configuration step.
             (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);

    (#) ADC pins configuration
         (++) Disable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Disable the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)

    (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA
              using function HAL_DMA_Init().
         (++) Disable the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)

    [..]

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_ADC_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function HAL_ADC_RegisterCallback() allows to register following callbacks:
       (+) ConvCpltCallback               : ADC conversion complete callback
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
       (+) ErrorCallback                  : ADC error callback
       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
       (+) EndOfSamplingCallback          : ADC end of sampling callback
       (+) MspInitCallback                : ADC Msp Init callback
       (+) MspDeInitCallback              : ADC Msp DeInit callback
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) ConvCpltCallback               : ADC conversion complete callback
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
       (+) ErrorCallback                  : ADC error callback
       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
       (+) EndOfSamplingCallback          : ADC end of sampling callback
       (+) MspInitCallback                : ADC Msp Init callback
       (+) MspDeInitCallback              : ADC Msp DeInit callback
     [..]

     By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the HAL_ADC_Init()/HAL_ADC_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the HAL_ADC_Init()/HAL_ADC_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
     or HAL_ADC_Init() function.
     [..]

     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

Definition in file stm32g0xx_hal_adc.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_adc_ex.c File Reference

  • File List
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  • STM32G0xx_HAL_Driver
  • Src
Defines | Functions
stm32g0xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Peripheral Control functions Other functions (generic functions) are available in file "stm32g0xx_hal_adc.c". More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_CALIBRATION_TIMEOUT (193024UL)
#define | ADC_DISABLE_TIMEOUT (2UL)

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
__weak void | HAL_ADCEx_ChannelConfigReadyCallback (ADC_HandleTypeDef *hadc)
ADC channel configuration ready callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Peripheral Control functions Other functions (generic functions) are available in file "stm32g0xx_hal_adc.c".

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  [..]
  (@) Sections "ADC peripheral features" and "How to use this driver" are
      available in file of generic functions "stm32g0xx_hal_adc.c".
  [..]

Definition in file stm32g0xx_hal_adc_ex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cec.c File Reference

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Functions
stm32g0xx_hal_cec.c File Reference

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CEC_Init (CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_CEC_DeInit (CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef | HAL_CEC_SetDeviceAddress (CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
__weak void | HAL_CEC_MspInit (CEC_HandleTypeDef *hcec)
CEC MSP Init.
__weak void | HAL_CEC_MspDeInit (CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
HAL_StatusTypeDef | HAL_CEC_RegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback)
Register a User CEC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterCallback (CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
Unregister an CEC Callback CEC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CEC_RegisterRxCpltCallback (CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
Register CEC RX complete Callback To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_UnRegisterRxCpltCallback (CEC_HandleTypeDef *hcec)
UnRegister CEC RX complete Callback CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback.
HAL_StatusTypeDef | HAL_CEC_Transmit_IT (CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, const uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
uint32_t | HAL_CEC_GetLastReceivedFrameSize (const CEC_HandleTypeDef *hcec)
Get size of the received frame.
void | HAL_CEC_ChangeRxBuffer (CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
void | HAL_CEC_IRQHandler (CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
__weak void | HAL_CEC_TxCpltCallback (CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
__weak void | HAL_CEC_RxCpltCallback (CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
__weak void | HAL_CEC_ErrorCallback (CEC_HandleTypeDef *hcec)
CEC error callbacks.
HAL_CEC_StateTypeDef | HAL_CEC_GetState (const CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t | HAL_CEC_GetError (const CEC_HandleTypeDef *hcec)
Return the CEC error code.

Detailed Description

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The CEC HAL driver can be used as follow:

    (#) Declare a CEC_HandleTypeDef handle structure.
    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
        (##) Enable the CEC interface clock.
        (##) CEC pins configuration:
            (+++) Enable the clock for the CEC GPIOs.
            (+++) Configure these CEC pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
             and HAL_CEC_Receive_IT() APIs):
            (+++) Configure the CEC interrupt priority.
            (+++) Enable the NVIC CEC IRQ handle.
            (+++) The specific CEC interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
                  and receive process.

    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
        in case of Bit Rising Error, Error-Bit generation conditions, device logical
        address and Listen mode in the hcec Init structure.

    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.

  [..]
    (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
        by calling the customed HAL_CEC_MspInit() API.
  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
  to register an interrupt callback.

  Function HAL_CEC_RegisterCallback() allows to register following callbacks:
    (+) TxCpltCallback     : Tx Transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CEC MspInit.
    (+) MspDeInitCallback  : CEC MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
  HAL_CEC_RegisterRxCpltCallback().

  Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) TxCpltCallback     : Tx Transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CEC MspInit.
    (+) MspDeInitCallback  : CEC MspDeInit.

  For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
  HAL_CEC_UnRegisterRxCpltCallback().

  By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
  all callbacks are set to the corresponding weak functions :
  examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
  keep and use the user MspInit/MspDeInit functions (registered beforehand)

  Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
  in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
  or HAL_CEC_Init() function.

  When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Definition in file stm32g0xx_hal_cec.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_comp.c File Reference

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Defines | Functions
stm32g0xx_hal_comp.c File Reference

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Peripheral control functions + Peripheral state functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | COMP_DELAY_STARTUP_US (80UL)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)
#define | COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Peripheral control functions + Peripheral state functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

================================================================================
          ##### COMP Peripheral features #####
================================================================================

  [..]
      The STM32G0xx device family integrates two analog comparators instances:
      COMP1, COMP2.
      (#) Comparators input minus (inverting input) and input plus (non inverting input)
          can be set to internal references or to GPIO pins
          (refer to GPIO list in reference manual).

      (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
          and can be redirected to other peripherals: GPIO pins (in mode
          alternate functions for comparator), timers.
          (refer to GPIO list in reference manual).

      (#) The comparators have interrupt capability through the EXTI controller
          with wake-up from sleep and stop modes.

      (#) Pairs of comparators instances can be combined in window mode
          (2 consecutive instances odd and even COMP<x> and COMP<x+1>).

          From the corresponding IRQ handler, the right interrupt source can be retrieved
          using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().

            ##### How to use this driver #####
================================================================================
  [..]
      This driver provides functions to configure and program the comparator instances
      of STM32G0xx devices.

      To use the comparator, perform the following steps:

      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
           using HAL_GPIO_Init().
      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
           using HAL_GPIO_Init().
      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
           interrupt vector using HAL_NVIC_EnableIRQ() function.

      (#) Configure the comparator using HAL_COMP_Init() function:
      (++) Select the input minus (inverting input)
      (++) Select the input plus (non-inverting input)
      (++) Select the hysteresis
      (++) Select the blanking source
      (++) Select the output polarity
      (++) Select the power mode
      (++) Select the window mode

      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
          to enable internal control clock of the comparators.
          However, this is a legacy strategy. In future STM32 families,
          COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
          Therefore, for compatibility anticipation, it is recommended to
          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".

      (#) Reconfiguration on-the-fly of comparator can be done by calling again
          function HAL_COMP_Init() with new input structure parameters values.

      (#) Enable the comparator using HAL_COMP_Start() function.

      (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
          to manage comparator outputs (events and output level).

      (#) Disable the comparator using HAL_COMP_Stop() function.

      (#) De-initialize the comparator using HAL_COMP_DeInit() function.

      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
          The only way to unlock the comparator is a device hardware reset.

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_COMP_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function HAL_COMP_RegisterCallback() allows to register following callbacks:
       (+) TriggerCallback       : callback for COMP trigger.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) TriggerCallback       : callback for COMP trigger.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     [..]

     By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     example HAL_COMP_TriggerCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
     or HAL_COMP_Init() function.
     [..]

     When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

Definition in file stm32g0xx_hal_comp.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cortex.c File Reference

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Functions
stm32g0xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
uint32_t | HAL_NVIC_GetPriority (IRQn_Type IRQn)
Get the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_Disable (void)
Disable the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex M0+ exceptions are managed by CMSIS functions.
      (#) Enable and Configure the priority of the selected IRQ Channels.
             The priority can be 0..3.

        -@- Lower priority values gives higher priority.
        -@- Priority Order:
            (#@) Lowest priority.
            (#@) Lowest hardware priority (IRQn position).

      (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()

      (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()

      -@-  Negative value of IRQn_Type are not allowed.

    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x03).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32g0xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_cortex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_crc.c File Reference

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stm32g0xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.
HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..]
         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
         (+) Initialize CRC calculator
             (++) specify generating polynomial (peripheral default or non-default one)
             (++) specify initialization value (peripheral default or non-default one)
             (++) specify input data format
             (++) specify input or output data inversion mode if any
         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
             input data buffer starting with the previously computed CRC as
             initialization value
         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
             input data buffer starting with the defined initialization value
             (default or non-default) to initiate CRC calculation

Definition in file stm32g0xx_hal_crc.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_crc_ex.c File Reference

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stm32g0xx_hal_crc_ex.c File Reference

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

================================================================================
            ##### How to use this driver #####
================================================================================
    [..]
         (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
         (+) Configure Input or Output data inversion

Definition in file stm32g0xx_hal_crc_ex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cryp.c File Reference

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Defines | Functions
stm32g0xx_hal_cryp.c File Reference

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define | CRYP_PHASE_READY 0x00000001U
#define | CRYP_PHASE_PROCESS 0x00000002U
#define | CRYP_PHASE_HEADER_SUSPENDED 0x00000004U
#define | CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U
#define | CRYP_PHASE_HEADER_DMA_FEED 0x00000006U
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER AES_CR_GCMPH_0
#define | CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
#define | CRYP_PHASE_FINAL AES_CR_GCMPH
#define | CRYP_CCM_CTR1_0 0x07FFFFFFU
#define | CRYP_CCM_CTR1_1 0xFFFFFF00U
#define | CRYP_CCM_CTR1_2 0x00000001U
#define | CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))

Functions

static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static HAL_StatusTypeDef | CRYP_SetHeaderDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
Set the DMA configuration and start the header DMA transfer.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_SetKey (CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
Writes Key in Key registers.
static void | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
static void | CRYP_GCMCCM_SetPayloadPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in interrupt mode.
static void | CRYP_GCMCCM_SetHeaderPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetPayloadPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in DMA mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
static HAL_StatusTypeDef | CRYP_AESCCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_IT (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static void | CRYP_AES_ProcessData (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
static HAL_StatusTypeDef | CRYP_AES_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_IT (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Encrypt_IT (CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_DMA (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
static HAL_StatusTypeDef | CRYP_WaitOnCCFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
static void | CRYP_ClearCCFlagWhenHigh (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Wait for Computation Complete Flag (CCF) to raise then clear it.
static void | CRYP_Read_IVRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Output)
In case of message processing suspension, read the Initialization Vector.
static void | CRYP_Write_IVRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Input)
In case of message processing resumption, rewrite the Initialization Vector in the AES_IVRx registers.
static void | CRYP_Read_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Output)
In case of message GCM/GMAC/CCM processing suspension, read the Suspend Registers.
static void | CRYP_Write_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Input)
In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend Registers in the AES_SUSPxR registers.
static void | CRYP_Read_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize)
In case of message GCM/GMAC/CCM processing suspension, read the Key Registers.
static void | CRYP_Write_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize)
In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key Registers in the AES_KEYRx registers.
static void | CRYP_PhaseProcessingResume (CRYP_HandleTypeDef *hcryp)
Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callback is redirected to the weak predefined callback.
void | HAL_CRYP_ProcessSuspend (CRYP_HandleTypeDef *hcryp)
Request CRYP processing suspension when in interruption mode.
HAL_StatusTypeDef | HAL_CRYP_Suspend (CRYP_HandleTypeDef *hcryp)
CRYP processing suspension and peripheral internal parameters storage.
HAL_StatusTypeDef | HAL_CRYP_Resume (CRYP_HandleTypeDef *hcryp)
CRYP processing resumption.
HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.

Detailed Description

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows:

      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
         (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
             (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams one for managing data transfer from
                 memory to peripheral (input stream) and another stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA channels. The output channel should have higher
                 priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().

      (#)Initialize the CRYP according to the specified parameters :
         (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
         (##) The key size: 128, 192 or 256.
         (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
         (##) The initialization vector (counter). It is not used in ECB mode.
         (##) The key buffer used for encryption/decryption.
             (+++) In some specific configurations, the key is written by the application
                   code out of the HAL scope. In that case, user can still resort to the
                   HAL APIs as usual but must make sure that pKey pointer is set to NULL.
         (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
               algorithms) is in words or bytes.
         (##) The Header used only in AES GCM and CCM Algorithm for authentication.
         (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field.
         (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes.
         (##) The B0 block is the first authentication block used only in AES CCM mode.
         (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).

      (#)Three processing (encryption/decryption) functions are available:
         (##) Polling mode: encryption and decryption APIs are blocking functions
              i.e. they process the data and wait till the processing is finished,
              e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
              i.e. they process the data under interrupt,
              e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
         (##) DMA mode: encryption and decryption APIs are not blocking functions
              i.e. the data transfer is ensured by DMA,
              e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

      (#)When the processing function is called at first time after HAL_CRYP_Init()
         the CRYP peripheral is configured and processes the buffer in input.
         At second call, no need to Initialize the CRYP, user have to get current configuration via
         HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
         new parametres, finally user can  start encryption/decryption.

       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.

       (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
          without having to configure again the Key or the Initialization Vector between each API call,
          the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
          Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
          or HAL_CRYP_Decrypt_DMA().

    [..]
      The cryptographic processor supports following standards:
      (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 peripheral:
         (##)64-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
         (##) keys length supported :64-bit, 128-bit and 192-bit.
      (#) The advanced encryption standard (AES) supported  by CRYP1 & TinyAES peripheral:
         (##)128-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
             (+++)  Counter mode (CTR)
             (+++)  Galois/counter mode (GCM/GMAC)
             (+++)  Counter with Cipher Block Chaining-Message(CCM)
         (##) keys length Supported :
             (+++) for CRYP1 peripheral: 128-bit, 192-bit and 256-bit.
             (+++) for TinyAES peripheral:  128-bit and 256-bit

    [..]
    (@) Specific care must be taken to format the key and the Initialization Vector IV!

    [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
         b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
         (+) as a sequence of words where the MSB word comes first (occupies the
           lowest memory address)
          (++)   address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96
          (++)   address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64
          (++)   address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32
          (++)   address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0
     [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
         The 4 32-bit words that make the key must be stored as follows in MCU memory:
          (+)    address n+0 : 0x B15 B14 B13 B12
          (+)    address n+4 : 0x B11 B10 B9 B8
          (+)    address n+8 : 0x B7 B6 B5 B4
          (+)    address n+C : 0x B3 B2 B1 B0
     [..]  which leads to the expected setting
       (+)       AES_KEYR3 = 0x B15 B14 B13 B12
       (+)       AES_KEYR2 = 0x B11 B10 B9 B8
       (+)       AES_KEYR1 = 0x B7 B6 B5 B4
       (+)       AES_KEYR0 = 0x B3 B2 B1 B0

    [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
          The 8 32-bit words that make the key must be stored as follows in MCU memory:
          (+)    address n+00 : 0x B31 B30 B29 B28
          (+)    address n+04 : 0x B27 B26 B25 B24
          (+)    address n+08 : 0x B23 B22 B21 B20
          (+)    address n+0C : 0x B19 B18 B17 B16
          (+)    address n+10 : 0x B15 B14 B13 B12
          (+)    address n+14 : 0x B11 B10 B9 B8
          (+)    address n+18 : 0x B7 B6 B5 B4
          (+)    address n+1C : 0x B3 B2 B1 B0
     [..]  which leads to the expected setting
       (+)       AES_KEYR7 = 0x B31 B30 B29 B28
       (+)       AES_KEYR6 = 0x B27 B26 B25 B24
       (+)       AES_KEYR5 = 0x B23 B22 B21 B20
       (+)       AES_KEYR4 = 0x B19 B18 B17 B16
       (+)       AES_KEYR3 = 0x B15 B14 B13 B12
       (+)       AES_KEYR2 = 0x B11 B10 B9 B8
       (+)       AES_KEYR1 = 0x B7 B6 B5 B4
       (+)       AES_KEYR0 = 0x B3 B2 B1 B0

    [..] Initialization Vector IV (4 32-bit words) format must follow the same as
         that of a 128-bit long key.

    [..] Note that key and IV registers are not sensitive to swap mode selection.

    [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 and TinyAES peripherals:
      (#)  Algorithm supported :
         (##) Galois/counter mode (GCM)
         (##) Galois message authentication code (GMAC) :is exactly the same as
              GCM algorithm composed only by an header.
      (#)  Four phases are performed in GCM :
         (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
      (#)  structure of message construction in GCM is defined as below  :
         (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
         (##) The authenticated header A (also knows as Additional Authentication Data AAD)
          this part of the message is only authenticated, not encrypted.
         (##) The plaintext message P is both authenticated and encrypted as ciphertext.
          GCM standard specifies that ciphertext has same bit length as the plaintext.
         (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
          (on 64 bits)

    [..]  A more detailed description of the GCM message structure is available below.

    [..]  This section describe The AES Counter with Cipher Block Chaining-Message
          Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
      (#)  Specific parameters for CCM  :

         (##) B0 block  : follows NIST Special Publication 800-38C,
         (##) B1 block (header)
         (##) CTRx block  : control blocks

    [..]  A detailed description of the CCM message structure is available below.

      (#)  Four phases are performed in CCM for CRYP1 peripheral:
         (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
      (#)    CCM in TinyAES peripheral:
         (##) To perform message payload encryption or decryption AES is configured in CTR mode.
         (##) For authentication two phases are performed :
          - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
          only cleartext payload (not the ciphertext payload) is used and no outpout.
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.

  *** Callback registration ***
  =============================

  [..]
  The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
  to register an interrupt callback.

  [..]
  Function HAL_CRYP_RegisterCallback() allows to register following callbacks:
    (+) InCpltCallback     :  Input FIFO transfer completed callback.
    (+) OutCpltCallback    : Output FIFO transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CRYP MspInit.
    (+) MspDeInitCallback  : CRYP MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  [..]
  Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) InCpltCallback     :  Input FIFO transfer completed callback.
    (+) OutCpltCallback    : Output FIFO transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CRYP MspInit.
    (+) MspDeInitCallback  : CRYP MspDeInit.

  [..]
  By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
  all callbacks are set to the corresponding weak functions :
  examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit()
  keep and use the user MspInit/MspDeInit functions (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
  in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit()
  or HAL_CRYP_Init() function.

  [..]
  When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

  *** Suspend/Resume feature ***
  ==============================

  [..]
  The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
  allows the user to resort to the suspend/resume feature.
  A low priority block processing can be suspended to process a high priority block
  instead. When the high priority block processing is over, the low priority block
  processing can be resumed, restarting from the point where it was suspended. This
  feature is applicable only in non-blocking interrupt mode.

  [..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block
  processing. This API manages the hardware block processing suspension and saves all the
  internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion,
  the user can launch the processing of any other block (high priority block processing).

  [..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume()
  to resume the low priority block processing. Ciphering (or deciphering) restarts from
  the suspension point and ends as usual.

  [..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late
  (i.e when the low priority block processing is about to end). There is no use to
  suspend the tag generation processing for authentication algorithms.

    [..]
    (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user),
        the block processing suspension/resumption mechanism is NOT applicable.

    [..]
    (@) If the Key and Initialization Vector are configured only once and configuration is
        skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE),
        the block processing suspension/resumption mechanism is NOT applicable.

Definition in file stm32g0xx_hal_cryp.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cryp_ex.c File Reference

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Defines | Functions
stm32g0xx_hal_cryp_ex.c File Reference

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER AES_CR_GCMPH_0
#define | CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
#define | CRYP_PHASE_FINAL AES_CR_GCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYPEx_PHASE_PROCESS 0x02U
#define | CRYPEx_PHASE_FINAL 0x03U
#define | CRYP_CCM_CTR0_0 0x07FFFFFFU
#define | CRYP_CCM_CTR0_3 0xFFFFFF00U

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.
void | HAL_CRYPEx_EnableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES enable key derivation functions.
void | HAL_CRYPEx_DisableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES disable key derivation functions.

Detailed Description

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_cryp_ex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dac.c File Reference

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Defines | Functions
stm32g0xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
HAL_StatusTypeDef | HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
Register a User DAC Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
Unregister a User DAC Callback DAC Callback is redirected to the weak (surcharged) predefined callback.
void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    STM32G0 devices integrate two 12-bit Digital Analog Converters

    The 2 converters (i.e. channel1 & channel2)
    can be used independently or simultaneously (dual mode):
      (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
          peripherals (ex. timers).
      (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
          peripherals (ex. timers).

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_PIN_9) must be configured in input mode.

      (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7
          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)

      (#) Software using DAC_TRIGGER_SOFTWARE

      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

      *** GPIO configurations guidelines ***
      =====================
      [..]
      When a DAC channel is used (ex channel1 on PA4) and the other is not
      (ex channel2 on PA5 is configured in Analog and disabled).
      Channel1 may disturb channel2 as coupling effect.
      Note that there is no coupling on channel2 as soon as channel2 is turned on.
      Coupling on adjacent channel could be avoided as follows:
      when unused PA5 is configured as INPUT PULL-UP or DOWN.
      PA5 is configured in ANALOG just before it is turned on.

      *** DAC Sample and Hold feature ***
      ========================
      [..]
      For each converter, 2 modes are supported: normal mode and
      "sample and hold" mode (i.e. low power mode).
      In the sample and hold mode, the DAC core converts data, then holds the
      converted voltage on a capacitor. When not converting, the DAC cores and
      buffer are completely turned off between samples and the DAC output is
      tri-stated, therefore  reducing the overall power consumption. A new
      stabilization period is needed before each new conversion.

      The sample and hold allow setting internal or external voltage @
      low power consumption cost (output value can be at any given rate either
      by CPU or DMA).

      The Sample and hold block and registers uses either LSI & run in
      several power modes: run mode, sleep mode, low power run, low power sleep
      mode & stop1 mode.

      Low power stop1 mode allows only static conversion.

      To enable Sample and Hold mode
      Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
      RCC_LSI_ON parameters.

      Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
         & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
           DAC_HoldTime & DAC_RefreshTime;

       *** DAC calibration feature ***
       ===================================
      [..]
       (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
       (++) Calibration aims at correcting some offset of output buffer.
       (++) The DAC uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_DACEx_SelfCalibrate.
       (++) HAL_DACEx_SelfCalibrate:
       (+++) Runs automatically the calibration.
       (+++) Enables the user trimming mode
       (+++) Updates a structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels can be used to generate
         (#) Noise wave
         (#) Triangle wave

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondence ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       [..]
       DAC_OUTx = VREF+ * DOR / 4095
       (+) with  DOR is the Data Output Register
       [..]
          VREF+ is the input voltage reference (refer to the device datasheet)
       [..]
        e.g. To set DAC_OUT1 to 0.7V, use
       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V

       *** DMA requests ***
       =====================
       [..]
       A DMA request can be generated when an external trigger (but not a software trigger)
       occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
       DMA requests are mapped as following:
      (#) DAC channel1: mapped on DMA request 8 (can be any DMA channel)
      (#) DAC channel2: mapped on DMA request 9 (can be any DMA channel)

     [..]
    (@) For Dual mode and specific signal (Triangle and noise) generation please
        refer to Extended Features Driver description

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.

     *** Calibration mode IO operation ***
     ======================================
     [..]
       (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
       (+) Run the calibration using HAL_DACEx_SelfCalibrate()
       (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
           First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

    Use Functions HAL_DAC_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
      (+) MspInitCallback         : DAC MspInit.
      (+) MspDeInitCallback       : DAC MspdeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

    Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
      (+) MspInitCallback         : DAC MspInit.
      (+) MspDeInitCallback       : DAC MspdeInit.
      (+) All Callbacks
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
      and  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
      or HAL_DAC_Init function.

      When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros

Definition in file stm32g0xx_hal_dac.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dac_ex.c File Reference

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stm32g0xx_hal_dac_ex.c File Reference

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DACEx_DualStart (DAC_HandleTypeDef *hdac)
Enables DAC and starts conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_DualStop (DAC_HandleTypeDef *hdac)
Disables DAC and stop conversion of both channels.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Dual mode IO operation ***
     ==============================
     [..]
      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
          Channel 1 and Channel 2.

     *** Signal generation operation ***
     ===================================
     [..]
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.

      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
          after reset, user setting if HAL_DACEx_SetUserTrimming have been used
          at least one time after reset).

Definition in file stm32g0xx_hal_dac_ex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dma.c File Reference

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Functions
stm32g0xx_hal_dma.c File Reference

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on channel number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA handle state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Channel
       (except for internal SRAM / FLASH memories: no initialization is
       necessary). Please refer to the Reference manual for connection between peripherals
       and DMA requests.

   (#) For a given Channel, program the required configuration through the following parameters:
       Channel request, Transfer Direction, Source and Destination data formats,
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
       using HAL_DMA_Init() function.

       Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
       thanks to:
      (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE();

   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
       detection.

   (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
           address and destination address and the Length of data to be transferred
       (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
           case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
       (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
       (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
           Source address and destination address and the Length of data to be transferred.
           In this case the DMA interrupt is configured
       (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
       (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function to register callbacks with HAL_DMA_RegisterCallback().

     *** DMA HAL driver macros list ***
     =============================================
     [..]
       Below the list of macros in DMA HAL driver.

       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros

Definition in file stm32g0xx_hal_dma.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dma_ex.c File Reference

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stm32g0xx_hal_dma_ex.c File Reference

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
  The DMA Extension HAL driver can be used as follows:
   (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
   (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
       to respectively enable/disable the request generator.

   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_dma_ex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_exti.c File Reference

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Defines | Functions
stm32g0xx_hal_exti.c File Reference

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
#define | EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicaated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.
void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### EXTI Peripheral features #####
  ==============================================================================
  [..]
    (+) Each Exti line can be configured within this driver.

    (+) Exti line can be configured in 3 different modes
        (++) Interrupt
        (++) Event
        (++) Both of them

    (+) Configurable Exti lines can be configured with 3 different triggers
        (++) Rising
        (++) Falling
        (++) Both of them

    (+) When set in interrupt mode, configurable Exti lines have two diffenrents
        interrupt pending registers which allow to distinguish which transition
        occurs:
        (++) Rising edge pending interrupt
        (++) Falling

    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
        be selected through multiplexer.

                     ##### How to use this driver #####
  ==============================================================================
  [..]

    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
        (++) Choose the interrupt line number by setting "Line" member from
             EXTI_ConfigTypeDef structure.
        (++) Configure the interrupt and/or event mode using "Mode" member from
             EXTI_ConfigTypeDef structure.
        (++) For configurable lines, configure rising and/or falling trigger
             "Trigger" member from EXTI_ConfigTypeDef structure.
        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
             member from GPIO_InitTypeDef structure.

    (#) Get current Exti configuration of a dedicated line using
        HAL_EXTI_GetConfigLine().
        (++) Provide exiting handle as parameter.
        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.

    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
        (++) Provide exiting handle as parameter.

    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
        (++) Provide exiting handle as first parameter.
        (++) Provide which callback will be registered using one value from
             EXTI_CallbackIDTypeDef.
        (++) Provide callback function pointer.

    (#) Get interrupt pending bit using HAL_EXTI_GetPending().

    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().

    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().

Definition in file stm32g0xx_hal_exti.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_fdcan.c File Reference

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stm32g0xx_hal_fdcan.c File Reference

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | FDCAN_TIMEOUT_VALUE 10U
#define | FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
#define | FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
#define | FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
#define | FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
#define | FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
#define | FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define | FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define | FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define | FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define | FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define | FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define | FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define | FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define | FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define | FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define | FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define | FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define | FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
#define | SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
#define | SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */
#define | SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */
#define | SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */
#define | SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */
#define | SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */
#define | SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */
#define | SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */
#define | SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
#define | SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
#define | SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */
#define | SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
#define | SRAMCAN_FLSSA
#define | SRAMCAN_FLESA
#define | SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
#define | SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
#define | SRAMCAN_TEFSA
#define | SRAMCAN_TFQSA
#define | SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */

Functions

static void | FDCAN_CalcultateRamBlockAddresses (FDCAN_HandleTypeDef *hfdcan)
Calculate each RAM block start address and size.
static void | FDCAN_CopyMessageToRAM (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
Copy Tx message to the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_Init (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN peripheral according to the specified parameters in the FDCAN_InitTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_DeInit (FDCAN_HandleTypeDef *hfdcan)
Deinitializes the FDCAN peripheral registers to their default reset values.
__weak void | HAL_FDCAN_MspInit (FDCAN_HandleTypeDef *hfdcan)
Initializes the FDCAN MSP.
__weak void | HAL_FDCAN_MspDeInit (FDCAN_HandleTypeDef *hfdcan)
DeInitializes the FDCAN MSP.
HAL_StatusTypeDef | HAL_FDCAN_EnterPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Enter FDCAN peripheral in sleep mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitPowerDownMode (FDCAN_HandleTypeDef *hfdcan)
Exit power down mode.
HAL_StatusTypeDef | HAL_FDCAN_RegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void(*pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
Register a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterCallback (FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
Unregister a FDCAN CallBack.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
Register Tx Event Fifo FDCAN Callback To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Event Fifo FDCAN Callback Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
Register Rx Fifo 0 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo0Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 0 FDCAN Callback Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
Register Rx Fifo 1 FDCAN Callback To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterRxFifo1Callback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Rx Fifo 1 FDCAN Callback Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
Register Tx Buffer Complete FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Complete FDCAN Callback Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
Register Tx Buffer Abort FDCAN Callback To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterTxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Tx Buffer Abort FDCAN Callback Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_RegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
Register Error Status FDCAN Callback To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_UnRegisterErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan)
UnRegister the Error Status FDCAN Callback Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback.
HAL_StatusTypeDef | HAL_FDCAN_ConfigFilter (FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
Configure the FDCAN reception filter according to the specified parameters in the FDCAN_FilterTypeDef structure.
HAL_StatusTypeDef | HAL_FDCAN_ConfigGlobalFilter (FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt)
Configure the FDCAN global filter.
HAL_StatusTypeDef | HAL_FDCAN_ConfigExtendedIdMask (FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
Configure the extended ID mask.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRxFifoOverwrite (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
Configure the Rx FIFO operation mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigRamWatchdog (FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
Configure the RAM watchdog.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
Configure the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimestampCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
Enable the timestamp counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timestamp counter.
uint16_t | HAL_FDCAN_GetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timestamp counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimestampCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timestamp counter to zero.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTimeoutCounter (FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
Configure the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_EnableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Enable the timeout counter.
HAL_StatusTypeDef | HAL_FDCAN_DisableTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Disable the timeout counter.
uint16_t | HAL_FDCAN_GetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Get the timeout counter value.
HAL_StatusTypeDef | HAL_FDCAN_ResetTimeoutCounter (FDCAN_HandleTypeDef *hfdcan)
Reset the timeout counter to its start value.
HAL_StatusTypeDef | HAL_FDCAN_ConfigTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
Configure the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Enable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_DisableTxDelayCompensation (FDCAN_HandleTypeDef *hfdcan)
Disable the transmitter delay compensation.
HAL_StatusTypeDef | HAL_FDCAN_EnableISOMode (FDCAN_HandleTypeDef *hfdcan)
Enable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_DisableISOMode (FDCAN_HandleTypeDef *hfdcan)
Disable ISO 11898-1 protocol mode.
HAL_StatusTypeDef | HAL_FDCAN_EnableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Enable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_DisableEdgeFiltering (FDCAN_HandleTypeDef *hfdcan)
Disable edge filtering during bus integration.
HAL_StatusTypeDef | HAL_FDCAN_Start (FDCAN_HandleTypeDef *hfdcan)
Start the FDCAN module.
HAL_StatusTypeDef | HAL_FDCAN_Stop (FDCAN_HandleTypeDef *hfdcan)
Stop the FDCAN module and enable access to configuration registers.
HAL_StatusTypeDef | HAL_FDCAN_AddMessageToTxFifoQ (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
Add a message to the Tx FIFO/Queue and activate the corresponding transmission request.
uint32_t | HAL_FDCAN_GetLatestTxFifoQRequestBuffer (FDCAN_HandleTypeDef *hfdcan)
Get Tx buffer index of latest Tx FIFO/Queue request.
HAL_StatusTypeDef | HAL_FDCAN_AbortTxRequest (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
Abort transmission request.
HAL_StatusTypeDef | HAL_FDCAN_GetRxMessage (FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
Get an FDCAN frame from the Rx FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetTxEvent (FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
HAL_StatusTypeDef | HAL_FDCAN_GetHighPriorityMessageStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
Get high priority message status.
HAL_StatusTypeDef | HAL_FDCAN_GetProtocolStatus (FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
Get protocol status.
HAL_StatusTypeDef | HAL_FDCAN_GetErrorCounters (FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
Get error counter values.
uint32_t | HAL_FDCAN_IsTxBufferMessagePending (FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
Check if a transmission request is pending on the selected Tx buffer.
uint32_t | HAL_FDCAN_GetRxFifoFillLevel (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
Return Rx FIFO fill level.
uint32_t | HAL_FDCAN_GetTxFifoFreeLevel (FDCAN_HandleTypeDef *hfdcan)
Return Tx FIFO free level: number of consecutive free Tx FIFO elements starting from Tx FIFO GetIndex.
uint32_t | HAL_FDCAN_IsRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Check if the FDCAN peripheral entered Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ExitRestrictedOperationMode (FDCAN_HandleTypeDef *hfdcan)
Exit Restricted Operation Mode.
HAL_StatusTypeDef | HAL_FDCAN_ConfigInterruptLines (FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
Assign interrupts to either Interrupt line 0 or 1.
HAL_StatusTypeDef | HAL_FDCAN_ActivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
Enable interrupts.
HAL_StatusTypeDef | HAL_FDCAN_DeactivateNotification (FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
Disable interrupts.
void | HAL_FDCAN_IRQHandler (FDCAN_HandleTypeDef *hfdcan)
Handles FDCAN interrupt request.
__weak void | HAL_FDCAN_TxEventFifoCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
Tx Event callback.
__weak void | HAL_FDCAN_RxFifo0Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
Rx FIFO 0 callback.
__weak void | HAL_FDCAN_RxFifo1Callback (FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
Rx FIFO 1 callback.
__weak void | HAL_FDCAN_TxFifoEmptyCallback (FDCAN_HandleTypeDef *hfdcan)
Tx FIFO Empty callback.
__weak void | HAL_FDCAN_TxBufferCompleteCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Complete callback.
__weak void | HAL_FDCAN_TxBufferAbortCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
Transmission Cancellation callback.
__weak void | HAL_FDCAN_TimestampWraparoundCallback (FDCAN_HandleTypeDef *hfdcan)
Timestamp Wraparound callback.
__weak void | HAL_FDCAN_TimeoutOccurredCallback (FDCAN_HandleTypeDef *hfdcan)
Timeout Occurred callback.
__weak void | HAL_FDCAN_HighPriorityMessageCallback (FDCAN_HandleTypeDef *hfdcan)
High Priority Message callback.
__weak void | HAL_FDCAN_ErrorCallback (FDCAN_HandleTypeDef *hfdcan)
Error callback.
__weak void | HAL_FDCAN_ErrorStatusCallback (FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
Error status callback.
HAL_FDCAN_StateTypeDef | HAL_FDCAN_GetState (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN state.
uint32_t | HAL_FDCAN_GetError (FDCAN_HandleTypeDef *hfdcan)
Return the FDCAN error code.

Variables

static const uint8_t | DLCtoBytes [] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}

Detailed Description

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.

      (#) If needed , configure the reception filters and optional features using
          the following configuration functions:
            (++) HAL_FDCAN_ConfigFilter
            (++) HAL_FDCAN_ConfigGlobalFilter
            (++) HAL_FDCAN_ConfigExtendedIdMask
            (++) HAL_FDCAN_ConfigRxFifoOverwrite
            (++) HAL_FDCAN_ConfigRamWatchdog
            (++) HAL_FDCAN_ConfigTimestampCounter
            (++) HAL_FDCAN_EnableTimestampCounter
            (++) HAL_FDCAN_DisableTimestampCounter
            (++) HAL_FDCAN_ConfigTimeoutCounter
            (++) HAL_FDCAN_EnableTimeoutCounter
            (++) HAL_FDCAN_DisableTimeoutCounter
            (++) HAL_FDCAN_ConfigTxDelayCompensation
            (++) HAL_FDCAN_EnableTxDelayCompensation
            (++) HAL_FDCAN_DisableTxDelayCompensation
            (++) HAL_FDCAN_EnableISOMode
            (++) HAL_FDCAN_DisableISOMode
            (++) HAL_FDCAN_EnableEdgeFiltering
            (++) HAL_FDCAN_DisableEdgeFiltering

      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
          the node is active on the bus: it can send and receive messages.

      (#) The following Tx control functions can only be called when the FDCAN
          module is started:
            (++) HAL_FDCAN_AddMessageToTxFifoQ
            (++) HAL_FDCAN_AbortTxRequest

      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
          get Tx buffer location used to place the Tx request thanks to
          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
          It is then possible to abort later on the corresponding Tx Request using
          HAL_FDCAN_AbortTxRequest API.

      (#) When a message is received into the FDCAN message RAM, it can be
          retrieved using the HAL_FDCAN_GetRxMessage function.

      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
          it to initialization mode and re-enabling access to configuration
          registers through the configuration functions listed here above.

      (#) All other control functions can be called any time after initialization
          phase, no matter if the FDCAN module is started or stopped.

      *** Polling mode operation ***
      ==============================
    [..]
        (#) Reception and transmission states can be monitored via the following
            functions:
              (++) HAL_FDCAN_IsTxBufferMessagePending
              (++) HAL_FDCAN_GetRxFifoFillLevel
              (++) HAL_FDCAN_GetTxFifoFreeLevel

      *** Interrupt mode operation ***
      ================================
      [..]
        (#) There are two interrupt lines: line 0 and 1.
            By default, all interrupts are assigned to line 0. Interrupt lines
            can be configured using HAL_FDCAN_ConfigInterruptLines function.

        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
            function. Then, the process can be controlled through one of the
            available user callbacks: HAL_FDCAN_xxxCallback.

  *** Callback registration ***
  =============================================

  The compilation define  USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
  to register an interrupt callback.

  Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
    (+) HighPriorityMessageCallback  : High Priority Message Callback.
    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
    (+) ErrorCallback                : Error Callback.
    (+) MspInitCallback              : FDCAN MspInit.
    (+) MspDeInitCallback            : FDCAN MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
  TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated
  register callbacks : respectively HAL_FDCAN_RegisterTxEventFifoCallback(),
  HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
  HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback()
  and HAL_FDCAN_RegisterErrorStatusCallback().

  Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
    (+) HighPriorityMessageCallback  : High Priority Message Callback.
    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
    (+) ErrorCallback                : Error Callback.
    (+) MspInitCallback              : FDCAN MspInit.
    (+) MspDeInitCallback            : FDCAN MspDeInit.

  For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
  TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
  unregister callbacks : respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
  HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(),
  HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback()
  and HAL_FDCAN_UnRegisterErrorStatusCallback().

  By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
  all callbacks are set to the corresponding weak functions:
  examples HAL_FDCAN_ErrorCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
  or HAL_FDCAN_Init() function.

  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Definition in file stm32g0xx_hal_fdcan.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_flash.c File Reference

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Functions | Variables
stm32g0xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program double-word (64-bit) at a specified address.
static void | FLASH_Program_Fast (uint32_t Address, uint32_t DataAddress)
Fast program a 32 row double-word (64-bit) at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================

  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
       prefetch and cache lines.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Option bytes programming
      (+) Prefetch on I-Code
      (+) 32 cache lines of 4*64 bits on I-Code
      (+) Error code correction (ECC) : Data in flash are 72-bits word
          (8 bits added per double word)

                        ##### How to use this driver #####
 ==============================================================================
    [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32G0xx devices.

      (#) Flash Memory IO Programming functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Program functions: double word and fast program (full row programming)
           (++) There are two modes of programming:
            (+++) Polling mode using HAL_FLASH_Program() function
            (+++) Interrupt mode using HAL_FLASH_Program_IT() function

      (#) Interrupts and flags management functions:
           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
           (++) Callback functions are called when the flash operations are finished :
                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
                HAL_FLASH_OperationErrorCallback()
           (++) Get error flag status by calling HAL_GetError()

      (#) Option bytes management functions :
           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
                HAL_FLASH_OB_Lock() functions
           (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
                In this case, a reset is generated

    [..]
      In addition to these functions, this driver includes a set of macros allowing
      to handle the following operations:
       (+) Set the latency
       (+) Enable/Disable the prefetch buffer
       (+) Enable/Disable the Instruction cache
       (+) Reset the Instruction cache
       (+) Enable/Disable the Flash power-down during low-power run and sleep modes
       (+) Enable/Disable the Flash interrupts
       (+) Monitor the Flash flags status
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_flash.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_flash_ex.c File Reference

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Functions
stm32g0xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

static void | FLASH_MassErase (uint32_t Banks)
Mass erase of FLASH memory.
void | FLASH_FlushCaches (void)
Flush the instruction cache.
static void | FLASH_OB_WRPConfig (uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
Configure the write protection of the desired pages.
static void | FLASH_OB_GetWRP (uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
Return the FLASH Write Protection Option Bytes value.
static void | FLASH_OB_OptrConfig (uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel)
Set user & RDP configuration.
static uint32_t | FLASH_OB_GetRDP (void)
Return the FLASH Read Protection level.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_PCROP1AConfig (uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
Configure the 1A Proprietary code readout protection & erase configuration on RDP regression.
static void | FLASH_OB_PCROP1BConfig (uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
Configure the 1B Proprietary code readout protection.
static void | FLASH_OB_GetPCROP1A (uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr)
Return the FLASH PCROP Protection Option Bytes value.
static void | FLASH_OB_GetPCROP1B (uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr)
Return the FLASH PCROP Protection Option Bytes value.
static void | FLASH_OB_PCROP2AConfig (uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr)
Configure the 2A Proprietary code readout protection.
static void | FLASH_OB_PCROP2BConfig (uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr)
Configure the 2B Proprietary code readout protection.
static void | FLASH_OB_GetPCROP2A (uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr)
Return the FLASH PCROP Protection Option Bytes value.
static void | FLASH_OB_GetPCROP2B (uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr)
Return the FLASH PCROP Protection Option Bytes value.
static void | FLASH_OB_SecMemConfig (uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2)
Configure Securable Memory area feature.
static void | FLASH_OB_GetSecMem (uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2)
Return the FLASH Securable memory area protection Option Bytes value.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
void | HAL_FLASHEx_EnableDebugger (void)
Enable Debugger.
void | HAL_FLASHEx_DisableDebugger (void)
Disable Debugger.
uint32_t | HAL_FLASHEx_FlashEmptyCheck (void)
Flash Empty check.
void | HAL_FLASHEx_ForceFlashEmpty (uint32_t FlashEmpty)
Force Empty check value.
void | HAL_FLASHEx_EnableSecMemProtection (uint32_t Banks)
Securable memory area protection enable.
void | FLASH_PageErase (uint32_t Banks, uint32_t Page)
Erase the specified FLASH memory page.

Detailed Description

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions.

Author:
MCD Application Team
 ==============================================================================
                   ##### Flash Extended features #####
  ==============================================================================

  [..] Comparing to other previous devices, the FLASH interface for STM32G0xx
       devices contains the following additional features

       (+) Capacity up to 128 Kbytes with single bank architecture supporting read-while-write
           capability (RWW)
       (+) Single bank memory organization
       (+) PCROP protection

                        ##### How to use this driver #####
 ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32G0xx devices. It includes
      (#) Flash Memory Erase functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Erase function: Erase page, erase all sectors
           (++) There are two modes of erase :
             (+++) Polling Mode using HAL_FLASHEx_Erase()
             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()

      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
        (++) Set/Reset the write protection
        (++) Set the Read protection Level
        (++) Program the user Option Bytes
        (++) Configure the PCROP protection
        (++) Set Securable memory area and boot entry point

      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
        (++) Get the value of a write protection area
        (++) Know if the read protection is activated
        (++) Get the value of the user Option Bytes
        (++) Get Securable memory area and boot entry point information

      (#) Enable or disable debugger usage using HAL_FLASHEx_EnableDebugger and
          HAL_FLASHEx_DisableDebugger.

      (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck.
          and modify this setting (for flash loader purpose e.g.) using
          HAL_FLASHEx_ForceFlashEmpty.

      (#) Enable securable memory area protectionusing HAL_FLASHEx_EnableSecMemProtection
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_flash_ex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_gpio.c File Reference

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Defines | Functions
stm32g0xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_NUMBER (16u)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Rising_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.
__weak void | HAL_GPIO_EXTI_Falling_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
        configured by software in several modes:
        (++) Input mode
        (++) Analog mode
        (++) Output mode
        (++) Alternate function mode
        (++) External interrupt/event lines

    (+) During and just after reset, the alternate functions and external interrupt
        lines are not active and the I/O ports are configured in input floating mode.

    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
        activated or not.

    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
        type and the IO speed can be selected depending on the VDD value.

    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
        multiplexer that allows only one peripheral alternate function (AF) connected
       to an IO pin at a time. In this way, there can be no conflict between peripherals
       sharing the same IO pin.

    (+) All ports have external interrupt/event capability. To use external interrupt
        lines, the port must be configured in input mode. All available GPIO pins are
        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

    (+) The external interrupt/event controller consists of up to 28 edge detectors
        (16 lines are connected to GPIO) for generating event/interrupt requests (each
        input line can be independently configured to select the type (interrupt or event)
        and the corresponding trigger event (rising or falling or both). Each line can
        also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.

Definition in file stm32g0xx_hal_gpio.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_hcd.c File Reference

  • File List
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Functions
stm32g0xx_hal_hcd.c File Reference

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Handle Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel OUT interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Host Port interrupt requests.
static void | HAL_HCD_ClearPhyChannel (HCD_HandleTypeDef *hhcd)
Free All Channel allocation.
static uint8_t | HAL_HCD_GetLogical_Channel (HCD_HandleTypeDef *hhcd, uint8_t phy_chnum, uint8_t dir)
Get a Logical Channel number from physical Channel.
static uint8_t | HAL_HCD_Check_usedChannel (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Check if the ch_num are already reserved to a physical channel.
static uint8_t | HAL_HCD_Get_FreePhyChannel (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t ep_type)
Get a free physical Channel number according to the direction.
static void | HCD_HC_IN_BulkDb (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue)
Handle Host Channel IN Double Buffer Bulk requests.
static void | HCD_HC_OUT_BulkDb (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue)
Handle Host Channel OUT Double Buffer Bulk requests.
static uint16_t | HAL_HCD_GetFreePMA (HCD_HandleTypeDef *hhcd, uint16_t mps)
Fetch in the PMA_LockupTable free space of number of mps byte.
static HAL_StatusTypeDef | HAL_HCD_PMAFree (HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps)
PMA Free.
static void | HCD_HC_IN_ISO (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue)
Handle Host Channel IN Isochronous Transaction.
HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Close (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
HAL_HCD_HC_Close Pipe.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
__weak void | HAL_HCD_SuspendCallback (HCD_HandleTypeDef *hhcd)
__weak void | HAL_HCD_ResumeCallback (HCD_HandleTypeDef *hhcd)
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_PortEnabled_Callback (HCD_HandleTypeDef *hhcd)
Port Enabled Event callback.
__weak void | HAL_HCD_PortDisabled_Callback (HCD_HandleTypeDef *hhcd)
Port Disabled Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_RegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
Register a User USB HCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterCallback (HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
Unregister an USB HCD Callback USB HCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_HCD_RegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
Register USB HCD Host Channel Notify URB Change Callback To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_UnRegisterHC_NotifyURBChangeCallback (HCD_HandleTypeDef *hhcd)
Unregister the USB HCD Host Channel Notify URB Change Callback USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the host driver.
HAL_StatusTypeDef | HAL_HCD_Suspend (HCD_HandleTypeDef *hhcd)
Put the Device in suspend mode.
HAL_StatusTypeDef | HAL_HCD_Resume (HCD_HandleTypeDef *hhcd)
Resume host port.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the host port.
HAL_StatusTypeDef | HAL_HCD_ResumePort (HCD_HandleTypeDef *hhcd)
Resme the host port.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.
HAL_StatusTypeDef | HAL_HCD_PMAlloc (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint16_t ch_kind, uint16_t mps)
Allocate PMA buffer for Channel This API will fetch a free space.
HAL_StatusTypeDef | HAL_HCD_PMADeAlloc (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable.
HAL_StatusTypeDef | HAL_HCD_PMAReset (HCD_HandleTypeDef *hhcd)
PMA Reset.

Detailed Description

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
  [..]
    (#)Declare a HCD_HandleTypeDef handle structure, for example:
       HCD_HandleTypeDef  hhcd;

    (#)Fill parameters of Init structure in HCD handle

    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)

    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
        (##) Enable the HCD/USB Low Level interface clock using the following macros
             (+++) __HAL_RCC_USB_CLK_ENABLE();
        (##) Initialize the related GPIO clocks
        (##) Configure HCD pin-out
        (##) Configure HCD NVIC interrupt

    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
        (##) hhcd.pData = phost;

    (#)Enable HCD transmission and reception:
        (##) HAL_HCD_Start();

Definition in file stm32g0xx_hal_hcd.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2c.c File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SLAVE_ADDR_SHIFT 7U
#define | SLAVE_ADDR_MSK 0x06U
#define | I2C_STATE_MSK
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX
#define | I2C_STATE_MASTER_BUSY_RX
#define | I2C_STATE_SLAVE_BUSY_TX
#define | I2C_STATE_SLAVE_BUSY_RX
#define | I2C_STATE_MEM_BUSY_TX
#define | I2C_STATE_MEM_BUSY_RX
#define | I2C_XFER_TX_IT (uint16_t)(0x0001U)
#define | I2C_XFER_RX_IT (uint16_t)(0x0002U)
#define | I2C_XFER_LISTEN_IT (uint16_t)(0x8000U)
#define | I2C_XFER_ERROR_IT (uint16_t)(0x0010U)
#define | I2C_XFER_CPLT_IT (uint16_t)(0x0020U)
#define | I2C_XFER_RELOAD_IT (uint16_t)(0x0040U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define | I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Mem_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Mem_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsErrorOccurred (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles errors detection during an I2C Communication.
static void | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static void | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_TreatErrorCallback (I2C_HandleTypeDef *hi2c)
I2C Error callback treatment.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | I2C_ConvertOtherXferOptions (I2C_HandleTypeDef *hi2c)
Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for
                  the transmit or receive channel
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx channel
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx channel

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode or DMA mode IO sequential operation ***
    ==========================================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
           no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
                            start condition, address and data to transfer without a final stop condition,
                            an then permit a call the same master sequential interface several times
                            (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to
                            transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to
                            transfer
                            if no direction change and with a final stop condition in both cases
      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
                            after several call of the same master sequential interface several times
                            (link with option I2C_FIRST_AND_NEXT_FRAME).
                            Usage can, transfer several bytes one by one using
                              HAL_I2C_Master_Seq_Transmit_IT
                              or HAL_I2C_Master_Seq_Receive_IT
                              or HAL_I2C_Master_Seq_Transmit_DMA
                              or HAL_I2C_Master_Seq_Receive_DMA
                              with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
                              Receive sequence permit to call the opposite interface Receive or Transmit
                              without stopping the communication and so generate a restart condition.
      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
                            each call of the same master sequential
                            interface.
                            Usage can, transfer several bytes one by one with a restart with slave address between
                            each bytes using
                              HAL_I2C_Master_Seq_Transmit_IT
                              or HAL_I2C_Master_Seq_Receive_IT
                              or HAL_I2C_Master_Seq_Transmit_DMA
                              or HAL_I2C_Master_Seq_Receive_DMA
                              with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
                            generation of STOP condition.

      (+) Different sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
            HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
            users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
            HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
            HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
           add their own code to check the Address Match Code and the transmission direction request by master
           (Write/Read).
      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
          add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
            HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
            users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
            HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_I2C_ErrorCallback()

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     *** Callback registration ***
     =============================================
    [..]
     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
     to register an interrupt callback.
    [..]
     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]
     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
    [..]
     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
     weak function.
     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
    [..]
     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
    [..]
     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
    [..]
     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
     or HAL_I2C_Init() function.
    [..]
     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros

Definition in file stm32g0xx_hal_i2c.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2c_ex.c File Reference

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Functions
stm32g0xx_hal_i2c_ex.c File Reference

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Filter Mode Functions + WakeUp Mode Functions + FastModePlus Functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Filter Mode Functions + WakeUp Mode Functions + FastModePlus Functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
               ##### I2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32G0xx
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop mode(s)
       (+) Disable or enable Fast Mode Plus

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
          (++) HAL_I2CEx_EnableWakeUp()
          (++) HAL_I2CEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_I2CEx_EnableFastModePlus()
          (++) HAL_I2CEx_DisableFastModePlus()

Definition in file stm32g0xx_hal_i2c_ex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2s.c File Reference

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Defines | Functions
stm32g0xx_hal_i2s.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | I2S_TIMEOUT_FLAG 100U

Functions

static void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
static void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
static void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
static void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
static void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
static void | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
static void | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
static HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
This function handles I2S Communication Timeout.
HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_RegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
Register a User I2S Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_UnRegisterCallback (I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
Unregister an I2S Callback I2S callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio DMA Stream/Channel playing from the Media.
HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Stops the audio DMA Stream/Channel playing from the Media.
void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The I2S HAL driver can be used as follow:

    (#) Declare a I2S_HandleTypeDef handle structure.
    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
        (##) Enable the SPIx interface clock.
        (##) I2S pins configuration:
            (+++) Enable the clock for the I2S GPIOs.
            (+++) Configure these I2S pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
             and HAL_I2S_Receive_IT() APIs).
            (+++) Configure the I2Sx interrupt priority.
            (+++) Enable the NVIC I2S IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
             and HAL_I2S_Receive_DMA() APIs:
            (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream/Channel.
            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                  DMA Tx/Rx Stream/Channel.

   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_I2S_Init() function.

   -@- The specific I2S interrupts (Transmission complete interrupt,
       RXNE interrupt and Error Interrupts) will be managed using the macros
       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
   -@- Make sure that either:
        (+@) SYSCLK is configured or
        (+@) PLLPCLK output is configured or
        (+@) HSI is enabled or
        (+@) External clock source is configured after setting correctly
             the define constant EXTERNAL_I2S1_CLOCK_VALUE in the stm32g0xx_hal_conf.h file.

    (#) Three mode of operations are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
         In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
         HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
         In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
         inside DR register and avoid using DeInit/Init process for the next transfer.

   *** I2S HAL driver macros list ***
   ===================================
   [..]
     Below the list of most used macros in I2S HAL driver.

      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
      (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data

    [..]
      (@) You can refer to the I2S HAL driver header file for more useful macros

   *** I2S HAL driver macros list ***
   ===================================
   [..]
       Callback registration:

      (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
          allows the user to configure dynamically the driver callbacks.
          Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.

          Function HAL_I2S_RegisterCallback() allows to register following callbacks:
            (++) TxCpltCallback        : I2S Tx Completed callback
            (++) RxCpltCallback        : I2S Rx Completed callback
            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
            (++) ErrorCallback         : I2S Error callback
            (++) MspInitCallback       : I2S Msp Init callback
            (++) MspDeInitCallback     : I2S Msp DeInit callback
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
          weak function.
          HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (++) TxCpltCallback        : I2S Tx Completed callback
            (++) RxCpltCallback        : I2S Rx Completed callback
            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
            (++) ErrorCallback         : I2S Error callback
            (++) MspInitCallback       : I2S Msp Init callback
            (++) MspDeInitCallback     : I2S Msp DeInit callback

       [..]
       By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
       all callbacks are set to the corresponding weak functions:
       examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
       Exception done for MspInit and MspDeInit functions that are
       reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
       these callbacks are null (not registered beforehand).
       If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

       [..]
       Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
       in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
       Then, the user first registers the MspInit/MspDeInit user callbacks
       using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
       or HAL_I2S_Init() function.

       [..]
       When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
       and weak (surcharged) callbacks are used.

Definition in file stm32g0xx_hal_i2s.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_irda.c File Reference

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stm32g0xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000U
#define | IRDA_CR1_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU
#define | IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.

Functions

void | IRDA_InitCallbacksToDefault (IRDA_HandleTypeDef *hirda)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static void | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static void | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (const IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
        in setting the associated USART or UART in IRDA mode:
        (++) Enable the USARTx/UARTx interface clock.
        (++) USARTx/UARTx pins configuration:
            (+++) Enable the clock for the USARTx/UARTx GPIOs.
            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx/UARTx interrupt priority.
            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
            (+++) The specific IRDA interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer
                  complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
        the normal or low power mode and the clock prescaler in the hirda handle Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_IRDA_MspInit() API.

         -@@- The specific IRDA interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** IRDA HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IRDA HAL driver.

       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled

     [..]
       (@) You can refer to the IRDA HAL driver header file for more useful macros

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_IRDA_RegisterCallback() to register a user callback.
    Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) MspInitCallback           : IRDA MspInit.
    (+) MspDeInitCallback         : IRDA MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) MspInitCallback           : IRDA MspInit.
    (+) MspDeInitCallback         : IRDA MspDeInit.

    [..]
    By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
    and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
    or HAL_IRDA_Init() function.

    [..]
    When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.

Definition in file stm32g0xx_hal_irda.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_iwdg.c File Reference

  • File List
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  • STM32G0xx_HAL_Driver
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Defines | Functions
stm32g0xx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define | IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
        active even if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
        disabled. The counter starts counting down from the reset value (0xFFF).
        When it reaches the end of count value (0x000) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded into the counter and the watchdog reset
        is prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode: When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI clock frequency dispersion.
         STM32G0xx devices provide the capability to measure the LSI clock
         frequency (LSI clock is internally connected to TIM16 CH1 input capture).
         The measured value can be used to have an IWDG timeout with an
         acceptable accuracy.

    [..] Default timeout value (necessary for IWDG_SR status register update):
         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
         This frequency being subject to variations as mentioned above, the
         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
         below) may become too short or too long.
         In such cases, this default timeout value can be tuned by redefining
         the constant LSI_VALUE at user-application level (based, for instance,
         on the measured LSI clock frequency as explained above).

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts counting down.
      (++) Enable write access to configuration registers:
          IWDG_PR, IWDG_RLR and IWDG_WINR.
      (++) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (++) Depending on window parameter:
        (+++) If Window Init parameter is same as Window register value,
             nothing more is done but reload counter value in order to exit
             function with exact time base.
        (+++) Else modify Window register. This will automatically reload
             watchdog counter.
      (++) Wait for status flags to be reset.

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register

Definition in file stm32g0xx_hal_iwdg.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_lptim.c File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_lptim.c File Reference

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT 1000UL /* Timeout is 1s */
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())

Functions

static void | LPTIM_ResetCallback (LPTIM_HandleTypeDef *lptim)
Reset interrupt callbacks to the legacy weak callbacks.
static HAL_StatusTypeDef | LPTIM_WaitForFlag (LPTIM_HandleTypeDef *hlptim, uint32_t flag)
LPTimer Wait for flag set.
HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (const LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (const LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (const LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.
void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.

Detailed Description

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The LPTIM HAL driver can be used as follows:

      (#)Initialize the LPTIM low level resources by implementing the
        HAL_LPTIM_MspInit():
         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().

      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
         configures mainly:
         (++) The instance: LPTIM1 or LPTIM2.
         (++) Clock: the counter clock.
             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
                              the internal clock; (APB, LSE, LSI or MSI).
             (+++) Prescaler: select the clock divider.
         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
               as counter clock source.
             (+++) Polarity:   polarity of the active edge for the counter unit
                               if the ULPTIM input is selected.
             (+++) SampleTime: clock sampling time to configure the clock glitch
                               filter.
         (++) Trigger: How the counter start.
             (+++) Source: trigger can be software or one of the hardware triggers.
             (+++) ActiveEdge : only for hardware trigger.
             (+++) SampleTime : trigger sampling time to configure the trigger
                                glitch filter.
         (++) OutputPolarity : 2 opposite polarities are possible.
         (++) UpdateMode: specifies whether the update of the autoreload and
              the compare values is done immediately or after the end of current
              period.
         (++) Input1Source: Source selected for input1 (GPIO or comparator output).
         (++) Input2Source: Source selected for input2 (GPIO or comparator output).
              Input2 is used only for encoder feature so is used only for LPTIM1 instance.

      (#)Six modes are available:

         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
         mode.

         (++) One Pulse Mode: To generate pulse with specified width in response
         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.

         (++) Set once Mode: In this mode, the output changes the level (from
         low level to high level if the output polarity is configured high, else
         the opposite) when a compare match occurs. To start this mode, call
         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
         interruption mode.

         (++) Encoder Mode: To use the encoder interface call
         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
         interruption mode. Only available for LPTIM1 instance.

         (++) Time out Mode: an active edge on one selected trigger input rests
         the counter. The first trigger event will start the timer, any
         successive trigger event will reset the counter and the timer will
         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.

         (++) Counter Mode: counter can be used to count external events on
         the LPTIM Input1 or it can be used to count internal clock cycles.
         To start this mode, call HAL_LPTIM_Counter_Start() or
         HAL_LPTIM_Counter_Start_IT() for interruption mode.

      (#) User can stop any process by calling the corresponding API:
          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
          already started in interruption mode.

      (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().

    *** Callback registration ***
  =============================================
  [..]
  The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  [..]
  Use Function HAL_LPTIM_RegisterCallback() to register a callback.
  HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.
  [..]
  Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
  default weak function.
  HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  [..]
  These functions allow to register/unregister following callbacks:

    (+) MspInitCallback         : LPTIM Base Msp Init Callback.
    (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
    (+) CompareMatchCallback    : Compare match Callback.
    (+) AutoReloadMatchCallback : Auto-reload match Callback.
    (+) TriggerCallback         : External trigger event detection Callback.
    (+) CompareWriteCallback    : Compare register write complete Callback.
    (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
    (+) DirectionUpCallback     : Up-counting direction change Callback.
    (+) DirectionDownCallback   : Down-counting direction change Callback.

  [..]
  By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
  all interrupt callbacks are set to the corresponding weak functions:
  examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init/DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.

  [..]
  When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Definition in file stm32g0xx_hal_lptim.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pcd.c File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Functions

static HAL_StatusTypeDef | PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.
static HAL_StatusTypeDef | HAL_PCD_EP_DB_Transmit (PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal)
Manage double buffer bulk IN transaction from ISR.
static uint16_t | HAL_PCD_EP_DB_Receive (PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal)
Manage double buffer bulk out transaction from ISR.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
Unregister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Abort (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Abort an USB EP transaction.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable PCD transmission and reception:
         (##) HAL_PCD_Start();

Definition in file stm32g0xx_hal_pcd.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pcd_ex.c File Reference

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Functions
stm32g0xx_hal_pcd_ex.c File Reference

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_pcd_ex.c.

Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pwr.c File Reference

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Functions
stm32g0xx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC & TAMP registers, backup registers, RCC BDCR register).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Enable Sleep-On-Exit Cortex feature.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit Cortex feature.
void | HAL_PWR_EnableSEVOnPend (void)
Enable Cortex Sev On Pending feature.
void | HAL_PWR_DisableSEVOnPend (void)
Disable Cortex Sev On Pending feature.

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_pwr.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pwr_ex.c File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT 0x00010000U
#define | PVD_MODE_EVT 0x00020000U
#define | PVD_RISING_EDGE 0x00000001U
#define | PVD_FALLING_EDGE 0x00000002U
#define | PWR_REGLPF_SETTING_DELAY_6_US 6u
#define | PWR_VOSF_SETTING_DELAY_6_US 6u
#define | PWR_GPIO_PIN_NB 16u

Functions

void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnablePORMonitorSampling (void)
Enable POR Monitor sampling mode.
void | HAL_PWREx_DisablePORMonitorSampling (void)
Disable POR Monitor sampling mode.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the Power Voltage Detector (PVD).
void | HAL_PWREx_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWREx_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnableVddIO2 (void)
Enable VDDIO2 supply.
void | HAL_PWREx_DisableVddIO2 (void)
Disable VDDIO2 supply.
void | HAL_PWREx_EnablePVMUSB (void)
Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)
void | HAL_PWREx_DisablePVMUSB (void)
Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAMRetention (void)
Enable SRAM content retention in Standby mode.
void | HAL_PWREx_DisableSRAMRetention (void)
Disable SRAM content retention in Standby mode.
void | HAL_PWREx_EnableFlashPowerDown (uint32_t PowerMode)
Enable Flash Power Down.
void | HAL_PWREx_DisableFlashPowerDown (uint32_t PowerMode)
Disable Flash Power Down.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main regulator output voltage.
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWREx_PVD_PVM_Rising_Callback (void)
PWR PVD interrupt rising callback.
__weak void | HAL_PWREx_PVD_PVM_Falling_Callback (void)
PWR PVD interrupt Falling callback.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_pwr_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rcc.c File Reference

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stm32g0xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define | PLLSOURCE_NONE (0U)
#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOA
#define | MCO2_PIN GPIO_PIN_10
#define | RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PA10)(*).
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCC_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
Handle the RCC HSE Clock Security System interrupt callback.
__weak void | HAL_RCC_LSECSSCallback (void)
RCC LSE Clock Security System interrupt callback.
uint32_t | HAL_RCC_GetResetSource (void)
Get and clear reset flags.

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from High Speed Internal oscillator
      (from 8 MHz to reach 16MHz) with Flash 0 wait state. Flash prefetch buffer,
      D-Cache and I-Cache are disabled, and all peripherals are off except internal
      SRAM, Flash and JTAG.

      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses:
          all peripherals mapped on these buses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in analog mode, except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB buses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals which clocks are not
          derived from the System clock (RTC, ADC, RNG, HSTIM)
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_rcc.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rcc_ex.c File Reference

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stm32g0xx_hal_rcc_ex.c File Reference

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | PLL_TIMEOUT_VALUE 100U /* 100 ms (minimum Tick + 1) */
#define | LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | LSCO_GPIO_PORT GPIOA
#define | LSCO_PIN GPIO_PIN_2

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLL.
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_rcc_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rng.c File Reference

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stm32g0xx_hal_rng.c File Reference

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_TIMEOUT_VALUE 2U

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      The RNG HAL driver can be used as follows:

      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
          in HAL_RNG_MspInit().
      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
      (#) Wait until the 32 bit Random Number Generator contains a valid
          random data using (polling/interrupt) mode.
      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_RNG_RegisterCallback() to register a user callback.
    Function HAL_RNG_RegisterCallback() allows to register following callbacks:
    (+) ErrorCallback             : RNG Error Callback.
    (+) MspInitCallback           : RNG MspInit.
    (+) MspDeInitCallback         : RNG MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) ErrorCallback             : RNG Error Callback.
    (+) MspInitCallback           : RNG MspInit.
    (+) MspDeInitCallback         : RNG MspDeInit.

    [..]
    For specific callback ReadyDataCallback, use dedicated register callbacks:
    respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().

    [..]
    By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    example HAL_RNG_ErrorCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
    and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
    or HAL_RNG_Init() function.

    [..]
    When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.

Definition in file stm32g0xx_hal_rng.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rtc.c File Reference

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Functions
stm32g0xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization functions + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callback is redirected to the weak predefined callback.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
HAL_StatusTypeDef | RTC_ExitInitMode (RTC_HandleTypeDef *hrtc)
Exit the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.
void | HAL_RTC_DST_Add1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Add one hour to the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_Sub1Hour (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Subtract one hour from the calendar in one single operation without going through the initialization procedure.
void | HAL_RTC_DST_SetStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Set the store operation bit.
void | HAL_RTC_DST_ClearStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Clear the store operation bit.
uint32_t | HAL_RTC_DST_ReadStoreOperation (RTC_HandleTypeDef *hrtc)
Daylight Saving Time, Read the store operation bit.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization functions + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ===============================================================================
                          ##### RTC Operating Condition #####
  ===============================================================================
  [..] The real-time clock (RTC) and the RTC backup registers can be powered
       from the VBAT voltage when the main VDD supply is powered off.
       To retain the content of the RTC backup registers and supply the RTC
       when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

                   ##### Backup Domain Reset #####
 ===============================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values.
       A backup domain reset is generated when one of the following events occurs:
    (+) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (+) VDD or VBAT power on, if both supplies have previously been powered off.
    (+) Tamper detection event resets all data backup registers.

                   ##### Backup Domain Access #####
  =============================================================================
  [..] After reset, the backup domain (RTC registers and RTC backup data registers)
       is protected against possible unwanted write accesses.
  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (+) Enable the Power Controller (PWR) APB1 interface clock using the
        __HAL_RCC_PWR_CLK_ENABLE() function.
    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.

  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.

                  ##### How to use RTC Driver #####
 ===================================================================
  [..]
    (+) Enable the RTC domain access (see description in the section above).
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
            You can also configure the RTC Alarm with interrupt mode using the
            HAL_RTC_SetAlarm_IT() function.
    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

                  ##### RTC and low power modes #####
  ==================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
       These RTC alternate functions can wake up the system from the Stop and
       Standby low power modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
       or the RTC wakeup events.
  [..] The RTC provides a programmable time base for waking up from the
       Stop or Standby mode at regular intervals.
       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
       is LSE or LSI.

  *** Callback registration ***
  =============================================

  [..]
  The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.

  [..]
  Function HAL_RTC_RegisterCallback() allows to register following callbacks:
    (+) AlarmAEventCallback          :  RTC Alarm A Event callback.
    (+) AlarmBEventCallback          :  RTC Alarm B Event callback.
    (+) TimeStampEventCallback       :  RTC TimeStamp Event callback.
    (+) WakeUpTimerEventCallback     :  RTC WakeUpTimer Event callback.
    (+) Tamper1EventCallback         :  RTC Tamper1Event callback.
    (+) Tamper2EventCallback         :  RTC Tamper2Event callback.
    (+) Tamper3EventCallback         :  RTC Tamper3Event callback. (*)
    (+) InternalTamper3EventCallback :  RTC Internal Tamper 3 Event callback.
    (+) InternalTamper4EventCallback :  RTC Internal Tamper 4 Event callback.
    (+) InternalTamper5EventCallback :  RTC Internal Tamper 5 Event callback.
    (+) InternalTamper6EventCallback :  RTC Internal Tamper 6 Event callback.
    (+) MspInitCallback              :  RTC MspInit.
    (+) MspDeInitCallback            :  RTC MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.(*)
    (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Event callback.
    (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Event callback.
    (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Event callback.
    (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Event callback.
    (+) MspInitCallback              : RTC MspInit callback.
    (+) MspDeInitCallback            : RTC MspDeInit callback.

  [..]
  By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
  all callbacks are set to the corresponding weak functions :
  examples AlarmAEventCallback(), WakeUpTimerEventCallback().
  Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
  in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
  (not registered beforehand).
  If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
  or HAL_RTC_Init() function.

  [..]
  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

Definition in file stm32g0xx_hal_rtc.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rtc_ex.c File Reference

  • File List
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Functions
stm32g0xx_hal_rtc_ex.c File Reference

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
void | HAL_RTCEx_TimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper in IT mode.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
Tamper event polling.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper in interrupt mode.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTamper_IT (RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper)
Set Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTamper (RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
Deactivate Internal Tamper.
HAL_StatusTypeDef | HAL_RTCEx_PollForInternalTamperEvent (RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
Internal Tamper event polling.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper3EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 3 callback.
__weak void | HAL_RTCEx_InternalTamper4EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 4 callback.
__weak void | HAL_RTCEx_InternalTamper5EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 5 callback.
__weak void | HAL_RTCEx_InternalTamper6EventCallback (RTC_HandleTypeDef *hrtc)
Internal Tamper 6 callback.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.

Detailed Description

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wakeup configuration ***
  ================================
  [..]
    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
        function. You can also configure the RTC Wakeup timer with interrupt mode
        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
        function.

  *** Outputs configuration ***
  =============================
  [..]  The RTC has 2 different outputs:
    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
        and WaKeUp signals.
        To output the selected RTC signal, use the HAL_RTC_Init() function.
    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
        the RTC_OR register.
    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
        automatically configured in output alternate function.

  *** Smooth digital Calibration configuration ***
  ================================================
  [..]
    (+) Configure the RTC Original Digital Calibration Value and the corresponding
        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
        You can also configure the RTC TimeStamp with interrupt mode using the
        HAL_RTCEx_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Internal TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

   *** Tamper configuration ***
   ============================
   [..]
     (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
         or Level according to the Tamper filter (if equal to 0 Edge else Level)
         value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
         Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
         with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
     (+) The default configuration of the Tamper erases the backup registers. To avoid
         erase, enable the NoErase field on the RTC_TAMPCR register.
     (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to
         perform TAMP base address offset calculation.
     (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization
         by setting ClockEnable inti field to RTC_CLOCK_DISABLE.
     (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using
         setting Interrupt field.

   *** Backup Data Registers configuration ***
   ===========================================
   [..]
     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
         function.
     (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
         function.
     (+) Before calling those functions you have to call HAL_RTC_Init() in order to
         perform TAMP base address offset calculation.

Definition in file stm32g0xx_hal_rtc_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smartcard.c File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Functions

void | SMARTCARD_InitCallbacksToDefault (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | SMARTCARD_TxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_TxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static void | SMARTCARD_RxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
static void | SMARTCARD_RxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (const SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
    (#) Associate a USART to the SMARTCARD handle hsmartcard.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) USART pins configuration:
             (+++) Enable the clock for the USART GPIOs.
             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
             (+++) Enable the NVIC USART IRQ handle.
        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx channel.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
             (+++) Configure the DMA Tx/Rx channel.
             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
             (+++) Configure the priority and enable the NVIC for the transfer complete
                   interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
        error enabling or disabling in the hsmartcard handle Init structure.

    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
        in the hsmartcard handle AdvancedInit structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
        [..]
        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

    [..]
    [..] Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** SMARTCARD HAL driver macros list ***
     ========================================
     [..]
       Below the list of most used macros in SMARTCARD HAL driver.

       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled

     [..]
       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
    Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : SMARTCARD MspInit.
    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : SMARTCARD MspInit.
    (+) MspDeInitCallback         : SMARTCARD MspDeInit.

    [..]
    By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
    and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
    or HAL_SMARTCARD_Init() function.

    [..]
    When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.

Definition in file stm32g0xx_hal_smartcard.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smartcard_ex.c File Reference

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Defines | Functions
stm32g0xx_hal_smartcard_ex.c File Reference

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | SMARTCARDEx_SetNbDataToProcess (SMARTCARD_HandleTypeDef *hsmartcard)
Calculate the number of data to process in RX/TX ISR.
void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.
__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  =============================================================================
               ##### SMARTCARD peripheral extended features  #####
  =============================================================================
  [..]
  The Extended SMARTCARD HAL driver can be used as follows:

    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
        auto-retry counter,...) in the hsmartcard AdvancedInit structure.

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.

Definition in file stm32g0xx_hal_smartcard_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smbus.c File Reference

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Defines | Functions
stm32g0xx_hal_smbus.c File Reference

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFUL)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ITErrorHandler (SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the enabling of Interrupts.
static void | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the disabling of Interrupts.
static void | SMBUS_Flush_TXDR (SMBUS_HandleTypeDef *hsmbus)
SMBUS Tx data register flush process.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | SMBUS_ConvertOtherXferOptions (SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The SMBUS HAL driver can be used as follows:

    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
        SMBUS_HandleTypeDef  hsmbus;

    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
        (##) Enable the SMBUSx interface clock
        (##) SMBUS pins configuration
            (+++) Enable the clock for the SMBUS GPIOs
            (+++) Configure SMBUS pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the SMBUSx interrupt priority
            (+++) Enable the NVIC SMBUS IRQ Channel

    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.

    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.

    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()

    (#) For SMBUS IO operations, only one mode of operations is available within this driver

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
          using HAL_SMBUS_Master_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
          using HAL_SMBUS_Master_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
           add their own code to check the Address Match Code and the transmission direction
           request by master/host (Write/Read).
      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
          using HAL_SMBUS_Slave_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
          using HAL_SMBUS_Slave_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
      (+) Enable/Disable the SMBUS alert mode using
          HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Alert Error Code using function HAL_SMBUS_GetError()
      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Error Code using function HAL_SMBUS_GetError()

     *** SMBUS HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in SMBUS HAL driver.

      (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
      (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
      (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
      (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
      (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
      (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt

     *** Callback registration ***
     =============================================
    [..]
     The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
     to register an interrupt callback.
    [..]
     Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]
     For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
    [..]
     Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
     weak function.
     HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
    [..]
     For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
    [..]
     By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
    [..]
     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
     or HAL_SMBUS_Init() function.
    [..]
     When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     [..]
       (@) You can refer to the SMBUS HAL driver header file for more useful macros

Definition in file stm32g0xx_hal_smbus.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smbus_ex.c File Reference

  • File List
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Functions
stm32g0xx_hal_smbus_ex.c File Reference

SMBUS Extended HAL module driver. This file provides firmware functions to manage the following functionalities of SMBUS Extended peripheral: + Extended features functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SMBUSEx_EnableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Enable SMBUS wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_SMBUSEx_DisableWakeUp (SMBUS_HandleTypeDef *hsmbus)
Disable SMBUS wakeup from Stop mode(s).
void | HAL_SMBUSEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the SMBUS fast mode plus driving capability.
void | HAL_SMBUSEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the SMBUS fast mode plus driving capability.

Detailed Description

SMBUS Extended HAL module driver. This file provides firmware functions to manage the following functionalities of SMBUS Extended peripheral: + Extended features functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
               ##### SMBUS peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the SMBUS interface for STM32G0xx
       devices contains the following additional features

       (+) Disable or enable wakeup from Stop mode(s)
       (+) Disable or enable Fast Mode Plus

                     ##### How to use this driver #####
  ==============================================================================
    (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
          (++) HAL_SMBUSEx_EnableWakeUp()
          (++) HAL_SMBUSEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_SMBUSEx_EnableFastModePlus()
          (++) HAL_SMBUSEx_DisableFastModePlus()

Definition in file stm32g0xx_hal_smbus_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_spi.c File Reference

  • File List
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Defines | Functions
stm32g0xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 100U

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx Stream/Channel
              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.
     [..]
       Circular mode restriction:
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (##) Master 2Lines RxOnly
          (##) Master 1Line Rx
      (#) The CRC feature is not managed when the DMA circular mode is enabled
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
     [..]
       Master Receive mode restriction:
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
          does not initiate a new transfer the following procedure has to be respected:
          (##) HAL_SPI_DeInit()
          (##) HAL_SPI_Init()
     [..]
       Callback registration:

      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
          allows the user to configure dynamically the driver callbacks.
          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.

          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
            (++) TxCpltCallback        : SPI Tx Completed callback
            (++) RxCpltCallback        : SPI Rx Completed callback
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
            (++) ErrorCallback         : SPI Error callback
            (++) AbortCpltCallback     : SPI Abort callback
            (++) MspInitCallback       : SPI Msp Init callback
            (++) MspDeInitCallback     : SPI Msp DeInit callback
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
          weak function.
          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (++) TxCpltCallback        : SPI Tx Completed callback
            (++) RxCpltCallback        : SPI Rx Completed callback
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
            (++) ErrorCallback         : SPI Error callback
            (++) AbortCpltCallback     : SPI Abort callback
            (++) MspInitCallback       : SPI Msp Init callback
            (++) MspDeInitCallback     : SPI Msp DeInit callback

       [..]
       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
       all callbacks are set to the corresponding weak functions:
       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
       Exception done for MspInit and MspDeInit functions that are
       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
       these callbacks are null (not registered beforehand).
       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

       [..]
       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
       Then, the user first registers the MspInit/MspDeInit user callbacks
       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
       or HAL_SPI_Init() function.

       [..]
       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
       and weak (surcharged) callbacks are used.

     [..]
       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
       the following table resume the max SPI frequency reached with data size 8bits/16bits,
         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.

Additional table :

DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+

DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+

Note:
The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()

Definition in file stm32g0xx_hal_spi.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_spi_ex.c File Reference

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Defines | Functions
stm32g0xx_hal_spi_ex.c File Reference

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_FIFO_SIZE 4UL

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_hal_spi_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_tim.c File Reference

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Defines | Functions
stm32g0xx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMx_OR1_OCREF_CLR 0x00000001U

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse half complete callback.
static void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger half complete callback.
static HAL_StatusTypeDef | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Slave Timer configuration function.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (const TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (const TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (const TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ActiveChannel | HAL_TIM_GetActiveChannel (const TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIM_GetChannelState (const TIM_HandleTypeDef *htim, uint32_t Channel)
Return actual state of the TIM channel.
HAL_TIM_DMABurstStateTypeDef | HAL_TIM_DMABurstState (const TIM_HandleTypeDef *htim)
Return actual state of a DMA burst operation.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output
       (#) Synchronization circuit to control the timer with external signals and to interconnect
            several timers together.
       (#) Supports incremental encoder for positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
            Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
            in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()

    *** Callback registration ***
  =============================================

  [..]
  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.

  [..]
  Use Function HAL_TIM_RegisterCallback() to register a callback.
  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.

  [..]
  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
  weak function.
  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.

  [..]
  These functions allow to register/unregister following callbacks:
    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
    (+) TriggerCallback                   : TIM Trigger Callback.
    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
    (+) IC_CaptureCallback                : TIM Input Capture Callback.
    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
    (+) ErrorCallback                     : TIM Error Callback.
    (+) CommutationCallback               : TIM Commutation Callback.
    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
    (+) BreakCallback                     : TIM Break Callback.
    (+) Break2Callback                    : TIM Break2 Callback.

  [..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init / DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)

  [..]
    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
    Exception done MspInit / MspDeInit that can be registered / unregistered
    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.

  [..]
      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
      are set to the corresponding weak functions.

Definition in file stm32g0xx_hal_tim.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_tim_ex.c File Reference

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Defines | Functions
stm32g0xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */

Functions

static void | TIM_DMADelayPulseNCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback (complementary channel).
static void | TIM_DMAErrorCCxN (DMA_HandleTypeDef *hdma)
TIM DMA error callback (complementary channel)
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_TISelection (TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
Select the timer input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_DisarmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Disarm the designated break input (when it operates in bidirectional mode).
HAL_StatusTypeDef | HAL_TIMEx_ReArmBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput)
Arm the designated break input (when it operates in bidirectional mode).
__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (const TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
HAL_TIM_ChannelStateTypeDef | HAL_TIMEx_GetChannelNState (const TIM_HandleTypeDef *htim, uint32_t ChannelN)
Return actual state of the TIM complementary channel.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
               Timer Hall Sensor Interface and the commutation event with the corresponding
               Interrupt and DMA request if needed (Note that One Timer is used to interface
               with the Hall sensor Interface and another Timer should be used to use
               the commutation event).

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
                HAL_TIMEx_OCN_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
                HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
                HAL_TIMEx_HallSensor_Start_IT().

Definition in file stm32g0xx_hal_tim_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_uart.c File Reference

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Defines | Functions | Variables
stm32g0xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define | LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define | UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define | UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | UART_TxISR_8BIT (UART_HandleTypeDef *huart)
TX interrupt handler for 7 or 8 bits data word length .
static void | UART_TxISR_16BIT (UART_HandleTypeDef *huart)
TX interrupt handler for 9 bits data word length.
static void | UART_TxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_TxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
static void | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static void | UART_RxISR_8BIT (UART_HandleTypeDef *huart)
RX interrupt handler for 7 or 8 bits data word length .
static void | UART_RxISR_16BIT (UART_HandleTypeDef *huart)
RX interrupt handler for 9 bits data word length .
static void | UART_RxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_RxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_RegisterRxEventCallback (UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
Register a User UART Rx Event Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterRxEventCallback (UART_HandleTypeDef *huart)
UnRegister the UART Rx Event Callback UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
__weak void | HAL_UARTEx_RxEventCallback (UART_HandleTypeDef *huart, uint16_t Size)
Reception Event Callback (Rx event notification called after use of advanced reception service).
void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_UART_StateTypeDef | HAL_UART_GetState (const UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (const UART_HandleTypeDef *huart)
Return the UART handle error code.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles UART Communication Timeout.
HAL_StatusTypeDef | UART_Start_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in interrupt mode.
HAL_StatusTypeDef | UART_Start_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Start Receive operation in DMA mode.

Variables

const uint16_t | UARTPrescTable [12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) UART interrupts handling:
              -@@-  The specific UART interrupts (Transmission complete interrupt,
                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
                inside the transmit and receive processes.
        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.

    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
        in the huart handle AdvancedInit structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
        by calling the HAL_LIN_Init() API.

    (#) For the UART Multiprocessor mode, initialize the UART registers
        by calling the HAL_MultiProcessor_Init() API.

    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    [..]
    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
        calling the customized HAL_UART_MspInit() API.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_UART_RegisterCallback() to register a user callback.
    Function HAL_UART_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) WakeupCallback            : Wakeup Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : UART MspInit.
    (+) MspDeInitCallback         : UART MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) WakeupCallback            : Wakeup Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : UART MspInit.
    (+) MspDeInitCallback         : UART MspDeInit.

    [..]
    For specific callback RxEventCallback, use dedicated registration/reset functions:
    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().

    [..]
    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
    or HAL_UART_Init() function.

    [..]
    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.

Definition in file stm32g0xx_hal_uart.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_uart_ex.c File Reference

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Defines | Functions
stm32g0xx_hal_uart_ex.c File Reference

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
static void | UARTEx_SetNbDataToProcess (UART_HandleTypeDef *huart)
Calculate the number of data to process in RX/TX ISR.
HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
HAL_StatusTypeDef | HAL_UARTEx_ReceiveToIdle_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
HAL_UART_RxEventTypeTypeDef | HAL_UARTEx_GetRxEventType (UART_HandleTypeDef *huart)
Provide Rx Event type that has lead to RxEvent callback execution.

Detailed Description

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
               ##### UART peripheral extended features  #####
  ==============================================================================

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.

Definition in file stm32g0xx_hal_uart_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_usart.c File Reference

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stm32g0xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))
#define | USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
#define | USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Functions

void | USART_InitCallbacksToDefault (USART_HandleTypeDef *husart)
Initialize the callbacks to their default values.
static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_TxISR_8BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static void | USART_RxISR_8BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an USART Callback USART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (const USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (const USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
      The USART HAL driver can be used as follows:

      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
          (++) Enable the USARTx interface clock.
          (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure these USART pins as alternate function pull-up.
          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (++) USART interrupts handling:
              -@@-   The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer
                  complete interrupt on the DMA Tx/Rx channel.

      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
          (Receiver/Transmitter) in the husart handle Init structure.

      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
               by calling the customized HAL_USART_MspInit(&husart) API.

    [..]
     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function HAL_USART_RegisterCallback() to register a user callback.
    Function HAL_USART_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : USART MspInit.
    (+) MspDeInitCallback         : USART MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : USART MspInit.
    (+) MspDeInitCallback         : USART MspDeInit.

    [..]
    By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
    and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
    or HAL_USART_Init() function.

    [..]
    When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.

Definition in file stm32g0xx_hal_usart.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_usart_ex.c File Reference

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Defines | Functions
stm32g0xx_hal_usart_ex.c File Reference

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | USARTEx_SetNbDataToProcess (USART_HandleTypeDef *husart)
Calculate the number of data to process in RX/TX ISR.
__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
               ##### USART peripheral extended features  #####
  ==============================================================================

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.

    (#) Slave mode enabling/disabling and NSS pin configuration.

        -@- When USART operates in Slave mode, Slave mode must be enabled prior
            starting RX/TX transfers.

Definition in file stm32g0xx_hal_usart_ex.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_wwdg.c File Reference

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Functions
stm32g0xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions. More...

#include "stm32g0xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

  ==============================================================================
                      ##### WWDG Specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (T[6;0] downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls down from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.
    (+) Once enabled the WWDG cannot be disabled except by a system reset.
    (+) If required by application, an Early Wakeup Interrupt can be triggered
        in order to be warned before WWDG expiration. The Early Wakeup Interrupt
        (EWI) can be used if specific safety operations or data logging must
        be performed before the actual reset is generated. When the downcounter
        reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
        line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
        disabled except by a system reset.
    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
        reset occurs.
    (+) The WWDG counter input clock is derived from the APB clock divided
        by a programmable prescaler.
    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
        where T[5;0] are the lowest 6 bits of Counter.
    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
    (+) Typical values:
        (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler:
             max timeout before reset: approximately 64us
        (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler
             dividing by 128:
             max timeout before reset: approximately 524.28ms

                     ##### How to use this driver #####
  ==============================================================================

    *** Common driver usage ***
    ===========================

  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
    (+) Configure the WWDG prescaler, refresh window value, counter value and early
        interrupt status using HAL_WWDG_Init() function. This will automatically
        enable WWDG and start its downcounter. Time reference can be taken from
        function exit. Care must be taken to provide a counter value
        greater than 0x40 to prevent generation of immediate reset.
    (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
        generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
        triggered by the interrupt service routine, flag will be automatically
        cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
        can add his own code by customization of callback HAL_WWDG_WakeupCallback.
    (+) Then the application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the refresh window value already programmed.

    *** Callback registration ***
    =============================

  [..]
    The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
    the user to configure dynamically the driver callbacks. Use Functions
    HAL_WWDG_RegisterCallback() to register a user callback.

    (+) Function HAL_WWDG_RegisterCallback() allows to register following
        callbacks:
        (++) EwiCallback : callback for Early WakeUp Interrupt.
        (++) MspInitCallback : WWDG MspInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
    the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
    takes as parameters the HAL peripheral handle and the Callback ID.
    This function allows to reset following callbacks:
        (++) EwiCallback : callback for  Early WakeUp Interrupt.
        (++) MspInitCallback : WWDG MspInit.

    [..]
    When calling HAL_WWDG_Init function, callbacks are reset to the
    corresponding legacy weak (surcharged) functions:
    HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
    not been registered before.

    [..]
    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.

    *** WWDG HAL driver macros list ***
    ===================================
    [..]
      Below the list of available macros in WWDG HAL driver.
      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt

Definition in file stm32g0xx_hal_wwdg.c.

Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_crs.c File Reference

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Functions
stm32g0xx_ll_crs.c File Reference
#include "stm32g0xx_ll_crs.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.
Generated on Mon Jun 6 2022 10:29:05 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_pwr.c File Reference

  • File List
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  • STM32G0xx_HAL_Driver
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Functions
stm32g0xx_ll_pwr.c File Reference

PWR LL module driver. More...

#include "stm32g0xx_ll_pwr.h"
#include "stm32g0xx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

PWR LL module driver.

Author:
MCD Application Team
Attention:

Copyright (c) 2018 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32g0xx_ll_pwr.c.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__ADC_HandleTypeDef | ADC handle Structure definition
__CEC_HandleTypeDef | CEC handle Structure definition
__COMP_HandleTypeDef | COMP Handle Structure definition
__CRYP_HandleTypeDef | CRYP handle Structure definition
__DAC_HandleTypeDef | DAC handle Structure definition
__DMA_HandleTypeDef | DMA handle Structure definition
__FDCAN_HandleTypeDef | FDCAN handle structure definition
__HCD_HandleTypeDef |
__I2C_HandleTypeDef |
__I2S_HandleTypeDef | I2S handle Structure definition
__IRDA_HandleTypeDef | IRDA handle Structure definition
__LPTIM_HandleTypeDef | LPTIM handle Structure definition
__PCD_HandleTypeDef | PCD Handle Structure definition
__RNG_HandleTypeDef |
__RTC_HandleTypeDef | RTC Handle Structure definition
__SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
__SMBUS_HandleTypeDef |
__SPI_HandleTypeDef | SPI handle Structure definition
__TIM_HandleTypeDef | TIM Time Base Handle Structure definition
__UART_HandleTypeDef | UART handle Structure definition
__USART_HandleTypeDef | USART handle Structure definition
__WWDG_HandleTypeDef | WWDG handle Structure definition
ADC_AnalogWDGConfTypeDef | Structure definition of ADC analog watchdog
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_InitTypeDef | Structure definition of ADC instance and ADC group regular
ADC_OversamplingTypeDef | ADC group regular oversampling structure definition
CEC_InitTypeDef | CEC Init Structure definition
COMP_InitTypeDef | COMP Init structure definition
CRC_HandleTypeDef | CRC Handle Structure definition
CRC_InitTypeDef | CRC Init Structure definition
CRYP_ConfigTypeDef | CRYP Init Structure definition
DAC_ChannelConfTypeDef | DAC Configuration regular Channel structure definition
DAC_SampleAndHoldConfTypeDef | DAC Configuration sample and hold Channel structure definition
DMA_InitTypeDef | DMA Configuration Structure definition
EXTI_ConfigTypeDef | EXTI Configuration structure definition
EXTI_HandleTypeDef | EXTI Handle structure definition
FDCAN_ErrorCountersTypeDef | FDCAN Error Counters structure definition
FDCAN_FilterTypeDef | FDCAN filter structure definition
FDCAN_HpMsgStatusTypeDef | FDCAN High Priority Message Status structure definition
FDCAN_InitTypeDef | FDCAN Init structure definition
FDCAN_MsgRamAddressTypeDef | FDCAN Message RAM blocks
FDCAN_ProtocolStatusTypeDef | FDCAN Protocol Status structure definition
FDCAN_RxHeaderTypeDef | FDCAN Rx header structure definition
FDCAN_TxEventFifoTypeDef | FDCAN Tx event FIFO structure definition
FDCAN_TxHeaderTypeDef | FDCAN Tx header structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Option Bytes Program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
GPIO_InitTypeDef | GPIO Init structure definition
HAL_DMA_MuxRequestGeneratorConfigTypeDef | HAL DMAMUX request generator parameters structure definition
HAL_DMA_MuxSyncConfigTypeDef | HAL DMAMUX Synchronization configuration structure definition
I2C_InitTypeDef |
I2S_InitTypeDef | I2S Init structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
LL_ADC_CommonInitTypeDef | Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance)
LL_ADC_InitTypeDef | Structure definition of some features of ADC instance
LL_ADC_REG_InitTypeDef | Structure definition of some features of ADC group regular
LL_COMP_InitTypeDef | Structure definition of some features of COMP instance
LL_DAC_InitTypeDef | Structure definition of some features of DAC instance
LL_DMA_InitTypeDef |
LL_EXTI_InitTypeDef |
LL_GPIO_InitTypeDef | LL GPIO Init Structure definition
LL_I2C_InitTypeDef |
LL_I2S_InitTypeDef | I2S Init structure definition
LL_LPTIM_InitTypeDef | LPTIM Init structure definition
LL_LPUART_InitTypeDef | LL LPUART Init Structure definition
LL_RCC_ClocksTypeDef | RCC Clocks Frequency Structure
LL_RNG_InitTypeDef | LL RNG Init Structure Definition
LL_RTC_AlarmTypeDef | RTC Alarm structure definition
LL_RTC_DateTypeDef | RTC Date structure definition
LL_RTC_InitTypeDef | RTC Init structures definition
LL_RTC_TimeTypeDef | RTC Time structure definition
LL_SPI_InitTypeDef | SPI Init structures definition
LL_TIM_BDTR_InitTypeDef | BDTR (Break and Dead Time) structure definition
LL_TIM_ENCODER_InitTypeDef | TIM Encoder interface configuration structure definition
LL_TIM_HALLSENSOR_InitTypeDef | TIM Hall sensor interface configuration structure definition
LL_TIM_IC_InitTypeDef | TIM Input Capture configuration structure definition
LL_TIM_InitTypeDef | TIM Time Base configuration structure definition
LL_TIM_OC_InitTypeDef | TIM Output Compare configuration structure definition
LL_UCPD_InitTypeDef | UCPD Init structures definition
LL_USART_ClockInitTypeDef | LL USART Clock Init Structure definition
LL_USART_InitTypeDef | LL USART Init Structure definition
LL_UTILS_ClkInitTypeDef | UTILS System, AHB and APB buses clock configuration structure definition
LL_UTILS_PLLInitTypeDef | UTILS PLL structure definition
LPTIM_ClockConfigTypeDef | LPTIM Clock configuration definition
LPTIM_InitTypeDef | LPTIM Initialization Structure definition
LPTIM_TriggerConfigTypeDef | LPTIM Trigger configuration definition
LPTIM_ULPClockConfigTypeDef | LPTIM Clock configuration definition
MPU_Region_InitTypeDef |
PWR_PVDTypeDef | PWR PVD configuration structure definition
PWR_PVMTypeDef | PWR PVM configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB buses clock configuration structure definition
RCC_CRSInitTypeDef | RCC_CRS Init structure definition
RCC_CRSSynchroInfoTypeDef | RCC_CRS Synchronization structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RNG_InitTypeDef |
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_InternalTamperTypeDef |
RTC_TamperTypeDef |
RTC_TimeTypeDef | RTC Time structure definition
SMARTCARD_AdvFeatureInitTypeDef | SMARTCARD advanced features initialization structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SMBUS_InitTypeDef |
SPI_InitTypeDef | SPI Configuration Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break input(s) and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | TIM Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
TIMEx_BreakInputConfigTypeDef | TIM Break/Break2 input configuration
UART_AdvFeatureInitTypeDef | UART Advanced Features initialization structure definition
UART_InitTypeDef | UART Init Structure definition
UART_WakeUpTypeDef | UART wake up from stop mode parameters
USART_InitTypeDef | USART Init Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | E | F | G | H | I | L | M | P | R | S | T | U | W | _
A
FLASH_EraseInitTypeDef LL_RTC_AlarmTypeDef RCC_PeriphCLKInitTypeDef UART_WakeUpTypeDef
FLASH_OBProgramInitTypeDef LL_RTC_DateTypeDef RCC_PLLInitTypeDef USART_InitTypeDef
ADC_AnalogWDGConfTypeDef FLASH_ProcessTypeDef LL_RTC_InitTypeDef RNG_InitTypeDef
W
ADC_ChannelConfTypeDef
G
LL_RTC_TimeTypeDef RTC_AlarmTypeDef
ADC_InitTypeDef LL_SPI_InitTypeDef RTC_DateTypeDef WWDG_InitTypeDef
ADC_OversamplingTypeDef GPIO_InitTypeDef LL_TIM_BDTR_InitTypeDef RTC_InitTypeDef
_
C
H
LL_TIM_ENCODER_InitTypeDef RTC_InternalTamperTypeDef
LL_TIM_HALLSENSOR_InitTypeDef RTC_TamperTypeDef __ADC_HandleTypeDef
CEC_InitTypeDef HAL_DMA_MuxRequestGeneratorConfigTypeDef LL_TIM_IC_InitTypeDef RTC_TimeTypeDef __CEC_HandleTypeDef
COMP_InitTypeDef HAL_DMA_MuxSyncConfigTypeDef LL_TIM_InitTypeDef
S
__COMP_HandleTypeDef
CRC_HandleTypeDef
I
LL_TIM_OC_InitTypeDef __CRYP_HandleTypeDef
CRC_InitTypeDef LL_UCPD_InitTypeDef SMARTCARD_AdvFeatureInitTypeDef __DAC_HandleTypeDef
CRYP_ConfigTypeDef I2C_InitTypeDef LL_USART_ClockInitTypeDef SMARTCARD_InitTypeDef __DMA_HandleTypeDef
D
I2S_InitTypeDef LL_USART_InitTypeDef SMBUS_InitTypeDef __FDCAN_HandleTypeDef
IRDA_InitTypeDef LL_UTILS_ClkInitTypeDef SPI_InitTypeDef __HCD_HandleTypeDef
DAC_ChannelConfTypeDef IWDG_HandleTypeDef LL_UTILS_PLLInitTypeDef
T
__I2C_HandleTypeDef
DAC_SampleAndHoldConfTypeDef IWDG_InitTypeDef LPTIM_ClockConfigTypeDef __I2S_HandleTypeDef
DMA_InitTypeDef
L
LPTIM_InitTypeDef TIM_Base_InitTypeDef __IRDA_HandleTypeDef
E
LPTIM_TriggerConfigTypeDef TIM_BreakDeadTimeConfigTypeDef __LPTIM_HandleTypeDef
LL_ADC_CommonInitTypeDef LPTIM_ULPClockConfigTypeDef TIM_ClearInputConfigTypeDef __PCD_HandleTypeDef
EXTI_ConfigTypeDef LL_ADC_InitTypeDef
M
TIM_ClockConfigTypeDef __RNG_HandleTypeDef
EXTI_HandleTypeDef LL_ADC_REG_InitTypeDef TIM_Encoder_InitTypeDef __RTC_HandleTypeDef
F
LL_COMP_InitTypeDef MPU_Region_InitTypeDef TIM_HallSensor_InitTypeDef __SMARTCARD_HandleTypeDef
LL_DAC_InitTypeDef
P
TIM_IC_InitTypeDef __SMBUS_HandleTypeDef
FDCAN_ErrorCountersTypeDef LL_DMA_InitTypeDef TIM_MasterConfigTypeDef __SPI_HandleTypeDef
FDCAN_FilterTypeDef LL_EXTI_InitTypeDef PWR_PVDTypeDef TIM_OC_InitTypeDef __TIM_HandleTypeDef
FDCAN_HpMsgStatusTypeDef LL_GPIO_InitTypeDef PWR_PVMTypeDef TIM_OnePulse_InitTypeDef __UART_HandleTypeDef
FDCAN_InitTypeDef LL_I2C_InitTypeDef
R
TIM_SlaveConfigTypeDef __USART_HandleTypeDef
FDCAN_MsgRamAddressTypeDef LL_I2S_InitTypeDef TIMEx_BreakInputConfigTypeDef __WWDG_HandleTypeDef
FDCAN_ProtocolStatusTypeDef LL_LPTIM_InitTypeDef RCC_ClkInitTypeDef
U
FDCAN_RxHeaderTypeDef LL_LPUART_InitTypeDef RCC_CRSInitTypeDef
FDCAN_TxEventFifoTypeDef LL_RCC_ClocksTypeDef RCC_CRSSynchroInfoTypeDef UART_AdvFeatureInitTypeDef
FDCAN_TxHeaderTypeDef LL_RNG_InitTypeDef RCC_OscInitTypeDef UART_InitTypeDef
A | C | D | E | F | G | H | I | L | M | P | R | S | T | U | W | _
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: C:/git/g0_release_v1.6.0/Firmware/Drivers/STM32G0xx_HAL_Driver/Src/ Directory Reference

  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32g0xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32g0xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions Other functions (extended functions) are available in file "stm32g0xx_hal_adc_ex.c".

file | stm32g0xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Peripheral Control functions Other functions (generic functions) are available in file "stm32g0xx_hal_adc.c".

file | stm32g0xx_hal_cec.c [code]

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

file | stm32g0xx_hal_comp.c [code]

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Peripheral control functions + Peripheral state functions.

file | stm32g0xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions.

file | stm32g0xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32g0xx_hal_crc_ex.c [code]

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

file | stm32g0xx_hal_cryp.c [code]

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

file | stm32g0xx_hal_cryp_ex.c [code]

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral.

file | stm32g0xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32g0xx_hal_dac_ex.c [code]

Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

file | stm32g0xx_hal_dma.c [code]

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

file | stm32g0xx_hal_dma_ex.c [code]

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

file | stm32g0xx_hal_exti.c [code]

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32g0xx_hal_fdcan.c [code]

FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions.

file | stm32g0xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

file | stm32g0xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions.

file | stm32g0xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32g0xx_hal_hcd.c [code]

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32g0xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32g0xx_hal_i2c_ex.c [code]

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Filter Mode Functions + WakeUp Mode Functions + FastModePlus Functions.

file | stm32g0xx_hal_i2s.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32g0xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

file | stm32g0xx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

file | stm32g0xx_hal_lptim.c [code]

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

file | stm32g0xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32g0xx_hal_pcd_ex.c [code]

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

file | stm32g0xx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

file | stm32g0xx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

file | stm32g0xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32g0xx_hal_rcc_ex.c [code]

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions.

file | stm32g0xx_hal_rng.c [code]

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions.

file | stm32g0xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization functions + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

file | stm32g0xx_hal_rtc_ex.c [code]

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

file | stm32g0xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32g0xx_hal_smartcard_ex.c [code]

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32g0xx_hal_smbus.c [code]

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32g0xx_hal_smbus_ex.c [code]

SMBUS Extended HAL module driver. This file provides firmware functions to manage the following functionalities of SMBUS Extended peripheral: + Extended features functions.

file | stm32g0xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32g0xx_hal_spi_ex.c [code]

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

file | stm32g0xx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration.

file | stm32g0xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

file | stm32g0xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32g0xx_hal_uart_ex.c [code]

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32g0xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32g0xx_hal_usart_ex.c [code]

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions.

file | stm32g0xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions.

file | stm32g0xx_ll_adc.c [code]

ADC LL module driver.

file | stm32g0xx_ll_comp.c [code]

COMP LL module driver.

file | stm32g0xx_ll_crc.c [code]

CRC LL module driver.

file | stm32g0xx_ll_crs.c [code]
file | stm32g0xx_ll_dac.c [code]

DAC LL module driver.

file | stm32g0xx_ll_dma.c [code]

DMA LL module driver.

file | stm32g0xx_ll_exti.c [code]

EXTI LL module driver.

file | stm32g0xx_ll_gpio.c [code]

GPIO LL module driver.

file | stm32g0xx_ll_i2c.c [code]

I2C LL module driver.

file | stm32g0xx_ll_lptim.c [code]

LPTIM LL module driver.

file | stm32g0xx_ll_lpuart.c [code]

LPUART LL module driver.

file | stm32g0xx_ll_pwr.c [code]

PWR LL module driver.

file | stm32g0xx_ll_rcc.c [code]

RCC LL module driver.

file | stm32g0xx_ll_rng.c [code]

RNG LL module driver.

file | stm32g0xx_ll_rtc.c [code]

RTC LL module driver.

file | stm32g0xx_ll_spi.c [code]

SPI LL module driver.

file | stm32g0xx_ll_tim.c [code]

TIM LL module driver.

file | stm32g0xx_ll_ucpd.c [code]

UCPD LL module driver.

file | stm32g0xx_ll_usart.c [code]

USART LL module driver.

file | stm32g0xx_ll_utils.c [code]

UTILS LL module driver.

Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: C:/git/g0_release_v1.6.0/Firmware/Drivers/STM32G0xx_HAL_Driver/Inc/ Directory Reference

  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32g0xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32g0xx_hal_adc.h [code]

Header file of ADC HAL module.

file | stm32g0xx_hal_adc_ex.h [code]

Header file of ADC HAL extended module.

file | stm32g0xx_hal_cec.h [code]

Header file of CEC HAL module.

file | stm32g0xx_hal_comp.h [code]

Header file of COMP HAL module.

file | stm32g0xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32g0xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32g0xx_hal_crc_ex.h [code]

Header file of CRC HAL extended module.

file | stm32g0xx_hal_cryp.h [code]

Header file of CRYP HAL module.

file | stm32g0xx_hal_cryp_ex.h [code]

Header file of CRYPEx HAL module.

file | stm32g0xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32g0xx_hal_dac_ex.h [code]

Header file of DAC HAL Extended module.

file | stm32g0xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32g0xx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32g0xx_hal_exti.h [code]

Header file of EXTI HAL module.

file | stm32g0xx_hal_fdcan.h [code]

Header file of FDCAN HAL module.

file | stm32g0xx_hal_flash.h [code]

Header file of FLASH HAL module.

file | stm32g0xx_hal_flash_ex.h [code]

Header file of FLASH HAL Extended module.

file | stm32g0xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32g0xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extended module.

file | stm32g0xx_hal_hcd.h [code]

Header file of HCD HAL module.

file | stm32g0xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32g0xx_hal_i2c_ex.h [code]

Header file of I2C HAL Extended module.

file | stm32g0xx_hal_i2s.h [code]

Header file of I2S HAL module.

file | stm32g0xx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32g0xx_hal_irda_ex.h [code]

Header file of IRDA HAL Extended module.

file | stm32g0xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32g0xx_hal_lptim.h [code]

Header file of LPTIM HAL module.

file | stm32g0xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32g0xx_hal_pcd_ex.h [code]

Header file of PCD HAL Extension module.

file | stm32g0xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32g0xx_hal_pwr_ex.h [code]

Header file of PWR HAL Extended module.

file | stm32g0xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32g0xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extended module.

file | stm32g0xx_hal_rng.h [code]

Header file of RNG HAL module.

file | stm32g0xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32g0xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extended module.

file | stm32g0xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32g0xx_hal_smartcard_ex.h [code]

Header file of SMARTCARD HAL Extended module.

file | stm32g0xx_hal_smbus.h [code]

Header file of SMBUS HAL module.

file | stm32g0xx_hal_smbus_ex.h [code]

Header file of SMBUS HAL Extended module.

file | stm32g0xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32g0xx_hal_spi_ex.h [code]

Header file of SPI HAL Extended module.

file | stm32g0xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32g0xx_hal_tim_ex.h [code]

Header file of TIM HAL Extended module.

file | stm32g0xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32g0xx_hal_uart_ex.h [code]

Header file of UART HAL Extended module.

file | stm32g0xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32g0xx_hal_usart_ex.h [code]

Header file of USART HAL Extended module.

file | stm32g0xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

file | stm32g0xx_ll_adc.h [code]

Header file of ADC LL module.

file | stm32g0xx_ll_bus.h [code]

Header file of BUS LL module.

file | stm32g0xx_ll_comp.h [code]

Header file of COMP LL module.

file | stm32g0xx_ll_cortex.h [code]

Header file of CORTEX LL module.

file | stm32g0xx_ll_crc.h [code]

Header file of CRC LL module.

file | stm32g0xx_ll_crs.h [code]

CRS LL module driver.

file | stm32g0xx_ll_dac.h [code]

Header file of DAC LL module.

file | stm32g0xx_ll_dma.h [code]

Header file of DMA LL module.

file | stm32g0xx_ll_dmamux.h [code]

Header file of DMAMUX LL module.

file | stm32g0xx_ll_exti.h [code]

Header file of EXTI LL module.

file | stm32g0xx_ll_gpio.h [code]

Header file of GPIO LL module.

file | stm32g0xx_ll_i2c.h [code]

Header file of I2C LL module.

file | stm32g0xx_ll_iwdg.h [code]

Header file of IWDG LL module.

file | stm32g0xx_ll_lptim.h [code]

Header file of LPTIM LL module.

file | stm32g0xx_ll_lpuart.h [code]

Header file of LPUART LL module.

file | stm32g0xx_ll_pwr.h [code]

Header file of PWR LL module.

file | stm32g0xx_ll_rcc.h [code]

Header file of RCC LL module.

file | stm32g0xx_ll_rng.h [code]

Header file of RNG LL module.

file | stm32g0xx_ll_rtc.h [code]

Header file of RTC LL module.

file | stm32g0xx_ll_spi.h [code]

Header file of SPI LL module.

file | stm32g0xx_ll_system.h [code]

Header file of SYSTEM LL module.

file | stm32g0xx_ll_tim.h [code]

Header file of TIM LL module.

file | stm32g0xx_ll_ucpd.h [code]

Header file of UCPD LL module.

file | stm32g0xx_ll_usart.h [code]

Header file of USART LL module.

file | stm32g0xx_ll_utils.h [code]

Header file of UTILS LL module.

file | stm32g0xx_ll_wwdg.h [code]

Header file of WWDG LL module.

Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: C:/git/g0_release_v1.6.0/Firmware/ Directory Reference

  • Firmware
Firmware Directory Reference

Directories

directory Drivers
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: C:/git/g0_release_v1.6.0/Firmware/Drivers/ Directory Reference

  • Firmware
  • Drivers
Drivers Directory Reference

Directories

directory STM32G0xx_HAL_Driver
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: C:/git/g0_release_v1.6.0/Firmware/Drivers/STM32G0xx_HAL_Driver/ Directory Reference

  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
STM32G0xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Firmware
    • Drivers
      • STM32G0xx_HAL_Driver
        • Inc
        • Src
Generated on Mon Jun 6 2022 10:29:21 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32g0xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32g0xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32g0xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions Other functions (extended functions) are available in file "stm32g0xx_hal_adc_ex.c"
stm32g0xx_hal_adc.h [code] | Header file of ADC HAL module
stm32g0xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Converter (ADC) peripheral: + Peripheral Control functions Other functions (generic functions) are available in file "stm32g0xx_hal_adc.c"
stm32g0xx_hal_adc_ex.h [code] | Header file of ADC HAL extended module
stm32g0xx_hal_cec.c [code] | CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function
stm32g0xx_hal_cec.h [code] | Header file of CEC HAL module
stm32g0xx_hal_comp.c [code] | COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Peripheral control functions + Peripheral state functions
stm32g0xx_hal_comp.h [code] | Header file of COMP HAL module
stm32g0xx_hal_conf.h [code] | HAL configuration template file. This file should be copied to the application folder and renamed to stm32g0xx_hal_conf.h
stm32g0xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions
stm32g0xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32g0xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32g0xx_hal_crc.h [code] | Header file of CRC HAL module
stm32g0xx_hal_crc_ex.c [code] | Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral
stm32g0xx_hal_crc_ex.h [code] | Header file of CRC HAL extended module
stm32g0xx_hal_cryp.c [code] | CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions
stm32g0xx_hal_cryp.h [code] | Header file of CRYP HAL module
stm32g0xx_hal_cryp_ex.c [code] | CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral
stm32g0xx_hal_cryp_ex.h [code] | Header file of CRYPEx HAL module
stm32g0xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32g0xx_hal_dac.h [code] | Header file of DAC HAL module
stm32g0xx_hal_dac_ex.c [code] | Extended DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral
stm32g0xx_hal_dac_ex.h [code] | Header file of DAC HAL Extended module
stm32g0xx_hal_dma.c [code] | DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
stm32g0xx_hal_dma.h [code] | Header file of DMA HAL module
stm32g0xx_hal_dma_ex.c [code] | DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions
stm32g0xx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32g0xx_hal_exti.c [code] | EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32g0xx_hal_exti.h [code] | Header file of EXTI HAL module
stm32g0xx_hal_fdcan.c [code] | FDCAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible DataRate Controller Area Network (FDCAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Configuration and Control functions + Peripheral State and Error functions
stm32g0xx_hal_fdcan.h [code] | Header file of FDCAN HAL module
stm32g0xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions
stm32g0xx_hal_flash.h [code] | Header file of FLASH HAL module
stm32g0xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions
stm32g0xx_hal_flash_ex.h [code] | Header file of FLASH HAL Extended module
stm32g0xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32g0xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32g0xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extended module
stm32g0xx_hal_hcd.c [code] | HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32g0xx_hal_hcd.h [code] | Header file of HCD HAL module
stm32g0xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32g0xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32g0xx_hal_i2c_ex.c [code] | I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Filter Mode Functions + WakeUp Mode Functions + FastModePlus Functions
stm32g0xx_hal_i2c_ex.h [code] | Header file of I2C HAL Extended module
stm32g0xx_hal_i2s.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32g0xx_hal_i2s.h [code] | Header file of I2S HAL module
stm32g0xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions
stm32g0xx_hal_irda.h [code] | Header file of IRDA HAL module
stm32g0xx_hal_irda_ex.h [code] | Header file of IRDA HAL Extended module
stm32g0xx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions
stm32g0xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32g0xx_hal_lptim.c [code] | LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions
stm32g0xx_hal_lptim.h [code] | Header file of LPTIM HAL module
stm32g0xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32g0xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32g0xx_hal_pcd_ex.c [code] | PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions
stm32g0xx_hal_pcd_ex.h [code] | Header file of PCD HAL Extension module
stm32g0xx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions
stm32g0xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32g0xx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
stm32g0xx_hal_pwr_ex.h [code] | Header file of PWR HAL Extended module
stm32g0xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32g0xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32g0xx_hal_rcc_ex.c [code] | Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions
stm32g0xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extended module
stm32g0xx_hal_rng.c [code] | RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions
stm32g0xx_hal_rng.h [code] | Header file of RNG HAL module
stm32g0xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization/de-initialization functions + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management
stm32g0xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32g0xx_hal_rtc_ex.c [code] | Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions
stm32g0xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extended module
stm32g0xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32g0xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32g0xx_hal_smartcard_ex.c [code] | SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions
stm32g0xx_hal_smartcard_ex.h [code] | Header file of SMARTCARD HAL Extended module
stm32g0xx_hal_smbus.c [code] | SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32g0xx_hal_smbus.h [code] | Header file of SMBUS HAL module
stm32g0xx_hal_smbus_ex.c [code] | SMBUS Extended HAL module driver. This file provides firmware functions to manage the following functionalities of SMBUS Extended peripheral: + Extended features functions
stm32g0xx_hal_smbus_ex.h [code] | Header file of SMBUS HAL Extended module
stm32g0xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32g0xx_hal_spi.h [code] | Header file of SPI HAL module
stm32g0xx_hal_spi_ex.c [code] | Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions
stm32g0xx_hal_spi_ex.h [code] | Header file of SPI HAL Extended module
stm32g0xx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration
stm32g0xx_hal_tim.h [code] | Header file of TIM HAL module
stm32g0xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration
stm32g0xx_hal_tim_ex.h [code] | Header file of TIM HAL Extended module
stm32g0xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32g0xx_hal_uart.h [code] | Header file of UART HAL module
stm32g0xx_hal_uart_ex.c [code] | Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions
stm32g0xx_hal_uart_ex.h [code] | Header file of UART HAL Extended module
stm32g0xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32g0xx_hal_usart.h [code] | Header file of USART HAL module
stm32g0xx_hal_usart_ex.c [code] | Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions
stm32g0xx_hal_usart_ex.h [code] | Header file of USART HAL Extended module
stm32g0xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions
stm32g0xx_hal_wwdg.h [code] | Header file of WWDG HAL module
stm32g0xx_ll_adc.c [code] | ADC LL module driver
stm32g0xx_ll_adc.h [code] | Header file of ADC LL module
stm32g0xx_ll_bus.h [code] | Header file of BUS LL module
stm32g0xx_ll_comp.c [code] | COMP LL module driver
stm32g0xx_ll_comp.h [code] | Header file of COMP LL module
stm32g0xx_ll_cortex.h [code] | Header file of CORTEX LL module
stm32g0xx_ll_crc.c [code] | CRC LL module driver
stm32g0xx_ll_crc.h [code] | Header file of CRC LL module
stm32g0xx_ll_crs.c [code] |
stm32g0xx_ll_crs.h [code] | CRS LL module driver
stm32g0xx_ll_dac.c [code] | DAC LL module driver
stm32g0xx_ll_dac.h [code] | Header file of DAC LL module
stm32g0xx_ll_dma.c [code] | DMA LL module driver
stm32g0xx_ll_dma.h [code] | Header file of DMA LL module
stm32g0xx_ll_dmamux.h [code] | Header file of DMAMUX LL module
stm32g0xx_ll_exti.c [code] | EXTI LL module driver
stm32g0xx_ll_exti.h [code] | Header file of EXTI LL module
stm32g0xx_ll_gpio.c [code] | GPIO LL module driver
stm32g0xx_ll_gpio.h [code] | Header file of GPIO LL module
stm32g0xx_ll_i2c.c [code] | I2C LL module driver
stm32g0xx_ll_i2c.h [code] | Header file of I2C LL module
stm32g0xx_ll_iwdg.h [code] | Header file of IWDG LL module
stm32g0xx_ll_lptim.c [code] | LPTIM LL module driver
stm32g0xx_ll_lptim.h [code] | Header file of LPTIM LL module
stm32g0xx_ll_lpuart.c [code] | LPUART LL module driver
stm32g0xx_ll_lpuart.h [code] | Header file of LPUART LL module
stm32g0xx_ll_pwr.c [code] | PWR LL module driver
stm32g0xx_ll_pwr.h [code] | Header file of PWR LL module
stm32g0xx_ll_rcc.c [code] | RCC LL module driver
stm32g0xx_ll_rcc.h [code] | Header file of RCC LL module
stm32g0xx_ll_rng.c [code] | RNG LL module driver
stm32g0xx_ll_rng.h [code] | Header file of RNG LL module
stm32g0xx_ll_rtc.c [code] | RTC LL module driver
stm32g0xx_ll_rtc.h [code] | Header file of RTC LL module
stm32g0xx_ll_spi.c [code] | SPI LL module driver
stm32g0xx_ll_spi.h [code] | Header file of SPI LL module
stm32g0xx_ll_system.h [code] | Header file of SYSTEM LL module
stm32g0xx_ll_tim.c [code] | TIM LL module driver
stm32g0xx_ll_tim.h [code] | Header file of TIM LL module
stm32g0xx_ll_ucpd.c [code] | UCPD LL module driver
stm32g0xx_ll_ucpd.h [code] | Header file of UCPD LL module
stm32g0xx_ll_usart.c [code] | USART LL module driver
stm32g0xx_ll_usart.h [code] | Header file of USART LL module
stm32g0xx_ll_utils.c [code] | UTILS LL module driver
stm32g0xx_ll_utils.h [code] | Header file of UTILS LL module
stm32g0xx_ll_wwdg.h [code] | Header file of WWDG LL module
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC

Modules
ADC
STM32G0xx_HAL_Driver

ADC HAL module driver. More...

Modules

ADC Private Constants
ADC Private Functions
ADC Exported Functions
ADC Exported Types
ADC Exported Constants
ADC Private Macros

Detailed Description

ADC HAL module driver.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC | ADC Private Macros

Modules

Initialization and de-initialization functions

ADC Initialization and Configuration functions.

ADC Input and Output operation functions

ADC IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

ADC Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC Private Macros

Modules

HAL ADC macro to manage HAL ADC handle, IT and flags.
HAL ADC helper macro
Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC

Modules
ADC
STM32G0xx_LL_Driver

Modules

ADC Private Constants
ADC Private Macros
ADC Exported Init structure
ADC Exported Constants
ADC Exported Macros
ADC Exported Functions
Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Exported Init structure

Data Structures
ADC Exported Init structure
ADC

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC flags

Flags defines which can be used with LL_ADC_ReadReg function.

ADC interruptions for configuration (interruption enable or disable)

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

ADC registers compliant with specific purpose
ADC common - Clock source
ADC common - Clock frequency mode
ADC common - Measurement path to internal channels
ADC instance - Clock source
ADC instance - Resolution
ADC instance - Data alignment
ADC instance - Low power mode
ADC group regular - Trigger frequency mode
ADC instance - Sampling time common to a group of channels
ADC instance - Groups
ADC instance - Channel number
ADC group regular - Trigger source
ADC group regular - Trigger edge
ADC group regular - Continuous mode
ADC group regular - DMA transfer of ADC conversion data
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer configuration flexibility
ADC group regular - Sequencer scan length
ADC group regular - Sequencer scan direction
ADC group regular - Sequencer discontinuous mode
ADC group regular - Sequencer ranks
Channel - Sampling time
Analog watchdog - Analog watchdog number
Analog watchdog - Monitored channels
Analog watchdog - Thresholds
Oversampling - Oversampling scope
Oversampling - Discontinuous mode
Oversampling - Ratio
Oversampling - Data shift
Definitions of constants used by helper macro
Definitions of ADC hardware constraints delays
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STM32G0C1xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

ADC DMA management
Configuration of ADC hierarchical scope: common to several ADC instances
Configuration of ADC hierarchical scope: ADC instance
Configuration of ADC hierarchical scope: group regular
Configuration of ADC hierarchical scope: channels
Configuration of ADC transversal scope: analog watchdog
Configuration of ADC transversal scope: oversampling
Operation on ADC hierarchical scope: ADC instance
Operation on ADC hierarchical scope: group regular
ADC flag management
ADC IT management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

Common write and read registers Macros
ADC helper macro
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STM32G0C1xx HAL User Manual: ADCEx

Modules
ADCEx
STM32G0xx_HAL_Driver

ADC Extended HAL module driver. More...

Modules

ADC Extended Private Constants
ADC Extended Exported Functions
ADC Extended Exported Types
ADC Extended Exported Constants
ADC Extended Private Macros

Detailed Description

ADC Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: ADC Extended Exported Constants

Modules
ADC Extended Exported Constants
ADCEx

Modules

ADC instance - Groups
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STM32G0C1xx HAL User Manual: BUS

Modules
BUS
STM32G0xx_LL_Driver

Modules

BUS Exported Constants
BUS Exported Functions
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STM32G0C1xx HAL User Manual: BUS Exported Constants

Modules
BUS Exported Constants
BUS

Modules

AHB1 GRP1 PERIPH
APB1 GRP1 PERIPH
APB2 GRP1 PERIPH
IOP GRP1 PERIPH
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STM32G0C1xx HAL User Manual: BUS Exported Functions

Modules
BUS Exported Functions
BUS

Modules

AHB1
APB1
APB2
IOP
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STM32G0C1xx HAL User Manual: CEC

Modules
CEC
STM32G0xx_HAL_Driver

HAL CEC module driver. More...

Modules

CEC Private Constants
CEC Private Functions
CEC Exported Functions
CEC Exported Types
CEC Exported Constants
CEC Exported Macros
CEC Private Types
CEC Private Variables
CEC Private Macros

Detailed Description

HAL CEC module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Exported Constants

Modules
CEC Exported Constants
CEC

Modules

CEC State Code Definition
CEC Error Code
CEC Signal Free Time setting parameter
CEC Receiver Tolerance
CEC Reception Stop on Error
CEC Error Bit Generation if Bit Rise Error reported
CEC Error Bit Generation if Long Bit Period Error reported
CEC Error Bit Generation on Broadcast message
CEC Signal Free Time start option
CEC Listening mode option
CEC Device Own Address position in CEC CFGR register
CEC Initiator logical address position in message header
CEC Own Address
CEC Interrupts definition
CEC Flags definition
CEC all RX or TX errors flags
CEC all RX errors interrupts enabling flag
CEC all TX errors interrupts enabling flag
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CEC Exported Functions

Modules
CEC Exported Functions
CEC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

CEC Transmit/Receive functions.

Peripheral Control function

CEC control functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP

Modules
COMP
STM32G0xx_HAL_Driver

COMP HAL module driver. More...

Modules

COMP Exported Functions
COMP Exported Types
COMP Exported Constants
COMP Exported Macros
COMP Private Constants
COMP Private Macros

Detailed Description

COMP HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

COMP Error Code
COMP Window Mode
COMP Window output
COMP power mode
COMP input plus (non-inverting input)
COMP input minus (inverting input)
COMP hysteresis
COMP output Polarity
COMP blanking source
COMP Output Level
COMP output to EXTI
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Initialization/de-initialization functions

Initialization and de-initialization functions.

Start-Stop operation functions

Start-Stop operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

COMP Handle Management
COMP external interrupt line management
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STM32G0C1xx HAL User Manual: COMP

Modules
COMP
STM32G0xx_LL_Driver

Modules

COMP Private Constants
COMP Private Macros
COMP Exported Init structure
COMP Exported Constants
COMP Exported Macros
COMP Exported Functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Exported Init structure

Data Structures
COMP Exported Init structure
COMP

Data Structures

struct LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...
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STM32G0C1xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

Comparator common modes - Window mode
Comparator common modes - Window output
Comparator modes - Power mode
Comparator inputs - Input plus (input non-inverting) selection
Comparator inputs - Input minus (input inverting) selection
Comparator input - Hysteresis
Comparator output - Output polarity
Comparator output - Blanking source
Comparator output - Output level
Definitions of COMP hardware constraints delays
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Configuration of COMP hierarchical scope: common to several COMP instances
Configuration of comparator modes
Configuration of comparator inputs
Configuration of comparator output
Operation on comparator instance
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

Common write and read registers macro
COMP helper macro
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: COMP Private Macros

Modules
COMP Private Macros
COMP

Modules

COMP private macros to get EXTI line associated with comparators
COMP private macros to check input parameters
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STM32G0C1xx HAL User Manual: CORTEX

Modules
CORTEX
STM32G0xx_HAL_Driver

CORTEX HAL module driver. More...

Modules

CORTEX Exported Types
CORTEX Exported Constants
CORTEX Exported Macros
CORTEX Exported Functions
CORTEX Private Macros

Detailed Description

CORTEX HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX SysTick clock source
CORTEX MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
CORTEX MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX Exported Types

Modules
CORTEX Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition

MPU Region initialization structure.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX

Modules
CORTEX
STM32G0xx_LL_Driver

Modules

CORTEX Exported Constants
CORTEX Exported Functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

SYSTICK Clock Source
MPU Control
MPU Region Number
MPU Region Size
MPU Region Privileges
MPU TEX Level
MPU Instruction Access
MPU Shareable Access
MPU Cacheable Access
MPU Bufferable Access
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

SYSTICK
LOW POWER MODE
MCU INFO
MPU
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
CORTEX Exported Types

MPU Region initialization structure. More...

Data Structures

struct MPU_Region_InitTypeDef

Detailed Description

MPU Region initialization structure.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC

Modules
CRC
STM32G0xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Private Functions
CRC Exported Functions
CRC Exported Types
CRC Exported Constants
CRC Exported Macros
CRC Private Macros

Detailed Description

CRC HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Default CRC generating polynomial
Default CRC computation initialization value
Indicates whether or not default polynomial is used
Indicates whether or not default init value is used
Polynomial sizes to configure the peripheral
CRC polynomial possible sizes actual definitions
Input Buffer Format
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STM32G0C1xx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

management functions.

Peripheral State functions

Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC

Modules
CRC
STM32G0xx_LL_Driver

Modules

CRC Exported Constants
CRC Exported Macros
CRC Exported Functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Polynomial length
Input Data Reverse
Output Data Reverse
Default CRC generating polynomial value

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Default CRC computation initialization value
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STM32G0C1xx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

CRC Configuration functions
Data_Management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC Exported Macros

Modules
CRC Exported Macros
CRC

Modules

Common Write and read registers Macros
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRCEx

Modules
CRCEx
STM32G0xx_HAL_Driver

CRC Extended HAL module driver. More...

Modules

CRC Extended Exported Functions
CRC Extended Exported Constants
CRC Extended Exported Macros
CRC Extended Private Macros

Detailed Description

CRC Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRC Extended Exported Constants

Modules
CRC Extended Exported Constants
CRCEx

Modules

Input Data Inversion Modes
Output Data Inversion Modes
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STM32G0C1xx HAL User Manual: CRC Extended Exported Functions

Modules
CRC Extended Exported Functions
CRCEx

Modules

Extended Initialization/de-initialization functions

Extended Initialization and Configuration functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRS

Modules
CRS
STM32G0xx_LL_Driver

Modules

CRS Exported Constants
CRS Exported Macros
CRS Exported Functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRS Exported Constants

Modules
CRS Exported Constants
CRS

Modules

Get Flags Defines

Flags defines which can be used with LL_CRS_ReadReg function.

IT Defines

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions.

Synchronization Signal Divider
Synchronization Signal Source
Synchronization Signal Polarity
Frequency Error Direction
Default Values
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STM32G0C1xx HAL User Manual: CRS Exported Functions

Modules
CRS Exported Functions
CRS

Modules

Configuration
CRS_Management
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRS Exported Macros

Modules
CRS Exported Macros
CRS

Modules

Common Write and read registers Macros
Exported_Macros_Calculate_Reload
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP

Modules
CRYP
STM32G0xx_HAL_Driver

CRYP HAL module driver. More...

Modules

CRYP Exported Types
CRYP Exported Constants
CRYP Exported Macros
CRYP Exported Functions
CRYP Private Macros
CRYP Private Constants
CRYP Private Defines
CRYP Private Variables
CRYP Private Functions

Detailed Description

CRYP HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Exported Constants

Modules
CRYP Exported Constants
CRYP

Modules

CRYP Error Definition
CRYP Data Width Unit
CRYP Header Width Unit
CRYP Algorithm Mode
CRYP Key Size
CRYP Data Type
CRYP Interrupt
CRYP Flags
CRYP Key and IV Configuration Skip Mode
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYP Exported Functions

Modules
CRYP Exported Functions
CRYP

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Encryption Decryption functions

Encryption Decryption functions.

CRYP IRQ handler management

CRYP IRQ handler.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYPEx

Modules
CRYPEx
STM32G0xx_HAL_Driver

CRYP Extension HAL module driver. More...

Modules

CRYPEx Private Types
CRYPEx Private Variables
CRYPEx Private Constants
CRYPEx Private Macros
CRYPEx Private Functions
CRYPEx Exported Functions
CRYPEx_Private_Defines

Detailed Description

CRYP Extension HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: CRYPEx Exported Functions

Modules
CRYPEx Exported Functions
CRYPEx

Modules

Extended AES processing functions

Extended processing functions.

Extended AES Key Derivations functions

Extended Key Derivations functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC

Modules
DAC
STM32G0xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Exported Functions
DAC Exported Types
DAC Exported Constants
DAC Exported Macros
DAC Private Macros
DAC Private Functions
DAC Private Constants

Detailed Description

DAC driver modules.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC Error Code
DAC trigger selection
DAC output buffer
DAC Channel selection
DAC data alignment
DAC flags definition
DAC IT definition
DAC ConnectOnChipPeripheral
DAC User Trimming
DAC power mode
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC

Modules
DAC
STM32G0xx_LL_Driver

Modules

DAC Private Constants
DAC Private Macros
DAC Exported Init structure
DAC Exported Constants
DAC Exported Macros
DAC Exported Functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Exported Init structure

Data Structures
DAC Exported Init structure
DAC

Data Structures

struct LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...
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STM32G0C1xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC flags

Flags defines which can be used with LL_DAC_ReadReg function.

DAC interruptions

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

DAC channels
DAC operating mode
DAC trigger source
DAC waveform automatic generation mode
DAC wave generation - Noise LFSR unmask bits
DAC wave generation - Triangle amplitude
DAC channel output mode
DAC channel output buffer
DAC channel output connection
DAC channel output resolution
DAC registers compliant with specific purpose
Definitions of DAC hardware constraints delays
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Configuration of DAC channels
DMA Management
Operation on DAC channels
FLAG Management
IT management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DAC Exported Macros

Modules
DAC Exported Macros
DAC

Modules

Common write and read registers macros
DAC helper macro
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DACEx

Modules
DACEx
STM32G0xx_HAL_Driver

DAC Extended HAL module driver. More...

Modules

DACEx Exported Functions
DACEx private functions

Extended private functions.

DACEx Exported Constants

HAL State structures definition.

DACEx Private Macros

Detailed Description

DAC Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DACEx Exported Constants

Modules
DACEx Exported Constants
DACEx

HAL State structures definition. More...

Modules

DACEx lfsrunmask triangle amplitude

Detailed Description

HAL State structures definition.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DACEx Exported Functions

Modules
DACEx Exported Functions
DACEx

Modules

IO operation functions

Extended IO operation functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA

Modules
DMA
STM32G0xx_HAL_Driver

DMA HAL module driver. More...

Modules

DMA Private Functions
DMA Exported Functions
DMA Exported Types
DMA Exported Constants
DMA Exported Macros
DMA Private Macros

Detailed Description

DMA HAL module driver.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

DMA Error Code
DMA request
DMA Data transfer direction
DMA Peripheral incremented mode
DMA Memory incremented mode
DMA Peripheral data size
DMA Memory data size
DMA mode
DMA Priority level
DMA interrupt enable definitions
DMA flag definitions
Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Input and Output operation functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Generated on Mon Jun 6 2022 10:29:07 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA

Modules
DMA
STM32G0xx_LL_Driver

Modules

DMA Private Variables
DMA Private Macros
DMA Exported Init structure
DMA Exported Constants
DMA Exported Macros
DMA Exported Functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Exported Init structure

Data Structures
DMA Exported Init structure
DMA

Data Structures

struct LL_DMA_InitTypeDef
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMA_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMA_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

CHANNEL
Transfer Direction
Transfer mode
Peripheral increment mode
Memory increment mode
Peripheral data alignment
Memory data alignment
Transfer Priority level
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:14 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: DMA Exported Macros

Modules
DMA Exported Macros
DMA

Modules

Common Write and read registers macros
Convert DMAxChannely
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STM32G0C1xx HAL User Manual: DMAEx

Modules
DMAEx
STM32G0xx_HAL_Driver

DMA Extended HAL module driver. More...

Modules

DMAEx Exported Functions
DMAEx Exported Types
DMAEx Exported Constants
DMAEx Private Macros

DMAEx private macros.

Detailed Description

DMA Extended HAL module driver.

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STM32G0C1xx HAL User Manual: DMAEx Exported Constants

Modules
DMAEx Exported Constants
DMAEx

Modules

DMAMUX SyncSignalID selection
DMAMUX SyncPolarity selection
DMAMUX SignalGeneratorID selection
DMAMUX RequestGeneneratorPolarity selection
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STM32G0C1xx HAL User Manual: DMAEx Exported Functions

Modules
DMAEx Exported Functions
DMAEx

Modules

DMAEx Extended features functions

Extended features functions.

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STM32G0C1xx HAL User Manual: DMAEx Exported Types

Data Structures
DMAEx Exported Types
DMAEx

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMAMUX Synchronization configuration structure definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...
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STM32G0C1xx HAL User Manual: DMAMUX

Modules
DMAMUX
STM32G0xx_LL_Driver

Modules

DMAMUX Private Constants
DMAMUX Exported Constants
DMAMUX Exported Macros
DMAMUX Exported Functions
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STM32G0C1xx HAL User Manual: DMAMUX Exported Constants

Modules
DMAMUX Exported Constants
DMAMUX

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMAMUX_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMAMUX_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions.

Transfer request
DMAMUX Channel
Synchronization Signal Polarity
Synchronization Signal Event
Request Generator Channel
External Request Signal Generation Polarity
External Request Signal Generation
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STM32G0C1xx HAL User Manual: DMAMUX Exported Functions

Modules
DMAMUX Exported Functions
DMAMUX

Modules

Configuration
FLAG_Management
IT_Management
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STM32G0C1xx HAL User Manual: DMAMUX Exported Macros

Modules
DMAMUX Exported Macros
DMAMUX

Modules

Common Write and read registers macros
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STM32G0C1xx HAL User Manual: EXTI

Modules
EXTI
STM32G0xx_HAL_Driver

EXTI HAL module driver. More...

Modules

EXTI Private Constants

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine.

EXTI Exported Types
EXTI Exported Constants
EXTI Exported Macros
EXTI Private Macros
EXTI Exported Functions

EXTI Exported Functions.

Detailed Description

EXTI HAL module driver.

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STM32G0C1xx HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

EXTI Line
EXTI Mode
EXTI Trigger
EXTI GPIOSel
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STM32G0C1xx HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

EXTI Exported Functions. More...

Modules

Configuration functions

Configuration functions.

IO operation functions

IO operation functions.

Detailed Description

EXTI Exported Functions.

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STM32G0C1xx HAL User Manual: EXTI Exported Init structure

Data Structures
EXTI Exported Init structure
EXTI

Data Structures

struct LL_EXTI_InitTypeDef
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STM32G0C1xx HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

LINE
Mode
Edge Trigger
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STM32G0C1xx HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

Modules

IT_Management
Event_Management
Rising_Trigger_Management
Falling_Trigger_Management
Software_Interrupt_Management
Flag_Management
EF configuration functions
Initialization and de-initialization functions
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STM32G0C1xx HAL User Manual: EXTI Exported Macros

Modules
EXTI Exported Macros
EXTI

Modules

Common Write and read registers Macros
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STM32G0C1xx HAL User Manual: FDCAN

Modules
FDCAN
STM32G0xx_HAL_Driver

FDCAN HAL module driver. More...

Modules

FDCAN Exported Functions
FDCAN Private Functions
FDCAN Exported Types
FDCAN Exported Constants
FDCAN Exported Macros
FDCAN Private Variables
FDCAN Private Constants
FDCAN Private Macros

Detailed Description

FDCAN HAL module driver.

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STM32G0C1xx HAL User Manual: FDCAN Exported Constants

Modules
FDCAN Exported Constants
FDCAN

Modules

HAL FDCAN Error Code
FDCAN Frame Format
FDCAN Operating Mode
FDCAN Clock Divider
FDCAN Tx FIFO/Queue Mode
FDCAN ID Type
FDCAN Frame Type
FDCAN Data Length Code
FDCAN Error State Indicator
FDCAN Bit Rate Switching
FDCAN format
FDCAN Event FIFO control
FDCAN Filter Type
FDCAN Filter Configuration
FDCAN Tx Location
FDCAN Rx Location
FDCAN Event Type
FDCAN High Priority Message Storage
FDCAN protocol error code
FDCAN communication state
FDCAN FIFO operation mode
FDCAN non-matching frames
FDCAN reject remote frames
FDCAN interrupt line
FDCAN timestamp
FDCAN timestamp prescaler
FDCAN timeout operation
Interrupt masks
FDCAN Flags
FDCAN Interrupts
FDCAN Interrupts List
FDCAN Interrupts Group
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STM32G0C1xx HAL User Manual: FDCAN Exported Functions

Modules
FDCAN Exported Functions
FDCAN

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Configuration functions

FDCAN Configuration functions.

Control functions

Control functions.

Interrupts management

Interrupts management.

Callback functions

FDCAN Callback functions.

Peripheral State functions

FDCAN Peripheral State functions.

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STM32G0C1xx HAL User Manual: FDCAN Interrupts

Modules
FDCAN Interrupts
FDCAN Exported Constants

Modules

FDCAN Tx Interrupts
FDCAN Rx Interrupts
FDCAN Counter Interrupts
FDCAN Tx Event FIFO Interrupts
FDCAN Rx FIFO 0 Interrupts
FDCAN Rx FIFO 1 Interrupts
FDCAN Error Interrupts
FDCAN Error Status Interrupts
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STM32G0C1xx HAL User Manual: FLASH

Modules
FLASH
STM32G0xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Private Variables
FLASH Private Functions
FLASH Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros

macros to control FLASH features

FLASH Interrupts Macros

macros to handle FLASH interrupts

FLASH Exported Variables
FLASH Private Types
FLASH Private Constants
FLASH Private Macros

Detailed Description

FLASH HAL module driver.

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STM32G0C1xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Keys
FLASH Latency
FLASH Flags Definition
FLASH Interrupts Definition

FLASH Interrupt definition.

FLASH Error
FLASH Erase Type
FLASH Banks
FLASH Program Type
FLASH Option Bytes Type
FLASH WRP Area
FLASH Option Bytes Read Protection
FLASH Option Bytes User Type
FLASH Option Bytes User BOR enable
FLASH Option Bytes User BOR Level
FLASH Option Bytes User Reset On Stop
FLASH Option Bytes User Reset On Standby
FLASH Option Bytes User Reset On Shutdown
FLASH Option Bytes User IWDG Type
FLASH Option Bytes User IWDG Mode On Stop
FLASH Option Bytes User IWDG Mode On Standby
FLASH Option Bytes User WWDG Type
FLASH Option Bytes User bank swap Type
FLASH Option Bytes User dual bank enable Type
FLASH Option Bytes User SRAM parity
FLASH Option Bytes User Boot0 Selection
FLASH Option Bytes User BOOT1 Type
FLASH Option Bytes User nBOOT0 option bit
FLASH Option Bytes User reset config bit
FLASH Option Bytes User input reset holder bit
FLASH Option Bytes PCROP ZONE
FLASH Option Bytes PCROP On RDP Level Type
FLASH Option Bytes Secure boot lock
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STM32G0C1xx HAL User Manual: FLASH Exported Functions

Modules
FLASH Exported Functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

Management functions.

Peripheral State and Errors functions

Peripheral Errors functions.

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STM32G0C1xx HAL User Manual: FLASH Exported Types

Data Structures
FLASH Exported Types
FLASH

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...
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STM32G0C1xx HAL User Manual: FLASHEx

Modules
FLASHEx
STM32G0xx_HAL_Driver

FLASH Extended HAL module driver. More...

Modules

FLASHEx Private Functions
FLASH Extended Exported Functions
FLASH Exported Constants
FLASHEx Private Constants
FLASHEx Private Macros

Detailed Description

FLASH Extended HAL module driver.

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STM32G0C1xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASHEx

Modules

FLASHEx Empty Check
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STM32G0C1xx HAL User Manual: FLASH Extended Exported Functions

Modules
FLASH Extended Exported Functions
FLASHEx

Modules

Extended IO operation functions

Extended IO operation functions.

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STM32G0C1xx HAL User Manual: GPIO

Modules
GPIO
STM32G0xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros
GPIO Private Constants

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit.

GPIO Private Macros
GPIO Exported Functions

GPIO Exported Functions.

Detailed Description

GPIO HAL module driver.

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STM32G0C1xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins
GPIO mode

GPIO Configuration Mode Elements values convention: 0x00WX00YZ.

GPIO speed

GPIO Output Maximum frequency.

GPIO pull

GPIO Pull-Up or Pull-Down Activation.

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STM32G0C1xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

GPIO Exported Functions. More...

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Detailed Description

GPIO Exported Functions.

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STM32G0C1xx HAL User Manual: GPIO

Modules
GPIO
STM32G0xx_LL_Driver

Modules

GPIO Private Macros

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15.

GPIO Exported Init structures
GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions
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STM32G0C1xx HAL User Manual: GPIO Exported Init structures

Data Structures
GPIO Exported Init structures
GPIO

Data Structures

struct LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...
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STM32G0C1xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Port Configuration
Data Access
Initialization and de-initialization functions
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STM32G0C1xx HAL User Manual: GPIO Exported Macros

Modules
GPIO Exported Macros
GPIO

Modules

Common Write and read registers Macros
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STM32G0C1xx HAL User Manual: GPIOEx

Modules
GPIOEx
STM32G0xx_HAL_Driver

GPIO Extended HAL module driver. More...

Modules

GPIOEx Exported Constants
GPIOEx Exported Macros

Detailed Description

GPIO Extended HAL module driver.

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STM32G0C1xx HAL User Manual: GPIOEx Exported Constants

Modules
GPIOEx Exported Constants
GPIOEx

Modules

GPIOEx Alternate function selection
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STM32G0C1xx HAL User Manual: GPIOEx Exported Macros

Modules
GPIOEx Exported Macros
GPIOEx

Modules

GPIOEx Get Port Index
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STM32G0C1xx HAL User Manual: HAL

Modules
HAL
STM32G0xx_HAL_Driver

HAL module driver. More...

Modules

HAL Private Constants
HAL Exported Variables
Tick Frequency
HAL Exported Constants
HAL Exported Macros
SYSCFG Private Macros
HAL Private Macros
HAL Exported Functions

Detailed Description

HAL module driver.

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STM32G0C1xx HAL User Manual: HAL Exported Constants

Modules
HAL Exported Constants
HAL

Modules

SYSCFG Exported Constants
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STM32G0C1xx HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

HAL Initialization and Configuration functions

HAL Initialization and Configuration functions.

HAL Control functions

HAL Control functions.

DBGMCU Control functions

HAL Debug functions.

SYSCFG configuration functions

SYSCFG configuration functions.

HAL Exported Variables
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STM32G0C1xx HAL User Manual: HAL Exported Macros

Modules
HAL Exported Macros
HAL

Modules

DBG Exported Macros
SYSCFG Exported Macros
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STM32G0C1xx HAL User Manual: HCD

Modules
HCD
STM32G0xx_HAL_Driver

HCD HAL module driver. More...

Modules

HCD Private Functions
HCD Exported Functions
HCD Exported Types
HCD Exported Constants
HCD Exported Macros

macros to handle interrupts and specific clock configurations

HCD Private Macros

Detailed Description

HCD HAL module driver.

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STM32G0C1xx HAL User Manual: HCD Exported Constants

Modules
HCD Exported Constants
HCD

Modules

HCD Speed
HCD Device Speed
HCD PHY Module
HCD Error Code definition

HCD Error Code definition.

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STM32G0C1xx HAL User Manual: HCD Exported Functions

Modules
HCD Exported Functions
HCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

HCD IO operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

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STM32G0C1xx HAL User Manual: HCD Exported Types

Modules
HCD Exported Types
HCD

Modules

HCD State Structure definition
HCD Handle Structure definition
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STM32G0C1xx HAL User Manual: I2C Configuration Structure definition

Data Structures
I2C Configuration Structure definition
I2C Exported Types

I2C Configuration Structure definition. More...

Data Structures

struct I2C_InitTypeDef

Detailed Description

I2C Configuration Structure definition.

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STM32G0C1xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Sequential Transfer Options
I2C Addressing Mode
I2C Dual Addressing Mode
I2C Own Address2 Masks
I2C General Call Addressing Mode
I2C No-Stretch Mode
I2C Memory Address Size
I2C Transfer Direction Master Point of View
I2C Reload End Mode
I2C Start or Stop Mode
I2C Interrupt configuration definition

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

I2C Flag definition
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STM32G0C1xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State, Mode and Error functions

Peripheral State, Mode and Error functions.

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STM32G0C1xx HAL User Manual: I2C Exported Types

Modules
I2C Exported Types
I2C

Modules

I2C Configuration Structure definition

I2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

HAL mode structure definition

HAL Mode structure definition.

I2C Error Code definition

I2C Error Code definition.

I2C handle Structure definition

I2C handle Structure definition.

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STM32G0C1xx HAL User Manual: I2C

Modules
I2C
STM32G0xx_LL_Driver

Modules

I2C Private Constants
I2C Private Macros
I2C Exported Init structure
I2C Exported Constants
I2C Exported Macros
I2C Exported Functions
Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Exported Init structure

Data Structures
I2C Exported Init structure
I2C

Data Structures

struct LL_I2C_InitTypeDef
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STM32G0C1xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

Clear Flags Defines

Flags defines which can be used with LL_I2C_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_I2C_ReadReg function.

IT Defines

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Peripheral Mode
Analog Filter Selection
Master Addressing Mode
Own Address 1 Length
Own Address 2 Masks
Acknowledge Generation
Slave Address Length
Transfer Request Direction
Transfer End Mode
Start And Stop Generation
Read Write Direction
DMA Register Data
SMBus TimeoutA Mode SCL SDA Timeout
SMBus Timeout Selection
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STM32G0C1xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Configuration
IT_Management
FLAG_management
Data_Management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Exported Macros

Modules
I2C Exported Macros
I2C

Modules

Common Write and read registers Macros
Convert SDA SCL timings
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STM32G0C1xx HAL User Manual: I2CEx

Modules
I2CEx
STM32G0xx_HAL_Driver

I2C Extended HAL module driver. More...

Modules

I2C Extended Exported Functions
I2C Extended Exported Constants
I2C Extended Exported Macros
I2C Extended Private Constants
I2C Extended Private Macros
I2C Extended Private Functions

Detailed Description

I2C Extended HAL module driver.

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STM32G0C1xx HAL User Manual: I2C Extended Exported Constants

Modules
I2C Extended Exported Constants
I2CEx

Modules

I2C Extended Analog Filter
I2C Extended Fast Mode Plus
Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2C Extended Exported Functions

Modules
I2C Extended Exported Functions
I2CEx

Modules

Filter Mode Functions

Filter Mode Functions.

WakeUp Mode Functions

WakeUp Mode Functions.

Fast Mode Plus Functions

Fast Mode Plus Functions.

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STM32G0C1xx HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

I2S Error
I2S Mode
I2S Standard
I2S Data Format
I2S MCLK Output
I2S Audio Frequency
I2S Clock Polarity
I2S Interrupts Definition
I2S Flags Definition
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STM32G0C1xx HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S

Modules
I2S
STM32G0xx_LL_Driver

Modules

I2S Private Constants
I2S Private Macros
I2S Exported Init structure
I2S Exported Constants
I2S Exported Macros
I2S Exported Functions
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: I2S Exported Init structure

Data Structures
I2S Exported Init structure
I2S

Data Structures

struct LL_I2S_InitTypeDef
I2S Init structure definition. More...
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STM32G0C1xx HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

Get Flags Defines

Flags defines which can be used with LL_I2S_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Data format
Clock Polarity
I2s Standard
Operation Mode
Prescaler Factor
MCLK Output
Audio Frequency
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STM32G0C1xx HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Configuration
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
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STM32G0C1xx HAL User Manual: I2S Exported Macros

Modules
I2S Exported Macros
I2S

Modules

Common Write and read registers Macros
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STM32G0C1xx HAL User Manual: IRDA

Modules
IRDA
STM32G0xx_HAL_Driver

HAL IRDA module driver. More...

Modules

IRDA Private Constants
IRDA Private Macros
IRDA Exported Functions
IRDA Private Functions
IRDA Exported Types
IRDA Exported Constants
IRDA Exported Macros

Detailed Description

HAL IRDA module driver.

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STM32G0C1xx HAL User Manual: IRDA Exported Constants

Modules
IRDA Exported Constants
IRDA

Modules

IRDA State Code Definition
IRDA Error Code Definition
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA Clock Prescaler
IRDA State
IRDA Mode
IRDA One Bit Sampling
IRDA DMA Tx
IRDA DMA Rx
IRDA Request Parameters
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

IRDA Interruption Clear Flags
IRDA interruptions flags mask
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STM32G0C1xx HAL User Manual: IRDA Exported Functions

Modules
IRDA Exported Functions
IRDA

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit and Receive functions.

Peripheral State and Error functions

IRDA State and Errors functions.

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STM32G0C1xx HAL User Manual: IRDAEx

Modules
IRDAEx
STM32G0xx_HAL_Driver

IRDA Extended HAL module driver. More...

Modules

IRDAEx Extended Exported Constants
IRDAEx Private Macros

Detailed Description

IRDA Extended HAL module driver.

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STM32G0C1xx HAL User Manual: IRDAEx Extended Exported Constants

Modules
IRDAEx Extended Exported Constants
IRDAEx

Modules

IRDAEx Word Length
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STM32G0C1xx HAL User Manual: IWDG

Modules
IWDG
STM32G0xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
IWDG Private Constants
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

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STM32G0C1xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Prescaler
IWDG Window option
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STM32G0C1xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and Start functions

Initialization and Start functions.

IO operation functions

IO operation functions.

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STM32G0C1xx HAL User Manual: IWDG Exported Types

Data Structures
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...
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STM32G0C1xx HAL User Manual: IWDG

Modules
IWDG
STM32G0xx_LL_Driver

Modules

IWDG Private Constants
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
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STM32G0C1xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

Get Flags Defines

Flags defines which can be used with LL_IWDG_ReadReg function.

Prescaler Divider
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STM32G0C1xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Configuration
FLAG_Management
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STM32G0C1xx HAL User Manual: IWDG Exported Macros

Modules
IWDG Exported Macros
IWDG

Modules

Common Write and read registers Macros
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STM32G0C1xx HAL User Manual: Clocks Frequency Structure

Data Structures
Clocks Frequency Structure
RCC Exported Types

Data Structures

struct LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...
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STM32G0C1xx HAL User Manual: LPTIM

Modules
LPTIM
STM32G0xx_HAL_Driver

LPTIM HAL module driver. More...

Modules

LPTIM Exported Functions
LPTIM Private Functions
LPTIM Exported Types
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Private Types
LPTIM Private Variables
LPTIM Private Constants
LPTIM Private Macros

Detailed Description

LPTIM HAL module driver.

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STM32G0C1xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

LPTIM Clock Source
LPTIM Clock Prescaler
LPTIM Output Polarity
LPTIM Clock Sample Time
LPTIM Clock Polarity
LPTIM Trigger Source
LPTIM External Trigger Polarity
LPTIM Trigger Sample Time
LPTIM Updating Mode
LPTIM Counter Source
LPTIM Input1 Source
LPTIM Input2 Source
LPTIM Flags Definition
LPTIM Interrupts Definition
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STM32G0C1xx HAL User Manual: LPTIM Exported Functions

Modules
LPTIM Exported Functions
LPTIM

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

LPTIM Start-Stop operation functions

Start-Stop operation functions.

LPTIM Read operation functions

Read operation functions.

LPTIM IRQ handler and callbacks

LPTIM IRQ handler.

Peripheral State functions

Peripheral State functions.

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STM32G0C1xx HAL User Manual: LPTIM

Modules
LPTIM
STM32G0xx_LL_Driver

Modules

LPTIM Private Functions
LPTIM Private Macros
LPTIM Exported Init structure
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Exported Functions
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STM32G0C1xx HAL User Manual: LPTIM Exported Init structure

Data Structures
LPTIM Exported Init structure
LPTIM

Data Structures

struct LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...
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STM32G0C1xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

Get Flags Defines

Flags defines which can be used with LL_LPTIM_ReadReg function.

IT Defines

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Operating Mode
Update Mode
Counter Mode
Output Waveform Type
Output Polarity
Prescaler Value
Trigger Source
Trigger Filter
Trigger Polarity
Clock Source
Clock Filter
Clock Polarity
Encoder Mode
Input1 Source
Input2 Source
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STM32G0C1xx HAL User Manual: LPTIM Exported Functions

Modules
LPTIM Exported Functions
LPTIM

Modules

Initialisation and deinitialisation functions
LPTIM Configuration
Trigger Configuration
Clock Configuration
Encoder Mode
FLAG Management
Interrupt Management
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STM32G0C1xx HAL User Manual: LPTIM Exported Macros

Modules
LPTIM Exported Macros
LPTIM

Modules

Common Write and read registers Macros
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STM32G0C1xx HAL User Manual: LPUART

Modules
LPUART
STM32G0xx_LL_Driver

Modules

LPUART Private Variables
LPUART Private Constants
LPUART Private Macros
LPUART Exported Init structures
LPUART Exported Constants
LPUART Exported Macros
LPUART Exported Functions
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STM32G0C1xx HAL User Manual: LPUART Exported Init structures

Data Structures
LPUART Exported Init structures
LPUART

Data Structures

struct LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...
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STM32G0C1xx HAL User Manual: LPUART Exported Constants

Modules
LPUART Exported Constants
LPUART

Modules

Clear Flags Defines

Flags defines which can be used with LL_LPUART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_LPUART_ReadReg function.

IT Defines

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

FIFO Threshold
Direction
Parity Control
Wakeup
Datawidth
Clock Source Prescaler
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Address Length Detection
Hardware Control
Wakeup Activation
Driver Enable Polarity
DMA Register Data
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STM32G0C1xx HAL User Manual: LPUART Exported Functions

Modules
LPUART Exported Functions
LPUART

Modules

Configuration functions
Configuration functions related to Half Duplex feature
Configuration functions related to Driver Enable feature
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
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STM32G0C1xx HAL User Manual: LPUART Exported Macros

Modules
LPUART Exported Macros
LPUART

Modules

Common Write and read registers Macros
Helper Macros
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STM32G0C1xx HAL User Manual: PCD

Modules
PCD
STM32G0xx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Macros
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

PCD Private Constants

Detailed Description

PCD HAL module driver.

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STM32G0C1xx HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Speed
PCD PHY Module
PCD Error Code definition

PCD Error Code definition.

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STM32G0C1xx HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PCD Private Constants

Modules
PCD Private Constants
PCD

Modules

USB EXTI line interrupt
PCD EP0 MPS
PCD ENDP
PCD Endpoint Kind
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STM32G0C1xx HAL User Manual: PCDEx

Modules
PCDEx
STM32G0xx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCDEx Exported Functions

Detailed Description

PCD Extended HAL module driver.

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STM32G0C1xx HAL User Manual: PCDEx Exported Functions

Modules
PCDEx Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

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STM32G0C1xx HAL User Manual: PWR

Modules
PWR
STM32G0xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Private Defines
PWR Exported Types
PWR Exported Constants
PWR Exported Macros
Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
PWR Private Macros
PWR Exported Functions

Detailed Description

PWR HAL module driver.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

PWR WakeUp pins
PWR Low Power Mode Selection
PWR regulator mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR Status Flags

Elements values convention: 0000 00XX 000Y YYYYb.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Low Power modes configuration functions.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Extended Private Defines

Modules
PWR Extended Private Defines
PWREx

Modules

PWR PVD Mode Mask
PWREx Flag Setting Time Out Value
PWREx Gpio Pin Number
PWR PVM Mode Mask
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STM32G0C1xx HAL User Manual: PWR

Modules
PWR
STM32G0xx_LL_Driver

Modules

PWR Exported Constants
PWR Exported Macros
PWR Exported Functions
Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Clear Flags Defines

Flags defines which can be used with LL_PWR_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_PWR_ReadReg function.

REGU VOLTAGE
MODE PWR
PVDLEVEL
PVM_IP
WAKEUP
BATT CHARG RESISTOR
GPIO
GPIO BIT
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STM32G0C1xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Configuration
FLAG_Management
De-initialization function
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STM32G0C1xx HAL User Manual: PWR Exported Macros

Modules
PWR Exported Macros
PWR

Modules

Common Write and read registers Macros
Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWREx

Modules
PWREx
STM32G0xx_HAL_Driver

PWR Extended HAL module driver. More...

Modules

PWR Extended Private Defines
PWR Extended Exported Types
PWR Extended Exported Constants
PWR Extended Exported Functions
PWR Extended Exported Macros
PWR Extended Private Macros

Detailed Description

PWR Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:09 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Extended Exported Constants

Modules
PWR Extended Exported Constants
PWREx

Modules

Programmable Voltage Detection levels
PWR PVD interrupt and event mode
PWR PVD external interrupt line
PWR PVD event line
Peripheral Voltage Monitoring type
PWR PVM interrupt and event mode
PWR PVM external interrupt line
PWR PVM event line
PWR battery charging resistor selection
GPIO bit position

for I/O pull up/down setting in standby/shutdown mode

GPIO Port
Flash Power Down modes
PWR Regulator voltage scale
PWR Status Flags

Elements values convention: 0000 00XX 000Y YYYYb.

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STM32G0C1xx HAL User Manual: PWR Extended Exported Functions

Modules
PWR Extended Exported Functions
PWREx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: PWR Extended Exported Types

Data Structures
PWR Extended Exported Types
PWREx

Data Structures

struct | PWR_PVMTypeDef
PWR PVM configuration structure definition. More...
struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
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STM32G0C1xx HAL User Manual: RCC

Modules
RCC
STM32G0xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Constants
RCC Private Macros
RCC Private Variables
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros

Detailed Description

RCC HAL module driver.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Timeout Values
Oscillator Type
HSE Config
LSE Config
HSI Config
HSI Div
LSI Config
HSI48 Config
PLL Config
PLLM Clock Divider
PLLP Clock Divider
PLLQ Clock Divider
PLLR Clock Divider
PLL Clock Source
PLL Clock Output
System Clock Type
System Clock Source
System Clock Source Status
AHB Clock Source
APB Clock Source
RTC Clock Source
MCO Index
MCO1 Clock Source
MCO1 Clock Prescaler
MCO2 Clock Source
MCO2 Clock Prescaler
Interrupts
Flags

Elements values convention: XXXYYYYYb.

LSE Drive Configuration
Reset Flag
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STM32G0C1xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

AHB Peripheral Clock Enable Disable

Enable or disable the AHB peripheral clock.

IOPORT Clock Enable Disable

Enable or disable the IO Ports clock.

APB1 Peripheral Clock Enable Disable

Enable or disable the APB1 peripheral clock.

APB2 Peripheral Clock Enable Disable

Enable or disable the APB2 peripheral clock.

AHB Peripheral Clock Enabled or Disabled Status

Check whether the AHB peripheral clock is enabled or not.

IOPORT Clock Enabled or Disabled Status

Check whether the IO Port clock is enabled or not.

APB1 Peripheral Clock Enabled or Disabled Status

Check whether the APB1 peripheral clock is enabled or not.

APB2 Peripheral Clock Enabled or Disabled Status

Check whether the APB2 peripheral clock is enabled or not.

AHB Peripheral Force Release Reset

Force or release AHB1 peripheral reset.

IOPORT Force Release Reset

Force or release IO Port reset.

APB1 Peripheral Force Release Reset

Force or release APB1 peripheral reset.

APB2 Peripheral Force Release Reset

Force or release APB2 peripheral reset.

AHB Peripherals Clock Sleep Enable Disable

Enable or disable the AHB peripherals clock during Low Power (Sleep) mode.

IOPORT Clock Sleep Enable Disable

Enable or disable the IOPORT clock during Low Power (Sleep) mode.

APB1 Peripheral Clock Sleep Enable Disable

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

APB2 Peripheral Clock Sleep Enable Disable

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

AHB Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.

IOPORT Clock Sleep Enabled or Disabled Status

Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not.

APB1 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

APB2 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

RCC Backup Domain Reset
RCC RTC Clock Configuration
RCC Clock Configuration
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB buses clock configuration structure definition. More...
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STM32G0C1xx HAL User Manual: RCC

Modules
RCC
STM32G0xx_LL_Driver

Modules

RCC Private functions
RCC Private Variables
RCC Private Macros
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Exported Functions
Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Values adaptation

Defines used to adapt values of different oscillators.

Clear Flags Defines

Flags defines which can be used with LL_RCC_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_RCC_ReadReg function.

IT Defines

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

LSE oscillator drive capability
LSCO Selection
System clock switch
System clock switch status
AHB prescaler
APB low-speed prescaler (APB1)
HSI division factor
MCO1 SOURCE selection
MCO1 prescaler
MCO2 SOURCE selection
MCO2 prescaler
Peripheral clock frequency
Peripheral USART clock source selection
Peripheral LPUART clock source selection
Peripheral I2C clock source selection
Peripheral I2S clock source selection
Peripheral TIM clock source selection
Peripheral LPTIM clock source selection
Peripheral CEC clock source selection
Peripheral FDCAN clock source selection
Peripheral RNG clock source selection
Peripheral RNG clock division factor
Peripheral USB clock source selection
Peripheral ADC clock source selection
Peripheral USARTx get clock source
Peripheral LPUART get clock source
Peripheral I2C get clock source
Peripheral I2S get clock source
Peripheral TIMx get clock source
Peripheral LPTIM get clock source
Peripheral CEC get clock source
Peripheral FDCAN get clock source
Peripheral USB get clock source
Peripheral RNG get clock source
Peripheral RNG get clock division factor
Peripheral ADC get clock source
RTC clock source selection
PLL entry clock source
PLL division factor (PLLM)
PLL division factor (PLLR)
PLL division factor (PLLP)
PLL division factor (PLLQ)
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STM32G0C1xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

HSE
HSI
HSI48
LSE
LSI
LSCO
System
MCO1
MCO2
Peripheral Clock Source
RTC
PLL
FLAG Management
IT Management
De-initialization function
Get system and peripherals clocks frequency functions

Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks and different peripheral clocks available on the device.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

Common Write and read registers Macros
Calculate frequencies
Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCC Exported Types

Modules
RCC Exported Types
RCC

Modules

Clocks Frequency Structure
Generated on Mon Jun 6 2022 10:29:15 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx

Modules
RCCEx
STM32G0xx_HAL_Driver

RCC Extended HAL module driver. More...

Modules

RCCEx Private Constants
RCCEx Exported Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Exported Macros
RCCEx CRS Extended Features
RCCEx Private Macros

Detailed Description

RCC Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RCCEx Exported Constants

Modules
RCCEx Exported Constants
RCCEx

Modules

Low Speed Clock Source
Periph Clock Selection
RCC USART1 Clock Source
RCC USART2 Clock Source
RCC USART3 Clock Source
RCC LPUART1 Clock Source
RCC LPUART2 Clock Source
RCC I2C1 Clock Source
RCC I2C2 Clock Source
RCC I2S1 Clock Source
RCC I2S2 Clock Source
RCC LPTIM1 Clock Source
RCC LPTIM2 Clock Source
RCC RNG Clock Source
RCC RNG Division factor
RCC FDCAN Clock Source
USB Clock Source
RCC ADC Clock Source
RCC CEC Clock Source
RCC TIM1 Clock Source
RCC TIM15 Clock Source
RCCEx CRS Status
RCCEx CRS SynchroSource
RCCEx CRS SynchroDivider
RCCEx CRS SynchroPolarity
RCCEx CRS ReloadValueDefault
RCCEx CRS ErrorLimitDefault
RCCEx CRS HSI48CalibrationDefault
RCCEx CRS FreqErrorDirection
RCCEx CRS Interrupt Sources
RCCEx CRS Flags
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STM32G0C1xx HAL User Manual: RCCEx Exported Functions

Modules
RCCEx Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended Clock management functions

Extended Clock management functions.

Extended Clock Recovery System Control functions

Extended Clock Recovery System Control functions.

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STM32G0C1xx HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...
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STM32G0C1xx HAL User Manual: RNG

Modules
RNG
STM32G0xx_HAL_Driver

RNG HAL module driver. More...

Modules

RNG Private Constants
RNG Exported Types
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG Private Macros

Detailed Description

RNG HAL module driver.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

RNG Interrupt definition
RNG Flag definition
RNG Clock Error Detection
RNG Error Definition
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STM32G0C1xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

Initialization and configuration functions

Initialization and configuration functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:10 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Exported Types

Modules
RNG Exported Types
RNG

Modules

RNG Init Structure definition
RNG State Structure definition
RNG Handle Structure definition
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STM32G0C1xx HAL User Manual: RNG Init Structure definition

Data Structures
RNG Init Structure definition
RNG Exported Types

Data Structures

struct RNG_InitTypeDef
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STM32G0C1xx HAL User Manual: RNG

Modules
RNG
STM32G0xx_LL_Driver

Modules

RNG Private Macros
RNG Exported Init structures
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
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STM32G0C1xx HAL User Manual: RNG Exported Init structures

Data Structures
RNG Exported Init structures
RNG

Data Structures

struct LL_RNG_InitTypeDef
LL RNG Init Structure Definition. More...
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STM32G0C1xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

Clock Error Detection
Get Flags Defines

Flags defines which can be used with LL_RNG_ReadReg function.

IT Defines

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

RNG Configuration functions
FLAG Management
IT Management
Data Management
Initialization and de-initialization functions
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STM32G0C1xx HAL User Manual: RNG Exported Macros

Modules
RNG Exported Macros
RNG

Modules

Common Write and read registers Macros
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STM32G0C1xx HAL User Manual: RTC

Modules
RTC
STM32G0xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions
RTC Private Constants
RTC Private Macros
RTC Private Functions

Detailed Description

RTC HAL module driver.

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STM32G0C1xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats
RTCEx Output Selection Definition
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC Output Pull-Up ALARM OUT
RTC Output ALARM OUT Remap
RTC AM PM Definitions
RTC DayLightSaving Definitions
RTC StoreOperation Definitions
RTC Input Parameter Format Definitions
RTC Month Date Definitions
RTC WeekDay Definitions
RTC AlarmDateWeekDay Definitions
RTC AlarmMask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
RTC Flags Definitions

Elements values convention: 000000XX000YYYYYb.

RTC Clear Flags Definitions
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STM32G0C1xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC

Modules
RTC
STM32G0xx_LL_Driver

Modules

RTC Private Constants
RTC Private Macros
RTC Exported Init structure
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions
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STM32G0C1xx HAL User Manual: RTC Exported Init structure

Data Structures
RTC Exported Init structure
RTC

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...
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STM32G0C1xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

FORMAT
RTC Alarm A Date WeekDay
RTC Alarm B Date WeekDay
Get Flags Defines

Flags defines which can be used with LL_RTC_ReadReg function.

IT Defines

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

WEEK DAY
MONTH
HOUR FORMAT
ALARM OUTPUT
ALARM OUTPUT TYPE
OUTPUT POLARITY PIN
TIME FORMAT
SHIFT SECOND
ALARMA MASK
ALARMA TIME FORMAT
ALARMB MASK
ALARMB TIME FORMAT
TIMESTAMP EDGE
TIMESTAMP TIME FORMAT
TAMPER
TAMPER MASK
TAMPER NO ERASE
TAMPER DURATION
TAMPER FILTER
TAMPER SAMPLING FREQUENCY DIVIDER
TAMPER ACTIVE LEVEL
INTERNAL TAMPER
BACKUP
WAKEUP CLOCK DIV
Calibration output
Calibration pulse insertion
Calibration period
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STM32G0C1xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Configuration
Time
Date
ALARMA
ALARMB
Timestamp
Tamper
Internal Tamper
Wakeup
Backup_Registers
Calibration
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Exported Macros

Modules
RTC Exported Macros
RTC

Modules

Common Write and read registers Macros
Convert helper Macros
Date helper Macros
Time helper Macros
Generated on Mon Jun 6 2022 10:29:16 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
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STM32G0C1xx HAL User Manual: RTCEx

Modules
RTCEx
STM32G0xx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros
RTCEx Exported Functions
RTCEx Private Constants
RTCEx Private Macros

Detailed Description

RTC Extended HAL module driver.

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STM32G0C1xx HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

RTCEx Time Stamp Edges definition
RTCEx TimeStamp Pin Selection
RTCEx Wakeup Timer Definitions
RTCEx Smooth calib period Definitions
RTCEx Smooth calib Plus pulses Definitions
RTCEx Calib Output selection Definitions
RTCEx Add 1 Second Parameter Definitions
RTCEx Tamper Pins Definition
RTCEx Internal Tamper Pins Definition
RTCEx Tamper Trigger
RTCEx Tamper MaskFlag
RTCEx Tamper EraseBackUp
RTCEx Tamper Filter
RTCEx Tamper Sampling Frequencies
RTCEx Tamper Pin Precharge Duration
RTCEx Tamper Pull UP
RTCEx Tamper TimeStamp On Tamper Detection Definitions
RTCEx Internal Tamper Interrupt
RTCEx Flags
RTCEx Backup Registers Definition
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STM32G0C1xx HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

Extended RTC TimeStamp functions

RTC TimeStamp and Tamper functions.

Extended RTC Wake-up functions

RTC Wake-up functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended features functions

Extended features functions.

Extended RTC Tamper functions

Extended RTC Tamper functions.

Extended RTC Backup register functions

Extended RTC Backup register functions.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: RTCEx Exported Types

Modules
RTCEx Exported Types
RTCEx

Modules

RTCEx Tamper structure definition
RTCEx Internal Tamper structure definition
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STM32G0C1xx HAL User Manual: RTCEx Internal Tamper structure definition

Data Structures
RTCEx Internal Tamper structure definition
RTCEx Exported Types

Data Structures

struct RTC_InternalTamperTypeDef
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STM32G0C1xx HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Private macros to check input parameters
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STM32G0C1xx HAL User Manual: RTCEx Tamper structure definition

Data Structures
RTCEx Tamper structure definition
RTCEx Exported Types

Data Structures

struct RTC_TamperTypeDef
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STM32G0C1xx HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32G0xx_HAL_Driver

HAL SMARTCARD module driver. More...

Modules

SMARTCARD Private Constants
SMARTCARD Exported Functions
SMARTCARD Private Functions
SMARTCARD Exported Types
SMARTCARD Exported Constants
SMARTCARD Exported Macros
SMARTCARD Private Macros

Detailed Description

HAL SMARTCARD module driver.

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STM32G0C1xx HAL User Manual: SMARTCARD Exported Constants

Modules
SMARTCARD Exported Constants
SMARTCARD

Modules

SMARTCARD State Code Definition
SMARTCARD Error Code Definition
SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Transfer Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD One Bit Sampling Method
SMARTCARD NACK Enable
SMARTCARD Timeout Enable
SMARTCARD Clock Prescaler
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD advanced feature Binary Data inversion
SMARTCARD advanced feature RX TX pins swap
SMARTCARD advanced feature Overrun Disable
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD advanced feature MSB first
SMARTCARD Request Parameters
SMARTCARD interruptions flags mask
Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARD Exported Functions

Modules
SMARTCARD Exported Functions
SMARTCARD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMARTCARDEx

Modules
SMARTCARDEx
STM32G0xx_HAL_Driver

SMARTCARD Extended HAL module driver. More...

Modules

SMARTCARD Extended Private Constants
SMARTCARD Extended Exported Functions
SMARTCARD Extended Private Functions
SMARTCARD Extended Private Macros
SMARTCARD Extended Exported Constants

Detailed Description

SMARTCARD Extended HAL module driver.

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STM32G0C1xx HAL User Manual: SMARTCARD Extended Exported Constants

Modules
SMARTCARD Extended Exported Constants
SMARTCARDEx

Modules

SMARTCARD Transmission Completion Indication
SMARTCARD advanced feature initialization type
SMARTCARD FIFO mode

SMARTCARD FIFO mode.

SMARTCARD TXFIFO threshold level

SMARTCARD TXFIFO level.

SMARTCARD RXFIFO threshold level

SMARTCARD RXFIFO level.

SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

SMARTCARD Interruption Clear Flags
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STM32G0C1xx HAL User Manual: SMARTCARD Extended Exported Functions

Modules
SMARTCARD Extended Exported Functions
SMARTCARDEx

Modules

Extended Peripheral Control functions

Extended control functions.

Extended Peripheral IO operation functions

SMARTCARD Transmit and Receive functions.

Extended Peripheral FIFO Control functions

SMARTCARD control functions.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS

Modules
SMBUS
STM32G0xx_HAL_Driver

SMBUS HAL module driver. More...

Modules

SMBUS Private Constants
SMBUS Exported Functions
SMBUS Exported Types
SMBUS Exported Constants
SMBUS Exported Macros
SMBUS Private Macros
SMBUS Private Functions

Data transfers Private functions.

Detailed Description

SMBUS HAL module driver.

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STM32G0C1xx HAL User Manual: SMBUS Configuration Structure definition

Data Structures
SMBUS Configuration Structure definition
SMBUS Exported Types

SMBUS Configuration Structure definition. More...

Data Structures

struct SMBUS_InitTypeDef

Detailed Description

SMBUS Configuration Structure definition.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Exported Constants

Modules
SMBUS Exported Constants
SMBUS

Modules

SMBUS Analog Filter
SMBUS addressing mode
SMBUS dual addressing mode
SMBUS ownaddress2 masks
SMBUS general call addressing mode
SMBUS nostretch mode
SMBUS packet error check mode
SMBUS peripheral mode
SMBUS ReloadEndMode definition
SMBUS StartStopMode definition
SMBUS XferOptions definition
SMBUS Interrupt configuration definition

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

SMBUS Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

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STM32G0C1xx HAL User Manual: SMBUS Exported Functions

Modules
SMBUS Exported Functions
SMBUS

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

SMBUS Private Functions

Data transfers Private functions.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Exported Types

Modules
SMBUS Exported Types
SMBUS

Modules

SMBUS Configuration Structure definition

SMBUS Configuration Structure definition.

HAL state definition

HAL State definition.

SMBUS Error Code definition

SMBUS Error Code definition.

SMBUS handle Structure definition

SMBUS handle Structure definition.

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STM32G0C1xx HAL User Manual: SMBUSEx

Modules
SMBUSEx
STM32G0xx_HAL_Driver

SMBUS Extended HAL module driver. More...

Modules

SMBUS Extended Exported Functions
SMBUS Extended Exported Constants
SMBUS Extended Exported Macros
SMBUS Extended Private Constants
SMBUS Extended Private Macros
SMBUS Extended Private Functions

Detailed Description

SMBUS Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SMBUS Extended Exported Constants

Modules
SMBUS Extended Exported Constants
SMBUSEx

Modules

SMBUS Extended Fast Mode Plus
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STM32G0C1xx HAL User Manual: SMBUS Extended Exported Functions

Modules
SMBUS Extended Exported Functions
SMBUSEx

Modules

WakeUp Mode Functions

WakeUp Mode Functions.

Fast Mode Plus Functions

Fast Mode Plus Functions.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI

Modules
SPI
STM32G0xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Private Functions

Private functions.

SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros

Detailed Description

SPI HAL module driver.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI Error Code
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select Management
SPI NSS Pulse Mode
SPI BaudRate Prescaler
SPI MSB LSB Transmission
SPI TI Mode
SPI CRC Calculation
SPI CRC Length

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

SPI FIFO Reception Threshold

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits).

SPI Interrupt Definition
SPI Flags Definition
SPI Transmission FIFO Status Level
SPI Reception FIFO Status Level
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STM32G0C1xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

Generated on Mon Jun 6 2022 10:29:11 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI

Modules
SPI
STM32G0xx_LL_Driver

Modules

SPI Private Constants
SPI Private Macros
SPI Exported Init structure
SPI Exported Constants
SPI Exported Macros
SPI Exported Functions
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Exported Init structure

Data Structures
SPI Exported Init structure
SPI

Data Structures

struct LL_SPI_InitTypeDef
SPI Init structures definition. More...
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STM32G0C1xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

Get Flags Defines

Flags defines which can be used with LL_SPI_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Operation Mode
Serial Protocol
Clock Phase
Clock Polarity
Baud Rate Prescaler
Transmission Bit Order
Transfer Mode
Slave Select Pin Mode
Datawidth
CRC Calculation
CRC Length
RX FIFO Threshold
RX FIFO Level
TX FIFO Level
DMA Parity
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Configuration
CRC Management
Slave Select Pin Management
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPI Exported Macros

Modules
SPI Exported Macros
SPI

Modules

Common Write and read registers Macros
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STM32G0C1xx HAL User Manual: SPIEx

Modules
SPIEx
STM32G0xx_HAL_Driver

SPI Extended HAL module driver. More...

Modules

SPIEx Private Constants
SPIEx Exported Functions

Detailed Description

SPI Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SPIEx Exported Functions

Modules
SPIEx Exported Functions
SPIEx

Modules

IO operation functions

Data transfers functions.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: STM32G0xx_HAL_Driver

Modules
STM32G0xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC HAL module driver.

ADCEx

ADC Extended HAL module driver.

CEC

HAL CEC module driver.

COMP

COMP HAL module driver.

CORTEX

CORTEX HAL module driver.

CRC

CRC HAL module driver.

CRCEx

CRC Extended HAL module driver.

CRYP

CRYP HAL module driver.

CRYPEx

CRYP Extension HAL module driver.

DAC

DAC driver modules.

DACEx

DAC Extended HAL module driver.

DMA

DMA HAL module driver.

DMAEx

DMA Extended HAL module driver.

EXTI

EXTI HAL module driver.

FDCAN

FDCAN HAL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FLASH Extended HAL module driver.

GPIO

GPIO HAL module driver.

GPIOEx

GPIO Extended HAL module driver.

HCD

HCD HAL module driver.

I2C

I2C HAL module driver.

I2CEx

I2C Extended HAL module driver.

I2S

I2S HAL module driver.

IRDA

HAL IRDA module driver.

IRDAEx

IRDA Extended HAL module driver.

IWDG

IWDG HAL module driver.

LPTIM

LPTIM HAL module driver.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PWR

PWR HAL module driver.

PWREx

PWR Extended HAL module driver.

RCC

RCC HAL module driver.

RCCEx

RCC Extended HAL module driver.

RNG

RNG HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SMARTCARD

HAL SMARTCARD module driver.

SMARTCARDEx

SMARTCARD Extended HAL module driver.

SMBUS

SMBUS HAL module driver.

SMBUSEx

SMBUS Extended HAL module driver.

SPI

SPI HAL module driver.

SPIEx

SPI Extended HAL module driver.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

UART

HAL UART module driver.

UARTEx

UART Extended HAL module driver.

USART

HAL USART Synchronous module driver.

USARTEx

USART Extended HAL module driver.

WWDG

WWDG HAL module driver.

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STM32G0C1xx HAL User Manual: STM32G0xx_LL_Driver

Modules
STM32G0xx_LL_Driver

Modules

ADC
BUS
COMP
CORTEX
CRC
CRS
DAC
DMA
DMAMUX
EXTI
GPIO
I2C
IWDG
LPTIM
LPUART
PWR
RCC
RNG
RTC
SPI
I2S
SYSTEM
TIM
UCPD
USART
UTILS
WWDG
Generated on Mon Jun 6 2022 10:29:19 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSCFG Exported Constants

Modules
SYSCFG Exported Constants
HAL Exported Constants

Modules

Boot Mode
Break
Clamping Diode
Pin remapping
IR Modulation Envelope signal selection
IR output polarity selection
VREFBUF Voltage Scale
VREFBUF High Impedance
Fast mode Plus on GPIO
Fast mode Plus driving capability activation for I2Cx
SYSCFG Dead Battery feature configuration
HAL ISR Wrapper

ISR Wrapper.

Generated on Mon Jun 6 2022 10:29:06 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSTEM

Modules
SYSTEM
STM32G0xx_LL_Driver

Modules

SYSTEM Private Constants
SYSTEM Exported Constants
SYSTEM Exported Functions
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STM32G0C1xx HAL User Manual: SYSTEM Exported Constants

Modules
SYSTEM Exported Constants
SYSTEM

Modules

SYSCFG REMAP
SYSCFG PIN RMP
SYSCFG IR Modulation
SYSCFG IR Polarity
SYSCFG I/O analog switch voltage booster enable
SYSCFG UCPD Dead Battery feature Disable
SYSCFG I2C FASTMODEPLUS
SYSCFG TIMER BREAK
SYSCFG CLAMPING DIODE
DBGMCU APB1 GRP1 STOP IP
DBGMCU APB2 GRP1 STOP IP
VREFBUF VOLTAGE
FLASH LATENCY
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: SYSTEM Exported Functions

Modules
SYSTEM Exported Functions
SYSTEM

Modules

SYSCFG
DBGMCU
VREFBUF
FLASH
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STM32G0C1xx HAL User Manual: TIM

Modules
TIM
STM32G0xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Private Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Constants
TIM Private Macros

Detailed Description

TIM HAL module driver.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Clear Input Source
TIM DMA Base Address
TIM Event Source
TIM Input Channel polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Update Interrupt Flag Remap
TIM Clock Division
TIM Output Compare State
TIM Auto-Reload Preload
TIM Output Fast State
TIM Complementary Output Compare State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Complementary Output Compare Idle State
TIM Input Capture Polarity
TIM Encoder Input Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM interrupt Definition
TIM Commutation Source
TIM DMA Sources
CCx DMA request selection
TIM Flag Definition
TIM Channel
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR OffState Selection for Run mode state
TIM OSSI OffState Selection for Idle mode state
TIM Lock level
TIM Break Input Enable
TIM Break Input Polarity
TIM Break Input Alternate Function Mode
TIM Break input 2 Enable
TIM Break Input 2 Polarity
TIM Break2 Input Alternate Function Mode
TIM Automatic Output Enable
TIM Group Channel 5 and Channel 1, 2 or 3
TIM Master Mode Selection
TIM Master Mode Selection 2 (TRGO2)
TIM Master/Slave Mode
TIM Slave mode
TIM Output Compare and PWM Modes
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Input Selection
TIM DMA Burst Length
TIM DMA Handle Index
TIM Capture/Compare Channel State
TIM Break System
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STM32G0C1xx HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

TIM Time Base functions

Time Base functions.

TIM Output Compare functions

TIM Output Compare functions.

TIM PWM functions

TIM PWM functions.

TIM Input Capture functions

TIM Input Capture functions.

TIM One Pulse functions

TIM One Pulse functions.

TIM Encoder functions

TIM Encoder functions.

TIM IRQ handler management

TIM IRQ handler management.

TIM Peripheral Control functions

TIM Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

TIM Peripheral State functions

TIM Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM

Modules
TIM
STM32G0xx_LL_Driver

Modules

TIM Private Functions

Private functions.

TIM Private Variables
TIM Private Constants
TIM Private Macros
TIM Exported Init structure
TIM Exported Constants
TIM Exported Macros
TIM Exported Functions
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STM32G0C1xx HAL User Manual: TIM Exported Init structure

Data Structures
TIM Exported Init structure
TIM

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

Get Flags Defines

Flags defines which can be used with LL_TIM_ReadReg function.

Break Enable
Break2 Enable
Automatic output enable
IT Defines

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Update Source
One Pulse Mode
Counter Mode
Clock Division
Counter Direction
Capture Compare Update Source
Capture Compare DMA Request
Lock Level
Channel
Output Configuration State
Output Configuration Mode
Output Configuration Polarity
Output Configuration Idle State
GROUPCH5
Active Input Selection
Input Configuration Prescaler
Input Configuration Filter
Input Configuration Polarity
Clock Source
Encoder Mode
Trigger Output
Trigger Output 2
Slave Mode
Trigger Selection
External Trigger Polarity
External Trigger Prescaler
External Trigger Filter
External Trigger Source
break polarity
break filter
BREAK2 POLARITY
BREAK2 FILTER
OSSI
OSSR
BREAK INPUT
BKIN SOURCE
BKIN POLARITY
BREAK AF MODE
BREAK2 AF MODE
DMA Burst Base Address
DMA Burst Length
TIM1 Timer Input Ch1 Remap
TIM1 Timer Input Ch2 Remap
TIM1 Timer Input Ch3 Remap
TIM2 Timer Input Ch1 Remap
TIM2 Timer Input Ch2 Remap
TIM2 Timer Input Ch3 Remap
TIM3 Timer Input Ch1 Remap
TIM3 Timer Input Ch2 Remap
TIM3 Timer Input Ch3 Remap
TIM4 Timer Input Ch1 Remap
TIM4 Timer Input Ch2 Remap
TIM4 Timer Input Ch3 Remap
TIM14 Timer Input Ch1 Remap
TIM15 Timer Input Ch1 Remap
TIM15 Timer Input Ch2 Remap
TIM16 Timer Input Ch1 Remap
TIM17 Timer Input Ch1 Remap
OCREF clear input selection
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base configuration
Capture Compare configuration
Output channel configuration
Input channel configuration
Counter clock selection
Timer synchronisation configuration
Break function configuration
DMA burst mode configuration
Timer input remapping
OCREF_Clear_Management
FLAG-Management
IT-Management
DMA Management
EVENT-Management
Initialisation and deinitialisation functions
Generated on Mon Jun 6 2022 10:29:17 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Exported Macros

Modules
TIM Exported Macros
TIM

Modules

Common Write and read registers Macros
Exported_Macros
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STM32G0C1xx HAL User Manual: TIMEx

Modules
TIMEx
STM32G0xx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIM Extended Private Constants
TIM Extended Exported Functions
TIM Extended Private Functions
TIM Extended Exported Types
TIM Extended Exported Constants
TIM Extended Exported Macros
TIM Extended Private Macros

Detailed Description

TIM Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: TIM Extended Exported Constants

Modules
TIM Extended Exported Constants
TIMEx

Modules

TIM Extended Remapping
TIM Extended Break input
TIM Extended Break input source
TIM Extended Break input source enabling
TIM Extended Break input polarity
TIM Extended Timer input selection
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STM32G0C1xx HAL User Manual: TIM Extended Exported Functions

Modules
TIM Extended Exported Functions
TIMEx

Modules

Extended Timer Hall Sensor functions

Timer Hall Sensor functions.

Extended Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Extended Timer Complementary PWM functions

Timer Complementary PWM functions.

Extended Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Extended Peripheral Control functions

Peripheral Control functions.

Extended Callbacks functions

Extended Callbacks functions.

Extended Peripheral State functions

Extended Peripheral State functions.

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STM32G0C1xx HAL User Manual: TIM Extended Exported Types

Data Structures
TIM Extended Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...
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STM32G0C1xx HAL User Manual: UART

Modules
UART
STM32G0xx_HAL_Driver

HAL UART module driver. More...

Modules

UART Private Constants
UART Exported Functions
UART Private Functions
UART Exported Types
UART Exported Constants
UART Exported Macros
UART Private Macros
UART Private variables

Detailed Description

HAL UART module driver.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UART Exported Constants

Modules
UART Exported Constants
UART

Modules

UART State Code Definition
UART Error Definition
UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART One Bit Sampling Method
UART Clock Prescaler
UART Advanced Feature AutoBaud Rate Mode
UART Receiver Timeout
UART Local Interconnection Network mode
UART LIN Break Detection
UART DMA Tx
UART DMA Rx
UART Half Duplex Selection
UART WakeUp Methods
UART Request Parameters
UART Advanced Feature Initialization Type
UART Advanced Feature TX Pin Active Level Inversion
UART Advanced Feature RX Pin Active Level Inversion
UART Advanced Feature Binary Data Inversion
UART Advanced Feature RX TX Pins Swap
UART Advanced Feature Overrun Disable
UART Advanced Feature Auto BaudRate Enable
UART Advanced Feature DMA Disable On Rx Error
UART Advanced Feature MSB First
UART Advanced Feature Stop Mode Enable
UART Advanced Feature Mute Mode Enable
UART Address-matching LSB Position In CR2 Register
UART WakeUp From Stop Selection
UART DriverEnable Polarity
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
UART Status Flags

Elements values convention: 0xXXXX.

UART Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

UART Interruption Clear Flags
UART Reception type values
UART RxEvent type values
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STM32G0C1xx HAL User Manual: UART Exported Functions

Modules
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit/Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Error functions

UART Peripheral State functions.

Generated on Mon Jun 6 2022 10:29:12 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx

Modules
UARTEx
STM32G0xx_HAL_Driver

UART Extended HAL module driver. More...

Modules

UARTEx Private Constants
UARTEx Private Functions
UARTEx Exported Functions
UARTEx Exported Types
UARTEx Exported Constants
UARTEx Private Macros

Detailed Description

UART Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx Exported Constants

Modules
UARTEx Exported Constants
UARTEx

Modules

UARTEx Word Length
UARTEx WakeUp Address Length
UARTEx FIFO mode

UART FIFO mode.

UARTEx TXFIFO threshold level

UART TXFIFO threshold level.

UARTEx RXFIFO threshold level

UART RXFIFO threshold level.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UARTEx Exported Functions

Modules
UARTEx Exported Functions
UARTEx

Modules

Initialization and de-initialization functions

Extended Initialization and Configuration Functions.

IO operation functions

Extended functions.

Peripheral Control functions

Extended Peripheral Control functions.

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STM32G0C1xx HAL User Manual: UARTEx Exported Types

Data Structures
UARTEx Exported Types
UARTEx

Data Structures

struct UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...
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STM32G0C1xx HAL User Manual: UCPD

Modules
UCPD
STM32G0xx_LL_Driver

Modules

UCPD Private Constants
UCPD Private Macros
UCPD Exported Init structure
UCPD Exported Constants
UCPD Exported Macros
UCPD Exported Functions
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Configuration

Modules
Configuration
UCPD Exported Functions

Modules

CFG1 register
CFG2 register
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STM32G0C1xx HAL User Manual: UCPD Exported Init structure

Data Structures
UCPD Exported Init structure
UCPD

Data Structures

struct LL_UCPD_InitTypeDef
UCPD Init structures definition. More...
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STM32G0C1xx HAL User Manual: UCPD Exported Constants

Modules
UCPD Exported Constants
UCPD

Modules

Get Flags Defines

Flags defines which can be used with LL_ucpd_ReadReg function.

IT Defines

IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions.

Ordered sets value

definition of the usual Ordered sets

Role Mode
Resistor value
ordered set configuration
CCx event
prescaler for UCPDCLK
CC pin enable
CC pin selection
Receiver mode
Type of Tx packet
Rx ordered set code detected
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STM32G0C1xx HAL User Manual: UCPD Exported Functions

Modules
UCPD Exported Functions
UCPD

Modules

Configuration
CR register
Interrupt Management
Interrupt Clear
FLAG Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UCPD Exported Macros

Modules
UCPD Exported Macros
UCPD

Modules

Common Write and read registers Macros
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STM32G0C1xx HAL User Manual: USART

Modules
USART
STM32G0xx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Private Constants
USART Exported Functions
USART Private Functions
USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Macros

Detailed Description

HAL USART Synchronous module driver.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Error Definition
USART Number of Stop Bits
USART Parity
USART Mode
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART Clock Prescaler
USART Request Parameters
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

USART Interruption Clear Flags
USART Interruption Flags Mask
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STM32G0C1xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Error functions

USART Peripheral State and Error functions.

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STM32G0C1xx HAL User Manual: USART

Modules
USART
STM32G0xx_LL_Driver

Modules

USART Private Variables
USART Private Macros
USART Exported Init structures
USART Exported Constants
USART Exported Macros
USART Exported Functions
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STM32G0C1xx HAL User Manual: USART Exported Init structures

Data Structures
USART Exported Init structures
USART

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...
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STM32G0C1xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

Clear Flags Defines

Flags defines which can be used with LL_USART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_USART_ReadReg function.

IT Defines

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

FIFO Threshold
Communication Direction
Parity Control
Wakeup
Datawidth
Oversampling
Clock Signal
Last Clock Pulse
Clock Phase
Clock Polarity
Clock Source Prescaler
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Autobaud Detection
Address Length Detection
Hardware Control
Wakeup Activation
IrDA Power
LIN Break Detection Length
Driver Enable Polarity
DMA Register Data
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STM32G0C1xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Configuration functions
Configuration functions related to Irda feature
Configuration functions related to Smartcard feature
Configuration functions related to Half Duplex feature
Configuration functions related to SPI Slave feature
Configuration functions related to LIN feature
Configuration functions related to Driver Enable feature
Advanced Configurations services
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USART Exported Macros

Modules
USART Exported Macros
USART

Modules

Common Write and read registers Macros
Exported_Macros_Helper
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx

Modules
USARTEx
STM32G0xx_HAL_Driver

USART Extended HAL module driver. More...

Modules

USARTEx Private Constants
USARTEx Private Functions
USARTEx Exported Functions
USARTEx Exported Constants
USARTEx Private Macros

Detailed Description

USART Extended HAL module driver.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx Exported Constants

Modules
USARTEx Exported Constants
USARTEx

Modules

USARTEx Word Length
USARTEx Slave Select Management
USARTEx Synchronous Slave mode enable

USART SLAVE mode.

USARTEx FIFO mode

USART FIFO mode.

USARTEx TXFIFO threshold level

USART TXFIFO level.

USARTEx RXFIFO threshold level

USART RXFIFO level.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: USARTEx Exported Functions

Modules
USARTEx Exported Functions
USARTEx

Modules

IO operation functions

Extended USART Transmit/Receive functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UTILS

Modules
UTILS
STM32G0xx_LL_Driver

Modules

UTILS Private functions
UTILS Private Constants
UTILS Private Macros
UTILS Exported structures
UTILS Exported Constants
UTILS Exported Functions
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UTILS Exported structures

Data Structures
UTILS Exported structures
UTILS

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UTILS Exported Constants

Modules
UTILS Exported Constants
UTILS

Modules

HSE Bypass activation
PACKAGE TYPE
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: UTILS Exported Functions

Modules
UTILS Exported Functions
UTILS

Modules

DEVICE ELECTRONIC SIGNATURE
DELAY
SYSTEM

System Configuration functions.

Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG

Modules
WWDG
STM32G0xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Private Macros
WWDG Exported Macros

Detailed Description

WWDG HAL module driver.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
WWDG Early Wakeup Interrupt Mode
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STM32G0C1xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Generated on Mon Jun 6 2022 10:29:13 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG

Modules
WWDG
STM32G0xx_LL_Driver

Modules

WWDG Exported Constants
WWDG Exported Macros
WWDG Exported Functions
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

IT Defines

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

PRESCALER
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Configuration
FLAG_Management
IT_Management
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STM32G0C1xx HAL User Manual: WWDG Exported Macros

Modules
WWDG Exported Macros
WWDG

Modules

Common Write and read registers macros
Generated on Mon Jun 6 2022 10:29:18 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: Modules

Modules
Here is a list of all modules:
  • STM32G0xx_HAL_Driver
    • HAL
      • HAL Private Constants
      • HAL Exported Variables
      • Tick Frequency
      • HAL Exported Constants
        • SYSCFG Exported Constants
          • Boot Mode
          • Break
          • Clamping Diode
          • Pin remapping
          • IR Modulation Envelope signal selection
          • IR output polarity selection
          • VREFBUF Voltage Scale
          • VREFBUF High Impedance
          • Fast mode Plus on GPIO
          • Fast mode Plus driving capability activation for I2Cx
          • SYSCFG Dead Battery feature configuration
          • HAL ISR Wrapper
      • HAL Exported Macros
        • DBG Exported Macros
        • SYSCFG Exported Macros
      • SYSCFG Private Macros
      • HAL Private Macros
      • HAL Exported Functions
        • HAL Initialization and Configuration functions
        • HAL Control functions
        • DBGMCU Control functions
        • SYSCFG configuration functions
        • HAL Exported Variables
    • ADC
      • ADC Private Constants
      • ADC Private Functions
      • ADC Exported Functions
        • Initialization and de-initialization functions
        • ADC Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • ADC Exported Types
        • ADC States
      • ADC Exported Constants
        • ADC Error Code
        • ADC common - Clock source
        • ADC instance - Resolution
        • ADC conversion data alignment
        • ADC sequencer scan mode
        • ADC group regular trigger source
        • ADC group regular trigger edge (when external trigger is selected)
        • ADC sequencer end of unitary conversion or sequence conversions
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer ranks
        • ADC instance - Sampling time common to a group of channels
        • Channel - Sampling time
        • ADC instance - Channel number
        • Analog watchdog - Analog watchdog number
        • ADC Analog Watchdog Mode
        • Oversampling - Ratio
        • Oversampling - Data shift
        • Oversampling - Discontinuous mode
        • ADC group regular - Trigger frequency mode
        • ADC Event type
        • ADC interrupts definition
        • ADC flags definition
      • ADC Private Macros
        • ADC Regular Conversion Number Verification
        • ADC Private Constants
        • ADC Exported Macros
          • HAL ADC macro to manage HAL ADC handle, IT and flags.
          • HAL ADC helper macro
        • ADC Exported Functions
          • Initialization and de-initialization functions
          • ADC Input and Output operation functions
          • Peripheral Control functions
          • Peripheral State functions
    • ADCEx
      • ADC Extended Private Constants
      • ADC Extended Exported Functions
        • Extended Input and Output operation functions
        • ADCEx_Exported_Functions_Group2
      • ADC Extended Exported Types
      • ADC Extended Exported Constants
        • ADC instance - Groups
      • ADC Extended Private Macros
    • CEC
      • CEC Private Constants
      • CEC Private Functions
      • CEC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control function
      • CEC Exported Types
      • CEC Exported Constants
        • CEC State Code Definition
        • CEC Error Code
        • CEC Signal Free Time setting parameter
        • CEC Receiver Tolerance
        • CEC Reception Stop on Error
        • CEC Error Bit Generation if Bit Rise Error reported
        • CEC Error Bit Generation if Long Bit Period Error reported
        • CEC Error Bit Generation on Broadcast message
        • CEC Signal Free Time start option
        • CEC Listening mode option
        • CEC Device Own Address position in CEC CFGR register
        • CEC Initiator logical address position in message header
        • CEC Own Address
        • CEC Interrupts definition
        • CEC Flags definition
        • CEC all RX or TX errors flags
        • CEC all RX errors interrupts enabling flag
        • CEC all TX errors interrupts enabling flag
      • CEC Exported Macros
      • CEC Private Types
      • CEC Private Variables
      • CEC Private Macros
    • COMP
      • COMP Exported Functions
        • Initialization/de-initialization functions
        • Start-Stop operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • COMP Exported Types
      • COMP Exported Constants
        • COMP Error Code
        • COMP Window Mode
        • COMP Window output
        • COMP power mode
        • COMP input plus (non-inverting input)
        • COMP input minus (inverting input)
        • COMP hysteresis
        • COMP output Polarity
        • COMP blanking source
        • COMP Output Level
        • COMP output to EXTI
      • COMP Exported Macros
        • COMP Handle Management
        • COMP external interrupt line management
      • COMP Private Constants
        • COMP window mode instance differentiator
        • COMP EXTI Lines
      • COMP Private Macros
        • COMP private macros to get EXTI line associated with comparators
        • COMP private macros to check input parameters
    • CORTEX
      • CORTEX Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX SysTick clock source
        • CORTEX MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • CORTEX MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Exported Macros
      • CORTEX Exported Functions
        • Initialization and Configuration functions
        • Peripheral Control functions
      • CORTEX Private Macros
    • CRC
      • CRC Private Functions
      • CRC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
      • CRC Exported Constants
        • Default CRC generating polynomial
        • Default CRC computation initialization value
        • Indicates whether or not default polynomial is used
        • Indicates whether or not default init value is used
        • Polynomial sizes to configure the peripheral
        • CRC polynomial possible sizes actual definitions
        • Input Buffer Format
      • CRC Exported Macros
      • CRC Private Macros
    • CRCEx
      • CRC Extended Exported Functions
        • Extended Initialization/de-initialization functions
      • CRC Extended Exported Constants
        • Input Data Inversion Modes
        • Output Data Inversion Modes
      • CRC Extended Exported Macros
      • CRC Extended Private Macros
    • CRYP
      • CRYP Exported Types
        • HAL CRYP Callback ID enumeration definition
        • HAL CRYP Callback pointer definition
      • CRYP Exported Constants
        • CRYP Error Definition
        • CRYP Data Width Unit
        • CRYP Header Width Unit
        • CRYP Algorithm Mode
        • CRYP Key Size
        • CRYP Data Type
        • CRYP Interrupt
        • CRYP Flags
        • CRYP Key and IV Configuration Skip Mode
      • CRYP Exported Macros
      • CRYP Exported Functions
        • Initialization and de-initialization functions
        • Encryption Decryption functions
        • CRYP IRQ handler management
      • CRYP Private Macros
        • CRYP Private macros to check input parameters
      • CRYP Private Constants
      • CRYP Private Defines
      • CRYP Private Variables
      • CRYP Private Functions
    • CRYPEx
      • CRYPEx Private Types
      • CRYPEx Private Variables
      • CRYPEx Private Constants
      • CRYPEx Private Macros
      • CRYPEx Private Functions
      • CRYPEx Exported Functions
        • Extended AES processing functions
        • Extended AES Key Derivations functions
      • CRYPEx_Private_Defines
    • DAC
      • DAC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • DAC Exported Types
      • DAC Exported Constants
        • DAC Error Code
        • DAC trigger selection
        • DAC output buffer
        • DAC Channel selection
        • DAC data alignment
        • DAC flags definition
        • DAC IT definition
        • DAC ConnectOnChipPeripheral
        • DAC User Trimming
        • DAC power mode
      • DAC Exported Macros
      • DAC Private Macros
      • DAC Private Functions
      • DAC Private Constants
    • DACEx
      • DACEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • DACEx private functions
      • DACEx Exported Constants
        • DACEx lfsrunmask triangle amplitude
      • DACEx Private Macros
    • DMA
      • DMA Private Functions
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Errors functions
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA request
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA interrupt enable definitions
        • DMA flag definitions
      • DMA Exported Macros
      • DMA Private Macros
    • DMAEx
      • DMAEx Exported Functions
        • DMAEx Extended features functions
      • DMAEx Exported Types
      • DMAEx Exported Constants
        • DMAMUX SyncSignalID selection
        • DMAMUX SyncPolarity selection
        • DMAMUX SignalGeneratorID selection
        • DMAMUX RequestGeneneratorPolarity selection
      • DMAEx Private Macros
    • EXTI
      • EXTI Private Constants
      • EXTI Exported Types
      • EXTI Exported Constants
        • EXTI Line
        • EXTI Mode
        • EXTI Trigger
        • EXTI GPIOSel
      • EXTI Exported Macros
      • EXTI Private Macros
      • EXTI Exported Functions
        • Configuration functions
        • IO operation functions
    • FDCAN
      • FDCAN Exported Functions
        • Initialization and de-initialization functions
        • Configuration functions
        • Control functions
        • Interrupts management
        • Callback functions
        • Peripheral State functions
      • FDCAN Private Functions
      • FDCAN Exported Types
      • FDCAN Exported Constants
        • HAL FDCAN Error Code
        • FDCAN Frame Format
        • FDCAN Operating Mode
        • FDCAN Clock Divider
        • FDCAN Tx FIFO/Queue Mode
        • FDCAN ID Type
        • FDCAN Frame Type
        • FDCAN Data Length Code
        • FDCAN Error State Indicator
        • FDCAN Bit Rate Switching
        • FDCAN format
        • FDCAN Event FIFO control
        • FDCAN Filter Type
        • FDCAN Filter Configuration
        • FDCAN Tx Location
        • FDCAN Rx Location
        • FDCAN Event Type
        • FDCAN High Priority Message Storage
        • FDCAN protocol error code
        • FDCAN communication state
        • FDCAN FIFO operation mode
        • FDCAN non-matching frames
        • FDCAN reject remote frames
        • FDCAN interrupt line
        • FDCAN timestamp
        • FDCAN timestamp prescaler
        • FDCAN timeout operation
        • Interrupt masks
        • FDCAN Flags
        • FDCAN Interrupts
          • FDCAN Tx Interrupts
          • FDCAN Rx Interrupts
          • FDCAN Counter Interrupts
          • FDCAN Tx Event FIFO Interrupts
          • FDCAN Rx FIFO 0 Interrupts
          • FDCAN Rx FIFO 1 Interrupts
          • FDCAN Error Interrupts
          • FDCAN Error Status Interrupts
        • FDCAN Interrupts List
        • FDCAN Interrupts Group
      • FDCAN Exported Macros
      • FDCAN Private Variables
      • FDCAN Private Constants
      • FDCAN Private Macros
    • FLASH
      • FLASH Private Variables
      • FLASH Private Functions
      • FLASH Exported Functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Keys
        • FLASH Latency
        • FLASH Flags Definition
        • FLASH Interrupts Definition
        • FLASH Error
        • FLASH Erase Type
        • FLASH Banks
        • FLASH Program Type
        • FLASH Option Bytes Type
        • FLASH WRP Area
        • FLASH Option Bytes Read Protection
        • FLASH Option Bytes User Type
        • FLASH Option Bytes User BOR enable
        • FLASH Option Bytes User BOR Level
        • FLASH Option Bytes User Reset On Stop
        • FLASH Option Bytes User Reset On Standby
        • FLASH Option Bytes User Reset On Shutdown
        • FLASH Option Bytes User IWDG Type
        • FLASH Option Bytes User IWDG Mode On Stop
        • FLASH Option Bytes User IWDG Mode On Standby
        • FLASH Option Bytes User WWDG Type
        • FLASH Option Bytes User bank swap Type
        • FLASH Option Bytes User dual bank enable Type
        • FLASH Option Bytes User SRAM parity
        • FLASH Option Bytes User Boot0 Selection
        • FLASH Option Bytes User BOOT1 Type
        • FLASH Option Bytes User nBOOT0 option bit
        • FLASH Option Bytes User reset config bit
        • FLASH Option Bytes User input reset holder bit
        • FLASH Option Bytes PCROP ZONE
        • FLASH Option Bytes PCROP On RDP Level Type
        • FLASH Option Bytes Secure boot lock
      • FLASH Exported Macros
      • FLASH Interrupts Macros
      • FLASH Exported Variables
      • FLASH Private Types
      • FLASH Private Constants
      • FLASH Private Macros
    • FLASHEx
      • FLASHEx Private Functions
      • FLASH Extended Exported Functions
        • Extended IO operation functions
      • FLASH Exported Constants
        • FLASHEx Empty Check
      • FLASHEx Private Constants
      • FLASHEx Private Macros
    • GPIO
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins
        • GPIO mode
        • GPIO speed
        • GPIO pull
      • GPIO Exported Macros
      • GPIO Private Constants
      • GPIO Private Macros
      • GPIO Exported Functions
        • Initialization/de-initialization functions
        • IO operation functions
    • GPIOEx
      • GPIOEx Exported Constants
        • GPIOEx Alternate function selection
      • GPIOEx Exported Macros
        • GPIOEx Get Port Index
    • HCD
      • HCD Private Functions
      • HCD Exported Functions
        • Initialization and de-initialization functions
          • HAL USB OTG HCD Callback ID enumeration definition
          • HAL USB OTG HCD Callback pointer definition
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
          • Allocation
      • HCD Exported Types
        • HCD State Structure definition
        • HCD Handle Structure definition
      • HCD Exported Constants
        • HCD Speed
        • HCD Device Speed
        • HCD PHY Module
        • HCD Error Code definition
      • HCD Exported Macros
      • HCD Private Macros
        • HCD Logical Channel
        • HCD Endpoint Kind
    • I2C
      • I2C Private Define
      • I2C Private Functions
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State, Mode and Error functions
      • I2C Exported Types
        • I2C Configuration Structure definition
        • HAL state structure definition
        • HAL mode structure definition
        • I2C Error Code definition
        • I2C handle Structure definition
      • I2C Exported Constants
        • I2C Sequential Transfer Options
        • I2C Addressing Mode
        • I2C Dual Addressing Mode
        • I2C Own Address2 Masks
        • I2C General Call Addressing Mode
        • I2C No-Stretch Mode
        • I2C Memory Address Size
        • I2C Transfer Direction Master Point of View
        • I2C Reload End Mode
        • I2C Start or Stop Mode
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
    • I2CEx
      • I2C Extended Exported Functions
        • Filter Mode Functions
        • WakeUp Mode Functions
        • Fast Mode Plus Functions
      • I2C Extended Exported Constants
        • I2C Extended Analog Filter
        • I2C Extended Fast Mode Plus
      • I2C Extended Exported Macros
      • I2C Extended Private Constants
      • I2C Extended Private Macros
      • I2C Extended Private Functions
    • I2S
      • I2S Private Functions
      • I2S Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • I2S Exported Types
      • I2S Exported Constants
        • I2S Error
        • I2S Mode
        • I2S Standard
        • I2S Data Format
        • I2S MCLK Output
        • I2S Audio Frequency
        • I2S Clock Polarity
        • I2S Interrupts Definition
        • I2S Flags Definition
      • I2S Exported Macros
      • I2S Private Macros
    • IRDA
      • IRDA Private Constants
      • IRDA Private Macros
      • IRDA Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • IRDA Private Functions
      • IRDA Exported Types
      • IRDA Exported Constants
        • IRDA State Code Definition
        • IRDA Error Code Definition
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA Clock Prescaler
        • IRDA State
        • IRDA Mode
        • IRDA One Bit Sampling
        • IRDA DMA Tx
        • IRDA DMA Rx
        • IRDA Request Parameters
        • IRDA Flags
        • IRDA Interrupts Definition
        • IRDA Interruption Clear Flags
        • IRDA interruptions flags mask
      • IRDA Exported Macros
    • IRDAEx
      • IRDAEx Extended Exported Constants
        • IRDAEx Word Length
      • IRDAEx Private Macros
    • IWDG
      • IWDG Private Defines
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
        • IWDG Window option
      • IWDG Exported Macros
      • IWDG Exported Functions
        • Initialization and Start functions
        • IO operation functions
      • IWDG Private Constants
      • IWDG Private Macros
    • LPTIM
      • LPTIM Exported Functions
        • Initialization/de-initialization functions
        • LPTIM Start-Stop operation functions
        • LPTIM Read operation functions
        • LPTIM IRQ handler and callbacks
        • Peripheral State functions
      • LPTIM Private Functions
      • LPTIM Exported Types
      • LPTIM Exported Constants
        • LPTIM Clock Source
        • LPTIM Clock Prescaler
        • LPTIM Output Polarity
        • LPTIM Clock Sample Time
        • LPTIM Clock Polarity
        • LPTIM Trigger Source
        • LPTIM External Trigger Polarity
        • LPTIM Trigger Sample Time
        • LPTIM Updating Mode
        • LPTIM Counter Source
        • LPTIM Input1 Source
        • LPTIM Input2 Source
        • LPTIM Flags Definition
        • LPTIM Interrupts Definition
      • LPTIM Exported Macros
      • LPTIM Private Types
      • LPTIM Private Variables
      • LPTIM Private Constants
      • LPTIM Private Macros
    • PCD
      • PCD Private Macros
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
          • HAL USB OTG PCD Callback ID enumeration definition
          • HAL USB OTG PCD Callback pointer definition
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Speed
        • PCD PHY Module
        • PCD Error Code definition
      • PCD Exported Macros
      • PCD Private Constants
        • USB EXTI line interrupt
        • PCD EP0 MPS
        • PCD ENDP
        • PCD Endpoint Kind
    • PCDEx
      • PCDEx Exported Functions
        • Peripheral Control functions
    • PWR
      • PWR Private Defines
      • PWR Exported Types
      • PWR Exported Constants
        • PWR WakeUp pins
        • PWR Low Power Mode Selection
        • PWR regulator mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR Status Flags
      • PWR Exported Macros
      • Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
      • PWR Private Macros
      • PWR Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
    • PWREx
      • PWR Extended Private Defines
        • PWR PVD Mode Mask
        • PWREx Flag Setting Time Out Value
        • PWREx Gpio Pin Number
        • PWR PVM Mode Mask
      • PWR Extended Exported Types
      • PWR Extended Exported Constants
        • Programmable Voltage Detection levels
        • PWR PVD interrupt and event mode
        • PWR PVD external interrupt line
        • PWR PVD event line
        • Peripheral Voltage Monitoring type
        • PWR PVM interrupt and event mode
        • PWR PVM external interrupt line
        • PWR PVM event line
        • PWR battery charging resistor selection
        • GPIO bit position
        • GPIO Port
        • Flash Power Down modes
        • PWR Regulator voltage scale
        • PWR Status Flags
      • PWR Extended Exported Functions
        • Extended Peripheral Control functions
      • PWR Extended Exported Macros
      • PWR Extended Private Macros
    • RCC
      • RCC Private Constants
      • RCC Private Macros
      • RCC Private Variables
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • RCC Exported Types
      • RCC Exported Constants
        • Timeout Values
        • Oscillator Type
        • HSE Config
        • LSE Config
        • HSI Config
        • HSI Div
        • LSI Config
        • HSI48 Config
        • PLL Config
        • PLLM Clock Divider
        • PLLP Clock Divider
        • PLLQ Clock Divider
        • PLLR Clock Divider
        • PLL Clock Source
        • PLL Clock Output
        • System Clock Type
        • System Clock Source
        • System Clock Source Status
        • AHB Clock Source
        • APB Clock Source
        • RTC Clock Source
        • MCO Index
        • MCO1 Clock Source
        • MCO1 Clock Prescaler
        • MCO2 Clock Source
        • MCO2 Clock Prescaler
        • Interrupts
        • Flags
        • LSE Drive Configuration
        • Reset Flag
      • RCC Exported Macros
        • AHB Peripheral Clock Enable Disable
        • IOPORT Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable
        • AHB Peripheral Clock Enabled or Disabled Status
        • IOPORT Clock Enabled or Disabled Status
        • APB1 Peripheral Clock Enabled or Disabled Status
        • APB2 Peripheral Clock Enabled or Disabled Status
        • AHB Peripheral Force Release Reset
        • IOPORT Force Release Reset
        • APB1 Peripheral Force Release Reset
        • APB2 Peripheral Force Release Reset
        • AHB Peripherals Clock Sleep Enable Disable
        • IOPORT Clock Sleep Enable Disable
        • APB1 Peripheral Clock Sleep Enable Disable
        • APB2 Peripheral Clock Sleep Enable Disable
        • AHB Peripheral Clock Sleep Enabled or Disabled Status
        • IOPORT Clock Sleep Enabled or Disabled Status
        • APB1 Peripheral Clock Sleep Enabled or Disabled Status
        • APB2 Peripheral Clock Sleep Enabled or Disabled Status
        • RCC Backup Domain Reset
        • RCC RTC Clock Configuration
        • RCC Clock Configuration
        • Flags Interrupts Management
    • RCCEx
      • RCCEx Private Constants
      • RCCEx Exported Functions
        • Extended Peripheral Control functions
        • Extended Clock management functions
        • Extended Clock Recovery System Control functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • Low Speed Clock Source
        • Periph Clock Selection
        • RCC USART1 Clock Source
        • RCC USART2 Clock Source
        • RCC USART3 Clock Source
        • RCC LPUART1 Clock Source
        • RCC LPUART2 Clock Source
        • RCC I2C1 Clock Source
        • RCC I2C2 Clock Source
        • RCC I2S1 Clock Source
        • RCC I2S2 Clock Source
        • RCC LPTIM1 Clock Source
        • RCC LPTIM2 Clock Source
        • RCC RNG Clock Source
        • RCC RNG Division factor
        • RCC FDCAN Clock Source
        • USB Clock Source
        • RCC ADC Clock Source
        • RCC CEC Clock Source
        • RCC TIM1 Clock Source
        • RCC TIM15 Clock Source
        • RCCEx CRS Status
        • RCCEx CRS SynchroSource
        • RCCEx CRS SynchroDivider
        • RCCEx CRS SynchroPolarity
        • RCCEx CRS ReloadValueDefault
        • RCCEx CRS ErrorLimitDefault
        • RCCEx CRS HSI48CalibrationDefault
        • RCCEx CRS FreqErrorDirection
        • RCCEx CRS Interrupt Sources
        • RCCEx CRS Flags
      • RCCEx Exported Macros
      • RCCEx CRS Extended Features
      • RCCEx Private Macros
    • RNG
      • RNG Private Constants
      • RNG Exported Types
        • RNG Init Structure definition
        • RNG State Structure definition
        • RNG Handle Structure definition
      • RNG Exported Constants
        • RNG Interrupt definition
        • RNG Flag definition
        • RNG Clock Error Detection
        • RNG Error Definition
      • RNG Exported Macros
      • RNG Exported Functions
        • Initialization and configuration functions
        • Peripheral Control functions
        • Peripheral State functions
      • RNG Private Macros
    • RTC
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats
        • RTCEx Output Selection Definition
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC Output Pull-Up ALARM OUT
        • RTC Output ALARM OUT Remap
        • RTC AM PM Definitions
        • RTC DayLightSaving Definitions
        • RTC StoreOperation Definitions
        • RTC Input Parameter Format Definitions
        • RTC Month Date Definitions
        • RTC WeekDay Definitions
        • RTC AlarmDateWeekDay Definitions
        • RTC AlarmMask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
        • RTC Flags Definitions
        • RTC Clear Flags Definitions
      • RTC Exported Macros
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
      • RTC Private Functions
    • RTCEx
      • RTCEx Exported Types
        • RTCEx Tamper structure definition
        • RTCEx Internal Tamper structure definition
      • RTCEx Exported Constants
        • RTCEx Time Stamp Edges definition
        • RTCEx TimeStamp Pin Selection
        • RTCEx Wakeup Timer Definitions
        • RTCEx Smooth calib period Definitions
        • RTCEx Smooth calib Plus pulses Definitions
        • RTCEx Calib Output selection Definitions
        • RTCEx Add 1 Second Parameter Definitions
        • RTCEx Tamper Pins Definition
        • RTCEx Internal Tamper Pins Definition
        • RTCEx Tamper Trigger
        • RTCEx Tamper MaskFlag
        • RTCEx Tamper EraseBackUp
        • RTCEx Tamper Filter
        • RTCEx Tamper Sampling Frequencies
        • RTCEx Tamper Pin Precharge Duration
        • RTCEx Tamper Pull UP
        • RTCEx Tamper TimeStamp On Tamper Detection Definitions
        • RTCEx Internal Tamper Interrupt
        • RTCEx Flags
        • RTCEx Backup Registers Definition
      • RTCEx Exported Macros
        • RTC WakeUp Timer
        • RTC Timestamp
        • RTC Calibration
        • RTCEx tamper
      • RTCEx Exported Functions
        • Extended RTC TimeStamp functions
        • Extended RTC Wake-up functions
        • Extended Peripheral Control functions
        • Extended features functions
        • Extended RTC Tamper functions
        • Extended RTC Backup register functions
      • RTCEx Private Constants
      • RTCEx Private Macros
        • Private macros to check input parameters
          • RTCEx Smooth calib Minus pulses Definitions
          • RTCEx Subtract Fraction Of Second Value
    • SMARTCARD
      • SMARTCARD Private Constants
      • SMARTCARD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Private Functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported Constants
        • SMARTCARD State Code Definition
        • SMARTCARD Error Code Definition
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Transfer Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD One Bit Sampling Method
        • SMARTCARD NACK Enable
        • SMARTCARD Timeout Enable
        • SMARTCARD Clock Prescaler
        • SMARTCARD advanced feature TX pin active level inversion
        • SMARTCARD advanced feature RX pin active level inversion
        • SMARTCARD advanced feature Binary Data inversion
        • SMARTCARD advanced feature RX TX pins swap
        • SMARTCARD advanced feature Overrun Disable
        • SMARTCARD advanced feature DMA Disable on Rx Error
        • SMARTCARD advanced feature MSB first
        • SMARTCARD Request Parameters
        • SMARTCARD interruptions flags mask
      • SMARTCARD Exported Macros
      • SMARTCARD Private Macros
    • SMARTCARDEx
      • SMARTCARD Extended Private Constants
      • SMARTCARD Extended Exported Functions
        • Extended Peripheral Control functions
        • Extended Peripheral IO operation functions
        • Extended Peripheral FIFO Control functions
      • SMARTCARD Extended Private Functions
      • SMARTCARD Extended Private Macros
      • SMARTCARD Extended Exported Constants
        • SMARTCARD Transmission Completion Indication
        • SMARTCARD advanced feature initialization type
        • SMARTCARD FIFO mode
        • SMARTCARD TXFIFO threshold level
        • SMARTCARD RXFIFO threshold level
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
        • SMARTCARD Interruption Clear Flags
    • SMBUS
      • SMBUS Private Constants
      • SMBUS Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
          • Blocking mode Polling
          • Non-Blocking mode Interrupt
          • IRQ Handler and Callbacks
          • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
        • SMBUS Private Functions
      • SMBUS Exported Types
        • SMBUS Configuration Structure definition
        • HAL state definition
        • SMBUS Error Code definition
        • SMBUS handle Structure definition
      • SMBUS Exported Constants
        • SMBUS Analog Filter
        • SMBUS addressing mode
        • SMBUS dual addressing mode
        • SMBUS ownaddress2 masks
        • SMBUS general call addressing mode
        • SMBUS nostretch mode
        • SMBUS packet error check mode
        • SMBUS peripheral mode
        • SMBUS ReloadEndMode definition
        • SMBUS StartStopMode definition
        • SMBUS XferOptions definition
        • SMBUS Interrupt configuration definition
        • SMBUS Flag definition
      • SMBUS Exported Macros
      • SMBUS Private Macros
      • SMBUS Private Functions
    • SMBUSEx
      • SMBUS Extended Exported Functions
        • WakeUp Mode Functions
        • Fast Mode Plus Functions
      • SMBUS Extended Exported Constants
        • SMBUS Extended Fast Mode Plus
      • SMBUS Extended Exported Macros
      • SMBUS Extended Private Constants
      • SMBUS Extended Private Macros
      • SMBUS Extended Private Functions
    • SPI
      • SPI Private Constants
      • SPI Private Functions
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI Error Code
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select Management
        • SPI NSS Pulse Mode
        • SPI BaudRate Prescaler
        • SPI MSB LSB Transmission
        • SPI TI Mode
        • SPI CRC Calculation
        • SPI CRC Length
        • SPI FIFO Reception Threshold
        • SPI Interrupt Definition
        • SPI Flags Definition
        • SPI Transmission FIFO Status Level
        • SPI Reception FIFO Status Level
      • SPI Exported Macros
      • SPI Private Macros
    • SPIEx
      • SPIEx Private Constants
      • SPIEx Exported Functions
        • IO operation functions
    • TIM
      • TIM Exported Functions
        • TIM Time Base functions
        • TIM Output Compare functions
        • TIM PWM functions
        • TIM Input Capture functions
        • TIM One Pulse functions
        • TIM Encoder functions
        • TIM IRQ handler management
        • TIM Peripheral Control functions
        • TIM Callbacks functions
        • TIM Peripheral State functions
      • TIM Private Functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Clear Input Source
        • TIM DMA Base Address
        • TIM Event Source
        • TIM Input Channel polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Update Interrupt Flag Remap
        • TIM Clock Division
        • TIM Output Compare State
        • TIM Auto-Reload Preload
        • TIM Output Fast State
        • TIM Complementary Output Compare State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Complementary Output Compare Idle State
        • TIM Input Capture Polarity
        • TIM Encoder Input Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM interrupt Definition
        • TIM Commutation Source
        • TIM DMA Sources
        • CCx DMA request selection
        • TIM Flag Definition
        • TIM Channel
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR OffState Selection for Run mode state
        • TIM OSSI OffState Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input Enable
        • TIM Break Input Polarity
        • TIM Break Input Alternate Function Mode
        • TIM Break input 2 Enable
        • TIM Break Input 2 Polarity
        • TIM Break2 Input Alternate Function Mode
        • TIM Automatic Output Enable
        • TIM Group Channel 5 and Channel 1, 2 or 3
        • TIM Master Mode Selection
        • TIM Master Mode Selection 2 (TRGO2)
        • TIM Master/Slave Mode
        • TIM Slave mode
        • TIM Output Compare and PWM Modes
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Input Selection
        • TIM DMA Burst Length
        • TIM DMA Handle Index
        • TIM Capture/Compare Channel State
        • TIM Break System
      • TIM Exported Macros
      • TIM Private Constants
      • TIM Private Macros
    • TIMEx
      • TIM Extended Private Constants
      • TIM Extended Exported Functions
        • Extended Timer Hall Sensor functions
        • Extended Timer Complementary Output Compare functions
        • Extended Timer Complementary PWM functions
        • Extended Timer Complementary One Pulse functions
        • Extended Peripheral Control functions
        • Extended Callbacks functions
        • Extended Peripheral State functions
      • TIM Extended Private Functions
      • TIM Extended Exported Types
      • TIM Extended Exported Constants
        • TIM Extended Remapping
        • TIM Extended Break input
        • TIM Extended Break input source
        • TIM Extended Break input source enabling
        • TIM Extended Break input polarity
        • TIM Extended Timer input selection
      • TIM Extended Exported Macros
      • TIM Extended Private Macros
    • UART
      • UART Private Constants
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • UART Private Functions
      • UART Exported Types
      • UART Exported Constants
        • UART State Code Definition
        • UART Error Definition
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART One Bit Sampling Method
        • UART Clock Prescaler
        • UART Advanced Feature AutoBaud Rate Mode
        • UART Receiver Timeout
        • UART Local Interconnection Network mode
        • UART LIN Break Detection
        • UART DMA Tx
        • UART DMA Rx
        • UART Half Duplex Selection
        • UART WakeUp Methods
        • UART Request Parameters
        • UART Advanced Feature Initialization Type
        • UART Advanced Feature TX Pin Active Level Inversion
        • UART Advanced Feature RX Pin Active Level Inversion
        • UART Advanced Feature Binary Data Inversion
        • UART Advanced Feature RX TX Pins Swap
        • UART Advanced Feature Overrun Disable
        • UART Advanced Feature Auto BaudRate Enable
        • UART Advanced Feature DMA Disable On Rx Error
        • UART Advanced Feature MSB First
        • UART Advanced Feature Stop Mode Enable
        • UART Advanced Feature Mute Mode Enable
        • UART Address-matching LSB Position In CR2 Register
        • UART WakeUp From Stop Selection
        • UART DriverEnable Polarity
        • UART Driver Enable Assertion Time LSB Position In CR1 Register
        • UART Driver Enable DeAssertion Time LSB Position In CR1 Register
        • UART Interruptions Flag Mask
        • UART polling-based communications time-out value
        • UART Status Flags
        • UART Interrupts Definition
        • UART Interruption Clear Flags
        • UART Reception type values
        • UART RxEvent type values
      • UART Exported Macros
      • UART Private Macros
      • UART Private variables
    • UARTEx
      • UARTEx Private Constants
      • UARTEx Private Functions
      • UARTEx Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
      • UARTEx Exported Types
      • UARTEx Exported Constants
        • UARTEx Word Length
        • UARTEx WakeUp Address Length
        • UARTEx FIFO mode
        • UARTEx TXFIFO threshold level
        • UARTEx RXFIFO threshold level
      • UARTEx Private Macros
    • USART
      • USART Private Constants
      • USART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • USART Private Functions
      • USART Exported Types
      • USART Exported Constants
        • USART Error Definition
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART Clock Prescaler
        • USART Request Parameters
        • USART Flags
        • USART Interrupts Definition
        • USART Interruption Clear Flags
        • USART Interruption Flags Mask
      • USART Exported Macros
      • USART Private Macros
    • USARTEx
      • USARTEx Private Constants
      • USARTEx Private Functions
      • USARTEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • USARTEx Exported Constants
        • USARTEx Word Length
        • USARTEx Slave Select Management
        • USARTEx Synchronous Slave mode enable
        • USARTEx FIFO mode
        • USARTEx TXFIFO threshold level
        • USARTEx RXFIFO threshold level
      • USARTEx Private Macros
    • WWDG
      • WWDG Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
        • WWDG Early Wakeup Interrupt Mode
      • WWDG Private Macros
      • WWDG Exported Macros
  • STM32G0xx_LL_Driver
    • ADC
      • ADC Private Constants
      • ADC Private Macros
      • ADC Exported Init structure
      • ADC Exported Constants
        • ADC flags
        • ADC interruptions for configuration (interruption enable or disable)
        • ADC registers compliant with specific purpose
        • ADC common - Clock source
        • ADC common - Clock frequency mode
        • ADC common - Measurement path to internal channels
        • ADC instance - Clock source
        • ADC instance - Resolution
        • ADC instance - Data alignment
        • ADC instance - Low power mode
        • ADC group regular - Trigger frequency mode
        • ADC instance - Sampling time common to a group of channels
        • ADC instance - Groups
        • ADC instance - Channel number
        • ADC group regular - Trigger source
        • ADC group regular - Trigger edge
        • ADC group regular - Continuous mode
        • ADC group regular - DMA transfer of ADC conversion data
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer configuration flexibility
        • ADC group regular - Sequencer scan length
        • ADC group regular - Sequencer scan direction
        • ADC group regular - Sequencer discontinuous mode
        • ADC group regular - Sequencer ranks
        • Channel - Sampling time
        • Analog watchdog - Analog watchdog number
        • Analog watchdog - Monitored channels
        • Analog watchdog - Thresholds
        • Oversampling - Oversampling scope
        • Oversampling - Discontinuous mode
        • Oversampling - Ratio
        • Oversampling - Data shift
        • Definitions of constants used by helper macro
        • Definitions of ADC hardware constraints delays
      • ADC Exported Macros
        • Common write and read registers Macros
        • ADC helper macro
      • ADC Exported Functions
        • ADC DMA management
        • Configuration of ADC hierarchical scope: common to several ADC instances
        • Configuration of ADC hierarchical scope: ADC instance
        • Configuration of ADC hierarchical scope: group regular
        • Configuration of ADC hierarchical scope: channels
        • Configuration of ADC transversal scope: analog watchdog
        • Configuration of ADC transversal scope: oversampling
        • Operation on ADC hierarchical scope: ADC instance
        • Operation on ADC hierarchical scope: group regular
        • ADC flag management
        • ADC IT management
        • Initialization and de-initialization functions
    • BUS
      • BUS Exported Constants
        • AHB1 GRP1 PERIPH
        • APB1 GRP1 PERIPH
        • APB2 GRP1 PERIPH
        • IOP GRP1 PERIPH
      • BUS Exported Functions
        • AHB1
        • APB1
        • APB2
        • IOP
    • COMP
      • COMP Private Constants
      • COMP Private Macros
      • COMP Exported Init structure
      • COMP Exported Constants
        • Comparator common modes - Window mode
        • Comparator common modes - Window output
        • Comparator modes - Power mode
        • Comparator inputs - Input plus (input non-inverting) selection
        • Comparator inputs - Input minus (input inverting) selection
        • Comparator input - Hysteresis
        • Comparator output - Output polarity
        • Comparator output - Blanking source
        • Comparator output - Output level
        • Definitions of COMP hardware constraints delays
      • COMP Exported Macros
        • Common write and read registers macro
        • COMP helper macro
      • COMP Exported Functions
        • Configuration of COMP hierarchical scope: common to several COMP instances
        • Configuration of comparator modes
        • Configuration of comparator inputs
        • Configuration of comparator output
        • Operation on comparator instance
        • Initialization and de-initialization functions
    • CORTEX
      • CORTEX Exported Constants
        • SYSTICK Clock Source
        • MPU Control
        • MPU Region Number
        • MPU Region Size
        • MPU Region Privileges
        • MPU TEX Level
        • MPU Instruction Access
        • MPU Shareable Access
        • MPU Cacheable Access
        • MPU Bufferable Access
      • CORTEX Exported Functions
        • SYSTICK
        • LOW POWER MODE
        • MCU INFO
        • MPU
    • CRC
      • CRC Exported Constants
        • Polynomial length
        • Input Data Reverse
        • Output Data Reverse
        • Default CRC generating polynomial value
        • Default CRC computation initialization value
      • CRC Exported Macros
        • Common Write and read registers Macros
      • CRC Exported Functions
        • CRC Configuration functions
        • Data_Management
        • Initialization and de-initialization functions
    • CRS
      • CRS Exported Constants
        • Get Flags Defines
        • IT Defines
        • Synchronization Signal Divider
        • Synchronization Signal Source
        • Synchronization Signal Polarity
        • Frequency Error Direction
        • Default Values
      • CRS Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Calculate_Reload
      • CRS Exported Functions
        • Configuration
        • CRS_Management
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • DAC
      • DAC Private Constants
      • DAC Private Macros
      • DAC Exported Init structure
      • DAC Exported Constants
        • DAC flags
        • DAC interruptions
        • DAC channels
        • DAC operating mode
        • DAC trigger source
        • DAC waveform automatic generation mode
        • DAC wave generation - Noise LFSR unmask bits
        • DAC wave generation - Triangle amplitude
        • DAC channel output mode
        • DAC channel output buffer
        • DAC channel output connection
        • DAC channel output resolution
        • DAC registers compliant with specific purpose
        • Definitions of DAC hardware constraints delays
      • DAC Exported Macros
        • Common write and read registers macros
        • DAC helper macro
      • DAC Exported Functions
        • Configuration of DAC channels
        • DMA Management
        • Operation on DAC channels
        • FLAG Management
        • IT management
        • Initialization and de-initialization functions
    • DMA
      • DMA Private Variables
      • DMA Private Macros
      • DMA Exported Init structure
      • DMA Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • CHANNEL
        • Transfer Direction
        • Transfer mode
        • Peripheral increment mode
        • Memory increment mode
        • Peripheral data alignment
        • Memory data alignment
        • Transfer Priority level
      • DMA Exported Macros
        • Common Write and read registers macros
        • Convert DMAxChannely
      • DMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • DMAMUX
      • DMAMUX Private Constants
      • DMAMUX Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Transfer request
        • DMAMUX Channel
        • Synchronization Signal Polarity
        • Synchronization Signal Event
        • Request Generator Channel
        • External Request Signal Generation Polarity
        • External Request Signal Generation
      • DMAMUX Exported Macros
        • Common Write and read registers macros
      • DMAMUX Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
    • EXTI
      • EXTI Private Macros
      • EXTI Exported Init structure
      • EXTI Exported Constants
        • LINE
          • EXTI CONFIG PORT
          • EXTI CONFIG LINE
        • Mode
        • Edge Trigger
      • EXTI Exported Macros
        • Common Write and read registers Macros
      • EXTI Exported Functions
        • IT_Management
        • Event_Management
        • Rising_Trigger_Management
        • Falling_Trigger_Management
        • Software_Interrupt_Management
        • Flag_Management
        • EF configuration functions
        • Initialization and de-initialization functions
    • GPIO
      • GPIO Private Macros
      • GPIO Exported Init structures
      • GPIO Exported Constants
        • PIN
        • Mode
        • Output Type
        • Output Speed
        • Pull Up Pull Down
        • Alternate Function
      • GPIO Exported Macros
        • Common Write and read registers Macros
      • GPIO Exported Functions
        • Port Configuration
        • Data Access
        • Initialization and de-initialization functions
    • I2C
      • I2C Private Constants
      • I2C Private Macros
      • I2C Exported Init structure
      • I2C Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Peripheral Mode
        • Analog Filter Selection
        • Master Addressing Mode
        • Own Address 1 Length
        • Own Address 2 Masks
        • Acknowledge Generation
        • Slave Address Length
        • Transfer Request Direction
        • Transfer End Mode
        • Start And Stop Generation
        • Read Write Direction
        • DMA Register Data
        • SMBus TimeoutA Mode SCL SDA Timeout
        • SMBus Timeout Selection
      • I2C Exported Macros
        • Common Write and read registers Macros
        • Convert SDA SCL timings
      • I2C Exported Functions
        • Configuration
        • IT_Management
        • FLAG_management
        • Data_Management
        • Initialization and de-initialization functions
    • IWDG
      • IWDG Private Constants
      • IWDG Exported Constants
        • Get Flags Defines
        • Prescaler Divider
      • IWDG Exported Macros
        • Common Write and read registers Macros
      • IWDG Exported Functions
        • Configuration
        • FLAG_Management
    • LPTIM
      • LPTIM Private Functions
      • LPTIM Private Macros
      • LPTIM Exported Init structure
      • LPTIM Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operating Mode
        • Update Mode
        • Counter Mode
        • Output Waveform Type
        • Output Polarity
        • Prescaler Value
        • Trigger Source
        • Trigger Filter
        • Trigger Polarity
        • Clock Source
        • Clock Filter
        • Clock Polarity
        • Encoder Mode
        • Input1 Source
        • Input2 Source
      • LPTIM Exported Macros
        • Common Write and read registers Macros
      • LPTIM Exported Functions
        • Initialisation and deinitialisation functions
        • LPTIM Configuration
        • Trigger Configuration
        • Clock Configuration
        • Encoder Mode
        • FLAG Management
        • Interrupt Management
    • LPUART
      • LPUART Private Variables
      • LPUART Private Constants
      • LPUART Private Macros
      • LPUART Exported Init structures
      • LPUART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • FIFO Threshold
        • Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Clock Source Prescaler
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • Driver Enable Polarity
        • DMA Register Data
      • LPUART Exported Macros
        • Common Write and read registers Macros
        • Helper Macros
      • LPUART Exported Functions
        • Configuration functions
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to Driver Enable feature
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • PWR
      • PWR Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • REGU VOLTAGE
        • MODE PWR
        • PVDLEVEL
        • PVM_IP
        • WAKEUP
        • BATT CHARG RESISTOR
        • GPIO
        • GPIO BIT
      • PWR Exported Macros
        • Common Write and read registers Macros
      • PWR Exported Functions
        • Configuration
        • FLAG_Management
        • De-initialization function
    • RCC
      • RCC Private functions
      • RCC Private Variables
      • RCC Private Macros
      • RCC Exported Types
        • Clocks Frequency Structure
      • RCC Exported Constants
        • Oscillator Values adaptation
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • LSE oscillator drive capability
        • LSCO Selection
        • System clock switch
        • System clock switch status
        • AHB prescaler
        • APB low-speed prescaler (APB1)
        • HSI division factor
        • MCO1 SOURCE selection
        • MCO1 prescaler
        • MCO2 SOURCE selection
        • MCO2 prescaler
        • Peripheral clock frequency
        • Peripheral USART clock source selection
        • Peripheral LPUART clock source selection
        • Peripheral I2C clock source selection
        • Peripheral I2S clock source selection
        • Peripheral TIM clock source selection
        • Peripheral LPTIM clock source selection
        • Peripheral CEC clock source selection
        • Peripheral FDCAN clock source selection
        • Peripheral RNG clock source selection
        • Peripheral RNG clock division factor
        • Peripheral USB clock source selection
        • Peripheral ADC clock source selection
        • Peripheral USARTx get clock source
        • Peripheral LPUART get clock source
        • Peripheral I2C get clock source
        • Peripheral I2S get clock source
        • Peripheral TIMx get clock source
        • Peripheral LPTIM get clock source
        • Peripheral CEC get clock source
        • Peripheral FDCAN get clock source
        • Peripheral USB get clock source
        • Peripheral RNG get clock source
        • Peripheral RNG get clock division factor
        • Peripheral ADC get clock source
        • RTC clock source selection
        • PLL entry clock source
        • PLL division factor (PLLM)
        • PLL division factor (PLLR)
        • PLL division factor (PLLP)
        • PLL division factor (PLLQ)
      • RCC Exported Macros
        • Common Write and read registers Macros
        • Calculate frequencies
      • RCC Exported Functions
        • HSE
        • HSI
        • HSI48
        • LSE
        • LSI
        • LSCO
        • System
        • MCO1
        • MCO2
        • Peripheral Clock Source
        • RTC
        • PLL
        • FLAG Management
        • IT Management
        • De-initialization function
        • Get system and peripherals clocks frequency functions
    • RNG
      • RNG Private Macros
      • RNG Exported Init structures
      • RNG Exported Constants
        • Clock Error Detection
        • Get Flags Defines
        • IT Defines
      • RNG Exported Macros
        • Common Write and read registers Macros
      • RNG Exported Functions
        • RNG Configuration functions
        • FLAG Management
        • IT Management
        • Data Management
        • Initialization and de-initialization functions
    • RTC
      • RTC Private Constants
      • RTC Private Macros
      • RTC Exported Init structure
      • RTC Exported Constants
        • FORMAT
        • RTC Alarm A Date WeekDay
        • RTC Alarm B Date WeekDay
        • Get Flags Defines
        • IT Defines
        • WEEK DAY
        • MONTH
        • HOUR FORMAT
        • ALARM OUTPUT
        • ALARM OUTPUT TYPE
        • OUTPUT POLARITY PIN
        • TIME FORMAT
        • SHIFT SECOND
        • ALARMA MASK
        • ALARMA TIME FORMAT
        • ALARMB MASK
        • ALARMB TIME FORMAT
        • TIMESTAMP EDGE
        • TIMESTAMP TIME FORMAT
        • TAMPER
        • TAMPER MASK
        • TAMPER NO ERASE
        • TAMPER DURATION
        • TAMPER FILTER
        • TAMPER SAMPLING FREQUENCY DIVIDER
        • TAMPER ACTIVE LEVEL
        • INTERNAL TAMPER
        • BACKUP
        • WAKEUP CLOCK DIV
        • Calibration output
        • Calibration pulse insertion
        • Calibration period
      • RTC Exported Macros
        • Common Write and read registers Macros
        • Convert helper Macros
        • Date helper Macros
        • Time helper Macros
      • RTC Exported Functions
        • Configuration
        • Time
        • Date
        • ALARMA
        • ALARMB
        • Timestamp
        • Tamper
        • Internal Tamper
        • Wakeup
        • Backup_Registers
        • Calibration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • SPI
      • SPI Private Constants
      • SPI Private Macros
      • SPI Exported Init structure
      • SPI Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operation Mode
        • Serial Protocol
        • Clock Phase
        • Clock Polarity
        • Baud Rate Prescaler
        • Transmission Bit Order
        • Transfer Mode
        • Slave Select Pin Mode
        • Datawidth
        • CRC Calculation
        • CRC Length
        • RX FIFO Threshold
        • RX FIFO Level
        • TX FIFO Level
        • DMA Parity
      • SPI Exported Macros
        • Common Write and read registers Macros
      • SPI Exported Functions
        • Configuration
        • CRC Management
        • Slave Select Pin Management
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • I2S
      • I2S Private Constants
      • I2S Private Macros
      • I2S Exported Init structure
      • I2S Exported Constants
        • Get Flags Defines
        • IT Defines
        • Data format
        • Clock Polarity
        • I2s Standard
        • Operation Mode
        • Prescaler Factor
        • MCLK Output
        • Audio Frequency
      • I2S Exported Macros
        • Common Write and read registers Macros
      • I2S Exported Functions
        • Configuration
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • SYSTEM
      • SYSTEM Private Constants
      • SYSTEM Exported Constants
        • SYSCFG REMAP
        • SYSCFG PIN RMP
        • SYSCFG IR Modulation
        • SYSCFG IR Polarity
        • SYSCFG I/O analog switch voltage booster enable
        • SYSCFG UCPD Dead Battery feature Disable
        • SYSCFG I2C FASTMODEPLUS
        • SYSCFG TIMER BREAK
        • SYSCFG CLAMPING DIODE
        • DBGMCU APB1 GRP1 STOP IP
        • DBGMCU APB2 GRP1 STOP IP
        • VREFBUF VOLTAGE
        • FLASH LATENCY
      • SYSTEM Exported Functions
        • SYSCFG
        • DBGMCU
        • VREFBUF
        • FLASH
    • TIM
      • TIM Private Functions
      • TIM Private Variables
      • TIM Private Constants
      • TIM Private Macros
      • TIM Exported Init structure
      • TIM Exported Constants
        • Get Flags Defines
        • Break Enable
        • Break2 Enable
        • Automatic output enable
        • IT Defines
        • Update Source
        • One Pulse Mode
        • Counter Mode
        • Clock Division
        • Counter Direction
        • Capture Compare Update Source
        • Capture Compare DMA Request
        • Lock Level
        • Channel
        • Output Configuration State
        • Output Configuration Mode
        • Output Configuration Polarity
        • Output Configuration Idle State
        • GROUPCH5
        • Active Input Selection
        • Input Configuration Prescaler
        • Input Configuration Filter
        • Input Configuration Polarity
        • Clock Source
        • Encoder Mode
        • Trigger Output
        • Trigger Output 2
        • Slave Mode
        • Trigger Selection
        • External Trigger Polarity
        • External Trigger Prescaler
        • External Trigger Filter
        • External Trigger Source
        • break polarity
        • break filter
        • BREAK2 POLARITY
        • BREAK2 FILTER
        • OSSI
        • OSSR
        • BREAK INPUT
        • BKIN SOURCE
        • BKIN POLARITY
        • BREAK AF MODE
        • BREAK2 AF MODE
        • DMA Burst Base Address
        • DMA Burst Length
        • TIM1 Timer Input Ch1 Remap
        • TIM1 Timer Input Ch2 Remap
        • TIM1 Timer Input Ch3 Remap
        • TIM2 Timer Input Ch1 Remap
        • TIM2 Timer Input Ch2 Remap
        • TIM2 Timer Input Ch3 Remap
        • TIM3 Timer Input Ch1 Remap
        • TIM3 Timer Input Ch2 Remap
        • TIM3 Timer Input Ch3 Remap
        • TIM4 Timer Input Ch1 Remap
        • TIM4 Timer Input Ch2 Remap
        • TIM4 Timer Input Ch3 Remap
        • TIM14 Timer Input Ch1 Remap
        • TIM15 Timer Input Ch1 Remap
        • TIM15 Timer Input Ch2 Remap
        • TIM16 Timer Input Ch1 Remap
        • TIM17 Timer Input Ch1 Remap
        • OCREF clear input selection
      • TIM Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros
      • TIM Exported Functions
        • Time Base configuration
        • Capture Compare configuration
        • Output channel configuration
        • Input channel configuration
        • Counter clock selection
        • Timer synchronisation configuration
        • Break function configuration
        • DMA burst mode configuration
        • Timer input remapping
        • OCREF_Clear_Management
        • FLAG-Management
        • IT-Management
        • DMA Management
        • EVENT-Management
        • Initialisation and deinitialisation functions
    • UCPD
      • UCPD Private Constants
      • UCPD Private Macros
      • UCPD Exported Init structure
      • UCPD Exported Constants
        • Get Flags Defines
        • IT Defines
        • Ordered sets value
        • Role Mode
        • Resistor value
        • ordered set configuration
        • CCx event
        • prescaler for UCPDCLK
        • CC pin enable
        • CC pin selection
        • Receiver mode
        • Type of Tx packet
        • Rx ordered set code detected
      • UCPD Exported Macros
        • Common Write and read registers Macros
      • UCPD Exported Functions
        • Configuration
          • CFG1 register
          • CFG2 register
        • CR register
        • Interrupt Management
        • Interrupt Clear
        • FLAG Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • USART
      • USART Private Variables
      • USART Private Macros
      • USART Exported Init structures
      • USART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • FIFO Threshold
        • Communication Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Oversampling
        • Clock Signal
        • Last Clock Pulse
        • Clock Phase
        • Clock Polarity
        • Clock Source Prescaler
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Autobaud Detection
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • IrDA Power
        • LIN Break Detection Length
        • Driver Enable Polarity
        • DMA Register Data
      • USART Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Helper
      • USART Exported Functions
        • Configuration functions
        • Configuration functions related to Irda feature
        • Configuration functions related to Smartcard feature
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to SPI Slave feature
        • Configuration functions related to LIN feature
        • Configuration functions related to Driver Enable feature
        • Advanced Configurations services
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • UTILS
      • UTILS Private functions
      • UTILS Private Constants
      • UTILS Private Macros
      • UTILS Exported structures
      • UTILS Exported Constants
        • HSE Bypass activation
        • PACKAGE TYPE
      • UTILS Exported Functions
        • DEVICE ELECTRONIC SIGNATURE
        • DELAY
        • SYSTEM
    • WWDG
      • WWDG Exported Constants
        • IT Defines
        • PRESCALER
      • WWDG Exported Macros
        • Common Write and read registers macros
      • WWDG Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
Generated on Mon Jun 6 2022 10:29:20 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal.c Source File

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stm32g0xx_hal.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal.c
00004   * @author  MCD Application Team
00005   * @brief   HAL module driver.
00006   *          This is the common part of the HAL initialization
00007   *
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * Copyright (c) 2018 STMicroelectronics.
00012   * All rights reserved.
00013   *
00014   * This software is licensed under terms that can be found in the LICENSE file
00015   * in the root directory of this software component.
00016   * If no LICENSE file comes with this software, it is provided AS-IS.
00017   *
00018   ******************************************************************************
00019   @verbatim
00020   ==============================================================================
00021                      ##### How to use this driver #####
00022   ==============================================================================
00023     [..]
00024     The common HAL driver contains a set of generic and common APIs that can be
00025     used by the PPP peripheral drivers and the user to start using the HAL.
00026     [..]
00027     The HAL contains two APIs categories:
00028          (+) Common HAL APIs
00029          (+) Services HAL APIs
00030
00031   @endverbatim
00032   ******************************************************************************
00033   */
00034
00035 /* Includes ------------------------------------------------------------------*/
00036 #include "stm32g0xx_hal.h"
00037
00038 /** @addtogroup STM32G0xx_HAL_Driver
00039   * @{
00040   */
00041
00042 /** @addtogroup HAL
00043   * @brief HAL module driver
00044   * @{
00045   */
00046
00047 #ifdef HAL_MODULE_ENABLED
00048
00049 /* Private typedef -----------------------------------------------------------*/
00050 /* Private define ------------------------------------------------------------*/
00051
00052 /** @defgroup HAL_Private_Constants HAL Private Constants
00053   * @{
00054   */
00055 /**
00056   * @brief STM32G0xx HAL Driver version number
00057   */
00058 #define __STM32G0xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
00059 #define __STM32G0xx_HAL_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
00060 #define __STM32G0xx_HAL_VERSION_SUB2   (0x05U) /*!< [15:8]  sub2 version */
00061 #define __STM32G0xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
00062 #define __STM32G0xx_HAL_VERSION         ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\
00063                                         |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\
00064                                         |(__STM32G0xx_HAL_VERSION_SUB2 << 8U )\
00065                                         |(__STM32G0xx_HAL_VERSION_RC))
00066
00067 #if defined(VREFBUF)
00068 #define VREFBUF_TIMEOUT_VALUE     10U   /*!<  10 ms */
00069 #endif /* VREFBUF */
00070
00071 /**
00072   * @}
00073   */
00074
00075 /* Private macro -------------------------------------------------------------*/
00076 /* Exported variables ---------------------------------------------------------*/
00077 /** @defgroup HAL_Exported_Variables HAL Exported Variables
00078   * @{
00079   */
00080 __IO uint32_t uwTick;
00081 uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
00082 HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
00083 /**
00084   * @}
00085   */
00086
00087 /* Private function prototypes -----------------------------------------------*/
00088 /* Exported functions --------------------------------------------------------*/
00089
00090 /** @addtogroup HAL_Exported_Functions
00091   * @{
00092   */
00093
00094 /** @addtogroup HAL_Exported_Functions_Group1
00095  *  @brief    HAL Initialization and Configuration functions
00096  *
00097 @verbatim
00098  ===============================================================================
00099            ##### HAL Initialization and Configuration functions #####
00100  ===============================================================================
00101     [..]  This section provides functions allowing to:
00102       (+) Initialize the Flash interface the NVIC allocation and initial time base
00103           clock configuration.
00104       (+) De-initialize common part of the HAL.
00105       (+) Configure the time base source to have 1ms time base with a dedicated
00106           Tick interrupt priority.
00107         (++) SysTick timer is used by default as source of time base, but user
00108              can eventually implement his proper time base source (a general purpose
00109              timer for example or other time source), keeping in mind that Time base
00110              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00111              handled in milliseconds basis.
00112         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00113              at the beginning of the program after reset by HAL_Init() or at any time
00114              when clock is configured, by HAL_RCC_ClockConfig().
00115         (++) Source of time base is configured  to generate interrupts at regular
00116              time intervals. Care must be taken if HAL_Delay() is called from a
00117              peripheral ISR process, the Tick interrupt line must have higher priority
00118             (numerically lower) than the peripheral interrupt. Otherwise the caller
00119             ISR process will be blocked.
00120        (++) functions affecting time base configurations are declared as __weak
00121              to make  override possible  in case of other  implementations in user file.
00122 @endverbatim
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  Configure the Flash prefetch and the Instruction cache,
00128   *         the time base source, NVIC and any required global low level hardware
00129   *         by calling the HAL_MspInit() callback function to be optionally defined in user file
00130   *         stm32g0xx_hal_msp.c.
00131   *
00132   * @note   HAL_Init() function is called at the beginning of program after reset and before
00133   *         the clock configuration.
00134   *
00135   * @note   In the default implementation the System Timer (Systick) is used as source of time base.
00136   *         The Systick configuration is based on HSI clock, as HSI is the clock
00137   *         used after a system Reset.
00138   *         Once done, time base tick starts incrementing: the tick variable counter is incremented
00139   *         each 1ms in the SysTick_Handler() interrupt handler.
00140   *
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_Init(void)
00144 {
00145   HAL_StatusTypeDef  status = HAL_OK;
00146
00147   /* Configure Flash prefetch, Instruction cache             */
00148   /* Default configuration at reset is:                      */
00149   /* - Prefetch disabled                                     */
00150   /* - Instruction cache enabled                             */
00151
00152 #if (INSTRUCTION_CACHE_ENABLE == 0U)
00153   __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00154 #endif /* INSTRUCTION_CACHE_ENABLE */
00155
00156 #if (PREFETCH_ENABLE != 0U)
00157   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
00158 #endif /* PREFETCH_ENABLE */
00159
00160   /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
00161   if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
00162   {
00163     status = HAL_ERROR;
00164   }
00165   else
00166   {
00167   /* Init the low level hardware */
00168   HAL_MspInit();
00169   }
00170
00171   /* Return function status */
00172   return status;
00173 }
00174
00175 /**
00176   * @brief  This function de-Initializes common part of the HAL and stops the source of time base.
00177   * @note   This function is optional.
00178   * @retval HAL status
00179   */
00180 HAL_StatusTypeDef HAL_DeInit(void)
00181 {
00182   /* Reset of all peripherals */
00183   __HAL_RCC_APB1_FORCE_RESET();
00184   __HAL_RCC_APB1_RELEASE_RESET();
00185
00186   __HAL_RCC_APB2_FORCE_RESET();
00187   __HAL_RCC_APB2_RELEASE_RESET();
00188
00189   __HAL_RCC_AHB_FORCE_RESET();
00190   __HAL_RCC_AHB_RELEASE_RESET();
00191
00192   __HAL_RCC_IOP_FORCE_RESET();
00193   __HAL_RCC_IOP_RELEASE_RESET();
00194
00195   /* De-Init the low level hardware */
00196   HAL_MspDeInit();
00197
00198   /* Return function status */
00199   return HAL_OK;
00200 }
00201
00202 /**
00203   * @brief  Initialize the MSP.
00204   * @retval None
00205   */
00206 __weak void HAL_MspInit(void)
00207 {
00208   /* NOTE : This function should not be modified, when the callback is needed,
00209             the HAL_MspInit could be implemented in the user file
00210    */
00211 }
00212
00213 /**
00214   * @brief  DeInitializes the MSP.
00215   * @retval None
00216   */
00217 __weak void HAL_MspDeInit(void)
00218 {
00219   /* NOTE : This function should not be modified, when the callback is needed,
00220             the HAL_MspDeInit could be implemented in the user file
00221    */
00222 }
00223
00224 /**
00225   * @brief This function configures the source of the time base:
00226   *        The time source is configured  to have 1ms time base with a dedicated
00227   *        Tick interrupt priority.
00228   * @note This function is called  automatically at the beginning of program after
00229   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00230   * @note In the default implementation, SysTick timer is the source of time base.
00231   *       It is used to generate interrupts at regular time intervals.
00232   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00233   *       The SysTick interrupt must have higher priority (numerically lower)
00234   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00235   *       The function is declared as __weak  to be overwritten  in case of other
00236   *       implementation  in user file.
00237   * @param TickPriority Tick interrupt priority.
00238   * @retval HAL status
00239   */
00240 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00241 {
00242   HAL_StatusTypeDef  status = HAL_OK;
00243
00244   /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
00245   if ((uint32_t)uwTickFreq != 0U)
00246   {
00247     /*Configure the SysTick to have interrupt in 1ms time basis*/
00248     if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
00249     {
00250       /* Configure the SysTick IRQ priority */
00251       if (TickPriority < (1UL << __NVIC_PRIO_BITS))
00252       {
00253         HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
00254         uwTickPrio = TickPriority;
00255       }
00256       else
00257       {
00258         status = HAL_ERROR;
00259       }
00260     }
00261     else
00262     {
00263       status = HAL_ERROR;
00264     }
00265   }
00266   else
00267   {
00268     status = HAL_ERROR;
00269   }
00270
00271   /* Return function status */
00272   return status;
00273 }
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @addtogroup HAL_Exported_Functions_Group2
00280  *  @brief    HAL Control functions
00281  *
00282 @verbatim
00283  ===============================================================================
00284                       ##### HAL Control functions #####
00285  ===============================================================================
00286     [..]  This section provides functions allowing to:
00287       (+) Provide a tick value in millisecond
00288       (+) Provide a blocking delay in millisecond
00289       (+) Suspend the time base source interrupt
00290       (+) Resume the time base source interrupt
00291       (+) Get the HAL API driver version
00292       (+) Get the device identifier
00293       (+) Get the device revision identifier
00294
00295 @endverbatim
00296   * @{
00297   */
00298
00299 /**
00300   * @brief This function is called to increment  a global variable "uwTick"
00301   *        used as application time base.
00302   * @note In the default implementation, this variable is incremented each 1ms
00303   *       in SysTick ISR.
00304   * @note This function is declared as __weak to be overwritten in case of other
00305   *      implementations in user file.
00306   * @retval None
00307   */
00308 __weak void HAL_IncTick(void)
00309 {
00310   uwTick += (uint32_t)uwTickFreq;
00311 }
00312
00313 /**
00314   * @brief Provides a tick value in millisecond.
00315   * @note This function is declared as __weak to be overwritten in case of other
00316   *       implementations in user file.
00317   * @retval tick value
00318   */
00319 __weak uint32_t HAL_GetTick(void)
00320 {
00321   return uwTick;
00322 }
00323
00324 /**
00325   * @brief This function returns a tick priority.
00326   * @retval tick priority
00327   */
00328 uint32_t HAL_GetTickPrio(void)
00329 {
00330   return uwTickPrio;
00331 }
00332
00333 /**
00334   * @brief Set new tick Freq.
00335   * @retval status
00336   */
00337 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
00338 {
00339   HAL_StatusTypeDef status  = HAL_OK;
00340   HAL_TickFreqTypeDef prevTickFreq;
00341   assert_param(IS_TICKFREQ(Freq));
00342
00343   if (uwTickFreq != Freq)
00344   {
00345     /* Back up uwTickFreq frequency */
00346     prevTickFreq = uwTickFreq;
00347
00348     /* Update uwTickFreq global variable used by HAL_InitTick() */
00349     uwTickFreq = Freq;
00350
00351     /* Apply the new tick Freq  */
00352     status = HAL_InitTick(uwTickPrio);
00353     if (status != HAL_OK)
00354     {
00355       /* Restore previous tick frequency */
00356       uwTickFreq = prevTickFreq;
00357     }
00358   }
00359
00360   return status;
00361 }
00362
00363 /**
00364   * @brief return tick frequency.
00365   * @retval tick period in Hz
00366   */
00367 HAL_TickFreqTypeDef HAL_GetTickFreq(void)
00368 {
00369   return uwTickFreq;
00370 }
00371
00372 /**
00373   * @brief This function provides minimum delay (in milliseconds) based
00374   *        on variable incremented.
00375   * @note In the default implementation , SysTick timer is the source of time base.
00376   *       It is used to generate interrupts at regular time intervals where uwTick
00377   *       is incremented.
00378   * @note This function is declared as __weak to be overwritten in case of other
00379   *       implementations in user file.
00380   * @param Delay  specifies the delay time length, in milliseconds.
00381   * @retval None
00382   */
00383 __weak void HAL_Delay(uint32_t Delay)
00384 {
00385   uint32_t tickstart = HAL_GetTick();
00386   uint32_t wait = Delay;
00387
00388   /* Add a freq to guarantee minimum wait */
00389   if (wait < HAL_MAX_DELAY)
00390   {
00391     wait += (uint32_t)(uwTickFreq);
00392   }
00393
00394   while ((HAL_GetTick() - tickstart) < wait)
00395   {
00396   }
00397 }
00398
00399 /**
00400   * @brief Suspend Tick increment.
00401   * @note In the default implementation , SysTick timer is the source of time base. It is
00402   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00403   *       is called, the SysTick interrupt will be disabled and so Tick increment
00404   *       is suspended.
00405   * @note This function is declared as __weak to be overwritten in case of other
00406   *       implementations in user file.
00407   * @retval None
00408   */
00409 __weak void HAL_SuspendTick(void)
00410 {
00411   /* Disable SysTick Interrupt */
00412   CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
00413 }
00414
00415 /**
00416   * @brief Resume Tick increment.
00417   * @note In the default implementation , SysTick timer is the source of time base. It is
00418   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00419   *       is called, the SysTick interrupt will be enabled and so Tick increment
00420   *       is resumed.
00421   * @note This function is declared as __weak to be overwritten in case of other
00422   *       implementations in user file.
00423   * @retval None
00424   */
00425 __weak void HAL_ResumeTick(void)
00426 {
00427   /* Enable SysTick Interrupt */
00428   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00429 }
00430
00431 /**
00432   * @brief  Returns the HAL revision
00433   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00434   */
00435 uint32_t HAL_GetHalVersion(void)
00436 {
00437   return __STM32G0xx_HAL_VERSION;
00438 }
00439
00440 /**
00441   * @brief  Returns the device revision identifier.
00442   * @retval Device revision identifier
00443   */
00444 uint32_t HAL_GetREVID(void)
00445 {
00446   return ((DBG->IDCODE & DBG_IDCODE_REV_ID) >> 16U);
00447 }
00448
00449 /**
00450   * @brief  Returns the device identifier.
00451   * @retval Device identifier
00452   */
00453 uint32_t HAL_GetDEVID(void)
00454 {
00455   return ((DBG->IDCODE) & DBG_IDCODE_DEV_ID);
00456 }
00457
00458 /**
00459   * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
00460   * @retval Device identifier
00461   */
00462 uint32_t HAL_GetUIDw0(void)
00463 {
00464   return (READ_REG(*((uint32_t *)UID_BASE)));
00465 }
00466
00467 /**
00468   * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
00469   * @retval Device identifier
00470   */
00471 uint32_t HAL_GetUIDw1(void)
00472 {
00473   return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
00474 }
00475
00476 /**
00477   * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
00478   * @retval Device identifier
00479   */
00480 uint32_t HAL_GetUIDw2(void)
00481 {
00482   return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
00483 }
00484
00485 /**
00486   * @}
00487   */
00488
00489 /** @addtogroup HAL_Exported_Functions_Group3
00490  *  @brief    HAL Debug functions
00491  *
00492 @verbatim
00493  ===============================================================================
00494                       ##### HAL Debug functions #####
00495  ===============================================================================
00496     [..]  This section provides functions allowing to:
00497       (+) Enable/Disable Debug module during STOP mode
00498       (+) Enable/Disable Debug module during STANDBY mode
00499
00500 @endverbatim
00501   * @{
00502   */
00503
00504 /**
00505   * @brief  Enable the Debug Module during STOP mode
00506   * @retval None
00507   */
00508 void HAL_DBGMCU_EnableDBGStopMode(void)
00509 {
00510   SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
00511 }
00512
00513 /**
00514   * @brief  Disable the Debug Module during STOP mode
00515   * @retval None
00516   */
00517 void HAL_DBGMCU_DisableDBGStopMode(void)
00518 {
00519   CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
00520 }
00521
00522 /**
00523   * @brief  Enable the Debug Module during STANDBY mode
00524   * @retval None
00525   */
00526 void HAL_DBGMCU_EnableDBGStandbyMode(void)
00527 {
00528   SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
00529 }
00530
00531 /**
00532   * @brief  Disable the Debug Module during STANDBY mode
00533   * @retval None
00534   */
00535 void HAL_DBGMCU_DisableDBGStandbyMode(void)
00536 {
00537   CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
00538 }
00539
00540 /**
00541   * @}
00542   */
00543
00544 /** @addtogroup HAL_Exported_Functions_Group4
00545  *  @brief    SYSCFG configuration functions
00546  *
00547 @verbatim
00548  ===============================================================================
00549                       ##### HAL SYSCFG configuration functions #####
00550  ===============================================================================
00551     [..]  This section provides functions allowing to:
00552       (+) Enable/Disable Pin remap
00553       (+) Configure the Voltage reference buffer
00554       (+) Enable/Disable the Voltage reference buffer
00555       (+) Enable/Disable the I/O analog switch voltage booster
00556       (+) Enable/Disable dead battery behavior(*)
00557       (+) Configure Clamping Diode on specific pins(*)
00558    (*) Feature not available on all devices
00559
00560 @endverbatim
00561   * @{
00562   */
00563 #if defined(VREFBUF)
00564 /**
00565   * @brief Configure the internal voltage reference buffer voltage scale.
00566   * @param  VoltageScaling specifies the output voltage to achieve
00567   *         This parameter can be one of the following values:
00568   *         @arg @ref SYSCFG_VREFBUF_VoltageScale
00569   * @retval None
00570   */
00571 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
00572 {
00573   /* Check the parameters */
00574   assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
00575
00576   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
00577 }
00578
00579 /**
00580   * @brief Configure the internal voltage reference buffer high impedance mode.
00581   * @param  Mode specifies the high impedance mode
00582   *          This parameter can be one of the following values:
00583   *          @arg @ref SYSCFG_VREFBUF_HighImpedance
00584   * @retval None
00585   */
00586 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
00587 {
00588   /* Check the parameters */
00589   assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
00590
00591   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
00592 }
00593
00594 /**
00595   * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
00596   * @note   VrefBuf voltage scale is calibrated in production for each device,
00597   *         using voltage scale 1. This calibration value is loaded
00598   *         as default trimming value at device power up.
00599   *         This trimming value can be fine tuned for voltage scales 0 and 1
00600   *         using this function.
00601   * @retval None
00602   */
00603 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
00604 {
00605   /* Check the parameters */
00606   assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
00607
00608   MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
00609 }
00610
00611 /**
00612   * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
00613   * @retval HAL_OK/HAL_TIMEOUT
00614   */
00615 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
00616 {
00617   uint32_t  tickstart;
00618
00619   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00620
00621   /* Get Start Tick*/
00622   tickstart = HAL_GetTick();
00623
00624   /* Wait for VRR bit  */
00625   while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U)
00626   {
00627     if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
00628     {
00629       return HAL_TIMEOUT;
00630     }
00631   }
00632
00633   return HAL_OK;
00634 }
00635
00636 /**
00637   * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
00638   *
00639   * @retval None
00640   */
00641 void HAL_SYSCFG_DisableVREFBUF(void)
00642 {
00643   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00644 }
00645 #endif /* VREFBUF */
00646
00647 /**
00648   * @brief  Enable the I/O analog switch voltage booster
00649   * @retval None
00650   */
00651 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
00652 {
00653   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00654 }
00655
00656 /**
00657   * @brief  Disable the I/O analog switch voltage booster
00658   * @retval None
00659   */
00660 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
00661 {
00662   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00663 }
00664
00665 /**
00666   * @brief  Enable the remap on PA11_PA12
00667   * @param  PinRemap specifies which pins have to be remapped
00668   *         This parameter can be any combination of the following values:
00669   *         @arg @ref SYSCFG_REMAP_PA11
00670   *         @arg @ref SYSCFG_REMAP_PA12
00671   * @retval None
00672   */
00673 void HAL_SYSCFG_EnableRemap(uint32_t PinRemap)
00674 {
00675   /* Check the parameter */
00676   assert_param(IS_HAL_REMAP_PIN(PinRemap));
00677   SET_BIT(SYSCFG->CFGR1, PinRemap);
00678 }
00679
00680 /**
00681   * @brief  Disable the remap on PA11_PA12
00682   * @param  PinRemap specifies which pins will behave normally
00683   *         This parameter can be any combination of the following values:
00684   *         @arg @ref SYSCFG_REMAP_PA11
00685   *         @arg @ref SYSCFG_REMAP_PA12
00686   * @retval None
00687   */
00688 void HAL_SYSCFG_DisableRemap(uint32_t PinRemap)
00689 {
00690   /* Check the parameter */
00691   assert_param(IS_HAL_REMAP_PIN(PinRemap));
00692   CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
00693 }
00694
00695 #if defined(SYSCFG_CDEN_SUPPORT)
00696 /**
00697   * @brief  Enable Clamping Diode on specified IO
00698   * @param  PinConfig specifies on which pins clamping Diode has to be enabled
00699   *         This parameter can be any combination of the following values:
00700   *         @arg @ref SYSCFG_ClampingDiode
00701   * @retval None
00702   */
00703 void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig)
00704 {
00705   /* Check the parameter */
00706   assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig));
00707   SET_BIT(SYSCFG->CFGR2, PinConfig);
00708 }
00709
00710 /**
00711   * @brief  Disable Clamping Diode on specified IO
00712   * @param  PinConfig specifies on which pins clamping Diode has to be disabled
00713   *         This parameter can be any combination of the following values:
00714   *         @arg @ref SYSCFG_ClampingDiode
00715   * @retval None
00716   */
00717 void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig)
00718 {
00719   /* Check the parameter */
00720   assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig));
00721   CLEAR_BIT(SYSCFG->CFGR2, PinConfig);
00722 }
00723 #endif /* SYSCFG_CDEN_SUPPORT */
00724
00725 #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
00726 /**
00727   * @brief  Strobe configuration of GPIO depending on UCPDx dead battery settings
00728   * @param  ConfigDeadBattery specifies on which pins to make effective or not Dead Battery sw configuration
00729   *         This parameter can be any combination of the following values:
00730   *         @arg @ref SYSCFG_UCPD1_STROBE
00731   *         @arg @ref SYSCFG_UCPD2_STROBE
00732   * @retval None
00733   */
00734 void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery)
00735 {
00736   assert_param(IS_SYSCFG_DBATT_CONFIG(ConfigDeadBattery));
00737
00738   /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
00739   MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), ConfigDeadBattery);
00740 }
00741 #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
00742 /**
00743   * @}
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 #endif /* HAL_MODULE_ENABLED */
00751 /**
00752   * @}
00753   */
00754
00755 /**
00756   * @}
00757   */
00758
00759
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal.h Source File

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stm32g0xx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the HAL
00006   *          module driver.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * Copyright (c) 2018 STMicroelectronics.
00011   * All rights reserved.
00012   *
00013   * This software is licensed under terms that can be found in the LICENSE file
00014   * in the root directory of this software component.
00015   * If no LICENSE file comes with this software, it is provided AS-IS.
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32G0xx_HAL_H
00022 #define STM32G0xx_HAL_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32g0xx_hal_conf.h"
00030
00031 /** @addtogroup STM32G0xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup HAL HAL
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup HAL_TICK_FREQ Tick Frequency
00041   * @{
00042   */
00043 typedef enum
00044 {
00045   HAL_TICK_FREQ_10HZ         = 100U,
00046   HAL_TICK_FREQ_100HZ        = 10U,
00047   HAL_TICK_FREQ_1KHZ         = 1U,
00048   HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
00049 } HAL_TickFreqTypeDef;
00050 /**
00051   * @}
00052   */
00053
00054 /* Exported constants --------------------------------------------------------*/
00055 /** @defgroup HAL_Exported_Constants HAL Exported Constants
00056   * @{
00057   */
00058
00059 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup SYSCFG_BootMode Boot Mode
00064   * @{
00065   */
00066 #define SYSCFG_BOOT_MAINFLASH          0x00000000U                      /*!< Main Flash memory mapped at 0x0000 0000   */
00067 #define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_CFGR1_MEM_MODE_0          /*!< System Flash memory mapped at 0x0000 0000 */
00068 #define SYSCFG_BOOT_SRAM               (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)  /*!< Embedded SRAM mapped at 0x0000 0000 */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup SYSCFG_Break Break
00075   * @{
00076   */
00077 #define SYSCFG_BREAK_SP                SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17 */
00078 #if defined(SYSCFG_CFGR2_PVDL)
00079 #define SYSCFG_BREAK_PVD               SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
00080 #endif /* SYSCFG_CFGR2_PVDL */
00081 #define SYSCFG_BREAK_LOCKUP            SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17 */
00082 #define SYSCFG_BREAK_ECC               SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17 */
00083 /**
00084   * @}
00085   */
00086
00087 #if defined(SYSCFG_CDEN_SUPPORT)
00088 /** @defgroup SYSCFG_ClampingDiode Clamping Diode
00089   * @{
00090   */
00091 #define SYSCFG_CDEN_PA1                SYSCFG_CFGR2_PA1_CDEN    /*!< Enables Clamping Diode on PA1 */
00092 #define SYSCFG_CDEN_PA3                SYSCFG_CFGR2_PA3_CDEN    /*!< Enables Clamping Diode on PA3 */
00093 #define SYSCFG_CDEN_PA5                SYSCFG_CFGR2_PA5_CDEN    /*!< Enables Clamping Diode on PA5 */
00094 #define SYSCFG_CDEN_PA6                SYSCFG_CFGR2_PA6_CDEN    /*!< Enables Clamping Diode on PA6 */
00095 #define SYSCFG_CDEN_PA13               SYSCFG_CFGR2_PA13_CDEN   /*!< Enables Clamping Diode on PA13 */
00096 #define SYSCFG_CDEN_PB0                SYSCFG_CFGR2_PB0_CDEN    /*!< Enables Clamping Diode on PB0 */
00097 #define SYSCFG_CDEN_PB1                SYSCFG_CFGR2_PB1_CDEN    /*!< Enables Clamping Diode on PB1 */
00098 #define SYSCFG_CDEN_PB2                SYSCFG_CFGR2_PB2_CDEN    /*!< Enables Clamping Diode on PB2 */
00099
00100 /**
00101   * @}
00102   */
00103 #endif /* SYSCFG_CDEN_SUPPORT */
00104
00105 /** @defgroup HAL_Pin_remapping Pin remapping
00106   * @{
00107   */
00108 /* Only available on cut2.0 */
00109 #define SYSCFG_REMAP_PA11                   SYSCFG_CFGR1_PA11_RMP       /*!< PA11 pad behaves digitally as PA9 GPIO pin */
00110 #define SYSCFG_REMAP_PA12                   SYSCFG_CFGR1_PA12_RMP       /*!< PA12 pad behaves digitally as PA10 GPIO pin */
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection
00116   * @{
00117   */
00118 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16     (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)    /*!< 00: Timer16 is selected as IR Modulation envelope source */
00119 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1    (SYSCFG_CFGR1_IR_MOD_0)                            /*!< 01: USART1 is selected as IR Modulation envelope source */
00120 #if defined(USART4)
00121 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4    (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART4 is selected as IR Modulation envelope source */
00122 #else
00123 #define HAL_SYSCFG_IRDA_ENV_SEL_USART2    (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART2 is selected as IR Modulation envelope source */
00124 #endif /* USART4 */
00125
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup HAL_IR_POL_SEL IR output polarity selection
00131   * @{
00132   */
00133 #define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED     0x00000000U                                /*!< 00: IR output polarity not inverted */
00134 #define HAL_SYSCFG_IRDA_POLARITY_INVERTED         SYSCFG_CFGR1_IR_POL                        /*!< 01: IR output polarity inverted */
00135
00136 /**
00137   * @}
00138   */
00139
00140 #if defined(VREFBUF)
00141 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
00142   * @{
00143   */
00144 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0x00000000U            /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V.
00145                                                                    This requires VDDA equal to or higher than 2.4 V.   */
00146 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V.
00147                                                                    This requires VDDA equal to or higher than 2.8 V.   */
00148
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
00154   * @{
00155   */
00156 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0x00000000U        /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
00157 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ    /*!< VREF_plus pin is high impedance */
00158
00159 /**
00160   * @}
00161   */
00162 #endif /* VREFBUF */
00163
00164 /** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO
00165   * @{
00166   */
00167
00168 /** @brief  Fast mode Plus driving capability on a specific GPIO
00169   */
00170 #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast mode Plus on PB6 */
00171 #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast mode Plus on PB7 */
00172 #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast mode Plus on PB8 */
00173 #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast mode Plus on PB9 */
00174 #define SYSCFG_FASTMODEPLUS_PA9        SYSCFG_CFGR1_I2C_PA9_FMP  /*!< Enable Fast mode Plus on PA9 */
00175 #define SYSCFG_FASTMODEPLUS_PA10       SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */
00176
00177 /**
00178  * @}
00179  */
00180
00181 /** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx
00182   * @{
00183   */
00184
00185 /** @brief  Fast mode Plus driving capability on a specific GPIO
00186   */
00187 #define SYSCFG_FASTMODEPLUS_I2C1       SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */
00188 #define SYSCFG_FASTMODEPLUS_I2C2       SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */
00189 #if  defined (I2C3)
00190 #define SYSCFG_FASTMODEPLUS_I2C3       SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast mode Plus on I2C3 */
00191 #endif /* I2C3 */
00192
00193 /**
00194  * @}
00195  */
00196 #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
00197 /** @defgroup SYSCFG_UCPDx_STROBE SYSCFG Dead Battery feature configuration
00198   * @{
00199   */
00200 #define SYSCFG_UCPD1_STROBE          SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 Dead battery sw configuration */
00201 #define SYSCFG_UCPD2_STROBE          SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 Dead battery sw configuration */
00202 /**
00203   * @}
00204   */
00205 #endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */
00206
00207 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
00208   * @brief ISR Wrapper
00209   * @{
00210   */
00211 #define HAL_SYSCFG_ITLINE0                           0x00000000U /*!< Internal define for macro handling */
00212 #define HAL_SYSCFG_ITLINE1                           0x00000001U /*!< Internal define for macro handling */
00213 #define HAL_SYSCFG_ITLINE2                           0x00000002U /*!< Internal define for macro handling */
00214 #define HAL_SYSCFG_ITLINE3                           0x00000003U /*!< Internal define for macro handling */
00215 #define HAL_SYSCFG_ITLINE4                           0x00000004U /*!< Internal define for macro handling */
00216 #define HAL_SYSCFG_ITLINE5                           0x00000005U /*!< Internal define for macro handling */
00217 #define HAL_SYSCFG_ITLINE6                           0x00000006U /*!< Internal define for macro handling */
00218 #define HAL_SYSCFG_ITLINE7                           0x00000007U /*!< Internal define for macro handling */
00219 #define HAL_SYSCFG_ITLINE8                           0x00000008U /*!< Internal define for macro handling */
00220 #define HAL_SYSCFG_ITLINE9                           0x00000009U /*!< Internal define for macro handling */
00221 #define HAL_SYSCFG_ITLINE10                          0x0000000AU /*!< Internal define for macro handling */
00222 #define HAL_SYSCFG_ITLINE11                          0x0000000BU /*!< Internal define for macro handling */
00223 #define HAL_SYSCFG_ITLINE12                          0x0000000CU /*!< Internal define for macro handling */
00224 #define HAL_SYSCFG_ITLINE13                          0x0000000DU /*!< Internal define for macro handling */
00225 #define HAL_SYSCFG_ITLINE14                          0x0000000EU /*!< Internal define for macro handling */
00226 #define HAL_SYSCFG_ITLINE15                          0x0000000FU /*!< Internal define for macro handling */
00227 #define HAL_SYSCFG_ITLINE16                          0x00000010U /*!< Internal define for macro handling */
00228 #define HAL_SYSCFG_ITLINE17                          0x00000011U /*!< Internal define for macro handling */
00229 #define HAL_SYSCFG_ITLINE18                          0x00000012U /*!< Internal define for macro handling */
00230 #define HAL_SYSCFG_ITLINE19                          0x00000013U /*!< Internal define for macro handling */
00231 #define HAL_SYSCFG_ITLINE20                          0x00000014U /*!< Internal define for macro handling */
00232 #define HAL_SYSCFG_ITLINE21                          0x00000015U /*!< Internal define for macro handling */
00233 #define HAL_SYSCFG_ITLINE22                          0x00000016U /*!< Internal define for macro handling */
00234 #define HAL_SYSCFG_ITLINE23                          0x00000017U /*!< Internal define for macro handling */
00235 #define HAL_SYSCFG_ITLINE24                          0x00000018U /*!< Internal define for macro handling */
00236 #define HAL_SYSCFG_ITLINE25                          0x00000019U /*!< Internal define for macro handling */
00237 #define HAL_SYSCFG_ITLINE26                          0x0000001AU /*!< Internal define for macro handling */
00238 #define HAL_SYSCFG_ITLINE27                          0x0000001BU /*!< Internal define for macro handling */
00239 #define HAL_SYSCFG_ITLINE28                          0x0000001CU /*!< Internal define for macro handling */
00240 #define HAL_SYSCFG_ITLINE29                          0x0000001DU /*!< Internal define for macro handling */
00241 #define HAL_SYSCFG_ITLINE30                          0x0000001EU /*!< Internal define for macro handling */
00242 #define HAL_SYSCFG_ITLINE31                          0x0000001FU /*!< Internal define for macro handling */
00243
00244 #define HAL_ITLINE_WWDG           ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)          /*!< WWDG has expired .... */
00245 #if defined (PWR_PVD_SUPPORT)
00246 #define HAL_ITLINE_PVDOUT         ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)        /*!< Power voltage detection Interrupt .... */
00247 #endif /* PWR_PVD_SUPPORT */
00248 #if defined (PWR_PVM_SUPPORT)
00249 #define HAL_ITLINE_PVMOUT         ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT)        /*!< Power voltage monitor Interrupt .... */
00250 #endif /* PWR_PVM_SUPPORT */
00251 #define HAL_ITLINE_RTC            ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC)           /*!< RTC -> exti[19] Interrupt */
00252 #define HAL_ITLINE_TAMPER         ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER)        /*!< TAMPER -> exti[21] interrupt .... */
00253 #define HAL_ITLINE_FLASH_ECC      ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC)     /*!< Flash ECC Interrupt */
00254 #define HAL_ITLINE_FLASH_ITF      ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)     /*!< Flash ITF Interrupt */
00255 #define HAL_ITLINE_CLK_CTRL       ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)      /*!< CLK Control Interrupt */
00256 #if defined (CRS)
00257 #define HAL_ITLINE_CRS            ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)           /*!< CRS Interrupt */
00258 #endif /*CRS  */
00259 #define HAL_ITLINE_EXTI0          ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)         /*!< External Interrupt 0 */
00260 #define HAL_ITLINE_EXTI1          ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)         /*!< External Interrupt 1 */
00261 #define HAL_ITLINE_EXTI2          ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)         /*!< External Interrupt 2 */
00262 #define HAL_ITLINE_EXTI3          ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)         /*!< External Interrupt 3 */
00263 #define HAL_ITLINE_EXTI4          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)         /*!< EXTI4 Interrupt */
00264 #define HAL_ITLINE_EXTI5          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)         /*!< EXTI5 Interrupt */
00265 #define HAL_ITLINE_EXTI6          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)         /*!< EXTI6 Interrupt */
00266 #define HAL_ITLINE_EXTI7          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)         /*!< EXTI7 Interrupt */
00267 #define HAL_ITLINE_EXTI8          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)         /*!< EXTI8 Interrupt */
00268 #define HAL_ITLINE_EXTI9          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)         /*!< EXTI9 Interrupt */
00269 #define HAL_ITLINE_EXTI10         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)        /*!< EXTI10 Interrupt */
00270 #define HAL_ITLINE_EXTI11         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)        /*!< EXTI11 Interrupt */
00271 #define HAL_ITLINE_EXTI12         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)        /*!< EXTI12 Interrupt */
00272 #define HAL_ITLINE_EXTI13         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)        /*!< EXTI13 Interrupt */
00273 #define HAL_ITLINE_EXTI14         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)        /*!< EXTI14 Interrupt */
00274 #define HAL_ITLINE_EXTI15         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)        /*!< EXTI15 Interrupt */
00275 #if defined (UCPD1)
00276 #define HAL_ITLINE_UCPD1          ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1)         /*!< UCPD1 Interrupt */
00277 #endif /* UCPD1 */
00278 #if defined (UCPD2)
00279 #define HAL_ITLINE_UCPD2          ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2)         /*!< UCPD2 Interrupt */
00280 #endif /* UCPD2 */
00281 #if defined (STM32G0C1xx) || defined (STM32G0B1xx) || defined (STM32G0B0xx)
00282 #define HAL_ITLINE_USB            ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB)           /*!< USB Interrupt */
00283 #endif /* STM32G0C1xx) || STM32G0B1xx) || STM32G0B0xx */
00284 #define HAL_ITLINE_DMA1_CH1       ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)      /*!< DMA1 Channel 1 Interrupt */
00285 #define HAL_ITLINE_DMA1_CH2       ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)    /*!< DMA1 Channel 2 Interrupt */
00286 #define HAL_ITLINE_DMA1_CH3       ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)    /*!< DMA1 Channel 3 Interrupt */
00287 #define HAL_ITLINE_DMAMUX1        ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1)     /*!< DMAMUX1 Interrupt */
00288 #define HAL_ITLINE_DMA1_CH4       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)    /*!< DMA1 Channel 4 Interrupt */
00289 #define HAL_ITLINE_DMA1_CH5       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)    /*!< DMA1 Channel 5 Interrupt */
00290 #if defined(DMA1_Channel7)
00291 #define HAL_ITLINE_DMA1_CH6       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)    /*!< DMA1 Channel 6 Interrupt */
00292 #define HAL_ITLINE_DMA1_CH7       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)    /*!< DMA1 Channel 7 Interrupt */
00293 #endif /* DMA1_Channel7 */
00294 #if defined (DMA2)
00295 #define HAL_ITLINE_DMA2_CH1       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1)    /*!< DMA2 Channel 1 Interrupt */
00296 #define HAL_ITLINE_DMA2_CH2       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2)    /*!< DMA2 Channel 2 Interrupt */
00297 #define HAL_ITLINE_DMA2_CH3       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)    /*!< DMA2 Channel 3 Interrupt */
00298 #define HAL_ITLINE_DMA2_CH4       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)    /*!< DMA2 Channel 4 Interrupt */
00299 #define HAL_ITLINE_DMA2_CH5       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)    /*!< DMA2 Channel 5 Interrupt */
00300 #endif /* DMA2 */
00301 #define HAL_ITLINE_ADC            ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)         /*!< ADC Interrupt */
00302 #if defined (COMP1)
00303 #define HAL_ITLINE_COMP1          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)       /*!< COMP1 Interrupt -> exti[17] */
00304 #endif /* COMP1 */
00305 #if defined (COMP2)
00306 #define HAL_ITLINE_COMP2          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)       /*!< COMP2 Interrupt -> exti[18] */
00307 #endif /* COMP2 */
00308 #if defined (COMP3)
00309 #define HAL_ITLINE_COMP3          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3)       /*!< COMP3 Interrupt -> exti[1x] */
00310 #endif /* COMP3 */
00311 #define HAL_ITLINE_TIM1_BRK       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)    /*!< TIM1 BRK Interrupt */
00312 #define HAL_ITLINE_TIM1_UPD       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)    /*!< TIM1 UPD Interrupt */
00313 #define HAL_ITLINE_TIM1_TRG       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)    /*!< TIM1 TRG Interrupt */
00314 #define HAL_ITLINE_TIM1_CCU       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)    /*!< TIM1 CCU Interrupt */
00315 #define HAL_ITLINE_TIM1_CC        ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)     /*!< TIM1 CC Interrupt */
00316 #if defined (TIM2)
00317 #define HAL_ITLINE_TIM2           ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)    /*!< TIM2 Interrupt */
00318 #endif /* TIM2 */
00319 #define HAL_ITLINE_TIM3           ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)    /*!< TIM3 Interrupt */
00320 #if defined (TIM4)
00321 #define HAL_ITLINE_TIM4           ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB)    /*!< TIM4 Interrupt */
00322 #endif /* TIM4 */
00323 #if defined(TIM6)
00324 #define HAL_ITLINE_TIM6           ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)    /*!< TIM6 Interrupt */
00325 #endif /* TIM6 */
00326 #if defined(DAC1)
00327 #define HAL_ITLINE_DAC            ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)         /*!< DAC Interrupt */
00328 #endif /* DAC1 */
00329 #if defined(LPTIM1)
00330 #define HAL_ITLINE_LPTIM1         ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB)  /*!< LPTIM1 Interrupt -> exti[29] */
00331 #endif /* LPTIM1 */
00332 #if defined(TIM7)
00333 #define HAL_ITLINE_TIM7           ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)    /*!< TIM7 Interrupt */
00334 #endif /* TIM7 */
00335 #if defined(LPTIM2)
00336 #define HAL_ITLINE_LPTIM2         ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB)  /*!< LPTIM2 Interrupt -> exti[30] */
00337 #endif /* LPTIM2 */
00338 #define HAL_ITLINE_TIM14          ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)   /*!< TIM14 Interrupt */
00339 #if defined(TIM15)
00340 #define HAL_ITLINE_TIM15          ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)   /*!< TIM15 Interrupt */
00341 #endif /* TIM15 */
00342 #define HAL_ITLINE_TIM16          ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)   /*!< TIM16 Interrupt */
00343 #if defined (FDCAN1) || defined (FDCAN2)
00344 #define HAL_ITLINE_FDCAN1_IT0     ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0)  /*!< FDCAN1_IT0 Interrupt */
00345 #define HAL_ITLINE_FDCAN2_IT0     ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0)  /*!< FDCAN2_IT0 Interrupt */
00346 #endif /* FDCAN1 || FDCAN2 */
00347 #define HAL_ITLINE_TIM17          ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)   /*!< TIM17 Interrupt */
00348 #if defined (FDCAN1) || defined (FDCAN2)
00349 #define HAL_ITLINE_FDCAN1_IT1     ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1)  /*!< FDCAN1_IT1 Interrupt */
00350 #define HAL_ITLINE_FDCAN2_IT1     ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1)  /*!< FDCAN2_IT1 Interrupt */
00351 #endif /* FDCAN1 || FDCAN2 */
00352 #define HAL_ITLINE_I2C1           ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)    /*!< I2C1 Interrupt -> exti[23] */
00353 #define HAL_ITLINE_I2C2           ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)    /*!< I2C2 Interrupt -> exti[24] */
00354 #if defined (I2C3)
00355 #define HAL_ITLINE_I2C3           ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB)    /*!< I2C3 Interrupt -> exti[22] */
00356 #endif /* I2C3 */
00357 #define HAL_ITLINE_SPI1           ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)        /*!< SPI1 Interrupt  */
00358 #define HAL_ITLINE_SPI2           ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)        /*!< SPI2 Interrupt */
00359 #if defined (SPI3)
00360 #define HAL_ITLINE_SPI3           ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3)        /*!< SPI3 Interrupt */
00361 #endif /* SPI3 */
00362 #define HAL_ITLINE_USART1         ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)  /*!< USART1 GLB Interrupt -> exti[25] */
00363 #define HAL_ITLINE_USART2         ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)  /*!< USART2 GLB Interrupt -> exti[26] */
00364 #if defined (LPUART2)
00365 #define HAL_ITLINE_LPUART2        ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB)  /*!< LPUART2 GLB Interrupt -> exti[26] */
00366 #endif /* LPUART2 */
00367 #if defined(USART3)
00368 #define HAL_ITLINE_USART3         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)  /*!< USART3 Interrupt .... */
00369 #endif /* USART3 */
00370 #if defined(USART4)
00371 #define HAL_ITLINE_USART4         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)  /*!< USART4 Interrupt .... */
00372 #endif /* USART4 */
00373 #if defined (LPUART1)
00374 #define HAL_ITLINE_LPUART1        ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/
00375 #endif /* LPUART1 */
00376 #if defined (USART5)
00377 #define HAL_ITLINE_USART5         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)  /*!< USART5 Interrupt .... */
00378 #endif /* USART5 */
00379 #if defined (USART6)
00380 #define HAL_ITLINE_USART6         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)  /*!< USART6 Interrupt .... */
00381 #endif /* USART6 */
00382 #if defined (CEC)
00383 #define HAL_ITLINE_CEC            ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)         /*!< CEC Interrupt -> exti[27] */
00384 #endif /* CEC */
00385 #if defined (RNG)
00386 #define HAL_ITLINE_RNG            ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG)         /*!< RNG Interrupt */
00387 #endif /* RNG */
00388 #if defined (AES)
00389 #define HAL_ITLINE_AES            ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES)         /*!< AES Interrupt */
00390 #endif /* AES */
00391 /**
00392   * @}
00393   */
00394
00395 /**
00396   * @}
00397   */
00398
00399 /**
00400   * @}
00401   */
00402
00403 /* Exported macros -----------------------------------------------------------*/
00404 /** @defgroup HAL_Exported_Macros HAL Exported Macros
00405   * @{
00406   */
00407
00408 /** @defgroup DBG_Exported_Macros DBG Exported Macros
00409   * @{
00410   */
00411
00412 /** @brief  Freeze and Unfreeze Peripherals in Debug mode
00413   */
00414 #if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
00415 #define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
00416 #define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
00417 #endif /* DBG_APB_FZ1_DBG_TIM2_STOP */
00418
00419 #if defined(DBG_APB_FZ1_DBG_TIM3_STOP)
00420 #define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
00421 #define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
00422 #endif /* DBG_APB_FZ1_DBG_TIM3_STOP */
00423
00424 #if defined(DBG_APB_FZ1_DBG_TIM4_STOP)
00425 #define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
00426 #define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
00427 #endif /* DBG_APB_FZ1_DBG_TIM4_STOP */
00428
00429 #if defined(DBG_APB_FZ1_DBG_TIM6_STOP)
00430 #define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
00431 #define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
00432 #endif /* DBG_APB_FZ1_DBG_TIM6_STOP */
00433
00434 #if defined(DBG_APB_FZ1_DBG_TIM7_STOP)
00435 #define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
00436 #define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
00437 #endif /* DBG_APB_FZ1_DBG_TIM7_STOP */
00438
00439 #if defined(DBG_APB_FZ1_DBG_RTC_STOP)
00440 #define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
00441 #define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
00442 #endif /* DBG_APB_FZ1_DBG_RTC_STOP */
00443
00444 #if defined(DBG_APB_FZ1_DBG_WWDG_STOP)
00445 #define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
00446 #define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
00447 #endif /* DBG_APB_FZ1_DBG_WWDG_STOP */
00448
00449 #if defined(DBG_APB_FZ1_DBG_IWDG_STOP)
00450 #define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
00451 #define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
00452 #endif /* DBG_APB_FZ1_DBG_IWDG_STOP */
00453
00454 #if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
00455 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
00456 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
00457 #endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */
00458
00459 #if defined(DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
00460 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
00461 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
00462 #endif /* DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP */
00463
00464 #if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP)
00465 #define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
00466 #define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
00467 #endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */
00468
00469 #if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP)
00470 #define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
00471 #define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
00472 #endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */
00473
00474 #if defined(DBG_APB_FZ2_DBG_TIM1_STOP)
00475 #define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
00476 #define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
00477 #endif /* DBG_APB_FZ2_DBG_TIM1_STOP */
00478
00479 #if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
00480 #define __HAL_DBGMCU_FREEZE_TIM14()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
00481 #define __HAL_DBGMCU_UNFREEZE_TIM14()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
00482 #endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
00483
00484 #if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
00485 #define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
00486 #define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
00487 #endif /* DBG_APB_FZ2_DBG_TIM15_STOP */
00488
00489 #if defined(DBG_APB_FZ2_DBG_TIM16_STOP)
00490 #define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
00491 #define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
00492 #endif /* DBG_APB_FZ2_DBG_TIM16_STOP */
00493
00494 #if defined(DBG_APB_FZ2_DBG_TIM17_STOP)
00495 #define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
00496 #define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
00497 #endif /* DBG_APB_FZ2_DBG_TIM17_STOP */
00498
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
00504   * @{
00505   */
00506
00507 /**
00508   * @brief ISR wrapper check
00509   * @note Allow to determine interrupt source per line.
00510   */
00511 #define __HAL_GET_PENDING_IT(__SOURCE__)     (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
00512
00513 /** @brief  Main Flash memory mapped at 0x00000000
00514   */
00515 #define __HAL_SYSCFG_REMAPMEMORY_FLASH()     CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
00516
00517 /** @brief  System Flash memory mapped at 0x00000000
00518   */
00519 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
00520
00521 /** @brief  Embedded SRAM mapped at 0x00000000
00522   */
00523 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
00524   MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))
00525
00526 /**
00527   * @brief  Return the boot mode as configured by user.
00528   * @retval The boot mode as configured by user. The returned value can be one
00529   *         of the following values @ref SYSCFG_BootMode
00530   */
00531 #define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
00532
00533 /** @brief  SYSCFG Break ECC lock.
00534   *         Enable and lock the connection of Flash ECC error connection to TIM1 Break input.
00535   * @note   The selected configuration is locked and can be unlocked only by system reset.
00536   */
00537 #define __HAL_SYSCFG_BREAK_ECC_LOCK()           SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
00538
00539
00540 /** @brief  SYSCFG Break Cortex-M0+ Lockup lock.
00541   *         Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
00542   * @note   The selected configuration is locked and can be unlocked only by system reset.
00543   */
00544 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
00545
00546 #if defined(SYSCFG_CFGR2_PVDL)
00547 /** @brief  SYSCFG Break PVD lock.
00548   *         Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register
00549   * @note   The selected configuration is locked and can be unlocked only by system reset
00550   */
00551 #define __HAL_SYSCFG_BREAK_PVD_LOCK()           SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
00552 #endif /* SYSCFG_CFGR2_PVDL */
00553
00554 /** @brief  SYSCFG Break SRAM PARITY lock
00555   *         Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17
00556   * @note   The selected configuration is locked and can only be unlocked by system reset
00557   */
00558 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK()    SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
00559
00560 /** @brief  Parity check on RAM disable macro
00561   * @note   Disabling the parity check on RAM locks the configuration bit.
00562   *         To re-enable the parity check on RAM perform a system reset.
00563   */
00564 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE()  (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
00565
00566 /** @brief  Set the PEF bit to clear the SRAM Parity Error Flag.
00567   */
00568 #define __HAL_SYSCFG_CLEAR_FLAG()               SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
00569
00570 /** @brief  Fast-mode Plus driving capability enable/disable macros
00571   * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
00572   */
00573 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00574                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00575                                                                }while(0U)
00576
00577 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00578                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00579                                                                }while(0U)
00580
00581 #if defined(SYSCFG_CDEN_SUPPORT)
00582 /** @brief  Clamping Diode on specific pins enable/disable macros
00583   * @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode
00584   */
00585 #define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__)  do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
00586                                                                 SET_BIT(SYSCFG->CFGR2, (__PIN__));\
00587                                                                }while(0U)
00588
00589 #define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
00590                                                                 CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
00591                                                                }while(0U)
00592 #endif /* SYSCFG_CDEN_SUPPORT */
00593
00594 /** @brief  ISR wrapper check
00595   * @note Allow to determine interrupt source per line.
00596   */
00597 #define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__)  \
00598   (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU))
00599
00600 /** @brief  selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
00601   * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL
00602   */
00603 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)  do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\
00604                                                          CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\
00605                                                          SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\
00606                                                         }while(0U)
00607
00608 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()  ((SYSCFG->CFGR1) & 0x000000C0U)
00609
00610 /** @brief  IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register
00611   * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL
00612   */
00613 #define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__)  do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\
00614                                                                 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\
00615                                                                 SET_BIT(SYSCFG->CFGR1,(__SEL__));\
00616                                                               }while(0U)
00617
00618 /**
00619   * @brief  Return the IROut Polarity mode as configured by user.
00620   * @retval The IROut polarity as configured by user. The returned value can be one
00621   *         of @ref HAL_IR_POL_SEL
00622   */
00623 #define __HAL_SYSCFG_GET_POLARITY()           READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
00624
00625 /** @brief  Break input to TIM1/15/16/17 capability enable/disable macros
00626   * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break
00627   */
00628 #define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__)     do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
00629                                                      SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
00630                                                     }while(0U)
00631
00632 #define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__)    do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
00633                                                      CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
00634                                                     }while(0U)
00635
00636
00637 /**
00638   * @}
00639   */
00640
00641 /**
00642   * @}
00643   */
00644
00645 /* Private macros ------------------------------------------------------------*/
00646 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
00647   * @{
00648   */
00649 #if defined (PWR_PVD_SUPPORT)
00650 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP)        || \
00651                                             ((__CONFIG__) == SYSCFG_BREAK_PVD)       || \
00652                                             ((__CONFIG__) == SYSCFG_BREAK_ECC)       || \
00653                                             ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
00654 #else
00655 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP)        || \
00656                                             ((__CONFIG__) == SYSCFG_BREAK_ECC)       || \
00657                                             ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
00658 #endif /* PWR_PVD_SUPPORT */
00659
00660 #if defined(SYSCFG_CDEN_SUPPORT)
00661 #define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1)  == SYSCFG_CDEN_PA1)  || \
00662                                           (((__PIN__) & SYSCFG_CDEN_PA3)  == SYSCFG_CDEN_PA3)  || \
00663                                           (((__PIN__) & SYSCFG_CDEN_PA5)  == SYSCFG_CDEN_PA5)  || \
00664                                           (((__PIN__) & SYSCFG_CDEN_PA6)  == SYSCFG_CDEN_PA6)  || \
00665                                           (((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \
00666                                           (((__PIN__) & SYSCFG_CDEN_PB0)  == SYSCFG_CDEN_PB0)  || \
00667                                           (((__PIN__) & SYSCFG_CDEN_PB1)  == SYSCFG_CDEN_PB1)  || \
00668                                           (((__PIN__) & SYSCFG_CDEN_PB2)  == SYSCFG_CDEN_PB2))
00669 #endif /* SYSCFG_CDEN_SUPPORT */
00670
00671 #if defined (USART4)
00672 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
00673                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)  || \
00674                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
00675 #else
00676 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
00677                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)  || \
00678                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
00679 #endif /* USART4 */
00680 #define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED)   || \
00681                                            ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
00682
00683 #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
00684 #define IS_SYSCFG_DBATT_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \
00685                                             ((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \
00686                                             ((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE)))
00687 #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
00688 #if defined(VREFBUF)
00689 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
00690                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
00691
00692 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
00693                                                       ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
00694
00695 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
00696 #endif /* VREFBUF */
00697
00698 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9)  == SYSCFG_FASTMODEPLUS_PA9)  || \
00699                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
00700                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
00701                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
00702                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
00703                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))
00704
00705 #define IS_HAL_REMAP_PIN(RMP)               (((RMP) == SYSCFG_REMAP_PA11) || \
00706                                              ((RMP) == SYSCFG_REMAP_PA12) || \
00707                                              ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12)))
00708 /**
00709   * @}
00710   */
00711
00712 /** @defgroup HAL_Private_Macros HAL Private Macros
00713   * @{
00714   */
00715 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
00716                            ((FREQ) == HAL_TICK_FREQ_100HZ) || \
00717                            ((FREQ) == HAL_TICK_FREQ_1KHZ))
00718 /**
00719   * @}
00720   */
00721 /* Exported functions --------------------------------------------------------*/
00722
00723 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00724   * @{
00725   */
00726
00727 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
00728   * @{
00729   */
00730
00731 /* Initialization and Configuration functions  ******************************/
00732 HAL_StatusTypeDef HAL_Init(void);
00733 HAL_StatusTypeDef HAL_DeInit(void);
00734 void HAL_MspInit(void);
00735 void HAL_MspDeInit(void);
00736 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
00737
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00743   * @{
00744   */
00745
00746 /* Peripheral Control functions  ************************************************/
00747 void HAL_IncTick(void);
00748 void HAL_Delay(uint32_t Delay);
00749 uint32_t HAL_GetTick(void);
00750 uint32_t HAL_GetTickPrio(void);
00751 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
00752 HAL_TickFreqTypeDef HAL_GetTickFreq(void);
00753 void HAL_SuspendTick(void);
00754 void HAL_ResumeTick(void);
00755 uint32_t HAL_GetHalVersion(void);
00756 uint32_t HAL_GetREVID(void);
00757 uint32_t HAL_GetDEVID(void);
00758 uint32_t HAL_GetUIDw0(void);
00759 uint32_t HAL_GetUIDw1(void);
00760 uint32_t HAL_GetUIDw2(void);
00761
00762 /**
00763   * @}
00764   */
00765
00766 /** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions
00767   * @{
00768   */
00769
00770 /* DBGMCU Peripheral Control functions  *****************************************/
00771 void HAL_DBGMCU_EnableDBGStopMode(void);
00772 void HAL_DBGMCU_DisableDBGStopMode(void);
00773 void HAL_DBGMCU_EnableDBGStandbyMode(void);
00774 void HAL_DBGMCU_DisableDBGStandbyMode(void);
00775
00776 /**
00777   * @}
00778   */
00779
00780 /* Exported variables ---------------------------------------------------------*/
00781 /** @addtogroup HAL_Exported_Variables
00782   * @{
00783   */
00784 extern __IO uint32_t uwTick;
00785 extern uint32_t uwTickPrio;
00786 extern HAL_TickFreqTypeDef uwTickFreq;
00787 /**
00788   * @}
00789   */
00790
00791 /** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions
00792   * @{
00793   */
00794
00795 /* SYSCFG Control functions  ****************************************************/
00796
00797 #if defined(VREFBUF)
00798 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
00799 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
00800 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
00801 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
00802 void HAL_SYSCFG_DisableVREFBUF(void);
00803 #endif /* VREFBUF */
00804
00805 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
00806 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
00807 void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
00808 void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
00809 #if defined(SYSCFG_CDEN_SUPPORT)
00810 void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig);
00811 void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig);
00812 #endif /* SYSCFG_CDEN_SUPPORT */
00813 #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
00814 void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery);
00815 #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
00816 /**
00817   * @}
00818   */
00819
00820 /**
00821   * @}
00822   */
00823
00824 /**
00825   * @}
00826   */
00827
00828 /**
00829   * @}
00830   */
00831
00832 #ifdef __cplusplus
00833 }
00834 #endif
00835
00836 #endif /* STM32G0xx_HAL_H */
00837
00838
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_adc.c Source File

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stm32g0xx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_adc.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Converter (ADC)
00007   *          peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *          Other functions (extended functions) are available in file
00012   *          "stm32g0xx_hal_adc_ex.c".
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2018 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                      ##### ADC peripheral features #####
00028   ==============================================================================
00029   [..]
00030   (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
00031
00032   (+) Interrupt generation at the end of regular conversion and in case of
00033       analog watchdog or overrun events.
00034
00035   (+) Single and continuous conversion modes.
00036
00037   (+) Scan mode for conversion of several channels sequentially.
00038
00039   (+) Data alignment with in-built data coherency.
00040
00041   (+) Programmable sampling time (common to group of channels)
00042
00043   (+) External trigger (timer or EXTI) with configurable polarity
00044
00045   (+) DMA request generation for transfer of conversions data of regular group.
00046
00047   (+) ADC calibration
00048
00049   (+) ADC conversion of regular group.
00050
00051   (+) ADC supply requirements: 1.62 V to 3.6 V.
00052
00053   (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
00054       Vdda or to an external voltage reference).
00055
00056
00057                      ##### How to use this driver #####
00058   ==============================================================================
00059     [..]
00060
00061      *** Configuration of top level parameters related to ADC ***
00062      ============================================================
00063      [..]
00064
00065     (#) Enable the ADC interface
00066         (++) As prerequisite, ADC clock must be configured at RCC top level.
00067              Caution: On STM32G0, ADC clock frequency max is 35MHz (refer
00068                       to device datasheet).
00069                       Therefore, ADC clock source from RCC and ADC clock
00070                       prescaler must be configured to remain below
00071                       this maximum frequency.
00072
00073         (++) Two clock settings are mandatory:
00074              (+++) ADC clock (core clock, also possibly conversion clock).
00075
00076              (+++) ADC clock (conversions clock).
00077                    Four possible clock sources: synchronous clock from APB clock (same as ADC core clock)
00078                    or asynchronous clock from RCC level: SYSCLK, HSI16, PLLPCLK.
00079
00080              (+++) Example:
00081                    Into HAL_ADC_MspInit() (recommended code location) or with
00082                    other device clock parameters configuration:
00083                (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory: core clock)
00084
00085         (++) ADC clock source and clock prescaler are configured at ADC level with
00086              parameter "ClockPrescaler" using function HAL_ADC_Init().
00087
00088     (#) ADC pins configuration
00089          (++) Enable the clock for the ADC GPIOs
00090               using macro __HAL_RCC_GPIOx_CLK_ENABLE()
00091          (++) Configure these ADC pins in analog mode
00092               using function HAL_GPIO_Init()
00093
00094     (#) Optionally, in case of usage of ADC with interruptions:
00095          (++) Configure the NVIC for ADC
00096               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00097          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00098               into the function of corresponding ADC interruption vector
00099               ADCx_IRQHandler().
00100
00101     (#) Optionally, in case of usage of DMA:
00102          (++) Configure the DMA (DMA channel, mode normal or circular, ...)
00103               using function HAL_DMA_Init().
00104          (++) Configure the NVIC for DMA
00105               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00106          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00107               into the function of corresponding DMA interruption vector
00108               DMAx_Channelx_IRQHandler().
00109
00110      *** Configuration of ADC, group regular, channels parameters ***
00111      ================================================================
00112      [..]
00113
00114     (#) Configure the ADC parameters (resolution, data alignment, ...)
00115         and regular group parameters (conversion trigger, sequencer, ...)
00116         using function HAL_ADC_Init().
00117
00118     (#) Configure the channels for regular group parameters (channel number,
00119         channel rank into sequencer, ..., into regular group)
00120         using function HAL_ADC_ConfigChannel().
00121
00122     (#) Optionally, configure the analog watchdog parameters (channels
00123         monitored, thresholds, ...)
00124         using function HAL_ADC_AnalogWDGConfig().
00125
00126      *** Execution of ADC conversions ***
00127      ====================================
00128      [..]
00129
00130     (#) Optionally, perform an automatic ADC calibration to improve the
00131         conversion accuracy
00132         using function HAL_ADCEx_Calibration_Start().
00133
00134     (#) ADC driver can be used among three modes: polling, interruption,
00135         transfer by DMA.
00136
00137         (++) ADC conversion by polling:
00138           (+++) Activate the ADC peripheral and start conversions
00139                 using function HAL_ADC_Start()
00140           (+++) Wait for ADC conversion completion
00141                 using function HAL_ADC_PollForConversion()
00142           (+++) Retrieve conversion results
00143                 using function HAL_ADC_GetValue()
00144           (+++) Stop conversion and disable the ADC peripheral
00145                 using function HAL_ADC_Stop()
00146
00147         (++) ADC conversion by interruption:
00148           (+++) Activate the ADC peripheral and start conversions
00149                 using function HAL_ADC_Start_IT()
00150           (+++) Wait for ADC conversion completion by call of function
00151                 HAL_ADC_ConvCpltCallback()
00152                 (this function must be implemented in user program)
00153           (+++) Retrieve conversion results
00154                 using function HAL_ADC_GetValue()
00155           (+++) Stop conversion and disable the ADC peripheral
00156                 using function HAL_ADC_Stop_IT()
00157
00158         (++) ADC conversion with transfer by DMA:
00159           (+++) Activate the ADC peripheral and start conversions
00160                 using function HAL_ADC_Start_DMA()
00161           (+++) Wait for ADC conversion completion by call of function
00162                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00163                 (these functions must be implemented in user program)
00164           (+++) Conversion results are automatically transferred by DMA into
00165                 destination variable address.
00166           (+++) Stop conversion and disable the ADC peripheral
00167                 using function HAL_ADC_Stop_DMA()
00168
00169      [..]
00170
00171     (@) Callback functions must be implemented in user program:
00172       (+@) HAL_ADC_ErrorCallback()
00173       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
00174       (+@) HAL_ADC_ConvCpltCallback()
00175       (+@) HAL_ADC_ConvHalfCpltCallback
00176
00177      *** Deinitialization of ADC ***
00178      ============================================================
00179      [..]
00180
00181     (#) Disable the ADC interface
00182       (++) ADC clock can be hard reset and disabled at RCC top level.
00183         (++) Hard reset of ADC peripherals
00184              using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
00185         (++) ADC clock disable
00186              using the equivalent macro/functions as configuration step.
00187              (+++) Example:
00188                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00189                    other device clock parameters configuration:
00190                (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
00191                (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
00192                (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
00193
00194     (#) ADC pins configuration
00195          (++) Disable the clock for the ADC GPIOs
00196               using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00197
00198     (#) Optionally, in case of usage of ADC with interruptions:
00199          (++) Disable the NVIC for ADC
00200               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00201
00202     (#) Optionally, in case of usage of DMA:
00203          (++) Deinitialize the DMA
00204               using function HAL_DMA_Init().
00205          (++) Disable the NVIC for DMA
00206               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00207
00208     [..]
00209
00210     *** Callback registration ***
00211     =============================================
00212     [..]
00213
00214      The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
00215      allows the user to configure dynamically the driver callbacks.
00216      Use Functions HAL_ADC_RegisterCallback()
00217      to register an interrupt callback.
00218     [..]
00219
00220      Function HAL_ADC_RegisterCallback() allows to register following callbacks:
00221        (+) ConvCpltCallback               : ADC conversion complete callback
00222        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
00223        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
00224        (+) ErrorCallback                  : ADC error callback
00225        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
00226        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
00227        (+) EndOfSamplingCallback          : ADC end of sampling callback
00228        (+) MspInitCallback                : ADC Msp Init callback
00229        (+) MspDeInitCallback              : ADC Msp DeInit callback
00230      This function takes as parameters the HAL peripheral handle, the Callback ID
00231      and a pointer to the user callback function.
00232     [..]
00233
00234      Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
00235      weak function.
00236     [..]
00237
00238      HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
00239      and the Callback ID.
00240      This function allows to reset following callbacks:
00241        (+) ConvCpltCallback               : ADC conversion complete callback
00242        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
00243        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
00244        (+) ErrorCallback                  : ADC error callback
00245        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
00246        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
00247        (+) EndOfSamplingCallback          : ADC end of sampling callback
00248        (+) MspInitCallback                : ADC Msp Init callback
00249        (+) MspDeInitCallback              : ADC Msp DeInit callback
00250      [..]
00251
00252      By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
00253      all callbacks are set to the corresponding weak functions:
00254      examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
00255      Exception done for MspInit and MspDeInit functions that are
00256      reset to the legacy weak functions in the HAL_ADC_Init()/HAL_ADC_DeInit() only when
00257      these callbacks are null (not registered beforehand).
00258     [..]
00259
00260      If MspInit or MspDeInit are not null, the HAL_ADC_Init()/HAL_ADC_DeInit()
00261      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00262      [..]
00263
00264      Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
00265      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00266      in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
00267      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00268     [..]
00269
00270      Then, the user first registers the MspInit/MspDeInit user callbacks
00271      using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
00272      or HAL_ADC_Init() function.
00273      [..]
00274
00275      When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
00276      not defined, the callback registration feature is not available and all callbacks
00277      are set to the corresponding weak functions.
00278
00279   @endverbatim
00280   */
00281
00282 /* Includes ------------------------------------------------------------------*/
00283 #include "stm32g0xx_hal.h"
00284
00285 /** @addtogroup STM32G0xx_HAL_Driver
00286   * @{
00287   */
00288
00289 /** @defgroup ADC ADC
00290   * @brief ADC HAL module driver
00291   * @{
00292   */
00293
00294 #ifdef HAL_ADC_MODULE_ENABLED
00295
00296 /* Private typedef -----------------------------------------------------------*/
00297 /* Private define ------------------------------------------------------------*/
00298
00299 /** @defgroup ADC_Private_Constants ADC Private Constants
00300   * @{
00301   */
00302
00303 /* Fixed timeout values for ADC calibration, enable settling time, disable  */
00304 /* settling time.                                                           */
00305 /* Values defined to be higher than worst cases: low clock frequency,       */
00306 /* maximum prescaler.                                                       */
00307 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
00308 /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits.     */
00309 /* Unit: ms                                                                 */
00310 #define ADC_ENABLE_TIMEOUT              (2UL)
00311 #define ADC_DISABLE_TIMEOUT             (2UL)
00312 #define ADC_STOP_CONVERSION_TIMEOUT     (2UL)
00313 #define ADC_CHANNEL_CONF_RDY_TIMEOUT    (1UL)
00314
00315 /* Register CHSELR bits corresponding to ranks 2 to 8 .                     */
00316 #define ADC_CHSELR_SQ2_TO_SQ8           (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \
00317                                          ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
00318
00319 /**
00320   * @}
00321   */
00322
00323 /* Private macro -------------------------------------------------------------*/
00324 /* Private variables ---------------------------------------------------------*/
00325 /* Private function prototypes -----------------------------------------------*/
00326 /** @defgroup ADC_Private_Functions ADC Private Functions
00327   * @{
00328   */
00329 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
00330 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00331 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
00332 /**
00333   * @}
00334   */
00335
00336 /* Exported functions ---------------------------------------------------------*/
00337
00338 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00339   * @{
00340   */
00341
00342 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00343   * @brief    ADC Initialization and Configuration functions
00344   *
00345 @verbatim
00346  ===============================================================================
00347               ##### Initialization and de-initialization functions #####
00348  ===============================================================================
00349     [..]  This section provides functions allowing to:
00350       (+) Initialize and configure the ADC.
00351       (+) De-initialize the ADC.
00352 @endverbatim
00353   * @{
00354   */
00355
00356 /**
00357   * @brief  Initialize the ADC peripheral and regular group according to
00358   *         parameters specified in structure "ADC_InitTypeDef".
00359   * @note   As prerequisite, ADC clock must be configured at RCC top level
00360   *         (refer to description of RCC configuration for ADC
00361   *         in header of this file).
00362   * @note   Possibility to update parameters on the fly:
00363   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00364   *         coming from ADC state reset. Following calls to this function can
00365   *         be used to reconfigure some parameters of ADC_InitTypeDef
00366   *         structure on the fly, without modifying MSP configuration. If ADC
00367   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00368   *         before HAL_ADC_Init().
00369   *         The setting of these parameters is conditioned to ADC state.
00370   *         For parameters constraints, see comments of structure
00371   *         "ADC_InitTypeDef".
00372   * @note   This function configures the ADC within 2 scopes: scope of entire
00373   *         ADC and scope of regular group. For parameters details, see comments
00374   *         of structure "ADC_InitTypeDef".
00375   * @param hadc ADC handle
00376   * @retval HAL status
00377   */
00378 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
00379 {
00380   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00381   uint32_t tmpCFGR1 = 0UL;
00382   uint32_t tmpCFGR2 = 0UL;
00383   uint32_t tmp_adc_reg_is_conversion_on_going;
00384   __IO uint32_t wait_loop_index = 0UL;
00385
00386   /* Check ADC handle */
00387   if (hadc == NULL)
00388   {
00389     return HAL_ERROR;
00390   }
00391
00392   /* Check the parameters */
00393   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00394   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00395   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00396   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00397   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00398   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00399   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00400   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
00401   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00402   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
00403   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
00404   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
00405   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
00406   assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
00407   assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
00408   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
00409   if (hadc->Init.OversamplingMode == ENABLE)
00410   {
00411     assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
00412     assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
00413     assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
00414   }
00415   assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
00416
00417   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00418   {
00419     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00420
00421     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00422     {
00423       assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00424     }
00425   }
00426
00427   /* ADC group regular discontinuous mode can be enabled only if              */
00428   /* continuous mode is disabled.                                             */
00429   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
00430
00431   /* Actions performed only if ADC is coming from state reset:                */
00432   /* - Initialization of ADC MSP                                              */
00433   if (hadc->State == HAL_ADC_STATE_RESET)
00434   {
00435 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00436     /* Init the ADC Callback settings */
00437     hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
00438     hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
00439     hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
00440     hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
00441     hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak callback */
00442     hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak callback */
00443     hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak callback */
00444
00445     if (hadc->MspInitCallback == NULL)
00446     {
00447       hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
00448     }
00449
00450     /* Init the low level hardware */
00451     hadc->MspInitCallback(hadc);
00452 #else
00453     /* Init the low level hardware */
00454     HAL_ADC_MspInit(hadc);
00455 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00456
00457     /* Set ADC error code to none */
00458     ADC_CLEAR_ERRORCODE(hadc);
00459
00460     /* Initialize Lock */
00461     hadc->Lock = HAL_UNLOCKED;
00462   }
00463
00464   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
00465   {
00466     /* Enable ADC internal voltage regulator */
00467     LL_ADC_EnableInternalRegulator(hadc->Instance);
00468
00469     /* Delay for ADC stabilization time */
00470     /* Wait loop initialization and execution */
00471     /* Note: Variable divided by 2 to compensate partially              */
00472     /*       CPU processing cycles, scaling in us split to not          */
00473     /*       exceed 32 bits register capacity and handle low frequency. */
00474     wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00475     while (wait_loop_index != 0UL)
00476     {
00477       wait_loop_index--;
00478     }
00479   }
00480
00481   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00482   /* or not ADC is coming from state reset (if any potential problem of       */
00483   /* clocking, voltage regulator would not be enabled).                       */
00484   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
00485   {
00486     /* Update ADC state machine to error */
00487     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00488
00489     /* Set ADC error code to ADC peripheral internal error */
00490     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00491
00492     tmp_hal_status = HAL_ERROR;
00493   }
00494
00495   /* Configuration of ADC parameters if previous preliminary actions are      */
00496   /* correctly completed and if there is no conversion on going on regular    */
00497   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
00498   /* called to update a parameter on the fly).                                */
00499   tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00500
00501   if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
00502       && (tmp_adc_reg_is_conversion_on_going == 0UL)
00503      )
00504   {
00505     /* Set ADC state */
00506     ADC_STATE_CLR_SET(hadc->State,
00507                       HAL_ADC_STATE_REG_BUSY,
00508                       HAL_ADC_STATE_BUSY_INTERNAL);
00509
00510     /* Configuration of common ADC parameters                                 */
00511
00512     /* Parameters update conditioned to ADC state:                            */
00513     /* Parameters that can be updated only when ADC is disabled:              */
00514     /*  - Internal voltage regulator (no parameter in HAL ADC init structure) */
00515     /*  - Clock configuration                                                 */
00516     /*  - ADC resolution                                                      */
00517     /*  - Oversampling                                                        */
00518     /*  - discontinuous mode                                                  */
00519     /*  - LowPowerAutoWait mode                                               */
00520     /*  - LowPowerAutoPowerOff mode                                           */
00521     /*  - continuous conversion mode                                          */
00522     /*  - overrun                                                             */
00523     /*  - external trigger to start conversion                                */
00524     /*  - external trigger polarity                                           */
00525     /*  - data alignment                                                      */
00526     /*  - resolution                                                          */
00527     /*  - scan direction                                                      */
00528     /*  - DMA continuous request                                              */
00529     /*  - Trigger frequency mode                                              */
00530     /* Note: If low power mode AutoPowerOff is enabled, ADC enable            */
00531     /*       and disable phases are performed automatically by hardware       */
00532     /*       (in this case, flag ADC_FLAG_RDY is not set).                    */
00533     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
00534     {
00535       /* Some parameters of this register are not reset, since they are set   */
00536       /* by other functions and must be kept in case of usage of this         */
00537       /* function on the fly (update of a parameter of ADC_InitTypeDef        */
00538       /* without needing to reconfigure all other ADC groups/channels         */
00539       /* parameters):                                                         */
00540       /*   - internal measurement paths (VrefInt, ...)                        */
00541       /*     (set into HAL_ADC_ConfigChannel() )                              */
00542
00543       tmpCFGR1 |= (hadc->Init.Resolution                                          |
00544                    ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)      |
00545                    ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff)   |
00546                    ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)  |
00547                    ADC_CFGR1_OVERRUN(hadc->Init.Overrun)                          |
00548                    hadc->Init.DataAlign                                           |
00549                    ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode)                     |
00550                    ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
00551
00552       /* Update setting of discontinuous mode only if continuous mode is disabled */
00553       if (hadc->Init.DiscontinuousConvMode == ENABLE)
00554       {
00555         if (hadc->Init.ContinuousConvMode == DISABLE)
00556         {
00557           /* Enable the selected ADC group regular discontinuous mode */
00558           tmpCFGR1 |= ADC_CFGR1_DISCEN;
00559         }
00560         else
00561         {
00562           /* ADC regular group discontinuous was intended to be enabled,        */
00563           /* but ADC regular group modes continuous and sequencer discontinuous */
00564           /* cannot be enabled simultaneously.                                  */
00565
00566           /* Update ADC state machine to error */
00567           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00568
00569           /* Set ADC error code to ADC peripheral internal error */
00570           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00571         }
00572       }
00573
00574       /* Enable external trigger if trigger selection is different of software  */
00575       /* start.                                                                 */
00576       /* Note: This configuration keeps the hardware feature of parameter       */
00577       /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
00578       /*       software start.                                                  */
00579       if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00580       {
00581         tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
00582                      hadc->Init.ExternalTrigConvEdge);
00583       }
00584
00585       /* Update ADC configuration register with previous settings */
00586       MODIFY_REG(hadc->Instance->CFGR1,
00587                  ADC_CFGR1_RES     |
00588                  ADC_CFGR1_DISCEN  |
00589                  ADC_CFGR1_AUTOFF  |
00590                  ADC_CFGR1_WAIT    |
00591                  ADC_CFGR1_CONT    |
00592                  ADC_CFGR1_OVRMOD  |
00593                  ADC_CFGR1_EXTSEL  |
00594                  ADC_CFGR1_EXTEN   |
00595                  ADC_CFGR1_ALIGN   |
00596                  ADC_CFGR1_SCANDIR |
00597                  ADC_CFGR1_DMACFG,
00598                  tmpCFGR1);
00599
00600       tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
00601                    hadc->Init.TriggerFrequencyMode
00602                   );
00603
00604       if (hadc->Init.OversamplingMode == ENABLE)
00605       {
00606         tmpCFGR2 |= (ADC_CFGR2_OVSE |
00607                      (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
00608                      hadc->Init.Oversampling.Ratio         |
00609                      hadc->Init.Oversampling.RightBitShift |
00610                      hadc->Init.Oversampling.TriggeredMode
00611                     );
00612       }
00613
00614       MODIFY_REG(hadc->Instance->CFGR2,
00615                  ADC_CFGR2_CKMODE |
00616                  ADC_CFGR2_LFTRIG |
00617                  ADC_CFGR2_OVSE   |
00618                  ADC_CFGR2_OVSR   |
00619                  ADC_CFGR2_OVSS   |
00620                  ADC_CFGR2_TOVS,
00621                  tmpCFGR2);
00622
00623       /* Configuration of ADC clock mode: asynchronous clock source           */
00624       /* with selectable prescaler.                                           */
00625       if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
00626           ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
00627           ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
00628       {
00629         MODIFY_REG(ADC1_COMMON->CCR,
00630                    ADC_CCR_PRESC,
00631                    hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
00632       }
00633     }
00634
00635     /* Channel sampling time configuration */
00636     LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
00637     LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
00638
00639     /* Configuration of regular group sequencer:                              */
00640     /* - if scan mode is disabled, regular channels sequence length is set to */
00641     /*   0x00: 1 channel converted (channel on regular rank 1)                */
00642     /*   Parameter "NbrOfConversion" is discarded.                            */
00643     /*   Note: Scan mode is not present by hardware on this device, but       */
00644     /*   emulated by software for alignment over all STM32 devices.           */
00645     /* - if scan mode is enabled, regular channels sequence length is set to  */
00646     /*   parameter "NbrOfConversion".                                         */
00647     /*   Channels must be configured into each rank using function            */
00648     /*   "HAL_ADC_ConfigChannel()".                                           */
00649     if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
00650     {
00651       /* Set sequencer scan length by clearing ranks above rank 1             */
00652       /* and do not modify rank 1 value.                                      */
00653       SET_BIT(hadc->Instance->CHSELR,
00654               ADC_CHSELR_SQ2_TO_SQ8);
00655     }
00656     else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00657     {
00658       /* Set ADC group regular sequencer:                                   */
00659       /*  - Set ADC group regular sequencer to value memorized              */
00660       /*    in HAL ADC handle                                               */
00661       /*    Note: This value maybe be initialized at a unknown value,       */
00662       /*          therefore after the first call of "HAL_ADC_Init()",       */
00663       /*          each rank corresponding to parameter "NbrOfConversion"    */
00664       /*          must be set using "HAL_ADC_ConfigChannel()".              */
00665       /*  - Set sequencer scan length by clearing ranks above maximum rank  */
00666       /*    and do not modify other ranks value.                            */
00667       MODIFY_REG(hadc->Instance->CHSELR,
00668                   ADC_CHSELR_SQ_ALL,
00669                   (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks)
00670                 );
00671     }
00672
00673     /* Check back that ADC registers have effectively been configured to      */
00674     /* ensure of no potential problem of ADC core peripheral clocking.        */
00675     if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
00676       == hadc->Init.SamplingTimeCommon1)
00677     {
00678       /* Set ADC error code to none */
00679       ADC_CLEAR_ERRORCODE(hadc);
00680
00681       /* Set the ADC state */
00682       ADC_STATE_CLR_SET(hadc->State,
00683                         HAL_ADC_STATE_BUSY_INTERNAL,
00684                         HAL_ADC_STATE_READY);
00685     }
00686     else
00687     {
00688       /* Update ADC state machine to error */
00689       ADC_STATE_CLR_SET(hadc->State,
00690                         HAL_ADC_STATE_BUSY_INTERNAL,
00691                         HAL_ADC_STATE_ERROR_INTERNAL);
00692
00693       /* Set ADC error code to ADC peripheral internal error */
00694       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00695
00696       tmp_hal_status = HAL_ERROR;
00697     }
00698
00699   }
00700   else
00701   {
00702     /* Update ADC state machine to error */
00703     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00704
00705     tmp_hal_status = HAL_ERROR;
00706   }
00707
00708   return tmp_hal_status;
00709 }
00710
00711 /**
00712   * @brief  Deinitialize the ADC peripheral registers to their default reset
00713   *         values, with deinitialization of the ADC MSP.
00714   * @note   For devices with several ADCs: reset of ADC common registers is done
00715   *         only if all ADCs sharing the same common group are disabled.
00716   *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
00717   *         all ADC instances use the same core clock at RCC level, disabling
00718   *         the core clock reset all ADC instances).
00719   *         If this is not the case, reset of these common parameters reset is
00720   *         bypassed without error reporting: it can be the intended behavior in
00721   *         case of reset of a single ADC while the other ADCs sharing the same
00722   *         common group is still running.
00723   * @param hadc ADC handle
00724   * @retval HAL status
00725   */
00726 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
00727 {
00728   HAL_StatusTypeDef tmp_hal_status;
00729
00730   /* Check ADC handle */
00731   if (hadc == NULL)
00732   {
00733     return HAL_ERROR;
00734   }
00735
00736   /* Check the parameters */
00737   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00738
00739   /* Set ADC state */
00740   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00741
00742   /* Stop potential conversion on going, on regular group */
00743   tmp_hal_status = ADC_ConversionStop(hadc);
00744
00745   /* Disable ADC peripheral if conversions are effectively stopped */
00746   if (tmp_hal_status == HAL_OK)
00747   {
00748     /* Disable the ADC peripheral */
00749     tmp_hal_status = ADC_Disable(hadc);
00750
00751     /* Check if ADC is effectively disabled */
00752     if (tmp_hal_status == HAL_OK)
00753     {
00754       /* Change ADC state */
00755       hadc->State = HAL_ADC_STATE_READY;
00756     }
00757
00758     /* Disable ADC internal voltage regulator */
00759     LL_ADC_DisableInternalRegulator(hadc->Instance);
00760   }
00761
00762   /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
00763   /*       and disable return status. In case of status fail, attempt to      */
00764   /*       perform deinitialization anyway and it is up user code in          */
00765   /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
00766   /*       system RCC hard reset.                                             */
00767
00768   /* ========== Reset ADC registers ========== */
00769   /* Reset register IER */
00770   __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 |
00771                               ADC_IT_AWD1  | ADC_IT_OVR  |
00772                               ADC_IT_EOS   | ADC_IT_EOC  |
00773                               ADC_IT_EOSMP | ADC_IT_RDY));
00774
00775   /* Reset register ISR */
00776   __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 |
00777                               ADC_FLAG_AWD1  | ADC_FLAG_OVR  |
00778                               ADC_FLAG_EOS   | ADC_FLAG_EOC  |
00779                               ADC_FLAG_EOSMP | ADC_FLAG_RDY));
00780
00781   /* Reset register CR */
00782   /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode     */
00783   /* "read-set": no direct reset applicable.                                */
00784
00785   /* Reset register CFGR1 */
00786   hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH   | ADC_CFGR1_AWD1EN  | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
00787                              ADC_CFGR1_AUTOFF  | ADC_CFGR1_WAIT   | ADC_CFGR1_CONT   | ADC_CFGR1_OVRMOD |
00788                              ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN  | ADC_CFGR1_RES    |
00789                              ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
00790
00791   /* Reset register CFGR2 */
00792   /* Note: Update of ADC clock mode is conditioned to ADC state disabled:   */
00793   /*       already done above.                                              */
00794   hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
00795
00796   /* Reset register SMPR */
00797   hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
00798
00799   /* Reset registers AWDxTR */
00800   hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
00801   hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2);
00802   hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3);
00803
00804   /* Reset register CHSELR */
00805   hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
00806
00807   /* Reset register DR */
00808   /* bits in access mode read only, no direct reset applicable */
00809
00810   /* Reset register CCR */
00811   ADC1_COMMON->CCR &= ~(ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
00812
00813   /* ========== Hard reset ADC peripheral ========== */
00814   /* Performs a global reset of the entire ADC peripheral: ADC state is     */
00815   /* forced to a similar state after device power-on.                       */
00816   /* Note: A possible implementation is to add RCC bus reset of ADC         */
00817   /* (for example, using macro                                              */
00818   /*  __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
00819   /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)":         */
00820 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00821   if (hadc->MspDeInitCallback == NULL)
00822   {
00823     hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
00824   }
00825
00826   /* DeInit the low level hardware */
00827   hadc->MspDeInitCallback(hadc);
00828 #else
00829   /* DeInit the low level hardware */
00830   HAL_ADC_MspDeInit(hadc);
00831 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00832
00833   /* Reset HAL ADC handle variable */
00834   hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
00835
00836   /* Set ADC error code to none */
00837   ADC_CLEAR_ERRORCODE(hadc);
00838
00839   /* Set ADC state */
00840   hadc->State = HAL_ADC_STATE_RESET;
00841
00842   __HAL_UNLOCK(hadc);
00843
00844   return tmp_hal_status;
00845 }
00846
00847 /**
00848   * @brief  Initialize the ADC MSP.
00849   * @param hadc ADC handle
00850   * @retval None
00851   */
00852 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
00853 {
00854   /* Prevent unused argument(s) compilation warning */
00855   UNUSED(hadc);
00856
00857   /* NOTE : This function should not be modified. When the callback is needed,
00858             function HAL_ADC_MspInit must be implemented in the user file.
00859    */
00860 }
00861
00862 /**
00863   * @brief  DeInitialize the ADC MSP.
00864   * @param hadc ADC handle
00865   * @note   All ADC instances use the same core clock at RCC level, disabling
00866   *         the core clock reset all ADC instances).
00867   * @retval None
00868   */
00869 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
00870 {
00871   /* Prevent unused argument(s) compilation warning */
00872   UNUSED(hadc);
00873
00874   /* NOTE : This function should not be modified. When the callback is needed,
00875             function HAL_ADC_MspDeInit must be implemented in the user file.
00876    */
00877 }
00878
00879 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00880 /**
00881   * @brief  Register a User ADC Callback
00882   *         To be used instead of the weak predefined callback
00883   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
00884   *                the configuration information for the specified ADC.
00885   * @param  CallbackID ID of the callback to be registered
00886   *         This parameter can be one of the following values:
00887   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
00888   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
00889   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
00890   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
00891   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
00892   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
00893   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
00894   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
00895   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
00896   *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
00897   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
00898   * @param  pCallback pointer to the Callback function
00899   * @retval HAL status
00900   */
00901 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
00902                                            pADC_CallbackTypeDef pCallback)
00903 {
00904   HAL_StatusTypeDef status = HAL_OK;
00905
00906   if (pCallback == NULL)
00907   {
00908     /* Update the error code */
00909     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
00910
00911     return HAL_ERROR;
00912   }
00913
00914   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
00915   {
00916     switch (CallbackID)
00917     {
00918       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
00919         hadc->ConvCpltCallback = pCallback;
00920         break;
00921
00922       case HAL_ADC_CONVERSION_HALF_CB_ID :
00923         hadc->ConvHalfCpltCallback = pCallback;
00924         break;
00925
00926       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
00927         hadc->LevelOutOfWindowCallback = pCallback;
00928         break;
00929
00930       case HAL_ADC_ERROR_CB_ID :
00931         hadc->ErrorCallback = pCallback;
00932         break;
00933
00934       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
00935         hadc->LevelOutOfWindow2Callback = pCallback;
00936         break;
00937
00938       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
00939         hadc->LevelOutOfWindow3Callback = pCallback;
00940         break;
00941
00942       case HAL_ADC_END_OF_SAMPLING_CB_ID :
00943         hadc->EndOfSamplingCallback = pCallback;
00944         break;
00945
00946       case HAL_ADC_MSPINIT_CB_ID :
00947         hadc->MspInitCallback = pCallback;
00948         break;
00949
00950       case HAL_ADC_MSPDEINIT_CB_ID :
00951         hadc->MspDeInitCallback = pCallback;
00952         break;
00953
00954       default :
00955         /* Update the error code */
00956         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
00957
00958         /* Return error status */
00959         status = HAL_ERROR;
00960         break;
00961     }
00962   }
00963   else if (HAL_ADC_STATE_RESET == hadc->State)
00964   {
00965     switch (CallbackID)
00966     {
00967       case HAL_ADC_MSPINIT_CB_ID :
00968         hadc->MspInitCallback = pCallback;
00969         break;
00970
00971       case HAL_ADC_MSPDEINIT_CB_ID :
00972         hadc->MspDeInitCallback = pCallback;
00973         break;
00974
00975       default :
00976         /* Update the error code */
00977         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
00978
00979         /* Return error status */
00980         status = HAL_ERROR;
00981         break;
00982     }
00983   }
00984   else
00985   {
00986     /* Update the error code */
00987     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
00988
00989     /* Return error status */
00990     status =  HAL_ERROR;
00991   }
00992
00993   return status;
00994 }
00995
00996 /**
00997   * @brief  Unregister a ADC Callback
00998   *         ADC callback is redirected to the weak predefined callback
00999   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
01000   *                the configuration information for the specified ADC.
01001   * @param  CallbackID ID of the callback to be unregistered
01002   *         This parameter can be one of the following values:
01003   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
01004   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
01005   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
01006   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
01007   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
01008   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
01009   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
01010   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
01011   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
01012   *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
01013   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
01014   * @retval HAL status
01015   */
01016 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
01017 {
01018   HAL_StatusTypeDef status = HAL_OK;
01019
01020   if ((hadc->State & HAL_ADC_STATE_READY) != 0)
01021   {
01022     switch (CallbackID)
01023     {
01024       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
01025         hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
01026         break;
01027
01028       case HAL_ADC_CONVERSION_HALF_CB_ID :
01029         hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
01030         break;
01031
01032       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
01033         hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
01034         break;
01035
01036       case HAL_ADC_ERROR_CB_ID :
01037         hadc->ErrorCallback = HAL_ADC_ErrorCallback;
01038         break;
01039
01040       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
01041         hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
01042         break;
01043
01044       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
01045         hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
01046         break;
01047
01048       case HAL_ADC_END_OF_SAMPLING_CB_ID :
01049         hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
01050         break;
01051
01052       case HAL_ADC_MSPINIT_CB_ID :
01053         hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
01054         break;
01055
01056       case HAL_ADC_MSPDEINIT_CB_ID :
01057         hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
01058         break;
01059
01060       default :
01061         /* Update the error code */
01062         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01063
01064         /* Return error status */
01065         status =  HAL_ERROR;
01066         break;
01067     }
01068   }
01069   else if (HAL_ADC_STATE_RESET == hadc->State)
01070   {
01071     switch (CallbackID)
01072     {
01073       case HAL_ADC_MSPINIT_CB_ID :
01074         hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
01075         break;
01076
01077       case HAL_ADC_MSPDEINIT_CB_ID :
01078         hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
01079         break;
01080
01081       default :
01082         /* Update the error code */
01083         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01084
01085         /* Return error status */
01086         status =  HAL_ERROR;
01087         break;
01088     }
01089   }
01090   else
01091   {
01092     /* Update the error code */
01093     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01094
01095     /* Return error status */
01096     status =  HAL_ERROR;
01097   }
01098
01099   return status;
01100 }
01101
01102 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01103
01104 /**
01105   * @}
01106   */
01107
01108 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
01109   *  @brief    ADC IO operation functions
01110   *
01111 @verbatim
01112  ===============================================================================
01113                       ##### IO operation functions #####
01114  ===============================================================================
01115     [..]  This section provides functions allowing to:
01116       (+) Start conversion of regular group.
01117       (+) Stop conversion of regular group.
01118       (+) Poll for conversion complete on regular group.
01119       (+) Poll for conversion event.
01120       (+) Get result of regular channel conversion.
01121       (+) Start conversion of regular group and enable interruptions.
01122       (+) Stop conversion of regular group and disable interruptions.
01123       (+) Handle ADC interrupt request
01124       (+) Start conversion of regular group and enable DMA transfer.
01125       (+) Stop conversion of regular group and disable ADC DMA transfer.
01126 @endverbatim
01127   * @{
01128   */
01129
01130 /**
01131   * @brief  Enable ADC, start conversion of regular group.
01132   * @note   Interruptions enabled in this function: None.
01133   * @param hadc ADC handle
01134   * @retval HAL status
01135   */
01136 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
01137 {
01138   HAL_StatusTypeDef tmp_hal_status;
01139
01140   /* Check the parameters */
01141   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01142
01143   /* Perform ADC enable and conversion start if no conversion is on going */
01144   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01145   {
01146     __HAL_LOCK(hadc);
01147
01148     /* Enable the ADC peripheral */
01149     tmp_hal_status = ADC_Enable(hadc);
01150
01151     /* Start conversion if ADC is effectively enabled */
01152     if (tmp_hal_status == HAL_OK)
01153     {
01154       /* Set ADC state                                                        */
01155       /* - Clear state bitfield related to regular group conversion results   */
01156       /* - Set state bitfield related to regular operation                    */
01157       ADC_STATE_CLR_SET(hadc->State,
01158                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01159                         HAL_ADC_STATE_REG_BUSY);
01160
01161       /* Set ADC error code */
01162       /* Reset all ADC error code fields */
01163       ADC_CLEAR_ERRORCODE(hadc);
01164
01165       /* Clear ADC group regular conversion flag and overrun flag               */
01166       /* (To ensure of no unknown state from potential previous ADC operations) */
01167       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01168
01169       /* Process unlocked */
01170       /* Unlock before starting ADC conversions: in case of potential         */
01171       /* interruption, to let the process to ADC IRQ Handler.                 */
01172       __HAL_UNLOCK(hadc);
01173
01174       /* Enable conversion of regular group.                                  */
01175       /* If software start has been selected, conversion starts immediately.  */
01176       /* If external trigger has been selected, conversion will start at next */
01177       /* trigger event.                                                       */
01178       /* Start ADC group regular conversion */
01179       LL_ADC_REG_StartConversion(hadc->Instance);
01180     }
01181     else
01182     {
01183       __HAL_UNLOCK(hadc);
01184     }
01185   }
01186   else
01187   {
01188     tmp_hal_status = HAL_BUSY;
01189   }
01190
01191   return tmp_hal_status;
01192 }
01193
01194 /**
01195   * @brief  Stop ADC conversion of regular group (and injected channels in
01196   *         case of auto_injection mode), disable ADC peripheral.
01197   * @note:  ADC peripheral disable is forcing stop of potential
01198   *         conversion on injected group. If injected group is under use, it
01199   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01200   * @param hadc ADC handle
01201   * @retval HAL status.
01202   */
01203 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
01204 {
01205   HAL_StatusTypeDef tmp_hal_status;
01206
01207   /* Check the parameters */
01208   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01209
01210   __HAL_LOCK(hadc);
01211
01212   /* 1. Stop potential conversion on going, on ADC group regular */
01213   tmp_hal_status = ADC_ConversionStop(hadc);
01214
01215   /* Disable ADC peripheral if conversions are effectively stopped */
01216   if (tmp_hal_status == HAL_OK)
01217   {
01218     /* 2. Disable the ADC peripheral */
01219     tmp_hal_status = ADC_Disable(hadc);
01220
01221     /* Check if ADC is effectively disabled */
01222     if (tmp_hal_status == HAL_OK)
01223     {
01224       /* Set ADC state */
01225       ADC_STATE_CLR_SET(hadc->State,
01226                         HAL_ADC_STATE_REG_BUSY,
01227                         HAL_ADC_STATE_READY);
01228     }
01229   }
01230
01231   __HAL_UNLOCK(hadc);
01232
01233   return tmp_hal_status;
01234 }
01235
01236 /**
01237   * @brief  Wait for regular group conversion to be completed.
01238   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
01239   *         conversion) are cleared by this function, with an exception:
01240   *         if low power feature "LowPowerAutoWait" is enabled, flags are
01241   *         not cleared to not interfere with this feature until data register
01242   *         is read using function HAL_ADC_GetValue().
01243   * @note   This function cannot be used in a particular setup: ADC configured
01244   *         in DMA mode and polling for end of each conversion (ADC init
01245   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
01246   *         In this case, DMA resets the flag EOC and polling cannot be
01247   *         performed on each conversion. Nevertheless, polling can still
01248   *         be performed on the complete sequence (ADC init
01249   *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
01250   * @param hadc ADC handle
01251   * @param Timeout Timeout value in millisecond.
01252   * @retval HAL status
01253   */
01254 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
01255 {
01256   uint32_t tickstart;
01257   uint32_t tmp_flag_end;
01258
01259   /* Check the parameters */
01260   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01261
01262   /* If end of conversion selected to end of sequence conversions */
01263   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
01264   {
01265     tmp_flag_end = ADC_FLAG_EOS;
01266   }
01267   /* If end of conversion selected to end of unitary conversion */
01268   else /* ADC_EOC_SINGLE_CONV */
01269   {
01270     /* Verification that ADC configuration is compliant with polling for      */
01271     /* each conversion:                                                       */
01272     /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
01273     /* several ranks and polling for end of each conversion.                  */
01274     /* For code simplicity sake, this particular case is generalized to       */
01275     /* ADC configured in DMA mode and and polling for end of each conversion. */
01276     if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL)
01277     {
01278       /* Update ADC state machine to error */
01279       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01280
01281       return HAL_ERROR;
01282     }
01283     else
01284     {
01285       tmp_flag_end = (ADC_FLAG_EOC);
01286     }
01287   }
01288
01289   /* Get tick count */
01290   tickstart = HAL_GetTick();
01291
01292   /* Wait until End of unitary conversion or sequence conversions flag is raised */
01293   while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
01294   {
01295     /* Check if timeout is disabled (set to infinite wait) */
01296     if (Timeout != HAL_MAX_DELAY)
01297     {
01298       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01299       {
01300         /* New check to avoid false timeout detection in case of preemption */
01301         if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
01302         {
01303           /* Update ADC state machine to timeout */
01304           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01305
01306           __HAL_UNLOCK(hadc);
01307
01308           return HAL_TIMEOUT;
01309         }
01310       }
01311     }
01312   }
01313
01314   /* Update ADC state machine */
01315   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01316
01317   /* Determine whether any further conversion upcoming on group regular       */
01318   /* by external trigger, continuous mode or scan sequence on going.          */
01319   if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
01320       && (hadc->Init.ContinuousConvMode == DISABLE)
01321      )
01322   {
01323     /* Check whether end of sequence is reached */
01324     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
01325     {
01326       /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit             */
01327       /* ADSTART==0 (no conversion on going)                                  */
01328       if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01329       {
01330         /* Disable ADC end of single conversion interrupt on group regular */
01331         /* Note: Overrun interrupt was enabled with EOC interrupt in          */
01332         /* HAL_Start_IT(), but is not disabled here because can be used       */
01333         /* by overrun IRQ process below.                                      */
01334         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
01335
01336         /* Set ADC state */
01337         ADC_STATE_CLR_SET(hadc->State,
01338                           HAL_ADC_STATE_REG_BUSY,
01339                           HAL_ADC_STATE_READY);
01340       }
01341       else
01342       {
01343         /* Change ADC state to error state */
01344         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01345
01346         /* Set ADC error code to ADC peripheral internal error */
01347         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01348       }
01349     }
01350   }
01351
01352   /* Clear end of conversion flag of regular group if low power feature       */
01353   /* "LowPowerAutoWait " is disabled, to not interfere with this feature      */
01354   /* until data register is read using function HAL_ADC_GetValue().           */
01355   if (hadc->Init.LowPowerAutoWait == DISABLE)
01356   {
01357     /* Clear regular group conversion flag */
01358     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
01359   }
01360
01361   /* Return function status */
01362   return HAL_OK;
01363 }
01364
01365 /**
01366   * @brief  Poll for ADC event.
01367   * @param hadc ADC handle
01368   * @param EventType the ADC event type.
01369   *          This parameter can be one of the following values:
01370   *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
01371   *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
01372   *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
01373   *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
01374   *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
01375   * @param Timeout Timeout value in millisecond.
01376   * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
01377   *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
01378   *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
01379   *         by a new converted data as soon as OVR is cleared.
01380   *         To reset OVR flag once the preserved data is retrieved, the user can resort
01381   *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01382   * @retval HAL status
01383   */
01384 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
01385 {
01386   uint32_t tickstart;
01387
01388   /* Check the parameters */
01389   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01390   assert_param(IS_ADC_EVENT_TYPE(EventType));
01391
01392   /* Get tick count */
01393   tickstart = HAL_GetTick();
01394
01395   /* Check selected event flag */
01396   while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
01397   {
01398     /* Check if timeout is disabled (set to infinite wait) */
01399     if (Timeout != HAL_MAX_DELAY)
01400     {
01401       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01402       {
01403         /* New check to avoid false timeout detection in case of preemption */
01404         if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
01405         {
01406           /* Update ADC state machine to timeout */
01407           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01408
01409           __HAL_UNLOCK(hadc);
01410
01411           return HAL_TIMEOUT;
01412         }
01413       }
01414     }
01415   }
01416
01417   switch (EventType)
01418   {
01419     /* End Of Sampling event */
01420     case ADC_EOSMP_EVENT:
01421       /* Set ADC state */
01422       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01423
01424       /* Clear the End Of Sampling flag */
01425       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01426
01427       break;
01428
01429     /* Analog watchdog (level out of window) event */
01430     /* Note: In case of several analog watchdog enabled, if needed to know      */
01431     /* which one triggered and on which ADCx, test ADC state of analog watchdog */
01432     /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
01433     /* For example:                                                             */
01434     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
01435     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
01436     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
01437
01438     /* Check analog watchdog 1 flag */
01439     case ADC_AWD_EVENT:
01440       /* Set ADC state */
01441       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01442
01443       /* Clear ADC analog watchdog flag */
01444       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01445
01446       break;
01447
01448     /* Check analog watchdog 2 flag */
01449     case ADC_AWD2_EVENT:
01450       /* Set ADC state */
01451       SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01452
01453       /* Clear ADC analog watchdog flag */
01454       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01455
01456       break;
01457
01458     /* Check analog watchdog 3 flag */
01459     case ADC_AWD3_EVENT:
01460       /* Set ADC state */
01461       SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01462
01463       /* Clear ADC analog watchdog flag */
01464       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01465
01466       break;
01467
01468     /* Overrun event */
01469     default: /* Case ADC_OVR_EVENT */
01470       /* If overrun is set to overwrite previous data, overrun event is not     */
01471       /* considered as an error.                                                */
01472       /* (cf ref manual "Managing conversions without using the DMA and without */
01473       /* overrun ")                                                             */
01474       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01475       {
01476         /* Set ADC state */
01477         SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01478
01479         /* Set ADC error code to overrun */
01480         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01481       }
01482       else
01483       {
01484         /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
01485            otherwise, data register is potentially overwritten by new converted data as soon
01486            as OVR is cleared. */
01487         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01488       }
01489       break;
01490   }
01491
01492   /* Return function status */
01493   return HAL_OK;
01494 }
01495
01496 /**
01497   * @brief  Enable ADC, start conversion of regular group with interruption.
01498   * @note   Interruptions enabled in this function according to initialization
01499   *         setting : EOC (end of conversion), EOS (end of sequence),
01500   *         OVR overrun.
01501   *         Each of these interruptions has its dedicated callback function.
01502   * @note   To guarantee a proper reset of all interruptions once all the needed
01503   *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
01504   *         a correct stop of the IT-based conversions.
01505   * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
01506   *         interruption. If required (e.g. in case of oversampling with trigger
01507   *         mode), the user must:
01508   *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
01509   *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
01510   *          before calling HAL_ADC_Start_IT().
01511   * @param hadc ADC handle
01512   * @retval HAL status
01513   */
01514 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
01515 {
01516   HAL_StatusTypeDef tmp_hal_status;
01517
01518   /* Check the parameters */
01519   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01520
01521   /* Perform ADC enable and conversion start if no conversion is on going */
01522   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01523   {
01524     __HAL_LOCK(hadc);
01525
01526     /* Enable the ADC peripheral */
01527     tmp_hal_status = ADC_Enable(hadc);
01528
01529     /* Start conversion if ADC is effectively enabled */
01530     if (tmp_hal_status == HAL_OK)
01531     {
01532       /* Set ADC state                                                        */
01533       /* - Clear state bitfield related to regular group conversion results   */
01534       /* - Set state bitfield related to regular operation                    */
01535       ADC_STATE_CLR_SET(hadc->State,
01536                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01537                         HAL_ADC_STATE_REG_BUSY);
01538
01539
01540       /* Set ADC error code */
01541       /* Reset all ADC error code fields */
01542       ADC_CLEAR_ERRORCODE(hadc);
01543
01544       /* Clear ADC group regular conversion flag and overrun flag               */
01545       /* (To ensure of no unknown state from potential previous ADC operations) */
01546       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01547
01548       /* Process unlocked */
01549       /* Unlock before starting ADC conversions: in case of potential         */
01550       /* interruption, to let the process to ADC IRQ Handler.                 */
01551       __HAL_UNLOCK(hadc);
01552
01553       /* Disable all interruptions before enabling the desired ones */
01554       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01555
01556       /* Enable ADC end of conversion interrupt */
01557       switch (hadc->Init.EOCSelection)
01558       {
01559         case ADC_EOC_SEQ_CONV:
01560           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
01561           break;
01562         /* case ADC_EOC_SINGLE_CONV */
01563         default:
01564           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
01565           break;
01566       }
01567
01568       /* Enable ADC overrun interrupt */
01569       /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
01570          ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
01571          behavior and no CPU time is lost for a non-processed interruption */
01572       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01573       {
01574         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01575       }
01576
01577       /* Enable conversion of regular group.                                  */
01578       /* If software start has been selected, conversion starts immediately.  */
01579       /* If external trigger has been selected, conversion will start at next */
01580       /* trigger event.                                                       */
01581       /* Start ADC group regular conversion */
01582       LL_ADC_REG_StartConversion(hadc->Instance);
01583     }
01584     else
01585     {
01586       __HAL_UNLOCK(hadc);
01587     }
01588
01589   }
01590   else
01591   {
01592     tmp_hal_status = HAL_BUSY;
01593   }
01594
01595   return tmp_hal_status;
01596 }
01597
01598 /**
01599   * @brief  Stop ADC conversion of regular group (and injected group in
01600   *         case of auto_injection mode), disable interrution of
01601   *         end-of-conversion, disable ADC peripheral.
01602   * @param hadc ADC handle
01603   * @retval HAL status.
01604   */
01605 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
01606 {
01607   HAL_StatusTypeDef tmp_hal_status;
01608
01609   /* Check the parameters */
01610   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01611
01612   __HAL_LOCK(hadc);
01613
01614   /* 1. Stop potential conversion on going, on ADC group regular */
01615   tmp_hal_status = ADC_ConversionStop(hadc);
01616
01617   /* Disable ADC peripheral if conversions are effectively stopped */
01618   if (tmp_hal_status == HAL_OK)
01619   {
01620     /* Disable ADC end of conversion interrupt for regular group */
01621     /* Disable ADC overrun interrupt */
01622     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01623
01624     /* 2. Disable the ADC peripheral */
01625     tmp_hal_status = ADC_Disable(hadc);
01626
01627     /* Check if ADC is effectively disabled */
01628     if (tmp_hal_status == HAL_OK)
01629     {
01630       /* Set ADC state */
01631       ADC_STATE_CLR_SET(hadc->State,
01632                         HAL_ADC_STATE_REG_BUSY,
01633                         HAL_ADC_STATE_READY);
01634     }
01635   }
01636
01637   __HAL_UNLOCK(hadc);
01638
01639   return tmp_hal_status;
01640 }
01641
01642 /**
01643   * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
01644   * @note   Interruptions enabled in this function:
01645   *         overrun (if applicable), DMA half transfer, DMA transfer complete.
01646   *         Each of these interruptions has its dedicated callback function.
01647   * @param hadc ADC handle
01648   * @param pData Destination Buffer address.
01649   * @param Length Number of data to be transferred from ADC peripheral to memory
01650   * @retval HAL status.
01651   */
01652 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
01653 {
01654   HAL_StatusTypeDef tmp_hal_status;
01655
01656   /* Check the parameters */
01657   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01658
01659   /* Perform ADC enable and conversion start if no conversion is on going */
01660   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01661   {
01662     __HAL_LOCK(hadc);
01663
01664     /* Specific case for first call occurrence of this function (DMA transfer */
01665     /* not activated and ADC disabled), DMA transfer must be activated        */
01666     /* with ADC disabled.                                                     */
01667     if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL)
01668     {
01669       if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
01670       {
01671         /* Disable ADC */
01672         LL_ADC_Disable(hadc->Instance);
01673       }
01674
01675       /* Enable ADC DMA mode */
01676       hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
01677     }
01678
01679     /* Enable the ADC peripheral */
01680     tmp_hal_status = ADC_Enable(hadc);
01681
01682     /* Start conversion if ADC is effectively enabled */
01683     if (tmp_hal_status == HAL_OK)
01684     {
01685       /* Set ADC state                                                        */
01686       /* - Clear state bitfield related to regular group conversion results   */
01687       /* - Set state bitfield related to regular operation                    */
01688       ADC_STATE_CLR_SET(hadc->State,
01689                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01690                         HAL_ADC_STATE_REG_BUSY);
01691
01692       /* Set ADC error code */
01693       /* Reset all ADC error code fields */
01694       ADC_CLEAR_ERRORCODE(hadc);
01695
01696       /* Set the DMA transfer complete callback */
01697       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01698
01699       /* Set the DMA half transfer complete callback */
01700       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01701
01702       /* Set the DMA error callback */
01703       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
01704
01705
01706       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
01707       /* start (in case of SW start):                                         */
01708
01709       /* Clear regular group conversion flag and overrun flag */
01710       /* (To ensure of no unknown state from potential previous ADC           */
01711       /* operations)                                                          */
01712       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01713
01714       /* Process unlocked */
01715       /* Unlock before starting ADC conversions: in case of potential         */
01716       /* interruption, to let the process to ADC IRQ Handler.                 */
01717       __HAL_UNLOCK(hadc);
01718
01719       /* Enable ADC overrun interrupt */
01720       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01721
01722       /* Start the DMA channel */
01723       tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
01724
01725       /* Enable conversion of regular group.                                  */
01726       /* If software start has been selected, conversion starts immediately.  */
01727       /* If external trigger has been selected, conversion will start at next */
01728       /* trigger event.                                                       */
01729       /* Start ADC group regular conversion */
01730       LL_ADC_REG_StartConversion(hadc->Instance);
01731     }
01732   }
01733   else
01734   {
01735     tmp_hal_status = HAL_BUSY;
01736   }
01737
01738   return tmp_hal_status;
01739 }
01740
01741 /**
01742   * @brief  Stop ADC conversion of regular group (and injected group in
01743   *         case of auto_injection mode), disable ADC DMA transfer, disable
01744   *         ADC peripheral.
01745   * @param hadc ADC handle
01746   * @retval HAL status.
01747   */
01748 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
01749 {
01750   HAL_StatusTypeDef tmp_hal_status;
01751
01752   /* Check the parameters */
01753   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01754
01755   __HAL_LOCK(hadc);
01756
01757   /* 1. Stop potential ADC group regular conversion on going */
01758   tmp_hal_status = ADC_ConversionStop(hadc);
01759
01760   /* Disable ADC peripheral if conversions are effectively stopped */
01761   if (tmp_hal_status == HAL_OK)
01762   {
01763     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01764     /* while DMA transfer is on going)                                        */
01765     if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
01766     {
01767       tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01768
01769       /* Check if DMA channel effectively disabled */
01770       if (tmp_hal_status != HAL_OK)
01771       {
01772         /* Update ADC state machine to error */
01773         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01774       }
01775     }
01776
01777     /* Disable ADC overrun interrupt */
01778     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01779
01780     /* 2. Disable the ADC peripheral */
01781     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
01782     /* to keep in memory a potential failing status.                          */
01783     if (tmp_hal_status == HAL_OK)
01784     {
01785       tmp_hal_status = ADC_Disable(hadc);
01786     }
01787     else
01788     {
01789       (void)ADC_Disable(hadc);
01790     }
01791
01792     /* Check if ADC is effectively disabled */
01793     if (tmp_hal_status == HAL_OK)
01794     {
01795       /* Set ADC state */
01796       ADC_STATE_CLR_SET(hadc->State,
01797                         HAL_ADC_STATE_REG_BUSY,
01798                         HAL_ADC_STATE_READY);
01799     }
01800
01801     /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
01802     CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
01803   }
01804
01805   __HAL_UNLOCK(hadc);
01806
01807   return tmp_hal_status;
01808 }
01809
01810 /**
01811   * @brief  Get ADC regular group conversion result.
01812   * @note   Reading register DR automatically clears ADC flag EOC
01813   *         (ADC group regular end of unitary conversion).
01814   * @note   This function does not clear ADC flag EOS
01815   *         (ADC group regular end of sequence conversion).
01816   *         Occurrence of flag EOS rising:
01817   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
01818   *            to flag EOC.
01819   *          - If sequencer is composed of several ranks, during the scan
01820   *            sequence flag EOC only is raised, at the end of the scan sequence
01821   *            both flags EOC and EOS are raised.
01822   *         To clear this flag, either use function:
01823   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
01824   *         model polling: @ref HAL_ADC_PollForConversion()
01825   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
01826   * @param hadc ADC handle
01827   * @retval ADC group regular conversion data
01828   */
01829 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
01830 {
01831   /* Check the parameters */
01832   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01833
01834   /* Note: EOC flag is not cleared here by software because automatically     */
01835   /*       cleared by hardware when reading register DR.                      */
01836
01837   /* Return ADC converted value */
01838   return hadc->Instance->DR;
01839 }
01840
01841 /**
01842   * @brief  Handle ADC interrupt request.
01843   * @param hadc ADC handle
01844   * @retval None
01845   */
01846 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
01847 {
01848   uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
01849   uint32_t tmp_isr = hadc->Instance->ISR;
01850   uint32_t tmp_ier = hadc->Instance->IER;
01851
01852   /* Check the parameters */
01853   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01854   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
01855
01856   /* ========== Check End of Sampling flag for ADC group regular ========== */
01857   if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
01858   {
01859     /* Update state machine on end of sampling status if not in error state */
01860     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
01861     {
01862       /* Set ADC state */
01863       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01864     }
01865
01866     /* End Of Sampling callback */
01867 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01868     hadc->EndOfSamplingCallback(hadc);
01869 #else
01870     HAL_ADCEx_EndOfSamplingCallback(hadc);
01871 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01872
01873     /* Clear regular group conversion flag */
01874     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01875   }
01876
01877   /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
01878   if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
01879       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
01880   {
01881     /* Update state machine on conversion status if not in error state */
01882     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
01883     {
01884       /* Set ADC state */
01885       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01886     }
01887
01888     /* Determine whether any further conversion upcoming on group regular     */
01889     /* by external trigger, continuous mode or scan sequence on going         */
01890     /* to disable interruption.                                               */
01891     if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
01892         && (hadc->Init.ContinuousConvMode == DISABLE)
01893        )
01894     {
01895       /* If End of Sequence is reached, disable interrupts */
01896       if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
01897       {
01898         /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
01899         /* ADSTART==0 (no conversion on going)                                */
01900         if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01901         {
01902           /* Disable ADC end of single conversion interrupt on group regular */
01903           /* Note: Overrun interrupt was enabled with EOC interrupt in        */
01904           /* HAL_Start_IT(), but is not disabled here because can be used     */
01905           /* by overrun IRQ process below.                                    */
01906           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
01907
01908           /* Set ADC state */
01909           ADC_STATE_CLR_SET(hadc->State,
01910                             HAL_ADC_STATE_REG_BUSY,
01911                             HAL_ADC_STATE_READY);
01912         }
01913         else
01914         {
01915           /* Change ADC state to error state */
01916           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01917
01918           /* Set ADC error code to ADC peripheral internal error */
01919           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01920         }
01921       }
01922     }
01923
01924     /* Conversion complete callback */
01925     /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
01926     /*       to determine if conversion has been triggered from EOC or EOS,   */
01927     /*       possibility to use:                                              */
01928     /*        " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "               */
01929 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01930     hadc->ConvCpltCallback(hadc);
01931 #else
01932     HAL_ADC_ConvCpltCallback(hadc);
01933 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01934
01935     /* Clear regular group conversion flag */
01936     /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
01937     /*       conversion flags clear induces the release of the preserved data.*/
01938     /*       Therefore, if the preserved data value is needed, it must be     */
01939     /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
01940     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
01941   }
01942
01943   /* ========== Check Analog watchdog 1 flag ========== */
01944   if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
01945   {
01946     /* Set ADC state */
01947     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01948
01949     /* Level out of window 1 callback */
01950 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01951     hadc->LevelOutOfWindowCallback(hadc);
01952 #else
01953     HAL_ADC_LevelOutOfWindowCallback(hadc);
01954 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01955
01956     /* Clear ADC analog watchdog flag */
01957     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01958   }
01959
01960   /* ========== Check analog watchdog 2 flag ========== */
01961   if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
01962   {
01963     /* Set ADC state */
01964     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01965
01966     /* Level out of window 2 callback */
01967 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01968     hadc->LevelOutOfWindow2Callback(hadc);
01969 #else
01970     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
01971 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01972
01973     /* Clear ADC analog watchdog flag */
01974     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01975   }
01976
01977   /* ========== Check analog watchdog 3 flag ========== */
01978   if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
01979   {
01980     /* Set ADC state */
01981     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01982
01983     /* Level out of window 3 callback */
01984 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01985     hadc->LevelOutOfWindow3Callback(hadc);
01986 #else
01987     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
01988 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01989
01990     /* Clear ADC analog watchdog flag */
01991     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01992   }
01993
01994   /* ========== Check Overrun flag ========== */
01995   if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
01996   {
01997     /* If overrun is set to overwrite previous data (default setting),        */
01998     /* overrun event is not considered as an error.                           */
01999     /* (cf ref manual "Managing conversions without using the DMA and without */
02000     /* overrun ")                                                             */
02001     /* Exception for usage with DMA overrun event always considered as an     */
02002     /* error.                                                                 */
02003     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
02004     {
02005       overrun_error = 1UL;
02006     }
02007     else
02008     {
02009       /* Check DMA configuration */
02010       if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
02011       {
02012         overrun_error = 1UL;
02013       }
02014     }
02015
02016     if (overrun_error == 1UL)
02017     {
02018       /* Change ADC state to error state */
02019       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
02020
02021       /* Set ADC error code to overrun */
02022       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
02023
02024       /* Error callback */
02025       /* Note: In case of overrun, ADC conversion data is preserved until     */
02026       /*       flag OVR is reset.                                             */
02027       /*       Therefore, old ADC conversion data can be retrieved in         */
02028       /*       function "HAL_ADC_ErrorCallback()".                            */
02029 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02030       hadc->ErrorCallback(hadc);
02031 #else
02032       HAL_ADC_ErrorCallback(hadc);
02033 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02034     }
02035
02036     /* Clear ADC overrun flag */
02037     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
02038   }
02039
02040   /* ========== Check channel configuration ready flag ========== */
02041   if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY))
02042   {
02043     /* Channel configuration ready callback */
02044     HAL_ADCEx_ChannelConfigReadyCallback(hadc);
02045
02046     /* Clear ADC analog watchdog flag */
02047     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY);
02048   }
02049 }
02050
02051 /**
02052   * @brief  Conversion complete callback in non-blocking mode.
02053   * @param hadc ADC handle
02054   * @retval None
02055   */
02056 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
02057 {
02058   /* Prevent unused argument(s) compilation warning */
02059   UNUSED(hadc);
02060
02061   /* NOTE : This function should not be modified. When the callback is needed,
02062             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
02063    */
02064 }
02065
02066 /**
02067   * @brief  Conversion DMA half-transfer callback in non-blocking mode.
02068   * @param hadc ADC handle
02069   * @retval None
02070   */
02071 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
02072 {
02073   /* Prevent unused argument(s) compilation warning */
02074   UNUSED(hadc);
02075
02076   /* NOTE : This function should not be modified. When the callback is needed,
02077             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
02078   */
02079 }
02080
02081 /**
02082   * @brief  Analog watchdog 1 callback in non-blocking mode.
02083   * @param hadc ADC handle
02084   * @retval None
02085   */
02086 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
02087 {
02088   /* Prevent unused argument(s) compilation warning */
02089   UNUSED(hadc);
02090
02091   /* NOTE : This function should not be modified. When the callback is needed,
02092             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
02093   */
02094 }
02095
02096 /**
02097   * @brief  ADC error callback in non-blocking mode
02098   *         (ADC conversion with interruption or transfer by DMA).
02099   * @note   In case of error due to overrun when using ADC with DMA transfer
02100   *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
02101   *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
02102   *         - If needed, restart a new ADC conversion using function
02103   *           "HAL_ADC_Start_DMA()"
02104   *           (this function is also clearing overrun flag)
02105   * @param hadc ADC handle
02106   * @retval None
02107   */
02108 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
02109 {
02110   /* Prevent unused argument(s) compilation warning */
02111   UNUSED(hadc);
02112
02113   /* NOTE : This function should not be modified. When the callback is needed,
02114             function HAL_ADC_ErrorCallback must be implemented in the user file.
02115   */
02116 }
02117
02118 /**
02119   * @}
02120   */
02121
02122 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
02123   * @brief    Peripheral Control functions
02124   *
02125 @verbatim
02126  ===============================================================================
02127              ##### Peripheral Control functions #####
02128  ===============================================================================
02129     [..]  This section provides functions allowing to:
02130       (+) Configure channels on regular group
02131       (+) Configure the analog watchdog
02132
02133 @endverbatim
02134   * @{
02135   */
02136
02137 /**
02138   * @brief  Configure a channel to be assigned to ADC group regular.
02139   * @note   In case of usage of internal measurement channels:
02140   *         Vbat/VrefInt/TempSensor.
02141   *         These internal paths can be disabled using function
02142   *         HAL_ADC_DeInit().
02143   * @note   Possibility to update parameters on the fly:
02144   *         This function initializes channel into ADC group regular,
02145   *         following calls to this function can be used to reconfigure
02146   *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
02147   *         without resetting the ADC.
02148   *         The setting of these parameters is conditioned to ADC state:
02149   *         Refer to comments of structure "ADC_ChannelConfTypeDef".
02150   * @param hadc ADC handle
02151   * @param pConfig Structure of ADC channel assigned to ADC group regular.
02152   * @retval HAL status
02153   */
02154 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
02155 {
02156   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02157   uint32_t tmp_config_internal_channel;
02158   __IO uint32_t wait_loop_index = 0UL;
02159
02160   /* Check the parameters */
02161   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02162   assert_param(IS_ADC_CHANNEL(pConfig->Channel));
02163   assert_param(IS_ADC_SAMPLING_TIME_COMMON(pConfig->SamplingTime));
02164
02165   if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
02166       (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
02167   {
02168     assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(pConfig->Rank));
02169   }
02170   else
02171   {
02172     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
02173
02174     assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
02175   }
02176
02177   __HAL_LOCK(hadc);
02178
02179   /* Parameters update conditioned to ADC state:                              */
02180   /* Parameters that can be updated when ADC is disabled or enabled without   */
02181   /* conversion on going on regular group:                                    */
02182   /*  - Channel number                                                        */
02183   /*  - Channel sampling time                                                 */
02184   /*  - Management of internal measurement channels: VrefInt/TempSensor/Vbat  */
02185   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02186   {
02187     /* Configure channel: depending on rank setting, add it or remove it from */
02188     /* ADC sequencer.                                                         */
02189     /* If sequencer set to not fully configurable with channel rank set to    */
02190     /* none, remove the channel from the sequencer.                           */
02191     /* Otherwise (sequencer set to fully configurable or to to not fully      */
02192     /* configurable with channel rank to be set), configure the selected      */
02193     /* channel.                                                               */
02194     if (pConfig->Rank != ADC_RANK_NONE)
02195     {
02196       /* Regular sequence configuration */
02197       /* Note: ADC channel configuration requires few ADC clock cycles        */
02198       /*       to be ready. Processing of ADC settings in this function       */
02199       /*       induce that a specific wait time is not necessary.             */
02200       /*       For more details on ADC channel configuration ready,           */
02201       /*       refer to function "LL_ADC_IsActiveFlag_CCRDY()".               */
02202       if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
02203           (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
02204       {
02205         /* Sequencer set to not fully configurable:                           */
02206         /* Set the channel by enabling the corresponding bitfield.            */
02207         LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel);
02208       }
02209       else
02210       {
02211         /* Sequencer set to fully configurable:                               */
02212         /* Set the channel by entering it into the selected rank.             */
02213
02214         /* Memorize the channel set into variable in HAL ADC handle */
02215         MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
02216                    ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL),
02217                    __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) << (pConfig->Rank & 0x1FUL));
02218
02219         /* If the selected rank is below ADC group regular sequencer length,  */
02220         /* apply the configuration in ADC register.                           */
02221         /* Note: Otherwise, configuration is not applied.                     */
02222         /*       To apply it, parameter'NbrOfConversion' must be increased.   */
02223         if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
02224         {
02225           LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
02226         }
02227       }
02228
02229       /* Set sampling time of the selected ADC channel */
02230       LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
02231
02232       /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
02233       /* internal measurement paths enable: If internal channel selected,     */
02234       /* enable dedicated internal buffers and path.                          */
02235       /* Note: these internal measurement paths can be disabled using         */
02236       /*       HAL_ADC_DeInit() or removing the channel from sequencer with   */
02237       /*       channel configuration parameter "Rank".                        */
02238       if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
02239       {
02240         tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02241
02242         /* If the requested internal measurement path has already been enabled,   */
02243         /* bypass the configuration processing.                                   */
02244         if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
02245             ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
02246         {
02247           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02248                                          LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
02249
02250           /* Delay for temperature sensor stabilization time */
02251           /* Wait loop initialization and execution */
02252           /* Note: Variable divided by 2 to compensate partially              */
02253           /*       CPU processing cycles, scaling in us split to not          */
02254           /*       exceed 32 bits register capacity and handle low frequency. */
02255           wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
02256           while (wait_loop_index != 0UL)
02257           {
02258             wait_loop_index--;
02259           }
02260         }
02261         else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
02262         {
02263           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02264                                          LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
02265         }
02266         else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
02267                  ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
02268         {
02269           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02270                                          LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
02271         }
02272         else
02273         {
02274           /* nothing to do */
02275         }
02276       }
02277     }
02278     else
02279     {
02280       /* Regular sequencer configuration */
02281       /* Note: Case of sequencer set to fully configurable:                   */
02282       /*       Sequencer rank cannot be disabled, only affected to            */
02283       /*       another channel.                                               */
02284       /*       To remove a rank, use parameter 'NbrOfConversion".             */
02285       if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
02286           (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
02287       {
02288         /* Sequencer set to not fully configurable:                           */
02289         /* Reset the channel by disabling the corresponding bitfield.         */
02290         LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel);
02291       }
02292
02293       /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
02294       /* If internal channel selected, enable dedicated internal buffers and    */
02295       /* paths.                                                                 */
02296       if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
02297       {
02298         tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02299
02300         if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
02301         {
02302           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02303                                          ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
02304         }
02305         else if (pConfig->Channel == ADC_CHANNEL_VBAT)
02306         {
02307           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02308                                          ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
02309         }
02310         else if (pConfig->Channel == ADC_CHANNEL_VREFINT)
02311         {
02312           LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
02313                                          ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
02314         }
02315         else
02316         {
02317           /* nothing to do */
02318         }
02319       }
02320     }
02321   }
02322
02323   /* If a conversion is on going on regular group, no update on regular       */
02324   /* channel could be done on neither of the channel configuration structure  */
02325   /* parameters.                                                              */
02326   else
02327   {
02328     /* Update ADC state machine to error */
02329     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02330
02331     tmp_hal_status = HAL_ERROR;
02332   }
02333
02334   __HAL_UNLOCK(hadc);
02335
02336   return tmp_hal_status;
02337 }
02338
02339 /**
02340   * @brief  Configure the analog watchdog.
02341   * @note   Possibility to update parameters on the fly:
02342   *         This function initializes the selected analog watchdog, successive
02343   *         calls to this function can be used to reconfigure some parameters
02344   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
02345   *         the ADC.
02346   *         The setting of these parameters is conditioned to ADC state.
02347   *         For parameters constraints, see comments of structure
02348   *         "ADC_AnalogWDGConfTypeDef".
02349   * @note   On this STM32 series, analog watchdog thresholds can be modified
02350   *         while ADC conversion is on going.
02351   *         In this case, some constraints must be taken into account:
02352   *         the programmed threshold values are effective from the next
02353   *         ADC EOC (end of unitary conversion).
02354   *         Considering that registers write delay may happen due to
02355   *         bus activity, this might cause an uncertainty on the
02356   *         effective timing of the new programmed threshold values.
02357   * @param hadc ADC handle
02358   * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
02359   * @retval HAL status
02360   */
02361 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
02362 {
02363   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02364   uint32_t tmp_awd_high_threshold_shifted;
02365   uint32_t tmp_awd_low_threshold_shifted;
02366   uint32_t backup_setting_adc_enable_state = 0UL;
02367
02368   /* Check the parameters */
02369   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02370   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
02371   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
02372   assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
02373
02374   if (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
02375   {
02376     assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel));
02377   }
02378
02379   /* Verify thresholds range */
02380   if (hadc->Init.OversamplingMode == ENABLE)
02381   {
02382     /* Case of oversampling enabled: depending on ratio and shift configuration,
02383        analog watchdog thresholds can be higher than ADC resolution.
02384        Verify if thresholds are within maximum thresholds range. */
02385     assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
02386     assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
02387   }
02388   else
02389   {
02390     /* Verify if thresholds are within the selected ADC resolution */
02391     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
02392     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
02393   }
02394
02395   __HAL_LOCK(hadc);
02396
02397   /* Parameters update conditioned to ADC state:                              */
02398   /* Parameters that can be updated when ADC is disabled or enabled without   */
02399   /* conversion on going on ADC group regular:                                */
02400   /*  - Analog watchdog channels                                              */
02401   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02402   {
02403     /* Analog watchdog configuration */
02404     if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
02405     {
02406       /* Constraint of ADC on this STM32 series: ADC must be disable
02407          to modify bitfields of register ADC_CFGR1 */
02408       if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
02409       {
02410         backup_setting_adc_enable_state = 1UL;
02411         tmp_hal_status = ADC_Disable(hadc);
02412       }
02413
02414       /* Configuration of analog watchdog:                                    */
02415       /*  - Set the analog watchdog enable mode: one or overall group of      */
02416       /*    channels.                                                         */
02417       switch (pAnalogWDGConfig->WatchdogMode)
02418       {
02419         case ADC_ANALOGWATCHDOG_SINGLE_REG:
02420           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
02421                                           __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
02422           break;
02423
02424         case ADC_ANALOGWATCHDOG_ALL_REG:
02425           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
02426           break;
02427
02428         default: /* ADC_ANALOGWATCHDOG_NONE */
02429           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
02430           break;
02431       }
02432
02433       if (backup_setting_adc_enable_state == 1UL)
02434       {
02435         if (tmp_hal_status == HAL_OK)
02436         {
02437           tmp_hal_status = ADC_Enable(hadc);
02438         }
02439       }
02440
02441       /* Update state, clear previous result related to AWD1 */
02442       CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02443
02444       /* Clear flag ADC analog watchdog */
02445       /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
02446       /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
02447       /* (in case left enabled by previous ADC operations).                 */
02448       LL_ADC_ClearFlag_AWD1(hadc->Instance);
02449
02450       /* Configure ADC analog watchdog interrupt */
02451       if (pAnalogWDGConfig->ITMode == ENABLE)
02452       {
02453         LL_ADC_EnableIT_AWD1(hadc->Instance);
02454       }
02455       else
02456       {
02457         LL_ADC_DisableIT_AWD1(hadc->Instance);
02458       }
02459     }
02460     /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
02461     else
02462     {
02463       switch (pAnalogWDGConfig->WatchdogMode)
02464       {
02465         case ADC_ANALOGWATCHDOG_SINGLE_REG:
02466           /* Update AWD by bitfield to keep the possibility to monitor        */
02467           /* several channels by successive calls of this function.           */
02468           if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
02469           {
02470             SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel)));
02471           }
02472           else
02473           {
02474             SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel)));
02475           }
02476           break;
02477
02478         case ADC_ANALOGWATCHDOG_ALL_REG:
02479           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
02480           break;
02481
02482         default: /* ADC_ANALOGWATCHDOG_NONE */
02483           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
02484           break;
02485       }
02486
02487       if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
02488       {
02489         /* Update state, clear previous result related to AWD2 */
02490         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02491
02492         /* Clear flag ADC analog watchdog */
02493         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
02494         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
02495         /* (in case left enabled by previous ADC operations).                 */
02496         LL_ADC_ClearFlag_AWD2(hadc->Instance);
02497
02498         /* Configure ADC analog watchdog interrupt */
02499         if (pAnalogWDGConfig->ITMode == ENABLE)
02500         {
02501           LL_ADC_EnableIT_AWD2(hadc->Instance);
02502         }
02503         else
02504         {
02505           LL_ADC_DisableIT_AWD2(hadc->Instance);
02506         }
02507       }
02508       /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
02509       else
02510       {
02511         /* Update state, clear previous result related to AWD3 */
02512         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02513
02514         /* Clear flag ADC analog watchdog */
02515         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
02516         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
02517         /* (in case left enabled by previous ADC operations).                 */
02518         LL_ADC_ClearFlag_AWD3(hadc->Instance);
02519
02520         /* Configure ADC analog watchdog interrupt */
02521         if (pAnalogWDGConfig->ITMode == ENABLE)
02522         {
02523           LL_ADC_EnableIT_AWD3(hadc->Instance);
02524         }
02525         else
02526         {
02527           LL_ADC_DisableIT_AWD3(hadc->Instance);
02528         }
02529       }
02530     }
02531
02532   }
02533
02534   /* Analog watchdog thresholds configuration */
02535   if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
02536   {
02537     /* Shift the offset with respect to the selected ADC resolution:        */
02538     /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
02539     /* are set to 0.                                                        */
02540     tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
02541     tmp_awd_low_threshold_shifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
02542   }
02543   /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
02544   else
02545   {
02546     /* No need to shift the offset with respect to the selected ADC resolution: */
02547     /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
02548     /* are set to 0.                                                        */
02549     tmp_awd_high_threshold_shifted = pAnalogWDGConfig->HighThreshold;
02550     tmp_awd_low_threshold_shifted  = pAnalogWDGConfig->LowThreshold;
02551   }
02552
02553   /* Set ADC analog watchdog thresholds value of both thresholds high and low */
02554   LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
02555                                   tmp_awd_low_threshold_shifted);
02556
02557   __HAL_UNLOCK(hadc);
02558
02559   return tmp_hal_status;
02560 }
02561
02562
02563 /**
02564   * @}
02565   */
02566
02567 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
02568   *  @brief    ADC Peripheral State functions
02569   *
02570 @verbatim
02571  ===============================================================================
02572             ##### Peripheral state and errors functions #####
02573  ===============================================================================
02574     [..]
02575     This subsection provides functions to get in run-time the status of the
02576     peripheral.
02577       (+) Check the ADC state
02578       (+) Check the ADC error code
02579
02580 @endverbatim
02581   * @{
02582   */
02583
02584 /**
02585   * @brief  Return the ADC handle state.
02586   * @note   ADC state machine is managed by bitfields, ADC status must be
02587   *         compared with states bits.
02588   *         For example:
02589   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
02590   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
02591   * @param hadc ADC handle
02592   * @retval ADC handle state (bitfield on 32 bits)
02593   */
02594 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
02595 {
02596   /* Check the parameters */
02597   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02598
02599   /* Return ADC handle state */
02600   return hadc->State;
02601 }
02602
02603 /**
02604   * @brief  Return the ADC error code.
02605   * @param hadc ADC handle
02606   * @retval ADC error code (bitfield on 32 bits)
02607   */
02608 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
02609 {
02610   /* Check the parameters */
02611   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02612
02613   return hadc->ErrorCode;
02614 }
02615
02616 /**
02617   * @}
02618   */
02619
02620 /**
02621   * @}
02622   */
02623
02624 /** @defgroup ADC_Private_Functions ADC Private Functions
02625   * @{
02626   */
02627
02628 /**
02629   * @brief  Stop ADC conversion.
02630   * @note   Prerequisite condition to use this function: ADC conversions must be
02631   *         stopped to disable the ADC.
02632   * @param  hadc ADC handle
02633   * @retval HAL status.
02634   */
02635 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc)
02636 {
02637   uint32_t tickstart;
02638
02639   /* Check the parameters */
02640   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02641
02642   /* Verification if ADC is not already stopped on regular group to bypass    */
02643   /* this function if not needed.                                             */
02644   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
02645   {
02646     /* Stop potential conversion on going on regular group */
02647     /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
02648     if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
02649     {
02650       /* Stop ADC group regular conversion */
02651       LL_ADC_REG_StopConversion(hadc->Instance);
02652     }
02653
02654     /* Wait for conversion effectively stopped */
02655     /* Get tick count */
02656     tickstart = HAL_GetTick();
02657
02658     while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
02659     {
02660       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
02661       {
02662         /* New check to avoid false timeout detection in case of preemption */
02663         if ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
02664         {
02665           /* Update ADC state machine to error */
02666           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02667
02668           /* Set ADC error code to ADC peripheral internal error */
02669           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02670
02671           return HAL_ERROR;
02672         }
02673       }
02674     }
02675
02676   }
02677
02678   /* Return HAL status */
02679   return HAL_OK;
02680 }
02681
02682 /**
02683   * @brief  Enable the selected ADC.
02684   * @note   Prerequisite condition to use this function: ADC must be disabled
02685   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
02686   * @param hadc ADC handle
02687   * @retval HAL status.
02688   */
02689 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
02690 {
02691   uint32_t tickstart;
02692   __IO uint32_t wait_loop_index = 0UL;
02693
02694   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
02695   /* enabling phase not yet completed: flag ADC ready not yet set).           */
02696   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
02697   /* causes: ADC clock not running, ...).                                     */
02698   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02699   {
02700     /* Check if conditions to enable the ADC are fulfilled */
02701     if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
02702     {
02703       /* Update ADC state machine to error */
02704       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02705
02706       /* Set ADC error code to ADC peripheral internal error */
02707       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02708
02709       return HAL_ERROR;
02710     }
02711
02712     /* Enable the ADC peripheral */
02713     LL_ADC_Enable(hadc->Instance);
02714
02715     if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
02716     {
02717       /* Delay for temperature sensor buffer stabilization time */
02718       /* Wait loop initialization and execution */
02719       /* Note: Variable divided by 2 to compensate partially              */
02720       /*       CPU processing cycles, scaling in us split to not          */
02721       /*       exceed 32 bits register capacity and handle low frequency. */
02722       wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
02723       while (wait_loop_index != 0UL)
02724       {
02725         wait_loop_index--;
02726       }
02727     }
02728
02729     /* If low power mode AutoPowerOff is enabled, power-on/off phases are     */
02730     /* performed automatically by hardware and flag ADC ready is not set.     */
02731     if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
02732     {
02733       /* Wait for ADC effectively enabled */
02734       tickstart = HAL_GetTick();
02735
02736       while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
02737       {
02738         /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
02739             has been cleared (after a calibration), ADEN bit is reset by the
02740             calibration logic.
02741             The workaround is to continue setting ADEN until ADRDY is becomes 1.
02742             Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
02743             4 ADC clock cycle duration */
02744         /* Note: Test of ADC enabled required due to hardware constraint to     */
02745         /*       not enable ADC if already enabled.                             */
02746         if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02747         {
02748           LL_ADC_Enable(hadc->Instance);
02749         }
02750
02751         if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
02752         {
02753           /* New check to avoid false timeout detection in case of preemption */
02754           if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
02755           {
02756             /* Update ADC state machine to error */
02757             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02758
02759             /* Set ADC error code to ADC peripheral internal error */
02760             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02761
02762             return HAL_ERROR;
02763           }
02764         }
02765       }
02766     }
02767   }
02768
02769   /* Return HAL status */
02770   return HAL_OK;
02771 }
02772
02773 /**
02774   * @brief  Disable the selected ADC.
02775   * @note   Prerequisite condition to use this function: ADC conversions must be
02776   *         stopped.
02777   * @param hadc ADC handle
02778   * @retval HAL status.
02779   */
02780 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
02781 {
02782   uint32_t tickstart;
02783   const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
02784
02785   /* Verification if ADC is not already disabled:                             */
02786   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
02787   /*       disabled.                                                          */
02788   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
02789       && (tmp_adc_is_disable_on_going == 0UL)
02790      )
02791   {
02792     /* Check if conditions to disable the ADC are fulfilled */
02793     if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
02794     {
02795       /* Disable the ADC peripheral */
02796       LL_ADC_Disable(hadc->Instance);
02797       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
02798     }
02799     else
02800     {
02801       /* Update ADC state machine to error */
02802       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02803
02804       /* Set ADC error code to ADC peripheral internal error */
02805       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02806
02807       return HAL_ERROR;
02808     }
02809
02810     /* Wait for ADC effectively disabled */
02811     /* Get tick count */
02812     tickstart = HAL_GetTick();
02813
02814     while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
02815     {
02816       if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
02817       {
02818         /* New check to avoid false timeout detection in case of preemption */
02819         if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
02820         {
02821           /* Update ADC state machine to error */
02822           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02823
02824           /* Set ADC error code to ADC peripheral internal error */
02825           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02826
02827           return HAL_ERROR;
02828         }
02829       }
02830     }
02831   }
02832
02833   /* Return HAL status */
02834   return HAL_OK;
02835 }
02836
02837 /**
02838   * @brief  DMA transfer complete callback.
02839   * @param hdma pointer to DMA handle.
02840   * @retval None
02841   */
02842 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
02843 {
02844   /* Retrieve ADC handle corresponding to current DMA handle */
02845   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02846
02847   /* Update state machine on conversion status if not in error state */
02848   if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
02849   {
02850     /* Set ADC state */
02851     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
02852
02853     /* Determine whether any further conversion upcoming on group regular     */
02854     /* by external trigger, continuous mode or scan sequence on going         */
02855     /* to disable interruption.                                               */
02856     if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
02857         && (hadc->Init.ContinuousConvMode == DISABLE)
02858        )
02859     {
02860       /* If End of Sequence is reached, disable interrupts */
02861       if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
02862       {
02863         /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
02864         /* ADSTART==0 (no conversion on going)                                */
02865         if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02866         {
02867           /* Disable ADC end of single conversion interrupt on group regular */
02868           /* Note: Overrun interrupt was enabled with EOC interrupt in        */
02869           /* HAL_Start_IT(), but is not disabled here because can be used     */
02870           /* by overrun IRQ process below.                                    */
02871           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
02872
02873           /* Set ADC state */
02874           ADC_STATE_CLR_SET(hadc->State,
02875                             HAL_ADC_STATE_REG_BUSY,
02876                             HAL_ADC_STATE_READY);
02877         }
02878         else
02879         {
02880           /* Change ADC state to error state */
02881           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02882
02883           /* Set ADC error code to ADC peripheral internal error */
02884           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02885         }
02886       }
02887     }
02888
02889     /* Conversion complete callback */
02890 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02891     hadc->ConvCpltCallback(hadc);
02892 #else
02893     HAL_ADC_ConvCpltCallback(hadc);
02894 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02895   }
02896   else /* DMA and-or internal error occurred */
02897   {
02898     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
02899     {
02900       /* Call HAL ADC Error Callback function */
02901 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02902       hadc->ErrorCallback(hadc);
02903 #else
02904       HAL_ADC_ErrorCallback(hadc);
02905 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02906     }
02907     else
02908     {
02909       /* Call ADC DMA error callback */
02910       hadc->DMA_Handle->XferErrorCallback(hdma);
02911     }
02912   }
02913 }
02914
02915 /**
02916   * @brief  DMA half transfer complete callback.
02917   * @param hdma pointer to DMA handle.
02918   * @retval None
02919   */
02920 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
02921 {
02922   /* Retrieve ADC handle corresponding to current DMA handle */
02923   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02924
02925   /* Half conversion callback */
02926 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02927   hadc->ConvHalfCpltCallback(hadc);
02928 #else
02929   HAL_ADC_ConvHalfCpltCallback(hadc);
02930 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02931 }
02932
02933 /**
02934   * @brief  DMA error callback.
02935   * @param hdma pointer to DMA handle.
02936   * @retval None
02937   */
02938 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
02939 {
02940   /* Retrieve ADC handle corresponding to current DMA handle */
02941   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02942
02943   /* Set ADC state */
02944   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
02945
02946   /* Set ADC error code to DMA error */
02947   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
02948
02949   /* Error callback */
02950 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02951   hadc->ErrorCallback(hadc);
02952 #else
02953   HAL_ADC_ErrorCallback(hadc);
02954 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02955 }
02956
02957 /**
02958   * @}
02959   */
02960
02961 #endif /* HAL_ADC_MODULE_ENABLED */
02962 /**
02963   * @}
02964   */
02965
02966 /**
02967   * @}
02968   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_adc.h Source File

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stm32g0xx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_ADC_H
00021 #define STM32G0xx_HAL_ADC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /* Include low level driver */
00031 #include "stm32g0xx_ll_adc.h"
00032
00033 /** @addtogroup STM32G0xx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup ADC
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup ADC_Exported_Types ADC Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  ADC group regular oversampling structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00052                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
00053
00054   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00055                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
00056
00057   uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
00058                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
00059
00060 } ADC_OversamplingTypeDef;
00061
00062 /**
00063   * @brief  Structure definition of ADC instance and ADC group regular.
00064   * @note   Parameters of this structure are shared within 2 scopes:
00065   *          - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
00066   *            ScanConvMode, EOCSelection, LowPowerAutoWait.
00067   *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
00068   *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
00069   * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
00070   *         ADC state can be either:
00071   *          - For all parameters: ADC disabled
00072   *          - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
00073   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00074   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter
00075   *         (which fulfills the ADC state condition) on the fly).
00076   */
00077 typedef struct
00078 {
00079   uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
00080                                        This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
00081                                        Note: The ADC clock configuration is common to all ADC instances.
00082                                        Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
00083                                              if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
00084                                              must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
00085                                        Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
00086                                        Note: This parameter can be modified only if all ADC instances are disabled. */
00087
00088   uint32_t Resolution;            /*!< Configure the ADC resolution.
00089                                        This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
00090
00091   uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
00092                                        Refer to reference manual for alignments formats versus resolutions.
00093                                        This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
00094
00095   uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC group regular.
00096                                        On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are
00097                                        available:
00098                                         - sequencer configured to fully configurable:
00099                                           sequencer length and each rank affectation to a channel are configurable.
00100                                            - Sequence length: Set number of ranks in the scan sequence.
00101                                            - Sequence direction: Unless specified in parameters, sequencer
00102                                              scan direction is forward (from rank 1 to rank n).
00103                                         - sequencer configured to not fully configurable:
00104                                           sequencer length and each rank affectation to a channel are fixed by channel HW number.
00105                                            - Sequence length: Number of ranks in the scan sequence is
00106                                              defined by number of channels set in the sequence,
00107                                              rank of each channel is fixed by channel HW number.
00108                                              (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
00109                                            - Sequence direction: Unless specified in parameters, sequencer
00110                                              scan direction is forward (from lowest channel number to
00111                                              highest channel number).
00112                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00113                                        Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
00114                                        If only 1 channel is set: Conversion is performed in single mode.
00115                                        If several channels are set:  Conversions are performed in sequence mode.
00116                                        This parameter can be a value of @ref ADC_Scan_mode */
00117
00118   uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
00119                                        This parameter can be a value of @ref ADC_EOCSelection. */
00120
00121   FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
00122                                        conversion (for ADC group regular) has been retrieved by user software,
00123                                        using function HAL_ADC_GetValue().
00124                                        This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
00125                                        for low frequency applications.
00126                                        This parameter can be set to ENABLE or DISABLE.
00127                                        Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
00128                                              Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
00129                                              Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
00130                                              use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
00131
00132   FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
00133                                        This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
00134                                        This parameter can be set to ENABLE or DISABLE. */
00135
00136   FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
00137                                        after the first ADC conversion start trigger occurred (software start or external trigger).
00138                                        This parameter can be set to ENABLE or DISABLE. */
00139
00140   uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group sequencer.
00141                                        This parameter is dependent on ScanConvMode:
00142                                         - sequencer configured to fully configurable:
00143                                           Number of ranks in the scan sequence is configurable using this parameter.
00144                                           Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
00145                                                 Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks
00146                                                 (sequencer ranks above 'NbrOfConversion' are discarded).
00147                                         - sequencer configured to not fully configurable:
00148                                           Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded.
00149                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8.
00150                                        Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
00151
00152   FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
00153                                        (main sequence subdivided in successive parts).
00154                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00155                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00156                                        This parameter can be set to ENABLE or DISABLE.
00157                                        Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
00158
00159   uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
00160                                        If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00161                                        This parameter can be a value of @ref ADC_regular_external_trigger_source.
00162                                        Caution: external trigger source is common to all ADC instances. */
00163
00164   uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
00165                                        If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
00166                                        This parameter can be a value of @ref ADC_regular_external_trigger_edge */
00167
00168   FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
00169                                        or in continuous mode (DMA transfer unlimited, whatever number of conversions).
00170                                        This parameter can be set to ENABLE or DISABLE.
00171                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
00172
00173   uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
00174                                        This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
00175                                        Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
00176                                        end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
00177                                        HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
00178                                        Note: Error reporting with respect to the conversion mode:
00179                                              - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
00180                                                overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
00181                                              - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
00182
00183   uint32_t SamplingTimeCommon1;   /*!< Set sampling time common to a group of channels.
00184                                        Unit: ADC clock cycles
00185                                        Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00186                                        Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
00187                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
00188                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00189                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00190                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
00191
00192   uint32_t SamplingTimeCommon2;   /*!< Set sampling time common to a group of channels, second common setting possible.
00193                                        Unit: ADC clock cycles
00194                                        Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00195                                        Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
00196                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
00197                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00198                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00199                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
00200
00201   FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
00202                                                This parameter can be set to ENABLE or DISABLE.
00203                                                Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
00204
00205   ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
00206                                                Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
00207
00208   uint32_t TriggerFrequencyMode;  /*!< Set ADC trigger frequency mode.
00209                                        This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
00210                                        Note: ADC trigger frequency mode must be set to low frequency when
00211                                              a duration is exceeded before ADC conversion start trigger event
00212                                              (between ADC enable and ADC conversion start trigger event
00213                                              or between two ADC conversion start trigger event).
00214                                              Duration value: Refer to device datasheet, parameter "tIdle".
00215                                        Note: When ADC trigger frequency mode is set to low frequency,
00216                                              some rearm cycles are inserted before performing ADC conversion
00217                                              start, inducing a delay of 2 ADC clock cycles. */
00218
00219 } ADC_InitTypeDef;
00220
00221 /**
00222   * @brief  Structure definition of ADC channel for regular group
00223   * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00224   *         ADC state can be either:
00225   *          - For all parameters: ADC disabled or enabled without conversion on going on regular group.
00226   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00227   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
00228   *         on the fly).
00229   */
00230 typedef struct
00231 {
00232   uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
00233                                         This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
00234                                         Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
00235
00236   uint32_t Rank;                   /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank.
00237                                         This parameter is dependent on ScanConvMode:
00238                                         - sequencer configured to fully configurable:
00239                                           Channels ordering into each rank of scan sequence:
00240                                           whatever channel can be placed into whatever rank.
00241                                         - sequencer configured to not fully configurable:
00242                                           rank of each channel is fixed by channel HW number.
00243                                           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
00244                                           Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
00245                                         This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */
00246
00247   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00248                                         Unit: ADC clock cycles
00249                                         Conversion time is the addition of sampling time and processing time
00250                                         (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00251                                         This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON
00252                                         Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings.
00253
00254                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00255                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00256                                               Refer to device datasheet for timings values. */
00257
00258 } ADC_ChannelConfTypeDef;
00259
00260 /**
00261   * @brief  Structure definition of ADC analog watchdog
00262   * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
00263   *         ADC state can be either:
00264   *          - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular.
00265   *          - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular.
00266   */
00267 typedef struct
00268 {
00269   uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
00270                                    For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
00271                                    For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
00272                                    This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
00273
00274   uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
00275                                    For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular.
00276                                    For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure.
00277                                    This parameter can be a value of @ref ADC_analog_watchdog_mode. */
00278
00279   uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
00280                                    For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
00281                                    For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
00282                                    This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
00283
00284   FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
00285                                    This parameter can be set to ENABLE or DISABLE */
00286
00287   uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
00288                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
00289                                    between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
00290                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00291                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
00292                                    Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
00293                                          impacted: the comparison of analog watchdog thresholds is done on
00294                                          oversampling final computation (after ratio and shift application):
00295                                          ADC data register bitfield [15:4] (12 most significant bits). */
00296
00297   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
00298                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
00299                                    between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
00300                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00301                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
00302                                    Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
00303                                          impacted: the comparison of analog watchdog thresholds is done on
00304                                          oversampling final computation (after ratio and shift application):
00305                                          ADC data register bitfield [15:4] (12 most significant bits). */
00306 } ADC_AnalogWDGConfTypeDef;
00307
00308 /** @defgroup ADC_States ADC States
00309   * @{
00310   */
00311
00312 /**
00313   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00314   * @note   ADC state machine is managed by bitfields, state must be compared
00315   *         with bit by bit.
00316   *         For example:
00317   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
00318   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
00319   */
00320 /* States of ADC global scope */
00321 #define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
00322 #define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
00323 #define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization, calibration) */
00324 #define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
00325
00326 /* States of ADC errors */
00327 #define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
00328 #define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
00329 #define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
00330
00331 /* States of ADC group regular */
00332 #define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
00333                                                               external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00334 #define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
00335 #define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
00336 #define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag raised  */
00337
00338 /* States of ADC group injected */
00339 #define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)  /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
00340                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))*/
00341 #define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)  /*!< Not available on this STM32 series: Conversion data available on group injected */
00342 #define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)  /*!< Not available on this STM32 series: Injected queue overflow occurrence */
00343
00344 /* States of ADC analog watchdogs */
00345 #define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
00346 #define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */
00347 #define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */
00348
00349 /* States of ADC multi-mode */
00350 #define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */
00351
00352
00353 /**
00354   * @}
00355   */
00356
00357 /**
00358   * @brief  ADC handle Structure definition
00359   */
00360 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00361 typedef struct __ADC_HandleTypeDef
00362 #else
00363 typedef struct
00364 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00365 {
00366   ADC_TypeDef                   *Instance;              /*!< Register base address */
00367   ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
00368   DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
00369   HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
00370   __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
00371   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
00372
00373   uint32_t                      ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */
00374 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00375   void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
00376   void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
00377   void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
00378   void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
00379   void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
00380   void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
00381   void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
00382   void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
00383   void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
00384 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00385 } ADC_HandleTypeDef;
00386
00387 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00388 /**
00389   * @brief  HAL ADC Callback ID enumeration definition
00390   */
00391 typedef enum
00392 {
00393   HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
00394   HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
00395   HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
00396   HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
00397   HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
00398   HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
00399   HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
00400   HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
00401   HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
00402 } HAL_ADC_CallbackIDTypeDef;
00403
00404 /**
00405   * @brief  HAL ADC Callback pointer definition
00406   */
00407 typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
00408
00409 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00410
00411 /**
00412   * @}
00413   */
00414
00415
00416 /* Exported constants --------------------------------------------------------*/
00417
00418 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00419   * @{
00420   */
00421
00422 /** @defgroup ADC_Error_Code ADC Error Code
00423   * @{
00424   */
00425 #define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
00426 #define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
00427                                                        enable/disable, erroneous state, ...)       */
00428 #define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
00429 #define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
00430 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00431 #define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
00432 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00438   * @{
00439   */
00440 #define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */
00441 #define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
00442 #define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
00443
00444 #define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without prescaler */
00445 #define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler division by 2   */
00446 #define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler division by 4   */
00447 #define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler division by 6   */
00448 #define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler division by 8   */
00449 #define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler division by 10  */
00450 #define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler division by 12  */
00451 #define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler division by 16  */
00452 #define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler division by 32  */
00453 #define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler division by 64  */
00454 #define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler division by 128 */
00455 #define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler division by 256 */
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
00461   * @{
00462   */
00463 #define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
00464 #define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
00465 #define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
00466 #define ADC_RESOLUTION_6B                  (LL_ADC_RESOLUTION_6B)   /*!< ADC resolution  6 bits */
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
00472   * @{
00473   */
00474 #define ADC_DATAALIGN_RIGHT                (LL_ADC_DATA_ALIGN_RIGHT)      /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
00475 #define ADC_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)       /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
00481   * @{
00482   */
00483 /* Note: On this STM32 family, ADC group regular sequencer both modes         */
00484 /*       "fully configurable" or "not fully configurable" are                 */
00485 /*       available.                                                           */
00486 /*       Scan mode values must be compatible with other STM32 devices having  */
00487 /*       a configurable sequencer.                                            */
00488 /*       Scan direction setting values are defined by taking in account       */
00489 /*       already defined values for other STM32 devices:                      */
00490 /*         ADC_SCAN_DISABLE         (0x00000000UL)                            */
00491 /*         ADC_SCAN_ENABLE          (0x00000001UL)                            */
00492 /*       Sequencer fully configurable with only rank 1 enabled is considered  */
00493 /*       as default setting equivalent to scan enable.                        */
00494 /*       In case of migration from another STM32 device, the user will be     */
00495 /*       warned of change of setting choices with assert check.               */
00496 #define ADC_SCAN_DISABLE                  (0x00000000UL)                               /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */
00497 #define ADC_SCAN_ENABLE                   (ADC_CFGR1_CHSELRMOD)                        /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */
00498
00499 #define ADC_SCAN_SEQ_FIXED                (ADC_SCAN_SEQ_FIXED_INT)                     /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
00500 #define ADC_SCAN_SEQ_FIXED_BACKWARD       (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
00501
00502 #define ADC_SCAN_DIRECTION_FORWARD        (ADC_SCAN_SEQ_FIXED)                   /* For compatibility with other STM32 devices */
00503 #define ADC_SCAN_DIRECTION_BACKWARD       (ADC_SCAN_SEQ_FIXED_BACKWARD)          /* For compatibility with other STM32 devices */
00504 /**
00505   * @}
00506   */
00507
00508 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
00509   * @{
00510   */
00511 /* ADC group regular trigger sources for all ADC instances */
00512 #define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                 /*!< ADC group regular conversion trigger internal: SW start. */
00513 #define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00514 #define ADC_EXTERNALTRIG_T1_CC4       (LL_ADC_REG_TRIG_EXT_TIM1_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00515 #if defined(TIM2)
00516 #define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00517 #endif /* TIM2 */
00518 #define ADC_EXTERNALTRIG_T3_TRGO      (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00519 #if defined(TIM4)
00520 #define ADC_EXTERNALTRIG_T4_TRGO      (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00521 #endif /* TIM4 */
00522 #if defined(TIM6)
00523 #define ADC_EXTERNALTRIG_T6_TRGO      (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00524 #endif /* TIM6 */
00525 #if defined(TIM15)
00526 #define ADC_EXTERNALTRIG_T15_TRGO     (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)           /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00527 #endif /* TIM15 */
00528 #define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)          /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00529 /**
00530   * @}
00531   */
00532
00533 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
00534   * @{
00535   */
00536 #define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< Regular conversions hardware trigger detection disabled */
00537 #define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion trigger polarity set to rising edge */
00538 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion trigger polarity set to falling edge */
00539 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
00545   * @{
00546   */
00547 #define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
00548 #define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
00549 /**
00550   * @}
00551   */
00552
00553 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00554   * @{
00555   */
00556 #define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case of overrun: data preserved */
00557 #define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case of overrun: data overwritten */
00558 /**
00559   * @}
00560   */
00561
00562 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00563   * @{
00564   */
00565 #define ADC_RANK_CHANNEL_NUMBER            (0x00000001U)  /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
00566 #define ADC_RANK_NONE                      (0x00000002U)  /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
00567
00568 #define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
00569 #define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
00570 #define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
00571 #define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
00572 #define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
00573 #define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
00574 #define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
00575 #define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON  ADC instance - Sampling time common to a group of channels
00581   * @{
00582   */
00583 #define ADC_SAMPLINGTIME_COMMON_1          (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
00584 #define ADC_SAMPLINGTIME_COMMON_2          (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
00590   * @{
00591   */
00592 #define ADC_SAMPLETIME_1CYCLE_5            (LL_ADC_SAMPLINGTIME_1CYCLE_5)     /*!< Sampling time 1.5 ADC clock cycle */
00593 #define ADC_SAMPLETIME_3CYCLES_5           (LL_ADC_SAMPLINGTIME_3CYCLES_5)    /*!< Sampling time 3.5 ADC clock cycles */
00594 #define ADC_SAMPLETIME_7CYCLES_5           (LL_ADC_SAMPLINGTIME_7CYCLES_5)    /*!< Sampling time 7.5 ADC clock cycles */
00595 #define ADC_SAMPLETIME_12CYCLES_5          (LL_ADC_SAMPLINGTIME_12CYCLES_5)   /*!< Sampling time 12.5 ADC clock cycles */
00596 #define ADC_SAMPLETIME_19CYCLES_5          (LL_ADC_SAMPLINGTIME_19CYCLES_5)   /*!< Sampling time 19.5 ADC clock cycles */
00597 #define ADC_SAMPLETIME_39CYCLES_5          (LL_ADC_SAMPLINGTIME_39CYCLES_5)   /*!< Sampling time 39.5 ADC clock cycles */
00598 #define ADC_SAMPLETIME_79CYCLES_5          (LL_ADC_SAMPLINGTIME_79CYCLES_5)   /*!< Sampling time 79.5 ADC clock cycles */
00599 #define ADC_SAMPLETIME_160CYCLES_5         (LL_ADC_SAMPLINGTIME_160CYCLES_5)  /*!< Sampling time 160.5 ADC clock cycles */
00600 /**
00601   * @}
00602   */
00603
00604 /** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
00605   * @{
00606   */
00607 #define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00608 #define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00609 #define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00610 #define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00611 #define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00612 #define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00613 #define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00614 #define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00615 #define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00616 #define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00617 #define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00618 #define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00619 #define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00620 #define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00621 #define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00622 #define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00623 #define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00624 #define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00625 #define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00626 #define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)         /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
00627 #define ADC_CHANNEL_TEMPSENSOR             (LL_ADC_CHANNEL_TEMPSENSOR)      /*!< ADC internal channel connected to Temperature sensor. */
00628 #define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)            /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
00634   * @{
00635   */
00636 #define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
00637 #define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
00638 #define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
00639 /**
00640   * @}
00641   */
00642
00643 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
00644   * @{
00645   */
00646 #define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                                          /*!< No analog watchdog selected                                             */
00647 #define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN)                  /*!< Analog watchdog applied to a regular group single channel               */
00648 #define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR1_AWD1EN)                                      /*!< Analog watchdog applied to regular group all channels                   */
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup ADC_HAL_EC_OVS_RATIO  Oversampling - Ratio
00654   * @{
00655   */
00656 #define ADC_OVERSAMPLING_RATIO_2           (LL_ADC_OVS_RATIO_2)   /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00657 #define ADC_OVERSAMPLING_RATIO_4           (LL_ADC_OVS_RATIO_4)   /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00658 #define ADC_OVERSAMPLING_RATIO_8           (LL_ADC_OVS_RATIO_8)   /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00659 #define ADC_OVERSAMPLING_RATIO_16          (LL_ADC_OVS_RATIO_16)  /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00660 #define ADC_OVERSAMPLING_RATIO_32          (LL_ADC_OVS_RATIO_32)  /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00661 #define ADC_OVERSAMPLING_RATIO_64          (LL_ADC_OVS_RATIO_64)  /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00662 #define ADC_OVERSAMPLING_RATIO_128         (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00663 #define ADC_OVERSAMPLING_RATIO_256         (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00664 /**
00665   * @}
00666   */
00667
00668 /** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
00669   * @{
00670   */
00671 #define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
00672 #define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
00673 #define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
00674 #define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
00675 #define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
00676 #define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
00677 #define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
00678 #define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
00679 #define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
00685   * @{
00686   */
00687 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
00688 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
00689 /**
00690   * @}
00691   */
00692
00693 /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ  ADC group regular - Trigger frequency mode
00694   * @{
00695   */
00696 #define ADC_TRIGGER_FREQ_HIGH              (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
00697 #define ADC_TRIGGER_FREQ_LOW               (LL_ADC_TRIGGER_FREQ_LOW)  /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup ADC_Event_type ADC Event type
00703   * @{
00704   */
00705 #define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
00706 #define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
00707 #define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
00708 #define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
00709 #define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
00710 /**
00711   * @}
00712   */
00713 #define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
00714
00715 /** @defgroup ADC_interrupts_definition ADC interrupts definition
00716   * @{
00717   */
00718 #define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
00719 #define ADC_IT_CCRDY         ADC_IER_CCRDYIE    /*!< ADC channel configuration ready interrupt source */
00720 #define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
00721 #define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
00722 #define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
00723 #define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
00724 #define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
00725 #define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
00726 #define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
00727 /**
00728   * @}
00729   */
00730
00731 /** @defgroup ADC_flags_definition ADC flags definition
00732   * @{
00733   */
00734 #define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
00735 #define ADC_FLAG_CCRDY         ADC_ISR_CCRDY    /*!< ADC channel configuration ready flag */
00736 #define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
00737 #define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
00738 #define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
00739 #define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
00740 #define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag */
00741 #define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag */
00742 #define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag */
00743 /**
00744   * @}
00745   */
00746
00747 /**
00748   * @}
00749   */
00750
00751 /* Private macro -------------------------------------------------------------*/
00752
00753 /** @defgroup ADC_Private_Macros ADC Private Macros
00754   * @{
00755   */
00756 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00757 /* code of final user.                                                        */
00758
00759 /**
00760   * @brief Test if conversion trigger of regular group is software start
00761   *        or external trigger.
00762   * @param __HANDLE__ ADC handle
00763   * @retval SET (software start) or RESET (external trigger)
00764   */
00765 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
00766   (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL)
00767
00768 /**
00769   * @brief Return resolution bits in CFGR1 register RES[1:0] field.
00770   * @param __HANDLE__ ADC handle
00771   * @retval Value of bitfield RES in CFGR1 register.
00772   */
00773 #define ADC_GET_RESOLUTION(__HANDLE__)                                         \
00774   (LL_ADC_GetResolution((__HANDLE__)->Instance))
00775
00776 /**
00777   * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
00778   * @param __HANDLE__ ADC handle
00779   * @retval None
00780   */
00781 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
00782
00783 /**
00784   * @brief Simultaneously clear and set specific bits of the handle State.
00785   * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
00786   *        the first parameter is the ADC handle State, the second parameter is the
00787   *        bit field to clear, the third and last parameter is the bit field to set.
00788   * @retval None
00789   */
00790 #define ADC_STATE_CLR_SET MODIFY_REG
00791
00792 /**
00793   * @brief Enable ADC discontinuous conversion mode for regular group
00794   * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
00795   * @retval None
00796   */
00797 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_)                 \
00798   ((_REG_DISCONTINUOUS_MODE_) << 16U)
00799
00800 /**
00801   * @brief Enable the ADC auto off mode.
00802   * @param _AUTOOFF_ Auto off bit enable or disable.
00803   * @retval None
00804   */
00805 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_)                                           \
00806   ((_AUTOOFF_) << 15U)
00807
00808 /**
00809   * @brief Enable the ADC auto delay mode.
00810   * @param _AUTOWAIT_ Auto delay bit enable or disable.
00811   * @retval None
00812   */
00813 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_)                                         \
00814   ((_AUTOWAIT_) << 14U)
00815
00816 /**
00817   * @brief Enable ADC continuous conversion mode.
00818   * @param _CONTINUOUS_MODE_ Continuous mode.
00819   * @retval None
00820   */
00821 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_)                                \
00822   ((_CONTINUOUS_MODE_) << 13U)
00823
00824 /**
00825   * @brief Enable ADC overrun mode.
00826   * @param _OVERRUN_MODE_ Overrun mode.
00827   * @retval Overrun bit setting to be programmed into CFGR register
00828   */
00829 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant                   */
00830 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it    */
00831 /* as the default case to be compliant with other STM32 devices.              */
00832 #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_)                                      \
00833   ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED)                             \
00834     )? (ADC_CFGR1_OVRMOD) : (0x00000000UL)                                     \
00835   )
00836
00837 /**
00838   * @brief Set ADC scan mode with differentiation of sequencer setting
00839   *        fixed or configurable
00840   * @param _SCAN_MODE_ Scan conversion mode.
00841   * @retval None
00842   */
00843 /* Note: Scan mode set using this macro (instead of parameter direct set)     */
00844 /*       due to different modes on other STM32 devices:                       */
00845 /*       if scan mode is disabled, sequencer is set to fully configurable     */
00846 /*       with setting of only rank 1 enabled afterwards.                      */
00847 #define ADC_SCAN_SEQ_MODE(_SCAN_MODE_)                                         \
00848   ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL                           \
00849     )?                                                                         \
00850     ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT))                                \
00851     :                                                                          \
00852     (ADC_CFGR1_CHSELRMOD)                                                      \
00853   )
00854
00855 /**
00856   * @brief Enable the ADC DMA continuous request.
00857   * @param _DMACONTREQ_MODE_: DMA continuous request mode.
00858   * @retval None
00859   */
00860 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_)                                \
00861   ((_DMACONTREQ_MODE_) << 1U)
00862
00863 /**
00864   * @brief Shift the AWD threshold in function of the selected ADC resolution.
00865   *        Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
00866   *        If resolution 12 bits, no shift.
00867   *        If resolution 10 bits, shift of 2 ranks on the left.
00868   *        If resolution 8 bits, shift of 4 ranks on the left.
00869   *        If resolution 6 bits, shift of 6 ranks on the left.
00870   *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
00871   * @param __HANDLE__ ADC handle
00872   * @param _Threshold_ Value to be shifted
00873   * @retval None
00874   */
00875 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)            \
00876   ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
00877
00878 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
00879                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
00880                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
00881                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1  )   ||\
00882                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2  )   ||\
00883                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4  )   ||\
00884                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6  )   ||\
00885                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8  )   ||\
00886                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 )   ||\
00887                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 )   ||\
00888                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 )   ||\
00889                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 )   ||\
00890                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 )   ||\
00891                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 )  ||\
00892                                           ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
00893
00894 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
00895                                        ((RESOLUTION) == ADC_RESOLUTION_10B) || \
00896                                        ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
00897                                        ((RESOLUTION) == ADC_RESOLUTION_6B)    )
00898
00899 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
00900                                   ((ALIGN) == ADC_DATAALIGN_LEFT)    )
00901
00902 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE)            || \
00903                                      ((SCAN_MODE) == ADC_SCAN_ENABLE)             || \
00904                                      ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED)          || \
00905                                      ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD)   )
00906
00907 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
00908                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
00909                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
00910                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
00911
00912 #if defined(TIM15) && defined(TIM6) && defined(TIM2)
00913 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
00914                                  ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4)   || \
00915                                  ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO)  || \
00916                                  ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)  || \
00917                                  ((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO)  || \
00918                                  ((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) || \
00919                                  ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
00920                                  ((REGTRIG) == ADC_SOFTWARE_START)          )
00921 #elif defined(TIM15) &&  defined(TIM6)
00922 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
00923                                  ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4)   || \
00924                                  ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)  || \
00925                                  ((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO)  || \
00926                                  ((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) || \
00927                                  ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
00928                                  ((REGTRIG) == ADC_SOFTWARE_START)          )
00929 #elif defined(TIM2)
00930 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
00931                                  ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4)   || \
00932                                  ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO)  || \
00933                                  ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)  || \
00934                                  ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
00935                                  ((REGTRIG) == ADC_SOFTWARE_START)          )
00936 #else
00937 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
00938                                  ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4)   || \
00939                                  ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)  || \
00940                                  ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
00941                                  ((REGTRIG) == ADC_SOFTWARE_START)          )
00942 #endif /* TIM15 && TIM6 && TIM2 */
00943
00944 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
00945                                              ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
00946
00947 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED)  || \
00948                              ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )
00949
00950 #define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \
00951                                              ((RANK) == ADC_RANK_NONE)             )
00952
00953 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
00954                                    ((RANK) == ADC_REGULAR_RANK_2 ) || \
00955                                    ((RANK) == ADC_REGULAR_RANK_3 ) || \
00956                                    ((RANK) == ADC_REGULAR_RANK_4 ) || \
00957                                    ((RANK) == ADC_REGULAR_RANK_5 ) || \
00958                                    ((RANK) == ADC_REGULAR_RANK_6 ) || \
00959                                    ((RANK) == ADC_REGULAR_RANK_7 ) || \
00960                                    ((RANK) == ADC_REGULAR_RANK_8 )   )
00961
00962 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
00963                                  ((CHANNEL) == ADC_CHANNEL_1)           || \
00964                                  ((CHANNEL) == ADC_CHANNEL_2)           || \
00965                                  ((CHANNEL) == ADC_CHANNEL_3)           || \
00966                                  ((CHANNEL) == ADC_CHANNEL_4)           || \
00967                                  ((CHANNEL) == ADC_CHANNEL_5)           || \
00968                                  ((CHANNEL) == ADC_CHANNEL_6)           || \
00969                                  ((CHANNEL) == ADC_CHANNEL_7)           || \
00970                                  ((CHANNEL) == ADC_CHANNEL_8)           || \
00971                                  ((CHANNEL) == ADC_CHANNEL_9)           || \
00972                                  ((CHANNEL) == ADC_CHANNEL_10)          || \
00973                                  ((CHANNEL) == ADC_CHANNEL_11)          || \
00974                                  ((CHANNEL) == ADC_CHANNEL_12)          || \
00975                                  ((CHANNEL) == ADC_CHANNEL_13)          || \
00976                                  ((CHANNEL) == ADC_CHANNEL_14)          || \
00977                                  ((CHANNEL) == ADC_CHANNEL_15)          || \
00978                                  ((CHANNEL) == ADC_CHANNEL_16)          || \
00979                                  ((CHANNEL) == ADC_CHANNEL_17)          || \
00980                                  ((CHANNEL) == ADC_CHANNEL_18)          || \
00981                                  ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
00982                                  ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
00983                                  ((CHANNEL) == ADC_CHANNEL_VBAT)          )
00984
00985 #define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \
00986                                                            ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2)   )
00987
00988 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
00989                                   ((TIME) == ADC_SAMPLETIME_3CYCLES_5)   || \
00990                                   ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
00991                                   ((TIME) == ADC_SAMPLETIME_12CYCLES_5)  || \
00992                                   ((TIME) == ADC_SAMPLETIME_19CYCLES_5)  || \
00993                                   ((TIME) == ADC_SAMPLETIME_39CYCLES_5)  || \
00994                                   ((TIME) == ADC_SAMPLETIME_79CYCLES_5)  || \
00995                                   ((TIME) == ADC_SAMPLETIME_160CYCLES_5)   )
00996
00997 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
00998                                                  ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
00999                                                  ((WATCHDOG) == ADC_ANALOGWATCHDOG_3)   )
01000
01001 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
01002                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
01003                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)            )
01004
01005 #define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
01006                                            ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW)    )
01007
01008 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \
01009                                   ((EVENT) == ADC_AWD1_EVENT)  || \
01010                                   ((EVENT) == ADC_AWD2_EVENT)  || \
01011                                   ((EVENT) == ADC_AWD3_EVENT)  || \
01012                                   ((EVENT) == ADC_OVR_EVENT)     )
01013
01014 /**
01015   * @brief Verify that a given value is aligned with the ADC resolution range.
01016   * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
01017   * @param __ADC_VALUE__ value checked against the resolution.
01018   * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
01019   */
01020 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
01021   ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
01022
01023 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
01024   * @{
01025   */
01026 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))
01027 /**
01028   * @}
01029   */
01030
01031
01032 /* Private constants ---------------------------------------------------------*/
01033
01034 /** @defgroup ADC_Private_Constants ADC Private Constants
01035   * @{
01036   */
01037
01038 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
01039 #define ADC_FLAG_POSTCONV_ALL    (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
01040
01041 #define ADC_SCAN_SEQ_FIXED_INT  0x80000000U  /* Internal definition to differentiate sequencer setting fixed or configurable */
01042
01043 /**
01044   * @}
01045   */
01046
01047 /* Exported macro ------------------------------------------------------------*/
01048
01049 /** @defgroup ADC_Exported_Macros ADC Exported Macros
01050   * @{
01051   */
01052 /* Macro for internal HAL driver usage, and possibly can be used into code of */
01053 /* final user.                                                                */
01054
01055 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
01056   * @{
01057   */
01058
01059 /** @brief  Reset ADC handle state.
01060   * @param __HANDLE__ ADC handle
01061   * @retval None
01062   */
01063 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01064 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
01065   do{                                                                          \
01066     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
01067     (__HANDLE__)->MspInitCallback = NULL;                                      \
01068     (__HANDLE__)->MspDeInitCallback = NULL;                                    \
01069   } while(0)
01070 #else
01071 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
01072   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
01073 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01074
01075 /**
01076   * @brief Enable ADC interrupt.
01077   * @param __HANDLE__ ADC handle
01078   * @param __INTERRUPT__ ADC Interrupt
01079   *        This parameter can be one of the following values:
01080   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01081   *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
01082   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01083   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01084   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01085   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01086   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01087   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01088   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01089   * @retval None
01090   */
01091 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
01092   (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
01093
01094 /**
01095   * @brief Disable ADC interrupt.
01096   * @param __HANDLE__ ADC handle
01097   * @param __INTERRUPT__ ADC Interrupt
01098   *        This parameter can be one of the following values:
01099   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01100   *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
01101   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01102   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01103   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01104   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01105   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01106   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01107   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01108   * @retval None
01109   */
01110 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
01111   (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
01112
01113 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
01114   * @param __HANDLE__ ADC handle
01115   * @param __INTERRUPT__ ADC interrupt source to check
01116   *          This parameter can be one of the following values:
01117   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01118   *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
01119   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01120   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01121   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01122   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01123   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01124   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01125   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01126   * @retval State of interruption (SET or RESET)
01127   */
01128 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
01129   (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
01130
01131 /**
01132   * @brief Check whether the specified ADC flag is set or not.
01133   * @param __HANDLE__ ADC handle
01134   * @param __FLAG__ ADC flag
01135   *        This parameter can be one of the following values:
01136   *            @arg @ref ADC_FLAG_RDY    ADC Ready flag
01137   *            @arg @ref ADC_FLAG_CCRDY  ADC channel configuration ready flag
01138   *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
01139   *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
01140   *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
01141   *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
01142   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
01143   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
01144   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
01145   * @retval State of flag (TRUE or FALSE).
01146   */
01147 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
01148   ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
01149
01150 /**
01151   * @brief Clear the specified ADC flag.
01152   * @param __HANDLE__ ADC handle
01153   * @param __FLAG__ ADC flag
01154   *        This parameter can be one of the following values:
01155   *            @arg @ref ADC_FLAG_RDY    ADC Ready flag
01156   *            @arg @ref ADC_FLAG_CCRDY  ADC channel configuration ready flag
01157   *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
01158   *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
01159   *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
01160   *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
01161   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
01162   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
01163   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
01164   * @retval None
01165   */
01166 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
01167 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
01168   (((__HANDLE__)->Instance->ISR) = (__FLAG__))
01169
01170 /**
01171   * @}
01172   */
01173
01174 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
01175   * @{
01176   */
01177
01178 /**
01179   * @brief  Helper macro to get ADC channel number in decimal format
01180   *         from literals ADC_CHANNEL_x.
01181   * @note   Example:
01182   *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
01183   *           will return decimal number "4".
01184   * @note   The input can be a value from functions where a channel
01185   *         number is returned, either defined with number
01186   *         or with bitfield (only one bit must be set).
01187   * @param  __CHANNEL__ This parameter can be one of the following values:
01188   *         @arg @ref ADC_CHANNEL_0
01189   *         @arg @ref ADC_CHANNEL_1
01190   *         @arg @ref ADC_CHANNEL_2
01191   *         @arg @ref ADC_CHANNEL_3
01192   *         @arg @ref ADC_CHANNEL_4
01193   *         @arg @ref ADC_CHANNEL_5
01194   *         @arg @ref ADC_CHANNEL_6
01195   *         @arg @ref ADC_CHANNEL_7
01196   *         @arg @ref ADC_CHANNEL_8
01197   *         @arg @ref ADC_CHANNEL_9
01198   *         @arg @ref ADC_CHANNEL_10
01199   *         @arg @ref ADC_CHANNEL_11
01200   *         @arg @ref ADC_CHANNEL_12
01201   *         @arg @ref ADC_CHANNEL_13
01202   *         @arg @ref ADC_CHANNEL_14
01203   *         @arg @ref ADC_CHANNEL_15         (1)
01204   *         @arg @ref ADC_CHANNEL_16         (1)
01205   *         @arg @ref ADC_CHANNEL_17         (1)
01206   *         @arg @ref ADC_CHANNEL_18
01207   *         @arg @ref ADC_CHANNEL_VREFINT
01208   *         @arg @ref ADC_CHANNEL_TEMPSENSOR
01209   *         @arg @ref ADC_CHANNEL_VBAT
01210   *
01211   *         (1) On STM32G0, parameter can be set in ADC group sequencer
01212   *             only if sequencer is set in mode "not fully configurable",
01213   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
01214   * @retval Value between Min_Data=0 and Max_Data=18
01215   */
01216 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
01217   __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
01218
01219 /**
01220   * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
01221   *         from number in decimal format.
01222   * @note   Example:
01223   *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01224   *           will return a data equivalent to "ADC_CHANNEL_4".
01225   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
01226   * @retval Returned value can be one of the following values:
01227   *         @arg @ref ADC_CHANNEL_0
01228   *         @arg @ref ADC_CHANNEL_1
01229   *         @arg @ref ADC_CHANNEL_2
01230   *         @arg @ref ADC_CHANNEL_3
01231   *         @arg @ref ADC_CHANNEL_4
01232   *         @arg @ref ADC_CHANNEL_5
01233   *         @arg @ref ADC_CHANNEL_6
01234   *         @arg @ref ADC_CHANNEL_7
01235   *         @arg @ref ADC_CHANNEL_8
01236   *         @arg @ref ADC_CHANNEL_9
01237   *         @arg @ref ADC_CHANNEL_10
01238   *         @arg @ref ADC_CHANNEL_11
01239   *         @arg @ref ADC_CHANNEL_12
01240   *         @arg @ref ADC_CHANNEL_13
01241   *         @arg @ref ADC_CHANNEL_14
01242   *         @arg @ref ADC_CHANNEL_15         (1)
01243   *         @arg @ref ADC_CHANNEL_16         (1)
01244   *         @arg @ref ADC_CHANNEL_17         (1)
01245   *         @arg @ref ADC_CHANNEL_18
01246   *         @arg @ref ADC_CHANNEL_VREFINT    (2)
01247   *         @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
01248   *         @arg @ref ADC_CHANNEL_VBAT       (2)
01249   *
01250   *         (1) On STM32G0, parameter can be set in ADC group sequencer
01251   *             only if sequencer is set in mode "not fully configurable",
01252   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
01253   *         (2) For ADC channel read back from ADC register,
01254   *             comparison with internal channel parameter to be done
01255   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01256   */
01257 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
01258   __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
01259
01260 /**
01261   * @brief  Helper macro to determine whether the selected channel
01262   *         corresponds to literal definitions of driver.
01263   * @note   The different literal definitions of ADC channels are:
01264   *         - ADC internal channel:
01265   *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
01266   *         - ADC external channel (channel connected to a GPIO pin):
01267   *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
01268   * @note   The channel parameter must be a value defined from literal
01269   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01270   *         ADC_CHANNEL_TEMPSENSOR, ...),
01271   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
01272   *         must not be a value from functions where a channel number is
01273   *         returned from ADC registers,
01274   *         because internal and external channels share the same channel
01275   *         number in ADC registers. The differentiation is made only with
01276   *         parameters definitions of driver.
01277   * @param  __CHANNEL__ This parameter can be one of the following values:
01278   *         @arg @ref ADC_CHANNEL_0
01279   *         @arg @ref ADC_CHANNEL_1
01280   *         @arg @ref ADC_CHANNEL_2
01281   *         @arg @ref ADC_CHANNEL_3
01282   *         @arg @ref ADC_CHANNEL_4
01283   *         @arg @ref ADC_CHANNEL_5
01284   *         @arg @ref ADC_CHANNEL_6
01285   *         @arg @ref ADC_CHANNEL_7
01286   *         @arg @ref ADC_CHANNEL_8
01287   *         @arg @ref ADC_CHANNEL_9
01288   *         @arg @ref ADC_CHANNEL_10
01289   *         @arg @ref ADC_CHANNEL_11
01290   *         @arg @ref ADC_CHANNEL_12
01291   *         @arg @ref ADC_CHANNEL_13
01292   *         @arg @ref ADC_CHANNEL_14
01293   *         @arg @ref ADC_CHANNEL_15         (1)
01294   *         @arg @ref ADC_CHANNEL_16         (1)
01295   *         @arg @ref ADC_CHANNEL_17         (1)
01296   *         @arg @ref ADC_CHANNEL_18
01297   *         @arg @ref ADC_CHANNEL_VREFINT
01298   *         @arg @ref ADC_CHANNEL_TEMPSENSOR
01299   *         @arg @ref ADC_CHANNEL_VBAT
01300   *
01301   *         (1) On STM32G0, parameter can be set in ADC group sequencer
01302   *             only if sequencer is set in mode "not fully configurable",
01303   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
01304   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01305   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01306   */
01307 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
01308   __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
01309
01310 /**
01311   * @brief  Helper macro to convert a channel defined from parameter
01312   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01313   *         ADC_CHANNEL_TEMPSENSOR, ...),
01314   *         to its equivalent parameter definition of a ADC external channel
01315   *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
01316   * @note   The channel parameter can be, additionally to a value
01317   *         defined from parameter definition of a ADC internal channel
01318   *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
01319   *         a value defined from parameter definition of
01320   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
01321   *         or a value from functions where a channel number is returned
01322   *         from ADC registers.
01323   * @param  __CHANNEL__ This parameter can be one of the following values:
01324   *         @arg @ref ADC_CHANNEL_0
01325   *         @arg @ref ADC_CHANNEL_1
01326   *         @arg @ref ADC_CHANNEL_2
01327   *         @arg @ref ADC_CHANNEL_3
01328   *         @arg @ref ADC_CHANNEL_4
01329   *         @arg @ref ADC_CHANNEL_5
01330   *         @arg @ref ADC_CHANNEL_6
01331   *         @arg @ref ADC_CHANNEL_7
01332   *         @arg @ref ADC_CHANNEL_8
01333   *         @arg @ref ADC_CHANNEL_9
01334   *         @arg @ref ADC_CHANNEL_10
01335   *         @arg @ref ADC_CHANNEL_11
01336   *         @arg @ref ADC_CHANNEL_12
01337   *         @arg @ref ADC_CHANNEL_13
01338   *         @arg @ref ADC_CHANNEL_14
01339   *         @arg @ref ADC_CHANNEL_15         (1)
01340   *         @arg @ref ADC_CHANNEL_16         (1)
01341   *         @arg @ref ADC_CHANNEL_17         (1)
01342   *         @arg @ref ADC_CHANNEL_18
01343   *         @arg @ref ADC_CHANNEL_VREFINT
01344   *         @arg @ref ADC_CHANNEL_TEMPSENSOR
01345   *         @arg @ref ADC_CHANNEL_VBAT
01346   *
01347   *         (1) On STM32G0, parameter can be set in ADC group sequencer
01348   *             only if sequencer is set in mode "not fully configurable",
01349   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
01350   * @retval Returned value can be one of the following values:
01351   *         @arg @ref ADC_CHANNEL_0
01352   *         @arg @ref ADC_CHANNEL_1
01353   *         @arg @ref ADC_CHANNEL_2
01354   *         @arg @ref ADC_CHANNEL_3
01355   *         @arg @ref ADC_CHANNEL_4
01356   *         @arg @ref ADC_CHANNEL_5
01357   *         @arg @ref ADC_CHANNEL_6
01358   *         @arg @ref ADC_CHANNEL_7
01359   *         @arg @ref ADC_CHANNEL_8
01360   *         @arg @ref ADC_CHANNEL_9
01361   *         @arg @ref ADC_CHANNEL_10
01362   *         @arg @ref ADC_CHANNEL_11
01363   *         @arg @ref ADC_CHANNEL_12
01364   *         @arg @ref ADC_CHANNEL_13
01365   *         @arg @ref ADC_CHANNEL_14
01366   *         @arg @ref ADC_CHANNEL_15
01367   *         @arg @ref ADC_CHANNEL_16
01368   *         @arg @ref ADC_CHANNEL_17
01369   *         @arg @ref ADC_CHANNEL_18
01370   */
01371 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
01372   __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
01373
01374 /**
01375   * @brief  Helper macro to determine whether the internal channel
01376   *         selected is available on the ADC instance selected.
01377   * @note   The channel parameter must be a value defined from parameter
01378   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01379   *         ADC_CHANNEL_TEMPSENSOR, ...),
01380   *         must not be a value defined from parameter definition of
01381   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
01382   *         or a value from functions where a channel number is
01383   *         returned from ADC registers,
01384   *         because internal and external channels share the same channel
01385   *         number in ADC registers. The differentiation is made only with
01386   *         parameters definitions of driver.
01387   * @param  __ADC_INSTANCE__ ADC instance
01388   * @param  __CHANNEL__ This parameter can be one of the following values:
01389   *         @arg @ref ADC_CHANNEL_VREFINT
01390   *         @arg @ref ADC_CHANNEL_TEMPSENSOR
01391   *         @arg @ref ADC_CHANNEL_VBAT
01392   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01393   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01394   */
01395 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01396   __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
01397
01398 /**
01399   * @brief  Helper macro to select the ADC common instance
01400   *         to which is belonging the selected ADC instance.
01401   * @note   ADC common register instance can be used for:
01402   *         - Set parameters common to several ADC instances
01403   *         - Multimode (for devices with several ADC instances)
01404   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01405   * @param  __ADCx__ ADC instance
01406   * @retval ADC common register instance
01407   */
01408 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
01409   __LL_ADC_COMMON_INSTANCE((__ADCx__))
01410
01411 /**
01412   * @brief  Helper macro to check if all ADC instances sharing the same
01413   *         ADC common instance are disabled.
01414   * @note   This check is required by functions with setting conditioned to
01415   *         ADC state:
01416   *         All ADC instances of the ADC common group must be disabled.
01417   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01418   * @note   On devices with only 1 ADC common instance, parameter of this macro
01419   *         is useless and can be ignored (parameter kept for compatibility
01420   *         with devices featuring several ADC common instances).
01421   * @param  __ADCXY_COMMON__ ADC common instance
01422   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01423   * @retval Value "0" if all ADC instances sharing the same ADC common instance
01424   *         are disabled.
01425   *         Value "1" if at least one ADC instance sharing the same ADC common instance
01426   *         is enabled.
01427   */
01428 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01429   __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
01430
01431 /**
01432   * @brief  Helper macro to define the ADC conversion data full-scale digital
01433   *         value corresponding to the selected ADC resolution.
01434   * @note   ADC conversion data full-scale corresponds to voltage range
01435   *         determined by analog voltage references Vref+ and Vref-
01436   *         (refer to reference manual).
01437   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01438   *         @arg @ref ADC_RESOLUTION_12B
01439   *         @arg @ref ADC_RESOLUTION_10B
01440   *         @arg @ref ADC_RESOLUTION_8B
01441   *         @arg @ref ADC_RESOLUTION_6B
01442   * @retval ADC conversion data full-scale digital value
01443   */
01444 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
01445   __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
01446
01447 /**
01448   * @brief  Helper macro to convert the ADC conversion data from
01449   *         a resolution to another resolution.
01450   * @param  __DATA__ ADC conversion data to be converted
01451   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
01452   *         This parameter can be one of the following values:
01453   *         @arg @ref ADC_RESOLUTION_12B
01454   *         @arg @ref ADC_RESOLUTION_10B
01455   *         @arg @ref ADC_RESOLUTION_8B
01456   *         @arg @ref ADC_RESOLUTION_6B
01457   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
01458   *         This parameter can be one of the following values:
01459   *         @arg @ref ADC_RESOLUTION_12B
01460   *         @arg @ref ADC_RESOLUTION_10B
01461   *         @arg @ref ADC_RESOLUTION_8B
01462   *         @arg @ref ADC_RESOLUTION_6B
01463   * @retval ADC conversion data to the requested resolution
01464   */
01465 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
01466                                           __ADC_RESOLUTION_CURRENT__,\
01467                                           __ADC_RESOLUTION_TARGET__) \
01468 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
01469                                  (__ADC_RESOLUTION_CURRENT__),\
01470                                  (__ADC_RESOLUTION_TARGET__))
01471
01472 /**
01473   * @brief  Helper macro to calculate the voltage (unit: mVolt)
01474   *         corresponding to a ADC conversion data (unit: digital value).
01475   * @note   Analog reference voltage (Vref+) must be either known from
01476   *         user board environment or can be calculated using ADC measurement
01477   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01478   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
01479   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
01480   *                       (unit: digital value).
01481   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01482   *         @arg @ref ADC_RESOLUTION_12B
01483   *         @arg @ref ADC_RESOLUTION_10B
01484   *         @arg @ref ADC_RESOLUTION_8B
01485   *         @arg @ref ADC_RESOLUTION_6B
01486   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01487   */
01488 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
01489                                        __ADC_DATA__,\
01490                                        __ADC_RESOLUTION__) \
01491 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
01492                               (__ADC_DATA__),\
01493                               (__ADC_RESOLUTION__))
01494
01495 /**
01496   * @brief  Helper macro to calculate analog reference voltage (Vref+)
01497   *         (unit: mVolt) from ADC conversion data of internal voltage
01498   *         reference VrefInt.
01499   * @note   Computation is using VrefInt calibration value
01500   *         stored in system memory for each device during production.
01501   * @note   This voltage depends on user board environment: voltage level
01502   *         connected to pin Vref+.
01503   *         On devices with small package, the pin Vref+ is not present
01504   *         and internally bonded to pin Vdda.
01505   * @note   On this STM32 series, calibration data of internal voltage reference
01506   *         VrefInt corresponds to a resolution of 12 bits,
01507   *         this is the recommended ADC resolution to convert voltage of
01508   *         internal voltage reference VrefInt.
01509   *         Otherwise, this macro performs the processing to scale
01510   *         ADC conversion data to 12 bits.
01511   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
01512   *         of internal voltage reference VrefInt (unit: digital value).
01513   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01514   *         @arg @ref ADC_RESOLUTION_12B
01515   *         @arg @ref ADC_RESOLUTION_10B
01516   *         @arg @ref ADC_RESOLUTION_8B
01517   *         @arg @ref ADC_RESOLUTION_6B
01518   * @retval Analog reference voltage (unit: mV)
01519   */
01520 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
01521                                           __ADC_RESOLUTION__) \
01522 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
01523                                  (__ADC_RESOLUTION__))
01524
01525 /**
01526   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01527   *         from ADC conversion data of internal temperature sensor.
01528   * @note   Computation is using temperature sensor calibration values
01529   *         stored in system memory for each device during production.
01530   * @note   Calculation formula:
01531   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
01532   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
01533   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
01534   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
01535   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
01536   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
01537   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
01538   *                            TEMP_DEGC_CAL1 (calibrated in factory)
01539   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
01540   *                            TEMP_DEGC_CAL2 (calibrated in factory)
01541   *         Caution: Calculation relevancy under reserve that calibration
01542   *                  parameters are correct (address and data).
01543   *                  To calculate temperature using temperature sensor
01544   *                  datasheet typical values (generic values less, therefore
01545   *                  less accurate than calibrated values),
01546   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
01547   * @note   As calculation input, the analog reference voltage (Vref+) must be
01548   *         defined as it impacts the ADC LSB equivalent voltage.
01549   * @note   Analog reference voltage (Vref+) must be either known from
01550   *         user board environment or can be calculated using ADC measurement
01551   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01552   * @note   On this STM32 series, calibration data of temperature sensor
01553   *         corresponds to a resolution of 12 bits,
01554   *         this is the recommended ADC resolution to convert voltage of
01555   *         temperature sensor.
01556   *         Otherwise, this macro performs the processing to scale
01557   *         ADC conversion data to 12 bits.
01558   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
01559   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
01560   *                                 temperature sensor (unit: digital value).
01561   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
01562   *                                 sensor voltage has been measured.
01563   *         This parameter can be one of the following values:
01564   *         @arg @ref ADC_RESOLUTION_12B
01565   *         @arg @ref ADC_RESOLUTION_10B
01566   *         @arg @ref ADC_RESOLUTION_8B
01567   *         @arg @ref ADC_RESOLUTION_6B
01568   * @retval Temperature (unit: degree Celsius)
01569   */
01570 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
01571                                    __TEMPSENSOR_ADC_DATA__,\
01572                                    __ADC_RESOLUTION__) \
01573 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
01574                           (__TEMPSENSOR_ADC_DATA__),\
01575                           (__ADC_RESOLUTION__))
01576
01577 /**
01578   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01579   *         from ADC conversion data of internal temperature sensor.
01580   * @note   Computation is using temperature sensor typical values
01581   *         (refer to device datasheet).
01582   * @note   Calculation formula:
01583   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
01584   *                         / Avg_Slope + CALx_TEMP
01585   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
01586   *                                   (unit: digital value)
01587   *                Avg_Slope        = temperature sensor slope
01588   *                                   (unit: uV/Degree Celsius)
01589   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
01590   *                                   temperature CALx_TEMP (unit: mV)
01591   *         Caution: Calculation relevancy under reserve the temperature sensor
01592   *                  of the current device has characteristics in line with
01593   *                  datasheet typical values.
01594   *                  If temperature sensor calibration values are available on
01595   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
01596   *                  temperature calculation will be more accurate using
01597   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
01598   * @note   As calculation input, the analog reference voltage (Vref+) must be
01599   *         defined as it impacts the ADC LSB equivalent voltage.
01600   * @note   Analog reference voltage (Vref+) must be either known from
01601   *         user board environment or can be calculated using ADC measurement
01602   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01603   * @note   ADC measurement data must correspond to a resolution of 12bits
01604   *         (full scale digital value 4095). If not the case, the data must be
01605   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01606   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
01607   *                                       On STM32G0, refer to device datasheet parameter "Avg_Slope".
01608   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
01609   *                                       On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
01610   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
01611   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
01612   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
01613   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
01614   *         This parameter can be one of the following values:
01615   *         @arg @ref ADC_RESOLUTION_12B
01616   *         @arg @ref ADC_RESOLUTION_10B
01617   *         @arg @ref ADC_RESOLUTION_8B
01618   *         @arg @ref ADC_RESOLUTION_6B
01619   * @retval Temperature (unit: degree Celsius)
01620   */
01621 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
01622                                               __TEMPSENSOR_TYP_CALX_V__,\
01623                                               __TEMPSENSOR_CALX_TEMP__,\
01624                                               __VREFANALOG_VOLTAGE__,\
01625                                               __TEMPSENSOR_ADC_DATA__,\
01626                                               __ADC_RESOLUTION__) \
01627 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
01628                                      (__TEMPSENSOR_TYP_CALX_V__),\
01629                                      (__TEMPSENSOR_CALX_TEMP__),\
01630                                      (__VREFANALOG_VOLTAGE__),\
01631                                      (__TEMPSENSOR_ADC_DATA__),\
01632                                      (__ADC_RESOLUTION__))
01633
01634 /**
01635   * @}
01636   */
01637
01638 /**
01639   * @}
01640   */
01641
01642 /* Include ADC HAL Extended module */
01643 #include "stm32g0xx_hal_adc_ex.h"
01644
01645 /* Exported functions --------------------------------------------------------*/
01646 /** @addtogroup ADC_Exported_Functions
01647   * @{
01648   */
01649
01650 /** @addtogroup ADC_Exported_Functions_Group1
01651   * @brief    Initialization and Configuration functions
01652   * @{
01653   */
01654 /* Initialization and de-initialization functions  ****************************/
01655 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
01656 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
01657 void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
01658 void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
01659
01660 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01661 /* Callbacks Register/UnRegister functions  ***********************************/
01662 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
01663                                            pADC_CallbackTypeDef pCallback);
01664 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
01665 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01666 /**
01667   * @}
01668   */
01669
01670 /** @addtogroup ADC_Exported_Functions_Group2
01671   * @brief    IO operation functions
01672   * @{
01673   */
01674 /* IO operation functions  *****************************************************/
01675
01676 /* Blocking mode: Polling */
01677 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
01678 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
01679 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
01680 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
01681
01682 /* Non-blocking mode: Interruption */
01683 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
01684 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
01685
01686 /* Non-blocking mode: DMA */
01687 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
01688 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
01689
01690 /* ADC retrieve conversion value intended to be used with polling or interruption */
01691 uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
01692
01693 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
01694 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
01695 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
01696 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
01697 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
01698 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
01699 /**
01700   * @}
01701   */
01702
01703 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
01704   *  @brief    Peripheral Control functions
01705   * @{
01706   */
01707 /* Peripheral Control functions ***********************************************/
01708 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig);
01709 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
01710
01711 /**
01712   * @}
01713   */
01714
01715 /* Peripheral State functions *************************************************/
01716 /** @addtogroup ADC_Exported_Functions_Group4
01717   * @{
01718   */
01719 uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
01720 uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
01721
01722 /**
01723   * @}
01724   */
01725
01726 /**
01727   * @}
01728   */
01729
01730 /* Private functions ---------------------------------------------------------*/
01731 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc);
01732 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
01733 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
01734
01735 /**
01736   * @}
01737   */
01738
01739 /**
01740   * @}
01741   */
01742
01743 /**
01744   * @}
01745   */
01746
01747 #ifdef __cplusplus
01748 }
01749 #endif
01750
01751
01752 #endif /* STM32G0xx_HAL_ADC_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_adc_ex.c Source File

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stm32g0xx_hal_adc_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Converter (ADC)
00007   *          peripheral:
00008   *           + Peripheral Control functions
00009   *          Other functions (generic functions) are available in file
00010   *          "stm32g0xx_hal_adc.c".
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   [..]
00025   (@) Sections "ADC peripheral features" and "How to use this driver" are
00026       available in file of generic functions "stm32g0xx_hal_adc.c".
00027   [..]
00028   @endverbatim
00029   */
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32g0xx_hal.h"
00033
00034 /** @addtogroup STM32G0xx_HAL_Driver
00035   * @{
00036   */
00037
00038 /** @defgroup ADCEx ADCEx
00039   * @brief ADC Extended HAL module driver
00040   * @{
00041   */
00042
00043 #ifdef HAL_ADC_MODULE_ENABLED
00044
00045 /* Private typedef -----------------------------------------------------------*/
00046 /* Private define ------------------------------------------------------------*/
00047
00048 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
00049   * @{
00050   */
00051
00052 /* Fixed timeout value for ADC calibration.                                   */
00053 /* Values defined to be higher than worst cases: maximum ratio between ADC    */
00054 /* and CPU clock frequencies.                                                 */
00055 /* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock    */
00056 /* source PLL 8MHz, ADC clock prescaler 256), CPU frequency 52MHz.            */
00057 /* Calibration time max = 116 / fADC (refer to datasheet)                     */
00058 /*                      = 193 024 CPU cycles                                  */
00059 #define ADC_CALIBRATION_TIMEOUT         (193024UL)   /*!< ADC calibration time-out value (unit: CPU cycles) */
00060 #define ADC_DISABLE_TIMEOUT             (2UL)
00061
00062 /**
00063   * @}
00064   */
00065
00066 /* Private macro -------------------------------------------------------------*/
00067 /* Private variables ---------------------------------------------------------*/
00068 /* Private function prototypes -----------------------------------------------*/
00069 /* Exported functions --------------------------------------------------------*/
00070
00071 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
00072   * @{
00073   */
00074
00075 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
00076   * @brief    Extended IO operation functions
00077   *
00078 @verbatim
00079  ===============================================================================
00080                       ##### IO operation functions #####
00081  ===============================================================================
00082     [..]  This section provides functions allowing to:
00083
00084       (+) Perform the ADC self-calibration.
00085       (+) Get calibration factors.
00086       (+) Set calibration factors.
00087
00088 @endverbatim
00089   * @{
00090   */
00091
00092 /**
00093   * @brief  Perform an ADC automatic self-calibration
00094   *         Calibration prerequisite: ADC must be disabled (execute this
00095   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
00096   * @note   Calibration factor can be read after calibration, using function
00097   *         HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
00098   * @param  hadc       ADC handle
00099   * @retval HAL status
00100   */
00101 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
00102 {
00103   HAL_StatusTypeDef tmp_hal_status;
00104   __IO uint32_t wait_loop_index = 0UL;
00105   uint32_t backup_setting_cfgr1;
00106   uint32_t calibration_index;
00107   uint32_t calibration_factor_accumulated = 0;
00108   uint32_t tickstart;
00109
00110   /* Check the parameters */
00111   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00112
00113   __HAL_LOCK(hadc);
00114
00115   /* Calibration prerequisite: ADC must be disabled. */
00116
00117   /* Disable the ADC (if not already disabled) */
00118   tmp_hal_status = ADC_Disable(hadc);
00119
00120   /* Check if ADC is effectively disabled */
00121   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
00122   {
00123     /* Set ADC state */
00124     ADC_STATE_CLR_SET(hadc->State,
00125                       HAL_ADC_STATE_REG_BUSY,
00126                       HAL_ADC_STATE_BUSY_INTERNAL);
00127
00128     /* Manage settings impacting calibration                                  */
00129     /* - Disable ADC mode auto power-off                                      */
00130     /* - Disable ADC DMA transfer request during calibration                  */
00131     /* Note: Specificity of this STM32 series: Calibration factor is          */
00132     /*       available in data register and also transferred by DMA.          */
00133     /*       To not insert ADC calibration factor among ADC conversion data   */
00134     /*       in array variable, DMA transfer must be disabled during          */
00135     /*       calibration.                                                     */
00136     backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
00137     CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
00138
00139     /* ADC calibration procedure */
00140     /* Note: Perform an averaging of 8 calibrations for optimized accuracy */
00141     for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
00142     {
00143       /* Start ADC calibration */
00144       LL_ADC_StartCalibration(hadc->Instance);
00145
00146       /* Wait for calibration completion */
00147       while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
00148       {
00149         wait_loop_index++;
00150         if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
00151         {
00152           /* Update ADC state machine to error */
00153           ADC_STATE_CLR_SET(hadc->State,
00154                             HAL_ADC_STATE_BUSY_INTERNAL,
00155                             HAL_ADC_STATE_ERROR_INTERNAL);
00156
00157           __HAL_UNLOCK(hadc);
00158
00159           return HAL_ERROR;
00160         }
00161       }
00162
00163       calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance);
00164     }
00165     /* Compute average */
00166     calibration_factor_accumulated /= calibration_index;
00167     /* Apply calibration factor */
00168     LL_ADC_Enable(hadc->Instance);
00169     LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated);
00170     LL_ADC_Disable(hadc->Instance);
00171
00172     /* Wait for ADC effectively disabled before changing configuration */
00173     /* Get tick count */
00174     tickstart = HAL_GetTick();
00175
00176     while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
00177     {
00178       if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
00179       {
00180         /* New check to avoid false timeout detection in case of preemption */
00181         if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
00182         {
00183           /* Update ADC state machine to error */
00184           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00185
00186           /* Set ADC error code to ADC peripheral internal error */
00187           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00188
00189           return HAL_ERROR;
00190         }
00191       }
00192     }
00193
00194     /* Restore configuration after calibration */
00195     SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1);
00196
00197     /* Set ADC state */
00198     ADC_STATE_CLR_SET(hadc->State,
00199                       HAL_ADC_STATE_BUSY_INTERNAL,
00200                       HAL_ADC_STATE_READY);
00201   }
00202   else
00203   {
00204     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00205
00206     /* Note: No need to update variable "tmp_hal_status" here: already set    */
00207     /*       to state "HAL_ERROR" by function disabling the ADC.              */
00208   }
00209
00210   __HAL_UNLOCK(hadc);
00211
00212   return tmp_hal_status;
00213 }
00214
00215 /**
00216   * @brief  Get the calibration factor.
00217   * @param hadc ADC handle.
00218   * @retval Calibration value.
00219   */
00220 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc)
00221 {
00222   /* Check the parameters */
00223   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00224
00225   /* Return the selected ADC calibration value */
00226   return ((hadc->Instance->CALFACT) & 0x0000007FU);
00227 }
00228
00229 /**
00230   * @brief  Set the calibration factor to overwrite automatic conversion result.
00231   *         ADC must be enabled and no conversion is ongoing.
00232   * @param hadc ADC handle
00233   * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
00234   * @retval HAL state
00235   */
00236 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor)
00237 {
00238   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00239   uint32_t tmp_adc_is_conversion_on_going_regular;
00240
00241   /* Check the parameters */
00242   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00243   assert_param(IS_ADC_CALFACT(CalibrationFactor));
00244
00245   __HAL_LOCK(hadc);
00246
00247   /* Verification of hardware constraints before modifying the calibration    */
00248   /* factors register: ADC must be enabled, no conversion on going.           */
00249   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00250
00251   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
00252       && (tmp_adc_is_conversion_on_going_regular == 0UL)
00253      )
00254   {
00255     hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT;
00256     hadc->Instance->CALFACT |= CalibrationFactor;
00257   }
00258   else
00259   {
00260     /* Update ADC state machine */
00261     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00262     /* Update ADC error code */
00263     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00264
00265     /* Update ADC state machine to error */
00266     tmp_hal_status = HAL_ERROR;
00267   }
00268
00269   __HAL_UNLOCK(hadc);
00270
00271   return tmp_hal_status;
00272 }
00273
00274 /**
00275   * @brief  Analog watchdog 2 callback in non-blocking mode.
00276   * @param hadc ADC handle
00277   * @retval None
00278   */
00279 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
00280 {
00281   /* Prevent unused argument(s) compilation warning */
00282   UNUSED(hadc);
00283
00284   /* NOTE : This function should not be modified. When the callback is needed,
00285             function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
00286   */
00287 }
00288
00289 /**
00290   * @brief  Analog watchdog 3 callback in non-blocking mode.
00291   * @param hadc ADC handle
00292   * @retval None
00293   */
00294 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
00295 {
00296   /* Prevent unused argument(s) compilation warning */
00297   UNUSED(hadc);
00298
00299   /* NOTE : This function should not be modified. When the callback is needed,
00300             function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
00301   */
00302 }
00303
00304
00305 /**
00306   * @brief  End Of Sampling callback in non-blocking mode.
00307   * @param hadc ADC handle
00308   * @retval None
00309   */
00310 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
00311 {
00312   /* Prevent unused argument(s) compilation warning */
00313   UNUSED(hadc);
00314
00315   /* NOTE : This function should not be modified. When the callback is needed,
00316             function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
00317   */
00318 }
00319
00320 /**
00321   * @brief  ADC channel configuration ready callback in non-blocking mode.
00322   * @param hadc ADC handle
00323   * @retval None
00324   */
00325 __weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc)
00326 {
00327   /* Prevent unused argument(s) compilation warning */
00328   UNUSED(hadc);
00329
00330   /* NOTE : This function should not be modified. When the callback is needed,
00331             function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file.
00332   */
00333 }
00334
00335 /**
00336   * @}
00337   */
00338
00339 /**
00340   * @brief  Disable ADC voltage regulator.
00341   * @note   Disabling voltage regulator allows to save power. This operation can
00342   *         be carried out only when ADC is disabled.
00343   * @note   To enable again the voltage regulator, the user is expected to
00344   *         resort to HAL_ADC_Init() API.
00345   * @param hadc ADC handle
00346   * @retval HAL status
00347   */
00348 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
00349 {
00350   HAL_StatusTypeDef tmp_hal_status;
00351
00352   /* Check the parameters */
00353   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00354
00355   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
00356   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
00357   {
00358     LL_ADC_DisableInternalRegulator(hadc->Instance);
00359     tmp_hal_status = HAL_OK;
00360   }
00361   else
00362   {
00363     tmp_hal_status = HAL_ERROR;
00364   }
00365
00366   return tmp_hal_status;
00367 }
00368
00369 /**
00370   * @}
00371   */
00372
00373 /**
00374   * @}
00375   */
00376
00377 #endif /* HAL_ADC_MODULE_ENABLED */
00378 /**
00379   * @}
00380   */
00381
00382 /**
00383   * @}
00384   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_adc_ex.h Source File

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stm32g0xx_hal_adc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_ADC_EX_H
00021 #define STM32G0xx_HAL_ADC_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup ADCEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @}
00045   */
00046
00047 /* Exported constants --------------------------------------------------------*/
00048
00049 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
00050   * @{
00051   */
00052
00053 /** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
00054   * @{
00055   */
00056 #define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)           /*!< ADC group regular (available on all STM32 devices) */
00057 /**
00058   * @}
00059   */
00060
00061 /**
00062   * @}
00063   */
00064
00065 /* Exported macros -----------------------------------------------------------*/
00066
00067 /* Private macros ------------------------------------------------------------*/
00068
00069 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
00070   * @{
00071   */
00072 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00073 /* code of final user.                                                        */
00074
00075 /**
00076   * @brief Check whether or not ADC is independent.
00077   * @param __HANDLE__ ADC handle.
00078   * @note  When multimode feature is not available, the macro always returns SET.
00079   * @retval SET (ADC is independent) or RESET (ADC is not).
00080   */
00081 #define ADC_IS_INDEPENDENT(__HANDLE__)   (SET)
00082
00083
00084 /**
00085   * @brief Calibration factor size verification (7 bits maximum).
00086   * @param __CALIBRATION_FACTOR__ Calibration factor value.
00087   * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
00088   */
00089 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
00090
00091 /**
00092   * @brief Verify the ADC oversampling ratio.
00093   * @param __RATIO__ programmed ADC oversampling ratio.
00094   * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
00095   */
00096 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
00097                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
00098                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
00099                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
00100                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
00101                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
00102                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
00103                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
00104
00105 /**
00106   * @brief Verify the ADC oversampling shift.
00107   * @param __SHIFT__ programmed ADC oversampling shift.
00108   * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
00109   */
00110 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
00111                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
00112                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
00113                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
00114                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
00115                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
00116                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
00117                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
00118                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
00119
00120 /**
00121   * @brief Verify the ADC oversampling triggered mode.
00122   * @param __MODE__ programmed ADC oversampling triggered mode.
00123   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00124   */
00125 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
00126                                                       ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
00127
00128
00129 /**
00130   * @}
00131   */
00132
00133
00134 /* Exported functions --------------------------------------------------------*/
00135 /** @addtogroup ADCEx_Exported_Functions
00136   * @{
00137   */
00138
00139 /** @addtogroup ADCEx_Exported_Functions_Group1
00140   * @{
00141   */
00142 /* IO operation functions *****************************************************/
00143
00144 /* ADC calibration */
00145 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
00146 uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc);
00147 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor);
00148
00149 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
00150 void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
00151 void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
00152 void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
00153 void                    HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc);
00154
00155 /**
00156   * @}
00157   */
00158
00159 /** @addtogroup ADCEx_Exported_Functions_Group2
00160   * @{
00161   */
00162 /* Peripheral Control functions ***********************************************/
00163 HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
00164
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 #ifdef __cplusplus
00182 }
00183 #endif
00184
00185 #endif /* STM32G0xx_HAL_ADC_EX_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cec.c Source File

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stm32g0xx_hal_cec.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_cec.c
00004   * @author  MCD Application Team
00005   * @brief   CEC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the High Definition Multimedia Interface
00008   *          Consumer Electronics Control Peripheral (CEC).
00009   *           + Initialization and de-initialization function
00010   *           + IO operation function
00011   *           + Peripheral Control function
00012   *
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2018 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026  ===============================================================================
00027                         ##### How to use this driver #####
00028  ===============================================================================
00029     [..]
00030     The CEC HAL driver can be used as follow:
00031
00032     (#) Declare a CEC_HandleTypeDef handle structure.
00033     (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
00034         (##) Enable the CEC interface clock.
00035         (##) CEC pins configuration:
00036             (+++) Enable the clock for the CEC GPIOs.
00037             (+++) Configure these CEC pins as alternate function pull-up.
00038         (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
00039              and HAL_CEC_Receive_IT() APIs):
00040             (+++) Configure the CEC interrupt priority.
00041             (+++) Enable the NVIC CEC IRQ handle.
00042             (+++) The specific CEC interrupts (Transmission complete interrupt,
00043                   RXNE interrupt and Error Interrupts) will be managed using the macros
00044                   __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
00045                   and receive process.
00046
00047     (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
00048         in case of Bit Rising Error, Error-Bit generation conditions, device logical
00049         address and Listen mode in the hcec Init structure.
00050
00051     (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
00052
00053   [..]
00054     (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00055         by calling the customed HAL_CEC_MspInit() API.
00056   *** Callback registration ***
00057   =============================================
00058
00059   The compilation define  USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
00060   allows the user to configure dynamically the driver callbacks.
00061   Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
00062   to register an interrupt callback.
00063
00064   Function HAL_CEC_RegisterCallback() allows to register following callbacks:
00065     (+) TxCpltCallback     : Tx Transfer completed callback.
00066     (+) ErrorCallback      : callback for error detection.
00067     (+) MspInitCallback    : CEC MspInit.
00068     (+) MspDeInitCallback  : CEC MspDeInit.
00069   This function takes as parameters the HAL peripheral handle, the Callback ID
00070   and a pointer to the user callback function.
00071
00072   For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
00073   HAL_CEC_RegisterRxCpltCallback().
00074
00075   Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
00076   weak function.
00077   HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00078   and the Callback ID.
00079   This function allows to reset following callbacks:
00080     (+) TxCpltCallback     : Tx Transfer completed callback.
00081     (+) ErrorCallback      : callback for error detection.
00082     (+) MspInitCallback    : CEC MspInit.
00083     (+) MspDeInitCallback  : CEC MspDeInit.
00084
00085   For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
00086   HAL_CEC_UnRegisterRxCpltCallback().
00087
00088   By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
00089   all callbacks are set to the corresponding weak functions :
00090   examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
00091   Exception done for MspInit and MspDeInit functions that are
00092   reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
00093   these callbacks are null (not registered beforehand).
00094   if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
00095   keep and use the user MspInit/MspDeInit functions (registered beforehand)
00096
00097   Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
00098   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
00099   in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
00100   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00101   In that case first register the MspInit/MspDeInit user callbacks
00102   using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
00103   or HAL_CEC_Init() function.
00104
00105   When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
00106   not defined, the callback registration feature is not available and all callbacks
00107   are set to the corresponding weak functions.
00108   @endverbatim
00109   ******************************************************************************
00110   */
00111
00112 /* Includes ------------------------------------------------------------------*/
00113 #include "stm32g0xx_hal.h"
00114
00115 /** @addtogroup STM32G0xx_HAL_Driver
00116   * @{
00117   */
00118
00119 /** @defgroup CEC CEC
00120   * @brief HAL CEC module driver
00121   * @{
00122   */
00123 #ifdef HAL_CEC_MODULE_ENABLED
00124 #if defined (CEC)
00125
00126 /* Private typedef -----------------------------------------------------------*/
00127 /* Private define ------------------------------------------------------------*/
00128 /** @defgroup CEC_Private_Constants CEC Private Constants
00129   * @{
00130   */
00131 /**
00132   * @}
00133   */
00134
00135 /* Private macro -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private function prototypes -----------------------------------------------*/
00138 /** @defgroup CEC_Private_Functions CEC Private Functions
00139   * @{
00140   */
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported functions ---------------------------------------------------------*/
00146
00147 /** @defgroup CEC_Exported_Functions CEC Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
00152   *  @brief    Initialization and Configuration functions
00153   *
00154 @verbatim
00155 ===============================================================================
00156             ##### Initialization and Configuration functions #####
00157  ===============================================================================
00158     [..]
00159     This subsection provides a set of functions allowing to initialize the CEC
00160       (+) The following parameters need to be configured:
00161         (++) SignalFreeTime
00162         (++) Tolerance
00163         (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
00164         (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
00165         (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
00166         (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
00167         (++) SignalFreeTimeOption      (SFT Timer start definition)
00168         (++) OwnAddress                (CEC device address)
00169         (++) ListenMode
00170
00171 @endverbatim
00172   * @{
00173   */
00174
00175 /**
00176   * @brief Initializes the CEC mode according to the specified
00177   *         parameters in the CEC_InitTypeDef and creates the associated handle .
00178   * @param hcec CEC handle
00179   * @retval HAL status
00180   */
00181 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
00182 {
00183   /* Check the CEC handle allocation */
00184   if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
00185   {
00186     return HAL_ERROR;
00187   }
00188
00189   /* Check the parameters */
00190   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00191   assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
00192   assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
00193   assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
00194   assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
00195   assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
00196   assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
00197   assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
00198   assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
00199   assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
00200
00201 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00202   if (hcec->gState == HAL_CEC_STATE_RESET)
00203   {
00204     /* Allocate lock resource and initialize it */
00205     hcec->Lock = HAL_UNLOCKED;
00206
00207     hcec->TxCpltCallback  = HAL_CEC_TxCpltCallback;  /* Legacy weak TxCpltCallback  */
00208     hcec->RxCpltCallback = HAL_CEC_RxCpltCallback;   /* Legacy weak RxCpltCallback */
00209     hcec->ErrorCallback = HAL_CEC_ErrorCallback;     /* Legacy weak ErrorCallback */
00210
00211     if (hcec->MspInitCallback == NULL)
00212     {
00213       hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit  */
00214     }
00215
00216     /* Init the low level hardware */
00217     hcec->MspInitCallback(hcec);
00218   }
00219 #else
00220   if (hcec->gState == HAL_CEC_STATE_RESET)
00221   {
00222     /* Allocate lock resource and initialize it */
00223     hcec->Lock = HAL_UNLOCKED;
00224     /* Init the low level hardware : GPIO, CLOCK */
00225     HAL_CEC_MspInit(hcec);
00226   }
00227 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00228
00229   hcec->gState = HAL_CEC_STATE_BUSY;
00230
00231   /* Disable the Peripheral */
00232   __HAL_CEC_DISABLE(hcec);
00233
00234   /* Write to CEC Control Register */
00235   hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
00236                          hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
00237                          hcec->Init.BroadcastMsgNoErrorBitGen | \
00238                          hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
00239                          hcec->Init.ListenMode;
00240
00241   /* Enable the following CEC Transmission/Reception interrupts as
00242     * well as the following CEC Transmission/Reception Errors interrupts
00243     * Rx Byte Received IT
00244     * End of Reception IT
00245     * Rx overrun
00246     * Rx bit rising error
00247     * Rx short bit period error
00248     * Rx long bit period error
00249     * Rx missing acknowledge
00250     * Tx Byte Request IT
00251     * End of Transmission IT
00252     * Tx Missing Acknowledge IT
00253     * Tx-Error IT
00254     * Tx-Buffer Underrun IT
00255     * Tx arbitration lost   */
00256   __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
00257                       CEC_IER_TX_ALL_ERR);
00258
00259   /* Enable the CEC Peripheral */
00260   __HAL_CEC_ENABLE(hcec);
00261
00262   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00263   hcec->gState = HAL_CEC_STATE_READY;
00264   hcec->RxState = HAL_CEC_STATE_READY;
00265
00266   return HAL_OK;
00267 }
00268
00269 /**
00270   * @brief DeInitializes the CEC peripheral
00271   * @param hcec CEC handle
00272   * @retval HAL status
00273   */
00274 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
00275 {
00276   /* Check the CEC handle allocation */
00277   if (hcec == NULL)
00278   {
00279     return HAL_ERROR;
00280   }
00281
00282   /* Check the parameters */
00283   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00284
00285   hcec->gState = HAL_CEC_STATE_BUSY;
00286
00287 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00288   if (hcec->MspDeInitCallback == NULL)
00289   {
00290     hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit  */
00291   }
00292
00293   /* DeInit the low level hardware */
00294   hcec->MspDeInitCallback(hcec);
00295
00296 #else
00297   /* DeInit the low level hardware */
00298   HAL_CEC_MspDeInit(hcec);
00299 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00300
00301   /* Disable the Peripheral */
00302   __HAL_CEC_DISABLE(hcec);
00303
00304   /* Clear Flags */
00305   __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR);
00306
00307   /* Disable the following CEC Transmission/Reception interrupts as
00308     * well as the following CEC Transmission/Reception Errors interrupts
00309     * Rx Byte Received IT
00310     * End of Reception IT
00311     * Rx overrun
00312     * Rx bit rising error
00313     * Rx short bit period error
00314     * Rx long bit period error
00315     * Rx missing acknowledge
00316     * Tx Byte Request IT
00317     * End of Transmission IT
00318     * Tx Missing Acknowledge IT
00319     * Tx-Error IT
00320     * Tx-Buffer Underrun IT
00321     * Tx arbitration lost   */
00322   __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
00323                        CEC_IER_TX_ALL_ERR);
00324
00325   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00326   hcec->gState = HAL_CEC_STATE_RESET;
00327   hcec->RxState = HAL_CEC_STATE_RESET;
00328
00329   /* Process Unlock */
00330   __HAL_UNLOCK(hcec);
00331
00332   return HAL_OK;
00333 }
00334
00335 /**
00336   * @brief Initializes the Own Address of the CEC device
00337   * @param hcec CEC handle
00338   * @param  CEC_OwnAddress The CEC own address.
00339   * @retval HAL status
00340   */
00341 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
00342 {
00343   /* Check the parameters */
00344   assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
00345
00346   if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
00347   {
00348     /* Process Locked */
00349     __HAL_LOCK(hcec);
00350
00351     hcec->gState = HAL_CEC_STATE_BUSY;
00352
00353     /* Disable the Peripheral */
00354     __HAL_CEC_DISABLE(hcec);
00355
00356     if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
00357     {
00358       hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16);
00359     }
00360     else
00361     {
00362       hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
00363     }
00364
00365     hcec->gState = HAL_CEC_STATE_READY;
00366     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00367
00368     /* Process Unlocked */
00369     __HAL_UNLOCK(hcec);
00370
00371     /* Enable the Peripheral */
00372     __HAL_CEC_ENABLE(hcec);
00373
00374     return  HAL_OK;
00375   }
00376   else
00377   {
00378     return HAL_BUSY;
00379   }
00380 }
00381
00382 /**
00383   * @brief CEC MSP Init
00384   * @param hcec CEC handle
00385   * @retval None
00386   */
00387 __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
00388 {
00389   /* Prevent unused argument(s) compilation warning */
00390   UNUSED(hcec);
00391   /* NOTE : This function should not be modified, when the callback is needed,
00392             the HAL_CEC_MspInit can be implemented in the user file
00393    */
00394 }
00395
00396 /**
00397   * @brief CEC MSP DeInit
00398   * @param hcec CEC handle
00399   * @retval None
00400   */
00401 __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
00402 {
00403   /* Prevent unused argument(s) compilation warning */
00404   UNUSED(hcec);
00405   /* NOTE : This function should not be modified, when the callback is needed,
00406             the HAL_CEC_MspDeInit can be implemented in the user file
00407    */
00408 }
00409 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00410 /**
00411   * @brief  Register a User CEC Callback
00412   *         To be used instead of the weak predefined callback
00413   * @param  hcec CEC handle
00414   * @param  CallbackID ID of the callback to be registered
00415   *         This parameter can be one of the following values:
00416   *          @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
00417   *          @arg HAL_CEC_ERROR_CB_ID Error callback ID
00418   *          @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
00419   *          @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
00420   * @param  pCallback pointer to the Callback function
00421   * @retval HAL status
00422   */
00423 HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
00424                                            pCEC_CallbackTypeDef pCallback)
00425 {
00426   HAL_StatusTypeDef status = HAL_OK;
00427
00428   if (pCallback == NULL)
00429   {
00430     /* Update the error code */
00431     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00432     return HAL_ERROR;
00433   }
00434   /* Process locked */
00435   __HAL_LOCK(hcec);
00436
00437   if (hcec->gState == HAL_CEC_STATE_READY)
00438   {
00439     switch (CallbackID)
00440     {
00441       case HAL_CEC_TX_CPLT_CB_ID :
00442         hcec->TxCpltCallback = pCallback;
00443         break;
00444
00445       case HAL_CEC_ERROR_CB_ID :
00446         hcec->ErrorCallback = pCallback;
00447         break;
00448
00449       case HAL_CEC_MSPINIT_CB_ID :
00450         hcec->MspInitCallback = pCallback;
00451         break;
00452
00453       case HAL_CEC_MSPDEINIT_CB_ID :
00454         hcec->MspDeInitCallback = pCallback;
00455         break;
00456
00457       default :
00458         /* Update the error code */
00459         hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00460         /* Return error status */
00461         status =  HAL_ERROR;
00462         break;
00463     }
00464   }
00465   else if (hcec->gState == HAL_CEC_STATE_RESET)
00466   {
00467     switch (CallbackID)
00468     {
00469       case HAL_CEC_MSPINIT_CB_ID :
00470         hcec->MspInitCallback = pCallback;
00471         break;
00472
00473       case HAL_CEC_MSPDEINIT_CB_ID :
00474         hcec->MspDeInitCallback = pCallback;
00475         break;
00476
00477       default :
00478         /* Update the error code */
00479         hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00480         /* Return error status */
00481         status =  HAL_ERROR;
00482         break;
00483     }
00484   }
00485   else
00486   {
00487     /* Update the error code */
00488     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00489     /* Return error status */
00490     status =  HAL_ERROR;
00491   }
00492
00493   /* Release Lock */
00494   __HAL_UNLOCK(hcec);
00495
00496   return status;
00497 }
00498
00499 /**
00500   * @brief  Unregister an CEC Callback
00501   *         CEC callback is redirected to the weak predefined callback
00502   * @param hcec uart handle
00503   * @param CallbackID ID of the callback to be unregistered
00504   *         This parameter can be one of the following values:
00505   *          @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
00506   *          @arg HAL_CEC_ERROR_CB_ID Error callback ID
00507   *          @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
00508   *          @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
00509   * @retval status
00510   */
00511 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
00512 {
00513   HAL_StatusTypeDef status = HAL_OK;
00514
00515   /* Process locked */
00516   __HAL_LOCK(hcec);
00517
00518   if (hcec->gState == HAL_CEC_STATE_READY)
00519   {
00520     switch (CallbackID)
00521     {
00522       case HAL_CEC_TX_CPLT_CB_ID :
00523         hcec->TxCpltCallback = HAL_CEC_TxCpltCallback;  /* Legacy weak  TxCpltCallback */
00524         break;
00525
00526       case HAL_CEC_ERROR_CB_ID :
00527         hcec->ErrorCallback = HAL_CEC_ErrorCallback;  /* Legacy weak ErrorCallback   */
00528         break;
00529
00530       case HAL_CEC_MSPINIT_CB_ID :
00531         hcec->MspInitCallback = HAL_CEC_MspInit;
00532         break;
00533
00534       case HAL_CEC_MSPDEINIT_CB_ID :
00535         hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
00536         break;
00537
00538       default :
00539         /* Update the error code */
00540         hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00541         /* Return error status */
00542         status =  HAL_ERROR;
00543         break;
00544     }
00545   }
00546   else if (hcec->gState == HAL_CEC_STATE_RESET)
00547   {
00548     switch (CallbackID)
00549     {
00550       case HAL_CEC_MSPINIT_CB_ID :
00551         hcec->MspInitCallback = HAL_CEC_MspInit;
00552         break;
00553
00554       case HAL_CEC_MSPDEINIT_CB_ID :
00555         hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
00556         break;
00557
00558       default :
00559         /* Update the error code */
00560         hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00561         /* Return error status */
00562         status =  HAL_ERROR;
00563         break;
00564     }
00565   }
00566   else
00567   {
00568     /* Update the error code */
00569     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00570     /* Return error status */
00571     status =  HAL_ERROR;
00572   }
00573
00574   /* Release Lock */
00575   __HAL_UNLOCK(hcec);
00576
00577   return status;
00578 }
00579
00580 /**
00581   * @brief  Register CEC RX complete Callback
00582   *         To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
00583   * @param  hcec CEC handle
00584   * @param  pCallback pointer to the Rx transfer compelete Callback function
00585   * @retval HAL status
00586   */
00587 HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
00588 {
00589   HAL_StatusTypeDef status = HAL_OK;
00590
00591   if (pCallback == NULL)
00592   {
00593     /* Update the error code */
00594     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00595     return HAL_ERROR;
00596   }
00597   /* Process locked */
00598   __HAL_LOCK(hcec);
00599
00600   if (HAL_CEC_STATE_READY == hcec->RxState)
00601   {
00602     hcec->RxCpltCallback = pCallback;
00603   }
00604   else
00605   {
00606     /* Update the error code */
00607     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00608     /* Return error status */
00609     status =  HAL_ERROR;
00610   }
00611
00612   /* Release Lock */
00613   __HAL_UNLOCK(hcec);
00614   return status;
00615 }
00616
00617 /**
00618   * @brief  UnRegister CEC RX complete Callback
00619   *         CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
00620   * @param  hcec CEC handle
00621   * @retval HAL status
00622   */
00623 HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
00624 {
00625   HAL_StatusTypeDef status = HAL_OK;
00626
00627   /* Process locked */
00628   __HAL_LOCK(hcec);
00629
00630   if (HAL_CEC_STATE_READY == hcec->RxState)
00631   {
00632     hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak  CEC RxCpltCallback  */
00633   }
00634   else
00635   {
00636     /* Update the error code */
00637     hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
00638     /* Return error status */
00639     status =  HAL_ERROR;
00640   }
00641
00642   /* Release Lock */
00643   __HAL_UNLOCK(hcec);
00644   return status;
00645 }
00646 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00647
00648 /**
00649   * @}
00650   */
00651
00652 /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
00653   *  @brief CEC Transmit/Receive functions
00654   *
00655 @verbatim
00656  ===============================================================================
00657                       ##### IO operation functions #####
00658  ===============================================================================
00659     This subsection provides a set of functions allowing to manage the CEC data transfers.
00660
00661     (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
00662         logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
00663
00664     (#) The communication is performed using Interrupts.
00665            These API's return the HAL status.
00666            The end of the data processing will be indicated through the
00667            dedicated CEC IRQ when using Interrupt mode.
00668            The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
00669            will be executed respectively at the end of the transmit or Receive process
00670            The HAL_CEC_ErrorCallback() user callback will be executed when a communication
00671            error is detected
00672
00673     (#) API's with Interrupt are :
00674          (+) HAL_CEC_Transmit_IT()
00675          (+) HAL_CEC_IRQHandler()
00676
00677     (#) A set of User Callbacks are provided:
00678          (+) HAL_CEC_TxCpltCallback()
00679          (+) HAL_CEC_RxCpltCallback()
00680          (+) HAL_CEC_ErrorCallback()
00681
00682 @endverbatim
00683   * @{
00684   */
00685
00686 /**
00687   * @brief Send data in interrupt mode
00688   * @param hcec CEC handle
00689   * @param InitiatorAddress Initiator address
00690   * @param DestinationAddress destination logical address
00691   * @param pData pointer to input byte data buffer
00692   * @param Size amount of data to be sent in bytes (without counting the header).
00693   *              0 means only the header is sent (ping operation).
00694   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00695   * @retval HAL status
00696   */
00697 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
00698                                       const uint8_t *pData, uint32_t Size)
00699 {
00700   /* if the peripheral isn't already busy and if there is no previous transmission
00701      already pending due to arbitration lost */
00702   if (hcec->gState == HAL_CEC_STATE_READY)
00703   {
00704     if ((pData == NULL) && (Size > 0U))
00705     {
00706       return  HAL_ERROR;
00707     }
00708
00709     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00710     assert_param(IS_CEC_ADDRESS(InitiatorAddress));
00711     assert_param(IS_CEC_MSGSIZE(Size));
00712
00713     /* Process Locked */
00714     __HAL_LOCK(hcec);
00715     hcec->pTxBuffPtr = pData;
00716     hcec->gState = HAL_CEC_STATE_BUSY_TX;
00717     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00718
00719     /* initialize the number of bytes to send,
00720       * 0 means only one header is sent (ping operation) */
00721     hcec->TxXferCount = (uint16_t)Size;
00722
00723     /* in case of no payload (Size = 0), sender is only pinging the system;
00724        Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
00725     if (Size == 0U)
00726     {
00727       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00728     }
00729
00730     /* send header block */
00731     hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress);
00732
00733     /* Set TX Start of Message  (TXSOM) bit */
00734     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
00735
00736     /* Process Unlocked */
00737     __HAL_UNLOCK(hcec);
00738
00739     return HAL_OK;
00740
00741   }
00742   else
00743   {
00744     return HAL_BUSY;
00745   }
00746 }
00747
00748 /**
00749   * @brief Get size of the received frame.
00750   * @param hcec CEC handle
00751   * @retval Frame size
00752   */
00753 uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
00754 {
00755   return hcec->RxXferSize;
00756 }
00757
00758 /**
00759   * @brief Change Rx Buffer.
00760   * @param hcec CEC handle
00761   * @param Rxbuffer Rx Buffer
00762   * @note  This function can be called only inside the HAL_CEC_RxCpltCallback()
00763   * @retval Frame size
00764   */
00765 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
00766 {
00767   hcec->Init.RxBuffer = Rxbuffer;
00768 }
00769
00770 /**
00771   * @brief This function handles CEC interrupt requests.
00772   * @param hcec CEC handle
00773   * @retval None
00774   */
00775 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
00776 {
00777
00778   /* save interrupts register for further error or interrupts handling purposes */
00779   uint32_t itflag;
00780   itflag = hcec->Instance->ISR;
00781
00782
00783   /* ----------------------------Arbitration Lost Management----------------------------------*/
00784   /* CEC TX arbitration error interrupt occurred --------------------------------------*/
00785   if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
00786   {
00787     hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
00788     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
00789   }
00790
00791   /* ----------------------------Rx Management----------------------------------*/
00792   /* CEC RX byte received interrupt  ---------------------------------------------------*/
00793   if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
00794   {
00795     /* reception is starting */
00796     hcec->RxState = HAL_CEC_STATE_BUSY_RX;
00797     hcec->RxXferSize++;
00798     /* read received byte */
00799     *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR;
00800     hcec->Init.RxBuffer++;
00801     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
00802   }
00803
00804   /* CEC RX end received interrupt  ---------------------------------------------------*/
00805   if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
00806   {
00807     /* clear IT */
00808     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
00809
00810     /* Rx process is completed, restore hcec->RxState to Ready */
00811     hcec->RxState = HAL_CEC_STATE_READY;
00812     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00813     hcec->Init.RxBuffer -= hcec->RxXferSize;
00814 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
00815     hcec->RxCpltCallback(hcec, hcec->RxXferSize);
00816 #else
00817     HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
00818 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00819     hcec->RxXferSize = 0U;
00820   }
00821
00822   /* ----------------------------Tx Management----------------------------------*/
00823   /* CEC TX byte request interrupt ------------------------------------------------*/
00824   if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
00825   {
00826     --hcec->TxXferCount;
00827     if (hcec->TxXferCount == 0U)
00828     {
00829       /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
00830       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00831     }
00832     /* In all cases transmit the byte */
00833     hcec->Instance->TXDR = (uint8_t)*hcec->pTxBuffPtr;
00834     hcec->pTxBuffPtr++;
00835     /* clear Tx-Byte request flag */
00836     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
00837   }
00838
00839   /* CEC TX end interrupt ------------------------------------------------*/
00840   if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
00841   {
00842     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
00843
00844     /* Tx process is ended, restore hcec->gState to Ready */
00845     hcec->gState = HAL_CEC_STATE_READY;
00846     /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
00847     start again the Transmission under the Tx call back API */
00848     __HAL_UNLOCK(hcec);
00849     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00850 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
00851     hcec->TxCpltCallback(hcec);
00852 #else
00853     HAL_CEC_TxCpltCallback(hcec);
00854 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00855   }
00856
00857   /* ----------------------------Rx/Tx Error Management----------------------------------*/
00858   if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
00859               CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
00860   {
00861     hcec->ErrorCode = itflag;
00862     __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
00863                          HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
00864
00865
00866     if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
00867     {
00868       hcec->Init.RxBuffer -= hcec->RxXferSize;
00869       hcec->RxXferSize = 0U;
00870       hcec->RxState = HAL_CEC_STATE_READY;
00871     }
00872     else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
00873     {
00874       /* Set the CEC state ready to be able to start again the process */
00875       hcec->gState = HAL_CEC_STATE_READY;
00876     }
00877     else
00878     {
00879       /* Nothing todo*/
00880     }
00881 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
00882     hcec->ErrorCallback(hcec);
00883 #else
00884     /* Error  Call Back */
00885     HAL_CEC_ErrorCallback(hcec);
00886 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00887   }
00888   else
00889   {
00890     /* Nothing todo*/
00891   }
00892 }
00893
00894 /**
00895   * @brief Tx Transfer completed callback
00896   * @param hcec CEC handle
00897   * @retval None
00898   */
00899 __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
00900 {
00901   /* Prevent unused argument(s) compilation warning */
00902   UNUSED(hcec);
00903   /* NOTE : This function should not be modified, when the callback is needed,
00904             the HAL_CEC_TxCpltCallback can be implemented in the user file
00905    */
00906 }
00907
00908 /**
00909   * @brief Rx Transfer completed callback
00910   * @param hcec CEC handle
00911   * @param RxFrameSize Size of frame
00912   * @retval None
00913   */
00914 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
00915 {
00916   /* Prevent unused argument(s) compilation warning */
00917   UNUSED(hcec);
00918   UNUSED(RxFrameSize);
00919   /* NOTE : This function should not be modified, when the callback is needed,
00920             the HAL_CEC_RxCpltCallback can be implemented in the user file
00921    */
00922 }
00923
00924 /**
00925   * @brief CEC error callbacks
00926   * @param hcec CEC handle
00927   * @retval None
00928   */
00929 __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
00930 {
00931   /* Prevent unused argument(s) compilation warning */
00932   UNUSED(hcec);
00933   /* NOTE : This function should not be modified, when the callback is needed,
00934             the HAL_CEC_ErrorCallback can be implemented in the user file
00935    */
00936 }
00937 /**
00938   * @}
00939   */
00940
00941 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
00942   *  @brief   CEC control functions
00943   *
00944 @verbatim
00945  ===============================================================================
00946                       ##### Peripheral Control function #####
00947  ===============================================================================
00948     [..]
00949     This subsection provides a set of functions allowing to control the CEC.
00950      (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
00951      (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
00952 @endverbatim
00953   * @{
00954   */
00955 /**
00956   * @brief return the CEC state
00957   * @param hcec pointer to a CEC_HandleTypeDef structure that contains
00958   *              the configuration information for the specified CEC module.
00959   * @retval HAL state
00960   */
00961 HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
00962 {
00963   uint32_t temp1;
00964   uint32_t temp2;
00965   temp1 = hcec->gState;
00966   temp2 = hcec->RxState;
00967
00968   return (HAL_CEC_StateTypeDef)(temp1 | temp2);
00969 }
00970
00971 /**
00972   * @brief  Return the CEC error code
00973   * @param  hcec  pointer to a CEC_HandleTypeDef structure that contains
00974   *              the configuration information for the specified CEC.
00975   * @retval CEC Error Code
00976   */
00977 uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
00978 {
00979   return hcec->ErrorCode;
00980 }
00981
00982 /**
00983   * @}
00984   */
00985
00986 /**
00987   * @}
00988   */
00989 #endif /* CEC */
00990 #endif /* HAL_CEC_MODULE_ENABLED */
00991 /**
00992   * @}
00993   */
00994
00995 /**
00996   * @}
00997   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cec.h Source File

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stm32g0xx_hal_cec.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_cec.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CEC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_CEC_H
00021 #define STM32G0xx_HAL_CEC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 #if defined (CEC)
00031
00032 /** @addtogroup STM32G0xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup CEC
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup CEC_Exported_Types CEC Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief CEC Init Structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.
00051                                               It can be one of CEC_Signal_Free_Time
00052                                               and belongs to the set {0,...,7} where
00053                                               0x0 is the default configuration
00054                                               else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
00055
00056   uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
00057                                               it can be a value of CEC_Tolerance :
00058                                               it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
00059
00060   uint32_t BRERxStop;                    /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
00061                                               Error stops the reception.
00062                                               CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
00063                                               CEC_RX_STOP_ON_BRE:    reception is stopped. */
00064
00065   uint32_t BREErrorBitGen;               /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
00066                                               Error-Bit is generated on the
00067                                               CEC line upon Bit Rising Error detection.
00068                                               CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
00069                                               CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */
00070
00071   uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
00072                                               Error-Bit is generated on the
00073                                               CEC line upon Long Bit Period Error detection.
00074                                               CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation.
00075                                               CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */
00076
00077   uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
00078                                               Error-Bit generation on the CEC line
00079                                               upon an error detected on a broadcast message.
00080
00081                                               It supersedes BREGEN and LBPEGEN bits for a broadcast message error
00082                                               handling. It can take two values:
00083
00084                                               1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
00085                                                  a) BRE detection: error-bit generation on the CEC line if
00086                                                     BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
00087                                                  b) LBPE detection: error-bit generation on the CEC line
00088                                                     if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
00089
00090                                               2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
00091                                                  no error-bit generation in case neither a) nor b) are satisfied.
00092                                                  Additionally, there is no error-bit generation in case of Short Bit
00093                                                  Period Error detection in a broadcast message while LSTN bit is set. */
00094
00095   uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
00096                                               CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
00097                                               CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end
00098                                               of message transmission/reception. */
00099
00100   uint32_t ListenMode;                   /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
00101                                               It can take two values:
00102
00103                                               CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
00104                                                 to its own address (OAR). Messages addressed to different destination
00105                                                 are ignored.
00106                                                 Broadcast messages are always received.
00107
00108                                               CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
00109                                                 own address (OAR) with positive acknowledge. Messages addressed to
00110                                                 different destination are received, but without interfering with the
00111                                                 CEC bus: no acknowledge sent.  */
00112
00113   uint16_t  OwnAddress;                  /*!< Own addresses configuration
00114                                               This parameter can be a value of CEC_OWN_ADDRESS */
00115
00116   uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointer */
00117
00118
00119 } CEC_InitTypeDef;
00120
00121 /**
00122   * @brief HAL CEC State definition
00123   * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState
00124            (see CEC_State_Definition).
00125   *        - gState contains CEC state information related to global Handle management
00126   *          and also information related to Tx operations.
00127   *          gState value coding follow below described bitmap :
00128   *          b7 (not used)
00129   *             x  : Should be set to 0
00130   *          b6  Error information
00131   *             0  : No Error
00132   *             1  : Error
00133   *          b5     CEC peripheral initialization status
00134   *             0  : Reset (peripheral not initialized)
00135   *             1  : Init done (peripheral initialized. HAL CEC Init function already called)
00136   *          b4-b3  (not used)
00137   *             xx : Should be set to 00
00138   *          b2     Intrinsic process state
00139   *             0  : Ready
00140   *             1  : Busy (peripheral busy with some configuration or internal operations)
00141   *          b1     (not used)
00142   *             x  : Should be set to 0
00143   *          b0     Tx state
00144   *             0  : Ready (no Tx operation ongoing)
00145   *             1  : Busy (Tx operation ongoing)
00146   *        - RxState contains information related to Rx operations.
00147   *          RxState value coding follow below described bitmap :
00148   *          b7-b6  (not used)
00149   *             xx : Should be set to 00
00150   *          b5     CEC peripheral initialization status
00151   *             0  : Reset (peripheral not initialized)
00152   *             1  : Init done (peripheral initialized)
00153   *          b4-b2  (not used)
00154   *            xxx : Should be set to 000
00155   *          b1     Rx state
00156   *             0  : Ready (no Rx operation ongoing)
00157   *             1  : Busy (Rx operation ongoing)
00158   *          b0     (not used)
00159   *             x  : Should be set to 0.
00160   */
00161 typedef uint32_t HAL_CEC_StateTypeDef;
00162
00163 /**
00164   * @brief  CEC handle Structure definition
00165   */
00166 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00167 typedef struct __CEC_HandleTypeDef
00168 #else
00169 typedef struct
00170 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00171 {
00172   CEC_TypeDef             *Instance;      /*!< CEC registers base address                                 */
00173
00174   CEC_InitTypeDef         Init;           /*!< CEC communication parameters                               */
00175
00176   const uint8_t           *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer                          */
00177
00178   uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter                                    */
00179
00180   uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only              */
00181
00182   HAL_LockTypeDef         Lock;           /*!< Locking object                                             */
00183
00184   HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management
00185                                                and also related to Tx operations.
00186                                                This parameter can be a value of HAL_CEC_StateTypeDef      */
00187
00188   HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
00189                                                This parameter can be a value of HAL_CEC_StateTypeDef      */
00190
00191   uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register
00192                                                in case error is reported                                  */
00193
00194 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00195   void (* TxCpltCallback)(struct __CEC_HandleTypeDef
00196                           *hcec);                                /*!< CEC Tx Transfer completed callback  */
00197   void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
00198                           uint32_t RxFrameSize);                 /*!< CEC Rx Transfer completed callback  */
00199   void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec);      /*!< CEC error callback                  */
00200
00201   void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec);    /*!< CEC Msp Init callback               */
00202   void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec);  /*!< CEC Msp DeInit callback             */
00203
00204 #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
00205 } CEC_HandleTypeDef;
00206
00207 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00208 /**
00209   * @brief  HAL CEC Callback ID enumeration definition
00210   */
00211 typedef enum
00212 {
00213   HAL_CEC_TX_CPLT_CB_ID      = 0x00U,    /*!< CEC Tx Transfer completed callback ID  */
00214   HAL_CEC_RX_CPLT_CB_ID      = 0x01U,    /*!< CEC Rx Transfer completed callback ID  */
00215   HAL_CEC_ERROR_CB_ID        = 0x02U,    /*!< CEC error callback ID                  */
00216   HAL_CEC_MSPINIT_CB_ID      = 0x03U,    /*!< CEC Msp Init callback ID               */
00217   HAL_CEC_MSPDEINIT_CB_ID    = 0x04U     /*!< CEC Msp DeInit callback ID             */
00218 } HAL_CEC_CallbackIDTypeDef;
00219
00220 /**
00221   * @brief  HAL CEC Callback pointer definition
00222   */
00223 typedef  void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec);  /*!< pointer to an CEC callback function */
00224 typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
00225                                         uint32_t RxFrameSize);  /*!< pointer to an Rx Transfer completed
00226                                                                      callback function */
00227 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00228 /**
00229   * @}
00230   */
00231
00232 /* Exported constants --------------------------------------------------------*/
00233 /** @defgroup CEC_Exported_Constants CEC Exported Constants
00234   * @{
00235   */
00236 /** @defgroup CEC_State_Definition CEC State Code Definition
00237   * @{
00238   */
00239 #define   HAL_CEC_STATE_RESET      ((uint32_t)0x00000000)   /*!< Peripheral is not yet Initialized
00240                                                                  Value is allowed for gState and RxState  */
00241 #define   HAL_CEC_STATE_READY      ((uint32_t)0x00000020)   /*!< Peripheral Initialized and ready for use
00242                                                                  Value is allowed for gState and RxState  */
00243 #define   HAL_CEC_STATE_BUSY       ((uint32_t)0x00000024)   /*!< an internal process is ongoing
00244                                                                  Value is allowed for gState only         */
00245 #define   HAL_CEC_STATE_BUSY_RX    ((uint32_t)0x00000022)   /*!< Data Reception process is ongoing
00246                                                                  Value is allowed for RxState only        */
00247 #define   HAL_CEC_STATE_BUSY_TX    ((uint32_t)0x00000021)   /*!< Data Transmission process is ongoing
00248                                                                  Value is allowed for gState only         */
00249 #define   HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)   /*!< an internal process is ongoing
00250                                                                  Value is allowed for gState only         */
00251 #define   HAL_CEC_STATE_ERROR      ((uint32_t)0x00000050)   /*!< Error Value is allowed for gState only   */
00252 /**
00253   * @}
00254   */
00255 /** @defgroup CEC_Error_Code CEC Error Code
00256   * @{
00257   */
00258 #define HAL_CEC_ERROR_NONE    (uint32_t) 0x0000U     /*!< no error                      */
00259 #define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */
00260 #define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */
00261 #define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */
00262 #define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */
00263 #define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */
00264 #define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */
00265 #define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */
00266 #define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */
00267 #define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */
00268 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00269 #define  HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error  */
00270 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter
00276   * @{
00277   */
00278 #define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000U)
00279 #define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001U)
00280 #define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002U)
00281 #define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003U)
00282 #define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004U)
00283 #define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005U)
00284 #define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006U)
00285 #define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007U)
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
00291   * @{
00292   */
00293 #define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000U)
00294 #define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
00300   * @{
00301   */
00302 #define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000U)
00303 #define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported
00309   * @{
00310   */
00311 #define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)
00312 #define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported
00318   * @{
00319   */
00320 #define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)
00321 #define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message
00327   * @{
00328   */
00329 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000U)
00330 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup CEC_SFT_Option     CEC Signal Free Time start option
00336   * @{
00337   */
00338 #define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000U)
00339 #define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup CEC_Listening_Mode    CEC Listening mode option
00345   * @{
00346   */
00347 #define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000U)
00348 #define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register
00354   * @{
00355   */
00356 #define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16U)
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header
00362   * @{
00363   */
00364 #define CEC_INITIATOR_LSB_POS           ((uint32_t) 4U)
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup CEC_OWN_ADDRESS   CEC Own Address
00370   * @{
00371   */
00372 #define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value        */
00373 #define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0  */
00374 #define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1  */
00375 #define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2  */
00376 #define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3  */
00377 #define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4  */
00378 #define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5  */
00379 #define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6  */
00380 #define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7  */
00381 #define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9  */
00382 #define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10 */
00383 #define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11 */
00384 #define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12 */
00385 #define CEC_OWN_ADDRESS_12             ((uint16_t) 0x1000U)   /* Logical Address 13 */
00386 #define CEC_OWN_ADDRESS_13             ((uint16_t) 0x2000U)   /* Logical Address 14 */
00387 #define CEC_OWN_ADDRESS_14             ((uint16_t) 0x4000U)   /* Logical Address 15 */
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition
00393   * @{
00394   */
00395 #define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
00396 #define CEC_IT_TXERR                    CEC_IER_TXERRIE
00397 #define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
00398 #define CEC_IT_TXEND                    CEC_IER_TXENDIE
00399 #define CEC_IT_TXBR                     CEC_IER_TXBRIE
00400 #define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
00401 #define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
00402 #define CEC_IT_LBPE                     CEC_IER_LBPEIE
00403 #define CEC_IT_SBPE                     CEC_IER_SBPEIE
00404 #define CEC_IT_BRE                      CEC_IER_BREIE
00405 #define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
00406 #define CEC_IT_RXEND                    CEC_IER_RXENDIE
00407 #define CEC_IT_RXBR                     CEC_IER_RXBRIE
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup CEC_Flags_Definitions  CEC Flags definition
00413   * @{
00414   */
00415 #define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
00416 #define CEC_FLAG_TXERR                  CEC_ISR_TXERR
00417 #define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
00418 #define CEC_FLAG_TXEND                  CEC_ISR_TXEND
00419 #define CEC_FLAG_TXBR                   CEC_ISR_TXBR
00420 #define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
00421 #define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
00422 #define CEC_FLAG_LBPE                   CEC_ISR_LBPE
00423 #define CEC_FLAG_SBPE                   CEC_ISR_SBPE
00424 #define CEC_FLAG_BRE                    CEC_ISR_BRE
00425 #define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
00426 #define CEC_FLAG_RXEND                  CEC_ISR_RXEND
00427 #define CEC_FLAG_RXBR                   CEC_ISR_RXBR
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
00433   * @{
00434   */
00435 #define CEC_ISR_ALL_ERROR       ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
00436                                  CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
00442   * @{
00443   */
00444 #define CEC_IER_RX_ALL_ERR      ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
00450   * @{
00451   */
00452 #define CEC_IER_TX_ALL_ERR      ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
00453 /**
00454   * @}
00455   */
00456
00457 /**
00458   * @}
00459   */
00460
00461 /* Exported macros -----------------------------------------------------------*/
00462 /** @defgroup CEC_Exported_Macros CEC Exported Macros
00463   * @{
00464   */
00465
00466 /** @brief  Reset CEC handle gstate & RxState
00467   * @param  __HANDLE__ CEC handle.
00468   * @retval None
00469   */
00470 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00471 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
00472                                                        (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
00473                                                        (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
00474                                                        (__HANDLE__)->MspInitCallback = NULL;           \
00475                                                        (__HANDLE__)->MspDeInitCallback = NULL;         \
00476                                                      } while(0)
00477 #else
00478 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
00479                                                        (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
00480                                                        (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
00481                                                      } while(0)
00482 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00483 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
00484   * @param  __HANDLE__ specifies the CEC Handle.
00485   * @param  __FLAG__ specifies the flag to check.
00486   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00487   *            @arg CEC_FLAG_TXERR: Tx Error.
00488   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00489   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00490   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00491   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00492   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00493   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00494   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00495   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00496   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00497   *            @arg CEC_FLAG_RXEND: End Of Reception.
00498   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00499   * @retval ITStatus
00500   */
00501 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__))
00502
00503 /** @brief  Clears the interrupt or status flag when raised (write at 1)
00504   * @param  __HANDLE__ specifies the CEC Handle.
00505   * @param  __FLAG__ specifies the interrupt/status flag to clear.
00506   *        This parameter can be one of the following values:
00507   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00508   *            @arg CEC_FLAG_TXERR: Tx Error.
00509   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00510   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00511   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00512   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00513   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00514   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00515   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00516   *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
00517   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00518   *            @arg CEC_FLAG_RXEND: End Of Reception.
00519   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00520   * @retval none
00521   */
00522 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__))
00523
00524 /** @brief  Enables the specified CEC interrupt.
00525   * @param  __HANDLE__ specifies the CEC Handle.
00526   * @param  __INTERRUPT__ specifies the CEC interrupt to enable.
00527   *          This parameter can be one of the following values:
00528   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00529   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00530   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00531   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00532   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00533   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00534   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00535   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00536   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00537   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00538   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00539   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00540   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00541   * @retval none
00542   */
00543 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00544
00545 /** @brief  Disables the specified CEC interrupt.
00546   * @param  __HANDLE__ specifies the CEC Handle.
00547   * @param  __INTERRUPT__ specifies the CEC interrupt to disable.
00548   *          This parameter can be one of the following values:
00549   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00550   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00551   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00552   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00553   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00554   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00555   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00556   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00557   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00558   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00559   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00560   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00561   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00562   * @retval none
00563   */
00564 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00565
00566 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
00567   * @param  __HANDLE__ specifies the CEC Handle.
00568   * @param  __INTERRUPT__ specifies the CEC interrupt to check.
00569   *          This parameter can be one of the following values:
00570   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00571   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00572   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00573   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00574   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00575   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00576   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00577   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00578   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00579   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00580   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00581   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00582   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00583   * @retval FlagStatus
00584   */
00585 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00586
00587 /** @brief  Enables the CEC device
00588   * @param  __HANDLE__ specifies the CEC Handle.
00589   * @retval none
00590   */
00591 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
00592
00593 /** @brief  Disables the CEC device
00594   * @param  __HANDLE__ specifies the CEC Handle.
00595   * @retval none
00596   */
00597 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
00598
00599 /** @brief  Set Transmission Start flag
00600   * @param  __HANDLE__ specifies the CEC Handle.
00601   * @retval none
00602   */
00603 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
00604
00605 /** @brief  Set Transmission End flag
00606   * @param  __HANDLE__ specifies the CEC Handle.
00607   * @retval none
00608   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
00609   */
00610 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
00611
00612 /** @brief  Get Transmission Start flag
00613   * @param  __HANDLE__ specifies the CEC Handle.
00614   * @retval FlagStatus
00615   */
00616 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
00617
00618 /** @brief  Get Transmission End flag
00619   * @param  __HANDLE__ specifies the CEC Handle.
00620   * @retval FlagStatus
00621   */
00622 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
00623
00624 /** @brief  Clear OAR register
00625   * @param  __HANDLE__ specifies the CEC Handle.
00626   * @retval none
00627   */
00628 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
00629
00630 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
00631   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
00632   * @param  __HANDLE__ specifies the CEC Handle.
00633   * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
00634   * @retval none
00635   */
00636 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, \
00637                                                             (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
00638
00639 /**
00640   * @}
00641   */
00642
00643 /* Exported functions --------------------------------------------------------*/
00644 /** @addtogroup CEC_Exported_Functions
00645   * @{
00646   */
00647
00648 /** @addtogroup CEC_Exported_Functions_Group1
00649   * @{
00650   */
00651 /* Initialization and de-initialization functions  ****************************/
00652 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
00653 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
00654 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
00655 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
00656 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
00657
00658 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
00659 HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
00660                                            pCEC_CallbackTypeDef pCallback);
00661 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
00662
00663 HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
00664 HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
00665 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
00666 /**
00667   * @}
00668   */
00669
00670 /** @addtogroup CEC_Exported_Functions_Group2
00671   * @{
00672   */
00673 /* I/O operation functions  ***************************************************/
00674 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
00675                                       const uint8_t *pData, uint32_t Size);
00676 uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
00677 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
00678 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
00679 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
00680 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
00681 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
00682 /**
00683   * @}
00684   */
00685
00686 /** @addtogroup CEC_Exported_Functions_Group3
00687   * @{
00688   */
00689 /* Peripheral State functions  ************************************************/
00690 HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
00691 uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
00692 /**
00693   * @}
00694   */
00695
00696 /**
00697   * @}
00698   */
00699
00700 /* Private types -------------------------------------------------------------*/
00701 /** @defgroup CEC_Private_Types CEC Private Types
00702   * @{
00703   */
00704
00705 /**
00706   * @}
00707   */
00708
00709 /* Private variables ---------------------------------------------------------*/
00710 /** @defgroup CEC_Private_Variables CEC Private Variables
00711   * @{
00712   */
00713
00714 /**
00715   * @}
00716   */
00717
00718 /* Private constants ---------------------------------------------------------*/
00719 /** @defgroup CEC_Private_Constants CEC Private Constants
00720   * @{
00721   */
00722
00723 /**
00724   * @}
00725   */
00726
00727 /* Private macros ------------------------------------------------------------*/
00728 /** @defgroup CEC_Private_Macros CEC Private Macros
00729   * @{
00730   */
00731
00732 #define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)
00733
00734 #define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
00735                                             ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
00736
00737 #define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
00738                                            ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
00739
00740 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
00741                                                 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
00742
00743 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
00744                                                  ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
00745
00746 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
00747   (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
00748    ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
00749
00750 #define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
00751                                           ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
00752
00753 #define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
00754                                              ((__MODE__) == CEC_FULL_LISTENING_MODE))
00755
00756 /** @brief Check CEC message size.
00757   *       The message size is the payload size: without counting the header,
00758   *       it varies from 0 byte (ping operation, one header only, no payload) to
00759   *       15 bytes (1 opcode and up to 14 operands following the header).
00760   * @param  __SIZE__ CEC message size.
00761   * @retval Test result (TRUE or FALSE).
00762   */
00763 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
00764
00765 /** @brief Check CEC device Own Address Register (OAR) setting.
00766   *        OAR address is written in a 15-bit field within CEC_CFGR register.
00767   * @param  __ADDRESS__ CEC own address.
00768   * @retval Test result (TRUE or FALSE).
00769   */
00770 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
00771
00772 /** @brief Check CEC initiator or destination logical address setting.
00773   *        Initiator and destination addresses are coded over 4 bits.
00774   * @param  __ADDRESS__ CEC initiator or logical address.
00775   * @retval Test result (TRUE or FALSE).
00776   */
00777 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
00778 /**
00779   * @}
00780   */
00781 /* Private functions ---------------------------------------------------------*/
00782 /** @defgroup CEC_Private_Functions CEC Private Functions
00783   * @{
00784   */
00785
00786 /**
00787   * @}
00788   */
00789
00790 /**
00791   * @}
00792   */
00793
00794 /**
00795   * @}
00796   */
00797
00798 #endif /* CEC */
00799
00800 #ifdef __cplusplus
00801 }
00802 #endif
00803
00804 #endif /* STM32G0xxHAL_CEC_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_comp.c Source File

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stm32g0xx_hal_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the COMP peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral control functions
00010   *           + Peripheral state functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024 ================================================================================
00025           ##### COMP Peripheral features #####
00026 ================================================================================
00027
00028   [..]
00029       The STM32G0xx device family integrates two analog comparators instances:
00030       COMP1, COMP2.
00031       (#) Comparators input minus (inverting input) and input plus (non inverting input)
00032           can be set to internal references or to GPIO pins
00033           (refer to GPIO list in reference manual).
00034
00035       (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
00036           and can be redirected to other peripherals: GPIO pins (in mode
00037           alternate functions for comparator), timers.
00038           (refer to GPIO list in reference manual).
00039
00040       (#) The comparators have interrupt capability through the EXTI controller
00041           with wake-up from sleep and stop modes.
00042
00043       (#) Pairs of comparators instances can be combined in window mode
00044           (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00045
00046           From the corresponding IRQ handler, the right interrupt source can be retrieved
00047           using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
00048
00049             ##### How to use this driver #####
00050 ================================================================================
00051   [..]
00052       This driver provides functions to configure and program the comparator instances
00053       of STM32G0xx devices.
00054
00055       To use the comparator, perform the following steps:
00056
00057       (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
00058       (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
00059            using HAL_GPIO_Init().
00060       (++) If needed, configure the GPIO connected to comparator output in alternate function mode
00061            using HAL_GPIO_Init().
00062       (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
00063            selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
00064            interrupt vector using HAL_NVIC_EnableIRQ() function.
00065
00066       (#) Configure the comparator using HAL_COMP_Init() function:
00067       (++) Select the input minus (inverting input)
00068       (++) Select the input plus (non-inverting input)
00069       (++) Select the hysteresis
00070       (++) Select the blanking source
00071       (++) Select the output polarity
00072       (++) Select the power mode
00073       (++) Select the window mode
00074
00075       -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
00076           to enable internal control clock of the comparators.
00077           However, this is a legacy strategy. In future STM32 families,
00078           COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
00079           Therefore, for compatibility anticipation, it is recommended to
00080           implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
00081
00082       (#) Reconfiguration on-the-fly of comparator can be done by calling again
00083           function HAL_COMP_Init() with new input structure parameters values.
00084
00085       (#) Enable the comparator using HAL_COMP_Start() function.
00086
00087       (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
00088           to manage comparator outputs (events and output level).
00089
00090       (#) Disable the comparator using HAL_COMP_Stop() function.
00091
00092       (#) De-initialize the comparator using HAL_COMP_DeInit() function.
00093
00094       (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
00095           The only way to unlock the comparator is a device hardware reset.
00096
00097     *** Callback registration ***
00098     =============================================
00099     [..]
00100
00101      The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
00102      allows the user to configure dynamically the driver callbacks.
00103      Use Functions HAL_COMP_RegisterCallback()
00104      to register an interrupt callback.
00105     [..]
00106
00107      Function HAL_COMP_RegisterCallback() allows to register following callbacks:
00108        (+) TriggerCallback       : callback for COMP trigger.
00109        (+) MspInitCallback       : callback for Msp Init.
00110        (+) MspDeInitCallback     : callback for Msp DeInit.
00111      This function takes as parameters the HAL peripheral handle, the Callback ID
00112      and a pointer to the user callback function.
00113     [..]
00114
00115      Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
00116      weak function.
00117     [..]
00118
00119      HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
00120      and the Callback ID.
00121      This function allows to reset following callbacks:
00122        (+) TriggerCallback       : callback for COMP trigger.
00123        (+) MspInitCallback       : callback for Msp Init.
00124        (+) MspDeInitCallback     : callback for Msp DeInit.
00125      [..]
00126
00127      By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
00128      all callbacks are set to the corresponding weak functions:
00129      example HAL_COMP_TriggerCallback().
00130      Exception done for MspInit and MspDeInit functions that are
00131      reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
00132      these callbacks are null (not registered beforehand).
00133     [..]
00134
00135      If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
00136      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00137      [..]
00138
00139      Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
00140      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00141      in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
00142      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00143     [..]
00144
00145      Then, the user first registers the MspInit/MspDeInit user callbacks
00146      using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
00147      or HAL_COMP_Init() function.
00148      [..]
00149
00150      When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
00151      not defined, the callback registration feature is not available and all callbacks
00152      are set to the corresponding weak functions.
00153
00154   @endverbatim
00155   ******************************************************************************
00156
00157   */
00158
00159 /* Includes ------------------------------------------------------------------*/
00160 #include "stm32g0xx_hal.h"
00161
00162 /** @addtogroup STM32G0xx_HAL_Driver
00163   * @{
00164   */
00165
00166 #ifdef HAL_COMP_MODULE_ENABLED
00167
00168 #if defined (COMP1) || defined (COMP2)
00169
00170 /** @defgroup COMP COMP
00171   * @brief COMP HAL module driver
00172   * @{
00173   */
00174
00175 /* Private typedef -----------------------------------------------------------*/
00176 /* Private define ------------------------------------------------------------*/
00177 /** @addtogroup COMP_Private_Constants
00178   * @{
00179   */
00180
00181 /* Delay for COMP startup time.                                               */
00182 /* Note: Delay required to reach propagation delay specification.             */
00183 /* Literal set to maximum value (refer to device datasheet,                   */
00184 /* parameter "tSTART").                                                       */
00185 /* Unit: us                                                                   */
00186 #define COMP_DELAY_STARTUP_US          (80UL) /*!< Delay for COMP startup time */
00187
00188 /* Delay for COMP voltage scaler stabilization time.                          */
00189 /* Literal set to maximum value (refer to device datasheet,                   */
00190 /* parameter "tSTART_SCALER").                                                */
00191 /* Unit: us                                                                   */
00192 #define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)  /*!< Delay for COMP voltage scaler stabilization time */
00193
00194 #define COMP_OUTPUT_LEVEL_BITOFFSET_POS    (30UL)
00195
00196 /**
00197   * @}
00198   */
00199
00200 /* Private macro -------------------------------------------------------------*/
00201 /* Private variables ---------------------------------------------------------*/
00202 /* Private function prototypes -----------------------------------------------*/
00203 /* Exported functions --------------------------------------------------------*/
00204
00205 /** @defgroup COMP_Exported_Functions COMP Exported Functions
00206   * @{
00207   */
00208
00209 /** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
00210   *  @brief    Initialization and de-initialization functions.
00211   *
00212 @verbatim
00213  ===============================================================================
00214               ##### Initialization and de-initialization functions #####
00215  ===============================================================================
00216     [..]  This section provides functions to initialize and de-initialize comparators
00217
00218 @endverbatim
00219   * @{
00220   */
00221
00222 /**
00223   * @brief  Initialize the COMP according to the specified
00224   *         parameters in the COMP_InitTypeDef and initialize the associated handle.
00225   * @note   If the selected comparator is locked, initialization can't be performed.
00226   *         To unlock the configuration, perform a system reset.
00227   * @param  hcomp  COMP handle
00228   * @retval HAL status
00229   */
00230 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
00231 {
00232   uint32_t tmp_csr;
00233   uint32_t exti_line;
00234   uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
00235   __IO uint32_t wait_loop_index = 0UL;
00236   HAL_StatusTypeDef status = HAL_OK;
00237 #if defined(COMP3)
00238   __IO uint32_t * comp_common_odd;
00239   __IO uint32_t * comp_common_even;
00240 #endif /* COMP3 */
00241
00242   /* Check the COMP handle allocation and lock status */
00243   if(hcomp == NULL)
00244   {
00245     status = HAL_ERROR;
00246   }
00247   else if(__HAL_COMP_IS_LOCKED(hcomp))
00248   {
00249     status = HAL_ERROR;
00250   }
00251   else
00252   {
00253     /* Check the parameters */
00254     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00255     assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus));
00256     assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus));
00257     assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
00258     assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
00259     assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
00260     assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
00261     assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
00262     assert_param(IS_COMP_WINDOWMODE(hcomp->Instance, hcomp->Init.WindowMode));
00263     if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
00264     {
00265       assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput));
00266     }
00267
00268     if(hcomp->State == HAL_COMP_STATE_RESET)
00269     {
00270       /* Allocate lock resource and initialize it */
00271       hcomp->Lock = HAL_UNLOCKED;
00272
00273       /* Set COMP error code to none */
00274       COMP_CLEAR_ERRORCODE(hcomp);
00275
00276
00277 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00278       /* Init the COMP Callback settings */
00279       hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
00280
00281       if (hcomp->MspInitCallback == NULL)
00282       {
00283         hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit  */
00284       }
00285
00286       /* Init the low level hardware */
00287       /* Note: Internal control clock of the comparators must                 */
00288       /*       be enabled in "HAL_COMP_MspInit()"                             */
00289       /*       using "__HAL_RCC_SYSCFG_CLK_ENABLE()".                         */
00290       hcomp->MspInitCallback(hcomp);
00291 #else
00292       /* Init the low level hardware */
00293       /* Note: Internal control clock of the comparators must                 */
00294       /*       be enabled in "HAL_COMP_MspInit()"                             */
00295       /*       using "__HAL_RCC_SYSCFG_CLK_ENABLE()".                         */
00296       HAL_COMP_MspInit(hcomp);
00297 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00298     }
00299
00300     /* Memorize voltage scaler state before initialization */
00301     comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0));
00302
00303     /* Set COMP parameters */
00304     tmp_csr = (  hcomp->Init.InputMinus
00305                | hcomp->Init.InputPlus
00306                | hcomp->Init.BlankingSrce
00307                | hcomp->Init.Hysteresis
00308                | hcomp->Init.OutputPol
00309                | hcomp->Init.Mode
00310               );
00311
00312     /* Set parameters in COMP register */
00313     /* Note: Update all bits except read-only, lock and enable bits */
00314     MODIFY_REG(hcomp->Instance->CSR,
00315                COMP_CSR_PWRMODE  | COMP_CSR_INMSEL   | COMP_CSR_INPSEL  |
00316                COMP_CSR_WINMODE  | COMP_CSR_POLARITY | COMP_CSR_HYST    |
00317                COMP_CSR_BLANKING                                         ,
00318                tmp_csr
00319               );
00320
00321     /* Set window mode */
00322     /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
00323     /*       instances. Therefore, this function can update another COMP      */
00324     /*       instance that the one currently selected.                        */
00325 #if defined(COMP3)
00326     if(hcomp->Instance == COMP3)
00327     {
00328       /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common   */
00329       /*       group of COMP2 and COMP3, instances odd and even are inverted.     */
00330       /*       Perform switch of parameter selected.                              */
00331       comp_common_odd = &(COMP23_COMMON->CSR_EVEN);
00332       comp_common_even = &(COMP23_COMMON->CSR_ODD);
00333     }
00334     else
00335     {
00336       comp_common_odd = &(COMP12_COMMON->CSR_ODD);
00337       comp_common_even = &(COMP12_COMMON->CSR_EVEN);
00338     }
00339
00340     if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
00341     {
00342       CLEAR_BIT(*comp_common_odd, COMP_CSR_WINMODE);
00343       SET_BIT(*comp_common_even, COMP_CSR_WINMODE);
00344     }
00345     else if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)
00346     {
00347       SET_BIT(*comp_common_odd, COMP_CSR_WINMODE);
00348       CLEAR_BIT(*comp_common_even, COMP_CSR_WINMODE);
00349     }
00350     else
00351     {
00352       CLEAR_BIT(*comp_common_odd, COMP_CSR_WINMODE);
00353       CLEAR_BIT(*comp_common_even, COMP_CSR_WINMODE);
00354     }
00355
00356     /* Set window mode output */
00357     /* Note: Window mode mode output can also be used when window mode        */
00358     /*       is disabled, to use comparators in independent mode with their   */
00359     /*       output connected through exclusive-or circuitry.                 */
00360     switch (hcomp->Init.WindowOutput)
00361     {
00362       case COMP_WINDOWOUTPUT_COMP1: /* idem COMP_WINDOWOUTPUT_COMP3 (same literal value) */
00363         SET_BIT(*comp_common_odd, COMP_CSR_WINOUT);
00364         CLEAR_BIT(*comp_common_even, COMP_CSR_WINOUT);
00365         break;
00366
00367       case COMP_WINDOWOUTPUT_COMP2:
00368         CLEAR_BIT(*comp_common_odd, COMP_CSR_WINOUT);
00369         SET_BIT(*comp_common_even, COMP_CSR_WINOUT);
00370         break;
00371
00372       case COMP_WINDOWOUTPUT_BOTH:
00373         SET_BIT(*comp_common_odd, COMP_CSR_WINOUT);
00374         SET_BIT(*comp_common_even, COMP_CSR_WINOUT);
00375         break;
00376
00377       default: /* COMP_WINDOWOUTPUT_EACH_COMP */
00378         CLEAR_BIT(*comp_common_odd, COMP_CSR_WINOUT);
00379         CLEAR_BIT(*comp_common_even, COMP_CSR_WINOUT);
00380         break;
00381     }
00382 #else
00383     if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
00384     {
00385       CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
00386       SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00387     }
00388     else if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)
00389     {
00390       SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
00391       CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00392     }
00393     else
00394     {
00395       CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
00396       CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00397     }
00398
00399     /* Set window mode output */
00400     /* Note: Window mode mode output can also be used when window mode        */
00401     /*       is disabled, to use comparators in independent mode with their   */
00402     /*       output connected through exclusive-or circuitry.                 */
00403     switch (hcomp->Init.WindowOutput)
00404     {
00405       case COMP_WINDOWOUTPUT_COMP1:
00406         SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
00407         CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
00408         break;
00409
00410       case COMP_WINDOWOUTPUT_COMP2:
00411         CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
00412         SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
00413         break;
00414
00415       case COMP_WINDOWOUTPUT_BOTH:
00416         SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
00417         SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
00418         break;
00419
00420       default: /* COMP_WINDOWOUTPUT_EACH_COMP */
00421         CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
00422         CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
00423         break;
00424     }
00425 #endif /* COMP3 */
00426
00427     /* Delay for COMP scaler bridge voltage stabilization */
00428     /* Apply the delay if voltage scaler bridge is required and not already enabled */
00429     if ((READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)) != 0UL) &&
00430         (comp_voltage_scaler_initialized == 0UL)               )
00431     {
00432       /* Wait loop initialization and execution */
00433       /* Note: Variable divided by 2 to compensate partially              */
00434       /*       CPU processing cycles, scaling in us split to not          */
00435       /*       exceed 32 bits register capacity and handle low frequency. */
00436       wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00437       while(wait_loop_index != 0UL)
00438       {
00439         wait_loop_index--;
00440       }
00441     }
00442
00443     /* Get the EXTI line corresponding to the selected COMP instance */
00444     exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00445
00446     /* Manage EXTI settings */
00447     if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
00448     {
00449       /* Configure EXTI rising edge */
00450       if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
00451       {
00452         LL_EXTI_EnableRisingTrig_0_31(exti_line);
00453       }
00454       else
00455       {
00456         LL_EXTI_DisableRisingTrig_0_31(exti_line);
00457       }
00458
00459       /* Configure EXTI falling edge */
00460       if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
00461       {
00462         LL_EXTI_EnableFallingTrig_0_31(exti_line);
00463       }
00464       else
00465       {
00466         LL_EXTI_DisableFallingTrig_0_31(exti_line);
00467       }
00468
00469       /* Clear COMP EXTI pending bit (if any) */
00470       LL_EXTI_ClearRisingFlag_0_31(exti_line);
00471       LL_EXTI_ClearFallingFlag_0_31(exti_line);
00472
00473       /* Configure EXTI event mode */
00474       if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
00475       {
00476         LL_EXTI_EnableEvent_0_31(exti_line);
00477       }
00478       else
00479       {
00480         LL_EXTI_DisableEvent_0_31(exti_line);
00481       }
00482
00483       /* Configure EXTI interrupt mode */
00484       if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
00485       {
00486         LL_EXTI_EnableIT_0_31(exti_line);
00487       }
00488       else
00489       {
00490         LL_EXTI_DisableIT_0_31(exti_line);
00491       }
00492     }
00493     else
00494     {
00495       /* Disable EXTI event mode */
00496       LL_EXTI_DisableEvent_0_31(exti_line);
00497
00498       /* Disable EXTI interrupt mode */
00499       LL_EXTI_DisableIT_0_31(exti_line);
00500     }
00501
00502     /* Set HAL COMP handle state */
00503     /* Note: Transition from state reset to state ready,                      */
00504     /*       otherwise (coming from state ready or busy) no state update.     */
00505     if (hcomp->State == HAL_COMP_STATE_RESET)
00506     {
00507       hcomp->State = HAL_COMP_STATE_READY;
00508     }
00509   }
00510
00511   return status;
00512 }
00513
00514 /**
00515   * @brief  DeInitialize the COMP peripheral.
00516   * @note   Deinitialization cannot be performed if the COMP configuration is locked.
00517   *         To unlock the configuration, perform a system reset.
00518   * @param  hcomp  COMP handle
00519   * @retval HAL status
00520   */
00521 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
00522 {
00523   HAL_StatusTypeDef status = HAL_OK;
00524
00525   /* Check the COMP handle allocation and lock status */
00526   if(hcomp == NULL)
00527   {
00528     status = HAL_ERROR;
00529   }
00530   else if(__HAL_COMP_IS_LOCKED(hcomp))
00531   {
00532     status = HAL_ERROR;
00533   }
00534   else
00535   {
00536     /* Check the parameter */
00537     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00538
00539     /* Set COMP_CSR register to reset value */
00540     WRITE_REG(hcomp->Instance->CSR, 0x00000000UL);
00541
00542 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00543     if (hcomp->MspDeInitCallback == NULL)
00544     {
00545       hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit  */
00546     }
00547
00548     /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
00549     hcomp->MspDeInitCallback(hcomp);
00550 #else
00551     /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
00552     HAL_COMP_MspDeInit(hcomp);
00553 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00554
00555     /* Set HAL COMP handle state */
00556     hcomp->State = HAL_COMP_STATE_RESET;
00557
00558     /* Release Lock */
00559     __HAL_UNLOCK(hcomp);
00560   }
00561
00562   return status;
00563 }
00564
00565 /**
00566   * @brief  Initialize the COMP MSP.
00567   * @param  hcomp  COMP handle
00568   * @retval None
00569   */
00570 __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
00571 {
00572   /* Prevent unused argument(s) compilation warning */
00573   UNUSED(hcomp);
00574
00575   /* NOTE : This function should not be modified, when the callback is needed,
00576             the HAL_COMP_MspInit could be implemented in the user file
00577    */
00578 }
00579
00580 /**
00581   * @brief  DeInitialize the COMP MSP.
00582   * @param  hcomp  COMP handle
00583   * @retval None
00584   */
00585 __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
00586 {
00587   /* Prevent unused argument(s) compilation warning */
00588   UNUSED(hcomp);
00589
00590   /* NOTE : This function should not be modified, when the callback is needed,
00591             the HAL_COMP_MspDeInit could be implemented in the user file
00592    */
00593 }
00594
00595 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00596 /**
00597   * @brief  Register a User COMP Callback
00598   *         To be used instead of the weak predefined callback
00599   * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
00600   *                the configuration information for the specified COMP.
00601   * @param  CallbackID ID of the callback to be registered
00602   *         This parameter can be one of the following values:
00603   *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
00604   *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
00605   *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
00606   * @param  pCallback pointer to the Callback function
00607   * @retval HAL status
00608   */
00609 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
00610 {
00611   HAL_StatusTypeDef status = HAL_OK;
00612
00613   if (pCallback == NULL)
00614   {
00615     /* Update the error code */
00616     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00617
00618     return HAL_ERROR;
00619   }
00620
00621   if (HAL_COMP_STATE_READY == hcomp->State)
00622   {
00623     switch (CallbackID)
00624     {
00625       case HAL_COMP_TRIGGER_CB_ID :
00626         hcomp->TriggerCallback = pCallback;
00627         break;
00628
00629       case HAL_COMP_MSPINIT_CB_ID :
00630         hcomp->MspInitCallback = pCallback;
00631         break;
00632
00633       case HAL_COMP_MSPDEINIT_CB_ID :
00634         hcomp->MspDeInitCallback = pCallback;
00635         break;
00636
00637       default :
00638         /* Update the error code */
00639         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00640
00641         /* Return error status */
00642         status = HAL_ERROR;
00643         break;
00644     }
00645   }
00646   else if (HAL_COMP_STATE_RESET == hcomp->State)
00647   {
00648     switch (CallbackID)
00649     {
00650       case HAL_COMP_MSPINIT_CB_ID :
00651         hcomp->MspInitCallback = pCallback;
00652         break;
00653
00654       case HAL_COMP_MSPDEINIT_CB_ID :
00655         hcomp->MspDeInitCallback = pCallback;
00656         break;
00657
00658       default :
00659         /* Update the error code */
00660         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00661
00662         /* Return error status */
00663         status = HAL_ERROR;
00664         break;
00665     }
00666   }
00667   else
00668   {
00669     /* Update the error code */
00670     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00671
00672     /* Return error status */
00673     status =  HAL_ERROR;
00674   }
00675
00676   return status;
00677 }
00678
00679 /**
00680   * @brief  Unregister a COMP Callback
00681   *         COMP callback is redirected to the weak predefined callback
00682   * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
00683   *                the configuration information for the specified COMP.
00684   * @param  CallbackID ID of the callback to be unregistered
00685   *         This parameter can be one of the following values:
00686   *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
00687   *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
00688   *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
00689   * @retval HAL status
00690   */
00691 HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
00692 {
00693   HAL_StatusTypeDef status = HAL_OK;
00694
00695   if (HAL_COMP_STATE_READY == hcomp->State)
00696   {
00697     switch (CallbackID)
00698     {
00699       case HAL_COMP_TRIGGER_CB_ID :
00700         hcomp->TriggerCallback = HAL_COMP_TriggerCallback;         /* Legacy weak callback */
00701         break;
00702
00703       case HAL_COMP_MSPINIT_CB_ID :
00704         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
00705         break;
00706
00707       case HAL_COMP_MSPDEINIT_CB_ID :
00708         hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
00709         break;
00710
00711       default :
00712         /* Update the error code */
00713         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00714
00715         /* Return error status */
00716         status =  HAL_ERROR;
00717         break;
00718     }
00719   }
00720   else if (HAL_COMP_STATE_RESET == hcomp->State)
00721   {
00722     switch (CallbackID)
00723     {
00724       case HAL_COMP_MSPINIT_CB_ID :
00725         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
00726         break;
00727
00728       case HAL_COMP_MSPDEINIT_CB_ID :
00729         hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
00730         break;
00731
00732       default :
00733         /* Update the error code */
00734         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00735
00736         /* Return error status */
00737         status =  HAL_ERROR;
00738         break;
00739     }
00740   }
00741   else
00742   {
00743     /* Update the error code */
00744     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00745
00746     /* Return error status */
00747     status =  HAL_ERROR;
00748   }
00749
00750   return status;
00751 }
00752
00753 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00754
00755 /**
00756   * @}
00757   */
00758
00759 /** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
00760   *  @brief   Start-Stop operation functions.
00761   *
00762 @verbatim
00763  ===============================================================================
00764                       ##### IO operation functions #####
00765  ===============================================================================
00766     [..]  This section provides functions allowing to:
00767       (+) Start a comparator instance.
00768       (+) Stop a comparator instance.
00769
00770 @endverbatim
00771   * @{
00772   */
00773
00774 /**
00775   * @brief  Start the comparator.
00776   * @param  hcomp  COMP handle
00777   * @retval HAL status
00778   */
00779 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
00780 {
00781   __IO uint32_t wait_loop_index = 0UL;
00782   HAL_StatusTypeDef status = HAL_OK;
00783
00784   /* Check the COMP handle allocation and lock status */
00785   if(hcomp == NULL)
00786   {
00787     status = HAL_ERROR;
00788   }
00789   else if(__HAL_COMP_IS_LOCKED(hcomp))
00790   {
00791     status = HAL_ERROR;
00792   }
00793   else
00794   {
00795     /* Check the parameter */
00796     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00797
00798     if(hcomp->State == HAL_COMP_STATE_READY)
00799     {
00800       /* Enable the selected comparator */
00801       SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
00802
00803       /* Set HAL COMP handle state */
00804       hcomp->State = HAL_COMP_STATE_BUSY;
00805
00806       /* Delay for COMP startup time */
00807       /* Wait loop initialization and execution */
00808       /* Note: Variable divided by 2 to compensate partially              */
00809       /*       CPU processing cycles, scaling in us split to not          */
00810       /*       exceed 32 bits register capacity and handle low frequency. */
00811       wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
00812       while(wait_loop_index != 0UL)
00813       {
00814         wait_loop_index--;
00815       }
00816     }
00817     else
00818     {
00819       status = HAL_ERROR;
00820     }
00821   }
00822
00823   return status;
00824 }
00825
00826 /**
00827   * @brief  Stop the comparator.
00828   * @param  hcomp  COMP handle
00829   * @retval HAL status
00830   */
00831 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
00832 {
00833   HAL_StatusTypeDef status = HAL_OK;
00834
00835   /* Check the COMP handle allocation and lock status */
00836   if(hcomp == NULL)
00837   {
00838     status = HAL_ERROR;
00839   }
00840   else if(__HAL_COMP_IS_LOCKED(hcomp))
00841   {
00842     status = HAL_ERROR;
00843   }
00844   else
00845   {
00846     /* Check the parameter */
00847     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00848
00849     /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY    */
00850     /* (all states except HAL_COMP_STATE_RESET and except locked status.      */
00851     if(hcomp->State != HAL_COMP_STATE_RESET)
00852     {
00853       /* Disable the selected comparator */
00854       CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
00855
00856       /* Set HAL COMP handle state */
00857       hcomp->State = HAL_COMP_STATE_READY;
00858     }
00859     else
00860     {
00861       status = HAL_ERROR;
00862     }
00863   }
00864
00865   return status;
00866 }
00867
00868 /**
00869   * @brief  Comparator IRQ handler.
00870   * @param  hcomp  COMP handle
00871   * @retval None
00872   */
00873 void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
00874 {
00875   /* Get the EXTI line corresponding to the selected COMP instance */
00876   uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00877   uint32_t comparator_window_mode;
00878   uint32_t comparator_window_exti_lines;
00879
00880 #if defined(COMP3)
00881   if(hcomp->Instance == COMP3)
00882   {
00883     /* Case of window mode with COMP2 and COMP3 */
00884     comparator_window_mode = READ_BIT(COMP23_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00885     comparator_window_exti_lines = (COMP_EXTI_LINE_COMP2 | COMP_EXTI_LINE_COMP3);
00886   }
00887   else
00888   {
00889     comparator_window_mode = READ_BIT(COMP23_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00890     if( (hcomp->Instance == COMP2) && (comparator_window_mode != 0UL))
00891     {
00892       /* Case of window mode with COMP2 and COMP3 */
00893       comparator_window_exti_lines = (COMP_EXTI_LINE_COMP2 | COMP_EXTI_LINE_COMP3);
00894     }
00895     else
00896     {
00897       /* Case of window mode with COMP1 and COMP2 */
00898       comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
00899       comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00900       comparator_window_exti_lines = (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2);
00901     }
00902   }
00903 #else
00904     comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
00905     comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00906     comparator_window_exti_lines = (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2);
00907 #endif /* COMP3 */
00908
00909   /* Check COMP EXTI flag */
00910   if(LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL)
00911   {
00912     /* Check whether comparator is in independent or window mode */
00913     if(comparator_window_mode != 0UL)
00914     {
00915       /* Clear COMP EXTI line pending bit of the pair of comparators          */
00916       /* in window mode.                                                      */
00917       /* Note: Pair of comparators in window mode can both trig IRQ when      */
00918       /*       input voltage is changing from "out of window" area            */
00919       /*       (low or high ) to the other "out of window" area (high or low).*/
00920       /*       Both flags must be cleared to call comparator trigger          */
00921       /*       callback is called once.                                       */
00922       LL_EXTI_ClearRisingFlag_0_31(comparator_window_exti_lines);
00923     }
00924     else
00925     {
00926       /* Clear COMP EXTI line pending bit */
00927       LL_EXTI_ClearRisingFlag_0_31(exti_line);
00928     }
00929
00930     /* COMP trigger user callback */
00931 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00932     hcomp->TriggerCallback(hcomp);
00933 #else
00934     HAL_COMP_TriggerCallback(hcomp);
00935 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00936   }
00937   else if(LL_EXTI_IsActiveFallingFlag_0_31(exti_line) != 0UL)
00938   {
00939     /* Check whether comparator is in independent or window mode */
00940     if(comparator_window_mode != 0UL)
00941     {
00942       /* Clear COMP EXTI line pending bit of the pair of comparators          */
00943       /* in window mode.                                                      */
00944       /* Note: Pair of comparators in window mode can both trig IRQ when      */
00945       /*       input voltage is changing from "out of window" area            */
00946       /*       (low or high ) to the other "out of window" area (high or low).*/
00947       /*       Both flags must be cleared to call comparator trigger          */
00948       /*       callback is called once.                                       */
00949       LL_EXTI_ClearFallingFlag_0_31(comparator_window_exti_lines);
00950     }
00951     else
00952     {
00953       /* Clear COMP EXTI line pending bit */
00954       LL_EXTI_ClearFallingFlag_0_31(exti_line);
00955     }
00956
00957     /* COMP trigger callback */
00958 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00959     hcomp->TriggerCallback(hcomp);
00960 #else
00961     HAL_COMP_TriggerCallback(hcomp);
00962 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00963   }
00964   else
00965   {
00966     /* nothing to do */
00967   }
00968 }
00969
00970 /**
00971   * @}
00972   */
00973
00974 /** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
00975   *  @brief   Management functions.
00976   *
00977 @verbatim
00978  ===============================================================================
00979                       ##### Peripheral Control functions #####
00980  ===============================================================================
00981     [..]
00982     This subsection provides a set of functions allowing to control the comparators.
00983
00984 @endverbatim
00985   * @{
00986   */
00987
00988 /**
00989   * @brief  Lock the selected comparator configuration.
00990   * @note   A system reset is required to unlock the comparator configuration.
00991   * @note   Locking the comparator from reset state is possible
00992   *         if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
00993   * @param  hcomp  COMP handle
00994   * @retval HAL status
00995   */
00996 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
00997 {
00998   HAL_StatusTypeDef status = HAL_OK;
00999
01000   /* Check the COMP handle allocation and lock status */
01001   if(hcomp == NULL)
01002   {
01003     status = HAL_ERROR;
01004   }
01005   else if(__HAL_COMP_IS_LOCKED(hcomp))
01006   {
01007     status = HAL_ERROR;
01008   }
01009   else
01010   {
01011     /* Check the parameter */
01012     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01013
01014     /* Set HAL COMP handle state */
01015     switch(hcomp->State)
01016     {
01017       case HAL_COMP_STATE_RESET:
01018         hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
01019         break;
01020       case HAL_COMP_STATE_READY:
01021         hcomp->State = HAL_COMP_STATE_READY_LOCKED;
01022         break;
01023       default: /* HAL_COMP_STATE_BUSY */
01024         hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
01025         break;
01026     }
01027   }
01028
01029   if(status == HAL_OK)
01030   {
01031     /* Set the lock bit corresponding to selected comparator */
01032     __HAL_COMP_LOCK(hcomp);
01033   }
01034
01035   return status;
01036 }
01037
01038 /**
01039   * @brief  Return the output level (high or low) of the selected comparator.
01040   *         The output level depends on the selected polarity.
01041   *         If the polarity is not inverted:
01042   *           - Comparator output is low when the input plus is at a lower
01043   *             voltage than the input minus
01044   *           - Comparator output is high when the input plus is at a higher
01045   *             voltage than the input minus
01046   *         If the polarity is inverted:
01047   *           - Comparator output is high when the input plus is at a lower
01048   *             voltage than the input minus
01049   *           - Comparator output is low when the input plus is at a higher
01050   *             voltage than the input minus
01051   * @param  hcomp  COMP handle
01052   * @retval Returns the selected comparator output level:
01053   *         @arg COMP_OUTPUT_LEVEL_LOW
01054   *         @arg COMP_OUTPUT_LEVEL_HIGH
01055   *
01056   */
01057 uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
01058 {
01059   /* Check the parameter */
01060   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01061
01062   return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)
01063                     >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
01064 }
01065
01066 /**
01067   * @brief  Comparator trigger callback.
01068   * @param  hcomp  COMP handle
01069   * @retval None
01070   */
01071 __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
01072 {
01073   /* Prevent unused argument(s) compilation warning */
01074   UNUSED(hcomp);
01075
01076   /* NOTE : This function should not be modified, when the callback is needed,
01077             the HAL_COMP_TriggerCallback should be implemented in the user file
01078    */
01079 }
01080
01081
01082 /**
01083   * @}
01084   */
01085
01086 /** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
01087   *  @brief   Peripheral State functions.
01088   *
01089 @verbatim
01090  ===============================================================================
01091                       ##### Peripheral State functions #####
01092  ===============================================================================
01093     [..]
01094     This subsection permit to get in run-time the status of the peripheral.
01095
01096 @endverbatim
01097   * @{
01098   */
01099
01100 /**
01101   * @brief  Return the COMP handle state.
01102   * @param  hcomp  COMP handle
01103   * @retval HAL state
01104   */
01105 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
01106 {
01107   /* Check the COMP handle allocation */
01108   if(hcomp == NULL)
01109   {
01110     return HAL_COMP_STATE_RESET;
01111   }
01112
01113   /* Check the parameter */
01114   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01115
01116   /* Return HAL COMP handle state */
01117   return hcomp->State;
01118 }
01119
01120 /**
01121   * @brief  Return the COMP error code.
01122   * @param hcomp COMP handle
01123   * @retval COMP error code
01124   */
01125 uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
01126 {
01127   /* Check the parameters */
01128   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
01129
01130   return hcomp->ErrorCode;
01131 }
01132
01133 /**
01134   * @}
01135   */
01136
01137 /**
01138   * @}
01139   */
01140
01141 /**
01142   * @}
01143   */
01144
01145 #endif /* COMP1 || COMP2 */
01146
01147 #endif /* HAL_COMP_MODULE_ENABLED */
01148
01149 /**
01150   * @}
01151   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_comp.h Source File

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stm32g0xx_hal_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_COMP_H
00021 #define STM32G0xx_HAL_COMP_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029 #include "stm32g0xx_ll_exti.h"
00030
00031 /** @addtogroup STM32G0xx_HAL_Driver
00032   * @{
00033   */
00034 #if defined (COMP1) || defined (COMP2)
00035
00036 /** @addtogroup COMP
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup COMP_Exported_Types COMP Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  COMP Init structure definition
00047   */
00048 typedef struct
00049 {
00050
00051   uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
00052                                     (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00053                                     Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode, except for window mode with COMP2 and COMP3 (for devices featuring COMP3): it must be set from COMP3 instance.
00054                                     This parameter can be a value of @ref COMP_WindowMode */
00055
00056   uint32_t WindowOutput;       /*!< Set window mode output.
00057                                     This parameter can be a value of @ref COMP_WindowOutput */
00058
00059   uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
00060                                     Note: For the characteristics of comparator power modes
00061                                           (propagation delay and power consumption), refer to device datasheet.
00062                                     This parameter can be a value of @ref COMP_PowerMode */
00063
00064   uint32_t InputPlus;          /*!< Set comparator input plus (non-inverting input).
00065                                     This parameter can be a value of @ref COMP_InputPlus */
00066
00067   uint32_t InputMinus;         /*!< Set comparator input minus (inverting input).
00068                                     This parameter can be a value of @ref COMP_InputMinus */
00069
00070   uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
00071                                     This parameter can be a value of @ref COMP_Hysteresis */
00072
00073   uint32_t OutputPol;          /*!< Set comparator output polarity.
00074                                     This parameter can be a value of @ref COMP_OutputPolarity */
00075
00076   uint32_t BlankingSrce;       /*!< Set comparator blanking source.
00077                                     This parameter can be a value of @ref COMP_BlankingSrce */
00078
00079   uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
00080                                     This parameter can be a value of @ref COMP_EXTI_TriggerMode */
00081
00082 } COMP_InitTypeDef;
00083
00084 /**
00085   * @brief  HAL COMP state machine: HAL COMP states definition
00086   */
00087 #define COMP_STATE_BITFIELD_LOCK  (0x10U)
00088 typedef enum
00089 {
00090   HAL_COMP_STATE_RESET             = 0x00U,                                             /*!< COMP not yet initialized                             */
00091   HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
00092   HAL_COMP_STATE_READY             = 0x01U,                                             /*!< COMP initialized and ready for use                   */
00093   HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
00094   HAL_COMP_STATE_BUSY              = 0x02U,                                             /*!< COMP is running                                      */
00095   HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
00096 } HAL_COMP_StateTypeDef;
00097
00098 /**
00099   * @brief  COMP Handle Structure definition
00100   */
00101 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00102 typedef struct __COMP_HandleTypeDef
00103 #else
00104 typedef struct
00105 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00106 {
00107   COMP_TypeDef       *Instance;       /*!< Register base address    */
00108   COMP_InitTypeDef   Init;            /*!< COMP required parameters */
00109   HAL_LockTypeDef    Lock;            /*!< Locking object           */
00110   __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
00111   __IO uint32_t      ErrorCode;       /*!< COMP error code */
00112 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00113   void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
00114   void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
00115   void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
00116 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00117 } COMP_HandleTypeDef;
00118
00119 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00120 /**
00121   * @brief  HAL COMP Callback ID enumeration definition
00122   */
00123 typedef enum
00124 {
00125   HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
00126   HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
00127   HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
00128 } HAL_COMP_CallbackIDTypeDef;
00129
00130 /**
00131   * @brief  HAL COMP Callback pointer definition
00132   */
00133 typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
00134
00135 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00136
00137 /**
00138   * @}
00139   */
00140
00141 /* Exported constants --------------------------------------------------------*/
00142 /** @defgroup COMP_Exported_Constants COMP Exported Constants
00143   * @{
00144   */
00145
00146 /** @defgroup COMP_Error_Code COMP Error Code
00147   * @{
00148   */
00149 #define HAL_COMP_ERROR_NONE             (0x00UL)  /*!< No error */
00150 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00151 #define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)  /*!< Invalid Callback error */
00152 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup COMP_WindowMode COMP Window Mode
00158   * @{
00159   */
00160 #define COMP_WINDOWMODE_DISABLE                 (0x00000000UL)         /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
00161 #define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00162 #define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). If used from COMP3 instance (when available), comparators instances pair COMP2 and COMP3 have their input plus connected together, the common input is COMP2 input plus (COMP3 input plus is no more accessible). */
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup COMP_WindowOutput COMP Window output
00168   * @{
00169   */
00170 #define COMP_WINDOWOUTPUT_EACH_COMP             (0x00000000UL)                            /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window.  */
00171 #define COMP_WINDOWOUTPUT_COMP1                 (COMP_CSR_WINOUT)                         /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window).
00172                                                                                                Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/
00173 #define COMP_WINDOWOUTPUT_COMP2                 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window).
00174                                                                                                Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/
00175 #if defined(COMP3)
00176 #define COMP_WINDOWOUTPUT_COMP3                 (COMP_CSR_WINOUT)                         /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
00177 #endif /* COMP3 */
00178 #define COMP_WINDOWOUTPUT_BOTH                  (0x00000001UL)                            /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup COMP_PowerMode COMP power mode
00184   * @{
00185   */
00186 /* Note: For the characteristics of comparator power modes                    */
00187 /*       (propagation delay and power consumption),                           */
00188 /*       refer to device datasheet.                                           */
00189 #define COMP_POWERMODE_HIGHSPEED       (0x00000000UL)         /*!< High Speed */
00190 #define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_PWRMODE_0)   /*!< Medium Speed */
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
00196   * @{
00197   */
00198 #define COMP_INPUT_PLUS_IO1            (0x00000000UL)         /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2, pin PB0 for COMP3 (for devices featuring COMP3 instance)) */
00199 #define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL_0)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2, pin PC1 for COMP3 (for devices featuring COMP3 instance)) */
00200 #define COMP_INPUT_PLUS_IO3            (COMP_CSR_INPSEL_1)    /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2, pin PE7 for COMP3 (for devices featuring COMP3 instance)) */
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup COMP_InputMinus COMP input minus (inverting input)
00206   * @{
00207   */
00208 #define COMP_INPUT_MINUS_1_4VREFINT    (0x00000000UL)                                                                  /*!< Comparator input minus connected to 1/4 VrefInt  */
00209 #define COMP_INPUT_MINUS_1_2VREFINT    (                                                            COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt  */
00210 #define COMP_INPUT_MINUS_3_4VREFINT    (                                        COMP_CSR_INMSEL_1                    ) /*!< Comparator input minus connected to 3/4 VrefInt  */
00211 #define COMP_INPUT_MINUS_VREFINT       (                                        COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */
00212 #define COMP_INPUT_MINUS_DAC1_CH1      (                    COMP_CSR_INMSEL_2                                        ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
00213 #define COMP_INPUT_MINUS_DAC1_CH2      (                    COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
00214 #define COMP_INPUT_MINUS_IO1           (                    COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2, pin PB2 for COMP3 (for devices featuring COMP3 instance)) */
00215 #define COMP_INPUT_MINUS_IO2           (                    COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2, pin PC0 for COMP3 (for devices featuring COMP3 instance)) */
00216 #define COMP_INPUT_MINUS_IO3           (COMP_CSR_INMSEL_3                                                            ) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2, pin PE8 for COMP3 (for devices featuring COMP3 instance)) */
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup COMP_Hysteresis COMP hysteresis
00222   * @{
00223   */
00224 #define COMP_HYSTERESIS_NONE           (0x00000000UL)                       /*!< No hysteresis */
00225 #define COMP_HYSTERESIS_LOW            (                  COMP_CSR_HYST_0)  /*!< Hysteresis level low */
00226 #define COMP_HYSTERESIS_MEDIUM         (COMP_CSR_HYST_1                  )  /*!< Hysteresis level medium */
00227 #define COMP_HYSTERESIS_HIGH           (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)  /*!< Hysteresis level high */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup COMP_OutputPolarity COMP output Polarity
00233   * @{
00234   */
00235 #define COMP_OUTPUTPOL_NONINVERTED     (0x00000000UL)         /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
00236 #define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup COMP_BlankingSrce  COMP blanking source
00242   * @{
00243   */
00244 #define COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
00245 /* Note: Output blanking source common to all COMP instances */
00246 #define COMP_BLANKINGSRC_TIM1_OC4        (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC4 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00247 #define COMP_BLANKINGSRC_TIM1_OC5        (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00248 #define COMP_BLANKINGSRC_TIM2_OC3        (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00249 #define COMP_BLANKINGSRC_TIM3_OC3        (COMP_CSR_BLANKING_3)   /*!< Comparator output blanking source TIM3 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00250 #define COMP_BLANKINGSRC_TIM15_OC2       (COMP_CSR_BLANKING_4)   /*!< Comparator output blanking source TIM15 OC2 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup COMP_OutputLevel COMP Output Level
00256   * @{
00257   */
00258 /* Note: Comparator output level values are fixed to "0" and "1",             */
00259 /* corresponding COMP register bit is managed by HAL function to match        */
00260 /* with these values (independently of bit position in register).             */
00261
00262 /* When output polarity is not inverted, comparator output is low when
00263    the input plus is at a lower voltage than the input minus */
00264 #define COMP_OUTPUT_LEVEL_LOW              (0x00000000UL)
00265 /* When output polarity is not inverted, comparator output is high when
00266    the input plus is at a higher voltage than the input minus */
00267 #define COMP_OUTPUT_LEVEL_HIGH             (0x00000001UL)
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
00273   * @{
00274   */
00275 #define COMP_TRIGGERMODE_NONE                 (0x00000000UL)                                            /*!< Comparator output triggering no External Interrupt Line */
00276 #define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
00277 #define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
00278 #define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
00279 #define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
00280 #define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
00281 #define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
00282 /**
00283   * @}
00284   */
00285
00286 /**
00287   * @}
00288   */
00289
00290 /* Exported macro ------------------------------------------------------------*/
00291 /** @defgroup COMP_Exported_Macros COMP Exported Macros
00292   * @{
00293   */
00294
00295 /** @defgroup COMP_Handle_Management  COMP Handle Management
00296   * @{
00297   */
00298
00299 /** @brief  Reset COMP handle state.
00300   * @param  __HANDLE__  COMP handle
00301   * @retval None
00302   */
00303 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00304 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \
00305                                                       (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
00306                                                       (__HANDLE__)->MspInitCallback = NULL;            \
00307                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
00308                                                     } while(0)
00309 #else
00310 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
00311 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00312
00313 /**
00314   * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
00315   * @param __HANDLE__ COMP handle
00316   * @retval None
00317   */
00318 #define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
00319
00320 /**
00321   * @brief  Enable the specified comparator.
00322   * @param  __HANDLE__  COMP handle
00323   * @retval None
00324   */
00325 #define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
00326
00327 /**
00328   * @brief  Disable the specified comparator.
00329   * @param  __HANDLE__  COMP handle
00330   * @retval None
00331   */
00332 #define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
00333
00334 /**
00335   * @brief  Lock the specified comparator configuration.
00336   * @note   Using this macro induce HAL COMP handle state machine being no
00337   *         more in line with COMP instance state.
00338   *         To keep HAL COMP handle state machine updated, it is recommended
00339   *         to use function "HAL_COMP_Lock')".
00340   * @param  __HANDLE__  COMP handle
00341   * @retval None
00342   */
00343 #define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
00344
00345 /**
00346   * @brief  Check whether the specified comparator is locked.
00347   * @param  __HANDLE__  COMP handle
00348   * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
00349   */
00350 #define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
00351
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup COMP_Exti_Management  COMP external interrupt line management
00357   * @{
00358   */
00359
00360 /**
00361   * @brief  Enable the COMP1 EXTI line rising edge trigger.
00362   * @retval None
00363   */
00364 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
00365
00366 /**
00367   * @brief  Disable the COMP1 EXTI line rising edge trigger.
00368   * @retval None
00369   */
00370 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
00371
00372 /**
00373   * @brief  Enable the COMP1 EXTI line falling edge trigger.
00374   * @retval None
00375   */
00376 #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
00377
00378 /**
00379   * @brief  Disable the COMP1 EXTI line falling edge trigger.
00380   * @retval None
00381   */
00382 #define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
00383
00384 /**
00385   * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
00386   * @retval None
00387   */
00388 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00389                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00390                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00391                                                              } while(0)
00392
00393 /**
00394   * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
00395   * @retval None
00396   */
00397 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00398                                                                LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00399                                                                LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00400                                                              } while(0)
00401
00402 /**
00403   * @brief  Enable the COMP1 EXTI line in interrupt mode.
00404   * @retval None
00405   */
00406 #define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
00407
00408 /**
00409   * @brief  Disable the COMP1 EXTI line in interrupt mode.
00410   * @retval None
00411   */
00412 #define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
00413
00414 /**
00415   * @brief  Generate a software interrupt on the COMP1 EXTI line.
00416   * @retval None
00417   */
00418 #define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
00419
00420 /**
00421   * @brief  Enable the COMP1 EXTI line in event mode.
00422   * @retval None
00423   */
00424 #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
00425
00426 /**
00427   * @brief  Disable the COMP1 EXTI line in event mode.
00428   * @retval None
00429   */
00430 #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
00431
00432 /**
00433   * @brief  Check whether the COMP1 EXTI line rising flag is set.
00434   * @retval RESET or SET
00435   */
00436 #define __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG()       LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
00437
00438 /**
00439   * @brief  Clear the COMP1 EXTI rising flag.
00440   * @retval None
00441   */
00442 #define __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG()     LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
00443
00444 /**
00445   * @brief  Check whether the COMP1 EXTI line falling flag is set.
00446   * @retval RESET or SET
00447   */
00448 #define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG()      LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
00449
00450 /**
00451   * @brief  Clear the COMP1 EXTI falling flag.
00452   * @retval None
00453   */
00454 #define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG()    LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
00455
00456 /**
00457   * @brief  Enable the COMP2 EXTI line rising edge trigger.
00458   * @retval None
00459   */
00460 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
00461
00462 /**
00463   * @brief  Disable the COMP2 EXTI line rising edge trigger.
00464   * @retval None
00465   */
00466 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
00467
00468 /**
00469   * @brief  Enable the COMP2 EXTI line falling edge trigger.
00470   * @retval None
00471   */
00472 #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
00473
00474 /**
00475   * @brief  Disable the COMP2 EXTI line falling edge trigger.
00476   * @retval None
00477   */
00478 #define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
00479
00480 /**
00481   * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
00482   * @retval None
00483   */
00484 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00485                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
00486                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
00487                                                              } while(0)
00488
00489 /**
00490   * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
00491   * @retval None
00492   */
00493 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00494                                                                LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
00495                                                                LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
00496                                                              } while(0)
00497
00498 /**
00499   * @brief  Enable the COMP2 EXTI line in interrupt mode.
00500   * @retval None
00501   */
00502 #define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
00503
00504 /**
00505   * @brief  Disable the COMP2 EXTI line in interrupt mode.
00506   * @retval None
00507   */
00508 #define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
00509
00510 /**
00511   * @brief  Generate a software interrupt on the COMP2 EXTI line.
00512   * @retval None
00513   */
00514 #define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
00515
00516 /**
00517   * @brief  Enable the COMP2 EXTI line in event mode.
00518   * @retval None
00519   */
00520 #define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
00521
00522 /**
00523   * @brief  Disable the COMP2 EXTI line in event mode.
00524   * @retval None
00525   */
00526 #define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
00527
00528 /**
00529   * @brief  Check whether the COMP2 EXTI line rising flag is set.
00530   * @retval RESET or SET
00531   */
00532 #define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG()       LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
00533
00534 /**
00535   * @brief  Clear the COMP2 EXTI rising flag.
00536   * @retval None
00537   */
00538 #define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG()     LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
00539
00540 /**
00541   * @brief  Check whether the COMP2 EXTI line falling flag is set.
00542   * @retval RESET or SET
00543   */
00544 #define __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG()      LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
00545
00546 /**
00547   * @brief  Clear the COMP2 EXTI falling flag.
00548   * @retval None
00549   */
00550 #define __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG()    LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
00551
00552 /**
00553   * @brief  Enable the COMP3 EXTI line rising edge trigger.
00554   * @retval None
00555   */
00556 #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
00557
00558 /**
00559   * @brief  Disable the COMP3 EXTI line rising edge trigger.
00560   * @retval None
00561   */
00562 #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
00563
00564 /**
00565   * @brief  Enable the COMP3 EXTI line falling edge trigger.
00566   * @retval None
00567   */
00568 #define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
00569
00570 /**
00571   * @brief  Disable the COMP3 EXTI line falling edge trigger.
00572   * @retval None
00573   */
00574 #define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
00575
00576 /**
00577   * @brief  Enable the COMP3 EXTI line rising & falling edge trigger.
00578   * @retval None
00579   */
00580 #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00581                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
00582                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
00583                                                              } while(0)
00584
00585 /**
00586   * @brief  Disable the COMP3 EXTI line rising & falling edge trigger.
00587   * @retval None
00588   */
00589 #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00590                                                                LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
00591                                                                LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
00592                                                              } while(0)
00593
00594 /**
00595   * @brief  Enable the COMP3 EXTI line in interrupt mode.
00596   * @retval None
00597   */
00598 #define __HAL_COMP_COMP3_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
00599
00600 /**
00601   * @brief  Disable the COMP3 EXTI line in interrupt mode.
00602   * @retval None
00603   */
00604 #define __HAL_COMP_COMP3_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
00605
00606 /**
00607   * @brief  Generate a software interrupt on the COMP3 EXTI line.
00608   * @retval None
00609   */
00610 #define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
00611
00612 /**
00613   * @brief  Enable the COMP3 EXTI line in event mode.
00614   * @retval None
00615   */
00616 #define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
00617
00618 /**
00619   * @brief  Disable the COMP3 EXTI line in event mode.
00620   * @retval None
00621   */
00622 #define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
00623
00624 /**
00625   * @brief  Check whether the COMP3 EXTI line rising flag is set.
00626   * @retval RESET or SET
00627   */
00628 #define __HAL_COMP_COMP3_EXTI_GET_RISING_FLAG()       LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP3)
00629
00630 /**
00631   * @brief  Clear the COMP3 EXTI rising flag.
00632   * @retval None
00633   */
00634 #define __HAL_COMP_COMP3_EXTI_CLEAR_RISING_FLAG()     LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP3)
00635
00636 /**
00637   * @brief  Check whether the COMP3 EXTI line falling flag is set.
00638   * @retval RESET or SET
00639   */
00640 #define __HAL_COMP_COMP3_EXTI_GET_FALLING_FLAG()      LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP3)
00641
00642 /**
00643   * @brief  Clear the COMP3 EXTI falling flag.
00644   * @retval None
00645   */
00646 #define __HAL_COMP_COMP3_EXTI_CLEAR_FALLING_FLAG()    LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP3)
00647
00648 /**
00649   * @}
00650   */
00651
00652 /**
00653   * @}
00654   */
00655
00656
00657 /* Private types -------------------------------------------------------------*/
00658 /* Private constants ---------------------------------------------------------*/
00659 /** @defgroup COMP_Private_Constants COMP Private Constants
00660   * @{
00661   */
00662
00663 /** @defgroup COMP_WindowMode_Instance_Differentiator COMP window mode instance differentiator
00664   * @{
00665   */
00666 #define COMP_WINDOWMODE_COMP2          0x00001000U       /*!< COMP window mode using common input of COMP instance: COMP2 */
00667 /**
00668   * @}
00669   */
00670
00671 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00672   * @{
00673   */
00674 #define COMP_EXTI_LINE_COMP1           (EXTI_IMR1_IM17)  /*!< EXTI line 17 connected to COMP1 output */
00675 #define COMP_EXTI_LINE_COMP2           (EXTI_IMR1_IM18)  /*!< EXTI line 18 connected to COMP2 output */
00676 #if defined(COMP3)
00677 #define COMP_EXTI_LINE_COMP3           (EXTI_IMR1_IM20)  /*!< EXTI line 20 connected to COMP3 output */
00678 #endif /* COMP3 */
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00684   * @{
00685   */
00686 #define COMP_EXTI_IT                        (0x00000001UL)  /*!< EXTI line event with interruption */
00687 #define COMP_EXTI_EVENT                     (0x00000002UL)  /*!< EXTI line event only (without interruption) */
00688 #define COMP_EXTI_RISING                    (0x00000010UL)  /*!< EXTI line event on rising edge */
00689 #define COMP_EXTI_FALLING                   (0x00000020UL)  /*!< EXTI line event on falling edge */
00690 /**
00691   * @}
00692   */
00693
00694 /**
00695   * @}
00696   */
00697
00698 /* Private macros ------------------------------------------------------------*/
00699 /** @defgroup COMP_Private_Macros COMP Private Macros
00700   * @{
00701   */
00702
00703 /** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
00704   * @{
00705   */
00706 /**
00707   * @brief  Get the specified EXTI line for a comparator instance.
00708   * @param  __INSTANCE__  specifies the COMP instance.
00709   * @retval value of @ref COMP_ExtiLine
00710   */
00711 #if defined(COMP3)
00712 #define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
00713                                              :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
00714                                              : COMP_EXTI_LINE_COMP3)
00715 #else
00716 #define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
00717                                              : COMP_EXTI_LINE_COMP2)
00718 #endif /* COMP3 */
00719 /**
00720   * @}
00721   */
00722
00723 /** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
00724   * @{
00725   */
00726 #if defined(COMP3)
00727 #define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \
00728 (((__INSTANCE__) == COMP3) \
00729   ? \
00730   (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                ||  \
00731    ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)  ) \
00732   :\
00733   (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                ||  \
00734    ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)||  \
00735    ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)  ) \
00736 )
00737 #else
00738 #define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \
00739 (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
00740  ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \
00741  ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)  )
00742 #endif /* COMP3 */
00743
00744 #define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \
00745                                                 ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1)     || \
00746                                                 ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP2)     || \
00747                                                 ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH)        )
00748
00749 #define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
00750                                              ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)    )
00751
00752 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
00753                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
00754                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
00755
00756 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
00757                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
00758                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
00759                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
00760                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
00761                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
00762                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
00763                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
00764                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3))
00765
00766 #define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
00767                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
00768                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
00769                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
00770
00771 #define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
00772                                              ((__POL__) == COMP_OUTPUTPOL_INVERTED))
00773
00774 #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)                    \
00775   (   ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)               \
00776    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC4)           \
00777    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)           \
00778    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)           \
00779    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3)           \
00780    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2)          \
00781   )
00782
00783 /* Note: Output blanking source common to all COMP instances */
00784 /*       Macro kept for compatibility with other STM32 series */
00785 #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
00786    (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
00787
00788
00789 #define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
00790                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
00791                                              ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
00792                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
00793                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
00794                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
00795                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
00796
00797 #define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
00798                                                 ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
00799
00800 /**
00801   * @}
00802   */
00803
00804 /**
00805   * @}
00806   */
00807
00808
00809 /* Exported functions --------------------------------------------------------*/
00810 /** @addtogroup COMP_Exported_Functions
00811   * @{
00812   */
00813
00814 /** @addtogroup COMP_Exported_Functions_Group1
00815   * @{
00816   */
00817
00818 /* Initialization and de-initialization functions  **********************************/
00819 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
00820 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
00821 void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
00822 void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
00823
00824 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00825 /* Callbacks Register/UnRegister functions  ***********************************/
00826 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
00827                                             pCOMP_CallbackTypeDef pCallback);
00828 HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
00829 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00830 /**
00831   * @}
00832   */
00833
00834 /* IO operation functions  *****************************************************/
00835 /** @addtogroup COMP_Exported_Functions_Group2
00836   * @{
00837   */
00838 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
00839 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
00840 void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
00841 /**
00842   * @}
00843   */
00844
00845 /* Peripheral Control functions  ************************************************/
00846 /** @addtogroup COMP_Exported_Functions_Group3
00847   * @{
00848   */
00849 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
00850 uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
00851 /* Callback in interrupt mode */
00852 void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
00853 /**
00854   * @}
00855   */
00856
00857 /* Peripheral State functions  **************************************************/
00858 /** @addtogroup COMP_Exported_Functions_Group4
00859   * @{
00860   */
00861 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
00862 uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
00863 /**
00864   * @}
00865   */
00866
00867 /**
00868   * @}
00869   */
00870
00871 /**
00872   * @}
00873   */
00874 #endif /* COMP1 || COMP2 */
00875 /**
00876   * @}
00877   */
00878
00879 #ifdef __cplusplus
00880 }
00881 #endif
00882
00883 #endif /* STM32G0xx_HAL_COMP_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_conf.h Source File

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stm32g0xx_hal_conf.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_conf.h
00004   * @author  MCD Application Team
00005   * @brief   HAL configuration template file.
00006   *          This file should be copied to the application folder and renamed
00007   *          to stm32g0xx_hal_conf.h.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * Copyright (c) 2018 STMicroelectronics.
00012   * All rights reserved.
00013   *
00014   * This software is licensed under terms that can be found in the LICENSE file
00015   * in the root directory of this software component.
00016   * If no LICENSE file comes with this software, it is provided AS-IS.
00017   *
00018   ******************************************************************************
00019   */
00020
00021 /* Define to prevent recursive inclusion -------------------------------------*/
00022 #ifndef STM32G0xx_HAL_CONF_H
00023 #define STM32G0xx_HAL_CONF_H
00024
00025 #ifdef __cplusplus
00026 extern "C" {
00027 #endif
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031
00032 /* ########################## Module Selection ############################## */
00033 /**
00034   * @brief This is the list of modules to be used in the HAL driver
00035   */
00036 #define HAL_MODULE_ENABLED
00037 #define HAL_ADC_MODULE_ENABLED
00038 #define HAL_CEC_MODULE_ENABLED
00039 #define HAL_COMP_MODULE_ENABLED
00040 #define HAL_CORTEX_MODULE_ENABLED
00041 #define HAL_CRC_MODULE_ENABLED
00042 #define HAL_CRYP_MODULE_ENABLED
00043 #define HAL_DAC_MODULE_ENABLED
00044 #define HAL_DMA_MODULE_ENABLED
00045 #define HAL_EXTI_MODULE_ENABLED
00046 #define HAL_FLASH_MODULE_ENABLED
00047 #define HAL_FDCAN_MODULE_ENABLED
00048 #define HAL_GPIO_MODULE_ENABLED
00049 #define HAL_I2C_MODULE_ENABLED
00050 #define HAL_I2S_MODULE_ENABLED
00051 #define HAL_IRDA_MODULE_ENABLED
00052 #define HAL_IWDG_MODULE_ENABLED
00053 #define HAL_LPTIM_MODULE_ENABLED
00054 #define HAL_HCD_MODULE_ENABLED
00055 #define HAL_PCD_MODULE_ENABLED
00056 #define HAL_PWR_MODULE_ENABLED
00057 #define HAL_RCC_MODULE_ENABLED
00058 #define HAL_RNG_MODULE_ENABLED
00059 #define HAL_RTC_MODULE_ENABLED
00060 #define HAL_SMARTCARD_MODULE_ENABLED
00061 #define HAL_SMBUS_MODULE_ENABLED
00062 #define HAL_SPI_MODULE_ENABLED
00063 #define HAL_TIM_MODULE_ENABLED
00064 #define HAL_UART_MODULE_ENABLED
00065 #define HAL_USART_MODULE_ENABLED
00066 #define HAL_WWDG_MODULE_ENABLED
00067
00068 /* ########################## Register Callbacks selection ############################## */
00069 /**
00070   * @brief This is the list of modules where register callback can be used
00071   */
00072 #define USE_HAL_ADC_REGISTER_CALLBACKS 1u
00073 #define USE_HAL_CEC_REGISTER_CALLBACKS 1u
00074 #define USE_HAL_COMP_REGISTER_CALLBACKS 1u
00075 #define USE_HAL_CRYP_REGISTER_CALLBACKS 1u
00076 #define USE_HAL_DAC_REGISTER_CALLBACKS 1u
00077 #define USE_HAL_FDCAN_REGISTER_CALLBACKS 1u
00078 #define USE_HAL_I2C_REGISTER_CALLBACKS 1u
00079 #define USE_HAL_I2S_REGISTER_CALLBACKS 1u
00080 #define USE_HAL_IRDA_REGISTER_CALLBACKS 1u
00081 #define USE_HAL_LPTIM_REGISTER_CALLBACKS 1u
00082 #define USE_HAL_HCD_REGISTER_CALLBACKS 1u
00083 #define USE_HAL_PCD_REGISTER_CALLBACKS 1u
00084 #define USE_HAL_RNG_REGISTER_CALLBACKS 1u
00085 #define USE_HAL_RTC_REGISTER_CALLBACKS 1u
00086 #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1u
00087 #define USE_HAL_SMBUS_REGISTER_CALLBACKS 1u
00088 #define USE_HAL_SPI_REGISTER_CALLBACKS 1u
00089 #define USE_HAL_TIM_REGISTER_CALLBACKS 1u
00090 #define USE_HAL_UART_REGISTER_CALLBACKS 1u
00091 #define USE_HAL_USART_REGISTER_CALLBACKS 1u
00092 #define USE_HAL_WWDG_REGISTER_CALLBACKS 1u
00093
00094 /* ########################## Oscillator Values adaptation ####################*/
00095 /**
00096   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00097   *        This value is used by the RCC HAL module to compute the system frequency
00098   *        (when HSE is used as system clock source, directly or through the PLL).
00099   */
00100 #if !defined  (HSE_VALUE)
00101 #define HSE_VALUE    (8000000UL)            /*!< Value of the External oscillator in Hz */
00102 #endif /* HSE_VALUE */
00103
00104 #if !defined  (HSE_STARTUP_TIMEOUT)
00105 #define HSE_STARTUP_TIMEOUT    (100UL)      /*!< Time out for HSE start up, in ms */
00106 #endif /* HSE_STARTUP_TIMEOUT */
00107
00108 /**
00109   * @brief Internal High Speed oscillator (HSI) value.
00110   *        This value is used by the RCC HAL module to compute the system frequency
00111   *        (when HSI is used as system clock source, directly or through the PLL).
00112   */
00113 #if !defined  (HSI_VALUE)
00114 #define HSI_VALUE    (16000000UL)           /*!< Value of the Internal oscillator in Hz*/
00115 #endif /* HSI_VALUE */
00116
00117 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00118 /**
00119   * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
00120   *        This internal oscillator is mainly dedicated to provide a high precision clock to
00121   *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
00122   *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
00123   *        which is subject to manufacturing process variations.
00124   */
00125 #if !defined  (HSI48_VALUE)
00126   #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
00127                                                The real value my vary depending on manufacturing process variations.*/
00128 #endif /* HSI48_VALUE */
00129 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00130
00131 /**
00132   * @brief Internal Low Speed oscillator (LSI) value.
00133   */
00134 #if !defined  (LSI_VALUE)
00135 #define LSI_VALUE  (32000UL)                /*!< LSI Typical Value in Hz*/
00136 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
00137 The real value may vary depending on the variations
00138 in voltage and temperature.*/
00139 /**
00140   * @brief External Low Speed oscillator (LSE) value.
00141   *        This value is used by the UART, RTC HAL module to compute the system frequency
00142   */
00143 #if !defined  (LSE_VALUE)
00144 #define LSE_VALUE    (32768UL)              /*!< Value of the External oscillator in Hz*/
00145 #endif /* LSE_VALUE */
00146
00147 #if !defined (LSE_STARTUP_TIMEOUT)
00148 #define LSE_STARTUP_TIMEOUT    (5000UL)     /*!< Time out for LSE start up, in ms */
00149 #endif /* LSE_STARTUP_TIMEOUT */
00150
00151 /**
00152   * @brief External clock source for I2S1 peripheral
00153   *        This value is used by the RCC HAL module to compute the I2S1 clock source
00154   *        frequency.
00155   */
00156 #if !defined  (EXTERNAL_I2S1_CLOCK_VALUE)
00157 #define EXTERNAL_I2S1_CLOCK_VALUE    (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
00158 #endif /* EXTERNAL_I2S1_CLOCK_VALUE */
00159
00160 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00161 /**
00162   * @brief External clock source for I2S2 peripheral
00163   *        This value is used by the RCC HAL module to compute the I2S2 clock source
00164   *        frequency.
00165   */
00166 #if !defined  (EXTERNAL_I2S2_CLOCK_VALUE)
00167   #define EXTERNAL_I2S2_CLOCK_VALUE    48000U /*!< Value of the I2S2 External clock source in Hz*/
00168 #endif /* EXTERNAL_I2S2_CLOCK_VALUE */
00169 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00170
00171 /* Tip: To avoid modifying this file each time you need to use different HSE,
00172    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00173
00174 /* ########################### System Configuration ######################### */
00175 /**
00176   * @brief This is the HAL system configuration section
00177   */
00178 #define  VDD_VALUE                    (3300UL) /*!< Value of VDD in mv */
00179 #define  TICK_INT_PRIORITY            ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority */
00180 #define  USE_RTOS                     0U
00181 #define  PREFETCH_ENABLE              1U
00182 #define  INSTRUCTION_CACHE_ENABLE     1U
00183
00184 /* ################## SPI peripheral configuration ########################## */
00185
00186 /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
00187 * Activated: CRC code is present inside driver
00188 * Deactivated: CRC code cleaned from driver
00189 */
00190
00191 #define USE_SPI_CRC                     1U
00192
00193 /* ################## CRYP peripheral configuration ########################## */
00194
00195 #define USE_HAL_CRYP_SUSPEND_RESUME     1U
00196
00197
00198 /* ########################## Assert Selection ############################## */
00199 /**
00200   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00201   *        HAL drivers code
00202   */
00203 /* #define USE_FULL_ASSERT    1U */
00204
00205 /* Includes ------------------------------------------------------------------*/
00206 /**
00207   * @brief Include modules header file
00208   */
00209
00210 #ifdef HAL_RCC_MODULE_ENABLED
00211 #include "stm32g0xx_hal_rcc.h"
00212 #endif /* HAL_RCC_MODULE_ENABLED */
00213
00214 #ifdef HAL_GPIO_MODULE_ENABLED
00215 #include "stm32g0xx_hal_gpio.h"
00216 #endif /* HAL_GPIO_MODULE_ENABLED */
00217
00218 #ifdef HAL_DMA_MODULE_ENABLED
00219 #include "stm32g0xx_hal_dma.h"
00220 #endif /* HAL_DMA_MODULE_ENABLED */
00221
00222 #ifdef HAL_CORTEX_MODULE_ENABLED
00223 #include "stm32g0xx_hal_cortex.h"
00224 #endif /* HAL_CORTEX_MODULE_ENABLED */
00225
00226 #ifdef HAL_ADC_MODULE_ENABLED
00227 #include "stm32g0xx_hal_adc.h"
00228 #include "stm32g0xx_hal_adc_ex.h"
00229 #endif /* HAL_ADC_MODULE_ENABLED */
00230
00231 #ifdef HAL_CEC_MODULE_ENABLED
00232 #include "stm32g0xx_hal_cec.h"
00233 #endif /* HAL_CEC_MODULE_ENABLED */
00234
00235 #ifdef HAL_COMP_MODULE_ENABLED
00236 #include "stm32g0xx_hal_comp.h"
00237 #endif /* HAL_COMP_MODULE_ENABLED */
00238
00239 #ifdef HAL_CRC_MODULE_ENABLED
00240 #include "stm32g0xx_hal_crc.h"
00241 #endif /* HAL_CRC_MODULE_ENABLED */
00242
00243 #ifdef HAL_CRYP_MODULE_ENABLED
00244 #include "stm32g0xx_hal_cryp.h"
00245 #endif /* HAL_CRYP_MODULE_ENABLED */
00246
00247 #ifdef HAL_DAC_MODULE_ENABLED
00248 #include "stm32g0xx_hal_dac.h"
00249 #endif /* HAL_DAC_MODULE_ENABLED */
00250
00251 #ifdef HAL_EXTI_MODULE_ENABLED
00252 #include "stm32g0xx_hal_exti.h"
00253 #endif /* HAL_EXTI_MODULE_ENABLED */
00254
00255 #ifdef HAL_FDCAN_MODULE_ENABLED
00256 #include "stm32g0xx_hal_fdcan.h"
00257 #endif /* HAL_FDCAN_MODULE_ENABLED */
00258
00259 #ifdef HAL_FLASH_MODULE_ENABLED
00260 #include "stm32g0xx_hal_flash.h"
00261 #endif /* HAL_FLASH_MODULE_ENABLED */
00262
00263 #ifdef HAL_I2C_MODULE_ENABLED
00264 #include "stm32g0xx_hal_i2c.h"
00265 #endif /* HAL_I2C_MODULE_ENABLED */
00266
00267 #ifdef HAL_I2S_MODULE_ENABLED
00268 #include "stm32g0xx_hal_i2s.h"
00269 #endif /* HAL_I2S_MODULE_ENABLED */
00270
00271 #ifdef HAL_IRDA_MODULE_ENABLED
00272 #include "stm32g0xx_hal_irda.h"
00273 #endif /* HAL_IRDA_MODULE_ENABLED */
00274
00275 #ifdef HAL_IWDG_MODULE_ENABLED
00276 #include "stm32g0xx_hal_iwdg.h"
00277 #endif /* HAL_IWDG_MODULE_ENABLED */
00278
00279 #ifdef HAL_LPTIM_MODULE_ENABLED
00280 #include "stm32g0xx_hal_lptim.h"
00281 #endif /* HAL_LPTIM_MODULE_ENABLED */
00282
00283 #ifdef HAL_PCD_MODULE_ENABLED
00284 #include "stm32g0xx_hal_pcd.h"
00285 #endif /* HAL_PCD_MODULE_ENABLED */
00286
00287 #ifdef HAL_HCD_MODULE_ENABLED
00288 #include "stm32g0xx_hal_hcd.h"
00289 #endif /* HAL_HCD_MODULE_ENABLED */
00290
00291 #ifdef HAL_PWR_MODULE_ENABLED
00292 #include "stm32g0xx_hal_pwr.h"
00293 #endif /* HAL_PWR_MODULE_ENABLED */
00294
00295 #ifdef HAL_RNG_MODULE_ENABLED
00296 #include "stm32g0xx_hal_rng.h"
00297 #endif /* HAL_RNG_MODULE_ENABLED */
00298
00299 #ifdef HAL_RTC_MODULE_ENABLED
00300 #include "stm32g0xx_hal_rtc.h"
00301 #endif /* HAL_RTC_MODULE_ENABLED */
00302
00303 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00304 #include "stm32g0xx_hal_smartcard.h"
00305 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00306
00307 #ifdef HAL_SMBUS_MODULE_ENABLED
00308 #include "stm32g0xx_hal_smbus.h"
00309 #endif /* HAL_SMBUS_MODULE_ENABLED */
00310
00311 #ifdef HAL_SPI_MODULE_ENABLED
00312 #include "stm32g0xx_hal_spi.h"
00313 #endif /* HAL_SPI_MODULE_ENABLED */
00314
00315 #ifdef HAL_TIM_MODULE_ENABLED
00316 #include "stm32g0xx_hal_tim.h"
00317 #endif /* HAL_TIM_MODULE_ENABLED */
00318
00319 #ifdef HAL_UART_MODULE_ENABLED
00320 #include "stm32g0xx_hal_uart.h"
00321 #endif /* HAL_UART_MODULE_ENABLED */
00322
00323 #ifdef HAL_USART_MODULE_ENABLED
00324 #include "stm32g0xx_hal_usart.h"
00325 #endif /* HAL_USART_MODULE_ENABLED */
00326
00327 #ifdef HAL_WWDG_MODULE_ENABLED
00328 #include "stm32g0xx_hal_wwdg.h"
00329 #endif /* HAL_WWDG_MODULE_ENABLED */
00330
00331 /* Exported macro ------------------------------------------------------------*/
00332 #ifdef  USE_FULL_ASSERT
00333 /**
00334   * @brief  The assert_param macro is used for functions parameters check.
00335   * @param  expr If expr is false, it calls assert_failed function
00336   *         which reports the name of the source file and the source
00337   *         line number of the call that failed.
00338   *         If expr is true, it returns no value.
00339   * @retval None
00340   */
00341 #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
00342 /* Exported functions ------------------------------------------------------- */
00343 void assert_failed(uint8_t *file, uint32_t line);
00344 #else
00345 #define assert_param(expr) ((void)0U)
00346 #endif /* USE_FULL_ASSERT */
00347
00348 #ifdef __cplusplus
00349 }
00350 #endif
00351
00352 #endif /* STM32G0xx_HAL_CONF_H */
00353
00354
00355
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cortex.c Source File

  • File List
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  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
  • Src
stm32g0xx_hal_cortex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @brief   CORTEX HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the CORTEX:
00008   *           + Initialization and Configuration functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                         ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016     *** How to configure Interrupts using CORTEX HAL driver ***
00017     ===========================================================
00018     [..]
00019     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00020     The Cortex M0+ exceptions are managed by CMSIS functions.
00021       (#) Enable and Configure the priority of the selected IRQ Channels.
00022              The priority can be 0..3.
00023
00024         -@- Lower priority values gives higher priority.
00025         -@- Priority Order:
00026             (#@) Lowest priority.
00027             (#@) Lowest hardware priority (IRQn position).
00028
00029       (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
00030
00031       (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
00032
00033       -@-  Negative value of IRQn_Type are not allowed.
00034
00035     *** How to configure Systick using CORTEX HAL driver ***
00036     ========================================================
00037     [..]
00038     Setup SysTick Timer for time base.
00039
00040    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
00041        is a CMSIS function that:
00042         (++) Configures the SysTick Reload register with value passed as function parameter.
00043         (++) Configures the SysTick IRQ priority to the lowest value (0x03).
00044         (++) Resets the SysTick Counter register.
00045         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00046         (++) Enables the SysTick Interrupt.
00047         (++) Starts the SysTick Counter.
00048
00049    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00050        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00051        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
00052        inside the stm32g0xx_hal_cortex.h file.
00053
00054    (+) You can change the SysTick IRQ priority by calling the
00055        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00056        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00057
00058    (+) To adjust the SysTick time base, use the following formula:
00059
00060        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00061        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00062        (++) Reload Value should not exceed 0xFFFFFF
00063
00064   @endverbatim
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * Copyright (c) 2018 STMicroelectronics.
00069   * All rights reserved.
00070   *
00071   * This software is licensed under terms that can be found in the LICENSE file in
00072   * the root directory of this software component.
00073   * If no LICENSE file comes with this software, it is provided AS-IS.
00074   *
00075   ******************************************************************************
00076   */
00077
00078 /* Includes ------------------------------------------------------------------*/
00079 #include "stm32g0xx_hal.h"
00080
00081 /** @addtogroup STM32G0xx_HAL_Driver
00082   * @{
00083   */
00084
00085 /** @addtogroup CORTEX
00086   * @{
00087   */
00088
00089 #ifdef HAL_CORTEX_MODULE_ENABLED
00090
00091 /* Private types -------------------------------------------------------------*/
00092 /* Private variables ---------------------------------------------------------*/
00093 /* Private constants ---------------------------------------------------------*/
00094 /* Private macros ------------------------------------------------------------*/
00095 /* Private function prototypes -----------------------------------------------*/
00096 /* Exported functions --------------------------------------------------------*/
00097
00098 /** @addtogroup CORTEX_Exported_Functions
00099   * @{
00100   */
00101
00102
00103 /** @addtogroup CORTEX_Exported_Functions_Group1
00104  *  @brief    Initialization and Configuration functions
00105  *
00106 @verbatim
00107   ==============================================================================
00108               ##### Initialization and Configuration functions #####
00109   ==============================================================================
00110     [..]
00111       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00112       Systick functionalities
00113
00114 @endverbatim
00115   * @{
00116   */
00117
00118 /**
00119   * @brief Sets the priority of an interrupt.
00120   * @param IRQn External interrupt number .
00121   *         This parameter can be an enumerator of IRQn_Type enumeration
00122   *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32g0xx.h file)
00123   * @param PreemptPriority The preemption priority for the IRQn channel.
00124   *         This parameter can be a value between 0 and 3.
00125   *         A lower priority value indicates a higher priority
00126   * @param SubPriority the subpriority level for the IRQ channel.
00127   *         with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
00128   *         no subpriority supported in Cortex M0+ based products.
00129   * @retval None
00130   */
00131 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00132 {
00133   /* Prevent unused argument(s) compilation warning */
00134   UNUSED(SubPriority);
00135
00136   /* Check the parameters */
00137   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00138   NVIC_SetPriority(IRQn, PreemptPriority);
00139 }
00140
00141 /**
00142   * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
00143   * @param  IRQn External interrupt number.
00144   *         This parameter can be an enumerator of IRQn_Type enumeration
00145   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
00146   * @retval None
00147   */
00148 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00149 {
00150   /* Check the parameters */
00151   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00152
00153   /* Enable interrupt */
00154   NVIC_EnableIRQ(IRQn);
00155 }
00156
00157 /**
00158   * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
00159   * @param  IRQn External interrupt number.
00160   *         This parameter can be an enumerator of IRQn_Type enumeration
00161   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
00162   * @retval None
00163   */
00164 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00165 {
00166   /* Check the parameters */
00167   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00168
00169   /* Disable interrupt */
00170   NVIC_DisableIRQ(IRQn);
00171 }
00172
00173 /**
00174   * @brief  Initiate a system reset request to reset the MCU.
00175   * @retval None
00176   */
00177 void HAL_NVIC_SystemReset(void)
00178 {
00179   /* System Reset */
00180   NVIC_SystemReset();
00181 }
00182
00183 /**
00184   * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
00185   *         Counter is in free running mode to generate periodic interrupts.
00186   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
00187   * @retval status:  - 0  Function succeeded.
00188   *                  - 1  Function failed.
00189   */
00190 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00191 {
00192   return SysTick_Config(TicksNumb);
00193 }
00194 /**
00195   * @}
00196   */
00197
00198 /** @addtogroup CORTEX_Exported_Functions_Group2
00199  *  @brief   Cortex control functions
00200  *
00201 @verbatim
00202   ==============================================================================
00203                       ##### Peripheral Control functions #####
00204   ==============================================================================
00205     [..]
00206       This subsection provides a set of functions allowing to control the CORTEX
00207       (NVIC, SYSTICK, MPU) functionalities.
00208
00209
00210 @endverbatim
00211   * @{
00212   */
00213
00214 /**
00215   * @brief  Get the priority of an interrupt.
00216   * @param  IRQn External interrupt number.
00217   *         This parameter can be an enumerator of IRQn_Type enumeration
00218   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
00219   * @retval None
00220   */
00221 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
00222 {
00223   /* Get priority for Cortex-M system or device specific interrupts */
00224   return NVIC_GetPriority(IRQn);
00225 }
00226
00227 /**
00228   * @brief  Set Pending bit of an external interrupt.
00229   * @param  IRQn External interrupt number
00230   *         This parameter can be an enumerator of IRQn_Type enumeration
00231   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
00232   * @retval None
00233   */
00234 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00235 {
00236   /* Check the parameters */
00237   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00238
00239   /* Set interrupt pending */
00240   NVIC_SetPendingIRQ(IRQn);
00241 }
00242
00243 /**
00244   * @brief  Get Pending Interrupt (read the pending register in the NVIC
00245   *         and return the pending bit for the specified interrupt).
00246   * @param  IRQn External interrupt number.
00247   *         This parameter can be an enumerator of IRQn_Type enumeration
00248   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
00249   * @retval status: - 0  Interrupt status is not pending.
00250   *                 - 1  Interrupt status is pending.
00251   */
00252 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00253 {
00254   /* Check the parameters */
00255   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00256
00257   /* Return 1 if pending else 0 */
00258   return NVIC_GetPendingIRQ(IRQn);
00259 }
00260
00261 /**
00262   * @brief  Clear the pending bit of an external interrupt.
00263   * @param  IRQn External interrupt number.
00264   *         This parameter can be an enumerator of IRQn_Type enumeration
00265   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
00266   * @retval None
00267   */
00268 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00269 {
00270   /* Check the parameters */
00271   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00272
00273   /* Clear pending interrupt */
00274   NVIC_ClearPendingIRQ(IRQn);
00275 }
00276
00277 /**
00278   * @brief  Configure the SysTick clock source.
00279   * @param CLKSource specifies the SysTick clock source.
00280   *         This parameter can be one of the following values:
00281   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00282   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00283   * @retval None
00284   */
00285 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00286 {
00287   /* Check the parameters */
00288   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00289   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00290   {
00291     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00292   }
00293   else
00294   {
00295     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00296   }
00297 }
00298
00299 /**
00300   * @brief  Handle SYSTICK interrupt request.
00301   * @retval None
00302   */
00303 void HAL_SYSTICK_IRQHandler(void)
00304 {
00305   HAL_SYSTICK_Callback();
00306 }
00307
00308 /**
00309   * @brief  SYSTICK callback.
00310   * @retval None
00311   */
00312 __weak void HAL_SYSTICK_Callback(void)
00313 {
00314   /* NOTE : This function should not be modified, when the callback is needed,
00315             the HAL_SYSTICK_Callback could be implemented in the user file
00316    */
00317 }
00318
00319 #if (__MPU_PRESENT == 1U)
00320 /**
00321   * @brief  Enable the MPU.
00322   * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
00323   *          NMI, FAULTMASK and privileged access to the default memory
00324   *          This parameter can be one of the following values:
00325   *            @arg MPU_HFNMI_PRIVDEF_NONE
00326   *            @arg MPU_HARDFAULT_NMI
00327   *            @arg MPU_PRIVILEGED_DEFAULT
00328   *            @arg MPU_HFNMI_PRIVDEF
00329   * @retval None
00330   */
00331 void HAL_MPU_Enable(uint32_t MPU_Control)
00332 {
00333   /* Enable the MPU */
00334   MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
00335
00336   /* Ensure MPU setting take effects */
00337   __DSB();
00338   __ISB();
00339 }
00340
00341
00342 /**
00343   * @brief  Disable the MPU.
00344   * @retval None
00345   */
00346 void HAL_MPU_Disable(void)
00347 {
00348   /* Make sure outstanding transfers are done */
00349   __DMB();
00350
00351   /* Disable the MPU and clear the control register*/
00352   MPU->CTRL  = 0;
00353 }
00354
00355
00356 /**
00357   * @brief  Initialize and configure the Region and the memory to be protected.
00358   * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
00359   *                the initialization and configuration information.
00360   * @retval None
00361   */
00362 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00363 {
00364   /* Check the parameters */
00365   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00366   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00367
00368   /* Set the Region number */
00369   MPU->RNR = MPU_Init->Number;
00370
00371   if ((MPU_Init->Enable) != 0U)
00372   {
00373     /* Check the parameters */
00374     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00375     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00376     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00377     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00378     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00379     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00380     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00381     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00382
00383     MPU->RBAR = MPU_Init->BaseAddress;
00384     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
00385                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
00386                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
00387                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
00388                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
00389                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
00390                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
00391                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
00392                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
00393   }
00394   else
00395   {
00396     MPU->RBAR = 0x00U;
00397     MPU->RASR = 0x00U;
00398   }
00399 }
00400 #endif /* __MPU_PRESENT */
00401
00402 /**
00403   * @}
00404   */
00405
00406 /**
00407   * @}
00408   */
00409
00410 #endif /* HAL_CORTEX_MODULE_ENABLED */
00411 /**
00412   * @}
00413   */
00414
00415 /**
00416   * @}
00417   */
00418
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cortex.h Source File

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stm32g0xx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_CORTEX_H
00021 #define STM32G0xx_HAL_CORTEX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup CORTEX CORTEX
00035   * @brief CORTEX HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
00041   * @{
00042   */
00043
00044 #if (__MPU_PRESENT == 1)
00045 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00046   * @brief  MPU Region initialization structure
00047   * @{
00048   */
00049 typedef struct
00050 {
00051   uint8_t Enable;                /*!< Specifies the status of the region.
00052                                       This parameter can be a value of @ref CORTEX_MPU_Region_Enable                */
00053   uint8_t Number;                /*!< Specifies the number of the region to protect.
00054                                       This parameter can be a value of @ref CORTEX_MPU_Region_Number                */
00055   uint32_t BaseAddress;          /*!< Specifies the base address of the region to protect.
00056                                                                                                                     */
00057   uint8_t Size;                  /*!< Specifies the size of the region to protect.
00058                                       This parameter can be a value of @ref CORTEX_MPU_Region_Size                  */
00059   uint8_t SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00060                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF   */
00061   uint8_t TypeExtField;          /*!< Specifies the TEX field level.
00062                                       This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                   */
00063   uint8_t AccessPermission;      /*!< Specifies the region access permission type.
00064                                       This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
00065   uint8_t DisableExec;           /*!< Specifies the instruction access status.
00066                                       This parameter can be a value of @ref CORTEX_MPU_Instruction_Access           */
00067   uint8_t IsShareable;           /*!< Specifies the shareability status of the protected region.
00068                                       This parameter can be a value of @ref CORTEX_MPU_Access_Shareable             */
00069   uint8_t IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00070                                       This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable             */
00071   uint8_t IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00072                                       This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable            */
00073 } MPU_Region_InitTypeDef;
00074 /**
00075   * @}
00076   */
00077 #endif /* __MPU_PRESENT */
00078
00079 /**
00080   * @}
00081   */
00082
00083 /* Exported constants --------------------------------------------------------*/
00084
00085 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00086   * @{
00087   */
00088
00089 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
00090   * @{
00091   */
00092 #define SYSTICK_CLKSOURCE_HCLK_DIV8       0x00000000U
00093 #define SYSTICK_CLKSOURCE_HCLK            0x00000004U
00094
00095 /**
00096   * @}
00097   */
00098
00099 #if (__MPU_PRESENT == 1)
00100 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
00101   * @{
00102   */
00103 #define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
00104 #define  MPU_HARDFAULT_NMI                (MPU_CTRL_HFNMIENA_Msk)
00105 #define  MPU_PRIVILEGED_DEFAULT           (MPU_CTRL_PRIVDEFENA_Msk)
00106 #define  MPU_HFNMI_PRIVDEF                (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
00107 /**
00108   * @}
00109   */
00110
00111 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00112   * @{
00113   */
00114 #define  MPU_REGION_ENABLE                ((uint8_t)0x01)
00115 #define  MPU_REGION_DISABLE               ((uint8_t)0x00)
00116 /**
00117   * @}
00118   */
00119
00120 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00121   * @{
00122   */
00123 #define  MPU_INSTRUCTION_ACCESS_ENABLE    ((uint8_t)0x00)
00124 #define  MPU_INSTRUCTION_ACCESS_DISABLE   ((uint8_t)0x01)
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00130   * @{
00131   */
00132 #define  MPU_ACCESS_SHAREABLE             ((uint8_t)0x01)
00133 #define  MPU_ACCESS_NOT_SHAREABLE         ((uint8_t)0x00)
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00139   * @{
00140   */
00141 #define  MPU_ACCESS_CACHEABLE             ((uint8_t)0x01)
00142 #define  MPU_ACCESS_NOT_CACHEABLE         ((uint8_t)0x00)
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00148   * @{
00149   */
00150 #define  MPU_ACCESS_BUFFERABLE            ((uint8_t)0x01)
00151 #define  MPU_ACCESS_NOT_BUFFERABLE        ((uint8_t)0x00)
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
00157   * @{
00158   */
00159 #define  MPU_TEX_LEVEL0                   ((uint8_t)0x00)
00160 #define  MPU_TEX_LEVEL1                   ((uint8_t)0x01)
00161 #define  MPU_TEX_LEVEL2                   ((uint8_t)0x02)
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00167   * @{
00168   */
00169 #define   MPU_REGION_SIZE_256B            ((uint8_t)0x07)
00170 #define   MPU_REGION_SIZE_512B            ((uint8_t)0x08)
00171 #define   MPU_REGION_SIZE_1KB             ((uint8_t)0x09)
00172 #define   MPU_REGION_SIZE_2KB             ((uint8_t)0x0A)
00173 #define   MPU_REGION_SIZE_4KB             ((uint8_t)0x0B)
00174 #define   MPU_REGION_SIZE_8KB             ((uint8_t)0x0C)
00175 #define   MPU_REGION_SIZE_16KB            ((uint8_t)0x0D)
00176 #define   MPU_REGION_SIZE_32KB            ((uint8_t)0x0E)
00177 #define   MPU_REGION_SIZE_64KB            ((uint8_t)0x0F)
00178 #define   MPU_REGION_SIZE_128KB           ((uint8_t)0x10)
00179 #define   MPU_REGION_SIZE_256KB           ((uint8_t)0x11)
00180 #define   MPU_REGION_SIZE_512KB           ((uint8_t)0x12)
00181 #define   MPU_REGION_SIZE_1MB             ((uint8_t)0x13)
00182 #define   MPU_REGION_SIZE_2MB             ((uint8_t)0x14)
00183 #define   MPU_REGION_SIZE_4MB             ((uint8_t)0x15)
00184 #define   MPU_REGION_SIZE_8MB             ((uint8_t)0x16)
00185 #define   MPU_REGION_SIZE_16MB            ((uint8_t)0x17)
00186 #define   MPU_REGION_SIZE_32MB            ((uint8_t)0x18)
00187 #define   MPU_REGION_SIZE_64MB            ((uint8_t)0x19)
00188 #define   MPU_REGION_SIZE_128MB           ((uint8_t)0x1A)
00189 #define   MPU_REGION_SIZE_256MB           ((uint8_t)0x1B)
00190 #define   MPU_REGION_SIZE_512MB           ((uint8_t)0x1C)
00191 #define   MPU_REGION_SIZE_1GB             ((uint8_t)0x1D)
00192 #define   MPU_REGION_SIZE_2GB             ((uint8_t)0x1E)
00193 #define   MPU_REGION_SIZE_4GB             ((uint8_t)0x1F)
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00199   * @{
00200   */
00201 #define  MPU_REGION_NO_ACCESS             ((uint8_t)0x00)
00202 #define  MPU_REGION_PRIV_RW               ((uint8_t)0x01)
00203 #define  MPU_REGION_PRIV_RW_URO           ((uint8_t)0x02)
00204 #define  MPU_REGION_FULL_ACCESS           ((uint8_t)0x03)
00205 #define  MPU_REGION_PRIV_RO               ((uint8_t)0x05)
00206 #define  MPU_REGION_PRIV_RO_URO           ((uint8_t)0x06)
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00212   * @{
00213   */
00214 #define  MPU_REGION_NUMBER0               ((uint8_t)0x00)
00215 #define  MPU_REGION_NUMBER1               ((uint8_t)0x01)
00216 #define  MPU_REGION_NUMBER2               ((uint8_t)0x02)
00217 #define  MPU_REGION_NUMBER3               ((uint8_t)0x03)
00218 #define  MPU_REGION_NUMBER4               ((uint8_t)0x04)
00219 #define  MPU_REGION_NUMBER5               ((uint8_t)0x05)
00220 #define  MPU_REGION_NUMBER6               ((uint8_t)0x06)
00221 #define  MPU_REGION_NUMBER7               ((uint8_t)0x07)
00222 /**
00223   * @}
00224   */
00225 #endif /* __MPU_PRESENT */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /* Exported macros -----------------------------------------------------------*/
00232 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
00233   * @{
00234   */
00235
00236 /**
00237   * @}
00238   */
00239
00240 /* Exported functions --------------------------------------------------------*/
00241 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00242   * @{
00243   */
00244
00245 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
00246  *  @brief    Initialization and Configuration functions
00247  * @{
00248  */
00249 /* Initialization and Configuration functions *****************************/
00250 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00251 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00252 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00253 void HAL_NVIC_SystemReset(void);
00254 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00260  *  @brief   Cortex control functions
00261  * @{
00262  */
00263 /* Peripheral Control functions *************************************************/
00264 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
00265 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00266 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00267 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00268 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00269 void HAL_SYSTICK_IRQHandler(void);
00270 void HAL_SYSTICK_Callback(void);
00271
00272 #if (__MPU_PRESENT == 1U)
00273 void HAL_MPU_Enable(uint32_t MPU_Control);
00274 void HAL_MPU_Disable(void);
00275 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00276 #endif /* __MPU_PRESENT */
00277 /**
00278   * @}
00279   */
00280
00281 /**
00282   * @}
00283   */
00284
00285 /* Private types -------------------------------------------------------------*/
00286 /* Private variables ---------------------------------------------------------*/
00287 /* Private constants ---------------------------------------------------------*/
00288 /* Private macros ------------------------------------------------------------*/
00289 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00290   * @{
00291   */
00292 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)     ((PRIORITY) < 0x4U)
00293
00294 #define IS_NVIC_DEVICE_IRQ(IRQ)                   ((IRQ) > SysTick_IRQn)
00295
00296 #define IS_SYSTICK_CLK_SOURCE(SOURCE)             (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00297                                                    ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00298
00299 #if (__MPU_PRESENT == 1)
00300 #define IS_MPU_REGION_ENABLE(STATE)               (((STATE) == MPU_REGION_ENABLE) || \
00301                                                    ((STATE) == MPU_REGION_DISABLE))
00302
00303 #define IS_MPU_INSTRUCTION_ACCESS(STATE)          (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00304                                                    ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00305
00306 #define IS_MPU_ACCESS_SHAREABLE(STATE)            (((STATE) == MPU_ACCESS_SHAREABLE) || \
00307                                                    ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00308
00309 #define IS_MPU_ACCESS_CACHEABLE(STATE)            (((STATE) == MPU_ACCESS_CACHEABLE) || \
00310                                                    ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00311
00312 #define IS_MPU_ACCESS_BUFFERABLE(STATE)           (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00313                                                    ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00314
00315 #define IS_MPU_TEX_LEVEL(TYPE)                    (((TYPE) == MPU_TEX_LEVEL0)  || \
00316                                                    ((TYPE) == MPU_TEX_LEVEL1)  || \
00317                                                    ((TYPE) == MPU_TEX_LEVEL2))
00318
00319 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)  (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00320                                                    ((TYPE) == MPU_REGION_PRIV_RW)     || \
00321                                                    ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00322                                                    ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00323                                                    ((TYPE) == MPU_REGION_PRIV_RO)     || \
00324                                                    ((TYPE) == MPU_REGION_PRIV_RO_URO))
00325
00326 #define IS_MPU_REGION_NUMBER(NUMBER)              (((NUMBER) == MPU_REGION_NUMBER0) || \
00327                                                    ((NUMBER) == MPU_REGION_NUMBER1) || \
00328                                                    ((NUMBER) == MPU_REGION_NUMBER2) || \
00329                                                    ((NUMBER) == MPU_REGION_NUMBER3) || \
00330                                                    ((NUMBER) == MPU_REGION_NUMBER4) || \
00331                                                    ((NUMBER) == MPU_REGION_NUMBER5) || \
00332                                                    ((NUMBER) == MPU_REGION_NUMBER6) || \
00333                                                    ((NUMBER) == MPU_REGION_NUMBER7))
00334
00335 #define IS_MPU_REGION_SIZE(SIZE)                  (((SIZE) == MPU_REGION_SIZE_256B)  || \
00336                                                    ((SIZE) == MPU_REGION_SIZE_512B)  || \
00337                                                    ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00338                                                    ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00339                                                    ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00340                                                    ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00341                                                    ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00342                                                    ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00343                                                    ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00344                                                    ((SIZE) == MPU_REGION_SIZE_128KB) || \
00345                                                    ((SIZE) == MPU_REGION_SIZE_256KB) || \
00346                                                    ((SIZE) == MPU_REGION_SIZE_512KB) || \
00347                                                    ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00348                                                    ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00349                                                    ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00350                                                    ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00351                                                    ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00352                                                    ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00353                                                    ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00354                                                    ((SIZE) == MPU_REGION_SIZE_128MB) || \
00355                                                    ((SIZE) == MPU_REGION_SIZE_256MB) || \
00356                                                    ((SIZE) == MPU_REGION_SIZE_512MB) || \
00357                                                    ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00358                                                    ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00359                                                    ((SIZE) == MPU_REGION_SIZE_4GB))
00360
00361 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)      ((SUBREGION) < (uint16_t)0x00FFU)
00362 #endif /* __MPU_PRESENT */
00363
00364 /**
00365   * @}
00366   */
00367
00368 /* Private functions ---------------------------------------------------------*/
00369
00370 /**
00371   * @}
00372   */
00373
00374 /**
00375   * @}
00376   */
00377
00378 #ifdef __cplusplus
00379 }
00380 #endif
00381
00382 #endif /* STM32G0xx_HAL_CORTEX_H */
00383
00384
00385
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_crc.c Source File

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  • Drivers
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  • Src
stm32g0xx_hal_crc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024  ===============================================================================
00025                      ##### How to use this driver #####
00026  ===============================================================================
00027     [..]
00028          (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00029          (+) Initialize CRC calculator
00030              (++) specify generating polynomial (peripheral default or non-default one)
00031              (++) specify initialization value (peripheral default or non-default one)
00032              (++) specify input data format
00033              (++) specify input or output data inversion mode if any
00034          (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
00035              input data buffer starting with the previously computed CRC as
00036              initialization value
00037          (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
00038              input data buffer starting with the defined initialization value
00039              (default or non-default) to initiate CRC calculation
00040
00041   @endverbatim
00042   ******************************************************************************
00043   */
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32g0xx_hal.h"
00047
00048 /** @addtogroup STM32G0xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @defgroup CRC CRC
00053   * @brief CRC HAL module driver.
00054   * @{
00055   */
00056
00057 #ifdef HAL_CRC_MODULE_ENABLED
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /* Private macro -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064 /** @defgroup CRC_Private_Functions CRC Private Functions
00065   * @{
00066   */
00067 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
00068 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
00069 /**
00070   * @}
00071   */
00072
00073 /* Exported functions --------------------------------------------------------*/
00074
00075 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00076   * @{
00077   */
00078
00079 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00080   *  @brief    Initialization and Configuration functions.
00081   *
00082 @verbatim
00083  ===============================================================================
00084             ##### Initialization and de-initialization functions #####
00085  ===============================================================================
00086     [..]  This section provides functions allowing to:
00087       (+) Initialize the CRC according to the specified parameters
00088           in the CRC_InitTypeDef and create the associated handle
00089       (+) DeInitialize the CRC peripheral
00090       (+) Initialize the CRC MSP (MCU Specific Package)
00091       (+) DeInitialize the CRC MSP
00092
00093 @endverbatim
00094   * @{
00095   */
00096
00097 /**
00098   * @brief  Initialize the CRC according to the specified
00099   *         parameters in the CRC_InitTypeDef and create the associated handle.
00100   * @param  hcrc CRC handle
00101   * @retval HAL status
00102   */
00103 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00104 {
00105   /* Check the CRC handle allocation */
00106   if (hcrc == NULL)
00107   {
00108     return HAL_ERROR;
00109   }
00110
00111   /* Check the parameters */
00112   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00113
00114   if (hcrc->State == HAL_CRC_STATE_RESET)
00115   {
00116     /* Allocate lock resource and initialize it */
00117     hcrc->Lock = HAL_UNLOCKED;
00118     /* Init the low level hardware */
00119     HAL_CRC_MspInit(hcrc);
00120   }
00121
00122   hcrc->State = HAL_CRC_STATE_BUSY;
00123
00124   /* check whether or not non-default generating polynomial has been
00125    * picked up by user */
00126   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
00127   if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
00128   {
00129     /* initialize peripheral with default generating polynomial */
00130     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
00131     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
00132   }
00133   else
00134   {
00135     /* initialize CRC peripheral with generating polynomial defined by user */
00136     if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
00137     {
00138       return HAL_ERROR;
00139     }
00140   }
00141
00142   /* check whether or not non-default CRC initial value has been
00143    * picked up by user */
00144   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
00145   if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
00146   {
00147     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
00148   }
00149   else
00150   {
00151     WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
00152   }
00153
00154
00155   /* set input data inversion mode */
00156   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
00157   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
00158
00159   /* set output data inversion mode */
00160   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
00161   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
00162
00163   /* makes sure the input data format (bytes, halfwords or words stream)
00164    * is properly specified by user */
00165   assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
00166
00167   /* Change CRC peripheral state */
00168   hcrc->State = HAL_CRC_STATE_READY;
00169
00170   /* Return function status */
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  DeInitialize the CRC peripheral.
00176   * @param  hcrc CRC handle
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00180 {
00181   /* Check the CRC handle allocation */
00182   if (hcrc == NULL)
00183   {
00184     return HAL_ERROR;
00185   }
00186
00187   /* Check the parameters */
00188   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00189
00190   /* Check the CRC peripheral state */
00191   if (hcrc->State == HAL_CRC_STATE_BUSY)
00192   {
00193     return HAL_BUSY;
00194   }
00195
00196   /* Change CRC peripheral state */
00197   hcrc->State = HAL_CRC_STATE_BUSY;
00198
00199   /* Reset CRC calculation unit */
00200   __HAL_CRC_DR_RESET(hcrc);
00201
00202   /* Reset IDR register content */
00203   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
00204
00205   /* DeInit the low level hardware */
00206   HAL_CRC_MspDeInit(hcrc);
00207
00208   /* Change CRC peripheral state */
00209   hcrc->State = HAL_CRC_STATE_RESET;
00210
00211   /* Process unlocked */
00212   __HAL_UNLOCK(hcrc);
00213
00214   /* Return function status */
00215   return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  Initializes the CRC MSP.
00220   * @param  hcrc CRC handle
00221   * @retval None
00222   */
00223 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00224 {
00225   /* Prevent unused argument(s) compilation warning */
00226   UNUSED(hcrc);
00227
00228   /* NOTE : This function should not be modified, when the callback is needed,
00229             the HAL_CRC_MspInit can be implemented in the user file
00230    */
00231 }
00232
00233 /**
00234   * @brief  DeInitialize the CRC MSP.
00235   * @param  hcrc CRC handle
00236   * @retval None
00237   */
00238 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00239 {
00240   /* Prevent unused argument(s) compilation warning */
00241   UNUSED(hcrc);
00242
00243   /* NOTE : This function should not be modified, when the callback is needed,
00244             the HAL_CRC_MspDeInit can be implemented in the user file
00245    */
00246 }
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00253   *  @brief    management functions.
00254   *
00255 @verbatim
00256  ===============================================================================
00257                       ##### Peripheral Control functions #####
00258  ===============================================================================
00259     [..]  This section provides functions allowing to:
00260       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00261           using combination of the previous CRC value and the new one.
00262
00263        [..]  or
00264
00265       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00266           independently of the previous CRC value.
00267
00268 @endverbatim
00269   * @{
00270   */
00271
00272 /**
00273   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00274   *         starting with the previously computed CRC as initialization value.
00275   * @param  hcrc CRC handle
00276   * @param  pBuffer pointer to the input data buffer, exact input data format is
00277   *         provided by hcrc->InputDataFormat.
00278   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00279   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00280   *         number of words if pBuffer type is * uint32_t).
00281   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00282   *        Input buffer pointers with other types simply need to be cast in uint32_t
00283   *        and the API will internally adjust its input data processing based on the
00284   *        handle field hcrc->InputDataFormat.
00285   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00286   */
00287 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00288 {
00289   uint32_t index;      /* CRC input data buffer index */
00290   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00291
00292   /* Change CRC peripheral state */
00293   hcrc->State = HAL_CRC_STATE_BUSY;
00294
00295   switch (hcrc->InputDataFormat)
00296   {
00297     case CRC_INPUTDATA_FORMAT_WORDS:
00298       /* Enter Data to the CRC calculator */
00299       for (index = 0U; index < BufferLength; index++)
00300       {
00301         hcrc->Instance->DR = pBuffer[index];
00302       }
00303       temp = hcrc->Instance->DR;
00304       break;
00305
00306     case CRC_INPUTDATA_FORMAT_BYTES:
00307       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
00308       break;
00309
00310     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00311       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
00312       break;
00313     default:
00314       break;
00315   }
00316
00317   /* Change CRC peripheral state */
00318   hcrc->State = HAL_CRC_STATE_READY;
00319
00320   /* Return the CRC computed value */
00321   return temp;
00322 }
00323
00324 /**
00325   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00326   *         starting with hcrc->Instance->INIT as initialization value.
00327   * @param  hcrc CRC handle
00328   * @param  pBuffer pointer to the input data buffer, exact input data format is
00329   *         provided by hcrc->InputDataFormat.
00330   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00331   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00332   *         number of words if pBuffer type is * uint32_t).
00333   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00334   *        Input buffer pointers with other types simply need to be cast in uint32_t
00335   *        and the API will internally adjust its input data processing based on the
00336   *        handle field hcrc->InputDataFormat.
00337   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00338   */
00339 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00340 {
00341   uint32_t index;      /* CRC input data buffer index */
00342   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00343
00344   /* Change CRC peripheral state */
00345   hcrc->State = HAL_CRC_STATE_BUSY;
00346
00347   /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
00348   *  written in hcrc->Instance->DR) */
00349   __HAL_CRC_DR_RESET(hcrc);
00350
00351   switch (hcrc->InputDataFormat)
00352   {
00353     case CRC_INPUTDATA_FORMAT_WORDS:
00354       /* Enter 32-bit input data to the CRC calculator */
00355       for (index = 0U; index < BufferLength; index++)
00356       {
00357         hcrc->Instance->DR = pBuffer[index];
00358       }
00359       temp = hcrc->Instance->DR;
00360       break;
00361
00362     case CRC_INPUTDATA_FORMAT_BYTES:
00363       /* Specific 8-bit input data handling  */
00364       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
00365       break;
00366
00367     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00368       /* Specific 16-bit input data handling  */
00369       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
00370       break;
00371
00372     default:
00373       break;
00374   }
00375
00376   /* Change CRC peripheral state */
00377   hcrc->State = HAL_CRC_STATE_READY;
00378
00379   /* Return the CRC computed value */
00380   return temp;
00381 }
00382
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00388   *  @brief    Peripheral State functions.
00389   *
00390 @verbatim
00391  ===============================================================================
00392                       ##### Peripheral State functions #####
00393  ===============================================================================
00394     [..]
00395     This subsection permits to get in run-time the status of the peripheral.
00396
00397 @endverbatim
00398   * @{
00399   */
00400
00401 /**
00402   * @brief  Return the CRC handle state.
00403   * @param  hcrc CRC handle
00404   * @retval HAL state
00405   */
00406 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00407 {
00408   /* Return CRC handle state */
00409   return hcrc->State;
00410 }
00411
00412 /**
00413   * @}
00414   */
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup CRC_Private_Functions
00421   * @{
00422   */
00423
00424 /**
00425   * @brief  Enter 8-bit input data to the CRC calculator.
00426   *         Specific data handling to optimize processing time.
00427   * @param  hcrc CRC handle
00428   * @param  pBuffer pointer to the input data buffer
00429   * @param  BufferLength input data buffer length
00430   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00431   */
00432 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
00433 {
00434   uint32_t i; /* input data buffer index */
00435   uint16_t data;
00436   __IO uint16_t *pReg;
00437
00438   /* Processing time optimization: 4 bytes are entered in a row with a single word write,
00439    * last bytes must be carefully fed to the CRC calculator to ensure a correct type
00440    * handling by the peripheral */
00441   for (i = 0U; i < (BufferLength / 4U); i++)
00442   {
00443     hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
00444                          ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
00445                          ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
00446                          (uint32_t)pBuffer[(4U * i) + 3U];
00447   }
00448   /* last bytes specific handling */
00449   if ((BufferLength % 4U) != 0U)
00450   {
00451     if ((BufferLength % 4U) == 1U)
00452     {
00453       *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
00454     }
00455     if ((BufferLength % 4U) == 2U)
00456     {
00457       data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
00458       pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
00459       *pReg = data;
00460     }
00461     if ((BufferLength % 4U) == 3U)
00462     {
00463       data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
00464       pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
00465       *pReg = data;
00466
00467       *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
00468     }
00469   }
00470
00471   /* Return the CRC computed value */
00472   return hcrc->Instance->DR;
00473 }
00474
00475 /**
00476   * @brief  Enter 16-bit input data to the CRC calculator.
00477   *         Specific data handling to optimize processing time.
00478   * @param  hcrc CRC handle
00479   * @param  pBuffer pointer to the input data buffer
00480   * @param  BufferLength input data buffer length
00481   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00482   */
00483 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
00484 {
00485   uint32_t i;  /* input data buffer index */
00486   __IO uint16_t *pReg;
00487
00488   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
00489    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
00490    * a correct type handling by the peripheral */
00491   for (i = 0U; i < (BufferLength / 2U); i++)
00492   {
00493     hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
00494   }
00495   if ((BufferLength % 2U) != 0U)
00496   {
00497     pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
00498     *pReg = pBuffer[2U * i];
00499   }
00500
00501   /* Return the CRC computed value */
00502   return hcrc->Instance->DR;
00503 }
00504
00505 /**
00506   * @}
00507   */
00508
00509 #endif /* HAL_CRC_MODULE_ENABLED */
00510 /**
00511   * @}
00512   */
00513
00514 /**
00515   * @}
00516   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_crc.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32G0xx_HAL_Driver
  • Inc
stm32g0xx_hal_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_CRC_H
00021 #define STM32G0xx_HAL_CRC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup CRC
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup CRC_Exported_Types CRC Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  CRC HAL State Structure definition
00045   */
00046 typedef enum
00047 {
00048   HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
00049   HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
00050   HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
00051   HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
00052   HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
00053 } HAL_CRC_StateTypeDef;
00054
00055 /**
00056   * @brief CRC Init Structure definition
00057   */
00058 typedef struct
00059 {
00060   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
00061                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
00062                                             X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
00063                                             X^4 + X^2+ X +1.
00064                                             In that case, there is no need to set GeneratingPolynomial field.
00065                                             If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
00066                                             CRCLength fields must be set. */
00067
00068   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
00069                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
00070                                            0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
00071                                            otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
00072
00073   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
00074                                            respectively equal to 7, 8, 16 or 32. This field is written in normal,
00075                                            representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
00076                                            is written 0x65. No need to specify it if DefaultPolynomialUse is set to
00077                                             DEFAULT_POLYNOMIAL_ENABLE.   */
00078
00079   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
00080                                            Value can be either one of
00081                                            @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
00082                                            @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
00083                                            @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
00084                                            @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
00085
00086   uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
00087                                            is set to DEFAULT_INIT_VALUE_ENABLE.   */
00088
00089   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
00090                                            Can be either one of the following values
00091                                            @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
00092                                            @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D
00093                                            becomes 0x58D43CB2
00094                                            @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion,
00095                                            0x1A2B3C4D becomes 0xD458B23C
00096                                            @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D
00097                                            becomes 0xB23CD458 */
00098
00099   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
00100                                             Can be either
00101                                             @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
00102                                             @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted
00103                                              into 0x22CC4488 */
00104 } CRC_InitTypeDef;
00105
00106 /**
00107   * @brief  CRC Handle Structure definition
00108   */
00109 typedef struct
00110 {
00111   CRC_TypeDef                 *Instance;   /*!< Register base address        */
00112
00113   CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
00114
00115   HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
00116
00117   __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
00118
00119   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
00120                                             Can be either
00121                                             @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes
00122                                             (8-bit data)
00123                                             @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of
00124                                             half-words (16-bit data)
00125                                             @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words
00126                                             (32-bit data)
00127
00128                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
00129                                           error must occur if InputBufferFormat is not one of the three values listed
00130                                           above  */
00131 } CRC_HandleTypeDef;
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported constants --------------------------------------------------------*/
00137 /** @defgroup CRC_Exported_Constants CRC Exported Constants
00138   * @{
00139   */
00140
00141 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
00142   * @{
00143   */
00144 #define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
00150   * @{
00151   */
00152 #define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
00158   * @{
00159   */
00160 #define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */
00161 #define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
00167   * @{
00168   */
00169 #define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */
00170 #define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
00176   * @{
00177   */
00178 #define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */
00179 #define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */
00180 #define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */
00181 #define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
00187   * @{
00188   */
00189 #define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */
00190 #define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */
00191 #define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */
00192 #define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup CRC_Input_Buffer_Format Input Buffer Format
00198   * @{
00199   */
00200 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
00201  * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
00202  * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
00203  * the CRC APIs to provide a correct result */
00204 #define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */
00205 #define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */
00206 #define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */
00207 #define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */
00208 /**
00209   * @}
00210   */
00211
00212 /**
00213   * @}
00214   */
00215
00216 /* Exported macros -----------------------------------------------------------*/
00217 /** @defgroup CRC_Exported_Macros CRC Exported Macros
00218   * @{
00219   */
00220
00221 /** @brief Reset CRC handle state.
00222   * @param  __HANDLE__ CRC handle.
00223   * @retval None
00224   */
00225 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00226
00227 /**
00228   * @brief  Reset CRC Data Register.
00229   * @param  __HANDLE__ CRC handle
00230   * @retval None
00231   */
00232 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00233
00234 /**
00235   * @brief  Set CRC INIT non-default value
00236   * @param  __HANDLE__ CRC handle
00237   * @param  __INIT__ 32-bit initial value
00238   * @retval None
00239   */
00240 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
00241
00242 /**
00243   * @brief Store data in the Independent Data (ID) register.
00244   * @param __HANDLE__ CRC handle
00245   * @param __VALUE__  Value to be stored in the ID register
00246   * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
00247   * @retval None
00248   */
00249 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00250
00251 /**
00252   * @brief Return the data stored in the Independent Data (ID) register.
00253   * @param __HANDLE__ CRC handle
00254   * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
00255   * @retval Value of the ID register
00256   */
00257 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00258 /**
00259   * @}
00260   */
00261
00262
00263 /* Private macros --------------------------------------------------------*/
00264 /** @defgroup  CRC_Private_Macros CRC Private Macros
00265   * @{
00266   */
00267
00268 #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
00269                                         ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
00270
00271 #define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
00272                                        ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
00273
00274 #define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
00275                                        ((LENGTH) == CRC_POLYLENGTH_16B) || \
00276                                        ((LENGTH) == CRC_POLYLENGTH_8B)  || \
00277                                        ((LENGTH) == CRC_POLYLENGTH_7B))
00278
00279 #define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
00280                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
00281                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Include CRC HAL Extended module */
00288 #include "stm32g0xx_hal_crc_ex.h"
00289
00290 /* Exported functions --------------------------------------------------------*/
00291 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00292   * @{
00293   */
00294
00295 /* Initialization and de-initialization functions  ****************************/
00296 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00297   * @{
00298   */
00299 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00300 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
00301 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00302 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00303 /**
00304   * @}
00305   */
00306
00307 /* Peripheral Control functions ***********************************************/
00308 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00309   * @{
00310   */
00311 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00312 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00313 /**
00314   * @}
00315   */
00316
00317 /* Peripheral State and Error functions ***************************************/
00318 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00319   * @{
00320   */
00321 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 #ifdef __cplusplus
00339 }
00340 #endif
00341
00342 #endif /* STM32G0xx_HAL_CRC_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_crc_ex.c Source File

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stm32g0xx_hal_crc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_crc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended CRC HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the CRC peripheral.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * Copyright (c) 2018 STMicroelectronics.
00013   * All rights reserved.
00014   *
00015   * This software is licensed under terms that can be found in the LICENSE file
00016   * in the root directory of this software component.
00017   * If no LICENSE file comes with this software, it is provided AS-IS.
00018   *
00019   ******************************************************************************
00020   @verbatim
00021 ================================================================================
00022             ##### How to use this driver #####
00023 ================================================================================
00024     [..]
00025          (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
00026          (+) Configure Input or Output data inversion
00027
00028   @endverbatim
00029   ******************************************************************************
00030   */
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32g0xx_hal.h"
00034
00035 /** @addtogroup STM32G0xx_HAL_Driver
00036   * @{
00037   */
00038
00039 /** @defgroup CRCEx CRCEx
00040   * @brief CRC Extended HAL module driver
00041   * @{
00042   */
00043
00044 #ifdef HAL_CRC_MODULE_ENABLED
00045
00046 /* Private typedef -----------------------------------------------------------*/
00047 /* Private define ------------------------------------------------------------*/
00048 /* Private macro -------------------------------------------------------------*/
00049 /* Private variables ---------------------------------------------------------*/
00050 /* Private function prototypes -----------------------------------------------*/
00051 /* Exported functions --------------------------------------------------------*/
00052
00053 /** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
00054   * @{
00055   */
00056
00057 /** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
00058   * @brief    Extended Initialization and Configuration functions.
00059   *
00060 @verbatim
00061  ===============================================================================
00062             ##### Extended configuration functions #####
00063  ===============================================================================
00064     [..]  This section provides functions allowing to:
00065       (+) Configure the generating polynomial
00066       (+) Configure the input data inversion
00067       (+) Configure the output data inversion
00068
00069 @endverbatim
00070   * @{
00071   */
00072
00073
00074 /**
00075   * @brief  Initialize the CRC polynomial if different from default one.
00076   * @param  hcrc CRC handle
00077   * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
00078   *         This parameter is written in normal representation, e.g.
00079   *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00080   *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
00081   * @param  PolyLength CRC polynomial length.
00082   *         This parameter can be one of the following values:
00083   *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
00084   *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
00085   *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
00086   *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
00087   * @retval HAL status
00088   */
00089 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
00090 {
00091   HAL_StatusTypeDef status = HAL_OK;
00092   uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
00093
00094   /* Check the parameters */
00095   assert_param(IS_CRC_POL_LENGTH(PolyLength));
00096
00097   /* check polynomial definition vs polynomial size:
00098    * polynomial length must be aligned with polynomial
00099    * definition. HAL_ERROR is reported if Pol degree is
00100    * larger than that indicated by PolyLength.
00101    * Look for MSB position: msb will contain the degree of
00102    *  the second to the largest polynomial member. E.g., for
00103    *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
00104   while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
00105   {
00106   }
00107
00108   switch (PolyLength)
00109   {
00110     case CRC_POLYLENGTH_7B:
00111       if (msb >= HAL_CRC_LENGTH_7B)
00112       {
00113         status =   HAL_ERROR;
00114       }
00115       break;
00116     case CRC_POLYLENGTH_8B:
00117       if (msb >= HAL_CRC_LENGTH_8B)
00118       {
00119         status =   HAL_ERROR;
00120       }
00121       break;
00122     case CRC_POLYLENGTH_16B:
00123       if (msb >= HAL_CRC_LENGTH_16B)
00124       {
00125         status =   HAL_ERROR;
00126       }
00127       break;
00128
00129     case CRC_POLYLENGTH_32B:
00130       /* no polynomial definition vs. polynomial length issue possible */
00131       break;
00132     default:
00133       status =  HAL_ERROR;
00134       break;
00135   }
00136   if (status == HAL_OK)
00137   {
00138     /* set generating polynomial */
00139     WRITE_REG(hcrc->Instance->POL, Pol);
00140
00141     /* set generating polynomial size */
00142     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
00143   }
00144   /* Return function status */
00145   return status;
00146 }
00147
00148 /**
00149   * @brief  Set the Reverse Input data mode.
00150   * @param  hcrc CRC handle
00151   * @param  InputReverseMode Input Data inversion mode.
00152   *         This parameter can be one of the following values:
00153   *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
00154   *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
00155   *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
00156   *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
00160 {
00161   /* Check the parameters */
00162   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
00163
00164   /* Change CRC peripheral state */
00165   hcrc->State = HAL_CRC_STATE_BUSY;
00166
00167   /* set input data inversion mode */
00168   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
00169   /* Change CRC peripheral state */
00170   hcrc->State = HAL_CRC_STATE_READY;
00171
00172   /* Return function status */
00173   return HAL_OK;
00174 }
00175
00176 /**
00177   * @brief  Set the Reverse Output data mode.
00178   * @param  hcrc CRC handle
00179   * @param  OutputReverseMode Output Data inversion mode.
00180   *         This parameter can be one of the following values:
00181   *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
00182   *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
00183   * @retval HAL status
00184   */
00185 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
00186 {
00187   /* Check the parameters */
00188   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
00189
00190   /* Change CRC peripheral state */
00191   hcrc->State = HAL_CRC_STATE_BUSY;
00192
00193   /* set output data inversion mode */
00194   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
00195
00196   /* Change CRC peripheral state */
00197   hcrc->State = HAL_CRC_STATE_READY;
00198
00199   /* Return function status */
00200   return HAL_OK;
00201 }
00202
00203
00204
00205
00206 /**
00207   * @}
00208   */
00209
00210
00211 /**
00212   * @}
00213   */
00214
00215
00216 #endif /* HAL_CRC_MODULE_ENABLED */
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_crc_ex.h Source File

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stm32g0xx_hal_crc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_crc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_CRC_EX_H
00021 #define STM32G0xx_HAL_CRC_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup CRCEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
00041   * @{
00042   */
00043
00044 /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
00045   * @{
00046   */
00047 #define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
00048 #define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
00049 #define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
00050 #define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
00056   * @{
00057   */
00058 #define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
00059 #define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
00060 /**
00061   * @}
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068 /* Exported macro ------------------------------------------------------------*/
00069 /** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
00070   * @{
00071   */
00072
00073 /**
00074   * @brief  Set CRC output reversal
00075   * @param  __HANDLE__ CRC handle
00076   * @retval None
00077   */
00078 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
00079
00080 /**
00081   * @brief  Unset CRC output reversal
00082   * @param  __HANDLE__ CRC handle
00083   * @retval None
00084   */
00085 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
00086
00087 /**
00088   * @brief  Set CRC non-default polynomial
00089   * @param  __HANDLE__ CRC handle
00090   * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
00091   * @retval None
00092   */
00093 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Private macros --------------------------------------------------------*/
00100 /** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
00101   * @{
00102   */
00103
00104 #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
00105                                                    ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
00106                                                    ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
00107                                                    ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
00108
00109 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
00110                                                    ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
00111
00112 /**
00113   * @}
00114   */
00115
00116 /* Exported functions --------------------------------------------------------*/
00117
00118 /** @addtogroup CRCEx_Exported_Functions
00119   * @{
00120   */
00121
00122 /** @addtogroup CRCEx_Exported_Functions_Group1
00123   * @{
00124   */
00125 /* Initialization and de-initialization functions  ****************************/
00126 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
00127 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
00128 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
00129
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146 #ifdef __cplusplus
00147 }
00148 #endif
00149
00150 #endif /* STM32G0xx_HAL_CRC_EX_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cryp.c Source File

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stm32g0xx_hal_cryp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_cryp.c
00004   * @author  MCD Application Team
00005   * @brief   CRYP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cryptography (CRYP) peripheral:
00008   *           + Initialization, de-initialization, set config and get config  functions
00009   *           + AES processing functions
00010   *           + DMA callback functions
00011   *           + CRYP IRQ handler management
00012   *           + Peripheral State functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2018 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                      ##### How to use this driver #####
00028   ==============================================================================
00029     [..]
00030       The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows:
00031
00032       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00033          (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
00034          (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
00035              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00036              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00037              (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00038          (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
00039              (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
00040              (+++) Configure and enable two DMA streams one for managing data transfer from
00041                  memory to peripheral (input stream) and another stream for managing data
00042                  transfer from peripheral to memory (output stream)
00043              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00044                  using  __HAL_LINKDMA()
00045              (+++) Configure the priority and enable the NVIC for the transfer complete
00046                  interrupt on the two DMA channels. The output channel should have higher
00047                  priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00048
00049       (#)Initialize the CRYP according to the specified parameters :
00050          (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
00051          (##) The key size: 128, 192 or 256.
00052          (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
00053          (##) The initialization vector (counter). It is not used in ECB mode.
00054          (##) The key buffer used for encryption/decryption.
00055              (+++) In some specific configurations, the key is written by the application
00056                    code out of the HAL scope. In that case, user can still resort to the
00057                    HAL APIs as usual but must make sure that pKey pointer is set to NULL.
00058          (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
00059                algorithms) is in words or bytes.
00060          (##) The Header used only in AES GCM and CCM Algorithm for authentication.
00061          (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field.
00062          (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes.
00063          (##) The B0 block is the first authentication block used only in AES CCM mode.
00064          (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).
00065
00066       (#)Three processing (encryption/decryption) functions are available:
00067          (##) Polling mode: encryption and decryption APIs are blocking functions
00068               i.e. they process the data and wait till the processing is finished,
00069               e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
00070          (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00071               i.e. they process the data under interrupt,
00072               e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
00073          (##) DMA mode: encryption and decryption APIs are not blocking functions
00074               i.e. the data transfer is ensured by DMA,
00075               e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
00076
00077       (#)When the processing function is called at first time after HAL_CRYP_Init()
00078          the CRYP peripheral is configured and processes the buffer in input.
00079          At second call, no need to Initialize the CRYP, user have to get current configuration via
00080          HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
00081          new parametres, finally user can  start encryption/decryption.
00082
00083        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00084
00085        (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
00086           without having to configure again the Key or the Initialization Vector between each API call,
00087           the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
00088           Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
00089           or HAL_CRYP_Decrypt_DMA().
00090
00091     [..]
00092       The cryptographic processor supports following standards:
00093       (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 peripheral:
00094          (##)64-bit data block processing
00095          (##) chaining modes supported :
00096              (+++)  Electronic Code Book(ECB)
00097              (+++)  Cipher Block Chaining (CBC)
00098          (##) keys length supported :64-bit, 128-bit and 192-bit.
00099       (#) The advanced encryption standard (AES) supported  by CRYP1 & TinyAES peripheral:
00100          (##)128-bit data block processing
00101          (##) chaining modes supported :
00102              (+++)  Electronic Code Book(ECB)
00103              (+++)  Cipher Block Chaining (CBC)
00104              (+++)  Counter mode (CTR)
00105              (+++)  Galois/counter mode (GCM/GMAC)
00106              (+++)  Counter with Cipher Block Chaining-Message(CCM)
00107          (##) keys length Supported :
00108              (+++) for CRYP1 peripheral: 128-bit, 192-bit and 256-bit.
00109              (+++) for TinyAES peripheral:  128-bit and 256-bit
00110
00111     [..]
00112     (@) Specific care must be taken to format the key and the Initialization Vector IV!
00113
00114     [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
00115          b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
00116          (+) as a sequence of words where the MSB word comes first (occupies the
00117            lowest memory address)
00118           (++)   address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96
00119           (++)   address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64
00120           (++)   address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32
00121           (++)   address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0
00122      [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
00123          The 4 32-bit words that make the key must be stored as follows in MCU memory:
00124           (+)    address n+0 : 0x B15 B14 B13 B12
00125           (+)    address n+4 : 0x B11 B10 B9 B8
00126           (+)    address n+8 : 0x B7 B6 B5 B4
00127           (+)    address n+C : 0x B3 B2 B1 B0
00128      [..]  which leads to the expected setting
00129        (+)       AES_KEYR3 = 0x B15 B14 B13 B12
00130        (+)       AES_KEYR2 = 0x B11 B10 B9 B8
00131        (+)       AES_KEYR1 = 0x B7 B6 B5 B4
00132        (+)       AES_KEYR0 = 0x B3 B2 B1 B0
00133
00134     [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
00135           The 8 32-bit words that make the key must be stored as follows in MCU memory:
00136           (+)    address n+00 : 0x B31 B30 B29 B28
00137           (+)    address n+04 : 0x B27 B26 B25 B24
00138           (+)    address n+08 : 0x B23 B22 B21 B20
00139           (+)    address n+0C : 0x B19 B18 B17 B16
00140           (+)    address n+10 : 0x B15 B14 B13 B12
00141           (+)    address n+14 : 0x B11 B10 B9 B8
00142           (+)    address n+18 : 0x B7 B6 B5 B4
00143           (+)    address n+1C : 0x B3 B2 B1 B0
00144      [..]  which leads to the expected setting
00145        (+)       AES_KEYR7 = 0x B31 B30 B29 B28
00146        (+)       AES_KEYR6 = 0x B27 B26 B25 B24
00147        (+)       AES_KEYR5 = 0x B23 B22 B21 B20
00148        (+)       AES_KEYR4 = 0x B19 B18 B17 B16
00149        (+)       AES_KEYR3 = 0x B15 B14 B13 B12
00150        (+)       AES_KEYR2 = 0x B11 B10 B9 B8
00151        (+)       AES_KEYR1 = 0x B7 B6 B5 B4
00152        (+)       AES_KEYR0 = 0x B3 B2 B1 B0
00153
00154     [..] Initialization Vector IV (4 32-bit words) format must follow the same as
00155          that of a 128-bit long key.
00156
00157     [..] Note that key and IV registers are not sensitive to swap mode selection.
00158
00159     [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 and TinyAES peripherals:
00160       (#)  Algorithm supported :
00161          (##) Galois/counter mode (GCM)
00162          (##) Galois message authentication code (GMAC) :is exactly the same as
00163               GCM algorithm composed only by an header.
00164       (#)  Four phases are performed in GCM :
00165          (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
00166          (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
00167           computation only.
00168          (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
00169           encryption + data XORing. It works in a similar way for ciphertext (C).
00170          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00171       (#)  structure of message construction in GCM is defined as below  :
00172          (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
00173          (##) The authenticated header A (also knows as Additional Authentication Data AAD)
00174           this part of the message is only authenticated, not encrypted.
00175          (##) The plaintext message P is both authenticated and encrypted as ciphertext.
00176           GCM standard specifies that ciphertext has same bit length as the plaintext.
00177          (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
00178           (on 64 bits)
00179
00180     [..]  A more detailed description of the GCM message structure is available below.
00181
00182     [..]  This section describe The AES Counter with Cipher Block Chaining-Message
00183           Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
00184       (#)  Specific parameters for CCM  :
00185
00186          (##) B0 block  : follows NIST Special Publication 800-38C,
00187          (##) B1 block (header)
00188          (##) CTRx block  : control blocks
00189
00190     [..]  A detailed description of the CCM message structure is available below.
00191
00192       (#)  Four phases are performed in CCM for CRYP1 peripheral:
00193          (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
00194          (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
00195           computation only.
00196          (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
00197           encryption + data XORing. It works in a similar way for ciphertext (C).
00198          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00199       (#)    CCM in TinyAES peripheral:
00200          (##) To perform message payload encryption or decryption AES is configured in CTR mode.
00201          (##) For authentication two phases are performed :
00202           - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
00203           only cleartext payload (not the ciphertext payload) is used and no outpout.
00204          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00205
00206   *** Callback registration ***
00207   =============================
00208
00209   [..]
00210   The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
00211   allows the user to configure dynamically the driver callbacks.
00212   Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
00213   to register an interrupt callback.
00214
00215   [..]
00216   Function HAL_CRYP_RegisterCallback() allows to register following callbacks:
00217     (+) InCpltCallback     :  Input FIFO transfer completed callback.
00218     (+) OutCpltCallback    : Output FIFO transfer completed callback.
00219     (+) ErrorCallback      : callback for error detection.
00220     (+) MspInitCallback    : CRYP MspInit.
00221     (+) MspDeInitCallback  : CRYP MspDeInit.
00222   This function takes as parameters the HAL peripheral handle, the Callback ID
00223   and a pointer to the user callback function.
00224
00225   [..]
00226   Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default
00227   weak function.
00228   HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00229   and the Callback ID.
00230   This function allows to reset following callbacks:
00231     (+) InCpltCallback     :  Input FIFO transfer completed callback.
00232     (+) OutCpltCallback    : Output FIFO transfer completed callback.
00233     (+) ErrorCallback      : callback for error detection.
00234     (+) MspInitCallback    : CRYP MspInit.
00235     (+) MspDeInitCallback  : CRYP MspDeInit.
00236
00237   [..]
00238   By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
00239   all callbacks are set to the corresponding weak functions :
00240   examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback().
00241   Exception done for MspInit and MspDeInit functions that are
00242   reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when
00243   these callbacks are null (not registered beforehand).
00244   if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit()
00245   keep and use the user MspInit/MspDeInit functions (registered beforehand)
00246
00247   [..]
00248   Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
00249   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
00250   in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
00251   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00252   In that case first register the MspInit/MspDeInit user callbacks
00253   using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit()
00254   or HAL_CRYP_Init() function.
00255
00256   [..]
00257   When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
00258   not defined, the callback registration feature is not available and all callbacks
00259   are set to the corresponding weak functions.
00260
00261
00262   *** Suspend/Resume feature ***
00263   ==============================
00264
00265   [..]
00266   The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
00267   allows the user to resort to the suspend/resume feature.
00268   A low priority block processing can be suspended to process a high priority block
00269   instead. When the high priority block processing is over, the low priority block
00270   processing can be resumed, restarting from the point where it was suspended. This
00271   feature is applicable only in non-blocking interrupt mode.
00272
00273   [..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block
00274   processing. This API manages the hardware block processing suspension and saves all the
00275   internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion,
00276   the user can launch the processing of any other block (high priority block processing).
00277
00278   [..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume()
00279   to resume the low priority block processing. Ciphering (or deciphering) restarts from
00280   the suspension point and ends as usual.
00281
00282   [..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late
00283   (i.e when the low priority block processing is about to end). There is no use to
00284   suspend the tag generation processing for authentication algorithms.
00285
00286     [..]
00287     (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user),
00288         the block processing suspension/resumption mechanism is NOT applicable.
00289
00290     [..]
00291     (@) If the Key and Initialization Vector are configured only once and configuration is
00292         skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE),
00293         the block processing suspension/resumption mechanism is NOT applicable.
00294
00295   @endverbatim
00296   ******************************************************************************
00297   */
00298
00299 /* Includes ------------------------------------------------------------------*/
00300 #include "stm32g0xx_hal.h"
00301
00302 /** @addtogroup STM32G0xx_HAL_Driver
00303   * @{
00304   */
00305
00306 /** @addtogroup CRYP
00307   * @{
00308   */
00309
00310 #if defined(AES)
00311 #ifdef HAL_CRYP_MODULE_ENABLED
00312
00313 /* Private typedef -----------------------------------------------------------*/
00314 /* Private define ------------------------------------------------------------*/
00315 /** @addtogroup CRYP_Private_Defines
00316   * @{
00317   */
00318 #define CRYP_TIMEOUT_KEYPREPARATION      82U         /* The latency of key preparation operation is 82 clock cycles.*/
00319 #define CRYP_TIMEOUT_GCMCCMINITPHASE     299U        /* The latency of  GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
00320 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE   290U        /* The latency of  GCM/CCM header phase is 290 clock cycles.*/
00321
00322 #define CRYP_PHASE_READY                 0x00000001U /*!< CRYP peripheral is ready for initialization. */
00323 #define CRYP_PHASE_PROCESS               0x00000002U /*!< CRYP peripheral is in processing phase */
00324 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00325 #define  CRYP_PHASE_HEADER_SUSPENDED     0x00000004U    /*!< GCM/GMAC/CCM header phase is suspended */
00326 #define  CRYP_PHASE_PAYLOAD_SUSPENDED    0x00000005U    /*!< GCM/CCM payload phase is suspended     */
00327 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00328 #define  CRYP_PHASE_HEADER_DMA_FEED      0x00000006U    /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */
00329
00330 #define CRYP_OPERATINGMODE_ENCRYPT                   0x00000000U     /*!< Encryption mode(Mode 1)  */
00331 #define CRYP_OPERATINGMODE_KEYDERIVATION             AES_CR_MODE_0   /*!< Key derivation mode  only used when performing ECB and CBC decryptions (Mode 2) */
00332 #define CRYP_OPERATINGMODE_DECRYPT                   AES_CR_MODE_1   /*!< Decryption    (Mode 3)    */
00333 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE     /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
00334 #define CRYP_PHASE_INIT                              0x00000000U     /*!< GCM/GMAC (or CCM) init phase */
00335 #define CRYP_PHASE_HEADER                            AES_CR_GCMPH_0  /*!< GCM/GMAC or CCM header phase */
00336 #define CRYP_PHASE_PAYLOAD                           AES_CR_GCMPH_1  /*!< GCM(/CCM) payload phase      */
00337 #define CRYP_PHASE_FINAL                             AES_CR_GCMPH    /*!< GCM/GMAC or CCM  final phase */
00338
00339 /*  CTR1 information to use in CCM algorithm */
00340 #define CRYP_CCM_CTR1_0                  0x07FFFFFFU
00341 #define CRYP_CCM_CTR1_1                  0xFFFFFF00U
00342 #define CRYP_CCM_CTR1_2                  0x00000001U
00343
00344 /**
00345   * @}
00346   */
00347
00348 /* Private macro -------------------------------------------------------------*/
00349 /** @addtogroup CRYP_Private_Macros
00350   * @{
00351   */
00352
00353 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__)   MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
00354
00355 /**
00356   * @}
00357   */
00358
00359 /* Private struct -------------------------------------------------------------*/
00360 /* Private variables ---------------------------------------------------------*/
00361 /* Private function prototypes -----------------------------------------------*/
00362 /** @addtogroup CRYP_Private_Functions
00363   * @{
00364   */
00365
00366 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00367 static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size);
00368 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
00369 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
00370 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
00371 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
00372 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
00373 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00374 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
00375 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
00376 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
00377 static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp);
00378 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00379 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00380 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00381 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00382 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00383 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00384 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
00385 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00386 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00387 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
00388 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
00389 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
00390 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00391 static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00392 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00393 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
00394 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
00395 static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
00396 static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
00397 static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize);
00398 static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize);
00399 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
00400 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00401
00402
00403 /**
00404   * @}
00405   */
00406
00407 /* Exported functions ---------------------------------------------------------*/
00408
00409 /** @addtogroup CRYP_Exported_Functions
00410   * @{
00411   */
00412
00413 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
00414   * @brief    Initialization and Configuration functions.
00415   *
00416 @verbatim
00417   ========================================================================================
00418      ##### Initialization, de-initialization and Set and Get configuration functions #####
00419   ========================================================================================
00420     [..]  This section provides functions allowing to:
00421       (+) Initialize the CRYP
00422       (+) DeInitialize the CRYP
00423       (+) Initialize the CRYP MSP
00424       (+) DeInitialize the CRYP MSP
00425       (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
00426           Parameters which are configured in This section are :
00427           (++) Key size
00428           (++) Data Type : 32,16, 8 or 1bit
00429           (++) AlgoMode :
00430               (+++) for CRYP1 peripheral :
00431                  ECB and CBC in DES/TDES Standard
00432                  ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
00433               (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
00434       (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
00435
00436 @endverbatim
00437   * @{
00438   */
00439
00440 /**
00441   * @brief  Initializes the CRYP according to the specified
00442   *         parameters in the CRYP_ConfigTypeDef and creates the associated handle.
00443   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00444   *         the configuration information for CRYP module
00445   * @retval HAL status
00446   */
00447 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
00448 {
00449   /* Check the CRYP handle allocation */
00450   if (hcryp == NULL)
00451   {
00452     return HAL_ERROR;
00453   }
00454
00455   /* Check parameters */
00456   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
00457   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
00458   assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
00459   assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
00460
00461 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00462   if (hcryp->State == HAL_CRYP_STATE_RESET)
00463   {
00464     /* Allocate lock resource and initialize it */
00465     hcryp->Lock = HAL_UNLOCKED;
00466
00467     hcryp->InCpltCallback  = HAL_CRYP_InCpltCallback;  /* Legacy weak InCpltCallback   */
00468     hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback  */
00469     hcryp->ErrorCallback   = HAL_CRYP_ErrorCallback;   /* Legacy weak ErrorCallback    */
00470
00471     if (hcryp->MspInitCallback == NULL)
00472     {
00473       hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit  */
00474     }
00475
00476     /* Init the low level hardware */
00477     hcryp->MspInitCallback(hcryp);
00478   }
00479 #else
00480   if (hcryp->State == HAL_CRYP_STATE_RESET)
00481   {
00482     /* Allocate lock resource and initialize it */
00483     hcryp->Lock = HAL_UNLOCKED;
00484
00485     /* Init the low level hardware */
00486     HAL_CRYP_MspInit(hcryp);
00487   }
00488 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00489
00490   /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and Algorithm */
00491   MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00492
00493   /* Reset Error Code field */
00494   hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00495
00496   /* Reset peripheral Key and IV configuration flag */
00497   hcryp->KeyIVConfig = 0U;
00498
00499   /* Change the CRYP state */
00500   hcryp->State = HAL_CRYP_STATE_READY;
00501
00502   /* Set the default CRYP phase */
00503   hcryp->Phase = CRYP_PHASE_READY;
00504
00505   /* Return function status */
00506   return HAL_OK;
00507 }
00508
00509 /**
00510   * @brief  De-Initializes the CRYP peripheral.
00511   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00512   *         the configuration information for CRYP module
00513   * @retval HAL status
00514 */
00515 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
00516 {
00517   /* Check the CRYP handle allocation */
00518   if (hcryp == NULL)
00519   {
00520     return HAL_ERROR;
00521   }
00522
00523   /* Set the default CRYP phase */
00524   hcryp->Phase = CRYP_PHASE_READY;
00525
00526   /* Reset CrypInCount and CrypOutCount */
00527   hcryp->CrypInCount = 0;
00528   hcryp->CrypOutCount = 0;
00529   hcryp->CrypHeaderCount = 0;
00530
00531   /* Disable the CRYP peripheral clock */
00532   __HAL_CRYP_DISABLE(hcryp);
00533
00534 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00535
00536   if (hcryp->MspDeInitCallback == NULL)
00537   {
00538     hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit  */
00539   }
00540   /* DeInit the low level hardware */
00541   hcryp->MspDeInitCallback(hcryp);
00542
00543 #else
00544
00545   /* DeInit the low level hardware: CLOCK, NVIC.*/
00546   HAL_CRYP_MspDeInit(hcryp);
00547
00548 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00549
00550   /* Change the CRYP state */
00551   hcryp->State = HAL_CRYP_STATE_RESET;
00552
00553   /* Release Lock */
00554   __HAL_UNLOCK(hcryp);
00555
00556   /* Return function status */
00557   return HAL_OK;
00558 }
00559
00560 /**
00561   * @brief  Configure the CRYP according to the specified
00562   *         parameters in the CRYP_ConfigTypeDef
00563   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
00564   * @param  pConf pointer to a CRYP_ConfigTypeDef structure that contains
00565   *         the configuration information for CRYP module
00566   * @retval HAL status
00567   */
00568 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
00569 {
00570   /* Check the CRYP handle allocation */
00571   if ((hcryp == NULL) || (pConf == NULL))
00572   {
00573     return HAL_ERROR;
00574   }
00575
00576   /* Check parameters */
00577   assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
00578   assert_param(IS_CRYP_DATATYPE(pConf->DataType));
00579   assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
00580
00581   if (hcryp->State == HAL_CRYP_STATE_READY)
00582   {
00583     /* Change the CRYP state */
00584     hcryp->State = HAL_CRYP_STATE_BUSY;
00585
00586     /* Process locked */
00587     __HAL_LOCK(hcryp);
00588
00589     /* Set  CRYP parameters  */
00590     hcryp->Init.DataType        = pConf->DataType;
00591     hcryp->Init.pKey            = pConf->pKey;
00592     hcryp->Init.Algorithm       = pConf->Algorithm;
00593     hcryp->Init.KeySize         = pConf->KeySize;
00594     hcryp->Init.pInitVect       = pConf->pInitVect;
00595     hcryp->Init.Header          = pConf->Header;
00596     hcryp->Init.HeaderSize      = pConf->HeaderSize;
00597     hcryp->Init.B0              = pConf->B0;
00598     hcryp->Init.DataWidthUnit   = pConf->DataWidthUnit;
00599     hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
00600     hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
00601
00602     /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/
00603     MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00604
00605     /*clear error flags*/
00606     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
00607
00608     /* Process Unlocked */
00609     __HAL_UNLOCK(hcryp);
00610
00611     /* Reset Error Code field */
00612     hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00613
00614     /* Change the CRYP state */
00615     hcryp->State = HAL_CRYP_STATE_READY;
00616
00617     /* Set the default CRYP phase */
00618     hcryp->Phase = CRYP_PHASE_READY;
00619
00620     /* Return function status */
00621     return HAL_OK;
00622   }
00623   else
00624   {
00625     /* Process Unlocked */
00626     __HAL_UNLOCK(hcryp);
00627
00628     /* Busy error code field */
00629     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00630     return HAL_ERROR;
00631   }
00632 }
00633
00634 /**
00635   * @brief  Get CRYP Configuration parameters in associated handle.
00636   * @param  pConf pointer to a CRYP_ConfigTypeDef structure
00637   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00638   *         the configuration information for CRYP module
00639   * @retval HAL status
00640   */
00641 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
00642 {
00643   /* Check the CRYP handle allocation */
00644   if ((hcryp == NULL) || (pConf == NULL))
00645   {
00646     return HAL_ERROR;
00647   }
00648
00649   if (hcryp->State == HAL_CRYP_STATE_READY)
00650   {
00651     /* Change the CRYP state */
00652     hcryp->State = HAL_CRYP_STATE_BUSY;
00653
00654     /* Process locked */
00655     __HAL_LOCK(hcryp);
00656
00657     /* Get  CRYP parameters  */
00658     pConf->DataType        = hcryp->Init.DataType;
00659     pConf->pKey            = hcryp->Init.pKey;
00660     pConf->Algorithm       = hcryp->Init.Algorithm;
00661     pConf->KeySize         = hcryp->Init.KeySize ;
00662     pConf->pInitVect       = hcryp->Init.pInitVect;
00663     pConf->Header          = hcryp->Init.Header ;
00664     pConf->HeaderSize      = hcryp->Init.HeaderSize;
00665     pConf->B0              = hcryp->Init.B0;
00666     pConf->DataWidthUnit   = hcryp->Init.DataWidthUnit;
00667     pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
00668     pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
00669
00670     /* Process Unlocked */
00671     __HAL_UNLOCK(hcryp);
00672
00673     /* Change the CRYP state */
00674     hcryp->State = HAL_CRYP_STATE_READY;
00675
00676     /* Return function status */
00677     return HAL_OK;
00678   }
00679   else
00680   {
00681     /* Process Unlocked */
00682     __HAL_UNLOCK(hcryp);
00683
00684     /* Busy error code field */
00685     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00686     return HAL_ERROR;
00687   }
00688 }
00689 /**
00690   * @brief  Initializes the CRYP MSP.
00691   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00692   *         the configuration information for CRYP module
00693   * @retval None
00694   */
00695 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
00696 {
00697   /* Prevent unused argument(s) compilation warning */
00698   UNUSED(hcryp);
00699
00700   /* NOTE : This function should not be modified; when the callback is needed,
00701             the HAL_CRYP_MspInit can be implemented in the user file
00702    */
00703 }
00704
00705 /**
00706   * @brief  DeInitializes CRYP MSP.
00707   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00708   *         the configuration information for CRYP module
00709   * @retval None
00710   */
00711 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
00712 {
00713   /* Prevent unused argument(s) compilation warning */
00714   UNUSED(hcryp);
00715
00716   /* NOTE : This function should not be modified; when the callback is needed,
00717             the HAL_CRYP_MspDeInit can be implemented in the user file
00718    */
00719 }
00720
00721 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00722 /**
00723   * @brief  Register a User CRYP Callback
00724   *         To be used instead of the weak predefined callback
00725   * @param hcryp cryp handle
00726   * @param CallbackID ID of the callback to be registered
00727   *        This parameter can be one of the following values:
00728   *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
00729   *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
00730   *          @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
00731   *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
00732   *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
00733   * @param pCallback pointer to the Callback function
00734   * @retval status
00735   */
00736 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
00737 {
00738   HAL_StatusTypeDef status = HAL_OK;
00739
00740   if (pCallback == NULL)
00741   {
00742     /* Update the error code */
00743     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00744
00745     return HAL_ERROR;
00746   }
00747   /* Process locked */
00748   __HAL_LOCK(hcryp);
00749
00750   if (hcryp->State == HAL_CRYP_STATE_READY)
00751   {
00752     switch (CallbackID)
00753     {
00754       case HAL_CRYP_INPUT_COMPLETE_CB_ID :
00755         hcryp->InCpltCallback = pCallback;
00756         break;
00757
00758       case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
00759         hcryp->OutCpltCallback = pCallback;
00760         break;
00761
00762       case HAL_CRYP_ERROR_CB_ID :
00763         hcryp->ErrorCallback = pCallback;
00764         break;
00765
00766       case HAL_CRYP_MSPINIT_CB_ID :
00767         hcryp->MspInitCallback = pCallback;
00768         break;
00769
00770       case HAL_CRYP_MSPDEINIT_CB_ID :
00771         hcryp->MspDeInitCallback = pCallback;
00772         break;
00773
00774       default :
00775         /* Update the error code */
00776         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00777         /* Return error status */
00778         status =  HAL_ERROR;
00779         break;
00780     }
00781   }
00782   else if (hcryp->State == HAL_CRYP_STATE_RESET)
00783   {
00784     switch (CallbackID)
00785     {
00786       case HAL_CRYP_MSPINIT_CB_ID :
00787         hcryp->MspInitCallback = pCallback;
00788         break;
00789
00790       case HAL_CRYP_MSPDEINIT_CB_ID :
00791         hcryp->MspDeInitCallback = pCallback;
00792         break;
00793
00794       default :
00795         /* Update the error code */
00796         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00797         /* Return error status */
00798         status =  HAL_ERROR;
00799         break;
00800     }
00801   }
00802   else
00803   {
00804     /* Update the error code */
00805     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00806     /* Return error status */
00807     status =  HAL_ERROR;
00808   }
00809
00810   /* Release Lock */
00811   __HAL_UNLOCK(hcryp);
00812
00813   return status;
00814 }
00815
00816 /**
00817   * @brief  Unregister an CRYP Callback
00818   *         CRYP callback is redirected to the weak predefined callback
00819   * @param hcryp cryp handle
00820   * @param CallbackID ID of the callback to be unregistered
00821   *        This parameter can be one of the following values:
00822   *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
00823   *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
00824   *          @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
00825   *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
00826   *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
00827   * @retval status
00828   */
00829 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
00830 {
00831   HAL_StatusTypeDef status = HAL_OK;
00832
00833   /* Process locked */
00834   __HAL_LOCK(hcryp);
00835
00836   if (hcryp->State == HAL_CRYP_STATE_READY)
00837   {
00838     switch (CallbackID)
00839     {
00840       case HAL_CRYP_INPUT_COMPLETE_CB_ID :
00841         hcryp->InCpltCallback = HAL_CRYP_InCpltCallback;  /* Legacy weak  InCpltCallback  */
00842         break;
00843
00844       case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
00845         hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback;         /* Legacy weak OutCpltCallback       */
00846         break;
00847
00848       case HAL_CRYP_ERROR_CB_ID :
00849         hcryp->ErrorCallback = HAL_CRYP_ErrorCallback;           /* Legacy weak ErrorCallback        */
00850         break;
00851
00852       case HAL_CRYP_MSPINIT_CB_ID :
00853         hcryp->MspInitCallback = HAL_CRYP_MspInit;
00854         break;
00855
00856       case HAL_CRYP_MSPDEINIT_CB_ID :
00857         hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
00858         break;
00859
00860       default :
00861         /* Update the error code */
00862         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00863         /* Return error status */
00864         status =  HAL_ERROR;
00865         break;
00866     }
00867   }
00868   else if (hcryp->State == HAL_CRYP_STATE_RESET)
00869   {
00870     switch (CallbackID)
00871     {
00872       case HAL_CRYP_MSPINIT_CB_ID :
00873         hcryp->MspInitCallback = HAL_CRYP_MspInit;
00874         break;
00875
00876       case HAL_CRYP_MSPDEINIT_CB_ID :
00877         hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
00878         break;
00879
00880       default :
00881         /* Update the error code */
00882         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00883         /* Return error status */
00884         status =  HAL_ERROR;
00885         break;
00886     }
00887   }
00888   else
00889   {
00890     /* Update the error code */
00891     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
00892     /* Return error status */
00893     status =  HAL_ERROR;
00894   }
00895
00896   /* Release Lock */
00897   __HAL_UNLOCK(hcryp);
00898
00899   return status;
00900 }
00901 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00902
00903 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00904 /**
00905   * @brief  Request CRYP processing suspension when in interruption mode.
00906   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00907   *         the configuration information for CRYP module.
00908   * @note   Set the handle field SuspendRequest to the appropriate value so that
00909   *         the on-going CRYP processing is suspended as soon as the required
00910   *         conditions are met.
00911   * @note   HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
00912   *         in non-blocking interrupt mode.
00913   * @note   It is advised not to suspend the CRYP processing when the DMA controller
00914   *         is managing the data transfer.
00915   * @retval None
00916   */
00917 void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
00918 {
00919   /* Set Handle SuspendRequest field */
00920   hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
00921 }
00922
00923
00924
00925 /**
00926   * @brief  CRYP processing suspension and peripheral internal parameters storage.
00927   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00928   *         the configuration information for CRYP module
00929   * @note   peripheral internal parameters are stored to be readily available when
00930   *         suspended processing is resumed later on.
00931   * @retval HAL status
00932   */
00933 HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
00934 {
00935   HAL_CRYP_STATETypeDef state;
00936
00937   /* Request suspension */
00938   HAL_CRYP_ProcessSuspend(hcryp);
00939
00940   do
00941   {
00942     state = HAL_CRYP_GetState(hcryp);
00943   } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
00944
00945   if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
00946   {
00947     /* Processing was already over or was about to end. No suspension done */
00948     return HAL_ERROR;
00949   }
00950   else
00951   {
00952     /* Suspend Processing */
00953
00954     /* If authentication algorithms on-going, carry out first saving steps
00955        before disable the peripheral */
00956     if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \
00957          (hcryp->Init.Algorithm == CRYP_AES_CCM))
00958     {
00959         /* Save Suspension registers */
00960         CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
00961         /* Save Key */
00962         CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
00963         /* Save IV */
00964         CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
00965     }
00966     /* Disable AES */
00967     __HAL_CRYP_DISABLE(hcryp);
00968
00969     /* Save low-priority block CRYP handle parameters */
00970     hcryp->Init_saved              = hcryp->Init;
00971     hcryp->pCrypInBuffPtr_saved    = hcryp->pCrypInBuffPtr;
00972     hcryp->pCrypOutBuffPtr_saved   = hcryp->pCrypOutBuffPtr;
00973     hcryp->CrypInCount_saved       = hcryp->CrypInCount;
00974     hcryp->CrypOutCount_saved      = hcryp->CrypOutCount;
00975     hcryp->Phase_saved             = hcryp->Phase;
00976     hcryp->State_saved             = hcryp->State;
00977     hcryp->Size_saved              = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size);
00978     hcryp->SizesSum_saved          = hcryp->SizesSum;
00979     hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation;
00980     hcryp->CrypHeaderCount_saved   = hcryp->CrypHeaderCount;
00981     hcryp->SuspendRequest          = HAL_CRYP_SUSPEND_NONE;
00982
00983     if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
00984         (hcryp->Init.Algorithm == CRYP_AES_CTR))
00985     {
00986       /* Save Initialisation Vector registers */
00987       CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
00988     }
00989
00990     /* Save Control register */
00991     hcryp->CR_saved = hcryp->Instance->CR;
00992
00993   }
00994   return HAL_OK;
00995 }
00996
00997
00998 /**
00999   * @brief  CRYP processing resumption.
01000   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01001   *         the configuration information for CRYP module
01002   * @note   Processing restarts at the exact point where it was suspended, based
01003   *         on the parameters saved at suspension time.
01004   * @retval HAL status
01005   */
01006 HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
01007 {
01008   /* Check the CRYP handle allocation */
01009   if (hcryp == NULL)
01010   {
01011     return HAL_ERROR;
01012   }
01013
01014   if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
01015   {
01016     /* CRYP was not suspended */
01017     return HAL_ERROR;
01018   }
01019   else
01020   {
01021
01022     /* Restore low-priority block CRYP handle parameters */
01023     hcryp->Init            = hcryp->Init_saved;
01024     hcryp->State           = hcryp->State_saved;
01025
01026     /* Chaining algorithms case */
01027     if ((hcryp->Init_saved.Algorithm == CRYP_AES_ECB) || \
01028         (hcryp->Init_saved.Algorithm == CRYP_AES_CBC) || \
01029         (hcryp->Init_saved.Algorithm == CRYP_AES_CTR))
01030     {
01031       /* Restore low-priority block CRYP handle parameters */
01032       hcryp->AutoKeyDerivation = hcryp->AutoKeyDerivation_saved;
01033
01034       if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
01035         (hcryp->Init.Algorithm == CRYP_AES_CTR))
01036       {
01037         hcryp->Init.pInitVect     = hcryp->IV_saved;
01038       }
01039       __HAL_CRYP_DISABLE(hcryp);
01040       (void) HAL_CRYP_Init(hcryp);
01041     }
01042     else    /* Authentication algorithms case */
01043     {
01044       /* Restore low-priority block CRYP handle parameters */
01045       hcryp->Phase           = hcryp->Phase_saved;
01046       hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
01047       hcryp->SizesSum        = hcryp->SizesSum_saved;
01048
01049       /* Disable AES and write-back SUSPxR registers */;
01050       __HAL_CRYP_DISABLE(hcryp);
01051       /* Restore AES Suspend Registers */
01052       CRYP_Write_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
01053       /* Restore Control,  Key and IV Registers, then enable AES */
01054       hcryp->Instance->CR = hcryp->CR_saved;
01055       CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
01056       CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
01057
01058       /* At the same time, set handle state back to READY to be able to resume the AES calculations
01059       without the processing APIs returning HAL_BUSY when called. */
01060       hcryp->State        = HAL_CRYP_STATE_READY;
01061     }
01062
01063
01064     /* Resume low-priority block processing under IT */
01065     hcryp->ResumingFlag = 1U;
01066     if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
01067     {
01068       if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
01069       {
01070         return HAL_ERROR;
01071       }
01072     }
01073     else
01074     {
01075       if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
01076       {
01077         return HAL_ERROR;
01078       }
01079     }
01080   }
01081   return HAL_OK;
01082 }
01083 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
01084
01085 /**
01086   * @}
01087   */
01088
01089 /** @defgroup CRYP_Exported_Functions_Group2 Encryption Decryption functions
01090   * @brief    Encryption Decryption functions.
01091   *
01092 @verbatim
01093   ==============================================================================
01094                       ##### Encrypt Decrypt  functions #####
01095   ==============================================================================
01096     [..]  This section provides API allowing to Encrypt/Decrypt Data following
01097           Standard DES/TDES or AES, and Algorithm configured by the user:
01098       (+) Standard DES/TDES only supported by CRYP1 peripheral, below list of Algorithm supported :
01099            - Electronic Code Book(ECB)
01100            - Cipher Block Chaining (CBC)
01101       (+) Standard AES  supported by CRYP1 peripheral & TinyAES, list of Algorithm supported:
01102            - Electronic Code Book(ECB)
01103            - Cipher Block Chaining (CBC)
01104            - Counter mode (CTR)
01105            - Cipher Block Chaining (CBC)
01106            - Counter mode (CTR)
01107            - Galois/counter mode (GCM)
01108            - Counter with Cipher Block Chaining-Message(CCM)
01109     [..]  Three processing functions are available:
01110       (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
01111       (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
01112       (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
01113
01114 @endverbatim
01115   * @{
01116   */
01117
01118 /* GCM message structure additional details
01119
01120                                   ICB
01121           +-------------------------------------------------------+
01122           |       Initialization vector (IV)      |  Counter      |
01123           |----------------|----------------|-----------|---------|
01124          127              95                63            31       0
01125
01126
01127               Bit Number    Register           Contents
01128               ----------   ---------------       -----------
01129               127 ...96    CRYP_IV1R[31:0]     ICB[127:96]
01130               95  ...64    CRYP_IV1L[31:0]     B0[95:64]
01131               63 ... 32    CRYP_IV0R[31:0]     ICB[63:32]
01132               31 ... 0     CRYP_IV0L[31:0]     ICB[31:0], where 32-bit counter= 0x2
01133
01134
01135
01136                                  GCM last block definition
01137           +-------------------------------------------------------------------+
01138           |  Bit[0]   |  Bit[32]           |  Bit[64]  | Bit[96]              |
01139           |-----------|--------------------|-----------|----------------------|
01140           |   0x0     | Header length[31:0]|     0x0   | Payload length[31:0] |
01141           |-----------|--------------------|-----------|----------------------|
01142
01143 */
01144
01145 /* CCM message blocks description
01146
01147          (##) B0 block  : According to NIST Special Publication 800-38C,
01148             The first block B0 is formatted as follows, where l(m) is encoded in
01149             most-significant-byte first order:
01150
01151                 Octet Number   Contents
01152                 ------------   ---------
01153                 0              Flags
01154                 1 ... 15-q     Nonce N
01155                 16-q ... 15    Q
01156
01157             the Flags field is formatted as follows:
01158
01159                 Bit Number   Contents
01160                 ----------   ----------------------
01161                 7            Reserved (always zero)
01162                 6            Adata
01163                 5 ... 3      (t-2)/2
01164                 2 ... 0      [q-1]3
01165
01166               - Q: a bit string representation of the octet length of P (plaintext)
01167               - q The octet length of the binary representation of the octet length of the payload
01168               - A nonce (N), n The octet length of the where n+q=15.
01169               - Flags: most significant octet containing four flags for control information,
01170               - t The octet length of the MAC.
01171          (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
01172               the associated data length expressed in bytes (a) defined as below:
01173             - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
01174             - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
01175             - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
01176          (##) CTRx block  : control blocks
01177             - Generation of CTR1 from first block B0 information :
01178               equal to B0 with first 5 bits zeroed and most significant bits storing octet
01179               length of P also zeroed, then incremented by one
01180
01181                 Bit Number    Register           Contents
01182                 ----------   ---------------       -----------
01183                 127 ...96    CRYP_IV1R[31:0]     B0[127:96], where Q length bits are set to 0, except for
01184                                                  bit 0 that is set to 1
01185                 95  ...64    CRYP_IV1L[31:0]     B0[95:64]
01186                 63 ... 32    CRYP_IV0R[31:0]     B0[63:32]
01187                 31 ... 0     CRYP_IV0L[31:0]     B0[31:0], where flag bits set to 0
01188
01189             - Generation of CTR0: same as CTR1 with bit[0] set to zero.
01190
01191 */
01192
01193 /**
01194   * @brief  Encryption mode.
01195   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01196   *         the configuration information for CRYP module
01197   * @param  Input Pointer to the input buffer (plaintext)
01198   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01199   * @param  Output Pointer to the output buffer(ciphertext)
01200   * @param  Timeout Specify Timeout value
01201   * @retval HAL status
01202   */
01203 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
01204 {
01205   uint32_t algo;
01206   HAL_StatusTypeDef status;
01207 #ifdef  USE_FULL_ASSERT
01208   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01209
01210   /* Check input buffer size */
01211   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01212 #endif /* USE_FULL_ASSERT */
01213
01214   if (hcryp->State == HAL_CRYP_STATE_READY)
01215   {
01216     /* Change state Busy */
01217     hcryp->State = HAL_CRYP_STATE_BUSY;
01218
01219     /* Process locked */
01220     __HAL_LOCK(hcryp);
01221
01222     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01223     hcryp->CrypInCount = 0U;
01224     hcryp->CrypOutCount = 0U;
01225     hcryp->pCrypInBuffPtr = Input;
01226     hcryp->pCrypOutBuffPtr = Output;
01227
01228     /*  Calculate Size parameter in Byte*/
01229     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01230     {
01231       hcryp->Size = Size * 4U;
01232     }
01233     else
01234     {
01235       hcryp->Size = Size;
01236     }
01237
01238     /* Set the operating mode*/
01239     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01240
01241     /* algo get algorithm selected */
01242     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01243
01244     switch (algo)
01245     {
01246
01247       case CRYP_AES_ECB:
01248       case CRYP_AES_CBC:
01249       case CRYP_AES_CTR:
01250
01251         /* AES encryption */
01252         status = CRYP_AES_Encrypt(hcryp, Timeout);
01253         break;
01254
01255       case CRYP_AES_GCM_GMAC:
01256
01257         /* AES GCM encryption */
01258         status = CRYP_AESGCM_Process(hcryp, Timeout) ;
01259         break;
01260
01261       case CRYP_AES_CCM:
01262
01263         /* AES CCM encryption */
01264         status = CRYP_AESCCM_Process(hcryp, Timeout);
01265         break;
01266
01267       default:
01268         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01269         status = HAL_ERROR;
01270         break;
01271     }
01272
01273     if (status == HAL_OK)
01274     {
01275       /* Change the CRYP peripheral state */
01276       hcryp->State = HAL_CRYP_STATE_READY;
01277
01278       /* Process unlocked */
01279       __HAL_UNLOCK(hcryp);
01280     }
01281   }
01282   else
01283   {
01284     /* Busy error code field */
01285     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01286     status = HAL_ERROR;
01287   }
01288
01289   /* Return function status */
01290   return status;
01291 }
01292
01293 /**
01294   * @brief  Decryption mode.
01295   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01296   *         the configuration information for CRYP module
01297   * @param  Input Pointer to the input buffer (ciphertext )
01298   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01299   * @param  Output Pointer to the output buffer(plaintext)
01300   * @param  Timeout Specify Timeout value
01301   * @retval HAL status
01302   */
01303 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
01304 {
01305   HAL_StatusTypeDef status;
01306   uint32_t algo;
01307 #ifdef  USE_FULL_ASSERT
01308   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01309
01310   /* Check input buffer size */
01311   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01312 #endif /* USE_FULL_ASSERT */
01313
01314   if (hcryp->State == HAL_CRYP_STATE_READY)
01315   {
01316     /* Change state Busy */
01317     hcryp->State = HAL_CRYP_STATE_BUSY;
01318
01319     /* Process locked */
01320     __HAL_LOCK(hcryp);
01321
01322     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr  parameters*/
01323     hcryp->CrypInCount = 0U;
01324     hcryp->CrypOutCount = 0U;
01325     hcryp->pCrypInBuffPtr = Input;
01326     hcryp->pCrypOutBuffPtr = Output;
01327
01328     /*  Calculate Size parameter in Byte*/
01329     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01330     {
01331       hcryp->Size = Size * 4U;
01332     }
01333     else
01334     {
01335       hcryp->Size = Size;
01336     }
01337
01338     /* Set Decryption operating mode*/
01339     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01340
01341     /* algo get algorithm selected */
01342     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01343
01344     switch (algo)
01345     {
01346
01347       case CRYP_AES_ECB:
01348       case CRYP_AES_CBC:
01349       case CRYP_AES_CTR:
01350
01351         /* AES decryption */
01352         status = CRYP_AES_Decrypt(hcryp, Timeout);
01353         break;
01354
01355       case CRYP_AES_GCM_GMAC:
01356
01357         /* AES GCM decryption */
01358         status = CRYP_AESGCM_Process(hcryp, Timeout) ;
01359         break;
01360
01361       case CRYP_AES_CCM:
01362
01363         /* AES CCM decryption */
01364         status = CRYP_AESCCM_Process(hcryp, Timeout);
01365         break;
01366
01367       default:
01368         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01369         status = HAL_ERROR;
01370         break;
01371     }
01372
01373     if (status == HAL_OK)
01374     {
01375       /* Change the CRYP peripheral state */
01376       hcryp->State = HAL_CRYP_STATE_READY;
01377
01378       /* Process unlocked */
01379       __HAL_UNLOCK(hcryp);
01380     }
01381   }
01382   else
01383   {
01384     /* Busy error code field */
01385     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01386     status = HAL_ERROR;
01387   }
01388
01389   /* Return function status */
01390   return status;
01391 }
01392
01393 /**
01394   * @brief  Encryption in interrupt mode.
01395   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01396   *         the configuration information for CRYP module
01397   * @param  Input Pointer to the input buffer (plaintext)
01398   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01399   * @param  Output Pointer to the output buffer(ciphertext)
01400   * @retval HAL status
01401   */
01402 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01403 {
01404   HAL_StatusTypeDef status;
01405   uint32_t algo;
01406 #ifdef  USE_FULL_ASSERT
01407   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01408
01409   /* Check input buffer size */
01410   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01411 #endif /* USE_FULL_ASSERT */
01412
01413   if (hcryp->State == HAL_CRYP_STATE_READY)
01414   {
01415     /* Change state Busy */
01416     hcryp->State = HAL_CRYP_STATE_BUSY;
01417
01418     /* Process locked */
01419     __HAL_LOCK(hcryp);
01420
01421     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01422 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
01423    if (hcryp->ResumingFlag == 1U)
01424    {
01425      hcryp->ResumingFlag = 0U;
01426      if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
01427      {
01428        hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
01429        hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
01430      }
01431      else
01432      {
01433     hcryp->CrypInCount = 0U;
01434     hcryp->CrypOutCount = 0U;
01435      }
01436    }
01437    else
01438 #endif  /* USE_HAL_CRYP_SUSPEND_RESUME */
01439    {
01440     hcryp->CrypInCount = 0U;
01441     hcryp->CrypOutCount = 0U;
01442    }
01443
01444     hcryp->pCrypInBuffPtr = Input;
01445     hcryp->pCrypOutBuffPtr = Output;
01446
01447     /*  Calculate Size parameter in Byte*/
01448     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01449     {
01450       hcryp->Size = Size * 4U;
01451     }
01452     else
01453     {
01454       hcryp->Size = Size;
01455     }
01456
01457     /* Set encryption operating mode*/
01458     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01459
01460     /* algo get algorithm selected */
01461     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01462
01463     switch (algo)
01464     {
01465
01466       case CRYP_AES_ECB:
01467       case CRYP_AES_CBC:
01468       case CRYP_AES_CTR:
01469
01470         /* AES encryption */
01471         status = CRYP_AES_Encrypt_IT(hcryp);
01472         break;
01473
01474       case CRYP_AES_GCM_GMAC:
01475
01476         /* AES GCM encryption */
01477         status = CRYP_AESGCM_Process_IT(hcryp) ;
01478         break;
01479
01480       case CRYP_AES_CCM:
01481
01482         /* AES CCM encryption */
01483         status = CRYP_AESCCM_Process_IT(hcryp);
01484         break;
01485
01486       default:
01487         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01488         status = HAL_ERROR;
01489         break;
01490     }
01491   }
01492   else
01493   {
01494     /* Busy error code field */
01495     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01496     status = HAL_ERROR;
01497   }
01498
01499   /* Return function status */
01500   return status;
01501 }
01502
01503 /**
01504   * @brief  Decryption in interrupt mode.
01505   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01506   *         the configuration information for CRYP module
01507   * @param  Input Pointer to the input buffer (ciphertext )
01508   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01509   * @param  Output Pointer to the output buffer(plaintext)
01510   * @retval HAL status
01511   */
01512 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01513 {
01514   HAL_StatusTypeDef status;
01515   uint32_t algo;
01516 #ifdef  USE_FULL_ASSERT
01517   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01518
01519   /* Check input buffer size */
01520   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01521 #endif /* USE_FULL_ASSERT */
01522
01523   if (hcryp->State == HAL_CRYP_STATE_READY)
01524   {
01525     /* Change state Busy */
01526     hcryp->State = HAL_CRYP_STATE_BUSY;
01527
01528     /* Process locked */
01529     __HAL_LOCK(hcryp);
01530
01531     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01532 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
01533    if (hcryp->ResumingFlag == 1U)
01534    {
01535      hcryp->ResumingFlag = 0U;
01536      if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
01537      {
01538        hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
01539        hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
01540      }
01541      else
01542      {
01543     hcryp->CrypInCount = 0U;
01544     hcryp->CrypOutCount = 0U;
01545      }
01546    }
01547    else
01548 #endif  /* USE_HAL_CRYP_SUSPEND_RESUME */
01549    {
01550      hcryp->CrypInCount = 0U;
01551      hcryp->CrypOutCount = 0U;
01552    }
01553     hcryp->pCrypInBuffPtr = Input;
01554     hcryp->pCrypOutBuffPtr = Output;
01555
01556     /*  Calculate Size parameter in Byte*/
01557     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01558     {
01559       hcryp->Size = Size * 4U;
01560     }
01561     else
01562     {
01563       hcryp->Size = Size;
01564     }
01565
01566     /* Set decryption operating mode*/
01567     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01568
01569     /* algo get algorithm selected */
01570     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01571
01572     switch (algo)
01573     {
01574
01575       case CRYP_AES_ECB:
01576       case CRYP_AES_CBC:
01577       case CRYP_AES_CTR:
01578
01579         /* AES decryption */
01580         status = CRYP_AES_Decrypt_IT(hcryp);
01581         break;
01582
01583       case CRYP_AES_GCM_GMAC:
01584
01585         /* AES GCM decryption */
01586         status = CRYP_AESGCM_Process_IT(hcryp) ;
01587         break;
01588
01589       case CRYP_AES_CCM:
01590
01591         /* AES CCM decryption */
01592         status = CRYP_AESCCM_Process_IT(hcryp);
01593         break;
01594
01595       default:
01596         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01597         status = HAL_ERROR;
01598         break;
01599     }
01600   }
01601   else
01602   {
01603     /* Busy error code field */
01604     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01605     status = HAL_ERROR;
01606   }
01607
01608   /* Return function status */
01609   return status;
01610 }
01611
01612 /**
01613   * @brief  Encryption in DMA mode.
01614   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01615   *         the configuration information for CRYP module
01616   * @param  Input Pointer to the input buffer (plaintext)
01617   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01618   * @param  Output Pointer to the output buffer(ciphertext)
01619   * @retval HAL status
01620   */
01621 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01622 {
01623   HAL_StatusTypeDef status;
01624   uint32_t algo;
01625   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
01626 #ifdef  USE_FULL_ASSERT
01627   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01628
01629   /* Check input buffer size */
01630   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01631 #endif /* USE_FULL_ASSERT */
01632
01633   if (hcryp->State == HAL_CRYP_STATE_READY)
01634   {
01635     /* Change state Busy */
01636     hcryp->State = HAL_CRYP_STATE_BUSY;
01637
01638     /* Process locked */
01639     __HAL_LOCK(hcryp);
01640
01641     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01642     hcryp->CrypInCount = 0U;
01643     hcryp->CrypOutCount = 0U;
01644     hcryp->pCrypInBuffPtr = Input;
01645     hcryp->pCrypOutBuffPtr = Output;
01646
01647     /*  Calculate Size parameter in Byte*/
01648     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01649     {
01650       hcryp->Size = Size * 4U;
01651     }
01652     else
01653     {
01654       hcryp->Size = Size;
01655     }
01656
01657     /* Set encryption operating mode*/
01658     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01659
01660     /* algo get algorithm selected */
01661     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01662
01663     switch (algo)
01664     {
01665
01666       case CRYP_AES_ECB:
01667       case CRYP_AES_CBC:
01668       case CRYP_AES_CTR:
01669
01670         if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
01671         {
01672           if (hcryp->KeyIVConfig == 1U)
01673           {
01674             /* If the Key and IV configuration has to be done only once
01675                and if it has already been done, skip it */
01676             DoKeyIVConfig = 0U;
01677           }
01678           else
01679           {
01680             /* If the Key and IV configuration has to be done only once
01681                and if it has not been done already, do it and set KeyIVConfig
01682                to keep track it won't have to be done again next time */
01683             hcryp->KeyIVConfig = 1U;
01684           }
01685         }
01686
01687         if (DoKeyIVConfig == 1U)
01688         {
01689           /*  Set the Key*/
01690           CRYP_SetKey(hcryp, hcryp->Init.KeySize);
01691
01692           /* Set the Initialization Vector*/
01693           if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01694           {
01695             hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
01696             hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
01697             hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
01698             hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
01699           }
01700         } /* if (DoKeyIVConfig == 1U) */
01701
01702         /* Set the phase */
01703         hcryp->Phase = CRYP_PHASE_PROCESS;
01704
01705         /* Start DMA process transfer for AES */
01706         CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
01707         status = HAL_OK;
01708         break;
01709
01710       case CRYP_AES_GCM_GMAC:
01711
01712         /* AES GCM encryption */
01713         status = CRYP_AESGCM_Process_DMA(hcryp) ;
01714         break;
01715
01716       case CRYP_AES_CCM:
01717
01718         /* AES CCM encryption */
01719         status = CRYP_AESCCM_Process_DMA(hcryp);
01720         break;
01721
01722       default:
01723         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01724         status = HAL_ERROR;
01725         break;
01726     }
01727   }
01728   else
01729   {
01730     /* Busy error code field */
01731     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01732     status = HAL_ERROR;
01733   }
01734
01735   /* Return function status */
01736   return status;
01737 }
01738
01739 /**
01740   * @brief  Decryption in DMA mode.
01741   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01742   *         the configuration information for CRYP module
01743   * @param  Input Pointer to the input buffer (ciphertext )
01744   * @param  Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
01745   * @param  Output Pointer to the output buffer(plaintext)
01746   * @retval HAL status
01747   */
01748 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01749 {
01750   HAL_StatusTypeDef status;
01751   uint32_t algo;
01752 #ifdef  USE_FULL_ASSERT
01753   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01754
01755   /* Check input buffer size */
01756   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01757 #endif /* USE_FULL_ASSERT */
01758
01759   if (hcryp->State == HAL_CRYP_STATE_READY)
01760   {
01761
01762     /* Change state Busy */
01763     hcryp->State = HAL_CRYP_STATE_BUSY;
01764
01765     /* Process locked */
01766     __HAL_LOCK(hcryp);
01767
01768     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01769     hcryp->CrypInCount = 0U;
01770     hcryp->CrypOutCount = 0U;
01771     hcryp->pCrypInBuffPtr = Input;
01772     hcryp->pCrypOutBuffPtr = Output;
01773
01774     /*  Calculate Size parameter in Byte*/
01775     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01776     {
01777       hcryp->Size = Size * 4U;
01778     }
01779     else
01780     {
01781       hcryp->Size = Size;
01782     }
01783
01784     /* Set decryption operating mode*/
01785     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01786
01787     /* algo get algorithm selected */
01788     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01789
01790     switch (algo)
01791     {
01792
01793       case CRYP_AES_ECB:
01794       case CRYP_AES_CBC:
01795       case CRYP_AES_CTR:
01796
01797         /* AES decryption */
01798         status = CRYP_AES_Decrypt_DMA(hcryp);
01799         break;
01800
01801       case CRYP_AES_GCM_GMAC:
01802
01803         /* AES GCM decryption */
01804         status = CRYP_AESGCM_Process_DMA(hcryp) ;
01805         break;
01806
01807       case CRYP_AES_CCM:
01808
01809         /* AES CCM decryption */
01810         status = CRYP_AESCCM_Process_DMA(hcryp);
01811         break;
01812
01813       default:
01814         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01815         status = HAL_ERROR;
01816         break;
01817     }
01818   }
01819   else
01820   {
01821     /* Busy error code field */
01822     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01823     status = HAL_ERROR;
01824   }
01825   /* Return function status */
01826   return status;
01827 }
01828
01829 /**
01830   * @}
01831   */
01832
01833 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
01834   * @brief    CRYP IRQ handler.
01835   *
01836 @verbatim
01837   ==============================================================================
01838                 ##### CRYP IRQ handler management #####
01839   ==============================================================================
01840 [..]  This section provides CRYP IRQ handler and callback functions.
01841       (+) HAL_CRYP_IRQHandler CRYP interrupt request
01842       (+) HAL_CRYP_InCpltCallback input data transfer complete callback
01843       (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
01844       (+) HAL_CRYP_ErrorCallback  CRYP error callback
01845       (+) HAL_CRYP_GetState return the CRYP state
01846       (+) HAL_CRYP_GetError return the CRYP error code
01847 @endverbatim
01848   * @{
01849   */
01850
01851 /**
01852   * @brief  This function handles cryptographic interrupt request.
01853   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01854   *         the configuration information for CRYP module
01855   * @retval None
01856   */
01857 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
01858 {
01859
01860   /* Check if error occurred */
01861   if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET)
01862   {
01863     /* If write Error occurred */
01864     if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET)
01865     {
01866       hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
01867     }
01868     /* If read Error occurred */
01869     if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET)
01870     {
01871       hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
01872     }
01873   }
01874
01875   if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
01876   {
01877     if(__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
01878   {
01879     /* Clear computation complete flag */
01880     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
01881
01882     if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
01883     {
01884
01885       /* if header phase */
01886       if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
01887       {
01888         CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
01889       }
01890       else  /* if payload phase */
01891       {
01892         CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
01893       }
01894     }
01895     else  /* AES Algorithm ECB,CBC or CTR*/
01896     {
01897       CRYP_AES_IT(hcryp);
01898     }
01899   }
01900 }
01901 }
01902
01903 /**
01904   * @brief  Return the CRYP error code.
01905   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01906   *                 the configuration information for the  CRYP peripheral
01907   * @retval CRYP error code
01908   */
01909 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
01910 {
01911   return hcryp->ErrorCode;
01912 }
01913
01914 /**
01915   * @brief  Returns the CRYP state.
01916   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01917   *         the configuration information for CRYP module.
01918   * @retval HAL state
01919   */
01920 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
01921 {
01922   return hcryp->State;
01923 }
01924
01925 /**
01926   * @brief  Input FIFO transfer completed callback.
01927   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01928   *         the configuration information for CRYP module.
01929   * @retval None
01930   */
01931 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
01932 {
01933   /* Prevent unused argument(s) compilation warning */
01934   UNUSED(hcryp);
01935
01936   /* NOTE : This function should not be modified; when the callback is needed,
01937             the HAL_CRYP_InCpltCallback can be implemented in the user file
01938    */
01939 }
01940
01941 /**
01942   * @brief  Output FIFO transfer completed callback.
01943   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01944   *         the configuration information for CRYP module.
01945   * @retval None
01946   */
01947 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
01948 {
01949   /* Prevent unused argument(s) compilation warning */
01950   UNUSED(hcryp);
01951
01952   /* NOTE : This function should not be modified; when the callback is needed,
01953             the HAL_CRYP_OutCpltCallback can be implemented in the user file
01954    */
01955 }
01956
01957 /**
01958   * @brief  CRYP error callback.
01959   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01960   *         the configuration information for CRYP module.
01961   * @retval None
01962   */
01963 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
01964 {
01965   /* Prevent unused argument(s) compilation warning */
01966   UNUSED(hcryp);
01967
01968   /* NOTE : This function should not be modified; when the callback is needed,
01969             the HAL_CRYP_ErrorCallback can be implemented in the user file
01970    */
01971 }
01972 /**
01973   * @}
01974   */
01975
01976 /**
01977   * @}
01978   */
01979
01980 /* Private functions ---------------------------------------------------------*/
01981 /** @addtogroup CRYP_Private_Functions
01982   * @{
01983   */
01984
01985 /**
01986   * @brief  Encryption in ECB/CBC & CTR Algorithm with AES Standard
01987   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
01988   * @param  Timeout specify Timeout value
01989   * @retval HAL status
01990   */
01991 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
01992 {
01993   uint16_t incount;  /* Temporary CrypInCount Value */
01994   uint16_t outcount;  /* Temporary CrypOutCount Value */
01995   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
01996
01997   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
01998   {
01999     if (hcryp->KeyIVConfig == 1U)
02000     {
02001       /* If the Key and IV configuration has to be done only once
02002          and if it has already been done, skip it */
02003       DoKeyIVConfig = 0U;
02004     }
02005     else
02006     {
02007       /* If the Key and IV configuration has to be done only once
02008          and if it has not been done already, do it and set KeyIVConfig
02009          to keep track it won't have to be done again next time */
02010       hcryp->KeyIVConfig = 1U;
02011     }
02012   }
02013
02014   if (DoKeyIVConfig == 1U)
02015   {
02016     /*  Set the Key*/
02017     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02018
02019     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02020     {
02021       /* Set the Initialization Vector*/
02022       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02023       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02024       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02025       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02026     }
02027   } /* if (DoKeyIVConfig == 1U) */
02028
02029   /* Set the phase */
02030   hcryp->Phase = CRYP_PHASE_PROCESS;
02031
02032   /* Enable CRYP */
02033   __HAL_CRYP_ENABLE(hcryp);
02034
02035   incount = hcryp->CrypInCount;
02036   outcount = hcryp->CrypOutCount;
02037   while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
02038   {
02039     /* Write plain Ddta and get cipher data */
02040     CRYP_AES_ProcessData(hcryp, Timeout);
02041     incount = hcryp->CrypInCount;
02042     outcount = hcryp->CrypOutCount;
02043   }
02044
02045   /* Disable CRYP */
02046   __HAL_CRYP_DISABLE(hcryp);
02047
02048   /* Change the CRYP state */
02049   hcryp->State = HAL_CRYP_STATE_READY;
02050
02051   /* Return function status */
02052   return HAL_OK;
02053 }
02054
02055 /**
02056   * @brief  Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
02057   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02058   *         the configuration information for CRYP module
02059   * @retval HAL status
02060   */
02061 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
02062 {
02063   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02064
02065   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02066   {
02067     if (hcryp->KeyIVConfig == 1U)
02068     {
02069       /* If the Key and IV configuration has to be done only once
02070          and if it has already been done, skip it */
02071       DoKeyIVConfig = 0U;
02072     }
02073     else
02074     {
02075       /* If the Key and IV configuration has to be done only once
02076          and if it has not been done already, do it and set KeyIVConfig
02077          to keep track it won't have to be done again next time */
02078       hcryp->KeyIVConfig = 1U;
02079     }
02080   }
02081
02082   if (DoKeyIVConfig == 1U)
02083   {
02084     /*  Set the Key*/
02085     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02086
02087     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02088     {
02089       /* Set the Initialization Vector*/
02090       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02091       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02092       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02093       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02094     }
02095   } /* if (DoKeyIVConfig == 1U) */
02096
02097   /* Set the phase */
02098   hcryp->Phase = CRYP_PHASE_PROCESS;
02099
02100   if (hcryp->Size != 0U)
02101   {
02102
02103     /* Enable computation complete flag and error interrupts */
02104     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02105
02106     /* Enable CRYP */
02107     __HAL_CRYP_ENABLE(hcryp);
02108
02109     /* Write the input block in the IN FIFO */
02110     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02111     hcryp->CrypInCount++;
02112     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02113     hcryp->CrypInCount++;
02114     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02115     hcryp->CrypInCount++;
02116     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02117     hcryp->CrypInCount++;
02118   }
02119   else
02120   {
02121     /* Change the CRYP state */
02122     hcryp->State = HAL_CRYP_STATE_READY;
02123
02124     /* Process unlocked */
02125     __HAL_UNLOCK(hcryp);
02126   }
02127
02128   /* Return function status */
02129   return HAL_OK;
02130 }
02131
02132 /**
02133   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard
02134   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
02135   * @param  Timeout Specify Timeout value
02136   * @retval HAL status
02137 */
02138 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02139 {
02140   uint16_t incount;  /* Temporary CrypInCount Value */
02141   uint16_t outcount;  /* Temporary CrypOutCount Value */
02142   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02143
02144   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02145   {
02146     if (hcryp->KeyIVConfig == 1U)
02147     {
02148       /* If the Key and IV configuration has to be done only once
02149          and if it has already been done, skip it */
02150       DoKeyIVConfig = 0U;
02151     }
02152     else
02153     {
02154       /* If the Key and IV configuration has to be done only once
02155          and if it has not been done already, do it and set KeyIVConfig
02156          to keep track it won't have to be done again next time */
02157       hcryp->KeyIVConfig = 1U;
02158     }
02159   }
02160
02161   if (DoKeyIVConfig == 1U)
02162   {
02163     /*  Key preparation for ECB/CBC */
02164     if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
02165     {
02166       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
02167       {
02168         /* Set key preparation for decryption operating mode*/
02169         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02170
02171         /*  Set the Key*/
02172         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02173
02174         /* Enable CRYP */
02175         __HAL_CRYP_ENABLE(hcryp);
02176
02177         /* Wait for CCF flag to be raised */
02178         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
02179         {
02180           /* Disable the CRYP peripheral clock */
02181           __HAL_CRYP_DISABLE(hcryp);
02182
02183           /* Change state & error code*/
02184           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02185           hcryp->State = HAL_CRYP_STATE_READY;
02186
02187           /* Process unlocked */
02188           __HAL_UNLOCK(hcryp);
02189           return HAL_ERROR;
02190         }
02191         /* Clear CCF Flag */
02192         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02193
02194         /* Return to decryption operating mode(Mode 3)*/
02195         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02196       }
02197       else /*Mode 4 : decryption & Key preparation*/
02198       {
02199         /*  Set the Key*/
02200         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02201
02202         /* Set decryption & Key preparation operating mode*/
02203         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02204       }
02205     }
02206     else  /*Algorithm CTR */
02207     {
02208       /*  Set the Key*/
02209       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02210     }
02211
02212     /* Set IV */
02213     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02214     {
02215       /* Set the Initialization Vector*/
02216       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02217       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02218       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02219       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02220     }
02221   } /* if (DoKeyIVConfig == 1U) */
02222
02223   /* Set the phase */
02224   hcryp->Phase = CRYP_PHASE_PROCESS;
02225
02226   /* Enable CRYP */
02227   __HAL_CRYP_ENABLE(hcryp);
02228
02229   incount = hcryp->CrypInCount;
02230   outcount = hcryp->CrypOutCount;
02231   while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
02232   {
02233     /* Write plain data and get cipher data */
02234     CRYP_AES_ProcessData(hcryp, Timeout);
02235     incount = hcryp->CrypInCount;
02236     outcount = hcryp->CrypOutCount;
02237   }
02238
02239   /* Disable CRYP */
02240   __HAL_CRYP_DISABLE(hcryp);
02241
02242   /* Change the CRYP state */
02243   hcryp->State = HAL_CRYP_STATE_READY;
02244
02245   /* Return function status */
02246   return HAL_OK;
02247 }
02248 /**
02249   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
02250   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02251   *         the configuration information for CRYP module
02252   * @retval HAL status
02253   */
02254 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
02255 {
02256   __IO uint32_t count = 0U;
02257   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02258
02259   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02260   {
02261     if (hcryp->KeyIVConfig == 1U)
02262     {
02263       /* If the Key and IV configuration has to be done only once
02264          and if it has already been done, skip it */
02265       DoKeyIVConfig = 0U;
02266     }
02267     else
02268     {
02269       /* If the Key and IV configuration has to be done only once
02270          and if it has not been done already, do it and set KeyIVConfig
02271          to keep track it won't have to be done again next time */
02272       hcryp->KeyIVConfig = 1U;
02273     }
02274   }
02275
02276   if (DoKeyIVConfig == 1U)
02277   {
02278     /*  Key preparation for ECB/CBC */
02279     if (hcryp->Init.Algorithm != CRYP_AES_CTR)
02280     {
02281       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
02282       {
02283         /* Set key preparation for decryption operating mode*/
02284         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02285
02286         /*  Set the Key*/
02287         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02288
02289         /* Enable CRYP */
02290         __HAL_CRYP_ENABLE(hcryp);
02291
02292         /* Wait for CCF flag to be raised */
02293         count = CRYP_TIMEOUT_KEYPREPARATION;
02294         do
02295         {
02296           count-- ;
02297           if (count == 0U)
02298           {
02299             /* Disable the CRYP peripheral clock */
02300             __HAL_CRYP_DISABLE(hcryp);
02301
02302             /* Change state */
02303             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02304             hcryp->State = HAL_CRYP_STATE_READY;
02305
02306             /* Process unlocked */
02307             __HAL_UNLOCK(hcryp);
02308             return HAL_ERROR;
02309           }
02310         }
02311         while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
02312
02313         /* Clear CCF Flag */
02314         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02315
02316         /* Return to decryption operating mode(Mode 3)*/
02317         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02318       }
02319       else /*Mode 4 : decryption & key preparation*/
02320       {
02321         /*  Set the Key*/
02322         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02323
02324         /* Set decryption & key preparation operating mode*/
02325         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02326       }
02327     }
02328     else  /*Algorithm CTR */
02329     {
02330       /*  Set the Key*/
02331       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02332     }
02333
02334     /* Set IV */
02335     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02336     {
02337       /* Set the Initialization Vector*/
02338       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02339       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02340       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02341       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02342     }
02343   } /* if (DoKeyIVConfig == 1U) */
02344
02345   /* Set the phase */
02346   hcryp->Phase = CRYP_PHASE_PROCESS;
02347   if (hcryp->Size != 0U)
02348   {
02349     /* Enable computation complete flag and error interrupts */
02350     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02351
02352     /* Enable CRYP */
02353     __HAL_CRYP_ENABLE(hcryp);
02354
02355     /* Write the input block in the IN FIFO */
02356     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02357     hcryp->CrypInCount++;
02358     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02359     hcryp->CrypInCount++;
02360     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02361     hcryp->CrypInCount++;
02362     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02363     hcryp->CrypInCount++;
02364   }
02365   else
02366   {
02367     /* Process locked */
02368     __HAL_UNLOCK(hcryp);
02369
02370     /* Change the CRYP state */
02371     hcryp->State = HAL_CRYP_STATE_READY;
02372   }
02373
02374   /* Return function status */
02375   return HAL_OK;
02376 }
02377 /**
02378   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
02379   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02380   *         the configuration information for CRYP module
02381   * @retval HAL status
02382   */
02383 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
02384 {
02385   __IO uint32_t count = 0U;
02386   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02387
02388   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02389   {
02390     if (hcryp->KeyIVConfig == 1U)
02391     {
02392       /* If the Key and IV configuration has to be done only once
02393          and if it has already been done, skip it */
02394       DoKeyIVConfig = 0U;
02395     }
02396     else
02397     {
02398       /* If the Key and IV configuration has to be done only once
02399          and if it has not been done already, do it and set KeyIVConfig
02400          to keep track it won't have to be done again next time */
02401       hcryp->KeyIVConfig = 1U;
02402     }
02403   }
02404
02405   if (DoKeyIVConfig == 1U)
02406   {
02407     /*  Key preparation for ECB/CBC */
02408     if (hcryp->Init.Algorithm != CRYP_AES_CTR)
02409     {
02410       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
02411       {
02412         /* Set key preparation for decryption operating mode*/
02413         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02414
02415         /*  Set the Key*/
02416         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02417
02418         /* Enable CRYP */
02419         __HAL_CRYP_ENABLE(hcryp);
02420
02421         /* Wait for CCF flag to be raised */
02422         count = CRYP_TIMEOUT_KEYPREPARATION;
02423         do
02424         {
02425           count-- ;
02426           if (count == 0U)
02427           {
02428             /* Disable the CRYP peripheral clock */
02429             __HAL_CRYP_DISABLE(hcryp);
02430
02431             /* Change state */
02432             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02433             hcryp->State = HAL_CRYP_STATE_READY;
02434
02435             /* Process unlocked */
02436             __HAL_UNLOCK(hcryp);
02437             return HAL_ERROR;
02438           }
02439         }
02440         while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
02441
02442         /* Clear CCF Flag */
02443         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02444
02445         /* Return to decryption operating mode(Mode 3)*/
02446         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02447       }
02448       else /*Mode 4 : decryption & key preparation*/
02449       {
02450         /*  Set the Key*/
02451         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02452
02453         /* Set decryption & Key preparation operating mode*/
02454         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02455       }
02456     }
02457     else  /*Algorithm CTR */
02458     {
02459       /*  Set the Key*/
02460       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02461     }
02462
02463     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02464     {
02465       /* Set the Initialization Vector*/
02466       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02467       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02468       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02469       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02470     }
02471   } /* if (DoKeyIVConfig == 1U) */
02472
02473   /* Set the phase */
02474   hcryp->Phase = CRYP_PHASE_PROCESS;
02475
02476   if (hcryp->Size != 0U)
02477   {
02478     /* Set the input and output addresses and start DMA transfer */
02479     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
02480   }
02481   else
02482   {
02483     /* Process unlocked */
02484     __HAL_UNLOCK(hcryp);
02485
02486     /* Change the CRYP state */
02487     hcryp->State = HAL_CRYP_STATE_READY;
02488   }
02489
02490   /* Return function status */
02491   return HAL_OK;
02492 }
02493
02494
02495 /**
02496   * @brief  DMA CRYP input data process complete callback.
02497   * @param  hdma DMA handle
02498   * @retval None
02499   */
02500 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
02501 {
02502   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02503   uint32_t loopcounter;
02504   uint32_t headersize_in_bytes;
02505   uint32_t tmp;
02506   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
02507                                     0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
02508                                     0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /*  8-bit data type */
02509
02510   /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */
02511   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
02512
02513   if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED)
02514   {
02515     /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */
02516     CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
02517
02518     /* Set the phase */
02519     hcryp->Phase = CRYP_PHASE_PROCESS;
02520
02521     if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
02522     {
02523       headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
02524     }
02525     else
02526     {
02527       headersize_in_bytes = hcryp->Init.HeaderSize;
02528     }
02529
02530     if ((headersize_in_bytes % 16U) != 0U)
02531     {
02532       /* Write last words that couldn't be fed by DMA */
02533       hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U);
02534       for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
02535       {
02536         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
02537         hcryp->CrypHeaderCount++ ;
02538       }
02539       /* If the header size is a multiple of words */
02540       if ((headersize_in_bytes % 4U) == 0U)
02541       {
02542         /* Pad the data with zeros to have a complete block */
02543         while (loopcounter < 4U)
02544         {
02545           hcryp->Instance->DINR = 0x0U;
02546           loopcounter++;
02547         }
02548       }
02549       else
02550       {
02551         /* Enter last bytes, padded with zeros */
02552         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
02553         tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
02554         hcryp->Instance->DINR = tmp;
02555         loopcounter++;
02556         /* Pad the data with zeros to have a complete block */
02557         while (loopcounter < 4U)
02558         {
02559           hcryp->Instance->DINR = 0x0U;
02560           loopcounter++;
02561         }
02562       }
02563
02564       /* Wait for computation completion before moving forward */
02565       CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
02566     } /* if ((headersize_in_bytes % 16U) != 0U) */
02567
02568     /* Set to 0 the number of non-valid bytes using NPBLB register*/
02569     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
02570
02571     /* Select payload phase once the header phase is performed */
02572     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02573
02574     /* Initiate payload DMA IN and processed data DMA OUT transfers */
02575     (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
02576   }
02577   else
02578   {
02579     uint32_t algo;
02580     /* ECB, CBC or CTR end of input data feeding
02581        or
02582        end of GCM/CCM payload data feeding through DMA */
02583     algo = hcryp->Instance->CR & AES_CR_CHMOD;
02584
02585     /* Don't call input data transfer complete callback only if
02586        it remains some input data to write to the peripheral.
02587        This case can only occur for GCM and CCM with a payload length
02588        not a multiple of 16 bytes */
02589     if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \
02590         (((hcryp->Size) % 16U) != 0U)))
02591     {
02592       /* Call input data transfer complete callback */
02593 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02594       /*Call registered Input complete callback*/
02595       hcryp->InCpltCallback(hcryp);
02596 #else
02597       /*Call legacy weak Input complete callback*/
02598       HAL_CRYP_InCpltCallback(hcryp);
02599 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02600     }
02601   } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */
02602 }
02603
02604 /**
02605   * @brief  DMA CRYP output data process complete callback.
02606   * @param  hdma DMA handle
02607   * @retval None
02608   */
02609 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
02610 {
02611   uint32_t count;
02612   uint32_t npblb;
02613   uint32_t lastwordsize;
02614   uint32_t temp[4];  /* Temporary CrypOutBuff */
02615   uint32_t mode;
02616
02617   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02618
02619   /* Stop the DMA transfers to the OUT FIFO by clearing to "0" the DMAOUTEN */
02620   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
02621
02622   /* Clear CCF flag */
02623   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02624
02625   /* Last block transfer in case of GCM or CCM with Size not %16*/
02626   if (((hcryp->Size) % 16U) != 0U)
02627   {
02628     /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA  */
02629     hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
02630     hcryp->CrypOutCount = hcryp->CrypInCount;
02631
02632     /* Compute the number of padding bytes in last block of payload */
02633     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
02634
02635     mode = hcryp->Instance->CR & AES_CR_MODE;
02636     if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
02637         ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
02638     {
02639       /* Specify the number of non-valid bytes using NPBLB register*/
02640       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
02641     }
02642
02643     /* Number of valid words (lastwordsize) in last block */
02644     if ((npblb % 4U) == 0U)
02645     {
02646       lastwordsize = (16U - npblb) / 4U;
02647     }
02648     else
02649     {
02650       lastwordsize = ((16U - npblb) / 4U) + 1U;
02651     }
02652
02653     /*  Last block optionally pad the data with zeros*/
02654     for (count = 0U; count < lastwordsize; count++)
02655     {
02656       hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02657       hcryp->CrypInCount++;
02658     }
02659     while (count < 4U)
02660     {
02661       /* Pad the data with zeros to have a complete block */
02662       hcryp->Instance->DINR = 0x0U;
02663       count++;
02664     }
02665     /* Call input data transfer complete callback */
02666 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02667     /*Call registered Input complete callback*/
02668     hcryp->InCpltCallback(hcryp);
02669 #else
02670     /*Call legacy weak Input complete callback*/
02671     HAL_CRYP_InCpltCallback(hcryp);
02672 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02673
02674     /*Wait on CCF flag*/
02675     CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
02676
02677     /*Read the output block from the output FIFO */
02678     for (count = 0U; count < 4U; count++)
02679     {
02680       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
02681       temp[count] = hcryp->Instance->DOUTR;
02682     }
02683
02684     count = 0U;
02685     while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U))
02686     {
02687       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
02688       hcryp->CrypOutCount++;
02689       count++;
02690     }
02691   }
02692
02693   if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
02694   {
02695     /* Disable CRYP (not allowed in  GCM)*/
02696     __HAL_CRYP_DISABLE(hcryp);
02697   }
02698
02699   /* Change the CRYP state to ready */
02700   hcryp->State = HAL_CRYP_STATE_READY;
02701
02702   /* Process unlocked */
02703   __HAL_UNLOCK(hcryp);
02704
02705   /* Call output data transfer complete callback */
02706 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02707   /*Call registered Output complete callback*/
02708   hcryp->OutCpltCallback(hcryp);
02709 #else
02710   /*Call legacy weak Output complete callback*/
02711   HAL_CRYP_OutCpltCallback(hcryp);
02712 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02713 }
02714
02715 /**
02716   * @brief  DMA CRYP communication error callback.
02717   * @param  hdma DMA handle
02718   * @retval None
02719   */
02720 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
02721 {
02722   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02723
02724   /* Change the CRYP peripheral state */
02725   hcryp->State = HAL_CRYP_STATE_READY;
02726
02727   /* DMA error code field */
02728   hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02729
02730   /* Clear CCF flag */
02731   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02732
02733   /* Call error callback */
02734 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02735   /*Call registered error callback*/
02736   hcryp->ErrorCallback(hcryp);
02737 #else
02738   /*Call legacy weak error callback*/
02739   HAL_CRYP_ErrorCallback(hcryp);
02740 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02741 }
02742
02743 /**
02744   * @brief  Set the DMA configuration and start the DMA transfer
02745   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02746   *         the configuration information for CRYP module
02747   * @param  inputaddr address of the input buffer
02748   * @param  Size size of the input and output buffers in words, must be a multiple of 4
02749   * @param  outputaddr address of the output buffer
02750   * @retval None
02751   */
02752 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
02753 {
02754   /* Set the CRYP DMA transfer complete callback */
02755   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
02756
02757   /* Set the DMA input error callback */
02758   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
02759
02760   /* Set the CRYP DMA transfer complete callback */
02761   hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
02762
02763   /* Set the DMA output error callback */
02764   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
02765
02766   if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
02767   {
02768     /* Enable CRYP (not allowed in  GCM & CCM)*/
02769     __HAL_CRYP_ENABLE(hcryp);
02770   }
02771
02772   /* Enable the DMA input stream */
02773   if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
02774   {
02775     /* DMA error code field */
02776     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02777
02778     /* Call error callback */
02779 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02780     /*Call registered error callback*/
02781     hcryp->ErrorCallback(hcryp);
02782 #else
02783     /*Call legacy weak error callback*/
02784     HAL_CRYP_ErrorCallback(hcryp);
02785 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02786   }
02787   /* Enable the DMA output stream */
02788   if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
02789   {
02790     /* DMA error code field */
02791     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02792
02793     /* Call error callback */
02794 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02795     /*Call registered error callback*/
02796     hcryp->ErrorCallback(hcryp);
02797 #else
02798     /*Call legacy weak error callback*/
02799     HAL_CRYP_ErrorCallback(hcryp);
02800 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02801   }
02802   /* Enable In and Out DMA requests */
02803   SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
02804 }
02805
02806 /**
02807   * @brief  Set the DMA configuration and start the header DMA transfer
02808   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02809   *         the configuration information for CRYP module
02810   * @param  inputaddr address of the input buffer
02811   * @param  Size size of the input buffer in words, must be a multiple of 4
02812   * @retval None
02813   */
02814 static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
02815 {
02816   /* Set the CRYP DMA transfer complete callback */
02817   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
02818
02819   /* Set the DMA input error callback */
02820   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
02821
02822   /* Mark that header is fed to the peripheral in DMA mode */
02823   hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED;
02824   /* Enable the DMA input stream */
02825   if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
02826   {
02827     /* DMA error code field */
02828     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02829     hcryp->State = HAL_CRYP_STATE_READY;
02830
02831     /* Process unlocked */
02832     __HAL_UNLOCK(hcryp);
02833     return HAL_ERROR;
02834     /* Call error callback */
02835   }
02836
02837   /* Enable IN DMA requests */
02838   SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
02839
02840   return HAL_OK;
02841 }
02842
02843 /**
02844   * @brief  Process Data: Write Input data in polling mode and used in AES functions.
02845   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02846   *         the configuration information for CRYP module
02847   * @param  Timeout Specify Timeout value
02848   * @retval None
02849   */
02850 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02851 {
02852
02853   uint32_t temp[4];  /* Temporary CrypOutBuff */
02854   uint32_t i;
02855
02856   /* Write the input block in the IN FIFO */
02857   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02858   hcryp->CrypInCount++;
02859   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02860   hcryp->CrypInCount++;
02861   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02862   hcryp->CrypInCount++;
02863   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02864   hcryp->CrypInCount++;
02865
02866   /* Wait for CCF flag to be raised */
02867   if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
02868   {
02869     /* Disable the CRYP peripheral clock */
02870     __HAL_CRYP_DISABLE(hcryp);
02871
02872     /* Change state */
02873     hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02874     hcryp->State = HAL_CRYP_STATE_READY;
02875
02876     /* Process unlocked */
02877     __HAL_UNLOCK(hcryp);
02878     /*Call registered error callback*/
02879 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02880     hcryp->ErrorCallback(hcryp);
02881 #else
02882     /*Call legacy weak error callback*/
02883     HAL_CRYP_ErrorCallback(hcryp);
02884 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02885   }
02886
02887   /* Clear CCF Flag */
02888   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02889
02890   /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
02891   for (i = 0U; i < 4U; i++)
02892   {
02893     temp[i] = hcryp->Instance->DOUTR;
02894   }
02895   i= 0U;
02896   while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
02897   {
02898     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
02899     hcryp->CrypOutCount++;
02900     i++;
02901   }
02902 }
02903
02904 /**
02905   * @brief  Handle CRYP block input/output data handling under interruption.
02906   * @note   The function is called under interruption only, once
02907   *         interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
02908   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02909   *         the configuration information for CRYP module.
02910   * @retval HAL status
02911   */
02912 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
02913 {
02914   uint32_t temp[4];  /* Temporary CrypOutBuff */
02915   uint32_t i;
02916
02917   if (hcryp->State == HAL_CRYP_STATE_BUSY)
02918   {
02919     /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
02920     for (i = 0U; i < 4U; i++)
02921     {
02922       temp[i] = hcryp->Instance->DOUTR;
02923     }
02924     i= 0U;
02925     while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
02926     {
02927       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
02928       hcryp->CrypOutCount++;
02929       i++;
02930     }
02931     if (hcryp->CrypOutCount ==  (hcryp->Size / 4U))
02932     {
02933       /* Disable Computation Complete flag and errors interrupts */
02934       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02935
02936       /* Change the CRYP state */
02937       hcryp->State = HAL_CRYP_STATE_READY;
02938
02939       /* Disable CRYP */
02940       __HAL_CRYP_DISABLE(hcryp);
02941
02942       /* Process Unlocked */
02943       __HAL_UNLOCK(hcryp);
02944
02945       /* Call Output transfer complete callback */
02946 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02947       /*Call registered Output complete callback*/
02948       hcryp->OutCpltCallback(hcryp);
02949 #else
02950       /*Call legacy weak Output complete callback*/
02951       HAL_CRYP_OutCpltCallback(hcryp);
02952 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02953     }
02954     else
02955     {
02956 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
02957       /* If suspension flag has been raised, suspend processing
02958          only if not already at the end of the payload */
02959       if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
02960       {
02961         /* Clear CCF Flag */
02962         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02963
02964         /* reset SuspendRequest */
02965         hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
02966         /* Disable Computation Complete Flag and Errors Interrupts */
02967         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02968         /* Change the CRYP state */
02969         hcryp->State = HAL_CRYP_STATE_SUSPENDED;
02970         /* Mark that the payload phase is suspended */
02971         hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
02972
02973        /* Process Unlocked */
02974         __HAL_UNLOCK(hcryp);
02975       }
02976       else
02977 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
02978       {
02979         /* Write the input block in the IN FIFO */
02980         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02981         hcryp->CrypInCount++;
02982         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02983         hcryp->CrypInCount++;
02984         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02985         hcryp->CrypInCount++;
02986         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02987         hcryp->CrypInCount++;
02988
02989         if (hcryp->CrypInCount ==  (hcryp->Size / 4U))
02990         {
02991           /* Call Input transfer complete callback */
02992 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02993           /*Call registered Input complete callback*/
02994           hcryp->InCpltCallback(hcryp);
02995 #else
02996           /*Call legacy weak Input complete callback*/
02997           HAL_CRYP_InCpltCallback(hcryp);
02998 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02999         }
03000       }
03001     }
03002   }
03003   else
03004   {
03005     /* Busy error code field */
03006     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
03007 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03008     /*Call registered error callback*/
03009     hcryp->ErrorCallback(hcryp);
03010 #else
03011     /*Call legacy weak error callback*/
03012     HAL_CRYP_ErrorCallback(hcryp);
03013 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03014   }
03015 }
03016
03017 /**
03018   * @brief  Writes Key in Key registers.
03019   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03020   *         the configuration information for CRYP module
03021   * @param  KeySize Size of Key
03022   * @note   If pKey is NULL, the Key registers are not written. This configuration
03023   *         occurs when the key is written out of HAL scope.
03024   * @retval None
03025   */
03026 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
03027 {
03028   if (hcryp->Init.pKey != NULL)
03029   {
03030     switch (KeySize)
03031     {
03032       case CRYP_KEYSIZE_256B:
03033         hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
03034         hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
03035         hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
03036         hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
03037         hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
03038         hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
03039         hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
03040         hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
03041         break;
03042       case CRYP_KEYSIZE_128B:
03043         hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
03044         hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
03045         hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
03046         hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
03047
03048         break;
03049       default:
03050         break;
03051     }
03052   }
03053 }
03054
03055 /**
03056   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
03057   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03058   *         the configuration information for CRYP module
03059   * @param  Timeout Timeout duration
03060   * @retval HAL status
03061   */
03062 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03063 {
03064   uint32_t tickstart;
03065   uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
03066   uint32_t npblb;
03067   uint32_t temp[4];  /* Temporary CrypOutBuff */
03068   uint32_t index;
03069   uint32_t lastwordsize;
03070   uint32_t incount;  /* Temporary CrypInCount Value */
03071   uint32_t outcount;  /* Temporary CrypOutCount Value */
03072   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03073
03074   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03075   {
03076     if (hcryp->KeyIVConfig == 1U)
03077     {
03078       /* If the Key and IV configuration has to be done only once
03079          and if it has already been done, skip it */
03080       DoKeyIVConfig = 0U;
03081       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03082     }
03083     else
03084     {
03085       /* If the Key and IV configuration has to be done only once
03086          and if it has not been done already, do it and set KeyIVConfig
03087          to keep track it won't have to be done again next time */
03088       hcryp->KeyIVConfig = 1U;
03089       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03090     }
03091   }
03092   else
03093   {
03094     hcryp->SizesSum = hcryp->Size;
03095   }
03096
03097   if (DoKeyIVConfig == 1U)
03098   {
03099
03100     /*  Reset CrypHeaderCount */
03101     hcryp->CrypHeaderCount = 0U;
03102
03103     /****************************** Init phase **********************************/
03104
03105     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03106
03107     /* Set the key */
03108     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03109
03110     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03111     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03112     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03113     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03114     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03115
03116     /* Enable the CRYP peripheral */
03117     __HAL_CRYP_ENABLE(hcryp);
03118
03119     /* just wait for hash computation */
03120     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03121     {
03122       /* Change state */
03123       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03124       hcryp->State = HAL_CRYP_STATE_READY;
03125
03126       /* Process unlocked & return error */
03127       __HAL_UNLOCK(hcryp);
03128       return HAL_ERROR;
03129     }
03130     /* Clear CCF flag */
03131     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03132
03133     /************************ Header phase *************************************/
03134
03135     if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
03136     {
03137       return HAL_ERROR;
03138     }
03139
03140     /*************************Payload phase ************************************/
03141
03142     /* Set the phase */
03143     hcryp->Phase = CRYP_PHASE_PROCESS;
03144
03145     /* Select payload phase once the header phase is performed */
03146     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03147
03148     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03149     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03150
03151   } /* if (DoKeyIVConfig == 1U) */
03152
03153   if ((hcryp->Size % 16U) != 0U)
03154   {
03155     /* recalculate  wordsize */
03156     wordsize = ((wordsize / 4U) * 4U) ;
03157   }
03158
03159   /* Get tick */
03160   tickstart = HAL_GetTick();
03161
03162   /* Write input data and get output Data */
03163   incount = hcryp->CrypInCount;
03164   outcount = hcryp->CrypOutCount;
03165   while ((incount < wordsize) && (outcount < wordsize))
03166   {
03167     /* Write plain data and get cipher data */
03168     CRYP_AES_ProcessData(hcryp, Timeout);
03169
03170     /* Check for the Timeout */
03171     if (Timeout != HAL_MAX_DELAY)
03172     {
03173       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03174       {
03175         /* Disable the CRYP peripheral clock */
03176         __HAL_CRYP_DISABLE(hcryp);
03177
03178         /* Change state & error code */
03179         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03180         hcryp->State = HAL_CRYP_STATE_READY;
03181
03182         /* Process unlocked */
03183         __HAL_UNLOCK(hcryp);
03184         return HAL_ERROR;
03185       }
03186     }
03187     incount = hcryp->CrypInCount;
03188     outcount = hcryp->CrypOutCount;
03189   }
03190
03191   if ((hcryp->Size % 16U) != 0U)
03192   {
03193     /* Compute the number of padding bytes in last block of payload */
03194     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
03195
03196     /*  Set Npblb in case of AES GCM payload encryption to get right tag*/
03197     if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03198     {
03199       /* Set to 0 the number of non-valid bytes using NPBLB register*/
03200       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03201     }
03202     /* Number of valid words (lastwordsize) in last block */
03203     if ((npblb % 4U) == 0U)
03204     {
03205       lastwordsize = (16U - npblb) / 4U;
03206     }
03207     else
03208     {
03209       lastwordsize = ((16U - npblb) / 4U) + 1U;
03210     }
03211     /*  last block optionally pad the data with zeros*/
03212     for (index = 0U; index < lastwordsize; index ++)
03213     {
03214       /* Write the last Input block in the IN FIFO */
03215       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03216       hcryp->CrypInCount++;
03217     }
03218     while (index < 4U)
03219     {
03220       /* pad the data with zeros to have a complete block */
03221       hcryp->Instance->DINR  = 0U;
03222       index++;
03223     }
03224     /* Wait for CCF flag to be raised */
03225     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03226     {
03227       hcryp->State = HAL_CRYP_STATE_READY;
03228       __HAL_UNLOCK(hcryp);
03229
03230 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03231       /*Call registered error callback*/
03232       hcryp->ErrorCallback(hcryp);
03233 #else
03234       /*Call legacy weak error callback*/
03235       HAL_CRYP_ErrorCallback(hcryp);
03236 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03237     }
03238
03239     /* Clear CCF Flag */
03240     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03241
03242     /*Read the output block from the output FIFO */
03243     for (index = 0U; index < 4U; index++)
03244     {
03245       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03246       temp[index] = hcryp->Instance->DOUTR;
03247     }
03248     for (index = 0U; index < lastwordsize; index++)
03249     {
03250       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
03251       hcryp->CrypOutCount++;
03252     }
03253   }
03254
03255   /* Return function status */
03256   return HAL_OK;
03257 }
03258
03259 /**
03260   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
03261   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03262   *         the configuration information for CRYP module
03263   * @retval HAL status
03264   */
03265 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
03266 {
03267   __IO uint32_t count = 0U;
03268   uint32_t loopcounter;
03269   uint32_t lastwordsize;
03270   uint32_t npblb;
03271   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03272   uint32_t headersize_in_bytes;
03273   uint32_t tmp;
03274   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
03275                                     0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
03276                                     0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /*  8-bit data type */
03277
03278
03279 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
03280   if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
03281   {
03282     CRYP_PhaseProcessingResume(hcryp);
03283     return HAL_OK;
03284   }
03285 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
03286
03287   /* Manage header size given in bytes to handle cases where
03288      header size is not a multiple of 4 bytes */
03289   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
03290   {
03291     headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
03292   }
03293   else
03294   {
03295     headersize_in_bytes = hcryp->Init.HeaderSize;
03296   }
03297
03298   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03299   {
03300     if (hcryp->KeyIVConfig == 1U)
03301     {
03302       /* If the Key and IV configuration has to be done only once
03303          and if it has already been done, skip it */
03304       DoKeyIVConfig = 0U;
03305       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03306     }
03307     else
03308     {
03309       /* If the Key and IV configuration has to be done only once
03310          and if it has not been done already, do it and set KeyIVConfig
03311          to keep track it won't have to be done again next time */
03312       hcryp->KeyIVConfig = 1U;
03313       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03314     }
03315   }
03316   else
03317   {
03318     hcryp->SizesSum = hcryp->Size;
03319   }
03320
03321   /* Configure Key, IV and process message (header and payload) */
03322   if (DoKeyIVConfig == 1U)
03323   {
03324     /*  Reset CrypHeaderCount */
03325     hcryp->CrypHeaderCount = 0U;
03326
03327     /******************************* Init phase *********************************/
03328
03329     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03330
03331     /* Set the key */
03332     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03333
03334     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03335     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03336     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03337     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03338     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03339
03340     /* Enable the CRYP peripheral */
03341     __HAL_CRYP_ENABLE(hcryp);
03342
03343     /* just wait for hash computation */
03344     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03345     do
03346     {
03347       count-- ;
03348       if (count == 0U)
03349       {
03350         /* Disable the CRYP peripheral clock */
03351         __HAL_CRYP_DISABLE(hcryp);
03352
03353         /* Change state */
03354         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03355         hcryp->State = HAL_CRYP_STATE_READY;
03356
03357         /* Process unlocked */
03358         __HAL_UNLOCK(hcryp);
03359         return HAL_ERROR;
03360       }
03361     }
03362     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
03363
03364     /* Clear CCF flag */
03365     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03366
03367     /***************************** Header phase *********************************/
03368
03369     /* Select header phase */
03370     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
03371
03372     /* Enable computation complete flag and error interrupts */
03373     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03374
03375     /* Enable the CRYP peripheral */
03376     __HAL_CRYP_ENABLE(hcryp);
03377
03378     if (hcryp->Init.HeaderSize == 0U) /*header phase is  skipped*/
03379     {
03380       /* Set the phase */
03381       hcryp->Phase = CRYP_PHASE_PROCESS;
03382
03383       /* Select payload phase once the header phase is performed */
03384       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
03385
03386       /* Set to 0 the number of non-valid bytes using NPBLB register*/
03387       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03388
03389       /* Write the payload Input block in the IN FIFO */
03390       if (hcryp->Size == 0U)
03391       {
03392         /* Disable interrupts */
03393         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03394
03395         /* Change the CRYP state */
03396         hcryp->State = HAL_CRYP_STATE_READY;
03397
03398         /* Process unlocked */
03399         __HAL_UNLOCK(hcryp);
03400       }
03401       else if (hcryp->Size >= 16U)
03402       {
03403         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03404         hcryp->CrypInCount++;
03405         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03406         hcryp->CrypInCount++;
03407         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03408         hcryp->CrypInCount++;
03409         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03410         hcryp->CrypInCount++;
03411         if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
03412         {
03413           /* Call Input transfer complete callback */
03414 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03415           /*Call registered Input complete callback*/
03416           hcryp->InCpltCallback(hcryp);
03417 #else
03418           /*Call legacy weak Input complete callback*/
03419           HAL_CRYP_InCpltCallback(hcryp);
03420 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03421         }
03422       }
03423       else /* Size < 16Bytes  : first block is the last block*/
03424       {
03425         /* Workaround not implemented for TinyAES2*/
03426         /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
03427         Workaround is implemented in polling mode, so if last block of
03428         payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
03429
03430
03431         /* Compute the number of padding bytes in last block of payload */
03432         npblb = 16U - ((uint32_t)hcryp->Size);
03433
03434         if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03435         {
03436           /* Set to 0 the number of non-valid bytes using NPBLB register*/
03437           MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03438         }
03439
03440         /* Number of valid words (lastwordsize) in last block */
03441         if ((npblb % 4U) == 0U)
03442         {
03443           lastwordsize = (16U - npblb) / 4U;
03444         }
03445         else
03446         {
03447           lastwordsize = ((16U - npblb) / 4U) + 1U;
03448         }
03449
03450         /*  last block optionally pad the data with zeros*/
03451         for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
03452         {
03453           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03454           hcryp->CrypInCount++;
03455         }
03456         while (loopcounter < 4U)
03457         {
03458           /* pad the data with zeros to have a complete block */
03459           hcryp->Instance->DINR = 0x0U;
03460           loopcounter++;
03461         }
03462         /* Call Input transfer complete callback */
03463 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03464         /*Call registered Input complete callback*/
03465         hcryp->InCpltCallback(hcryp);
03466 #else
03467         /*Call legacy weak Input complete callback*/
03468         HAL_CRYP_InCpltCallback(hcryp);
03469 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03470       }
03471     }
03472     /* Enter header data */
03473     /* Cher first whether header length is small enough to enter the full header in one shot */
03474     else if (headersize_in_bytes <= 16U)
03475     {
03476       /* Write header data, padded with zeros if need be */
03477       for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
03478       {
03479         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03480         hcryp->CrypHeaderCount++ ;
03481       }
03482       /* If the header size is a multiple of words */
03483       if ((headersize_in_bytes % 4U) == 0U)
03484       {
03485         /* Pad the data with zeros to have a complete block */
03486         while (loopcounter < 4U)
03487         {
03488           hcryp->Instance->DINR = 0x0U;
03489           loopcounter++;
03490           hcryp->CrypHeaderCount++;
03491         }
03492       }
03493       else
03494       {
03495         /* Enter last bytes, padded with zeros */
03496         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03497         tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
03498         hcryp->Instance->DINR = tmp;
03499         loopcounter++;
03500         hcryp->CrypHeaderCount++ ;
03501         /* Pad the data with zeros to have a complete block */
03502       while (loopcounter < 4U)
03503       {
03504         hcryp->Instance->DINR = 0x0U;
03505         loopcounter++;
03506           hcryp->CrypHeaderCount++;
03507         }
03508       }
03509     }
03510     else
03511     {
03512       /* Write the first input header block in the Input FIFO,
03513          the following header data will be fed after interrupt occurrence */
03514       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03515       hcryp->CrypHeaderCount++;
03516       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03517       hcryp->CrypHeaderCount++;
03518       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03519       hcryp->CrypHeaderCount++;
03520       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03521       hcryp->CrypHeaderCount++;
03522     }
03523
03524   } /* end of if (DoKeyIVConfig == 1U) */
03525   else  /* Key and IV have already been configured,
03526           header has already been processed;
03527           only process here message payload */
03528   {
03529
03530     /* Enable computation complete flag and error interrupts */
03531     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03532
03533     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03534     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03535
03536     /* Write the payload Input block in the IN FIFO */
03537     if (hcryp->Size == 0U)
03538     {
03539       /* Disable interrupts */
03540       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03541
03542       /* Change the CRYP state */
03543       hcryp->State = HAL_CRYP_STATE_READY;
03544
03545       /* Process unlocked */
03546       __HAL_UNLOCK(hcryp);
03547     }
03548     else if (hcryp->Size >= 16U)
03549     {
03550       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03551       hcryp->CrypInCount++;
03552       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03553       hcryp->CrypInCount++;
03554       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03555       hcryp->CrypInCount++;
03556       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03557       hcryp->CrypInCount++;
03558       if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
03559       {
03560         /* Call Input transfer complete callback */
03561 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03562         /*Call registered Input complete callback*/
03563         hcryp->InCpltCallback(hcryp);
03564 #else
03565         /*Call legacy weak Input complete callback*/
03566         HAL_CRYP_InCpltCallback(hcryp);
03567 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03568       }
03569     }
03570     else /* Size < 16Bytes  : first block is the last block*/
03571     {
03572       /* Workaround not implemented for TinyAES2*/
03573       /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
03574       Workaround is implemented in polling mode, so if last block of
03575       payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
03576
03577
03578       /* Compute the number of padding bytes in last block of payload */
03579       npblb = 16U - ((uint32_t)hcryp->Size);
03580
03581       if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03582       {
03583         /* Set to 0 the number of non-valid bytes using NPBLB register*/
03584         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03585       }
03586
03587       /* Number of valid words (lastwordsize) in last block */
03588       if ((npblb % 4U) == 0U)
03589       {
03590         lastwordsize = (16U - npblb) / 4U;
03591       }
03592       else
03593       {
03594         lastwordsize = ((16U - npblb) / 4U) + 1U;
03595       }
03596
03597       /*  last block optionally pad the data with zeros*/
03598       for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
03599       {
03600         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03601         hcryp->CrypInCount++;
03602       }
03603       while (loopcounter < 4U)
03604       {
03605         /* pad the data with zeros to have a complete block */
03606         hcryp->Instance->DINR = 0x0U;
03607         loopcounter++;
03608       }
03609       /* Call Input transfer complete callback */
03610 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03611       /*Call registered Input complete callback*/
03612       hcryp->InCpltCallback(hcryp);
03613 #else
03614       /*Call legacy weak Input complete callback*/
03615       HAL_CRYP_InCpltCallback(hcryp);
03616 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03617     }
03618   }
03619
03620   /* Return function status */
03621   return HAL_OK;
03622 }
03623
03624
03625 /**
03626   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
03627   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03628   *         the configuration information for CRYP module
03629   * @retval HAL status
03630   */
03631 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
03632 {
03633   uint32_t count;
03634   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03635
03636   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03637   {
03638     if (hcryp->KeyIVConfig == 1U)
03639     {
03640       /* If the Key and IV configuration has to be done only once
03641          and if it has already been done, skip it */
03642       DoKeyIVConfig = 0U;
03643       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03644     }
03645     else
03646     {
03647       /* If the Key and IV configuration has to be done only once
03648          and if it has not been done already, do it and set KeyIVConfig
03649          to keep track it won't have to be done again next time */
03650       hcryp->KeyIVConfig = 1U;
03651       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03652     }
03653   }
03654   else
03655   {
03656     hcryp->SizesSum = hcryp->Size;
03657   }
03658
03659   if (DoKeyIVConfig == 1U)
03660   {
03661
03662     /*  Reset CrypHeaderCount */
03663     hcryp->CrypHeaderCount = 0U;
03664
03665     /*************************** Init phase ************************************/
03666
03667     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03668
03669     /* Set the key */
03670     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03671
03672     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03673     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03674     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03675     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03676     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03677
03678     /* Enable the CRYP peripheral */
03679     __HAL_CRYP_ENABLE(hcryp);
03680
03681     /* just wait for hash computation */
03682     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03683     do
03684     {
03685       count-- ;
03686       if (count == 0U)
03687       {
03688         /* Disable the CRYP peripheral clock */
03689         __HAL_CRYP_DISABLE(hcryp);
03690
03691         /* Change state */
03692         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03693         hcryp->State = HAL_CRYP_STATE_READY;
03694
03695         /* Process unlocked */
03696         __HAL_UNLOCK(hcryp);
03697         return HAL_ERROR;
03698       }
03699     }
03700     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
03701
03702     /* Clear CCF flag */
03703     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03704
03705     /************************ Header phase *************************************/
03706
03707     if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
03708     {
03709       return HAL_ERROR;
03710     }
03711
03712   }
03713   else
03714   {
03715     /* Initialization and header phases already done, only do payload phase */
03716     if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
03717     {
03718       return HAL_ERROR;
03719     }
03720   } /* if (DoKeyIVConfig == 1U) */
03721
03722   /* Return function status */
03723   return HAL_OK;
03724 }
03725
03726
03727 /**
03728   * @brief  AES CCM encryption/decryption processing in polling mode
03729   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
03730   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03731   *         the configuration information for CRYP module
03732   * @param  Timeout Timeout duration
03733   * @retval HAL status
03734   */
03735 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03736 {
03737   uint32_t tickstart;
03738   uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
03739   uint32_t loopcounter;
03740   uint32_t npblb;
03741   uint32_t lastwordsize;
03742   uint32_t temp[4] ;  /* Temporary CrypOutBuff */
03743   uint32_t incount;  /* Temporary CrypInCount Value */
03744   uint32_t outcount;  /* Temporary CrypOutCount Value */
03745   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03746
03747   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03748   {
03749     if (hcryp->KeyIVConfig == 1U)
03750     {
03751       /* If the Key and IV configuration has to be done only once
03752          and if it has already been done, skip it */
03753       DoKeyIVConfig = 0U;
03754       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03755     }
03756     else
03757     {
03758       /* If the Key and IV configuration has to be done only once
03759          and if it has not been done already, do it and set KeyIVConfig
03760          to keep track it won't have to be done again next time */
03761       hcryp->KeyIVConfig = 1U;
03762       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03763     }
03764   }
03765   else
03766   {
03767     hcryp->SizesSum = hcryp->Size;
03768   }
03769
03770   if (DoKeyIVConfig == 1U)
03771   {
03772     /*  Reset CrypHeaderCount */
03773     hcryp->CrypHeaderCount = 0U;
03774
03775     /********************** Init phase ******************************************/
03776
03777     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03778
03779     /* Set the key */
03780     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03781
03782     /* Set the initialization vector (IV) with B0 */
03783     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
03784     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
03785     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
03786     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
03787
03788     /* Enable the CRYP peripheral */
03789     __HAL_CRYP_ENABLE(hcryp);
03790
03791     /* just wait for hash computation */
03792     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03793     {
03794       /* Change state */
03795       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03796       hcryp->State = HAL_CRYP_STATE_READY;
03797
03798       /* Process unlocked & return error */
03799       __HAL_UNLOCK(hcryp);
03800       return HAL_ERROR;
03801     }
03802     /* Clear CCF flag */
03803     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03804
03805     /************************ Header phase *************************************/
03806     /* Header block(B1) : associated data length expressed in bytes concatenated
03807     with Associated Data (A)*/
03808     if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
03809     {
03810       return HAL_ERROR;
03811     }
03812
03813     /*************************Payload phase ************************************/
03814
03815     /* Set the phase */
03816     hcryp->Phase = CRYP_PHASE_PROCESS;
03817
03818     /* Select payload phase once the header phase is performed */
03819     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
03820
03821     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03822     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03823
03824   } /* if (DoKeyIVConfig == 1U) */
03825
03826   if ((hcryp->Size % 16U) != 0U)
03827   {
03828     /* recalculate  wordsize */
03829     wordsize = ((wordsize / 4U) * 4U) ;
03830   }
03831   /* Get tick */
03832   tickstart = HAL_GetTick();
03833
03834   /* Write input data and get output data */
03835   incount = hcryp->CrypInCount;
03836   outcount = hcryp->CrypOutCount;
03837   while ((incount < wordsize) && (outcount < wordsize))
03838   {
03839     /* Write plain data and get cipher data */
03840     CRYP_AES_ProcessData(hcryp, Timeout);
03841
03842     /* Check for the Timeout */
03843     if (Timeout != HAL_MAX_DELAY)
03844     {
03845       if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U))
03846       {
03847         /* Disable the CRYP peripheral clock */
03848         __HAL_CRYP_DISABLE(hcryp);
03849
03850         /* Change state */
03851         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03852         hcryp->State = HAL_CRYP_STATE_READY;
03853
03854         /* Process unlocked */
03855         __HAL_UNLOCK(hcryp);
03856         return HAL_ERROR;
03857       }
03858     }
03859     incount = hcryp->CrypInCount;
03860     outcount = hcryp->CrypOutCount;
03861   }
03862
03863   if ((hcryp->Size % 16U) != 0U)
03864   {
03865     /* Compute the number of padding bytes in last block of payload */
03866     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
03867
03868     if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
03869     {
03870       /* Set Npblb in case of AES CCM payload decryption to get right tag  */
03871       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20);
03872
03873     }
03874     /* Number of valid words (lastwordsize) in last block */
03875     if ((npblb % 4U) == 0U)
03876     {
03877       lastwordsize = (16U - npblb) / 4U;
03878     }
03879     else
03880     {
03881       lastwordsize = ((16U - npblb) / 4U) + 1U;
03882     }
03883
03884     /* Write the last input block in the IN FIFO */
03885     for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
03886     {
03887       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03888       hcryp->CrypInCount++;
03889     }
03890
03891     /* Pad the data with zeros to have a complete block */
03892     while (loopcounter < 4U)
03893     {
03894       hcryp->Instance->DINR  = 0U;
03895       loopcounter++;
03896     }
03897     /* just wait for hash computation */
03898     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03899     {
03900       /* Change state */
03901       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03902       hcryp->State = HAL_CRYP_STATE_READY;
03903
03904       /* Process unlocked & return error */
03905       __HAL_UNLOCK(hcryp);
03906       return HAL_ERROR;
03907     }
03908     /* Clear CCF flag */
03909     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03910
03911     for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
03912     {
03913       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03914       temp[loopcounter] = hcryp->Instance->DOUTR;
03915     }
03916     for (loopcounter = 0U; loopcounter<lastwordsize; loopcounter++)
03917     {
03918       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter];
03919       hcryp->CrypOutCount++;
03920     }
03921   }
03922
03923   /* Return function status */
03924   return HAL_OK;
03925 }
03926
03927 /**
03928   * @brief  AES CCM encryption/decryption process in interrupt mode
03929   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
03930   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03931   *         the configuration information for CRYP module
03932   * @retval HAL status
03933   */
03934 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
03935 {
03936   __IO uint32_t count = 0U;
03937   uint32_t loopcounter;
03938   uint32_t lastwordsize;
03939   uint32_t npblb;
03940   uint32_t mode;
03941   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03942   uint32_t headersize_in_bytes;
03943   uint32_t tmp;
03944   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
03945                                     0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
03946                                     0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /*  8-bit data type */
03947
03948 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
03949   if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
03950   {
03951     CRYP_PhaseProcessingResume(hcryp);
03952     return HAL_OK;
03953   }
03954 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
03955
03956   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03957   {
03958     if (hcryp->KeyIVConfig == 1U)
03959     {
03960       /* If the Key and IV configuration has to be done only once
03961          and if it has already been done, skip it */
03962       DoKeyIVConfig = 0U;
03963       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03964     }
03965     else
03966     {
03967       /* If the Key and IV configuration has to be done only once
03968          and if it has not been done already, do it and set KeyIVConfig
03969          to keep track it won't have to be done again next time */
03970       hcryp->KeyIVConfig = 1U;
03971       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03972     }
03973   }
03974   else
03975   {
03976     hcryp->SizesSum = hcryp->Size;
03977   }
03978
03979   /* Configure Key, IV and process message (header and payload) */
03980   if (DoKeyIVConfig == 1U)
03981   {
03982     /*  Reset CrypHeaderCount */
03983     hcryp->CrypHeaderCount = 0U;
03984
03985     /********************** Init phase ******************************************/
03986
03987     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03988
03989     /* Set the key */
03990     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03991
03992     /* Set the initialization vector (IV) with B0 */
03993     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
03994     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
03995     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
03996     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
03997
03998     /* Enable the CRYP peripheral */
03999     __HAL_CRYP_ENABLE(hcryp);
04000
04001     /* just wait for hash computation */
04002     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
04003     do
04004     {
04005       count-- ;
04006       if (count == 0U)
04007       {
04008         /* Disable the CRYP peripheral clock */
04009         __HAL_CRYP_DISABLE(hcryp);
04010
04011         /* Change state */
04012         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04013         hcryp->State = HAL_CRYP_STATE_READY;
04014
04015         /* Process unlocked */
04016         __HAL_UNLOCK(hcryp);
04017         return HAL_ERROR;
04018       }
04019     }
04020     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04021
04022     /* Clear CCF flag */
04023     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04024
04025     /***************************** Header phase *********************************/
04026
04027     /* Select header phase */
04028     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04029
04030     /* Enable computation complete flag and error interrupts */
04031     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04032
04033     /* Enable the CRYP peripheral */
04034     __HAL_CRYP_ENABLE(hcryp);
04035
04036     if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
04037     {
04038       headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
04039     }
04040     else
04041     {
04042       headersize_in_bytes = hcryp->Init.HeaderSize;
04043     }
04044
04045     if (headersize_in_bytes == 0U) /* Header phase is  skipped */
04046     {
04047       /* Set the phase */
04048       hcryp->Phase = CRYP_PHASE_PROCESS;
04049       /* Select payload phase once the header phase is performed */
04050       CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
04051       /* Set to 0 the number of non-valid bytes using NPBLB register*/
04052       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
04053
04054       if (hcryp->Init.Algorithm == CRYP_AES_CCM)
04055       {
04056         /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
04057         hcryp->CrypHeaderCount++;
04058       }
04059       /* Write the payload Input block in the IN FIFO */
04060       if (hcryp->Size == 0U)
04061       {
04062         /* Disable interrupts */
04063         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04064
04065         /* Change the CRYP state */
04066         hcryp->State = HAL_CRYP_STATE_READY;
04067
04068         /* Process unlocked */
04069         __HAL_UNLOCK(hcryp);
04070       }
04071       else if (hcryp->Size >= 16U)
04072       {
04073         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04074         hcryp->CrypInCount++;
04075         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04076         hcryp->CrypInCount++;
04077         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04078         hcryp->CrypInCount++;
04079         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04080         hcryp->CrypInCount++;
04081
04082         if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04083         {
04084           /* Call Input transfer complete callback */
04085 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04086           /*Call registered Input complete callback*/
04087           hcryp->InCpltCallback(hcryp);
04088 #else
04089           /*Call legacy weak Input complete callback*/
04090           HAL_CRYP_InCpltCallback(hcryp);
04091 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04092         }
04093       }
04094       else /* Size < 4 words  : first block is the last block*/
04095       {
04096         /* Compute the number of padding bytes in last block of payload */
04097         npblb = 16U - (uint32_t)hcryp->Size;
04098
04099         mode = hcryp->Instance->CR & AES_CR_MODE;
04100         if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04101             ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04102         {
04103           /* Specify the number of non-valid bytes using NPBLB register*/
04104           MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04105         }
04106
04107         /* Number of valid words (lastwordsize) in last block */
04108         if ((npblb % 4U) == 0U)
04109         {
04110           lastwordsize = (16U - npblb) / 4U;
04111         }
04112         else
04113         {
04114           lastwordsize = ((16U - npblb) / 4U) + 1U;
04115         }
04116
04117         /*  Last block optionally pad the data with zeros*/
04118         for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04119         {
04120           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04121           hcryp->CrypInCount++;
04122         }
04123         while (loopcounter < 4U)
04124         {
04125           /* Pad the data with zeros to have a complete block */
04126           hcryp->Instance->DINR = 0x0U;
04127           loopcounter++;
04128         }
04129         /* Call Input transfer complete callback */
04130 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04131         /*Call registered Input complete callback*/
04132         hcryp->InCpltCallback(hcryp);
04133 #else
04134         /*Call legacy weak Input complete callback*/
04135         HAL_CRYP_InCpltCallback(hcryp);
04136 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04137       }
04138     }
04139     /* Enter header data */
04140     /* Check first whether header length is small enough to enter the full header in one shot */
04141     else if (headersize_in_bytes <= 16U)
04142     {
04143       for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
04144       {
04145         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04146         hcryp->CrypHeaderCount++ ;
04147       }
04148       /* If the header size is a multiple of words */
04149       if ((headersize_in_bytes % 4U) == 0U)
04150       {
04151         /* Pad the data with zeros to have a complete block */
04152         while (loopcounter < 4U)
04153         {
04154           hcryp->Instance->DINR = 0x0U;
04155           loopcounter++;
04156         }
04157       }
04158       else
04159       {
04160         /* Enter last bytes, padded with zeros */
04161         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04162         tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
04163         hcryp->Instance->DINR = tmp;
04164         hcryp->CrypHeaderCount++;
04165         loopcounter++;
04166         /* Pad the data with zeros to have a complete block */
04167       while (loopcounter < 4U)
04168       {
04169         hcryp->Instance->DINR = 0x0U;
04170         loopcounter++;
04171       }
04172     }
04173       /* Call Input transfer complete callback */
04174 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04175       /*Call registered Input complete callback*/
04176       hcryp->InCpltCallback(hcryp);
04177 #else
04178       /*Call legacy weak Input complete callback*/
04179       HAL_CRYP_InCpltCallback(hcryp);
04180 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04181     }
04182     else
04183     {
04184       /* Write the first input header block in the Input FIFO,
04185          the following header data will be fed after interrupt occurrence */
04186       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04187       hcryp->CrypHeaderCount++;
04188       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04189       hcryp->CrypHeaderCount++;
04190       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04191       hcryp->CrypHeaderCount++;
04192       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04193       hcryp->CrypHeaderCount++;
04194     }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is  skipped*/
04195   } /* end of if (dokeyivconfig == 1U) */
04196   else  /* Key and IV have already been configured,
04197           header has already been processed;
04198           only process here message payload */
04199   {
04200     /* Write the payload Input block in the IN FIFO */
04201     if (hcryp->Size == 0U)
04202     {
04203       /* Disable interrupts */
04204       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04205
04206       /* Change the CRYP state */
04207       hcryp->State = HAL_CRYP_STATE_READY;
04208
04209       /* Process unlocked */
04210       __HAL_UNLOCK(hcryp);
04211     }
04212     else if (hcryp->Size >= 16U)
04213     {
04214       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04215       hcryp->CrypInCount++;
04216       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04217       hcryp->CrypInCount++;
04218       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04219       hcryp->CrypInCount++;
04220       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04221       hcryp->CrypInCount++;
04222
04223       if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04224       {
04225         /* Call Input transfer complete callback */
04226 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04227         /*Call registered Input complete callback*/
04228         hcryp->InCpltCallback(hcryp);
04229 #else
04230         /*Call legacy weak Input complete callback*/
04231         HAL_CRYP_InCpltCallback(hcryp);
04232 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04233       }
04234     }
04235     else /* Size < 4 words  : first block is the last block*/
04236     {
04237       /* Compute the number of padding bytes in last block of payload */
04238       npblb = 16U - (uint32_t)hcryp->Size;
04239
04240       mode = hcryp->Instance->CR & AES_CR_MODE;
04241       if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04242           ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04243       {
04244         /* Specify the number of non-valid bytes using NPBLB register*/
04245         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04246       }
04247
04248       /* Number of valid words (lastwordsize) in last block */
04249       if ((npblb % 4U) == 0U)
04250       {
04251         lastwordsize = (16U - npblb) / 4U;
04252       }
04253       else
04254       {
04255         lastwordsize = ((16U - npblb) / 4U) + 1U;
04256       }
04257
04258       /*  Last block optionally pad the data with zeros*/
04259       for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04260       {
04261         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04262         hcryp->CrypInCount++;
04263       }
04264       while (loopcounter < 4U)
04265       {
04266         /* Pad the data with zeros to have a complete block */
04267         hcryp->Instance->DINR = 0x0U;
04268         loopcounter++;
04269       }
04270       /* Call Input transfer complete callback */
04271 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04272       /*Call registered Input complete callback*/
04273       hcryp->InCpltCallback(hcryp);
04274 #else
04275       /*Call legacy weak Input complete callback*/
04276       HAL_CRYP_InCpltCallback(hcryp);
04277 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04278     }
04279   }
04280
04281   /* Return function status */
04282   return HAL_OK;
04283 }
04284
04285 /**
04286   * @brief  AES CCM encryption/decryption process in DMA mode
04287   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
04288   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04289   *         the configuration information for CRYP module
04290   * @retval HAL status
04291   */
04292 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
04293 {
04294   uint32_t count;
04295   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
04296
04297   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
04298   {
04299     if (hcryp->KeyIVConfig == 1U)
04300     {
04301       /* If the Key and IV configuration has to be done only once
04302          and if it has already been done, skip it */
04303       DoKeyIVConfig = 0U;
04304       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
04305     }
04306     else
04307     {
04308       /* If the Key and IV configuration has to be done only once
04309          and if it has not been done already, do it and set KeyIVConfig
04310          to keep track it won't have to be done again next time */
04311       hcryp->KeyIVConfig = 1U;
04312       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
04313     }
04314   }
04315   else
04316   {
04317     hcryp->SizesSum = hcryp->Size;
04318   }
04319
04320   if (DoKeyIVConfig == 1U)
04321   {
04322
04323     /*  Reset CrypHeaderCount */
04324     hcryp->CrypHeaderCount = 0U;
04325
04326
04327     /********************** Init phase ******************************************/
04328
04329     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
04330
04331     /* Set the key */
04332     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
04333
04334     /* Set the initialization vector (IV) with B0 */
04335     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
04336     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
04337     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
04338     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
04339
04340     /* Enable the CRYP peripheral */
04341     __HAL_CRYP_ENABLE(hcryp);
04342
04343     /* just wait for hash computation */
04344     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
04345     do
04346     {
04347       count-- ;
04348       if (count == 0U)
04349       {
04350         /* Disable the CRYP peripheral clock */
04351         __HAL_CRYP_DISABLE(hcryp);
04352
04353         /* Change state */
04354         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04355         hcryp->State = HAL_CRYP_STATE_READY;
04356
04357         /* Process unlocked */
04358         __HAL_UNLOCK(hcryp);
04359         return HAL_ERROR;
04360       }
04361     }
04362     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04363
04364     /* Clear CCF flag */
04365     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04366
04367
04368     /********************* Header phase *****************************************/
04369
04370     if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
04371     {
04372       return HAL_ERROR;
04373     }
04374
04375   }
04376   else
04377   {
04378     /* Initialization and header phases already done, only do payload phase */
04379     if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
04380     {
04381       return HAL_ERROR;
04382     }
04383   } /* if (DoKeyIVConfig == 1U) */
04384
04385   /* Return function status */
04386   return HAL_OK;
04387 }
04388
04389 /**
04390   * @brief  Sets the payload phase in interrupt mode
04391   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04392   *         the configuration information for CRYP module
04393   * @retval state
04394   */
04395 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
04396 {
04397   uint32_t loopcounter;
04398   uint32_t temp[4];  /* Temporary CrypOutBuff */
04399   uint32_t lastwordsize;
04400   uint32_t npblb;
04401   uint32_t mode;
04402   uint16_t incount;  /* Temporary CrypInCount Value */
04403   uint16_t outcount;  /* Temporary CrypOutCount Value */
04404   uint32_t i;
04405
04406   /***************************** Payload phase *******************************/
04407
04408   /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
04409   for (i = 0U; i < 4U; i++)
04410   {
04411     temp[i] = hcryp->Instance->DOUTR;
04412   }
04413   i= 0U;
04414   while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
04415   {
04416     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
04417     hcryp->CrypOutCount++;
04418     i++;
04419   }
04420   incount = hcryp->CrypInCount;
04421   outcount = hcryp->CrypOutCount;
04422   if ((outcount >=  (hcryp->Size / 4U)) && ((incount * 4U) >=  hcryp->Size))
04423   {
04424
04425      /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
04426      if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
04427      {
04428       /* Disable computation complete flag and errors interrupts */
04429       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04430      }
04431
04432     /* Change the CRYP state */
04433     hcryp->State = HAL_CRYP_STATE_READY;
04434
04435     /* Process unlocked */
04436     __HAL_UNLOCK(hcryp);
04437
04438     /* Call output transfer complete callback */
04439 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04440     /*Call registered Output complete callback*/
04441     hcryp->OutCpltCallback(hcryp);
04442 #else
04443     /*Call legacy weak Output complete callback*/
04444     HAL_CRYP_OutCpltCallback(hcryp);
04445 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04446   }
04447
04448   else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
04449   {
04450
04451 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
04452     /* If suspension flag has been raised, suspend processing
04453        only if not already at the end of the payload */
04454     if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
04455     {
04456       /* Clear CCF Flag */
04457       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04458
04459       /* reset SuspendRequest */
04460       hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
04461       /* Disable Computation Complete Flag and Errors Interrupts */
04462       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
04463       /* Change the CRYP state */
04464       hcryp->State = HAL_CRYP_STATE_SUSPENDED;
04465       /* Mark that the payload phase is suspended */
04466       hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
04467
04468      /* Process Unlocked */
04469       __HAL_UNLOCK(hcryp);
04470     }
04471     else
04472 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
04473     {
04474     /* Write the input block in the IN FIFO */
04475     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04476     hcryp->CrypInCount++;
04477     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04478     hcryp->CrypInCount++;
04479     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04480     hcryp->CrypInCount++;
04481     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04482     hcryp->CrypInCount++;
04483     if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04484     {
04485       /* Call input transfer complete callback */
04486 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04487       /*Call registered Input complete callback*/
04488       hcryp->InCpltCallback(hcryp);
04489 #else
04490       /*Call legacy weak Input complete callback*/
04491       HAL_CRYP_InCpltCallback(hcryp);
04492 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04493     }
04494   }
04495   }
04496   else /* Last block of payload < 128bit*/
04497   {
04498     /* Compute the number of padding bytes in last block of payload */
04499     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
04500
04501     mode = hcryp->Instance->CR & AES_CR_MODE;
04502     if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04503         ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04504     {
04505       /* Specify the number of non-valid bytes using NPBLB register*/
04506       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04507     }
04508
04509     /* Number of valid words (lastwordsize) in last block */
04510     if ((npblb % 4U) == 0U)
04511     {
04512       lastwordsize = (16U - npblb) / 4U;
04513     }
04514     else
04515     {
04516       lastwordsize = ((16U - npblb) / 4U) + 1U;
04517     }
04518
04519     /*  Last block optionally pad the data with zeros*/
04520     for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04521     {
04522       hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04523       hcryp->CrypInCount++;
04524     }
04525     while (loopcounter < 4U)
04526     {
04527       /* pad the data with zeros to have a complete block */
04528       hcryp->Instance->DINR = 0x0U;
04529       loopcounter++;
04530     }
04531       /* Call input transfer complete callback */
04532 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04533       /*Call registered Input complete callback*/
04534       hcryp->InCpltCallback(hcryp);
04535 #else
04536       /*Call legacy weak Input complete callback*/
04537       HAL_CRYP_InCpltCallback(hcryp);
04538 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04539   }
04540 }
04541
04542
04543 /**
04544   * @brief  Sets the payload phase in DMA mode
04545   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04546   *         the configuration information for CRYP module
04547   * @retval state
04548   */
04549 static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp)
04550 {
04551   uint16_t wordsize = hcryp->Size / 4U ;
04552   uint32_t index;
04553   uint32_t npblb;
04554   uint32_t lastwordsize;
04555   uint32_t temp[4];  /* Temporary CrypOutBuff */
04556   uint32_t count;
04557   uint32_t reg;
04558
04559   /************************ Payload phase ************************************/
04560   if (hcryp->Size == 0U)
04561   {
04562     /* Process unLocked */
04563     __HAL_UNLOCK(hcryp);
04564
04565     /* Change the CRYP state and phase */
04566     hcryp->State = HAL_CRYP_STATE_READY;
04567   }
04568   else if (hcryp->Size >= 16U)
04569   {
04570     /*DMA transfer must not include the last block in case of Size is not %16 */
04571     wordsize = wordsize - (wordsize % 4U);
04572
04573     /*DMA transfer */
04574     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
04575   }
04576   else /* length of input data is < 16 */
04577   {
04578     /* Compute the number of padding bytes in last block of payload */
04579     npblb = 16U - (uint32_t)hcryp->Size;
04580
04581     /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
04582     reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE);
04583     if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\
04584         (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT)))
04585     {
04586       /* Specify the number of non-valid bytes using NPBLB register*/
04587       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04588     }
04589
04590     /* Number of valid words (lastwordsize) in last block */
04591     if ((npblb % 4U) == 0U)
04592     {
04593       lastwordsize = (16U - npblb) / 4U;
04594     }
04595     else
04596     {
04597       lastwordsize = ((16U - npblb) / 4U) + 1U;
04598     }
04599
04600     /*  last block optionally pad the data with zeros*/
04601     for (index = 0U; index < lastwordsize; index ++)
04602     {
04603       /* Write the last Input block in the IN FIFO */
04604       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04605       hcryp->CrypInCount++;
04606     }
04607     while (index < 4U)
04608     {
04609       /* pad the data with zeros to have a complete block */
04610       hcryp->Instance->DINR  = 0U;
04611       index++;
04612     }
04613     /* Call the input data transfer complete callback */
04614 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04615     /*Call registered Input complete callback*/
04616     hcryp->InCpltCallback(hcryp);
04617 #else
04618     /*Call legacy weak Input complete callback*/
04619     HAL_CRYP_InCpltCallback(hcryp);
04620 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04621     /* Wait for CCF flag to be raised */
04622     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04623     do
04624     {
04625       count-- ;
04626       if (count == 0U)
04627       {
04628         /* Disable the CRYP peripheral clock */
04629         __HAL_CRYP_DISABLE(hcryp);
04630
04631         /* Change state */
04632         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04633         hcryp->State = HAL_CRYP_STATE_READY;
04634
04635         /* Process unlocked */
04636         __HAL_UNLOCK(hcryp);
04637         return HAL_ERROR;
04638       }
04639     }
04640     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04641
04642     /* Clear CCF Flag */
04643     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04644
04645     /*Read the output block from the output FIFO */
04646     for (index = 0U; index < 4U; index++)
04647     {
04648       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
04649       temp[index] = hcryp->Instance->DOUTR;
04650     }
04651     for (index = 0U; index < lastwordsize; index++)
04652     {
04653       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
04654       hcryp->CrypOutCount++;
04655     }
04656
04657     /* Change the CRYP state to ready */
04658     hcryp->State = HAL_CRYP_STATE_READY;
04659
04660     /* Process unlocked */
04661     __HAL_UNLOCK(hcryp);
04662
04663       /* Call Output transfer complete callback */
04664 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04665       /*Call registered Output complete callback*/
04666       hcryp->OutCpltCallback(hcryp);
04667 #else
04668       /*Call legacy weak Output complete callback*/
04669       HAL_CRYP_OutCpltCallback(hcryp);
04670 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04671   }
04672
04673   return HAL_OK;
04674 }
04675
04676 /**
04677   * @brief  Sets the header phase in polling mode
04678   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04679   *         the configuration information for CRYP module(Header & HeaderSize)
04680   * @param  Timeout Timeout value
04681   * @retval state
04682   */
04683 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
04684 {
04685   uint32_t loopcounter;
04686   uint32_t size_in_bytes;
04687   uint32_t tmp;
04688   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
04689                                     0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
04690                                     0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /*  8-bit data type */
04691
04692   /***************************** Header phase for GCM/GMAC or CCM *********************************/
04693   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
04694   {
04695     size_in_bytes = hcryp->Init.HeaderSize * 4U;
04696   }
04697   else
04698   {
04699     size_in_bytes = hcryp->Init.HeaderSize;
04700   }
04701
04702   if ((size_in_bytes != 0U))
04703   {
04704     /* Select header phase */
04705     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04706
04707     /* Enable the CRYP peripheral */
04708     __HAL_CRYP_ENABLE(hcryp);
04709
04710     /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
04711     if ((size_in_bytes % 16U) == 0U)
04712     {
04713       /*  No padding */
04714       for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
04715       {
04716         /* Write the input block in the data input register */
04717         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04718         hcryp->CrypHeaderCount++ ;
04719         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04720         hcryp->CrypHeaderCount++ ;
04721         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04722         hcryp->CrypHeaderCount++ ;
04723         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04724         hcryp->CrypHeaderCount++ ;
04725
04726         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04727         {
04728           /* Disable the CRYP peripheral clock */
04729           __HAL_CRYP_DISABLE(hcryp);
04730
04731           /* Change state */
04732           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04733           hcryp->State = HAL_CRYP_STATE_READY;
04734
04735           /* Process unlocked */
04736           __HAL_UNLOCK(hcryp);
04737           return HAL_ERROR;
04738         }
04739         /* Clear CCF flag */
04740         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04741       }
04742     }
04743     else
04744     {
04745       /* Write header block in the IN FIFO without last block */
04746       for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
04747       {
04748         /* Write the input block in the data input register */
04749         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04750         hcryp->CrypHeaderCount++ ;
04751         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04752         hcryp->CrypHeaderCount++ ;
04753         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04754         hcryp->CrypHeaderCount++ ;
04755         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04756         hcryp->CrypHeaderCount++ ;
04757
04758         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04759         {
04760           /* Disable the CRYP peripheral clock */
04761           __HAL_CRYP_DISABLE(hcryp);
04762
04763           /* Change state */
04764           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04765           hcryp->State = HAL_CRYP_STATE_READY;
04766
04767           /* Process unlocked */
04768           __HAL_UNLOCK(hcryp);
04769           return HAL_ERROR;
04770         }
04771         /* Clear CCF flag */
04772         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04773       }
04774       /* Write last complete words */
04775       for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
04776       {
04777         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04778         hcryp->CrypHeaderCount++ ;
04779       }
04780       /* If the header size is a multiple of words */
04781       if ((size_in_bytes % 4U) == 0U)
04782       {
04783         /* Pad the data with zeros to have a complete block */
04784         while (loopcounter < 4U)
04785         {
04786           hcryp->Instance->DINR = 0x0U;
04787           loopcounter++;
04788         }
04789       }
04790       else
04791       {
04792          /* Enter last bytes, padded with zeros */
04793          tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04794          tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
04795          hcryp->Instance->DINR = tmp;
04796          loopcounter++;
04797          /* Pad the data with zeros to have a complete block */
04798          while (loopcounter < 4U)
04799          {
04800            hcryp->Instance->DINR = 0x0U;
04801            loopcounter++;
04802          }
04803       }
04804
04805       if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04806       {
04807         /* Disable the CRYP peripheral clock */
04808         __HAL_CRYP_DISABLE(hcryp);
04809
04810         /* Change state */
04811         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04812         hcryp->State = HAL_CRYP_STATE_READY;
04813
04814         /* Process unlocked */
04815         __HAL_UNLOCK(hcryp);
04816         return HAL_ERROR;
04817       }
04818       /* Clear CCF flag */
04819       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04820     }
04821   }
04822   else
04823   {
04824     /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
04825     MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
04826
04827     /* Select header phase */
04828     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04829
04830     /* Enable the CRYP peripheral */
04831     __HAL_CRYP_ENABLE(hcryp);
04832   }
04833   /* Return function status */
04834   return HAL_OK;
04835 }
04836
04837 /**
04838   * @brief  Sets the header phase when using DMA in process
04839   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04840   *         the configuration information for CRYP module(Header & HeaderSize)
04841   * @retval None
04842   */
04843 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
04844 {
04845   uint32_t loopcounter;
04846   uint32_t headersize_in_bytes;
04847   uint32_t tmp;
04848   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
04849                                     0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
04850                                     0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /*  8-bit data type */
04851
04852   /***************************** Header phase for GCM/GMAC or CCM *********************************/
04853   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
04854   {
04855     headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
04856   }
04857   else
04858   {
04859     headersize_in_bytes = hcryp->Init.HeaderSize;
04860   }
04861
04862   /* Select header phase */
04863   CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04864
04865   /* Enable the CRYP peripheral */
04866   __HAL_CRYP_ENABLE(hcryp);
04867
04868   /* Set the phase */
04869   hcryp->Phase = CRYP_PHASE_PROCESS;
04870
04871   /* If header size is at least equal to 16 bytes, feed the header through DMA.
04872      If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ),
04873      last bytes feeding and padding will be done in CRYP_DMAInCplt() */
04874   if (headersize_in_bytes >= 16U)
04875   {
04876     /* Initiate header DMA transfer */
04877     if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK)
04878     {
04879       return HAL_ERROR;
04880     }
04881   }
04882   else
04883   {
04884     if (headersize_in_bytes != 0U)
04885     {
04886       /* Header length is larger than 0 and strictly less than 16 bytes */
04887       /* Write last complete words */
04888       for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
04889       {
04890         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04891         hcryp->CrypHeaderCount++ ;
04892       }
04893       /* If the header size is a multiple of words */
04894       if ((headersize_in_bytes % 4U) == 0U)
04895       {
04896         /* Pad the data with zeros to have a complete block */
04897         while (loopcounter < 4U)
04898         {
04899           hcryp->Instance->DINR = 0x0U;
04900           loopcounter++;
04901         }
04902       }
04903       else
04904       {
04905         /* Enter last bytes, padded with zeros */
04906         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04907         tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
04908         hcryp->Instance->DINR = tmp;
04909         loopcounter++;
04910         /* Pad the data with zeros to have a complete block */
04911         while (loopcounter < 4U)
04912         {
04913           hcryp->Instance->DINR = 0x0U;
04914           loopcounter++;
04915         }
04916       }
04917
04918       if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK)
04919       {
04920         /* Disable the CRYP peripheral clock */
04921         __HAL_CRYP_DISABLE(hcryp);
04922
04923         /* Change state */
04924         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04925         hcryp->State = HAL_CRYP_STATE_READY;
04926
04927         /* Process unlocked */
04928         __HAL_UNLOCK(hcryp);
04929         return HAL_ERROR;
04930       }
04931       /* Clear CCF flag */
04932       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04933     } /* if (headersize_in_bytes != 0U) */
04934
04935     /* Move to payload phase if header length is null or
04936        if the header length was less than 16 and header written by software instead of DMA */
04937
04938     /* Set to 0 the number of non-valid bytes using NPBLB register*/
04939     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
04940
04941     /* Select payload phase once the header phase is performed */
04942     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
04943
04944     /* Initiate payload DMA IN and processed data DMA OUT transfers */
04945     if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
04946     {
04947       return HAL_ERROR;
04948     }
04949   } /* if (headersize_in_bytes >= 16U) */
04950
04951   /* Return function status */
04952   return HAL_OK;
04953 }
04954
04955 /**
04956   * @brief  Sets the header phase in interrupt mode
04957   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04958   *         the configuration information for CRYP module(Header & HeaderSize)
04959   * @retval None
04960   */
04961 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
04962 {
04963   uint32_t loopcounter;
04964   uint32_t lastwordsize;
04965   uint32_t npblb;
04966   uint32_t mode;
04967   uint32_t headersize_in_bytes;
04968   uint32_t tmp;
04969   static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
04970                                     0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
04971                                     0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /*  8-bit data type */
04972
04973   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
04974   {
04975     headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
04976   }
04977   else
04978   {
04979     headersize_in_bytes = hcryp->Init.HeaderSize;
04980   }
04981
04982   /***************************** Header phase *********************************/
04983   /* Test whether or not the header phase is over.
04984      If the test below is true, move to payload phase */
04985   if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
04986   {
04987     /* Set the phase */
04988     hcryp->Phase = CRYP_PHASE_PROCESS;
04989     /* Select payload phase */
04990     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
04991     /* Set to 0 the number of non-valid bytes using NPBLB register*/
04992     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
04993
04994     if (hcryp->Init.Algorithm == CRYP_AES_CCM)
04995     {
04996       /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
04997       hcryp->CrypHeaderCount++;
04998     }
04999     /* Write the payload Input block in the IN FIFO */
05000     if (hcryp->Size == 0U)
05001     {
05002       /* Disable interrupts */
05003       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
05004
05005       /* Change the CRYP state */
05006       hcryp->State = HAL_CRYP_STATE_READY;
05007
05008       /* Process unlocked */
05009       __HAL_UNLOCK(hcryp);
05010     }
05011     else if (hcryp->Size >= 16U)
05012     {
05013       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05014       hcryp->CrypInCount++;
05015       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05016       hcryp->CrypInCount++;
05017       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05018       hcryp->CrypInCount++;
05019       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05020       hcryp->CrypInCount++;
05021
05022       if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
05023       {
05024         /* Call the input data transfer complete callback */
05025 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
05026         /*Call registered Input complete callback*/
05027         hcryp->InCpltCallback(hcryp);
05028 #else
05029         /*Call legacy weak Input complete callback*/
05030         HAL_CRYP_InCpltCallback(hcryp);
05031 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05032       }
05033     }
05034     else /* Size < 4 words  : first block is the last block*/
05035     {
05036       /* Compute the number of padding bytes in last block of payload */
05037       npblb = 16U - ((uint32_t)hcryp->Size);
05038       mode = hcryp->Instance->CR & AES_CR_MODE;
05039       if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
05040           ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
05041       {
05042         /* Specify the number of non-valid bytes using NPBLB register*/
05043         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
05044       }
05045
05046       /* Number of valid words (lastwordsize) in last block */
05047       if ((npblb % 4U) == 0U)
05048       {
05049         lastwordsize = (16U - npblb) / 4U;
05050       }
05051       else
05052       {
05053         lastwordsize = ((16U - npblb) / 4U) + 1U;
05054       }
05055
05056       /*  Last block optionally pad the data with zeros*/
05057       for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
05058       {
05059         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
05060         hcryp->CrypInCount++;
05061       }
05062       while (loopcounter < 4U)
05063       {
05064         /* Pad the data with zeros to have a complete block */
05065         hcryp->Instance->DINR = 0x0U;
05066         loopcounter++;
05067       }
05068       /* Call the input data transfer complete callback */
05069 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
05070       /*Call registered Input complete callback*/
05071       hcryp->InCpltCallback(hcryp);
05072 #else
05073       /*Call legacy weak Input complete callback*/
05074       HAL_CRYP_InCpltCallback(hcryp);
05075 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05076     }
05077   }
05078   else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
05079   {
05080     /* Can enter full 4 header words */
05081 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
05082     /* If suspension flag has been raised, suspend processing
05083        only if not already at the end of the header */
05084     if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
05085     {
05086       /* Clear CCF Flag */
05087       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
05088
05089       /* reset SuspendRequest */
05090       hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
05091       /* Disable Computation Complete Flag and Errors Interrupts */
05092       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
05093       /* Change the CRYP state */
05094       hcryp->State = HAL_CRYP_STATE_SUSPENDED;
05095       /* Mark that the payload phase is suspended */
05096       hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
05097
05098      /* Process Unlocked */
05099       __HAL_UNLOCK(hcryp);
05100     }
05101     else
05102 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
05103     {
05104     /* Write the input block in the IN FIFO */
05105     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05106     hcryp->CrypHeaderCount++;
05107     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05108     hcryp->CrypHeaderCount++;
05109     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05110     hcryp->CrypHeaderCount++;
05111     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05112     hcryp->CrypHeaderCount++;
05113   }
05114   }
05115   else /* Write last header block (4 words), padded with zeros if needed */
05116   {
05117
05118     for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
05119     {
05120       hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05121       hcryp->CrypHeaderCount++ ;
05122     }
05123     /* If the header size is a multiple of words */
05124     if ((headersize_in_bytes % 4U) == 0U)
05125     {
05126       /* Pad the data with zeros to have a complete block */
05127       while (loopcounter < 4U)
05128       {
05129         hcryp->Instance->DINR = 0x0U;
05130         loopcounter++;
05131         hcryp->CrypHeaderCount++;
05132       }
05133     }
05134     else
05135     {
05136       /* Enter last bytes, padded with zeros */
05137       tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05138       tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
05139       hcryp->Instance->DINR = tmp;
05140       loopcounter++;
05141       hcryp->CrypHeaderCount++;
05142       /* Pad the data with zeros to have a complete block */
05143     while (loopcounter < 4U)
05144     {
05145       hcryp->Instance->DINR = 0x0U;
05146       loopcounter++;
05147         hcryp->CrypHeaderCount++;
05148       }
05149     }
05150   }
05151 }
05152
05153 /**
05154   * @brief  Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
05155   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05156   *         the configuration information for CRYP module.
05157   * @param  Timeout Timeout duration.
05158   * @note   This function can only be used in thread mode.
05159   * @retval HAL status
05160   */
05161 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
05162 {
05163   uint32_t tickstart;
05164
05165   /* Get timeout */
05166   tickstart = HAL_GetTick();
05167
05168   while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
05169   {
05170     /* Check for the Timeout */
05171     if (Timeout != HAL_MAX_DELAY)
05172     {
05173       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
05174       {
05175         return HAL_ERROR;
05176       }
05177     }
05178   }
05179   return HAL_OK;
05180 }
05181
05182 /**
05183   * @brief  Wait for Computation Complete Flag (CCF) to raise then clear it.
05184   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05185   *         the configuration information for CRYP module.
05186   * @param  Timeout Timeout duration.
05187   * @note   This function can be used in thread or handler mode.
05188   * @retval HAL status
05189   */
05190 static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
05191 {
05192   uint32_t count = Timeout;
05193
05194   do
05195   {
05196     count-- ;
05197     if (count == 0U)
05198     {
05199       /* Disable the CRYP peripheral clock */
05200       __HAL_CRYP_DISABLE(hcryp);
05201
05202       /* Change state */
05203       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
05204
05205       /* Process unlocked */
05206       __HAL_UNLOCK(hcryp);
05207       hcryp->State = HAL_CRYP_STATE_READY;
05208
05209 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
05210     /*Call registered error callback*/
05211     hcryp->ErrorCallback(hcryp);
05212 #else
05213     /*Call legacy weak error callback*/
05214     HAL_CRYP_ErrorCallback(hcryp);
05215 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05216     }
05217   }
05218   while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
05219
05220   /* Clear CCF flag */
05221   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
05222 }
05223
05224 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
05225 /**
05226   * @brief  In case of message processing suspension, read the Initialization Vector.
05227   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05228   *         the configuration information for CRYP module.
05229   * @param  Output Pointer to the buffer containing the saved Initialization Vector.
05230   * @note   This value has to be stored for reuse by writing the AES_IVRx registers
05231   *         as soon as the suspended processing has to be resumed.
05232   * @retval None
05233   */
05234 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output)
05235 {
05236   uint32_t outputaddr = (uint32_t)Output;
05237
05238   *(uint32_t*)(outputaddr) = hcryp->Instance->IVR3;
05239   outputaddr+=4U;
05240   *(uint32_t*)(outputaddr) = hcryp->Instance->IVR2;
05241   outputaddr+=4U;
05242   *(uint32_t*)(outputaddr) = hcryp->Instance->IVR1;
05243   outputaddr+=4U;
05244   *(uint32_t*)(outputaddr) = hcryp->Instance->IVR0;
05245 }
05246
05247 /**
05248   * @brief  In case of message processing resumption, rewrite the Initialization
05249   *         Vector in the AES_IVRx registers.
05250   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05251   *         the configuration information for CRYP module.
05252   * @param  Input Pointer to the buffer containing the saved Initialization Vector to
05253   *         write back in the CRYP hardware block.
05254   * @note   AES must be disabled when reconfiguring the IV values.
05255   * @retval None
05256   */
05257 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input)
05258 {
05259   uint32_t ivaddr = (uint32_t)Input;
05260
05261   hcryp->Instance->IVR3 = *(uint32_t*)(ivaddr);
05262   ivaddr+=4U;
05263   hcryp->Instance->IVR2 = *(uint32_t*)(ivaddr);
05264   ivaddr+=4U;
05265   hcryp->Instance->IVR1 = *(uint32_t*)(ivaddr);
05266   ivaddr+=4U;
05267   hcryp->Instance->IVR0 = *(uint32_t*)(ivaddr);
05268 }
05269
05270 /**
05271   * @brief  In case of message GCM/GMAC/CCM processing suspension,
05272   *         read the Suspend Registers.
05273   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05274   *         the configuration information for CRYP module.
05275   * @param  Output Pointer to the buffer containing the saved Suspend Registers.
05276   * @note   These values have to be stored for reuse by writing back the AES_SUSPxR registers
05277   *         as soon as the suspended processing has to be resumed.
05278   * @retval None
05279   */
05280 static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output)
05281 {
05282   uint32_t outputaddr = (uint32_t)Output;
05283   __IO uint32_t count = 0U;
05284
05285   /* In case of GCM payload phase encryption, check that suspension can be carried out */
05286   if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U))
05287   {
05288
05289       /* Wait for BUSY flag to be cleared */
05290       count = 0xFFF;
05291       do
05292       {
05293         count-- ;
05294         if(count == 0U)
05295         {
05296           /* Change state */
05297           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
05298           hcryp->State = HAL_CRYP_STATE_READY;
05299
05300           /* Process unlocked */
05301           __HAL_UNLOCK(hcryp);
05302           HAL_CRYP_ErrorCallback(hcryp);
05303           return;
05304         }
05305       }
05306       while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY));
05307
05308   }
05309
05310
05311   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP7R;
05312   outputaddr+=4U;
05313   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP6R;
05314   outputaddr+=4U;
05315   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP5R;
05316   outputaddr+=4U;
05317   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP4R;
05318   outputaddr+=4U;
05319   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP3R;
05320   outputaddr+=4U;
05321   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP2R;
05322   outputaddr+=4U;
05323   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP1R;
05324   outputaddr+=4U;
05325   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP0R;
05326 }
05327
05328 /**
05329   * @brief  In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend
05330   *         Registers in the AES_SUSPxR registers.
05331   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05332   *         the configuration information for CRYP module.
05333   * @param  Input Pointer to the buffer containing the saved suspend registers to
05334   *         write back in the CRYP hardware block.
05335   * @note   AES must be disabled when reconfiguring the suspend registers.
05336   * @retval None
05337   */
05338 static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input)
05339 {
05340   uint32_t ivaddr = (uint32_t)Input;
05341
05342   hcryp->Instance->SUSP7R = *(uint32_t*)(ivaddr);
05343   ivaddr+=4U;
05344   hcryp->Instance->SUSP6R = *(uint32_t*)(ivaddr);
05345   ivaddr+=4U;
05346   hcryp->Instance->SUSP5R = *(uint32_t*)(ivaddr);
05347   ivaddr+=4U;
05348   hcryp->Instance->SUSP4R = *(uint32_t*)(ivaddr);
05349   ivaddr+=4U;
05350   hcryp->Instance->SUSP3R = *(uint32_t*)(ivaddr);
05351   ivaddr+=4U;
05352   hcryp->Instance->SUSP2R = *(uint32_t*)(ivaddr);
05353   ivaddr+=4U;
05354   hcryp->Instance->SUSP1R = *(uint32_t*)(ivaddr);
05355   ivaddr+=4U;
05356   hcryp->Instance->SUSP0R = *(uint32_t*)(ivaddr);
05357 }
05358
05359 /**
05360   * @brief  In case of message GCM/GMAC/CCM processing suspension, read the Key Registers.
05361   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05362   *         the configuration information for CRYP module.
05363   * @param  Output Pointer to the buffer containing the saved Key Registers.
05364   * @param  KeySize Indicates the key size (128 or 256 bits).
05365   * @note   These values have to be stored for reuse by writing back the AES_KEYRx registers
05366   *         as soon as the suspended processing has to be resumed.
05367   * @retval None
05368   */
05369 static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize)
05370 {
05371   uint32_t keyaddr = (uint32_t)Output;
05372
05373   switch (KeySize)
05374   {
05375     case CRYP_KEYSIZE_256B:
05376       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
05377       keyaddr+=4U;
05378       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
05379       keyaddr+=4U;
05380       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
05381       keyaddr+=4U;
05382       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
05383       keyaddr+=4U;
05384       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U);
05385       keyaddr+=4U;
05386       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U);
05387       keyaddr+=4U;
05388       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U);
05389       keyaddr+=4U;
05390       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U);
05391       break;
05392     case CRYP_KEYSIZE_128B:
05393       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
05394       keyaddr+=4U;
05395       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
05396       keyaddr+=4U;
05397       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
05398       keyaddr+=4U;
05399       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
05400       break;
05401     default:
05402       break;
05403   }
05404 }
05405
05406 /**
05407   * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key
05408   *         Registers in the AES_KEYRx registers.
05409   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05410   *         the configuration information for CRYP module.
05411   * @param  Input Pointer to the buffer containing the saved key registers to
05412   *         write back in the CRYP hardware block.
05413   * @param  KeySize Indicates the key size (128 or 256 bits)
05414   * @note   AES must be disabled when reconfiguring the Key registers.
05415   * @retval None
05416   */
05417 static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize)
05418 {
05419   uint32_t keyaddr = (uint32_t)Input;
05420
05421   if (KeySize == CRYP_KEYSIZE_256B)
05422   {
05423     hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr);
05424     keyaddr+=4U;
05425     hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr);
05426     keyaddr+=4U;
05427     hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr);
05428     keyaddr+=4U;
05429     hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr);
05430     keyaddr+=4U;
05431   }
05432
05433     hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr);
05434     keyaddr+=4U;
05435     hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr);
05436     keyaddr+=4U;
05437     hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr);
05438     keyaddr+=4U;
05439     hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr);
05440 }
05441
05442 /**
05443   * @brief  Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode
05444   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05445   *         the configuration information for CRYP module(Header & HeaderSize)
05446   * @retval None
05447   */
05448 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
05449 {
05450   uint32_t loopcounter;
05451   uint16_t lastwordsize;
05452   uint16_t npblb;
05453   uint32_t cr_temp;
05454
05455
05456   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR | CRYP_CCF_CLEAR);
05457
05458   /* Enable computation complete flag and error interrupts */
05459   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
05460
05461   /* Enable the CRYP peripheral */
05462   __HAL_CRYP_ENABLE(hcryp);
05463
05464   /* Case of header phase resumption =================================================*/
05465   if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
05466   {
05467       /* Set the phase */
05468     hcryp->Phase = CRYP_PHASE_PROCESS;
05469
05470     /* Select header phase */
05471     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
05472
05473     if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
05474     {
05475       /* Write the input block in the IN FIFO */
05476       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
05477       hcryp->CrypHeaderCount++;
05478       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
05479       hcryp->CrypHeaderCount++;
05480       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
05481       hcryp->CrypHeaderCount++;
05482       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
05483       hcryp->CrypHeaderCount++;
05484     }
05485     else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
05486     {
05487       /*  Last block optionally pad the data with zeros*/
05488       for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
05489       {
05490         hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05491         hcryp->CrypHeaderCount++ ;
05492       }
05493       while(loopcounter <4U )
05494       {
05495         /* pad the data with zeros to have a complete block */
05496         hcryp->Instance->DINR = 0x0U;
05497         loopcounter++;
05498       }
05499     }
05500   }
05501   /* Case of payload phase resumption =================================================*/
05502   else
05503   {
05504     if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
05505     {
05506
05507       /* Set the phase */
05508       hcryp->Phase = CRYP_PHASE_PROCESS;
05509
05510       /* Select payload phase once the header phase is performed */
05511       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
05512
05513       /* Set to 0 the number of non-valid bytes using NPBLB register*/
05514       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
05515
05516       if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
05517       {
05518         /* Write the input block in the IN FIFO */
05519         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05520         hcryp->CrypInCount++;
05521         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05522         hcryp->CrypInCount++;
05523         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05524         hcryp->CrypInCount++;
05525         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05526         hcryp->CrypInCount++;
05527         if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
05528         {
05529           /* Call input transfer complete callback */
05530 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
05531           /*Call registered Input complete callback*/
05532           hcryp->InCpltCallback(hcryp);
05533 #else
05534           /*Call legacy weak Input complete callback*/
05535           HAL_CRYP_InCpltCallback(hcryp);
05536 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05537         }
05538       }
05539       else /* Last block of payload < 128bit*/
05540       {
05541         /* Compute the number of padding bytes in last block of payload */
05542         npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size);
05543         cr_temp = hcryp->Instance->CR;
05544         if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
05545            (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
05546         {
05547           /* Specify the number of non-valid bytes using NPBLB register*/
05548             MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U);
05549         }
05550
05551         /* Number of valid words (lastwordsize) in last block */
05552         if ((npblb % 4U) ==0U)
05553         {
05554           lastwordsize = (16U-npblb)/4U;
05555         }
05556         else
05557         {
05558           lastwordsize = ((16U-npblb)/4U) +1U;
05559         }
05560
05561         /*  Last block optionally pad the data with zeros*/
05562         for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
05563         {
05564           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05565           hcryp->CrypInCount++;
05566         }
05567         while(loopcounter < 4U )
05568         {
05569           /* pad the data with zeros to have a complete block */
05570           hcryp->Instance->DINR = 0x0U;
05571           loopcounter++;
05572         }
05573       }
05574     }
05575   }
05576 }
05577 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
05578 /**
05579   * @}
05580   */
05581
05582
05583 #endif /* HAL_CRYP_MODULE_ENABLED */
05584
05585 #endif /* AES */
05586 /**
05587   * @}
05588   */
05589
05590 /**
05591  * @}
05592  */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cryp.h Source File

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stm32g0xx_hal_cryp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_cryp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRYP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_CRYP_H
00021 #define STM32G0xx_HAL_CRYP_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 #if defined(AES)
00035
00036 /** @defgroup CRYP CRYP
00037   * @brief CRYP HAL module driver.
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042
00043 /** @defgroup CRYP_Exported_Types CRYP Exported Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief CRYP Init Structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00054                                         This parameter can be a value of @ref CRYP_Data_Type */
00055   uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
00056                                         128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
00057   uint32_t *pKey;                      /*!< The key used for encryption/decryption */
00058   uint32_t *pInitVect;                 /*!< The initialization vector used also as initialization
00059                                          counter in CTR mode */
00060   uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC
00061                                         AES Algorithm ECB/CBC/CTR/GCM or CCM
00062                                         This parameter can be a value of @ref CRYP_Algorithm_Mode */
00063   uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
00064                                         GCM : also known as Additional Authentication Data
00065                                         CCM : named B1 composed of the associated data length and Associated Data. */
00066   uint32_t HeaderSize;                 /*!< The size of header buffer */
00067   uint32_t *B0;                        /*!< B0 is first authentication block used only  in AES CCM mode */
00068   uint32_t DataWidthUnit;              /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
00069   uint32_t HeaderWidthUnit;            /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
00070   uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
00071                                            Vector only once and to skip configuration for consecutive processings.
00072                                            This parameter can be a value of @ref CRYP_Configuration_Skip */
00073
00074 } CRYP_ConfigTypeDef;
00075
00076
00077 /**
00078   * @brief  CRYP State Structure definition
00079   */
00080
00081 typedef enum
00082 {
00083   HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
00084   HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
00085   HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP BUSY, internal processing is ongoing  */
00086 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00087   HAL_CRYP_STATE_SUSPENDED         = 0x03U,   /*!< CRYP suspended                        */
00088 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00089 } HAL_CRYP_STATETypeDef;
00090
00091 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00092 /**
00093   * @brief HAL CRYP mode suspend definitions
00094   */
00095 typedef enum
00096 {
00097   HAL_CRYP_SUSPEND_NONE            = 0x00U,    /*!< CRYP processing suspension not requested */
00098   HAL_CRYP_SUSPEND                 = 0x01U     /*!< CRYP processing suspension requested     */
00099 }HAL_SuspendTypeDef;
00100 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00101
00102 /**
00103   * @brief  CRYP handle Structure definition
00104   */
00105 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00106 typedef struct __CRYP_HandleTypeDef
00107 #else
00108 typedef struct
00109 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00110 {
00111   AES_TypeDef                       *Instance;        /*!< AES Register base address */
00112
00113   CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
00114
00115   FunctionalState                   AutoKeyDerivation;   /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
00116                                                          This parameter can be a value of ENABLE/DISABLE */
00117
00118   uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00119
00120   uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00121
00122   __IO uint16_t                     CrypHeaderCount;  /*!< Counter of header data in words */
00123
00124   __IO uint16_t                     CrypInCount;      /*!< Counter of input data in words */
00125
00126   __IO uint16_t                     CrypOutCount;     /*!< Counter of output data in words */
00127
00128   uint16_t                          Size;             /*!< Length of input data */
00129
00130   uint32_t                          Phase;            /*!< CRYP peripheral phase */
00131
00132   DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
00133
00134   DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
00135
00136   HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
00137
00138   __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
00139
00140   __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
00141
00142   uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when
00143                                                            configuration can be skipped */
00144
00145   uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored
00146                                                            for a single signature computation after several
00147                                                            messages processing */
00148
00149 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00150   void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
00151   void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
00152   void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp);       /*!< CRYP Error callback */
00153
00154   void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp);    /*!< CRYP Msp Init callback  */
00155   void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp);  /*!< CRYP Msp DeInit callback  */
00156
00157 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00158
00159 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00160
00161   __IO HAL_SuspendTypeDef     SuspendRequest;          /*!< CRYP peripheral suspension request flag */
00162
00163   CRYP_ConfigTypeDef          Init_saved;              /*!< copy of CRYP required parameters when processing is suspended */
00164
00165   uint32_t                    *pCrypInBuffPtr_saved;   /*!< copy of CRYP input pointer when processing is suspended */
00166
00167   uint32_t                    *pCrypOutBuffPtr_saved;  /*!< copy of CRYP output pointer when processing is suspended */
00168
00169   uint32_t                    CrypInCount_saved;       /*!< copy of CRYP input data counter when processing is suspended */
00170
00171   uint32_t                    CrypOutCount_saved;      /*!< copy of CRYP output data counter when processing is suspended */
00172
00173   uint32_t                    Phase_saved;             /*!< copy of CRYP authentication phase when processing is suspended */
00174
00175   __IO HAL_CRYP_STATETypeDef  State_saved;             /*!< copy of CRYP peripheral state when processing is suspended */
00176
00177   uint32_t                    IV_saved[4];             /*!< copy of Initialisation Vector registers */
00178
00179   uint32_t                    SUSPxR_saved[8];         /*!< copy of suspension registers */
00180
00181   uint32_t                    CR_saved;                /*!< copy of CRYP control register  when processing is suspended*/
00182
00183   uint32_t                    Key_saved[8];            /*!< copy of key registers */
00184
00185   uint16_t                    Size_saved;              /*!< copy of input buffer size */
00186
00187   uint16_t                    CrypHeaderCount_saved;   /*!< copy of CRYP header data counter when processing is suspended */
00188
00189   uint32_t                    SizesSum_saved;          /*!< copy of SizesSum when processing is suspended */
00190
00191   uint32_t                    ResumingFlag;            /*!< resumption flag to bypass steps already carried out */
00192
00193   FunctionalState             AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
00194
00195 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00196
00197 } CRYP_HandleTypeDef;
00198
00199 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00200 /** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
00201   * @brief  HAL CRYP Callback ID enumeration definition
00202   * @{
00203   */
00204 typedef enum
00205 {
00206   HAL_CRYP_MSPINIT_CB_ID           = 0x00U,    /*!< CRYP MspInit callback ID                        */
00207   HAL_CRYP_MSPDEINIT_CB_ID         = 0x01U,     /*!< CRYP MspDeInit callback ID                      */
00208   HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x02U,    /*!< CRYP Input FIFO transfer completed callback ID  */
00209   HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x03U,    /*!< CRYP Output FIFO transfer completed callback ID */
00210   HAL_CRYP_ERROR_CB_ID             = 0x04U,    /*!< CRYP Error callback ID                          */
00211 } HAL_CRYP_CallbackIDTypeDef;
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
00217   * @brief  HAL CRYP Callback pointer definition
00218   * @{
00219   */
00220
00221 typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< pointer to a common CRYP callback function */
00222
00223 /**
00224   * @}
00225   */
00226
00227 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /* Exported constants --------------------------------------------------------*/
00234 /** @defgroup CRYP_Exported_Constants CRYP Exported Constants
00235   * @{
00236   */
00237
00238 /** @defgroup CRYP_Error_Definition   CRYP Error Definition
00239   * @{
00240   */
00241 #define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
00242 #define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
00243 #define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
00244 #define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
00245 #define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
00246 #define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
00247 #define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
00248 #define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
00249 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00250 #define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
00251 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00252
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
00258   * @{
00259   */
00260
00261 #define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
00262 #define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is byte */
00263
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
00269   * @{
00270   */
00271
00272 #define CRYP_HEADERWIDTHUNIT_WORD   0x00000000U  /*!< By default, header size unit is word */
00273 #define CRYP_HEADERWIDTHUNIT_BYTE   0x00000001U  /*!< By default, header size unit is byte */
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
00280   * @{
00281   */
00282
00283 #define CRYP_AES_ECB            0x00000000U                       /*!< Electronic codebook chaining algorithm                   */
00284 #define CRYP_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
00285 #define CRYP_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
00286 #define CRYP_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
00287 #define CRYP_AES_CCM            AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode                                 */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup CRYP_Key_Size CRYP Key Size
00294   * @{
00295   */
00296
00297 #define CRYP_KEYSIZE_128B         0x00000000U          /*!< 128-bit long key */
00298 #define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE       /*!< 256-bit long key */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup CRYP_Data_Type CRYP Data Type
00305   * @{
00306   */
00307
00308 #define CRYP_DATATYPE_32B         0x00000000U  /*!< 32-bit data type (no swapping)        */
00309 #define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
00310 #define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
00311 #define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup CRYP_Interrupt  CRYP Interrupt
00318   * @{
00319   */
00320
00321 #define CRYP_IT_CCFIE     AES_CR_CCFIE /*!< Computation Complete interrupt enable */
00322 #define CRYP_IT_ERRIE     AES_CR_ERRIE /*!< Error interrupt enable                */
00323 #define CRYP_IT_WRERR     AES_SR_WRERR  /*!< Write Error           */
00324 #define CRYP_IT_RDERR     AES_SR_RDERR  /*!< Read Error            */
00325 #define CRYP_IT_CCF       AES_SR_CCF    /*!< Computation completed */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup CRYP_Flags CRYP Flags
00332   * @{
00333   */
00334
00335 /* status flags */
00336 #define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
00337 #define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
00338 #define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
00339 #define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
00340 /* clearing flags */
00341 #define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
00342 #define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear  */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
00349   * @{
00350   */
00351
00352 #define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration to do systematically */
00353 #define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration to do only once      */
00354
00355 /**
00356   * @}
00357   */
00358
00359
00360 /**
00361   * @}
00362   */
00363
00364 /* Exported macros -----------------------------------------------------------*/
00365 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
00366   * @{
00367   */
00368
00369 /** @brief Reset CRYP handle state
00370   * @param  __HANDLE__ specifies the CRYP handle.
00371   * @retval None
00372   */
00373 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00374 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
00375                                                       (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
00376                                                       (__HANDLE__)->MspInitCallback = NULL;\
00377                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00378                                                      }while(0U)
00379 #else
00380 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
00381 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00382
00383 /**
00384   * @brief  Enable/Disable the CRYP peripheral.
00385   * @param  __HANDLE__ specifies the CRYP handle.
00386   * @retval None
00387   */
00388
00389 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  AES_CR_EN)
00390 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~AES_CR_EN)
00391
00392
00393 /** @brief  Check whether the specified CRYP status flag is set or not.
00394   * @param  __HANDLE__ specifies the CRYP handle.
00395   * @param  __FLAG__ specifies the flag to check.
00396   *         This parameter can be one of the following values for TinyAES:
00397   *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
00398   *            @arg @ref CRYP_IT_WRERR Write Error
00399   *            @arg @ref CRYP_IT_RDERR Read Error
00400   *            @arg @ref CRYP_IT_CCF Computation Complete
00401   *         This parameter can be one of the following values for CRYP:
00402   *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
00403   *                                 or a key preparation (for AES decryption).
00404   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
00405   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
00406   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
00407   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
00408   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
00409   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
00410  * @retval The state of __FLAG__ (TRUE or FALSE).
00411   */
00412
00413 #define CRYP_FLAG_MASK  0x0000001FU
00414 #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00415
00416 /** @brief  Clear the CRYP pending status flag.
00417   * @param  __HANDLE__ specifies the CRYP handle.
00418   * @param  __FLAG__ specifies the flag to clear.
00419   *         This parameter can be one of the following values:
00420   *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
00421   *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
00422   * @retval None
00423   */
00424
00425 #define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
00426
00427
00428 /** @brief  Check whether the specified CRYP interrupt source is enabled or not.
00429   * @param  __HANDLE__ specifies the CRYP handle.
00430   * @param __INTERRUPT__ CRYP interrupt source to check
00431   *         This parameter can be one of the following values for TinyAES:
00432   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00433   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00434   * @retval State of interruption (TRUE or FALSE).
00435   */
00436
00437 #define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00438
00439 /** @brief  Check whether the specified CRYP interrupt is set or not.
00440   * @param  __HANDLE__ specifies the CRYP handle.
00441   * @param  __INTERRUPT__ specifies the interrupt to check.
00442   *         This parameter can be one of the following values for TinyAES:
00443   *            @arg @ref CRYP_IT_WRERR Write Error
00444   *            @arg @ref CRYP_IT_RDERR Read Error
00445   *            @arg @ref CRYP_IT_CCF  Computation Complete
00446   *         This parameter can be one of the following values for CRYP:
00447   *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
00448   *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
00449   * @retval The state of __INTERRUPT__ (TRUE or FALSE).
00450   */
00451
00452 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00453
00454 /**
00455   * @brief  Enable the CRYP interrupt.
00456   * @param  __HANDLE__ specifies the CRYP handle.
00457   * @param  __INTERRUPT__ CRYP Interrupt.
00458   *         This parameter can be one of the following values for TinyAES:
00459   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00460   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00461   *         This parameter can be one of the following values for CRYP:
00462   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00463   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00464   * @retval None
00465   */
00466
00467 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00468
00469 /**
00470   * @brief  Disable the CRYP interrupt.
00471   * @param  __HANDLE__ specifies the CRYP handle.
00472   * @param  __INTERRUPT__ CRYP Interrupt.
00473   *         This parameter can be one of the following values for TinyAES:
00474   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00475   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00476   *         This parameter can be one of the following values for CRYP:
00477   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00478   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00479   * @retval None
00480   */
00481
00482 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00483
00484 /**
00485   * @}
00486   */
00487
00488 /* Include CRYP HAL Extended module */
00489 #include "stm32g0xx_hal_cryp_ex.h"
00490
00491 /* Exported functions --------------------------------------------------------*/
00492 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00493   * @{
00494   */
00495
00496 /** @addtogroup CRYP_Exported_Functions_Group1
00497   * @{
00498   */
00499 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
00500 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
00501 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
00502 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
00503 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
00504 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
00505 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00506 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
00507 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
00508 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00509 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00510 void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
00511 HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
00512 HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
00513 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
00514 /**
00515   * @}
00516   */
00517
00518 /** @addtogroup CRYP_Exported_Functions_Group2
00519   * @{
00520   */
00521
00522 /* encryption/decryption ***********************************/
00523 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
00524 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
00525 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00526 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00527 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00528 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00529
00530 /**
00531   * @}
00532   */
00533
00534
00535 /** @addtogroup CRYP_Exported_Functions_Group3
00536   * @{
00537   */
00538 /* Interrupt Handler functions  **********************************************/
00539 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
00540 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
00541 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
00542 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
00543 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
00544 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
00545
00546 /**
00547   * @}
00548   */
00549
00550 /**
00551   * @}
00552   */
00553
00554 /* Private macros --------------------------------------------------------*/
00555 /** @defgroup CRYP_Private_Macros CRYP Private Macros
00556   * @{
00557   */
00558
00559 /** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
00560   * @{
00561   */
00562
00563 #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB)      || \
00564                                       ((ALGORITHM)  == CRYP_AES_CBC)     || \
00565                                       ((ALGORITHM)  == CRYP_AES_CTR)     || \
00566                                       ((ALGORITHM)  == CRYP_AES_GCM_GMAC)|| \
00567                                       ((ALGORITHM)  == CRYP_AES_CCM))
00568
00569
00570 #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
00571                                  ((KEYSIZE) == CRYP_KEYSIZE_256B))
00572
00573 #define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
00574                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
00575                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
00576                                    ((DATATYPE) == CRYP_DATATYPE_1B))
00577
00578 #define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
00579                              ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
00580
00581 #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)                                             \
00582        (((((ALGO) == CRYP_AES_CTR)) &&                                             \
00583             ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U))           || \
00584              (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U))))        || \
00585          (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC)                  || \
00586           ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
00587
00588 /**
00589   * @}
00590   */
00591
00592 /**
00593   * @}
00594   */
00595
00596
00597 /* Private constants ---------------------------------------------------------*/
00598 /** @defgroup CRYP_Private_Constants CRYP Private Constants
00599   * @{
00600   */
00601
00602 /**
00603   * @}
00604   */
00605 /* Private defines -----------------------------------------------------------*/
00606 /** @defgroup CRYP_Private_Defines CRYP Private Defines
00607   * @{
00608   */
00609
00610 /**
00611   * @}
00612   */
00613
00614 /* Private variables ---------------------------------------------------------*/
00615 /** @defgroup CRYP_Private_Variables CRYP Private Variables
00616   * @{
00617   */
00618
00619 /**
00620   * @}
00621   */
00622
00623 /* Private functions ---------------------------------------------------------*/
00624 /** @defgroup CRYP_Private_Functions CRYP Private Functions
00625   * @{
00626   */
00627
00628 /**
00629   * @}
00630   */
00631
00632 /**
00633   * @}
00634   */
00635
00636 #endif /* AES */
00637 /**
00638   * @}
00639   */
00640
00641 #ifdef __cplusplus
00642 }
00643 #endif
00644
00645 #endif /* STM32G0xx_HAL_CRYP_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cryp_ex.c Source File

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stm32g0xx_hal_cryp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_cryp_ex.c
00004   * @author  MCD Application Team
00005   * @brief   CRYPEx HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the Cryptography (CRYP) peripheral.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * Copyright (c) 2018 STMicroelectronics.
00013   * All rights reserved.
00014   *
00015   * This software is licensed under terms that can be found in the LICENSE file
00016   * in the root directory of this software component.
00017   * If no LICENSE file comes with this software, it is provided AS-IS.
00018   *
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32g0xx_hal.h"
00024
00025 /** @addtogroup STM32G0xx_HAL_Driver
00026   * @{
00027   */
00028
00029 /** @addtogroup CRYPEx
00030   * @{
00031   */
00032
00033 #if defined(AES)
00034
00035 #ifdef HAL_CRYP_MODULE_ENABLED
00036
00037 /* Private typedef -----------------------------------------------------------*/
00038 /* Private define ------------------------------------------------------------*/
00039 /** @addtogroup CRYPEx_Private_Defines
00040   * @{
00041   */
00042
00043 #define CRYP_PHASE_INIT                              0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
00044 #define CRYP_PHASE_HEADER                            AES_CR_GCMPH_0          /*!< GCM/GMAC or CCM header phase */
00045 #define CRYP_PHASE_PAYLOAD                           AES_CR_GCMPH_1          /*!< GCM(/CCM) payload phase   */
00046 #define CRYP_PHASE_FINAL                             AES_CR_GCMPH            /*!< GCM/GMAC or CCM  final phase  */
00047
00048 #define CRYP_OPERATINGMODE_ENCRYPT                   0x00000000U             /*!< Encryption mode   */
00049 #define CRYP_OPERATINGMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode  only used when performing ECB and CBC decryptions  */
00050 #define CRYP_OPERATINGMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption       */
00051 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption only used when performing ECB and CBC decryptions  */
00052
00053 #define  CRYPEx_PHASE_PROCESS       0x02U     /*!< CRYP peripheral is in processing phase */
00054 #define  CRYPEx_PHASE_FINAL         0x03U     /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
00055
00056 /*  CTR0 information to use in CCM algorithm */
00057 #define CRYP_CCM_CTR0_0            0x07FFFFFFU
00058 #define CRYP_CCM_CTR0_3            0xFFFFFF00U
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Private macro -------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Private function prototypes -----------------------------------------------*/
00067
00068 /* Exported functions---------------------------------------------------------*/
00069 /** @addtogroup CRYPEx_Exported_Functions
00070   * @{
00071   */
00072
00073 /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
00074  *  @brief   Extended processing functions.
00075  *
00076 @verbatim
00077   ==============================================================================
00078               ##### Extended AES processing functions #####
00079   ==============================================================================
00080     [..]  This section provides functions allowing to generate the authentication
00081           TAG in Polling mode
00082       (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
00083       (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
00084          they should be used after Encrypt/Decrypt operation.
00085
00086 @endverbatim
00087   * @{
00088   */
00089
00090 /**
00091   * @brief  generate the GCM authentication TAG.
00092   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00093   *         the configuration information for CRYP module
00094   * @param  AuthTag Pointer to the authentication buffer
00095   * @param  Timeout Timeout duration
00096   * @retval HAL status
00097   */
00098 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00099 {
00100   uint32_t tickstart;
00101   /* Assume first Init.HeaderSize is in words */
00102   uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
00103   uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
00104   uint32_t tagaddr = (uint32_t)AuthTag;
00105
00106   /* Correct headerlength if Init.HeaderSize is actually in bytes */
00107   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
00108   {
00109     headerlength /= 4U;
00110   }
00111
00112   if (hcryp->State == HAL_CRYP_STATE_READY)
00113   {
00114     /* Process locked */
00115     __HAL_LOCK(hcryp);
00116
00117     /* Change the CRYP peripheral state */
00118     hcryp->State = HAL_CRYP_STATE_BUSY;
00119
00120     /* Check if initialization phase has already been performed */
00121     if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
00122     {
00123       /* Change the CRYP phase */
00124       hcryp->Phase = CRYPEx_PHASE_FINAL;
00125     }
00126     else /* Initialization phase has not been performed*/
00127     {
00128       /* Disable the Peripheral */
00129       __HAL_CRYP_DISABLE(hcryp);
00130
00131       /* Sequence error code field */
00132       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00133
00134       /* Change the CRYP peripheral state */
00135       hcryp->State = HAL_CRYP_STATE_READY;
00136
00137       /* Process unlocked */
00138       __HAL_UNLOCK(hcryp);
00139       return HAL_ERROR;
00140     }
00141
00142     /* Select final phase */
00143     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
00144
00145     /* Set the encrypt operating mode*/
00146     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
00147
00148     /*TinyAES peripheral from V3.1.1 : data has to be inserted normally (no swapping)*/
00149     /* Write into the AES_DINR register the number of bits in header (64 bits)
00150     followed by the number of bits in the payload */
00151
00152     hcryp->Instance->DINR = 0U;
00153     hcryp->Instance->DINR = (uint32_t)(headerlength);
00154     hcryp->Instance->DINR = 0U;
00155     hcryp->Instance->DINR = (uint32_t)(inputlength);
00156
00157     /* Wait for CCF flag to be raised */
00158     tickstart = HAL_GetTick();
00159     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
00160     {
00161       /* Check for the Timeout */
00162       if (Timeout != HAL_MAX_DELAY)
00163       {
00164         if (((HAL_GetTick() - tickstart) > Timeout)||(Timeout == 0U))
00165         {
00166           /* Disable the CRYP peripheral clock */
00167           __HAL_CRYP_DISABLE(hcryp);
00168
00169           /* Change state */
00170           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00171           hcryp->State = HAL_CRYP_STATE_READY;
00172
00173           /* Process unlocked */
00174           __HAL_UNLOCK(hcryp);
00175           return HAL_ERROR;
00176         }
00177       }
00178     }
00179
00180     /* Read the authentication TAG in the output FIFO */
00181     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00182     tagaddr += 4U;
00183     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00184     tagaddr += 4U;
00185     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00186     tagaddr += 4U;
00187     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00188
00189     /* Clear CCF flag */
00190     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
00191
00192     /* Disable the peripheral */
00193     __HAL_CRYP_DISABLE(hcryp);
00194
00195     /* Change the CRYP peripheral state */
00196     hcryp->State = HAL_CRYP_STATE_READY;
00197
00198     /* Process unlocked */
00199     __HAL_UNLOCK(hcryp);
00200   }
00201   else
00202   {
00203     /* Busy error code field */
00204     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00205     return HAL_ERROR;
00206   }
00207   /* Return function status */
00208   return HAL_OK;
00209 }
00210
00211 /**
00212   * @brief  AES CCM Authentication TAG generation.
00213   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00214   *         the configuration information for CRYP module
00215   * @param  AuthTag Pointer to the authentication buffer
00216   * @param  Timeout Timeout duration
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00220 {
00221   uint32_t tagaddr = (uint32_t)AuthTag;
00222   uint32_t tickstart;
00223
00224   if (hcryp->State == HAL_CRYP_STATE_READY)
00225   {
00226     /* Process locked */
00227     __HAL_LOCK(hcryp);
00228
00229     /* Disable interrupts in case they were kept enabled to proceed
00230        a single message in several iterations */
00231     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
00232
00233     /* Change the CRYP peripheral state */
00234     hcryp->State = HAL_CRYP_STATE_BUSY;
00235
00236     /* Check if initialization phase has already been performed */
00237     if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
00238     {
00239       /* Change the CRYP phase */
00240       hcryp->Phase = CRYPEx_PHASE_FINAL;
00241     }
00242     else /* Initialization phase has not been performed*/
00243     {
00244       /* Disable the peripheral */
00245       __HAL_CRYP_DISABLE(hcryp);
00246
00247       /* Sequence error code field */
00248       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00249
00250       /* Change the CRYP peripheral state */
00251       hcryp->State = HAL_CRYP_STATE_READY;
00252
00253       /* Process unlocked */
00254       __HAL_UNLOCK(hcryp);
00255       return HAL_ERROR;
00256     }
00257     /* Select final phase */
00258     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
00259
00260     /* Set encrypt  operating mode*/
00261     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
00262
00263     /* Wait for CCF flag to be raised */
00264     tickstart = HAL_GetTick();
00265     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
00266     {
00267       /* Check for the Timeout */
00268       if (Timeout != HAL_MAX_DELAY)
00269       {
00270         if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U))
00271         {
00272           /* Disable the CRYP peripheral Clock */
00273           __HAL_CRYP_DISABLE(hcryp);
00274
00275           /* Change state */
00276           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00277           hcryp->State = HAL_CRYP_STATE_READY;
00278
00279           /* Process unlocked */
00280           __HAL_UNLOCK(hcryp);
00281           return HAL_ERROR;
00282         }
00283       }
00284     }
00285
00286     /* Read the authentication TAG in the output FIFO */
00287     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00288     tagaddr += 4U;
00289     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00290     tagaddr += 4U;
00291     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00292     tagaddr += 4U;
00293     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00294
00295     /* Clear CCF Flag */
00296     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
00297
00298
00299     /* Change the CRYP peripheral state */
00300     hcryp->State = HAL_CRYP_STATE_READY;
00301
00302     /* Process unlocked */
00303     __HAL_UNLOCK(hcryp);
00304
00305     /* Disable CRYP  */
00306     __HAL_CRYP_DISABLE(hcryp);
00307   }
00308   else
00309   {
00310     /* Busy error code field */
00311     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00312     return HAL_ERROR;
00313   }
00314   /* Return function status */
00315   return HAL_OK;
00316 }
00317
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup CRYPEx_Exported_Functions_Group2 Extended AES Key Derivations functions
00323   * @brief   Extended Key Derivations functions.
00324   *
00325 @verbatim
00326   ==============================================================================
00327               ##### Key Derivation functions #####
00328   ==============================================================================
00329     [..]  This section provides functions allowing to Enable or Disable the
00330           the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
00331           These function are allowed only in TinyAES peripheral.
00332 @endverbatim
00333   * @{
00334   */
00335
00336 /**
00337   * @brief  AES enable key derivation functions
00338   * @param  hcryp pointer to a CRYP_HandleTypeDef structure.
00339   */
00340 void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
00341 {
00342   if (hcryp->State == HAL_CRYP_STATE_READY)
00343   {
00344     hcryp->AutoKeyDerivation = ENABLE;
00345   }
00346   else
00347   {
00348     /* Busy error code field */
00349     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00350   }
00351 }
00352 /**
00353   * @brief  AES disable key derivation functions
00354   * @param  hcryp pointer to a CRYP_HandleTypeDef structure.
00355   */
00356 void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
00357 {
00358   if (hcryp->State == HAL_CRYP_STATE_READY)
00359   {
00360     hcryp->AutoKeyDerivation = DISABLE;
00361   }
00362   else
00363   {
00364     /* Busy error code field */
00365     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00366   }
00367 }
00368
00369 /**
00370   * @}
00371   */
00372
00373 /**
00374   * @}
00375   */
00376
00377 #endif /* HAL_CRYP_MODULE_ENABLED */
00378
00379 #endif /* AES */
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_cryp_ex.h Source File

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stm32g0xx_hal_cryp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_cryp_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRYPEx HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_CRYP_EX_H
00021 #define STM32G0xx_HAL_CRYP_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 #if defined(AES)
00035
00036 /** @defgroup CRYPEx CRYPEx
00037   * @brief CRYP Extension HAL module driver.
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /* Exported constants --------------------------------------------------------*/
00043 /* Private types -------------------------------------------------------------*/
00044 /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
00045   * @{
00046   */
00047
00048 /**
00049   * @}
00050   */
00051
00052 /* Private variables ---------------------------------------------------------*/
00053 /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
00054   * @{
00055   */
00056
00057 /**
00058   * @}
00059   */
00060
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
00063   * @{
00064   */
00065
00066 /**
00067   * @}
00068   */
00069
00070 /* Private macros ------------------------------------------------------------*/
00071 /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
00072   * @{
00073   */
00074
00075 /**
00076  * @}
00077  */
00078
00079 /* Private functions ---------------------------------------------------------*/
00080 /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
00081   * @{
00082   */
00083
00084 /**
00085   * @}
00086   */
00087
00088 /* Exported functions --------------------------------------------------------*/
00089 /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
00090   * @{
00091   */
00092
00093 /** @addtogroup CRYPEx_Exported_Functions_Group1
00094   * @{
00095   */
00096 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00097 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @addtogroup CRYPEx_Exported_Functions_Group2
00104   * @{
00105   */
00106 void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
00107 void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
00108
00109 /**
00110   * @}
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 /**
00118   * @}
00119   */
00120 #endif /* AES */
00121
00122 /**
00123   * @}
00124   */
00125
00126 #ifdef __cplusplus
00127 }
00128 #endif
00129
00130 #endif /* STM32G0xx_HAL_CRYP_EX_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dac.c Source File

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stm32g0xx_hal_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @brief   DAC HAL module driver.
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2018 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                       ##### DAC Peripheral features #####
00028   ==============================================================================
00029     [..]
00030       *** DAC Channels ***
00031       ====================
00032     [..]
00033     STM32G0 devices integrate two 12-bit Digital Analog Converters
00034
00035     The 2 converters (i.e. channel1 & channel2)
00036     can be used independently or simultaneously (dual mode):
00037       (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
00038           peripherals (ex. timers).
00039       (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
00040           peripherals (ex. timers).
00041
00042       *** DAC Triggers ***
00043       ====================
00044     [..]
00045     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00046     and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
00047     [..]
00048     Digital to Analog conversion can be triggered by:
00049       (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
00050           The used pin (GPIOx_PIN_9) must be configured in input mode.
00051
00052       (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7
00053           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
00054
00055       (#) Software using DAC_TRIGGER_SOFTWARE
00056
00057       *** DAC Buffer mode feature ***
00058       ===============================
00059       [..]
00060       Each DAC channel integrates an output buffer that can be used to
00061       reduce the output impedance, and to drive external loads directly
00062       without having to add an external operational amplifier.
00063       To enable, the output buffer use
00064       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00065       [..]
00066       (@) Refer to the device datasheet for more details about output
00067           impedance value with and without output buffer.
00068
00069       *** GPIO configurations guidelines ***
00070       =====================
00071       [..]
00072       When a DAC channel is used (ex channel1 on PA4) and the other is not
00073       (ex channel2 on PA5 is configured in Analog and disabled).
00074       Channel1 may disturb channel2 as coupling effect.
00075       Note that there is no coupling on channel2 as soon as channel2 is turned on.
00076       Coupling on adjacent channel could be avoided as follows:
00077       when unused PA5 is configured as INPUT PULL-UP or DOWN.
00078       PA5 is configured in ANALOG just before it is turned on.
00079
00080       *** DAC Sample and Hold feature ***
00081       ========================
00082       [..]
00083       For each converter, 2 modes are supported: normal mode and
00084       "sample and hold" mode (i.e. low power mode).
00085       In the sample and hold mode, the DAC core converts data, then holds the
00086       converted voltage on a capacitor. When not converting, the DAC cores and
00087       buffer are completely turned off between samples and the DAC output is
00088       tri-stated, therefore  reducing the overall power consumption. A new
00089       stabilization period is needed before each new conversion.
00090
00091       The sample and hold allow setting internal or external voltage @
00092       low power consumption cost (output value can be at any given rate either
00093       by CPU or DMA).
00094
00095       The Sample and hold block and registers uses either LSI & run in
00096       several power modes: run mode, sleep mode, low power run, low power sleep
00097       mode & stop1 mode.
00098
00099       Low power stop1 mode allows only static conversion.
00100
00101       To enable Sample and Hold mode
00102       Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
00103       RCC_LSI_ON parameters.
00104
00105       Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
00106          & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
00107            DAC_HoldTime & DAC_RefreshTime;
00108
00109        *** DAC calibration feature ***
00110        ===================================
00111       [..]
00112        (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
00113        (++) Calibration aims at correcting some offset of output buffer.
00114        (++) The DAC uses either factory calibration settings OR user defined
00115            calibration (trimming) settings (i.e. trimming mode).
00116        (++) The user defined settings can be figured out using self calibration
00117            handled by HAL_DACEx_SelfCalibrate.
00118        (++) HAL_DACEx_SelfCalibrate:
00119        (+++) Runs automatically the calibration.
00120        (+++) Enables the user trimming mode
00121        (+++) Updates a structure with trimming values with fresh calibration
00122             results.
00123             The user may store the calibration results for larger
00124             (ex monitoring the trimming as a function of temperature
00125             for instance)
00126
00127        *** DAC wave generation feature ***
00128        ===================================
00129        [..]
00130        Both DAC channels can be used to generate
00131          (#) Noise wave
00132          (#) Triangle wave
00133
00134        *** DAC data format ***
00135        =======================
00136        [..]
00137        The DAC data format can be:
00138          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00139          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00140          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00141
00142        *** DAC data value to voltage correspondence ***
00143        ================================================
00144        [..]
00145        The analog output voltage on each DAC channel pin is determined
00146        by the following equation:
00147        [..]
00148        DAC_OUTx = VREF+ * DOR / 4095
00149        (+) with  DOR is the Data Output Register
00150        [..]
00151           VREF+ is the input voltage reference (refer to the device datasheet)
00152        [..]
00153         e.g. To set DAC_OUT1 to 0.7V, use
00154        (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
00155
00156        *** DMA requests ***
00157        =====================
00158        [..]
00159        A DMA request can be generated when an external trigger (but not a software trigger)
00160        occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
00161        DMA requests are mapped as following:
00162       (#) DAC channel1: mapped on DMA request 8 (can be any DMA channel)
00163       (#) DAC channel2: mapped on DMA request 9 (can be any DMA channel)
00164
00165      [..]
00166     (@) For Dual mode and specific signal (Triangle and noise) generation please
00167         refer to Extended Features Driver description
00168
00169                       ##### How to use this driver #####
00170   ==============================================================================
00171     [..]
00172       (+) DAC APB clock must be enabled to get write access to DAC
00173           registers using HAL_DAC_Init()
00174       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00175       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00176       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
00177
00178      *** Calibration mode IO operation ***
00179      ======================================
00180      [..]
00181        (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
00182        (+) Run the calibration using HAL_DACEx_SelfCalibrate()
00183        (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
00184
00185      *** Polling mode IO operation ***
00186      =================================
00187      [..]
00188        (+) Start the DAC peripheral using HAL_DAC_Start()
00189        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00190        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00191
00192      *** DMA mode IO operation ***
00193      ==============================
00194      [..]
00195        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00196            of data to be transferred at each end of conversion
00197            First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
00198        (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00199            function is executed and user can add his own code by customization of function pointer
00200            HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00201        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00202            function is executed and user can add his own code by customization of function pointer
00203            HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00204        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
00205             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
00206        (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
00207            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
00208            function is executed and user can add his own code by customization of function pointer
00209            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
00210            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
00211        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00212
00213     *** Callback registration ***
00214     =============================================
00215     [..]
00216       The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
00217       allows the user to configure dynamically the driver callbacks.
00218
00219     Use Functions HAL_DAC_RegisterCallback() to register a user callback,
00220       it allows to register following callbacks:
00221       (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
00222       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
00223       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
00224       (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
00225       (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
00226       (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
00227       (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
00228       (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
00229       (+) MspInitCallback         : DAC MspInit.
00230       (+) MspDeInitCallback       : DAC MspdeInit.
00231       This function takes as parameters the HAL peripheral handle, the Callback ID
00232       and a pointer to the user callback function.
00233
00234     Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
00235       weak (surcharged) function. It allows to reset following callbacks:
00236       (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
00237       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
00238       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
00239       (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
00240       (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
00241       (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
00242       (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
00243       (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
00244       (+) MspInitCallback         : DAC MspInit.
00245       (+) MspDeInitCallback       : DAC MspdeInit.
00246       (+) All Callbacks
00247       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00248
00249       By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
00250       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00251       Exception done for MspInit and MspDeInit callbacks that are respectively
00252       reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
00253       and  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
00254       If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
00255       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00256
00257       Callbacks can be registered/unregistered in READY state only.
00258       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00259       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00260       during the Init/DeInit.
00261       In that case first register the MspInit/MspDeInit user callbacks
00262       using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
00263       or HAL_DAC_Init function.
00264
00265       When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
00266       not defined, the callback registering feature is not available
00267       and weak (surcharged) callbacks are used.
00268
00269      *** DAC HAL driver macros list ***
00270      =============================================
00271      [..]
00272        Below the list of most used macros in DAC HAL driver.
00273
00274       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
00275       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
00276       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
00277       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
00278
00279      [..]
00280       (@) You can refer to the DAC HAL driver header file for more useful macros
00281
00282 @endverbatim
00283   ******************************************************************************
00284   */
00285
00286 /* Includes ------------------------------------------------------------------*/
00287 #include "stm32g0xx_hal.h"
00288
00289 /** @addtogroup STM32G0xx_HAL_Driver
00290   * @{
00291   */
00292
00293 #ifdef HAL_DAC_MODULE_ENABLED
00294 #if defined(DAC1)
00295
00296 /** @defgroup DAC DAC
00297   * @brief DAC driver modules
00298   * @{
00299   */
00300
00301 /* Private typedef -----------------------------------------------------------*/
00302 /* Private define ------------------------------------------------------------*/
00303 /* Private constants ---------------------------------------------------------*/
00304 /** @addtogroup DAC_Private_Constants DAC Private Constants
00305   * @{
00306   */
00307 #define TIMEOUT_DAC_CALIBCONFIG        1U         /* 1   ms        */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /* Private macro -------------------------------------------------------------*/
00314 /* Private variables ---------------------------------------------------------*/
00315 /* Private function prototypes -----------------------------------------------*/
00316 /* Exported functions -------------------------------------------------------*/
00317
00318 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00319   * @{
00320   */
00321
00322 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00323   *  @brief    Initialization and Configuration functions
00324   *
00325 @verbatim
00326   ==============================================================================
00327               ##### Initialization and de-initialization functions #####
00328   ==============================================================================
00329     [..]  This section provides functions allowing to:
00330       (+) Initialize and configure the DAC.
00331       (+) De-initialize the DAC.
00332
00333 @endverbatim
00334   * @{
00335   */
00336
00337 /**
00338   * @brief  Initialize the DAC peripheral according to the specified parameters
00339   *         in the DAC_InitStruct and initialize the associated handle.
00340   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00341   *         the configuration information for the specified DAC.
00342   * @retval HAL status
00343   */
00344 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
00345 {
00346   /* Check DAC handle */
00347   if (hdac == NULL)
00348   {
00349     return HAL_ERROR;
00350   }
00351   /* Check the parameters */
00352   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00353
00354   if (hdac->State == HAL_DAC_STATE_RESET)
00355   {
00356 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00357     /* Init the DAC Callback settings */
00358     hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;
00359     hdac->ConvHalfCpltCallbackCh1       = HAL_DAC_ConvHalfCpltCallbackCh1;
00360     hdac->ErrorCallbackCh1              = HAL_DAC_ErrorCallbackCh1;
00361     hdac->DMAUnderrunCallbackCh1        = HAL_DAC_DMAUnderrunCallbackCh1;
00362
00363     hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;
00364     hdac->ConvHalfCpltCallbackCh2       = HAL_DACEx_ConvHalfCpltCallbackCh2;
00365     hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;
00366     hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2;
00367
00368     if (hdac->MspInitCallback == NULL)
00369     {
00370       hdac->MspInitCallback             = HAL_DAC_MspInit;
00371     }
00372 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00373
00374     /* Allocate lock resource and initialize it */
00375     hdac->Lock = HAL_UNLOCKED;
00376
00377 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00378     /* Init the low level hardware */
00379     hdac->MspInitCallback(hdac);
00380 #else
00381     /* Init the low level hardware */
00382     HAL_DAC_MspInit(hdac);
00383 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00384   }
00385
00386   /* Initialize the DAC state*/
00387   hdac->State = HAL_DAC_STATE_BUSY;
00388
00389   /* Set DAC error code to none */
00390   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00391
00392   /* Initialize the DAC state*/
00393   hdac->State = HAL_DAC_STATE_READY;
00394
00395   /* Return function status */
00396   return HAL_OK;
00397 }
00398
00399 /**
00400   * @brief  Deinitialize the DAC peripheral registers to their default reset values.
00401   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00402   *         the configuration information for the specified DAC.
00403   * @retval HAL status
00404   */
00405 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
00406 {
00407   /* Check DAC handle */
00408   if (hdac == NULL)
00409   {
00410     return HAL_ERROR;
00411   }
00412
00413   /* Check the parameters */
00414   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00415
00416   /* Change DAC state */
00417   hdac->State = HAL_DAC_STATE_BUSY;
00418
00419 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00420   if (hdac->MspDeInitCallback == NULL)
00421   {
00422     hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
00423   }
00424   /* DeInit the low level hardware */
00425   hdac->MspDeInitCallback(hdac);
00426 #else
00427   /* DeInit the low level hardware */
00428   HAL_DAC_MspDeInit(hdac);
00429 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00430
00431   /* Set DAC error code to none */
00432   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00433
00434   /* Change DAC state */
00435   hdac->State = HAL_DAC_STATE_RESET;
00436
00437   /* Release Lock */
00438   __HAL_UNLOCK(hdac);
00439
00440   /* Return function status */
00441   return HAL_OK;
00442 }
00443
00444 /**
00445   * @brief  Initialize the DAC MSP.
00446   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00447   *         the configuration information for the specified DAC.
00448   * @retval None
00449   */
00450 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
00451 {
00452   /* Prevent unused argument(s) compilation warning */
00453   UNUSED(hdac);
00454
00455   /* NOTE : This function should not be modified, when the callback is needed,
00456             the HAL_DAC_MspInit could be implemented in the user file
00457    */
00458 }
00459
00460 /**
00461   * @brief  DeInitialize the DAC MSP.
00462   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00463   *         the configuration information for the specified DAC.
00464   * @retval None
00465   */
00466 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
00467 {
00468   /* Prevent unused argument(s) compilation warning */
00469   UNUSED(hdac);
00470
00471   /* NOTE : This function should not be modified, when the callback is needed,
00472             the HAL_DAC_MspDeInit could be implemented in the user file
00473    */
00474 }
00475
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
00481   *  @brief    IO operation functions
00482   *
00483 @verbatim
00484   ==============================================================================
00485              ##### IO operation functions #####
00486   ==============================================================================
00487     [..]  This section provides functions allowing to:
00488       (+) Start conversion.
00489       (+) Stop conversion.
00490       (+) Start conversion and enable DMA transfer.
00491       (+) Stop conversion and disable DMA transfer.
00492       (+) Get result of conversion.
00493
00494 @endverbatim
00495   * @{
00496   */
00497
00498 /**
00499   * @brief  Enables DAC and starts conversion of channel.
00500   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00501   *         the configuration information for the specified DAC.
00502   * @param  Channel The selected DAC channel.
00503   *          This parameter can be one of the following values:
00504   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00505   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00506   * @retval HAL status
00507   */
00508 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
00509 {
00510   /* Check the parameters */
00511   assert_param(IS_DAC_CHANNEL(Channel));
00512
00513   /* Process locked */
00514   __HAL_LOCK(hdac);
00515
00516   /* Change DAC state */
00517   hdac->State = HAL_DAC_STATE_BUSY;
00518
00519   /* Enable the Peripheral */
00520   __HAL_DAC_ENABLE(hdac, Channel);
00521
00522   if (Channel == DAC_CHANNEL_1)
00523   {
00524     /* Check if software trigger enabled */
00525     if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
00526     {
00527       /* Enable the selected DAC software conversion */
00528       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00529     }
00530   }
00531
00532   else
00533   {
00534     /* Check if software trigger enabled */
00535     if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
00536     {
00537       /* Enable the selected DAC software conversion*/
00538       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
00539     }
00540   }
00541
00542
00543   /* Change DAC state */
00544   hdac->State = HAL_DAC_STATE_READY;
00545
00546   /* Process unlocked */
00547   __HAL_UNLOCK(hdac);
00548
00549   /* Return function status */
00550   return HAL_OK;
00551 }
00552
00553 /**
00554   * @brief  Disables DAC and stop conversion of channel.
00555   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00556   *         the configuration information for the specified DAC.
00557   * @param  Channel The selected DAC channel.
00558   *          This parameter can be one of the following values:
00559   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00560   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00561   * @retval HAL status
00562   */
00563 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
00564 {
00565   /* Check the parameters */
00566   assert_param(IS_DAC_CHANNEL(Channel));
00567
00568   /* Disable the Peripheral */
00569   __HAL_DAC_DISABLE(hdac, Channel);
00570
00571   /* Change DAC state */
00572   hdac->State = HAL_DAC_STATE_READY;
00573
00574   /* Return function status */
00575   return HAL_OK;
00576 }
00577
00578 /**
00579   * @brief  Enables DAC and starts conversion of channel.
00580   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00581   *         the configuration information for the specified DAC.
00582   * @param  Channel The selected DAC channel.
00583   *          This parameter can be one of the following values:
00584   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00585   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00586   * @param  pData The source Buffer address.
00587   * @param  Length The length of data to be transferred from memory to DAC peripheral
00588   * @param  Alignment Specifies the data alignment for DAC channel.
00589   *          This parameter can be one of the following values:
00590   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00591   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00592   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00593   * @retval HAL status
00594   */
00595 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
00596                                     uint32_t Alignment)
00597 {
00598   HAL_StatusTypeDef status;
00599   uint32_t tmpreg = 0U;
00600
00601   /* Check the parameters */
00602   assert_param(IS_DAC_CHANNEL(Channel));
00603   assert_param(IS_DAC_ALIGN(Alignment));
00604
00605   /* Process locked */
00606   __HAL_LOCK(hdac);
00607
00608   /* Change DAC state */
00609   hdac->State = HAL_DAC_STATE_BUSY;
00610
00611   if (Channel == DAC_CHANNEL_1)
00612   {
00613     /* Set the DMA transfer complete callback for channel1 */
00614     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00615
00616     /* Set the DMA half transfer complete callback for channel1 */
00617     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00618
00619     /* Set the DMA error callback for channel1 */
00620     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00621
00622     /* Enable the selected DAC channel1 DMA request */
00623     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00624
00625     /* Case of use of channel 1 */
00626     switch (Alignment)
00627     {
00628       case DAC_ALIGN_12B_R:
00629         /* Get DHR12R1 address */
00630         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00631         break;
00632       case DAC_ALIGN_12B_L:
00633         /* Get DHR12L1 address */
00634         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00635         break;
00636       case DAC_ALIGN_8B_R:
00637         /* Get DHR8R1 address */
00638         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00639         break;
00640       default:
00641         break;
00642     }
00643   }
00644
00645   else
00646   {
00647     /* Set the DMA transfer complete callback for channel2 */
00648     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00649
00650     /* Set the DMA half transfer complete callback for channel2 */
00651     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00652
00653     /* Set the DMA error callback for channel2 */
00654     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00655
00656     /* Enable the selected DAC channel2 DMA request */
00657     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00658
00659     /* Case of use of channel 2 */
00660     switch (Alignment)
00661     {
00662       case DAC_ALIGN_12B_R:
00663         /* Get DHR12R2 address */
00664         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00665         break;
00666       case DAC_ALIGN_12B_L:
00667         /* Get DHR12L2 address */
00668         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00669         break;
00670       case DAC_ALIGN_8B_R:
00671         /* Get DHR8R2 address */
00672         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00673         break;
00674       default:
00675         break;
00676     }
00677   }
00678
00679
00680   /* Enable the DMA channel */
00681   if (Channel == DAC_CHANNEL_1)
00682   {
00683     /* Enable the DAC DMA underrun interrupt */
00684     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00685
00686     /* Enable the DMA channel */
00687     status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00688   }
00689
00690   else
00691   {
00692     /* Enable the DAC DMA underrun interrupt */
00693     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00694
00695     /* Enable the DMA channel */
00696     status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00697   }
00698
00699
00700   /* Process Unlocked */
00701   __HAL_UNLOCK(hdac);
00702
00703   if (status == HAL_OK)
00704   {
00705     /* Enable the Peripheral */
00706     __HAL_DAC_ENABLE(hdac, Channel);
00707   }
00708   else
00709   {
00710     hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00711   }
00712
00713   /* Return function status */
00714   return status;
00715 }
00716
00717 /**
00718   * @brief  Disables DAC and stop conversion of channel.
00719   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00720   *         the configuration information for the specified DAC.
00721   * @param  Channel The selected DAC channel.
00722   *          This parameter can be one of the following values:
00723   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00724   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00725   * @retval HAL status
00726   */
00727 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
00728 {
00729   /* Check the parameters */
00730   assert_param(IS_DAC_CHANNEL(Channel));
00731
00732   /* Disable the selected DAC channel DMA request */
00733   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
00734
00735   /* Disable the Peripheral */
00736   __HAL_DAC_DISABLE(hdac, Channel);
00737
00738   /* Disable the DMA channel */
00739
00740   /* Channel1 is used */
00741   if (Channel == DAC_CHANNEL_1)
00742   {
00743     /* Disable the DMA channel */
00744     (void)HAL_DMA_Abort(hdac->DMA_Handle1);
00745
00746     /* Disable the DAC DMA underrun interrupt */
00747     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00748   }
00749
00750   else /* Channel2 is used for */
00751   {
00752     /* Disable the DMA channel */
00753     (void)HAL_DMA_Abort(hdac->DMA_Handle2);
00754
00755     /* Disable the DAC DMA underrun interrupt */
00756     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00757   }
00758
00759
00760   /* Change DAC state */
00761   hdac->State = HAL_DAC_STATE_READY;
00762
00763   /* Return function status */
00764   return HAL_OK;
00765 }
00766
00767 /**
00768   * @brief  Handles DAC interrupt request
00769   *         This function uses the interruption of DMA
00770   *         underrun.
00771   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00772   *         the configuration information for the specified DAC.
00773   * @retval None
00774   */
00775 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
00776 {
00777   if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
00778   {
00779     /* Check underrun flag of DAC channel 1 */
00780     if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00781     {
00782       /* Change DAC state to error state */
00783       hdac->State = HAL_DAC_STATE_ERROR;
00784
00785       /* Set DAC error code to channel1 DMA underrun error */
00786       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
00787
00788       /* Clear the underrun flag */
00789       __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
00790
00791       /* Disable the selected DAC channel1 DMA request */
00792       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00793
00794       /* Error callback */
00795 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00796       hdac->DMAUnderrunCallbackCh1(hdac);
00797 #else
00798       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00799 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00800     }
00801   }
00802
00803
00804   if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
00805   {
00806     /* Check underrun flag of DAC channel 2 */
00807     if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
00808     {
00809       /* Change DAC state to error state */
00810       hdac->State = HAL_DAC_STATE_ERROR;
00811
00812       /* Set DAC error code to channel2 DMA underrun error */
00813       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
00814
00815       /* Clear the underrun flag */
00816       __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
00817
00818       /* Disable the selected DAC channel2 DMA request */
00819       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00820
00821       /* Error callback */
00822 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00823       hdac->DMAUnderrunCallbackCh2(hdac);
00824 #else
00825       HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00826 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00827     }
00828   }
00829
00830 }
00831
00832 /**
00833   * @brief  Set the specified data holding register value for DAC channel.
00834   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00835   *         the configuration information for the specified DAC.
00836   * @param  Channel The selected DAC channel.
00837   *          This parameter can be one of the following values:
00838   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00839   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00840   * @param  Alignment Specifies the data alignment.
00841   *          This parameter can be one of the following values:
00842   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00843   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00844   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00845   * @param  Data Data to be loaded in the selected data holding register.
00846   * @retval HAL status
00847   */
00848 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00849 {
00850   __IO uint32_t tmp = 0UL;
00851
00852   /* Check the parameters */
00853   assert_param(IS_DAC_CHANNEL(Channel));
00854   assert_param(IS_DAC_ALIGN(Alignment));
00855   assert_param(IS_DAC_DATA(Data));
00856
00857   tmp = (uint32_t)hdac->Instance;
00858   if (Channel == DAC_CHANNEL_1)
00859   {
00860     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00861   }
00862
00863   else
00864   {
00865     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00866   }
00867
00868
00869   /* Set the DAC channel selected data holding register */
00870   *(__IO uint32_t *) tmp = Data;
00871
00872   /* Return function status */
00873   return HAL_OK;
00874 }
00875
00876 /**
00877   * @brief  Conversion complete callback in non-blocking mode for Channel1
00878   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00879   *         the configuration information for the specified DAC.
00880   * @retval None
00881   */
00882 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
00883 {
00884   /* Prevent unused argument(s) compilation warning */
00885   UNUSED(hdac);
00886
00887   /* NOTE : This function should not be modified, when the callback is needed,
00888             the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
00889    */
00890 }
00891
00892 /**
00893   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
00894   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00895   *         the configuration information for the specified DAC.
00896   * @retval None
00897   */
00898 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
00899 {
00900   /* Prevent unused argument(s) compilation warning */
00901   UNUSED(hdac);
00902
00903   /* NOTE : This function should not be modified, when the callback is needed,
00904             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
00905    */
00906 }
00907
00908 /**
00909   * @brief  Error DAC callback for Channel1.
00910   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00911   *         the configuration information for the specified DAC.
00912   * @retval None
00913   */
00914 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
00915 {
00916   /* Prevent unused argument(s) compilation warning */
00917   UNUSED(hdac);
00918
00919   /* NOTE : This function should not be modified, when the callback is needed,
00920             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
00921    */
00922 }
00923
00924 /**
00925   * @brief  DMA underrun DAC callback for channel1.
00926   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00927   *         the configuration information for the specified DAC.
00928   * @retval None
00929   */
00930 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
00931 {
00932   /* Prevent unused argument(s) compilation warning */
00933   UNUSED(hdac);
00934
00935   /* NOTE : This function should not be modified, when the callback is needed,
00936             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
00937    */
00938 }
00939
00940 /**
00941   * @}
00942   */
00943
00944 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
00945   *  @brief    Peripheral Control functions
00946   *
00947 @verbatim
00948   ==============================================================================
00949              ##### Peripheral Control functions #####
00950   ==============================================================================
00951     [..]  This section provides functions allowing to:
00952       (+) Configure channels.
00953       (+) Set the specified data holding register value for DAC channel.
00954
00955 @endverbatim
00956   * @{
00957   */
00958
00959 /**
00960   * @brief  Returns the last data output value of the selected DAC channel.
00961   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00962   *         the configuration information for the specified DAC.
00963   * @param  Channel The selected DAC channel.
00964   *          This parameter can be one of the following values:
00965   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00966   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00967   * @retval The selected DAC channel data output value.
00968   */
00969 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
00970 {
00971   uint32_t result;
00972
00973   /* Check the parameters */
00974   assert_param(IS_DAC_CHANNEL(Channel));
00975
00976   if (Channel == DAC_CHANNEL_1)
00977   {
00978     result = hdac->Instance->DOR1;
00979   }
00980
00981   else
00982   {
00983     result = hdac->Instance->DOR2;
00984   }
00985
00986   /* Returns the DAC channel data output register value */
00987   return result;
00988 }
00989
00990 /**
00991   * @brief  Configures the selected DAC channel.
00992   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00993   *         the configuration information for the specified DAC.
00994   * @param  sConfig DAC configuration structure.
00995   * @param  Channel The selected DAC channel.
00996   *          This parameter can be one of the following values:
00997   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00998   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00999   * @retval HAL status
01000   */
01001 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
01002 {
01003   uint32_t tmpreg1;
01004   uint32_t tmpreg2;
01005   uint32_t tickstart;
01006
01007   /* Check the DAC parameters */
01008   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
01009   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
01010   assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
01011   assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
01012   if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
01013   {
01014     assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
01015   }
01016   assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
01017   if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
01018   {
01019     assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
01020     assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
01021     assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
01022   }
01023   assert_param(IS_DAC_CHANNEL(Channel));
01024
01025   /* Process locked */
01026   __HAL_LOCK(hdac);
01027
01028   /* Change DAC state */
01029   hdac->State = HAL_DAC_STATE_BUSY;
01030
01031   /* Sample and hold configuration */
01032   if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
01033   {
01034     /* Get timeout */
01035     tickstart = HAL_GetTick();
01036
01037     if (Channel == DAC_CHANNEL_1)
01038     {
01039       /* SHSR1 can be written when BWST1 is cleared */
01040       while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
01041       {
01042         /* Check for the Timeout */
01043         if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
01044         {
01045           /* Update error code */
01046           SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
01047
01048           /* Change the DMA state */
01049           hdac->State = HAL_DAC_STATE_TIMEOUT;
01050
01051           return HAL_TIMEOUT;
01052         }
01053       }
01054       HAL_Delay(1);
01055       hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
01056     }
01057
01058     else /* Channel 2 */
01059     {
01060       /* SHSR2 can be written when BWST2 is cleared */
01061       while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
01062       {
01063         /* Check for the Timeout */
01064         if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
01065         {
01066           /* Update error code */
01067           SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
01068
01069           /* Change the DMA state */
01070           hdac->State = HAL_DAC_STATE_TIMEOUT;
01071
01072           return HAL_TIMEOUT;
01073         }
01074       }
01075       HAL_Delay(1U);
01076       hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
01077     }
01078
01079
01080     /* HoldTime */
01081     MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
01082                (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
01083     /* RefreshTime */
01084     MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
01085                (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
01086   }
01087
01088   if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
01089     /* USER TRIMMING */
01090   {
01091     /* Get the DAC CCR value */
01092     tmpreg1 = hdac->Instance->CCR;
01093     /* Clear trimming value */
01094     tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
01095     /* Configure for the selected trimming offset */
01096     tmpreg2 = sConfig->DAC_TrimmingValue;
01097     /* Calculate CCR register value depending on DAC_Channel */
01098     tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01099     /* Write to DAC CCR */
01100     hdac->Instance->CCR = tmpreg1;
01101   }
01102   /* else factory trimming is used (factory setting are available at reset)*/
01103   /* SW Nothing has nothing to do */
01104
01105   /* Get the DAC MCR value */
01106   tmpreg1 = hdac->Instance->MCR;
01107   /* Clear DAC_MCR_MODEx bits */
01108   tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
01109   /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
01110   tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
01111   /* Calculate MCR register value depending on DAC_Channel */
01112   tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01113   /* Write to DAC MCR */
01114   hdac->Instance->MCR = tmpreg1;
01115
01116   /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
01117   CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
01118
01119   /* Get the DAC CR value */
01120   tmpreg1 = hdac->Instance->CR;
01121   /* Clear TENx, TSELx, WAVEx and MAMPx bits */
01122   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
01123   /* Configure for the selected DAC channel: trigger */
01124   /* Set TSELx and TENx bits according to DAC_Trigger value */
01125   tmpreg2 = sConfig->DAC_Trigger;
01126   /* Calculate CR register value depending on DAC_Channel */
01127   tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
01128   /* Write to DAC CR */
01129   hdac->Instance->CR = tmpreg1;
01130   /* Disable wave generation */
01131   CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
01132
01133   /* Change DAC state */
01134   hdac->State = HAL_DAC_STATE_READY;
01135
01136   /* Process unlocked */
01137   __HAL_UNLOCK(hdac);
01138
01139   /* Return function status */
01140   return HAL_OK;
01141 }
01142
01143 /**
01144   * @}
01145   */
01146
01147 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
01148   *  @brief   Peripheral State and Errors functions
01149   *
01150 @verbatim
01151   ==============================================================================
01152             ##### Peripheral State and Errors functions #####
01153   ==============================================================================
01154     [..]
01155     This subsection provides functions allowing to
01156       (+) Check the DAC state.
01157       (+) Check the DAC Errors.
01158
01159 @endverbatim
01160   * @{
01161   */
01162
01163 /**
01164   * @brief  return the DAC handle state
01165   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01166   *         the configuration information for the specified DAC.
01167   * @retval HAL state
01168   */
01169 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
01170 {
01171   /* Return DAC handle state */
01172   return hdac->State;
01173 }
01174
01175
01176 /**
01177   * @brief  Return the DAC error code
01178   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
01179   *         the configuration information for the specified DAC.
01180   * @retval DAC Error Code
01181   */
01182 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
01183 {
01184   return hdac->ErrorCode;
01185 }
01186
01187 /**
01188   * @}
01189   */
01190
01191 /**
01192   * @}
01193   */
01194
01195 /** @addtogroup DAC_Exported_Functions
01196   * @{
01197   */
01198
01199 /** @addtogroup DAC_Exported_Functions_Group1
01200   * @{
01201   */
01202 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01203 /**
01204   * @brief  Register a User DAC Callback
01205   *         To be used instead of the weak (surcharged) predefined callback
01206   * @param  hdac DAC handle
01207   * @param  CallbackID ID of the callback to be registered
01208   *         This parameter can be one of the following values:
01209   *          @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK   DAC Error Callback ID
01210   *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID       DAC CH1 Complete Callback ID
01211   *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID  DAC CH1 Half Complete Callback ID
01212   *          @arg @ref HAL_DAC_CH1_ERROR_ID             DAC CH1 Error Callback ID
01213   *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID       DAC CH1 UnderRun Callback ID
01214   *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID
01215   *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID
01216   *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID
01217   *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID
01218   *          @arg @ref HAL_DAC_MSPINIT_CB_ID            DAC MSP Init Callback ID
01219   *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID          DAC MSP DeInit Callback ID
01220   *
01221   * @param  pCallback pointer to the Callback function
01222   * @retval status
01223   */
01224 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
01225                                            pDAC_CallbackTypeDef pCallback)
01226 {
01227   HAL_StatusTypeDef status = HAL_OK;
01228
01229   if (pCallback == NULL)
01230   {
01231     /* Update the error code */
01232     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01233     return HAL_ERROR;
01234   }
01235
01236   /* Process locked */
01237   __HAL_LOCK(hdac);
01238
01239   if (hdac->State == HAL_DAC_STATE_READY)
01240   {
01241     switch (CallbackID)
01242     {
01243       case HAL_DAC_CH1_COMPLETE_CB_ID :
01244         hdac->ConvCpltCallbackCh1 = pCallback;
01245         break;
01246       case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
01247         hdac->ConvHalfCpltCallbackCh1 = pCallback;
01248         break;
01249       case HAL_DAC_CH1_ERROR_ID :
01250         hdac->ErrorCallbackCh1 = pCallback;
01251         break;
01252       case HAL_DAC_CH1_UNDERRUN_CB_ID :
01253         hdac->DMAUnderrunCallbackCh1 = pCallback;
01254         break;
01255
01256       case HAL_DAC_CH2_COMPLETE_CB_ID :
01257         hdac->ConvCpltCallbackCh2 = pCallback;
01258         break;
01259       case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
01260         hdac->ConvHalfCpltCallbackCh2 = pCallback;
01261         break;
01262       case HAL_DAC_CH2_ERROR_ID :
01263         hdac->ErrorCallbackCh2 = pCallback;
01264         break;
01265       case HAL_DAC_CH2_UNDERRUN_CB_ID :
01266         hdac->DMAUnderrunCallbackCh2 = pCallback;
01267         break;
01268
01269       case HAL_DAC_MSPINIT_CB_ID :
01270         hdac->MspInitCallback = pCallback;
01271         break;
01272       case HAL_DAC_MSPDEINIT_CB_ID :
01273         hdac->MspDeInitCallback = pCallback;
01274         break;
01275       default :
01276         /* Update the error code */
01277         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01278         /* update return status */
01279         status =  HAL_ERROR;
01280         break;
01281     }
01282   }
01283   else if (hdac->State == HAL_DAC_STATE_RESET)
01284   {
01285     switch (CallbackID)
01286     {
01287       case HAL_DAC_MSPINIT_CB_ID :
01288         hdac->MspInitCallback = pCallback;
01289         break;
01290       case HAL_DAC_MSPDEINIT_CB_ID :
01291         hdac->MspDeInitCallback = pCallback;
01292         break;
01293       default :
01294         /* Update the error code */
01295         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01296         /* update return status */
01297         status =  HAL_ERROR;
01298         break;
01299     }
01300   }
01301   else
01302   {
01303     /* Update the error code */
01304     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01305     /* update return status */
01306     status =  HAL_ERROR;
01307   }
01308
01309   /* Release Lock */
01310   __HAL_UNLOCK(hdac);
01311   return status;
01312 }
01313
01314 /**
01315   * @brief  Unregister a User DAC Callback
01316   *         DAC Callback is redirected to the weak (surcharged) predefined callback
01317   * @param  hdac DAC handle
01318   * @param  CallbackID ID of the callback to be unregistered
01319   *         This parameter can be one of the following values:
01320   *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 transfer Complete Callback ID
01321   *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID
01322   *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID
01323   *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
01324   *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID
01325   *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID
01326   *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID
01327   *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID
01328   *          @arg @ref HAL_DAC_MSPINIT_CB_ID               DAC MSP Init Callback ID
01329   *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID             DAC MSP DeInit Callback ID
01330   *          @arg @ref HAL_DAC_ALL_CB_ID                   DAC All callbacks
01331   * @retval status
01332   */
01333 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
01334 {
01335   HAL_StatusTypeDef status = HAL_OK;
01336
01337   /* Process locked */
01338   __HAL_LOCK(hdac);
01339
01340   if (hdac->State == HAL_DAC_STATE_READY)
01341   {
01342     switch (CallbackID)
01343     {
01344       case HAL_DAC_CH1_COMPLETE_CB_ID :
01345         hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
01346         break;
01347       case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
01348         hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
01349         break;
01350       case HAL_DAC_CH1_ERROR_ID :
01351         hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
01352         break;
01353       case HAL_DAC_CH1_UNDERRUN_CB_ID :
01354         hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
01355         break;
01356
01357       case HAL_DAC_CH2_COMPLETE_CB_ID :
01358         hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
01359         break;
01360       case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
01361         hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
01362         break;
01363       case HAL_DAC_CH2_ERROR_ID :
01364         hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
01365         break;
01366       case HAL_DAC_CH2_UNDERRUN_CB_ID :
01367         hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
01368         break;
01369
01370       case HAL_DAC_MSPINIT_CB_ID :
01371         hdac->MspInitCallback = HAL_DAC_MspInit;
01372         break;
01373       case HAL_DAC_MSPDEINIT_CB_ID :
01374         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01375         break;
01376       case HAL_DAC_ALL_CB_ID :
01377         hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
01378         hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
01379         hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
01380         hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
01381
01382         hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
01383         hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
01384         hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
01385         hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
01386
01387         hdac->MspInitCallback = HAL_DAC_MspInit;
01388         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01389         break;
01390       default :
01391         /* Update the error code */
01392         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01393         /* update return status */
01394         status =  HAL_ERROR;
01395         break;
01396     }
01397   }
01398   else if (hdac->State == HAL_DAC_STATE_RESET)
01399   {
01400     switch (CallbackID)
01401     {
01402       case HAL_DAC_MSPINIT_CB_ID :
01403         hdac->MspInitCallback = HAL_DAC_MspInit;
01404         break;
01405       case HAL_DAC_MSPDEINIT_CB_ID :
01406         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
01407         break;
01408       default :
01409         /* Update the error code */
01410         hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01411         /* update return status */
01412         status =  HAL_ERROR;
01413         break;
01414     }
01415   }
01416   else
01417   {
01418     /* Update the error code */
01419     hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
01420     /* update return status */
01421     status =  HAL_ERROR;
01422   }
01423
01424   /* Release Lock */
01425   __HAL_UNLOCK(hdac);
01426   return status;
01427 }
01428 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01429
01430 /**
01431   * @}
01432   */
01433
01434 /**
01435   * @}
01436   */
01437
01438 /** @addtogroup DAC_Private_Functions
01439   * @{
01440   */
01441
01442 /**
01443   * @brief  DMA conversion complete callback.
01444   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01445   *                the configuration information for the specified DMA module.
01446   * @retval None
01447   */
01448 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
01449 {
01450   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01451
01452 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01453   hdac->ConvCpltCallbackCh1(hdac);
01454 #else
01455   HAL_DAC_ConvCpltCallbackCh1(hdac);
01456 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01457
01458   hdac->State = HAL_DAC_STATE_READY;
01459 }
01460
01461 /**
01462   * @brief  DMA half transfer complete callback.
01463   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01464   *                the configuration information for the specified DMA module.
01465   * @retval None
01466   */
01467 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
01468 {
01469   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01470   /* Conversion complete callback */
01471 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01472   hdac->ConvHalfCpltCallbackCh1(hdac);
01473 #else
01474   HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
01475 #endif  /* USE_HAL_DAC_REGISTER_CALLBACKS */
01476 }
01477
01478 /**
01479   * @brief  DMA error callback
01480   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01481   *                the configuration information for the specified DMA module.
01482   * @retval None
01483   */
01484 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
01485 {
01486   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
01487
01488   /* Set DAC error code to DMA error */
01489   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
01490
01491 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
01492   hdac->ErrorCallbackCh1(hdac);
01493 #else
01494   HAL_DAC_ErrorCallbackCh1(hdac);
01495 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
01496
01497   hdac->State = HAL_DAC_STATE_READY;
01498 }
01499
01500 /**
01501   * @}
01502   */
01503
01504 /**
01505   * @}
01506   */
01507
01508 #endif /* DAC1 */
01509
01510 #endif /* HAL_DAC_MODULE_ENABLED */
01511
01512 /**
01513   * @}
01514   */
01515
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dac.h Source File

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stm32g0xx_hal_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_DAC_H
00021 #define STM32G0xx_HAL_DAC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /** @addtogroup STM32G0xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32g0xx_hal_def.h"
00033
00034 #if defined(DAC1)
00035
00036 /** @addtogroup DAC
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /** @defgroup DAC_Exported_Types DAC Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  HAL State structures definition
00048   */
00049 typedef enum
00050 {
00051   HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
00052   HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
00053   HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
00054   HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
00055   HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
00056
00057 } HAL_DAC_StateTypeDef;
00058
00059 /**
00060   * @brief  DAC handle Structure definition
00061   */
00062 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00063 typedef struct __DAC_HandleTypeDef
00064 #else
00065 typedef struct
00066 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00067 {
00068   DAC_TypeDef                 *Instance;     /*!< Register base address             */
00069
00070   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
00071
00072   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00073
00074   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
00075
00076   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
00077
00078   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00079
00080 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00081   void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
00082   void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
00083   void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
00084   void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
00085
00086   void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef *hdac);
00087   void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef *hdac);
00088   void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef *hdac);
00089   void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef *hdac);
00090
00091
00092   void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
00093   void (* MspDeInitCallback)              (struct __DAC_HandleTypeDef *hdac);
00094 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00095
00096 } DAC_HandleTypeDef;
00097
00098 /**
00099   * @brief   DAC Configuration sample and hold Channel structure definition
00100   */
00101 typedef struct
00102 {
00103   uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
00104                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00105                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00106
00107   uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
00108                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00109                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00110
00111   uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
00112                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00113                                           This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
00114 } DAC_SampleAndHoldConfTypeDef;
00115
00116 /**
00117   * @brief   DAC Configuration regular Channel structure definition
00118   */
00119 typedef struct
00120 {
00121   uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
00122                                               This parameter can be a value of @ref DAC_SampleAndHold */
00123
00124   uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
00125                                               This parameter can be a value of @ref DAC_trigger_selection */
00126
00127   uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00128                                                This parameter can be a value of @ref DAC_output_buffer */
00129
00130   uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
00131                                               This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
00132
00133   uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
00134                                               This parameter must be a value of @ref DAC_UserTrimming
00135                                               DAC_UserTrimming is either factory or user trimming */
00136
00137   uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
00138                                                i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
00139                                                This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00140   DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
00141 } DAC_ChannelConfTypeDef;
00142
00143 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00144 /**
00145   * @brief  HAL DAC Callback ID enumeration definition
00146   */
00147 typedef enum
00148 {
00149   HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
00150   HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
00151   HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
00152   HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
00153
00154   HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
00155   HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
00156   HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
00157   HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
00158
00159   HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
00160   HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
00161   HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
00162 } HAL_DAC_CallbackIDTypeDef;
00163
00164 /**
00165   * @brief  HAL DAC Callback pointer definition
00166   */
00167 typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
00168 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00169
00170 /**
00171   * @}
00172   */
00173
00174 /* Exported constants --------------------------------------------------------*/
00175
00176 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00177   * @{
00178   */
00179
00180 /** @defgroup DAC_Error_Code DAC Error Code
00181   * @{
00182   */
00183 #define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
00184 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
00185 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
00186 #define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
00187 #define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
00188 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00189 #define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
00190 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00191
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup DAC_trigger_selection DAC trigger selection
00197   * @{
00198   */
00199 #define DAC_TRIGGER_NONE                0x00000000UL                                                     /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
00200 #define DAC_TRIGGER_SOFTWARE            (DAC_CR_TEN1)                                                    /*!< Conversion started by software trigger for DAC channel */
00201 #define DAC_TRIGGER_T1_TRGO             (DAC_CR_TSEL1_0 | DAC_CR_TEN1)                                   /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
00202 #define DAC_TRIGGER_T2_TRGO             (DAC_CR_TSEL1_1 | DAC_CR_TEN1)                                   /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00203 #define DAC_TRIGGER_T3_TRGO             (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)                  /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
00204 #define DAC_TRIGGER_T6_TRGO             (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)                  /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00205 #define DAC_TRIGGER_T7_TRGO             (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)                  /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00206 #define DAC_TRIGGER_T15_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TEN1)                                   /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
00207 #define DAC_TRIGGER_LPTIM1_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */
00208 #define DAC_TRIGGER_LPTIM2_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)                  /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */
00209 #define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00210
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup DAC_output_buffer DAC output buffer
00216   * @{
00217   */
00218 #define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
00219 #define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)
00220
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup DAC_Channel_selection DAC Channel selection
00226   * @{
00227   */
00228 #define DAC_CHANNEL_1                      0x00000000U
00229
00230 #define DAC_CHANNEL_2                      0x00000010U
00231
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup DAC_data_alignment DAC data alignment
00237   * @{
00238   */
00239 #define DAC_ALIGN_12B_R                    0x00000000U
00240 #define DAC_ALIGN_12B_L                    0x00000004U
00241 #define DAC_ALIGN_8B_R                     0x00000008U
00242
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup DAC_flags_definition DAC flags definition
00248   * @{
00249   */
00250 #define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
00251
00252 #define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
00253
00254
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup DAC_IT_definition  DAC IT definition
00260   * @{
00261   */
00262 #define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
00263
00264 #define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
00265
00266
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
00272   * @{
00273   */
00274 #define DAC_CHIPCONNECT_DISABLE    (0x00000000UL)
00275 #define DAC_CHIPCONNECT_ENABLE     (DAC_MCR_MODE1_0)
00276
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup DAC_UserTrimming DAC User Trimming
00282   * @{
00283   */
00284 #define DAC_TRIMMING_FACTORY        (0x00000000UL)        /*!< Factory trimming */
00285 #define DAC_TRIMMING_USER           (0x00000001UL)        /*!< User trimming */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup DAC_SampleAndHold DAC power mode
00291   * @{
00292   */
00293 #define DAC_SAMPLEANDHOLD_DISABLE     (0x00000000UL)
00294 #define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)
00295
00296 /**
00297   * @}
00298   */
00299 /**
00300   * @}
00301   */
00302
00303 /* Exported macro ------------------------------------------------------------*/
00304
00305 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00306   * @{
00307   */
00308
00309 /** @brief Reset DAC handle state.
00310   * @param  __HANDLE__ specifies the DAC handle.
00311   * @retval None
00312   */
00313 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00314 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
00315                                                       (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
00316                                                       (__HANDLE__)->MspInitCallback   = NULL;                \
00317                                                       (__HANDLE__)->MspDeInitCallback = NULL;                \
00318                                                      } while(0)
00319 #else
00320 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00321 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00322
00323 /** @brief Enable the DAC channel.
00324   * @param  __HANDLE__ specifies the DAC handle.
00325   * @param  __DAC_Channel__ specifies the DAC channel
00326   * @retval None
00327   */
00328 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
00329   ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
00330
00331 /** @brief Disable the DAC channel.
00332   * @param  __HANDLE__ specifies the DAC handle
00333   * @param  __DAC_Channel__ specifies the DAC channel.
00334   * @retval None
00335   */
00336 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
00337   ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
00338
00339 /** @brief Set DHR12R1 alignment.
00340   * @param  __ALIGNMENT__ specifies the DAC alignment
00341   * @retval None
00342   */
00343 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
00344
00345
00346 /** @brief  Set DHR12R2 alignment.
00347   * @param  __ALIGNMENT__ specifies the DAC alignment
00348   * @retval None
00349   */
00350 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
00351
00352
00353 /** @brief  Set DHR12RD alignment.
00354   * @param  __ALIGNMENT__ specifies the DAC alignment
00355   * @retval None
00356   */
00357 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
00358
00359 /** @brief Enable the DAC interrupt.
00360   * @param  __HANDLE__ specifies the DAC handle
00361   * @param  __INTERRUPT__ specifies the DAC interrupt.
00362   *          This parameter can be any combination of the following values:
00363   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00364   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
00365   * @retval None
00366   */
00367 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00368
00369 /** @brief Disable the DAC interrupt.
00370   * @param  __HANDLE__ specifies the DAC handle
00371   * @param  __INTERRUPT__ specifies the DAC interrupt.
00372   *          This parameter can be any combination of the following values:
00373   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00374   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
00375   * @retval None
00376   */
00377 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00378
00379 /** @brief  Check whether the specified DAC interrupt source is enabled or not.
00380   * @param __HANDLE__ DAC handle
00381   * @param __INTERRUPT__ DAC interrupt source to check
00382   *          This parameter can be any combination of the following values:
00383   *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
00384   *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
00385   * @retval State of interruption (SET or RESET)
00386   */
00387 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
00388                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
00389
00390 /** @brief  Get the selected DAC's flag status.
00391   * @param  __HANDLE__ specifies the DAC handle.
00392   * @param  __FLAG__ specifies the DAC flag to get.
00393   *          This parameter can be any combination of the following values:
00394   *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
00395   *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
00396   * @retval None
00397   */
00398 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00399
00400 /** @brief  Clear the DAC's flag.
00401   * @param  __HANDLE__ specifies the DAC handle.
00402   * @param  __FLAG__ specifies the DAC flag to clear.
00403   *          This parameter can be any combination of the following values:
00404   *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
00405   *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
00406   * @retval None
00407   */
00408 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00409
00410 /**
00411   * @}
00412   */
00413
00414 /* Private macro -------------------------------------------------------------*/
00415
00416 /** @defgroup DAC_Private_Macros DAC Private Macros
00417   * @{
00418   */
00419 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00420                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00421
00422 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00423                                  ((CHANNEL) == DAC_CHANNEL_2))
00424
00425 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00426                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00427                              ((ALIGN) == DAC_ALIGN_8B_R))
00428
00429 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
00430
00431 #define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFUL)
00432
00433 /**
00434   * @}
00435   */
00436
00437 /* Include DAC HAL Extended module */
00438 #include "stm32g0xx_hal_dac_ex.h"
00439
00440 /* Exported functions --------------------------------------------------------*/
00441
00442 /** @addtogroup DAC_Exported_Functions
00443   * @{
00444   */
00445
00446 /** @addtogroup DAC_Exported_Functions_Group1
00447   * @{
00448   */
00449 /* Initialization and de-initialization functions *****************************/
00450 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
00451 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
00452 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
00453 void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
00454
00455 /**
00456   * @}
00457   */
00458
00459 /** @addtogroup DAC_Exported_Functions_Group2
00460   * @{
00461   */
00462 /* IO operation functions *****************************************************/
00463 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
00464 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
00465 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
00466                                     uint32_t Alignment);
00467 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
00468 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
00469 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00470
00471 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
00472 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
00473 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00474 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00475
00476 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00477 /* DAC callback registering/unregistering */
00478 HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
00479                                                pDAC_CallbackTypeDef pCallback);
00480 HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
00481 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00482
00483 /**
00484   * @}
00485   */
00486
00487 /** @addtogroup DAC_Exported_Functions_Group3
00488   * @{
00489   */
00490 /* Peripheral Control functions ***********************************************/
00491 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
00492 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
00493 /**
00494   * @}
00495   */
00496
00497 /** @addtogroup DAC_Exported_Functions_Group4
00498   * @{
00499   */
00500 /* Peripheral State and Error functions ***************************************/
00501 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
00502 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
00503
00504 /**
00505   * @}
00506   */
00507
00508 /**
00509   * @}
00510   */
00511
00512 /** @defgroup DAC_Private_Functions DAC Private Functions
00513   * @{
00514   */
00515 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00516 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00517 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00518 /**
00519   * @}
00520   */
00521
00522 /**
00523   * @}
00524   */
00525
00526 #endif /* DAC1 */
00527
00528 /**
00529   * @}
00530   */
00531
00532 #ifdef __cplusplus
00533 }
00534 #endif
00535
00536
00537 #endif /* STM32G0xx_HAL_DAC_H */
00538
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dac_ex.c Source File

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stm32g0xx_hal_dac_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended DAC HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the DAC peripheral.
00008   *
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2018 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   @verbatim
00022   ==============================================================================
00023                       ##### How to use this driver #####
00024   ==============================================================================
00025     [..]
00026
00027      *** Dual mode IO operation ***
00028      ==============================
00029      [..]
00030       (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
00031           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00032           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
00033           Channel 1 and Channel 2.
00034
00035      *** Signal generation operation ***
00036      ===================================
00037      [..]
00038       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00039       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00040
00041       (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
00042       (+) HAL_DACEx_SetUserTrimming to set user trimming value.
00043       (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
00044           after reset, user setting if HAL_DACEx_SetUserTrimming have been used
00045           at least one time after reset).
00046
00047  @endverbatim
00048   ******************************************************************************
00049   */
00050
00051
00052 /* Includes ------------------------------------------------------------------*/
00053 #include "stm32g0xx_hal.h"
00054
00055 /** @addtogroup STM32G0xx_HAL_Driver
00056   * @{
00057   */
00058
00059 #ifdef HAL_DAC_MODULE_ENABLED
00060
00061 #if defined(DAC1)
00062
00063 /** @defgroup DACEx DACEx
00064   * @brief DAC Extended HAL module driver
00065   * @{
00066   */
00067
00068 /* Private typedef -----------------------------------------------------------*/
00069 /* Private define ------------------------------------------------------------*/
00070 /* Private macro -------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 /* Exported functions --------------------------------------------------------*/
00074
00075 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
00076   * @{
00077   */
00078
00079 /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
00080   *  @brief    Extended IO operation functions
00081   *
00082 @verbatim
00083   ==============================================================================
00084                  ##### Extended features functions #####
00085   ==============================================================================
00086     [..]  This section provides functions allowing to:
00087       (+) Start conversion.
00088       (+) Stop conversion.
00089       (+) Start conversion and enable DMA transfer.
00090       (+) Stop conversion and disable DMA transfer.
00091       (+) Get result of conversion.
00092       (+) Get result of dual mode conversion.
00093
00094 @endverbatim
00095   * @{
00096   */
00097
00098
00099 /**
00100   * @brief  Enables DAC and starts conversion of both channels.
00101   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00102   *         the configuration information for the specified DAC.
00103   * @retval HAL status
00104   */
00105 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
00106 {
00107   uint32_t tmp_swtrig = 0UL;
00108
00109
00110   /* Process locked */
00111   __HAL_LOCK(hdac);
00112
00113   /* Change DAC state */
00114   hdac->State = HAL_DAC_STATE_BUSY;
00115
00116   /* Enable the Peripheral */
00117   __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
00118   __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
00119
00120   /* Check if software trigger enabled */
00121   if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
00122   {
00123     tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
00124   }
00125   if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
00126   {
00127     tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
00128   }
00129   /* Enable the selected DAC software conversion*/
00130   SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
00131
00132   /* Change DAC state */
00133   hdac->State = HAL_DAC_STATE_READY;
00134
00135   /* Process unlocked */
00136   __HAL_UNLOCK(hdac);
00137
00138   /* Return function status */
00139   return HAL_OK;
00140 }
00141
00142 /**
00143   * @brief  Disables DAC and stop conversion of both channels.
00144   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00145   *         the configuration information for the specified DAC.
00146   * @retval HAL status
00147   */
00148 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
00149 {
00150
00151   /* Disable the Peripheral */
00152   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
00153   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
00154
00155   /* Change DAC state */
00156   hdac->State = HAL_DAC_STATE_READY;
00157
00158   /* Return function status */
00159   return HAL_OK;
00160 }
00161
00162
00163 /**
00164   * @brief  Enable or disable the selected DAC channel wave generation.
00165   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00166   *         the configuration information for the specified DAC.
00167   * @param  Channel The selected DAC channel.
00168   *          This parameter can be one of the following values:
00169   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00170   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00171   * @param  Amplitude Select max triangle amplitude.
00172   *          This parameter can be one of the following values:
00173   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00174   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00175   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00176   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00177   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00178   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00179   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00180   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00181   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00182   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00183   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00184   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00185   * @retval HAL status
00186   */
00187 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
00188 {
00189   /* Check the parameters */
00190   assert_param(IS_DAC_CHANNEL(Channel));
00191   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00192
00193   /* Process locked */
00194   __HAL_LOCK(hdac);
00195
00196   /* Change DAC state */
00197   hdac->State = HAL_DAC_STATE_BUSY;
00198
00199   /* Enable the triangle wave generation for the selected DAC channel */
00200   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
00201              (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
00202
00203   /* Change DAC state */
00204   hdac->State = HAL_DAC_STATE_READY;
00205
00206   /* Process unlocked */
00207   __HAL_UNLOCK(hdac);
00208
00209   /* Return function status */
00210   return HAL_OK;
00211 }
00212
00213 /**
00214   * @brief  Enable or disable the selected DAC channel wave generation.
00215   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00216   *         the configuration information for the specified DAC.
00217   * @param  Channel The selected DAC channel.
00218   *          This parameter can be one of the following values:
00219   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00220   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00221   * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
00222   *          This parameter can be one of the following values:
00223   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00224   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00225   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00226   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00227   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00228   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00229   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00230   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00231   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00232   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00233   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00234   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
00238 {
00239   /* Check the parameters */
00240   assert_param(IS_DAC_CHANNEL(Channel));
00241   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00242
00243   /* Process locked */
00244   __HAL_LOCK(hdac);
00245
00246   /* Change DAC state */
00247   hdac->State = HAL_DAC_STATE_BUSY;
00248
00249   /* Enable the noise wave generation for the selected DAC channel */
00250   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
00251              (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
00252
00253   /* Change DAC state */
00254   hdac->State = HAL_DAC_STATE_READY;
00255
00256   /* Process unlocked */
00257   __HAL_UNLOCK(hdac);
00258
00259   /* Return function status */
00260   return HAL_OK;
00261 }
00262
00263
00264 /**
00265   * @brief  Set the specified data holding register value for dual DAC channel.
00266   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00267   *               the configuration information for the specified DAC.
00268   * @param  Alignment Specifies the data alignment for dual channel DAC.
00269   *          This parameter can be one of the following values:
00270   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
00271   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
00272   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
00273   * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
00274   * @param  Data2 Data for DAC Channel2 to be loaded in the selected data  holding register.
00275   * @note   In dual mode, a unique register access is required to write in both
00276   *          DAC channels at the same time.
00277   * @retval HAL status
00278   */
00279 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00280 {
00281   uint32_t data;
00282   uint32_t tmp;
00283
00284   /* Check the parameters */
00285   assert_param(IS_DAC_ALIGN(Alignment));
00286   assert_param(IS_DAC_DATA(Data1));
00287   assert_param(IS_DAC_DATA(Data2));
00288
00289   /* Calculate and set dual DAC data holding register value */
00290   if (Alignment == DAC_ALIGN_8B_R)
00291   {
00292     data = ((uint32_t)Data2 << 8U) | Data1;
00293   }
00294   else
00295   {
00296     data = ((uint32_t)Data2 << 16U) | Data1;
00297   }
00298
00299   tmp = (uint32_t)hdac->Instance;
00300   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00301
00302   /* Set the dual DAC selected data holding register */
00303   *(__IO uint32_t *)tmp = data;
00304
00305   /* Return function status */
00306   return HAL_OK;
00307 }
00308
00309 /**
00310   * @brief  Conversion complete callback in non-blocking mode for Channel2.
00311   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00312   *         the configuration information for the specified DAC.
00313   * @retval None
00314   */
00315 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
00316 {
00317   /* Prevent unused argument(s) compilation warning */
00318   UNUSED(hdac);
00319
00320   /* NOTE : This function should not be modified, when the callback is needed,
00321             the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
00322    */
00323 }
00324
00325 /**
00326   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
00327   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00328   *         the configuration information for the specified DAC.
00329   * @retval None
00330   */
00331 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
00332 {
00333   /* Prevent unused argument(s) compilation warning */
00334   UNUSED(hdac);
00335
00336   /* NOTE : This function should not be modified, when the callback is needed,
00337             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
00338    */
00339 }
00340
00341 /**
00342   * @brief  Error DAC callback for Channel2.
00343   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00344   *         the configuration information for the specified DAC.
00345   * @retval None
00346   */
00347 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00348 {
00349   /* Prevent unused argument(s) compilation warning */
00350   UNUSED(hdac);
00351
00352   /* NOTE : This function should not be modified, when the callback is needed,
00353             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
00354    */
00355 }
00356
00357 /**
00358   * @brief  DMA underrun DAC callback for Channel2.
00359   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00360   *         the configuration information for the specified DAC.
00361   * @retval None
00362   */
00363 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
00364 {
00365   /* Prevent unused argument(s) compilation warning */
00366   UNUSED(hdac);
00367
00368   /* NOTE : This function should not be modified, when the callback is needed,
00369             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
00370    */
00371 }
00372
00373
00374 /**
00375   * @brief  Run the self calibration of one DAC channel.
00376   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00377   *         the configuration information for the specified DAC.
00378   * @param  sConfig DAC channel configuration structure.
00379   * @param  Channel The selected DAC channel.
00380   *          This parameter can be one of the following values:
00381   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00382   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00383   * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
00384   * @retval HAL status
00385   * @note   Calibration runs about 7 ms.
00386   */
00387 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
00388 {
00389   HAL_StatusTypeDef status = HAL_OK;
00390
00391   __IO uint32_t tmp;
00392   uint32_t trimmingvalue;
00393   uint32_t delta;
00394
00395   /* store/restore channel configuration structure purpose */
00396   uint32_t oldmodeconfiguration;
00397
00398   /* Check the parameters */
00399   assert_param(IS_DAC_CHANNEL(Channel));
00400
00401   /* Check the DAC handle allocation */
00402   /* Check if DAC running */
00403   if (hdac == NULL)
00404   {
00405     status = HAL_ERROR;
00406   }
00407   else if (hdac->State == HAL_DAC_STATE_BUSY)
00408   {
00409     status = HAL_ERROR;
00410   }
00411   else
00412   {
00413     /* Process locked */
00414     __HAL_LOCK(hdac);
00415
00416     /* Store configuration */
00417     oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
00418
00419     /* Disable the selected DAC channel */
00420     CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
00421
00422     /* Set mode in MCR  for calibration */
00423     MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
00424
00425     /* Set DAC Channel1 DHR register to the middle value */
00426     tmp = (uint32_t)hdac->Instance;
00427
00428     if (Channel == DAC_CHANNEL_1)
00429     {
00430       tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
00431     }
00432     else
00433     {
00434       tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
00435     }
00436
00437     *(__IO uint32_t *) tmp = 0x0800UL;
00438
00439     /* Enable the selected DAC channel calibration */
00440     /* i.e. set DAC_CR_CENx bit */
00441     SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
00442
00443     /* Init trimming counter */
00444     /* Medium value */
00445     trimmingvalue = 16UL;
00446     delta = 8UL;
00447     while (delta != 0UL)
00448     {
00449       /* Set candidate trimming */
00450       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00451
00452       /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
00453       /* i.e. minimum time needed between two calibration steps */
00454       HAL_Delay(1);
00455
00456       if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
00457       {
00458         /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
00459         trimmingvalue -= delta;
00460       }
00461       else
00462       {
00463         /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
00464         trimmingvalue += delta;
00465       }
00466       delta >>= 1UL;
00467     }
00468
00469     /* Still need to check if right calibration is current value or one step below */
00470     /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
00471     /* Set candidate trimming */
00472     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00473
00474     /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
00475     /* i.e. minimum time needed between two calibration steps */
00476     HAL_Delay(1U);
00477
00478     if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
00479     {
00480       /* Trimming is actually one value more */
00481       trimmingvalue++;
00482       /* Set right trimming */
00483       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
00484     }
00485
00486     /* Disable the selected DAC channel calibration */
00487     /* i.e. clear DAC_CR_CENx bit */
00488     CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
00489
00490     sConfig->DAC_TrimmingValue = trimmingvalue;
00491     sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00492
00493     /* Restore configuration */
00494     MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
00495
00496     /* Process unlocked */
00497     __HAL_UNLOCK(hdac);
00498   }
00499
00500   return status;
00501 }
00502
00503 /**
00504   * @brief  Set the trimming mode and trimming value (user trimming mode applied).
00505   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00506   *         the configuration information for the specified DAC.
00507   * @param  sConfig DAC configuration structure updated with new DAC trimming value.
00508   * @param  Channel The selected DAC channel.
00509   *          This parameter can be one of the following values:
00510   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00511   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00512   * @param  NewTrimmingValue DAC new trimming value
00513   * @retval HAL status
00514   */
00515 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
00516                                             uint32_t NewTrimmingValue)
00517 {
00518   HAL_StatusTypeDef status = HAL_OK;
00519
00520   /* Check the parameters */
00521   assert_param(IS_DAC_CHANNEL(Channel));
00522   assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
00523
00524   /* Check the DAC handle allocation */
00525   if (hdac == NULL)
00526   {
00527     status = HAL_ERROR;
00528   }
00529   else
00530   {
00531     /* Process locked */
00532     __HAL_LOCK(hdac);
00533
00534     /* Set new trimming */
00535     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
00536
00537     /* Update trimming mode */
00538     sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00539     sConfig->DAC_TrimmingValue = NewTrimmingValue;
00540
00541     /* Process unlocked */
00542     __HAL_UNLOCK(hdac);
00543   }
00544   return status;
00545 }
00546
00547 /**
00548   * @brief  Return the DAC trimming value.
00549   * @param  hdac DAC handle
00550   * @param  Channel The selected DAC channel.
00551   *          This parameter can be one of the following values:
00552   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00553   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00554   * @retval Trimming value : range: 0->31
00555   *
00556  */
00557 uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
00558 {
00559   /* Check the parameter */
00560   assert_param(IS_DAC_CHANNEL(Channel));
00561
00562   /* Retrieve trimming */
00563   return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
00564 }
00565
00566 /**
00567   * @}
00568   */
00569
00570 /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
00571   *  @brief    Extended Peripheral Control functions
00572   *
00573 @verbatim
00574   ==============================================================================
00575              ##### Peripheral Control functions #####
00576   ==============================================================================
00577     [..]  This section provides functions allowing to:
00578       (+) Set the specified data holding register value for DAC channel.
00579
00580 @endverbatim
00581   * @{
00582   */
00583
00584
00585 /**
00586   * @brief  Return the last data output value of the selected DAC channel.
00587   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
00588   *         the configuration information for the specified DAC.
00589   * @retval The selected DAC channel data output value.
00590   */
00591 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
00592 {
00593   uint32_t tmp = 0UL;
00594
00595   tmp |= hdac->Instance->DOR1;
00596
00597   tmp |= hdac->Instance->DOR2 << 16UL;
00598
00599   /* Returns the DAC channel data output register value */
00600   return tmp;
00601 }
00602
00603
00604 /**
00605   * @}
00606   */
00607 /**
00608   * @}
00609   */
00610
00611 /* Private functions ---------------------------------------------------------*/
00612 /** @defgroup DACEx_Private_Functions DACEx private functions
00613   *  @brief    Extended private functions
00614   * @{
00615   */
00616
00617
00618 /**
00619   * @brief  DMA conversion complete callback.
00620   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00621   *                the configuration information for the specified DMA module.
00622   * @retval None
00623   */
00624 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
00625 {
00626   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00627
00628 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00629   hdac->ConvCpltCallbackCh2(hdac);
00630 #else
00631   HAL_DACEx_ConvCpltCallbackCh2(hdac);
00632 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00633
00634   hdac->State = HAL_DAC_STATE_READY;
00635 }
00636
00637 /**
00638   * @brief  DMA half transfer complete callback.
00639   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00640   *                the configuration information for the specified DMA module.
00641   * @retval None
00642   */
00643 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
00644 {
00645   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00646   /* Conversion complete callback */
00647 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00648   hdac->ConvHalfCpltCallbackCh2(hdac);
00649 #else
00650   HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
00651 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00652 }
00653
00654 /**
00655   * @brief  DMA error callback.
00656   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
00657   *                the configuration information for the specified DMA module.
00658   * @retval None
00659   */
00660 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
00661 {
00662   DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
00663
00664   /* Set DAC error code to DMA error */
00665   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00666
00667 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
00668   hdac->ErrorCallbackCh2(hdac);
00669 #else
00670   HAL_DACEx_ErrorCallbackCh2(hdac);
00671 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
00672
00673   hdac->State = HAL_DAC_STATE_READY;
00674 }
00675
00676
00677 /**
00678   * @}
00679   */
00680
00681 /**
00682   * @}
00683   */
00684
00685 #endif /* DAC1 */
00686
00687 #endif /* HAL_DAC_MODULE_ENABLED */
00688
00689 /**
00690   * @}
00691   */
00692
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dac_ex.h Source File

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stm32g0xx_hal_dac_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_dac_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_DAC_EX_H
00021 #define STM32G0xx_HAL_DAC_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /** @addtogroup STM32G0xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32g0xx_hal_def.h"
00033
00034 #if defined(DAC1)
00035
00036 /** @addtogroup DACEx
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /**
00043   * @brief  HAL State structures definition
00044   */
00045
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
00049   * @{
00050   */
00051
00052 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
00053   * @{
00054   */
00055 #define DAC_LFSRUNMASK_BIT0                0x00000000UL                                                        /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00056 #define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00057 #define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00058 #define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00059 #define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00060 #define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00061 #define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00062 #define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00063 #define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00064 #define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00065 #define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00066 #define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00067 #define DAC_TRIANGLEAMPLITUDE_1            0x00000000UL                                                        /*!< Select max triangle amplitude of 1 */
00068 #define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
00069 #define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
00070 #define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
00071 #define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
00072 #define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
00073 #define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
00074 #define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
00075 #define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
00076 #define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
00077 #define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
00078 #define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /**
00085   * @}
00086   */
00087
00088 /* Exported macro ------------------------------------------------------------*/
00089
00090
00091 /* Private macro -------------------------------------------------------------*/
00092
00093 /** @defgroup DACEx_Private_Macros DACEx Private Macros
00094   * @{
00095   */
00096 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
00097                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE)   || \
00098                                  ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
00099                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
00100                                  ((TRIGGER) == DAC_TRIGGER_T3_TRGO)    || \
00101                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
00102                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
00103                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
00104                                  ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
00105                                  ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
00106                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9))
00107
00108 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
00109
00110 #define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x000003FFU)
00111
00112 #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
00113                                     ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
00114
00115 #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
00116
00117 #define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
00118
00119 #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
00120                                          ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
00121
00122 #define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
00123                                    ((TRIMMING) == DAC_TRIMMING_USER))
00124
00125 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00126                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00127                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00128                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00129                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00130                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00131                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00132                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00133                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00134                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00135                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00136                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00137                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00138                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00139                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00140                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00141                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00142                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00143                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00144                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00145                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00146                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00147                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00148                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported functions --------------------------------------------------------*/
00154 /* Extended features functions ***********************************************/
00155
00156 /** @addtogroup DACEx_Exported_Functions
00157   * @{
00158   */
00159
00160 /** @addtogroup DACEx_Exported_Functions_Group2
00161   * @{
00162   */
00163 /* IO operation functions *****************************************************/
00164
00165 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
00166 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
00167
00168 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
00169 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
00170 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00171 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
00172
00173 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
00174 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
00175 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
00176 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
00177
00178
00179 /**
00180   * @}
00181   */
00182
00183 /** @addtogroup DACEx_Exported_Functions_Group3
00184   * @{
00185   */
00186 /* Peripheral Control functions ***********************************************/
00187
00188 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
00189 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
00190                                             uint32_t NewTrimmingValue);
00191 uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
00192
00193 /**
00194   * @}
00195   */
00196
00197 /**
00198   * @}
00199   */
00200
00201 /** @addtogroup DACEx_Private_Functions
00202   * @{
00203   */
00204
00205 /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
00206 /* are called by HAL_DAC_Start_DMA */
00207 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00208 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00209 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00210
00211 /**
00212   * @}
00213   */
00214
00215 /**
00216   * @}
00217   */
00218
00219 #endif /* DAC1 */
00220
00221 /**
00222   * @}
00223   */
00224
00225 #ifdef __cplusplus
00226 }
00227 #endif
00228
00229 #endif /* STM32G0xx_HAL_DAC_EX_H */
00230
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dma.c Source File

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stm32g0xx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Direct Memory Access (DMA) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and errors functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                         ##### How to use this driver #####
00026   ==============================================================================
00027   [..]
00028    (#) Enable and configure the peripheral to be connected to the DMA Channel
00029        (except for internal SRAM / FLASH memories: no initialization is
00030        necessary). Please refer to the Reference manual for connection between peripherals
00031        and DMA requests.
00032
00033    (#) For a given Channel, program the required configuration through the following parameters:
00034        Channel request, Transfer Direction, Source and Destination data formats,
00035        Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
00036        using HAL_DMA_Init() function.
00037
00038        Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
00039        thanks to:
00040       (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE();
00041
00042    (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00043        detection.
00044
00045    (#) Use HAL_DMA_Abort() function to abort the current transfer
00046
00047      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00048
00049      *** Polling mode IO operation ***
00050      =================================
00051      [..]
00052        (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00053            address and destination address and the Length of data to be transferred
00054        (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00055            case a fixed Timeout can be configured by User depending from his application.
00056
00057      *** Interrupt mode IO operation ***
00058      ===================================
00059      [..]
00060        (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00061        (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00062        (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00063            Source address and destination address and the Length of data to be transferred.
00064            In this case the DMA interrupt is configured
00065        (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00066        (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00067               add his own function to register callbacks with HAL_DMA_RegisterCallback().
00068
00069      *** DMA HAL driver macros list ***
00070      =============================================
00071      [..]
00072        Below the list of macros in DMA HAL driver.
00073
00074        (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
00075        (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
00076        (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
00077        (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
00078        (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
00079        (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
00080        (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
00081
00082      [..]
00083       (@) You can refer to the DMA HAL driver header file for more useful macros
00084
00085   @endverbatim
00086   ******************************************************************************
00087   */
00088
00089 /* Includes ------------------------------------------------------------------*/
00090 #include "stm32g0xx_hal.h"
00091
00092 /** @addtogroup STM32G0xx_HAL_Driver
00093   * @{
00094   */
00095
00096 /** @defgroup DMA DMA
00097   * @brief DMA HAL module driver
00098   * @{
00099   */
00100
00101 #ifdef HAL_DMA_MODULE_ENABLED
00102
00103 /* Private typedef -----------------------------------------------------------*/
00104 /* Private define ------------------------------------------------------------*/
00105 /* Private macro -------------------------------------------------------------*/
00106 /* Private variables ---------------------------------------------------------*/
00107 /* Private function prototypes -----------------------------------------------*/
00108
00109 /** @defgroup DMA_Private_Functions DMA Private Functions
00110   * @{
00111   */
00112 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00113 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
00114 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
00115
00116 /**
00117   * @}
00118   */
00119
00120 /* Exported functions ---------------------------------------------------------*/
00121
00122 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00123   * @{
00124   */
00125
00126 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00127   *  @brief   Initialization and de-initialization functions
00128   *
00129 @verbatim
00130  ===============================================================================
00131              ##### Initialization and de-initialization functions  #####
00132  ===============================================================================
00133     [..]
00134     This section provides functions allowing to initialize the DMA Channel source
00135     and destination addresses, incrementation and data sizes, transfer direction,
00136     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
00137     [..]
00138     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00139     reference manual.
00140
00141 @endverbatim
00142   * @{
00143   */
00144
00145 /**
00146   * @brief Initialize the DMA according to the specified
00147   *        parameters in the DMA_InitTypeDef and initialize the associated handle.
00148   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00149   *             the configuration information for the specified DMA Channel.
00150   * @retval HAL status
00151   */
00152 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00153 {
00154   /* Check the DMA handle allocation */
00155   if (hdma == NULL)
00156   {
00157     return HAL_ERROR;
00158   }
00159
00160   /* Check the parameters */
00161   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00162   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00163   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00164   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00165   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00166   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00167   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00168   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00169
00170   assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
00171
00172   /* Compute the channel index */
00173 #if defined(DMA2)
00174   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00175   {
00176     /* DMA1 */
00177     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00178     hdma->DmaBaseAddress = DMA1;
00179   }
00180   else
00181   {
00182     /* DMA2 */
00183     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
00184     hdma->DmaBaseAddress = DMA2;
00185   }
00186 #else
00187   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00188 #endif /* DMA2 */
00189
00190   /* Change DMA peripheral state */
00191   hdma->State = HAL_DMA_STATE_BUSY;
00192
00193   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
00194   CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
00195                                   DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
00196                                   DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
00197
00198   /* Set the DMA Channel configuration */
00199   SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction           |                               \
00200                                 hdma->Init.PeriphInc           | hdma->Init.MemInc           | \
00201                                 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \
00202                                 hdma->Init.Mode                | hdma->Init.Priority));
00203
00204   /* Initialize parameters for DMAMUX channel :
00205      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
00206   */
00207   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00208
00209   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
00210   {
00211     /* if memory to memory force the request to 0*/
00212     hdma->Init.Request = DMA_REQUEST_MEM2MEM;
00213   }
00214
00215   /* Set peripheral request  to DMAMUX channel */
00216   hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
00217
00218   /* Clear the DMAMUX synchro overrun flag */
00219   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00220
00221   if (((hdma->Init.Request >  0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
00222   {
00223     /* Initialize parameters for DMAMUX request generator :
00224        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
00225     */
00226     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00227
00228     /* Reset the DMAMUX request generator register*/
00229     hdma->DMAmuxRequestGen->RGCR = 0U;
00230
00231     /* Clear the DMAMUX request generator overrun flag */
00232     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00233   }
00234   else
00235   {
00236     hdma->DMAmuxRequestGen = 0U;
00237     hdma->DMAmuxRequestGenStatus = 0U;
00238     hdma->DMAmuxRequestGenStatusMask = 0U;
00239   }
00240
00241   /* Initialize the error code */
00242   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00243
00244   /* Initialize the DMA state*/
00245   hdma->State = HAL_DMA_STATE_READY;
00246
00247   /* Release Lock */
00248   __HAL_UNLOCK(hdma);
00249
00250   return HAL_OK;
00251 }
00252
00253 /**
00254   * @brief DeInitialize the DMA peripheral.
00255   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00256   *             the configuration information for the specified DMA Channel.
00257   * @retval HAL status
00258   */
00259 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00260 {
00261   /* Check the DMA handle allocation */
00262   if (NULL == hdma)
00263   {
00264     return HAL_ERROR;
00265   }
00266
00267   /* Check the parameters */
00268   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00269
00270   /* Disable the selected DMA Channelx */
00271   __HAL_DMA_DISABLE(hdma);
00272
00273   /* Compute the channel index */
00274 #if defined(DMA2)
00275   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00276   {
00277     /* DMA1 */
00278     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00279     hdma->DmaBaseAddress = DMA1;
00280   }
00281   else
00282   {
00283     /* DMA2 */
00284     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
00285     hdma->DmaBaseAddress = DMA2;
00286   }
00287 #else
00288   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00289 #endif /* DMA2 */
00290
00291   /* Reset DMA Channel control register */
00292   hdma->Instance->CCR = 0U;
00293
00294   /* Clear all flags */
00295 #if defined(DMA2)
00296   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
00297 #else
00298   __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
00299 #endif /* DMA2 */
00300
00301   /* Initialize parameters for DMAMUX channel :
00302      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
00303
00304   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00305
00306   /* Reset the DMAMUX channel that corresponds to the DMA channel */
00307   hdma->DMAmuxChannel->CCR = 0U;
00308
00309   /* Clear the DMAMUX synchro overrun flag */
00310   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00311
00312   /* Reset Request generator parameters if any */
00313   if (((hdma->Init.Request >  0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
00314   {
00315     /* Initialize parameters for DMAMUX request generator :
00316        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
00317     */
00318     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00319
00320     /* Reset the DMAMUX request generator register*/
00321     hdma->DMAmuxRequestGen->RGCR = 0U;
00322
00323     /* Clear the DMAMUX request generator overrun flag */
00324     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00325   }
00326
00327   hdma->DMAmuxRequestGen = 0U;
00328   hdma->DMAmuxRequestGenStatus = 0U;
00329   hdma->DMAmuxRequestGenStatusMask = 0U;
00330
00331   /* Clean callbacks */
00332   hdma->XferCpltCallback = NULL;
00333   hdma->XferHalfCpltCallback = NULL;
00334   hdma->XferErrorCallback = NULL;
00335   hdma->XferAbortCallback = NULL;
00336
00337   /* Initialize the error code */
00338   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00339
00340   /* Initialize the DMA state */
00341   hdma->State = HAL_DMA_STATE_RESET;
00342
00343   /* Release Lock */
00344   __HAL_UNLOCK(hdma);
00345
00346   return HAL_OK;
00347 }
00348
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
00354   *  @brief   Input and Output operation functions
00355   *
00356 @verbatim
00357  ===============================================================================
00358                       #####  IO operation functions  #####
00359  ===============================================================================
00360     [..]  This section provides functions allowing to:
00361       (+) Configure the source, destination address and data length and Start DMA transfer
00362       (+) Configure the source, destination address and data length and
00363           Start DMA transfer with interrupt
00364       (+) Abort DMA transfer
00365       (+) Poll for transfer complete
00366       (+) Handle DMA interrupt request
00367       (+) Register and Unregister DMA callbacks
00368
00369 @endverbatim
00370   * @{
00371   */
00372
00373 /**
00374   * @brief Start the DMA Transfer.
00375   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00376   *             the configuration information for the specified DMA Channel.
00377   * @param SrcAddress The source memory Buffer address
00378   * @param DstAddress The destination memory Buffer address
00379   * @param DataLength The length of data to be transferred from source to destination
00380   * @retval HAL status
00381   */
00382 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00383 {
00384   HAL_StatusTypeDef status = HAL_OK;
00385
00386   /* Check the parameters */
00387   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00388
00389   /* Process locked */
00390   __HAL_LOCK(hdma);
00391
00392   if (hdma->State == HAL_DMA_STATE_READY)
00393   {
00394     /* Change DMA peripheral state */
00395     hdma->State = HAL_DMA_STATE_BUSY;
00396
00397     /* Initialize the error code */
00398     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00399
00400     /* Disable the peripheral */
00401     __HAL_DMA_DISABLE(hdma);
00402
00403     /* Configure the source, destination address and the data length & clear flags*/
00404     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00405
00406     /* Enable the Peripheral */
00407     __HAL_DMA_ENABLE(hdma);
00408   }
00409   else
00410   {
00411     /* Change the error code */
00412     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00413
00414     /* Process Unlocked */
00415     __HAL_UNLOCK(hdma);
00416
00417     /* Return error status */
00418     status = HAL_ERROR;
00419   }
00420
00421   return status;
00422 }
00423
00424 /**
00425   * @brief Start the DMA Transfer with interrupt enabled.
00426   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00427   *             the configuration information for the specified DMA Channel.
00428   * @param SrcAddress The source memory Buffer address
00429   * @param DstAddress The destination memory Buffer address
00430   * @param DataLength The length of data to be transferred from source to destination
00431   * @retval HAL status
00432   */
00433 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
00434                                    uint32_t DataLength)
00435 {
00436   HAL_StatusTypeDef status = HAL_OK;
00437
00438   /* Check the parameters */
00439   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00440
00441   /* Process locked */
00442   __HAL_LOCK(hdma);
00443
00444   if (hdma->State == HAL_DMA_STATE_READY)
00445   {
00446     /* Change DMA peripheral state */
00447     hdma->State = HAL_DMA_STATE_BUSY;
00448     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00449
00450     /* Disable the peripheral */
00451     __HAL_DMA_DISABLE(hdma);
00452
00453     /* Configure the source, destination address and the data length & clear flags*/
00454     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00455
00456     /* Enable the transfer complete interrupt */
00457     /* Enable the transfer Error interrupt */
00458     if (NULL != hdma->XferHalfCpltCallback)
00459     {
00460       /* Enable the Half transfer complete interrupt as well */
00461       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00462     }
00463     else
00464     {
00465       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00466       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
00467     }
00468
00469     /* Check if DMAMUX Synchronization is enabled*/
00470     if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
00471     {
00472       /* Enable DMAMUX sync overrun IT*/
00473       hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
00474     }
00475
00476     if (hdma->DMAmuxRequestGen != 0U)
00477     {
00478       /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
00479       /* enable the request gen overrun IT*/
00480       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00481     }
00482
00483     /* Enable the Peripheral */
00484     __HAL_DMA_ENABLE(hdma);
00485   }
00486   else
00487   {
00488     /* Change the error code */
00489     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00490
00491     /* Process Unlocked */
00492     __HAL_UNLOCK(hdma);
00493
00494     /* Return error status */
00495     status = HAL_ERROR;
00496   }
00497
00498   return status;
00499 }
00500
00501 /**
00502   * @brief Abort the DMA Transfer.
00503   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00504   *             the configuration information for the specified DMA Channel.
00505   * @retval HAL status
00506   */
00507 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00508 {
00509   /* Check the DMA peripheral handle */
00510   if (NULL == hdma)
00511   {
00512     return HAL_ERROR;
00513   }
00514
00515   /* Check the DMA peripheral state */
00516   if (hdma->State != HAL_DMA_STATE_BUSY)
00517   {
00518     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00519
00520     /* Process Unlocked */
00521     __HAL_UNLOCK(hdma);
00522
00523     return HAL_ERROR;
00524   }
00525   else
00526   {
00527     /* Disable DMA IT */
00528     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00529
00530     /* disable the DMAMUX sync overrun IT*/
00531     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00532
00533     /* Disable the channel */
00534     __HAL_DMA_DISABLE(hdma);
00535
00536     /* Clear all flags */
00537 #if defined(DMA2)
00538     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
00539 #else
00540     __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex  & 0x1CU)));
00541 #endif /* DMA2 */
00542
00543     /* Clear the DMAMUX synchro overrun flag */
00544     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00545
00546     if (hdma->DMAmuxRequestGen != 0U)
00547     {
00548       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00549       /* disable the request gen overrun IT*/
00550       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00551
00552       /* Clear the DMAMUX request generator overrun flag */
00553       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00554     }
00555
00556     /* Change the DMA state */
00557     hdma->State = HAL_DMA_STATE_READY;
00558
00559     /* Process Unlocked */
00560     __HAL_UNLOCK(hdma);
00561   }
00562
00563   return HAL_OK;
00564 }
00565
00566 /**
00567   * @brief Aborts the DMA Transfer in Interrupt mode.
00568   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00569   *             the configuration information for the specified DMA Channel.
00570   * @retval HAL status
00571   */
00572 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
00573 {
00574   HAL_StatusTypeDef status = HAL_OK;
00575
00576   if (hdma->State != HAL_DMA_STATE_BUSY)
00577   {
00578     /* no transfer ongoing */
00579     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00580
00581     status = HAL_ERROR;
00582   }
00583   else
00584   {
00585     /* Disable DMA IT */
00586     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00587
00588     /* Disable the channel */
00589     __HAL_DMA_DISABLE(hdma);
00590
00591     /* disable the DMAMUX sync overrun IT*/
00592     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00593
00594     /* Clear all flags */
00595 #if defined(DMA2)
00596     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
00597 #else
00598     __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
00599 #endif /* DMA2 */
00600
00601     /* Clear the DMAMUX synchro overrun flag */
00602     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00603
00604     if (hdma->DMAmuxRequestGen != 0U)
00605     {
00606       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00607       /* disable the request gen overrun IT*/
00608       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00609
00610       /* Clear the DMAMUX request generator overrun flag */
00611       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00612     }
00613
00614     /* Change the DMA state */
00615     hdma->State = HAL_DMA_STATE_READY;
00616
00617     /* Process Unlocked */
00618     __HAL_UNLOCK(hdma);
00619
00620     /* Call User Abort callback */
00621     if (hdma->XferAbortCallback != NULL)
00622     {
00623       hdma->XferAbortCallback(hdma);
00624     }
00625   }
00626   return status;
00627 }
00628
00629 /**
00630   * @brief Polling for transfer complete.
00631   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00632   *             the configuration information for the specified DMA Channel.
00633   * @param CompleteLevel Specifies the DMA level complete.
00634   * @param Timeout Timeout duration.
00635   * @retval HAL status
00636   */
00637 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
00638                                           uint32_t Timeout)
00639 {
00640   uint32_t temp;
00641   uint32_t tickstart;
00642
00643   if (hdma->State != HAL_DMA_STATE_BUSY)
00644   {
00645     /* no transfer ongoing */
00646     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00647     __HAL_UNLOCK(hdma);
00648     return HAL_ERROR;
00649   }
00650
00651   /* Polling mode not supported in circular mode */
00652   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
00653   {
00654     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00655     return HAL_ERROR;
00656   }
00657
00658   /* Get the level transfer complete flag */
00659   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
00660   {
00661     /* Transfer Complete flag */
00662     temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
00663   }
00664   else
00665   {
00666     /* Half Transfer Complete flag */
00667     temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
00668   }
00669
00670   /* Get tick */
00671   tickstart = HAL_GetTick();
00672
00673 #if defined(DMA2)
00674   while ((hdma->DmaBaseAddress->ISR & temp) == 0U)
00675   {
00676     if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U)
00677     {
00678       /* When a DMA transfer error occurs */
00679       /* A hardware clear of its EN bits is performed */
00680       /* Clear all flags */
00681       hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
00682
00683       /* Update error code */
00684       hdma->ErrorCode = HAL_DMA_ERROR_TE;
00685
00686       /* Change the DMA state */
00687       hdma->State = HAL_DMA_STATE_READY;
00688
00689       /* Process Unlocked */
00690       __HAL_UNLOCK(hdma);
00691
00692       return HAL_ERROR;
00693     }
00694 #else
00695   while (0U == __HAL_DMA_GET_FLAG(hdma, temp))
00696   {
00697     if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))))
00698     {
00699       /* When a DMA transfer error occurs */
00700       /* A hardware clear of its EN bits is performed */
00701       /* Clear all flags */
00702       __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
00703
00704       /* Update error code */
00705       hdma->ErrorCode = HAL_DMA_ERROR_TE;
00706
00707       /* Change the DMA state */
00708       hdma->State = HAL_DMA_STATE_READY;
00709
00710       /* Process Unlocked */
00711       __HAL_UNLOCK(hdma);
00712
00713       return HAL_ERROR;
00714     }
00715 #endif /* DMA2 */
00716     /* Check for the Timeout */
00717     if (Timeout != HAL_MAX_DELAY)
00718     {
00719       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00720       {
00721         /* Update error code */
00722         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00723
00724         /* Change the DMA state */
00725         hdma->State = HAL_DMA_STATE_READY;
00726
00727         /* Process Unlocked */
00728         __HAL_UNLOCK(hdma);
00729
00730         return HAL_ERROR;
00731       }
00732     }
00733   }
00734
00735   /*Check for DMAMUX Request generator (if used) overrun status */
00736   if (hdma->DMAmuxRequestGen != 0U)
00737   {
00738     /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
00739     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
00740     {
00741       /* Disable the request gen overrun interrupt */
00742       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00743
00744       /* Clear the DMAMUX request generator overrun flag */
00745       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00746
00747       /* Update error code */
00748       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
00749     }
00750   }
00751
00752   /* Check for DMAMUX Synchronization overrun */
00753   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
00754   {
00755     /* Clear the DMAMUX synchro overrun flag */
00756     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00757
00758     /* Update error code */
00759     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
00760   }
00761
00762   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
00763   {
00764     /* Clear the transfer complete flag */
00765 #if defined(DMA2)
00766     hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
00767 #else
00768     __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
00769 #endif /* DMA2 */
00770
00771     /* Process unlocked */
00772     __HAL_UNLOCK(hdma);
00773
00774     /* The selected Channelx EN bit is cleared (DMA is disabled and
00775     all transfers are complete) */
00776     hdma->State = HAL_DMA_STATE_READY;
00777   }
00778   else
00779   {
00780     /* Clear the half transfer complete flag */
00781 #if defined(DMA2)
00782     hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
00783 #else
00784     __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
00785 #endif /* DMA2 */
00786   }
00787
00788   return HAL_OK;
00789 }
00790
00791 /**
00792   * @brief Handle DMA interrupt request.
00793   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00794   *             the configuration information for the specified DMA Channel.
00795   * @retval None
00796   */
00797 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
00798 {
00799 #if defined(DMA2)
00800   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
00801 #else
00802   uint32_t flag_it = DMA1->ISR;
00803 #endif /* DMA2 */
00804   uint32_t source_it = hdma->Instance->CCR;
00805
00806   /* Half Transfer Complete Interrupt management ******************************/
00807   if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
00808   {
00809       /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
00810       if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00811       {
00812         /* Disable the half transfer interrupt */
00813         __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00814       }
00815       /* Clear the half transfer complete flag */
00816 #if defined(DMA2)
00817       hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
00818 #else
00819       __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
00820 #endif /* DMA2 */
00821
00822       /* DMA peripheral state is not updated in Half Transfer */
00823       /* but in Transfer Complete case */
00824
00825       if (hdma->XferHalfCpltCallback != NULL)
00826       {
00827         /* Half transfer callback */
00828         hdma->XferHalfCpltCallback(hdma);
00829       }
00830   }
00831
00832   /* Transfer Complete Interrupt management ***********************************/
00833   else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC)))
00834   {
00835       if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00836       {
00837         /* Disable the transfer complete and error interrupt */
00838         __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
00839
00840         /* Change the DMA state */
00841         hdma->State = HAL_DMA_STATE_READY;
00842       }
00843       /* Clear the transfer complete flag */
00844       __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
00845
00846       /* Process Unlocked */
00847       __HAL_UNLOCK(hdma);
00848
00849       if (hdma->XferCpltCallback != NULL)
00850       {
00851         /* Transfer complete callback */
00852         hdma->XferCpltCallback(hdma);
00853       }
00854   }
00855
00856   /* Transfer Error Interrupt management **************************************/
00857   else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
00858   {
00859     /* When a DMA transfer error occurs */
00860     /* A hardware clear of its EN bits is performed */
00861     /* Disable ALL DMA IT */
00862     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00863
00864     /* Clear all flags */
00865 #if defined(DMA2)
00866     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
00867 #else
00868     __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
00869 #endif /* DMA2 */
00870
00871     /* Update error code */
00872     hdma->ErrorCode = HAL_DMA_ERROR_TE;
00873
00874     /* Change the DMA state */
00875     hdma->State = HAL_DMA_STATE_READY;
00876
00877     /* Process Unlocked */
00878     __HAL_UNLOCK(hdma);
00879
00880     if (hdma->XferErrorCallback != NULL)
00881     {
00882       /* Transfer error callback */
00883       hdma->XferErrorCallback(hdma);
00884     }
00885   }
00886   else
00887   {
00888     /* Nothing To Do */
00889   }
00890   return;
00891 }
00892
00893 /**
00894   * @brief Register callbacks
00895   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00896   *             the configuration information for the specified DMA Channel.
00897   * @param CallbackID User Callback identifier
00898   *                   a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00899   * @param pCallback Pointer to private callback function which has pointer to
00900   *                  a DMA_HandleTypeDef structure as parameter.
00901   * @retval HAL status
00902   */
00903 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
00904 {
00905   HAL_StatusTypeDef status = HAL_OK;
00906
00907   /* Process locked */
00908   __HAL_LOCK(hdma);
00909
00910   if (hdma->State == HAL_DMA_STATE_READY)
00911   {
00912     switch (CallbackID)
00913     {
00914       case  HAL_DMA_XFER_CPLT_CB_ID:
00915         hdma->XferCpltCallback = pCallback;
00916         break;
00917
00918       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00919         hdma->XferHalfCpltCallback = pCallback;
00920         break;
00921
00922       case  HAL_DMA_XFER_ERROR_CB_ID:
00923         hdma->XferErrorCallback = pCallback;
00924         break;
00925
00926       case  HAL_DMA_XFER_ABORT_CB_ID:
00927         hdma->XferAbortCallback = pCallback;
00928         break;
00929
00930       default:
00931         status = HAL_ERROR;
00932         break;
00933     }
00934   }
00935   else
00936   {
00937     status = HAL_ERROR;
00938   }
00939
00940   /* Release Lock */
00941   __HAL_UNLOCK(hdma);
00942
00943   return status;
00944 }
00945
00946 /**
00947   * @brief UnRegister callbacks
00948   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00949   *             the configuration information for the specified DMA Channel.
00950   * @param CallbackID User Callback identifier
00951   *                   a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00952   * @retval HAL status
00953   */
00954 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
00955 {
00956   HAL_StatusTypeDef status = HAL_OK;
00957
00958   /* Process locked */
00959   __HAL_LOCK(hdma);
00960
00961   if (hdma->State == HAL_DMA_STATE_READY)
00962   {
00963     switch (CallbackID)
00964     {
00965       case  HAL_DMA_XFER_CPLT_CB_ID:
00966         hdma->XferCpltCallback = NULL;
00967         break;
00968
00969       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00970         hdma->XferHalfCpltCallback = NULL;
00971         break;
00972
00973       case  HAL_DMA_XFER_ERROR_CB_ID:
00974         hdma->XferErrorCallback = NULL;
00975         break;
00976
00977       case  HAL_DMA_XFER_ABORT_CB_ID:
00978         hdma->XferAbortCallback = NULL;
00979         break;
00980
00981       case   HAL_DMA_XFER_ALL_CB_ID:
00982         hdma->XferCpltCallback = NULL;
00983         hdma->XferHalfCpltCallback = NULL;
00984         hdma->XferErrorCallback = NULL;
00985         hdma->XferAbortCallback = NULL;
00986         break;
00987
00988       default:
00989         status = HAL_ERROR;
00990         break;
00991     }
00992   }
00993   else
00994   {
00995     status = HAL_ERROR;
00996   }
00997
00998   /* Release Lock */
00999   __HAL_UNLOCK(hdma);
01000
01001   return status;
01002 }
01003
01004 /**
01005   * @}
01006   */
01007
01008
01009
01010 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
01011   *  @brief    Peripheral State and Errors functions
01012   *
01013 @verbatim
01014  ===============================================================================
01015             ##### Peripheral State and Errors functions #####
01016  ===============================================================================
01017     [..]
01018     This subsection provides functions allowing to
01019       (+) Check the DMA state
01020       (+) Get error code
01021
01022 @endverbatim
01023   * @{
01024   */
01025
01026 /**
01027   * @brief Return the DMA handle state.
01028   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
01029   *             the configuration information for the specified DMA Channel.
01030   * @retval HAL state
01031   */
01032 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
01033 {
01034   /* Return DMA handle state */
01035   return hdma->State;
01036 }
01037
01038 /**
01039   * @brief Return the DMA error code.
01040   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
01041   *             the configuration information for the specified DMA Channel.
01042   * @retval DMA Error Code
01043   */
01044 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
01045 {
01046   /* Return the DMA error code */
01047   return hdma->ErrorCode;
01048 }
01049
01050 /**
01051   * @}
01052   */
01053
01054 /**
01055   * @}
01056   */
01057
01058 /** @addtogroup DMA_Private_Functions
01059   * @{
01060   */
01061
01062 /**
01063   * @brief Sets the DMA Transfer parameter.
01064   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
01065   *             the configuration information for the specified DMA Channel.
01066   * @param SrcAddress The source memory Buffer address
01067   * @param DstAddress The destination memory Buffer address
01068   * @param DataLength The length of data to be transferred from source to destination
01069   * @retval HAL status
01070   */
01071 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
01072 {
01073   /* Clear the DMAMUX synchro overrun flag */
01074   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
01075
01076   if (hdma->DMAmuxRequestGen != 0U)
01077   {
01078     /* Clear the DMAMUX request generator overrun flag */
01079     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
01080   }
01081
01082   /* Clear all flags */
01083 #if defined(DMA2)
01084   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
01085 #else
01086   __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
01087 #endif /* DMA2 */
01088
01089   /* Configure DMA Channel data length */
01090   hdma->Instance->CNDTR = DataLength;
01091
01092   /* Memory to Peripheral */
01093   if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
01094   {
01095     /* Configure DMA Channel destination address */
01096     hdma->Instance->CPAR = DstAddress;
01097
01098     /* Configure DMA Channel source address */
01099     hdma->Instance->CMAR = SrcAddress;
01100   }
01101   /* Peripheral to Memory */
01102   else
01103   {
01104     /* Configure DMA Channel source address */
01105     hdma->Instance->CPAR = SrcAddress;
01106
01107     /* Configure DMA Channel destination address */
01108     hdma->Instance->CMAR = DstAddress;
01109   }
01110 }
01111
01112 /**
01113   * @brief Updates the DMA handle with the DMAMUX  channel and status mask depending on channel number
01114   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
01115   *             the configuration information for the specified DMA Channel.
01116   * @retval None
01117   */
01118 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
01119 {
01120   uint32_t channel_number;
01121
01122 #if defined(DMA2)
01123   /* check if instance is not outside the DMA channel range */
01124   if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
01125   {
01126     /* DMA1 */
01127     /* Associate a DMA Channel to a DMAMUX channel */
01128     hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
01129
01130     /* Prepare channel_number used for DMAmuxChannelStatusMask computation */
01131     channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
01132   }
01133   else
01134   {
01135     /* DMA2 */
01136     /* Associate a DMA Channel to a DMAMUX channel */
01137     hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
01138
01139     /* Prepare channel_number used for DMAmuxChannelStatusMask computation */
01140     channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U);
01141   }
01142 #else
01143   /* Associate a DMA Channel to a DMAMUX channel */
01144   hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
01145
01146   /* Prepare channel_number used for DMAmuxChannelStatusMask computation */
01147   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
01148 #endif /* DMA2 */
01149
01150   /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */
01151   hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
01152
01153   /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */
01154   hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
01155 }
01156
01157 /**
01158   * @brief Updates the DMA handle with the DMAMUX  request generator params
01159   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
01160   *             the configuration information for the specified DMA Channel.
01161   * @retval None
01162   */
01163
01164 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
01165 {
01166   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
01167
01168   /* DMA Channels are connected to DMAMUX1 request generator blocks*/
01169   hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
01170
01171   hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
01172
01173   /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
01174   hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
01175 }
01176
01177 /**
01178   * @}
01179   */
01180
01181 /**
01182   * @}
01183   */
01184
01185 #endif /* HAL_DMA_MODULE_ENABLED */
01186 /**
01187   * @}
01188   */
01189
01190 /**
01191   * @}
01192   */
01193
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dma.h Source File

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stm32g0xx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_DMA_H
00021 #define STM32G0xx_HAL_DMA_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029 #include "stm32g0xx_ll_dma.h"
00030
00031 /** @addtogroup STM32G0xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup DMA
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup DMA_Exported_Types DMA Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  DMA Configuration Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Request;               /*!< Specifies the request selected for the specified channel.
00050                                        This parameter can be a value of @ref DMA_request */
00051
00052   uint32_t Direction;             /*!< Specifies if the data will be transferred from memory to peripheral,
00053                                        from memory to memory or from peripheral to memory.
00054                                        This parameter can be a value of @ref DMA_Data_transfer_direction */
00055
00056   uint32_t PeriphInc;             /*!< Specifies whether the Peripheral address register should be incremented or not.
00057                                        This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
00058
00059   uint32_t MemInc;                /*!< Specifies whether the memory address register should be incremented or not.
00060                                        This parameter can be a value of @ref DMA_Memory_incremented_mode */
00061
00062   uint32_t PeriphDataAlignment;   /*!< Specifies the Peripheral data width.
00063                                        This parameter can be a value of @ref DMA_Peripheral_data_size */
00064
00065   uint32_t MemDataAlignment;      /*!< Specifies the Memory data width.
00066                                        This parameter can be a value of @ref DMA_Memory_data_size */
00067
00068   uint32_t Mode;                  /*!< Specifies the operation mode of the DMAy Channelx.
00069                                        This parameter can be a value of @ref DMA_mode
00070                                        @note The circular buffer mode cannot be used if the memory-to-memory
00071                                              data transfer is configured on the selected Channel */
00072
00073   uint32_t Priority;              /*!< Specifies the software priority for the DMAy Channelx.
00074                                        This parameter can be a value of @ref DMA_Priority_level */
00075 } DMA_InitTypeDef;
00076
00077 /**
00078   * @brief  HAL DMA State structures definition
00079   */
00080 typedef enum
00081 {
00082   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
00083   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
00084   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
00085   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
00086 } HAL_DMA_StateTypeDef;
00087
00088 /**
00089   * @brief  HAL DMA Error Code structure definition
00090   */
00091 typedef enum
00092 {
00093   HAL_DMA_FULL_TRANSFER           = 0x00U,  /*!< Full transfer     */
00094   HAL_DMA_HALF_TRANSFER           = 0x01U   /*!< Half Transfer     */
00095 } HAL_DMA_LevelCompleteTypeDef;
00096
00097 /**
00098   * @brief  HAL DMA Callback ID structure definition
00099   */
00100 typedef enum
00101 {
00102   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,  /*!< Full transfer    */
00103   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,  /*!< Half transfer    */
00104   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,  /*!< Error            */
00105   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,  /*!< Abort            */
00106   HAL_DMA_XFER_ALL_CB_ID           = 0x04U   /*!< All              */
00107
00108 } HAL_DMA_CallbackIDTypeDef;
00109
00110 /**
00111   * @brief  DMA handle Structure definition
00112   */
00113 typedef struct __DMA_HandleTypeDef
00114 {
00115   DMA_Channel_TypeDef             *Instance;                          /*!< Register base address                 */
00116
00117   DMA_InitTypeDef                 Init;                               /*!< DMA communication parameters          */
00118
00119   HAL_LockTypeDef                 Lock;                               /*!< DMA locking object                    */
00120
00121   __IO HAL_DMA_StateTypeDef       State;                              /*!< DMA transfer state                    */
00122
00123   void   *Parent;                                                     /*!< Parent object state                   */
00124
00125   void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);        /*!< DMA transfer complete callback        */
00126
00127   void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma);    /*!< DMA Half transfer complete callback   */
00128
00129   void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);       /*!< DMA transfer error callback           */
00130
00131   void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);       /*!< DMA transfer abort callback           */
00132
00133   __IO uint32_t                   ErrorCode;                          /*!< DMA Error code                        */
00134
00135 #if defined(DMA2)
00136   DMA_TypeDef            *DmaBaseAddress;                             /*!< DMA Channel Base Address              */
00137
00138 #endif /* DMA2 */
00139   uint32_t                        ChannelIndex;                       /*!< DMA Channel Index                     */
00140
00141   DMAMUX_Channel_TypeDef           *DMAmuxChannel;                    /*!< Register base address                 */
00142
00143   DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;              /*!< DMAMUX Channels Status Base Address   */
00144
00145   uint32_t                         DMAmuxChannelStatusMask;           /*!< DMAMUX Channel Status Mask            */
00146
00147   DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                 /*!< DMAMUX request generator Base Address */
00148
00149   DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;           /*!< DMAMUX request generator Address      */
00150
00151   uint32_t                         DMAmuxRequestGenStatusMask;        /*!< DMAMUX request generator Status mask  */
00152 } DMA_HandleTypeDef;
00153 /**
00154   * @}
00155   */
00156
00157 /* Exported constants --------------------------------------------------------*/
00158
00159 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00160   * @{
00161   */
00162
00163 /** @defgroup DMA_Error_Code DMA Error Code
00164   * @{
00165   */
00166 #define HAL_DMA_ERROR_NONE           0x00000000U       /*!< No error                                */
00167 #define HAL_DMA_ERROR_TE             0x00000001U       /*!< Transfer error                          */
00168 #define HAL_DMA_ERROR_NO_XFER        0x00000004U       /*!< Abort requested with no Xfer ongoing    */
00169 #define HAL_DMA_ERROR_TIMEOUT        0x00000020U       /*!< Timeout error                           */
00170 #define HAL_DMA_ERROR_PARAM          0x00000040U       /*!< Parameter error                         */
00171 #define HAL_DMA_ERROR_BUSY           0x00000080U       /*!< DMA Busy error                          */
00172 #define HAL_DMA_ERROR_NOT_SUPPORTED  0x00000100U       /*!< Not supported mode                      */
00173 #define HAL_DMA_ERROR_SYNC           0x00000200U       /*!< DMAMUX sync overrun error               */
00174 #define HAL_DMA_ERROR_REQGEN         0x00000400U       /*!< DMAMUX request generator overrun error  */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup DMA_request DMA request
00181   * @{
00182   */
00183 #define DMA_REQUEST_MEM2MEM          LL_DMAMUX_REQ_MEM2MEM        /*!< memory to memory transfer  */
00184 #define DMA_REQUEST_GENERATOR0       LL_DMAMUX_REQ_GENERATOR0     /*!< DMAMUX request generator 0 */
00185 #define DMA_REQUEST_GENERATOR1       LL_DMAMUX_REQ_GENERATOR1     /*!< DMAMUX request generator 1 */
00186 #define DMA_REQUEST_GENERATOR2       LL_DMAMUX_REQ_GENERATOR2     /*!< DMAMUX request generator 2 */
00187 #define DMA_REQUEST_GENERATOR3       LL_DMAMUX_REQ_GENERATOR3     /*!< DMAMUX request generator 3 */
00188 #define DMA_REQUEST_ADC1             LL_DMAMUX_REQ_ADC1           /*!< DMAMUX ADC1 request        */
00189 #if defined(AES)
00190 #define DMA_REQUEST_AES_IN           LL_DMAMUX_REQ_AES_IN         /*!< DMAMUX AES_IN request      */
00191 #define DMA_REQUEST_AES_OUT          LL_DMAMUX_REQ_AES_OUT        /*!< DMAMUX AES_OUT request     */
00192 #endif /* AES */
00193 #if defined(DAC1)
00194 #define DMA_REQUEST_DAC1_CH1         LL_DMAMUX_REQ_DAC1_CH1       /*!< DMAMUX DAC_CH1 request     */
00195 #define DMA_REQUEST_DAC1_CH2         LL_DMAMUX_REQ_DAC1_CH2       /*!< DMAMUX DAC_CH2 request     */
00196 #endif /* DAC1 */
00197 #define DMA_REQUEST_I2C1_RX          LL_DMAMUX_REQ_I2C1_RX        /*!< DMAMUX I2C1 RX request     */
00198 #define DMA_REQUEST_I2C1_TX          LL_DMAMUX_REQ_I2C1_TX        /*!< DMAMUX I2C1 TX request     */
00199 #define DMA_REQUEST_I2C2_RX          LL_DMAMUX_REQ_I2C2_RX        /*!< DMAMUX I2C2 RX request     */
00200 #define DMA_REQUEST_I2C2_TX          LL_DMAMUX_REQ_I2C2_TX        /*!< DMAMUX I2C2 TX request     */
00201 #if defined(LPUART1)
00202 #define DMA_REQUEST_LPUART1_RX       LL_DMAMUX_REQ_LPUART1_RX     /*!< DMAMUX LPUART1 RX request  */
00203 #define DMA_REQUEST_LPUART1_TX       LL_DMAMUX_REQ_LPUART1_TX     /*!< DMAMUX LPUART1 TX request  */
00204 #endif /* LPUART1 */
00205 #define DMA_REQUEST_SPI1_RX          LL_DMAMUX_REQ_SPI1_RX        /*!< DMAMUX SPI1 RX request     */
00206 #define DMA_REQUEST_SPI1_TX          LL_DMAMUX_REQ_SPI1_TX        /*!< DMAMUX SPI1 TX request     */
00207 #define DMA_REQUEST_SPI2_RX          LL_DMAMUX_REQ_SPI2_RX        /*!< DMAMUX SPI2 RX request     */
00208 #define DMA_REQUEST_SPI2_TX          LL_DMAMUX_REQ_SPI2_TX        /*!< DMAMUX SPI2 TX request     */
00209 #define DMA_REQUEST_TIM1_CH1         LL_DMAMUX_REQ_TIM1_CH1       /*!< DMAMUX TIM1 CH1 request    */
00210 #define DMA_REQUEST_TIM1_CH2         LL_DMAMUX_REQ_TIM1_CH2       /*!< DMAMUX TIM1 CH2 request    */
00211 #define DMA_REQUEST_TIM1_CH3         LL_DMAMUX_REQ_TIM1_CH3       /*!< DMAMUX TIM1 CH3 request    */
00212 #define DMA_REQUEST_TIM1_CH4         LL_DMAMUX_REQ_TIM1_CH4       /*!< DMAMUX TIM1 CH4 request    */
00213 #define DMA_REQUEST_TIM1_TRIG_COM    LL_DMAMUX_REQ_TIM1_TRIG_COM  /*!< DMAMUX TIM1 TRIG COM request */
00214 #define DMA_REQUEST_TIM1_UP          LL_DMAMUX_REQ_TIM1_UP        /*!< DMAMUX TIM1 UP request     */
00215 #if defined(TIM2)
00216 #define DMA_REQUEST_TIM2_CH1         LL_DMAMUX_REQ_TIM2_CH1       /*!< DMAMUX TIM2 CH1 request    */
00217 #define DMA_REQUEST_TIM2_CH2         LL_DMAMUX_REQ_TIM2_CH2       /*!< DMAMUX TIM2 CH2 request    */
00218 #define DMA_REQUEST_TIM2_CH3         LL_DMAMUX_REQ_TIM2_CH3       /*!< DMAMUX TIM2 CH3 request    */
00219 #define DMA_REQUEST_TIM2_CH4         LL_DMAMUX_REQ_TIM2_CH4       /*!< DMAMUX TIM2 CH4 request    */
00220 #define DMA_REQUEST_TIM2_TRIG        LL_DMAMUX_REQ_TIM2_TRIG      /*!< DMAMUX TIM2 TRIG request   */
00221 #define DMA_REQUEST_TIM2_UP          LL_DMAMUX_REQ_TIM2_UP        /*!< DMAMUX TIM2 UP request     */
00222 #endif /* TIM2 */
00223 #define DMA_REQUEST_TIM3_CH1         LL_DMAMUX_REQ_TIM3_CH1       /*!< DMAMUX TIM3 CH1 request    */
00224 #define DMA_REQUEST_TIM3_CH2         LL_DMAMUX_REQ_TIM3_CH2       /*!< DMAMUX TIM3 CH2 request    */
00225 #define DMA_REQUEST_TIM3_CH3         LL_DMAMUX_REQ_TIM3_CH3       /*!< DMAMUX TIM3 CH3 request    */
00226 #define DMA_REQUEST_TIM3_CH4         LL_DMAMUX_REQ_TIM3_CH4       /*!< DMAMUX TIM3 CH4 request    */
00227 #define DMA_REQUEST_TIM3_TRIG        LL_DMAMUX_REQ_TIM3_TRIG      /*!< DMAMUX TIM3 TRIG request   */
00228 #define DMA_REQUEST_TIM3_UP          LL_DMAMUX_REQ_TIM3_UP        /*!< DMAMUX TIM3 UP request     */
00229 #if defined(TIM6)
00230 #define DMA_REQUEST_TIM6_UP          LL_DMAMUX_REQ_TIM6_UP        /*!< DMAMUX TIM6 UP request     */
00231 #endif /* TIM6 */
00232 #if defined(TIM7)
00233 #define DMA_REQUEST_TIM7_UP          LL_DMAMUX_REQ_TIM7_UP        /*!< DMAMUX TIM7 UP request     */
00234 #endif /* TIM7 */
00235 #if defined(TIM15)
00236 #define DMA_REQUEST_TIM15_CH1        LL_DMAMUX_REQ_TIM15_CH1      /*!< DMAMUX TIM15 CH1 request   */
00237 #define DMA_REQUEST_TIM15_CH2        LL_DMAMUX_REQ_TIM15_CH2      /*!< DMAMUX TIM15 CH2 request   */
00238 #define DMA_REQUEST_TIM15_TRIG_COM   LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */
00239 #define DMA_REQUEST_TIM15_UP         LL_DMAMUX_REQ_TIM15_UP       /*!< DMAMUX TIM15 UP request    */
00240 #endif /* TIM15 */
00241 #define DMA_REQUEST_TIM16_CH1        LL_DMAMUX_REQ_TIM16_CH1      /*!< DMAMUX TIM16 CH1 request   */
00242 #define DMA_REQUEST_TIM16_COM        LL_DMAMUX_REQ_TIM16_COM      /*!< DMAMUX TIM16 COM request   */
00243 #define DMA_REQUEST_TIM16_UP         LL_DMAMUX_REQ_TIM16_UP       /*!< DMAMUX TIM16 UP request    */
00244 #define DMA_REQUEST_TIM17_CH1        LL_DMAMUX_REQ_TIM17_CH1      /*!< DMAMUX TIM17 CH1 request   */
00245 #define DMA_REQUEST_TIM17_COM        LL_DMAMUX_REQ_TIM17_COM      /*!< DMAMUX TIM17 COM request   */
00246 #define DMA_REQUEST_TIM17_UP         LL_DMAMUX_REQ_TIM17_UP       /*!< DMAMUX TIM17 UP request    */
00247 #define DMA_REQUEST_USART1_RX        LL_DMAMUX_REQ_USART1_RX      /*!< DMAMUX USART1 RX request  */
00248 #define DMA_REQUEST_USART1_TX        LL_DMAMUX_REQ_USART1_TX      /*!< DMAMUX USART1 TX request  */
00249 #define DMA_REQUEST_USART2_RX        LL_DMAMUX_REQ_USART2_RX      /*!< DMAMUX USART2 RX request  */
00250 #define DMA_REQUEST_USART2_TX        LL_DMAMUX_REQ_USART2_TX      /*!< DMAMUX USART2 TX request  */
00251 #if defined(USART3)
00252 #define DMA_REQUEST_USART3_RX        LL_DMAMUX_REQ_USART3_RX      /*!< DMAMUX USART3 RX request  */
00253 #define DMA_REQUEST_USART3_TX        LL_DMAMUX_REQ_USART3_TX      /*!< DMAMUX USART3 TX request  */
00254 #endif /* USART3 */
00255 #if defined(USART4)
00256 #define DMA_REQUEST_USART4_RX        LL_DMAMUX_REQ_USART4_RX      /*!< DMAMUX USART4 RX request  */
00257 #define DMA_REQUEST_USART4_TX        LL_DMAMUX_REQ_USART4_TX      /*!< DMAMUX USART4 TX request  */
00258 #endif /* USART4 */
00259 #if defined(UCPD1)
00260 #define DMA_REQUEST_UCPD1_RX         LL_DMAMUX_REQ_UCPD1_RX       /*!< DMAMUX UCPD1 RX request  */
00261 #define DMA_REQUEST_UCPD1_TX         LL_DMAMUX_REQ_UCPD1_TX       /*!< DMAMUX UCPD1 TX request  */
00262 #endif/* UCPD1 */
00263 #if defined(UCPD2)
00264 #define DMA_REQUEST_UCPD2_RX         LL_DMAMUX_REQ_UCPD2_RX       /*!< DMAMUX UCPD2 RX request  */
00265 #define DMA_REQUEST_UCPD2_TX         LL_DMAMUX_REQ_UCPD2_TX       /*!< DMAMUX UCPD2 TX request  */
00266 #endif /* UCPD2 */
00267
00268 #if defined(I2C3)
00269 #define DMA_REQUEST_I2C3_RX          LL_DMAMUX_REQ_I2C3_RX        /*!< DMAMUX I2C3 RX request  */
00270 #define DMA_REQUEST_I2C3_TX          LL_DMAMUX_REQ_I2C3_TX        /*!< DMAMUX I2C3 TX request  */
00271 #endif /* I2C3 */
00272
00273 #if defined(LPUART2)
00274 #define DMA_REQUEST_LPUART2_RX       LL_DMAMUX_REQ_LPUART2_RX     /*!< DMAMUX LPUART2 RX request  */
00275 #define DMA_REQUEST_LPUART2_TX       LL_DMAMUX_REQ_LPUART2_TX     /*!< DMAMUX LPUART2 TX request  */
00276 #endif /* LPUART2 */
00277
00278 #if defined(SPI3)
00279 #define DMA_REQUEST_SPI3_RX          LL_DMAMUX_REQ_SPI3_RX        /*!< DMAMUX SPI3 RX request     */
00280 #define DMA_REQUEST_SPI3_TX          LL_DMAMUX_REQ_SPI3_TX        /*!< DMAMUX SPI3 TX request     */
00281 #endif /* SPI3 */
00282
00283 #if defined(TIM4)
00284 #define DMA_REQUEST_TIM4_CH1         LL_DMAMUX_REQ_TIM4_CH1       /*!< DMAMUX TIM4 CH1 request    */
00285 #define DMA_REQUEST_TIM4_CH2         LL_DMAMUX_REQ_TIM4_CH2       /*!< DMAMUX TIM4 CH2 request    */
00286 #define DMA_REQUEST_TIM4_CH3         LL_DMAMUX_REQ_TIM4_CH3       /*!< DMAMUX TIM4 CH3 request    */
00287 #define DMA_REQUEST_TIM4_CH4         LL_DMAMUX_REQ_TIM4_CH4       /*!< DMAMUX TIM4 CH4 request    */
00288 #define DMA_REQUEST_TIM4_TRIG        LL_DMAMUX_REQ_TIM4_TRIG      /*!< DMAMUX TIM4 TRIG request   */
00289 #define DMA_REQUEST_TIM4_UP          LL_DMAMUX_REQ_TIM4_UP        /*!< DMAMUX TIM4 UP request     */
00290 #endif /* TIM4 */
00291
00292 #if defined(USART5)
00293 #define DMA_REQUEST_USART5_RX        LL_DMAMUX_REQ_USART5_RX      /*!< DMAMUX USART5 RX request  */
00294 #define DMA_REQUEST_USART5_TX        LL_DMAMUX_REQ_USART5_TX      /*!< DMAMUX USART5 TX request  */
00295 #endif /* USART5 */
00296
00297 #if defined(USART6)
00298 #define DMA_REQUEST_USART6_RX        LL_DMAMUX_REQ_USART6_RX      /*!< DMAMUX USART6 RX request  */
00299 #define DMA_REQUEST_USART6_TX        LL_DMAMUX_REQ_USART6_TX      /*!< DMAMUX USART6 TX request  */
00300 #endif /* USART6 */
00301
00302
00303 #define DMA_MAX_REQUEST              LL_DMAMUX_MAX_REQ
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00309   * @{
00310   */
00311 #define DMA_PERIPH_TO_MEMORY         LL_DMA_DIRECTION_PERIPH_TO_MEMORY  /*!< Peripheral to memory direction */
00312 #define DMA_MEMORY_TO_PERIPH         LL_DMA_DIRECTION_MEMORY_TO_PERIPH  /*!< Memory to peripheral direction */
00313 #define DMA_MEMORY_TO_MEMORY         LL_DMA_DIRECTION_MEMORY_TO_MEMORY  /*!< Memory to memory direction     */
00314
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00320   * @{
00321   */
00322 #define DMA_PINC_ENABLE              LL_DMA_PERIPH_INCREMENT            /*!< Peripheral increment mode Enable  */
00323 #define DMA_PINC_DISABLE             LL_DMA_PERIPH_NOINCREMENT          /*!< Peripheral increment mode Disable */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00329   * @{
00330   */
00331 #define DMA_MINC_ENABLE              LL_DMA_MEMORY_INCREMENT            /*!< Memory increment mode Enable  */
00332 #define DMA_MINC_DISABLE             LL_DMA_MEMORY_NOINCREMENT          /*!< Memory increment mode Disable */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00338   * @{
00339   */
00340 #define DMA_PDATAALIGN_BYTE          LL_DMA_PDATAALIGN_BYTE             /*!< Peripheral data alignment : Byte     */
00341 #define DMA_PDATAALIGN_HALFWORD      LL_DMA_PDATAALIGN_HALFWORD         /*!< Peripheral data alignment : HalfWord */
00342 #define DMA_PDATAALIGN_WORD          LL_DMA_PDATAALIGN_WORD             /*!< Peripheral data alignment : Word     */
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup DMA_Memory_data_size DMA Memory data size
00348   * @{
00349   */
00350 #define DMA_MDATAALIGN_BYTE          LL_DMA_MDATAALIGN_BYTE             /*!< Memory data alignment : Byte     */
00351 #define DMA_MDATAALIGN_HALFWORD      LL_DMA_MDATAALIGN_HALFWORD         /*!< Memory data alignment : HalfWord */
00352 #define DMA_MDATAALIGN_WORD          LL_DMA_MDATAALIGN_WORD             /*!< Memory data alignment : Word     */
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup DMA_mode DMA mode
00358   * @{
00359   */
00360 #define DMA_NORMAL                   LL_DMA_MODE_NORMAL                 /*!< Normal mode    */
00361 #define DMA_CIRCULAR                 LL_DMA_MODE_CIRCULAR               /*!< Circular mode  */
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup DMA_Priority_level DMA Priority level
00367   * @{
00368   */
00369 #define DMA_PRIORITY_LOW             LL_DMA_PRIORITY_LOW                /*!< Priority level : Low       */
00370 #define DMA_PRIORITY_MEDIUM          LL_DMA_PRIORITY_MEDIUM             /*!< Priority level : Medium    */
00371 #define DMA_PRIORITY_HIGH            LL_DMA_PRIORITY_HIGH               /*!< Priority level : High      */
00372 #define DMA_PRIORITY_VERY_HIGH       LL_DMA_PRIORITY_VERYHIGH           /*!< Priority level : Very_High */
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00378   * @{
00379   */
00380 #define DMA_IT_TC                    DMA_CCR_TCIE                       /*!< Transfer Complete interrupt      */
00381 #define DMA_IT_HT                    DMA_CCR_HTIE                       /*!< Half Transfer Complete interrupt */
00382 #define DMA_IT_TE                    DMA_CCR_TEIE                       /*!< Transfer Error interrupt         */
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup DMA_flag_definitions DMA flag definitions
00388   * @{
00389   */
00390
00391 #define DMA_FLAG_GI1                 DMA_ISR_GIF1                       /*!< Global Interrupt flag for Channel 1  */
00392 #define DMA_FLAG_TC1                 DMA_ISR_TCIF1                      /*!< Transfer Complete flag for Channel 1 */
00393 #define DMA_FLAG_HT1                 DMA_ISR_HTIF1                      /*!< Half Transfer flag for Channel 1     */
00394 #define DMA_FLAG_TE1                 DMA_ISR_TEIF1                      /*!< Transfer Error flag for Channel 1    */
00395 #define DMA_FLAG_GI2                 DMA_ISR_GIF2                       /*!< Global Interrupt flag for Channel 2  */
00396 #define DMA_FLAG_TC2                 DMA_ISR_TCIF2                      /*!< Transfer Complete flag for Channel 2 */
00397 #define DMA_FLAG_HT2                 DMA_ISR_HTIF2                      /*!< Half Transfer flag for Channel 2     */
00398 #define DMA_FLAG_TE2                 DMA_ISR_TEIF2                      /*!< Transfer Error flag for Channel 2    */
00399 #define DMA_FLAG_GI3                 DMA_ISR_GIF3                       /*!< Global Interrupt flag for Channel 3  */
00400 #define DMA_FLAG_TC3                 DMA_ISR_TCIF3                      /*!< Transfer Complete flag for Channel 3 */
00401 #define DMA_FLAG_HT3                 DMA_ISR_HTIF3                      /*!< Half Transfer flag for Channel 3     */
00402 #define DMA_FLAG_TE3                 DMA_ISR_TEIF3                      /*!< Transfer Error flag for Channel 3    */
00403 #define DMA_FLAG_GI4                 DMA_ISR_GIF4                       /*!< Global Interrupt flag for Channel 4  */
00404 #define DMA_FLAG_TC4                 DMA_ISR_TCIF4                      /*!< Transfer Complete flag for Channel 4 */
00405 #define DMA_FLAG_HT4                 DMA_ISR_HTIF4                      /*!< Half Transfer flag for Channel 4     */
00406 #define DMA_FLAG_TE4                 DMA_ISR_TEIF4                      /*!< Transfer Error flag for Channel 4    */
00407 #define DMA_FLAG_GI5                 DMA_ISR_GIF5                       /*!< Global Interrupt flag for Channel 5  */
00408 #define DMA_FLAG_TC5                 DMA_ISR_TCIF5                      /*!< Transfer Complete flag for Channel 5 */
00409 #define DMA_FLAG_HT5                 DMA_ISR_HTIF5                      /*!< Half Transfer flag for Channel 5     */
00410 #define DMA_FLAG_TE5                 DMA_ISR_TEIF5                      /*!< Transfer Error for Channel 5         */
00411 #if defined(DMA1_Channel6)
00412 #define DMA_FLAG_GI6                 DMA_ISR_GIF6                       /*!< Global Interrupt flag for Channel 6  */
00413 #define DMA_FLAG_TC6                 DMA_ISR_TCIF6                      /*!< Transfer Complete flag for Channel 6 */
00414 #define DMA_FLAG_HT6                 DMA_ISR_HTIF6                      /*!< Half Transfer flag for Channel 6     */
00415 #define DMA_FLAG_TE6                 DMA_ISR_TEIF6                      /*!< Transfer Error flag for Channel 6    */
00416 #endif /* DMA1_Channel6 */
00417 #if defined(DMA1_Channel7)
00418 #define DMA_FLAG_GI7                 DMA_ISR_GIF7                       /*!< Global Interrupt flag for Channel 7  */
00419 #define DMA_FLAG_TC7                 DMA_ISR_TCIF7                      /*!< Transfer Complete flag for Channel 7 */
00420 #define DMA_FLAG_HT7                 DMA_ISR_HTIF7                      /*!< Half Transfer flag for Channel 7     */
00421 #define DMA_FLAG_TE7                 DMA_ISR_TEIF7                      /*!< Transfer Error flag for Channel 7    */
00422 #endif /* DMA1_Channel7 */
00423 /**
00424   * @}
00425   */
00426
00427 /**
00428   * @}
00429   */
00430
00431 /* Exported macros -----------------------------------------------------------*/
00432 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00433   * @{
00434   */
00435
00436 /** @brief  Reset DMA handle state
00437   * @param __HANDLE__ DMA handle
00438   * @retval None
00439   */
00440 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00441
00442 /**
00443   * @brief  Enable the specified DMA Channel.
00444   * @param __HANDLE__ DMA handle
00445   * @retval None
00446   */
00447 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
00448
00449 /**
00450   * @brief  Disable the specified DMA Channel.
00451   * @param __HANDLE__ DMA handle
00452   * @retval None
00453   */
00454 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
00455
00456 /**
00457   * @brief  Return the current DMA Channel transfer complete flag.
00458   * @param __HANDLE__ DMA handle
00459   * @retval The specified transfer complete flag index.
00460   */
00461 #if defined(DMA2)
00462 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00464  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
00465  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00466  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
00467  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00468  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
00469  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00470  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
00471  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00472  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
00473  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00474    DMA_FLAG_TC7)
00475 #else /* DMA1 */
00476 #if   defined(DMA1_Channel7)
00477 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00478 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00481  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00482  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00483  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00484    DMA_FLAG_TC7)
00485 #else
00486 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00487 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00488  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00489  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00490  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00491    DMA_FLAG_TC5)
00492 #endif /* DMA1_Channel8 */
00493 #endif /* DMA2 */
00494
00495 /**
00496   * @brief  Return the current DMA Channel half transfer complete flag.
00497   * @param __HANDLE__ DMA handle
00498   * @retval The specified half transfer complete flag index.
00499   */
00500 #if defined(DMA2)
00501 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
00502 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00503  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
00504  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00505  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
00506  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00507  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
00508  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00509  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
00510  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00511  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
00512  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00513    DMA_FLAG_HT7)
00514 #else /* DMA1 */
00515 #if   defined(DMA1_Channel7)
00516 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
00517 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00518  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00519  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00520  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00521  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00522  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00523    DMA_FLAG_HT7)
00524 #else
00525 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
00526 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00527  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00528  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00529  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00530    DMA_FLAG_HT5)
00531 #endif /* DMA1_Channel8 */
00532 #endif /* DMA2 */
00533
00534 /**
00535   * @brief  Return the current DMA Channel transfer error flag.
00536   * @param  __HANDLE__ DMA handle
00537   * @retval The specified transfer error flag index.
00538   */
00539 #if defined(DMA2)
00540 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
00541 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00542  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
00543  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00544  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
00545  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00546  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
00547  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00548  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
00549  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00550  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
00551  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00552    DMA_FLAG_TE7)
00553 #else /* DMA1 */
00554 #if   defined(DMA1_Channel7)
00555 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
00556 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00557  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00558  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00559  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00560  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00561  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00562    DMA_FLAG_TE7)
00563 #else
00564 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
00565 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00566  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00567  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00568  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00569    DMA_FLAG_TE5)
00570 #endif /* DMA1_Channel8 */
00571 #endif /* DMA2 */
00572
00573 /**
00574   * @brief  Return the current DMA Channel Global interrupt flag.
00575   * @param  __HANDLE__ DMA handle
00576   * @retval The specified transfer error flag index.
00577   */
00578 #if defined(DMA2)
00579 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
00580 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
00581  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\
00582  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
00583  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\
00584  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
00585  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\
00586  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
00587  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\
00588  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
00589  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\
00590  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
00591    DMA_FLAG_GI7)
00592 #else /* DMA1 */
00593 #if   defined(DMA1_Channel7)
00594 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
00595 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
00596  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
00597  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
00598  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
00599  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
00600  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
00601    DMA_FLAG_GI7)
00602 #else
00603 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
00604 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
00605  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
00606  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
00607  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
00608    DMA_FLAG_GI5)
00609 #endif /* DMA1_Channel8 */
00610 #endif /* DMA2 */
00611
00612 /**
00613   * @brief  Get the DMA Channel pending flags.
00614   * @param  __HANDLE__ DMA handle
00615   * @param  __FLAG__ Get the specified flag.
00616   *          This parameter can be any combination of the following values:
00617   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00618   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00619   *            @arg DMA_FLAG_TEx:  Transfer error flag
00620   *            @arg DMA_FLAG_GIx:  Global interrupt flag
00621   *         Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
00622   * @retval The state of FLAG (SET or RESET).
00623   */
00624 #if defined(DMA2)
00625 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
00626                                                   (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
00627 #else /* DMA1 */
00628 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)  (DMA1->ISR & (__FLAG__))
00629 #endif /* DMA2 */
00630
00631 /**
00632   * @brief  Clear the DMA Channel pending flags.
00633   * @param  __HANDLE__ DMA handle
00634   * @param  __FLAG__ specifies the flag to clear.
00635   *          This parameter can be any combination of the following values:
00636   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00637   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00638   *            @arg DMA_FLAG_TEx:  Transfer error flag
00639   *            @arg DMA_FLAG_GIx:  Global interrupt flag
00640   *         Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
00641   * @retval None
00642   */
00643 #if defined(DMA2)
00644 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
00645                                                     (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
00646 #else /* DMA1 */
00647 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__))
00648 #endif /* DMA2 */
00649
00650 /**
00651   * @brief  Enable the specified DMA Channel interrupts.
00652   * @param  __HANDLE__ DMA handle
00653   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
00654   *          This parameter can be any combination of the following values:
00655   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00656   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00657   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00658   * @retval None
00659   */
00660 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
00661
00662 /**
00663   * @brief  Disable the specified DMA Channel interrupts.
00664   * @param  __HANDLE__ DMA handle
00665   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
00666   *          This parameter can be any combination of the following values:
00667   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00668   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00669   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00670   * @retval None
00671   */
00672 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
00673
00674 /**
00675   * @brief  Check whether the specified DMA Channel interrupt is enabled or disabled.
00676   * @param  __HANDLE__ DMA handle
00677   * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
00678   *          This parameter can be one of the following values:
00679   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00680   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00681   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00682   * @retval The state of DMA_IT (SET or RESET).
00683   */
00684 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
00685
00686 /**
00687   * @brief  Returns the number of remaining data units in the current DMA Channel transfer.
00688   * @param  __HANDLE__ DMA handle
00689   * @retval The number of remaining data units in the current DMA Channel transfer.
00690   */
00691 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
00692
00693 /**
00694   * @}
00695   */
00696
00697 /* Include DMA HAL Extension module */
00698 #include "stm32g0xx_hal_dma_ex.h"
00699
00700 /* Exported functions --------------------------------------------------------*/
00701
00702 /** @addtogroup DMA_Exported_Functions
00703   * @{
00704   */
00705
00706 /** @addtogroup DMA_Exported_Functions_Group1
00707   * @{
00708   */
00709 /* Initialization and de-initialization functions *****************************/
00710 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00711 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
00712 /**
00713   * @}
00714   */
00715
00716 /** @addtogroup DMA_Exported_Functions_Group2
00717   * @{
00718   */
00719 /* IO operation functions *****************************************************/
00720 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00721 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
00722                                    uint32_t DataLength);
00723 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00724 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
00725 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
00726                                           uint32_t Timeout);
00727 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00728 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
00729 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
00730
00731 /**
00732   * @}
00733   */
00734
00735 /** @addtogroup DMA_Exported_Functions_Group3
00736   * @{
00737   */
00738 /* Peripheral State and Error functions ***************************************/
00739 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00740 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00741 /**
00742   * @}
00743   */
00744
00745 /**
00746   * @}
00747   */
00748
00749 /* Private macros ------------------------------------------------------------*/
00750 /** @defgroup DMA_Private_Macros DMA Private Macros
00751   * @{
00752   */
00753
00754 #define IS_DMA_DIRECTION(DIRECTION)             (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00755                                                  ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00756                                                  ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00757
00758 #define IS_DMA_BUFFER_SIZE(SIZE)                (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT))
00759
00760 #define IS_DMA_PERIPHERAL_INC_STATE(STATE)      (((STATE) == DMA_PINC_ENABLE) || \
00761                                                  ((STATE) == DMA_PINC_DISABLE))
00762
00763 #define IS_DMA_MEMORY_INC_STATE(STATE)          (((STATE) == DMA_MINC_ENABLE)  || \
00764                                                  ((STATE) == DMA_MINC_DISABLE))
00765
00766 #define IS_DMA_ALL_REQUEST(REQUEST)             ((REQUEST) <= DMA_MAX_REQUEST)
00767
00768 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)       (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00769                                                  ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00770                                                  ((SIZE) == DMA_PDATAALIGN_WORD))
00771
00772 #define IS_DMA_MEMORY_DATA_SIZE(SIZE)           (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00773                                                  ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00774                                                  ((SIZE) == DMA_MDATAALIGN_WORD ))
00775
00776 #define IS_DMA_MODE(MODE)                       (((MODE) == DMA_NORMAL )  || \
00777                                                  ((MODE) == DMA_CIRCULAR))
00778
00779 #define IS_DMA_PRIORITY(PRIORITY)               (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00780                                                  ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00781                                                  ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00782                                                  ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00783
00784 /**
00785   * @}
00786   */
00787
00788 /* Private functions ---------------------------------------------------------*/
00789
00790 /**
00791   * @}
00792   */
00793
00794 /**
00795   * @}
00796   */
00797
00798 #ifdef __cplusplus
00799 }
00800 #endif
00801
00802 #endif /* STM32G0xx_HAL_DMA_H */
00803
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dma_ex.c Source File

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stm32g0xx_hal_dma_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_dma_ex.c
00004   * @author  MCD Application Team
00005   * @brief   DMA Extension HAL module driver
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the DMA Extension peripheral:
00008   *           + Extended features functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                         ##### How to use this driver #####
00013   ==============================================================================
00014   [..]
00015   The DMA Extension HAL driver can be used as follows:
00016    (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00017    (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00018        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00019        to respectively enable/disable the request generator.
00020
00021    (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
00022        the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
00023        As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
00024        called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
00025       (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
00026
00027   @endverbatim
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * Copyright (c) 2018 STMicroelectronics.
00032   * All rights reserved.
00033   *
00034   * This software is licensed under terms that can be found in the LICENSE file
00035   * in the root directory of this software component.
00036   * If no LICENSE file comes with this software, it is provided AS-IS.
00037   *
00038   ******************************************************************************
00039   */
00040
00041 /* Includes ------------------------------------------------------------------*/
00042 #include "stm32g0xx_hal.h"
00043
00044 /** @addtogroup STM32G0xx_HAL_Driver
00045   * @{
00046   */
00047
00048 /** @defgroup DMAEx DMAEx
00049   * @brief DMA Extended HAL module driver
00050   * @{
00051   */
00052
00053 #ifdef HAL_DMA_MODULE_ENABLED
00054
00055 /* Private typedef -----------------------------------------------------------*/
00056 /* Private define ------------------------------------------------------------*/
00057 /* Private macro -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private Constants ---------------------------------------------------------*/
00060 /* Private function prototypes -----------------------------------------------*/
00061 /* Exported functions --------------------------------------------------------*/
00062
00063
00064 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
00065   * @{
00066   */
00067
00068 /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
00069   *  @brief   Extended features functions
00070   *
00071 @verbatim
00072  ===============================================================================
00073                 #####  Extended features functions  #####
00074  ===============================================================================
00075     [..]  This section provides functions allowing to:
00076
00077     (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00078     (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00079        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00080        to respectively enable/disable the request generator.
00081     (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
00082         the DMAMUX IRQ handler
00083
00084 @endverbatim
00085   * @{
00086   */
00087
00088 /**
00089   * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
00090   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00091   *             the configuration information for the specified DMA channel.
00092   * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization parameters
00093   * @retval HAL status
00094   */
00095 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
00096 {
00097   /* Check the parameters */
00098   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00099
00100   assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
00101
00102   assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
00103   assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
00104   assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
00105   assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
00106
00107   /*Check if the DMA state is ready */
00108   if (hdma->State == HAL_DMA_STATE_READY)
00109   {
00110     /* Process Locked */
00111     __HAL_LOCK(hdma);
00112
00113     /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
00114     MODIFY_REG(hdma->DMAmuxChannel->CCR, \
00115                (~DMAMUX_CxCR_DMAREQ_ID), \
00116                (pSyncConfig->SyncSignalID | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
00117                 pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
00118                 ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)));
00119
00120     /* Process UnLocked */
00121     __HAL_UNLOCK(hdma);
00122
00123     return HAL_OK;
00124   }
00125   else
00126   {
00127     /* Set the error code to busy */
00128     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00129
00130     /* Return error status */
00131     return HAL_ERROR;
00132   }
00133 }
00134
00135 /**
00136   * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
00137   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00138   *             the configuration information for the specified DMA channel.
00139   * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef
00140   *                                contains the request generator parameters.
00141   *
00142   * @retval HAL status
00143   */
00144 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
00145                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
00146 {
00147   HAL_StatusTypeDef status;
00148   HAL_DMA_StateTypeDef temp_state = hdma->State;
00149
00150   /* Check the parameters */
00151   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00152
00153   assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
00154
00155   assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
00156   assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
00157
00158   /* check if the DMA state is ready
00159      and DMA is using a DMAMUX request generator block
00160   */
00161   if (hdma->DMAmuxRequestGen == 0U)
00162   {
00163     /* Set the error code to busy */
00164     hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
00165
00166     /* error status */
00167     status = HAL_ERROR;
00168   }
00169   else if (((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
00170   {
00171     /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
00172
00173     /* Process Locked */
00174     __HAL_LOCK(hdma);
00175
00176     /* Set the request generator new parameters*/
00177     hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
00178                                    ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
00179                                    pRequestGeneratorConfig->Polarity;
00180     /* Process UnLocked */
00181     __HAL_UNLOCK(hdma);
00182
00183     return HAL_OK;
00184   }
00185   else
00186   {
00187     /* Set the error code to busy */
00188     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
00189
00190     /* error status */
00191     status = HAL_ERROR;
00192   }
00193
00194   return status;
00195 }
00196
00197 /**
00198   * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
00199   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00200   *             the configuration information for the specified DMA channel.
00201   * @retval HAL status
00202   */
00203 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
00204 {
00205   /* Check the parameters */
00206   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00207
00208   /* check if the DMA state is ready
00209      and DMA is using a DMAMUX request generator block
00210   */
00211   if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
00212   {
00213
00214     /* Enable the request generator*/
00215     hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
00216
00217     return HAL_OK;
00218   }
00219   else
00220   {
00221     return HAL_ERROR;
00222   }
00223 }
00224
00225 /**
00226   * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
00227   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00228   *             the configuration information for the specified DMA channel.
00229   * @retval HAL status
00230   */
00231 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
00232 {
00233   /* Check the parameters */
00234   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00235
00236   /* check if the DMA state is ready
00237      and DMA is using a DMAMUX request generator block
00238   */
00239   if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
00240   {
00241
00242     /* Disable the request generator*/
00243     hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
00244
00245     return HAL_OK;
00246   }
00247   else
00248   {
00249     return HAL_ERROR;
00250   }
00251 }
00252
00253 /**
00254   * @brief Handles DMAMUX interrupt request.
00255   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00256   *             the configuration information for the specified DMA channel.
00257   * @retval None
00258   */
00259 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
00260 {
00261   /* Check for DMAMUX Synchronization overrun */
00262   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
00263   {
00264     /* Disable the synchro overrun interrupt */
00265     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00266
00267     /* Clear the DMAMUX synchro overrun flag */
00268     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00269
00270     /* Update error code */
00271     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
00272
00273     if (hdma->XferErrorCallback != NULL)
00274     {
00275       /* Transfer error callback */
00276       hdma->XferErrorCallback(hdma);
00277     }
00278   }
00279
00280   if (hdma->DMAmuxRequestGen != 0)
00281   {
00282     /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
00283     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
00284     {
00285       /* Disable the request gen overrun interrupt */
00286       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00287
00288       /* Clear the DMAMUX request generator overrun flag */
00289       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00290
00291       /* Update error code */
00292       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
00293
00294       if (hdma->XferErrorCallback != NULL)
00295       {
00296         /* Transfer error callback */
00297         hdma->XferErrorCallback(hdma);
00298       }
00299     }
00300   }
00301 }
00302
00303 /**
00304   * @}
00305   */
00306
00307 /**
00308   * @}
00309   */
00310
00311 #endif /* HAL_DMA_MODULE_ENABLED */
00312 /**
00313   * @}
00314   */
00315
00316 /**
00317   * @}
00318   */
00319
00320 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_dma_ex.h Source File

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stm32g0xx_hal_dma_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_DMA_EX_H
00021 #define STM32G0xx_HAL_DMA_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029 #include "stm32g0xx_ll_dmamux.h"
00030
00031 /** @addtogroup STM32G0xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup DMAEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  HAL DMAMUX Synchronization configuration structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t SyncSignalID;        /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
00050                                   This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
00051
00052   uint32_t SyncPolarity;        /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
00053                                   This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
00054
00055   FunctionalState SyncEnable;   /*!< Specifies if the synchronization shall be enabled or disabled
00056                                   This parameter can take the value ENABLE or DISABLE */
00057
00058   FunctionalState EventEnable;  /*!< Specifies if an event shall be generated once the RequestNumber is reached.
00059                                   This parameter can take the value ENABLE or DISABLE */
00060
00061   uint32_t RequestNumber;       /*!< Specifies the number of DMA request that will be authorized after a sync event
00062                                   This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00063
00064
00065 } HAL_DMA_MuxSyncConfigTypeDef;
00066
00067
00068 /**
00069   * @brief  HAL DMAMUX request generator parameters structure definition
00070   */
00071 typedef struct
00072 {
00073   uint32_t SignalID;            /*!< Specifies the ID of the signal used for DMAMUX request generator
00074                                   This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
00075
00076   uint32_t Polarity;            /*!< Specifies the polarity of the signal on which the request is generated.
00077                                   This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
00078
00079   uint32_t RequestNumber;       /*!< Specifies the number of DMA request that will be generated after a signal event
00080                                   This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00081
00082 } HAL_DMA_MuxRequestGeneratorConfigTypeDef;
00083
00084 /**
00085   * @}
00086   */
00087
00088 /* Exported constants --------------------------------------------------------*/
00089 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
00090   * @{
00091   */
00092
00093 /** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
00094   * @{
00095   */
00096 #define HAL_DMAMUX1_SYNC_EXTI0            LL_DMAMUX_SYNC_EXTI_LINE0      /*!< Synchronization signal from EXTI Line0  */
00097 #define HAL_DMAMUX1_SYNC_EXTI1            LL_DMAMUX_SYNC_EXTI_LINE1      /*!< Synchronization signal from EXTI Line1  */
00098 #define HAL_DMAMUX1_SYNC_EXTI2            LL_DMAMUX_SYNC_EXTI_LINE2      /*!< Synchronization signal from EXTI Line2  */
00099 #define HAL_DMAMUX1_SYNC_EXTI3            LL_DMAMUX_SYNC_EXTI_LINE3      /*!< Synchronization signal from EXTI Line3  */
00100 #define HAL_DMAMUX1_SYNC_EXTI4            LL_DMAMUX_SYNC_EXTI_LINE4      /*!< Synchronization signal from EXTI Line4  */
00101 #define HAL_DMAMUX1_SYNC_EXTI5            LL_DMAMUX_SYNC_EXTI_LINE5      /*!< Synchronization signal from EXTI Line5  */
00102 #define HAL_DMAMUX1_SYNC_EXTI6            LL_DMAMUX_SYNC_EXTI_LINE6      /*!< Synchronization signal from EXTI Line6  */
00103 #define HAL_DMAMUX1_SYNC_EXTI7            LL_DMAMUX_SYNC_EXTI_LINE7      /*!< Synchronization signal from EXTI Line7  */
00104 #define HAL_DMAMUX1_SYNC_EXTI8            LL_DMAMUX_SYNC_EXTI_LINE8      /*!< Synchronization signal from EXTI Line8  */
00105 #define HAL_DMAMUX1_SYNC_EXTI9            LL_DMAMUX_SYNC_EXTI_LINE9      /*!< Synchronization signal from EXTI Line9  */
00106 #define HAL_DMAMUX1_SYNC_EXTI10           LL_DMAMUX_SYNC_EXTI_LINE10     /*!< Synchronization signal from EXTI Line10  */
00107 #define HAL_DMAMUX1_SYNC_EXTI11           LL_DMAMUX_SYNC_EXTI_LINE11     /*!< Synchronization signal from EXTI Line11  */
00108 #define HAL_DMAMUX1_SYNC_EXTI12           LL_DMAMUX_SYNC_EXTI_LINE12     /*!< Synchronization signal from EXTI Line12  */
00109 #define HAL_DMAMUX1_SYNC_EXTI13           LL_DMAMUX_SYNC_EXTI_LINE13     /*!< Synchronization signal from EXTI Line1 3 */
00110 #define HAL_DMAMUX1_SYNC_EXTI14           LL_DMAMUX_SYNC_EXTI_LINE14     /*!< Synchronization signal from EXTI Line1 4 */
00111 #define HAL_DMAMUX1_SYNC_EXTI15           LL_DMAMUX_SYNC_EXTI_LINE15     /*!< Synchronization signal from EXTI Line1 5 */
00112 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT  LL_DMAMUX_SYNC_DMAMUX_CH0      /*!< Synchronization signal from DMAMUX channel0 Event */
00113 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT  LL_DMAMUX_SYNC_DMAMUX_CH1      /*!< Synchronization signal from DMAMUX channel1 Event */
00114 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT  LL_DMAMUX_SYNC_DMAMUX_CH2      /*!< Synchronization signal from DMAMUX channel2 Event */
00115 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT  LL_DMAMUX_SYNC_DMAMUX_CH3      /*!< Synchronization signal from DMAMUX channel3 Event */
00116 #if defined(LPTIM1)
00117 #define HAL_DMAMUX1_SYNC_LPTIM1_OUT       LL_DMAMUX_SYNC_LPTIM1_OUT      /*!< Synchronization signal from LPTIM1 Output */
00118 #endif /* LPTIM1 */
00119 #if defined(LPTIM2)
00120 #define HAL_DMAMUX1_SYNC_LPTIM2_OUT       LL_DMAMUX_SYNC_LPTIM2_OUT      /*!< Synchronization signal from LPTIM2 Output */
00121 #endif /* LPTIM2 */
00122 #define HAL_DMAMUX1_SYNC_TIM14_OC         LL_DMAMUX_SYNC_TIM14_OC        /*!< Synchronization signal from TIM14 OC */
00123
00124 #define HAL_DMAMUX1_MAX_SYNC              HAL_DMAMUX1_SYNC_TIM14_OC
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
00130   * @{
00131   */
00132 #define HAL_DMAMUX_SYNC_NO_EVENT          LL_DMAMUX_SYNC_NO_EVENT               /*!< block synchronization events                       */
00133 #define HAL_DMAMUX_SYNC_RISING            LL_DMAMUX_SYNC_POL_RISING             /*!< synchronize with rising edge events                */
00134 #define HAL_DMAMUX_SYNC_FALLING           LL_DMAMUX_SYNC_POL_FALLING            /*!< synchronize with falling edge events               */
00135 #define HAL_DMAMUX_SYNC_RISING_FALLING    LL_DMAMUX_SYNC_POL_RISING_FALLING     /*!< synchronize with rising and falling edge events    */
00136
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
00142   * @{
00143   */
00144 #define HAL_DMAMUX1_REQ_GEN_EXTI0            LL_DMAMUX_REQ_GEN_EXTI_LINE0    /*!< Request signal generation from EXTI Line0  */
00145 #define HAL_DMAMUX1_REQ_GEN_EXTI1            LL_DMAMUX_REQ_GEN_EXTI_LINE1    /*!< Request signal generation from EXTI Line1  */
00146 #define HAL_DMAMUX1_REQ_GEN_EXTI2            LL_DMAMUX_REQ_GEN_EXTI_LINE2    /*!< Request signal generation from EXTI Line2  */
00147 #define HAL_DMAMUX1_REQ_GEN_EXTI3            LL_DMAMUX_REQ_GEN_EXTI_LINE3    /*!< Request signal generation from EXTI Line3  */
00148 #define HAL_DMAMUX1_REQ_GEN_EXTI4            LL_DMAMUX_REQ_GEN_EXTI_LINE4    /*!< Request signal generation from EXTI Line4  */
00149 #define HAL_DMAMUX1_REQ_GEN_EXTI5            LL_DMAMUX_REQ_GEN_EXTI_LINE5    /*!< Request signal generation from EXTI Line5  */
00150 #define HAL_DMAMUX1_REQ_GEN_EXTI6            LL_DMAMUX_REQ_GEN_EXTI_LINE6    /*!< Request signal generation from EXTI Line6  */
00151 #define HAL_DMAMUX1_REQ_GEN_EXTI7            LL_DMAMUX_REQ_GEN_EXTI_LINE7    /*!< Request signal generation from EXTI Line7  */
00152 #define HAL_DMAMUX1_REQ_GEN_EXTI8            LL_DMAMUX_REQ_GEN_EXTI_LINE8    /*!< Request signal generation from EXTI Line8  */
00153 #define HAL_DMAMUX1_REQ_GEN_EXTI9            LL_DMAMUX_REQ_GEN_EXTI_LINE9    /*!< Request signal generation from EXTI Line9  */
00154 #define HAL_DMAMUX1_REQ_GEN_EXTI10           LL_DMAMUX_REQ_GEN_EXTI_LINE10   /*!< Request signal generation from EXTI Line10 */
00155 #define HAL_DMAMUX1_REQ_GEN_EXTI11           LL_DMAMUX_REQ_GEN_EXTI_LINE11   /*!< Request signal generation from EXTI Line11 */
00156 #define HAL_DMAMUX1_REQ_GEN_EXTI12           LL_DMAMUX_REQ_GEN_EXTI_LINE12   /*!< Request signal generation from EXTI Line12 */
00157 #define HAL_DMAMUX1_REQ_GEN_EXTI13           LL_DMAMUX_REQ_GEN_EXTI_LINE13   /*!< Request signal generation from EXTI Line13 */
00158 #define HAL_DMAMUX1_REQ_GEN_EXTI14           LL_DMAMUX_REQ_GEN_EXTI_LINE14   /*!< Request signal generation from EXTI Line14 */
00159 #define HAL_DMAMUX1_REQ_GEN_EXTI15           LL_DMAMUX_REQ_GEN_EXTI_LINE15   /*!< Request signal generation from EXTI Line15 */
00160 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH0    /*!< Request signal generation from DMAMUX channel0 Event */
00161 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH1    /*!< Request signal generation from DMAMUX channel1 Event */
00162 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH2    /*!< Request signal generation from DMAMUX channel2 Event */
00163 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH3    /*!< Request signal generation from DMAMUX channel3 Event */
00164 #if defined(LPTIM1)
00165 #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT       LL_DMAMUX_REQ_GEN_LPTIM1_OUT    /*!< Request signal generation from LPTIM1 Output */
00166 #endif /* LPTIM1 */
00167 #if defined(LPTIM2)
00168 #define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT       LL_DMAMUX_REQ_GEN_LPTIM2_OUT    /*!< Request signal generation from LPTIM2 Output */
00169 #endif /* LPTIM2 */
00170 #define HAL_DMAMUX1_REQ_GEN_TIM14_OC         LL_DMAMUX_REQ_GEN_TIM14_OC      /*!< Request signal generation from TIM14 OC */
00171
00172 #define HAL_DMAMUX1_MAX_REQ_GEN              HAL_DMAMUX1_REQ_GEN_TIM14_OC
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
00178   * @{
00179   */
00180 #define HAL_DMAMUX_REQ_GEN_NO_EVENT       LL_DMAMUX_REQ_GEN_NO_EVENT            /*!< block request generator events                     */
00181 #define HAL_DMAMUX_REQ_GEN_RISING         LL_DMAMUX_REQ_GEN_POL_RISING          /*!< generate request on rising edge events             */
00182 #define HAL_DMAMUX_REQ_GEN_FALLING        LL_DMAMUX_REQ_GEN_POL_FALLING         /*!< generate request on falling edge events            */
00183 #define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING  /*!< generate request on rising and falling edge events */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192
00193 /* Exported macro ------------------------------------------------------------*/
00194
00195 /* Exported functions --------------------------------------------------------*/
00196 /** @addtogroup DMAEx_Exported_Functions
00197   * @{
00198   */
00199
00200 /* IO operation functions *****************************************************/
00201 /** @addtogroup DMAEx_Exported_Functions_Group1
00202   * @{
00203   */
00204
00205 /* ------------------------- REQUEST -----------------------------------------*/
00206 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
00207                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
00208 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
00209 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
00210 /* -------------------------------------------------------------------------- */
00211
00212 /* ------------------------- SYNCHRO -----------------------------------------*/
00213 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
00214 /* -------------------------------------------------------------------------- */
00215
00216 void              HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
00217
00218 /**
00219   * @}
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226
00227 /* Private macros ------------------------------------------------------------*/
00228 /** @defgroup DMAEx_Private_Macros DMAEx Private Macros
00229   * @brief    DMAEx private macros
00230   * @{
00231   */
00232
00233 #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID)             (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \
00234                                                          (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \
00235                                                           ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC)))
00236
00237 #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER)   (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
00238
00239 #define IS_DMAMUX_SYNC_POLARITY(POLARITY)               (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
00240                                                          ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
00241                                                          ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
00242                                                          ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
00243
00244 #define IS_DMAMUX_SYNC_STATE(SYNC)                      (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
00245
00246 #define IS_DMAMUX_SYNC_EVENT(EVENT)                     (((EVENT) == DISABLE)   || \
00247                                                          ((EVENT) == ENABLE))
00248
00249 #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID)      (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \
00250                                                          (((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \
00251                                                           ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN)))
00252
00253 #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
00254
00255 #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)        (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \
00256                                                          ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \
00257                                                          ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
00258                                                          ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
00259
00260 /**
00261   * @}
00262   */
00263
00264
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 #ifdef __cplusplus
00274 }
00275 #endif
00276
00277 #endif /* STM32G0xx_HAL_DMA_EX_H */
00278
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_exti.c Source File

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stm32g0xx_hal_exti.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2018 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   ==============================================================================
00024                     ##### EXTI Peripheral features #####
00025   ==============================================================================
00026   [..]
00027     (+) Each Exti line can be configured within this driver.
00028
00029     (+) Exti line can be configured in 3 different modes
00030         (++) Interrupt
00031         (++) Event
00032         (++) Both of them
00033
00034     (+) Configurable Exti lines can be configured with 3 different triggers
00035         (++) Rising
00036         (++) Falling
00037         (++) Both of them
00038
00039     (+) When set in interrupt mode, configurable Exti lines have two diffenrents
00040         interrupt pending registers which allow to distinguish which transition
00041         occurs:
00042         (++) Rising edge pending interrupt
00043         (++) Falling
00044
00045     (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
00046         be selected through multiplexer.
00047
00048                      ##### How to use this driver #####
00049   ==============================================================================
00050   [..]
00051
00052     (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
00053         (++) Choose the interrupt line number by setting "Line" member from
00054              EXTI_ConfigTypeDef structure.
00055         (++) Configure the interrupt and/or event mode using "Mode" member from
00056              EXTI_ConfigTypeDef structure.
00057         (++) For configurable lines, configure rising and/or falling trigger
00058              "Trigger" member from EXTI_ConfigTypeDef structure.
00059         (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
00060              member from GPIO_InitTypeDef structure.
00061
00062     (#) Get current Exti configuration of a dedicated line using
00063         HAL_EXTI_GetConfigLine().
00064         (++) Provide exiting handle as parameter.
00065         (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
00066
00067     (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
00068         (++) Provide exiting handle as parameter.
00069
00070     (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
00071         (++) Provide exiting handle as first parameter.
00072         (++) Provide which callback will be registered using one value from
00073              EXTI_CallbackIDTypeDef.
00074         (++) Provide callback function pointer.
00075
00076     (#) Get interrupt pending bit using HAL_EXTI_GetPending().
00077
00078     (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
00079
00080     (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
00081
00082   @endverbatim
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32g0xx_hal.h"
00087
00088 /** @addtogroup STM32G0xx_HAL_Driver
00089   * @{
00090   */
00091
00092 /** @addtogroup EXTI
00093   * @{
00094   */
00095 /** MISRA C:2012 deviation rule has been granted for following rule:
00096   * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
00097   * of bounds [0,3] in following API :
00098   * HAL_EXTI_SetConfigLine
00099   * HAL_EXTI_GetConfigLine
00100   * HAL_EXTI_ClearConfigLine
00101   */
00102
00103 #ifdef HAL_EXTI_MODULE_ENABLED
00104
00105 /* Private typedef -----------------------------------------------------------*/
00106 /* Private defines ------------------------------------------------------------*/
00107 /** @defgroup EXTI_Private_Constants EXTI Private Constants
00108   * @{
00109   */
00110 #define EXTI_MODE_OFFSET                    0x04u   /* 0x10: offset between CPU IMR/EMR registers */
00111 #define EXTI_CONFIG_OFFSET                  0x08u   /* 0x20: offset between CPU Rising/Falling configuration registers */
00112 /**
00113   * @}
00114   */
00115
00116 /* Private macros ------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /* Exported functions --------------------------------------------------------*/
00120
00121 /** @addtogroup EXTI_Exported_Functions
00122   * @{
00123   */
00124
00125 /** @addtogroup EXTI_Exported_Functions_Group1
00126  *  @brief    Configuration functions
00127  *
00128 @verbatim
00129  ===============================================================================
00130               ##### Configuration functions #####
00131  ===============================================================================
00132
00133 @endverbatim
00134   * @{
00135   */
00136
00137 /**
00138   * @brief  Set configuration of a dedicated Exti line.
00139   * @param  hexti Exti handle.
00140   * @param  pExtiConfig Pointer on EXTI configuration to be set.
00141   * @retval HAL Status.
00142   */
00143 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
00144 {
00145   __IO uint32_t *regaddr;
00146   uint32_t regval;
00147   uint32_t linepos;
00148   uint32_t maskline;
00149   uint32_t offset;
00150
00151   /* Check null pointer */
00152   if ((hexti == NULL) || (pExtiConfig == NULL))
00153   {
00154     return HAL_ERROR;
00155   }
00156
00157   /* Check parameters */
00158   assert_param(IS_EXTI_LINE(pExtiConfig->Line));
00159   assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
00160
00161   /* Assign line number to handle */
00162   hexti->Line = pExtiConfig->Line;
00163
00164   /* compute line register offset and line mask */
00165   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00166   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
00167   maskline = (1uL << linepos);
00168
00169   /* Configure triggers for configurable lines */
00170   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
00171   {
00172     assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
00173
00174     /* Configure rising trigger */
00175     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00176     regval = *regaddr;
00177
00178     /* Mask or set line */
00179     if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
00180     {
00181       regval |= maskline;
00182     }
00183     else
00184     {
00185       regval &= ~maskline;
00186     }
00187
00188     /* Store rising trigger mode */
00189     *regaddr = regval;
00190
00191     /* Configure falling trigger */
00192     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00193     regval = *regaddr;
00194
00195     /* Mask or set line */
00196     if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
00197     {
00198       regval |= maskline;
00199     }
00200     else
00201     {
00202       regval &= ~maskline;
00203     }
00204
00205     /* Store falling trigger mode */
00206     *regaddr = regval;
00207
00208     /* Configure gpio port selection in case of gpio exti line */
00209     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
00210     {
00211       assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
00212       assert_param(IS_EXTI_GPIO_PIN(linepos));
00213
00214       regval = EXTI->EXTICR[linepos >> 2u];
00215       regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00216       regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00217       EXTI->EXTICR[linepos >> 2u] = regval;
00218     }
00219   }
00220
00221   /* Configure interrupt mode : read current mode */
00222   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00223   regval = *regaddr;
00224
00225   /* Mask or set line */
00226   if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
00227   {
00228     regval |= maskline;
00229   }
00230   else
00231   {
00232     regval &= ~maskline;
00233   }
00234
00235   /* Store interrupt mode */
00236   *regaddr = regval;
00237
00238   /* Configure event mode : read current mode */
00239   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00240   regval = *regaddr;
00241
00242   /* Mask or set line */
00243   if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
00244   {
00245     regval |= maskline;
00246   }
00247   else
00248   {
00249     regval &= ~maskline;
00250   }
00251
00252   /* Store event mode */
00253   *regaddr = regval;
00254
00255   return HAL_OK;
00256 }
00257
00258
00259 /**
00260   * @brief  Get configuration of a dedicated Exti line.
00261   * @param  hexti Exti handle.
00262   * @param  pExtiConfig Pointer on structure to store Exti configuration.
00263   * @retval HAL Status.
00264   */
00265 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
00266 {
00267   __IO uint32_t *regaddr;
00268   uint32_t regval;
00269   uint32_t linepos;
00270   uint32_t maskline;
00271   uint32_t offset;
00272
00273   /* Check null pointer */
00274   if ((hexti == NULL) || (pExtiConfig == NULL))
00275   {
00276     return HAL_ERROR;
00277   }
00278
00279   /* Check the parameter */
00280   assert_param(IS_EXTI_LINE(hexti->Line));
00281
00282   /* Store handle line number to configiguration structure */
00283   pExtiConfig->Line = hexti->Line;
00284
00285   /* compute line register offset and line mask */
00286   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00287   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
00288   maskline = (1uL << linepos);
00289
00290   /* 1] Get core mode : interrupt */
00291   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00292   regval = *regaddr;
00293
00294   /* Check if selected line is enable */
00295   if ((regval & maskline) != 0x00u)
00296   {
00297     pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
00298   }
00299   else
00300   {
00301     pExtiConfig->Mode = EXTI_MODE_NONE;
00302   }
00303
00304   /* Get event mode */
00305   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00306   regval = *regaddr;
00307
00308   /* Check if selected line is enable */
00309   if ((regval & maskline) != 0x00u)
00310   {
00311     pExtiConfig->Mode |= EXTI_MODE_EVENT;
00312   }
00313
00314   /* Get default Trigger and GPIOSel configuration */
00315   pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
00316   pExtiConfig->GPIOSel = 0x00u;
00317
00318   /* 2] Get trigger for configurable lines : rising */
00319   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
00320   {
00321     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00322     regval = *regaddr;
00323
00324     /* Check if configuration of selected line is enable */
00325     if ((regval & maskline) != 0x00u)
00326     {
00327       pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
00328     }
00329
00330     /* Get falling configuration */
00331     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00332     regval = *regaddr;
00333
00334     /* Check if configuration of selected line is enable */
00335     if ((regval & maskline) != 0x00u)
00336     {
00337       pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
00338     }
00339
00340     /* Get Gpio port selection for gpio lines */
00341     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
00342     {
00343       assert_param(IS_EXTI_GPIO_PIN(linepos));
00344
00345       regval = EXTI->EXTICR[linepos >> 2u];
00346       pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
00347     }
00348   }
00349
00350   return HAL_OK;
00351 }
00352
00353
00354 /**
00355   * @brief  Clear whole configuration of a dedicated Exti line.
00356   * @param  hexti Exti handle.
00357   * @retval HAL Status.
00358   */
00359 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
00360 {
00361   __IO uint32_t *regaddr;
00362   uint32_t regval;
00363   uint32_t linepos;
00364   uint32_t maskline;
00365   uint32_t offset;
00366
00367   /* Check null pointer */
00368   if (hexti == NULL)
00369   {
00370     return HAL_ERROR;
00371   }
00372
00373   /* Check the parameter */
00374   assert_param(IS_EXTI_LINE(hexti->Line));
00375
00376   /* compute line register offset and line mask */
00377   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00378   linepos = (hexti->Line & EXTI_PIN_MASK);
00379   maskline = (1uL << linepos);
00380
00381   /* 1] Clear interrupt mode */
00382   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00383   regval = (*regaddr & ~maskline);
00384   *regaddr = regval;
00385
00386   /* 2] Clear event mode */
00387   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00388   regval = (*regaddr & ~maskline);
00389   *regaddr = regval;
00390
00391   /* 3] Clear triggers in case of configurable lines */
00392   if ((hexti->Line & EXTI_CONFIG) != 0x00u)
00393   {
00394     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00395     regval = (*regaddr & ~maskline);
00396     *regaddr = regval;
00397
00398     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00399     regval = (*regaddr & ~maskline);
00400     *regaddr = regval;
00401
00402     /* Get Gpio port selection for gpio lines */
00403     if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
00404     {
00405       assert_param(IS_EXTI_GPIO_PIN(linepos));
00406
00407       regval = EXTI->EXTICR[linepos >> 2u];
00408       regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00409       EXTI->EXTICR[linepos >> 2u] = regval;
00410     }
00411   }
00412
00413   return HAL_OK;
00414 }
00415
00416
00417 /**
00418   * @brief  Register callback for a dedicaated Exti line.
00419   * @param  hexti Exti handle.
00420   * @param  CallbackID User callback identifier.
00421   *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
00422   * @param  pPendingCbfn function pointer to be stored as callback.
00423   * @retval HAL Status.
00424   */
00425 HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
00426 {
00427   HAL_StatusTypeDef status = HAL_OK;
00428
00429   switch (CallbackID)
00430   {
00431     case  HAL_EXTI_COMMON_CB_ID:
00432       hexti->RisingCallback = pPendingCbfn;
00433       hexti->FallingCallback = pPendingCbfn;
00434       break;
00435
00436     case  HAL_EXTI_RISING_CB_ID:
00437       hexti->RisingCallback = pPendingCbfn;
00438       break;
00439
00440     case  HAL_EXTI_FALLING_CB_ID:
00441       hexti->FallingCallback = pPendingCbfn;
00442       break;
00443
00444     default:
00445       status = HAL_ERROR;
00446       break;
00447   }
00448
00449   return status;
00450 }
00451
00452
00453 /**
00454   * @brief  Store line number as handle private field.
00455   * @param  hexti Exti handle.
00456   * @param  ExtiLine Exti line number.
00457   *         This parameter can be from 0 to @ref EXTI_LINE_NB.
00458   * @retval HAL Status.
00459   */
00460 HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
00461 {
00462   /* Check the parameters */
00463   assert_param(IS_EXTI_LINE(ExtiLine));
00464
00465   /* Check null pointer */
00466   if (hexti == NULL)
00467   {
00468     return HAL_ERROR;
00469   }
00470   else
00471   {
00472     /* Store line number as handle private field */
00473     hexti->Line = ExtiLine;
00474
00475     return HAL_OK;
00476   }
00477 }
00478
00479
00480 /**
00481   * @}
00482   */
00483
00484 /** @addtogroup EXTI_Exported_Functions_Group2
00485  *  @brief EXTI IO functions.
00486  *
00487 @verbatim
00488  ===============================================================================
00489                        ##### IO operation functions #####
00490  ===============================================================================
00491
00492 @endverbatim
00493   * @{
00494   */
00495
00496 /**
00497   * @brief  Handle EXTI interrupt request.
00498   * @param  hexti Exti handle.
00499   * @retval none.
00500   */
00501 void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
00502 {
00503   __IO uint32_t *regaddr;
00504   uint32_t regval;
00505   uint32_t maskline;
00506   uint32_t offset;
00507
00508   /* Compute line register offset and line mask */
00509   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00510   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00511
00512   /* Get rising edge pending bit  */
00513   regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
00514   regval = (*regaddr & maskline);
00515
00516   if (regval != 0x00u)
00517   {
00518     /* Clear pending bit */
00519     *regaddr = maskline;
00520
00521     /* Call rising callback */
00522     if (hexti->RisingCallback != NULL)
00523     {
00524       hexti->RisingCallback();
00525     }
00526   }
00527
00528   /* Get falling edge pending bit  */
00529   regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
00530   regval = (*regaddr & maskline);
00531
00532   if (regval != 0x00u)
00533   {
00534     /* Clear pending bit */
00535     *regaddr = maskline;
00536
00537     /* Call rising callback */
00538     if (hexti->FallingCallback != NULL)
00539     {
00540       hexti->FallingCallback();
00541     }
00542   }
00543 }
00544
00545
00546 /**
00547   * @brief  Get interrupt pending bit of a dedicated line.
00548   * @param  hexti Exti handle.
00549   * @param  Edge Specify which pending edge as to be checked.
00550   *         This parameter can be one of the following values:
00551   *           @arg @ref EXTI_TRIGGER_RISING
00552   *           @arg @ref EXTI_TRIGGER_FALLING
00553   * @retval 1 if interrupt is pending else 0.
00554   */
00555 uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
00556 {
00557   __IO uint32_t *regaddr;
00558   uint32_t regval;
00559   uint32_t linepos;
00560   uint32_t maskline;
00561   uint32_t offset;
00562
00563   /* Check parameters */
00564   assert_param(IS_EXTI_LINE(hexti->Line));
00565   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00566   assert_param(IS_EXTI_PENDING_EDGE(Edge));
00567
00568   /* compute line register offset and line mask */
00569   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00570   linepos = (hexti->Line & EXTI_PIN_MASK);
00571   maskline = (1uL << linepos);
00572
00573   if (Edge != EXTI_TRIGGER_RISING)
00574   {
00575     /* Get falling edge pending bit */
00576     regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
00577   }
00578   else
00579   {
00580     /* Get rising edge pending bit */
00581     regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
00582   }
00583
00584   /* return 1 if bit is set else 0 */
00585   regval = ((*regaddr & maskline) >> linepos);
00586   return regval;
00587 }
00588
00589
00590 /**
00591   * @brief  Clear interrupt pending bit of a dedicated line.
00592   * @param  hexti Exti handle.
00593   * @param  Edge Specify which pending edge as to be clear.
00594   *         This parameter can be one of the following values:
00595   *           @arg @ref EXTI_TRIGGER_RISING
00596   *           @arg @ref EXTI_TRIGGER_FALLING
00597   * @retval None.
00598   */
00599 void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
00600 {
00601   __IO uint32_t *regaddr;
00602   uint32_t maskline;
00603   uint32_t offset;
00604
00605   /* Check parameters */
00606   assert_param(IS_EXTI_LINE(hexti->Line));
00607   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00608   assert_param(IS_EXTI_PENDING_EDGE(Edge));
00609
00610   /* compute line register offset and line mask */
00611   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00612   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00613
00614   if (Edge != EXTI_TRIGGER_RISING)
00615   {
00616     /* Get falling edge pending register address */
00617     regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
00618   }
00619   else
00620   {
00621     /* Get falling edge pending register address */
00622     regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
00623   }
00624
00625   /* Clear Pending bit */
00626   *regaddr =  maskline;
00627 }
00628
00629
00630 /**
00631   * @brief  Generate a software interrupt for a dedicated line.
00632   * @param  hexti Exti handle.
00633   * @retval None.
00634   */
00635 void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
00636 {
00637   __IO uint32_t *regaddr;
00638   uint32_t maskline;
00639   uint32_t offset;
00640
00641   /* Check parameterd */
00642   assert_param(IS_EXTI_LINE(hexti->Line));
00643   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00644
00645   /* compute line register offset and line mask */
00646   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00647   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00648
00649   regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
00650   *regaddr = maskline;
00651 }
00652
00653
00654 /**
00655   * @}
00656   */
00657
00658 /**
00659   * @}
00660   */
00661
00662 #endif /* HAL_EXTI_MODULE_ENABLED */
00663 /**
00664   * @}
00665   */
00666
00667 /**
00668   * @}
00669   */
00670
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_exti.h Source File

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stm32g0xx_hal_exti.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_EXTI_H
00021 #define STM32G0xx_HAL_EXTI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup EXTI EXTI
00035   * @brief EXTI HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup EXTI_Exported_Types EXTI Exported Types
00042   * @{
00043   */
00044 typedef enum
00045 {
00046   HAL_EXTI_COMMON_CB_ID          = 0x00U,
00047   HAL_EXTI_RISING_CB_ID          = 0x01U,
00048   HAL_EXTI_FALLING_CB_ID         = 0x02U,
00049 } EXTI_CallbackIDTypeDef;
00050
00051
00052 /**
00053   * @brief  EXTI Handle structure definition
00054   */
00055 typedef struct
00056 {
00057   uint32_t Line;                    /*!<  Exti line number */
00058   void (* RisingCallback)(void);    /*!<  Exti rising callback */
00059   void (* FallingCallback)(void);   /*!<  Exti falling callback */
00060 } EXTI_HandleTypeDef;
00061
00062 /**
00063   * @brief  EXTI Configuration structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Line;      /*!< The Exti line to be configured. This parameter
00068                            can be a value of @ref EXTI_Line */
00069   uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
00070                            This parameter can be a combination of @ref EXTI_Mode */
00071   uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
00072                            can be a value of @ref EXTI_Trigger */
00073   uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
00074                            This parameter is only possible for line 0 to 15. It
00075                            can be a value of @ref EXTI_GPIOSel */
00076 } EXTI_ConfigTypeDef;
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Exported constants --------------------------------------------------------*/
00083 /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
00084   * @{
00085   */
00086
00087 /** @defgroup EXTI_Line  EXTI Line
00088   * @{
00089   */
00090 #define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | 0x00u)
00091 #define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | 0x01u)
00092 #define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | 0x02u)
00093 #define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | 0x03u)
00094 #define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | 0x04u)
00095 #define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | 0x05u)
00096 #define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | 0x06u)
00097 #define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | 0x07u)
00098 #define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | 0x08u)
00099 #define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | 0x09u)
00100 #define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | 0x0Au)
00101 #define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | 0x0Bu)
00102 #define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | 0x0Cu)
00103 #define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | 0x0Du)
00104 #define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | 0x0Eu)
00105 #define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | 0x0Fu)
00106 #define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | 0x10u)
00107 #if defined(COMP1)
00108 #define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_REG1 | 0x11u)
00109 #else
00110 #define EXTI_LINE_17                        (EXTI_RESERVED | EXTI_REG1 | 0x11u)
00111 #endif /* COMP1 */
00112 #if defined(COMP2)
00113 #define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | 0x12u)
00114 #else
00115 #define EXTI_LINE_18                        (EXTI_RESERVED | EXTI_REG1 | 0x12u)
00116 #endif /* COMP2 */
00117 #define EXTI_LINE_19                        (EXTI_DIRECT   | EXTI_REG1 | 0x13u)
00118 #if defined(COMP3)
00119 #define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | 0x14u)
00120 #else
00121 #define EXTI_LINE_20                        (EXTI_RESERVED | EXTI_REG1 | 0x14u)
00122 #endif /* COMP3 */
00123 #define EXTI_LINE_21                        (EXTI_DIRECT   | EXTI_REG1 | 0x15u)
00124 #if defined(RCC_CCIPR_I2C2SEL)
00125 #define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_REG1 | 0x16u)
00126 #else
00127 #define EXTI_LINE_22                        (EXTI_RESERVED | EXTI_REG1 | 0x16u)
00128 #endif /* RCC_CCIPR_I2C2SEL */
00129 #define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | 0x17u)
00130 #if defined(RCC_CCIPR_USART3SEL)
00131 #define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | 0x18u)
00132 #else
00133 #define EXTI_LINE_24                        (EXTI_RESERVED | EXTI_REG1 | 0x18u)
00134 #endif /* RCC_CCIPR_USART3SEL */
00135 #define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | 0x19u)
00136 #if defined(RCC_CCIPR_USART2SEL)
00137 #define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Au)
00138 #else
00139 #define EXTI_LINE_26                        (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
00140 #endif /* RCC_CCIPR_USART2SEL */
00141 #if defined(CEC)
00142 #define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Bu)
00143 #else
00144 #define EXTI_LINE_27                        (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
00145 #endif /* CEC */
00146 #if defined(LPUART1)
00147 #define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Cu)
00148 #else
00149 #define EXTI_LINE_28                        (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
00150 #endif /* LPUART1 */
00151 #if defined(LPTIM1)
00152 #define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Du)
00153 #else
00154 #define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
00155 #endif /* LPTIM1 */
00156 #if defined(LPTIM2)
00157 #define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Eu)
00158 #else
00159 #define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
00160 #endif /* LPTIM2 */
00161 #define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Fu)
00162 #if defined(UCPD1)
00163 #define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | 0x00u)
00164 #else
00165 #define EXTI_LINE_32                        (EXTI_RESERVED | EXTI_REG2 | 0x00u)
00166 #endif /* UCPD1 */
00167 #if defined(UCPD2)
00168 #define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | 0x01u)
00169 #else
00170 #define EXTI_LINE_33                        (EXTI_RESERVED | EXTI_REG2 | 0x01u)
00171 #endif /* UCPD2 */
00172 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00173 #define EXTI_LINE_34                        (EXTI_CONFIG   | EXTI_REG2 | 0x02u)
00174 #else
00175 #define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2 | 0x02u)
00176 #endif /* STM32G0C1xx || STM32G0B1xx */
00177 #if defined(LPUART2)
00178 #define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_REG2 | 0x03u)
00179 #else
00180 #define EXTI_LINE_35                        (EXTI_RESERVED | EXTI_REG2 | 0x03u)
00181 #endif /* LPUART2 */
00182 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00183 #define EXTI_LINE_36                        (EXTI_DIRECT | EXTI_REG2 | 0x04u)
00184 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup EXTI_Mode  EXTI Mode
00190   * @{
00191   */
00192 #define EXTI_MODE_NONE                      0x00000000u
00193 #define EXTI_MODE_INTERRUPT                 0x00000001u
00194 #define EXTI_MODE_EVENT                     0x00000002u
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup EXTI_Trigger  EXTI Trigger
00200   * @{
00201   */
00202 #define EXTI_TRIGGER_NONE                   0x00000000u
00203 #define EXTI_TRIGGER_RISING                 0x00000001u
00204 #define EXTI_TRIGGER_FALLING                0x00000002u
00205 #define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup EXTI_GPIOSel  EXTI GPIOSel
00211   * @brief
00212   * @{
00213   */
00214 #define EXTI_GPIOA                          0x00000000u
00215 #define EXTI_GPIOB                          0x00000001u
00216 #define EXTI_GPIOC                          0x00000002u
00217 #define EXTI_GPIOD                          0x00000003u
00218 #if defined(GPIOE)
00219 #define EXTI_GPIOE                          0x00000004u
00220 #endif /* GPIOE */
00221 #define EXTI_GPIOF                          0x00000005u
00222 /**
00223   * @}
00224   */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /* Exported macro ------------------------------------------------------------*/
00231 /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
00232   * @{
00233   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /* Private constants --------------------------------------------------------*/
00240 /** @defgroup EXTI_Private_Constants EXTI Private Constants
00241   * @{
00242   */
00243 /**
00244   * @brief  EXTI Line property definition
00245   */
00246 #define EXTI_PROPERTY_SHIFT                  24u
00247 #define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)
00248 #define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
00249 #define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
00250 #define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
00251 #define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
00252
00253 /**
00254   * @brief  EXTI Register and bit usage
00255   */
00256 #define EXTI_REG_SHIFT                      16u
00257 #define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)
00258 #define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)
00259 #define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)
00260 #define EXTI_PIN_MASK                       0x0000001Fu
00261
00262 /**
00263   * @brief  EXTI Mask for interrupt & event mode
00264   */
00265 #define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
00266
00267 /**
00268   * @brief  EXTI Mask for trigger possibilities
00269   */
00270 #define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
00271
00272 /**
00273   * @brief  EXTI Line number
00274   */
00275 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00276 #define EXTI_LINE_NB                        37uL
00277 #elif defined(STM32G0B0xx)
00278 #define EXTI_LINE_NB                        37uL
00279 #elif defined(STM32G081xx) || defined(STM32G071xx)
00280 #define EXTI_LINE_NB                        34uL
00281 #elif defined(STM32G070xx)
00282 #define EXTI_LINE_NB                        34uL
00283 #elif defined(STM32G041xx) || defined(STM32G031xx)
00284 #define EXTI_LINE_NB                        32uL
00285 #else
00286 #define EXTI_LINE_NB                        32uL
00287 #endif /* STM32G0C1xx || STM32G0B1xx */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /* Private macros ------------------------------------------------------------*/
00294 /** @defgroup EXTI_Private_Macros EXTI Private Macros
00295   * @{
00296   */
00297 #define IS_EXTI_LINE(__EXTI_LINE__)     ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
00298                                         ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
00299                                          (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
00300                                          (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
00301                                          (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
00302                                          (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
00303
00304 #define IS_EXTI_MODE(__MODE__)          ((((__MODE__) & EXTI_MODE_MASK) != 0x00u) && \
00305                                          (((__MODE__) & ~EXTI_MODE_MASK) == 0x00u))
00306
00307 #define IS_EXTI_TRIGGER(__EXTI_LINE__)  (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
00308
00309 #define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
00310                                               ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING))
00311
00312 #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
00313
00314 #if defined(GPIOE)
00315 #define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
00316                                          ((__PORT__) == EXTI_GPIOB) || \
00317                                          ((__PORT__) == EXTI_GPIOC) || \
00318                                          ((__PORT__) == EXTI_GPIOD) || \
00319                                          ((__PORT__) == EXTI_GPIOE) || \
00320                                          ((__PORT__) == EXTI_GPIOF))
00321 #else
00322 #define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
00323                                          ((__PORT__) == EXTI_GPIOB) || \
00324                                          ((__PORT__) == EXTI_GPIOC) || \
00325                                          ((__PORT__) == EXTI_GPIOD) || \
00326                                          ((__PORT__) == EXTI_GPIOF))
00327 #endif /* GPIOE */
00328
00329 #define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16u)
00330
00331 /**
00332   * @}
00333   */
00334
00335
00336 /* Exported functions --------------------------------------------------------*/
00337 /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
00338   * @brief    EXTI Exported Functions
00339   * @{
00340   */
00341
00342 /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
00343   * @brief    Configuration functions
00344   * @{
00345   */
00346 /* Configuration functions ****************************************************/
00347 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
00348 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
00349 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
00350 HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
00351 HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
00357   * @brief    IO operation functions
00358   * @{
00359   */
00360 /* IO operation functions *****************************************************/
00361 void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
00362 uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
00363 void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
00364 void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
00365
00366 /**
00367   * @}
00368   */
00369
00370 /**
00371   * @}
00372   */
00373
00374 /**
00375   * @}
00376   */
00377
00378 /**
00379   * @}
00380   */
00381
00382 #ifdef __cplusplus
00383 }
00384 #endif
00385
00386 #endif /* STM32G0xx_HAL_EXTI_H */
00387
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_fdcan.c Source File

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stm32g0xx_hal_fdcan.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_fdcan.c
00004   * @author  MCD Application Team
00005   * @brief   FDCAN HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Flexible DataRate Controller Area Network
00008   *          (FDCAN) peripheral:
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Configuration and Control functions
00012   *           + Peripheral State and Error functions
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2018 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                         ##### How to use this driver #####
00027   ==============================================================================
00028     [..]
00029       (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
00030
00031       (#) If needed , configure the reception filters and optional features using
00032           the following configuration functions:
00033             (++) HAL_FDCAN_ConfigFilter
00034             (++) HAL_FDCAN_ConfigGlobalFilter
00035             (++) HAL_FDCAN_ConfigExtendedIdMask
00036             (++) HAL_FDCAN_ConfigRxFifoOverwrite
00037             (++) HAL_FDCAN_ConfigRamWatchdog
00038             (++) HAL_FDCAN_ConfigTimestampCounter
00039             (++) HAL_FDCAN_EnableTimestampCounter
00040             (++) HAL_FDCAN_DisableTimestampCounter
00041             (++) HAL_FDCAN_ConfigTimeoutCounter
00042             (++) HAL_FDCAN_EnableTimeoutCounter
00043             (++) HAL_FDCAN_DisableTimeoutCounter
00044             (++) HAL_FDCAN_ConfigTxDelayCompensation
00045             (++) HAL_FDCAN_EnableTxDelayCompensation
00046             (++) HAL_FDCAN_DisableTxDelayCompensation
00047             (++) HAL_FDCAN_EnableISOMode
00048             (++) HAL_FDCAN_DisableISOMode
00049             (++) HAL_FDCAN_EnableEdgeFiltering
00050             (++) HAL_FDCAN_DisableEdgeFiltering
00051
00052       (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
00053           the node is active on the bus: it can send and receive messages.
00054
00055       (#) The following Tx control functions can only be called when the FDCAN
00056           module is started:
00057             (++) HAL_FDCAN_AddMessageToTxFifoQ
00058             (++) HAL_FDCAN_AbortTxRequest
00059
00060       (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
00061           get Tx buffer location used to place the Tx request thanks to
00062           HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
00063           It is then possible to abort later on the corresponding Tx Request using
00064           HAL_FDCAN_AbortTxRequest API.
00065
00066       (#) When a message is received into the FDCAN message RAM, it can be
00067           retrieved using the HAL_FDCAN_GetRxMessage function.
00068
00069       (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
00070           it to initialization mode and re-enabling access to configuration
00071           registers through the configuration functions listed here above.
00072
00073       (#) All other control functions can be called any time after initialization
00074           phase, no matter if the FDCAN module is started or stopped.
00075
00076       *** Polling mode operation ***
00077       ==============================
00078     [..]
00079         (#) Reception and transmission states can be monitored via the following
00080             functions:
00081               (++) HAL_FDCAN_IsTxBufferMessagePending
00082               (++) HAL_FDCAN_GetRxFifoFillLevel
00083               (++) HAL_FDCAN_GetTxFifoFreeLevel
00084
00085       *** Interrupt mode operation ***
00086       ================================
00087       [..]
00088         (#) There are two interrupt lines: line 0 and 1.
00089             By default, all interrupts are assigned to line 0. Interrupt lines
00090             can be configured using HAL_FDCAN_ConfigInterruptLines function.
00091
00092         (#) Notifications are activated using HAL_FDCAN_ActivateNotification
00093             function. Then, the process can be controlled through one of the
00094             available user callbacks: HAL_FDCAN_xxxCallback.
00095
00096   *** Callback registration ***
00097   =============================================
00098
00099   The compilation define  USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
00100   allows the user to configure dynamically the driver callbacks.
00101   Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
00102   to register an interrupt callback.
00103
00104   Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
00105     (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
00106     (+) HighPriorityMessageCallback  : High Priority Message Callback.
00107     (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
00108     (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
00109     (+) ErrorCallback                : Error Callback.
00110     (+) MspInitCallback              : FDCAN MspInit.
00111     (+) MspDeInitCallback            : FDCAN MspDeInit.
00112   This function takes as parameters the HAL peripheral handle, the Callback ID
00113   and a pointer to the user callback function.
00114
00115   For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
00116   TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated
00117   register callbacks : respectively HAL_FDCAN_RegisterTxEventFifoCallback(),
00118   HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
00119   HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback()
00120   and HAL_FDCAN_RegisterErrorStatusCallback().
00121
00122   Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
00123   weak function.
00124   HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
00125   and the Callback ID.
00126   This function allows to reset following callbacks:
00127     (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
00128     (+) HighPriorityMessageCallback  : High Priority Message Callback.
00129     (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
00130     (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
00131     (+) ErrorCallback                : Error Callback.
00132     (+) MspInitCallback              : FDCAN MspInit.
00133     (+) MspDeInitCallback            : FDCAN MspDeInit.
00134
00135   For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
00136   TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
00137   unregister callbacks : respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
00138   HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(),
00139   HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback()
00140   and HAL_FDCAN_UnRegisterErrorStatusCallback().
00141
00142   By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
00143   all callbacks are set to the corresponding weak functions:
00144   examples HAL_FDCAN_ErrorCallback().
00145   Exception done for MspInit and MspDeInit functions that are
00146   reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
00147   these callbacks are null (not registered beforehand).
00148   if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
00149   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00150
00151   Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
00152   Exception done MspInit/MspDeInit that can be registered/unregistered
00153   in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
00154   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00155   In that case first register the MspInit/MspDeInit user callbacks
00156   using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
00157   or HAL_FDCAN_Init() function.
00158
00159   When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
00160   not defined, the callback registration feature is not available and all callbacks
00161   are set to the corresponding weak functions.
00162
00163   @endverbatim
00164   ******************************************************************************
00165   */
00166
00167 /* Includes ------------------------------------------------------------------*/
00168 #include "stm32g0xx_hal.h"
00169
00170 #if defined(FDCAN1)
00171
00172 /** @addtogroup STM32G0xx_HAL_Driver
00173   * @{
00174   */
00175
00176 /** @defgroup FDCAN FDCAN
00177   * @brief FDCAN HAL module driver
00178   * @{
00179   */
00180
00181 #ifdef HAL_FDCAN_MODULE_ENABLED
00182
00183 /* Private typedef -----------------------------------------------------------*/
00184 /* Private define ------------------------------------------------------------*/
00185 /** @addtogroup FDCAN_Private_Constants
00186   * @{
00187   */
00188 #define FDCAN_TIMEOUT_VALUE 10U
00189
00190 #define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
00191 #define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
00192 #define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
00193 #define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
00194 #define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
00195
00196 #define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
00197 #define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
00198 #define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
00199 #define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
00200 #define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
00201 #define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
00202 #define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
00203 #define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
00204 #define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
00205 #define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
00206 #define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
00207 #define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
00208 #define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
00209 #define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
00210
00211 #define SRAMCAN_FLS_NBR                  (28U)         /* Max. Filter List Standard Number      */
00212 #define SRAMCAN_FLE_NBR                  ( 8U)         /* Max. Filter List Extended Number      */
00213 #define SRAMCAN_RF0_NBR                  ( 3U)         /* RX FIFO 0 Elements Number             */
00214 #define SRAMCAN_RF1_NBR                  ( 3U)         /* RX FIFO 1 Elements Number             */
00215 #define SRAMCAN_TEF_NBR                  ( 3U)         /* TX Event FIFO Elements Number         */
00216 #define SRAMCAN_TFQ_NBR                  ( 3U)         /* TX FIFO/Queue Elements Number         */
00217
00218 #define SRAMCAN_FLS_SIZE            ( 1U * 4U)         /* Filter Standard Element Size in bytes */
00219 #define SRAMCAN_FLE_SIZE            ( 2U * 4U)         /* Filter Extended Element Size in bytes */
00220 #define SRAMCAN_RF0_SIZE            (18U * 4U)         /* RX FIFO 0 Elements Size in bytes      */
00221 #define SRAMCAN_RF1_SIZE            (18U * 4U)         /* RX FIFO 1 Elements Size in bytes      */
00222 #define SRAMCAN_TEF_SIZE            ( 2U * 4U)         /* TX Event FIFO Elements Size in bytes  */
00223 #define SRAMCAN_TFQ_SIZE            (18U * 4U)         /* TX FIFO/Queue Elements Size in bytes  */
00224
00225 #define SRAMCAN_FLSSA ((uint32_t)0)                                                      /* Filter List Standard Start
00226                                                                                             Address                  */
00227 #define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start
00228                                                                                             Address                  */
00229 #define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address  */
00230 #define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address  */
00231 #define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start
00232                                                                                             Address */
00233 #define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start
00234                                                                                             Address                  */
00235 #define SRAMCAN_SIZE  ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size         */
00236
00237 /**
00238   * @}
00239   */
00240
00241 /* Private macro -------------------------------------------------------------*/
00242 /* Private variables ---------------------------------------------------------*/
00243 /** @addtogroup FDCAN_Private_Variables
00244   * @{
00245   */
00246 static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
00247 /**
00248   * @}
00249   */
00250
00251 /* Private function prototypes -----------------------------------------------*/
00252 static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
00253 static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
00254                                    uint32_t BufferIndex);
00255
00256 /* Exported functions --------------------------------------------------------*/
00257 /** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
00258   * @{
00259   */
00260
00261 /** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
00262   *  @brief    Initialization and Configuration functions
00263   *
00264 @verbatim
00265   ==============================================================================
00266               ##### Initialization and de-initialization functions #####
00267   ==============================================================================
00268     [..]  This section provides functions allowing to:
00269       (+) Initialize and configure the FDCAN.
00270       (+) De-initialize the FDCAN.
00271       (+) Enter FDCAN peripheral in power down mode.
00272       (+) Exit power down mode.
00273       (+) Register callbacks.
00274       (+) Unregister callbacks.
00275
00276 @endverbatim
00277   * @{
00278   */
00279
00280 /**
00281   * @brief  Initializes the FDCAN peripheral according to the specified
00282   *         parameters in the FDCAN_InitTypeDef structure.
00283   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00284   *         the configuration information for the specified FDCAN.
00285   * @retval HAL status
00286   */
00287 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
00288 {
00289   uint32_t tickstart;
00290
00291   /* Check FDCAN handle */
00292   if (hfdcan == NULL)
00293   {
00294     return HAL_ERROR;
00295   }
00296
00297   /* Check function parameters */
00298   assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
00299   if (hfdcan->Instance == FDCAN1)
00300   {
00301     assert_param(IS_FDCAN_CKDIV(hfdcan->Init.ClockDivider));
00302   }
00303   assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
00304   assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
00305   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
00306   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
00307   assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
00308   assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
00309   assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
00310   assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
00311   assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
00312   if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
00313   {
00314     assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
00315     assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
00316     assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
00317     assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
00318   }
00319   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, SRAMCAN_FLS_NBR));
00320   assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, SRAMCAN_FLE_NBR));
00321   assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
00322
00323 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00324   if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00325   {
00326     /* Allocate lock resource and initialize it */
00327     hfdcan->Lock = HAL_UNLOCKED;
00328
00329     /* Reset callbacks to legacy functions */
00330     hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* Legacy weak TxEventFifoCallback */
00331     hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* Legacy weak RxFifo0Callback     */
00332     hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* Legacy weak RxFifo1Callback     */
00333     hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* Legacy weak TxFifoEmptyCallback */
00334     hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* Legacy weak
00335                                                                                     TxBufferCompleteCallback        */
00336     hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* Legacy weak
00337                                                                                     TxBufferAbortCallback           */
00338     hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak
00339                                                                                     HighPriorityMessageCallback     */
00340     hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak
00341                                                                                     TimestampWraparoundCallback     */
00342     hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* Legacy weak
00343                                                                                     TimeoutOccurredCallback         */
00344     hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* Legacy weak ErrorCallback       */
00345     hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* Legacy weak ErrorStatusCallback */
00346
00347     if (hfdcan->MspInitCallback == NULL)
00348     {
00349       hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
00350     }
00351
00352     /* Init the low level hardware: CLOCK, NVIC */
00353     hfdcan->MspInitCallback(hfdcan);
00354   }
00355 #else
00356   if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00357   {
00358     /* Allocate lock resource and initialize it */
00359     hfdcan->Lock = HAL_UNLOCKED;
00360
00361     /* Init the low level hardware: CLOCK, NVIC */
00362     HAL_FDCAN_MspInit(hfdcan);
00363   }
00364 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00365
00366   /* Exit from Sleep mode */
00367   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00368
00369   /* Get tick */
00370   tickstart = HAL_GetTick();
00371
00372   /* Check Sleep mode acknowledge */
00373   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
00374   {
00375     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00376     {
00377       /* Update error code */
00378       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00379
00380       /* Change FDCAN state */
00381       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00382
00383       return HAL_ERROR;
00384     }
00385   }
00386
00387   /* Request initialisation */
00388   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
00389
00390   /* Get tick */
00391   tickstart = HAL_GetTick();
00392
00393   /* Wait until the INIT bit into CCCR register is set */
00394   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
00395   {
00396     /* Check for the Timeout */
00397     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00398     {
00399       /* Update error code */
00400       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00401
00402       /* Change FDCAN state */
00403       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00404
00405       return HAL_ERROR;
00406     }
00407   }
00408
00409   /* Enable configuration change */
00410   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
00411
00412   /* Check FDCAN instance */
00413   if (hfdcan->Instance == FDCAN1)
00414   {
00415     /* Configure Clock divider */
00416     FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider;
00417   }
00418
00419   /* Set the no automatic retransmission */
00420   if (hfdcan->Init.AutoRetransmission == ENABLE)
00421   {
00422     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
00423   }
00424   else
00425   {
00426     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
00427   }
00428
00429   /* Set the transmit pause feature */
00430   if (hfdcan->Init.TransmitPause == ENABLE)
00431   {
00432     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
00433   }
00434   else
00435   {
00436     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
00437   }
00438
00439   /* Set the Protocol Exception Handling */
00440   if (hfdcan->Init.ProtocolException == ENABLE)
00441   {
00442     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
00443   }
00444   else
00445   {
00446     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
00447   }
00448
00449   /* Set FDCAN Frame Format */
00450   MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
00451
00452   /* Reset FDCAN Operation Mode */
00453   CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
00454   CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
00455
00456   /* Set FDCAN Operating Mode:
00457                | Normal | Restricted |    Bus     | Internal | External
00458                |        | Operation  | Monitoring | LoopBack | LoopBack
00459      CCCR.TEST |   0    |     0      |     0      |    1     |    1
00460      CCCR.MON  |   0    |     0      |     1      |    1     |    0
00461      TEST.LBCK |   0    |     0      |     0      |    1     |    1
00462      CCCR.ASM  |   0    |     1      |     0      |    0     |    0
00463   */
00464   if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
00465   {
00466     /* Enable Restricted Operation mode */
00467     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
00468   }
00469   else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
00470   {
00471     if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
00472     {
00473       /* Enable write access to TEST register */
00474       SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
00475
00476       /* Enable LoopBack mode */
00477       SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
00478
00479       if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
00480       {
00481         SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
00482       }
00483     }
00484     else
00485     {
00486       /* Enable bus monitoring mode */
00487       SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
00488     }
00489   }
00490   else
00491   {
00492     /* Nothing to do: normal mode */
00493   }
00494
00495   /* Set the nominal bit timing register */
00496   hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
00497                             (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
00498                             (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
00499                             (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
00500
00501   /* If FD operation with BRS is selected, set the data bit timing register */
00502   if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
00503   {
00504     hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos)  | \
00505                               (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)     | \
00506                               (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)     | \
00507                               (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
00508   }
00509
00510   /* Select between Tx FIFO and Tx Queue operation modes */
00511   SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
00512
00513   /* Calculate each RAM block address */
00514   FDCAN_CalcultateRamBlockAddresses(hfdcan);
00515
00516   /* Initialize the Latest Tx request buffer index */
00517   hfdcan->LatestTxFifoQRequest = 0U;
00518
00519   /* Initialize the error code */
00520   hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
00521
00522   /* Initialize the FDCAN state */
00523   hfdcan->State = HAL_FDCAN_STATE_READY;
00524
00525   /* Return function status */
00526   return HAL_OK;
00527 }
00528
00529 /**
00530   * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
00531   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00532   *         the configuration information for the specified FDCAN.
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
00536 {
00537   /* Check FDCAN handle */
00538   if (hfdcan == NULL)
00539   {
00540     return HAL_ERROR;
00541   }
00542
00543   /* Check function parameters */
00544   assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
00545
00546   /* Stop the FDCAN module: return value is voluntary ignored */
00547   (void)HAL_FDCAN_Stop(hfdcan);
00548
00549   /* Disable Interrupt lines */
00550   CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
00551
00552 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00553   if (hfdcan->MspDeInitCallback == NULL)
00554   {
00555     hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
00556   }
00557
00558   /* DeInit the low level hardware: CLOCK, NVIC */
00559   hfdcan->MspDeInitCallback(hfdcan);
00560 #else
00561   /* DeInit the low level hardware: CLOCK, NVIC */
00562   HAL_FDCAN_MspDeInit(hfdcan);
00563 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00564
00565   /* Reset the FDCAN ErrorCode */
00566   hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
00567
00568   /* Change FDCAN state */
00569   hfdcan->State = HAL_FDCAN_STATE_RESET;
00570
00571   /* Return function status */
00572   return HAL_OK;
00573 }
00574
00575 /**
00576   * @brief  Initializes the FDCAN MSP.
00577   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00578   *         the configuration information for the specified FDCAN.
00579   * @retval None
00580   */
00581 __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
00582 {
00583   /* Prevent unused argument(s) compilation warning */
00584   UNUSED(hfdcan);
00585   /* NOTE : This function Should not be modified, when the callback is needed,
00586             the HAL_FDCAN_MspInit could be implemented in the user file
00587    */
00588 }
00589
00590 /**
00591   * @brief  DeInitializes the FDCAN MSP.
00592   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00593   *         the configuration information for the specified FDCAN.
00594   * @retval None
00595   */
00596 __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
00597 {
00598   /* Prevent unused argument(s) compilation warning */
00599   UNUSED(hfdcan);
00600   /* NOTE : This function Should not be modified, when the callback is needed,
00601             the HAL_FDCAN_MspDeInit could be implemented in the user file
00602    */
00603 }
00604
00605 /**
00606   * @brief  Enter FDCAN peripheral in sleep mode.
00607   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00608   *         the configuration information for the specified FDCAN.
00609   * @retval HAL status
00610   */
00611 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
00612 {
00613   uint32_t tickstart;
00614
00615   /* Request clock stop */
00616   SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00617
00618   /* Get tick */
00619   tickstart = HAL_GetTick();
00620
00621   /* Wait until FDCAN is ready for power down */
00622   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
00623   {
00624     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00625     {
00626       /* Update error code */
00627       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00628
00629       /* Change FDCAN state */
00630       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00631
00632       return HAL_ERROR;
00633     }
00634   }
00635
00636   /* Return function status */
00637   return HAL_OK;
00638 }
00639
00640 /**
00641   * @brief  Exit power down mode.
00642   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
00643   *         the configuration information for the specified FDCAN.
00644   * @retval HAL status
00645   */
00646 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
00647 {
00648   uint32_t tickstart;
00649
00650   /* Reset clock stop request */
00651   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
00652
00653   /* Get tick */
00654   tickstart = HAL_GetTick();
00655
00656   /* Wait until FDCAN exits sleep mode */
00657   while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
00658   {
00659     if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
00660     {
00661       /* Update error code */
00662       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
00663
00664       /* Change FDCAN state */
00665       hfdcan->State = HAL_FDCAN_STATE_ERROR;
00666
00667       return HAL_ERROR;
00668     }
00669   }
00670
00671   /* Enter normal operation */
00672   CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
00673
00674   /* Return function status */
00675   return HAL_OK;
00676 }
00677
00678 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00679 /**
00680   * @brief  Register a FDCAN CallBack.
00681   *         To be used instead of the weak predefined callback
00682   * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
00683   *         the configuration information for FDCAN module
00684   * @param  CallbackID ID of the callback to be registered
00685   *         This parameter can be one of the following values:
00686   *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
00687   *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
00688   *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
00689   *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
00690   *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
00691   *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
00692   *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
00693   * @param  pCallback pointer to the Callback function
00694   * @retval HAL status
00695   */
00696 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
00697                                              void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
00698 {
00699   HAL_StatusTypeDef status = HAL_OK;
00700
00701   if (pCallback == NULL)
00702   {
00703     /* Update the error code */
00704     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00705
00706     return HAL_ERROR;
00707   }
00708
00709   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00710   {
00711     switch (CallbackID)
00712     {
00713       case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
00714         hfdcan->TxFifoEmptyCallback = pCallback;
00715         break;
00716
00717       case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
00718         hfdcan->HighPriorityMessageCallback = pCallback;
00719         break;
00720
00721       case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
00722         hfdcan->TimestampWraparoundCallback = pCallback;
00723         break;
00724
00725       case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
00726         hfdcan->TimeoutOccurredCallback = pCallback;
00727         break;
00728
00729       case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
00730         hfdcan->ErrorCallback = pCallback;
00731         break;
00732
00733       case HAL_FDCAN_MSPINIT_CB_ID :
00734         hfdcan->MspInitCallback = pCallback;
00735         break;
00736
00737       case HAL_FDCAN_MSPDEINIT_CB_ID :
00738         hfdcan->MspDeInitCallback = pCallback;
00739         break;
00740
00741       default :
00742         /* Update the error code */
00743         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00744
00745         /* Return error status */
00746         status =  HAL_ERROR;
00747         break;
00748     }
00749   }
00750   else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00751   {
00752     switch (CallbackID)
00753     {
00754       case HAL_FDCAN_MSPINIT_CB_ID :
00755         hfdcan->MspInitCallback = pCallback;
00756         break;
00757
00758       case HAL_FDCAN_MSPDEINIT_CB_ID :
00759         hfdcan->MspDeInitCallback = pCallback;
00760         break;
00761
00762       default :
00763         /* Update the error code */
00764         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00765
00766         /* Return error status */
00767         status =  HAL_ERROR;
00768         break;
00769     }
00770   }
00771   else
00772   {
00773     /* Update the error code */
00774     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00775
00776     /* Return error status */
00777     status =  HAL_ERROR;
00778   }
00779
00780   return status;
00781 }
00782
00783 /**
00784   * @brief  Unregister a FDCAN CallBack.
00785   *         FDCAN callback is redirected to the weak predefined callback
00786   * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
00787   *         the configuration information for FDCAN module
00788   * @param  CallbackID ID of the callback to be unregistered
00789   *         This parameter can be one of the following values:
00790   *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
00791   *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
00792   *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
00793   *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
00794   *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
00795   *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
00796   *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
00797   * @retval HAL status
00798   */
00799 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
00800 {
00801   HAL_StatusTypeDef status = HAL_OK;
00802
00803   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00804   {
00805     switch (CallbackID)
00806     {
00807       case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
00808         hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
00809         break;
00810
00811       case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
00812         hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
00813         break;
00814
00815       case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
00816         hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
00817         break;
00818
00819       case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
00820         hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
00821         break;
00822
00823       case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
00824         hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
00825         break;
00826
00827       case HAL_FDCAN_MSPINIT_CB_ID :
00828         hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
00829         break;
00830
00831       case HAL_FDCAN_MSPDEINIT_CB_ID :
00832         hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
00833         break;
00834
00835       default :
00836         /* Update the error code */
00837         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00838
00839         /* Return error status */
00840         status =  HAL_ERROR;
00841         break;
00842     }
00843   }
00844   else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
00845   {
00846     switch (CallbackID)
00847     {
00848       case HAL_FDCAN_MSPINIT_CB_ID :
00849         hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
00850         break;
00851
00852       case HAL_FDCAN_MSPDEINIT_CB_ID :
00853         hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
00854         break;
00855
00856       default :
00857         /* Update the error code */
00858         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00859
00860         /* Return error status */
00861         status =  HAL_ERROR;
00862         break;
00863     }
00864   }
00865   else
00866   {
00867     /* Update the error code */
00868     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00869
00870     /* Return error status */
00871     status =  HAL_ERROR;
00872   }
00873
00874   return status;
00875 }
00876
00877 /**
00878   * @brief  Register Tx Event Fifo FDCAN Callback
00879   *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
00880   * @param  hfdcan FDCAN handle
00881   * @param  pCallback pointer to the Tx Event Fifo Callback function
00882   * @retval HAL status
00883   */
00884 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
00885                                                         pFDCAN_TxEventFifoCallbackTypeDef pCallback)
00886 {
00887   HAL_StatusTypeDef status = HAL_OK;
00888
00889   if (pCallback == NULL)
00890   {
00891     /* Update the error code */
00892     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00893     return HAL_ERROR;
00894   }
00895
00896   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00897   {
00898     hfdcan->TxEventFifoCallback = pCallback;
00899   }
00900   else
00901   {
00902     /* Update the error code */
00903     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00904
00905     /* Return error status */
00906     status =  HAL_ERROR;
00907   }
00908
00909   return status;
00910 }
00911
00912 /**
00913   * @brief  UnRegister the Tx Event Fifo FDCAN Callback
00914   *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
00915   * @param  hfdcan FDCAN handle
00916   * @retval HAL status
00917   */
00918 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
00919 {
00920   HAL_StatusTypeDef status = HAL_OK;
00921
00922   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00923   {
00924     hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
00925   }
00926   else
00927   {
00928     /* Update the error code */
00929     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00930
00931     /* Return error status */
00932     status =  HAL_ERROR;
00933   }
00934
00935   return status;
00936 }
00937
00938 /**
00939   * @brief  Register Rx Fifo 0 FDCAN Callback
00940   *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
00941   * @param  hfdcan FDCAN handle
00942   * @param  pCallback pointer to the Rx Fifo 0 Callback function
00943   * @retval HAL status
00944   */
00945 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
00946                                                     pFDCAN_RxFifo0CallbackTypeDef pCallback)
00947 {
00948   HAL_StatusTypeDef status = HAL_OK;
00949
00950   if (pCallback == NULL)
00951   {
00952     /* Update the error code */
00953     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00954     return HAL_ERROR;
00955   }
00956
00957   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00958   {
00959     hfdcan->RxFifo0Callback = pCallback;
00960   }
00961   else
00962   {
00963     /* Update the error code */
00964     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00965
00966     /* Return error status */
00967     status =  HAL_ERROR;
00968   }
00969
00970   return status;
00971 }
00972
00973 /**
00974   * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
00975   *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
00976   * @param  hfdcan FDCAN handle
00977   * @retval HAL status
00978   */
00979 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
00980 {
00981   HAL_StatusTypeDef status = HAL_OK;
00982
00983   if (hfdcan->State == HAL_FDCAN_STATE_READY)
00984   {
00985     hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
00986   }
00987   else
00988   {
00989     /* Update the error code */
00990     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
00991
00992     /* Return error status */
00993     status =  HAL_ERROR;
00994   }
00995
00996   return status;
00997 }
00998
00999 /**
01000   * @brief  Register Rx Fifo 1 FDCAN Callback
01001   *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
01002   * @param  hfdcan FDCAN handle
01003   * @param  pCallback pointer to the Rx Fifo 1 Callback function
01004   * @retval HAL status
01005   */
01006 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
01007                                                     pFDCAN_RxFifo1CallbackTypeDef pCallback)
01008 {
01009   HAL_StatusTypeDef status = HAL_OK;
01010
01011   if (pCallback == NULL)
01012   {
01013     /* Update the error code */
01014     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01015     return HAL_ERROR;
01016   }
01017
01018   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01019   {
01020     hfdcan->RxFifo1Callback = pCallback;
01021   }
01022   else
01023   {
01024     /* Update the error code */
01025     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01026
01027     /* Return error status */
01028     status =  HAL_ERROR;
01029   }
01030
01031   return status;
01032 }
01033
01034 /**
01035   * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
01036   *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
01037   * @param  hfdcan FDCAN handle
01038   * @retval HAL status
01039   */
01040 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
01041 {
01042   HAL_StatusTypeDef status = HAL_OK;
01043
01044   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01045   {
01046     hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
01047   }
01048   else
01049   {
01050     /* Update the error code */
01051     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01052
01053     /* Return error status */
01054     status =  HAL_ERROR;
01055   }
01056
01057   return status;
01058 }
01059
01060 /**
01061   * @brief  Register Tx Buffer Complete FDCAN Callback
01062   *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
01063   * @param  hfdcan FDCAN handle
01064   * @param  pCallback pointer to the Tx Buffer Complete Callback function
01065   * @retval HAL status
01066   */
01067 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
01068                                                              pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
01069 {
01070   HAL_StatusTypeDef status = HAL_OK;
01071
01072   if (pCallback == NULL)
01073   {
01074     /* Update the error code */
01075     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01076     return HAL_ERROR;
01077   }
01078
01079   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01080   {
01081     hfdcan->TxBufferCompleteCallback = pCallback;
01082   }
01083   else
01084   {
01085     /* Update the error code */
01086     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01087
01088     /* Return error status */
01089     status =  HAL_ERROR;
01090   }
01091
01092   return status;
01093 }
01094
01095 /**
01096   * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
01097   *         Tx Buffer Complete FDCAN Callback is redirected to
01098   *         the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
01099   * @param  hfdcan FDCAN handle
01100   * @retval HAL status
01101   */
01102 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
01103 {
01104   HAL_StatusTypeDef status = HAL_OK;
01105
01106   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01107   {
01108     hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
01109   }
01110   else
01111   {
01112     /* Update the error code */
01113     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01114
01115     /* Return error status */
01116     status =  HAL_ERROR;
01117   }
01118
01119   return status;
01120 }
01121
01122 /**
01123   * @brief  Register Tx Buffer Abort FDCAN Callback
01124   *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
01125   * @param  hfdcan FDCAN handle
01126   * @param  pCallback pointer to the Tx Buffer Abort Callback function
01127   * @retval HAL status
01128   */
01129 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
01130                                                           pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
01131 {
01132   HAL_StatusTypeDef status = HAL_OK;
01133
01134   if (pCallback == NULL)
01135   {
01136     /* Update the error code */
01137     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01138     return HAL_ERROR;
01139   }
01140
01141   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01142   {
01143     hfdcan->TxBufferAbortCallback = pCallback;
01144   }
01145   else
01146   {
01147     /* Update the error code */
01148     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01149
01150     /* Return error status */
01151     status =  HAL_ERROR;
01152   }
01153
01154   return status;
01155 }
01156
01157 /**
01158   * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
01159   *         Tx Buffer Abort FDCAN Callback is redirected to
01160   *         the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
01161   * @param  hfdcan FDCAN handle
01162   * @retval HAL status
01163   */
01164 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
01165 {
01166   HAL_StatusTypeDef status = HAL_OK;
01167
01168   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01169   {
01170     hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
01171   }
01172   else
01173   {
01174     /* Update the error code */
01175     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01176
01177     /* Return error status */
01178     status =  HAL_ERROR;
01179   }
01180
01181   return status;
01182 }
01183
01184 /**
01185   * @brief  Register Error Status FDCAN Callback
01186   *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
01187   * @param  hfdcan FDCAN handle
01188   * @param  pCallback pointer to the Error Status Callback function
01189   * @retval HAL status
01190   */
01191 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
01192                                                         pFDCAN_ErrorStatusCallbackTypeDef pCallback)
01193 {
01194   HAL_StatusTypeDef status = HAL_OK;
01195
01196   if (pCallback == NULL)
01197   {
01198     /* Update the error code */
01199     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01200     return HAL_ERROR;
01201   }
01202
01203   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01204   {
01205     hfdcan->ErrorStatusCallback = pCallback;
01206   }
01207   else
01208   {
01209     /* Update the error code */
01210     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01211
01212     /* Return error status */
01213     status =  HAL_ERROR;
01214   }
01215
01216   return status;
01217 }
01218
01219 /**
01220   * @brief  UnRegister the Error Status FDCAN Callback
01221   *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
01222   * @param  hfdcan FDCAN handle
01223   * @retval HAL status
01224   */
01225 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
01226 {
01227   HAL_StatusTypeDef status = HAL_OK;
01228
01229   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01230   {
01231     hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
01232   }
01233   else
01234   {
01235     /* Update the error code */
01236     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
01237
01238     /* Return error status */
01239     status =  HAL_ERROR;
01240   }
01241
01242   return status;
01243 }
01244
01245 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01246
01247 /**
01248   * @}
01249   */
01250
01251 /** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
01252   *  @brief    FDCAN Configuration functions.
01253   *
01254 @verbatim
01255   ==============================================================================
01256               ##### Configuration functions #####
01257   ==============================================================================
01258     [..]  This section provides functions allowing to:
01259       (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
01260       (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
01261       (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
01262       (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
01263       (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
01264       (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
01265         (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
01266         (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
01267         (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
01268         (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
01269       (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
01270         (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
01271         (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
01272         (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
01273         (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
01274       (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
01275         (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
01276         (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
01277       (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
01278       (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
01279       (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
01280       (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
01281
01282 @endverbatim
01283   * @{
01284   */
01285
01286 /**
01287   * @brief  Configure the FDCAN reception filter according to the specified
01288   *         parameters in the FDCAN_FilterTypeDef structure.
01289   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01290   *         the configuration information for the specified FDCAN.
01291   * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
01292   *         contains the filter configuration information
01293   * @retval HAL status
01294   */
01295 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
01296 {
01297   uint32_t FilterElementW1;
01298   uint32_t FilterElementW2;
01299   uint32_t *FilterAddress;
01300   HAL_FDCAN_StateTypeDef state = hfdcan->State;
01301
01302   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
01303   {
01304     /* Check function parameters */
01305     assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
01306     assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
01307
01308     if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
01309     {
01310       /* Check function parameters */
01311       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
01312       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
01313       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
01314       assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
01315
01316       /* Build filter element */
01317       FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
01318                          (sFilterConfig->FilterConfig << 27U) |
01319                          (sFilterConfig->FilterID1 << 16U)    |
01320                          sFilterConfig->FilterID2);
01321
01322       /* Calculate filter address */
01323       FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE));
01324
01325       /* Write filter element to the message RAM */
01326       *FilterAddress = FilterElementW1;
01327     }
01328     else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
01329     {
01330       /* Check function parameters */
01331       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
01332       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
01333       assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
01334       assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
01335
01336       /* Build first word of filter element */
01337       FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
01338
01339       /* Build second word of filter element */
01340       FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
01341
01342       /* Calculate filter address */
01343       FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE));
01344
01345       /* Write filter element to the message RAM */
01346       *FilterAddress = FilterElementW1;
01347       FilterAddress++;
01348       *FilterAddress = FilterElementW2;
01349     }
01350
01351     /* Return function status */
01352     return HAL_OK;
01353   }
01354   else
01355   {
01356     /* Update error code */
01357     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
01358
01359     return HAL_ERROR;
01360   }
01361 }
01362
01363 /**
01364   * @brief  Configure the FDCAN global filter.
01365   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01366   *         the configuration information for the specified FDCAN.
01367   * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
01368   *         do not match any element of the filter list are treated.
01369   *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
01370   * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
01371   *         do not match any element of the filter list are treated.
01372   *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
01373   * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
01374   *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
01375   * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
01376   *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
01377   * @retval HAL status
01378   */
01379 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
01380                                                uint32_t NonMatchingStd,
01381                                                uint32_t NonMatchingExt,
01382                                                uint32_t RejectRemoteStd,
01383                                                uint32_t RejectRemoteExt)
01384 {
01385   /* Check function parameters */
01386   assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
01387   assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
01388   assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
01389   assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
01390
01391   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01392   {
01393     /* Configure global filter */
01394     MODIFY_REG(hfdcan->Instance->RXGFC, (FDCAN_RXGFC_ANFS |
01395                                          FDCAN_RXGFC_ANFE |
01396                                          FDCAN_RXGFC_RRFS |
01397                                          FDCAN_RXGFC_RRFE),
01398                ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos)  |
01399                 (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos)  |
01400                 (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
01401                 (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
01402
01403     /* Return function status */
01404     return HAL_OK;
01405   }
01406   else
01407   {
01408     /* Update error code */
01409     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01410
01411     return HAL_ERROR;
01412   }
01413 }
01414
01415 /**
01416   * @brief  Configure the extended ID mask.
01417   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01418   *         the configuration information for the specified FDCAN.
01419   * @param  Mask Extended ID Mask.
01420             This parameter must be a number between 0 and 0x1FFFFFFF
01421   * @retval HAL status
01422   */
01423 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
01424 {
01425   /* Check function parameters */
01426   assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
01427
01428   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01429   {
01430     /* Configure the extended ID mask */
01431     hfdcan->Instance->XIDAM = Mask;
01432
01433     /* Return function status */
01434     return HAL_OK;
01435   }
01436   else
01437   {
01438     /* Update error code */
01439     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01440
01441     return HAL_ERROR;
01442   }
01443 }
01444
01445 /**
01446   * @brief  Configure the Rx FIFO operation mode.
01447   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01448   *         the configuration information for the specified FDCAN.
01449   * @param  RxFifo Rx FIFO.
01450   *         This parameter can be one of the following values:
01451   *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
01452   *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
01453   * @param  OperationMode operation mode.
01454   *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
01455   * @retval HAL status
01456   */
01457 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
01458 {
01459   /* Check function parameters */
01460   assert_param(IS_FDCAN_RX_FIFO(RxFifo));
01461   assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
01462
01463   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01464   {
01465     if (RxFifo == FDCAN_RX_FIFO0)
01466     {
01467       /* Select FIFO 0 Operation Mode */
01468       MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F0OM, (OperationMode << FDCAN_RXGFC_F0OM_Pos));
01469     }
01470     else /* RxFifo == FDCAN_RX_FIFO1 */
01471     {
01472       /* Select FIFO 1 Operation Mode */
01473       MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F1OM, (OperationMode << FDCAN_RXGFC_F1OM_Pos));
01474     }
01475
01476     /* Return function status */
01477     return HAL_OK;
01478   }
01479   else
01480   {
01481     /* Update error code */
01482     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01483
01484     return HAL_ERROR;
01485   }
01486 }
01487
01488 /**
01489   * @brief  Configure the RAM watchdog.
01490   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01491   *         the configuration information for the specified FDCAN.
01492   * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
01493   *         This parameter must be a number between 0x00 and 0xFF,
01494   *         with the reset value of 0x00 the counter is disabled.
01495   * @retval HAL status
01496   */
01497 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
01498 {
01499   /* Check function parameters */
01500   assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
01501
01502   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01503   {
01504     /* Configure the RAM watchdog counter start value */
01505     MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
01506
01507     /* Return function status */
01508     return HAL_OK;
01509   }
01510   else
01511   {
01512     /* Update error code */
01513     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01514
01515     return HAL_ERROR;
01516   }
01517 }
01518
01519 /**
01520   * @brief  Configure the timestamp counter.
01521   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01522   *         the configuration information for the specified FDCAN.
01523   * @param  TimestampPrescaler Timestamp Counter Prescaler.
01524   *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
01525   * @retval HAL status
01526   */
01527 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
01528 {
01529   /* Check function parameters */
01530   assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
01531
01532   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01533   {
01534     /* Configure prescaler */
01535     MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
01536
01537     /* Return function status */
01538     return HAL_OK;
01539   }
01540   else
01541   {
01542     /* Update error code */
01543     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01544
01545     return HAL_ERROR;
01546   }
01547 }
01548
01549 /**
01550   * @brief  Enable the timestamp counter.
01551   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01552   *         the configuration information for the specified FDCAN.
01553   * @param  TimestampOperation Timestamp counter operation.
01554   *         This parameter can be a value of @arg FDCAN_Timestamp.
01555   * @retval HAL status
01556   */
01557 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
01558 {
01559   /* Check function parameters */
01560   assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
01561
01562   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01563   {
01564     /* Enable timestamp counter */
01565     MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
01566
01567     /* Return function status */
01568     return HAL_OK;
01569   }
01570   else
01571   {
01572     /* Update error code */
01573     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01574
01575     return HAL_ERROR;
01576   }
01577 }
01578
01579 /**
01580   * @brief  Disable the timestamp counter.
01581   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01582   *         the configuration information for the specified FDCAN.
01583   * @retval HAL status
01584   */
01585 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
01586 {
01587   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01588   {
01589     /* Disable timestamp counter */
01590     CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
01591
01592     /* Return function status */
01593     return HAL_OK;
01594   }
01595   else
01596   {
01597     /* Update error code */
01598     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01599
01600     return HAL_ERROR;
01601   }
01602 }
01603
01604 /**
01605   * @brief  Get the timestamp counter value.
01606   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01607   *         the configuration information for the specified FDCAN.
01608   * @retval Timestamp counter value
01609   */
01610 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
01611 {
01612   return (uint16_t)(hfdcan->Instance->TSCV);
01613 }
01614
01615 /**
01616   * @brief  Reset the timestamp counter to zero.
01617   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01618   *         the configuration information for the specified FDCAN.
01619   * @retval HAL status
01620   */
01621 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
01622 {
01623   if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
01624   {
01625     /* Reset timestamp counter.
01626        Actually any write operation to TSCV clears the counter */
01627     CLEAR_REG(hfdcan->Instance->TSCV);
01628   }
01629   else
01630   {
01631     /* Update error code.
01632        Unable to reset external counter */
01633     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
01634
01635     return HAL_ERROR;
01636   }
01637
01638   /* Return function status */
01639   return HAL_OK;
01640 }
01641
01642 /**
01643   * @brief  Configure the timeout counter.
01644   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01645   *         the configuration information for the specified FDCAN.
01646   * @param  TimeoutOperation Timeout counter operation.
01647   *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
01648   * @param  TimeoutPeriod Start value of the timeout down-counter.
01649   *         This parameter must be a number between 0x0000 and 0xFFFF
01650   * @retval HAL status
01651   */
01652 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
01653                                                  uint32_t TimeoutPeriod)
01654 {
01655   /* Check function parameters */
01656   assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
01657   assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
01658
01659   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01660   {
01661     /* Select timeout operation and configure period */
01662     MODIFY_REG(hfdcan->Instance->TOCC,
01663                (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
01664
01665     /* Return function status */
01666     return HAL_OK;
01667   }
01668   else
01669   {
01670     /* Update error code */
01671     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01672
01673     return HAL_ERROR;
01674   }
01675 }
01676
01677 /**
01678   * @brief  Enable the timeout counter.
01679   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01680   *         the configuration information for the specified FDCAN.
01681   * @retval HAL status
01682   */
01683 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01684 {
01685   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01686   {
01687     /* Enable timeout counter */
01688     SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
01689
01690     /* Return function status */
01691     return HAL_OK;
01692   }
01693   else
01694   {
01695     /* Update error code */
01696     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01697
01698     return HAL_ERROR;
01699   }
01700 }
01701
01702 /**
01703   * @brief  Disable the timeout counter.
01704   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01705   *         the configuration information for the specified FDCAN.
01706   * @retval HAL status
01707   */
01708 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01709 {
01710   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01711   {
01712     /* Disable timeout counter */
01713     CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
01714
01715     /* Return function status */
01716     return HAL_OK;
01717   }
01718   else
01719   {
01720     /* Update error code */
01721     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01722
01723     return HAL_ERROR;
01724   }
01725 }
01726
01727 /**
01728   * @brief  Get the timeout counter value.
01729   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01730   *         the configuration information for the specified FDCAN.
01731   * @retval Timeout counter value
01732   */
01733 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01734 {
01735   return (uint16_t)(hfdcan->Instance->TOCV);
01736 }
01737
01738 /**
01739   * @brief  Reset the timeout counter to its start value.
01740   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01741   *         the configuration information for the specified FDCAN.
01742   * @retval HAL status
01743   */
01744 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
01745 {
01746   if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
01747   {
01748     /* Reset timeout counter to start value */
01749     CLEAR_REG(hfdcan->Instance->TOCV);
01750
01751     /* Return function status */
01752     return HAL_OK;
01753   }
01754   else
01755   {
01756     /* Update error code.
01757        Unable to reset counter: controlled only by FIFO empty state */
01758     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
01759
01760     return HAL_ERROR;
01761   }
01762 }
01763
01764 /**
01765   * @brief  Configure the transmitter delay compensation.
01766   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01767   *         the configuration information for the specified FDCAN.
01768   * @param  TdcOffset Transmitter Delay Compensation Offset.
01769   *         This parameter must be a number between 0x00 and 0x7F.
01770   * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
01771   *         This parameter must be a number between 0x00 and 0x7F.
01772   * @retval HAL status
01773   */
01774 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
01775                                                       uint32_t TdcFilter)
01776 {
01777   /* Check function parameters */
01778   assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
01779   assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
01780
01781   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01782   {
01783     /* Configure TDC offset and filter window */
01784     hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
01785
01786     /* Return function status */
01787     return HAL_OK;
01788   }
01789   else
01790   {
01791     /* Update error code */
01792     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01793
01794     return HAL_ERROR;
01795   }
01796 }
01797
01798 /**
01799   * @brief  Enable the transmitter delay compensation.
01800   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01801   *         the configuration information for the specified FDCAN.
01802   * @retval HAL status
01803   */
01804 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
01805 {
01806   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01807   {
01808     /* Enable transmitter delay compensation */
01809     SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
01810
01811     /* Return function status */
01812     return HAL_OK;
01813   }
01814   else
01815   {
01816     /* Update error code */
01817     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01818
01819     return HAL_ERROR;
01820   }
01821 }
01822
01823 /**
01824   * @brief  Disable the transmitter delay compensation.
01825   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01826   *         the configuration information for the specified FDCAN.
01827   * @retval HAL status
01828   */
01829 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
01830 {
01831   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01832   {
01833     /* Disable transmitter delay compensation */
01834     CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
01835
01836     /* Return function status */
01837     return HAL_OK;
01838   }
01839   else
01840   {
01841     /* Update error code */
01842     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01843
01844     return HAL_ERROR;
01845   }
01846 }
01847
01848 /**
01849   * @brief  Enable ISO 11898-1 protocol mode.
01850   *         CAN FD frame format is according to ISO 11898-1 standard.
01851   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01852   *         the configuration information for the specified FDCAN.
01853   * @retval HAL status
01854   */
01855 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
01856 {
01857   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01858   {
01859     /* Disable Non ISO protocol mode */
01860     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
01861
01862     /* Return function status */
01863     return HAL_OK;
01864   }
01865   else
01866   {
01867     /* Update error code */
01868     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01869
01870     return HAL_ERROR;
01871   }
01872 }
01873
01874 /**
01875   * @brief  Disable ISO 11898-1 protocol mode.
01876   *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
01877   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01878   *         the configuration information for the specified FDCAN.
01879   * @retval HAL status
01880   */
01881 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
01882 {
01883   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01884   {
01885     /* Enable Non ISO protocol mode */
01886     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
01887
01888     /* Return function status */
01889     return HAL_OK;
01890   }
01891   else
01892   {
01893     /* Update error code */
01894     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01895
01896     return HAL_ERROR;
01897   }
01898 }
01899
01900 /**
01901   * @brief  Enable edge filtering during bus integration.
01902   *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
01903   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01904   *         the configuration information for the specified FDCAN.
01905   * @retval HAL status
01906   */
01907 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
01908 {
01909   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01910   {
01911     /* Enable edge filtering */
01912     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
01913
01914     /* Return function status */
01915     return HAL_OK;
01916   }
01917   else
01918   {
01919     /* Update error code */
01920     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01921
01922     return HAL_ERROR;
01923   }
01924 }
01925
01926 /**
01927   * @brief  Disable edge filtering during bus integration.
01928   *         One dominant tq is required to detect an edge for hard synchronization.
01929   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01930   *         the configuration information for the specified FDCAN.
01931   * @retval HAL status
01932   */
01933 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
01934 {
01935   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01936   {
01937     /* Disable edge filtering */
01938     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
01939
01940     /* Return function status */
01941     return HAL_OK;
01942   }
01943   else
01944   {
01945     /* Update error code */
01946     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
01947
01948     return HAL_ERROR;
01949   }
01950 }
01951
01952 /**
01953   * @}
01954   */
01955
01956 /** @defgroup FDCAN_Exported_Functions_Group3 Control functions
01957   *  @brief    Control functions
01958   *
01959 @verbatim
01960   ==============================================================================
01961                           ##### Control functions #####
01962   ==============================================================================
01963     [..]  This section provides functions allowing to:
01964       (+) HAL_FDCAN_Start                         : Start the FDCAN module
01965       (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
01966       (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding
01967                                                     transmission request
01968       (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
01969       (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
01970       (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx FIFO zone into the message RAM
01971       (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone
01972                                                     into the message RAM
01973       (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
01974       (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
01975       (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
01976       (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending
01977                                                     on the selected Tx buffer
01978       (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
01979       (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
01980       (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
01981       (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
01982
01983 @endverbatim
01984   * @{
01985   */
01986
01987 /**
01988   * @brief  Start the FDCAN module.
01989   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
01990   *         the configuration information for the specified FDCAN.
01991   * @retval HAL status
01992   */
01993 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
01994 {
01995   if (hfdcan->State == HAL_FDCAN_STATE_READY)
01996   {
01997     /* Change FDCAN peripheral state */
01998     hfdcan->State = HAL_FDCAN_STATE_BUSY;
01999
02000     /* Request leave initialisation */
02001     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
02002
02003     /* Reset the FDCAN ErrorCode */
02004     hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
02005
02006     /* Return function status */
02007     return HAL_OK;
02008   }
02009   else
02010   {
02011     /* Update error code */
02012     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
02013
02014     return HAL_ERROR;
02015   }
02016 }
02017
02018 /**
02019   * @brief  Stop the FDCAN module and enable access to configuration registers.
02020   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02021   *         the configuration information for the specified FDCAN.
02022   * @retval HAL status
02023   */
02024 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
02025 {
02026   uint32_t Counter = 0U;
02027
02028   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02029   {
02030     /* Request initialisation */
02031     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
02032
02033     /* Wait until the INIT bit into CCCR register is set */
02034     while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
02035     {
02036       /* Check for the Timeout */
02037       if (Counter > FDCAN_TIMEOUT_VALUE)
02038       {
02039         /* Update error code */
02040         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02041
02042         /* Change FDCAN state */
02043         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02044
02045         return HAL_ERROR;
02046       }
02047
02048       /* Increment counter */
02049       Counter++;
02050     }
02051
02052     /* Reset counter */
02053     Counter = 0U;
02054
02055     /* Exit from Sleep mode */
02056     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
02057
02058     /* Wait until FDCAN exits sleep mode */
02059     while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
02060     {
02061       /* Check for the Timeout */
02062       if (Counter > FDCAN_TIMEOUT_VALUE)
02063       {
02064         /* Update error code */
02065         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
02066
02067         /* Change FDCAN state */
02068         hfdcan->State = HAL_FDCAN_STATE_ERROR;
02069
02070         return HAL_ERROR;
02071       }
02072
02073       /* Increment counter */
02074       Counter++;
02075     }
02076
02077     /* Enable configuration change */
02078     SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
02079
02080     /* Reset Latest Tx FIFO/Queue Request Buffer Index */
02081     hfdcan->LatestTxFifoQRequest = 0U;
02082
02083     /* Change FDCAN peripheral state */
02084     hfdcan->State = HAL_FDCAN_STATE_READY;
02085
02086     /* Return function status */
02087     return HAL_OK;
02088   }
02089   else
02090   {
02091     /* Update error code */
02092     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02093
02094     return HAL_ERROR;
02095   }
02096 }
02097
02098 /**
02099   * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
02100   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02101   *         the configuration information for the specified FDCAN.
02102   * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
02103   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
02104   * @retval HAL status
02105   */
02106 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
02107                                                 uint8_t *pTxData)
02108 {
02109   uint32_t PutIndex;
02110
02111   /* Check function parameters */
02112   assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
02113   if (pTxHeader->IdType == FDCAN_STANDARD_ID)
02114   {
02115     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
02116   }
02117   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
02118   {
02119     assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
02120   }
02121   assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
02122   assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
02123   assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
02124   assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
02125   assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
02126   assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
02127   assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
02128
02129   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02130   {
02131     /* Check that the Tx FIFO/Queue is not full */
02132     if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
02133     {
02134       /* Update error code */
02135       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
02136
02137       return HAL_ERROR;
02138     }
02139     else
02140     {
02141       /* Retrieve the Tx FIFO PutIndex */
02142       PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
02143
02144       /* Add the message to the Tx FIFO/Queue */
02145       FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
02146
02147       /* Activate the corresponding transmission request */
02148       hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
02149
02150       /* Store the Latest Tx FIFO/Queue Request Buffer Index */
02151       hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
02152     }
02153
02154     /* Return function status */
02155     return HAL_OK;
02156   }
02157   else
02158   {
02159     /* Update error code */
02160     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02161
02162     return HAL_ERROR;
02163   }
02164 }
02165
02166 /**
02167   * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
02168   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02169   *         the configuration information for the specified FDCAN.
02170   * @retval Tx buffer index of last Tx FIFO/Queue request
02171   *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
02172   *          - 0 if no Tx FIFO/Queue request have been submitted.
02173   */
02174 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
02175 {
02176   /* Return Last Tx FIFO/Queue Request Buffer */
02177   return hfdcan->LatestTxFifoQRequest;
02178 }
02179
02180 /**
02181   * @brief  Abort transmission request
02182   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02183   *         the configuration information for the specified FDCAN.
02184   * @param  BufferIndex buffer index.
02185   *         This parameter can be any combination of @arg FDCAN_Tx_location.
02186   * @retval HAL status
02187   */
02188 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
02189 {
02190   /* Check function parameters */
02191   assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndex));
02192
02193   if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
02194   {
02195     /* Add cancellation request */
02196     hfdcan->Instance->TXBCR = BufferIndex;
02197
02198     /* Return function status */
02199     return HAL_OK;
02200   }
02201   else
02202   {
02203     /* Update error code */
02204     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02205
02206     return HAL_ERROR;
02207   }
02208 }
02209
02210 /**
02211   * @brief  Get an FDCAN frame from the Rx FIFO zone into the message RAM.
02212   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02213   *         the configuration information for the specified FDCAN.
02214   * @param  RxLocation Location of the received message to be read.
02215   *         This parameter can be a value of @arg FDCAN_Rx_location.
02216   * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
02217   * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
02218   * @retval HAL status
02219   */
02220 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
02221                                          FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
02222 {
02223   uint32_t *RxAddress;
02224   uint8_t  *pData;
02225   uint32_t ByteCounter;
02226   uint32_t GetIndex;
02227   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02228
02229   /* Check function parameters */
02230   assert_param(IS_FDCAN_RX_FIFO(RxLocation));
02231
02232   if (state == HAL_FDCAN_STATE_BUSY)
02233   {
02234     if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
02235     {
02236       /* Check that the Rx FIFO 0 is not empty */
02237       if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
02238       {
02239         /* Update error code */
02240         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
02241
02242         return HAL_ERROR;
02243       }
02244       else
02245       {
02246         /* Calculate Rx FIFO 0 element address */
02247         GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
02248         RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE));
02249       }
02250     }
02251     else /* Rx element is assigned to the Rx FIFO 1 */
02252     {
02253       /* Check that the Rx FIFO 1 is not empty */
02254       if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
02255       {
02256         /* Update error code */
02257         hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
02258
02259         return HAL_ERROR;
02260       }
02261       else
02262       {
02263         /* Calculate Rx FIFO 1 element address */
02264         GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
02265         RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE));
02266       }
02267     }
02268
02269     /* Retrieve IdType */
02270     pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
02271
02272     /* Retrieve Identifier */
02273     if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
02274     {
02275       pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
02276     }
02277     else /* Extended ID element */
02278     {
02279       pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
02280     }
02281
02282     /* Retrieve RxFrameType */
02283     pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
02284
02285     /* Retrieve ErrorStateIndicator */
02286     pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
02287
02288     /* Increment RxAddress pointer to second word of Rx FIFO element */
02289     RxAddress++;
02290
02291     /* Retrieve RxTimestamp */
02292     pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
02293
02294     /* Retrieve DataLength */
02295     pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
02296
02297     /* Retrieve BitRateSwitch */
02298     pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
02299
02300     /* Retrieve FDFormat */
02301     pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
02302
02303     /* Retrieve FilterIndex */
02304     pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
02305
02306     /* Retrieve NonMatchingFrame */
02307     pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
02308
02309     /* Increment RxAddress pointer to payload of Rx FIFO element */
02310     RxAddress++;
02311
02312     /* Retrieve Rx payload */
02313     pData = (uint8_t *)RxAddress;
02314     for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++)
02315     {
02316       pRxData[ByteCounter] = pData[ByteCounter];
02317     }
02318
02319     if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
02320     {
02321       /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
02322       hfdcan->Instance->RXF0A = GetIndex;
02323     }
02324     else /* Rx element is assigned to the Rx FIFO 1 */
02325     {
02326       /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
02327       hfdcan->Instance->RXF1A = GetIndex;
02328     }
02329
02330     /* Return function status */
02331     return HAL_OK;
02332   }
02333   else
02334   {
02335     /* Update error code */
02336     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02337
02338     return HAL_ERROR;
02339   }
02340 }
02341
02342 /**
02343   * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
02344   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02345   *         the configuration information for the specified FDCAN.
02346   * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
02347   * @retval HAL status
02348   */
02349 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
02350 {
02351   uint32_t *TxEventAddress;
02352   uint32_t GetIndex;
02353   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02354
02355   if (state == HAL_FDCAN_STATE_BUSY)
02356   {
02357     /* Check that the Tx event FIFO is not empty */
02358     if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
02359     {
02360       /* Update error code */
02361       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
02362
02363       return HAL_ERROR;
02364     }
02365
02366     /* Calculate Tx event FIFO element address */
02367     GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
02368     TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * SRAMCAN_TEF_SIZE));
02369
02370     /* Retrieve IdType */
02371     pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
02372
02373     /* Retrieve Identifier */
02374     if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
02375     {
02376       pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
02377     }
02378     else /* Extended ID element */
02379     {
02380       pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
02381     }
02382
02383     /* Retrieve TxFrameType */
02384     pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
02385
02386     /* Retrieve ErrorStateIndicator */
02387     pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
02388
02389     /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
02390     TxEventAddress++;
02391
02392     /* Retrieve TxTimestamp */
02393     pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
02394
02395     /* Retrieve DataLength */
02396     pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
02397
02398     /* Retrieve BitRateSwitch */
02399     pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
02400
02401     /* Retrieve FDFormat */
02402     pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
02403
02404     /* Retrieve EventType */
02405     pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
02406
02407     /* Retrieve MessageMarker */
02408     pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
02409
02410     /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
02411     hfdcan->Instance->TXEFA = GetIndex;
02412
02413     /* Return function status */
02414     return HAL_OK;
02415   }
02416   else
02417   {
02418     /* Update error code */
02419     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
02420
02421     return HAL_ERROR;
02422   }
02423 }
02424
02425 /**
02426   * @brief  Get high priority message status.
02427   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02428   *         the configuration information for the specified FDCAN.
02429   * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
02430   * @retval HAL status
02431   */
02432 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
02433                                                          FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
02434 {
02435   HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
02436   HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
02437   HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
02438   HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
02439
02440   /* Return function status */
02441   return HAL_OK;
02442 }
02443
02444 /**
02445   * @brief  Get protocol status.
02446   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02447   *         the configuration information for the specified FDCAN.
02448   * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
02449   * @retval HAL status
02450   */
02451 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
02452 {
02453   uint32_t StatusReg;
02454
02455   /* Read the protocol status register */
02456   StatusReg = READ_REG(hfdcan->Instance->PSR);
02457
02458   /* Fill the protocol status structure */
02459   ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
02460   ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
02461   ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
02462   ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
02463   ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
02464   ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
02465   ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
02466   ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
02467   ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
02468   ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
02469   ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
02470
02471   /* Return function status */
02472   return HAL_OK;
02473 }
02474
02475 /**
02476   * @brief  Get error counter values.
02477   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02478   *         the configuration information for the specified FDCAN.
02479   * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
02480   * @retval HAL status
02481   */
02482 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
02483 {
02484   uint32_t CountersReg;
02485
02486   /* Read the error counters register */
02487   CountersReg = READ_REG(hfdcan->Instance->ECR);
02488
02489   /* Fill the error counters structure */
02490   ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
02491   ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
02492   ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
02493   ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
02494
02495   /* Return function status */
02496   return HAL_OK;
02497 }
02498
02499 /**
02500   * @brief  Check if a transmission request is pending on the selected Tx buffer.
02501   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02502   *         the configuration information for the specified FDCAN.
02503   * @param  TxBufferIndex Tx buffer index.
02504   *         This parameter can be any combination of @arg FDCAN_Tx_location.
02505   * @retval Status
02506   *          - 0 : No pending transmission request on TxBufferIndex list
02507   *          - 1 : Pending transmission request on TxBufferIndex.
02508   */
02509 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
02510 {
02511   /* Check function parameters */
02512   assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
02513
02514   /* Check pending transmission request on the selected buffer */
02515   if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
02516   {
02517     return 0;
02518   }
02519   return 1;
02520 }
02521
02522 /**
02523   * @brief  Return Rx FIFO fill level.
02524   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02525   *         the configuration information for the specified FDCAN.
02526   * @param  RxFifo Rx FIFO.
02527   *         This parameter can be one of the following values:
02528   *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
02529   *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
02530   * @retval Rx FIFO fill level.
02531   */
02532 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
02533 {
02534   uint32_t FillLevel;
02535
02536   /* Check function parameters */
02537   assert_param(IS_FDCAN_RX_FIFO(RxFifo));
02538
02539   if (RxFifo == FDCAN_RX_FIFO0)
02540   {
02541     FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
02542   }
02543   else /* RxFifo == FDCAN_RX_FIFO1 */
02544   {
02545     FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
02546   }
02547
02548   /* Return Rx FIFO fill level */
02549   return FillLevel;
02550 }
02551
02552 /**
02553   * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
02554   *         elements starting from Tx FIFO GetIndex.
02555   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02556   *         the configuration information for the specified FDCAN.
02557   * @retval Tx FIFO free level.
02558   */
02559 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
02560 {
02561   uint32_t FreeLevel;
02562
02563   FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
02564
02565   /* Return Tx FIFO free level */
02566   return FreeLevel;
02567 }
02568
02569 /**
02570   * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
02571   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02572   *         the configuration information for the specified FDCAN.
02573   * @retval Status
02574   *          - 0 : Normal FDCAN operation.
02575   *          - 1 : Restricted Operation Mode active.
02576   */
02577 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
02578 {
02579   uint32_t OperationMode;
02580
02581   /* Get Operation Mode */
02582   OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
02583
02584   return OperationMode;
02585 }
02586
02587 /**
02588   * @brief  Exit Restricted Operation Mode.
02589   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02590   *         the configuration information for the specified FDCAN.
02591   * @retval HAL status
02592   */
02593 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
02594 {
02595   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02596
02597   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02598   {
02599     /* Exit Restricted Operation mode */
02600     CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
02601
02602     /* Return function status */
02603     return HAL_OK;
02604   }
02605   else
02606   {
02607     /* Update error code */
02608     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02609
02610     return HAL_ERROR;
02611   }
02612 }
02613
02614 /**
02615   * @}
02616   */
02617
02618 /** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management
02619   *  @brief    Interrupts management
02620   *
02621 @verbatim
02622   ==============================================================================
02623                        ##### Interrupts management #####
02624   ==============================================================================
02625     [..]  This section provides functions allowing to:
02626       (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
02627       (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
02628       (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
02629       (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
02630
02631 @endverbatim
02632   * @{
02633   */
02634
02635 /**
02636   * @brief  Assign interrupts to either Interrupt line 0 or 1.
02637   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02638   *         the configuration information for the specified FDCAN.
02639   * @param  ITList indicates which interrupts group will be assigned to the selected interrupt line.
02640   *         This parameter can be any combination of @arg FDCAN_Interrupts_Group.
02641   * @param  InterruptLine Interrupt line.
02642   *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
02643   * @retval HAL status
02644   */
02645 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
02646 {
02647   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02648
02649   /* Check function parameters */
02650   assert_param(IS_FDCAN_IT_GROUP(ITList));
02651   assert_param(IS_FDCAN_IT_LINE(InterruptLine));
02652
02653   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02654   {
02655     /* Assign list of interrupts to the selected line */
02656     if (InterruptLine == FDCAN_INTERRUPT_LINE0)
02657     {
02658       CLEAR_BIT(hfdcan->Instance->ILS, ITList);
02659     }
02660     else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
02661     {
02662       SET_BIT(hfdcan->Instance->ILS, ITList);
02663     }
02664
02665     /* Return function status */
02666     return HAL_OK;
02667   }
02668   else
02669   {
02670     /* Update error code */
02671     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02672
02673     return HAL_ERROR;
02674   }
02675 }
02676
02677 /**
02678   * @brief  Enable interrupts.
02679   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02680   *         the configuration information for the specified FDCAN.
02681   * @param  ActiveITs indicates which interrupts will be enabled.
02682   *         This parameter can be any combination of @arg FDCAN_Interrupts.
02683   * @param  BufferIndexes Tx Buffer Indexes.
02684   *         This parameter can be any combination of @arg FDCAN_Tx_location.
02685   *         This parameter is ignored if ActiveITs does not include one of the following:
02686   *           - FDCAN_IT_TX_COMPLETE
02687   *           - FDCAN_IT_TX_ABORT_COMPLETE
02688   * @retval HAL status
02689   */
02690 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
02691                                                  uint32_t BufferIndexes)
02692 {
02693   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02694   uint32_t ITs_lines_selection;
02695
02696   /* Check function parameters */
02697   assert_param(IS_FDCAN_IT(ActiveITs));
02698   if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U)
02699   {
02700     assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes));
02701   }
02702
02703   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02704   {
02705     /* Get interrupts line selection */
02706     ITs_lines_selection = hfdcan->Instance->ILS;
02707
02708     /* Enable Interrupt lines */
02709     if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
02710          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
02711         (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1)       != 0U)
02712          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
02713         (((ActiveITs & FDCAN_IT_LIST_SMSG)           != 0U)
02714          && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG)     == 0U)) || \
02715         (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR)  != 0U)
02716          && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR)  == 0U)) || \
02717         (((ActiveITs & FDCAN_IT_LIST_MISC)           != 0U)
02718          && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC)           == 0U)) || \
02719         (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
02720          && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
02721         (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
02722          && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
02723     {
02724       /* Enable Interrupt line 0 */
02725       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
02726     }
02727     if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0)       != 0U)
02728          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0)      != 0U)) || \
02729         (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1)       != 0U)
02730          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1)       != 0U)) || \
02731         (((ActiveITs & FDCAN_IT_LIST_SMSG)           != 0U)
02732          && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG)           != 0U)) || \
02733         (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR)  != 0U)
02734          && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR)  != 0U)) || \
02735         (((ActiveITs & FDCAN_IT_LIST_MISC)           != 0U)
02736          && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC)           != 0U)) || \
02737         (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
02738          && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
02739         (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
02740          && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
02741     {
02742       /* Enable Interrupt line 1 */
02743       SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
02744     }
02745
02746     if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
02747     {
02748       /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
02749          but interrupt will only occur if TC is enabled in IE register */
02750       SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
02751     }
02752
02753     if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
02754     {
02755       /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
02756          but interrupt will only occur if TCF is enabled in IE register */
02757       SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
02758     }
02759
02760     /* Enable the selected interrupts */
02761     __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
02762
02763     /* Return function status */
02764     return HAL_OK;
02765   }
02766   else
02767   {
02768     /* Update error code */
02769     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02770
02771     return HAL_ERROR;
02772   }
02773 }
02774
02775 /**
02776   * @brief  Disable interrupts.
02777   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02778   *         the configuration information for the specified FDCAN.
02779   * @param  InactiveITs indicates which interrupts will be disabled.
02780   *         This parameter can be any combination of @arg FDCAN_Interrupts.
02781   * @retval HAL status
02782   */
02783 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
02784 {
02785   HAL_FDCAN_StateTypeDef state = hfdcan->State;
02786   uint32_t ITs_enabled;
02787   uint32_t ITs_lines_selection;
02788
02789   /* Check function parameters */
02790   assert_param(IS_FDCAN_IT(InactiveITs));
02791
02792   if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
02793   {
02794     /* Disable the selected interrupts */
02795     __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
02796
02797     if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
02798     {
02799       /* Disable Tx Buffer Transmission Interrupts */
02800       CLEAR_REG(hfdcan->Instance->TXBTIE);
02801     }
02802
02803     if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
02804     {
02805       /* Disable Tx Buffer Cancellation Finished Interrupt */
02806       CLEAR_REG(hfdcan->Instance->TXBCIE);
02807     }
02808
02809     /* Get interrupts enabled and interrupts line selection */
02810     ITs_enabled = hfdcan->Instance->IE;
02811     ITs_lines_selection = hfdcan->Instance->ILS;
02812
02813     /* Check if some interrupts are still enabled on interrupt line 0 */
02814     if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0)       != 0U)
02815          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0)       == 0U)) || \
02816         (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1)       != 0U)
02817          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1)       == 0U)) || \
02818         (((ITs_enabled & FDCAN_IT_LIST_SMSG)           != 0U)
02819          && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG)           == 0U)) || \
02820         (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR)  != 0U)
02821          && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR)  == 0U)) || \
02822         (((ITs_enabled & FDCAN_IT_LIST_MISC)           != 0U)
02823          && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC)           == 0U)) || \
02824         (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
02825          && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
02826         (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
02827          && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
02828     {
02829       /* Do nothing */
02830     }
02831     else /* no more interrupts enabled on interrupt line 0 */
02832     {
02833       /* Disable interrupt line 0 */
02834       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
02835     }
02836
02837     /* Check if some interrupts are still enabled on interrupt line 1 */
02838     if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0)       != 0U)
02839          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0)       != 0U)) || \
02840         (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1)       != 0U)
02841          && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1)       != 0U)) || \
02842         (((ITs_enabled & FDCAN_IT_LIST_SMSG)           != 0U)
02843          && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG)           != 0U)) || \
02844         (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR)  != 0U)
02845          && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR)  != 0U)) || \
02846         (((ITs_enabled & FDCAN_IT_LIST_MISC)           != 0U)
02847          && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC)           != 0U)) || \
02848         (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
02849          && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
02850         (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
02851          && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
02852     {
02853       /* Do nothing */
02854     }
02855     else /* no more interrupts enabled on interrupt line 1 */
02856     {
02857       /* Disable interrupt line 1 */
02858       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
02859     }
02860
02861     /* Return function status */
02862     return HAL_OK;
02863   }
02864   else
02865   {
02866     /* Update error code */
02867     hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
02868
02869     return HAL_ERROR;
02870   }
02871 }
02872
02873 /**
02874   * @brief  Handles FDCAN interrupt request.
02875   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
02876   *         the configuration information for the specified FDCAN.
02877   * @retval HAL status
02878   */
02879 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
02880 {
02881   uint32_t TxEventFifoITs;
02882   uint32_t RxFifo0ITs;
02883   uint32_t RxFifo1ITs;
02884   uint32_t Errors;
02885   uint32_t ErrorStatusITs;
02886   uint32_t TransmittedBuffers;
02887   uint32_t AbortedBuffers;
02888   uint32_t itsource;
02889   uint32_t itflag;
02890
02891   TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
02892   TxEventFifoITs &= hfdcan->Instance->IE;
02893   RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
02894   RxFifo0ITs &= hfdcan->Instance->IE;
02895   RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
02896   RxFifo1ITs &= hfdcan->Instance->IE;
02897   Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
02898   Errors &= hfdcan->Instance->IE;
02899   ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
02900   ErrorStatusITs &= hfdcan->Instance->IE;
02901   itsource = hfdcan->Instance->IE;
02902   itflag = hfdcan->Instance->IR;
02903
02904   /* High Priority Message interrupt management *******************************/
02905   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
02906   {
02907     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
02908     {
02909       /* Clear the High Priority Message flag */
02910       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
02911
02912 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02913       /* Call registered callback*/
02914       hfdcan->HighPriorityMessageCallback(hfdcan);
02915 #else
02916       /* High Priority Message Callback */
02917       HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
02918 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02919     }
02920   }
02921
02922   /* Transmission Abort interrupt management **********************************/
02923   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
02924   {
02925     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
02926     {
02927       /* List of aborted monitored buffers */
02928       AbortedBuffers = hfdcan->Instance->TXBCF;
02929       AbortedBuffers &= hfdcan->Instance->TXBCIE;
02930
02931       /* Clear the Transmission Cancellation flag */
02932       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
02933
02934 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02935       /* Call registered callback*/
02936       hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
02937 #else
02938       /* Transmission Cancellation Callback */
02939       HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
02940 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02941     }
02942   }
02943
02944   /* Tx event FIFO interrupts management **************************************/
02945   if (TxEventFifoITs != 0U)
02946   {
02947     /* Clear the Tx Event FIFO flags */
02948     __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
02949
02950 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02951     /* Call registered callback*/
02952     hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
02953 #else
02954     /* Tx Event FIFO Callback */
02955     HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
02956 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02957   }
02958
02959   /* Rx FIFO 0 interrupts management ******************************************/
02960   if (RxFifo0ITs != 0U)
02961   {
02962     /* Clear the Rx FIFO 0 flags */
02963     __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
02964
02965 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02966     /* Call registered callback*/
02967     hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
02968 #else
02969     /* Rx FIFO 0 Callback */
02970     HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
02971 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02972   }
02973
02974   /* Rx FIFO 1 interrupts management ******************************************/
02975   if (RxFifo1ITs != 0U)
02976   {
02977     /* Clear the Rx FIFO 1 flags */
02978     __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
02979
02980 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02981     /* Call registered callback*/
02982     hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
02983 #else
02984     /* Rx FIFO 1 Callback */
02985     HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
02986 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
02987   }
02988
02989   /* Tx FIFO empty interrupt management ***************************************/
02990   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
02991   {
02992     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
02993     {
02994       /* Clear the Tx FIFO empty flag */
02995       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
02996
02997 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
02998       /* Call registered callback*/
02999       hfdcan->TxFifoEmptyCallback(hfdcan);
03000 #else
03001       /* Tx FIFO empty Callback */
03002       HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
03003 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03004     }
03005   }
03006
03007   /* Transmission Complete interrupt management *******************************/
03008   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_COMPLETE) != RESET)
03009   {
03010     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_COMPLETE) != RESET)
03011     {
03012       /* List of transmitted monitored buffers */
03013       TransmittedBuffers = hfdcan->Instance->TXBTO;
03014       TransmittedBuffers &= hfdcan->Instance->TXBTIE;
03015
03016       /* Clear the Transmission Complete flag */
03017       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
03018
03019 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03020       /* Call registered callback*/
03021       hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
03022 #else
03023       /* Transmission Complete Callback */
03024       HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
03025 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03026     }
03027   }
03028
03029   /* Timestamp Wraparound interrupt management ********************************/
03030   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
03031   {
03032     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
03033     {
03034       /* Clear the Timestamp Wraparound flag */
03035       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
03036
03037 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03038       /* Call registered callback*/
03039       hfdcan->TimestampWraparoundCallback(hfdcan);
03040 #else
03041       /* Timestamp Wraparound Callback */
03042       HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
03043 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03044     }
03045   }
03046
03047   /* Timeout Occurred interrupt management ************************************/
03048   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
03049   {
03050     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
03051     {
03052       /* Clear the Timeout Occurred flag */
03053       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
03054
03055 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03056       /* Call registered callback*/
03057       hfdcan->TimeoutOccurredCallback(hfdcan);
03058 #else
03059       /* Timeout Occurred Callback */
03060       HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
03061 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03062     }
03063   }
03064
03065   /* Message RAM access failure interrupt management **************************/
03066   if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
03067   {
03068     if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
03069     {
03070       /* Clear the Message RAM access failure flag */
03071       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
03072
03073       /* Update error code */
03074       hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
03075     }
03076   }
03077
03078   /* Error Status interrupts management ***************************************/
03079   if (ErrorStatusITs != 0U)
03080   {
03081     /* Clear the Error flags */
03082     __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
03083
03084 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03085     /* Call registered callback*/
03086     hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
03087 #else
03088     /* Error Status Callback */
03089     HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
03090 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03091   }
03092
03093   /* Error interrupts management **********************************************/
03094   if (Errors != 0U)
03095   {
03096     /* Clear the Error flags */
03097     __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
03098
03099     /* Update error code */
03100     hfdcan->ErrorCode |= Errors;
03101   }
03102
03103   if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
03104   {
03105 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
03106     /* Call registered callback*/
03107     hfdcan->ErrorCallback(hfdcan);
03108 #else
03109     /* Error Callback */
03110     HAL_FDCAN_ErrorCallback(hfdcan);
03111 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
03112   }
03113 }
03114
03115 /**
03116   * @}
03117   */
03118
03119 /** @defgroup FDCAN_Exported_Functions_Group5 Callback functions
03120   *  @brief   FDCAN Callback functions
03121   *
03122 @verbatim
03123   ==============================================================================
03124                           ##### Callback functions #####
03125   ==============================================================================
03126     [..]
03127     This subsection provides the following callback functions:
03128       (+) HAL_FDCAN_TxEventFifoCallback
03129       (+) HAL_FDCAN_RxFifo0Callback
03130       (+) HAL_FDCAN_RxFifo1Callback
03131       (+) HAL_FDCAN_TxFifoEmptyCallback
03132       (+) HAL_FDCAN_TxBufferCompleteCallback
03133       (+) HAL_FDCAN_TxBufferAbortCallback
03134       (+) HAL_FDCAN_HighPriorityMessageCallback
03135       (+) HAL_FDCAN_TimestampWraparoundCallback
03136       (+) HAL_FDCAN_TimeoutOccurredCallback
03137       (+) HAL_FDCAN_ErrorCallback
03138       (+) HAL_FDCAN_ErrorStatusCallback
03139
03140 @endverbatim
03141   * @{
03142   */
03143
03144 /**
03145   * @brief  Tx Event callback.
03146   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03147   *         the configuration information for the specified FDCAN.
03148   * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled.
03149   *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
03150   * @retval None
03151   */
03152 __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
03153 {
03154   /* Prevent unused argument(s) compilation warning */
03155   UNUSED(hfdcan);
03156   UNUSED(TxEventFifoITs);
03157
03158   /* NOTE : This function Should not be modified, when the callback is needed,
03159             the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
03160    */
03161 }
03162
03163 /**
03164   * @brief  Rx FIFO 0 callback.
03165   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03166   *         the configuration information for the specified FDCAN.
03167   * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled.
03168   *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
03169   * @retval None
03170   */
03171 __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
03172 {
03173   /* Prevent unused argument(s) compilation warning */
03174   UNUSED(hfdcan);
03175   UNUSED(RxFifo0ITs);
03176
03177   /* NOTE : This function Should not be modified, when the callback is needed,
03178             the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
03179    */
03180 }
03181
03182 /**
03183   * @brief  Rx FIFO 1 callback.
03184   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03185   *         the configuration information for the specified FDCAN.
03186   * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled.
03187   *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
03188   * @retval None
03189   */
03190 __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
03191 {
03192   /* Prevent unused argument(s) compilation warning */
03193   UNUSED(hfdcan);
03194   UNUSED(RxFifo1ITs);
03195
03196   /* NOTE : This function Should not be modified, when the callback is needed,
03197             the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
03198    */
03199 }
03200
03201 /**
03202   * @brief  Tx FIFO Empty callback.
03203   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03204   *         the configuration information for the specified FDCAN.
03205   * @retval None
03206   */
03207 __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
03208 {
03209   /* Prevent unused argument(s) compilation warning */
03210   UNUSED(hfdcan);
03211
03212   /* NOTE : This function Should not be modified, when the callback is needed,
03213             the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
03214    */
03215 }
03216
03217 /**
03218   * @brief  Transmission Complete callback.
03219   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03220   *         the configuration information for the specified FDCAN.
03221   * @param  BufferIndexes Indexes of the transmitted buffers.
03222   *         This parameter can be any combination of @arg FDCAN_Tx_location.
03223   * @retval None
03224   */
03225 __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
03226 {
03227   /* Prevent unused argument(s) compilation warning */
03228   UNUSED(hfdcan);
03229   UNUSED(BufferIndexes);
03230
03231   /* NOTE : This function Should not be modified, when the callback is needed,
03232             the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
03233    */
03234 }
03235
03236 /**
03237   * @brief  Transmission Cancellation callback.
03238   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03239   *         the configuration information for the specified FDCAN.
03240   * @param  BufferIndexes Indexes of the aborted buffers.
03241   *         This parameter can be any combination of @arg FDCAN_Tx_location.
03242   * @retval None
03243   */
03244 __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
03245 {
03246   /* Prevent unused argument(s) compilation warning */
03247   UNUSED(hfdcan);
03248   UNUSED(BufferIndexes);
03249
03250   /* NOTE : This function Should not be modified, when the callback is needed,
03251             the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
03252    */
03253 }
03254
03255 /**
03256   * @brief  Timestamp Wraparound callback.
03257   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03258   *         the configuration information for the specified FDCAN.
03259   * @retval None
03260   */
03261 __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
03262 {
03263   /* Prevent unused argument(s) compilation warning */
03264   UNUSED(hfdcan);
03265
03266   /* NOTE : This function Should not be modified, when the callback is needed,
03267             the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
03268    */
03269 }
03270
03271 /**
03272   * @brief  Timeout Occurred callback.
03273   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03274   *         the configuration information for the specified FDCAN.
03275   * @retval None
03276   */
03277 __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
03278 {
03279   /* Prevent unused argument(s) compilation warning */
03280   UNUSED(hfdcan);
03281
03282   /* NOTE : This function Should not be modified, when the callback is needed,
03283             the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
03284    */
03285 }
03286
03287 /**
03288   * @brief  High Priority Message callback.
03289   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03290   *         the configuration information for the specified FDCAN.
03291   * @retval None
03292   */
03293 __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
03294 {
03295   /* Prevent unused argument(s) compilation warning */
03296   UNUSED(hfdcan);
03297
03298   /* NOTE : This function Should not be modified, when the callback is needed,
03299             the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
03300    */
03301 }
03302
03303 /**
03304   * @brief  Error callback.
03305   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03306   *         the configuration information for the specified FDCAN.
03307   * @retval None
03308   */
03309 __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
03310 {
03311   /* Prevent unused argument(s) compilation warning */
03312   UNUSED(hfdcan);
03313
03314   /* NOTE : This function Should not be modified, when the callback is needed,
03315             the HAL_FDCAN_ErrorCallback could be implemented in the user file
03316    */
03317 }
03318
03319 /**
03320   * @brief  Error status callback.
03321   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03322   *         the configuration information for the specified FDCAN.
03323   * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
03324   *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
03325   * @retval None
03326   */
03327 __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
03328 {
03329   /* Prevent unused argument(s) compilation warning */
03330   UNUSED(hfdcan);
03331   UNUSED(ErrorStatusITs);
03332
03333   /* NOTE : This function Should not be modified, when the callback is needed,
03334             the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
03335    */
03336 }
03337
03338 /**
03339   * @}
03340   */
03341
03342 /** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions
03343   *  @brief   FDCAN Peripheral State functions
03344   *
03345 @verbatim
03346   ==============================================================================
03347                       ##### Peripheral State functions #####
03348   ==============================================================================
03349     [..]
03350     This subsection provides functions allowing to :
03351       (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
03352       (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
03353
03354 @endverbatim
03355   * @{
03356   */
03357 /**
03358   * @brief  Return the FDCAN state
03359   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03360   *         the configuration information for the specified FDCAN.
03361   * @retval HAL state
03362   */
03363 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
03364 {
03365   /* Return FDCAN state */
03366   return hfdcan->State;
03367 }
03368
03369 /**
03370   * @brief  Return the FDCAN error code
03371   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03372   *         the configuration information for the specified FDCAN.
03373   * @retval FDCAN Error Code
03374   */
03375 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
03376 {
03377   /* Return FDCAN error code */
03378   return hfdcan->ErrorCode;
03379 }
03380
03381 /**
03382   * @}
03383   */
03384
03385 /**
03386   * @}
03387   */
03388
03389 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions
03390   * @{
03391   */
03392
03393 /**
03394   * @brief  Calculate each RAM block start address and size
03395   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03396   *         the configuration information for the specified FDCAN.
03397   * @retval none
03398  */
03399 static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
03400 {
03401   uint32_t RAMcounter;
03402   uint32_t SramCanInstanceBase = SRAMCAN_BASE;
03403 #if defined(FDCAN2)
03404
03405   if (hfdcan->Instance == FDCAN2)
03406   {
03407     SramCanInstanceBase += SRAMCAN_SIZE;
03408   }
03409 #endif /* FDCAN2 */
03410
03411   /* Standard filter list start address */
03412   hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA;
03413
03414   /* Standard filter elements number */
03415   MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos));
03416
03417   /* Extended filter list start address */
03418   hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA;
03419
03420   /* Extended filter elements number */
03421   MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos));
03422
03423   /* Rx FIFO 0 start address */
03424   hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA;
03425
03426   /* Rx FIFO 1 start address */
03427   hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA;
03428
03429   /* Tx event FIFO start address */
03430   hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA;
03431
03432   /* Tx FIFO/queue start address */
03433   hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA;
03434
03435   /* Flush the allocated Message RAM area */
03436   for (RAMcounter = SramCanInstanceBase; RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U)
03437   {
03438     *(uint32_t *)(RAMcounter) = 0x00000000U;
03439   }
03440 }
03441
03442 /**
03443   * @brief  Copy Tx message to the message RAM.
03444   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
03445   *         the configuration information for the specified FDCAN.
03446   * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
03447   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
03448   * @param  BufferIndex index of the buffer to be configured.
03449   * @retval none
03450  */
03451 static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
03452                                    uint32_t BufferIndex)
03453 {
03454   uint32_t TxElementW1;
03455   uint32_t TxElementW2;
03456   uint32_t *TxAddress;
03457   uint32_t ByteCounter;
03458
03459   /* Build first word of Tx header element */
03460   if (pTxHeader->IdType == FDCAN_STANDARD_ID)
03461   {
03462     TxElementW1 = (pTxHeader->ErrorStateIndicator |
03463                    FDCAN_STANDARD_ID |
03464                    pTxHeader->TxFrameType |
03465                    (pTxHeader->Identifier << 18U));
03466   }
03467   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
03468   {
03469     TxElementW1 = (pTxHeader->ErrorStateIndicator |
03470                    FDCAN_EXTENDED_ID |
03471                    pTxHeader->TxFrameType |
03472                    pTxHeader->Identifier);
03473   }
03474
03475   /* Build second word of Tx header element */
03476   TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
03477                  pTxHeader->TxEventFifoControl |
03478                  pTxHeader->FDFormat |
03479                  pTxHeader->BitRateSwitch |
03480                  pTxHeader->DataLength);
03481
03482   /* Calculate Tx element address */
03483   TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
03484
03485   /* Write Tx element header to the message RAM */
03486   *TxAddress = TxElementW1;
03487   TxAddress++;
03488   *TxAddress = TxElementW2;
03489   TxAddress++;
03490
03491   /* Write Tx payload to the message RAM */
03492   for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U)
03493   {
03494     *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
03495                   ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
03496                   ((uint32_t)pTxData[ByteCounter + 1U] << 8U)  |
03497                   (uint32_t)pTxData[ByteCounter]);
03498     TxAddress++;
03499   }
03500 }
03501
03502 /**
03503   * @}
03504   */
03505 #endif /* HAL_FDCAN_MODULE_ENABLED */
03506 /**
03507   * @}
03508   */
03509
03510 /**
03511   * @}
03512   */
03513
03514 #endif /* FDCAN1 */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_fdcan.h Source File

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stm32g0xx_hal_fdcan.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_fdcan.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FDCAN HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_FDCAN_H
00021 #define STM32G0xx_HAL_FDCAN_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 #if defined(FDCAN1)
00031
00032 /** @addtogroup STM32G0xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup FDCAN
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief HAL State structures definition
00047   */
00048 typedef enum
00049 {
00050   HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
00051   HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
00052   HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
00053   HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
00054 } HAL_FDCAN_StateTypeDef;
00055
00056 /**
00057   * @brief FDCAN Init structure definition
00058   */
00059 typedef struct
00060 {
00061   uint32_t ClockDivider;                 /*!< Specifies the FDCAN kernel clock divider.
00062                                               The clock is common to all FDCAN instances.
00063                                               This parameter is applied only at initialisation of
00064                                               first FDCAN instance.
00065                                               This parameter can be a value of @ref FDCAN_clock_divider.   */
00066
00067   uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
00068                                               This parameter can be a value of @ref FDCAN_frame_format     */
00069
00070   uint32_t Mode;                         /*!< Specifies the FDCAN mode.
00071                                               This parameter can be a value of @ref FDCAN_operating_mode   */
00072
00073   FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
00074                                               This parameter can be set to ENABLE or DISABLE               */
00075
00076   FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
00077                                               This parameter can be set to ENABLE or DISABLE               */
00078
00079   FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
00080                                               This parameter can be set to ENABLE or DISABLE               */
00081
00082   uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
00083                                               divided for generating the nominal bit time quanta.
00084                                               This parameter must be a number between 1 and 512            */
00085
00086   uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
00087                                               hardware is allowed to lengthen or shorten a bit to perform
00088                                               resynchronization.
00089                                               This parameter must be a number between 1 and 128            */
00090
00091   uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
00092                                               This parameter must be a number between 2 and 256            */
00093
00094   uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
00095                                               This parameter must be a number between 2 and 128            */
00096
00097   uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
00098                                               divided for generating the data bit time quanta.
00099                                               This parameter must be a number between 1 and 32             */
00100
00101   uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
00102                                               hardware is allowed to lengthen or shorten a data bit to
00103                                               perform resynchronization.
00104                                               This parameter must be a number between 1 and 16             */
00105
00106   uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
00107                                               This parameter must be a number between 1 and 32             */
00108
00109   uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
00110                                               This parameter must be a number between 1 and 16             */
00111
00112   uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
00113                                               This parameter must be a number between 0 and 28             */
00114
00115   uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
00116                                               This parameter must be a number between 0 and 8             */
00117
00118   uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
00119                                               This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
00120
00121 } FDCAN_InitTypeDef;
00122
00123 /**
00124   * @brief  FDCAN filter structure definition
00125   */
00126 typedef struct
00127 {
00128   uint32_t IdType;           /*!< Specifies the identifier type.
00129                                   This parameter can be a value of @ref FDCAN_id_type       */
00130
00131   uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
00132                                   This parameter must be a number between:
00133                                    - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
00134                                    - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */
00135
00136   uint32_t FilterType;       /*!< Specifies the filter type.
00137                                   This parameter can be a value of @ref FDCAN_filter_type.
00138                                   The value FDCAN_FILTER_RANGE_NO_EIDM is permitted
00139                                   only when IdType is FDCAN_EXTENDED_ID.                    */
00140
00141   uint32_t FilterConfig;     /*!< Specifies the filter configuration.
00142                                   This parameter can be a value of @ref FDCAN_filter_config */
00143
00144   uint32_t FilterID1;        /*!< Specifies the filter identification 1.
00145                                   This parameter must be a number between:
00146                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00147                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
00148
00149   uint32_t FilterID2;        /*!< Specifies the filter identification 2.
00150                                   This parameter must be a number between:
00151                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00152                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
00153
00154 } FDCAN_FilterTypeDef;
00155
00156 /**
00157   * @brief  FDCAN Tx header structure definition
00158   */
00159 typedef struct
00160 {
00161   uint32_t Identifier;          /*!< Specifies the identifier.
00162                                      This parameter must be a number between:
00163                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00164                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00165
00166   uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
00167                                      transmitted.
00168                                      This parameter can be a value of @ref FDCAN_id_type               */
00169
00170   uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
00171                                      This parameter can be a value of @ref FDCAN_frame_type            */
00172
00173   uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
00174                                       This parameter can be a value of @ref FDCAN_data_length_code     */
00175
00176   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
00177                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
00178
00179   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
00180                                      bit rate switching.
00181                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00182
00183   uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
00184                                      FD format.
00185                                      This parameter can be a value of @ref FDCAN_format                */
00186
00187   uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
00188                                      This parameter can be a value of @ref FDCAN_EFC                   */
00189
00190   uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
00191                                      element for identification of Tx message status.
00192                                      This parameter must be a number between 0 and 0xFF                */
00193
00194 } FDCAN_TxHeaderTypeDef;
00195
00196 /**
00197   * @brief  FDCAN Rx header structure definition
00198   */
00199 typedef struct
00200 {
00201   uint32_t Identifier;            /*!< Specifies the identifier.
00202                                        This parameter must be a number between:
00203                                         - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00204                                         - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00205
00206   uint32_t IdType;                /*!< Specifies the identifier type of the received message.
00207                                        This parameter can be a value of @ref FDCAN_id_type               */
00208
00209   uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
00210                                        This parameter can be a value of @ref FDCAN_frame_type            */
00211
00212   uint32_t DataLength;            /*!< Specifies the received frame length.
00213                                         This parameter can be a value of @ref FDCAN_data_length_code     */
00214
00215   uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
00216                                        This parameter can be a value of @ref FDCAN_error_state_indicator */
00217
00218   uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
00219                                        rate switching.
00220                                        This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00221
00222   uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
00223                                        format.
00224                                        This parameter can be a value of @ref FDCAN_format                */
00225
00226   uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
00227                                        reception.
00228                                        This parameter must be a number between 0 and 0xFFFF              */
00229
00230   uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
00231                                        This parameter must be a number between:
00232                                         - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
00233                                         - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID
00234                                        When the frame is a Non-Filter matching frame, this parameter
00235                                        is unused.                                                        */
00236
00237   uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
00238                                        Acceptance of non-matching frames may be enabled via
00239                                        HAL_FDCAN_ConfigGlobalFilter().
00240                                        This parameter takes 0 if the frame matched an Rx filter or
00241                                        1 if it did not match any Rx filter                               */
00242
00243 } FDCAN_RxHeaderTypeDef;
00244
00245 /**
00246   * @brief  FDCAN Tx event FIFO structure definition
00247   */
00248 typedef struct
00249 {
00250   uint32_t Identifier;          /*!< Specifies the identifier.
00251                                      This parameter must be a number between:
00252                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
00253                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
00254
00255   uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
00256                                      This parameter can be a value of @ref FDCAN_id_type               */
00257
00258   uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
00259                                      This parameter can be a value of @ref FDCAN_frame_type            */
00260
00261   uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
00262                                      This parameter can be a value of @ref FDCAN_data_length_code      */
00263
00264   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
00265                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
00266
00267   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
00268                                      rate switching.
00269                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
00270
00271   uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
00272                                      format.
00273                                      This parameter can be a value of @ref FDCAN_format                */
00274
00275   uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
00276                                      transmission.
00277                                      This parameter must be a number between 0 and 0xFFFF              */
00278
00279   uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
00280                                      for identification of Tx message status.
00281                                      This parameter must be a number between 0 and 0xFF                */
00282
00283   uint32_t EventType;           /*!< Specifies the event type.
00284                                      This parameter can be a value of @ref FDCAN_event_type            */
00285
00286 } FDCAN_TxEventFifoTypeDef;
00287
00288 /**
00289   * @brief  FDCAN High Priority Message Status structure definition
00290   */
00291 typedef struct
00292 {
00293   uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
00294                                 This parameter can be:
00295                                  - 0 : Standard Filter List
00296                                  - 1 : Extended Filter List                                */
00297
00298   uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
00299                                 This parameter can be a number between:
00300                                 - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard)
00301                                 - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */
00302
00303   uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
00304                                 This parameter can be a value of @ref FDCAN_hp_msg_storage */
00305
00306   uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
00307                                 message was stored.
00308                                 This parameter is valid only when MessageStorage is:
00309                                   FDCAN_HP_STORAGE_RXFIFO0
00310                                  or
00311                                   FDCAN_HP_STORAGE_RXFIFO1                                 */
00312
00313 } FDCAN_HpMsgStatusTypeDef;
00314
00315 /**
00316   * @brief FDCAN Protocol Status structure definition
00317   */
00318 typedef struct
00319 {
00320   uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
00321                                    This parameter can be a value of @ref FDCAN_protocol_error_code */
00322
00323   uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
00324                                    of a CAN FD format frame with its BRS flag set.
00325                                    This parameter can be a value of @ref FDCAN_protocol_error_code */
00326
00327   uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
00328                                    This parameter can be a value of @ref FDCAN_communication_state */
00329
00330   uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
00331                                    This parameter can be:
00332                                     - 0 : The FDCAN is in Error_Active state
00333                                     - 1 : The FDCAN is in Error_Passive state */
00334
00335   uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
00336                                    This parameter can be:
00337                                     - 0 : error counters (RxErrorCnt and TxErrorCnt)
00338                                           are below the Error_Warning limit of 96
00339                                     - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
00340
00341   uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
00342                                    This parameter can be:
00343                                     - 0 : The FDCAN is not in Bus_Off state
00344                                     - 1 : The FDCAN is in Bus_Off state */
00345
00346   uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
00347                                    This parameter can be:
00348                                     - 0 : Last received CAN FD message did not have its ESI flag set
00349                                     - 1 : Last received CAN FD message had its ESI flag set */
00350
00351   uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
00352                                    This parameter can be:
00353                                     - 0 : Last received CAN FD message did not have its BRS flag set
00354                                     - 1 : Last received CAN FD message had its BRS flag set */
00355
00356   uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received
00357                                    since last protocol status.This parameter can be:
00358                                     - 0 : No CAN FD message received
00359                                     - 1 : CAN FD message received */
00360
00361   uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
00362                                    This parameter can be:
00363                                     - 0 : No protocol exception event occurred since last read access
00364                                     - 1 : Protocol exception event occurred */
00365
00366   uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
00367                                    This parameter can be a number between 0 and 127 */
00368
00369 } FDCAN_ProtocolStatusTypeDef;
00370
00371 /**
00372   * @brief FDCAN Error Counters structure definition
00373   */
00374 typedef struct
00375 {
00376   uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
00377                                 This parameter can be a number between 0 and 255 */
00378
00379   uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
00380                                 This parameter can be a number between 0 and 127 */
00381
00382   uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
00383                                 This parameter can be:
00384                                  - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
00385                                  - 1 : The Receive Error Counter (RxErrorCnt)
00386                                        has reached the error passive level of 128 */
00387
00388   uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
00389                                 This parameter can be a number between 0 and 255.
00390                                 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
00391                                 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
00392                                 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
00393
00394 } FDCAN_ErrorCountersTypeDef;
00395
00396 /**
00397   * @brief  FDCAN Message RAM blocks
00398   */
00399 typedef struct
00400 {
00401   uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
00402                                   This parameter must be a 32-bit word address      */
00403
00404   uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
00405                                   This parameter must be a 32-bit word address      */
00406
00407   uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
00408                                   This parameter must be a 32-bit word address      */
00409
00410   uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
00411                                   This parameter must be a 32-bit word address      */
00412
00413   uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
00414                                   This parameter must be a 32-bit word address      */
00415
00416   uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
00417                                   This parameter must be a 32-bit word address      */
00418
00419 } FDCAN_MsgRamAddressTypeDef;
00420
00421 /**
00422   * @brief  FDCAN handle structure definition
00423   */
00424 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00425 typedef struct __FDCAN_HandleTypeDef
00426 #else
00427 typedef struct
00428 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00429 {
00430   FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
00431
00432   FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
00433
00434   FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
00435
00436   uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
00437                                                of latest Tx FIFO/Queue request */
00438
00439   __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
00440
00441   HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
00442
00443   __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
00444
00445 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00446   void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);     /*!< FDCAN Tx Event Fifo callback         */
00447   void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);             /*!< FDCAN Rx Fifo 0 callback             */
00448   void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);             /*!< FDCAN Rx Fifo 1 callback             */
00449   void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                              /*!< FDCAN Tx Fifo Empty callback         */
00450   void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback    */
00451   void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);    /*!< FDCAN Tx Buffer abort callback       */
00452   void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                      /*!< FDCAN High priority message callback */
00453   void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                      /*!< FDCAN Timestamp wraparound callback  */
00454   void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                          /*!< FDCAN Timeout occurred callback      */
00455   void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                    /*!< FDCAN Error callback                 */
00456   void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);     /*!< FDCAN Error status callback          */
00457
00458   void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Msp Init callback              */
00459   void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                /*!< FDCAN Msp DeInit callback            */
00460
00461 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00462
00463 } FDCAN_HandleTypeDef;
00464
00465 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00466 /**
00467   * @brief  HAL FDCAN common Callback ID enumeration definition
00468   */
00469 typedef enum
00470 {
00471   HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U,    /*!< FDCAN Tx Fifo Empty callback ID         */
00472   HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x01U,    /*!< FDCAN High priority message callback ID */
00473   HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U,    /*!< FDCAN Timestamp wraparound callback ID  */
00474   HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x03U,    /*!< FDCAN Timeout occurred callback ID      */
00475   HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x04U,    /*!< FDCAN Error callback ID                 */
00476
00477   HAL_FDCAN_MSPINIT_CB_ID              = 0x05U,    /*!< FDCAN MspInit callback ID               */
00478   HAL_FDCAN_MSPDEINIT_CB_ID            = 0x06U,    /*!< FDCAN MspDeInit callback ID             */
00479
00480 } HAL_FDCAN_CallbackIDTypeDef;
00481
00482 /**
00483   * @brief  HAL FDCAN Callback pointer definition
00484   */
00485 typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                         /*!< pointer to a common FDCAN callback function           */
00486 typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);     /*!< pointer to Tx event Fifo FDCAN callback function      */
00487 typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);             /*!< pointer to Rx Fifo 0 FDCAN callback function          */
00488 typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);             /*!< pointer to Rx Fifo 1 FDCAN callback function          */
00489 typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */
00490 typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);    /*!< pointer to Tx Buffer abort FDCAN callback function    */
00491 typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);     /*!< pointer to Error Status callback function             */
00492
00493 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00494
00495 /**
00496   * @}
00497   */
00498
00499 /* Exported constants --------------------------------------------------------*/
00500 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
00501   * @{
00502   */
00503
00504 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
00505   * @{
00506   */
00507 #define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
00508 #define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
00509 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
00510 #define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
00511 #define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
00512 #define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
00513 #define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
00514 #define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
00515 #define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
00516 #define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
00517 #define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
00518 #define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
00519 #define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
00520 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
00521 #define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
00522 #define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
00523
00524 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
00525 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
00526 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
00527 /**
00528   * @}
00529   */
00530
00531 /** @defgroup FDCAN_frame_format FDCAN Frame Format
00532   * @{
00533   */
00534 #define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
00535 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
00536 #define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode
00542   * @{
00543   */
00544 #define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
00545 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
00546 #define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
00547 #define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
00548 #define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
00549 /**
00550   * @}
00551   */
00552
00553 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider
00554   * @{
00555   */
00556 #define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
00557 #define FDCAN_CLOCK_DIV2  ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2  */
00558 #define FDCAN_CLOCK_DIV4  ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4  */
00559 #define FDCAN_CLOCK_DIV6  ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6  */
00560 #define FDCAN_CLOCK_DIV8  ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8  */
00561 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
00562 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
00563 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
00564 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
00565 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
00566 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
00567 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
00568 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
00569 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
00570 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
00571 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
00572 /**
00573   * @}
00574   */
00575
00576 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
00577   * @{
00578   */
00579 #define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
00580 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
00581 /**
00582   * @}
00583   */
00584
00585 /** @defgroup FDCAN_id_type FDCAN ID Type
00586   * @{
00587   */
00588 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
00589 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
00590 /**
00591   * @}
00592   */
00593
00594 /** @defgroup FDCAN_frame_type FDCAN Frame Type
00595   * @{
00596   */
00597 #define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
00598 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code
00604   * @{
00605   */
00606 #define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
00607 #define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
00608 #define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
00609 #define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
00610 #define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
00611 #define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
00612 #define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
00613 #define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
00614 #define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
00615 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
00616 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
00617 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
00618 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
00619 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
00620 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
00621 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
00622 /**
00623   * @}
00624   */
00625
00626 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
00627   * @{
00628   */
00629 #define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
00630 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
00636   * @{
00637   */
00638 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
00639 #define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
00640 /**
00641   * @}
00642   */
00643
00644 /** @defgroup FDCAN_format FDCAN format
00645   * @{
00646   */
00647 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
00648 #define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup FDCAN_EFC FDCAN Event FIFO control
00654   * @{
00655   */
00656 #define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
00657 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup FDCAN_filter_type FDCAN Filter Type
00663   * @{
00664   */
00665 #define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
00666 #define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
00667 #define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
00668 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
00669 /**
00670   * @}
00671   */
00672
00673 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration
00674   * @{
00675   */
00676 #define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
00677 #define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
00678 #define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
00679 #define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
00680 #define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
00681 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
00682 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
00683 /**
00684   * @}
00685   */
00686
00687 /** @defgroup FDCAN_Tx_location FDCAN Tx Location
00688   * @{
00689   */
00690 #define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
00691 #define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
00692 #define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
00693 /**
00694   * @}
00695   */
00696
00697 /** @defgroup FDCAN_Rx_location FDCAN Rx Location
00698   * @{
00699   */
00700 #define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
00701 #define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
00702 /**
00703   * @}
00704   */
00705
00706 /** @defgroup FDCAN_event_type FDCAN Event Type
00707   * @{
00708   */
00709 #define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
00710 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
00716   * @{
00717   */
00718 #define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
00719 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
00720 #define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
00721 #define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
00722 /**
00723   * @}
00724   */
00725
00726 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
00727   * @{
00728   */
00729 #define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
00730 #define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
00731 #define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
00732 #define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
00733 #define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
00734 #define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
00735 #define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
00736 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
00737 /**
00738   * @}
00739   */
00740
00741 /** @defgroup FDCAN_communication_state FDCAN communication state
00742   * @{
00743   */
00744 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
00745 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
00746 #define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
00747 #define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
00748 /**
00749   * @}
00750   */
00751
00752 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
00753   * @{
00754   */
00755 #define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
00756 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
00757 /**
00758   * @}
00759   */
00760
00761 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
00762   * @{
00763   */
00764 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
00765 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
00766 #define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
00767 /**
00768   * @}
00769   */
00770
00771 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
00772   * @{
00773   */
00774 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
00775 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
00776 /**
00777   * @}
00778   */
00779
00780 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
00781   * @{
00782   */
00783 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
00784 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
00785 /**
00786   * @}
00787   */
00788
00789 /** @defgroup FDCAN_Timestamp FDCAN timestamp
00790   * @{
00791   */
00792 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
00793 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
00794 /**
00795   * @}
00796   */
00797
00798 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
00799   * @{
00800   */
00801 #define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
00802 #define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2  */
00803 #define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3  */
00804 #define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4  */
00805 #define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5  */
00806 #define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6  */
00807 #define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7  */
00808 #define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8  */
00809 #define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9  */
00810 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
00811 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
00812 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
00813 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
00814 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
00815 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
00816 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
00817 /**
00818   * @}
00819   */
00820
00821 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
00822   * @{
00823   */
00824 #define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
00825 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
00826 #define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
00827 #define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
00828 /**
00829   * @}
00830   */
00831
00832 /** @defgroup Interrupt_Masks Interrupt masks
00833   * @{
00834   */
00835 #define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */
00836 #define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */
00837 /**
00838   * @}
00839   */
00840
00841 /** @defgroup FDCAN_flags FDCAN Flags
00842   * @{
00843   */
00844 #define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
00845 #define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
00846 #define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
00847 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
00848 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
00849 #define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
00850 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
00851 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
00852 #define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
00853 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
00854 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
00855 #define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
00856 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
00857 #define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
00858 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
00859 #define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
00860 #define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
00861 #define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
00862 #define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
00863 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
00864 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
00865 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
00866 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
00867 #define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
00868 /**
00869   * @}
00870   */
00871
00872 /** @defgroup FDCAN_Interrupts FDCAN Interrupts
00873   * @{
00874   */
00875
00876 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
00877   * @{
00878   */
00879 #define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
00880 #define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
00881 #define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
00882 /**
00883   * @}
00884   */
00885
00886 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
00887   * @{
00888   */
00889 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
00890 /**
00891   * @}
00892   */
00893
00894 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
00895   * @{
00896   */
00897 #define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
00898 #define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
00899 /**
00900   * @}
00901   */
00902
00903 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
00904   * @{
00905   */
00906 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
00907 #define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
00908 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
00909 /**
00910   * @}
00911   */
00912
00913 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
00914   * @{
00915   */
00916 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
00917 #define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
00918 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
00919 /**
00920   * @}
00921   */
00922
00923 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
00924   * @{
00925   */
00926 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
00927 #define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
00928 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
00929 /**
00930   * @}
00931   */
00932
00933 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
00934   * @{
00935   */
00936 #define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
00937 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
00938 #define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
00939 #define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
00940 #define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
00941 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
00942 /**
00943   * @}
00944   */
00945
00946 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
00947   * @{
00948   */
00949 #define FDCAN_IT_ERROR_PASSIVE           FDCAN_IE_EPE   /*!< Error_Passive status changed      */
00950 #define FDCAN_IT_ERROR_WARNING           FDCAN_IE_EWE   /*!< Error_Warning status changed      */
00951 #define FDCAN_IT_BUS_OFF                 FDCAN_IE_BOE   /*!< Bus_Off status changed            */
00952 /**
00953   * @}
00954   */
00955
00956 /**
00957   * @}
00958   */
00959
00960 /** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List
00961   * @{
00962   */
00963 #define FDCAN_IT_LIST_RX_FIFO0         (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \
00964                                         FDCAN_IT_RX_FIFO0_FULL         | \
00965                                         FDCAN_IT_RX_FIFO0_NEW_MESSAGE)       /*!< RX FIFO 0 Interrupts List          */
00966 #define FDCAN_IT_LIST_RX_FIFO1         (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \
00967                                         FDCAN_IT_RX_FIFO1_FULL         | \
00968                                         FDCAN_IT_RX_FIFO1_NEW_MESSAGE)       /*!< RX FIFO 1 Interrupts List          */
00969 #define FDCAN_IT_LIST_SMSG             (FDCAN_IT_TX_ABORT_COMPLETE | \
00970                                         FDCAN_IT_TX_COMPLETE | \
00971                                         FDCAN_IT_RX_HIGH_PRIORITY_MSG)       /*!< Status Message Interrupts List     */
00972 #define FDCAN_IT_LIST_TX_FIFO_ERROR    (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \
00973                                         FDCAN_IT_TX_EVT_FIFO_FULL | \
00974                                         FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
00975                                         FDCAN_IT_TX_FIFO_EMPTY)              /*!< TX FIFO Error Interrupts List      */
00976 #define FDCAN_IT_LIST_MISC             (FDCAN_IT_TIMEOUT_OCCURRED | \
00977                                         FDCAN_IT_RAM_ACCESS_FAILURE | \
00978                                         FDCAN_IT_TIMESTAMP_WRAPAROUND)       /*!< Misc. Interrupts List              */
00979 #define FDCAN_IT_LIST_BIT_LINE_ERROR   (FDCAN_IT_ERROR_PASSIVE | \
00980                                         FDCAN_IT_ERROR_LOGGING_OVERFLOW)     /*!< Bit and Line Error Interrupts List */
00981 #define FDCAN_IT_LIST_PROTOCOL_ERROR   (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \
00982                                         FDCAN_IT_DATA_PROTOCOL_ERROR | \
00983                                         FDCAN_IT_ARB_PROTOCOL_ERROR | \
00984                                         FDCAN_IT_RAM_WATCHDOG | \
00985                                         FDCAN_IT_BUS_OFF | \
00986                                         FDCAN_IT_ERROR_WARNING)              /*!< Protocol Error Interrupts List     */
00987 /**
00988   * @}
00989   */
00990
00991 /** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group
00992   * @{
00993   */
00994 #define FDCAN_IT_GROUP_RX_FIFO0          FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group:
00995                                                                   RF0LL: Rx FIFO 0 Message Lost
00996                                                                   RF0FL: Rx FIFO 0 is Full
00997                                                                   RF0NL: Rx FIFO 0 Has New Message            */
00998 #define FDCAN_IT_GROUP_RX_FIFO1          FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group:
00999                                                                   RF1LL: Rx FIFO 1 Message Lost
01000                                                                   RF1FL: Rx FIFO 1 is Full
01001                                                                   RF1NL: Rx FIFO 1 Has New Message            */
01002 #define FDCAN_IT_GROUP_SMSG              FDCAN_ILS_SMSG    /*!< Status Message Interrupts Group:
01003                                                                   TCFL: Transmission Cancellation Finished
01004                                                                   TCL: Transmission Completed
01005                                                                   HPML: High Priority Message                 */
01006 #define FDCAN_IT_GROUP_TX_FIFO_ERROR     FDCAN_ILS_TFERR   /*!< TX FIFO Error Interrupts Group:
01007                                                                   TEFLL: Tx Event FIFO Element Lost
01008                                                                   TEFFL: Tx Event FIFO Full
01009                                                                   TEFNL: Tx Event FIFO New Entry
01010                                                                   TFEL: Tx FIFO Empty Interrupt Line          */
01011 #define FDCAN_IT_GROUP_MISC              FDCAN_ILS_MISC    /*!< Misc. Interrupts Group:
01012                                                                   TOOL: Timeout Occurred
01013                                                                   MRAFL: Message RAM Access Failure
01014                                                                   TSWL: Timestamp Wraparound                  */
01015 #define FDCAN_IT_GROUP_BIT_LINE_ERROR    FDCAN_ILS_BERR    /*!< Bit and Line Error Interrupts Group:
01016                                                                   EPL: Error Passive
01017                                                                   ELOL: Error Logging Overflow                */
01018 #define FDCAN_IT_GROUP_PROTOCOL_ERROR    FDCAN_ILS_PERR    /*!< Protocol Error Group:
01019                                                                   ARAL: Access to Reserved Address Line
01020                                                                   PEDL: Protocol Error in Data Phase Line
01021                                                                   PEAL: Protocol Error in Arbitration Phase Line
01022                                                                   WDIL: Watchdog Interrupt Line
01023                                                                   BOL: Bus_Off Status
01024                                                                   EWL: Warning Status                         */
01025 /**
01026   * @}
01027   */
01028
01029 /**
01030   * @}
01031   */
01032
01033 /* Exported macro ------------------------------------------------------------*/
01034 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
01035   * @{
01036   */
01037
01038 /** @brief  Reset FDCAN handle state.
01039   * @param  __HANDLE__ FDCAN handle.
01040   * @retval None
01041   */
01042 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
01043 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
01044                                                        (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
01045                                                        (__HANDLE__)->MspInitCallback = NULL;           \
01046                                                        (__HANDLE__)->MspDeInitCallback = NULL;         \
01047                                                      } while(0)
01048 #else
01049 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
01050 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01051
01052 /**
01053   * @brief  Enable the specified FDCAN interrupts.
01054   * @param  __HANDLE__ FDCAN handle.
01055   * @param  __INTERRUPT__ FDCAN interrupt.
01056   *         This parameter can be any combination of @arg FDCAN_Interrupts
01057   * @retval None
01058   */
01059 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
01060   (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
01061
01062 /**
01063   * @brief  Disable the specified FDCAN interrupts.
01064   * @param  __HANDLE__ FDCAN handle.
01065   * @param  __INTERRUPT__ FDCAN interrupt.
01066   *         This parameter can be any combination of @arg FDCAN_Interrupts
01067   * @retval None
01068   */
01069 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
01070   ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
01071
01072 /**
01073   * @brief  Check whether the specified FDCAN interrupt is set or not.
01074   * @param  __HANDLE__ FDCAN handle.
01075   * @param  __INTERRUPT__ FDCAN interrupt.
01076   *         This parameter can be one of @arg FDCAN_Interrupts
01077   * @retval ITStatus
01078   */
01079 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
01080
01081 /**
01082   * @brief  Clear the specified FDCAN interrupts.
01083   * @param  __HANDLE__ FDCAN handle.
01084   * @param  __INTERRUPT__ specifies the interrupts to clear.
01085   *         This parameter can be any combination of @arg FDCAN_Interrupts
01086   * @retval None
01087   */
01088 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)             \
01089   ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
01090
01091 /**
01092   * @brief  Check whether the specified FDCAN flag is set or not.
01093   * @param  __HANDLE__ FDCAN handle.
01094   * @param  __FLAG__ FDCAN flag.
01095   *         This parameter can be one of @arg FDCAN_flags
01096   * @retval FlagStatus
01097   */
01098 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
01099
01100 /**
01101   * @brief  Clear the specified FDCAN flags.
01102   * @param  __HANDLE__ FDCAN handle.
01103   * @param  __FLAG__ specifies the flags to clear.
01104   *         This parameter can be any combination of @arg FDCAN_flags
01105   * @retval None
01106   */
01107 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
01108   ((__HANDLE__)->Instance->IR) = (__FLAG__)
01109
01110 /** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
01111   * @param  __HANDLE__ FDCAN handle.
01112   * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
01113   *         This parameter can be a value of @arg FDCAN_Interrupts
01114   * @retval ITStatus
01115   */
01116 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
01117
01118 /**
01119   * @}
01120   */
01121
01122 /* Exported functions --------------------------------------------------------*/
01123 /** @addtogroup FDCAN_Exported_Functions
01124   * @{
01125   */
01126
01127 /** @addtogroup FDCAN_Exported_Functions_Group1
01128   * @{
01129   */
01130 /* Initialization and de-initialization functions *****************************/
01131 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
01132 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
01133 void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
01134 void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
01135 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
01136 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
01137
01138 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
01139 /* Callbacks Register/UnRegister functions  ***********************************/
01140 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
01141                                              pFDCAN_CallbackTypeDef pCallback);
01142 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
01143 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
01144                                                         pFDCAN_TxEventFifoCallbackTypeDef pCallback);
01145 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
01146 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
01147                                                     pFDCAN_RxFifo0CallbackTypeDef pCallback);
01148 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
01149 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
01150                                                     pFDCAN_RxFifo1CallbackTypeDef pCallback);
01151 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
01152 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
01153                                                              pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
01154 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
01155 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
01156                                                           pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
01157 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
01158 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
01159                                                         pFDCAN_ErrorStatusCallbackTypeDef pCallback);
01160 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
01161 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
01162 /**
01163   * @}
01164   */
01165
01166 /** @addtogroup FDCAN_Exported_Functions_Group2
01167   * @{
01168   */
01169 /* Configuration functions ****************************************************/
01170 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
01171 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
01172                                                uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
01173                                                uint32_t RejectRemoteExt);
01174 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
01175 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
01176 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
01177 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
01178 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
01179 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01180 uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01181 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
01182 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
01183                                                  uint32_t TimeoutPeriod);
01184 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01185 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01186 uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01187 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
01188 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
01189                                                       uint32_t TdcFilter);
01190 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
01191 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
01192 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
01193 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
01194 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
01195 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
01196 /**
01197   * @}
01198   */
01199
01200 /** @addtogroup FDCAN_Exported_Functions_Group3
01201   * @{
01202   */
01203 /* Control functions **********************************************************/
01204 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
01205 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
01206 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
01207                                                 uint8_t *pTxData);
01208 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
01209 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
01210 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
01211                                          FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
01212 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
01213 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
01214                                                          FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
01215 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
01216 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
01217 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
01218 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
01219 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
01220 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
01221 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
01222 /**
01223   * @}
01224   */
01225
01226 /** @addtogroup FDCAN_Exported_Functions_Group4
01227   * @{
01228   */
01229 /* Interrupts management ******************************************************/
01230 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
01231 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
01232                                                  uint32_t BufferIndexes);
01233 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
01234 void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
01235 /**
01236   * @}
01237   */
01238
01239 /** @addtogroup FDCAN_Exported_Functions_Group5
01240   * @{
01241   */
01242 /* Callback functions *********************************************************/
01243 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
01244 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
01245 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
01246 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
01247 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
01248 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
01249 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
01250 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
01251 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
01252 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
01253 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
01254 /**
01255   * @}
01256   */
01257
01258 /** @addtogroup FDCAN_Exported_Functions_Group6
01259   * @{
01260   */
01261 /* Peripheral State functions *************************************************/
01262 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
01263 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
01264 /**
01265   * @}
01266   */
01267
01268 /**
01269   * @}
01270   */
01271
01272 /* Private types -------------------------------------------------------------*/
01273 /* Private variables ---------------------------------------------------------*/
01274 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables
01275   * @{
01276   */
01277
01278 /**
01279   * @}
01280   */
01281
01282 /* Private constants ---------------------------------------------------------*/
01283 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants
01284   * @{
01285   */
01286
01287 /**
01288   * @}
01289   */
01290
01291 /* Private macros ------------------------------------------------------------*/
01292 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros
01293   * @{
01294   */
01295 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
01296                                        ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
01297                                        ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
01298 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
01299                              ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
01300                              ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
01301                              ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
01302                              ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
01303 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
01304                                ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
01305                                ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
01306                                ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
01307                                ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
01308                                ((CKDIV) == FDCAN_CLOCK_DIV10) || \
01309                                ((CKDIV) == FDCAN_CLOCK_DIV12) || \
01310                                ((CKDIV) == FDCAN_CLOCK_DIV14) || \
01311                                ((CKDIV) == FDCAN_CLOCK_DIV16) || \
01312                                ((CKDIV) == FDCAN_CLOCK_DIV18) || \
01313                                ((CKDIV) == FDCAN_CLOCK_DIV20) || \
01314                                ((CKDIV) == FDCAN_CLOCK_DIV22) || \
01315                                ((CKDIV) == FDCAN_CLOCK_DIV24) || \
01316                                ((CKDIV) == FDCAN_CLOCK_DIV26) || \
01317                                ((CKDIV) == FDCAN_CLOCK_DIV28) || \
01318                                ((CKDIV) == FDCAN_CLOCK_DIV30))
01319 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
01320 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
01321 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
01322 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
01323 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
01324 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
01325 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
01326 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
01327 #define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
01328 #define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
01329 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
01330                                            ((MODE) == FDCAN_TX_QUEUE_OPERATION))
01331 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
01332                                    ((ID_TYPE) == FDCAN_EXTENDED_ID))
01333 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
01334                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
01335                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
01336                                      ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
01337                                      ((CONFIG) == FDCAN_FILTER_HP           ) || \
01338                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
01339                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))
01340 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
01341                                         ((LOCATION) == FDCAN_TX_BUFFER2 ))
01342 #define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \
01343                                              ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))
01344 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
01345                                 ((FIFO) == FDCAN_RX_FIFO1))
01346 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
01347                                      ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
01348 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
01349                                         ((TYPE) == FDCAN_FILTER_DUAL ) || \
01350                                         ((TYPE) == FDCAN_FILTER_MASK ))
01351 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
01352                                         ((TYPE) == FDCAN_FILTER_DUAL         ) || \
01353                                         ((TYPE) == FDCAN_FILTER_MASK         ) || \
01354                                         ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
01355 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
01356                                    ((TYPE) == FDCAN_REMOTE_FRAME))
01357 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
01358                            ((DLC) == FDCAN_DLC_BYTES_1 ) || \
01359                            ((DLC) == FDCAN_DLC_BYTES_2 ) || \
01360                            ((DLC) == FDCAN_DLC_BYTES_3 ) || \
01361                            ((DLC) == FDCAN_DLC_BYTES_4 ) || \
01362                            ((DLC) == FDCAN_DLC_BYTES_5 ) || \
01363                            ((DLC) == FDCAN_DLC_BYTES_6 ) || \
01364                            ((DLC) == FDCAN_DLC_BYTES_7 ) || \
01365                            ((DLC) == FDCAN_DLC_BYTES_8 ) || \
01366                            ((DLC) == FDCAN_DLC_BYTES_12) || \
01367                            ((DLC) == FDCAN_DLC_BYTES_16) || \
01368                            ((DLC) == FDCAN_DLC_BYTES_20) || \
01369                            ((DLC) == FDCAN_DLC_BYTES_24) || \
01370                            ((DLC) == FDCAN_DLC_BYTES_32) || \
01371                            ((DLC) == FDCAN_DLC_BYTES_48) || \
01372                            ((DLC) == FDCAN_DLC_BYTES_64))
01373 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
01374                            ((ESI) == FDCAN_ESI_PASSIVE))
01375 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
01376                            ((BRS) == FDCAN_BRS_ON ))
01377 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
01378                            ((FDF) == FDCAN_FD_CAN     ))
01379 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
01380                            ((EFC) == FDCAN_STORE_TX_EVENTS))
01381 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
01382 #define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
01383 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
01384                                             ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
01385                                             ((DESTINATION) == FDCAN_REJECT            ))
01386 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
01387                                              ((DESTINATION) == FDCAN_REJECT_REMOTE))
01388 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
01389                                    ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
01390 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
01391                                        ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
01392 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
01393                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
01394                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
01395                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
01396                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
01397                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
01398                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
01399                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
01400                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
01401                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
01402                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
01403                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
01404                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
01405                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
01406                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
01407                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
01408 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
01409                                      ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
01410                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
01411                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
01412
01413 #define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__)  ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
01414
01415 #define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
01416 /**
01417   * @}
01418   */
01419
01420 /* Private functions prototypes ----------------------------------------------*/
01421 /* Private functions ---------------------------------------------------------*/
01422
01423 /**
01424   * @}
01425   */
01426
01427 /**
01428   * @}
01429   */
01430 #endif /* FDCAN1 */
01431
01432 #ifdef __cplusplus
01433 }
01434 #endif
01435
01436 #endif /* STM32G0xx_HAL_FDCAN_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_flash.c Source File

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stm32g0xx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @brief   FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the internal FLASH memory:
00008   *           + Program operations functions
00009   *           + Memory Control functions
00010   *           + Peripheral Errors functions
00011   *
00012  @verbatim
00013   ==============================================================================
00014                         ##### FLASH peripheral features #####
00015   ==============================================================================
00016
00017   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
00018        to the Flash memory. It implements the erase and program Flash memory operations
00019        and the read and write protection mechanisms.
00020
00021   [..] The Flash memory interface accelerates code execution with a system of instruction
00022        prefetch and cache lines.
00023
00024   [..] The FLASH main features are:
00025       (+) Flash memory read operations
00026       (+) Flash memory program/erase operations
00027       (+) Read / write protections
00028       (+) Option bytes programming
00029       (+) Prefetch on I-Code
00030       (+) 32 cache lines of 4*64 bits on I-Code
00031       (+) Error code correction (ECC) : Data in flash are 72-bits word
00032           (8 bits added per double word)
00033
00034                         ##### How to use this driver #####
00035  ==============================================================================
00036     [..]
00037       This driver provides functions and macros to configure and program the FLASH
00038       memory of all STM32G0xx devices.
00039
00040       (#) Flash Memory IO Programming functions:
00041            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00042                 HAL_FLASH_Lock() functions
00043            (++) Program functions: double word and fast program (full row programming)
00044            (++) There are two modes of programming:
00045             (+++) Polling mode using HAL_FLASH_Program() function
00046             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
00047
00048       (#) Interrupts and flags management functions:
00049            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
00050            (++) Callback functions are called when the flash operations are finished :
00051                 HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
00052                 HAL_FLASH_OperationErrorCallback()
00053            (++) Get error flag status by calling HAL_GetError()
00054
00055       (#) Option bytes management functions :
00056            (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
00057                 HAL_FLASH_OB_Lock() functions
00058            (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
00059                 In this case, a reset is generated
00060
00061     [..]
00062       In addition to these functions, this driver includes a set of macros allowing
00063       to handle the following operations:
00064        (+) Set the latency
00065        (+) Enable/Disable the prefetch buffer
00066        (+) Enable/Disable the Instruction cache
00067        (+) Reset the Instruction cache
00068        (+) Enable/Disable the Flash power-down during low-power run and sleep modes
00069        (+) Enable/Disable the Flash interrupts
00070        (+) Monitor the Flash flags status
00071
00072  @endverbatim
00073   ******************************************************************************
00074   * @attention
00075   *
00076   * Copyright (c) 2018 STMicroelectronics.
00077   * All rights reserved.
00078   *
00079   * This software is licensed under terms that can be found in the LICENSE file in
00080   * the root directory of this software component.
00081   * If no LICENSE file comes with this software, it is provided AS-IS.
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32g0xx_hal.h"
00087
00088 /** @addtogroup STM32G0xx_HAL_Driver
00089   * @{
00090   */
00091
00092 /** @defgroup FLASH FLASH
00093   * @brief FLASH HAL module driver
00094   * @{
00095   */
00096
00097 #ifdef HAL_FLASH_MODULE_ENABLED
00098
00099 /* Private typedef -----------------------------------------------------------*/
00100 /* Private defines -----------------------------------------------------------*/
00101 /* Private macros ------------------------------------------------------------*/
00102 /* Private variables ---------------------------------------------------------*/
00103 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00104   * @{
00105   */
00106 /**
00107   * @brief  Variable used for Program/Erase sectors under interruption
00108   */
00109 FLASH_ProcessTypeDef pFlash  = {.Lock = HAL_UNLOCKED, \
00110                                 .ErrorCode = HAL_FLASH_ERROR_NONE, \
00111                                 .ProcedureOnGoing = FLASH_TYPENONE, \
00112                                 .Address = 0U, \
00113                                 .Banks = 0U, \
00114                                 .Page = 0U, \
00115                                 .NbPagesToErase = 0U
00116                                };
00117 /**
00118   * @}
00119   */
00120
00121 /* Private function prototypes -----------------------------------------------*/
00122 /** @defgroup FLASH_Private_Functions FLASH Private Functions
00123   * @{
00124   */
00125 static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
00126 static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
00127 /**
00128   * @}
00129   */
00130
00131 /* Exported functions --------------------------------------------------------*/
00132 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
00133   * @{
00134   */
00135
00136 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00137   *  @brief   Programming operation functions
00138   *
00139 @verbatim
00140  ===============================================================================
00141                   ##### Programming operation functions #####
00142  ===============================================================================
00143     [..]
00144     This subsection provides a set of functions allowing to manage the FLASH
00145     program operations.
00146
00147 @endverbatim
00148   * @{
00149   */
00150
00151 /**
00152   * @brief  Program double word or fast program of a row at a specified address.
00153   * @param  TypeProgram Indicate the way to program at a specified address.
00154   *                      This parameter can be a value of @ref FLASH_Type_Program
00155   * @param  Address Specifies the address to be programmed.
00156   * @param  Data Specifies the data to be programmed
00157   *               This parameter is the data for the double word program and the address where
00158   *               are stored the data for the row fast program depending on the TypeProgram:
00159   *               TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit)
00160   *               TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit).
00161   *
00162   * @retval HAL_StatusTypeDef HAL Status
00163   */
00164 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00165 {
00166   HAL_StatusTypeDef status;
00167
00168   /* Check the parameters */
00169   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00170
00171   /* Process Locked */
00172   __HAL_LOCK(&pFlash);
00173
00174   /* Reset error code */
00175   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00176
00177   /* Wait for last operation to be completed */
00178   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00179
00180   if (status == HAL_OK)
00181   {
00182     if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
00183     {
00184       /* Check the parameters */
00185       assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00186
00187       /* Program double-word (64-bit) at a specified address */
00188       FLASH_Program_DoubleWord(Address, Data);
00189     }
00190     else
00191     {
00192       /* Check the parameters */
00193       assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
00194
00195       /* Fast program a 32 row double-word (64-bit) at a specified address */
00196       FLASH_Program_Fast(Address, (uint32_t)Data);
00197     }
00198
00199     /* Wait for last operation to be completed */
00200     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00201
00202     /* If the program operation is completed, disable the PG or FSTPG Bit */
00203     CLEAR_BIT(FLASH->CR, TypeProgram);
00204   }
00205
00206   /* Process Unlocked */
00207   __HAL_UNLOCK(&pFlash);
00208
00209   /* return status */
00210   return status;
00211 }
00212
00213 /**
00214   * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
00215   * @param  TypeProgram Indicate the way to program at a specified address.
00216   *                      This parameter can be a value of @ref FLASH_Type_Program
00217   * @param  Address Specifies the address to be programmed.
00218   * @param  Data Specifies the data to be programmed
00219   *               This parameter is the data for the double word program and the address where
00220   *               are stored the data for the row fast program depending on the TypeProgram:
00221   *               TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit)
00222   *               TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit).
00223   *
00224   * @retval HAL Status
00225   */
00226 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00227 {
00228   HAL_StatusTypeDef status;
00229
00230   /* Check the parameters */
00231   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00232
00233   /* Process Locked */
00234   __HAL_LOCK(&pFlash);
00235
00236   /* Reset error code */
00237   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00238
00239   /* Wait for last operation to be completed */
00240   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00241
00242   if (status != HAL_OK)
00243   {
00244     /* Process Unlocked */
00245     __HAL_UNLOCK(&pFlash);
00246   }
00247   else
00248   {
00249     /* Set internal variables used by the IRQ handler */
00250     pFlash.ProcedureOnGoing = TypeProgram;
00251     pFlash.Address = Address;
00252
00253     /* Enable End of Operation and Error interrupts */
00254     FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE;
00255
00256     if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
00257     {
00258       /* Check the parameters */
00259       assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00260
00261       /* Program double-word (64-bit) at a specified address */
00262       FLASH_Program_DoubleWord(Address, Data);
00263     }
00264     else
00265     {
00266       /* Check the parameters */
00267       assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
00268
00269       /* Fast program a 32 row double-word (64-bit) at a specified address */
00270       FLASH_Program_Fast(Address, (uint32_t)Data);
00271     }
00272   }
00273
00274   /* return status */
00275   return status;
00276 }
00277
00278 /**
00279   * @brief Handle FLASH interrupt request.
00280   * @retval None
00281   */
00282 void HAL_FLASH_IRQHandler(void)
00283 {
00284   uint32_t param;
00285   uint32_t error;
00286
00287   /* Save flash errors. */
00288   error = (FLASH->SR & FLASH_SR_ERRORS);
00289
00290   /* A] Set parameter for user or error callbacks */
00291   /* check operation was a program or erase */
00292   if ((pFlash.ProcedureOnGoing & FLASH_TYPEERASE_MASS) != 0x00U)
00293   {
00294     /* return bank number */
00295     param = pFlash.Banks;
00296   }
00297   else
00298   {
00299     /* Clear operation only for page erase or program */
00300     CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing);
00301
00302     if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00U)
00303     {
00304       /* return address being programmed */
00305       param = pFlash.Address;
00306     }
00307     else
00308     {
00309       /* return page number being erased */
00310       param = pFlash.Page;
00311     }
00312   }
00313
00314   /* B] Check errors */
00315   if (error != 0x00U)
00316   {
00317     /*Save the error code*/
00318     pFlash.ErrorCode |= error;
00319
00320     /* clear error flags */
00321     FLASH->SR = FLASH_SR_ERRORS;
00322
00323     /*Stop the procedure ongoing*/
00324     pFlash.ProcedureOnGoing = FLASH_TYPENONE;
00325
00326     /* Error callback */
00327     HAL_FLASH_OperationErrorCallback(param);
00328   }
00329
00330   /* C] Check FLASH End of Operation flag */
00331   if ((FLASH->SR & FLASH_SR_EOP) != 0x00U)
00332   {
00333     /* Clear FLASH End of Operation pending bit */
00334     FLASH->SR = FLASH_SR_EOP;
00335
00336     if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES)
00337     {
00338       /* Nb of pages to erased can be decreased */
00339       pFlash.NbPagesToErase--;
00340
00341       /* Check if there are still pages to erase*/
00342       if (pFlash.NbPagesToErase != 0x00U)
00343       {
00344         /* Increment page number */
00345         pFlash.Page++;
00346         FLASH_PageErase(pFlash.Banks, pFlash.Page);
00347       }
00348       else
00349       {
00350         /* No more pages to erase: stop erase pages procedure */
00351         pFlash.ProcedureOnGoing = FLASH_TYPENONE;
00352       }
00353     }
00354     else
00355     {
00356       /*Stop the ongoing procedure */
00357       pFlash.ProcedureOnGoing = FLASH_TYPENONE;
00358     }
00359
00360     /* User callback */
00361     HAL_FLASH_EndOfOperationCallback(param);
00362   }
00363
00364   if (pFlash.ProcedureOnGoing == FLASH_TYPENONE)
00365   {
00366     /* Disable End of Operation and Error interrupts */
00367     FLASH->CR &= ~(FLASH_CR_EOPIE | FLASH_CR_ERRIE);
00368
00369     /* Process Unlocked */
00370     __HAL_UNLOCK(&pFlash);
00371   }
00372 }
00373
00374 /**
00375   * @brief  FLASH end of operation interrupt callback.
00376   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00377   *                  Mass Erase: 0
00378   *                  Page Erase: Page which has been erased
00379   *                  Program: Address which was selected for data program
00380   * @retval None
00381   */
00382 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00383 {
00384   /* Prevent unused argument(s) compilation warning */
00385   UNUSED(ReturnValue);
00386
00387   /* NOTE : This function should not be modified, when the callback is needed,
00388             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00389    */
00390 }
00391
00392 /**
00393   * @brief  FLASH operation error interrupt callback.
00394   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00395   *                 Mass Erase: 0
00396   *                 Page Erase: Page number which returned an error
00397   *                 Program: Address which was selected for data program
00398   * @retval None
00399   */
00400 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00401 {
00402   /* Prevent unused argument(s) compilation warning */
00403   UNUSED(ReturnValue);
00404
00405   /* NOTE : This function should not be modified, when the callback is needed,
00406             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00407    */
00408 }
00409
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00415   *  @brief   Management functions
00416   *
00417 @verbatim
00418  ===============================================================================
00419                       ##### Peripheral Control functions #####
00420  ===============================================================================
00421     [..]
00422     This subsection provides a set of functions allowing to control the FLASH
00423     memory operations.
00424
00425 @endverbatim
00426   * @{
00427   */
00428
00429 /**
00430   * @brief  Unlock the FLASH control register access.
00431   * @retval HAL Status
00432   */
00433 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00434 {
00435   HAL_StatusTypeDef status = HAL_OK;
00436
00437   if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U)
00438   {
00439     /* Authorize the FLASH Registers access */
00440     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
00441     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
00442
00443     /* verify Flash is unlock */
00444     if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U)
00445     {
00446       status = HAL_ERROR;
00447     }
00448   }
00449
00450   return status;
00451 }
00452
00453 /**
00454   * @brief  Lock the FLASH control register access.
00455   * @retval HAL Status
00456   */
00457 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00458 {
00459   HAL_StatusTypeDef status = HAL_ERROR;
00460
00461   /* Set the LOCK Bit to lock the FLASH Registers access */
00462   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
00463
00464   /* verify Flash is locked */
00465   if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u)
00466   {
00467     status = HAL_OK;
00468   }
00469
00470   return status;
00471 }
00472
00473 /**
00474   * @brief  Unlock the FLASH Option Bytes Registers access.
00475   * @retval HAL Status
00476   */
00477 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00478 {
00479   HAL_StatusTypeDef status = HAL_ERROR;
00480
00481   if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00U)
00482   {
00483     /* Authorizes the Option Byte register programming */
00484     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
00485     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
00486
00487     /* verify option bytes are unlocked */
00488     if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00U)
00489     {
00490       status = HAL_OK;
00491     }
00492   }
00493
00494   return status;
00495 }
00496
00497 /**
00498   * @brief  Lock the FLASH Option Bytes Registers access.
00499   * @retval HAL Status
00500   */
00501 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00502 {
00503   HAL_StatusTypeDef status = HAL_ERROR;
00504
00505   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
00506   SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
00507
00508   /* verify option bytes are locked */
00509   if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u)
00510   {
00511     status = HAL_OK;
00512   }
00513
00514   return status;
00515 }
00516
00517 /**
00518   * @brief  Launch the option byte loading.
00519   * @retval HAL Status
00520   */
00521 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00522 {
00523   /* Set the bit to force the option byte reloading */
00524   SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
00525
00526   /* We should not reach here : Option byte launch generates Option byte reset
00527      so return error */
00528   return HAL_ERROR;
00529 }
00530
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
00536   *  @brief   Peripheral Errors functions
00537   *
00538 @verbatim
00539  ===============================================================================
00540                 ##### Peripheral Errors functions #####
00541  ===============================================================================
00542     [..]
00543     This subsection permits to get in run-time Errors of the FLASH peripheral.
00544
00545 @endverbatim
00546   * @{
00547   */
00548
00549 /**
00550   * @brief  Get the specific FLASH error flag.
00551   * @retval FLASH_ErrorCode The returned value can be
00552   *            @arg @ref HAL_FLASH_ERROR_NONE No error set
00553   *            @arg @ref HAL_FLASH_ERROR_OP Operation error
00554   *            @arg @ref HAL_FLASH_ERROR_PROG Programming error
00555   *            @arg @ref HAL_FLASH_ERROR_WRP Write protection error
00556   *            @arg @ref HAL_FLASH_ERROR_PGA Programming alignment error
00557   *            @arg @ref HAL_FLASH_ERROR_SIZ Size error
00558   *            @arg @ref HAL_FLASH_ERROR_PGS Programming sequence error
00559   *            @arg @ref HAL_FLASH_ERROR_MIS Fast programming data miss error
00560   *            @arg @ref HAL_FLASH_ERROR_FAST Fast programming error
00561   *            @arg @ref HAL_FLASH_ERROR_RD Read Protection error (PCROP)(*)
00562   *            @arg @ref HAL_FLASH_ERROR_OPTV Option validity error
00563   *            @arg @ref HAL_FLASH_ERROR_ECCD two ECC errors have been detected
00564   * @note (*) availability depends on devices
00565   */
00566 uint32_t HAL_FLASH_GetError(void)
00567 {
00568   return pFlash.ErrorCode;
00569 }
00570
00571 /**
00572   * @}
00573   */
00574
00575 /**
00576   * @}
00577   */
00578
00579 /* Private functions ---------------------------------------------------------*/
00580
00581 /** @addtogroup FLASH_Private_Functions
00582   * @{
00583   */
00584
00585 /**
00586   * @brief  Wait for a FLASH operation to complete.
00587   * @param  Timeout maximum flash operation timeout
00588   * @retval HAL_StatusTypeDef HAL Status
00589   */
00590 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
00591 {
00592   uint32_t error;
00593   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00594      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00595      flag will be set */
00596   uint32_t timeout = HAL_GetTick() + Timeout;
00597
00598   /* Wait if any operation is ongoing */
00599 #if defined(FLASH_DBANK_SUPPORT)
00600   error = (FLASH_SR_BSY1 | FLASH_SR_BSY2);
00601 #else
00602   error = FLASH_SR_BSY1;
00603 #endif /* FLASH_DBANK_SUPPORT */
00604
00605   while ((FLASH->SR & error) != 0x00U)
00606   {
00607     if (HAL_GetTick() >= timeout)
00608     {
00609       return HAL_TIMEOUT;
00610     }
00611   }
00612
00613   /* check flash errors */
00614   error = (FLASH->SR & FLASH_SR_ERRORS);
00615
00616   /* Clear SR register */
00617   FLASH->SR = FLASH_SR_CLEAR;
00618
00619   if (error != 0x00U)
00620   {
00621     /*Save the error code*/
00622     pFlash.ErrorCode = error;
00623     return HAL_ERROR;
00624   }
00625
00626   /* Wait for control register to be written */
00627   timeout = HAL_GetTick() + Timeout;
00628
00629   while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U)
00630   {
00631     if (HAL_GetTick() >= timeout)
00632     {
00633       return HAL_TIMEOUT;
00634     }
00635   }
00636
00637   return HAL_OK;
00638 }
00639
00640 /**
00641   * @brief  Program double-word (64-bit) at a specified address.
00642   * @param  Address Specifies the address to be programmed.
00643   * @param  Data Specifies the data to be programmed.
00644   * @retval None
00645   */
00646 static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
00647 {
00648   /* Set PG bit */
00649   SET_BIT(FLASH->CR, FLASH_CR_PG);
00650
00651   /* Program first word */
00652   *(uint32_t *)Address = (uint32_t)Data;
00653
00654   /* Barrier to ensure programming is performed in 2 steps, in right order
00655     (independently of compiler optimization behavior) */
00656   __ISB();
00657
00658   /* Program second word */
00659   *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
00660 }
00661
00662 /**
00663   * @brief  Fast program a 32 row double-word (64-bit) at a specified address.
00664   * @param  Address Specifies the address to be programmed.
00665   * @param  DataAddress Specifies the address where the data are stored.
00666   * @retval None
00667   */
00668 static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
00669 {
00670   uint8_t index = 0;
00671   uint32_t dest = Address;
00672   uint32_t src = DataAddress;
00673   uint32_t primask_bit;
00674
00675   /* Set FSTPG bit */
00676   SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
00677
00678   /* Enter critical section: row programming should not be longer than 7 ms */
00679   primask_bit = __get_PRIMASK();
00680   __disable_irq();
00681
00682   /* Fast Program : 64 words */
00683   while (index < 64U)
00684   {
00685     *(uint32_t *)dest = *(uint32_t *)src;
00686     src += 4U;
00687     dest += 4U;
00688     index++;
00689   }
00690
00691   /* wait for BSY1 in order to be sure that flash operation is ended befoire
00692      allowing prefetch in flash. Timeout does not return status, as it will
00693      be anyway done later */
00694
00695 #if defined(FLASH_DBANK_SUPPORT)
00696   while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U)
00697 #else
00698   while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U)
00699 #endif /* FLASH_DBANK_SUPPORT */
00700   {
00701   }
00702
00703   /* Exit critical section: restore previous priority mask */
00704   __set_PRIMASK(primask_bit);
00705 }
00706
00707 /**
00708   * @}
00709   */
00710
00711 #endif /* HAL_FLASH_MODULE_ENABLED */
00712
00713 /**
00714   * @}
00715   */
00716
00717 /**
00718   * @}
00719   */
00720
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_flash.h Source File

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stm32g0xx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G0xx_HAL_FLASH_H
00020 #define STM32G0xx_HAL_FLASH_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g0xx_hal_def.h"
00028
00029 /** @addtogroup STM32G0xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup FLASH
00034   * @{
00035   */
00036
00037 /* Exported types ------------------------------------------------------------*/
00038 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  FLASH Erase structure definition
00044   */
00045 typedef struct
00046 {
00047   uint32_t TypeErase;   /*!< Mass erase or page erase.
00048                              This parameter can be a value of @ref FLASH_Type_Erase */
00049   uint32_t Banks;       /*!< Select bank to erase.
00050                              This parameter must be a value of @ref FLASH_Banks
00051                              (FLASH_BANK_BOTH should be used only for mass erase) */
00052   uint32_t Page;        /*!< Initial Flash page to erase when page erase is enabled
00053                              This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */
00054   uint32_t NbPages;     /*!< Number of pages to be erased.
00055                              This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/
00056 } FLASH_EraseInitTypeDef;
00057
00058 /**
00059   * @brief  FLASH Option Bytes Program structure definition
00060   */
00061 typedef struct
00062 {
00063   uint32_t OptionType;        /*!< Option byte to be configured.
00064                                    This parameter can be a combination of the values of @ref FLASH_OB_Type */
00065   uint32_t WRPArea;           /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
00066                                    Only one WRP area could be programmed at the same time.
00067                                    This parameter can be value of @ref FLASH_OB_WRP_Area */
00068   uint32_t WRPStartOffset;    /*!< Write protection start offset (used for OPTIONBYTE_WRP).
00069                                    This parameter must be a value between 0 and [FLASH_PAGE_NB - 1]*/
00070   uint32_t WRPEndOffset;      /*!< Write protection end offset (used for OPTIONBYTE_WRP).
00071                                    This parameter must be a value between WRPStartOffset and [FLASH_PAGE_NB - 1] */
00072   uint32_t RDPLevel;          /*!< Set the read protection level (used for OPTIONBYTE_RDP).
00073                                    This parameter can be a value of @ref FLASH_OB_Read_Protection */
00074   uint32_t USERType;          /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
00075                                    This parameter can be a combination of @ref FLASH_OB_USER_Type */
00076   uint32_t USERConfig;        /*!< Value of the user option byte (used for OPTIONBYTE_USER).
00077                                    This parameter can be a combination of
00078                                    @ref FLASH_OB_USER_BOR_ENABLE(*),
00079                                    @ref FLASH_OB_USER_BOR_LEVEL(*),
00080                                    @ref FLASH_OB_USER_RESET_CONFIG(*),
00081                                    @ref FLASH_OB_USER_nRST_STOP,
00082                                    @ref FLASH_OB_USER_nRST_STANDBY,
00083                                    @ref FLASH_OB_USER_nRST_SHUTDOWN(*),
00084                                    @ref FLASH_OB_USER_IWDG_SW,
00085                                    @ref FLASH_OB_USER_IWDG_STOP,
00086                                    @ref FLASH_OB_USER_IWDG_STANDBY,
00087                                    @ref FLASH_OB_USER_WWDG_SW,
00088                                    @ref FLASH_OB_USER_SRAM_PARITY,
00089                                    @ref FLASH_OB_USER_BANK_SWAP(*),
00090                                    @ref FLASH_OB_USER_DUAL_BANK(*),
00091                                    @ref FLASH_OB_USER_nBOOT_SEL,
00092                                    @ref FLASH_OB_USER_nBOOT1,
00093                                    @ref FLASH_OB_USER_nBOOT0,
00094                                    @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*)
00095                                    @note (*) availability depends on devices */
00096 #if defined(FLASH_PCROP_SUPPORT)
00097   uint32_t PCROPConfig;       /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
00098                                    This parameter must be a combination of @ref FLASH_OB_PCROP_ZONE
00099                                    and @ref FLASH_OB_PCROP_RDP. Note that once set, Pcrop erase on RDP level 1 regression
00100                                    (PCROP_RDP bit) can not be reset. It will be reset by mass erase */
00101   uint32_t PCROP1AStartAddr;  /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
00102                                    to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
00103   uint32_t PCROP1AEndAddr;    /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
00104                                    to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
00105   uint32_t PCROP1BStartAddr;  /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
00106                                    to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
00107   uint32_t PCROP1BEndAddr;    /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
00108                                    to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
00109 #if defined(FLASH_DBANK_SUPPORT)
00110   uint32_t PCROP2AStartAddr;  /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
00111                                    to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
00112   uint32_t PCROP2AEndAddr;    /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
00113                                    to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
00114   uint32_t PCROP2BStartAddr;  /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
00115                                    to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
00116   uint32_t PCROP2BEndAddr;    /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
00117                                    to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
00118 #endif /* FLASH_DBANK_SUPPORT */
00119 #endif /* FLASH_PCROP_SUPPORT */
00120 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00121   uint32_t BootEntryPoint;    /*!< Allow to force a unique boot entry point to Flash or system Flash */
00122   uint32_t SecSize;           /*!< This parameter defines securable memory area width in number of pages starting from Flash base address.
00123                                    This parameter must be a value between [0] and [FLASH_PAGE_NB],
00124                                    [0] meaning no secure area defined, [1] meaning first page only protected, etc... */
00125 #if defined(FLASH_DBANK_SUPPORT)
00126   uint32_t SecSize2;           /*!< This parameter defines securable memory area width in number of pages starting from 2nd Bank start address.
00127                                    This parameter must be a value between [0] and [FLASH_PAGE_NB],
00128                                    [0] meaning no secure area defined, [1] meaning first page only protected, etc... */
00129 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
00130 #endif /* FLASH_DBANK_SUPPORT */
00131 } FLASH_OBProgramInitTypeDef;
00132
00133 /**
00134   * @brief  FLASH handle Structure definition
00135   */
00136 typedef struct
00137 {
00138   HAL_LockTypeDef   Lock;              /* FLASH locking object */
00139   uint32_t          ErrorCode;         /* FLASH error code */
00140   uint32_t          ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
00141   uint32_t          Address;           /* Internal variable to save address selected for program in IT context */
00142   uint32_t          Banks;             /* Internal variable to save current bank selected during erase in IT context */
00143   uint32_t          Page;              /* Internal variable to define the current page which is erasing in IT context */
00144   uint32_t          NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
00145 } FLASH_ProcessTypeDef;
00146
00147 /**
00148   * @}
00149   */
00150
00151 /* Exported constants --------------------------------------------------------*/
00152 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00153   * @{
00154   */
00155 /** @defgroup FLASH_Keys FLASH Keys
00156   * @{
00157   */
00158 #define FLASH_KEY1                      0x45670123U   /*!< Flash key1 */
00159 #define FLASH_KEY2                      0xCDEF89ABU   /*!< Flash key2: used with FLASH_KEY1
00160                                                            to unlock the FLASH registers access */
00161 #define FLASH_OPTKEY1                   0x08192A3BU   /*!< Flash option byte key1 */
00162 #define FLASH_OPTKEY2                   0x4C5D6E7FU   /*!< Flash option byte key2: used with FLASH_OPTKEY1
00163                                                            to allow option bytes operations */
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup FLASH_Latency FLASH Latency
00169   * @{
00170   */
00171 #define FLASH_LATENCY_0                 0x00000000UL        /*!< FLASH Zero wait state */
00172 #define FLASH_LATENCY_1                 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */
00173 #define FLASH_LATENCY_2                 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup FLASH_Flags FLASH Flags Definition
00179   * @{
00180   */
00181 #define FLASH_FLAG_EOP                  ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_EOP_Pos)         /*!< FLASH End of operation flag */
00182 #define FLASH_FLAG_OPERR                ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPERR_Pos)       /*!< FLASH Operation error flag */
00183 #define FLASH_FLAG_PROGERR              ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PROGERR_Pos)     /*!< FLASH Programming error flag */
00184 #define FLASH_FLAG_WRPERR               ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_WRPERR_Pos)      /*!< FLASH Write protection error flag */
00185 #define FLASH_FLAG_PGAERR               ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGAERR_Pos)      /*!< FLASH Programming alignment error flag */
00186 #define FLASH_FLAG_SIZERR               ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_SIZERR_Pos)      /*!< FLASH Size error flag  */
00187 #define FLASH_FLAG_PGSERR               ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGSERR_Pos)      /*!< FLASH Programming sequence error flag */
00188 #define FLASH_FLAG_MISERR               ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_MISERR_Pos)      /*!< FLASH Fast programming data miss error flag */
00189 #define FLASH_FLAG_FASTERR              ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_FASTERR_Pos)     /*!< FLASH Fast programming error flag */
00190 #if defined(FLASH_PCROP_SUPPORT)
00191 #define FLASH_FLAG_RDERR                ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_RDERR_Pos)       /*!< FLASH PCROP read error flag */
00192 #endif /* FLASH_PCROP_SUPPORT */
00193 #define FLASH_FLAG_OPTVERR              ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPTVERR_Pos)     /*!< FLASH Option validity error flag */
00194 #define FLASH_FLAG_BSY1                 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY1_Pos)        /*!< FLASH Operation Busy flag for Bank 1 */
00195 #if defined(FLASH_DBANK_SUPPORT)
00196 #define FLASH_FLAG_BSY2                  ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY2_Pos)       /*!< FLASH Operation Busy flag for Bank 2 */
00197 #endif /* FLASH_DBANK_SUPPORT */
00198 #define FLASH_FLAG_BSY                  FLASH_FLAG_BSY1                                                       /*!< FLASH Operation Busy flag - legacy name for single bank */
00199 #define FLASH_FLAG_CFGBSY               ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos)      /*!< FLASH Configuration Busy flag */
00200 #if defined(FLASH_DBANK_SUPPORT)
00201 #define FLASH_FLAG_PESD                 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos)        /*!< FLASH Programming/erase operation suspended */
00202 #endif /* FLASH_DBANK_SUPPORT */
00203 #define FLASH_FLAG_ECCC1                ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos)   /*!< FLASH ECC correction on bank 1 */
00204 #define FLASH_FLAG_ECCD1                ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos)   /*!< FLASH ECC detection on bank 1 */
00205 #if defined(FLASH_DBANK_SUPPORT)
00206 #define FLASH_FLAG_ECCC2                ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCC_Pos)  /*!< FLASH ECC correction on bank 2 */
00207 #define FLASH_FLAG_ECCD2                ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCD_Pos)  /*!< FLASH ECC detection on bank 2 */
00208 #endif /* FLASH_DBANK_SUPPORT */
00209 #define FLASH_FLAG_ECCC                 FLASH_FLAG_ECCC1   /*!< FLASH ECC correction - legacy name for single bank */
00210 #define FLASH_FLAG_ECCD                 FLASH_FLAG_ECCD1   /*!< FLASH ECC detection - legacy name for single bank */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
00216   * @brief FLASH Interrupt definition
00217   * @{
00218   */
00219 #define FLASH_IT_EOP                    ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_EOPIE_Pos)         /*!< End of FLASH Operation Interrupt source */
00220 #define FLASH_IT_OPERR                  ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_ERRIE_Pos)         /*!< Error Interrupt source */
00221 #if defined(FLASH_PCROP_SUPPORT)
00222 #define FLASH_IT_RDERR                  ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_RDERRIE_Pos)       /*!< PCROP Read Error Interrupt source*/
00223 #endif /* FLASH_PCROP_SUPPORT */
00224 #define FLASH_IT_ECCC1                  ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCCIE_Pos)   /*!< ECC Correction on Bank 1 Interrupt source */
00225 #if defined(FLASH_DBANK_SUPPORT)
00226 #define FLASH_IT_ECCC2                  ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCCIE_Pos)  /*!< ECC Correction on Bank 2 Interrupt source */
00227 #endif /* FLASH_DBANK_SUPPORT */
00228 #define FLASH_IT_ECCC                   FLASH_IT_ECCC1                                                          /*!< ECC Correction - legacy name for single bank */
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup FLASH_Error FLASH Error
00234   * @{
00235   */
00236 #define HAL_FLASH_ERROR_NONE            0x00000000U
00237 #define HAL_FLASH_ERROR_OP              FLASH_SR_OPERR
00238 #define HAL_FLASH_ERROR_PROG            FLASH_SR_PROGERR
00239 #define HAL_FLASH_ERROR_WRP             FLASH_SR_WRPERR
00240 #define HAL_FLASH_ERROR_PGA             FLASH_SR_PGAERR
00241 #define HAL_FLASH_ERROR_SIZ             FLASH_SR_SIZERR
00242 #define HAL_FLASH_ERROR_PGS             FLASH_SR_PGSERR
00243 #define HAL_FLASH_ERROR_MIS             FLASH_SR_MISERR
00244 #define HAL_FLASH_ERROR_FAST            FLASH_SR_FASTERR
00245 #if defined(FLASH_PCROP_SUPPORT)
00246 #define HAL_FLASH_ERROR_RD              FLASH_SR_RDERR
00247 #endif /* FLASH_PCROP_SUPPORT */
00248 #define HAL_FLASH_ERROR_OPTV            FLASH_SR_OPTVERR
00249 #define HAL_FLASH_ERROR_ECCD            FLASH_ECCR_ECCD
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup FLASH_Type_Erase FLASH Erase Type
00255   * @{
00256   */
00257 #define FLASH_TYPEERASE_PAGES           FLASH_CR_PER    /*!< Pages erase only */
00258 #define FLASH_TYPEERASE_MASS            FLASH_CR_MER1   /*!< Flash mass erase activation */
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup FLASH_Banks FLASH Banks
00264   * @{
00265   */
00266 #define FLASH_BANK_1                    FLASH_CR_MER1   /*!< Bank 1 */
00267 #if defined(FLASH_DBANK_SUPPORT)
00268 #define FLASH_BANK_2                    FLASH_CR_MER2   /*!< Bank 2 */
00269 #endif /* FLASH_DBANK_SUPPORT */
00270 /**
00271   * @}
00272   */
00273
00274
00275 /** @defgroup FLASH_Type_Program FLASH Program Type
00276   * @{
00277   */
00278 #define FLASH_TYPEPROGRAM_DOUBLEWORD    FLASH_CR_PG     /*!< Program a double-word (64-bit) at a specified address */
00279 #define FLASH_TYPEPROGRAM_FAST          FLASH_CR_FSTPG  /*!< Fast program a 32 row double-word (64-bit) at a specified address */
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type
00285   * @{
00286   */
00287 #define OPTIONBYTE_WRP                  0x00000001U  /*!< WRP option byte configuration */
00288 #define OPTIONBYTE_RDP                  0x00000002U  /*!< RDP option byte configuration */
00289 #define OPTIONBYTE_USER                 0x00000004U  /*!< USER option byte configuration */
00290 #if defined(FLASH_PCROP_SUPPORT)
00291 #define OPTIONBYTE_PCROP                0x00000008U  /*!< PCROP option byte configuration */
00292 #endif /* FLASH_PCROP_SUPPORT */
00293 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00294 #define OPTIONBYTE_SEC                  0x00000010U  /*!< SEC option byte configuration */
00295 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
00296
00297 #if defined(FLASH_PCROP_SUPPORT) && defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00298 #define OPTIONBYTE_ALL                  (OPTIONBYTE_WRP   | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
00299                                          OPTIONBYTE_PCROP | OPTIONBYTE_SEC)                   /*!< All option byte configuration */
00300 #else
00301 #define OPTIONBYTE_ALL                  (OPTIONBYTE_WRP   | OPTIONBYTE_RDP | OPTIONBYTE_USER) /*!< All option byte configuration */
00302 #endif /* FLASH_PCROP_SUPPORT && FLASH_SECURABLE_MEMORY_SUPPORT */
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
00308   * @{
00309   */
00310 #define OB_WRPAREA_ZONE_A               0x00000001U  /*!< Flash Zone A */
00311 #define OB_WRPAREA_ZONE_B               0x00000002U  /*!< Flash Zone B */
00312 #if defined(FLASH_DBANK_SUPPORT)
00313 #define OB_WRPAREA_ZONE2_A              0x00000004U  /*!< Flash Bank 2 Zone A */
00314 #define OB_WRPAREA_ZONE2_B              0x00000008U  /*!< Flash Bank 2 Zone B */
00315 #endif /* FLASH_DBANK_SUPPORT */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
00321   * @{
00322   */
00323 #define OB_RDP_LEVEL_0                  0x000000AAU
00324 #define OB_RDP_LEVEL_1                  0x000000BBU
00325 #define OB_RDP_LEVEL_2                  0x000000CCU  /*!< Warning: When enabling read protection level 2
00326                                                           it is no more possible to go back to level 1 or 0 */
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
00332   * @{
00333   */
00334 #if defined(PWR_BOR_SUPPORT)
00335 #define OB_USER_BOR_EN                  FLASH_OPTR_BOR_EN                           /*!< BOR reset enable */
00336 #define OB_USER_BOR_LEV                 (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV) /*!< BOR reset Level */
00337 #endif /* PWR_BOR_SUPPORT */
00338 #define OB_USER_nRST_STOP               FLASH_OPTR_nRST_STOP                        /*!< Reset generated when entering the stop mode */
00339 #define OB_USER_nRST_STDBY              FLASH_OPTR_nRST_STDBY                       /*!< Reset generated when entering the standby mode */
00340 #if defined(PWR_SHDW_SUPPORT)
00341 #define OB_USER_nRST_SHDW               FLASH_OPTR_nRST_SHDW                        /*!< Reset generated when entering the shutdown mode */
00342 #endif /* PWR_SHDW_SUPPORT */
00343 #define OB_USER_IWDG_SW                 FLASH_OPTR_IWDG_SW                          /*!< Independent watchdog selection */
00344 #define OB_USER_IWDG_STOP               FLASH_OPTR_IWDG_STOP                        /*!< Independent watchdog counter freeze in stop mode */
00345 #define OB_USER_IWDG_STDBY              FLASH_OPTR_IWDG_STDBY                       /*!< Independent watchdog counter freeze in standby mode */
00346 #define OB_USER_WWDG_SW                 FLASH_OPTR_WWDG_SW                          /*!< Window watchdog selection */
00347 #if defined(FLASH_DBANK_SUPPORT)
00348 #define OB_USER_BANK_SWAP               FLASH_OPTR_nSWAP_BANK                       /*!< Swap bank memory addresses */
00349 #define OB_USER_DUAL_BANK               FLASH_OPTR_DUAL_BANK                        /*!< Select single or dual bank (depending of device memory size) */
00350 #endif /* FLASH_DBANK_SUPPORT */
00351 #define OB_USER_RAM_PARITY_CHECK        FLASH_OPTR_RAM_PARITY_CHECK                 /*!< Sram parity check control */
00352 #define OB_USER_nBOOT_SEL               FLASH_OPTR_nBOOT_SEL                        /*!< Boot Selection */
00353 #define OB_USER_nBOOT1                  FLASH_OPTR_nBOOT1                           /*!< nBoot1 configuration */
00354 #define OB_USER_nBOOT0                  FLASH_OPTR_nBOOT0                           /*!< nBoot0 configuration */
00355 #if defined(GPIO_NRST_CONFIG_SUPPORT)
00356 #define OB_USER_NRST_MODE               FLASH_OPTR_NRST_MODE                        /*!< Reset pin configuration */
00357 #endif /* GPIO_NRST_CONFIG_SUPPORT */
00358 #if defined(FLASH_OPTR_IRHEN)
00359 #define OB_USER_INPUT_RESET_HOLDER      FLASH_OPTR_IRHEN                            /*!< Internal reset holder enable */
00360 #endif /* FLASH_OPTR_IRHEN */
00361
00362 #if defined(FLASH_DBANK_SUPPORT)
00363 #if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT)
00364 #define OB_USER_ALL                     (OB_USER_BOR_EN           | OB_USER_BOR_LEV    | OB_USER_nRST_STOP | \
00365                                          OB_USER_nRST_STDBY       | OB_USER_nRST_SHDW  | OB_USER_IWDG_SW   | \
00366                                          OB_USER_IWDG_STOP        | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | \
00367                                          OB_USER_BANK_SWAP        | OB_USER_DUAL_BANK                      | \
00368                                          OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL  | OB_USER_nBOOT1    | \
00369                                          OB_USER_nBOOT0           | OB_USER_NRST_MODE  | OB_USER_INPUT_RESET_HOLDER)   /*!< all option bits */
00370 #else
00371 #define OB_USER_ALL                     (                                                OB_USER_nRST_STOP | \
00372     OB_USER_nRST_STDBY                            | OB_USER_IWDG_SW   | \
00373     OB_USER_IWDG_STOP        | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | \
00374     OB_USER_BANK_SWAP        | OB_USER_DUAL_BANK                      | \
00375     OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL  | OB_USER_nBOOT1    | \
00376     OB_USER_nBOOT0)                                                               /*!< all option bits */
00377 #endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */
00378 #else
00379 #if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT)
00380 #define OB_USER_ALL                     (OB_USER_BOR_EN           | OB_USER_BOR_LEV    | OB_USER_nRST_STOP | \
00381                                          OB_USER_nRST_STDBY       | OB_USER_nRST_SHDW  | OB_USER_IWDG_SW   | \
00382                                          OB_USER_IWDG_STOP        | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | \
00383                                          OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL  | OB_USER_nBOOT1    | \
00384                                          OB_USER_nBOOT0           | OB_USER_NRST_MODE  | OB_USER_INPUT_RESET_HOLDER)   /*!< all option bits */
00385 #else
00386 #define OB_USER_ALL                     (                                                OB_USER_nRST_STOP | \
00387     OB_USER_nRST_STDBY                            | OB_USER_IWDG_SW   | \
00388     OB_USER_IWDG_STOP        | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | \
00389     OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL  | OB_USER_nBOOT1    | \
00390     OB_USER_nBOOT0)                                                               /*!< all option bits */
00391 #endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */
00392 #endif /* FLASH_DBANK_SUPPORT */
00393 /**
00394   * @}
00395   */
00396
00397 #if defined(PWR_BOR_SUPPORT)
00398 /** @defgroup FLASH_OB_USER_BOR_ENABLE FLASH Option Bytes User BOR enable
00399   * @{
00400   */
00401 #define OB_BOR_DISABLE                  0x00000000U        /*!< BOR Reset set to default */
00402 #define OB_BOR_ENABLE                   FLASH_OPTR_BOR_EN  /*!< Use option byte to define BOR thresholds */
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
00408   * @{
00409   */
00410 #define OB_BOR_LEVEL_FALLING_0          0x00000000U                                     /*!< BOR falling level 1 with threshold around 2.0V */
00411 #define OB_BOR_LEVEL_FALLING_1          FLASH_OPTR_BORF_LEV_0                           /*!< BOR falling level 2 with threshold around 2.2V */
00412 #define OB_BOR_LEVEL_FALLING_2          FLASH_OPTR_BORF_LEV_1                           /*!< BOR falling level 3 with threshold around 2.5V */
00413 #define OB_BOR_LEVEL_FALLING_3          (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1) /*!< BOR falling level 4 with threshold around 2.8V */
00414 #define OB_BOR_LEVEL_RISING_0           0x00000000U                                     /*!< BOR rising level 1 with threshold around 2.1V */
00415 #define OB_BOR_LEVEL_RISING_1           FLASH_OPTR_BORR_LEV_0                           /*!< BOR rising level 2 with threshold around 2.3V */
00416 #define OB_BOR_LEVEL_RISING_2           FLASH_OPTR_BORR_LEV_1                           /*!< BOR rising level 3 with threshold around 2.6V */
00417 #define OB_BOR_LEVEL_RISING_3           (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1) /*!< BOR rising level 4 with threshold around 2.9V */
00418 /**
00419   * @}
00420   */
00421 #endif /* PWR_BOR_SUPPORT */
00422
00423 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
00424   * @{
00425   */
00426 #define OB_STOP_RST                     0x00000000U           /*!< Reset generated when entering the stop mode */
00427 #define OB_STOP_NORST                   FLASH_OPTR_nRST_STOP  /*!< No reset generated when entering the stop mode */
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
00433   * @{
00434   */
00435 #define OB_STANDBY_RST                  0x00000000U           /*!< Reset generated when entering the standby mode */
00436 #define OB_STANDBY_NORST                FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */
00437 /**
00438   * @}
00439   */
00440
00441 #if defined(PWR_SHDW_SUPPORT)
00442 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
00443   * @{
00444   */
00445 #define OB_SHUTDOWN_RST                 0x00000000U           /*!< Reset generated when entering the shutdown mode */
00446 #define OB_SHUTDOWN_NORST               FLASH_OPTR_nRST_SHDW  /*!< No reset generated when entering the shutdown mode */
00447 /**
00448   * @}
00449   */
00450 #endif /* PWR_SHDW_SUPPORT */
00451
00452 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
00453   * @{
00454   */
00455 #define OB_IWDG_HW                      0x00000000U           /*!< Hardware independent watchdog */
00456 #define OB_IWDG_SW                      FLASH_OPTR_IWDG_SW    /*!< Software independent watchdog */
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
00462   * @{
00463   */
00464 #define OB_IWDG_STOP_FREEZE             0x00000000U           /*!< Independent watchdog counter is frozen in Stop mode */
00465 #define OB_IWDG_STOP_RUN                FLASH_OPTR_IWDG_STOP  /*!< Independent watchdog counter is running in Stop mode */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
00471   * @{
00472   */
00473 #define OB_IWDG_STDBY_FREEZE            0x00000000U           /*!< Independent watchdog counter is frozen in Standby mode */
00474 #define OB_IWDG_STDBY_RUN               FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
00480   * @{
00481   */
00482 #define OB_WWDG_HW                      0x00000000U           /*!< Hardware window watchdog */
00483 #define OB_WWDG_SW                      FLASH_OPTR_WWDG_SW    /*!< Software window watchdog */
00484 /**
00485   * @}
00486   */
00487
00488 #if defined(FLASH_DBANK_SUPPORT)
00489 /** @defgroup FLASH_OB_USER_BANK_SWAP FLASH Option Bytes User bank swap Type
00490   * @{
00491   */
00492 #define OB_USER_DUALBANK_SWAP_ENABLE    0x00000000U            /*!< Enable bank swap */
00493 #define OB_USER_DUALBANK_SWAP_DISABLE   FLASH_OPTR_nSWAP_BANK  /*!< Disable bank swap */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup FLASH_OB_USER_DUAL_BANK FLASH Option Bytes User dual bank enable Type
00499   * @{
00500   */
00501 #define OB_USER_DUALBANK_DISABLE        0x00000000U           /*!< Disable dual bank */
00502 #define OB_USER_DUALBANK_ENABLE         FLASH_OPTR_DUAL_BANK  /*!< Enable dual bank */
00503 /**
00504   * @}
00505   */
00506 #endif /* FLASH_DBANK_SUPPORT */
00507
00508 /** @defgroup FLASH_OB_USER_SRAM_PARITY FLASH Option Bytes User SRAM parity
00509   * @{
00510   */
00511 #define OB_SRAM_PARITY_ENABLE           0x00000000U                  /*!< Sram parity enable */
00512 #define OB_SRAM_PARITY_DISABLE          FLASH_OPTR_RAM_PARITY_CHECK  /*!< Sram parity disable */
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup FLASH_OB_USER_nBOOT_SEL FLASH Option Bytes User Boot0 Selection
00518   * @{
00519   */
00520 #define OB_BOOT0_FROM_PIN               0x00000000U             /*!< BOOT0 signal is defined by PA14/BOOT0 pin value */
00521 #define OB_BOOT0_FROM_OB                FLASH_OPTR_nBOOT_SEL    /*!< BOOT0 signal is defined by nBOOT0 option bit */
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
00527   * @{
00528   */
00529 #define OB_BOOT1_SRAM                   0x00000000U           /*!< Embedded SRAM is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */
00530 #define OB_BOOT1_SYSTEM                 FLASH_OPTR_nBOOT1     /*!< System memory is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
00536   * @{
00537   */
00538 #define OB_nBOOT0_RESET                 0x00000000U           /*!< nBOOT0 = 0 */
00539 #define OB_nBOOT0_SET                   FLASH_OPTR_nBOOT0     /*!< nBOOT0 = 1 */
00540 /**
00541   * @}
00542   */
00543
00544 #if defined(GPIO_NRST_CONFIG_SUPPORT)
00545 /** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit
00546   * @{
00547   */
00548 #define OB_RESET_MODE_INPUT_ONLY        FLASH_OPTR_NRST_MODE_0  /*!< Reset pin is in Reset input mode only */
00549 #define OB_RESET_MODE_GPIO              FLASH_OPTR_NRST_MODE_1  /*!< Reset pin is in GPIO mode mode only */
00550 #define OB_RESET_MODE_INPUT_OUTPUT      FLASH_OPTR_NRST_MODE    /*!< Reset pin is in reset input and output mode */
00551 /**
00552   * @}
00553   */
00554 #endif /* GPIO_NRST_CONFIG_SUPPORT */
00555
00556 #if defined(FLASH_OPTR_IRHEN)
00557 /** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit
00558   * @{
00559   */
00560 #define OB_IRH_ENABLE                   0x00000000U           /*!< Internal Reset handler enable */
00561 #define OB_IRH_DISABLE                  FLASH_OPTR_IRHEN      /*!< Internal Reset handler disable */
00562 /**
00563   * @}
00564   */
00565 #endif /* FLASH_OPTR_IRHEN */
00566
00567 #if defined(FLASH_PCROP_SUPPORT)
00568 /** @defgroup FLASH_OB_PCROP_ZONE FLASH Option Bytes PCROP ZONE
00569   * @{
00570   */
00571 #define OB_PCROP_ZONE_A                 0x00000001U /*!< PCROP Zone A */
00572 #define OB_PCROP_ZONE_B                 0x00000002U /*!< PCROP Zone B */
00573 #if defined(FLASH_DBANK_SUPPORT)
00574 #define OB_PCROP_ZONE2_A                0x00000004U /*!< PCROP Bank 2 Zone A */
00575 #define OB_PCROP_ZONE2_B                0x00000008U /*!< PCROP Bank 2 Zone B */
00576 #endif /* FLASH_DBANK_SUPPORT */
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
00582   * @{
00583   */
00584 #define OB_PCROP_RDP_NOT_ERASE          0x00000000U               /*!< PCROP area is not erased when the RDP level
00585                                                                        is decreased from Level 1 to Level 0 */
00586 #define OB_PCROP_RDP_ERASE              FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is
00587                                                                        decreased from Level 1 to Level 0 (full mass erase).
00588                                                                        Once this bit is set only, it will be reset by mass erase */
00589 /**
00590   * @}
00591   */
00592 #endif /* FLASH_PCROP_SUPPORT */
00593
00594 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00595 /** @defgroup FLASH_OB_SEC_BOOT_LOCK FLASH Option Bytes Secure boot lock
00596   * @{
00597   */
00598 #define OB_BOOT_ENTRY_FORCED_NONE        0x00000000U               /*!< Boot entry is free */
00599 #define OB_BOOT_ENTRY_FORCED_FLASH       FLASH_SECR_BOOT_LOCK      /*!< Boot entry is forced to Flash or System Flash */
00600 /**
00601   * @}
00602   */
00603 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
00604
00605 /**
00606   * @}
00607   */
00608
00609 /* Exported macros -----------------------------------------------------------*/
00610 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00611   *  @brief macros to control FLASH features
00612   *  @{
00613   */
00614
00615 /**
00616   * @brief  Set the FLASH Latency.
00617   * @param  __LATENCY__ FLASH Latency
00618   *         This parameter can be one of the following values :
00619   *     @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
00620   *     @arg @ref FLASH_LATENCY_1 FLASH One wait state
00621   *     @arg @ref FLASH_LATENCY_2 FLASH Two wait states
00622   * @retval None
00623   */
00624 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
00625
00626 /**
00627   * @brief  Get the FLASH Latency.
00628   * @retval FLASH Latency
00629   *         Returned value can be one of the following values :
00630   *     @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
00631   *     @arg @ref FLASH_LATENCY_1 FLASH One wait state
00632   *     @arg @ref FLASH_LATENCY_2 FLASH Two wait states
00633   */
00634 #define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
00635
00636 /**
00637   * @brief  Enable the FLASH prefetch buffer.
00638   * @retval None
00639   */
00640 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
00641
00642 /**
00643   * @brief  Disable the FLASH prefetch buffer.
00644   * @retval None
00645   */
00646 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
00647
00648 /**
00649   * @brief  Enable the FLASH instruction cache.
00650   * @retval none
00651   */
00652 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
00653
00654 /**
00655   * @brief  Disable the FLASH instruction cache.
00656   * @retval none
00657   */
00658 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
00659
00660 /**
00661   * @brief  Reset the FLASH instruction Cache.
00662   * @note   This function must be used only when the Instruction Cache is disabled.
00663   * @retval None
00664   */
00665 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
00666                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
00667                                                    } while (0U)
00668 /**
00669   * @}
00670   */
00671
00672 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
00673   *  @brief macros to handle FLASH interrupts
00674   * @{
00675   */
00676
00677 /**
00678   * @brief  Enable the specified FLASH interrupt.
00679   * @param  __INTERRUPT__ FLASH interrupt
00680   *         This parameter can be one of the following values :
00681   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
00682   *     @arg @ref FLASH_IT_OPERR Error Interrupt
00683   *     @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*)
00684   *     @arg @ref FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1
00685   *     @arg @ref FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*)
00686   *     @arg @ref FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank
00687   * @note (*) availability depends on devices
00688   * @retval none
00689   */
00690 #if defined(FLASH_DBANK_SUPPORT)
00691 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }             \
00692                                                      else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }   \
00693                                                      else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); }  \
00694                                                    } while(0U)
00695 #else
00696 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }             \
00697                                                      else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }   \
00698                                                    } while(0U)
00699 #endif /* FLASH_DBANK_SUPPORT */
00700
00701 /**
00702   * @brief  Disable the specified FLASH interrupt.
00703   * @param  __INTERRUPT__ FLASH interrupt
00704   *         This parameter can be one of the following values :
00705   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
00706   *     @arg @ref FLASH_IT_OPERR Error Interrupt
00707   *     @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*)
00708   *     @arg @ref FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1
00709   *     @arg @ref FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*)
00710   *     @arg @ref FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank
00711   * @note (*) availability depends on devices
00712   * @retval none
00713   */
00714 #if defined(FLASH_DBANK_SUPPORT)
00715 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }             \
00716                                                      else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }   \
00717                                                      else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); }  \
00718                                                    } while(0U)
00719 #else
00720 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }             \
00721                                                      else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); }   \
00722                                                    } while(0U)
00723 #endif /* FLASH_DBANK_SUPPORT */
00724
00725 /**
00726   * @brief  Check whether the specified FLASH flag is set or not.
00727   * @param  __FLAG__ specifies the FLASH flag to check.
00728   *         This parameter can be one of the following values :
00729   *     @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
00730   *     @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
00731   *     @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
00732   *     @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
00733   *     @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
00734   *     @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
00735   *     @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
00736   *     @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
00737   *     @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
00738   *     @arg @ref FLASH_FLAG_RDERR FLASH PCROP read  error flag(*)
00739   *     @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
00740   *     @arg @ref FLASH_FLAG_BSY1 FLASH bank 1 write/erase operations in progress flag
00741   *     @arg @ref FLASH_FLAG_BSY2 FLASH bank 2 write/erase operations in progress flag(*)
00742   *     @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag  - legacy name for single bank
00743   *     @arg @ref FLASH_FLAG_CFGBSY FLASH configuration is busy : program or erase setting are used.
00744   *     @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
00745   *     @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1
00746   *     @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*)
00747   *     @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*)
00748   *     @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank
00749   *     @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank
00750   * @note (*) availability depends on devices
00751   * @retval The state of FLASH_FLAG (SET or RESET).
00752   */
00753 #if defined(FLASH_DBANK_SUPPORT)
00754 #define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ?             \
00755                                                  (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) :        \
00756                                                  ((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
00757                                                   (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) :      \
00758                                                   (READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)))
00759 #else
00760 #define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ?   \
00761                                                  (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
00762                                                  (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u))
00763 #endif /* FLASH_DBANK_SUPPORT */
00764
00765 /**
00766   * @brief  Clear the FLASH pending flags.
00767   * @param  __FLAG__ specifies the FLASH flags to clear.
00768   *         This parameter can be one of the following values :
00769   *     @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
00770   *     @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
00771   *     @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
00772   *     @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
00773   *     @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
00774   *     @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
00775   *     @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
00776   *     @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
00777   *     @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
00778   *     @arg @ref FLASH_FLAG_RDERR FLASH PCROP read  error flag
00779   *     @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
00780   *     @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
00781   *     @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1
00782   *     @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*)
00783   *     @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*)
00784   *     @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank
00785   *     @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank
00786   * @note (*) availability depends on devices
00787   * @retval None
00788   */
00789 #if defined(FLASH_DBANK_SUPPORT)
00790 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U)         { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); }    \
00791                                                      else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); }  \
00792                                                      else if(((__FLAG__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECC2R = (1uL << ((__FLAG__) & 0x1Fu)); }  \
00793                                                    } while(0U)
00794 #else
00795 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U)         { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); }    \
00796                                                      else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); }  \
00797                                                    } while(0U)
00798 #endif /* FLASH_DBANK_SUPPORT */
00799 /**
00800   * @}
00801   */
00802
00803 /* Include FLASH HAL Extended module */
00804 #include "stm32g0xx_hal_flash_ex.h"
00805 /* Exported variables --------------------------------------------------------*/
00806 /** @defgroup FLASH_Exported_Variables FLASH Exported Variables
00807   * @{
00808   */
00809 extern FLASH_ProcessTypeDef pFlash;
00810 /**
00811   * @}
00812   */
00813
00814 /* Exported functions --------------------------------------------------------*/
00815 /** @addtogroup FLASH_Exported_Functions
00816   * @{
00817   */
00818
00819 /* Program operation functions  ***********************************************/
00820 /** @addtogroup FLASH_Exported_Functions_Group1
00821   * @{
00822   */
00823 HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00824 HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00825 /* FLASH IRQ handler method */
00826 void               HAL_FLASH_IRQHandler(void);
00827 /* Callbacks in non blocking modes */
00828 void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00829 void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00830 /**
00831   * @}
00832   */
00833
00834 /* Peripheral Control functions  **********************************************/
00835 /** @addtogroup FLASH_Exported_Functions_Group2
00836   * @{
00837   */
00838 HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
00839 HAL_StatusTypeDef  HAL_FLASH_Lock(void);
00840 /* Option bytes control */
00841 HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
00842 HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
00843 HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
00844 /**
00845   * @}
00846   */
00847
00848 /* Peripheral State functions  ************************************************/
00849 /** @addtogroup FLASH_Exported_Functions_Group3
00850   * @{
00851   */
00852 uint32_t HAL_FLASH_GetError(void);
00853 /**
00854   * @}
00855   */
00856
00857 /**
00858   * @}
00859   */
00860
00861 /* Private types --------------------------------------------------------*/
00862 /** @defgroup FLASH_Private_types FLASH Private Types
00863   * @{
00864   */
00865 HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
00866 /**
00867   * @}
00868   */
00869
00870 /* Private constants --------------------------------------------------------*/
00871 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00872   * @{
00873   */
00874 #define FLASH_SIZE_DATA_REGISTER        FLASHSIZE_BASE
00875
00876 #if defined(FLASH_DBANK_SUPPORT)
00877 #define OB_DUAL_BANK_BASE               (FLASH_R_BASE + 0x20U)               /*!< Not use cmsis FLASH alias to avoid iar warning about volatile reading sequence */
00878 #define FLASH_SALES_TYPE_Pos            (24U)
00879 #define FLASH_SALES_TYPE                (0x3UL << FLASH_SALES_TYPE_Pos)     /*!< 0x000001E0 */
00880 #define FLASH_SALES_TYPE_0              (0x1UL << FLASH_SALES_TYPE_Pos)     /*!< 0x01000000 */
00881 #define FLASH_SALES_TYPE_1              (0x2UL << FLASH_SALES_TYPE_Pos)     /*!< 0x02000000 */
00882 #define FLASH_SALES_VALUE               ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE))
00883 #define OB_DUAL_BANK_VALUE              ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK))
00884 #define FLASH_BANK_NB                   (((FLASH_SALES_VALUE == 0U)\
00885                                           || ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U)
00886 #define FLASH_BANK_SIZE                 ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U)) /*!< FLASH Bank Size. Divided by 2 if 2 Banks */
00887 #else /* FLASH_DBANK_SUPPORT */
00888 #define FLASH_BANK_SIZE                 (FLASH_SIZE)   /*!< FLASH Bank Size */
00889 #endif /* FLASH_DBANK_SUPPORT */
00890
00891 #define FLASH_PAGE_SIZE                 0x00000800U    /*!< FLASH Page Size, 2 KBytes */
00892 #define FLASH_PAGE_NB                   (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of pages per bank */
00893 #define FLASH_TIMEOUT_VALUE             1000U          /*!< FLASH Execution Timeout, 1 s */
00894 #define FLASH_TYPENONE                  0x00000000U    /*!< No programming Procedure On Going */
00895
00896 #if defined(FLASH_PCROP_SUPPORT)
00897 #define FLASH_SR_ERRORS                 (FLASH_SR_OPERR  | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \
00898                                          FLASH_SR_PGAERR | FLASH_SR_SIZERR  | FLASH_SR_PGSERR |  \
00899                                          FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR |   \
00900                                          FLASH_SR_OPTVERR) /*!< All SR error flags */
00901 #else
00902 #define FLASH_SR_ERRORS                 (FLASH_SR_OPERR  | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \
00903                                          FLASH_SR_PGAERR | FLASH_SR_SIZERR  | FLASH_SR_PGSERR |  \
00904                                          FLASH_SR_MISERR | FLASH_SR_FASTERR |                    \
00905                                          FLASH_SR_OPTVERR) /*!< All SR error flags */
00906 #endif /* FLASH_PCROP_SUPPORT */
00907
00908 #if defined(FLASH_DBANK_SUPPORT)
00909 #define FLASH_SR_CLEAR                  (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD)
00910 #else
00911 #define FLASH_SR_CLEAR                  (FLASH_SR_ERRORS | FLASH_SR_EOP)
00912 #endif /* FLASH_DBANK_SUPPORT */
00913
00914 /* Internal defines for HAL macro usage */
00915 #define FLASH_FLAG_REG_POS              16u
00916 #define FLASH_FLAG_SR_ID                1u
00917 #define FLASH_FLAG_CR_ID                2u
00918 #define FLASH_FLAG_ECCR1_ID             4u
00919 #define FLASH_FLAG_ECCR2_ID             8u
00920
00921 /**
00922   * @}
00923   */
00924
00925 /* Private macros ------------------------------------------------------------*/
00926 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00927   *  @{
00928   */
00929 #define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__)         (((__ADDRESS__) >= (FLASH_BASE))\
00930                                                         && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
00931
00932 #define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__)  (((__ADDRESS__) >= (FLASH_BASE))\
00933                                                            && ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL)))
00934 #if defined(FLASH_DBANK_SUPPORT)
00935 #define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE))\
00936                                                            && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
00937 #endif /* FLASH_DBANK_SUPPORT */
00938
00939 #define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
00940                                                         && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL)))
00941
00942 #define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__)      (((__ADDRESS__) >= 0x1FFF7000U)\
00943                                                         && ((__ADDRESS__) <= (0x1FFF7400U - 8UL)))
00944
00945 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)          ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__))\
00946                                                         || (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__)))
00947
00948 #define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__)     (((__ADDRESS__) >= (FLASH_BASE))\
00949                                                         && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL)))
00950
00951 #define IS_FLASH_PAGE(__PAGE__)                        ((__PAGE__) < FLASH_PAGE_NB)
00952
00953 #if defined(FLASH_DBANK_SUPPORT)
00954 #define IS_FLASH_BANK(__BANK__)                       \
00955   ((FLASH_BANK_NB == 2U) ?                         \
00956    (((__BANK__) == FLASH_BANK_1)  ||               \
00957     ((__BANK__) == FLASH_BANK_2)  ||                \
00958     ((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \
00959    ((__BANK__) == FLASH_BANK_1))
00960 #else
00961 #define IS_FLASH_BANK(__BANK__)                        ((__BANK__) == FLASH_BANK_1)
00962 #endif /* FLASH_DBANK_SUPPORT */
00963
00964 #define IS_FLASH_TYPEERASE(__VALUE__)                  (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
00965                                                         ((__VALUE__) == FLASH_TYPEERASE_MASS))
00966
00967 #define IS_FLASH_TYPEPROGRAM(__VALUE__)                (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
00968                                                         ((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
00969
00970 #define IS_OPTIONBYTE(__VALUE__)                       ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \
00971                                                         (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U))
00972
00973 #if defined(FLASH_DBANK_SUPPORT)
00974 #define IS_OB_WRPAREA(__VALUE__)                                                     \
00975   ((FLASH_BANK_NB == 2U) ?                                                        \
00976    (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) ||   \
00977     ((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) :  \
00978    (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B)))
00979 #else
00980 #define IS_OB_WRPAREA(__VALUE__)                       (((__VALUE__) == OB_WRPAREA_ZONE_A)\
00981                                                         || ((__VALUE__) == OB_WRPAREA_ZONE_B))
00982 #endif /* FLASH_DBANK_SUPPORT */
00983
00984 #define IS_OB_RDP_LEVEL(__LEVEL__)                     (((__LEVEL__) == OB_RDP_LEVEL_0)   ||\
00985                                                         ((__LEVEL__) == OB_RDP_LEVEL_1)   ||\
00986                                                         ((__LEVEL__) == OB_RDP_LEVEL_2))
00987
00988 #define IS_OB_USER_TYPE(__TYPE__)                      ((((__TYPE__) & OB_USER_ALL) != 0x00U) && \
00989                                                         (((__TYPE__) & ~OB_USER_ALL) == 0x00U))
00990
00991 #define IS_OB_USER_CONFIG(__TYPE__,__CONFIG__)         ((~(__TYPE__) & (__CONFIG__)) == 0x00U)
00992
00993 #if defined(FLASH_PCROP_SUPPORT)
00994 #if defined(FLASH_DBANK_SUPPORT)
00995 #define IS_OB_PCROP_CONFIG(__CONFIG__)                                                           \
00996   ((FLASH_BANK_NB == 2U) ?                                                                    \
00997    (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B |                                     \
00998                       OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U):   \
00999    (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U))
01000 #else
01001 #define IS_OB_PCROP_CONFIG(__CONFIG__)                 (((__CONFIG__)\
01002                                                          & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U)
01003 #endif /* FLASH_DBANK_SUPPORT */
01004 #endif /* FLASH_PCROP_SUPPORT */
01005
01006 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
01007 #define IS_OB_SEC_BOOT_LOCK(__VALUE__)                 (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE)\
01008                                                         || ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH))
01009
01010 #define IS_OB_SEC_SIZE(__VALUE__)                      ((__VALUE__) < (FLASH_PAGE_NB + 1U))
01011 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
01012
01013 #define IS_FLASH_LATENCY(__LATENCY__)                  (((__LATENCY__) == FLASH_LATENCY_0) || \
01014                                                         ((__LATENCY__) == FLASH_LATENCY_1) || \
01015                                                         ((__LATENCY__) == FLASH_LATENCY_2))
01016 /**
01017   * @}
01018   */
01019
01020 /**
01021   * @}
01022   */
01023
01024 /**
01025   * @}
01026   */
01027
01028 #ifdef __cplusplus
01029 }
01030 #endif
01031
01032 #endif /* STM32G0xx_HAL_FLASH_H */
01033
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_flash_ex.c Source File

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stm32g0xx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the FLASH extended peripheral:
00008   *           + Extended programming operations functions
00009   *
00010  @verbatim
00011  ==============================================================================
00012                    ##### Flash Extended features #####
00013   ==============================================================================
00014
00015   [..] Comparing to other previous devices, the FLASH interface for STM32G0xx
00016        devices contains the following additional features
00017
00018        (+) Capacity up to 128 Kbytes with single bank architecture supporting read-while-write
00019            capability (RWW)
00020        (+) Single bank memory organization
00021        (+) PCROP protection
00022
00023                         ##### How to use this driver #####
00024  ==============================================================================
00025   [..] This driver provides functions to configure and program the FLASH memory
00026        of all STM32G0xx devices. It includes
00027       (#) Flash Memory Erase functions:
00028            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00029                 HAL_FLASH_Lock() functions
00030            (++) Erase function: Erase page, erase all sectors
00031            (++) There are two modes of erase :
00032              (+++) Polling Mode using HAL_FLASHEx_Erase()
00033              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
00034
00035       (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
00036         (++) Set/Reset the write protection
00037         (++) Set the Read protection Level
00038         (++) Program the user Option Bytes
00039         (++) Configure the PCROP protection
00040         (++) Set Securable memory area and boot entry point
00041
00042       (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
00043         (++) Get the value of a write protection area
00044         (++) Know if the read protection is activated
00045         (++) Get the value of the user Option Bytes
00046         (++) Get Securable memory area and boot entry point information
00047
00048       (#) Enable or disable debugger usage using HAL_FLASHEx_EnableDebugger and
00049           HAL_FLASHEx_DisableDebugger.
00050
00051       (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck.
00052           and modify this setting (for flash loader purpose e.g.) using
00053           HAL_FLASHEx_ForceFlashEmpty.
00054
00055       (#) Enable securable memory area protectionusing HAL_FLASHEx_EnableSecMemProtection
00056
00057  @endverbatim
00058   ******************************************************************************
00059   * @attention
00060   *
00061   * Copyright (c) 2018 STMicroelectronics.
00062   * All rights reserved.
00063   *
00064   * This software is licensed under terms that can be found in the LICENSE file in
00065   * the root directory of this software component.
00066   * If no LICENSE file comes with this software, it is provided AS-IS.
00067   ******************************************************************************
00068   */
00069
00070 /* Includes ------------------------------------------------------------------*/
00071 #include "stm32g0xx_hal.h"
00072
00073 /** @addtogroup STM32G0xx_HAL_Driver
00074   * @{
00075   */
00076
00077 /** @defgroup FLASHEx FLASHEx
00078   * @brief FLASH Extended HAL module driver
00079   * @{
00080   */
00081
00082 #ifdef HAL_FLASH_MODULE_ENABLED
00083
00084 /* Private typedef -----------------------------------------------------------*/
00085 /* Private define ------------------------------------------------------------*/
00086 /* Private macro -------------------------------------------------------------*/
00087 /* Private variables ---------------------------------------------------------*/
00088 /* Private function prototypes -----------------------------------------------*/
00089 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00090   * @{
00091   */
00092 static void               FLASH_MassErase(uint32_t Banks);
00093 void                      FLASH_FlushCaches(void);
00094 static void               FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
00095 static void               FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset);
00096 static void               FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel);
00097 static uint32_t           FLASH_OB_GetRDP(void);
00098 static uint32_t           FLASH_OB_GetUser(void);
00099 #if defined(FLASH_PCROP_SUPPORT)
00100 static void               FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr,
00101                                                  uint32_t PCROP1AEndAddr);
00102 static void               FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr);
00103 static void               FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr,
00104                                               uint32_t *PCROP1AEndAddr);
00105 static void               FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr);
00106 #if defined(FLASH_DBANK_SUPPORT)
00107 static void               FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr);
00108 static void               FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr);
00109 static void               FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr);
00110 static void               FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr);
00111 #endif /* FLASH_DBANK_SUPPORT */
00112 #endif /* FLASH_PCROP_SUPPORT */
00113 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00114 #if defined(FLASH_DBANK_SUPPORT)
00115 static void               FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2);
00116 static void               FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2);
00117 #else
00118 static void               FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize);
00119 static void               FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize);
00120 #endif /* FLASH_DBANK_SUPPORT */
00121 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported functions -------------------------------------------------------*/
00127 /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
00128   * @{
00129   */
00130
00131 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
00132   *  @brief   Extended IO operation functions
00133   *
00134 @verbatim
00135  ===============================================================================
00136                 ##### Extended programming operation functions #####
00137  ===============================================================================
00138     [..]
00139     This subsection provides a set of functions allowing to manage the Extended FLASH
00140     programming operations Operations.
00141
00142 @endverbatim
00143   * @{
00144   */
00145 /**
00146   * @brief  Perform a mass erase or erase the specified FLASH memory pages.
00147   * @param[in]  pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
00148   *         contains the configuration information for the erasing.
00149   * @param[out]  PageError Pointer to variable that contains the configuration
00150   *         information on faulty page in case of error (0xFFFFFFFF means that all
00151   *         the pages have been correctly erased)
00152   * @retval HAL Status
00153   */
00154 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
00155 {
00156   HAL_StatusTypeDef status;
00157   uint32_t index;
00158
00159   /* Check the parameters */
00160   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00161
00162   /* Process Locked */
00163   __HAL_LOCK(&pFlash);
00164
00165   /* Reset error code */
00166   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00167
00168   /* Wait for last operation to be completed */
00169   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00170
00171   if (status == HAL_OK)
00172   {
00173 #if !defined(FLASH_DBANK_SUPPORT)
00174     /* For single bank product force Banks to Bank 1 */
00175     pEraseInit->Banks = FLASH_BANK_1;
00176 #endif /* FLASH_DBANK_SUPPORT */
00177
00178     if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS)
00179     {
00180       /* Proceed to Mass Erase */
00181       FLASH_MassErase(pEraseInit->Banks);
00182
00183       /* Wait for last operation to be completed */
00184       status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00185     }
00186     else
00187     {
00188       /*Initialization of PageError variable*/
00189       *PageError = 0xFFFFFFFFU;
00190
00191       for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++)
00192       {
00193         /* Start erase page */
00194         FLASH_PageErase(pEraseInit->Banks, index);
00195
00196         /* Wait for last operation to be completed */
00197         status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00198
00199         if (status != HAL_OK)
00200         {
00201           /* In case of error, stop erase procedure and return the faulty address */
00202           *PageError = index;
00203           break;
00204         }
00205       }
00206
00207       /* If operation is completed or interrupted, disable the Page Erase Bit */
00208       CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
00209     }
00210   }
00211
00212   /* Process Unlocked */
00213   __HAL_UNLOCK(&pFlash);
00214
00215   /* return status */
00216   return status;
00217 }
00218
00219
00220 /**
00221   * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
00222   * @param  pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
00223   *         contains the configuration information for the erasing.
00224   * @retval HAL Status
00225   */
00226 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00227 {
00228   HAL_StatusTypeDef status;
00229
00230   /* Check the parameters */
00231   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00232
00233   /* Process Locked */
00234   __HAL_LOCK(&pFlash);
00235
00236   /* Reset error code */
00237   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00238
00239   /* save procedure for interrupt treatment */
00240   pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
00241
00242   /* Wait for last operation to be completed */
00243   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00244
00245   if (status != HAL_OK)
00246   {
00247     /* Process Unlocked */
00248     __HAL_UNLOCK(&pFlash);
00249   }
00250   else
00251   {
00252 #if !defined(FLASH_DBANK_SUPPORT)
00253     /* For single bank product force Banks to Bank 1 */
00254     pEraseInit->Banks = FLASH_BANK_1;
00255 #endif /* FLASH_DBANK_SUPPORT */
00256     /* Store Bank number */
00257     pFlash.Banks = pEraseInit->Banks;
00258
00259     /* Enable End of Operation and Error interrupts */
00260     FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE;
00261
00262     if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS)
00263     {
00264       /* Set Page to 0 for Interrupt callback management */
00265       pFlash.Page = 0;
00266
00267       /* Proceed to Mass Erase */
00268       FLASH_MassErase(pEraseInit->Banks);
00269     }
00270     else
00271     {
00272       /* Erase by page to be done */
00273       pFlash.NbPagesToErase = pEraseInit->NbPages;
00274       pFlash.Page = pEraseInit->Page;
00275
00276       /*Erase 1st page and wait for IT */
00277       FLASH_PageErase(pEraseInit->Banks, pEraseInit->Page);
00278     }
00279   }
00280
00281   /* return status */
00282   return status;
00283 }
00284
00285 /**
00286   * @brief  Program Option bytes.
00287   * @param  pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that
00288   *         contains the configuration information for the programming.
00289   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
00290   *         cleared with the call of @ref HAL_FLASH_OB_Unlock() function.
00291   * @note   New option bytes configuration will be taken into account only
00292   *         - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch()
00293   *         - a Power On Reset
00294   *         - an exit from Standby or Shutdown mode.
00295   * @retval HAL Status
00296   */
00297 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00298 {
00299   uint32_t optr;
00300   HAL_StatusTypeDef status;
00301
00302   /* Check the parameters */
00303   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00304
00305   /* Process Locked */
00306   __HAL_LOCK(&pFlash);
00307
00308   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00309
00310   /* Write protection configuration */
00311   if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0x00U)
00312   {
00313     /* Configure of Write protection on the selected area */
00314     FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
00315   }
00316
00317   /* Option register */
00318   if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER))
00319   {
00320     /* Fully modify OPTR register with RDP & user data */
00321     FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->RDPLevel);
00322   }
00323   else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0x00U)
00324   {
00325     /* Only modify RDP so get current user data */
00326     optr = FLASH_OB_GetUser();
00327     FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel);
00328   }
00329   else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0x00U)
00330   {
00331     /* Only modify user so get current RDP level */
00332     optr = FLASH_OB_GetRDP();
00333     FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, optr);
00334   }
00335   else
00336   {
00337     /* nothing to do */
00338   }
00339
00340 #if defined(FLASH_PCROP_SUPPORT)
00341   /* PCROP Configuration */
00342   if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0x00U)
00343   {
00344     /* Check the parameters */
00345     assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig));
00346
00347     if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0x00U)
00348     {
00349       /* Configure the 1A Proprietary code readout protection */
00350       FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr);
00351     }
00352
00353     if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0x00U)
00354     {
00355       /* Configure the 1B Proprietary code readout protection */
00356       FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr);
00357     }
00358
00359 #if defined(FLASH_DBANK_SUPPORT)
00360     if ((pOBInit->PCROPConfig & OB_PCROP_ZONE2_A) != 0x00U)
00361     {
00362       /* Configure the 2A Proprietary code readout protection */
00363       FLASH_OB_PCROP2AConfig(pOBInit->PCROP2AStartAddr, pOBInit->PCROP2AEndAddr);
00364     }
00365
00366     if ((pOBInit->PCROPConfig & OB_PCROP_ZONE2_B) != 0x00U)
00367     {
00368       /* Configure the 2B Proprietary code readout protection */
00369       FLASH_OB_PCROP2BConfig(pOBInit->PCROP2BStartAddr, pOBInit->PCROP2BEndAddr);
00370     }
00371 #endif /* FLASH_DBANK_SUPPORT */
00372   }
00373 #endif /* FLASH_PCROP_SUPPORT */
00374
00375 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00376   /* Securable Memory Area Configuration */
00377   if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0x00U)
00378   {
00379 #if defined(FLASH_DBANK_SUPPORT)
00380     /* Configure the securable memory area protection */
00381     FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize, pOBInit->SecSize2);
00382 #else
00383     /* Configure the securable memory area protection */
00384     FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize);
00385 #endif /* FLASH_DBANK_SUPPORT */
00386   }
00387 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
00388
00389   /* Wait for last operation to be completed */
00390   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00391
00392   if (status == HAL_OK)
00393   {
00394     /* Set OPTSTRT Bit */
00395     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00396
00397     /* Wait for last operation to be completed */
00398     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00399
00400     /* If the option byte program operation is completed, disable the OPTSTRT Bit */
00401     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00402   }
00403
00404   /* Process Unlocked */
00405   __HAL_UNLOCK(&pFlash);
00406
00407   /* return status */
00408   return status;
00409 }
00410
00411 /**
00412   * @brief  Get the Option bytes configuration.
00413   * @note   warning: this API only read flash register, it does not reflect any
00414   *         change that would have been programmed between previous Option byte
00415   *         loading and current call.
00416   * @param  pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the
00417   *                  configuration information. The fields pOBInit->WRPArea should
00418   *                  indicate which area is requested for the WRP.
00419   * @retval None
00420   */
00421 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00422 {
00423   pOBInit->OptionType = OPTIONBYTE_ALL;
00424
00425   /* Get write protection on the selected area */
00426   FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
00427
00428   /* Get Read protection level */
00429   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00430
00431   /* Get the user option bytes */
00432   pOBInit->USERConfig = FLASH_OB_GetUser();
00433   pOBInit->USERType = OB_USER_ALL;
00434
00435 #if defined(FLASH_PCROP_SUPPORT)
00436   /* Get the Proprietary code readout protection */
00437   FLASH_OB_GetPCROP1A(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr));
00438   FLASH_OB_GetPCROP1B(&(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr));
00439   pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B);
00440 #if defined(FLASH_DBANK_SUPPORT)
00441   FLASH_OB_GetPCROP2A(&(pOBInit->PCROP2AStartAddr), &(pOBInit->PCROP2AEndAddr));
00442   FLASH_OB_GetPCROP2B(&(pOBInit->PCROP2BStartAddr), &(pOBInit->PCROP2BEndAddr));
00443   pOBInit->PCROPConfig |= (OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B);
00444 #endif /* FLASH_DBANK_SUPPORT */
00445 #endif /* FLASH_PCROP_SUPPORT */
00446
00447 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00448 #if defined(FLASH_DBANK_SUPPORT)
00449   /* Get the Securable Memory Area protection */
00450   FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize), &(pOBInit->SecSize2));
00451 #else
00452   /* Get the Securable Memory Area protection */
00453   FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize));
00454 #endif /* FLASH_DBANK_SUPPORT */
00455 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
00456 }
00457
00458 #if defined(FLASH_ACR_DBG_SWEN)
00459 /**
00460   * @brief  Enable Debugger.
00461   * @note   After calling this API, flash interface allow debugger intrusion.
00462   * @retval None
00463   */
00464 void HAL_FLASHEx_EnableDebugger(void)
00465 {
00466   FLASH->ACR |= FLASH_ACR_DBG_SWEN;
00467 }
00468
00469
00470 /**
00471   * @brief  Disable Debugger.
00472   * @note   After calling this API, Debugger is disabled: it is no more possible to
00473   *         break, see CPU register, etc...
00474   * @retval None
00475   */
00476 void HAL_FLASHEx_DisableDebugger(void)
00477 {
00478   FLASH->ACR &= ~FLASH_ACR_DBG_SWEN;
00479 }
00480 #endif /* FLASH_ACR_DBG_SWEN */
00481
00482 /**
00483   * @brief  Flash Empty check
00484   * @note   This API checks if first location in Flash is programmed or not.
00485   *         This check is done once by Option Byte Loader.
00486   * @retval 0 if 1st location is not programmed else
00487   */
00488 uint32_t HAL_FLASHEx_FlashEmptyCheck(void)
00489 {
00490   return ((FLASH->ACR & FLASH_ACR_PROGEMPTY));
00491 }
00492
00493
00494 /**
00495   * @brief  Force Empty check value.
00496   * @note   Allows to modify program empty check value in order to force this
00497   *         infrmation in Flash Interface, for all next reset that do not launch
00498   *         Option Byte Loader.
00499   * @param  FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check
00500   * @retval None
00501   */
00502 void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty)
00503 {
00504   uint32_t acr;
00505   assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty));
00506
00507   acr = (FLASH->ACR & ~FLASH_ACR_PROGEMPTY);
00508   FLASH->ACR = (acr | FlashEmpty);
00509 }
00510
00511
00512 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00513 /**
00514   * @brief  Securable memory area protection enable
00515   * @param  Banks Select Bank to be secured.
00516   *         This parameter can be a value of @ref FLASH_Banks
00517   * @note   On some devices, there is only 1 bank so parameter has to be set FLASH_BANK_1.
00518   * @note   This API locks Securable memory area which is defined in SEC_SIZE option byte
00519   *         (that can be retrieved calling HAL_FLASHEx_OBGetConfig API and checking
00520   *         Secsize).
00521   * @note   SEC_PROT bit can only be set, it will be reset by system reset.
00522   * @retval None
00523   */
00524 void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks)
00525 {
00526 #if defined(FLASH_DBANK_SUPPORT)
00527   assert_param(IS_FLASH_BANK(Banks));
00528
00529   if (Banks == (FLASH_BANK_2  | FLASH_BANK_1))
00530   {
00531     FLASH->CR |= (FLASH_CR_SEC_PROT2 | FLASH_CR_SEC_PROT);
00532   }
00533   else if (Banks == FLASH_BANK_2)
00534   {
00535     FLASH->CR |= FLASH_CR_SEC_PROT2;
00536   }
00537   else
00538 #else
00539   UNUSED(Banks);
00540 #endif /* FLASH_DBANK_SUPPORT */
00541   {
00542     FLASH->CR |= FLASH_CR_SEC_PROT;
00543   }
00544 }
00545 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
00546 /**
00547   * @}
00548   */
00549
00550 /**
00551   * @}
00552   */
00553
00554 /* Private functions ---------------------------------------------------------*/
00555 /** @addtogroup FLASHEx_Private_Functions
00556   * @{
00557   */
00558
00559 /**
00560   * @brief  Mass erase of FLASH memory.
00561   * @param  Banks: Banks to be erased
00562   *         This parameter can be a combination of the following values:
00563   *            @arg FLASH_BANK_1: Bank1 to be erased
00564   *            @arg FLASH_BANK_2: Bank2 to be erased*
00565   * @note (*) availability depends on devices
00566   * @retval None
00567   */
00568 static void FLASH_MassErase(uint32_t Banks)
00569 {
00570   /* Check the parameters */
00571   assert_param(IS_FLASH_BANK(Banks));
00572
00573   /* Set the Mass Erase Bit and start bit */
00574   FLASH->CR |= (FLASH_CR_STRT | Banks);
00575 }
00576
00577 /**
00578   * @brief  Erase the specified FLASH memory page.
00579   * @param  Banks: Banks to be erased
00580   *         This parameter can one of the following values:
00581   *            @arg FLASH_BANK_1: Bank1 to be erased
00582   *            @arg FLASH_BANK_2: Bank2 to be erased*
00583   * @param  Page FLASH page to erase
00584   *         This parameter must be a value between 0 and (max number of pages in Flash - 1)
00585   * @note (*) availability depends on devices
00586   * @retval None
00587   */
00588 void FLASH_PageErase(uint32_t Banks, uint32_t Page)
00589 {
00590   uint32_t tmp;
00591
00592   /* Check the parameters */
00593   assert_param(IS_FLASH_BANK(Banks));
00594   assert_param(IS_FLASH_PAGE(Page));
00595
00596   /* Get configuration register, then clear page number */
00597   tmp = (FLASH->CR & ~FLASH_CR_PNB);
00598
00599 #if defined(FLASH_DBANK_SUPPORT)
00600   /* Check if page has to be erased in bank 1 or 2 */
00601   if (Banks != FLASH_BANK_1)
00602   {
00603     tmp |= FLASH_CR_BKER;
00604   }
00605   else
00606   {
00607     tmp &= ~FLASH_CR_BKER;
00608   }
00609 #endif /* FLASH_DBANK_SUPPORT */
00610
00611   /* Set page number, Page Erase bit & Start bit */
00612   FLASH->CR = (tmp | (FLASH_CR_STRT | (Page <<  FLASH_CR_PNB_Pos) | FLASH_CR_PER));
00613 }
00614
00615 /**
00616   * @brief  Flush the instruction cache.
00617   * @retval None
00618   */
00619 void FLASH_FlushCaches(void)
00620 {
00621   /* Flush instruction cache  */
00622   if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
00623   {
00624     /* Disable instruction cache  */
00625     __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00626     /* Reset instruction cache */
00627     __HAL_FLASH_INSTRUCTION_CACHE_RESET();
00628     /* Enable instruction cache */
00629     __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
00630   }
00631 }
00632
00633
00634 /**
00635   * @brief  Configure the write protection of the desired pages.
00636   * @note   When WRP is active in a zone, it cannot be erased or programmed.
00637   *         Consequently, a software mass erase cannot be performed if one zone
00638   *         is write-protected.
00639   * @note   When the memory read protection level is selected (RDP level = 1),
00640   *         it is not possible to program or erase Flash memory if the CPU debug
00641   *         features are connected (JTAG or single wire) or boot code is being
00642   *         executed from RAM or System flash, even if WRP is not activated.
00643   * @param  WRPArea  Specifies the area to be configured.
00644   *         This parameter can be one of the following values:
00645   *           @arg @ref OB_WRPAREA_ZONE_A Flash Zone A
00646   *           @arg @ref OB_WRPAREA_ZONE_B Flash Zone B
00647   *           @arg @ref OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*)
00648   *           @arg @ref OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*)
00649   * @note  (*) availability depends on devices
00650   * @param  WRPStartOffset  Specifies the start page of the write protected area
00651   *         This parameter can be page number between 0 and (max number of pages in the Flash Bank - 1)
00652   * @param  WRDPEndOffset  Specifies the end page of the write protected area
00653   *         This parameter can be page number between WRPStartOffset and (max number of pages in the Flash Bank - 1)
00654   * @retval None
00655   */
00656 static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
00657 {
00658   /* Check the parameters */
00659   assert_param(IS_OB_WRPAREA(WRPArea));
00660   assert_param(IS_FLASH_PAGE(WRPStartOffset));
00661   assert_param(IS_FLASH_PAGE(WRDPEndOffset));
00662
00663   /* Configure the write protected area */
00664   if (WRPArea == OB_WRPAREA_ZONE_A)
00665   {
00666     FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset);
00667   }
00668 #if defined(FLASH_DBANK_SUPPORT)
00669   else if (WRPArea == OB_WRPAREA_ZONE2_A)
00670   {
00671     FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset);
00672   }
00673   else if (WRPArea == OB_WRPAREA_ZONE2_B)
00674   {
00675     FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset);
00676   }
00677 #endif /* FLASH_DBANK_SUPPORT */
00678   else
00679   {
00680     FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset);
00681   }
00682 }
00683
00684 /**
00685   * @brief  Return the FLASH Write Protection Option Bytes value.
00686   * @param[in]  WRPArea Specifies the area to be returned.
00687   *             This parameter can be one of the following values:
00688   *               @arg @ref OB_WRPAREA_ZONE_A Flash Zone A
00689   *               @arg @ref OB_WRPAREA_ZONE_B Flash Zone B
00690   *               @arg @ref OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*)
00691   *               @arg @ref OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*)
00692   * @note  (*) availability depends on devices
00693   * @param[out]  WRPStartOffset  Specifies the address where to copied the start page
00694   *                         of the write protected area
00695   * @param[out]  WRDPEndOffset  Dpecifies the address where to copied the end page of
00696   *                        the write protected area
00697   * @retval None
00698   */
00699 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
00700 {
00701   /* Check the parameters */
00702   assert_param(IS_OB_WRPAREA(WRPArea));
00703
00704   /* Get the configuration of the write protected area */
00705   if (WRPArea == OB_WRPAREA_ZONE_A)
00706   {
00707     *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
00708     *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos);
00709   }
00710 #if defined(FLASH_DBANK_SUPPORT)
00711   else if (WRPArea == OB_WRPAREA_ZONE2_A)
00712   {
00713     *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
00714     *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos);
00715   }
00716   else if (WRPArea == OB_WRPAREA_ZONE2_B)
00717   {
00718     *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
00719     *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos);
00720   }
00721 #endif /* FLASH_DBANK_SUPPORT */
00722   else
00723   {
00724     *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
00725     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos);
00726   }
00727 }
00728
00729 /**
00730   * @brief  Set user & RDP configuration
00731   * @note   !!! Warning : When enabling OB_RDP level 2 it is no more possible
00732   *         to go back to level 1 or 0 !!!
00733   * @param  UserType  The FLASH User Option Bytes to be modified.
00734   *         This parameter can be a combination of @ref FLASH_OB_USER_Type
00735   * @param  UserConfig  The FLASH User Option Bytes values.
00736   *         This parameter can be a combination of:
00737   *           @arg @ref FLASH_OB_USER_BOR_ENABLE(*)
00738   *           @arg @ref FLASH_OB_USER_BOR_LEVEL(*)
00739   *           @arg @ref FLASH_OB_USER_RESET_CONFIG(*)
00740   *           @arg @ref FLASH_OB_USER_nRST_STOP
00741   *           @arg @ref FLASH_OB_USER_nRST_STANDBY
00742   *           @arg @ref FLASH_OB_USER_nRST_SHUTDOWN(*)
00743   *           @arg @ref FLASH_OB_USER_IWDG_SW
00744   *           @arg @ref FLASH_OB_USER_IWDG_STOP
00745   *           @arg @ref FLASH_OB_USER_IWDG_STANDBY
00746   *           @arg @ref FLASH_OB_USER_WWDG_SW
00747   *           @arg @ref FLASH_OB_USER_SRAM_PARITY
00748   *           @arg @ref FLASH_OB_USER_BANK_SWAP(*)
00749   *           @arg @ref FLASH_OB_USER_DUAL_BANK(*)
00750   *           @arg @ref FLASH_OB_USER_nBOOT_SEL
00751   *           @arg @ref FLASH_OB_USER_nBOOT1
00752   *           @arg @ref FLASH_OB_USER_nBOOT0
00753   *           @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*)
00754   * @param  RDPLevel  specifies the read protection level.
00755   *         This parameter can be one of the following values:
00756   *           @arg @ref OB_RDP_LEVEL_0 No protection
00757   *           @arg @ref OB_RDP_LEVEL_1 Memory Read protection
00758   *           @arg @ref OB_RDP_LEVEL_2 Full chip protection
00759   * @note  (*) availability depends on devices
00760   * @retval None
00761   */
00762 static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel)
00763 {
00764   uint32_t optr;
00765
00766   /* Check the parameters */
00767   assert_param(IS_OB_USER_TYPE(UserType));
00768   assert_param(IS_OB_USER_CONFIG(UserType, UserConfig));
00769   assert_param(IS_OB_RDP_LEVEL(RDPLevel));
00770
00771   /* Configure the RDP level in the option bytes register */
00772   optr = FLASH->OPTR;
00773   optr &= ~(UserType | FLASH_OPTR_RDP);
00774   FLASH->OPTR = (optr | UserConfig | RDPLevel);
00775 }
00776
00777 /**
00778   * @brief  Return the FLASH Read Protection level.
00779   * @retval FLASH ReadOut Protection Status:
00780   *         This return value can be one of the following values:
00781   *           @arg @ref OB_RDP_LEVEL_0 No protection
00782   *           @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
00783   *           @arg @ref OB_RDP_LEVEL_2 Full chip protection
00784   */
00785 static uint32_t FLASH_OB_GetRDP(void)
00786 {
00787   uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
00788
00789   if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2))
00790   {
00791     return (OB_RDP_LEVEL_1);
00792   }
00793   else
00794   {
00795     return rdplvl;
00796   }
00797 }
00798
00799 /**
00800   * @brief  Return the FLASH User Option Byte value.
00801   * @retval The FLASH User Option Bytes values. It will be a combination of all the following values:
00802   *           @arg @ref FLASH_OB_USER_BOR_ENABLE(*)
00803   *           @arg @ref FLASH_OB_USER_BOR_LEVEL(*)
00804   *           @arg @ref FLASH_OB_USER_RESET_CONFIG(*)
00805   *           @arg @ref FLASH_OB_USER_nRST_STOP
00806   *           @arg @ref FLASH_OB_USER_nRST_STANDBY
00807   *           @arg @ref FLASH_OB_USER_nRST_SHUTDOWN(*)
00808   *           @arg @ref FLASH_OB_USER_IWDG_SW
00809   *           @arg @ref FLASH_OB_USER_IWDG_STOP
00810   *           @arg @ref FLASH_OB_USER_IWDG_STANDBY
00811   *           @arg @ref FLASH_OB_USER_WWDG_SW
00812   *           @arg @ref FLASH_OB_USER_SRAM_PARITY
00813   *           @arg @ref FLASH_OB_USER_BANK_SWAP(*)
00814   *           @arg @ref FLASH_OB_USER_DUAL_BANK(*)
00815   *           @arg @ref FLASH_OB_USER_nBOOT_SEL
00816   *           @arg @ref FLASH_OB_USER_nBOOT1
00817   *           @arg @ref FLASH_OB_USER_nBOOT0
00818   *           @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*)
00819   * @note  (*) availability depends on devices
00820   */
00821 static uint32_t FLASH_OB_GetUser(void)
00822 {
00823   uint32_t user = ((FLASH->OPTR & ~FLASH_OPTR_RDP) & OB_USER_ALL);
00824   return user;
00825 }
00826
00827 #if defined(FLASH_PCROP_SUPPORT)
00828 /**
00829   * @brief  Configure the 1A Proprietary code readout protection & erase configuration on RDP regression.
00830   * @note   It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid
00831   *         having some executable code in a page where PCROP zone starts or ends.
00832   * @note   Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END.
00833   *         So if the requirement is to be able to read-protect 1KB areas, the ROP granularity
00834   *         has to be set to 512 Bytes
00835   * @param  PCROPConfig  specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE)
00836   *         on RDP level 1 regression.
00837   * @param  PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection
00838   *          This parameter can be an address between begin and end of the flash
00839   * @param  PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection
00840   *          This parameter can be an address between PCROP1AStartAddr and end of the flash
00841   * @retval None
00842   */
00843 static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
00844 {
00845   uint32_t startoffset;
00846   uint32_t endoffset;
00847   uint32_t pcrop1aend;
00848   uint32_t ropbase;
00849
00850   /* Check the parameters */
00851   assert_param(IS_OB_PCROP_CONFIG(PCROPConfig));
00852
00853 #if defined(FLASH_DBANK_SUPPORT)
00854   /* Check if banks are swapped (valid if only one bank) */
00855   if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U))
00856   {
00857     /* Check the parameters */
00858     assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AStartAddr));
00859     assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AEndAddr));
00860
00861     /* Bank swap, bank 1 read only protection is on second half of Flash */
00862     ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
00863   }
00864   else
00865 #endif /* FLASH_DBANK_SUPPORT */
00866   {
00867     /* Check the parameters */
00868     assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AStartAddr));
00869     assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AEndAddr));
00870
00871     /* No Bank swap, bank 1 read only protection is on first half of Flash */
00872     ropbase = FLASH_BASE;
00873   }
00874
00875   /* get pcrop 1A end register */
00876   pcrop1aend = FLASH->PCROP1AER;
00877
00878   /* Configure the Proprietary code readout protection offset */
00879   if ((PCROPConfig & OB_PCROP_ZONE_A) != 0x00U)
00880   {
00881     /* Compute offset depending on pcrop granularity */
00882     startoffset = ((PCROP1AStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET);
00883     endoffset = ((PCROP1AEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET);
00884
00885     /* Set Zone A start offset */
00886     FLASH->PCROP1ASR = startoffset;
00887
00888     /* Set Zone A end offset */
00889     pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END;
00890     pcrop1aend |= endoffset;
00891   }
00892
00893   /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */
00894   if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0x00U)
00895   {
00896     pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP;
00897   }
00898
00899   /* set 1A End register */
00900   FLASH->PCROP1AER = pcrop1aend;
00901 }
00902
00903 /**
00904   * @brief  Configure the 1B Proprietary code readout protection.
00905   * @note   It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid
00906   *         having some executable code in a page where PCROP zone starts or ends.
00907   * @note   Minimum PCROP area size is 2 times the chosen granularity: PCROPB_STRT and PCROPB_END.
00908   *         So if the requirement is to be able to read-protect 1KB areas, the ROP granularity
00909   *         has to be set to 512 Bytes
00910   * @param  PCROP1BStartAddr  Specifies the Zone 1B Start address of the Proprietary code readout protection
00911   *         This parameter can be an address between begin and end of the flash
00912   * @param  PCROP1BEndAddr  Specifies the Zone 1B end address of the Proprietary code readout protection
00913   *         This parameter can be an address between PCROP1BStartAddr and end of the flash
00914   * @retval None
00915   */
00916 static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
00917 {
00918   uint32_t startoffset;
00919   uint32_t endoffset;
00920   uint32_t ropbase;
00921
00922 #if defined(FLASH_DBANK_SUPPORT)
00923   /* Check if banks are swapped (valid if only one bank) */
00924   if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U))
00925   {
00926     /* Check the parameters */
00927     assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BStartAddr));
00928     assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BEndAddr));
00929
00930     /* Bank swap, bank 1 read only protection is on second half of Flash */
00931     ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
00932   }
00933   else
00934 #endif /* FLASH_DBANK_SUPPORT */
00935   {
00936     /* Check the parameters */
00937     assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BStartAddr));
00938     assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BEndAddr));
00939
00940     /* No Bank swap, bank 1 read only protection is on first half of Flash */
00941     ropbase = FLASH_BASE;
00942   }
00943
00944   /* Configure the Proprietary code readout protection offset */
00945   startoffset = ((PCROP1BStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET);
00946   endoffset = ((PCROP1BEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET);
00947
00948   /* Set Zone B start offset */
00949   FLASH->PCROP1BSR = startoffset;
00950   /* Set Zone B end offset */
00951   FLASH->PCROP1BER = endoffset;
00952 }
00953
00954 /**
00955   * @brief  Return the FLASH PCROP Protection Option Bytes value.
00956   * @param  PCROPConfig [out]  specifies the configuration of PCROP_RDP option.
00957   * @param  PCROP1AStartAddr [out]  Specifies the address where to copied the start address
00958   *         of the 1A Proprietary code readout protection
00959   * @param  PCROP1AEndAddr [out]  Specifies the address where to copied the end address of
00960   *         the 1A Proprietary code readout protection
00961   * @retval None
00962   */
00963 static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr)
00964 {
00965   uint32_t pcrop;
00966   uint32_t ropbase;
00967
00968 #if defined(FLASH_DBANK_SUPPORT)
00969   /* Check if banks are swapped (valid if only one bank) */
00970   if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U))
00971   {
00972     /* Bank swap, bank 1 read only protection is on second half of Flash */
00973     ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
00974   }
00975   else
00976 #endif /* FLASH_DBANK_SUPPORT */
00977   {
00978     /* No Bank swap, bank 1 read only protection is on first half of Flash */
00979     ropbase = FLASH_BASE;
00980   }
00981
00982   pcrop = (FLASH->PCROP1ASR & FLASH_PCROP1ASR_PCROP1A_STRT);
00983   *PCROP1AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
00984   *PCROP1AStartAddr += ropbase;
00985
00986   pcrop = FLASH->PCROP1AER;
00987   *PCROP1AEndAddr = ((pcrop & FLASH_PCROP1AER_PCROP1A_END) << FLASH_PCROP_GRANULARITY_OFFSET);
00988   *PCROP1AEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U);
00989
00990   *PCROPConfig &= ~OB_PCROP_RDP_ERASE;
00991   *PCROPConfig |= (pcrop & FLASH_PCROP1AER_PCROP_RDP);
00992 }
00993
00994 /**
00995   * @brief  Return the FLASH PCROP Protection Option Bytes value.
00996   * @param  PCROP1BStartAddr [out]  Specifies the address where to copied the start address
00997   *         of the 1B Proprietary code readout protection
00998   * @param  PCROP1BEndAddr [out]  Specifies the address where to copied the end address of
00999   *         the 1B Proprietary code readout protection
01000   * @retval None
01001   */
01002 static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr)
01003 {
01004   uint32_t pcrop;
01005   uint32_t ropbase;
01006
01007 #if defined(FLASH_DBANK_SUPPORT)
01008   /* Check if banks are swapped (valid if only one bank) */
01009   if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U))
01010   {
01011     /* Bank swap, bank 1 read only protection is on second half of Flash */
01012     ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
01013   }
01014   else
01015 #endif /* FLASH_DBANK_SUPPORT */
01016   {
01017     /* No Bank swap, bank 1 read only protection is on first half of Flash */
01018     ropbase = FLASH_BASE;
01019   }
01020
01021   pcrop = (FLASH->PCROP1BSR & FLASH_PCROP1BSR_PCROP1B_STRT);
01022   *PCROP1BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
01023   *PCROP1BStartAddr += ropbase;
01024
01025   pcrop = (FLASH->PCROP1BER & FLASH_PCROP1BER_PCROP1B_END);
01026   *PCROP1BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
01027   *PCROP1BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U);
01028 }
01029
01030 #if defined(FLASH_DBANK_SUPPORT)
01031 /**
01032   * @brief  Configure the 2A Proprietary code readout protection.
01033   * @note   It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid
01034   *         having some executable code in a page where PCROP zone starts or ends.
01035   * @note   Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END.
01036   *         So if the requirement is to be able to read-protect 1KB areas, the ROP granularity
01037   *         has to be set to 512 Bytes
01038   * @param  PCROP2AStartAddr  Specifies the Zone 2A Start address of the Proprietary code readout protection
01039   *         This parameter can be an address between begin and end of the flash
01040   * @param  PCROP2AEndAddr  Specifies the Zone 2A end address of the Proprietary code readout protection
01041   *         This parameter can be an address between PCROP2AStartAddr and end of the flash
01042   * @retval None
01043   */
01044 static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr)
01045 {
01046   uint32_t startoffset;
01047   uint32_t endoffset;
01048   uint32_t ropbase;
01049
01050   /* Check if banks are swapped */
01051   if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u)
01052   {
01053     /* Check the parameters */
01054     assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2AStartAddr));
01055     assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2AEndAddr));
01056
01057     /* No Bank swap, bank 2 read only protection is on second half of Flash */
01058     ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
01059   }
01060   else
01061   {
01062     /* Check the parameters */
01063     assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2AStartAddr));
01064     assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2AEndAddr));
01065
01066     /* Bank swap, bank 2 read only protection is on first half of Flash */
01067     ropbase = FLASH_BASE;
01068   }
01069
01070   /* Configure the Proprietary code readout protection offset */
01071   startoffset = ((PCROP2AStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET);
01072   endoffset = ((PCROP2AEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET);
01073
01074   /* Set Zone A start offset */
01075   FLASH->PCROP2ASR = startoffset;
01076   /* Set Zone A end offset */
01077   FLASH->PCROP2AER = endoffset;
01078 }
01079
01080 /**
01081   * @brief  Configure the 2B Proprietary code readout protection.
01082   * @note   It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid
01083   *         having some executable code in a page where PCROP zone starts or ends.
01084   * @note   Minimum PCROP area size is 2 times the chosen granularity: PCROP_STRT and PCROP_END.
01085   *         So if the requirement is to be able to read-protect 1KB areas, the ROP granularity
01086   *         has to be set to 512 Bytes
01087   * @param  PCROP2BStartAddr  Specifies the Zone 2B Start address of the Proprietary code readout protection
01088   *         This parameter can be an address between begin and end of the flash
01089   * @param  PCROP2BEndAddr  Specifies the Zone 2B end address of the Proprietary code readout protection
01090   *         This parameter can be an address between PCROP2BStartAddr and end of the flash
01091   * @retval None
01092   */
01093 static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr)
01094 {
01095   uint32_t startoffset;
01096   uint32_t endoffset;
01097   uint32_t ropbase;
01098
01099   /* Check if banks are swapped */
01100   if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u)
01101   {
01102     /* Check the parameters */
01103     assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2BStartAddr));
01104     assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2BEndAddr));
01105
01106     /* No Bank swap, bank 2 read only protection is on second half of Flash */
01107     ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
01108   }
01109   else
01110   {
01111     /* Check the parameters */
01112     assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2BStartAddr));
01113     assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2BEndAddr));
01114
01115     /* Bank swap, bank 2 read only protection is on first half of Flash */
01116     ropbase = FLASH_BASE;
01117   }
01118
01119   /* Configure the Proprietary code readout protection offset */
01120   startoffset = ((PCROP2BStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET);
01121   endoffset = ((PCROP2BEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET);
01122
01123   /* Set Zone B start offset */
01124   FLASH->PCROP2BSR = startoffset;
01125   /* Set Zone B end offset */
01126   FLASH->PCROP2BER = endoffset;
01127 }
01128
01129 /**
01130   * @brief  Return the FLASH PCROP Protection Option Bytes value.
01131   * @param  PCROP2AStartAddr [out]  Specifies the address where to copied the start address
01132   *         of the 2A Proprietary code readout protection
01133   * @param  PCROP2AEndAddr [out]  Specifies the address where to copied the end address of
01134   *         the 2A Proprietary code readout protection
01135   * @retval None
01136   */
01137 static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr)
01138 {
01139   uint32_t pcrop;
01140   uint32_t ropbase;
01141
01142   /* Check if banks are swapped */
01143   if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u)
01144   {
01145     /* No Bank swap, bank 2 read only protection is on second half of Flash */
01146     ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
01147   }
01148   else
01149   {
01150     /* Bank swap, bank 2 read only protection is on first half of Flash */
01151     ropbase = FLASH_BASE;
01152   }
01153
01154   pcrop = (FLASH->PCROP2ASR & FLASH_PCROP2ASR_PCROP2A_STRT);
01155   *PCROP2AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
01156   *PCROP2AStartAddr += ropbase;
01157
01158   pcrop = (FLASH->PCROP2AER & FLASH_PCROP2AER_PCROP2A_END);
01159   *PCROP2AEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
01160   *PCROP2AEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U);
01161 }
01162
01163 /**
01164   * @brief  Return the FLASH PCROP Protection Option Bytes value.
01165   * @param  PCROP2BStartAddr [out]  Specifies the address where to copied the start address
01166   *         of the 2B Proprietary code readout protection
01167   * @param  PCROP2BEndAddr [out]  Specifies the address where to copied the end address of
01168   *         the 2B Proprietary code readout protection
01169   * @retval None
01170   */
01171 static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr)
01172 {
01173   uint32_t pcrop;
01174   uint32_t ropbase;
01175
01176   /* Check if banks are swapped */
01177   if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u)
01178   {
01179     /* No Bank swap, bank 2 read only protection is on second half of Flash */
01180     ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
01181   }
01182   else
01183   {
01184     /* Bank swap, bank 2 read only protection is on first half of Flash */
01185     ropbase = FLASH_BASE;
01186   }
01187
01188   pcrop = (FLASH->PCROP2BSR & FLASH_PCROP2BSR_PCROP2B_STRT);
01189   *PCROP2BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
01190   *PCROP2BStartAddr += ropbase;
01191
01192   pcrop = (FLASH->PCROP2BER & FLASH_PCROP2BER_PCROP2B_END);
01193   *PCROP2BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
01194   *PCROP2BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U);
01195 }
01196 #endif /* FLASH_DBANK_SUPPORT */
01197 #endif /* FLASH_PCROP_SUPPORT */
01198
01199 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
01200 #if defined(FLASH_DBANK_SUPPORT)
01201 /**
01202   * @brief  Configure Securable Memory area feature.
01203   * @param  BootEntry  specifies if boot scheme is forced to Flash (System or user) or not
01204   *         This parameter can be one of the following values:
01205   *           @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced
01206   *           @arg @ref OB_BOOT_ENTRY_FORCED_FLASH Flash selected as unique entry boot
01207   * @param  SecSize specifies number of pages to protect as securable memory area, starting from
01208   *         beginning of Bank1 (page 0).
01209   * @param  SecSize2 specifies number of pages to protect as securable memory area, starting from
01210   *         beginning of Bank2 (page 0).
01211   * @retval None
01212   */
01213 static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2)
01214 {
01215   uint32_t secmem;
01216
01217   /* Check the parameters */
01218   assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry));
01219   assert_param(IS_OB_SEC_SIZE(SecSize));
01220
01221   if ((FLASH_BANK_NB == 2U))
01222   {
01223     assert_param(IS_OB_SEC_SIZE(SecSize2));
01224   }
01225
01226   /* Set securable memory area configuration */
01227   secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE | FLASH_SECR_SEC_SIZE2));
01228   FLASH->SECR = (secmem | BootEntry | SecSize | (SecSize2 << FLASH_SECR_SEC_SIZE2_Pos));
01229 }
01230
01231 /**
01232   * @brief  Return the FLASH Securable memory area protection Option Bytes value.
01233   * @param  BootEntry  specifies boot scheme configuration
01234   * @param  SecSize specifies number of pages to protect as secure memory area, starting from
01235   *         beginning of Bank1 (page 0).
01236   * @param  SecSize2 specifies number of pages to protect as secure memory area, starting from
01237   *         beginning of Bank2 (page 0).
01238   * @retval None
01239   */
01240 static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2)
01241 {
01242   uint32_t secmem = FLASH->SECR;
01243
01244   *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK);
01245   *SecSize = (secmem & FLASH_SECR_SEC_SIZE);
01246   *SecSize2 = (secmem & FLASH_SECR_SEC_SIZE2) >> FLASH_SECR_SEC_SIZE2_Pos;
01247 }
01248
01249 #else
01250 /**
01251   * @brief  Configure Securable Memory area feature.
01252   * @param  BootEntry  specifies if boot scheme is forced to Flash (System or user) or not
01253   *         This parameter can be one of the following values:
01254   *           @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced
01255   *           @arg @ref OB_BOOT_ENTRY_FORCED_FLASH FLash selected as unique entry boot
01256   * @param  SecSize specifies number of pages to protect as securable memory area, starting from
01257   *         beginning of the Flash (page 0).
01258   * @retval None
01259   */
01260 static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize)
01261 {
01262   uint32_t secmem;
01263
01264   /* Check the parameters */
01265   assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry));
01266   assert_param(IS_OB_SEC_SIZE(SecSize));
01267
01268   /* Set securable memory area configuration */
01269   secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE));
01270   FLASH->SECR = (secmem | BootEntry | SecSize);
01271 }
01272
01273 /**
01274   * @brief  Return the FLASH Securable memory area protection Option Bytes value.
01275   * @param  BootEntry  specifies boot scheme configuration
01276   * @param  SecSize specifies number of pages to protect as secure memory area, starting from
01277   *         beginning of the Flash (page 0).
01278   * @retval None
01279   */
01280 static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize)
01281 {
01282   uint32_t secmem = FLASH->SECR;
01283
01284   *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK);
01285   *SecSize = (secmem & FLASH_SECR_SEC_SIZE);
01286 }
01287 #endif /* FLASH_DBANK_SUPPORT */
01288 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
01289
01290 /**
01291   * @}
01292   */
01293
01294 /**
01295   * @}
01296   */
01297
01298 #endif /* HAL_FLASH_MODULE_ENABLED */
01299
01300 /**
01301   * @}
01302   */
01303
01304 /**
01305   * @}
01306   */
01307
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_flash_ex.h Source File

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stm32g0xx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G0xx_HAL_FLASH_EX_H
00020 #define STM32G0xx_HAL_FLASH_EX_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g0xx_hal_def.h"
00028
00029 /** @addtogroup STM32G0xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup FLASHEx
00034   * @{
00035   */
00036
00037 /* Exported types ------------------------------------------------------------*/
00038 /* Exported constants --------------------------------------------------------*/
00039 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
00040   * @{
00041   */
00042 /** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check
00043   * @{
00044   */
00045 #define FLASH_PROG_NOT_EMPTY                0x00000000u          /*!< 1st location in Flash is programmed */
00046 #define FLASH_PROG_EMPTY                    FLASH_ACR_PROGEMPTY  /*!< 1st location in Flash is empty */
00047 /**
00048   * @}
00049   */
00050 /**
00051   * @}
00052   */
00053
00054 /* Exported macro ------------------------------------------------------------*/
00055 /* Exported functions --------------------------------------------------------*/
00056 /** @addtogroup FLASHEx_Exported_Functions
00057   * @{
00058   */
00059
00060 /* Extended Program operation functions  *************************************/
00061 /** @addtogroup FLASHEx_Exported_Functions_Group1
00062   * @{
00063   */
00064 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
00065 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00066 void              HAL_FLASHEx_EnableDebugger(void);
00067 void              HAL_FLASHEx_DisableDebugger(void);
00068 uint32_t          HAL_FLASHEx_FlashEmptyCheck(void);
00069 void              HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
00070 #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
00071 void              HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks);
00072 #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
00073 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00074 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00075 /**
00076   * @}
00077   */
00078
00079 /**
00080   * @}
00081   */
00082
00083 /* Private macros ------------------------------------------------------------*/
00084 /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
00085   * @{
00086   */
00087 #define FLASH_PCROP_GRANULARITY_OFFSET             9u                                        /*!< FLASH Code Readout Protection granularity offset */
00088 #define FLASH_PCROP_GRANULARITY                    (1UL << FLASH_PCROP_GRANULARITY_OFFSET)   /*!< FLASH Code Readout Protection granularity, 512 Bytes */
00089 /**
00090   * @}
00091   */
00092
00093
00094 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
00095   *  @{
00096   */
00097 #define IS_FLASH_EMPTY_CHECK(__VALUE__)     (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
00098 void              FLASH_PageErase(uint32_t Banks, uint32_t Page);
00099 /**
00100   * @}
00101   */
00102
00103 /**
00104   * @}
00105   */
00106
00107 /**
00108   * @}
00109   */
00110
00111 #ifdef __cplusplus
00112 }
00113 #endif
00114
00115 #endif /* STM32G0xx_HAL_FLASH_EX_H */
00116
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_gpio.c Source File

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stm32g0xx_hal_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2018 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   ==============================================================================
00024                     ##### GPIO Peripheral features #####
00025   ==============================================================================
00026   [..]
00027     (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
00028         configured by software in several modes:
00029         (++) Input mode
00030         (++) Analog mode
00031         (++) Output mode
00032         (++) Alternate function mode
00033         (++) External interrupt/event lines
00034
00035     (+) During and just after reset, the alternate functions and external interrupt
00036         lines are not active and the I/O ports are configured in input floating mode.
00037
00038     (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00039         activated or not.
00040
00041     (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00042         type and the IO speed can be selected depending on the VDD value.
00043
00044     (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
00045         multiplexer that allows only one peripheral alternate function (AF) connected
00046        to an IO pin at a time. In this way, there can be no conflict between peripherals
00047        sharing the same IO pin.
00048
00049     (+) All ports have external interrupt/event capability. To use external interrupt
00050         lines, the port must be configured in input mode. All available GPIO pins are
00051         connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00052
00053     (+) The external interrupt/event controller consists of up to 28 edge detectors
00054         (16 lines are connected to GPIO) for generating event/interrupt requests (each
00055         input line can be independently configured to select the type (interrupt or event)
00056         and the corresponding trigger event (rising or falling or both). Each line can
00057         also be masked independently.
00058
00059                      ##### How to use this driver #####
00060   ==============================================================================
00061   [..]
00062     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00063
00064     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00065         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00066         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00067              structure.
00068         (++) In case of Output or alternate function mode selection: the speed is
00069              configured through "Speed" member from GPIO_InitTypeDef structure.
00070         (++) In alternate mode is selection, the alternate function connected to the IO
00071              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00072         (++) Analog mode is required when a pin is to be used as ADC channel
00073              or DAC output.
00074         (++) In case of external interrupt/event selection the "Mode" member from
00075              GPIO_InitTypeDef structure select the type (interrupt or event) and
00076              the corresponding trigger event (rising or falling or both).
00077
00078     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00079         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00080         HAL_NVIC_EnableIRQ().
00081
00082     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00083
00084     (#) To set/reset the level of a pin configured in output mode use
00085         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00086
00087    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00088
00089     (#) During and just after reset, the alternate functions are not
00090         active and the GPIO pins are configured in input floating mode (except JTAG
00091         pins).
00092
00093     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00094         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00095         priority over the GPIO function.
00096
00097     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00098         general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
00099         The HSE has priority over the GPIO function.
00100
00101   @endverbatim
00102   ******************************************************************************
00103   */
00104
00105 /* Includes ------------------------------------------------------------------*/
00106 #include "stm32g0xx_hal.h"
00107
00108 /** @addtogroup STM32G0xx_HAL_Driver
00109   * @{
00110   */
00111
00112 /** @addtogroup GPIO
00113   * @{
00114   */
00115 /** MISRA C:2012 deviation rule has been granted for following rules:
00116   * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
00117   * range of the shift operator in following API :
00118   * HAL_GPIO_Init
00119   * HAL_GPIO_DeInit
00120   */
00121
00122 #ifdef HAL_GPIO_MODULE_ENABLED
00123
00124 /* Private typedef -----------------------------------------------------------*/
00125 /* Private defines ------------------------------------------------------------*/
00126 /** @addtogroup GPIO_Private_Constants
00127   * @{
00128   */
00129 #define GPIO_NUMBER           (16u)
00130 /**
00131   * @}
00132   */
00133
00134 /* Private macros ------------------------------------------------------------*/
00135 /* Private variables ---------------------------------------------------------*/
00136 /* Private function prototypes -----------------------------------------------*/
00137 /* Exported functions --------------------------------------------------------*/
00138
00139 /** @addtogroup GPIO_Exported_Functions
00140   * @{
00141   */
00142
00143 /** @addtogroup GPIO_Exported_Functions_Group1
00144  *  @brief    Initialization and Configuration functions
00145  *
00146 @verbatim
00147  ===============================================================================
00148               ##### Initialization and de-initialization functions #####
00149  ===============================================================================
00150
00151 @endverbatim
00152   * @{
00153   */
00154
00155 /**
00156   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00157   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
00158   * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
00159   *         the configuration information for the specified GPIO peripheral.
00160   * @retval None
00161   */
00162 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00163 {
00164   uint32_t position = 0x00u;
00165   uint32_t iocurrent;
00166   uint32_t temp;
00167
00168   /* Check the parameters */
00169   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00170   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00171   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00172
00173   /* Configure the port pins */
00174   while (((GPIO_Init->Pin) >> position) != 0x00u)
00175   {
00176     /* Get current io position */
00177     iocurrent = (GPIO_Init->Pin) & (1uL << position);
00178
00179     if (iocurrent != 0x00u)
00180     {
00181       /*--------------------- GPIO Mode Configuration ------------------------*/
00182       /* In case of Output or Alternate function mode selection */
00183       if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
00184       {
00185         /* Check the Speed parameter */
00186         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00187
00188         /* Configure the IO Speed */
00189         temp = GPIOx->OSPEEDR;
00190         temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
00191         temp |= (GPIO_Init->Speed << (position * 2u));
00192         GPIOx->OSPEEDR = temp;
00193
00194         /* Configure the IO Output Type */
00195         temp = GPIOx->OTYPER;
00196         temp &= ~(GPIO_OTYPER_OT0 << position) ;
00197         temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
00198         GPIOx->OTYPER = temp;
00199       }
00200
00201       if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
00202       {
00203         /* Check the Pull parameter */
00204         assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00205
00206         /* Activate the Pull-up or Pull down resistor for the current IO */
00207         temp = GPIOx->PUPDR;
00208         temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
00209         temp |= ((GPIO_Init->Pull) << (position * 2u));
00210         GPIOx->PUPDR = temp;
00211       }
00212
00213       /* In case of Alternate function mode selection */
00214       if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
00215       {
00216         /* Check the Alternate function parameters */
00217         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
00218         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00219
00220         /* Configure Alternate function mapped with the current IO */
00221         temp = GPIOx->AFR[position >> 3u];
00222         temp &= ~(0xFu << ((position & 0x07u) * 4u));
00223         temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
00224         GPIOx->AFR[position >> 3u] = temp;
00225       }
00226
00227       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00228       temp = GPIOx->MODER;
00229       temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
00230       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
00231       GPIOx->MODER = temp;
00232
00233       /*--------------------- EXTI Mode Configuration ------------------------*/
00234       /* Configure the External Interrupt or event for the current IO */
00235       if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
00236       {
00237         temp = EXTI->EXTICR[position >> 2u];
00238         temp &= ~(0x0FuL << (8u * (position & 0x03u)));
00239         temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
00240         EXTI->EXTICR[position >> 2u] = temp;
00241
00242         /* Clear Rising Falling edge configuration */
00243         temp = EXTI->RTSR1;
00244         temp &= ~(iocurrent);
00245         if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
00246         {
00247           temp |= iocurrent;
00248         }
00249         EXTI->RTSR1 = temp;
00250
00251         temp = EXTI->FTSR1;
00252         temp &= ~(iocurrent);
00253         if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
00254         {
00255           temp |= iocurrent;
00256         }
00257         EXTI->FTSR1 = temp;
00258
00259         /* Clear EXTI line configuration */
00260         temp = EXTI->EMR1;
00261         temp &= ~(iocurrent);
00262         if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
00263         {
00264           temp |= iocurrent;
00265         }
00266         EXTI->EMR1 = temp;
00267
00268         temp = EXTI->IMR1;
00269         temp &= ~(iocurrent);
00270         if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
00271         {
00272           temp |= iocurrent;
00273         }
00274         EXTI->IMR1 = temp;
00275       }
00276     }
00277
00278     position++;
00279   }
00280 }
00281
00282 /**
00283   * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
00284   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
00285   * @param  GPIO_Pin specifies the port bit to be written.
00286   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00287   * @retval None
00288   */
00289 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00290 {
00291   uint32_t position = 0x00u;
00292   uint32_t iocurrent;
00293   uint32_t tmp;
00294
00295   /* Check the parameters */
00296   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00297   assert_param(IS_GPIO_PIN(GPIO_Pin));
00298
00299   /* Configure the port pins */
00300   while ((GPIO_Pin >> position) != 0x00u)
00301   {
00302     /* Get current io position */
00303     iocurrent = (GPIO_Pin) & (1uL << position);
00304
00305     if (iocurrent != 0x00u)
00306     {
00307       /*------------------------- EXTI Mode Configuration --------------------*/
00308       /* Clear the External Interrupt or Event for the current IO */
00309
00310       tmp = EXTI->EXTICR[position >> 2u];
00311       tmp &= (0x0FuL << (8u * (position & 0x03u)));
00312       if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))))
00313       {
00314         /* Clear EXTI line configuration */
00315         EXTI->IMR1 &= ~(iocurrent);
00316         EXTI->EMR1 &= ~(iocurrent);
00317
00318         /* Clear Rising Falling edge configuration */
00319         EXTI->FTSR1 &= ~(iocurrent);
00320         EXTI->RTSR1 &= ~(iocurrent);
00321
00322         tmp = 0x0FuL << (8u * (position & 0x03u));
00323         EXTI->EXTICR[position >> 2u] &= ~tmp;
00324       }
00325
00326       /*------------------------- GPIO Mode Configuration --------------------*/
00327       /* Configure IO in Analog Mode */
00328       GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
00329
00330       /* Configure the default Alternate Function in current IO */
00331       GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
00332
00333       /* Configure the default value for IO Speed */
00334       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
00335
00336       /* Configure the default value IO Output Type */
00337       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
00338
00339       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00340       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
00341     }
00342
00343     position++;
00344   }
00345 }
00346
00347 /**
00348   * @}
00349   */
00350
00351 /** @addtogroup GPIO_Exported_Functions_Group2
00352  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
00353  *
00354 @verbatim
00355  ===============================================================================
00356                        ##### IO operation functions #####
00357  ===============================================================================
00358
00359 @endverbatim
00360   * @{
00361   */
00362
00363 /**
00364   * @brief  Read the specified input port pin.
00365   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
00366   * @param  GPIO_Pin specifies the port bit to read.
00367   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00368   * @retval The input port pin value.
00369   */
00370 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00371 {
00372   GPIO_PinState bitstatus;
00373
00374   /* Check the parameters */
00375   assert_param(IS_GPIO_PIN(GPIO_Pin));
00376
00377   if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
00378   {
00379     bitstatus = GPIO_PIN_SET;
00380   }
00381   else
00382   {
00383     bitstatus = GPIO_PIN_RESET;
00384   }
00385   return bitstatus;
00386 }
00387
00388 /**
00389   * @brief  Set or clear the selected data port bit.
00390   *
00391   * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
00392   *         accesses. In this way, there is no risk of an IRQ occurring between
00393   *         the read and the modify access.
00394   *
00395   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
00396   * @param  GPIO_Pin specifies the port bit to be written.
00397   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00398   * @param  PinState specifies the value to be written to the selected bit.
00399   *         This parameter can be one of the GPIO_PinState enum values:
00400   *            @arg GPIO_PIN_RESET: to clear the port pin
00401   *            @arg GPIO_PIN_SET: to set the port pin
00402   * @retval None
00403   */
00404 void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00405 {
00406   /* Check the parameters */
00407   assert_param(IS_GPIO_PIN(GPIO_Pin));
00408   assert_param(IS_GPIO_PIN_ACTION(PinState));
00409
00410   if (PinState != GPIO_PIN_RESET)
00411   {
00412     GPIOx->BSRR = (uint32_t)GPIO_Pin;
00413   }
00414   else
00415   {
00416     GPIOx->BRR = (uint32_t)GPIO_Pin;
00417   }
00418 }
00419
00420 /**
00421   * @brief  Toggle the specified GPIO pin.
00422   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
00423   * @param  GPIO_Pin specifies the pin to be toggled.
00424   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00425   * @retval None
00426   */
00427 void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00428 {
00429   uint32_t odr;
00430
00431   /* Check the parameters */
00432   assert_param(IS_GPIO_PIN(GPIO_Pin));
00433
00434   /* get current Output Data Register value */
00435   odr = GPIOx->ODR;
00436
00437   /* Set selected pins that were at low level, and reset ones that were high */
00438   GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
00439 }
00440
00441 /**
00442 * @brief  Lock GPIO Pins configuration registers.
00443   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00444   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00445   * @note   The configuration of the locked GPIO pins can no longer be modified
00446   *         until the next reset.
00447   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
00448   * @param  GPIO_Pin specifies the port bits to be locked.
00449   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00450   * @retval None
00451   */
00452 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
00453 {
00454   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00455
00456   /* Check the parameters */
00457   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00458   assert_param(IS_GPIO_PIN(GPIO_Pin));
00459
00460   /* Apply lock key write sequence */
00461   tmp |= GPIO_Pin;
00462   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00463   GPIOx->LCKR = tmp;
00464   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00465   GPIOx->LCKR = GPIO_Pin;
00466   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00467   GPIOx->LCKR = tmp;
00468   /* Read LCKK register. This read is mandatory to complete key lock sequence */
00469   tmp = GPIOx->LCKR;
00470
00471   /* read again in order to confirm lock is active */
00472   if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
00473   {
00474     return HAL_OK;
00475   }
00476   else
00477   {
00478     return HAL_ERROR;
00479   }
00480 }
00481
00482 /**
00483   * @brief  Handle EXTI interrupt request.
00484   * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
00485   * @retval None
00486   */
00487 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00488 {
00489   /* EXTI line interrupt detected */
00490   if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u)
00491   {
00492     __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
00493     HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
00494   }
00495
00496   if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u)
00497   {
00498     __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
00499     HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
00500   }
00501 }
00502
00503 /**
00504   * @brief  EXTI line detection callback.
00505   * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
00506   * @retval None
00507   */
00508 __weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
00509 {
00510   /* Prevent unused argument(s) compilation warning */
00511   UNUSED(GPIO_Pin);
00512
00513   /* NOTE: This function should not be modified, when the callback is needed,
00514            the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
00515    */
00516 }
00517
00518 /**
00519   * @brief  EXTI line detection callback.
00520   * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
00521   * @retval None
00522   */
00523 __weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
00524 {
00525   /* Prevent unused argument(s) compilation warning */
00526   UNUSED(GPIO_Pin);
00527
00528   /* NOTE: This function should not be modified, when the callback is needed,
00529            the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
00530    */
00531 }
00532
00533 /**
00534   * @}
00535   */
00536
00537
00538 /**
00539   * @}
00540   */
00541
00542 #endif /* HAL_GPIO_MODULE_ENABLED */
00543 /**
00544   * @}
00545   */
00546
00547 /**
00548   * @}
00549   */
00550
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_gpio.h Source File

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stm32g0xx_hal_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_GPIO_H
00021 #define STM32G0xx_HAL_GPIO_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup GPIO GPIO
00035   * @brief GPIO HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00042   * @{
00043   */
00044 /**
00045   * @brief   GPIO Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
00050                            This parameter can be any value of @ref GPIO_pins */
00051
00052   uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
00053                            This parameter can be a value of @ref GPIO_mode */
00054
00055   uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00056                            This parameter can be a value of @ref GPIO_pull */
00057
00058   uint32_t Speed;      /*!< Specifies the speed for the selected pins.
00059                            This parameter can be a value of @ref GPIO_speed */
00060
00061   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
00062                             This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
00063 } GPIO_InitTypeDef;
00064
00065 /**
00066   * @brief  GPIO Bit SET and Bit RESET enumeration
00067   */
00068 typedef enum
00069 {
00070   GPIO_PIN_RESET = 0U,
00071   GPIO_PIN_SET
00072 } GPIO_PinState;
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported constants --------------------------------------------------------*/
00078 /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
00079   * @{
00080   */
00081 /** @defgroup GPIO_pins GPIO pins
00082   * @{
00083   */
00084 #define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
00085 #define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
00086 #define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
00087 #define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
00088 #define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
00089 #define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
00090 #define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
00091 #define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
00092 #define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
00093 #define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
00094 #define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
00095 #define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
00096 #define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
00097 #define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
00098 #define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
00099 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
00100 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
00101
00102 #define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup GPIO_mode GPIO mode
00108   * @brief GPIO Configuration Mode
00109   *        Elements values convention: 0x00WX00YZ
00110   *           - W  : EXTI trigger detection on 3 bits
00111   *           - X  : EXTI mode (IT or Event) on 2 bits
00112   *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
00113   *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
00114   * @{
00115   */
00116 #define GPIO_MODE_INPUT                 MODE_INPUT                                                  /*!< Input Floating Mode                                                */
00117 #define GPIO_MODE_OUTPUT_PP             (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                                              */
00118 #define GPIO_MODE_OUTPUT_OD             (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                                             */
00119 #define GPIO_MODE_AF_PP                 (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode                                  */
00120 #define GPIO_MODE_AF_OD                 (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode                                 */
00121 #define GPIO_MODE_ANALOG                MODE_ANALOG                                                 /*!< Analog Mode                                                        */
00122 #define GPIO_MODE_IT_RISING             (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection         */
00123 #define GPIO_MODE_IT_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection        */
00124 #define GPIO_MODE_IT_RISING_FALLING     (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00125 #define GPIO_MODE_EVT_RISING            (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                    /*!< External Event Mode with Rising edge trigger detection             */
00126 #define GPIO_MODE_EVT_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                   /*!< External Event Mode with Falling edge trigger detection            */
00127 #define GPIO_MODE_EVT_RISING_FALLING    (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)  /*!< External Event Mode with Rising/Falling edge trigger detection     */
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup GPIO_speed GPIO speed
00133   * @brief GPIO Output Maximum frequency
00134   * @{
00135   */
00136 #define GPIO_SPEED_FREQ_LOW             0x00000000u  /*!< Low speed       */
00137 #define GPIO_SPEED_FREQ_MEDIUM          0x00000001u  /*!< Medium speed    */
00138 #define GPIO_SPEED_FREQ_HIGH            0x00000002u  /*!< High speed      */
00139 #define GPIO_SPEED_FREQ_VERY_HIGH       0x00000003u  /*!< Very high speed */
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup GPIO_pull GPIO pull
00145   * @brief GPIO Pull-Up or Pull-Down Activation
00146   * @{
00147   */
00148 #define GPIO_NOPULL                     0x00000000u   /*!< No Pull-up or Pull-down activation  */
00149 #define GPIO_PULLUP                     0x00000001u   /*!< Pull-up activation                  */
00150 #define GPIO_PULLDOWN                   0x00000002u   /*!< Pull-down activation                */
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /* Exported macro ------------------------------------------------------------*/
00160 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00161   * @{
00162   */
00163
00164 /**
00165   * @brief  Check whether the specified EXTI line is rising edge asserted or not.
00166   * @param  __EXTI_LINE__ specifies the EXTI line to check.
00167   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00168   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00169   */
00170 #define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__)         (EXTI->RPR1 & (__EXTI_LINE__))
00171
00172 /**
00173   * @brief  Clear the EXTI line rising pending bits.
00174   * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
00175   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00176   * @retval None
00177   */
00178 #define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__)       (EXTI->RPR1 = (__EXTI_LINE__))
00179
00180 /**
00181   * @brief  Check whether the specified EXTI line is falling edge asserted or not.
00182   * @param  __EXTI_LINE__ specifies the EXTI line to check.
00183   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00184   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00185   */
00186 #define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)        (EXTI->FPR1 & (__EXTI_LINE__))
00187
00188 /**
00189   * @brief  Clear the EXTI line falling pending bits.
00190   * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
00191   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00192   * @retval None
00193   */
00194 #define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__)      (EXTI->FPR1 = (__EXTI_LINE__))
00195
00196 /**
00197   * @brief  Check whether the specified EXTI line is asserted or not.
00198   * @param __EXTI_LINE__ specifies the EXTI line to check.
00199   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00200   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00201   */
00202 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \
00203                                                        __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__))
00204
00205 /**
00206   * @brief  Clear the EXTI's line pending bits.
00207   * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
00208   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00209   * @retval None
00210   */
00211 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)         \
00212   do {                                                  \
00213     __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__);     \
00214     __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__);    \
00215   } while(0)
00216
00217
00218 /**
00219   * @brief  Generate a Software interrupt on selected EXTI line.
00220   * @param __EXTI_LINE__ specifies the EXTI line to check.
00221   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00222   * @retval None
00223   */
00224 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
00225
00226 /**
00227   * @brief  Check whether the specified EXTI line flag is set or not.
00228   * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
00229   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00230   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00231   */
00232 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
00233
00234 /**
00235   * @brief  Clear the EXTI line pending flags.
00236   * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
00237   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00238   * @retval None
00239   */
00240 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
00241
00242 /**
00243   * @}
00244   */
00245
00246 /* Private macros ------------------------------------------------------------*/
00247 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00248   * @{
00249   */
00250 #define GPIO_MODE_Pos                           0u
00251 #define GPIO_MODE                               (0x3uL << GPIO_MODE_Pos)
00252 #define MODE_INPUT                              (0x0uL << GPIO_MODE_Pos)
00253 #define MODE_OUTPUT                             (0x1uL << GPIO_MODE_Pos)
00254 #define MODE_AF                                 (0x2uL << GPIO_MODE_Pos)
00255 #define MODE_ANALOG                             (0x3uL << GPIO_MODE_Pos)
00256 #define OUTPUT_TYPE_Pos                         4u
00257 #define OUTPUT_TYPE                             (0x1uL << OUTPUT_TYPE_Pos)
00258 #define OUTPUT_PP                               (0x0uL << OUTPUT_TYPE_Pos)
00259 #define OUTPUT_OD                               (0x1uL << OUTPUT_TYPE_Pos)
00260 #define EXTI_MODE_Pos                           16u
00261 #define EXTI_MODE                               (0x3uL << EXTI_MODE_Pos)
00262 #define EXTI_IT                                 (0x1uL << EXTI_MODE_Pos)
00263 #define EXTI_EVT                                (0x2uL << EXTI_MODE_Pos)
00264 #define TRIGGER_MODE_Pos                         20u
00265 #define TRIGGER_MODE                            (0x7uL << TRIGGER_MODE_Pos)
00266 #define TRIGGER_RISING                          (0x1uL << TRIGGER_MODE_Pos)
00267 #define TRIGGER_FALLING                         (0x2uL << TRIGGER_MODE_Pos)
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00273   * @{
00274   */
00275 #define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00276
00277 #define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
00278                                      (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
00279
00280 #define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
00281                                      ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
00282                                      ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
00283                                      ((__MODE__) == GPIO_MODE_AF_PP)              ||\
00284                                      ((__MODE__) == GPIO_MODE_AF_OD)              ||\
00285                                      ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
00286                                      ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
00287                                      ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
00288                                      ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
00289                                      ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
00290                                      ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
00291                                      ((__MODE__) == GPIO_MODE_ANALOG))
00292
00293 #define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)    ||\
00294                                      ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
00295                                      ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)   ||\
00296                                      ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
00297
00298 #define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
00299                                      ((__PULL__) == GPIO_PULLUP)   || \
00300                                      ((__PULL__) == GPIO_PULLDOWN))
00301 /**
00302   * @}
00303   */
00304
00305 /* Include GPIO HAL Extended module */
00306 #include "stm32g0xx_hal_gpio_ex.h"
00307
00308 /* Exported functions --------------------------------------------------------*/
00309 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00310  *  @brief    GPIO Exported Functions
00311   * @{
00312   */
00313
00314 /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
00315  *  @brief    Initialization and Configuration functions
00316  * @{
00317  */
00318
00319 /* Initialization and de-initialization functions *****************************/
00320 void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00321 void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00322
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00328  *  @brief    IO operation functions
00329  * @{
00330  */
00331
00332 /* IO operation functions *****************************************************/
00333 GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00334 void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00335 void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00336 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
00337 void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00338 void              HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin);
00339 void              HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
00340
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 /**
00350   * @}
00351   */
00352
00353 /**
00354   * @}
00355   */
00356
00357 #ifdef __cplusplus
00358 }
00359 #endif
00360
00361 #endif /* STM32G0xx_HAL_GPIO_H */
00362
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_gpio_ex.h Source File

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stm32g0xx_hal_gpio_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_GPIO_EX_H
00021 #define STM32G0xx_HAL_GPIO_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup GPIOEx GPIOEx
00035   * @brief GPIO Extended HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
00046   * @{
00047   */
00048 #if defined (STM32G0C1xx) || defined (STM32G0B1xx)
00049 /*------------------------- STM32G0C1xx / STM32G0B1xx ------------------------*/
00050 /**
00051   * @brief   AF 0 selection
00052   */
00053 #define GPIO_AF0_CEC           ((uint8_t)0x00)  /*!< CEC Alternate Function mapping */
00054 #define GPIO_AF0_CRS           ((uint8_t)0x00)  /*!< CRS Alternate Function mapping */
00055 #define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
00056 #define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
00057 #define GPIO_AF0_LPTIM1        ((uint8_t)0x00)  /*!< LPTIM1 Alternate Function mapping */
00058 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
00059 #define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00060 #define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
00061 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
00062 #define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
00063 #define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
00064 #define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
00065 #define GPIO_AF0_TIM15         ((uint8_t)0x00)  /*!< TIM15 Alternate Function mapping */
00066 #define GPIO_AF0_TIM16         ((uint8_t)0x00)  /*!< TIM16 Alternate Function mapping */
00067 #define GPIO_AF0_TIM17         ((uint8_t)0x00)  /*!< TIM17 Alternate Function mapping */
00068 #define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
00069 #define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
00070 #define GPIO_AF0_USART3        ((uint8_t)0x00)  /*!< USART3 Alternate Function mapping */
00071 #define GPIO_AF0_USART4        ((uint8_t)0x00)  /*!< USART4 Alternate Function mapping */
00072 #define GPIO_AF0_UCPD1         ((uint8_t)0x00)  /*!< UCPD1 Alternate Function mapping */
00073 #define GPIO_AF0_UCPD2         ((uint8_t)0x00)  /*!< UCPD2 Alternate Function mapping */
00074
00075 /**
00076   * @brief   AF 1 selection
00077   */
00078 #define GPIO_AF1_CEC           ((uint8_t)0x01)  /*!< CEC Alternate Function mapping */
00079 #define GPIO_AF1_EVENTOUT      ((uint8_t)0x01)  /*!< EVENTOUT Alternate Function mapping */
00080 #define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
00081 #define GPIO_AF1_LPTIM2        ((uint8_t)0x01)  /*!< LPTIM2 Alternate Function mapping */
00082 #define GPIO_AF1_LPUART1       ((uint8_t)0x01)  /*!< LPUART1 Alternate Function mapping */
00083 #define GPIO_AF1_LPUART2       ((uint8_t)0x01)  /*!< LPUART2 Alternate Function mapping */
00084 #define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00085 #define GPIO_AF1_SPI1          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00086 #define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00087 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
00088 #define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
00089 #define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
00090 #define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
00091 #define GPIO_AF1_USART4        ((uint8_t)0x01)  /*!< USART4 Alternate Function mapping */
00092 #define GPIO_AF1_UCPD1         ((uint8_t)0x01)  /*!< UCPD1 Alternate Function mapping */
00093 #define GPIO_AF1_UCPD2         ((uint8_t)0x01)  /*!< UCPD2 Alternate Function mapping */
00094
00095 /**
00096   * @brief   AF 2 selection
00097   */
00098 #define GPIO_AF2_LPTIM1        ((uint8_t)0x02)  /*!< LPTIM1 Alternate Function mapping */
00099 #define GPIO_AF2_LPTIM2        ((uint8_t)0x02)  /*!< LPTIM2 Alternate Function mapping */
00100 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
00101 #define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
00102 #define GPIO_AF2_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */
00103 #define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
00104 #define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
00105 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
00106 #define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
00107 #define GPIO_AF2_USB           ((uint8_t)0x02)  /*!< USB Alternate Function mapping */
00108
00109
00110 /**
00111   * @brief   AF 3 selection
00112   */
00113 #define GPIO_AF3_FDCAN1        ((uint8_t)0x03)  /*!< FDCAN1 Alternate Function mapping */
00114 #define GPIO_AF3_FDCAN2        ((uint8_t)0x03)  /*!< FDCAN2 Alternate Function mapping */
00115 #define GPIO_AF3_LPUART2       ((uint8_t)0x03)  /*!< LPUART2 Alternate Function mapping */
00116 #define GPIO_AF3_USART5        ((uint8_t)0x03)  /*!< USART5 Alternate Function mapping */
00117 #define GPIO_AF3_USART6        ((uint8_t)0x03)  /*!< USART6 Alternate Function mapping */
00118 #define GPIO_AF3_MCO2          ((uint8_t)0x03)  /*!< MCO2 Alternate Function mapping */
00119
00120 /**
00121   * @brief   AF 4 selection
00122   */
00123 #define GPIO_AF4_CRS           ((uint8_t)0x04)  /*!< CRS Alternate Function mapping */
00124 #define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
00125 #define GPIO_AF4_SPI3          ((uint8_t)0x04)  /*!< SPI3 Alternate Function mapping */
00126 #define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
00127 #define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
00128 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
00129 #define GPIO_AF4_USART3        ((uint8_t)0x04)  /*!< USART3 Alternate Function mapping */
00130 #define GPIO_AF4_USART4        ((uint8_t)0x04)  /*!< USART4 Alternate Function mapping */
00131 #define GPIO_AF4_USART6        ((uint8_t)0x04)  /*!< USART6 Alternate Function mapping */
00132 #define GPIO_AF4_UCPD1         ((uint8_t)0x04)  /*!< UCPD1 Alternate Function mapping */
00133 #define GPIO_AF4_UCPD2         ((uint8_t)0x04)  /*!< UCPD2 Alternate Function mapping */
00134
00135 /**
00136   * @brief   AF 5 selection
00137   */
00138 #define GPIO_AF5_LPTIM1        ((uint8_t)0x05)  /*!< LPTIM1 Alternate Function mapping */
00139 #define GPIO_AF5_LPTIM2        ((uint8_t)0x05)  /*!< LPTIM2 Alternate Function mapping */
00140 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00141 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00142 #define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
00143 #define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
00144 #define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
00145 #define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
00146 #define GPIO_AF5_USART3        ((uint8_t)0x05)  /*!< USART3 Alternate Function mapping */
00147
00148 /**
00149   * @brief   AF 6 selection
00150   */
00151 #define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
00152 #define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
00153 #define GPIO_AF6_I2C3          ((uint8_t)0x06)  /*!< I2C3 Alternate Function mapping */
00154 #define GPIO_AF6_LPUART1       ((uint8_t)0x06)  /*!< LPUART1 Alternate Function mapping */
00155 #define GPIO_AF6_UCPD1         ((uint8_t)0x06)  /*!< UCPD1 Alternate Function mapping */
00156 #define GPIO_AF6_UCPD2         ((uint8_t)0x06)  /*!< UCPD2 Alternate Function mapping */
00157 #define GPIO_AF6_USB           ((uint8_t)0x06)  /*!< USB Alternate Function mapping */
00158
00159 /**
00160   * @brief   AF 7 selection
00161   */
00162 #define GPIO_AF7_COMP1         ((uint8_t)0x07)  /*!< COMP1 Alternate Function mapping */
00163 #define GPIO_AF7_COMP2         ((uint8_t)0x07)  /*!< COMP2 Alternate Function mapping */
00164 #define GPIO_AF7_COMP3         ((uint8_t)0x07)  /*!< COMP3 Alternate Function mapping */
00165 #define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
00166
00167 /**
00168   * @brief   AF 8 selection
00169   */
00170 #define GPIO_AF8_I2C2          ((uint8_t)0x08)  /*!< I2C2 Alternate Function mapping */
00171 #define GPIO_AF8_USART5        ((uint8_t)0x08)  /*!< USART5 Alternate Function mapping */
00172 #define GPIO_AF8_USART6        ((uint8_t)0x08)  /*!< USART5 Alternate Function mapping */
00173
00174 /**
00175   * @brief   AF 9 selection
00176   */
00177 #define GPIO_AF9_I2C3          ((uint8_t)0x09)  /*!< I2C3 Alternate Function mapping */
00178 #define GPIO_AF9_SPI3          ((uint8_t)0x09)  /*!< SPI3 Alternate Function mapping */
00179 #define GPIO_AF9_TIM4          ((uint8_t)0x09)  /*!< TIM4 Alternate Function mapping */
00180
00181 /**
00182   * @brief   AF 10 selection
00183   */
00184 #define GPIO_AF10_LPUART2      ((uint8_t)0x0A)  /*!< LPUART2 Alternate Function mapping */
00185
00186 #define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x0A)
00187
00188 #endif /* STM32G0C1xx || STM32G0B1xx */
00189
00190 #if defined (STM32G0B0xx)
00191 /*------------------------- STM32G0B0xx ------------------------*/
00192 /**
00193   * @brief   AF 0 selection
00194   */
00195 #define GPIO_AF0_CRS           ((uint8_t)0x00)  /*!< CRS Alternate Function mapping */
00196 #define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
00197 #define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
00198 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
00199 #define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00200 #define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
00201 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
00202 #define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
00203 #define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
00204 #define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
00205 #define GPIO_AF0_TIM15         ((uint8_t)0x00)  /*!< TIM15 Alternate Function mapping */
00206 #define GPIO_AF0_TIM16         ((uint8_t)0x00)  /*!< TIM16 Alternate Function mapping */
00207 #define GPIO_AF0_TIM17         ((uint8_t)0x00)  /*!< TIM17 Alternate Function mapping */
00208 #define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
00209 #define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
00210 #define GPIO_AF0_USART3        ((uint8_t)0x00)  /*!< USART3 Alternate Function mapping */
00211 #define GPIO_AF0_USART4        ((uint8_t)0x00)  /*!< USART4 Alternate Function mapping */
00212
00213 /**
00214   * @brief   AF 1 selection
00215   */
00216 #define GPIO_AF1_EVENTOUT      ((uint8_t)0x01)  /*!< EVENTOUT Alternate Function mapping */
00217 #define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
00218 #define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00219 #define GPIO_AF1_SPI1          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00220 #define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00221 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
00222 #define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
00223 #define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
00224 #define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
00225 #define GPIO_AF1_USART4        ((uint8_t)0x01)  /*!< USART4 Alternate Function mapping */
00226
00227 /**
00228   * @brief   AF 2 selection
00229   */
00230 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
00231 #define GPIO_AF2_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */
00232 #define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
00233 #define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
00234 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
00235 #define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
00236 #define GPIO_AF2_USB           ((uint8_t)0x02)  /*!< USB Alternate Function mapping */
00237
00238
00239 /**
00240   * @brief   AF 3 selection
00241   */
00242 #define GPIO_AF3_USART5        ((uint8_t)0x03)  /*!< USART5 Alternate Function mapping */
00243 #define GPIO_AF3_USART6        ((uint8_t)0x03)  /*!< USART6 Alternate Function mapping */
00244 #define GPIO_AF3_MCO2          ((uint8_t)0x03)  /*!< MCO2 Alternate Function mapping */
00245
00246 /**
00247   * @brief   AF 4 selection
00248   */
00249 #define GPIO_AF4_CRS           ((uint8_t)0x04)  /*!< CRS Alternate Function mapping */
00250 #define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
00251 #define GPIO_AF4_SPI3          ((uint8_t)0x04)  /*!< SPI3 Alternate Function mapping */
00252 #define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
00253 #define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
00254 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
00255 #define GPIO_AF4_USART3        ((uint8_t)0x04)  /*!< USART3 Alternate Function mapping */
00256 #define GPIO_AF4_USART4        ((uint8_t)0x04)  /*!< USART4 Alternate Function mapping */
00257 #define GPIO_AF4_USART6        ((uint8_t)0x04)  /*!< USART6 Alternate Function mapping */
00258
00259 /**
00260   * @brief   AF 5 selection
00261   */
00262 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00263 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00264 #define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
00265 #define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
00266 #define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
00267 #define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
00268 #define GPIO_AF5_USART3        ((uint8_t)0x05)  /*!< USART3 Alternate Function mapping */
00269
00270 /**
00271   * @brief   AF 6 selection
00272   */
00273 #define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
00274 #define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
00275 #define GPIO_AF6_I2C3          ((uint8_t)0x06)  /*!< I2C3 Alternate Function mapping */
00276 #define GPIO_AF6_USB           ((uint8_t)0x06)  /*!< USB Alternate Function mapping */
00277
00278 /**
00279   * @brief   AF 7 selection
00280   */
00281 #define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
00282
00283 /**
00284   * @brief   AF 8 selection
00285   */
00286 #define GPIO_AF8_I2C2          ((uint8_t)0x08)  /*!< I2C2 Alternate Function mapping */
00287 #define GPIO_AF8_USART5        ((uint8_t)0x08)  /*!< USART5 Alternate Function mapping */
00288 #define GPIO_AF8_USART6        ((uint8_t)0x08)  /*!< USART5 Alternate Function mapping */
00289
00290 /**
00291   * @brief   AF 9 selection
00292   */
00293 #define GPIO_AF9_I2C3          ((uint8_t)0x09)  /*!< I2C3 Alternate Function mapping */
00294 #define GPIO_AF9_SPI3          ((uint8_t)0x09)  /*!< SPI3 Alternate Function mapping */
00295 #define GPIO_AF9_TIM4          ((uint8_t)0x09)  /*!< TIM4 Alternate Function mapping */
00296
00297 #define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x09)
00298
00299 #endif /* STM32G0B0xx */
00300
00301
00302 #if defined (STM32G081xx) || defined (STM32G071xx)
00303 /*------------------------- STM32G081xx / STM32G071xx ------------------------*/
00304 /**
00305   * @brief   AF 0 selection
00306   */
00307 #define GPIO_AF0_CEC           ((uint8_t)0x00)  /*!< CEC Alternate Function mapping */
00308 #define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
00309 #define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
00310 #define GPIO_AF0_LPTIM1        ((uint8_t)0x00)  /*!< LPTIM1 Alternate Function mapping */
00311 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
00312 #define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00313 #define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
00314 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
00315 #define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
00316 #define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
00317 #define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
00318 #define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
00319 #define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
00320 #define GPIO_AF0_USART3        ((uint8_t)0x00)  /*!< USART3 Alternate Function mapping */
00321 #define GPIO_AF0_UCPD1         ((uint8_t)0x00)  /*!< UCPD1 Alternate Function mapping */
00322 #define GPIO_AF0_UCPD2         ((uint8_t)0x00)  /*!< UCPD2 Alternate Function mapping */
00323
00324 /**
00325   * @brief   AF 1 selection
00326   */
00327 #define GPIO_AF1_CEC           ((uint8_t)0x01)  /*!< CEC Alternate Function mapping */
00328 #define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
00329 #define GPIO_AF1_LPUART1       ((uint8_t)0x01)  /*!< LPUART1 Alternate Function mapping */
00330 #define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00331 #define GPIO_AF1_SPI1          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00332 #define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00333 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
00334 #define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
00335 #define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
00336 #define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
00337 #define GPIO_AF1_USART4        ((uint8_t)0x01)  /*!< USART4 Alternate Function mapping */
00338 #define GPIO_AF1_UCPD1         ((uint8_t)0x01)  /*!< UCPD1 Alternate Function mapping */
00339 #define GPIO_AF1_UCPD2         ((uint8_t)0x01)  /*!< UCPD2 Alternate Function mapping */
00340
00341 /**
00342   * @brief   AF 2 selection
00343   */
00344 #define GPIO_AF2_LPTIM1        ((uint8_t)0x02)  /*!< LPTIM1 Alternate Function mapping */
00345 #define GPIO_AF2_LPTIM2        ((uint8_t)0x02)  /*!< LPTIM2 Alternate Function mapping */
00346 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
00347 #define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
00348 #define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
00349 #define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
00350 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
00351 #define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
00352
00353 /**
00354   * @brief   AF 3 selection
00355   */
00356 #define GPIO_AF3_UCPD1         ((uint8_t)0x03)  /*!< UCPD1 Alternate Function mapping */
00357 #define GPIO_AF3_UCPD2         ((uint8_t)0x03)  /*!< UCPD2 Alternate Function mapping */
00358
00359 /**
00360   * @brief   AF 4 selection
00361   */
00362 #define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
00363 #define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
00364 #define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
00365 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
00366 #define GPIO_AF4_USART3        ((uint8_t)0x04)  /*!< USART3 Alternate Function mapping */
00367 #define GPIO_AF4_USART4        ((uint8_t)0x04)  /*!< USART4 Alternate Function mapping */
00368 #define GPIO_AF4_UCPD1         ((uint8_t)0x04)  /*!< UCPD1 Alternate Function mapping */
00369 #define GPIO_AF4_UCPD2         ((uint8_t)0x04)  /*!< UCPD2 Alternate Function mapping */
00370
00371 /**
00372   * @brief   AF 5 selection
00373   */
00374 #define GPIO_AF5_LPTIM1        ((uint8_t)0x05)  /*!< LPTIM1 Alternate Function mapping */
00375 #define GPIO_AF5_LPTIM2        ((uint8_t)0x05)  /*!< LPTIM2 Alternate Function mapping */
00376 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00377 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00378 #define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
00379 #define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
00380 #define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
00381 #define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
00382 #define GPIO_AF5_USART3        ((uint8_t)0x05)  /*!< USART3 Alternate Function mapping */
00383
00384 /**
00385   * @brief   AF 6 selection
00386   */
00387 #define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
00388 #define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
00389 #define GPIO_AF6_LPUART1       ((uint8_t)0x06)  /*!< LPUART1 Alternate Function mapping */
00390 #define GPIO_AF6_UCPD1         ((uint8_t)0x06)  /*!< UCPD1 Alternate Function mapping */
00391 #define GPIO_AF6_UCPD2         ((uint8_t)0x06)  /*!< UCPD2 Alternate Function mapping */
00392
00393 /**
00394   * @brief   AF 7 selection
00395   */
00396 #define GPIO_AF7_COMP1         ((uint8_t)0x07)  /*!< COMP1 Alternate Function mapping */
00397 #define GPIO_AF7_COMP2         ((uint8_t)0x07)  /*!< COMP2 Alternate Function mapping */
00398 #define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
00399
00400 #define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
00401
00402 #endif /* STM32G081xx || STM32G071xx */
00403
00404 #if defined (STM32G070xx)
00405 /**
00406   * @brief   AF 0 selection
00407   */
00408 #define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
00409 #define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
00410 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
00411 #define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00412 #define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
00413 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
00414 #define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
00415 #define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
00416 #define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
00417 #define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
00418 #define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
00419 #define GPIO_AF0_USART3        ((uint8_t)0x00)  /*!< USART3 Alternate Function mapping */
00420
00421 /**
00422   * @brief   AF 1 selection
00423   */
00424 #define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
00425 #define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00426 #define GPIO_AF1_SPI1          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00427 #define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00428 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
00429 #define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
00430 #define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
00431 #define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
00432 #define GPIO_AF1_USART4        ((uint8_t)0x01)  /*!< USART4 Alternate Function mapping */
00433
00434 /**
00435   * @brief   AF 2 selection
00436   */
00437 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
00438 #define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
00439 #define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
00440 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
00441 #define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
00442
00443 /**
00444   * @brief   AF 3 selection
00445   */
00446
00447 /**
00448   * @brief   AF 4 selection
00449   */
00450 #define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
00451 #define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
00452 #define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
00453 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
00454 #define GPIO_AF4_USART3        ((uint8_t)0x04)  /*!< USART3 Alternate Function mapping */
00455 #define GPIO_AF4_USART4        ((uint8_t)0x04)  /*!< USART4 Alternate Function mapping */
00456
00457 /**
00458   * @brief   AF 5 selection
00459   */
00460 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00461 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00462 #define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
00463 #define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
00464 #define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
00465 #define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
00466 #define GPIO_AF5_USART3        ((uint8_t)0x05)  /*!< USART3 Alternate Function mapping */
00467
00468 /**
00469   * @brief   AF 6 selection
00470   */
00471 #define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
00472 #define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
00473
00474 /**
00475   * @brief   AF 7 selection
00476   */
00477 #define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
00478
00479 #define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
00480
00481 #endif /* STM32G070xx */
00482
00483 #if defined (STM32G051xx) || defined (STM32G061xx)
00484 /*------------------------- STM32G061xx / STM32G051xx ------------------------*/
00485 /**
00486   * @brief   AF 0 selection
00487   */
00488 #define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
00489 #define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
00490 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
00491 #define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00492 #define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
00493 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
00494 #define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
00495 #define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
00496 #define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
00497 #define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
00498 #define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
00499
00500 /**
00501   * @brief   AF 1 selection
00502   */
00503 #define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
00504 #define GPIO_AF1_LPUART1       ((uint8_t)0x01)  /*!< LPUART1 Alternate Function mapping */
00505 #define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00506 #define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00507 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
00508 #define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
00509 #define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
00510 #define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
00511
00512 /**
00513   * @brief   AF 2 selection
00514   */
00515 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
00516 #define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
00517 #define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
00518 #define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
00519 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
00520 #define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
00521
00522 /**
00523   * @brief   AF 3 selection
00524   */
00525
00526 /**
00527   * @brief   AF 4 selection
00528   */
00529 #define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
00530 #define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
00531 #define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
00532 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
00533
00534 /**
00535   * @brief   AF 5 selection
00536   */
00537 #define GPIO_AF5_LPTIM1        ((uint8_t)0x05)  /*!< LPTIM1 Alternate Function mapping */
00538 #define GPIO_AF5_LPTIM2        ((uint8_t)0x05)  /*!< LPTIM2 Alternate Function mapping */
00539 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00540 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00541 #define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
00542 #define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
00543 #define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
00544 #define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
00545
00546 /**
00547   * @brief   AF 6 selection
00548   */
00549 #define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
00550 #define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
00551 #define GPIO_AF6_LPUART1       ((uint8_t)0x06)  /*!< LPUART1 Alternate Function mapping */
00552
00553 /**
00554   * @brief   AF 7 selection
00555   */
00556 #define GPIO_AF7_COMP1         ((uint8_t)0x07)  /*!< COMP1 Alternate Function mapping */
00557 #define GPIO_AF7_COMP2         ((uint8_t)0x07)  /*!< COMP2 Alternate Function mapping */
00558 #define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
00559
00560 #define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
00561
00562 #endif /* STM32G051xx || STM32G061xx */
00563
00564 #if defined (STM32G050xx)
00565 /*------------------------- STM32G050xx --------------------------------------*/
00566 /**
00567   * @brief   AF 0 selection
00568   */
00569 #define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
00570 #define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
00571 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
00572 #define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00573 #define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
00574 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
00575 #define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
00576 #define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
00577 #define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
00578 #define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
00579 #define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
00580
00581 /**
00582   * @brief   AF 1 selection
00583   */
00584 #define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
00585 #define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00586 #define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00587 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
00588 #define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
00589 #define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
00590 #define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
00591
00592 /**
00593   * @brief   AF 2 selection
00594   */
00595 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
00596 #define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
00597 #define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
00598 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
00599 #define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
00600
00601 /**
00602   * @brief   AF 3 selection
00603   */
00604
00605 /**
00606   * @brief   AF 4 selection
00607   */
00608 #define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
00609 #define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
00610 #define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
00611 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
00612
00613 /**
00614   * @brief   AF 5 selection
00615   */
00616 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00617 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00618 #define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
00619 #define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
00620 #define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
00621 #define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
00622
00623 /**
00624   * @brief   AF 6 selection
00625   */
00626 #define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
00627 #define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
00628
00629 /**
00630   * @brief   AF 7 selection
00631   */
00632 #define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
00633
00634 #define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
00635
00636 #endif /* STM32G050xx */
00637
00638 #if defined (STM32G031xx) || defined (STM32G041xx)
00639 /*------------------------- STM32G041xx / STM32G031xx ------------------------*/
00640 /**
00641   * @brief   AF 0 selection
00642   */
00643 #define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
00644 #define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
00645 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
00646 #define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00647 #define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
00648 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
00649 #define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
00650 #define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
00651 #define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
00652 #define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
00653 #define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
00654
00655 /**
00656   * @brief   AF 1 selection
00657   */
00658 #define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
00659 #define GPIO_AF1_LPUART1       ((uint8_t)0x01)  /*!< LPUART1 Alternate Function mapping */
00660 #define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00661 #define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00662 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
00663 #define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
00664 #define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
00665 #define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
00666
00667 /**
00668   * @brief   AF 2 selection
00669   */
00670 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
00671 #define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
00672 #define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
00673 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
00674 #define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
00675
00676 /**
00677   * @brief   AF 3 selection
00678   */
00679
00680 /**
00681   * @brief   AF 4 selection
00682   */
00683 #define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
00684 #define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
00685 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
00686
00687 /**
00688   * @brief   AF 5 selection
00689   */
00690 #define GPIO_AF5_LPTIM1        ((uint8_t)0x05)  /*!< LPTIM1 Alternate Function mapping */
00691 #define GPIO_AF5_LPTIM2        ((uint8_t)0x05)  /*!< LPTIM2 Alternate Function mapping */
00692 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00693 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00694 #define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
00695 #define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
00696 #define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
00697
00698 /**
00699   * @brief   AF 6 selection
00700   */
00701 #define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
00702 #define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
00703 #define GPIO_AF6_LPUART1       ((uint8_t)0x06)  /*!< LPUART1 Alternate Function mapping */
00704
00705 /**
00706   * @brief   AF 7 selection
00707   */
00708 #define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
00709
00710 #define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
00711
00712 #endif /* STM32G031xx || STM32G041xx */
00713
00714 #if defined (STM32G030xx)
00715 /*------------------------- STM32G030xx --------------------------------------*/
00716 /**
00717   * @brief   AF 0 selection
00718   */
00719 #define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
00720 #define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
00721 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
00722 #define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00723 #define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
00724 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
00725 #define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
00726 #define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
00727 #define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
00728 #define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
00729 #define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
00730
00731 /**
00732   * @brief   AF 1 selection
00733   */
00734 #define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
00735 #define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
00736 #define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
00737 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
00738 #define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
00739 #define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
00740 #define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
00741
00742 /**
00743   * @brief   AF 2 selection
00744   */
00745 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
00746 #define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
00747 #define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
00748 #define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
00749
00750 /**
00751   * @brief   AF 3 selection
00752   */
00753
00754 /**
00755   * @brief   AF 4 selection
00756   */
00757 #define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
00758 #define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
00759 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
00760
00761 /**
00762   * @brief   AF 5 selection
00763   */
00764 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
00765 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
00766 #define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
00767 #define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
00768 #define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
00769
00770 /**
00771   * @brief   AF 6 selection
00772   */
00773 #define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
00774 #define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
00775
00776 /**
00777   * @brief   AF 7 selection
00778   */
00779 #define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
00780
00781 #define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
00782
00783 #endif /* STM32G030xx */
00784
00785 /**
00786   * @}
00787   */
00788
00789 /**
00790   * @}
00791   */
00792
00793 /* Exported macro ------------------------------------------------------------*/
00794 /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
00795   * @{
00796   */
00797
00798 /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
00799 * @{
00800   */
00801 #if defined(GPIOE)
00802 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\
00803                                       ((__GPIOx__) == (GPIOB))? 1uL :\
00804                                       ((__GPIOx__) == (GPIOC))? 2uL :\
00805                                       ((__GPIOx__) == (GPIOD))? 3uL :\
00806                                       ((__GPIOx__) == (GPIOE))? 4uL : 5uL)
00807 #else
00808 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\
00809                                       ((__GPIOx__) == (GPIOB))? 1uL :\
00810                                       ((__GPIOx__) == (GPIOC))? 2uL :\
00811                                       ((__GPIOx__) == (GPIOD))? 3uL : 5uL)
00812 #endif /* GPIOE */
00813
00814 /**
00815   * @}
00816   */
00817
00818 /**
00819   * @}
00820   */
00821
00822 /* Exported functions --------------------------------------------------------*/
00823 /**
00824   * @}
00825   */
00826
00827 /**
00828   * @}
00829   */
00830
00831 #ifdef __cplusplus
00832 }
00833 #endif
00834
00835 #endif /* STM32G0xx_HAL_GPIO_EX_H */
00836
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_hcd.c Source File

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stm32g0xx_hal_hcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_hcd.c
00004   * @author  MCD Application Team
00005   * @brief   HCD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2018 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                     ##### How to use this driver #####
00027   ==============================================================================
00028   [..]
00029     (#)Declare a HCD_HandleTypeDef handle structure, for example:
00030        HCD_HandleTypeDef  hhcd;
00031
00032     (#)Fill parameters of Init structure in HCD handle
00033
00034     (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
00035
00036     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
00037         (##) Enable the HCD/USB Low Level interface clock using the following macros
00038              (+++) __HAL_RCC_USB_CLK_ENABLE();
00039         (##) Initialize the related GPIO clocks
00040         (##) Configure HCD pin-out
00041         (##) Configure HCD NVIC interrupt
00042
00043     (#)Associate the Upper USB Host stack to the HAL HCD Driver:
00044         (##) hhcd.pData = phost;
00045
00046     (#)Enable HCD transmission and reception:
00047         (##) HAL_HCD_Start();
00048
00049   @endverbatim
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32g0xx_hal.h"
00055
00056 /** @addtogroup STM32G0xx_HAL_Driver
00057   * @{
00058   */
00059
00060 #ifdef HAL_HCD_MODULE_ENABLED
00061 #if defined (USB_DRD_FS)
00062
00063 /** @defgroup HCD HCD
00064   * @brief HCD HAL module driver
00065   * @{
00066   */
00067
00068 /* Private typedef -----------------------------------------------------------*/
00069 /* Private define ------------------------------------------------------------*/
00070 /* Private macro -------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function ----------------------------------------------------------*/
00073 /** @defgroup HCD_Private_Functions HCD Private Functions
00074   * @{
00075   */
00076 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00077 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00078 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
00079 static void HAL_HCD_ClearPhyChannel(HCD_HandleTypeDef *hhcd);
00080 static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef *hhcd, uint8_t phy_chnum, uint8_t dir);
00081 static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
00082 static uint8_t HAL_HCD_Get_FreePhyChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t ep_type);
00083
00084 #if (USE_USB_DOUBLE_BUFFER == 1U)
00085 static void HCD_HC_IN_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue);
00086 static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue);
00087 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
00088
00089 static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps);
00090 static HAL_StatusTypeDef  HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps);
00091 static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue);
00092 /**
00093   * @}
00094   */
00095
00096 /* Exported functions --------------------------------------------------------*/
00097 /** @defgroup HCD_Exported_Functions HCD Exported Functions
00098   * @{
00099   */
00100
00101 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00102   *  @brief    Initialization and Configuration functions
00103   *
00104 @verbatim
00105 ===============================================================================
00106 ##### Initialization and de-initialization functions #####
00107 ===============================================================================
00108 [..]  This section provides functions allowing to:
00109
00110 @endverbatim
00111   * @{
00112   */
00113
00114 /**
00115   * @brief  Initialize the host driver.
00116   * @param  hhcd HCD handle
00117   * @retval HAL status
00118   */
00119 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
00120 {
00121   /* Check the HCD handle allocation */
00122   if (hhcd == NULL)
00123   {
00124     return HAL_ERROR;
00125   }
00126
00127   /* Check the parameters */
00128   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
00129
00130   if (hhcd->State == HAL_HCD_STATE_RESET)
00131   {
00132     /* Allocate lock resource and initialize it */
00133     hhcd->Lock = HAL_UNLOCKED;
00134
00135 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00136     hhcd->SOFCallback = HAL_HCD_SOF_Callback;
00137     hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
00138     hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
00139     hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
00140     hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
00141     hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
00142
00143     if (hhcd->MspInitCallback == NULL)
00144     {
00145       hhcd->MspInitCallback = HAL_HCD_MspInit;
00146     }
00147
00148     /* Init the low level hardware */
00149     hhcd->MspInitCallback(hhcd);
00150 #else
00151     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00152     HAL_HCD_MspInit(hhcd);
00153 #endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
00154   }
00155   hhcd->State = HAL_HCD_STATE_BUSY;
00156
00157   /* Disable the Interrupts */
00158   (void)__HAL_HCD_DISABLE(hhcd);
00159
00160   /* Dma not supported, force to zero */
00161   hhcd->Init.dma_enable = 0U;
00162
00163   /* Init the Core (common init.) */
00164   (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
00165
00166   /* Force Host Mode */
00167   (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
00168
00169   /* Init Host */
00170   (void)USB_HostInit(hhcd->Instance, hhcd->Init);
00171
00172   /* Deactivate the power down */
00173   hhcd->Instance->CNTR  &= ~USB_CNTR_PDWN;
00174
00175   hhcd->State = HAL_HCD_STATE_READY;
00176
00177   /* Host Port State */
00178   hhcd->HostState = HCD_HCD_STATE_DISCONNECTED;
00179
00180   /* Init PMA Address */
00181   (void)HAL_HCD_PMAReset(hhcd);
00182
00183   hhcd->State = HAL_HCD_STATE_READY;
00184
00185   return HAL_OK;
00186 }
00187
00188 /**
00189   * @brief  Initialize a host channel.
00190   * @param  hhcd HCD handle
00191   * @param  ch_num Channel number.
00192   *         This parameter can be a value from 1 to 15
00193   * @param  epnum Endpoint number.
00194   *          This parameter can be a value from 1 to 15
00195   * @param  dev_address Current device address
00196   *          This parameter can be a value from 0 to 255
00197   * @param  speed Current device speed.
00198   *          This parameter can be one of these values:
00199   *            HCD_DEVICE_SPEED_HIGH High speed mode,
00200   *            HCD_DEVICE_SPEED_FULL Full speed mode,
00201   *            HCD_DEVICE_SPEED_LOW Low speed mode
00202   * @param  ep_type Endpoint Type.
00203   *          This parameter can be one of these values:
00204   *            USBH_EP_CONTROL Control type,
00205   *            USBH_EP_ISO Isochronous type,
00206   *            USBH_EP_BULK Bulk type,
00207   *            USBH_EP_INTERRUPT Interrupt type
00208   * @param  mps Max Packet Size.
00209   *          This parameter can be a value from 0 to32K
00210   * @retval HAL status
00211   */
00212 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
00213                                   uint8_t epnum, uint8_t dev_address,
00214                                   uint8_t speed, uint8_t ep_type, uint16_t mps)
00215 {
00216   HAL_StatusTypeDef status;
00217   uint8_t used_channel;
00218   uint8_t ep0_virtual_channel;
00219
00220   __HAL_LOCK(hhcd);
00221
00222   /* Check if the logical channel are already allocated */
00223   used_channel = HAL_HCD_Check_usedChannel(hhcd, ch_num);
00224
00225   /* Check if the channel is not already opened */
00226   if (used_channel == 0U)
00227   {
00228     /* Allocate New Physical channel */
00229     hhcd->hc[ch_num & 0xFU].phy_ch_num = HAL_HCD_Get_FreePhyChannel(hhcd, ch_num, epnum, ep_type);
00230
00231     /* No free Channel available, return error */
00232     if (hhcd->hc[ch_num & 0xFU].phy_ch_num == HCD_FREE_CH_NOT_FOUND)
00233     {
00234       return HAL_ERROR;
00235     }
00236   }
00237   /* Channel already opened */
00238   else
00239   {
00240     /* Get Physical Channel number */
00241     hhcd->hc[ch_num & 0xFU].phy_ch_num = (used_channel & 0xF0U) >> 4U;
00242   }
00243
00244   if ((epnum & 0x80U) != 0U)
00245   {
00246     hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR;
00247   }
00248   else
00249   {
00250     hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR;
00251   }
00252
00253   hhcd->hc[ch_num & 0xFU].dev_addr   = dev_address;
00254   hhcd->hc[ch_num & 0xFU].max_packet = mps;
00255   hhcd->hc[ch_num & 0xFU].ep_type    = ep_type;
00256   hhcd->hc[ch_num & 0xFU].ep_num     = epnum & 0x7FU;
00257   hhcd->hc[ch_num & 0xFU].speed      = speed;
00258
00259   /* Check if the channel is not already opened */
00260   if (used_channel == 0U)
00261   {
00262     if (((ep_type == EP_TYPE_ISOC) && (hhcd->Init.iso_singlebuffer_enable == 0U)) ||
00263         ((ep_type == EP_TYPE_BULK) && (hhcd->Init.bulk_doublebuffer_enable == 1U)))
00264     {
00265       /* PMA Dynamic Allocation */
00266       status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_DBL_BUF, mps);
00267
00268       if (status == HAL_ERROR)
00269       {
00270         return HAL_ERROR;
00271       }
00272
00273       /* Clear Channel DTOG_TX */
00274       HCD_CLEAR_TX_DTOG(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num);
00275
00276       /* Clear Channel DTOG RX */
00277       HCD_CLEAR_RX_DTOG(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num);
00278
00279     }
00280     else
00281     {
00282       if (hhcd->hc[ch_num & 0xFU].ep_num != 0U)
00283       {
00284         status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, mps);
00285
00286         if (status == HAL_ERROR)
00287         {
00288           return HAL_ERROR;
00289         }
00290       }
00291       else
00292       {
00293         if (ch_num == 0U)
00294         {
00295           ep0_virtual_channel = (uint8_t)(hhcd->ep0_PmaAllocState & 0xFU);
00296
00297           if ((ep0_virtual_channel != 0U) && (((hhcd->ep0_PmaAllocState & 0xF0U) >> 4) == CH_IN_DIR))
00298           {
00299             if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_OUT_DIR)
00300             {
00301               status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U);
00302
00303               if (status == HAL_ERROR)
00304               {
00305                 return HAL_ERROR;
00306               }
00307             }
00308             else
00309             {
00310               return HAL_ERROR;
00311             }
00312           }
00313           else
00314           {
00315             /* PMA Dynamic Allocation for EP0 OUT direction */
00316             hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR;
00317             status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U);
00318
00319             if (status == HAL_ERROR)
00320             {
00321               return HAL_ERROR;
00322             }
00323
00324             /* PMA Dynamic Allocation for EP0 IN direction */
00325             hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR;
00326             status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U);
00327
00328             if (status == HAL_ERROR)
00329             {
00330               return HAL_ERROR;
00331             }
00332           }
00333         }
00334         else
00335         {
00336           if (((hhcd->ep0_PmaAllocState & 0xF00U) >> 8) == 1U)
00337           {
00338             ep0_virtual_channel = (uint8_t)(hhcd->ep0_PmaAllocState & 0xFU);
00339
00340             if (((hhcd->ep0_PmaAllocState & 0xF0U) >> 4) == CH_IN_DIR)
00341             {
00342               hhcd->hc[ch_num & 0xFU].pmaaddr1 = hhcd->hc[ep0_virtual_channel & 0xFU].pmaaddr1;
00343             }
00344             else
00345             {
00346               hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[ep0_virtual_channel & 0xFU].pmaaddr0;
00347             }
00348           }
00349           else
00350           {
00351             status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U);
00352
00353             if (status == HAL_ERROR)
00354             {
00355               return HAL_ERROR;
00356             }
00357           }
00358         }
00359       }
00360     }
00361   }
00362
00363   if ((epnum & 0x80U) != 0U)
00364   {
00365     hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR;
00366
00367     if (hhcd->hc[ch_num & 0xFU].ep_num == 0U)
00368     {
00369       hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[ch_num & 0xFU].pmaaddr1;
00370     }
00371   }
00372   else
00373   {
00374     hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR;
00375
00376     if (hhcd->hc[ch_num & 0xFU].ep_num == 0U)
00377     {
00378       hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[ch_num & 0xFU].pmaaddr0;
00379     }
00380   }
00381
00382   /* Init the USB Channel CHEPRx */
00383   status =  USB_HC_Init(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num,
00384                         epnum, dev_address, speed, ep_type, mps);
00385
00386   /* check single buffer for isochronous channel */
00387   if (ep_type == EP_TYPE_ISOC)
00388   {
00389     if (hhcd->Init.iso_singlebuffer_enable == 1U)
00390     {
00391       (void)USB_HC_DoubleBuffer(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num,
00392                                 USB_DRD_ISOC_DBUFF_DISABLE);
00393     }
00394   }
00395
00396   /* Bulk double buffer check */
00397   if (ep_type == EP_TYPE_BULK)
00398   {
00399     if (hhcd->Init.bulk_doublebuffer_enable == 1U)
00400     {
00401       (void)USB_HC_DoubleBuffer(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num,
00402                                 USB_DRD_BULK_DBUFF_ENBALE);
00403     }
00404   }
00405
00406   __HAL_UNLOCK(hhcd);
00407
00408   return status;
00409 }
00410
00411 /**
00412   * @brief  HAL_HCD_HC_Close Pipe
00413   * @param  hhcd HCD handle
00414   * @param  ch_num Channel number.
00415   *         This parameter can be a value from 1 to 15
00416   * @retval HAL status
00417   */
00418 HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
00419 {
00420   /* Stop the channel */
00421   (void) HAL_HCD_HC_Halt(hhcd, ch_num);
00422
00423   HAL_Delay(3U);
00424
00425   if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_IN_DIR)
00426   {
00427     /* Free Allocated Channel */
00428     hhcd->phy_chin_state[hhcd->hc[ch_num & 0xFU].phy_ch_num] = 0U;
00429   }
00430   else
00431   {
00432     /* Free Allocated Channel */
00433     hhcd->phy_chout_state[hhcd->hc[ch_num & 0xFU].phy_ch_num] = 0U;
00434   }
00435
00436   /* Reset PMA Channel_Allocation */
00437   (void)HAL_HCD_PMADeAlloc(hhcd, ch_num);
00438
00439   return HAL_OK;
00440 }
00441
00442 /**
00443   * @brief  Halt a host channel.
00444   * @param  hhcd HCD handle
00445   * @param  ch_num Channel number.
00446   *         This parameter can be a value from 1 to 15
00447   * @retval HAL status
00448   */
00449 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
00450 {
00451   HAL_StatusTypeDef status = HAL_OK;
00452
00453   __HAL_LOCK(hhcd);
00454   if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_IN_DIR)
00455   {
00456     (void)USB_HC_IN_Halt(hhcd->Instance, (uint8_t) hhcd->hc[ch_num & 0xFU].phy_ch_num);
00457   }
00458   else
00459   {
00460     (void)USB_HC_OUT_Halt(hhcd->Instance, (uint8_t) hhcd->hc[ch_num & 0xFU].phy_ch_num);
00461   }
00462   __HAL_UNLOCK(hhcd);
00463
00464   return status;
00465 }
00466
00467 /**
00468   * @brief  DeInitialize the host driver.
00469   * @param  hhcd HCD handle
00470   * @retval HAL status
00471   */
00472 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
00473 {
00474   uint8_t idx;
00475
00476   /* Check the HCD handle allocation */
00477   if (hhcd == NULL)
00478   {
00479     return HAL_ERROR;
00480   }
00481
00482   /* Host Port State */
00483   hhcd->HostState = HCD_HCD_STATE_DISCONNECTED;
00484
00485   /* Reset PMA Address */
00486   (void)HAL_HCD_PMAReset(hhcd);
00487
00488   for (idx = 0U; idx < hhcd->Init.Host_channels; idx++)
00489   {
00490     hhcd->phy_chin_state[idx] = 0U;
00491     hhcd->phy_chout_state[idx] = 0U;
00492   }
00493
00494   /* reset Ep0 Pma allocation state */
00495   hhcd->ep0_PmaAllocState = 0U;
00496
00497   hhcd->State = HAL_HCD_STATE_BUSY;
00498
00499 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00500   if (hhcd->MspDeInitCallback == NULL)
00501   {
00502     hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */
00503   }
00504
00505   /* DeInit the low level hardware */
00506   hhcd->MspDeInitCallback(hhcd);
00507 #else
00508   /* DeInit the low level hardware: CLOCK, NVIC. */
00509   HAL_HCD_MspDeInit(hhcd);
00510 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00511
00512   hhcd->State = HAL_HCD_STATE_RESET;
00513
00514   return HAL_OK;
00515 }
00516
00517 /**
00518   * @brief  Initialize the HCD MSP.
00519   * @param  hhcd HCD handle
00520   * @retval None
00521   */
00522 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
00523 {
00524   /* Prevent unused argument(s) compilation warning */
00525   UNUSED(hhcd);
00526
00527   /* NOTE : This function Should not be modified, when the callback is needed,
00528   the HAL_HCD_MspInit could be implemented in the user file
00529   */
00530 }
00531
00532 /**
00533   * @brief  DeInitialize the HCD MSP.
00534   * @param  hhcd HCD handle
00535   * @retval None
00536   */
00537 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
00538 {
00539   /* Prevent unused argument(s) compilation warning */
00540   UNUSED(hhcd);
00541
00542   /* NOTE : This function Should not be modified, when the callback is needed,
00543   the HAL_HCD_MspDeInit could be implemented in the user file
00544   */
00545 }
00546
00547 __weak void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd)
00548 {
00549   /* Prevent unused argument(s) compilation warning */
00550   UNUSED(hhcd);
00551
00552   /* NOTE : This function Should not be modified, when the callback is needed,
00553   the HAL_HCD_SuspendCallback could be implemented in the user file
00554   */
00555
00556 }
00557
00558 __weak void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd)
00559 {
00560   /* Prevent unused argument(s) compilation warning */
00561   UNUSED(hhcd);
00562
00563   /* NOTE : This function Should not be modified, when the callback is needed,
00564   the HAL_HCD_ResumeCallback could be implemented in the user file
00565   */
00566 }
00567
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
00573   *  @brief   HCD IO operation functions
00574   *
00575 @verbatim
00576 ===============================================================================
00577 ##### IO operation functions #####
00578 ===============================================================================
00579 [..] This subsection provides a set of functions allowing to manage the USB Host Data
00580 Transfer
00581
00582 @endverbatim
00583   * @{
00584   */
00585
00586 /**
00587   * @brief  Submit a new URB for processing.
00588   * @param  hhcd HCD handle
00589   * @param  ch_num Channel number.
00590   *         This parameter can be a value from 1 to 15
00591   * @param  direction Channel number.
00592   *          This parameter can be one of these values:
00593   *           0 : Output / 1 : Input
00594   * @param  ep_type Endpoint Type.
00595   *          This parameter can be one of these values:
00596   *            USBH_EP_CONTROL   : Control type/
00597   *            USBH_EP_ISO       : Isochronous type/
00598   *            USBH_EP_BULK      : Bulk type/
00599   *            USBH_EP_INTERRUPT : Interrupt type/
00600   * @param  token Endpoint Type.
00601   *          This parameter can be one of these values:
00602   *            0: HC_PID_SETUP / 1: HC_PID_DATA1
00603   * @param  pbuff pointer to URB data
00604   * @param  length Length of URB data
00605   * @param  do_ping activate do ping protocol (for high speed only).
00606   *          This parameter can be one of these values:
00607   *           0 : do ping inactive / 1 : do ping active
00608   * @retval HAL status
00609   */
00610 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
00611                                            uint8_t direction, uint8_t ep_type,
00612                                            uint8_t token, uint8_t *pbuff,
00613                                            uint16_t length, uint8_t do_ping)
00614 {
00615   UNUSED(do_ping);
00616
00617   if (token == 0U)
00618   {
00619     hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_SETUP;
00620   }
00621   else
00622   {
00623     hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1;
00624   }
00625
00626   /* Manage Data Toggle */
00627   switch (ep_type)
00628   {
00629     case EP_TYPE_CTRL:
00630       if ((token == 1U) && (direction == 0U)) /* send data */
00631       {
00632         if (length == 0U)
00633         {
00634           /* For Status OUT stage, Length==0, Status Out PID = 1 */
00635           hhcd->hc[ch_num & 0xFU].toggle_out = 1U;
00636         }
00637
00638         /* Set the Data Toggle bit as per the Flag */
00639         if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U)
00640         {
00641           /* Put the PID 0 */
00642           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0;
00643         }
00644         else
00645         {
00646           /* Put the PID 1 */
00647           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1;
00648         }
00649       }
00650       break;
00651
00652     case EP_TYPE_BULK:
00653       if (direction == 0U)
00654       {
00655         /* Set the Data Toggle bit as per the Flag */
00656         if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U)
00657         {
00658           /* Put the PID 0 */
00659           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0;
00660         }
00661         else
00662         {
00663           /* Put the PID 1 */
00664           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1;
00665         }
00666       }
00667       else
00668       {
00669         if (hhcd->hc[ch_num & 0xFU].toggle_in == 0U)
00670         {
00671           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0;
00672         }
00673         else
00674         {
00675           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1;
00676         }
00677       }
00678       break;
00679
00680     case EP_TYPE_INTR:
00681       if (direction == 0U)
00682       {
00683         /* Set the Data Toggle bit as per the Flag */
00684         if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U)
00685         {
00686           /* Put the PID 0 */
00687           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0;
00688         }
00689         else
00690         {
00691           /* Put the PID 1 */
00692           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1;
00693         }
00694       }
00695       else
00696       {
00697         if (hhcd->hc[ch_num & 0xFU].toggle_in == 0U)
00698         {
00699           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0;
00700         }
00701         else
00702         {
00703           hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1;
00704         }
00705       }
00706       break;
00707
00708     case EP_TYPE_ISOC:
00709       hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0;
00710       break;
00711
00712     default:
00713       break;
00714   }
00715
00716   hhcd->hc[ch_num & 0xFU].xfer_buff = pbuff;
00717   hhcd->hc[ch_num & 0xFU].xfer_len  = length;
00718   hhcd->hc[ch_num & 0xFU].xfer_len_db  = length;
00719   hhcd->hc[ch_num & 0xFU].urb_state = URB_IDLE;
00720   hhcd->hc[ch_num & 0xFU].xfer_count = 0U;
00721   hhcd->hc[ch_num & 0xFU].state = HC_IDLE;
00722
00723   return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]);
00724 }
00725 /**
00726   * @brief  Handle HCD interrupt request.
00727   * @param  hhcd HCD handle
00728   * @retval None
00729   */
00730 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
00731 {
00732   uint8_t phy_chnum;
00733   uint8_t chnum;
00734   uint32_t epch_reg;
00735   uint32_t wIstr = USB_ReadInterrupts(hhcd->Instance);
00736
00737   /* check if this is an USB pending IT */
00738   if ((SYSCFG->IT_LINE_SR[8] & (0x1U << 2)) == 0U)
00739   {
00740     return;
00741   }
00742
00743   /* Port Change Detected (Connection/Disconnection) */
00744   if ((wIstr & USB_ISTR_DCON) == USB_ISTR_DCON)
00745   {
00746     /* Clear Flag */
00747     __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_DCON);
00748
00749     /* Call Port IRQHandler */
00750     HCD_Port_IRQHandler(hhcd);
00751
00752     return;
00753   }
00754
00755   /* Correct Transaction Detected -------*/
00756   if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
00757   {
00758     /* Handle Host channel Interrupt */
00759     for (phy_chnum = 0U; phy_chnum < hhcd->Init.Host_channels; phy_chnum++)
00760     {
00761       if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTRX) != 0U)
00762       {
00763         /* Get Logical channel to check if the channel is already opened */
00764         chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U);
00765
00766         if (chnum != HCD_LOGICAL_CH_NOT_OPENED)
00767         {
00768           /* Call Channel_IN_IRQ() */
00769           HCD_HC_IN_IRQHandler(hhcd, chnum);
00770         }
00771         else
00772         {
00773           /*Channel was not closed correctly still have interrupt */
00774           epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum);
00775           epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRRX) & (~USB_CH_VTRX))) |
00776                      (USB_CH_VTTX | USB_CH_ERRTX);
00777
00778           HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg);
00779         }
00780       }
00781
00782       if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTTX) != 0U)
00783       {
00784         /* Get Logical channel to check if the channel is already opened */
00785         chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U);
00786
00787         if (chnum != HCD_LOGICAL_CH_NOT_OPENED)
00788         {
00789           /*Call Channel_OUT_IRQ()*/
00790           HCD_HC_OUT_IRQHandler(hhcd, chnum);
00791         }
00792         else
00793         {
00794           /* Clear Error & unwanted VTTX or Channel was not closed correctly */
00795           epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum);
00796           epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRTX) & (~USB_CH_VTTX))) |
00797                      (USB_CH_VTRX | USB_CH_ERRRX);
00798
00799           HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg);
00800         }
00801       }
00802     }
00803
00804     return;
00805   }
00806
00807   /* Wakeup Flag Detected */
00808   if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
00809   {
00810     if (hhcd->HostState == HCD_HCD_STATE_SUSPEND)
00811     {
00812       /* Set The L2Resume bit */
00813       hhcd->Instance->CNTR |= USB_CNTR_L2RES;
00814
00815       /* Clear the wake-up flag */
00816       __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_WKUP);
00817
00818       /* Update the USB Software state machine */
00819       HAL_HCD_ResumeCallback(hhcd);
00820       hhcd->HostState = HCD_HCD_STATE_RESUME;
00821     }
00822     else
00823     {
00824       /* Clear the wake-up flag */
00825       __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_WKUP);
00826     }
00827
00828     return;
00829   }
00830
00831   /* Global Error Flag Detected */
00832   if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
00833   {
00834     __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_ERR);
00835
00836     return;
00837   }
00838
00839   /* PMA Overrun detected */
00840   if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
00841   {
00842     __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_PMAOVR);
00843
00844     return;
00845   }
00846
00847   /* Suspend Detected */
00848   if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
00849   {
00850     /* Set HAL State to Suspend */
00851     hhcd->HostState = HCD_HCD_STATE_SUSPEND;
00852
00853     /* Force low-power mode in the macrocell */
00854     hhcd->Instance->CNTR |= USB_CNTR_SUSPEN;
00855
00856     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
00857     __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_SUSP);
00858
00859     /* Call suspend Callback */
00860     HAL_HCD_SuspendCallback(hhcd);
00861
00862     return;
00863   }
00864
00865   /* Start Of Frame Detected */
00866   if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
00867   {
00868 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00869     hhcd->SOFCallback(hhcd);
00870 #else
00871     HAL_HCD_SOF_Callback(hhcd);
00872 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00873
00874     __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_SOF);
00875
00876     /* when first SOF is detected after USB_RESET is asserted */
00877     if (hhcd->HostState == HCD_HCD_STATE_RESETED)
00878     {
00879       /* HAL State */
00880       hhcd->HostState = HCD_HCD_STATE_RUN;
00881
00882 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00883       hhcd->PortEnabledCallback(hhcd);
00884 #else
00885       HAL_HCD_PortEnabled_Callback(hhcd);
00886 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00887     }
00888
00889     return;
00890   }
00891 }
00892
00893 /**
00894   * @brief  SOF callback.
00895   * @param  hhcd HCD handle
00896   * @retval None
00897   */
00898 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
00899 {
00900   /* Prevent unused argument(s) compilation warning */
00901   UNUSED(hhcd);
00902
00903   /* NOTE : This function Should not be modified, when the callback is needed,
00904   the HAL_HCD_SOF_Callback could be implemented in the user file
00905   */
00906 }
00907
00908 /**
00909   * @brief Connection Event callback.
00910   * @param  hhcd HCD handle
00911   * @retval None
00912   */
00913 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
00914 {
00915   /* Prevent unused argument(s) compilation warning */
00916   UNUSED(hhcd);
00917
00918   /* NOTE : This function Should not be modified, when the callback is needed,
00919   the HAL_HCD_Connect_Callback could be implemented in the user file
00920   */
00921 }
00922
00923 /**
00924   * @brief  Disconnection Event callback.
00925   * @param  hhcd HCD handle
00926   * @retval None
00927   */
00928 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
00929 {
00930   /* Prevent unused argument(s) compilation warning */
00931   UNUSED(hhcd);
00932
00933   /* NOTE : This function Should not be modified, when the callback is needed,
00934   the HAL_HCD_Disconnect_Callback could be implemented in the user file
00935   */
00936 }
00937 /**
00938   * @brief  Port Enabled  Event callback.
00939   * @param  hhcd HCD handle
00940   * @retval None
00941   */
00942 __weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
00943 {
00944   /* Prevent unused argument(s) compilation warning */
00945   UNUSED(hhcd);
00946
00947   /* NOTE : This function should not be modified, when the callback is needed,
00948             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00949    */
00950 }
00951 /**
00952   * @brief  Port Disabled  Event callback.
00953   * @param  hhcd HCD handle
00954   * @retval None
00955   */
00956 __weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
00957 {
00958   /* Prevent unused argument(s) compilation warning */
00959   UNUSED(hhcd);
00960
00961   /* NOTE : This function should not be modified, when the callback is needed,
00962             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00963    */
00964 }
00965
00966 /**
00967   * @brief  Notify URB state change callback.
00968   * @param  hhcd HCD handle
00969   * @param  chnum Channel number.
00970   *         This parameter can be a value from 1 to 15
00971   * @param  urb_state
00972   *          This parameter can be one of these values:
00973   *            URB_IDLE/
00974   *            URB_DONE/
00975   *            URB_NOTREADY/
00976   *            URB_NYET/
00977   *            URB_ERROR/
00978   *            URB_STALL/
00979   * @retval None
00980   */
00981 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
00982                                                 uint8_t chnum, HCD_URBStateTypeDef urb_state)
00983 {
00984   /* Prevent unused argument(s) compilation warning */
00985   UNUSED(hhcd);
00986   UNUSED(chnum);
00987   UNUSED(urb_state);
00988
00989   /* NOTE : This function Should not be modified, when the callback is needed,
00990   the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
00991   */
00992 }
00993 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00994 /**
00995   * @brief  Register a User USB HCD Callback
00996   *         To be used instead of the weak predefined callback
00997   * @param  hhcd USB HCD handle
00998   * @param  CallbackID ID of the callback to be registered
00999   *         This parameter can be one of the following values:
01000   *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
01001   *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
01002   *          @arg @ref HAL_HCD_DISCONNECT_CB_ID HCD Disconnect callback ID
01003   *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
01004   *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
01005   *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
01006   *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
01007   * @param  pCallback pointer to the Callback function
01008   * @retval HAL status
01009   */
01010 HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
01011                                            HAL_HCD_CallbackIDTypeDef CallbackID,
01012                                            pHCD_CallbackTypeDef pCallback)
01013 {
01014   HAL_StatusTypeDef status = HAL_OK;
01015
01016   if (pCallback == NULL)
01017   {
01018     /* Update the error code */
01019     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01020     return HAL_ERROR;
01021   }
01022   /* Process locked */
01023   __HAL_LOCK(hhcd);
01024
01025   if (hhcd->State == HAL_HCD_STATE_READY)
01026   {
01027     switch (CallbackID)
01028     {
01029       case HAL_HCD_SOF_CB_ID :
01030         hhcd->SOFCallback = pCallback;
01031         break;
01032
01033       case HAL_HCD_CONNECT_CB_ID :
01034         hhcd->ConnectCallback = pCallback;
01035         break;
01036
01037       case HAL_HCD_DISCONNECT_CB_ID :
01038         hhcd->DisconnectCallback = pCallback;
01039         break;
01040
01041       case HAL_HCD_PORT_ENABLED_CB_ID :
01042         hhcd->PortEnabledCallback = pCallback;
01043         break;
01044
01045       case HAL_HCD_PORT_DISABLED_CB_ID :
01046         hhcd->PortDisabledCallback = pCallback;
01047         break;
01048
01049       case HAL_HCD_MSPINIT_CB_ID :
01050         hhcd->MspInitCallback = pCallback;
01051         break;
01052
01053       case HAL_HCD_MSPDEINIT_CB_ID :
01054         hhcd->MspDeInitCallback = pCallback;
01055         break;
01056
01057       default :
01058         /* Update the error code */
01059         hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01060         /* Return error status */
01061         status =  HAL_ERROR;
01062         break;
01063     }
01064   }
01065   else if (hhcd->State == HAL_HCD_STATE_RESET)
01066   {
01067     switch (CallbackID)
01068     {
01069       case HAL_HCD_MSPINIT_CB_ID :
01070         hhcd->MspInitCallback = pCallback;
01071         break;
01072
01073       case HAL_HCD_MSPDEINIT_CB_ID :
01074         hhcd->MspDeInitCallback = pCallback;
01075         break;
01076
01077       default :
01078         /* Update the error code */
01079         hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01080         /* Return error status */
01081         status =  HAL_ERROR;
01082         break;
01083     }
01084   }
01085   else
01086   {
01087     /* Update the error code */
01088     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01089     /* Return error status */
01090     status =  HAL_ERROR;
01091   }
01092
01093   /* Release Lock */
01094   __HAL_UNLOCK(hhcd);
01095   return status;
01096 }
01097
01098 /**
01099   * @brief  Unregister an USB HCD Callback
01100   *         USB HCD callback is redirected to the weak predefined callback
01101   * @param  hhcd USB HCD handle
01102   * @param  CallbackID ID of the callback to be unregistered
01103   *         This parameter can be one of the following values:
01104   *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
01105   *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
01106   *          @arg @ref HAL_HCD_DISCONNECT_CB_ID DRD HCD Disconnect callback ID
01107   *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
01108   *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
01109   *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
01110   *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
01111   * @retval HAL status
01112   */
01113 HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
01114                                              HAL_HCD_CallbackIDTypeDef CallbackID)
01115 {
01116   HAL_StatusTypeDef status = HAL_OK;
01117
01118   /* Process locked */
01119   __HAL_LOCK(hhcd);
01120
01121   /* Setup Legacy weak Callbacks */
01122   if (hhcd->State == HAL_HCD_STATE_READY)
01123   {
01124     switch (CallbackID)
01125     {
01126       case HAL_HCD_SOF_CB_ID :
01127         hhcd->SOFCallback = HAL_HCD_SOF_Callback;
01128         break;
01129
01130       case HAL_HCD_CONNECT_CB_ID :
01131         hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
01132         break;
01133
01134       case HAL_HCD_DISCONNECT_CB_ID :
01135         hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
01136         break;
01137
01138       case HAL_HCD_PORT_ENABLED_CB_ID :
01139         hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
01140         break;
01141
01142       case HAL_HCD_PORT_DISABLED_CB_ID :
01143         hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
01144         break;
01145
01146       case HAL_HCD_MSPINIT_CB_ID :
01147         hhcd->MspInitCallback = HAL_HCD_MspInit;
01148         break;
01149
01150       case HAL_HCD_MSPDEINIT_CB_ID :
01151         hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
01152         break;
01153
01154       default :
01155         /* Update the error code */
01156         hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01157
01158         /* Return error status */
01159         status =  HAL_ERROR;
01160         break;
01161     }
01162   }
01163   else if (hhcd->State == HAL_HCD_STATE_RESET)
01164   {
01165     switch (CallbackID)
01166     {
01167       case HAL_HCD_MSPINIT_CB_ID :
01168         hhcd->MspInitCallback = HAL_HCD_MspInit;
01169         break;
01170
01171       case HAL_HCD_MSPDEINIT_CB_ID :
01172         hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
01173         break;
01174
01175       default :
01176         /* Update the error code */
01177         hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01178
01179         /* Return error status */
01180         status =  HAL_ERROR;
01181         break;
01182     }
01183   }
01184   else
01185   {
01186     /* Update the error code */
01187     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01188
01189     /* Return error status */
01190     status =  HAL_ERROR;
01191   }
01192
01193   /* Release Lock */
01194   __HAL_UNLOCK(hhcd);
01195   return status;
01196 }
01197
01198 /**
01199   * @brief  Register USB HCD Host Channel Notify URB Change Callback
01200   *         To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
01201   * @param  hhcd HCD handle
01202   * @param  pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
01203   * @retval HAL status
01204   */
01205 HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
01206                                                              pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
01207 {
01208   HAL_StatusTypeDef status = HAL_OK;
01209
01210   if (pCallback == NULL)
01211   {
01212     /* Update the error code */
01213     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01214
01215     return HAL_ERROR;
01216   }
01217
01218   /* Process locked */
01219   __HAL_LOCK(hhcd);
01220
01221   if (hhcd->State == HAL_HCD_STATE_READY)
01222   {
01223     hhcd->HC_NotifyURBChangeCallback = pCallback;
01224   }
01225   else
01226   {
01227     /* Update the error code */
01228     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01229
01230     /* Return error status */
01231     status = HAL_ERROR;
01232   }
01233
01234   /* Release Lock */
01235   __HAL_UNLOCK(hhcd);
01236
01237   return status;
01238 }
01239
01240 /**
01241   * @brief  Unregister the USB HCD Host Channel Notify URB Change Callback
01242   *         USB HCD Host Channel Notify URB Change Callback is redirected
01243   *         to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
01244   * @param  hhcd HCD handle
01245   * @retval HAL status
01246   */
01247 HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
01248 {
01249   HAL_StatusTypeDef status = HAL_OK;
01250
01251   /* Process locked */
01252   __HAL_LOCK(hhcd);
01253
01254   if (hhcd->State == HAL_HCD_STATE_READY)
01255   {
01256     hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */
01257   }
01258   else
01259   {
01260     /* Update the error code */
01261     hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
01262
01263     /* Return error status */
01264     status =  HAL_ERROR;
01265   }
01266
01267   /* Release Lock */
01268   __HAL_UNLOCK(hhcd);
01269
01270   return status;
01271 }
01272 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
01273
01274
01275 /**
01276   * @}
01277   */
01278
01279 /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
01280   *  @brief   Management functions
01281   *
01282 @verbatim
01283 ===============================================================================
01284 ##### Peripheral Control functions #####
01285 ===============================================================================
01286 [..]
01287 This subsection provides a set of functions allowing to control the HCD data
01288 transfers.
01289
01290 @endverbatim
01291   * @{
01292   */
01293
01294 /**
01295   * @brief  Start the host driver.
01296   * @param  hhcd HCD handle
01297   * @retval HAL status
01298   */
01299 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
01300 {
01301   __HAL_LOCK(hhcd);
01302
01303   /*Set the PullDown on the PHY */
01304   hhcd->Instance->BCDR |= USB_BCDR_DPPD;
01305
01306   /* Clear Reset  */
01307   hhcd->Instance->CNTR &= ~USB_CNTR_USBRST;
01308
01309   /*Remove PowerDown */
01310   hhcd->Instance->CNTR &= ~USB_CNTR_PDWN;
01311
01312   __HAL_UNLOCK(hhcd);
01313
01314   return HAL_OK;
01315 }
01316
01317 /**
01318   * @brief  Stop the host driver.
01319   * @param  hhcd HCD handle
01320   * @retval HAL status
01321   */
01322 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
01323 {
01324   __HAL_LOCK(hhcd);
01325   /*Stop the Host IP: setting powerdown  */
01326   (void)USB_StopHost(hhcd->Instance);
01327
01328   /* clear all allocated virtual channel */
01329   HAL_HCD_ClearPhyChannel(hhcd);
01330
01331   /* Reset the PMA current pointer */
01332   (void)HAL_HCD_PMAReset(hhcd);
01333
01334   /* reset Ep0 Pma allocation state */
01335   hhcd->ep0_PmaAllocState = 0U;
01336
01337   __HAL_UNLOCK(hhcd);
01338   return HAL_OK;
01339 }
01340
01341 /**
01342   * @brief  Put the Device in suspend mode
01343   * @param  hhcd HCD handle
01344   * @retval HAL status
01345   */
01346 HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd)
01347 {
01348   __IO uint32_t count = 0U;
01349
01350   /* Set Suspend Mode */
01351   hhcd->Instance->CNTR |= USB_CNTR_SUSPEN;
01352
01353   /* wait for Suspend Ready */
01354   while ((hhcd->Instance->CNTR & USB_CNTR_SUSPRDY) == 0U)
01355   {
01356     if (++count > 0xFFFFFFU)
01357     {
01358       return HAL_TIMEOUT;
01359     }
01360   }
01361
01362   return HAL_OK;
01363 }
01364
01365 /**
01366   * @brief  Resume host port
01367   * @param  hhcd HCD handle
01368   * @retval HAL status
01369   */
01370 HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd)
01371 {
01372   /* Set Resume bit */
01373   hhcd->Instance->CNTR |= USB_CNTR_L2RES;
01374
01375   return HAL_OK;
01376 }
01377
01378 /**
01379   * @brief  Reset the host port.
01380   * @param  hhcd HCD handle
01381   * @retval HAL status
01382   */
01383 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
01384 {
01385   __HAL_LOCK(hhcd);
01386
01387   /* Reset the USB Port by inserting an SE0 on the bus */
01388   (void)USB_ResetPort(hhcd->Instance);
01389
01390   if (hhcd->HostState == HCD_HCD_STATE_CONNECTED)
01391   {
01392     hhcd->HostState = HCD_HCD_STATE_RESETED;
01393   }
01394   __HAL_UNLOCK(hhcd);
01395
01396   return HAL_OK;
01397 }
01398
01399 /**
01400   * @brief  Resme the host port.
01401   * @param  hhcd HCD handle
01402   * @retval HAL status
01403   */
01404 HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd)
01405 {
01406   /* Set Resume bit */
01407   hhcd->Instance->CNTR |= USB_CNTR_L2RES;
01408   HAL_Delay(30U);
01409
01410   /* Clear Resume bit */
01411   hhcd->Instance->CNTR &= ~USB_CNTR_L2RES;
01412
01413   return HAL_OK;
01414 }
01415
01416
01417 /**
01418   * @}
01419   */
01420
01421 /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
01422   *  @brief   Peripheral State functions
01423   *
01424 @verbatim
01425 ===============================================================================
01426 ##### Peripheral State functions #####
01427 ===============================================================================
01428 [..]
01429 This subsection permits to get in run-time the status of the peripheral
01430 and the data flow.
01431
01432 @endverbatim
01433   * @{
01434   */
01435
01436 /**
01437   * @brief  Return the HCD handle state.
01438   * @param  hhcd HCD handle
01439   * @retval HAL state
01440   */
01441 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
01442 {
01443   return hhcd->State;
01444 }
01445
01446 /**
01447   * @brief  Return  URB state for a channel.
01448   * @param  hhcd HCD handle
01449   * @param  chnum Channel number.
01450   *         This parameter can be a value from 1 to 15
01451   * @retval URB state.
01452   *          This parameter can be one of these values:
01453   *            URB_IDLE/
01454   *            URB_DONE/
01455   *            URB_NOTREADY/
01456   *            URB_NYET/
01457   *            URB_ERROR/
01458   *            URB_STALL
01459   */
01460 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01461 {
01462   return hhcd->hc[chnum].urb_state;
01463 }
01464
01465
01466 /**
01467   * @brief  Return the last host transfer size.
01468   * @param  hhcd HCD handle
01469   * @param  chnum Channel number.
01470   *         This parameter can be a value from 1 to 15
01471   * @retval last transfer size in byte
01472   */
01473 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01474 {
01475   return hhcd->hc[chnum].xfer_count;
01476 }
01477
01478 /**
01479   * @brief  Return the Host Channel state.
01480   * @param  hhcd HCD handle
01481   * @param  chnum Channel number.
01482   *         This parameter can be a value from 1 to 15
01483   * @retval Host channel state
01484   *          This parameter can be one of these values:
01485   *            HC_IDLE/
01486   *            HC_XFRC/
01487   *            HC_HALTED/
01488   *            HC_NYET/
01489   *            HC_NAK/
01490   *            HC_STALL/
01491   *            HC_XACTERR/
01492   *            HC_BBLERR/
01493   *            HC_DATATGLERR
01494   */
01495 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01496 {
01497   return hhcd->hc[chnum].state;
01498 }
01499
01500 /**
01501   * @brief  Return the current Host frame number.
01502   * @param  hhcd HCD handle
01503   * @retval Current Host frame number
01504   */
01505 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
01506 {
01507   return (USB_GetCurrentFrame(hhcd->Instance));
01508 }
01509
01510 /**
01511   * @brief  Return the Host enumeration speed.
01512   * @param  hhcd HCD handle
01513   * @retval speed : Device speed after Host enumeration
01514   *          This parameter can be one of these values:
01515   *            @arg HCD_DEVICE_SPEED_FULL: Full speed mode
01516   *            @arg HCD_DEVICE_SPEED_LOW: Low speed mode
01517   */
01518 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
01519 {
01520   return (USB_GetHostSpeed(hhcd->Instance));
01521 }
01522
01523 #if (USE_USB_DOUBLE_BUFFER == 1U)
01524 /**
01525   * @brief  Handle Host Channel OUT Double Buffer Bulk requests.
01526   * @param  hhcd HCD handle
01527   * @param  ch_num Channel number This parameter can be a value from 1 to 15
01528   * @param  phy_chnum Physical Channel number [0..7]
01529   * @param  regvalue contain Snapshot of the EPCHn register when ISR is detected
01530   * @retval none
01531   */
01532 static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
01533                               uint8_t phy_chnum, uint32_t regvalue)
01534 {
01535   uint16_t data_xfr;
01536   uint16_t len;
01537
01538   /* Send Buffer0 */
01539   if ((regvalue & USB_CH_DTOG_TX) != 0U)
01540   {
01541     data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U);
01542
01543     if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr)
01544     {
01545       hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr;
01546     }
01547     else
01548     {
01549       hhcd->hc[ch_num & 0xFU].xfer_len = 0U;
01550     }
01551
01552     /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */
01553     if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U)
01554     {
01555       /* manage multiple Xfer */
01556       hhcd->hc[ch_num & 0xFU].xfer_count  += data_xfr;
01557
01558       /* check if we need to free user buffer */
01559       if ((regvalue & USB_CH_DTOG_RX) != 0U)
01560       {
01561         /* Toggle SwBuff */
01562         HCD_CLEAR_TX_DTOG(hhcd->Instance, phy_chnum);
01563         HCD_CLEAR_RX_DTOG(hhcd->Instance, phy_chnum);
01564         HCD_TX_DTOG(hhcd->Instance, phy_chnum);
01565       }
01566
01567       /* hhcd->hc[ch_num&0xFU].xfer_len_db==0 ==> when all data are written in the PMA to yet transferred */
01568       if (hhcd->hc[ch_num & 0xFU].xfer_len_db > 0U) /* Still data to fill in the buffer */
01569       {
01570         hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr;
01571
01572         /* calculate len of new buffer to fill */
01573         if (hhcd->hc[ch_num & 0xFU].xfer_len_db > hhcd->hc[ch_num & 0xFU].max_packet)
01574         {
01575           len = (uint16_t)hhcd->hc[ch_num & 0xFU].max_packet;
01576           hhcd->hc[ch_num & 0xFU].xfer_len_db -= len;
01577         }
01578         else
01579         {
01580           len = (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_len_db;
01581           hhcd->hc[ch_num & 0xFU].xfer_len_db = 0U; /* end of fill buffer */
01582         }
01583
01584         /* Write remaining data to Buffer0 */
01585         HCD_SET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum, 1U, (uint16_t)len);
01586         USB_WritePMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff,
01587                      hhcd->hc[ch_num & 0xFU].pmaaddr0, (uint16_t)len);
01588       }
01589       /* start a new transfer */
01590       HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_VALID);
01591     }
01592     else
01593     {
01594       /* Transfer complete state */
01595       hhcd->hc[ch_num & 0xFU].xfer_count  += data_xfr;
01596       hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
01597       hhcd->hc[ch_num & 0xFU].urb_state  = URB_DONE;
01598       hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U;
01599       /* Close the Channel */
01600       HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS);
01601     }
01602   }
01603   else
01604   {
01605     /* Send Buffer1 */
01606     data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->RXBD & 0x03FF0000U) >> 16U);
01607
01608     if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) /* updated */
01609     {
01610       hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr;
01611     }
01612
01613     /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */
01614     if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U)
01615     {
01616       /* manage multiple Xfer */
01617       hhcd->hc[ch_num & 0xFU].xfer_count  += data_xfr;
01618
01619       /* check if we need to free user buffer */
01620       if ((regvalue & USB_CH_DTOG_RX) == 0U)
01621       {
01622         /* Toggle SwBuff */
01623         HCD_CLEAR_TX_DTOG(hhcd->Instance, phy_chnum);
01624         HCD_CLEAR_RX_DTOG(hhcd->Instance, phy_chnum);
01625         HCD_RX_DTOG(hhcd->Instance, phy_chnum);
01626       }
01627
01628       /* hhcd->hc[ch_num&0xFU].xfer_len_db==0 ==> when all data are written in the PMA to yet transferred */
01629       if (hhcd->hc[ch_num & 0xFU].xfer_len_db > 0U) /* Still data to fill in the buffer */
01630       {
01631         hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr;
01632
01633         /* calculate len of new buffer to fill */
01634         if (hhcd->hc[ch_num & 0xFU].xfer_len_db > hhcd->hc[ch_num & 0xFU].max_packet)
01635         {
01636           len = hhcd->hc[ch_num & 0xFU].max_packet;
01637           hhcd->hc[ch_num & 0xFU].xfer_len_db -= len;
01638         }
01639         else
01640         {
01641           len = (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_len_db;
01642           hhcd->hc[ch_num & 0xFU].xfer_len_db = 0U; /* end of fill buffer */
01643         }
01644
01645         /* Write remaining data to Buffer0 */
01646         HCD_SET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum, 1U, (uint16_t)len);
01647
01648         USB_WritePMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff,
01649                      hhcd->hc[ch_num & 0xFU].pmaaddr1, (uint16_t)len);
01650       }
01651
01652       /* start a new transfer */
01653       HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_VALID);
01654     }
01655     else
01656     {
01657       /* Transfer complete state */
01658       hhcd->hc[ch_num & 0xFU].xfer_count  += data_xfr;
01659       hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
01660       hhcd->hc[ch_num & 0xFU].urb_state  = URB_DONE;
01661       hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U;
01662
01663       /* Close the channel */
01664       HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS);
01665     }
01666   }
01667 }
01668
01669
01670 /**
01671   * @brief  Handle Host Channel IN Double Buffer Bulk requests.
01672   * @param  hhcd HCD handle
01673   * @param  ch_num Channel number: This parameter can be a value from 1 to 15
01674   * @param  phy_chnum Physical Channel number [0..7]
01675   * @param  regvalue contain Snapshot of the EPCHn register when ISR is detected
01676   * @retval none
01677   */
01678 static void HCD_HC_IN_BulkDb(HCD_HandleTypeDef *hhcd,
01679                              uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue)
01680 {
01681   uint16_t received_bytes;
01682
01683   /* Read from Buffer 0 */
01684   if ((regvalue & USB_CH_DTOG_RX) != 0U)
01685   {
01686     received_bytes = (uint16_t)HCD_GET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum);
01687
01688     if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes)
01689     {
01690       hhcd->hc[ch_num & 0xFU].xfer_len = 0U;
01691     }
01692     else
01693     {
01694       hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes;
01695     }
01696
01697     /* Check if we Need to free the other buffer for the IP */
01698     if ((hhcd->hc[ch_num & 0xFU].xfer_len != 0U) && ((regvalue & USB_CH_DTOG_TX) != 0U))
01699     {
01700       /* Toggle SwBuff to Allow the IP to submit a new IN */
01701       HCD_FREE_USER_BUFFER(hhcd->Instance, phy_chnum, 0U);
01702     }
01703
01704     /* Read the byte from PMA to user Buffer(System Memory) */
01705     USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff,
01706                 hhcd->hc[ch_num & 0xFU].pmaaddr0, (uint16_t)received_bytes);
01707   }
01708   else
01709   {
01710     /* Read from Buffer 1 */
01711     received_bytes = (uint16_t) HCD_GET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum);
01712
01713     if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes)
01714     {
01715       hhcd->hc[ch_num & 0xFU].xfer_len = 0U;
01716     }
01717     else
01718     {
01719       hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes;
01720     }
01721
01722     /* Check if we Need to free the other buffer for the IP */
01723     if ((hhcd->hc[ch_num & 0xFU].xfer_len != 0U) && ((regvalue & USB_CH_DTOG_TX) == 0U))
01724     {
01725       /* Toggle SwBuff */
01726       HCD_FREE_USER_BUFFER(hhcd->Instance, phy_chnum, 0U);
01727     }
01728
01729     /* Read the byte from PMA to user Buffer(System Memory) */
01730     USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff,
01731                 hhcd->hc[ch_num & 0xFU].pmaaddr1, (uint16_t)received_bytes);
01732   }
01733
01734   /* update the global number of all received bytes */
01735   hhcd->hc[ch_num & 0xFU].xfer_count += received_bytes;
01736
01737   /* Transfer complete state */
01738   hhcd->hc[ch_num & 0xFU].state = HC_ACK;
01739   hhcd->hc[ch_num & 0xFU].ErrCnt = 0U;
01740
01741   if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) ||
01742       ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet)))
01743   {
01744     hhcd->hc[ch_num & 0xFU].urb_state  = URB_DONE;
01745     hhcd->hc[ch_num & 0xFU].state  = HC_XFRC;
01746
01747     /* disable channel */
01748     HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS);
01749   }
01750   else
01751   {
01752     hhcd->hc[ch_num & 0xFU].xfer_buff += received_bytes;
01753
01754     /* Reactivate the Channel Submit an other URB since the Transfer is not yet completed */
01755     HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_STRX);
01756   }
01757 }
01758 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01759
01760 /**
01761   * @brief  Handle Host Channel IN Isochronous Transaction
01762   * @param  hhcd HCD handle
01763   * @param  ch_num Channel number: This parameter can be a value from 1 to 15
01764   * @param  phy_chnum Physical Channel number [0..7]
01765   * @param  regvalue contain Snapshot of the EPCHn register when ISR is detected
01766   * @retval none
01767   */
01768 static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
01769                                  uint8_t phy_chnum, uint32_t regvalue)
01770 {
01771   /* Check if Double buffer isochronous */
01772   if ((regvalue & USB_CH_KIND) != 0U)
01773   {
01774     /* Get Data IN Packet */
01775     hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_RX_CNT(hhcd->Instance, phy_chnum);
01776     if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U)
01777     {
01778       USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff,
01779                   hhcd->hc[ch_num & 0xFU].pmaadress,
01780                   (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count);
01781
01782       hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE;
01783     }
01784   }
01785 #if (USE_USB_DOUBLE_BUFFER == 1U)
01786   else  /* double buffer isochronous */
01787   {
01788     /* Read from Buffer0 */
01789     if ((regvalue & USB_CH_DTOG_RX) != 0U)
01790     {
01791       /* Get number of Received byte in buffer0 */
01792       hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum);
01793
01794       if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U)
01795       {
01796         /* Read from Buffer0 */
01797         USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff,
01798                     hhcd->hc[ch_num & 0xFU].pmaaddr0,
01799                     (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count);
01800
01801         hhcd->hc[ch_num & 0xFU].urb_state  = URB_DONE;
01802       }
01803     }
01804     else
01805     {
01806       /* Get number of Received byte in buffer1 */
01807       hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum);
01808
01809       if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U)
01810       {
01811         /* Read from Buffer1 */
01812         USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff,
01813                     hhcd->hc[ch_num & 0xFU].pmaaddr1,
01814                     (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count);
01815
01816         hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE;
01817       }
01818     }
01819   }
01820 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01821
01822   /* Transfer complete state */
01823   hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
01824
01825   /* Clear VTRX */
01826   HCD_CLEAR_RX_CH_CTR(hhcd->Instance, phy_chnum);
01827 }
01828
01829 /**
01830   * @brief  Handle Host Channel IN interrupt requests.
01831   * @param  hhcd HCD handle
01832   * @param  ch_num Channel number
01833   *         This parameter can be a value from 1 to 15
01834   * @retval none
01835   */
01836 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
01837 {
01838   uint16_t received_bytes;
01839   uint8_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd);
01840
01841   /*Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */
01842   uint32_t ch_reg =  HCD_GET_CHANNEL(hhcd->Instance, phy_chnum);
01843
01844   /* Manage Correct Transaction */
01845   if ((ch_reg & USB_CH_ERRRX) == 0U)
01846   {
01847     /* Isochronous Channel */
01848     if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS)
01849     {
01850       HCD_HC_IN_ISO(hhcd, ch_num, phy_chnum, ch_reg);
01851     }
01852     else
01853     {
01854       /* manage ACK response single buffer */
01855       if (((ch_reg) & USB_CH_RX_STRX) == USB_CH_RX_ACK_SBUF)
01856       {
01857         /* Get Control Data OUT Packet */
01858         received_bytes = (uint16_t)HCD_GET_CH_RX_CNT(hhcd->Instance, phy_chnum);
01859
01860         /* Read the byte from PMA to user Buffer(System Memory) */
01861         USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff,
01862                     hhcd->hc[ch_num & 0xFU].pmaadress, (uint16_t)received_bytes);
01863
01864         /* update the global number of all received bytes */
01865         hhcd->hc[ch_num & 0xFU].xfer_count += received_bytes;
01866
01867         /* Transfer complete state */
01868         hhcd->hc[ch_num & 0xFU].state = HC_ACK;
01869         hhcd->hc[ch_num & 0xFU].ErrCnt = 0U;
01870
01871         if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes)
01872         {
01873           hhcd->hc[ch_num & 0xFU].xfer_len = 0U;
01874         }
01875         else
01876         {
01877           hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes;
01878         }
01879
01880         if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) ||
01881             ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet)))
01882         {
01883           hhcd->hc[ch_num & 0xFU].urb_state  = URB_DONE;
01884           hhcd->hc[ch_num & 0xFU].state  = HC_XFRC;
01885         }
01886         else
01887         {
01888           hhcd->hc[ch_num & 0xFU].xfer_buff += received_bytes;
01889
01890           /* Reactivate the Channel to Submit another URB since the Transfer is not yet completed */
01891           HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_STRX);
01892         }
01893
01894         if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) ||
01895             (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR))
01896         {
01897           hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U;
01898         }
01899       }
01900       /* manage NACK Response */
01901       else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK)
01902                && (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE))
01903       {
01904         hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY;
01905         hhcd->hc[ch_num & 0xFU].ErrCnt = 0U;
01906         hhcd->hc[ch_num & 0xFU].state = HC_NAK;
01907       }
01908       /* manage STALL Response */
01909       else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL)
01910       {
01911         (void)HAL_HCD_HC_Halt(hhcd, (uint8_t)ch_num);
01912         hhcd->hc[ch_num & 0xFU].state = HC_STALL;
01913         hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL;
01914
01915         /* Close the channel */
01916         HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS);
01917       }
01918 #if (USE_USB_DOUBLE_BUFFER == 1U)
01919       /* Double Buffer Management in case of Bulk Transaction */
01920       else  if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_ACK_DBUF)
01921                 && ((ch_reg & USB_CH_KIND) != 0U))
01922       {
01923         /* Bulk IN Double Buffer ISR */
01924         HCD_HC_IN_BulkDb(hhcd, ch_num, phy_chnum, ch_reg);
01925       }
01926 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01927       else
01928       {
01929         /*....*/
01930         /* not defined state: STRX=11 in single buffer no iso is not defined */
01931       }
01932
01933 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
01934       hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
01935 #else
01936       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
01937 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
01938
01939       /*Clear VTRX */
01940       HCD_CLEAR_RX_CH_CTR(hhcd->Instance, phy_chnum);
01941     }
01942   }
01943   else   /* Error detected during last transaction */
01944   {
01945     /* Set URB Error State */
01946     hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY;
01947     hhcd->hc[ch_num & 0xFU].ErrCnt++;
01948     hhcd->hc[ch_num & 0xFU].state = HC_XACTERR;
01949
01950     /* Clear VTTRX & ERR_RX */
01951     HCD_CLEAR_RX_CH_ERR(hhcd->Instance, phy_chnum);
01952
01953     /* Check Error number */
01954     if (hhcd->hc[ch_num & 0xFU].ErrCnt > 3U)
01955     {
01956       hhcd->hc[ch_num & 0xFU].urb_state = URB_ERROR;
01957       HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS);
01958
01959       /* Clear pending err_tx */
01960       HCD_CLEAR_RX_CH_ERR(hhcd->Instance, phy_chnum);
01961     }
01962
01963 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
01964     hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
01965 #else
01966     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
01967 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
01968   }
01969 }
01970
01971
01972 /**
01973   * @brief  Handle Host Channel OUT interrupt requests.
01974   * @param  hhcd  HCD handle
01975   * @param  chnum Channel number
01976   *         This parameter can be a value from 1 to 15
01977   * @retval none
01978   */
01979 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
01980 {
01981   uint16_t data_xfr;
01982   __IO uint32_t WregCh;
01983
01984   /* Get Physical Channel number */
01985   uint32_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd);
01986
01987   /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control &status */
01988   uint32_t ch_reg =  *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum);
01989
01990   /*------ Manage Correct Transaction ------*/
01991   if ((ch_reg & USB_CH_ERRTX) == 0U)
01992   {
01993     /* Handle Isochronous channel */
01994     if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS)
01995     {
01996       /* correct transaction */
01997       if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U)
01998       {
01999         /* Double buffer isochronous out */
02000         if ((ch_reg & USB_CH_KIND) != 0U)
02001         {
02002           HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U);
02003         }
02004 #if (USE_USB_DOUBLE_BUFFER == 1U)
02005         else /* double buffer isochronous out */
02006         {
02007           /* Odd Transaction */
02008           if ((ch_reg & USB_CH_DTOG_TX) != 0U)
02009           {
02010             HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U);
02011           }
02012           /* Even Transaction */
02013           else
02014           {
02015             HCD_SET_CH_RX_CNT(hhcd->Instance, phy_chnum, 0U);
02016           }
02017
02018           USB_DRD_SET_CHEP_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS);
02019         }
02020 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
02021
02022         /* Transfer complete state */
02023         hhcd->hc[chnum & 0xFU].state = HC_XFRC;
02024         hhcd->hc[chnum & 0xFU].urb_state = URB_DONE;
02025       }
02026
02027       /*Clear Correct Transfer */
02028       HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum);
02029
02030       /*TX COMPLETE*/
02031 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
02032       hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
02033 #else
02034       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
02035 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
02036
02037     }
02038     else /* Manage all Non Isochronous Transaction */
02039     {
02040       /* Check ACK response */
02041       if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_SBUF)
02042       {
02043         data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U);
02044
02045         if (hhcd->hc[chnum & 0xFU].xfer_len >= data_xfr)
02046         {
02047           hhcd->hc[chnum & 0xFU].xfer_len -= data_xfr;
02048         }
02049         else
02050         {
02051           hhcd->hc[chnum & 0xFU].xfer_len = 0U;
02052         }
02053
02054         /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */
02055         if (hhcd->hc[chnum & 0xFU].xfer_len != 0U)
02056         {
02057           /* manage multiple Xfer */
02058           hhcd->hc[chnum & 0xFU].xfer_buff += data_xfr;
02059           hhcd->hc[chnum & 0xFU].xfer_count  += data_xfr;
02060
02061           /* start a new transfer */
02062           (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[chnum & 0xFU]);
02063         }
02064         else
02065         {
02066           /* Transfer complete */
02067           hhcd->hc[chnum & 0xFU].xfer_count += data_xfr;
02068           hhcd->hc[chnum & 0xFU].state = HC_XFRC;
02069           hhcd->hc[chnum & 0xFU].urb_state = URB_DONE;
02070
02071           if ((hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_BULK) ||
02072               (hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_INTR))
02073           {
02074             hhcd->hc[chnum & 0xFU].toggle_out ^= 1U;
02075           }
02076         }
02077       }
02078       /* Check NACK Response */
02079       else if (((ch_reg & USB_CHEP_NAK) == USB_CHEP_NAK) ||
02080                ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_NAK))
02081       {
02082         /* Update Channel status */
02083         hhcd->hc[chnum & 0xFU].state = HC_NAK;
02084         hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY;
02085         hhcd->hc[chnum & 0xFU].ErrCnt = 0U;
02086
02087         /* Get Channel register value */
02088         WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum);
02089
02090         /*clear NAK status*/
02091         WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK;
02092
02093         /* Update channel register Value */
02094         HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, WregCh);
02095
02096         if (hhcd->hc[chnum & 0xFU].doublebuffer == 0U)
02097         {
02098 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
02099           hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
02100 #else
02101           HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
02102 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
02103         }
02104       }
02105       /* Check STALL Response */
02106       else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_STALL)
02107       {
02108         (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)chnum);
02109         hhcd->hc[chnum & 0xFU].state = HC_STALL;
02110         hhcd->hc[chnum & 0xFU].urb_state = URB_STALL;
02111       }
02112 #if (USE_USB_DOUBLE_BUFFER == 1U)
02113       /* Check double buffer ACK in case of bulk transaction */
02114       else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_DBUF)
02115       {
02116         /* Double buffer management Bulk Out */
02117         (void) HCD_HC_OUT_BulkDb(hhcd, chnum, (uint8_t)phy_chnum, ch_reg);
02118       }
02119 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
02120       else
02121       {
02122         /*...*/
02123       }
02124
02125       if ((ch_reg & USB_CH_TX_STTX) != USB_CH_TX_NAK)
02126       {
02127 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
02128         hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
02129 #else
02130         HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
02131 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
02132       }
02133
02134       HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum);
02135     }  /* end no isochronous */
02136   }
02137   /*------ Manage Transaction Error------*/
02138   else
02139   {
02140     hhcd->hc[chnum & 0xFU].ErrCnt++;
02141     if (hhcd->hc[chnum & 0xFU].ErrCnt > 3U)
02142     {
02143       HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS);
02144       hhcd->hc[chnum & 0xFU].urb_state = URB_ERROR;
02145     }
02146     else
02147     {
02148       hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY;
02149     }
02150
02151     hhcd->hc[chnum & 0xFU].state = HC_XACTERR;
02152
02153     /*Clear ERR_TX*/
02154     HCD_CLEAR_TX_CH_ERR(hhcd->Instance, phy_chnum);
02155
02156 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
02157     hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
02158 #else
02159     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
02160 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
02161   }
02162 }
02163
02164
02165 /**
02166   * @brief  Handle Host Port interrupt requests.
02167   * @param  hhcd  HCD handle
02168   * @retval None
02169   */
02170 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
02171 {
02172   uint32_t FnrReg = hhcd->Instance->FNR;
02173   uint32_t IstrReg = hhcd->Instance->ISTR;
02174
02175   /* SE0 detected USB Disconnected state */
02176   if ((FnrReg & (USB_FNR_RXDP | USB_FNR_RXDM)) == 0U)
02177   {
02178     /* Host Port State */
02179     hhcd->HostState = HCD_HCD_STATE_DISCONNECTED;
02180
02181     /* clear all allocated virtual channel */
02182     HAL_HCD_ClearPhyChannel(hhcd);
02183
02184     /* Reset the PMA current pointer */
02185     (void)HAL_HCD_PMAReset(hhcd);
02186
02187     /* reset Ep0 Pma allocation state */
02188     hhcd->ep0_PmaAllocState = 0U;
02189
02190     /* Disconnection Callback */
02191 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
02192     hhcd->DisconnectCallback(hhcd);
02193 #else
02194     HAL_HCD_Disconnect_Callback(hhcd);
02195 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
02196
02197     return;
02198   }
02199
02200   if ((hhcd->HostState == HCD_HCD_STATE_DISCONNECTED) != 0U)
02201   {
02202     /* J-state or K-state detected & LastState=Disconnected */
02203     if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U))
02204     {
02205       hhcd->HostState = HCD_HCD_STATE_CONNECTED;
02206
02207 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
02208       hhcd->ConnectCallback(hhcd);
02209 #else
02210       HAL_HCD_Connect_Callback(hhcd);
02211 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
02212     }
02213   }
02214   else
02215   {
02216     /* J-state or K-state detected & lastState=Connected: a Missed disconnection is detected */
02217     if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U))
02218     {
02219       /* Host Port State */
02220       hhcd->HostState = HCD_HCD_STATE_DISCONNECTED;
02221
02222       /* clear all allocated virtual channel */
02223       HAL_HCD_ClearPhyChannel(hhcd);
02224
02225       /* Reset the PMA current pointer */
02226       (void)HAL_HCD_PMAReset(hhcd);
02227
02228       /* reset Ep0 PMA allocation state */
02229       hhcd->ep0_PmaAllocState = 0U;
02230
02231       /* Disconnection Callback */
02232 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
02233       hhcd->DisconnectCallback(hhcd);
02234 #else
02235       HAL_HCD_Disconnect_Callback(hhcd);
02236 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
02237     }
02238   }
02239 }
02240
02241
02242 /**
02243   * @brief  Check if the ch_num are already reserved to a physical channel
02244   * @param  hhcd  HCD handle
02245   * @param  ch_num  Channel number
02246   *         This parameter can be a value from 1 to 15
02247   * @retval HAL status
02248   */
02249 static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
02250 {
02251   uint8_t idx;
02252
02253   /* Check if the logical channel are already opened  */
02254   for (idx = 0U; idx < hhcd->Init.Host_channels; idx++)
02255   {
02256     if ((((hhcd->phy_chin_state[idx] & 0xF0U) >> 4U) == ((uint16_t)ch_num + 1U)) &&
02257         (hhcd->phy_chin_state[idx] != 0U))
02258     {
02259       return (1U | (idx << 4U));
02260     }
02261
02262     if ((((hhcd->phy_chout_state[idx] & 0xF0U) >> 4U) == ((uint16_t)ch_num + 1U)) &&
02263         (hhcd->phy_chout_state[idx] != 0U))
02264     {
02265       return (1U | (idx << 4U));
02266     }
02267   }
02268
02269   return 0U;
02270 }
02271
02272
02273 /**
02274   * @brief  Get a Logical Channel number from  physical Channel
02275   * @param  hhcd  HCD handle
02276   * @param  phy_chnum
02277   *         This parameter can be a value from 1 to 15
02278   * @param  dir  Channel direction
02279   *         -0 OUT_Channel
02280   *         -1 IN_Channel
02281   * @retval HAL status
02282   */
02283 static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef *hhcd,
02284                                           uint8_t phy_chnum, uint8_t dir)
02285 {
02286   /* Out Channel Direction */
02287   if (dir == 0U)
02288   {
02289     if (((hhcd->phy_chout_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) != 0U)
02290     {
02291       return ((uint8_t)((hhcd->phy_chout_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) - 1U);
02292     }
02293     else
02294     {
02295       /* Channel not registered Error */
02296       return HCD_LOGICAL_CH_NOT_OPENED;
02297     }
02298   }
02299   /* IN Channel Direction */
02300   else
02301   {
02302     if (((hhcd->phy_chin_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) != 0U)
02303     {
02304       return ((uint8_t)((hhcd->phy_chin_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) - 1U);
02305     }
02306     else
02307     {
02308       /* Channel not registered Error */
02309       return HCD_LOGICAL_CH_NOT_OPENED;
02310     }
02311   }
02312 }
02313
02314
02315 /**
02316   * @brief  Get a free physical Channel number according to the direction
02317   * @param  hhcd HCD handle
02318   * @param  ch_num Channel number
02319   *         This parameter can be a value from 1 to 15
02320   * @param  epnum Endpoint number
02321   *          This parameter can be a value from 1 to 15
02322   * @param  ep_type Endpoint Type
02323   *          This parameter can be one of these values:
02324   *            EP_TYPE_CTRL Control type,
02325   *            EP_TYPE_ISOC Isochronous type,
02326   *            EP_TYPE_BULK Bulk type,
02327   *            EP_TYPE_INTR Interrupt type
02328   * @retval if physical channel is available return Phy_channel number
02329          else return HCD_FREE_CH_NOT_FOUND
02330   */
02331 static uint8_t HAL_HCD_Get_FreePhyChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
02332                                           uint8_t epnum, uint8_t ep_type)
02333 {
02334   uint8_t idx;
02335
02336   if ((epnum & 0x7FU) == 0U)
02337   {
02338     idx = 0U;
02339
02340     if (ch_num == 0U)
02341     {
02342       if (hhcd->phy_chin_state[idx] == 0U)
02343       {
02344         /* chin_state to store the ep_type to be used for the same channel in OUT direction
02345          * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */
02346         hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) |
02347                                     ((uint16_t)ep_type + 1U) |
02348                                     (((uint16_t)epnum & 0x0FU) << 8U);
02349       }
02350
02351       if (hhcd->phy_chout_state[idx] == 0U)
02352       {
02353         /* chout_state will store the ep_type to be used for the same channel in IN direction
02354          * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */
02355         hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) |
02356                                      ((uint16_t)ep_type + 1U) |
02357                                      (((uint16_t)epnum & 0x0FU) << 8U);
02358       }
02359     }
02360     else
02361     {
02362       if ((epnum & 0x80U) != 0U)
02363       {
02364         if (((hhcd->phy_chin_state[idx] & 0xF0U) >> 4U) != ((uint16_t)ch_num + 1U))
02365         {
02366           /* chin_state to store the ep_type to be used for the same channel in OUT direction
02367            * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */
02368           hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) |
02369                                       ((uint16_t)ep_type + 1U) |
02370                                       (((uint16_t)epnum & 0x0FU) << 8U);
02371         }
02372       }
02373       else
02374       {
02375         if (((hhcd->phy_chout_state[idx] & 0xF0U) >> 4U) != ((uint16_t)ch_num + 1U))
02376         {
02377           /* chout_state will store the ep_type to be used for the same channel in IN direction
02378            * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */
02379           hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) |
02380                                        ((uint16_t)ep_type + 1U) |
02381                                        (((uint16_t)epnum & 0x0FU) << 8U);
02382         }
02383       }
02384     }
02385
02386     return idx;
02387   }
02388
02389   if ((epnum & 0x80U) != 0U)
02390   {
02391     /* Find a new available physical in channel */
02392     for (idx = 1U; idx < hhcd->Init.Host_channels; idx++)
02393     {
02394       /* Check if the same epnum is allocated then allocate the same physical channel OUT for IN Logical Channel */
02395       if ((hhcd->phy_chin_state[idx] == 0U) &&
02396           ((((hhcd->phy_chout_state[idx] & 0x000FU) == ((uint16_t)ep_type + 1U)) &&
02397             (((hhcd->phy_chout_state[idx] & 0x0F00U) == ((uint16_t)epnum & 0x0FU)))) ||
02398            (hhcd->phy_chout_state[idx] == 0U)))
02399       {
02400         /* chin_state to store the ep_type to be used for the same channel in OUT direction
02401          * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */
02402         hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) |
02403                                     ((uint16_t)ep_type + 1U) |
02404                                     (((uint16_t)epnum & 0x0FU) << 8U);
02405
02406         return idx;
02407       }
02408     }
02409   }
02410   else
02411   {
02412     /* Find a new available physical out channel */
02413     for (idx = 1U; idx < hhcd->Init.Host_channels; idx++)
02414     {
02415       /* Check if the same epnum is allocated then allocate the same physical channel IN for OUT Logical Channel */
02416       if ((hhcd->phy_chout_state[idx] == 0U) &&
02417           ((((hhcd->phy_chin_state[idx] & 0x0FU) == ((uint16_t)ep_type + 1U)) &&
02418             ((hhcd->phy_chin_state[idx] & 0x0F00U) == ((uint16_t)epnum & 0x0FU))) ||
02419            (hhcd->phy_chin_state[idx] == 0U)))
02420       {
02421         /* chout_state will store the ep_type to be used for the same channel in IN direction
02422          * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */
02423         hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) |
02424                                      ((uint16_t)ep_type + 1U) |
02425                                      (((uint16_t)epnum & 0x0FU) << 8U);
02426
02427         return idx;
02428       }
02429     }
02430   }
02431
02432   /* in case of Error */
02433   return HCD_FREE_CH_NOT_FOUND;
02434 }
02435
02436 /**
02437   * @brief  Free All Channel allocation
02438   * @param  hhcd HCD handle
02439   * @retval HAL status
02440   */
02441 static void  HAL_HCD_ClearPhyChannel(HCD_HandleTypeDef *hhcd)
02442 {
02443   uint8_t idx;
02444
02445   for (idx = 0U; idx < hhcd->Init.Host_channels; idx++)
02446   {
02447     /*Reset channel allocation value */
02448     hhcd->phy_chout_state[idx] = 0U;
02449     hhcd->phy_chin_state[idx] = 0U;
02450   }
02451 }
02452
02453 /*----------------------  PMA Allocation Section --------------------- */
02454 /*
02455                 __col31________________col0__   Column-- >
02456           lin0 | entry31.|.......  | entry0 |   Line
02457                |---------|---------|--------|    |
02458           line1| entry63.|.......  | entry32|    |
02459                |---------|---------|--------|   \|/
02460                | entry127|.......  | entry64|
02461                |---------|---------|--------|
02462                | entry256|......   |entry128|
02463                 ----------------------------
02464            an allocation space of 64byte need 8 Free contiguous Entry in the Matrix
02465            - a Free Entry is a bit with 0 Value/  a busy entry is a bit with 1 value. */
02466
02467 /**
02468   * @brief  Fetch in the PMA_LockupTable free space of number of mps byte
02469   * @param  hhcd  Host instance
02470   * @param  mps  Channel Max Packet Size
02471   * @retval PMA_Address of the first free block containing mps byte
02472             0xFFFF in case of no space available
02473   */
02474 static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps)
02475 {
02476   uint32_t Entry;
02477   uint32_t FreeBlocks = 0U;
02478   uint8_t FirstFreeBlock_col = 0U;
02479   uint8_t FirstFreeBlock_line = 0U;
02480   uint8_t ColIndex;
02481   uint16_t NbrReqBlocks;
02482   uint16_t mps_t = mps;
02483
02484   /* since PMA buffer descriptor RXBD allocate address according to BLSIZE, BLSIZE=1==> mps>64
02485     allocation in PMA is done in 32Bytes each entry */
02486   if ((mps_t > 64U) && ((mps_t % 32U) != 0U))
02487   {
02488     /* Align the mps to 32byte block to match the allocation in PMA,
02489       check Definition of allocation buffer memory in usb user spec */
02490     mps_t = (uint16_t)(((mps_t / 32U) + 1U) * 32U);
02491   }
02492
02493   /* calculate the number of block(8byte) to allocate */
02494   NbrReqBlocks = mps_t / 8U;
02495
02496   /* check if we need remaining Block */
02497   if ((mps_t % 8U) != 0U)
02498   {
02499     NbrReqBlocks++;
02500   }
02501
02502   /* Look For NbrReqBlocks * Empty Block */
02503   for (uint8_t i = 0U; ((i < PMA_BLOCKS) && (FreeBlocks != NbrReqBlocks)); i++)
02504   {
02505     Entry = hhcd->PMALookupTable[i];
02506
02507     /* when parse is in progress, check the first col to look for a contiguous block */
02508     if ((FreeBlocks != 0U) && ((Entry & (uint32_t)1U) != 0U))
02509     {
02510       FreeBlocks = 0U;
02511     }
02512     uint8_t j = 0U;
02513     while ((j <= 31U) && (FreeBlocks != NbrReqBlocks))
02514     {
02515       /* check if block j is free */
02516       if ((Entry & ((uint32_t)1U << j)) == 0U)
02517       {
02518         if (FreeBlocks == 0U)
02519         {
02520           FirstFreeBlock_col = j;
02521           FirstFreeBlock_line = i;
02522           FreeBlocks++;
02523         }
02524         j++;
02525
02526         /* Parse Column PMALockTable */
02527         while ((j <= 31U) && ((Entry & ((uint32_t)1U << j)) == 0U) && (FreeBlocks < NbrReqBlocks))
02528         {
02529           FreeBlocks++;
02530           j++;
02531         }
02532
02533         /* Free contiguous Blocks not found */
02534         if (((FreeBlocks < NbrReqBlocks) && (j < 31U)) ||
02535             ((j == 31U) && ((Entry & ((uint32_t)1U << j)) != 0U)))
02536         {
02537           FreeBlocks = 0U;
02538         }
02539       }
02540       j++;
02541     } /* end for j */
02542   } /* end for i */
02543
02544   /* Free block found */
02545   if (FreeBlocks >= NbrReqBlocks)
02546   {
02547     ColIndex = FirstFreeBlock_col;
02548
02549     for (uint8_t i = FirstFreeBlock_line; ((i < PMA_BLOCKS) && (FreeBlocks > 0U)); i++)
02550     {
02551       for (uint8_t j = ColIndex; j <= 31U; j++)
02552       {
02553         hhcd->PMALookupTable[i] |= ((uint32_t)1U << j);
02554         if (--FreeBlocks == 0U)
02555         {
02556           break;
02557         }
02558       }
02559       ColIndex = 0U;
02560     }
02561
02562     return (uint16_t)((FirstFreeBlock_line * (uint16_t)256U) + (FirstFreeBlock_col * (uint16_t)8U));
02563   }
02564   else
02565   {
02566     return 0xFFFFU;
02567   }
02568 }
02569
02570 /**
02571   * @brief  Allocate PMA buffer for Channel
02572   *         This API will fetch a free space
02573   * @param  hhcd    Host instance
02574   * @param  ch_num  Channel number
02575   * @param  ch_kind endpoint Kind
02576   *                  USB_SNG_BUF Single Buffer used
02577   *                  USB_DBL_BUF Double Buffer used
02578   * @param  mps Channel Max Packet Size
02579   * @retval HAL status
02580   */
02581 HAL_StatusTypeDef  HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
02582                                    uint16_t ch_kind, uint16_t mps)
02583 {
02584   uint16_t pma_addr0;
02585 #if (USE_USB_DOUBLE_BUFFER == 1U)
02586   uint16_t pma_addr1; /* used for double buffer mode if enabled */
02587 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
02588
02589   /* Host Channel */
02590   HCD_HCTypeDef *hc = &(hhcd->hc[ch_num]);
02591
02592   /* Get a FreePMA Address */
02593   pma_addr0 = HAL_HCD_GetFreePMA(hhcd, mps);
02594
02595   /* if there is no free space to allocate */
02596   if (pma_addr0 == 0xFFFFU)
02597   {
02598     return HAL_ERROR;
02599   }
02600   else
02601   {
02602     /* Here we check if the endpoint is single or double Buffer */
02603     if (ch_kind == HCD_SNG_BUF)
02604     {
02605       /* Single Buffer */
02606       hc->doublebuffer = 0U;
02607
02608       if (hc->ep_num == 0U)
02609       {
02610         hhcd->ep0_PmaAllocState = ch_num;
02611         hhcd->ep0_PmaAllocState |= (1U << 8);
02612       }
02613
02614       /* Configure the PMA */
02615       if (hc->ch_dir == CH_IN_DIR)
02616       {
02617         hc->pmaaddr1 = pma_addr0;
02618         (USB_DRD_PMA_BUFF + hc->phy_ch_num)->RXBD = hc->pmaaddr1;
02619
02620         if (hc->ep_num == 0U)
02621         {
02622           hhcd->ep0_PmaAllocState |= (CH_IN_DIR << 4);
02623         }
02624       }
02625       else
02626       {
02627         hc->pmaaddr0 = pma_addr0;
02628         (USB_DRD_PMA_BUFF + hc->phy_ch_num)->TXBD = hc->pmaaddr0;
02629       }
02630
02631       /* Set the PmaAddress */
02632       hc->pmaadress = pma_addr0;
02633     }
02634 #if (USE_USB_DOUBLE_BUFFER == 1U)
02635     else /* USB_DBL_BUF */
02636     {
02637       /* Double Buffer Endpoint */
02638       hc->doublebuffer = 1U;
02639
02640       /* Get a FreePMA Address for buffer 2 */
02641       pma_addr1 = HAL_HCD_GetFreePMA(hhcd, mps);
02642
02643       if (pma_addr1 == 0xFFFFU)
02644       {
02645         /* Free the first buffer */
02646         (void)HAL_HCD_PMAFree(hhcd, pma_addr0, mps);
02647         return HAL_ERROR;
02648       }
02649       else
02650       {
02651         /* Configure the PMA */
02652         hc->pmaaddr0 = (uint16_t)(pma_addr0);
02653         hc->pmaaddr1 = (uint16_t)(pma_addr1);
02654
02655         /* Set Buffer0 pma address */
02656         (USB_DRD_PMA_BUFF + hc->phy_ch_num)->TXBD = pma_addr0;
02657
02658         /* Set Buffer1 pma address */
02659         (USB_DRD_PMA_BUFF + hc->phy_ch_num)->RXBD = pma_addr1;
02660
02661         /* Used for Bulk DB MPS < 64bytes */
02662         if (hc->ch_dir == CH_IN_DIR)
02663         {
02664           hc->pmaadress = hc->pmaaddr1;
02665         }
02666         else
02667         {
02668           hc->pmaadress = hc->pmaaddr0;
02669         }
02670       }
02671     }
02672 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
02673   }
02674
02675   return HAL_OK;
02676 }
02677
02678 /**
02679   * @brief  PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable
02680   * @param  hhcd  Host instance
02681   * @param  ch_num Channel number
02682   * @retval HAL status
02683   */
02684 HAL_StatusTypeDef  HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
02685 {
02686   HAL_StatusTypeDef status;
02687
02688 #if (USE_USB_DOUBLE_BUFFER == 1U)
02689   uint8_t Err = 0U;
02690 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
02691
02692   /* Host Channel */
02693   HCD_HCTypeDef *hc = &(hhcd->hc[ch_num]);
02694
02695   /* Single Buffer */
02696   if (hc->doublebuffer == 0U)
02697   {
02698     status = HAL_HCD_PMAFree(hhcd, hc->pmaadress, hc->max_packet);
02699   }
02700   else   /* Double buffer */
02701   {
02702 #if (USE_USB_DOUBLE_BUFFER == 1U)
02703     status = HAL_HCD_PMAFree(hhcd, hc->pmaaddr0, hc->max_packet);
02704     if (status != HAL_OK)
02705     {
02706       Err++;
02707     }
02708
02709     status = HAL_HCD_PMAFree(hhcd, hc->pmaaddr1, hc->max_packet);
02710     if (status != HAL_OK)
02711     {
02712       Err++;
02713     }
02714
02715     if (Err != 0U)
02716     {
02717       return HAL_ERROR;
02718     }
02719 #else
02720     status = HAL_ERROR;
02721 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
02722   }
02723
02724   return status;
02725 }
02726
02727
02728 /**
02729   * @brief  PMA Reset
02730   * @param  hhcd  Host instance
02731   * @retval HAL status
02732   */
02733 HAL_StatusTypeDef  HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd)
02734 {
02735   /* Reset All PMA Entry */
02736   for (uint8_t i = 0U; i < PMA_BLOCKS; i++)
02737   {
02738     hhcd->PMALookupTable[i] = 0U;
02739   }
02740
02741   /* Allocate a Space for buffer descriptor table depending on the Host channel number */
02742   for (uint8_t i = 0U; i < hhcd->Init.Host_channels; i++)
02743   {
02744     hhcd->PMALookupTable[0] |= ((uint32_t)1U << i);
02745   }
02746
02747   return HAL_OK;
02748 }
02749
02750 /**
02751   * @brief  PMA Free
02752   * @param  hhcd   Host instance
02753   * @param  pma_base PMA base offset stored in hhcd->hc.pmaaddr
02754   * @param  mps  Max Packet Size
02755   * @retval HAL status
02756   */
02757 static HAL_StatusTypeDef  HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps)
02758 {
02759   uint32_t block_nbr;
02760   uint8_t ColIndex;
02761   uint8_t LineIndex;
02762   uint16_t mps_t = mps;
02763
02764   /* since PMA buffer descriptor RXBD allocate address according to BLSIZE, BLSIZE=1==> mps>64
02765     allocation in PMA is done in 32Bytes each entry */
02766   if ((mps_t > 64U) && ((mps_t % 32U) != 0U))
02767   {
02768     /* Align the mps to 32byte block to match the allocation in PMA,
02769       check Definition of allocation buffer memory in usb user spec */
02770     mps_t = (uint16_t)(((mps_t / 32U) + 1U) * 32U);
02771   }
02772
02773   /* Calculate the number of needed block to Free */
02774   if ((mps_t / 8U) != 0U)
02775   {
02776     block_nbr = ((uint32_t)mps_t / 8U);
02777
02778     if ((mps_t % 8U) != 0U)
02779     {
02780       block_nbr++;
02781     }
02782   }
02783   else
02784   {
02785     block_nbr = 1U;
02786   }
02787
02788   /* Decode Col/Line of PMA_Base position in the PMA_LookupTable */
02789   if (pma_base > 256U)
02790   {
02791     LineIndex = (uint8_t)(pma_base / 256U);
02792     ColIndex = (uint8_t)((pma_base - ((uint32_t)LineIndex * 256U)) / 8U);
02793   }
02794   else
02795   {
02796     LineIndex = 0U;
02797     ColIndex = (uint8_t)(pma_base / 8U);
02798   }
02799
02800   /* Reset the corresponding bit in the lookupTable */
02801   for (uint8_t i = LineIndex; ((i < PMA_BLOCKS) && (block_nbr > 0U)); i++)
02802   {
02803     for (uint8_t j = ColIndex; j <= 31U; j++)
02804     {
02805       /* Check if the block is not already reserved or it was already closed */
02806       if ((hhcd->PMALookupTable[i] & ((uint32_t)1U << j)) == 0U)
02807       {
02808         return HAL_ERROR;
02809       }
02810       /* Free the reserved block by resetting the corresponding bit */
02811       hhcd->PMALookupTable[i] &= ~(1U << j);
02812
02813       if (--block_nbr == 0U)
02814       {
02815         break;
02816       }
02817     }
02818     ColIndex = 0U;
02819   }
02820
02821   return HAL_OK;
02822 }
02823
02824 /**
02825   * @}
02826   */
02827
02828 /**
02829   * @}
02830   */
02831 #endif /* defined (USB_DRD_FS) */
02832 #endif /* HAL_HCD_MODULE_ENABLED */
02833
02834 /**
02835   * @}
02836   */
02837
02838 /**
02839   * @}
02840   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_hcd.h Source File

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stm32g0xx_hal_hcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_hcd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HCD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_HCD_H
00021 #define STM32G0xx_HAL_HCD_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_ll_usb.h"
00029
00030 #if defined (USB_DRD_FS)
00031 /** @addtogroup STM32G0xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup HCD HCD
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup HCD_Exported_Types HCD Exported Types
00041   * @{
00042   */
00043
00044 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
00045   * @{
00046   */
00047 typedef enum
00048 {
00049   HAL_HCD_STATE_RESET    = 0x00,
00050   HAL_HCD_STATE_READY    = 0x01,
00051   HAL_HCD_STATE_ERROR    = 0x02,
00052   HAL_HCD_STATE_BUSY     = 0x03,
00053   HAL_HCD_STATE_TIMEOUT  = 0x04
00054 } HCD_StateTypeDef;
00055
00056 typedef USB_DRD_TypeDef   HCD_TypeDef;
00057 typedef USB_DRD_CfgTypeDef      HCD_InitTypeDef;
00058 typedef USB_DRD_HCTypeDef       HCD_HCTypeDef;
00059 typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef;
00060 typedef USB_DRD_HCStateTypeDef  HCD_HCStateTypeDef;
00061
00062 typedef enum
00063 {
00064   HCD_HCD_STATE_DISCONNECTED = 0x00U,
00065   HCD_HCD_STATE_CONNECTED    = 0x01U,
00066   HCD_HCD_STATE_RESETED      = 0x02U,
00067   HCD_HCD_STATE_RUN          = 0x03U,
00068   HCD_HCD_STATE_SUSPEND      = 0x04U,
00069   HCD_HCD_STATE_RESUME       = 0x05U,
00070 } HCD_HostStateTypeDef;
00071
00072 /* PMA lookup Table size depending on PMA Size
00073  * 8Bytes each Block 32Bit in each word
00074  */
00075 #define PMA_BLOCKS        ((USB_DRD_PMA_SIZE) / (8U * 32U))
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
00081   * @{
00082   */
00083 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00084 typedef struct __HCD_HandleTypeDef
00085 #else
00086 typedef struct
00087 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00088 {
00089   HCD_TypeDef               *Instance;  /*!< Register base address    */
00090   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
00091   HCD_HCTypeDef             hc[16];     /*!< Host channels parameters */
00092   uint32_t                  ep0_PmaAllocState;  /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */
00093   uint16_t                  phy_chin_state[8];  /*!< Physical Channel in State (Used/Free) */
00094   uint16_t                  phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/
00095   uint32_t                  PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */
00096   HCD_HostStateTypeDef      HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */
00097   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
00098   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
00099   __IO  uint32_t            ErrorCode;  /*!< HCD Error code           */
00100   void                      *pData;     /*!< Pointer Stack Handler    */
00101 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00102   void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd);                               /*!< USB OTG HCD SOF callback                */
00103   void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Connect callback            */
00104   void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd);                        /*!< USB OTG HCD Disconnect callback         */
00105   void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd);                       /*!< USB OTG HCD Port Enable callback        */
00106   void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd);                      /*!< USB OTG HCD Port Disable callback       */
00107   void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
00108                                       HCD_URBStateTypeDef urb_state);                   /*!< USB OTG HCD Host Channel Notify URB Change callback  */
00109
00110   void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Msp Init callback           */
00111   void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd);                         /*!< USB OTG HCD Msp DeInit callback         */
00112 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00113 } HCD_HandleTypeDef;
00114 /**
00115   * @}
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Exported constants --------------------------------------------------------*/
00123 /** @defgroup HCD_Exported_Constants HCD Exported Constants
00124   * @{
00125   */
00126
00127 /** @defgroup HCD_Speed HCD Speed
00128   * @{
00129   */
00130 #define HCD_SPEED_FULL               USBH_FSLS_SPEED
00131 #define HCD_SPEED_LOW                USBH_FSLS_SPEED
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup HCD_Device_Speed HCD Device Speed
00137   * @{
00138   */
00139 #define HCD_DEVICE_SPEED_HIGH               0U
00140 #define HCD_DEVICE_SPEED_FULL               1U
00141 #define HCD_DEVICE_SPEED_LOW                2U
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup HCD_PHY_Module HCD PHY Module
00147   * @{
00148   */
00149 #define HCD_PHY_ULPI                 1U
00150 #define HCD_PHY_EMBEDDED             2U
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup HCD_Error_Code_definition HCD Error Code definition
00156   * @brief  HCD Error Code definition
00157   * @{
00158   */
00159 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00160 #define  HAL_HCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
00161 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /**
00168   * @}
00169   */
00170
00171 /* Exported macro ------------------------------------------------------------*/
00172 /** @defgroup HCD_Exported_Macros HCD Exported Macros
00173   *  @brief macros to handle interrupts and specific clock configurations
00174   * @{
00175   */
00176 #define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
00177 #define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
00178
00179 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance)\
00180                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
00181 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
00182 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
00183
00184 #define __HAL_HCD_GET_CHNUM(__HANDLE__)                    (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)
00185 #define __HAL_HCD_GET_CHDIR(__HANDLE__)                    (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported functions --------------------------------------------------------*/
00191 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
00192   * @{
00193   */
00194
00195 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00196   * @{
00197   */
00198 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
00199 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
00200 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
00201                                   uint8_t epnum, uint8_t dev_address,
00202                                   uint8_t speed, uint8_t ep_type, uint16_t mps);
00203
00204 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
00205 HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
00206 void              HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
00207 void              HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
00208
00209 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
00210 /** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
00211   * @brief  HAL USB OTG HCD Callback ID enumeration definition
00212   * @{
00213   */
00214 typedef enum
00215 {
00216   HAL_HCD_SOF_CB_ID            = 0x01,       /*!< USB HCD SOF callback ID           */
00217   HAL_HCD_CONNECT_CB_ID        = 0x02,       /*!< USB HCD Connect callback ID       */
00218   HAL_HCD_DISCONNECT_CB_ID     = 0x03,       /*!< USB HCD Disconnect callback ID    */
00219   HAL_HCD_PORT_ENABLED_CB_ID   = 0x04,       /*!< USB HCD Port Enable callback ID   */
00220   HAL_HCD_PORT_DISABLED_CB_ID  = 0x05,       /*!< USB HCD Port Disable callback ID  */
00221
00222   HAL_HCD_MSPINIT_CB_ID        = 0x06,       /*!< USB HCD MspInit callback ID       */
00223   HAL_HCD_MSPDEINIT_CB_ID      = 0x07        /*!< USB HCD MspDeInit callback ID     */
00224
00225 } HAL_HCD_CallbackIDTypeDef;
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
00231   * @brief  HAL USB OTG HCD Callback pointer definition
00232   * @{
00233   */
00234
00235 typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd);                   /*!< pointer to a common USB OTG HCD callback function  */
00236 typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
00237                                                        uint8_t epnum,
00238                                                        HCD_URBStateTypeDef urb_state);   /*!< pointer to USB OTG HCD host channel  callback */
00239 /**
00240   * @}
00241   */
00242
00243 HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
00244                                            HAL_HCD_CallbackIDTypeDef CallbackID,
00245                                            pHCD_CallbackTypeDef pCallback);
00246
00247 HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
00248                                              HAL_HCD_CallbackIDTypeDef CallbackID);
00249
00250 HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
00251                                                              pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
00252
00253 HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
00254 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
00255 /**
00256   * @}
00257   */
00258
00259 /* I/O operation functions  ***************************************************/
00260 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
00261   * @{
00262   */
00263 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
00264                                            uint8_t direction, uint8_t ep_type,
00265                                            uint8_t token, uint8_t *pbuff,
00266                                            uint16_t length, uint8_t do_ping);
00267
00268 /* Non-Blocking mode: Interrupt */
00269 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
00270 void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
00271 void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
00272 void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
00273 void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
00274 void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
00275 void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd);
00276 void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd);
00277 void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
00278                                          HCD_URBStateTypeDef urb_state);
00279 /**
00280   * @}
00281   */
00282
00283 /* Peripheral Control functions  **********************************************/
00284 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
00285   * @{
00286   */
00287 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
00288 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
00289 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
00290 HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd);
00291 HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd);
00292 HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd);
00293 /**
00294   * @}
00295   */
00296
00297 /* Peripheral State functions  ************************************************/
00298 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
00299   * @{
00300   */
00301 HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
00302 HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00303 HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00304 uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00305 uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
00306 uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
00307
00308 /* PMA Allocation functions  **********************************************/
00309 /** @addtogroup PMA Allocation
00310   * @{
00311   */
00312 HAL_StatusTypeDef  HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
00313                                    uint16_t ch_kind, uint16_t mps);
00314
00315 HAL_StatusTypeDef  HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
00316 HAL_StatusTypeDef  HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
00317
00318 /**
00319   * @}
00320   */
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /* Private macros ------------------------------------------------------------*/
00330 /** @defgroup HCD_Private_Macros HCD Private Macros
00331   * @{
00332   */
00333 /** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel
00334   * @{
00335   */
00336 #define HCD_LOGICAL_CH_NOT_OPENED             0xFFU
00337 #define HCD_FREE_CH_NOT_FOUND                 0xFFU
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup HCD_ENDP_Kind HCD Endpoint Kind
00343   * @{
00344   */
00345 #define HCD_SNG_BUF                            0U
00346 #define HCD_DBL_BUF                            1U
00347 /**
00348   * @}
00349   */
00350
00351 /* Set Channel */
00352 #define HCD_SET_CHANNEL                        USB_DRD_SET_CHEP
00353
00354 /* Get Channel Register */
00355 #define HCD_GET_CHANNEL                        USB_DRD_GET_CHEP
00356
00357
00358 /**
00359   * @brief free buffer used from the application realizing it to the line
00360   *         toggles bit SW_BUF in the double buffered endpoint register
00361   * @param USBx USB device.
00362   * @param   bChNum, bDir
00363   * @retval None
00364   */
00365 #define HCD_FREE_USER_BUFFER                   USB_DRD_FREE_USER_BUFFER
00366
00367 /**
00368   * @brief Set the Setup bit in the corresponding channel, when a Setup
00369      transaction is needed.
00370   * @param USBx USB device.
00371   * @param   bChNum
00372   * @retval None
00373   */
00374 #define HAC_SET_CH_TX_SETUP                    USB_DRD_CHEP_TX_SETUP
00375
00376 /**
00377   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
00378   * @param  USBx USB peripheral instance register address.
00379   * @param  bChNum Endpoint Number.
00380   * @param  wState new state
00381   * @retval None
00382   */
00383 #define HCD_SET_CH_TX_STATUS                   USB_DRD_SET_CHEP_TX_STATUS
00384
00385 /**
00386   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
00387   * @param  USBx USB peripheral instance register address.
00388   * @param  bChNum Endpoint Number.
00389   * @param  wState new state
00390   * @retval None
00391   */
00392 #define HCD_SET_CH_RX_STATUS                   USB_DRD_SET_CHEP_RX_STATUS
00393 /**
00394   * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
00395   *         /STAT_RX[1:0])
00396   * @param  USBx USB peripheral instance register address.
00397   * @param  bChNum Endpoint Number.
00398   * @retval status
00399   */
00400 #define HCD_GET_CH_TX_STATUS                   USB_DRD_GET_CHEP_TX_STATUS
00401 #define HCD_GET_CH_RX_STATUS                   USB_DRD_GET_CHEP_RX_STATUS
00402 /**
00403   * @brief  Sets/clears CH_KIND bit in the Channel register.
00404   * @param  USBx USB peripheral instance register address.
00405   * @param  bChNum Endpoint Number.
00406   * @retval None
00407   */
00408 #define HCD_SET_CH_KIND                        USB_DRD_SET_CH_KIND
00409 #define HCD_CLEAR_CH_KIND                      USB_DRD_CLEAR_CH_KIND
00410 #define HCD_SET_BULK_CH_DBUF                   HCD_SET_CH_KIND
00411 #define HCD_CLEAR_BULK_CH_DBUF                 HCD_CLEAR_CH_KIND
00412
00413 /**
00414   * @brief  Clears bit ERR_RX in the Channel register
00415   * @param  USBx USB peripheral instance register address.
00416   * @param  bChNum Endpoint Number.
00417   * @retval None
00418   */
00419 #define HCD_CLEAR_RX_CH_ERR                    USB_DRD_CLEAR_CHEP_RX_ERR
00420
00421 /**
00422   * @brief  Clears bit ERR_TX in the Channel register
00423   * @param  USBx USB peripheral instance register address.
00424   * @param  bChNum Endpoint Number.
00425   * @retval None
00426   */
00427 #define HCD_CLEAR_TX_CH_ERR                    USB_DRD_CLEAR_CHEP_TX_ERR
00428 /**
00429   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
00430   * @param  USBx USB peripheral instance register address.
00431   * @param  bChNum Endpoint Number.
00432   * @retval None
00433   */
00434 #define HCD_CLEAR_RX_CH_CTR                    USB_DRD_CLEAR_RX_CHEP_CTR
00435 #define HCD_CLEAR_TX_CH_CTR                    USB_DRD_CLEAR_TX_CHEP_CTR
00436
00437 /**
00438   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
00439   * @param  USBx USB peripheral instance register address.
00440   * @param  bChNum Endpoint Number.
00441   * @retval None
00442   */
00443 #define HCD_RX_DTOG                            USB_DRD_RX_DTOG
00444 #define HCD_TX_DTOG                            USB_DRD_TX_DTOG
00445 /**
00446   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
00447   * @param  USBx USB peripheral instance register address.
00448   * @param  bChNum Endpoint Number.
00449   * @retval None
00450   */
00451 #define HCD_CLEAR_RX_DTOG                      USB_DRD_CLEAR_RX_DTOG
00452 #define HCD_CLEAR_TX_DTOG                      USB_DRD_CLEAR_TX_DTOG
00453
00454 /**
00455   * @brief  sets counter for the tx/rx buffer.
00456   * @param  USBx USB peripheral instance register address.
00457   * @param  bChNum Endpoint Number.
00458   * @param  wCount Counter value.
00459   * @retval None
00460   */
00461 #define HCD_SET_CH_TX_CNT                      USB_DRD_SET_CHEP_TX_CNT
00462 #define HCD_SET_CH_RX_CNT                      USB_DRD_SET_CHEP_RX_CNT
00463
00464 /**
00465   * @brief  gets counter of the tx buffer.
00466   * @param  USBx USB peripheral instance register address.
00467   * @param  bChNum channel Number.
00468   * @retval Counter value
00469   */
00470 #define HCD_GET_CH_TX_CNT                      USB_DRD_GET_CHEP_TX_CNT
00471
00472 /**
00473   * @brief  gets counter of the rx buffer.
00474   * @param  Instance USB peripheral instance register address.
00475   * @param  bChNum channel Number.
00476   * @retval Counter value
00477   */
00478 __STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
00479 {
00480   UNUSED(Instance);
00481   __IO uint32_t count = 10U;
00482
00483   /* WA: few cycles for RX PMA descriptor to update */
00484   while (count > 0U)
00485   {
00486     count--;
00487   }
00488
00489   return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum));
00490 }
00491
00492 /**
00493   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00494   * @param  USBx USB peripheral instance register address.
00495   * @param  bChNum Endpoint Number.
00496   * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
00497   *         EP_DBUF_IN  = IN
00498   * @param  wCount: Counter value
00499   * @retval None
00500   */
00501 #define HCD_SET_CH_DBUF0_CNT                   USB_DRD_SET_CHEP_DBUF0_CNT
00502 #define HCD_SET_CH_DBUF1_CNT                   USB_DRD_SET_CHEP_DBUF1_CNT
00503 #define HCD_SET_CH_DBUF_CNT                    USB_DRD_SET_CHEP_DBUF_CNT
00504
00505
00506 /**
00507   * @brief  gets counter of the rx buffer0.
00508   * @param  Instance USB peripheral instance register address.
00509   * @param  bChNum channel Number.
00510   * @retval Counter value
00511   */
00512 __STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
00513 {
00514   UNUSED(Instance);
00515   __IO uint32_t count = 10U;
00516
00517   /* WA: few cycles for RX PMA descriptor to update */
00518   while (count > 0U)
00519   {
00520     count--;
00521   }
00522
00523   return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum));
00524 }
00525
00526 /**
00527   * @brief  gets counter of the rx buffer1.
00528   * @param  Instance USB peripheral instance register address.
00529   * @param  bChNum channel Number.
00530   * @retval Counter value
00531   */
00532 __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
00533 {
00534   UNUSED(Instance);
00535   __IO uint32_t count = 10U;
00536
00537   /* WA: few cycles for RX PMA descriptor to update */
00538   while (count > 0U)
00539   {
00540     count--;
00541   }
00542
00543   return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum));
00544 }
00545
00546 /**
00547   * @}
00548   */
00549 /* Private functions prototypes ----------------------------------------------*/
00550
00551 /**
00552   * @}
00553   */
00554 /**
00555   * @}
00556   */
00557 #endif /* defined (USB_DRD_FS) */
00558
00559 #ifdef __cplusplus
00560 }
00561 #endif
00562
00563 #endif /* STM32G0xx_HAL_HCD_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2c.c Source File

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stm32g0xx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                         ##### How to use this driver #####
00026   ==============================================================================
00027     [..]
00028     The I2C HAL driver can be used as follows:
00029
00030     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00031         I2C_HandleTypeDef  hi2c;
00032
00033     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
00034         (##) Enable the I2Cx interface clock
00035         (##) I2C pins configuration
00036             (+++) Enable the clock for the I2C GPIOs
00037             (+++) Configure I2C pins as alternate function open-drain
00038         (##) NVIC configuration if you need to use interrupt process
00039             (+++) Configure the I2Cx interrupt priority
00040             (+++) Enable the NVIC I2C IRQ Channel
00041         (##) DMA Configuration if you need to use DMA process
00042             (+++) Declare a DMA_HandleTypeDef handle structure for
00043                   the transmit or receive channel
00044             (+++) Enable the DMAx interface clock using
00045             (+++) Configure the DMA handle parameters
00046             (+++) Configure the DMA Tx or Rx channel
00047             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00048             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00049                   the DMA Tx or Rx channel
00050
00051     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00052         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00053
00054     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00055         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
00056
00057     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00058
00059     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00060
00061     *** Polling mode IO operation ***
00062     =================================
00063     [..]
00064       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00065       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00066       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00067       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00068
00069     *** Polling mode IO MEM operation ***
00070     =====================================
00071     [..]
00072       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00073       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00074
00075
00076     *** Interrupt mode IO operation ***
00077     ===================================
00078     [..]
00079       (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
00080       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
00081            add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00082       (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
00083       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
00084            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00085       (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
00086       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
00087            add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00088       (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
00089       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
00090            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00091       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00092            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00093       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00094       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
00095            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00096       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00097            This action will inform Master to generate a Stop condition to discard the communication.
00098
00099
00100     *** Interrupt mode or DMA mode IO sequential operation ***
00101     ==========================================================
00102     [..]
00103       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00104           when a direction change during transfer
00105     [..]
00106       (+) A specific option field manage the different steps of a sequential transfer
00107       (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
00108       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
00109            no sequential mode
00110       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00111                             and data to transfer without a final stop condition
00112       (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
00113                             start condition, address and data to transfer without a final stop condition,
00114                             an then permit a call the same master sequential interface several times
00115                             (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
00116                             or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
00117       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00118                             and with new data to transfer if the direction change or manage only the new data to
00119                             transfer
00120                             if no direction change and without a final stop condition in both cases
00121       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00122                             and with new data to transfer if the direction change or manage only the new data to
00123                             transfer
00124                             if no direction change and with a final stop condition in both cases
00125       (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
00126                             after several call of the same master sequential interface several times
00127                             (link with option I2C_FIRST_AND_NEXT_FRAME).
00128                             Usage can, transfer several bytes one by one using
00129                               HAL_I2C_Master_Seq_Transmit_IT
00130                               or HAL_I2C_Master_Seq_Receive_IT
00131                               or HAL_I2C_Master_Seq_Transmit_DMA
00132                               or HAL_I2C_Master_Seq_Receive_DMA
00133                               with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
00134                              Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
00135                               Receive sequence permit to call the opposite interface Receive or Transmit
00136                               without stopping the communication and so generate a restart condition.
00137       (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
00138                             each call of the same master sequential
00139                             interface.
00140                             Usage can, transfer several bytes one by one with a restart with slave address between
00141                             each bytes using
00142                               HAL_I2C_Master_Seq_Transmit_IT
00143                               or HAL_I2C_Master_Seq_Receive_IT
00144                               or HAL_I2C_Master_Seq_Transmit_DMA
00145                               or HAL_I2C_Master_Seq_Receive_DMA
00146                               with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
00147                             Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
00148                             generation of STOP condition.
00149
00150       (+) Different sequential I2C interfaces are listed below:
00151       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
00152             HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
00153       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
00154             users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00155       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
00156             HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
00157       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
00158            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00159       (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00160       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
00161            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00162       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
00163             HAL_I2C_DisableListen_IT()
00164       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
00165            add their own code to check the Address Match Code and the transmission direction request by master
00166            (Write/Read).
00167       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
00168           add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
00169       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
00170             HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
00171       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
00172             users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00173       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
00174             HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
00175       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
00176            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00177       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00178            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00179       (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00180            This action will inform Master to generate a Stop condition to discard the communication.
00181
00182     *** Interrupt mode IO MEM operation ***
00183     =======================================
00184     [..]
00185       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
00186           HAL_I2C_Mem_Write_IT()
00187       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
00188            add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00189       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
00190           HAL_I2C_Mem_Read_IT()
00191       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
00192            add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00193       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00194            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00195
00196     *** DMA mode IO operation ***
00197     ==============================
00198     [..]
00199       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
00200           HAL_I2C_Master_Transmit_DMA()
00201       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
00202            add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00203       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
00204           HAL_I2C_Master_Receive_DMA()
00205       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
00206            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00207       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
00208           HAL_I2C_Slave_Transmit_DMA()
00209       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
00210            add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00211       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
00212           HAL_I2C_Slave_Receive_DMA()
00213       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
00214            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00215       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00216            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00217       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00218       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
00219            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00220       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00221            This action will inform Master to generate a Stop condition to discard the communication.
00222
00223     *** DMA mode IO MEM operation ***
00224     =================================
00225     [..]
00226       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
00227           HAL_I2C_Mem_Write_DMA()
00228       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
00229            add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00230       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
00231           HAL_I2C_Mem_Read_DMA()
00232       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
00233            add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00234       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
00235            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
00236
00237
00238      *** I2C HAL driver macros list ***
00239      ==================================
00240      [..]
00241        Below the list of most used macros in I2C HAL driver.
00242
00243       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00244       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00245       (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
00246       (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
00247       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00248       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00249       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00250
00251      *** Callback registration ***
00252      =============================================
00253     [..]
00254      The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
00255      allows the user to configure dynamically the driver callbacks.
00256      Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
00257      to register an interrupt callback.
00258     [..]
00259      Function HAL_I2C_RegisterCallback() allows to register following callbacks:
00260        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00261        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00262        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00263        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00264        (+) ListenCpltCallback   : callback for end of listen mode.
00265        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
00266        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
00267        (+) ErrorCallback        : callback for error detection.
00268        (+) AbortCpltCallback    : callback for abort completion process.
00269        (+) MspInitCallback      : callback for Msp Init.
00270        (+) MspDeInitCallback    : callback for Msp DeInit.
00271      This function takes as parameters the HAL peripheral handle, the Callback ID
00272      and a pointer to the user callback function.
00273     [..]
00274      For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
00275     [..]
00276      Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
00277      weak function.
00278      HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
00279      and the Callback ID.
00280      This function allows to reset following callbacks:
00281        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00282        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00283        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00284        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00285        (+) ListenCpltCallback   : callback for end of listen mode.
00286        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
00287        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
00288        (+) ErrorCallback        : callback for error detection.
00289        (+) AbortCpltCallback    : callback for abort completion process.
00290        (+) MspInitCallback      : callback for Msp Init.
00291        (+) MspDeInitCallback    : callback for Msp DeInit.
00292     [..]
00293      For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
00294     [..]
00295      By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
00296      all callbacks are set to the corresponding weak functions:
00297      examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
00298      Exception done for MspInit and MspDeInit functions that are
00299      reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
00300      these callbacks are null (not registered beforehand).
00301      If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
00302      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00303     [..]
00304      Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
00305      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00306      in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
00307      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00308      Then, the user first registers the MspInit/MspDeInit user callbacks
00309      using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
00310      or HAL_I2C_Init() function.
00311     [..]
00312      When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
00313      not defined, the callback registration feature is not available and all callbacks
00314      are set to the corresponding weak functions.
00315
00316      [..]
00317        (@) You can refer to the I2C HAL driver header file for more useful macros
00318
00319   @endverbatim
00320   */
00321
00322 /* Includes ------------------------------------------------------------------*/
00323 #include "stm32g0xx_hal.h"
00324
00325 /** @addtogroup STM32G0xx_HAL_Driver
00326   * @{
00327   */
00328
00329 /** @defgroup I2C I2C
00330   * @brief I2C HAL module driver
00331   * @{
00332   */
00333
00334 #ifdef HAL_I2C_MODULE_ENABLED
00335
00336 /* Private typedef -----------------------------------------------------------*/
00337 /* Private define ------------------------------------------------------------*/
00338
00339 /** @defgroup I2C_Private_Define I2C Private Define
00340   * @{
00341   */
00342 #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
00343 #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
00344 #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
00345 #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
00346 #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
00347 #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
00348 #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
00349 #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
00350 #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
00351 #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
00352
00353 #define MAX_NBYTE_SIZE      255U
00354 #define SLAVE_ADDR_SHIFT     7U
00355 #define SLAVE_ADDR_MSK       0x06U
00356
00357 /* Private define for @ref PreviousState usage */
00358 #define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
00359                                                          (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
00360                                               (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
00361 /*!< Mask State define, keep only RX and TX bits */
00362 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
00363 /*!< Default Value */
00364 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
00365                                               (uint32_t)HAL_I2C_MODE_MASTER))
00366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00367 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
00368                                               (uint32_t)HAL_I2C_MODE_MASTER))
00369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00370 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
00371                                               (uint32_t)HAL_I2C_MODE_SLAVE))
00372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
00373 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
00374                                               (uint32_t)HAL_I2C_MODE_SLAVE))
00375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00376 #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
00377                                               (uint32_t)HAL_I2C_MODE_MEM))
00378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00379 #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
00380                                               (uint32_t)HAL_I2C_MODE_MEM))
00381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00382
00383
00384 /* Private define to centralize the enable/disable of Interrupts */
00385 #define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
00386                                                          @ref I2C_XFER_LISTEN_IT */
00387 #define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
00388                                                          @ref I2C_XFER_LISTEN_IT */
00389 #define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
00390                                                          and @ref I2C_XFER_RX_IT */
00391
00392 #define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of global Error
00393                                                          and NACK treatment */
00394 #define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evenement */
00395 #define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of NBYTE */
00396
00397 /* Private define Sequential Transfer Options default/reset value */
00398 #define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
00399 /**
00400   * @}
00401   */
00402
00403 /* Private macro -------------------------------------------------------------*/
00404 /* Macro to get remaining data to transfer on DMA side */
00405 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     __HAL_DMA_GET_COUNTER(__HANDLE__)
00406
00407 /* Private variables ---------------------------------------------------------*/
00408 /* Private function prototypes -----------------------------------------------*/
00409
00410 /** @defgroup I2C_Private_Functions I2C Private Functions
00411   * @{
00412   */
00413 /* Private functions to handle DMA transfer */
00414 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00415 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00416 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00417 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00418 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00419 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00420
00421 /* Private functions to handle IT transfer */
00422 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00423 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
00424 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
00425 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00426 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00427 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00428 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
00429
00430 /* Private functions to handle IT transfer */
00431 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
00432                                                 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
00433                                                 uint32_t Tickstart);
00434 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
00435                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
00436                                                uint32_t Tickstart);
00437
00438 /* Private functions for I2C transfer IRQ handler */
00439 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00440                                            uint32_t ITSources);
00441 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00442                                         uint32_t ITSources);
00443 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00444                                           uint32_t ITSources);
00445 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00446                                             uint32_t ITSources);
00447 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00448                                          uint32_t ITSources);
00449 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
00450                                            uint32_t ITSources);
00451
00452 /* Private functions to handle flags during polling transfer */
00453 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
00454                                                     uint32_t Timeout, uint32_t Tickstart);
00455 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
00456                                                         uint32_t Tickstart);
00457 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
00458                                                         uint32_t Tickstart);
00459 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
00460                                                         uint32_t Tickstart);
00461 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
00462                                              uint32_t Tickstart);
00463
00464 /* Private functions to centralize the enable/disable of Interrupts */
00465 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00466 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00467
00468 /* Private function to treat different error callback */
00469 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
00470
00471 /* Private function to flush TXDR register */
00472 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
00473
00474 /* Private function to handle  start, restart or stop a transfer */
00475 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
00476                                uint32_t Request);
00477
00478 /* Private function to Convert Specific options */
00479 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
00480 /**
00481   * @}
00482   */
00483
00484 /* Exported functions --------------------------------------------------------*/
00485
00486 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00487   * @{
00488   */
00489
00490 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00491   *  @brief    Initialization and Configuration functions
00492   *
00493 @verbatim
00494  ===============================================================================
00495               ##### Initialization and de-initialization functions #####
00496  ===============================================================================
00497     [..]  This subsection provides a set of functions allowing to initialize and
00498           deinitialize the I2Cx peripheral:
00499
00500       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00501           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00502
00503       (+) Call the function HAL_I2C_Init() to configure the selected device with
00504           the selected configuration:
00505         (++) Clock Timing
00506         (++) Own Address 1
00507         (++) Addressing mode (Master, Slave)
00508         (++) Dual Addressing mode
00509         (++) Own Address 2
00510         (++) Own Address 2 Mask
00511         (++) General call mode
00512         (++) Nostretch mode
00513
00514       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00515           of the selected I2Cx peripheral.
00516
00517 @endverbatim
00518   * @{
00519   */
00520
00521 /**
00522   * @brief  Initializes the I2C according to the specified parameters
00523   *         in the I2C_InitTypeDef and initialize the associated handle.
00524   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00525   *                the configuration information for the specified I2C.
00526   * @retval HAL status
00527   */
00528 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00529 {
00530   /* Check the I2C handle allocation */
00531   if (hi2c == NULL)
00532   {
00533     return HAL_ERROR;
00534   }
00535
00536   /* Check the parameters */
00537   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00538   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00539   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00540   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00541   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00542   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00543   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00544   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00545
00546   if (hi2c->State == HAL_I2C_STATE_RESET)
00547   {
00548     /* Allocate lock resource and initialize it */
00549     hi2c->Lock = HAL_UNLOCKED;
00550
00551 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00552     /* Init the I2C Callback settings */
00553     hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00554     hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00555     hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
00556     hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
00557     hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
00558     hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
00559     hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
00560     hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
00561     hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00562     hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
00563
00564     if (hi2c->MspInitCallback == NULL)
00565     {
00566       hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
00567     }
00568
00569     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00570     hi2c->MspInitCallback(hi2c);
00571 #else
00572     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00573     HAL_I2C_MspInit(hi2c);
00574 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00575   }
00576
00577   hi2c->State = HAL_I2C_STATE_BUSY;
00578
00579   /* Disable the selected I2C peripheral */
00580   __HAL_I2C_DISABLE(hi2c);
00581
00582   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00583   /* Configure I2Cx: Frequency range */
00584   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00585
00586   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00587   /* Disable Own Address1 before set the Own Address1 configuration */
00588   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00589
00590   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00591   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00592   {
00593     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00594   }
00595   else /* I2C_ADDRESSINGMODE_10BIT */
00596   {
00597     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00598   }
00599
00600   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00601   /* Configure I2Cx: Addressing Master mode */
00602   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00603   {
00604     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
00605   }
00606   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00607   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00608
00609   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00610   /* Disable Own Address2 before set the Own Address2 configuration */
00611   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
00612
00613   /* Configure I2Cx: Dual mode and Own Address2 */
00614   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
00615                           (hi2c->Init.OwnAddress2Masks << 8));
00616
00617   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00618   /* Configure I2Cx: Generalcall and NoStretch mode */
00619   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00620
00621   /* Enable the selected I2C peripheral */
00622   __HAL_I2C_ENABLE(hi2c);
00623
00624   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00625   hi2c->State = HAL_I2C_STATE_READY;
00626   hi2c->PreviousState = I2C_STATE_NONE;
00627   hi2c->Mode = HAL_I2C_MODE_NONE;
00628
00629   return HAL_OK;
00630 }
00631
00632 /**
00633   * @brief  DeInitialize the I2C peripheral.
00634   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00635   *                the configuration information for the specified I2C.
00636   * @retval HAL status
00637   */
00638 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00639 {
00640   /* Check the I2C handle allocation */
00641   if (hi2c == NULL)
00642   {
00643     return HAL_ERROR;
00644   }
00645
00646   /* Check the parameters */
00647   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00648
00649   hi2c->State = HAL_I2C_STATE_BUSY;
00650
00651   /* Disable the I2C Peripheral Clock */
00652   __HAL_I2C_DISABLE(hi2c);
00653
00654 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00655   if (hi2c->MspDeInitCallback == NULL)
00656   {
00657     hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
00658   }
00659
00660   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00661   hi2c->MspDeInitCallback(hi2c);
00662 #else
00663   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00664   HAL_I2C_MspDeInit(hi2c);
00665 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00666
00667   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00668   hi2c->State = HAL_I2C_STATE_RESET;
00669   hi2c->PreviousState = I2C_STATE_NONE;
00670   hi2c->Mode = HAL_I2C_MODE_NONE;
00671
00672   /* Release Lock */
00673   __HAL_UNLOCK(hi2c);
00674
00675   return HAL_OK;
00676 }
00677
00678 /**
00679   * @brief Initialize the I2C MSP.
00680   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00681   *                the configuration information for the specified I2C.
00682   * @retval None
00683   */
00684 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00685 {
00686   /* Prevent unused argument(s) compilation warning */
00687   UNUSED(hi2c);
00688
00689   /* NOTE : This function should not be modified, when the callback is needed,
00690             the HAL_I2C_MspInit could be implemented in the user file
00691    */
00692 }
00693
00694 /**
00695   * @brief DeInitialize the I2C MSP.
00696   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00697   *                the configuration information for the specified I2C.
00698   * @retval None
00699   */
00700 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00701 {
00702   /* Prevent unused argument(s) compilation warning */
00703   UNUSED(hi2c);
00704
00705   /* NOTE : This function should not be modified, when the callback is needed,
00706             the HAL_I2C_MspDeInit could be implemented in the user file
00707    */
00708 }
00709
00710 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00711 /**
00712   * @brief  Register a User I2C Callback
00713   *         To be used instead of the weak predefined callback
00714   * @note   The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
00715   *         to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
00716   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00717   *                the configuration information for the specified I2C.
00718   * @param  CallbackID ID of the callback to be registered
00719   *         This parameter can be one of the following values:
00720   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00721   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00722   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00723   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00724   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00725   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
00726   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
00727   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
00728   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
00729   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
00730   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
00731   * @param  pCallback pointer to the Callback function
00732   * @retval HAL status
00733   */
00734 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
00735                                            pI2C_CallbackTypeDef pCallback)
00736 {
00737   HAL_StatusTypeDef status = HAL_OK;
00738
00739   if (pCallback == NULL)
00740   {
00741     /* Update the error code */
00742     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00743
00744     return HAL_ERROR;
00745   }
00746
00747   if (HAL_I2C_STATE_READY == hi2c->State)
00748   {
00749     switch (CallbackID)
00750     {
00751       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
00752         hi2c->MasterTxCpltCallback = pCallback;
00753         break;
00754
00755       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
00756         hi2c->MasterRxCpltCallback = pCallback;
00757         break;
00758
00759       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
00760         hi2c->SlaveTxCpltCallback = pCallback;
00761         break;
00762
00763       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
00764         hi2c->SlaveRxCpltCallback = pCallback;
00765         break;
00766
00767       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
00768         hi2c->ListenCpltCallback = pCallback;
00769         break;
00770
00771       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
00772         hi2c->MemTxCpltCallback = pCallback;
00773         break;
00774
00775       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
00776         hi2c->MemRxCpltCallback = pCallback;
00777         break;
00778
00779       case HAL_I2C_ERROR_CB_ID :
00780         hi2c->ErrorCallback = pCallback;
00781         break;
00782
00783       case HAL_I2C_ABORT_CB_ID :
00784         hi2c->AbortCpltCallback = pCallback;
00785         break;
00786
00787       case HAL_I2C_MSPINIT_CB_ID :
00788         hi2c->MspInitCallback = pCallback;
00789         break;
00790
00791       case HAL_I2C_MSPDEINIT_CB_ID :
00792         hi2c->MspDeInitCallback = pCallback;
00793         break;
00794
00795       default :
00796         /* Update the error code */
00797         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00798
00799         /* Return error status */
00800         status =  HAL_ERROR;
00801         break;
00802     }
00803   }
00804   else if (HAL_I2C_STATE_RESET == hi2c->State)
00805   {
00806     switch (CallbackID)
00807     {
00808       case HAL_I2C_MSPINIT_CB_ID :
00809         hi2c->MspInitCallback = pCallback;
00810         break;
00811
00812       case HAL_I2C_MSPDEINIT_CB_ID :
00813         hi2c->MspDeInitCallback = pCallback;
00814         break;
00815
00816       default :
00817         /* Update the error code */
00818         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00819
00820         /* Return error status */
00821         status =  HAL_ERROR;
00822         break;
00823     }
00824   }
00825   else
00826   {
00827     /* Update the error code */
00828     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00829
00830     /* Return error status */
00831     status =  HAL_ERROR;
00832   }
00833
00834   return status;
00835 }
00836
00837 /**
00838   * @brief  Unregister an I2C Callback
00839   *         I2C callback is redirected to the weak predefined callback
00840   * @note   The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
00841   *         to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
00842   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00843   *                the configuration information for the specified I2C.
00844   * @param  CallbackID ID of the callback to be unregistered
00845   *         This parameter can be one of the following values:
00846   *         This parameter can be one of the following values:
00847   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00848   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00849   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00850   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00851   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00852   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
00853   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
00854   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
00855   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
00856   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
00857   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
00858   * @retval HAL status
00859   */
00860 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
00861 {
00862   HAL_StatusTypeDef status = HAL_OK;
00863
00864   if (HAL_I2C_STATE_READY == hi2c->State)
00865   {
00866     switch (CallbackID)
00867     {
00868       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
00869         hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00870         break;
00871
00872       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
00873         hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00874         break;
00875
00876       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
00877         hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
00878         break;
00879
00880       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
00881         hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
00882         break;
00883
00884       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
00885         hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
00886         break;
00887
00888       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
00889         hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
00890         break;
00891
00892       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
00893         hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
00894         break;
00895
00896       case HAL_I2C_ERROR_CB_ID :
00897         hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
00898         break;
00899
00900       case HAL_I2C_ABORT_CB_ID :
00901         hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00902         break;
00903
00904       case HAL_I2C_MSPINIT_CB_ID :
00905         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
00906         break;
00907
00908       case HAL_I2C_MSPDEINIT_CB_ID :
00909         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
00910         break;
00911
00912       default :
00913         /* Update the error code */
00914         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00915
00916         /* Return error status */
00917         status =  HAL_ERROR;
00918         break;
00919     }
00920   }
00921   else if (HAL_I2C_STATE_RESET == hi2c->State)
00922   {
00923     switch (CallbackID)
00924     {
00925       case HAL_I2C_MSPINIT_CB_ID :
00926         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
00927         break;
00928
00929       case HAL_I2C_MSPDEINIT_CB_ID :
00930         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
00931         break;
00932
00933       default :
00934         /* Update the error code */
00935         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00936
00937         /* Return error status */
00938         status =  HAL_ERROR;
00939         break;
00940     }
00941   }
00942   else
00943   {
00944     /* Update the error code */
00945     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00946
00947     /* Return error status */
00948     status =  HAL_ERROR;
00949   }
00950
00951   return status;
00952 }
00953
00954 /**
00955   * @brief  Register the Slave Address Match I2C Callback
00956   *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
00957   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00958   *                the configuration information for the specified I2C.
00959   * @param  pCallback pointer to the Address Match Callback function
00960   * @retval HAL status
00961   */
00962 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
00963 {
00964   HAL_StatusTypeDef status = HAL_OK;
00965
00966   if (pCallback == NULL)
00967   {
00968     /* Update the error code */
00969     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00970
00971     return HAL_ERROR;
00972   }
00973
00974   if (HAL_I2C_STATE_READY == hi2c->State)
00975   {
00976     hi2c->AddrCallback = pCallback;
00977   }
00978   else
00979   {
00980     /* Update the error code */
00981     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00982
00983     /* Return error status */
00984     status =  HAL_ERROR;
00985   }
00986
00987   return status;
00988 }
00989
00990 /**
00991   * @brief  UnRegister the Slave Address Match I2C Callback
00992   *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
00993   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00994   *                the configuration information for the specified I2C.
00995   * @retval HAL status
00996   */
00997 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
00998 {
00999   HAL_StatusTypeDef status = HAL_OK;
01000
01001   if (HAL_I2C_STATE_READY == hi2c->State)
01002   {
01003     hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
01004   }
01005   else
01006   {
01007     /* Update the error code */
01008     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
01009
01010     /* Return error status */
01011     status =  HAL_ERROR;
01012   }
01013
01014   return status;
01015 }
01016
01017 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
01018
01019 /**
01020   * @}
01021   */
01022
01023 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
01024   *  @brief   Data transfers functions
01025   *
01026 @verbatim
01027  ===============================================================================
01028                       ##### IO operation functions #####
01029  ===============================================================================
01030     [..]
01031     This subsection provides a set of functions allowing to manage the I2C data
01032     transfers.
01033
01034     (#) There are two modes of transfer:
01035        (++) Blocking mode : The communication is performed in the polling mode.
01036             The status of all data processing is returned by the same function
01037             after finishing transfer.
01038        (++) No-Blocking mode : The communication is performed using Interrupts
01039             or DMA. These functions return the status of the transfer startup.
01040             The end of the data processing will be indicated through the
01041             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
01042             using DMA mode.
01043
01044     (#) Blocking mode functions are :
01045         (++) HAL_I2C_Master_Transmit()
01046         (++) HAL_I2C_Master_Receive()
01047         (++) HAL_I2C_Slave_Transmit()
01048         (++) HAL_I2C_Slave_Receive()
01049         (++) HAL_I2C_Mem_Write()
01050         (++) HAL_I2C_Mem_Read()
01051         (++) HAL_I2C_IsDeviceReady()
01052
01053     (#) No-Blocking mode functions with Interrupt are :
01054         (++) HAL_I2C_Master_Transmit_IT()
01055         (++) HAL_I2C_Master_Receive_IT()
01056         (++) HAL_I2C_Slave_Transmit_IT()
01057         (++) HAL_I2C_Slave_Receive_IT()
01058         (++) HAL_I2C_Mem_Write_IT()
01059         (++) HAL_I2C_Mem_Read_IT()
01060         (++) HAL_I2C_Master_Seq_Transmit_IT()
01061         (++) HAL_I2C_Master_Seq_Receive_IT()
01062         (++) HAL_I2C_Slave_Seq_Transmit_IT()
01063         (++) HAL_I2C_Slave_Seq_Receive_IT()
01064         (++) HAL_I2C_EnableListen_IT()
01065         (++) HAL_I2C_DisableListen_IT()
01066         (++) HAL_I2C_Master_Abort_IT()
01067
01068     (#) No-Blocking mode functions with DMA are :
01069         (++) HAL_I2C_Master_Transmit_DMA()
01070         (++) HAL_I2C_Master_Receive_DMA()
01071         (++) HAL_I2C_Slave_Transmit_DMA()
01072         (++) HAL_I2C_Slave_Receive_DMA()
01073         (++) HAL_I2C_Mem_Write_DMA()
01074         (++) HAL_I2C_Mem_Read_DMA()
01075         (++) HAL_I2C_Master_Seq_Transmit_DMA()
01076         (++) HAL_I2C_Master_Seq_Receive_DMA()
01077         (++) HAL_I2C_Slave_Seq_Transmit_DMA()
01078         (++) HAL_I2C_Slave_Seq_Receive_DMA()
01079
01080     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
01081         (++) HAL_I2C_MasterTxCpltCallback()
01082         (++) HAL_I2C_MasterRxCpltCallback()
01083         (++) HAL_I2C_SlaveTxCpltCallback()
01084         (++) HAL_I2C_SlaveRxCpltCallback()
01085         (++) HAL_I2C_MemTxCpltCallback()
01086         (++) HAL_I2C_MemRxCpltCallback()
01087         (++) HAL_I2C_AddrCallback()
01088         (++) HAL_I2C_ListenCpltCallback()
01089         (++) HAL_I2C_ErrorCallback()
01090         (++) HAL_I2C_AbortCpltCallback()
01091
01092 @endverbatim
01093   * @{
01094   */
01095
01096 /**
01097   * @brief  Transmits in master mode an amount of data in blocking mode.
01098   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01099   *                the configuration information for the specified I2C.
01100   * @param  DevAddress Target device address: The device 7 bits address value
01101   *         in datasheet must be shifted to the left before calling the interface
01102   * @param  pData Pointer to data buffer
01103   * @param  Size Amount of data to be sent
01104   * @param  Timeout Timeout duration
01105   * @retval HAL status
01106   */
01107 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01108                                           uint16_t Size, uint32_t Timeout)
01109 {
01110   uint32_t tickstart;
01111
01112   if (hi2c->State == HAL_I2C_STATE_READY)
01113   {
01114     /* Process Locked */
01115     __HAL_LOCK(hi2c);
01116
01117     /* Init tickstart for timeout management*/
01118     tickstart = HAL_GetTick();
01119
01120     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01121     {
01122       return HAL_ERROR;
01123     }
01124
01125     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01126     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01127     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01128
01129     /* Prepare transfer parameters */
01130     hi2c->pBuffPtr  = pData;
01131     hi2c->XferCount = Size;
01132     hi2c->XferISR   = NULL;
01133
01134     /* Send Slave Address */
01135     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01136     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01137     {
01138       hi2c->XferSize = MAX_NBYTE_SIZE;
01139       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
01140                          I2C_GENERATE_START_WRITE);
01141     }
01142     else
01143     {
01144       hi2c->XferSize = hi2c->XferCount;
01145       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
01146                          I2C_GENERATE_START_WRITE);
01147     }
01148
01149     while (hi2c->XferCount > 0U)
01150     {
01151       /* Wait until TXIS flag is set */
01152       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01153       {
01154         return HAL_ERROR;
01155       }
01156       /* Write data to TXDR */
01157       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01158
01159       /* Increment Buffer pointer */
01160       hi2c->pBuffPtr++;
01161
01162       hi2c->XferCount--;
01163       hi2c->XferSize--;
01164
01165       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
01166       {
01167         /* Wait until TCR flag is set */
01168         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01169         {
01170           return HAL_ERROR;
01171         }
01172
01173         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01174         {
01175           hi2c->XferSize = MAX_NBYTE_SIZE;
01176           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
01177                              I2C_NO_STARTSTOP);
01178         }
01179         else
01180         {
01181           hi2c->XferSize = hi2c->XferCount;
01182           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
01183                              I2C_NO_STARTSTOP);
01184         }
01185       }
01186     }
01187
01188     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01189     /* Wait until STOPF flag is set */
01190     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01191     {
01192       return HAL_ERROR;
01193     }
01194
01195     /* Clear STOP Flag */
01196     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01197
01198     /* Clear Configuration Register 2 */
01199     I2C_RESET_CR2(hi2c);
01200
01201     hi2c->State = HAL_I2C_STATE_READY;
01202     hi2c->Mode  = HAL_I2C_MODE_NONE;
01203
01204     /* Process Unlocked */
01205     __HAL_UNLOCK(hi2c);
01206
01207     return HAL_OK;
01208   }
01209   else
01210   {
01211     return HAL_BUSY;
01212   }
01213 }
01214
01215 /**
01216   * @brief  Receives in master mode an amount of data in blocking mode.
01217   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01218   *                the configuration information for the specified I2C.
01219   * @param  DevAddress Target device address: The device 7 bits address value
01220   *         in datasheet must be shifted to the left before calling the interface
01221   * @param  pData Pointer to data buffer
01222   * @param  Size Amount of data to be sent
01223   * @param  Timeout Timeout duration
01224   * @retval HAL status
01225   */
01226 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01227                                          uint16_t Size, uint32_t Timeout)
01228 {
01229   uint32_t tickstart;
01230
01231   if (hi2c->State == HAL_I2C_STATE_READY)
01232   {
01233     /* Process Locked */
01234     __HAL_LOCK(hi2c);
01235
01236     /* Init tickstart for timeout management*/
01237     tickstart = HAL_GetTick();
01238
01239     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01240     {
01241       return HAL_ERROR;
01242     }
01243
01244     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01245     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01246     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01247
01248     /* Prepare transfer parameters */
01249     hi2c->pBuffPtr  = pData;
01250     hi2c->XferCount = Size;
01251     hi2c->XferISR   = NULL;
01252
01253     /* Send Slave Address */
01254     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01255     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01256     {
01257       hi2c->XferSize = MAX_NBYTE_SIZE;
01258       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
01259                          I2C_GENERATE_START_READ);
01260     }
01261     else
01262     {
01263       hi2c->XferSize = hi2c->XferCount;
01264       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
01265                          I2C_GENERATE_START_READ);
01266     }
01267
01268     while (hi2c->XferCount > 0U)
01269     {
01270       /* Wait until RXNE flag is set */
01271       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01272       {
01273         return HAL_ERROR;
01274       }
01275
01276       /* Read data from RXDR */
01277       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01278
01279       /* Increment Buffer pointer */
01280       hi2c->pBuffPtr++;
01281
01282       hi2c->XferSize--;
01283       hi2c->XferCount--;
01284
01285       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
01286       {
01287         /* Wait until TCR flag is set */
01288         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01289         {
01290           return HAL_ERROR;
01291         }
01292
01293         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01294         {
01295           hi2c->XferSize = MAX_NBYTE_SIZE;
01296           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
01297                              I2C_NO_STARTSTOP);
01298         }
01299         else
01300         {
01301           hi2c->XferSize = hi2c->XferCount;
01302           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
01303                              I2C_NO_STARTSTOP);
01304         }
01305       }
01306     }
01307
01308     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01309     /* Wait until STOPF flag is set */
01310     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01311     {
01312       return HAL_ERROR;
01313     }
01314
01315     /* Clear STOP Flag */
01316     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01317
01318     /* Clear Configuration Register 2 */
01319     I2C_RESET_CR2(hi2c);
01320
01321     hi2c->State = HAL_I2C_STATE_READY;
01322     hi2c->Mode  = HAL_I2C_MODE_NONE;
01323
01324     /* Process Unlocked */
01325     __HAL_UNLOCK(hi2c);
01326
01327     return HAL_OK;
01328   }
01329   else
01330   {
01331     return HAL_BUSY;
01332   }
01333 }
01334
01335 /**
01336   * @brief  Transmits in slave mode an amount of data in blocking mode.
01337   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01338   *                the configuration information for the specified I2C.
01339   * @param  pData Pointer to data buffer
01340   * @param  Size Amount of data to be sent
01341   * @param  Timeout Timeout duration
01342   * @retval HAL status
01343   */
01344 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
01345                                          uint32_t Timeout)
01346 {
01347   uint32_t tickstart;
01348
01349   if (hi2c->State == HAL_I2C_STATE_READY)
01350   {
01351     if ((pData == NULL) || (Size == 0U))
01352     {
01353       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
01354       return  HAL_ERROR;
01355     }
01356     /* Process Locked */
01357     __HAL_LOCK(hi2c);
01358
01359     /* Init tickstart for timeout management*/
01360     tickstart = HAL_GetTick();
01361
01362     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01363     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01364     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01365
01366     /* Prepare transfer parameters */
01367     hi2c->pBuffPtr  = pData;
01368     hi2c->XferCount = Size;
01369     hi2c->XferISR   = NULL;
01370
01371     /* Enable Address Acknowledge */
01372     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01373
01374     /* Wait until ADDR flag is set */
01375     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01376     {
01377       /* Disable Address Acknowledge */
01378       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01379       return HAL_ERROR;
01380     }
01381
01382     /* Clear ADDR flag */
01383     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01384
01385     /* If 10bit addressing mode is selected */
01386     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
01387     {
01388       /* Wait until ADDR flag is set */
01389       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01390       {
01391         /* Disable Address Acknowledge */
01392         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01393         return HAL_ERROR;
01394       }
01395
01396       /* Clear ADDR flag */
01397       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01398     }
01399
01400     /* Wait until DIR flag is set Transmitter mode */
01401     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
01402     {
01403       /* Disable Address Acknowledge */
01404       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01405       return HAL_ERROR;
01406     }
01407
01408     while (hi2c->XferCount > 0U)
01409     {
01410       /* Wait until TXIS flag is set */
01411       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01412       {
01413         /* Disable Address Acknowledge */
01414         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01415         return HAL_ERROR;
01416       }
01417
01418       /* Write data to TXDR */
01419       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01420
01421       /* Increment Buffer pointer */
01422       hi2c->pBuffPtr++;
01423
01424       hi2c->XferCount--;
01425     }
01426
01427     /* Wait until AF flag is set */
01428     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
01429     {
01430       /* Disable Address Acknowledge */
01431       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01432       return HAL_ERROR;
01433     }
01434
01435     /* Flush TX register */
01436     I2C_Flush_TXDR(hi2c);
01437
01438     /* Clear AF flag */
01439     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
01440
01441     /* Wait until STOP flag is set */
01442     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01443     {
01444       /* Disable Address Acknowledge */
01445       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01446
01447       return HAL_ERROR;
01448     }
01449
01450     /* Clear STOP flag */
01451     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01452
01453     /* Wait until BUSY flag is reset */
01454     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01455     {
01456       /* Disable Address Acknowledge */
01457       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01458       return HAL_ERROR;
01459     }
01460
01461     /* Disable Address Acknowledge */
01462     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01463
01464     hi2c->State = HAL_I2C_STATE_READY;
01465     hi2c->Mode  = HAL_I2C_MODE_NONE;
01466
01467     /* Process Unlocked */
01468     __HAL_UNLOCK(hi2c);
01469
01470     return HAL_OK;
01471   }
01472   else
01473   {
01474     return HAL_BUSY;
01475   }
01476 }
01477
01478 /**
01479   * @brief  Receive in slave mode an amount of data in blocking mode
01480   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01481   *                the configuration information for the specified I2C.
01482   * @param  pData Pointer to data buffer
01483   * @param  Size Amount of data to be sent
01484   * @param  Timeout Timeout duration
01485   * @retval HAL status
01486   */
01487 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
01488                                         uint32_t Timeout)
01489 {
01490   uint32_t tickstart;
01491
01492   if (hi2c->State == HAL_I2C_STATE_READY)
01493   {
01494     if ((pData == NULL) || (Size == 0U))
01495     {
01496       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
01497       return  HAL_ERROR;
01498     }
01499     /* Process Locked */
01500     __HAL_LOCK(hi2c);
01501
01502     /* Init tickstart for timeout management*/
01503     tickstart = HAL_GetTick();
01504
01505     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01506     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01507     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01508
01509     /* Prepare transfer parameters */
01510     hi2c->pBuffPtr  = pData;
01511     hi2c->XferCount = Size;
01512     hi2c->XferSize = hi2c->XferCount;
01513     hi2c->XferISR   = NULL;
01514
01515     /* Enable Address Acknowledge */
01516     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01517
01518     /* Wait until ADDR flag is set */
01519     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01520     {
01521       /* Disable Address Acknowledge */
01522       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01523       return HAL_ERROR;
01524     }
01525
01526     /* Clear ADDR flag */
01527     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01528
01529     /* Wait until DIR flag is reset Receiver mode */
01530     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
01531     {
01532       /* Disable Address Acknowledge */
01533       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01534       return HAL_ERROR;
01535     }
01536
01537     while (hi2c->XferCount > 0U)
01538     {
01539       /* Wait until RXNE flag is set */
01540       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01541       {
01542         /* Disable Address Acknowledge */
01543         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01544
01545         /* Store Last receive data if any */
01546         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
01547         {
01548           /* Read data from RXDR */
01549           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01550
01551           /* Increment Buffer pointer */
01552           hi2c->pBuffPtr++;
01553
01554           hi2c->XferCount--;
01555           hi2c->XferSize--;
01556         }
01557
01558         return HAL_ERROR;
01559       }
01560
01561       /* Read data from RXDR */
01562       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01563
01564       /* Increment Buffer pointer */
01565       hi2c->pBuffPtr++;
01566
01567       hi2c->XferCount--;
01568       hi2c->XferSize--;
01569     }
01570
01571     /* Wait until STOP flag is set */
01572     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01573     {
01574       /* Disable Address Acknowledge */
01575       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01576       return HAL_ERROR;
01577     }
01578
01579     /* Clear STOP flag */
01580     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01581
01582     /* Wait until BUSY flag is reset */
01583     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01584     {
01585       /* Disable Address Acknowledge */
01586       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01587       return HAL_ERROR;
01588     }
01589
01590     /* Disable Address Acknowledge */
01591     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01592
01593     hi2c->State = HAL_I2C_STATE_READY;
01594     hi2c->Mode  = HAL_I2C_MODE_NONE;
01595
01596     /* Process Unlocked */
01597     __HAL_UNLOCK(hi2c);
01598
01599     return HAL_OK;
01600   }
01601   else
01602   {
01603     return HAL_BUSY;
01604   }
01605 }
01606
01607 /**
01608   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01609   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01610   *                the configuration information for the specified I2C.
01611   * @param  DevAddress Target device address: The device 7 bits address value
01612   *         in datasheet must be shifted to the left before calling the interface
01613   * @param  pData Pointer to data buffer
01614   * @param  Size Amount of data to be sent
01615   * @retval HAL status
01616   */
01617 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01618                                              uint16_t Size)
01619 {
01620   uint32_t xfermode;
01621
01622   if (hi2c->State == HAL_I2C_STATE_READY)
01623   {
01624     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01625     {
01626       return HAL_BUSY;
01627     }
01628
01629     /* Process Locked */
01630     __HAL_LOCK(hi2c);
01631
01632     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01633     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01634     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01635
01636     /* Prepare transfer parameters */
01637     hi2c->pBuffPtr    = pData;
01638     hi2c->XferCount   = Size;
01639     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01640     hi2c->XferISR     = I2C_Master_ISR_IT;
01641
01642     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01643     {
01644       hi2c->XferSize = MAX_NBYTE_SIZE;
01645       xfermode = I2C_RELOAD_MODE;
01646     }
01647     else
01648     {
01649       hi2c->XferSize = hi2c->XferCount;
01650       xfermode = I2C_AUTOEND_MODE;
01651     }
01652
01653     /* Send Slave Address */
01654     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01655     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01656
01657     /* Process Unlocked */
01658     __HAL_UNLOCK(hi2c);
01659
01660     /* Note : The I2C interrupts must be enabled after unlocking current process
01661               to avoid the risk of I2C interrupt handle execution before current
01662               process unlock */
01663
01664     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01665     /* possible to enable all of these */
01666     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01667       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01668     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01669
01670     return HAL_OK;
01671   }
01672   else
01673   {
01674     return HAL_BUSY;
01675   }
01676 }
01677
01678 /**
01679   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01680   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01681   *                the configuration information for the specified I2C.
01682   * @param  DevAddress Target device address: The device 7 bits address value
01683   *         in datasheet must be shifted to the left before calling the interface
01684   * @param  pData Pointer to data buffer
01685   * @param  Size Amount of data to be sent
01686   * @retval HAL status
01687   */
01688 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01689                                             uint16_t Size)
01690 {
01691   uint32_t xfermode;
01692
01693   if (hi2c->State == HAL_I2C_STATE_READY)
01694   {
01695     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01696     {
01697       return HAL_BUSY;
01698     }
01699
01700     /* Process Locked */
01701     __HAL_LOCK(hi2c);
01702
01703     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01704     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01705     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01706
01707     /* Prepare transfer parameters */
01708     hi2c->pBuffPtr    = pData;
01709     hi2c->XferCount   = Size;
01710     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01711     hi2c->XferISR     = I2C_Master_ISR_IT;
01712
01713     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01714     {
01715       hi2c->XferSize = MAX_NBYTE_SIZE;
01716       xfermode = I2C_RELOAD_MODE;
01717     }
01718     else
01719     {
01720       hi2c->XferSize = hi2c->XferCount;
01721       xfermode = I2C_AUTOEND_MODE;
01722     }
01723
01724     /* Send Slave Address */
01725     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01726     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01727
01728     /* Process Unlocked */
01729     __HAL_UNLOCK(hi2c);
01730
01731     /* Note : The I2C interrupts must be enabled after unlocking current process
01732               to avoid the risk of I2C interrupt handle execution before current
01733               process unlock */
01734
01735     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01736     /* possible to enable all of these */
01737     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01738       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01739     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
01740
01741     return HAL_OK;
01742   }
01743   else
01744   {
01745     return HAL_BUSY;
01746   }
01747 }
01748
01749 /**
01750   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01751   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01752   *                the configuration information for the specified I2C.
01753   * @param  pData Pointer to data buffer
01754   * @param  Size Amount of data to be sent
01755   * @retval HAL status
01756   */
01757 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01758 {
01759   if (hi2c->State == HAL_I2C_STATE_READY)
01760   {
01761     /* Process Locked */
01762     __HAL_LOCK(hi2c);
01763
01764     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01765     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01766     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01767
01768     /* Enable Address Acknowledge */
01769     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01770
01771     /* Prepare transfer parameters */
01772     hi2c->pBuffPtr    = pData;
01773     hi2c->XferCount   = Size;
01774     hi2c->XferSize    = hi2c->XferCount;
01775     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01776     hi2c->XferISR     = I2C_Slave_ISR_IT;
01777
01778     /* Process Unlocked */
01779     __HAL_UNLOCK(hi2c);
01780
01781     /* Note : The I2C interrupts must be enabled after unlocking current process
01782               to avoid the risk of I2C interrupt handle execution before current
01783               process unlock */
01784
01785     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01786     /* possible to enable all of these */
01787     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01788       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01789     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
01790
01791     return HAL_OK;
01792   }
01793   else
01794   {
01795     return HAL_BUSY;
01796   }
01797 }
01798
01799 /**
01800   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
01801   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01802   *                the configuration information for the specified I2C.
01803   * @param  pData Pointer to data buffer
01804   * @param  Size Amount of data to be sent
01805   * @retval HAL status
01806   */
01807 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01808 {
01809   if (hi2c->State == HAL_I2C_STATE_READY)
01810   {
01811     /* Process Locked */
01812     __HAL_LOCK(hi2c);
01813
01814     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01815     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01816     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01817
01818     /* Enable Address Acknowledge */
01819     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01820
01821     /* Prepare transfer parameters */
01822     hi2c->pBuffPtr    = pData;
01823     hi2c->XferCount   = Size;
01824     hi2c->XferSize    = hi2c->XferCount;
01825     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01826     hi2c->XferISR     = I2C_Slave_ISR_IT;
01827
01828     /* Process Unlocked */
01829     __HAL_UNLOCK(hi2c);
01830
01831     /* Note : The I2C interrupts must be enabled after unlocking current process
01832               to avoid the risk of I2C interrupt handle execution before current
01833               process unlock */
01834
01835     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01836     /* possible to enable all of these */
01837     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01838       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01839     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
01840
01841     return HAL_OK;
01842   }
01843   else
01844   {
01845     return HAL_BUSY;
01846   }
01847 }
01848
01849 /**
01850   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01851   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01852   *                the configuration information for the specified I2C.
01853   * @param  DevAddress Target device address: The device 7 bits address value
01854   *         in datasheet must be shifted to the left before calling the interface
01855   * @param  pData Pointer to data buffer
01856   * @param  Size Amount of data to be sent
01857   * @retval HAL status
01858   */
01859 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
01860                                               uint16_t Size)
01861 {
01862   uint32_t xfermode;
01863   HAL_StatusTypeDef dmaxferstatus;
01864
01865   if (hi2c->State == HAL_I2C_STATE_READY)
01866   {
01867     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01868     {
01869       return HAL_BUSY;
01870     }
01871
01872     /* Process Locked */
01873     __HAL_LOCK(hi2c);
01874
01875     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01876     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01877     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01878
01879     /* Prepare transfer parameters */
01880     hi2c->pBuffPtr    = pData;
01881     hi2c->XferCount   = Size;
01882     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01883     hi2c->XferISR     = I2C_Master_ISR_DMA;
01884
01885     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01886     {
01887       hi2c->XferSize = MAX_NBYTE_SIZE;
01888       xfermode = I2C_RELOAD_MODE;
01889     }
01890     else
01891     {
01892       hi2c->XferSize = hi2c->XferCount;
01893       xfermode = I2C_AUTOEND_MODE;
01894     }
01895
01896     if (hi2c->XferSize > 0U)
01897     {
01898       if (hi2c->hdmatx != NULL)
01899       {
01900         /* Set the I2C DMA transfer complete callback */
01901         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01902
01903         /* Set the DMA error callback */
01904         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01905
01906         /* Set the unused DMA callbacks to NULL */
01907         hi2c->hdmatx->XferHalfCpltCallback = NULL;
01908         hi2c->hdmatx->XferAbortCallback = NULL;
01909
01910         /* Enable the DMA channel */
01911         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
01912                                          hi2c->XferSize);
01913       }
01914       else
01915       {
01916         /* Update I2C state */
01917         hi2c->State     = HAL_I2C_STATE_READY;
01918         hi2c->Mode      = HAL_I2C_MODE_NONE;
01919
01920         /* Update I2C error code */
01921         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
01922
01923         /* Process Unlocked */
01924         __HAL_UNLOCK(hi2c);
01925
01926         return HAL_ERROR;
01927       }
01928
01929       if (dmaxferstatus == HAL_OK)
01930       {
01931         /* Send Slave Address */
01932         /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01933         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01934
01935         /* Update XferCount value */
01936         hi2c->XferCount -= hi2c->XferSize;
01937
01938         /* Process Unlocked */
01939         __HAL_UNLOCK(hi2c);
01940
01941         /* Note : The I2C interrupts must be enabled after unlocking current process
01942                   to avoid the risk of I2C interrupt handle execution before current
01943                   process unlock */
01944         /* Enable ERR and NACK interrupts */
01945         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01946
01947         /* Enable DMA Request */
01948         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01949       }
01950       else
01951       {
01952         /* Update I2C state */
01953         hi2c->State     = HAL_I2C_STATE_READY;
01954         hi2c->Mode      = HAL_I2C_MODE_NONE;
01955
01956         /* Update I2C error code */
01957         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
01958
01959         /* Process Unlocked */
01960         __HAL_UNLOCK(hi2c);
01961
01962         return HAL_ERROR;
01963       }
01964     }
01965     else
01966     {
01967       /* Update Transfer ISR function pointer */
01968       hi2c->XferISR = I2C_Master_ISR_IT;
01969
01970       /* Send Slave Address */
01971       /* Set NBYTES to write and generate START condition */
01972       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
01973                          I2C_GENERATE_START_WRITE);
01974
01975       /* Process Unlocked */
01976       __HAL_UNLOCK(hi2c);
01977
01978       /* Note : The I2C interrupts must be enabled after unlocking current process
01979                 to avoid the risk of I2C interrupt handle execution before current
01980                 process unlock */
01981       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01982       /* possible to enable all of these */
01983       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
01984         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01985       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01986     }
01987
01988     return HAL_OK;
01989   }
01990   else
01991   {
01992     return HAL_BUSY;
01993   }
01994 }
01995
01996 /**
01997   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
01998   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01999   *                the configuration information for the specified I2C.
02000   * @param  DevAddress Target device address: The device 7 bits address value
02001   *         in datasheet must be shifted to the left before calling the interface
02002   * @param  pData Pointer to data buffer
02003   * @param  Size Amount of data to be sent
02004   * @retval HAL status
02005   */
02006 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
02007                                              uint16_t Size)
02008 {
02009   uint32_t xfermode;
02010   HAL_StatusTypeDef dmaxferstatus;
02011
02012   if (hi2c->State == HAL_I2C_STATE_READY)
02013   {
02014     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02015     {
02016       return HAL_BUSY;
02017     }
02018
02019     /* Process Locked */
02020     __HAL_LOCK(hi2c);
02021
02022     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02023     hi2c->Mode        = HAL_I2C_MODE_MASTER;
02024     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02025
02026     /* Prepare transfer parameters */
02027     hi2c->pBuffPtr    = pData;
02028     hi2c->XferCount   = Size;
02029     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02030     hi2c->XferISR     = I2C_Master_ISR_DMA;
02031
02032     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02033     {
02034       hi2c->XferSize = MAX_NBYTE_SIZE;
02035       xfermode = I2C_RELOAD_MODE;
02036     }
02037     else
02038     {
02039       hi2c->XferSize = hi2c->XferCount;
02040       xfermode = I2C_AUTOEND_MODE;
02041     }
02042
02043     if (hi2c->XferSize > 0U)
02044     {
02045       if (hi2c->hdmarx != NULL)
02046       {
02047         /* Set the I2C DMA transfer complete callback */
02048         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
02049
02050         /* Set the DMA error callback */
02051         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02052
02053         /* Set the unused DMA callbacks to NULL */
02054         hi2c->hdmarx->XferHalfCpltCallback = NULL;
02055         hi2c->hdmarx->XferAbortCallback = NULL;
02056
02057         /* Enable the DMA channel */
02058         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
02059                                          hi2c->XferSize);
02060       }
02061       else
02062       {
02063         /* Update I2C state */
02064         hi2c->State     = HAL_I2C_STATE_READY;
02065         hi2c->Mode      = HAL_I2C_MODE_NONE;
02066
02067         /* Update I2C error code */
02068         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02069
02070         /* Process Unlocked */
02071         __HAL_UNLOCK(hi2c);
02072
02073         return HAL_ERROR;
02074       }
02075
02076       if (dmaxferstatus == HAL_OK)
02077       {
02078         /* Send Slave Address */
02079         /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02080         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02081
02082         /* Update XferCount value */
02083         hi2c->XferCount -= hi2c->XferSize;
02084
02085         /* Process Unlocked */
02086         __HAL_UNLOCK(hi2c);
02087
02088         /* Note : The I2C interrupts must be enabled after unlocking current process
02089                   to avoid the risk of I2C interrupt handle execution before current
02090                   process unlock */
02091         /* Enable ERR and NACK interrupts */
02092         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02093
02094         /* Enable DMA Request */
02095         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02096       }
02097       else
02098       {
02099         /* Update I2C state */
02100         hi2c->State     = HAL_I2C_STATE_READY;
02101         hi2c->Mode      = HAL_I2C_MODE_NONE;
02102
02103         /* Update I2C error code */
02104         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02105
02106         /* Process Unlocked */
02107         __HAL_UNLOCK(hi2c);
02108
02109         return HAL_ERROR;
02110       }
02111     }
02112     else
02113     {
02114       /* Update Transfer ISR function pointer */
02115       hi2c->XferISR = I2C_Master_ISR_IT;
02116
02117       /* Send Slave Address */
02118       /* Set NBYTES to read and generate START condition */
02119       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
02120                          I2C_GENERATE_START_READ);
02121
02122       /* Process Unlocked */
02123       __HAL_UNLOCK(hi2c);
02124
02125       /* Note : The I2C interrupts must be enabled after unlocking current process
02126                 to avoid the risk of I2C interrupt handle execution before current
02127                 process unlock */
02128       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02129       /* possible to enable all of these */
02130       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
02131         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02132       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02133     }
02134
02135     return HAL_OK;
02136   }
02137   else
02138   {
02139     return HAL_BUSY;
02140   }
02141 }
02142
02143 /**
02144   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
02145   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02146   *                the configuration information for the specified I2C.
02147   * @param  pData Pointer to data buffer
02148   * @param  Size Amount of data to be sent
02149   * @retval HAL status
02150   */
02151 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02152 {
02153   HAL_StatusTypeDef dmaxferstatus;
02154
02155   if (hi2c->State == HAL_I2C_STATE_READY)
02156   {
02157     if ((pData == NULL) || (Size == 0U))
02158     {
02159       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02160       return  HAL_ERROR;
02161     }
02162     /* Process Locked */
02163     __HAL_LOCK(hi2c);
02164
02165     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02166     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
02167     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02168
02169     /* Prepare transfer parameters */
02170     hi2c->pBuffPtr    = pData;
02171     hi2c->XferCount   = Size;
02172     hi2c->XferSize    = hi2c->XferCount;
02173     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02174     hi2c->XferISR     = I2C_Slave_ISR_DMA;
02175
02176     if (hi2c->hdmatx != NULL)
02177     {
02178       /* Set the I2C DMA transfer complete callback */
02179       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
02180
02181       /* Set the DMA error callback */
02182       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02183
02184       /* Set the unused DMA callbacks to NULL */
02185       hi2c->hdmatx->XferHalfCpltCallback = NULL;
02186       hi2c->hdmatx->XferAbortCallback = NULL;
02187
02188       /* Enable the DMA channel */
02189       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
02190                                        hi2c->XferSize);
02191     }
02192     else
02193     {
02194       /* Update I2C state */
02195       hi2c->State     = HAL_I2C_STATE_LISTEN;
02196       hi2c->Mode      = HAL_I2C_MODE_NONE;
02197
02198       /* Update I2C error code */
02199       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02200
02201       /* Process Unlocked */
02202       __HAL_UNLOCK(hi2c);
02203
02204       return HAL_ERROR;
02205     }
02206
02207     if (dmaxferstatus == HAL_OK)
02208     {
02209       /* Enable Address Acknowledge */
02210       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02211
02212       /* Process Unlocked */
02213       __HAL_UNLOCK(hi2c);
02214
02215       /* Note : The I2C interrupts must be enabled after unlocking current process
02216                 to avoid the risk of I2C interrupt handle execution before current
02217                 process unlock */
02218       /* Enable ERR, STOP, NACK, ADDR interrupts */
02219       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02220
02221       /* Enable DMA Request */
02222       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02223     }
02224     else
02225     {
02226       /* Update I2C state */
02227       hi2c->State     = HAL_I2C_STATE_LISTEN;
02228       hi2c->Mode      = HAL_I2C_MODE_NONE;
02229
02230       /* Update I2C error code */
02231       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02232
02233       /* Process Unlocked */
02234       __HAL_UNLOCK(hi2c);
02235
02236       return HAL_ERROR;
02237     }
02238
02239     return HAL_OK;
02240   }
02241   else
02242   {
02243     return HAL_BUSY;
02244   }
02245 }
02246
02247 /**
02248   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
02249   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02250   *                the configuration information for the specified I2C.
02251   * @param  pData Pointer to data buffer
02252   * @param  Size Amount of data to be sent
02253   * @retval HAL status
02254   */
02255 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02256 {
02257   HAL_StatusTypeDef dmaxferstatus;
02258
02259   if (hi2c->State == HAL_I2C_STATE_READY)
02260   {
02261     if ((pData == NULL) || (Size == 0U))
02262     {
02263       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02264       return  HAL_ERROR;
02265     }
02266     /* Process Locked */
02267     __HAL_LOCK(hi2c);
02268
02269     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02270     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
02271     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02272
02273     /* Prepare transfer parameters */
02274     hi2c->pBuffPtr    = pData;
02275     hi2c->XferCount   = Size;
02276     hi2c->XferSize    = hi2c->XferCount;
02277     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02278     hi2c->XferISR     = I2C_Slave_ISR_DMA;
02279
02280     if (hi2c->hdmarx != NULL)
02281     {
02282       /* Set the I2C DMA transfer complete callback */
02283       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
02284
02285       /* Set the DMA error callback */
02286       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02287
02288       /* Set the unused DMA callbacks to NULL */
02289       hi2c->hdmarx->XferHalfCpltCallback = NULL;
02290       hi2c->hdmarx->XferAbortCallback = NULL;
02291
02292       /* Enable the DMA channel */
02293       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
02294                                        hi2c->XferSize);
02295     }
02296     else
02297     {
02298       /* Update I2C state */
02299       hi2c->State     = HAL_I2C_STATE_LISTEN;
02300       hi2c->Mode      = HAL_I2C_MODE_NONE;
02301
02302       /* Update I2C error code */
02303       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02304
02305       /* Process Unlocked */
02306       __HAL_UNLOCK(hi2c);
02307
02308       return HAL_ERROR;
02309     }
02310
02311     if (dmaxferstatus == HAL_OK)
02312     {
02313       /* Enable Address Acknowledge */
02314       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02315
02316       /* Process Unlocked */
02317       __HAL_UNLOCK(hi2c);
02318
02319       /* Note : The I2C interrupts must be enabled after unlocking current process
02320                 to avoid the risk of I2C interrupt handle execution before current
02321                 process unlock */
02322       /* Enable ERR, STOP, NACK, ADDR interrupts */
02323       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02324
02325       /* Enable DMA Request */
02326       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02327     }
02328     else
02329     {
02330       /* Update I2C state */
02331       hi2c->State     = HAL_I2C_STATE_LISTEN;
02332       hi2c->Mode      = HAL_I2C_MODE_NONE;
02333
02334       /* Update I2C error code */
02335       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02336
02337       /* Process Unlocked */
02338       __HAL_UNLOCK(hi2c);
02339
02340       return HAL_ERROR;
02341     }
02342
02343     return HAL_OK;
02344   }
02345   else
02346   {
02347     return HAL_BUSY;
02348   }
02349 }
02350 /**
02351   * @brief  Write an amount of data in blocking mode to a specific memory address
02352   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02353   *                the configuration information for the specified I2C.
02354   * @param  DevAddress Target device address: The device 7 bits address value
02355   *         in datasheet must be shifted to the left before calling the interface
02356   * @param  MemAddress Internal memory address
02357   * @param  MemAddSize Size of internal memory address
02358   * @param  pData Pointer to data buffer
02359   * @param  Size Amount of data to be sent
02360   * @param  Timeout Timeout duration
02361   * @retval HAL status
02362   */
02363 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02364                                     uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02365 {
02366   uint32_t tickstart;
02367
02368   /* Check the parameters */
02369   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02370
02371   if (hi2c->State == HAL_I2C_STATE_READY)
02372   {
02373     if ((pData == NULL) || (Size == 0U))
02374     {
02375       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02376       return  HAL_ERROR;
02377     }
02378
02379     /* Process Locked */
02380     __HAL_LOCK(hi2c);
02381
02382     /* Init tickstart for timeout management*/
02383     tickstart = HAL_GetTick();
02384
02385     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
02386     {
02387       return HAL_ERROR;
02388     }
02389
02390     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02391     hi2c->Mode      = HAL_I2C_MODE_MEM;
02392     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02393
02394     /* Prepare transfer parameters */
02395     hi2c->pBuffPtr  = pData;
02396     hi2c->XferCount = Size;
02397     hi2c->XferISR   = NULL;
02398
02399     /* Send Slave Address and Memory Address */
02400     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02401     {
02402       /* Process Unlocked */
02403       __HAL_UNLOCK(hi2c);
02404       return HAL_ERROR;
02405     }
02406
02407     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
02408     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02409     {
02410       hi2c->XferSize = MAX_NBYTE_SIZE;
02411       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02412     }
02413     else
02414     {
02415       hi2c->XferSize = hi2c->XferCount;
02416       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02417     }
02418
02419     do
02420     {
02421       /* Wait until TXIS flag is set */
02422       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02423       {
02424         return HAL_ERROR;
02425       }
02426
02427       /* Write data to TXDR */
02428       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
02429
02430       /* Increment Buffer pointer */
02431       hi2c->pBuffPtr++;
02432
02433       hi2c->XferCount--;
02434       hi2c->XferSize--;
02435
02436       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
02437       {
02438         /* Wait until TCR flag is set */
02439         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
02440         {
02441           return HAL_ERROR;
02442         }
02443
02444         if (hi2c->XferCount > MAX_NBYTE_SIZE)
02445         {
02446           hi2c->XferSize = MAX_NBYTE_SIZE;
02447           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
02448                              I2C_NO_STARTSTOP);
02449         }
02450         else
02451         {
02452           hi2c->XferSize = hi2c->XferCount;
02453           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
02454                              I2C_NO_STARTSTOP);
02455         }
02456       }
02457
02458     } while (hi2c->XferCount > 0U);
02459
02460     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02461     /* Wait until STOPF flag is reset */
02462     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02463     {
02464       return HAL_ERROR;
02465     }
02466
02467     /* Clear STOP Flag */
02468     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02469
02470     /* Clear Configuration Register 2 */
02471     I2C_RESET_CR2(hi2c);
02472
02473     hi2c->State = HAL_I2C_STATE_READY;
02474     hi2c->Mode  = HAL_I2C_MODE_NONE;
02475
02476     /* Process Unlocked */
02477     __HAL_UNLOCK(hi2c);
02478
02479     return HAL_OK;
02480   }
02481   else
02482   {
02483     return HAL_BUSY;
02484   }
02485 }
02486
02487 /**
02488   * @brief  Read an amount of data in blocking mode from a specific memory address
02489   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02490   *                the configuration information for the specified I2C.
02491   * @param  DevAddress Target device address: The device 7 bits address value
02492   *         in datasheet must be shifted to the left before calling the interface
02493   * @param  MemAddress Internal memory address
02494   * @param  MemAddSize Size of internal memory address
02495   * @param  pData Pointer to data buffer
02496   * @param  Size Amount of data to be sent
02497   * @param  Timeout Timeout duration
02498   * @retval HAL status
02499   */
02500 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02501                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02502 {
02503   uint32_t tickstart;
02504
02505   /* Check the parameters */
02506   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02507
02508   if (hi2c->State == HAL_I2C_STATE_READY)
02509   {
02510     if ((pData == NULL) || (Size == 0U))
02511     {
02512       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02513       return  HAL_ERROR;
02514     }
02515
02516     /* Process Locked */
02517     __HAL_LOCK(hi2c);
02518
02519     /* Init tickstart for timeout management*/
02520     tickstart = HAL_GetTick();
02521
02522     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
02523     {
02524       return HAL_ERROR;
02525     }
02526
02527     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02528     hi2c->Mode      = HAL_I2C_MODE_MEM;
02529     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02530
02531     /* Prepare transfer parameters */
02532     hi2c->pBuffPtr  = pData;
02533     hi2c->XferCount = Size;
02534     hi2c->XferISR   = NULL;
02535
02536     /* Send Slave Address and Memory Address */
02537     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02538     {
02539       /* Process Unlocked */
02540       __HAL_UNLOCK(hi2c);
02541       return HAL_ERROR;
02542     }
02543
02544     /* Send Slave Address */
02545     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02546     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02547     {
02548       hi2c->XferSize = MAX_NBYTE_SIZE;
02549       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
02550                          I2C_GENERATE_START_READ);
02551     }
02552     else
02553     {
02554       hi2c->XferSize = hi2c->XferCount;
02555       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
02556                          I2C_GENERATE_START_READ);
02557     }
02558
02559     do
02560     {
02561       /* Wait until RXNE flag is set */
02562       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
02563       {
02564         return HAL_ERROR;
02565       }
02566
02567       /* Read data from RXDR */
02568       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
02569
02570       /* Increment Buffer pointer */
02571       hi2c->pBuffPtr++;
02572
02573       hi2c->XferSize--;
02574       hi2c->XferCount--;
02575
02576       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
02577       {
02578         /* Wait until TCR flag is set */
02579         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
02580         {
02581           return HAL_ERROR;
02582         }
02583
02584         if (hi2c->XferCount > MAX_NBYTE_SIZE)
02585         {
02586           hi2c->XferSize = MAX_NBYTE_SIZE;
02587           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
02588                              I2C_NO_STARTSTOP);
02589         }
02590         else
02591         {
02592           hi2c->XferSize = hi2c->XferCount;
02593           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
02594                              I2C_NO_STARTSTOP);
02595         }
02596       }
02597     } while (hi2c->XferCount > 0U);
02598
02599     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02600     /* Wait until STOPF flag is reset */
02601     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02602     {
02603       return HAL_ERROR;
02604     }
02605
02606     /* Clear STOP Flag */
02607     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02608
02609     /* Clear Configuration Register 2 */
02610     I2C_RESET_CR2(hi2c);
02611
02612     hi2c->State = HAL_I2C_STATE_READY;
02613     hi2c->Mode  = HAL_I2C_MODE_NONE;
02614
02615     /* Process Unlocked */
02616     __HAL_UNLOCK(hi2c);
02617
02618     return HAL_OK;
02619   }
02620   else
02621   {
02622     return HAL_BUSY;
02623   }
02624 }
02625 /**
02626   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02627   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02628   *                the configuration information for the specified I2C.
02629   * @param  DevAddress Target device address: The device 7 bits address value
02630   *         in datasheet must be shifted to the left before calling the interface
02631   * @param  MemAddress Internal memory address
02632   * @param  MemAddSize Size of internal memory address
02633   * @param  pData Pointer to data buffer
02634   * @param  Size Amount of data to be sent
02635   * @retval HAL status
02636   */
02637 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02638                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02639 {
02640   /* Check the parameters */
02641   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02642
02643   if (hi2c->State == HAL_I2C_STATE_READY)
02644   {
02645     if ((pData == NULL) || (Size == 0U))
02646     {
02647       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02648       return  HAL_ERROR;
02649     }
02650
02651     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02652     {
02653       return HAL_BUSY;
02654     }
02655
02656     /* Process Locked */
02657     __HAL_LOCK(hi2c);
02658
02659     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02660     hi2c->Mode        = HAL_I2C_MODE_MEM;
02661     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02662
02663     /* Prepare transfer parameters */
02664     hi2c->pBuffPtr    = pData;
02665     hi2c->XferCount   = Size;
02666     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02667     hi2c->XferISR     = I2C_Mem_ISR_IT;
02668     hi2c->Devaddress  = DevAddress;
02669
02670     /* If Memory address size is 8Bit */
02671     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
02672     {
02673       /* Prefetch Memory Address */
02674       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
02675
02676       /* Reset Memaddress content */
02677       hi2c->Memaddress = 0xFFFFFFFFU;
02678     }
02679     /* If Memory address size is 16Bit */
02680     else
02681     {
02682       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
02683       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
02684
02685       /* Prepare Memaddress buffer for LSB part */
02686       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
02687     }
02688     /* Send Slave Address and Memory Address */
02689     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
02690
02691     /* Process Unlocked */
02692     __HAL_UNLOCK(hi2c);
02693
02694     /* Note : The I2C interrupts must be enabled after unlocking current process
02695               to avoid the risk of I2C interrupt handle execution before current
02696               process unlock */
02697
02698     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02699     /* possible to enable all of these */
02700     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
02701       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02702     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02703
02704     return HAL_OK;
02705   }
02706   else
02707   {
02708     return HAL_BUSY;
02709   }
02710 }
02711
02712 /**
02713   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02714   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02715   *                the configuration information for the specified I2C.
02716   * @param  DevAddress Target device address: The device 7 bits address value
02717   *         in datasheet must be shifted to the left before calling the interface
02718   * @param  MemAddress Internal memory address
02719   * @param  MemAddSize Size of internal memory address
02720   * @param  pData Pointer to data buffer
02721   * @param  Size Amount of data to be sent
02722   * @retval HAL status
02723   */
02724 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02725                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02726 {
02727   /* Check the parameters */
02728   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02729
02730   if (hi2c->State == HAL_I2C_STATE_READY)
02731   {
02732     if ((pData == NULL) || (Size == 0U))
02733     {
02734       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02735       return  HAL_ERROR;
02736     }
02737
02738     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02739     {
02740       return HAL_BUSY;
02741     }
02742
02743     /* Process Locked */
02744     __HAL_LOCK(hi2c);
02745
02746     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02747     hi2c->Mode        = HAL_I2C_MODE_MEM;
02748     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02749
02750     /* Prepare transfer parameters */
02751     hi2c->pBuffPtr    = pData;
02752     hi2c->XferCount   = Size;
02753     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02754     hi2c->XferISR     = I2C_Mem_ISR_IT;
02755     hi2c->Devaddress  = DevAddress;
02756
02757     /* If Memory address size is 8Bit */
02758     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
02759     {
02760       /* Prefetch Memory Address */
02761       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
02762
02763       /* Reset Memaddress content */
02764       hi2c->Memaddress = 0xFFFFFFFFU;
02765     }
02766     /* If Memory address size is 16Bit */
02767     else
02768     {
02769       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
02770       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
02771
02772       /* Prepare Memaddress buffer for LSB part */
02773       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
02774     }
02775     /* Send Slave Address and Memory Address */
02776     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
02777
02778     /* Process Unlocked */
02779     __HAL_UNLOCK(hi2c);
02780
02781     /* Note : The I2C interrupts must be enabled after unlocking current process
02782               to avoid the risk of I2C interrupt handle execution before current
02783               process unlock */
02784
02785     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02786     /* possible to enable all of these */
02787     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
02788       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02789     I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
02790
02791     return HAL_OK;
02792   }
02793   else
02794   {
02795     return HAL_BUSY;
02796   }
02797 }
02798 /**
02799   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
02800   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02801   *                the configuration information for the specified I2C.
02802   * @param  DevAddress Target device address: The device 7 bits address value
02803   *         in datasheet must be shifted to the left before calling the interface
02804   * @param  MemAddress Internal memory address
02805   * @param  MemAddSize Size of internal memory address
02806   * @param  pData Pointer to data buffer
02807   * @param  Size Amount of data to be sent
02808   * @retval HAL status
02809   */
02810 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02811                                         uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02812 {
02813   HAL_StatusTypeDef dmaxferstatus;
02814
02815   /* Check the parameters */
02816   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02817
02818   if (hi2c->State == HAL_I2C_STATE_READY)
02819   {
02820     if ((pData == NULL) || (Size == 0U))
02821     {
02822       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02823       return  HAL_ERROR;
02824     }
02825
02826     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02827     {
02828       return HAL_BUSY;
02829     }
02830
02831     /* Process Locked */
02832     __HAL_LOCK(hi2c);
02833
02834     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02835     hi2c->Mode        = HAL_I2C_MODE_MEM;
02836     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02837
02838     /* Prepare transfer parameters */
02839     hi2c->pBuffPtr    = pData;
02840     hi2c->XferCount   = Size;
02841     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02842     hi2c->XferISR     = I2C_Mem_ISR_DMA;
02843     hi2c->Devaddress  = DevAddress;
02844
02845     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02846     {
02847       hi2c->XferSize = MAX_NBYTE_SIZE;
02848     }
02849     else
02850     {
02851       hi2c->XferSize = hi2c->XferCount;
02852     }
02853
02854     /* If Memory address size is 8Bit */
02855     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
02856     {
02857       /* Prefetch Memory Address */
02858       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
02859
02860       /* Reset Memaddress content */
02861       hi2c->Memaddress = 0xFFFFFFFFU;
02862     }
02863     /* If Memory address size is 16Bit */
02864     else
02865     {
02866       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
02867       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
02868
02869       /* Prepare Memaddress buffer for LSB part */
02870       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
02871     }
02872
02873     if (hi2c->hdmatx != NULL)
02874     {
02875       /* Set the I2C DMA transfer complete callback */
02876       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
02877
02878       /* Set the DMA error callback */
02879       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02880
02881       /* Set the unused DMA callbacks to NULL */
02882       hi2c->hdmatx->XferHalfCpltCallback = NULL;
02883       hi2c->hdmatx->XferAbortCallback = NULL;
02884
02885       /* Enable the DMA channel */
02886       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
02887                                        hi2c->XferSize);
02888     }
02889     else
02890     {
02891       /* Update I2C state */
02892       hi2c->State     = HAL_I2C_STATE_READY;
02893       hi2c->Mode      = HAL_I2C_MODE_NONE;
02894
02895       /* Update I2C error code */
02896       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02897
02898       /* Process Unlocked */
02899       __HAL_UNLOCK(hi2c);
02900
02901       return HAL_ERROR;
02902     }
02903
02904     if (dmaxferstatus == HAL_OK)
02905     {
02906       /* Send Slave Address and Memory Address */
02907       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
02908
02909       /* Process Unlocked */
02910       __HAL_UNLOCK(hi2c);
02911
02912       /* Note : The I2C interrupts must be enabled after unlocking current process
02913                 to avoid the risk of I2C interrupt handle execution before current
02914                 process unlock */
02915       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02916       /* possible to enable all of these */
02917       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
02918         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02919       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02920     }
02921     else
02922     {
02923       /* Update I2C state */
02924       hi2c->State     = HAL_I2C_STATE_READY;
02925       hi2c->Mode      = HAL_I2C_MODE_NONE;
02926
02927       /* Update I2C error code */
02928       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02929
02930       /* Process Unlocked */
02931       __HAL_UNLOCK(hi2c);
02932
02933       return HAL_ERROR;
02934     }
02935
02936     return HAL_OK;
02937   }
02938   else
02939   {
02940     return HAL_BUSY;
02941   }
02942 }
02943
02944 /**
02945   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
02946   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02947   *                the configuration information for the specified I2C.
02948   * @param  DevAddress Target device address: The device 7 bits address value
02949   *         in datasheet must be shifted to the left before calling the interface
02950   * @param  MemAddress Internal memory address
02951   * @param  MemAddSize Size of internal memory address
02952   * @param  pData Pointer to data buffer
02953   * @param  Size Amount of data to be read
02954   * @retval HAL status
02955   */
02956 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
02957                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02958 {
02959   HAL_StatusTypeDef dmaxferstatus;
02960
02961   /* Check the parameters */
02962   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02963
02964   if (hi2c->State == HAL_I2C_STATE_READY)
02965   {
02966     if ((pData == NULL) || (Size == 0U))
02967     {
02968       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02969       return  HAL_ERROR;
02970     }
02971
02972     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02973     {
02974       return HAL_BUSY;
02975     }
02976
02977     /* Process Locked */
02978     __HAL_LOCK(hi2c);
02979
02980     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02981     hi2c->Mode        = HAL_I2C_MODE_MEM;
02982     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02983
02984     /* Prepare transfer parameters */
02985     hi2c->pBuffPtr    = pData;
02986     hi2c->XferCount   = Size;
02987     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02988     hi2c->XferISR     = I2C_Mem_ISR_DMA;
02989     hi2c->Devaddress  = DevAddress;
02990
02991     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02992     {
02993       hi2c->XferSize = MAX_NBYTE_SIZE;
02994     }
02995     else
02996     {
02997       hi2c->XferSize = hi2c->XferCount;
02998     }
02999
03000     /* If Memory address size is 8Bit */
03001     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
03002     {
03003       /* Prefetch Memory Address */
03004       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03005
03006       /* Reset Memaddress content */
03007       hi2c->Memaddress = 0xFFFFFFFFU;
03008     }
03009     /* If Memory address size is 16Bit */
03010     else
03011     {
03012       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
03013       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03014
03015       /* Prepare Memaddress buffer for LSB part */
03016       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
03017     }
03018
03019     if (hi2c->hdmarx != NULL)
03020     {
03021       /* Set the I2C DMA transfer complete callback */
03022       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
03023
03024       /* Set the DMA error callback */
03025       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
03026
03027       /* Set the unused DMA callbacks to NULL */
03028       hi2c->hdmarx->XferHalfCpltCallback = NULL;
03029       hi2c->hdmarx->XferAbortCallback = NULL;
03030
03031       /* Enable the DMA channel */
03032       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
03033                                        hi2c->XferSize);
03034     }
03035     else
03036     {
03037       /* Update I2C state */
03038       hi2c->State     = HAL_I2C_STATE_READY;
03039       hi2c->Mode      = HAL_I2C_MODE_NONE;
03040
03041       /* Update I2C error code */
03042       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03043
03044       /* Process Unlocked */
03045       __HAL_UNLOCK(hi2c);
03046
03047       return HAL_ERROR;
03048     }
03049
03050     if (dmaxferstatus == HAL_OK)
03051     {
03052       /* Send Slave Address and Memory Address */
03053       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
03054
03055       /* Process Unlocked */
03056       __HAL_UNLOCK(hi2c);
03057
03058       /* Note : The I2C interrupts must be enabled after unlocking current process
03059                 to avoid the risk of I2C interrupt handle execution before current
03060                 process unlock */
03061       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03062       /* possible to enable all of these */
03063       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03064         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03065       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03066     }
03067     else
03068     {
03069       /* Update I2C state */
03070       hi2c->State     = HAL_I2C_STATE_READY;
03071       hi2c->Mode      = HAL_I2C_MODE_NONE;
03072
03073       /* Update I2C error code */
03074       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03075
03076       /* Process Unlocked */
03077       __HAL_UNLOCK(hi2c);
03078
03079       return HAL_ERROR;
03080     }
03081
03082     return HAL_OK;
03083   }
03084   else
03085   {
03086     return HAL_BUSY;
03087   }
03088 }
03089
03090 /**
03091   * @brief  Checks if target device is ready for communication.
03092   * @note   This function is used with Memory devices
03093   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03094   *                the configuration information for the specified I2C.
03095   * @param  DevAddress Target device address: The device 7 bits address value
03096   *         in datasheet must be shifted to the left before calling the interface
03097   * @param  Trials Number of trials
03098   * @param  Timeout Timeout duration
03099   * @retval HAL status
03100   */
03101 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
03102                                         uint32_t Timeout)
03103 {
03104   uint32_t tickstart;
03105
03106   __IO uint32_t I2C_Trials = 0UL;
03107
03108   FlagStatus tmp1;
03109   FlagStatus tmp2;
03110
03111   if (hi2c->State == HAL_I2C_STATE_READY)
03112   {
03113     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
03114     {
03115       return HAL_BUSY;
03116     }
03117
03118     /* Process Locked */
03119     __HAL_LOCK(hi2c);
03120
03121     hi2c->State = HAL_I2C_STATE_BUSY;
03122     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03123
03124     do
03125     {
03126       /* Generate Start */
03127       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
03128
03129       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03130       /* Wait until STOPF flag is set or a NACK flag is set*/
03131       tickstart = HAL_GetTick();
03132
03133       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03134       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03135
03136       while ((tmp1 == RESET) && (tmp2 == RESET))
03137       {
03138         if (Timeout != HAL_MAX_DELAY)
03139         {
03140           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03141           {
03142             /* Update I2C state */
03143             hi2c->State = HAL_I2C_STATE_READY;
03144
03145             /* Update I2C error code */
03146             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03147
03148             /* Process Unlocked */
03149             __HAL_UNLOCK(hi2c);
03150
03151             return HAL_ERROR;
03152           }
03153         }
03154
03155         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03156         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03157       }
03158
03159       /* Check if the NACKF flag has not been set */
03160       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
03161       {
03162         /* Wait until STOPF flag is reset */
03163         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03164         {
03165           return HAL_ERROR;
03166         }
03167
03168         /* Clear STOP Flag */
03169         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03170
03171         /* Device is ready */
03172         hi2c->State = HAL_I2C_STATE_READY;
03173
03174         /* Process Unlocked */
03175         __HAL_UNLOCK(hi2c);
03176
03177         return HAL_OK;
03178       }
03179       else
03180       {
03181         /* Wait until STOPF flag is reset */
03182         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03183         {
03184           return HAL_ERROR;
03185         }
03186
03187         /* Clear NACK Flag */
03188         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03189
03190         /* Clear STOP Flag, auto generated with autoend*/
03191         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03192       }
03193
03194       /* Check if the maximum allowed number of trials has been reached */
03195       if (I2C_Trials == Trials)
03196       {
03197         /* Generate Stop */
03198         hi2c->Instance->CR2 |= I2C_CR2_STOP;
03199
03200         /* Wait until STOPF flag is reset */
03201         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03202         {
03203           return HAL_ERROR;
03204         }
03205
03206         /* Clear STOP Flag */
03207         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03208       }
03209
03210       /* Increment Trials */
03211       I2C_Trials++;
03212     } while (I2C_Trials < Trials);
03213
03214     /* Update I2C state */
03215     hi2c->State = HAL_I2C_STATE_READY;
03216
03217     /* Update I2C error code */
03218     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03219
03220     /* Process Unlocked */
03221     __HAL_UNLOCK(hi2c);
03222
03223     return HAL_ERROR;
03224   }
03225   else
03226   {
03227     return HAL_BUSY;
03228   }
03229 }
03230
03231 /**
03232   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
03233   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03234   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03235   *                the configuration information for the specified I2C.
03236   * @param  DevAddress Target device address: The device 7 bits address value
03237   *         in datasheet must be shifted to the left before calling the interface
03238   * @param  pData Pointer to data buffer
03239   * @param  Size Amount of data to be sent
03240   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03241   * @retval HAL status
03242   */
03243 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
03244                                                  uint16_t Size, uint32_t XferOptions)
03245 {
03246   uint32_t xfermode;
03247   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
03248
03249   /* Check the parameters */
03250   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03251
03252   if (hi2c->State == HAL_I2C_STATE_READY)
03253   {
03254     /* Process Locked */
03255     __HAL_LOCK(hi2c);
03256
03257     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03258     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03259     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03260
03261     /* Prepare transfer parameters */
03262     hi2c->pBuffPtr    = pData;
03263     hi2c->XferCount   = Size;
03264     hi2c->XferOptions = XferOptions;
03265     hi2c->XferISR     = I2C_Master_ISR_IT;
03266
03267     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03268     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03269     {
03270       hi2c->XferSize = MAX_NBYTE_SIZE;
03271       xfermode = I2C_RELOAD_MODE;
03272     }
03273     else
03274     {
03275       hi2c->XferSize = hi2c->XferCount;
03276       xfermode = hi2c->XferOptions;
03277     }
03278
03279     /* If transfer direction not change and there is no request to start another frame,
03280        do not generate Restart Condition */
03281     /* Mean Previous state is same as current state */
03282     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
03283         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03284     {
03285       xferrequest = I2C_NO_STARTSTOP;
03286     }
03287     else
03288     {
03289       /* Convert OTHER_xxx XferOptions if any */
03290       I2C_ConvertOtherXferOptions(hi2c);
03291
03292       /* Update xfermode accordingly if no reload is necessary */
03293       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
03294       {
03295         xfermode = hi2c->XferOptions;
03296       }
03297     }
03298
03299     /* Send Slave Address and set NBYTES to write */
03300     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03301
03302     /* Process Unlocked */
03303     __HAL_UNLOCK(hi2c);
03304
03305     /* Note : The I2C interrupts must be enabled after unlocking current process
03306               to avoid the risk of I2C interrupt handle execution before current
03307               process unlock */
03308     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03309     /* possible to enable all of these */
03310     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03311        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03312     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03313
03314     return HAL_OK;
03315   }
03316   else
03317   {
03318     return HAL_BUSY;
03319   }
03320 }
03321
03322 /**
03323   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
03324   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03325   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03326   *                the configuration information for the specified I2C.
03327   * @param  DevAddress Target device address: The device 7 bits address value
03328   *         in datasheet must be shifted to the left before calling the interface
03329   * @param  pData Pointer to data buffer
03330   * @param  Size Amount of data to be sent
03331   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03332   * @retval HAL status
03333   */
03334 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
03335                                                   uint16_t Size, uint32_t XferOptions)
03336 {
03337   uint32_t xfermode;
03338   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
03339   HAL_StatusTypeDef dmaxferstatus;
03340
03341   /* Check the parameters */
03342   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03343
03344   if (hi2c->State == HAL_I2C_STATE_READY)
03345   {
03346     /* Process Locked */
03347     __HAL_LOCK(hi2c);
03348
03349     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03350     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03351     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03352
03353     /* Prepare transfer parameters */
03354     hi2c->pBuffPtr    = pData;
03355     hi2c->XferCount   = Size;
03356     hi2c->XferOptions = XferOptions;
03357     hi2c->XferISR     = I2C_Master_ISR_DMA;
03358
03359     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03360     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03361     {
03362       hi2c->XferSize = MAX_NBYTE_SIZE;
03363       xfermode = I2C_RELOAD_MODE;
03364     }
03365     else
03366     {
03367       hi2c->XferSize = hi2c->XferCount;
03368       xfermode = hi2c->XferOptions;
03369     }
03370
03371     /* If transfer direction not change and there is no request to start another frame,
03372        do not generate Restart Condition */
03373     /* Mean Previous state is same as current state */
03374     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
03375         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03376     {
03377       xferrequest = I2C_NO_STARTSTOP;
03378     }
03379     else
03380     {
03381       /* Convert OTHER_xxx XferOptions if any */
03382       I2C_ConvertOtherXferOptions(hi2c);
03383
03384       /* Update xfermode accordingly if no reload is necessary */
03385       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
03386       {
03387         xfermode = hi2c->XferOptions;
03388       }
03389     }
03390
03391     if (hi2c->XferSize > 0U)
03392     {
03393       if (hi2c->hdmatx != NULL)
03394       {
03395         /* Set the I2C DMA transfer complete callback */
03396         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
03397
03398         /* Set the DMA error callback */
03399         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03400
03401         /* Set the unused DMA callbacks to NULL */
03402         hi2c->hdmatx->XferHalfCpltCallback = NULL;
03403         hi2c->hdmatx->XferAbortCallback = NULL;
03404
03405         /* Enable the DMA channel */
03406         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
03407                                          hi2c->XferSize);
03408       }
03409       else
03410       {
03411         /* Update I2C state */
03412         hi2c->State     = HAL_I2C_STATE_READY;
03413         hi2c->Mode      = HAL_I2C_MODE_NONE;
03414
03415         /* Update I2C error code */
03416         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03417
03418         /* Process Unlocked */
03419         __HAL_UNLOCK(hi2c);
03420
03421         return HAL_ERROR;
03422       }
03423
03424       if (dmaxferstatus == HAL_OK)
03425       {
03426         /* Send Slave Address and set NBYTES to write */
03427         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03428
03429         /* Update XferCount value */
03430         hi2c->XferCount -= hi2c->XferSize;
03431
03432         /* Process Unlocked */
03433         __HAL_UNLOCK(hi2c);
03434
03435         /* Note : The I2C interrupts must be enabled after unlocking current process
03436                   to avoid the risk of I2C interrupt handle execution before current
03437                   process unlock */
03438         /* Enable ERR and NACK interrupts */
03439         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
03440
03441         /* Enable DMA Request */
03442         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03443       }
03444       else
03445       {
03446         /* Update I2C state */
03447         hi2c->State     = HAL_I2C_STATE_READY;
03448         hi2c->Mode      = HAL_I2C_MODE_NONE;
03449
03450         /* Update I2C error code */
03451         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03452
03453         /* Process Unlocked */
03454         __HAL_UNLOCK(hi2c);
03455
03456         return HAL_ERROR;
03457       }
03458     }
03459     else
03460     {
03461       /* Update Transfer ISR function pointer */
03462       hi2c->XferISR = I2C_Master_ISR_IT;
03463
03464       /* Send Slave Address */
03465       /* Set NBYTES to write and generate START condition */
03466       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
03467                          I2C_GENERATE_START_WRITE);
03468
03469       /* Process Unlocked */
03470       __HAL_UNLOCK(hi2c);
03471
03472       /* Note : The I2C interrupts must be enabled after unlocking current process
03473                 to avoid the risk of I2C interrupt handle execution before current
03474                 process unlock */
03475       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03476       /* possible to enable all of these */
03477       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03478         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03479       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03480     }
03481
03482     return HAL_OK;
03483   }
03484   else
03485   {
03486     return HAL_BUSY;
03487   }
03488 }
03489
03490 /**
03491   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
03492   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03493   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03494   *                the configuration information for the specified I2C.
03495   * @param  DevAddress Target device address: The device 7 bits address value
03496   *         in datasheet must be shifted to the left before calling the interface
03497   * @param  pData Pointer to data buffer
03498   * @param  Size Amount of data to be sent
03499   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03500   * @retval HAL status
03501   */
03502 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
03503                                                 uint16_t Size, uint32_t XferOptions)
03504 {
03505   uint32_t xfermode;
03506   uint32_t xferrequest = I2C_GENERATE_START_READ;
03507
03508   /* Check the parameters */
03509   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03510
03511   if (hi2c->State == HAL_I2C_STATE_READY)
03512   {
03513     /* Process Locked */
03514     __HAL_LOCK(hi2c);
03515
03516     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03517     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03518     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03519
03520     /* Prepare transfer parameters */
03521     hi2c->pBuffPtr    = pData;
03522     hi2c->XferCount   = Size;
03523     hi2c->XferOptions = XferOptions;
03524     hi2c->XferISR     = I2C_Master_ISR_IT;
03525
03526     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03527     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03528     {
03529       hi2c->XferSize = MAX_NBYTE_SIZE;
03530       xfermode = I2C_RELOAD_MODE;
03531     }
03532     else
03533     {
03534       hi2c->XferSize = hi2c->XferCount;
03535       xfermode = hi2c->XferOptions;
03536     }
03537
03538     /* If transfer direction not change and there is no request to start another frame,
03539        do not generate Restart Condition */
03540     /* Mean Previous state is same as current state */
03541     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
03542         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03543     {
03544       xferrequest = I2C_NO_STARTSTOP;
03545     }
03546     else
03547     {
03548       /* Convert OTHER_xxx XferOptions if any */
03549       I2C_ConvertOtherXferOptions(hi2c);
03550
03551       /* Update xfermode accordingly if no reload is necessary */
03552       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
03553       {
03554         xfermode = hi2c->XferOptions;
03555       }
03556     }
03557
03558     /* Send Slave Address and set NBYTES to read */
03559     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03560
03561     /* Process Unlocked */
03562     __HAL_UNLOCK(hi2c);
03563
03564     /* Note : The I2C interrupts must be enabled after unlocking current process
03565               to avoid the risk of I2C interrupt handle execution before current
03566               process unlock */
03567     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
03568
03569     return HAL_OK;
03570   }
03571   else
03572   {
03573     return HAL_BUSY;
03574   }
03575 }
03576
03577 /**
03578   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
03579   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03580   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03581   *                the configuration information for the specified I2C.
03582   * @param  DevAddress Target device address: The device 7 bits address value
03583   *         in datasheet must be shifted to the left before calling the interface
03584   * @param  pData Pointer to data buffer
03585   * @param  Size Amount of data to be sent
03586   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03587   * @retval HAL status
03588   */
03589 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
03590                                                  uint16_t Size, uint32_t XferOptions)
03591 {
03592   uint32_t xfermode;
03593   uint32_t xferrequest = I2C_GENERATE_START_READ;
03594   HAL_StatusTypeDef dmaxferstatus;
03595
03596   /* Check the parameters */
03597   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03598
03599   if (hi2c->State == HAL_I2C_STATE_READY)
03600   {
03601     /* Process Locked */
03602     __HAL_LOCK(hi2c);
03603
03604     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03605     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03606     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03607
03608     /* Prepare transfer parameters */
03609     hi2c->pBuffPtr    = pData;
03610     hi2c->XferCount   = Size;
03611     hi2c->XferOptions = XferOptions;
03612     hi2c->XferISR     = I2C_Master_ISR_DMA;
03613
03614     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03615     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03616     {
03617       hi2c->XferSize = MAX_NBYTE_SIZE;
03618       xfermode = I2C_RELOAD_MODE;
03619     }
03620     else
03621     {
03622       hi2c->XferSize = hi2c->XferCount;
03623       xfermode = hi2c->XferOptions;
03624     }
03625
03626     /* If transfer direction not change and there is no request to start another frame,
03627        do not generate Restart Condition */
03628     /* Mean Previous state is same as current state */
03629     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
03630         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03631     {
03632       xferrequest = I2C_NO_STARTSTOP;
03633     }
03634     else
03635     {
03636       /* Convert OTHER_xxx XferOptions if any */
03637       I2C_ConvertOtherXferOptions(hi2c);
03638
03639       /* Update xfermode accordingly if no reload is necessary */
03640       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
03641       {
03642         xfermode = hi2c->XferOptions;
03643       }
03644     }
03645
03646     if (hi2c->XferSize > 0U)
03647     {
03648       if (hi2c->hdmarx != NULL)
03649       {
03650         /* Set the I2C DMA transfer complete callback */
03651         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
03652
03653         /* Set the DMA error callback */
03654         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
03655
03656         /* Set the unused DMA callbacks to NULL */
03657         hi2c->hdmarx->XferHalfCpltCallback = NULL;
03658         hi2c->hdmarx->XferAbortCallback = NULL;
03659
03660         /* Enable the DMA channel */
03661         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
03662                                          hi2c->XferSize);
03663       }
03664       else
03665       {
03666         /* Update I2C state */
03667         hi2c->State     = HAL_I2C_STATE_READY;
03668         hi2c->Mode      = HAL_I2C_MODE_NONE;
03669
03670         /* Update I2C error code */
03671         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03672
03673         /* Process Unlocked */
03674         __HAL_UNLOCK(hi2c);
03675
03676         return HAL_ERROR;
03677       }
03678
03679       if (dmaxferstatus == HAL_OK)
03680       {
03681         /* Send Slave Address and set NBYTES to read */
03682         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03683
03684         /* Update XferCount value */
03685         hi2c->XferCount -= hi2c->XferSize;
03686
03687         /* Process Unlocked */
03688         __HAL_UNLOCK(hi2c);
03689
03690         /* Note : The I2C interrupts must be enabled after unlocking current process
03691                   to avoid the risk of I2C interrupt handle execution before current
03692                   process unlock */
03693         /* Enable ERR and NACK interrupts */
03694         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
03695
03696         /* Enable DMA Request */
03697         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03698       }
03699       else
03700       {
03701         /* Update I2C state */
03702         hi2c->State     = HAL_I2C_STATE_READY;
03703         hi2c->Mode      = HAL_I2C_MODE_NONE;
03704
03705         /* Update I2C error code */
03706         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03707
03708         /* Process Unlocked */
03709         __HAL_UNLOCK(hi2c);
03710
03711         return HAL_ERROR;
03712       }
03713     }
03714     else
03715     {
03716       /* Update Transfer ISR function pointer */
03717       hi2c->XferISR = I2C_Master_ISR_IT;
03718
03719       /* Send Slave Address */
03720       /* Set NBYTES to read and generate START condition */
03721       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
03722                          I2C_GENERATE_START_READ);
03723
03724       /* Process Unlocked */
03725       __HAL_UNLOCK(hi2c);
03726
03727       /* Note : The I2C interrupts must be enabled after unlocking current process
03728                 to avoid the risk of I2C interrupt handle execution before current
03729                 process unlock */
03730       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03731       /* possible to enable all of these */
03732       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
03733         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03734       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03735     }
03736
03737     return HAL_OK;
03738   }
03739   else
03740   {
03741     return HAL_BUSY;
03742   }
03743 }
03744
03745 /**
03746   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
03747   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03748   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03749   *                the configuration information for the specified I2C.
03750   * @param  pData Pointer to data buffer
03751   * @param  Size Amount of data to be sent
03752   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03753   * @retval HAL status
03754   */
03755 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
03756                                                 uint32_t XferOptions)
03757 {
03758   /* Declaration of tmp to prevent undefined behavior of volatile usage */
03759   FlagStatus tmp;
03760
03761   /* Check the parameters */
03762   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03763
03764   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03765   {
03766     if ((pData == NULL) || (Size == 0U))
03767     {
03768       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03769       return  HAL_ERROR;
03770     }
03771
03772     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03773     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
03774
03775     /* Process Locked */
03776     __HAL_LOCK(hi2c);
03777
03778     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03779     /* and then toggle the HAL slave RX state to TX state */
03780     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03781     {
03782       /* Disable associated Interrupts */
03783       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03784
03785       /* Abort DMA Xfer if any */
03786       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
03787       {
03788         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03789
03790         if (hi2c->hdmarx != NULL)
03791         {
03792           /* Set the I2C DMA Abort callback :
03793            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03794           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
03795
03796           /* Abort DMA RX */
03797           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
03798           {
03799             /* Call Directly XferAbortCallback function in case of error */
03800             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
03801           }
03802         }
03803       }
03804     }
03805
03806     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
03807     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03808     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03809
03810     /* Enable Address Acknowledge */
03811     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03812
03813     /* Prepare transfer parameters */
03814     hi2c->pBuffPtr    = pData;
03815     hi2c->XferCount   = Size;
03816     hi2c->XferSize    = hi2c->XferCount;
03817     hi2c->XferOptions = XferOptions;
03818     hi2c->XferISR     = I2C_Slave_ISR_IT;
03819
03820     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
03821     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
03822     {
03823       /* Clear ADDR flag after prepare the transfer parameters */
03824       /* This action will generate an acknowledge to the Master */
03825       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03826     }
03827
03828     /* Process Unlocked */
03829     __HAL_UNLOCK(hi2c);
03830
03831     /* Note : The I2C interrupts must be enabled after unlocking current process
03832     to avoid the risk of I2C interrupt handle execution before current
03833     process unlock */
03834     /* REnable ADDR interrupt */
03835     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
03836
03837     return HAL_OK;
03838   }
03839   else
03840   {
03841     return HAL_ERROR;
03842   }
03843 }
03844
03845 /**
03846   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
03847   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03848   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03849   *                the configuration information for the specified I2C.
03850   * @param  pData Pointer to data buffer
03851   * @param  Size Amount of data to be sent
03852   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03853   * @retval HAL status
03854   */
03855 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
03856                                                  uint32_t XferOptions)
03857 {
03858   /* Declaration of tmp to prevent undefined behavior of volatile usage */
03859   FlagStatus tmp;
03860   HAL_StatusTypeDef dmaxferstatus;
03861
03862   /* Check the parameters */
03863   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03864
03865   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03866   {
03867     if ((pData == NULL) || (Size == 0U))
03868     {
03869       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03870       return  HAL_ERROR;
03871     }
03872
03873     /* Process Locked */
03874     __HAL_LOCK(hi2c);
03875
03876     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03877     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
03878
03879     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03880     /* and then toggle the HAL slave RX state to TX state */
03881     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03882     {
03883       /* Disable associated Interrupts */
03884       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03885
03886       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
03887       {
03888         /* Abort DMA Xfer if any */
03889         if (hi2c->hdmarx != NULL)
03890         {
03891           hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03892
03893           /* Set the I2C DMA Abort callback :
03894            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03895           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
03896
03897           /* Abort DMA RX */
03898           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
03899           {
03900             /* Call Directly XferAbortCallback function in case of error */
03901             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
03902           }
03903         }
03904       }
03905     }
03906     else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03907     {
03908       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
03909       {
03910         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03911
03912         /* Abort DMA Xfer if any */
03913         if (hi2c->hdmatx != NULL)
03914         {
03915           /* Set the I2C DMA Abort callback :
03916            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03917           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
03918
03919           /* Abort DMA TX */
03920           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
03921           {
03922             /* Call Directly XferAbortCallback function in case of error */
03923             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
03924           }
03925         }
03926       }
03927     }
03928     else
03929     {
03930       /* Nothing to do */
03931     }
03932
03933     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
03934     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03935     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03936
03937     /* Enable Address Acknowledge */
03938     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03939
03940     /* Prepare transfer parameters */
03941     hi2c->pBuffPtr    = pData;
03942     hi2c->XferCount   = Size;
03943     hi2c->XferSize    = hi2c->XferCount;
03944     hi2c->XferOptions = XferOptions;
03945     hi2c->XferISR     = I2C_Slave_ISR_DMA;
03946
03947     if (hi2c->hdmatx != NULL)
03948     {
03949       /* Set the I2C DMA transfer complete callback */
03950       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
03951
03952       /* Set the DMA error callback */
03953       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03954
03955       /* Set the unused DMA callbacks to NULL */
03956       hi2c->hdmatx->XferHalfCpltCallback = NULL;
03957       hi2c->hdmatx->XferAbortCallback = NULL;
03958
03959       /* Enable the DMA channel */
03960       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
03961                                        hi2c->XferSize);
03962     }
03963     else
03964     {
03965       /* Update I2C state */
03966       hi2c->State     = HAL_I2C_STATE_LISTEN;
03967       hi2c->Mode      = HAL_I2C_MODE_NONE;
03968
03969       /* Update I2C error code */
03970       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03971
03972       /* Process Unlocked */
03973       __HAL_UNLOCK(hi2c);
03974
03975       return HAL_ERROR;
03976     }
03977
03978     if (dmaxferstatus == HAL_OK)
03979     {
03980       /* Update XferCount value */
03981       hi2c->XferCount -= hi2c->XferSize;
03982
03983       /* Reset XferSize */
03984       hi2c->XferSize = 0;
03985     }
03986     else
03987     {
03988       /* Update I2C state */
03989       hi2c->State     = HAL_I2C_STATE_LISTEN;
03990       hi2c->Mode      = HAL_I2C_MODE_NONE;
03991
03992       /* Update I2C error code */
03993       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03994
03995       /* Process Unlocked */
03996       __HAL_UNLOCK(hi2c);
03997
03998       return HAL_ERROR;
03999     }
04000
04001     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
04002     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
04003     {
04004       /* Clear ADDR flag after prepare the transfer parameters */
04005       /* This action will generate an acknowledge to the Master */
04006       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04007     }
04008
04009     /* Process Unlocked */
04010     __HAL_UNLOCK(hi2c);
04011
04012     /* Enable DMA Request */
04013     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
04014
04015     /* Note : The I2C interrupts must be enabled after unlocking current process
04016     to avoid the risk of I2C interrupt handle execution before current
04017     process unlock */
04018     /* Enable ERR, STOP, NACK, ADDR interrupts */
04019     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04020
04021     return HAL_OK;
04022   }
04023   else
04024   {
04025     return HAL_ERROR;
04026   }
04027 }
04028
04029 /**
04030   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
04031   * @note   This interface allow to manage repeated start condition when a direction change during transfer
04032   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04033   *                the configuration information for the specified I2C.
04034   * @param  pData Pointer to data buffer
04035   * @param  Size Amount of data to be sent
04036   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
04037   * @retval HAL status
04038   */
04039 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
04040                                                uint32_t XferOptions)
04041 {
04042   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04043   FlagStatus tmp;
04044
04045   /* Check the parameters */
04046   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
04047
04048   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
04049   {
04050     if ((pData == NULL) || (Size == 0U))
04051     {
04052       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
04053       return  HAL_ERROR;
04054     }
04055
04056     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
04057     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
04058
04059     /* Process Locked */
04060     __HAL_LOCK(hi2c);
04061
04062     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
04063     /* and then toggle the HAL slave TX state to RX state */
04064     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
04065     {
04066       /* Disable associated Interrupts */
04067       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04068
04069       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04070       {
04071         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04072
04073         /* Abort DMA Xfer if any */
04074         if (hi2c->hdmatx != NULL)
04075         {
04076           /* Set the I2C DMA Abort callback :
04077            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04078           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04079
04080           /* Abort DMA TX */
04081           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04082           {
04083             /* Call Directly XferAbortCallback function in case of error */
04084             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04085           }
04086         }
04087       }
04088     }
04089
04090     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
04091     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
04092     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04093
04094     /* Enable Address Acknowledge */
04095     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
04096
04097     /* Prepare transfer parameters */
04098     hi2c->pBuffPtr    = pData;
04099     hi2c->XferCount   = Size;
04100     hi2c->XferSize    = hi2c->XferCount;
04101     hi2c->XferOptions = XferOptions;
04102     hi2c->XferISR     = I2C_Slave_ISR_IT;
04103
04104     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
04105     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
04106     {
04107       /* Clear ADDR flag after prepare the transfer parameters */
04108       /* This action will generate an acknowledge to the Master */
04109       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04110     }
04111
04112     /* Process Unlocked */
04113     __HAL_UNLOCK(hi2c);
04114
04115     /* Note : The I2C interrupts must be enabled after unlocking current process
04116     to avoid the risk of I2C interrupt handle execution before current
04117     process unlock */
04118     /* REnable ADDR interrupt */
04119     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
04120
04121     return HAL_OK;
04122   }
04123   else
04124   {
04125     return HAL_ERROR;
04126   }
04127 }
04128
04129 /**
04130   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
04131   * @note   This interface allow to manage repeated start condition when a direction change during transfer
04132   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04133   *                the configuration information for the specified I2C.
04134   * @param  pData Pointer to data buffer
04135   * @param  Size Amount of data to be sent
04136   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
04137   * @retval HAL status
04138   */
04139 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
04140                                                 uint32_t XferOptions)
04141 {
04142   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04143   FlagStatus tmp;
04144   HAL_StatusTypeDef dmaxferstatus;
04145
04146   /* Check the parameters */
04147   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
04148
04149   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
04150   {
04151     if ((pData == NULL) || (Size == 0U))
04152     {
04153       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
04154       return  HAL_ERROR;
04155     }
04156
04157     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
04158     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
04159
04160     /* Process Locked */
04161     __HAL_LOCK(hi2c);
04162
04163     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
04164     /* and then toggle the HAL slave TX state to RX state */
04165     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
04166     {
04167       /* Disable associated Interrupts */
04168       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04169
04170       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04171       {
04172         /* Abort DMA Xfer if any */
04173         if (hi2c->hdmatx != NULL)
04174         {
04175           hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04176
04177           /* Set the I2C DMA Abort callback :
04178            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04179           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04180
04181           /* Abort DMA TX */
04182           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04183           {
04184             /* Call Directly XferAbortCallback function in case of error */
04185             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04186           }
04187         }
04188       }
04189     }
04190     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
04191     {
04192       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04193       {
04194         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04195
04196         /* Abort DMA Xfer if any */
04197         if (hi2c->hdmarx != NULL)
04198         {
04199           /* Set the I2C DMA Abort callback :
04200            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04201           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04202
04203           /* Abort DMA RX */
04204           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04205           {
04206             /* Call Directly XferAbortCallback function in case of error */
04207             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04208           }
04209         }
04210       }
04211     }
04212     else
04213     {
04214       /* Nothing to do */
04215     }
04216
04217     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
04218     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
04219     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04220
04221     /* Enable Address Acknowledge */
04222     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
04223
04224     /* Prepare transfer parameters */
04225     hi2c->pBuffPtr    = pData;
04226     hi2c->XferCount   = Size;
04227     hi2c->XferSize    = hi2c->XferCount;
04228     hi2c->XferOptions = XferOptions;
04229     hi2c->XferISR     = I2C_Slave_ISR_DMA;
04230
04231     if (hi2c->hdmarx != NULL)
04232     {
04233       /* Set the I2C DMA transfer complete callback */
04234       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
04235
04236       /* Set the DMA error callback */
04237       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
04238
04239       /* Set the unused DMA callbacks to NULL */
04240       hi2c->hdmarx->XferHalfCpltCallback = NULL;
04241       hi2c->hdmarx->XferAbortCallback = NULL;
04242
04243       /* Enable the DMA channel */
04244       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
04245                                        (uint32_t)pData, hi2c->XferSize);
04246     }
04247     else
04248     {
04249       /* Update I2C state */
04250       hi2c->State     = HAL_I2C_STATE_LISTEN;
04251       hi2c->Mode      = HAL_I2C_MODE_NONE;
04252
04253       /* Update I2C error code */
04254       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
04255
04256       /* Process Unlocked */
04257       __HAL_UNLOCK(hi2c);
04258
04259       return HAL_ERROR;
04260     }
04261
04262     if (dmaxferstatus == HAL_OK)
04263     {
04264       /* Update XferCount value */
04265       hi2c->XferCount -= hi2c->XferSize;
04266
04267       /* Reset XferSize */
04268       hi2c->XferSize = 0;
04269     }
04270     else
04271     {
04272       /* Update I2C state */
04273       hi2c->State     = HAL_I2C_STATE_LISTEN;
04274       hi2c->Mode      = HAL_I2C_MODE_NONE;
04275
04276       /* Update I2C error code */
04277       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
04278
04279       /* Process Unlocked */
04280       __HAL_UNLOCK(hi2c);
04281
04282       return HAL_ERROR;
04283     }
04284
04285     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
04286     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
04287     {
04288       /* Clear ADDR flag after prepare the transfer parameters */
04289       /* This action will generate an acknowledge to the Master */
04290       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04291     }
04292
04293     /* Process Unlocked */
04294     __HAL_UNLOCK(hi2c);
04295
04296     /* Enable DMA Request */
04297     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
04298
04299     /* Note : The I2C interrupts must be enabled after unlocking current process
04300     to avoid the risk of I2C interrupt handle execution before current
04301     process unlock */
04302     /* REnable ADDR interrupt */
04303     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
04304
04305     return HAL_OK;
04306   }
04307   else
04308   {
04309     return HAL_ERROR;
04310   }
04311 }
04312
04313 /**
04314   * @brief  Enable the Address listen mode with Interrupt.
04315   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04316   *                the configuration information for the specified I2C.
04317   * @retval HAL status
04318   */
04319 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
04320 {
04321   if (hi2c->State == HAL_I2C_STATE_READY)
04322   {
04323     hi2c->State = HAL_I2C_STATE_LISTEN;
04324     hi2c->XferISR = I2C_Slave_ISR_IT;
04325
04326     /* Enable the Address Match interrupt */
04327     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04328
04329     return HAL_OK;
04330   }
04331   else
04332   {
04333     return HAL_BUSY;
04334   }
04335 }
04336
04337 /**
04338   * @brief  Disable the Address listen mode with Interrupt.
04339   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04340   *                the configuration information for the specified I2C
04341   * @retval HAL status
04342   */
04343 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
04344 {
04345   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04346   uint32_t tmp;
04347
04348   /* Disable Address listen mode only if a transfer is not ongoing */
04349   if (hi2c->State == HAL_I2C_STATE_LISTEN)
04350   {
04351     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
04352     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
04353     hi2c->State = HAL_I2C_STATE_READY;
04354     hi2c->Mode = HAL_I2C_MODE_NONE;
04355     hi2c->XferISR = NULL;
04356
04357     /* Disable the Address Match interrupt */
04358     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04359
04360     return HAL_OK;
04361   }
04362   else
04363   {
04364     return HAL_BUSY;
04365   }
04366 }
04367
04368 /**
04369   * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
04370   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04371   *                the configuration information for the specified I2C.
04372   * @param  DevAddress Target device address: The device 7 bits address value
04373   *         in datasheet must be shifted to the left before calling the interface
04374   * @retval HAL status
04375   */
04376 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
04377 {
04378   if (hi2c->Mode == HAL_I2C_MODE_MASTER)
04379   {
04380     /* Process Locked */
04381     __HAL_LOCK(hi2c);
04382
04383     /* Disable Interrupts and Store Previous state */
04384     if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
04385     {
04386       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04387       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
04388     }
04389     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
04390     {
04391       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
04392       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
04393     }
04394     else
04395     {
04396       /* Do nothing */
04397     }
04398
04399     /* Set State at HAL_I2C_STATE_ABORT */
04400     hi2c->State = HAL_I2C_STATE_ABORT;
04401
04402     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
04403     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
04404     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
04405
04406     /* Process Unlocked */
04407     __HAL_UNLOCK(hi2c);
04408
04409     /* Note : The I2C interrupts must be enabled after unlocking current process
04410               to avoid the risk of I2C interrupt handle execution before current
04411               process unlock */
04412     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04413
04414     return HAL_OK;
04415   }
04416   else
04417   {
04418     /* Wrong usage of abort function */
04419     /* This function should be used only in case of abort monitored by master device */
04420     return HAL_ERROR;
04421   }
04422 }
04423
04424 /**
04425   * @}
04426   */
04427
04428 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
04429   * @{
04430   */
04431
04432 /**
04433   * @brief  This function handles I2C event interrupt request.
04434   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04435   *                the configuration information for the specified I2C.
04436   * @retval None
04437   */
04438 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
04439 {
04440   /* Get current IT Flags and IT sources value */
04441   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
04442   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
04443
04444   /* I2C events treatment -------------------------------------*/
04445   if (hi2c->XferISR != NULL)
04446   {
04447     hi2c->XferISR(hi2c, itflags, itsources);
04448   }
04449 }
04450
04451 /**
04452   * @brief  This function handles I2C error interrupt request.
04453   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04454   *                the configuration information for the specified I2C.
04455   * @retval None
04456   */
04457 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
04458 {
04459   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
04460   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
04461   uint32_t tmperror;
04462
04463   /* I2C Bus error interrupt occurred ------------------------------------*/
04464   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
04465       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04466   {
04467     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
04468
04469     /* Clear BERR flag */
04470     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
04471   }
04472
04473   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
04474   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
04475       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04476   {
04477     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
04478
04479     /* Clear OVR flag */
04480     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
04481   }
04482
04483   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
04484   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
04485       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04486   {
04487     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
04488
04489     /* Clear ARLO flag */
04490     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
04491   }
04492
04493   /* Store current volatile hi2c->ErrorCode, misra rule */
04494   tmperror = hi2c->ErrorCode;
04495
04496   /* Call the Error Callback in case of Error detected */
04497   if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
04498   {
04499     I2C_ITError(hi2c, tmperror);
04500   }
04501 }
04502
04503 /**
04504   * @brief  Master Tx Transfer completed callback.
04505   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04506   *                the configuration information for the specified I2C.
04507   * @retval None
04508   */
04509 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
04510 {
04511   /* Prevent unused argument(s) compilation warning */
04512   UNUSED(hi2c);
04513
04514   /* NOTE : This function should not be modified, when the callback is needed,
04515             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
04516    */
04517 }
04518
04519 /**
04520   * @brief  Master Rx Transfer completed callback.
04521   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04522   *                the configuration information for the specified I2C.
04523   * @retval None
04524   */
04525 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
04526 {
04527   /* Prevent unused argument(s) compilation warning */
04528   UNUSED(hi2c);
04529
04530   /* NOTE : This function should not be modified, when the callback is needed,
04531             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
04532    */
04533 }
04534
04535 /** @brief  Slave Tx Transfer completed callback.
04536   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04537   *                the configuration information for the specified I2C.
04538   * @retval None
04539   */
04540 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
04541 {
04542   /* Prevent unused argument(s) compilation warning */
04543   UNUSED(hi2c);
04544
04545   /* NOTE : This function should not be modified, when the callback is needed,
04546             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
04547    */
04548 }
04549
04550 /**
04551   * @brief  Slave Rx Transfer completed callback.
04552   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04553   *                the configuration information for the specified I2C.
04554   * @retval None
04555   */
04556 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
04557 {
04558   /* Prevent unused argument(s) compilation warning */
04559   UNUSED(hi2c);
04560
04561   /* NOTE : This function should not be modified, when the callback is needed,
04562             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
04563    */
04564 }
04565
04566 /**
04567   * @brief  Slave Address Match callback.
04568   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04569   *                the configuration information for the specified I2C.
04570   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
04571   * @param  AddrMatchCode Address Match Code
04572   * @retval None
04573   */
04574 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
04575 {
04576   /* Prevent unused argument(s) compilation warning */
04577   UNUSED(hi2c);
04578   UNUSED(TransferDirection);
04579   UNUSED(AddrMatchCode);
04580
04581   /* NOTE : This function should not be modified, when the callback is needed,
04582             the HAL_I2C_AddrCallback() could be implemented in the user file
04583    */
04584 }
04585
04586 /**
04587   * @brief  Listen Complete callback.
04588   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04589   *                the configuration information for the specified I2C.
04590   * @retval None
04591   */
04592 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
04593 {
04594   /* Prevent unused argument(s) compilation warning */
04595   UNUSED(hi2c);
04596
04597   /* NOTE : This function should not be modified, when the callback is needed,
04598             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
04599    */
04600 }
04601
04602 /**
04603   * @brief  Memory Tx Transfer completed callback.
04604   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04605   *                the configuration information for the specified I2C.
04606   * @retval None
04607   */
04608 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
04609 {
04610   /* Prevent unused argument(s) compilation warning */
04611   UNUSED(hi2c);
04612
04613   /* NOTE : This function should not be modified, when the callback is needed,
04614             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
04615    */
04616 }
04617
04618 /**
04619   * @brief  Memory Rx Transfer completed callback.
04620   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04621   *                the configuration information for the specified I2C.
04622   * @retval None
04623   */
04624 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
04625 {
04626   /* Prevent unused argument(s) compilation warning */
04627   UNUSED(hi2c);
04628
04629   /* NOTE : This function should not be modified, when the callback is needed,
04630             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
04631    */
04632 }
04633
04634 /**
04635   * @brief  I2C error callback.
04636   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04637   *                the configuration information for the specified I2C.
04638   * @retval None
04639   */
04640 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
04641 {
04642   /* Prevent unused argument(s) compilation warning */
04643   UNUSED(hi2c);
04644
04645   /* NOTE : This function should not be modified, when the callback is needed,
04646             the HAL_I2C_ErrorCallback could be implemented in the user file
04647    */
04648 }
04649
04650 /**
04651   * @brief  I2C abort callback.
04652   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04653   *                the configuration information for the specified I2C.
04654   * @retval None
04655   */
04656 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
04657 {
04658   /* Prevent unused argument(s) compilation warning */
04659   UNUSED(hi2c);
04660
04661   /* NOTE : This function should not be modified, when the callback is needed,
04662             the HAL_I2C_AbortCpltCallback could be implemented in the user file
04663    */
04664 }
04665
04666 /**
04667   * @}
04668   */
04669
04670 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
04671   *  @brief   Peripheral State, Mode and Error functions
04672   *
04673 @verbatim
04674  ===============================================================================
04675             ##### Peripheral State, Mode and Error functions #####
04676  ===============================================================================
04677     [..]
04678     This subsection permit to get in run-time the status of the peripheral
04679     and the data flow.
04680
04681 @endverbatim
04682   * @{
04683   */
04684
04685 /**
04686   * @brief  Return the I2C handle state.
04687   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04688   *                the configuration information for the specified I2C.
04689   * @retval HAL state
04690   */
04691 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
04692 {
04693   /* Return I2C handle state */
04694   return hi2c->State;
04695 }
04696
04697 /**
04698   * @brief  Returns the I2C Master, Slave, Memory or no mode.
04699   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04700   *         the configuration information for I2C module
04701   * @retval HAL mode
04702   */
04703 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
04704 {
04705   return hi2c->Mode;
04706 }
04707
04708 /**
04709   * @brief  Return the I2C error code.
04710   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04711   *              the configuration information for the specified I2C.
04712   * @retval I2C Error Code
04713   */
04714 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
04715 {
04716   return hi2c->ErrorCode;
04717 }
04718
04719 /**
04720   * @}
04721   */
04722
04723 /**
04724   * @}
04725   */
04726
04727 /** @addtogroup I2C_Private_Functions
04728   * @{
04729   */
04730
04731 /**
04732   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
04733   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04734   *                the configuration information for the specified I2C.
04735   * @param  ITFlags Interrupt flags to handle.
04736   * @param  ITSources Interrupt sources enabled.
04737   * @retval HAL status
04738   */
04739 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
04740                                            uint32_t ITSources)
04741 {
04742   uint16_t devaddress;
04743   uint32_t tmpITFlags = ITFlags;
04744
04745   /* Process Locked */
04746   __HAL_LOCK(hi2c);
04747
04748   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
04749       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04750   {
04751     /* Clear NACK Flag */
04752     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04753
04754     /* Set corresponding Error Code */
04755     /* No need to generate STOP, it is automatically done */
04756     /* Error callback will be send during stop flag treatment */
04757     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04758
04759     /* Flush TX register */
04760     I2C_Flush_TXDR(hi2c);
04761   }
04762   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
04763            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
04764   {
04765     /* Remove RXNE flag on temporary variable as read done */
04766     tmpITFlags &= ~I2C_FLAG_RXNE;
04767
04768     /* Read data from RXDR */
04769     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
04770
04771     /* Increment Buffer pointer */
04772     hi2c->pBuffPtr++;
04773
04774     hi2c->XferSize--;
04775     hi2c->XferCount--;
04776   }
04777   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
04778            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
04779   {
04780     /* Write data to TXDR */
04781     hi2c->Instance->TXDR = *hi2c->pBuffPtr;
04782
04783     /* Increment Buffer pointer */
04784     hi2c->pBuffPtr++;
04785
04786     hi2c->XferSize--;
04787     hi2c->XferCount--;
04788   }
04789   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
04790            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04791   {
04792     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
04793     {
04794       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
04795
04796       if (hi2c->XferCount > MAX_NBYTE_SIZE)
04797       {
04798         hi2c->XferSize = MAX_NBYTE_SIZE;
04799         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
04800       }
04801       else
04802       {
04803         hi2c->XferSize = hi2c->XferCount;
04804         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04805         {
04806           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
04807                              hi2c->XferOptions, I2C_NO_STARTSTOP);
04808         }
04809         else
04810         {
04811           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
04812                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
04813         }
04814       }
04815     }
04816     else
04817     {
04818       /* Call TxCpltCallback() if no stop mode is set */
04819       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04820       {
04821         /* Call I2C Master Sequential complete process */
04822         I2C_ITMasterSeqCplt(hi2c);
04823       }
04824       else
04825       {
04826         /* Wrong size Status regarding TCR flag event */
04827         /* Call the corresponding callback to inform upper layer of End of Transfer */
04828         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04829       }
04830     }
04831   }
04832   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
04833            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04834   {
04835     if (hi2c->XferCount == 0U)
04836     {
04837       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04838       {
04839         /* Generate a stop condition in case of no transfer option */
04840         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
04841         {
04842           /* Generate Stop */
04843           hi2c->Instance->CR2 |= I2C_CR2_STOP;
04844         }
04845         else
04846         {
04847           /* Call I2C Master Sequential complete process */
04848           I2C_ITMasterSeqCplt(hi2c);
04849         }
04850       }
04851     }
04852     else
04853     {
04854       /* Wrong size Status regarding TC flag event */
04855       /* Call the corresponding callback to inform upper layer of End of Transfer */
04856       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04857     }
04858   }
04859   else
04860   {
04861     /* Nothing to do */
04862   }
04863
04864   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
04865       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
04866   {
04867     /* Call I2C Master complete process */
04868     I2C_ITMasterCplt(hi2c, tmpITFlags);
04869   }
04870
04871   /* Process Unlocked */
04872   __HAL_UNLOCK(hi2c);
04873
04874   return HAL_OK;
04875 }
04876
04877 /**
04878   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
04879   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04880   *                the configuration information for the specified I2C.
04881   * @param  ITFlags Interrupt flags to handle.
04882   * @param  ITSources Interrupt sources enabled.
04883   * @retval HAL status
04884   */
04885 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
04886                                            uint32_t ITSources)
04887 {
04888   uint32_t direction = I2C_GENERATE_START_WRITE;
04889   uint32_t tmpITFlags = ITFlags;
04890
04891   /* Process Locked */
04892   __HAL_LOCK(hi2c);
04893
04894   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
04895       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04896   {
04897     /* Clear NACK Flag */
04898     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04899
04900     /* Set corresponding Error Code */
04901     /* No need to generate STOP, it is automatically done */
04902     /* Error callback will be send during stop flag treatment */
04903     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04904
04905     /* Flush TX register */
04906     I2C_Flush_TXDR(hi2c);
04907   }
04908   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
04909            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
04910   {
04911     /* Remove RXNE flag on temporary variable as read done */
04912     tmpITFlags &= ~I2C_FLAG_RXNE;
04913
04914     /* Read data from RXDR */
04915     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
04916
04917     /* Increment Buffer pointer */
04918     hi2c->pBuffPtr++;
04919
04920     hi2c->XferSize--;
04921     hi2c->XferCount--;
04922   }
04923   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
04924            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
04925   {
04926     if (hi2c->Memaddress == 0xFFFFFFFFU)
04927     {
04928       /* Write data to TXDR */
04929       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
04930
04931       /* Increment Buffer pointer */
04932       hi2c->pBuffPtr++;
04933
04934       hi2c->XferSize--;
04935       hi2c->XferCount--;
04936     }
04937     else
04938     {
04939       /* Write LSB part of Memory Address */
04940       hi2c->Instance->TXDR = hi2c->Memaddress;
04941
04942       /* Reset Memaddress content */
04943       hi2c->Memaddress = 0xFFFFFFFFU;
04944     }
04945   }
04946   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
04947            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04948   {
04949     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
04950     {
04951       if (hi2c->XferCount > MAX_NBYTE_SIZE)
04952       {
04953         hi2c->XferSize = MAX_NBYTE_SIZE;
04954         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
04955                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
04956       }
04957       else
04958       {
04959         hi2c->XferSize = hi2c->XferCount;
04960         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
04961                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
04962       }
04963     }
04964     else
04965     {
04966       /* Wrong size Status regarding TCR flag event */
04967       /* Call the corresponding callback to inform upper layer of End of Transfer */
04968       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04969     }
04970   }
04971   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
04972            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04973   {
04974     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
04975     {
04976       direction = I2C_GENERATE_START_READ;
04977     }
04978
04979     if (hi2c->XferCount > MAX_NBYTE_SIZE)
04980     {
04981       hi2c->XferSize = MAX_NBYTE_SIZE;
04982
04983       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
04984       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
04985                          I2C_RELOAD_MODE, direction);
04986     }
04987     else
04988     {
04989       hi2c->XferSize = hi2c->XferCount;
04990
04991       /* Set NBYTES to write and generate RESTART */
04992       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
04993                          I2C_AUTOEND_MODE, direction);
04994     }
04995   }
04996   else
04997   {
04998     /* Nothing to do */
04999   }
05000
05001   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
05002       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05003   {
05004     /* Call I2C Master complete process */
05005     I2C_ITMasterCplt(hi2c, tmpITFlags);
05006   }
05007
05008   /* Process Unlocked */
05009   __HAL_UNLOCK(hi2c);
05010
05011   return HAL_OK;
05012 }
05013
05014 /**
05015   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
05016   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05017   *                the configuration information for the specified I2C.
05018   * @param  ITFlags Interrupt flags to handle.
05019   * @param  ITSources Interrupt sources enabled.
05020   * @retval HAL status
05021   */
05022 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05023                                           uint32_t ITSources)
05024 {
05025   uint32_t tmpoptions = hi2c->XferOptions;
05026   uint32_t tmpITFlags = ITFlags;
05027
05028   /* Process locked */
05029   __HAL_LOCK(hi2c);
05030
05031   /* Check if STOPF is set */
05032   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
05033       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05034   {
05035     /* Call I2C Slave complete process */
05036     I2C_ITSlaveCplt(hi2c, tmpITFlags);
05037   }
05038
05039   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
05040       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05041   {
05042     /* Check that I2C transfer finished */
05043     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
05044     /* Mean XferCount == 0*/
05045     /* So clear Flag NACKF only */
05046     if (hi2c->XferCount == 0U)
05047     {
05048       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
05049         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
05050            Warning[Pa134]: left and right operands are identical */
05051       {
05052         /* Call I2C Listen complete process */
05053         I2C_ITListenCplt(hi2c, tmpITFlags);
05054       }
05055       else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
05056       {
05057         /* Clear NACK Flag */
05058         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05059
05060         /* Flush TX register */
05061         I2C_Flush_TXDR(hi2c);
05062
05063         /* Last Byte is Transmitted */
05064         /* Call I2C Slave Sequential complete process */
05065         I2C_ITSlaveSeqCplt(hi2c);
05066       }
05067       else
05068       {
05069         /* Clear NACK Flag */
05070         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05071       }
05072     }
05073     else
05074     {
05075       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
05076       /* Clear NACK Flag */
05077       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05078
05079       /* Set ErrorCode corresponding to a Non-Acknowledge */
05080       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05081
05082       if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
05083       {
05084         /* Call the corresponding callback to inform upper layer of End of Transfer */
05085         I2C_ITError(hi2c, hi2c->ErrorCode);
05086       }
05087     }
05088   }
05089   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
05090            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
05091   {
05092     if (hi2c->XferCount > 0U)
05093     {
05094       /* Read data from RXDR */
05095       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
05096
05097       /* Increment Buffer pointer */
05098       hi2c->pBuffPtr++;
05099
05100       hi2c->XferSize--;
05101       hi2c->XferCount--;
05102     }
05103
05104     if ((hi2c->XferCount == 0U) && \
05105         (tmpoptions != I2C_NO_OPTION_FRAME))
05106     {
05107       /* Call I2C Slave Sequential complete process */
05108       I2C_ITSlaveSeqCplt(hi2c);
05109     }
05110   }
05111   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
05112            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
05113   {
05114     I2C_ITAddrCplt(hi2c, tmpITFlags);
05115   }
05116   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
05117            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
05118   {
05119     /* Write data to TXDR only if XferCount not reach "0" */
05120     /* A TXIS flag can be set, during STOP treatment      */
05121     /* Check if all Data have already been sent */
05122     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
05123     if (hi2c->XferCount > 0U)
05124     {
05125       /* Write data to TXDR */
05126       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
05127
05128       /* Increment Buffer pointer */
05129       hi2c->pBuffPtr++;
05130
05131       hi2c->XferCount--;
05132       hi2c->XferSize--;
05133     }
05134     else
05135     {
05136       if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
05137       {
05138         /* Last Byte is Transmitted */
05139         /* Call I2C Slave Sequential complete process */
05140         I2C_ITSlaveSeqCplt(hi2c);
05141       }
05142     }
05143   }
05144   else
05145   {
05146     /* Nothing to do */
05147   }
05148
05149   /* Process Unlocked */
05150   __HAL_UNLOCK(hi2c);
05151
05152   return HAL_OK;
05153 }
05154
05155 /**
05156   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
05157   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05158   *                the configuration information for the specified I2C.
05159   * @param  ITFlags Interrupt flags to handle.
05160   * @param  ITSources Interrupt sources enabled.
05161   * @retval HAL status
05162   */
05163 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05164                                             uint32_t ITSources)
05165 {
05166   uint16_t devaddress;
05167   uint32_t xfermode;
05168
05169   /* Process Locked */
05170   __HAL_LOCK(hi2c);
05171
05172   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
05173       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05174   {
05175     /* Clear NACK Flag */
05176     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05177
05178     /* Set corresponding Error Code */
05179     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05180
05181     /* No need to generate STOP, it is automatically done */
05182     /* But enable STOP interrupt, to treat it */
05183     /* Error callback will be send during stop flag treatment */
05184     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
05185
05186     /* Flush TX register */
05187     I2C_Flush_TXDR(hi2c);
05188   }
05189   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
05190            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05191   {
05192     /* Disable TC interrupt */
05193     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
05194
05195     if (hi2c->XferCount != 0U)
05196     {
05197       /* Recover Slave address */
05198       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
05199
05200       /* Prepare the new XferSize to transfer */
05201       if (hi2c->XferCount > MAX_NBYTE_SIZE)
05202       {
05203         hi2c->XferSize = MAX_NBYTE_SIZE;
05204         xfermode = I2C_RELOAD_MODE;
05205       }
05206       else
05207       {
05208         hi2c->XferSize = hi2c->XferCount;
05209         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
05210         {
05211           xfermode = hi2c->XferOptions;
05212         }
05213         else
05214         {
05215           xfermode = I2C_AUTOEND_MODE;
05216         }
05217       }
05218
05219       /* Set the new XferSize in Nbytes register */
05220       I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
05221
05222       /* Update XferCount value */
05223       hi2c->XferCount -= hi2c->XferSize;
05224
05225       /* Enable DMA Request */
05226       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05227       {
05228         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
05229       }
05230       else
05231       {
05232         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
05233       }
05234     }
05235     else
05236     {
05237       /* Call TxCpltCallback() if no stop mode is set */
05238       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
05239       {
05240         /* Call I2C Master Sequential complete process */
05241         I2C_ITMasterSeqCplt(hi2c);
05242       }
05243       else
05244       {
05245         /* Wrong size Status regarding TCR flag event */
05246         /* Call the corresponding callback to inform upper layer of End of Transfer */
05247         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05248       }
05249     }
05250   }
05251   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
05252            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05253   {
05254     if (hi2c->XferCount == 0U)
05255     {
05256       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
05257       {
05258         /* Generate a stop condition in case of no transfer option */
05259         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
05260         {
05261           /* Generate Stop */
05262           hi2c->Instance->CR2 |= I2C_CR2_STOP;
05263         }
05264         else
05265         {
05266           /* Call I2C Master Sequential complete process */
05267           I2C_ITMasterSeqCplt(hi2c);
05268         }
05269       }
05270     }
05271     else
05272     {
05273       /* Wrong size Status regarding TC flag event */
05274       /* Call the corresponding callback to inform upper layer of End of Transfer */
05275       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05276     }
05277   }
05278   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
05279            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05280   {
05281     /* Call I2C Master complete process */
05282     I2C_ITMasterCplt(hi2c, ITFlags);
05283   }
05284   else
05285   {
05286     /* Nothing to do */
05287   }
05288
05289   /* Process Unlocked */
05290   __HAL_UNLOCK(hi2c);
05291
05292   return HAL_OK;
05293 }
05294
05295 /**
05296   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
05297   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05298   *                the configuration information for the specified I2C.
05299   * @param  ITFlags Interrupt flags to handle.
05300   * @param  ITSources Interrupt sources enabled.
05301   * @retval HAL status
05302   */
05303 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05304                                             uint32_t ITSources)
05305 {
05306   uint32_t direction = I2C_GENERATE_START_WRITE;
05307
05308   /* Process Locked */
05309   __HAL_LOCK(hi2c);
05310
05311   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
05312       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05313   {
05314     /* Clear NACK Flag */
05315     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05316
05317     /* Set corresponding Error Code */
05318     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05319
05320     /* No need to generate STOP, it is automatically done */
05321     /* But enable STOP interrupt, to treat it */
05322     /* Error callback will be send during stop flag treatment */
05323     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
05324
05325     /* Flush TX register */
05326     I2C_Flush_TXDR(hi2c);
05327   }
05328   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
05329            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
05330   {
05331     /* Write LSB part of Memory Address */
05332     hi2c->Instance->TXDR = hi2c->Memaddress;
05333
05334     /* Reset Memaddress content */
05335     hi2c->Memaddress = 0xFFFFFFFFU;
05336   }
05337   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
05338            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05339   {
05340     /* Enable only Error interrupt */
05341     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
05342
05343     if (hi2c->XferCount != 0U)
05344     {
05345       /* Prepare the new XferSize to transfer */
05346       if (hi2c->XferCount > MAX_NBYTE_SIZE)
05347       {
05348         hi2c->XferSize = MAX_NBYTE_SIZE;
05349         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05350                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
05351       }
05352       else
05353       {
05354         hi2c->XferSize = hi2c->XferCount;
05355         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05356                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
05357       }
05358
05359       /* Update XferCount value */
05360       hi2c->XferCount -= hi2c->XferSize;
05361
05362       /* Enable DMA Request */
05363       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05364       {
05365         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
05366       }
05367       else
05368       {
05369         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
05370       }
05371     }
05372     else
05373     {
05374       /* Wrong size Status regarding TCR flag event */
05375       /* Call the corresponding callback to inform upper layer of End of Transfer */
05376       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
05377     }
05378   }
05379   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
05380            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
05381   {
05382     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05383     {
05384       direction = I2C_GENERATE_START_READ;
05385     }
05386
05387     if (hi2c->XferCount > MAX_NBYTE_SIZE)
05388     {
05389       hi2c->XferSize = MAX_NBYTE_SIZE;
05390
05391       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
05392       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05393                          I2C_RELOAD_MODE, direction);
05394     }
05395     else
05396     {
05397       hi2c->XferSize = hi2c->XferCount;
05398
05399       /* Set NBYTES to write and generate RESTART */
05400       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
05401                          I2C_AUTOEND_MODE, direction);
05402     }
05403
05404     /* Update XferCount value */
05405     hi2c->XferCount -= hi2c->XferSize;
05406
05407     /* Enable DMA Request */
05408     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05409     {
05410       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
05411     }
05412     else
05413     {
05414       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
05415     }
05416   }
05417   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
05418            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05419   {
05420     /* Call I2C Master complete process */
05421     I2C_ITMasterCplt(hi2c, ITFlags);
05422   }
05423   else
05424   {
05425     /* Nothing to do */
05426   }
05427
05428   /* Process Unlocked */
05429   __HAL_UNLOCK(hi2c);
05430
05431   return HAL_OK;
05432 }
05433
05434 /**
05435   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
05436   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05437   *                the configuration information for the specified I2C.
05438   * @param  ITFlags Interrupt flags to handle.
05439   * @param  ITSources Interrupt sources enabled.
05440   * @retval HAL status
05441   */
05442 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
05443                                            uint32_t ITSources)
05444 {
05445   uint32_t tmpoptions = hi2c->XferOptions;
05446   uint32_t treatdmanack = 0U;
05447   HAL_I2C_StateTypeDef tmpstate;
05448
05449   /* Process locked */
05450   __HAL_LOCK(hi2c);
05451
05452   /* Check if STOPF is set */
05453   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
05454       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05455   {
05456     /* Call I2C Slave complete process */
05457     I2C_ITSlaveCplt(hi2c, ITFlags);
05458   }
05459
05460   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
05461       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05462   {
05463     /* Check that I2C transfer finished */
05464     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
05465     /* Mean XferCount == 0 */
05466     /* So clear Flag NACKF only */
05467     if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
05468         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
05469     {
05470       /* Split check of hdmarx, for MISRA compliance */
05471       if (hi2c->hdmarx != NULL)
05472       {
05473         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
05474         {
05475           if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
05476           {
05477             treatdmanack = 1U;
05478           }
05479         }
05480       }
05481
05482       /* Split check of hdmatx, for MISRA compliance  */
05483       if (hi2c->hdmatx != NULL)
05484       {
05485         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
05486         {
05487           if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
05488           {
05489             treatdmanack = 1U;
05490           }
05491         }
05492       }
05493
05494       if (treatdmanack == 1U)
05495       {
05496         if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
05497           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
05498              Warning[Pa134]: left and right operands are identical */
05499         {
05500           /* Call I2C Listen complete process */
05501           I2C_ITListenCplt(hi2c, ITFlags);
05502         }
05503         else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
05504         {
05505           /* Clear NACK Flag */
05506           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05507
05508           /* Flush TX register */
05509           I2C_Flush_TXDR(hi2c);
05510
05511           /* Last Byte is Transmitted */
05512           /* Call I2C Slave Sequential complete process */
05513           I2C_ITSlaveSeqCplt(hi2c);
05514         }
05515         else
05516         {
05517           /* Clear NACK Flag */
05518           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05519         }
05520       }
05521       else
05522       {
05523         /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
05524         /* Clear NACK Flag */
05525         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05526
05527         /* Set ErrorCode corresponding to a Non-Acknowledge */
05528         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05529
05530         /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
05531         tmpstate = hi2c->State;
05532
05533         if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
05534         {
05535           if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
05536           {
05537             hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
05538           }
05539           else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
05540           {
05541             hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
05542           }
05543           else
05544           {
05545             /* Do nothing */
05546           }
05547
05548           /* Call the corresponding callback to inform upper layer of End of Transfer */
05549           I2C_ITError(hi2c, hi2c->ErrorCode);
05550         }
05551       }
05552     }
05553     else
05554     {
05555       /* Only Clear NACK Flag, no DMA treatment is pending */
05556       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05557     }
05558   }
05559   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
05560            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
05561   {
05562     I2C_ITAddrCplt(hi2c, ITFlags);
05563   }
05564   else
05565   {
05566     /* Nothing to do */
05567   }
05568
05569   /* Process Unlocked */
05570   __HAL_UNLOCK(hi2c);
05571
05572   return HAL_OK;
05573 }
05574
05575 /**
05576   * @brief  Master sends target device address followed by internal memory address for write request.
05577   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05578   *                the configuration information for the specified I2C.
05579   * @param  DevAddress Target device address: The device 7 bits address value
05580   *         in datasheet must be shifted to the left before calling the interface
05581   * @param  MemAddress Internal memory address
05582   * @param  MemAddSize Size of internal memory address
05583   * @param  Timeout Timeout duration
05584   * @param  Tickstart Tick start value
05585   * @retval HAL status
05586   */
05587 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
05588                                                 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
05589                                                 uint32_t Tickstart)
05590 {
05591   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
05592
05593   /* Wait until TXIS flag is set */
05594   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05595   {
05596     return HAL_ERROR;
05597   }
05598
05599   /* If Memory address size is 8Bit */
05600   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
05601   {
05602     /* Send Memory Address */
05603     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05604   }
05605   /* If Memory address size is 16Bit */
05606   else
05607   {
05608     /* Send MSB of Memory Address */
05609     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
05610
05611     /* Wait until TXIS flag is set */
05612     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05613     {
05614       return HAL_ERROR;
05615     }
05616
05617     /* Send LSB of Memory Address */
05618     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05619   }
05620
05621   /* Wait until TCR flag is set */
05622   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
05623   {
05624     return HAL_ERROR;
05625   }
05626
05627   return HAL_OK;
05628 }
05629
05630 /**
05631   * @brief  Master sends target device address followed by internal memory address for read request.
05632   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05633   *                the configuration information for the specified I2C.
05634   * @param  DevAddress Target device address: The device 7 bits address value
05635   *         in datasheet must be shifted to the left before calling the interface
05636   * @param  MemAddress Internal memory address
05637   * @param  MemAddSize Size of internal memory address
05638   * @param  Timeout Timeout duration
05639   * @param  Tickstart Tick start value
05640   * @retval HAL status
05641   */
05642 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
05643                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
05644                                                uint32_t Tickstart)
05645 {
05646   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
05647
05648   /* Wait until TXIS flag is set */
05649   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05650   {
05651     return HAL_ERROR;
05652   }
05653
05654   /* If Memory address size is 8Bit */
05655   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
05656   {
05657     /* Send Memory Address */
05658     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05659   }
05660   /* If Memory address size is 16Bit */
05661   else
05662   {
05663     /* Send MSB of Memory Address */
05664     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
05665
05666     /* Wait until TXIS flag is set */
05667     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05668     {
05669       return HAL_ERROR;
05670     }
05671
05672     /* Send LSB of Memory Address */
05673     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05674   }
05675
05676   /* Wait until TC flag is set */
05677   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
05678   {
05679     return HAL_ERROR;
05680   }
05681
05682   return HAL_OK;
05683 }
05684
05685 /**
05686   * @brief  I2C Address complete process callback.
05687   * @param  hi2c I2C handle.
05688   * @param  ITFlags Interrupt flags to handle.
05689   * @retval None
05690   */
05691 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05692 {
05693   uint8_t transferdirection;
05694   uint16_t slaveaddrcode;
05695   uint16_t ownadd1code;
05696   uint16_t ownadd2code;
05697
05698   /* Prevent unused argument(s) compilation warning */
05699   UNUSED(ITFlags);
05700
05701   /* In case of Listen state, need to inform upper layer of address match code event */
05702   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
05703   {
05704     transferdirection = I2C_GET_DIR(hi2c);
05705     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
05706     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
05707     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
05708
05709     /* If 10bits addressing mode is selected */
05710     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
05711     {
05712       if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
05713       {
05714         slaveaddrcode = ownadd1code;
05715         hi2c->AddrEventCount++;
05716         if (hi2c->AddrEventCount == 2U)
05717         {
05718           /* Reset Address Event counter */
05719           hi2c->AddrEventCount = 0U;
05720
05721           /* Clear ADDR flag */
05722           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
05723
05724           /* Process Unlocked */
05725           __HAL_UNLOCK(hi2c);
05726
05727           /* Call Slave Addr callback */
05728 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05729           hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05730 #else
05731           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05732 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05733         }
05734       }
05735       else
05736       {
05737         slaveaddrcode = ownadd2code;
05738
05739         /* Disable ADDR Interrupts */
05740         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
05741
05742         /* Process Unlocked */
05743         __HAL_UNLOCK(hi2c);
05744
05745         /* Call Slave Addr callback */
05746 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05747         hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05748 #else
05749         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05750 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05751       }
05752     }
05753     /* else 7 bits addressing mode is selected */
05754     else
05755     {
05756       /* Disable ADDR Interrupts */
05757       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
05758
05759       /* Process Unlocked */
05760       __HAL_UNLOCK(hi2c);
05761
05762       /* Call Slave Addr callback */
05763 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05764       hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05765 #else
05766       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05767 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05768     }
05769   }
05770   /* Else clear address flag only */
05771   else
05772   {
05773     /* Clear ADDR flag */
05774     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
05775
05776     /* Process Unlocked */
05777     __HAL_UNLOCK(hi2c);
05778   }
05779 }
05780
05781 /**
05782   * @brief  I2C Master sequential complete process.
05783   * @param  hi2c I2C handle.
05784   * @retval None
05785   */
05786 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
05787 {
05788   /* Reset I2C handle mode */
05789   hi2c->Mode = HAL_I2C_MODE_NONE;
05790
05791   /* No Generate Stop, to permit restart mode */
05792   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
05793   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
05794   {
05795     hi2c->State         = HAL_I2C_STATE_READY;
05796     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
05797     hi2c->XferISR       = NULL;
05798
05799     /* Disable Interrupts */
05800     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05801
05802     /* Process Unlocked */
05803     __HAL_UNLOCK(hi2c);
05804
05805     /* Call the corresponding callback to inform upper layer of End of Transfer */
05806 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05807     hi2c->MasterTxCpltCallback(hi2c);
05808 #else
05809     HAL_I2C_MasterTxCpltCallback(hi2c);
05810 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05811   }
05812   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
05813   else
05814   {
05815     hi2c->State         = HAL_I2C_STATE_READY;
05816     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
05817     hi2c->XferISR       = NULL;
05818
05819     /* Disable Interrupts */
05820     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
05821
05822     /* Process Unlocked */
05823     __HAL_UNLOCK(hi2c);
05824
05825     /* Call the corresponding callback to inform upper layer of End of Transfer */
05826 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05827     hi2c->MasterRxCpltCallback(hi2c);
05828 #else
05829     HAL_I2C_MasterRxCpltCallback(hi2c);
05830 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05831   }
05832 }
05833
05834 /**
05835   * @brief  I2C Slave sequential complete process.
05836   * @param  hi2c I2C handle.
05837   * @retval None
05838   */
05839 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
05840 {
05841   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
05842
05843   /* Reset I2C handle mode */
05844   hi2c->Mode = HAL_I2C_MODE_NONE;
05845
05846   /* If a DMA is ongoing, Update handle size context */
05847   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
05848   {
05849     /* Disable DMA Request */
05850     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
05851   }
05852   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
05853   {
05854     /* Disable DMA Request */
05855     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
05856   }
05857   else
05858   {
05859     /* Do nothing */
05860   }
05861
05862   if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
05863   {
05864     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
05865     hi2c->State         = HAL_I2C_STATE_LISTEN;
05866     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
05867
05868     /* Disable Interrupts */
05869     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05870
05871     /* Process Unlocked */
05872     __HAL_UNLOCK(hi2c);
05873
05874     /* Call the corresponding callback to inform upper layer of End of Transfer */
05875 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05876     hi2c->SlaveTxCpltCallback(hi2c);
05877 #else
05878     HAL_I2C_SlaveTxCpltCallback(hi2c);
05879 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05880   }
05881
05882   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
05883   {
05884     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
05885     hi2c->State         = HAL_I2C_STATE_LISTEN;
05886     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
05887
05888     /* Disable Interrupts */
05889     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
05890
05891     /* Process Unlocked */
05892     __HAL_UNLOCK(hi2c);
05893
05894     /* Call the corresponding callback to inform upper layer of End of Transfer */
05895 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05896     hi2c->SlaveRxCpltCallback(hi2c);
05897 #else
05898     HAL_I2C_SlaveRxCpltCallback(hi2c);
05899 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05900   }
05901   else
05902   {
05903     /* Nothing to do */
05904   }
05905 }
05906
05907 /**
05908   * @brief  I2C Master complete process.
05909   * @param  hi2c I2C handle.
05910   * @param  ITFlags Interrupt flags to handle.
05911   * @retval None
05912   */
05913 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05914 {
05915   uint32_t tmperror;
05916   uint32_t tmpITFlags = ITFlags;
05917   __IO uint32_t tmpreg;
05918
05919   /* Clear STOP Flag */
05920   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
05921
05922   /* Disable Interrupts and Store Previous state */
05923   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
05924   {
05925     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05926     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
05927   }
05928   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05929   {
05930     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
05931     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
05932   }
05933   else
05934   {
05935     /* Do nothing */
05936   }
05937
05938   /* Clear Configuration Register 2 */
05939   I2C_RESET_CR2(hi2c);
05940
05941   /* Reset handle parameters */
05942   hi2c->XferISR       = NULL;
05943   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
05944
05945   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
05946   {
05947     /* Clear NACK Flag */
05948     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05949
05950     /* Set acknowledge error code */
05951     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05952   }
05953
05954   /* Fetch Last receive data if any */
05955   if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
05956   {
05957     /* Read data from RXDR */
05958     tmpreg = (uint8_t)hi2c->Instance->RXDR;
05959     UNUSED(tmpreg);
05960   }
05961
05962   /* Flush TX register */
05963   I2C_Flush_TXDR(hi2c);
05964
05965   /* Store current volatile hi2c->ErrorCode, misra rule */
05966   tmperror = hi2c->ErrorCode;
05967
05968   /* Call the corresponding callback to inform upper layer of End of Transfer */
05969   if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
05970   {
05971     /* Call the corresponding callback to inform upper layer of End of Transfer */
05972     I2C_ITError(hi2c, hi2c->ErrorCode);
05973   }
05974   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
05975   else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
05976   {
05977     hi2c->State = HAL_I2C_STATE_READY;
05978     hi2c->PreviousState = I2C_STATE_NONE;
05979
05980     if (hi2c->Mode == HAL_I2C_MODE_MEM)
05981     {
05982       hi2c->Mode = HAL_I2C_MODE_NONE;
05983
05984       /* Process Unlocked */
05985       __HAL_UNLOCK(hi2c);
05986
05987       /* Call the corresponding callback to inform upper layer of End of Transfer */
05988 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05989       hi2c->MemTxCpltCallback(hi2c);
05990 #else
05991       HAL_I2C_MemTxCpltCallback(hi2c);
05992 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05993     }
05994     else
05995     {
05996       hi2c->Mode = HAL_I2C_MODE_NONE;
05997
05998       /* Process Unlocked */
05999       __HAL_UNLOCK(hi2c);
06000
06001       /* Call the corresponding callback to inform upper layer of End of Transfer */
06002 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06003       hi2c->MasterTxCpltCallback(hi2c);
06004 #else
06005       HAL_I2C_MasterTxCpltCallback(hi2c);
06006 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06007     }
06008   }
06009   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
06010   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
06011   {
06012     hi2c->State = HAL_I2C_STATE_READY;
06013     hi2c->PreviousState = I2C_STATE_NONE;
06014
06015     if (hi2c->Mode == HAL_I2C_MODE_MEM)
06016     {
06017       hi2c->Mode = HAL_I2C_MODE_NONE;
06018
06019       /* Process Unlocked */
06020       __HAL_UNLOCK(hi2c);
06021
06022       /* Call the corresponding callback to inform upper layer of End of Transfer */
06023 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06024       hi2c->MemRxCpltCallback(hi2c);
06025 #else
06026       HAL_I2C_MemRxCpltCallback(hi2c);
06027 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06028     }
06029     else
06030     {
06031       hi2c->Mode = HAL_I2C_MODE_NONE;
06032
06033       /* Process Unlocked */
06034       __HAL_UNLOCK(hi2c);
06035
06036       /* Call the corresponding callback to inform upper layer of End of Transfer */
06037 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06038       hi2c->MasterRxCpltCallback(hi2c);
06039 #else
06040       HAL_I2C_MasterRxCpltCallback(hi2c);
06041 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06042     }
06043   }
06044   else
06045   {
06046     /* Nothing to do */
06047   }
06048 }
06049
06050 /**
06051   * @brief  I2C Slave complete process.
06052   * @param  hi2c I2C handle.
06053   * @param  ITFlags Interrupt flags to handle.
06054   * @retval None
06055   */
06056 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
06057 {
06058   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
06059   uint32_t tmpITFlags = ITFlags;
06060   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
06061
06062   /* Clear STOP Flag */
06063   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06064
06065   /* Disable Interrupts and Store Previous state */
06066   if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
06067   {
06068     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
06069     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
06070   }
06071   else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
06072   {
06073     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
06074     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
06075   }
06076   else
06077   {
06078     /* Do nothing */
06079   }
06080
06081   /* Disable Address Acknowledge */
06082   hi2c->Instance->CR2 |= I2C_CR2_NACK;
06083
06084   /* Clear Configuration Register 2 */
06085   I2C_RESET_CR2(hi2c);
06086
06087   /* Flush TX register */
06088   I2C_Flush_TXDR(hi2c);
06089
06090   /* If a DMA is ongoing, Update handle size context */
06091   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
06092   {
06093     /* Disable DMA Request */
06094     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06095
06096     if (hi2c->hdmatx != NULL)
06097     {
06098       hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
06099     }
06100   }
06101   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
06102   {
06103     /* Disable DMA Request */
06104     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06105
06106     if (hi2c->hdmarx != NULL)
06107     {
06108       hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
06109     }
06110   }
06111   else
06112   {
06113     /* Do nothing */
06114   }
06115
06116   /* Store Last receive data if any */
06117   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
06118   {
06119     /* Remove RXNE flag on temporary variable as read done */
06120     tmpITFlags &= ~I2C_FLAG_RXNE;
06121
06122     /* Read data from RXDR */
06123     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
06124
06125     /* Increment Buffer pointer */
06126     hi2c->pBuffPtr++;
06127
06128     if ((hi2c->XferSize > 0U))
06129     {
06130       hi2c->XferSize--;
06131       hi2c->XferCount--;
06132     }
06133   }
06134
06135   /* All data are not transferred, so set error code accordingly */
06136   if (hi2c->XferCount != 0U)
06137   {
06138     /* Set ErrorCode corresponding to a Non-Acknowledge */
06139     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06140   }
06141
06142   hi2c->Mode = HAL_I2C_MODE_NONE;
06143   hi2c->XferISR = NULL;
06144
06145   if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
06146   {
06147     /* Call the corresponding callback to inform upper layer of End of Transfer */
06148     I2C_ITError(hi2c, hi2c->ErrorCode);
06149
06150     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
06151     if (hi2c->State == HAL_I2C_STATE_LISTEN)
06152     {
06153       /* Call I2C Listen complete process */
06154       I2C_ITListenCplt(hi2c, tmpITFlags);
06155     }
06156   }
06157   else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
06158   {
06159     /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
06160     I2C_ITSlaveSeqCplt(hi2c);
06161
06162     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
06163     hi2c->State = HAL_I2C_STATE_READY;
06164     hi2c->PreviousState = I2C_STATE_NONE;
06165
06166     /* Process Unlocked */
06167     __HAL_UNLOCK(hi2c);
06168
06169     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
06170 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06171     hi2c->ListenCpltCallback(hi2c);
06172 #else
06173     HAL_I2C_ListenCpltCallback(hi2c);
06174 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06175   }
06176   /* Call the corresponding callback to inform upper layer of End of Transfer */
06177   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
06178   {
06179     hi2c->State = HAL_I2C_STATE_READY;
06180     hi2c->PreviousState = I2C_STATE_NONE;
06181
06182     /* Process Unlocked */
06183     __HAL_UNLOCK(hi2c);
06184
06185     /* Call the corresponding callback to inform upper layer of End of Transfer */
06186 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06187     hi2c->SlaveRxCpltCallback(hi2c);
06188 #else
06189     HAL_I2C_SlaveRxCpltCallback(hi2c);
06190 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06191   }
06192   else
06193   {
06194     hi2c->State = HAL_I2C_STATE_READY;
06195     hi2c->PreviousState = I2C_STATE_NONE;
06196
06197     /* Process Unlocked */
06198     __HAL_UNLOCK(hi2c);
06199
06200     /* Call the corresponding callback to inform upper layer of End of Transfer */
06201 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06202     hi2c->SlaveTxCpltCallback(hi2c);
06203 #else
06204     HAL_I2C_SlaveTxCpltCallback(hi2c);
06205 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06206   }
06207 }
06208
06209 /**
06210   * @brief  I2C Listen complete process.
06211   * @param  hi2c I2C handle.
06212   * @param  ITFlags Interrupt flags to handle.
06213   * @retval None
06214   */
06215 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
06216 {
06217   /* Reset handle parameters */
06218   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
06219   hi2c->PreviousState = I2C_STATE_NONE;
06220   hi2c->State = HAL_I2C_STATE_READY;
06221   hi2c->Mode = HAL_I2C_MODE_NONE;
06222   hi2c->XferISR = NULL;
06223
06224   /* Store Last receive data if any */
06225   if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
06226   {
06227     /* Read data from RXDR */
06228     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
06229
06230     /* Increment Buffer pointer */
06231     hi2c->pBuffPtr++;
06232
06233     if ((hi2c->XferSize > 0U))
06234     {
06235       hi2c->XferSize--;
06236       hi2c->XferCount--;
06237
06238       /* Set ErrorCode corresponding to a Non-Acknowledge */
06239       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06240     }
06241   }
06242
06243   /* Disable all Interrupts*/
06244   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
06245
06246   /* Clear NACK Flag */
06247   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06248
06249   /* Process Unlocked */
06250   __HAL_UNLOCK(hi2c);
06251
06252   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
06253 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06254   hi2c->ListenCpltCallback(hi2c);
06255 #else
06256   HAL_I2C_ListenCpltCallback(hi2c);
06257 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06258 }
06259
06260 /**
06261   * @brief  I2C interrupts error process.
06262   * @param  hi2c I2C handle.
06263   * @param  ErrorCode Error code to handle.
06264   * @retval None
06265   */
06266 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
06267 {
06268   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
06269   uint32_t tmppreviousstate;
06270
06271   /* Reset handle parameters */
06272   hi2c->Mode          = HAL_I2C_MODE_NONE;
06273   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
06274   hi2c->XferCount     = 0U;
06275
06276   /* Set new error code */
06277   hi2c->ErrorCode |= ErrorCode;
06278
06279   /* Disable Interrupts */
06280   if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
06281       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
06282       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
06283   {
06284     /* Disable all interrupts, except interrupts related to LISTEN state */
06285     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
06286
06287     /* keep HAL_I2C_STATE_LISTEN if set */
06288     hi2c->State         = HAL_I2C_STATE_LISTEN;
06289     hi2c->XferISR       = I2C_Slave_ISR_IT;
06290   }
06291   else
06292   {
06293     /* Disable all interrupts */
06294     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
06295
06296     /* If state is an abort treatment on going, don't change state */
06297     /* This change will be do later */
06298     if (hi2c->State != HAL_I2C_STATE_ABORT)
06299     {
06300       /* Set HAL_I2C_STATE_READY */
06301       hi2c->State         = HAL_I2C_STATE_READY;
06302     }
06303     hi2c->XferISR       = NULL;
06304   }
06305
06306   /* Abort DMA TX transfer if any */
06307   tmppreviousstate = hi2c->PreviousState;
06308   if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
06309                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
06310   {
06311     if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
06312     {
06313       hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06314     }
06315
06316     if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
06317     {
06318       /* Set the I2C DMA Abort callback :
06319        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
06320       hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
06321
06322       /* Process Unlocked */
06323       __HAL_UNLOCK(hi2c);
06324
06325       /* Abort DMA TX */
06326       if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
06327       {
06328         /* Call Directly XferAbortCallback function in case of error */
06329         hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
06330       }
06331     }
06332     else
06333     {
06334       I2C_TreatErrorCallback(hi2c);
06335     }
06336   }
06337   /* Abort DMA RX transfer if any */
06338   else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
06339                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
06340   {
06341     if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
06342     {
06343       hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06344     }
06345
06346     if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
06347     {
06348       /* Set the I2C DMA Abort callback :
06349         will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
06350       hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
06351
06352       /* Process Unlocked */
06353       __HAL_UNLOCK(hi2c);
06354
06355       /* Abort DMA RX */
06356       if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
06357       {
06358         /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
06359         hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
06360       }
06361     }
06362     else
06363     {
06364       I2C_TreatErrorCallback(hi2c);
06365     }
06366   }
06367   else
06368   {
06369     I2C_TreatErrorCallback(hi2c);
06370   }
06371 }
06372
06373 /**
06374   * @brief  I2C Error callback treatment.
06375   * @param  hi2c I2C handle.
06376   * @retval None
06377   */
06378 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
06379 {
06380   if (hi2c->State == HAL_I2C_STATE_ABORT)
06381   {
06382     hi2c->State = HAL_I2C_STATE_READY;
06383     hi2c->PreviousState = I2C_STATE_NONE;
06384
06385     /* Process Unlocked */
06386     __HAL_UNLOCK(hi2c);
06387
06388     /* Call the corresponding callback to inform upper layer of End of Transfer */
06389 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06390     hi2c->AbortCpltCallback(hi2c);
06391 #else
06392     HAL_I2C_AbortCpltCallback(hi2c);
06393 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06394   }
06395   else
06396   {
06397     hi2c->PreviousState = I2C_STATE_NONE;
06398
06399     /* Process Unlocked */
06400     __HAL_UNLOCK(hi2c);
06401
06402     /* Call the corresponding callback to inform upper layer of End of Transfer */
06403 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06404     hi2c->ErrorCallback(hi2c);
06405 #else
06406     HAL_I2C_ErrorCallback(hi2c);
06407 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06408   }
06409 }
06410
06411 /**
06412   * @brief  I2C Tx data register flush process.
06413   * @param  hi2c I2C handle.
06414   * @retval None
06415   */
06416 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
06417 {
06418   /* If a pending TXIS flag is set */
06419   /* Write a dummy data in TXDR to clear it */
06420   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
06421   {
06422     hi2c->Instance->TXDR = 0x00U;
06423   }
06424
06425   /* Flush TX register if not empty */
06426   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
06427   {
06428     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
06429   }
06430 }
06431
06432 /**
06433   * @brief  DMA I2C master transmit process complete callback.
06434   * @param  hdma DMA handle
06435   * @retval None
06436   */
06437 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
06438 {
06439   /* Derogation MISRAC2012-Rule-11.5 */
06440   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06441
06442   /* Disable DMA Request */
06443   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06444
06445   /* If last transfer, enable STOP interrupt */
06446   if (hi2c->XferCount == 0U)
06447   {
06448     /* Enable STOP interrupt */
06449     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
06450   }
06451   /* else prepare a new DMA transfer and enable TCReload interrupt */
06452   else
06453   {
06454     /* Update Buffer pointer */
06455     hi2c->pBuffPtr += hi2c->XferSize;
06456
06457     /* Set the XferSize to transfer */
06458     if (hi2c->XferCount > MAX_NBYTE_SIZE)
06459     {
06460       hi2c->XferSize = MAX_NBYTE_SIZE;
06461     }
06462     else
06463     {
06464       hi2c->XferSize = hi2c->XferCount;
06465     }
06466
06467     /* Enable the DMA channel */
06468     if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
06469                          hi2c->XferSize) != HAL_OK)
06470     {
06471       /* Call the corresponding callback to inform upper layer of End of Transfer */
06472       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
06473     }
06474     else
06475     {
06476       /* Enable TC interrupts */
06477       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
06478     }
06479   }
06480 }
06481
06482 /**
06483   * @brief  DMA I2C slave transmit process complete callback.
06484   * @param  hdma DMA handle
06485   * @retval None
06486   */
06487 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
06488 {
06489   /* Derogation MISRAC2012-Rule-11.5 */
06490   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06491   uint32_t tmpoptions = hi2c->XferOptions;
06492
06493   if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
06494   {
06495     /* Disable DMA Request */
06496     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
06497
06498     /* Last Byte is Transmitted */
06499     /* Call I2C Slave Sequential complete process */
06500     I2C_ITSlaveSeqCplt(hi2c);
06501   }
06502   else
06503   {
06504     /* No specific action, Master fully manage the generation of STOP condition */
06505     /* Mean that this generation can arrive at any time, at the end or during DMA process */
06506     /* So STOP condition should be manage through Interrupt treatment */
06507   }
06508 }
06509
06510 /**
06511   * @brief DMA I2C master receive process complete callback.
06512   * @param  hdma DMA handle
06513   * @retval None
06514   */
06515 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
06516 {
06517   /* Derogation MISRAC2012-Rule-11.5 */
06518   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06519
06520   /* Disable DMA Request */
06521   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06522
06523   /* If last transfer, enable STOP interrupt */
06524   if (hi2c->XferCount == 0U)
06525   {
06526     /* Enable STOP interrupt */
06527     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
06528   }
06529   /* else prepare a new DMA transfer and enable TCReload interrupt */
06530   else
06531   {
06532     /* Update Buffer pointer */
06533     hi2c->pBuffPtr += hi2c->XferSize;
06534
06535     /* Set the XferSize to transfer */
06536     if (hi2c->XferCount > MAX_NBYTE_SIZE)
06537     {
06538       hi2c->XferSize = MAX_NBYTE_SIZE;
06539     }
06540     else
06541     {
06542       hi2c->XferSize = hi2c->XferCount;
06543     }
06544
06545     /* Enable the DMA channel */
06546     if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
06547                          hi2c->XferSize) != HAL_OK)
06548     {
06549       /* Call the corresponding callback to inform upper layer of End of Transfer */
06550       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
06551     }
06552     else
06553     {
06554       /* Enable TC interrupts */
06555       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
06556     }
06557   }
06558 }
06559
06560 /**
06561   * @brief  DMA I2C slave receive process complete callback.
06562   * @param  hdma DMA handle
06563   * @retval None
06564   */
06565 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
06566 {
06567   /* Derogation MISRAC2012-Rule-11.5 */
06568   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06569   uint32_t tmpoptions = hi2c->XferOptions;
06570
06571   if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
06572       (tmpoptions != I2C_NO_OPTION_FRAME))
06573   {
06574     /* Disable DMA Request */
06575     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06576
06577     /* Call I2C Slave Sequential complete process */
06578     I2C_ITSlaveSeqCplt(hi2c);
06579   }
06580   else
06581   {
06582     /* No specific action, Master fully manage the generation of STOP condition */
06583     /* Mean that this generation can arrive at any time, at the end or during DMA process */
06584     /* So STOP condition should be manage through Interrupt treatment */
06585   }
06586 }
06587
06588 /**
06589   * @brief  DMA I2C communication error callback.
06590   * @param hdma DMA handle
06591   * @retval None
06592   */
06593 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
06594 {
06595   /* Derogation MISRAC2012-Rule-11.5 */
06596   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06597
06598   /* Disable Acknowledge */
06599   hi2c->Instance->CR2 |= I2C_CR2_NACK;
06600
06601   /* Call the corresponding callback to inform upper layer of End of Transfer */
06602   I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
06603 }
06604
06605 /**
06606   * @brief DMA I2C communication abort callback
06607   *        (To be called at end of DMA Abort procedure).
06608   * @param hdma DMA handle.
06609   * @retval None
06610   */
06611 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
06612 {
06613   /* Derogation MISRAC2012-Rule-11.5 */
06614   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
06615
06616   /* Reset AbortCpltCallback */
06617   if (hi2c->hdmatx != NULL)
06618   {
06619     hi2c->hdmatx->XferAbortCallback = NULL;
06620   }
06621   if (hi2c->hdmarx != NULL)
06622   {
06623     hi2c->hdmarx->XferAbortCallback = NULL;
06624   }
06625
06626   I2C_TreatErrorCallback(hi2c);
06627 }
06628
06629 /**
06630   * @brief  This function handles I2C Communication Timeout. It waits
06631   *                until a flag is no longer in the specified status.
06632   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06633   *                the configuration information for the specified I2C.
06634   * @param  Flag Specifies the I2C flag to check.
06635   * @param  Status The actual Flag status (SET or RESET).
06636   * @param  Timeout Timeout duration
06637   * @param  Tickstart Tick start value
06638   * @retval HAL status
06639   */
06640 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
06641                                                     uint32_t Timeout, uint32_t Tickstart)
06642 {
06643   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
06644   {
06645     /* Check for the Timeout */
06646     if (Timeout != HAL_MAX_DELAY)
06647     {
06648       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06649       {
06650         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06651         hi2c->State = HAL_I2C_STATE_READY;
06652         hi2c->Mode = HAL_I2C_MODE_NONE;
06653
06654         /* Process Unlocked */
06655         __HAL_UNLOCK(hi2c);
06656         return HAL_ERROR;
06657       }
06658     }
06659   }
06660   return HAL_OK;
06661 }
06662
06663 /**
06664   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
06665   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06666   *                the configuration information for the specified I2C.
06667   * @param  Timeout Timeout duration
06668   * @param  Tickstart Tick start value
06669   * @retval HAL status
06670   */
06671 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
06672                                                         uint32_t Tickstart)
06673 {
06674   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
06675   {
06676     /* Check if an error is detected */
06677     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
06678     {
06679       return HAL_ERROR;
06680     }
06681
06682     /* Check for the Timeout */
06683     if (Timeout != HAL_MAX_DELAY)
06684     {
06685       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06686       {
06687         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06688         hi2c->State = HAL_I2C_STATE_READY;
06689         hi2c->Mode = HAL_I2C_MODE_NONE;
06690
06691         /* Process Unlocked */
06692         __HAL_UNLOCK(hi2c);
06693
06694         return HAL_ERROR;
06695       }
06696     }
06697   }
06698   return HAL_OK;
06699 }
06700
06701 /**
06702   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
06703   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06704   *                the configuration information for the specified I2C.
06705   * @param  Timeout Timeout duration
06706   * @param  Tickstart Tick start value
06707   * @retval HAL status
06708   */
06709 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
06710                                                         uint32_t Tickstart)
06711 {
06712   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
06713   {
06714     /* Check if an error is detected */
06715     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
06716     {
06717       return HAL_ERROR;
06718     }
06719
06720     /* Check for the Timeout */
06721     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06722     {
06723       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06724       hi2c->State = HAL_I2C_STATE_READY;
06725       hi2c->Mode = HAL_I2C_MODE_NONE;
06726
06727       /* Process Unlocked */
06728       __HAL_UNLOCK(hi2c);
06729
06730       return HAL_ERROR;
06731     }
06732   }
06733   return HAL_OK;
06734 }
06735
06736 /**
06737   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
06738   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06739   *                the configuration information for the specified I2C.
06740   * @param  Timeout Timeout duration
06741   * @param  Tickstart Tick start value
06742   * @retval HAL status
06743   */
06744 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
06745                                                         uint32_t Tickstart)
06746 {
06747   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
06748   {
06749     /* Check if an error is detected */
06750     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
06751     {
06752       return HAL_ERROR;
06753     }
06754
06755     /* Check if a STOPF is detected */
06756     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
06757     {
06758       /* Check if an RXNE is pending */
06759       /* Store Last receive data if any */
06760       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
06761       {
06762         /* Return HAL_OK */
06763         /* The Reading of data from RXDR will be done in caller function */
06764         return HAL_OK;
06765       }
06766       else
06767       {
06768         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
06769         {
06770           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06771           hi2c->ErrorCode = HAL_I2C_ERROR_AF;
06772         }
06773         else
06774         {
06775           hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
06776         }
06777
06778         /* Clear STOP Flag */
06779         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06780
06781         /* Clear Configuration Register 2 */
06782         I2C_RESET_CR2(hi2c);
06783
06784         hi2c->State = HAL_I2C_STATE_READY;
06785         hi2c->Mode = HAL_I2C_MODE_NONE;
06786
06787         /* Process Unlocked */
06788         __HAL_UNLOCK(hi2c);
06789
06790         return HAL_ERROR;
06791       }
06792     }
06793
06794     /* Check for the Timeout */
06795     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06796     {
06797       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06798       hi2c->State = HAL_I2C_STATE_READY;
06799
06800       /* Process Unlocked */
06801       __HAL_UNLOCK(hi2c);
06802
06803       return HAL_ERROR;
06804     }
06805   }
06806   return HAL_OK;
06807 }
06808
06809 /**
06810   * @brief  This function handles errors detection during an I2C Communication.
06811   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06812   *                the configuration information for the specified I2C.
06813   * @param  Timeout Timeout duration
06814   * @param  Tickstart Tick start value
06815   * @retval HAL status
06816   */
06817 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06818 {
06819   HAL_StatusTypeDef status = HAL_OK;
06820   uint32_t itflag   = hi2c->Instance->ISR;
06821   uint32_t error_code = 0;
06822   uint32_t tickstart = Tickstart;
06823   uint32_t tmp1;
06824   HAL_I2C_ModeTypeDef tmp2;
06825
06826   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
06827   {
06828     /* Clear NACKF Flag */
06829     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06830
06831     /* Wait until STOP Flag is set or timeout occurred */
06832     /* AutoEnd should be initiate after AF */
06833     while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
06834     {
06835       /* Check for the Timeout */
06836       if (Timeout != HAL_MAX_DELAY)
06837       {
06838         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
06839         {
06840           tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
06841           tmp2 = hi2c->Mode;
06842
06843           /* In case of I2C still busy, try to regenerate a STOP manually */
06844           if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
06845               (tmp1 != I2C_CR2_STOP) && \
06846               (tmp2 != HAL_I2C_MODE_SLAVE))
06847           {
06848             /* Generate Stop */
06849             hi2c->Instance->CR2 |= I2C_CR2_STOP;
06850
06851             /* Update Tick with new reference */
06852             tickstart = HAL_GetTick();
06853           }
06854
06855           while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
06856           {
06857             /* Check for the Timeout */
06858             if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
06859             {
06860               error_code |=HAL_I2C_ERROR_TIMEOUT;
06861
06862               status = HAL_ERROR;
06863
06864               break;
06865             }
06866           }
06867         }
06868       }
06869     }
06870
06871     /* In case STOP Flag is detected, clear it */
06872     if (status == HAL_OK)
06873     {
06874       /* Clear STOP Flag */
06875       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06876     }
06877
06878     error_code |= HAL_I2C_ERROR_AF;
06879
06880     status = HAL_ERROR;
06881   }
06882
06883   /* Refresh Content of Status register */
06884   itflag = hi2c->Instance->ISR;
06885
06886   /* Then verify if an additional errors occurs */
06887   /* Check if a Bus error occurred */
06888   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
06889   {
06890     error_code |= HAL_I2C_ERROR_BERR;
06891
06892     /* Clear BERR flag */
06893     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
06894
06895     status = HAL_ERROR;
06896   }
06897
06898   /* Check if an Over-Run/Under-Run error occurred */
06899   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
06900   {
06901     error_code |= HAL_I2C_ERROR_OVR;
06902
06903     /* Clear OVR flag */
06904     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
06905
06906     status = HAL_ERROR;
06907   }
06908
06909   /* Check if an Arbitration Loss error occurred */
06910   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
06911   {
06912     error_code |= HAL_I2C_ERROR_ARLO;
06913
06914     /* Clear ARLO flag */
06915     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
06916
06917     status = HAL_ERROR;
06918   }
06919
06920   if (status != HAL_OK)
06921   {
06922     /* Flush TX register */
06923     I2C_Flush_TXDR(hi2c);
06924
06925     /* Clear Configuration Register 2 */
06926     I2C_RESET_CR2(hi2c);
06927
06928     hi2c->ErrorCode |= error_code;
06929     hi2c->State = HAL_I2C_STATE_READY;
06930     hi2c->Mode = HAL_I2C_MODE_NONE;
06931
06932     /* Process Unlocked */
06933     __HAL_UNLOCK(hi2c);
06934   }
06935
06936   return status;
06937 }
06938
06939 /**
06940   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
06941   * @param  hi2c I2C handle.
06942   * @param  DevAddress Specifies the slave address to be programmed.
06943   * @param  Size Specifies the number of bytes to be programmed.
06944   *   This parameter must be a value between 0 and 255.
06945   * @param  Mode New state of the I2C START condition generation.
06946   *   This parameter can be one of the following values:
06947   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
06948   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
06949   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
06950   * @param  Request New state of the I2C START condition generation.
06951   *   This parameter can be one of the following values:
06952   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
06953   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
06954   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
06955   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
06956   * @retval None
06957   */
06958 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
06959                                uint32_t Request)
06960 {
06961   /* Check the parameters */
06962   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
06963   assert_param(IS_TRANSFER_MODE(Mode));
06964   assert_param(IS_TRANSFER_REQUEST(Request));
06965
06966   /* Declaration of tmp to prevent undefined behavior of volatile usage */
06967   uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
06968                              (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
06969                              (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
06970
06971   /* update CR2 register */
06972   MODIFY_REG(hi2c->Instance->CR2, \
06973              ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
06974                (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
06975                I2C_CR2_START | I2C_CR2_STOP)), tmp);
06976 }
06977
06978 /**
06979   * @brief  Manage the enabling of Interrupts.
06980   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06981   *                the configuration information for the specified I2C.
06982   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
06983   * @retval None
06984   */
06985 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
06986 {
06987   uint32_t tmpisr = 0U;
06988
06989   if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
06990       (hi2c->XferISR == I2C_Slave_ISR_DMA))
06991   {
06992     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
06993     {
06994       /* Enable ERR, STOP, NACK and ADDR interrupts */
06995       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06996     }
06997
06998     if (InterruptRequest == I2C_XFER_ERROR_IT)
06999     {
07000       /* Enable ERR and NACK interrupts */
07001       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
07002     }
07003
07004     if (InterruptRequest == I2C_XFER_CPLT_IT)
07005     {
07006       /* Enable STOP interrupts */
07007       tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
07008     }
07009
07010     if (InterruptRequest == I2C_XFER_RELOAD_IT)
07011     {
07012       /* Enable TC interrupts */
07013       tmpisr |= I2C_IT_TCI;
07014     }
07015   }
07016   else
07017   {
07018     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
07019     {
07020       /* Enable ERR, STOP, NACK, and ADDR interrupts */
07021       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07022     }
07023
07024     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
07025     {
07026       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
07027       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
07028     }
07029
07030     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
07031     {
07032       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
07033       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
07034     }
07035
07036     if (InterruptRequest == I2C_XFER_ERROR_IT)
07037     {
07038       /* Enable ERR and NACK interrupts */
07039       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
07040     }
07041
07042     if (InterruptRequest == I2C_XFER_CPLT_IT)
07043     {
07044       /* Enable STOP interrupts */
07045       tmpisr |= I2C_IT_STOPI;
07046     }
07047   }
07048
07049   /* Enable interrupts only at the end */
07050   /* to avoid the risk of I2C interrupt handle execution before */
07051   /* all interrupts requested done */
07052   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
07053 }
07054
07055 /**
07056   * @brief  Manage the disabling of Interrupts.
07057   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
07058   *                the configuration information for the specified I2C.
07059   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
07060   * @retval None
07061   */
07062 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
07063 {
07064   uint32_t tmpisr = 0U;
07065
07066   if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
07067   {
07068     /* Disable TC and TXI interrupts */
07069     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
07070
07071     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
07072     {
07073       /* Disable NACK and STOP interrupts */
07074       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07075     }
07076   }
07077
07078   if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
07079   {
07080     /* Disable TC and RXI interrupts */
07081     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
07082
07083     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
07084     {
07085       /* Disable NACK and STOP interrupts */
07086       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07087     }
07088   }
07089
07090   if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
07091   {
07092     /* Disable ADDR, NACK and STOP interrupts */
07093     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
07094   }
07095
07096   if (InterruptRequest == I2C_XFER_ERROR_IT)
07097   {
07098     /* Enable ERR and NACK interrupts */
07099     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
07100   }
07101
07102   if (InterruptRequest == I2C_XFER_CPLT_IT)
07103   {
07104     /* Enable STOP interrupts */
07105     tmpisr |= I2C_IT_STOPI;
07106   }
07107
07108   if (InterruptRequest == I2C_XFER_RELOAD_IT)
07109   {
07110     /* Enable TC interrupts */
07111     tmpisr |= I2C_IT_TCI;
07112   }
07113
07114   /* Disable interrupts only at the end */
07115   /* to avoid a breaking situation like at "t" time */
07116   /* all disable interrupts request are not done */
07117   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
07118 }
07119
07120 /**
07121   * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
07122   * @param  hi2c I2C handle.
07123   * @retval None
07124   */
07125 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
07126 {
07127   /* if user set XferOptions to I2C_OTHER_FRAME            */
07128   /* it request implicitly to generate a restart condition */
07129   /* set XferOptions to I2C_FIRST_FRAME                    */
07130   if (hi2c->XferOptions == I2C_OTHER_FRAME)
07131   {
07132     hi2c->XferOptions = I2C_FIRST_FRAME;
07133   }
07134   /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
07135   /* it request implicitly to generate a restart condition    */
07136   /* then generate a stop condition at the end of transfer    */
07137   /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
07138   else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
07139   {
07140     hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
07141   }
07142   else
07143   {
07144     /* Nothing to do */
07145   }
07146 }
07147
07148 /**
07149   * @}
07150   */
07151
07152 #endif /* HAL_I2C_MODULE_ENABLED */
07153 /**
07154   * @}
07155   */
07156
07157 /**
07158   * @}
07159   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2c.h Source File

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stm32g0xx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_I2C_H
00021 #define STM32G0xx_HAL_I2C_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup I2C
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup I2C_Exported_Types I2C Exported Types
00040   * @{
00041   */
00042
00043 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
00044   * @brief  I2C Configuration Structure definition
00045   * @{
00046   */
00047 typedef struct
00048 {
00049   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
00050                                      This parameter calculated by referring to I2C initialization section
00051                                      in Reference manual */
00052
00053   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00054                                      This parameter can be a 7-bit or 10-bit address. */
00055
00056   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00057                                      This parameter can be a value of @ref I2C_ADDRESSING_MODE */
00058
00059   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00060                                      This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
00061
00062   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00063                                      This parameter can be a 7-bit address. */
00064
00065   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing
00066                                      mode is selected.
00067                                      This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
00068
00069   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00070                                      This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
00071
00072   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00073                                      This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
00074
00075 } I2C_InitTypeDef;
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup HAL_state_structure_definition HAL state structure definition
00082   * @brief  HAL State structure definition
00083   * @note  HAL I2C State value coding follow below described bitmap :\n
00084   *          b7-b6  Error information\n
00085   *             00 : No Error\n
00086   *             01 : Abort (Abort user request on going)\n
00087   *             10 : Timeout\n
00088   *             11 : Error\n
00089   *          b5     Peripheral initialization status\n
00090   *             0  : Reset (peripheral not initialized)\n
00091   *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
00092   *          b4     (not used)\n
00093   *             x  : Should be set to 0\n
00094   *          b3\n
00095   *             0  : Ready or Busy (No Listen mode ongoing)\n
00096   *             1  : Listen (peripheral in Address Listen Mode)\n
00097   *          b2     Intrinsic process state\n
00098   *             0  : Ready\n
00099   *             1  : Busy (peripheral busy with some configuration or internal operations)\n
00100   *          b1     Rx state\n
00101   *             0  : Ready (no Rx operation ongoing)\n
00102   *             1  : Busy (Rx operation ongoing)\n
00103   *          b0     Tx state\n
00104   *             0  : Ready (no Tx operation ongoing)\n
00105   *             1  : Busy (Tx operation ongoing)
00106   * @{
00107   */
00108 typedef enum
00109 {
00110   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00111   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00112   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00113   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00114   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00115   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00116   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00117                                                  process is ongoing                         */
00118   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00119                                                  process is ongoing                         */
00120   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
00121   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00122   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00123
00124 } HAL_I2C_StateTypeDef;
00125
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
00131   * @brief  HAL Mode structure definition
00132   * @note  HAL I2C Mode value coding follow below described bitmap :\n
00133   *          b7     (not used)\n
00134   *             x  : Should be set to 0\n
00135   *          b6\n
00136   *             0  : None\n
00137   *             1  : Memory (HAL I2C communication is in Memory Mode)\n
00138   *          b5\n
00139   *             0  : None\n
00140   *             1  : Slave (HAL I2C communication is in Slave Mode)\n
00141   *          b4\n
00142   *             0  : None\n
00143   *             1  : Master (HAL I2C communication is in Master Mode)\n
00144   *          b3-b2-b1-b0  (not used)\n
00145   *             xxxx : Should be set to 0000
00146   * @{
00147   */
00148 typedef enum
00149 {
00150   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00151   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00152   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00153   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00154
00155 } HAL_I2C_ModeTypeDef;
00156
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
00162   * @brief  I2C Error Code definition
00163   * @{
00164   */
00165 #define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
00166 #define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
00167 #define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
00168 #define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
00169 #define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
00170 #define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
00171 #define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00172 #define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
00173 #define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
00174 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00175 #define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
00176 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00177 #define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
00183   * @brief  I2C handle Structure definition
00184   * @{
00185   */
00186 typedef struct __I2C_HandleTypeDef
00187 {
00188   I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
00189
00190   I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
00191
00192   uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
00193
00194   uint16_t                   XferSize;       /*!< I2C transfer size                         */
00195
00196   __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
00197
00198   __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
00199                                                   be a value of @ref I2C_XFEROPTIONS */
00200
00201   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
00202
00203   HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00204   /*!< I2C transfer IRQ handler function pointer */
00205
00206   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
00207
00208   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
00209
00210   HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
00211
00212   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
00213
00214   __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
00215
00216   __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
00217
00218   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
00219
00220   __IO uint32_t              Devaddress;     /*!< I2C Target device address                 */
00221
00222   __IO uint32_t              Memaddress;     /*!< I2C Target memory address                 */
00223
00224 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00225   void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00226   /*!< I2C Master Tx Transfer completed callback */
00227   void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00228   /*!< I2C Master Rx Transfer completed callback */
00229   void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00230   /*!< I2C Slave Tx Transfer completed callback  */
00231   void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00232   /*!< I2C Slave Rx Transfer completed callback  */
00233   void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00234   /*!< I2C Listen Complete callback              */
00235   void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00236   /*!< I2C Memory Tx Transfer completed callback */
00237   void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00238   /*!< I2C Memory Rx Transfer completed callback */
00239   void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
00240   /*!< I2C Error callback                        */
00241   void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
00242   /*!< I2C Abort callback                        */
00243
00244   void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00245   /*!< I2C Slave Address Match callback */
00246
00247   void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
00248   /*!< I2C Msp Init callback                     */
00249   void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
00250   /*!< I2C Msp DeInit callback                   */
00251
00252 #endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
00253 } I2C_HandleTypeDef;
00254
00255 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00256 /**
00257   * @brief  HAL I2C Callback ID enumeration definition
00258   */
00259 typedef enum
00260 {
00261   HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
00262   HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
00263   HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
00264   HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
00265   HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
00266   HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
00267   HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
00268   HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
00269   HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
00270
00271   HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
00272   HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
00273
00274 } HAL_I2C_CallbackIDTypeDef;
00275
00276 /**
00277   * @brief  HAL I2C Callback pointer definition
00278   */
00279 typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
00280 /*!< pointer to an I2C callback function */
00281 typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
00282                                           uint16_t AddrMatchCode);
00283 /*!< pointer to an I2C Address Match callback function */
00284
00285 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293 /* Exported constants --------------------------------------------------------*/
00294
00295 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00296   * @{
00297   */
00298
00299 /** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
00300   * @{
00301   */
00302 #define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
00303 #define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00304 #define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00305 #define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
00306 #define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
00307 #define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
00308
00309 /* List of XferOptions in usage of :
00310  * 1- Restart condition in all use cases (direction change or not)
00311  */
00312 #define  I2C_OTHER_FRAME                (0x000000AAU)
00313 #define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
00319   * @{
00320   */
00321 #define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
00322 #define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
00328   * @{
00329   */
00330 #define I2C_DUALADDRESS_DISABLE         (0x00000000U)
00331 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
00337   * @{
00338   */
00339 #define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
00340 #define I2C_OA2_MASK01                  ((uint8_t)0x01U)
00341 #define I2C_OA2_MASK02                  ((uint8_t)0x02U)
00342 #define I2C_OA2_MASK03                  ((uint8_t)0x03U)
00343 #define I2C_OA2_MASK04                  ((uint8_t)0x04U)
00344 #define I2C_OA2_MASK05                  ((uint8_t)0x05U)
00345 #define I2C_OA2_MASK06                  ((uint8_t)0x06U)
00346 #define I2C_OA2_MASK07                  ((uint8_t)0x07U)
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
00352   * @{
00353   */
00354 #define I2C_GENERALCALL_DISABLE         (0x00000000U)
00355 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
00361   * @{
00362   */
00363 #define I2C_NOSTRETCH_DISABLE           (0x00000000U)
00364 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
00370   * @{
00371   */
00372 #define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
00373 #define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
00379   * @{
00380   */
00381 #define I2C_DIRECTION_TRANSMIT          (0x00000000U)
00382 #define I2C_DIRECTION_RECEIVE           (0x00000001U)
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
00388   * @{
00389   */
00390 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
00391 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
00392 #define  I2C_SOFTEND_MODE               (0x00000000U)
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
00398   * @{
00399   */
00400 #define  I2C_NO_STARTSTOP               (0x00000000U)
00401 #define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
00402 #define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00403 #define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
00404 /**
00405   * @}
00406   */
00407
00408 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00409   * @brief I2C Interrupt definition
00410   *        Elements values convention: 0xXXXXXXXX
00411   *           - XXXXXXXX  : Interrupt control mask
00412   * @{
00413   */
00414 #define I2C_IT_ERRI                     I2C_CR1_ERRIE
00415 #define I2C_IT_TCI                      I2C_CR1_TCIE
00416 #define I2C_IT_STOPI                    I2C_CR1_STOPIE
00417 #define I2C_IT_NACKI                    I2C_CR1_NACKIE
00418 #define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
00419 #define I2C_IT_RXI                      I2C_CR1_RXIE
00420 #define I2C_IT_TXI                      I2C_CR1_TXIE
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup I2C_Flag_definition I2C Flag definition
00426   * @{
00427   */
00428 #define I2C_FLAG_TXE                    I2C_ISR_TXE
00429 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
00430 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
00431 #define I2C_FLAG_ADDR                   I2C_ISR_ADDR
00432 #define I2C_FLAG_AF                     I2C_ISR_NACKF
00433 #define I2C_FLAG_STOPF                  I2C_ISR_STOPF
00434 #define I2C_FLAG_TC                     I2C_ISR_TC
00435 #define I2C_FLAG_TCR                    I2C_ISR_TCR
00436 #define I2C_FLAG_BERR                   I2C_ISR_BERR
00437 #define I2C_FLAG_ARLO                   I2C_ISR_ARLO
00438 #define I2C_FLAG_OVR                    I2C_ISR_OVR
00439 #define I2C_FLAG_PECERR                 I2C_ISR_PECERR
00440 #define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
00441 #define I2C_FLAG_ALERT                  I2C_ISR_ALERT
00442 #define I2C_FLAG_BUSY                   I2C_ISR_BUSY
00443 #define I2C_FLAG_DIR                    I2C_ISR_DIR
00444 /**
00445   * @}
00446   */
00447
00448 /**
00449   * @}
00450   */
00451
00452 /* Exported macros -----------------------------------------------------------*/
00453
00454 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00455   * @{
00456   */
00457
00458 /** @brief Reset I2C handle state.
00459   * @param  __HANDLE__ specifies the I2C Handle.
00460   * @retval None
00461   */
00462 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00463 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
00464                                                                     (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
00465                                                                     (__HANDLE__)->MspInitCallback = NULL;       \
00466                                                                     (__HANDLE__)->MspDeInitCallback = NULL;     \
00467                                                                   } while(0)
00468 #else
00469 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00470 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00471
00472 /** @brief  Enable the specified I2C interrupt.
00473   * @param  __HANDLE__ specifies the I2C Handle.
00474   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00475   *        This parameter can be one of the following values:
00476   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00477   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00478   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00479   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00480   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00481   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00482   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00483   *
00484   * @retval None
00485   */
00486 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00487
00488 /** @brief  Disable the specified I2C interrupt.
00489   * @param  __HANDLE__ specifies the I2C Handle.
00490   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00491   *        This parameter can be one of the following values:
00492   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00493   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00494   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00495   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00496   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00497   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00498   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00499   *
00500   * @retval None
00501   */
00502 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00503
00504 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
00505   * @param  __HANDLE__ specifies the I2C Handle.
00506   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
00507   *          This parameter can be one of the following values:
00508   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00509   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00510   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00511   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00512   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00513   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00514   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00515   *
00516   * @retval The new state of __INTERRUPT__ (SET or RESET).
00517   */
00518 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & \
00519                                                                    (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00520
00521 /** @brief  Check whether the specified I2C flag is set or not.
00522   * @param  __HANDLE__ specifies the I2C Handle.
00523   * @param  __FLAG__ specifies the flag to check.
00524   *        This parameter can be one of the following values:
00525   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00526   *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
00527   *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
00528   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00529   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00530   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00531   *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
00532   *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
00533   *            @arg @ref I2C_FLAG_BERR    Bus error
00534   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00535   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00536   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00537   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00538   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00539   *            @arg @ref I2C_FLAG_BUSY    Bus busy
00540   *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
00541   *
00542   * @retval The new state of __FLAG__ (SET or RESET).
00543   */
00544 #define I2C_FLAG_MASK  (0x0001FFFFU)
00545 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
00546                                                     (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00547
00548 /** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
00549   * @param  __HANDLE__ specifies the I2C Handle.
00550   * @param  __FLAG__ specifies the flag to clear.
00551   *          This parameter can be any combination of the following values:
00552   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00553   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00554   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00555   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00556   *            @arg @ref I2C_FLAG_BERR    Bus error
00557   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00558   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00559   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00560   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00561   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00562   *
00563   * @retval None
00564   */
00565 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
00566                                                     ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
00567                                                     ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00568
00569 /** @brief  Enable the specified I2C peripheral.
00570   * @param  __HANDLE__ specifies the I2C Handle.
00571   * @retval None
00572   */
00573 #define __HAL_I2C_ENABLE(__HANDLE__)                         (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00574
00575 /** @brief  Disable the specified I2C peripheral.
00576   * @param  __HANDLE__ specifies the I2C Handle.
00577   * @retval None
00578   */
00579 #define __HAL_I2C_DISABLE(__HANDLE__)                        (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00580
00581 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
00582   * @param  __HANDLE__ specifies the I2C Handle.
00583   * @retval None
00584   */
00585 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00586 /**
00587   * @}
00588   */
00589
00590 /* Include I2C HAL Extended module */
00591 #include "stm32g0xx_hal_i2c_ex.h"
00592
00593 /* Exported functions --------------------------------------------------------*/
00594 /** @addtogroup I2C_Exported_Functions
00595   * @{
00596   */
00597
00598 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00599   * @{
00600   */
00601 /* Initialization and de-initialization functions******************************/
00602 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00603 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
00604 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00605 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00606
00607 /* Callbacks Register/UnRegister functions  ***********************************/
00608 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00609 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
00610                                            pI2C_CallbackTypeDef pCallback);
00611 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
00612
00613 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
00614 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
00615 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00616 /**
00617   * @}
00618   */
00619
00620 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
00621   * @{
00622   */
00623 /* IO operation functions  ****************************************************/
00624 /******* Blocking mode: Polling */
00625 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00626                                           uint16_t Size, uint32_t Timeout);
00627 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00628                                          uint16_t Size, uint32_t Timeout);
00629 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00630                                          uint32_t Timeout);
00631 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00632                                         uint32_t Timeout);
00633 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00634                                     uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00635 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00636                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00637 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
00638                                         uint32_t Timeout);
00639
00640 /******* Non-Blocking mode: Interrupt */
00641 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00642                                              uint16_t Size);
00643 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00644                                             uint16_t Size);
00645 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00646 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00647 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00648                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00649 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00650                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00651
00652 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00653                                                  uint16_t Size, uint32_t XferOptions);
00654 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00655                                                 uint16_t Size, uint32_t XferOptions);
00656 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00657                                                 uint32_t XferOptions);
00658 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00659                                                uint32_t XferOptions);
00660 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00661 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00662 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00663
00664 /******* Non-Blocking mode: DMA */
00665 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00666                                               uint16_t Size);
00667 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00668                                              uint16_t Size);
00669 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00670 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00671 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00672                                         uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00673 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
00674                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00675
00676 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00677                                                   uint16_t Size, uint32_t XferOptions);
00678 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
00679                                                  uint16_t Size, uint32_t XferOptions);
00680 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00681                                                  uint32_t XferOptions);
00682 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
00683                                                 uint32_t XferOptions);
00684 /**
00685   * @}
00686   */
00687
00688 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00689   * @{
00690   */
00691 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00692 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00693 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00694 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00695 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00696 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00697 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00698 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00699 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00700 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00701 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00702 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00703 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
00704 /**
00705   * @}
00706   */
00707
00708 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
00709   * @{
00710   */
00711 /* Peripheral State, Mode and Error functions  *********************************/
00712 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00713 HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
00714 uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00715
00716 /**
00717   * @}
00718   */
00719
00720 /**
00721   * @}
00722   */
00723
00724 /* Private constants ---------------------------------------------------------*/
00725 /** @defgroup I2C_Private_Constants I2C Private Constants
00726   * @{
00727   */
00728
00729 /**
00730   * @}
00731   */
00732
00733 /* Private macros ------------------------------------------------------------*/
00734 /** @defgroup I2C_Private_Macro I2C Private Macros
00735   * @{
00736   */
00737
00738 #define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
00739                                          ((MODE) == I2C_ADDRESSINGMODE_10BIT))
00740
00741 #define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00742                                          ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00743
00744 #define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
00745                                          ((MASK) == I2C_OA2_MASK01) || \
00746                                          ((MASK) == I2C_OA2_MASK02) || \
00747                                          ((MASK) == I2C_OA2_MASK03) || \
00748                                          ((MASK) == I2C_OA2_MASK04) || \
00749                                          ((MASK) == I2C_OA2_MASK05) || \
00750                                          ((MASK) == I2C_OA2_MASK06) || \
00751                                          ((MASK) == I2C_OA2_MASK07))
00752
00753 #define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
00754                                          ((CALL) == I2C_GENERALCALL_ENABLE))
00755
00756 #define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00757                                          ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00758
00759 #define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00760                                          ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00761
00762 #define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
00763                                          ((MODE) == I2C_AUTOEND_MODE) || \
00764                                          ((MODE) == I2C_SOFTEND_MODE))
00765
00766 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
00767                                          ((REQUEST) == I2C_GENERATE_START_READ)  || \
00768                                          ((REQUEST) == I2C_GENERATE_START_WRITE) || \
00769                                          ((REQUEST) == I2C_NO_STARTSTOP))
00770
00771 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
00772                                                    ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
00773                                                    ((REQUEST) == I2C_NEXT_FRAME)           || \
00774                                                    ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
00775                                                    ((REQUEST) == I2C_LAST_FRAME)           || \
00776                                                    ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
00777                                                    IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
00778
00779 #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
00780                                                         ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
00781
00782 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= \
00783                                                    (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
00784                                                                           I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
00785                                                                           I2C_CR2_RD_WRN)))
00786
00787 #define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
00788                                                               >> 16U))
00789 #define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
00790                                                              >> 16U))
00791 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00792 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
00793 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
00794
00795 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
00796 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
00797
00798 #define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
00799                                                                          (uint16_t)(0xFF00U))) >> 8U)))
00800 #define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00801
00802 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
00803                                                      (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
00804                                                                  (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
00805                                                                 (~I2C_CR2_RD_WRN)) : \
00806                                                      (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
00807                                                                  (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
00808                                                                 (~I2C_CR2_RD_WRN)))
00809
00810 #define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
00811                                                     ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
00812 #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
00813 /**
00814   * @}
00815   */
00816
00817 /* Private Functions ---------------------------------------------------------*/
00818 /** @defgroup I2C_Private_Functions I2C Private Functions
00819   * @{
00820   */
00821 /* Private functions are defined in stm32g0xx_hal_i2c.c file */
00822 /**
00823   * @}
00824   */
00825
00826 /**
00827   * @}
00828   */
00829
00830 /**
00831   * @}
00832   */
00833
00834 #ifdef __cplusplus
00835 }
00836 #endif
00837
00838
00839 #endif /* STM32G0xx_HAL_I2C_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2c_ex.c Source File

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stm32g0xx_hal_i2c_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @brief   I2C Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of I2C Extended peripheral:
00008   *           + Filter Mode Functions
00009   *           + WakeUp Mode Functions
00010   *           + FastModePlus Functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                ##### I2C peripheral Extended features  #####
00026   ==============================================================================
00027
00028   [..] Comparing to other previous devices, the I2C interface for STM32G0xx
00029        devices contains the following additional features
00030
00031        (+) Possibility to disable or enable Analog Noise Filter
00032        (+) Use of a configured Digital Noise Filter
00033        (+) Disable or enable wakeup from Stop mode(s)
00034        (+) Disable or enable Fast Mode Plus
00035
00036                      ##### How to use this driver #####
00037   ==============================================================================
00038   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
00039     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
00040     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
00041     (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
00042           (++) HAL_I2CEx_EnableWakeUp()
00043           (++) HAL_I2CEx_DisableWakeUp()
00044     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00045           (++) HAL_I2CEx_EnableFastModePlus()
00046           (++) HAL_I2CEx_DisableFastModePlus()
00047   @endverbatim
00048   */
00049
00050 /* Includes ------------------------------------------------------------------*/
00051 #include "stm32g0xx_hal.h"
00052
00053 /** @addtogroup STM32G0xx_HAL_Driver
00054   * @{
00055   */
00056
00057 /** @defgroup I2CEx I2CEx
00058   * @brief I2C Extended HAL module driver
00059   * @{
00060   */
00061
00062 #ifdef HAL_I2C_MODULE_ENABLED
00063
00064 /* Private typedef -----------------------------------------------------------*/
00065 /* Private define ------------------------------------------------------------*/
00066 /* Private macro -------------------------------------------------------------*/
00067 /* Private variables ---------------------------------------------------------*/
00068 /* Private function prototypes -----------------------------------------------*/
00069 /* Private functions ---------------------------------------------------------*/
00070
00071 /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
00072   * @{
00073   */
00074
00075 /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
00076   * @brief    Filter Mode Functions
00077   *
00078 @verbatim
00079  ===============================================================================
00080                       ##### Filter Mode Functions #####
00081  ===============================================================================
00082     [..] This section provides functions allowing to:
00083       (+) Configure Noise Filters
00084
00085 @endverbatim
00086   * @{
00087   */
00088
00089 /**
00090   * @brief  Configure I2C Analog noise filter.
00091   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00092   *                the configuration information for the specified I2Cx peripheral.
00093   * @param  AnalogFilter New state of the Analog filter.
00094   * @retval HAL status
00095   */
00096 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00097 {
00098   /* Check the parameters */
00099   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00100   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00101
00102   if (hi2c->State == HAL_I2C_STATE_READY)
00103   {
00104     /* Process Locked */
00105     __HAL_LOCK(hi2c);
00106
00107     hi2c->State = HAL_I2C_STATE_BUSY;
00108
00109     /* Disable the selected I2C peripheral */
00110     __HAL_I2C_DISABLE(hi2c);
00111
00112     /* Reset I2Cx ANOFF bit */
00113     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00114
00115     /* Set analog filter bit*/
00116     hi2c->Instance->CR1 |= AnalogFilter;
00117
00118     __HAL_I2C_ENABLE(hi2c);
00119
00120     hi2c->State = HAL_I2C_STATE_READY;
00121
00122     /* Process Unlocked */
00123     __HAL_UNLOCK(hi2c);
00124
00125     return HAL_OK;
00126   }
00127   else
00128   {
00129     return HAL_BUSY;
00130   }
00131 }
00132
00133 /**
00134   * @brief  Configure I2C Digital noise filter.
00135   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00136   *                the configuration information for the specified I2Cx peripheral.
00137   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00138   * @retval HAL status
00139   */
00140 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00141 {
00142   uint32_t tmpreg;
00143
00144   /* Check the parameters */
00145   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00146   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00147
00148   if (hi2c->State == HAL_I2C_STATE_READY)
00149   {
00150     /* Process Locked */
00151     __HAL_LOCK(hi2c);
00152
00153     hi2c->State = HAL_I2C_STATE_BUSY;
00154
00155     /* Disable the selected I2C peripheral */
00156     __HAL_I2C_DISABLE(hi2c);
00157
00158     /* Get the old register value */
00159     tmpreg = hi2c->Instance->CR1;
00160
00161     /* Reset I2Cx DNF bits [11:8] */
00162     tmpreg &= ~(I2C_CR1_DNF);
00163
00164     /* Set I2Cx DNF coefficient */
00165     tmpreg |= DigitalFilter << 8U;
00166
00167     /* Store the new register value */
00168     hi2c->Instance->CR1 = tmpreg;
00169
00170     __HAL_I2C_ENABLE(hi2c);
00171
00172     hi2c->State = HAL_I2C_STATE_READY;
00173
00174     /* Process Unlocked */
00175     __HAL_UNLOCK(hi2c);
00176
00177     return HAL_OK;
00178   }
00179   else
00180   {
00181     return HAL_BUSY;
00182   }
00183 }
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
00189   * @brief    WakeUp Mode Functions
00190   *
00191 @verbatim
00192  ===============================================================================
00193                       ##### WakeUp Mode Functions #####
00194  ===============================================================================
00195     [..] This section provides functions allowing to:
00196       (+) Configure Wake Up Feature
00197
00198 @endverbatim
00199   * @{
00200   */
00201
00202 /**
00203   * @brief  Enable I2C wakeup from Stop mode(s).
00204   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00205   *                the configuration information for the specified I2Cx peripheral.
00206   * @retval HAL status
00207   */
00208 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
00209 {
00210   /* Check the parameters */
00211   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00212
00213   if (hi2c->State == HAL_I2C_STATE_READY)
00214   {
00215     /* Process Locked */
00216     __HAL_LOCK(hi2c);
00217
00218     hi2c->State = HAL_I2C_STATE_BUSY;
00219
00220     /* Disable the selected I2C peripheral */
00221     __HAL_I2C_DISABLE(hi2c);
00222
00223     /* Enable wakeup from stop mode */
00224     hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
00225
00226     __HAL_I2C_ENABLE(hi2c);
00227
00228     hi2c->State = HAL_I2C_STATE_READY;
00229
00230     /* Process Unlocked */
00231     __HAL_UNLOCK(hi2c);
00232
00233     return HAL_OK;
00234   }
00235   else
00236   {
00237     return HAL_BUSY;
00238   }
00239 }
00240
00241 /**
00242   * @brief  Disable I2C wakeup from Stop mode(s).
00243   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00244   *                the configuration information for the specified I2Cx peripheral.
00245   * @retval HAL status
00246   */
00247 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
00248 {
00249   /* Check the parameters */
00250   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00251
00252   if (hi2c->State == HAL_I2C_STATE_READY)
00253   {
00254     /* Process Locked */
00255     __HAL_LOCK(hi2c);
00256
00257     hi2c->State = HAL_I2C_STATE_BUSY;
00258
00259     /* Disable the selected I2C peripheral */
00260     __HAL_I2C_DISABLE(hi2c);
00261
00262     /* Enable wakeup from stop mode */
00263     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00264
00265     __HAL_I2C_ENABLE(hi2c);
00266
00267     hi2c->State = HAL_I2C_STATE_READY;
00268
00269     /* Process Unlocked */
00270     __HAL_UNLOCK(hi2c);
00271
00272     return HAL_OK;
00273   }
00274   else
00275   {
00276     return HAL_BUSY;
00277   }
00278 }
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
00284   * @brief    Fast Mode Plus Functions
00285   *
00286 @verbatim
00287  ===============================================================================
00288                       ##### Fast Mode Plus Functions #####
00289  ===============================================================================
00290     [..] This section provides functions allowing to:
00291       (+) Configure Fast Mode Plus
00292
00293 @endverbatim
00294   * @{
00295   */
00296
00297 /**
00298   * @brief Enable the I2C fast mode plus driving capability.
00299   * @param ConfigFastModePlus Selects the pin.
00300   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00301   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00302   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00303   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00304   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00305   *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00306   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
00307   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00308   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
00309   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00310   * @retval None
00311   */
00312 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00313 {
00314   /* Check the parameter */
00315   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00316
00317   /* Enable SYSCFG clock */
00318   __HAL_RCC_SYSCFG_CLK_ENABLE();
00319
00320   /* Enable fast mode plus driving capability for selected pin */
00321   SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00322 }
00323
00324 /**
00325   * @brief Disable the I2C fast mode plus driving capability.
00326   * @param ConfigFastModePlus Selects the pin.
00327   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00328   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
00329   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00330   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00331   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00332   *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00333   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
00334   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00335   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
00336   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00337   * @retval None
00338   */
00339 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00340 {
00341   /* Check the parameter */
00342   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00343
00344   /* Enable SYSCFG clock */
00345   __HAL_RCC_SYSCFG_CLK_ENABLE();
00346
00347   /* Disable fast mode plus driving capability for selected pin */
00348   CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00349 }
00350 /**
00351   * @}
00352   */
00353 /**
00354   * @}
00355   */
00356
00357 #endif /* HAL_I2C_MODULE_ENABLED */
00358 /**
00359   * @}
00360   */
00361
00362 /**
00363   * @}
00364   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2c_ex.h Source File

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stm32g0xx_hal_i2c_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_I2C_EX_H
00021 #define STM32G0xx_HAL_I2C_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup I2CEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
00041   * @{
00042   */
00043
00044 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
00045   * @{
00046   */
00047 #define I2C_ANALOGFILTER_ENABLE         0x00000000U
00048 #define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
00049 /**
00050   * @}
00051   */
00052
00053 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
00054   * @{
00055   */
00056 #define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
00057 #define I2C_FASTMODEPLUS_PA9            SYSCFG_CFGR1_I2C_PA9_FMP                        /*!< Enable Fast Mode Plus on PA9       */
00058 #define I2C_FASTMODEPLUS_PA10           SYSCFG_CFGR1_I2C_PA10_FMP                       /*!< Enable Fast Mode Plus on PA10      */
00059 #define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
00060 #define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
00061 #define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
00062 #define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
00063 #define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
00064 #define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
00065 #if defined(SYSCFG_CFGR1_I2C3_FMP)
00066 #define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
00067 #else
00068 #define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
00069 #endif /* SYSCFG_CFGR1_I2C3_FMP */
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Exported macro ------------------------------------------------------------*/
00079 /** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
00080   * @{
00081   */
00082
00083 /**
00084   * @}
00085   */
00086
00087 /* Exported functions --------------------------------------------------------*/
00088 /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
00089   * @{
00090   */
00091
00092 /** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
00093   * @{
00094   */
00095 /* Peripheral Control functions  ************************************************/
00096 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00097 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00098 /**
00099   * @}
00100   */
00101
00102 /** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
00103   * @{
00104   */
00105 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
00106 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
00107 /**
00108   * @}
00109   */
00110
00111 /** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
00112   * @{
00113   */
00114 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00115 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 /* Private constants ---------------------------------------------------------*/
00125 /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
00126   * @{
00127   */
00128
00129 /**
00130   * @}
00131   */
00132
00133 /* Private macros ------------------------------------------------------------*/
00134 /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
00135   * @{
00136   */
00137 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00138                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00139
00140 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
00141
00142 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
00143                                          ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9))  == I2C_FASTMODEPLUS_PA9)     || \
00144                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10)    || \
00145                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
00146                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
00147                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
00148                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
00149                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
00150                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
00151                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
00152 /**
00153   * @}
00154   */
00155
00156 /* Private Functions ---------------------------------------------------------*/
00157 /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
00158   * @{
00159   */
00160 /* Private functions are defined in stm32g0xx_hal_i2c_ex.c file */
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 #ifdef __cplusplus
00174 }
00175 #endif
00176
00177 #endif /* STM32G0xx_HAL_I2C_EX_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2s.c Source File

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stm32g0xx_hal_i2s.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_i2s.c
00004   * @author  MCD Application Team
00005   * @brief   I2S HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2018 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023  ===============================================================================
00024                   ##### How to use this driver #####
00025  ===============================================================================
00026  [..]
00027     The I2S HAL driver can be used as follow:
00028
00029     (#) Declare a I2S_HandleTypeDef handle structure.
00030     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
00031         (##) Enable the SPIx interface clock.
00032         (##) I2S pins configuration:
00033             (+++) Enable the clock for the I2S GPIOs.
00034             (+++) Configure these I2S pins as alternate function pull-up.
00035         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
00036              and HAL_I2S_Receive_IT() APIs).
00037             (+++) Configure the I2Sx interrupt priority.
00038             (+++) Enable the NVIC I2S IRQ handle.
00039         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
00040              and HAL_I2S_Receive_DMA() APIs:
00041             (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
00042             (+++) Enable the DMAx interface clock.
00043             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00044             (+++) Configure the DMA Tx/Rx Stream/Channel.
00045             (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
00046             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00047                   DMA Tx/Rx Stream/Channel.
00048
00049    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00050        using HAL_I2S_Init() function.
00051
00052    -@- The specific I2S interrupts (Transmission complete interrupt,
00053        RXNE interrupt and Error Interrupts) will be managed using the macros
00054        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
00055    -@- Make sure that either:
00056         (+@) SYSCLK is configured or
00057         (+@) PLLPCLK output is configured or
00058         (+@) HSI is enabled or
00059         (+@) External clock source is configured after setting correctly
00060              the define constant EXTERNAL_I2S1_CLOCK_VALUE in the stm32g0xx_hal_conf.h file.
00061
00062     (#) Three mode of operations are available within this driver :
00063
00064    *** Polling mode IO operation ***
00065    =================================
00066    [..]
00067      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
00068      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
00069
00070    *** Interrupt mode IO operation ***
00071    ===================================
00072    [..]
00073      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
00074      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00075          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00076      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00077          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00078      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
00079      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00080          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00081      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00082          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00083      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00084          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00085
00086    *** DMA mode IO operation ***
00087    ==============================
00088    [..]
00089      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
00090      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00091          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00092      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00093          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00094      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
00095      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00096          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00097      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00098          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00099      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00100          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00101      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00102      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00103      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00104          In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
00105          HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
00106          In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
00107          inside DR register and avoid using DeInit/Init process for the next transfer.
00108
00109    *** I2S HAL driver macros list ***
00110    ===================================
00111    [..]
00112      Below the list of most used macros in I2S HAL driver.
00113
00114       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
00115       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
00116       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
00117       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
00118       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
00119       (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
00120
00121     [..]
00122       (@) You can refer to the I2S HAL driver header file for more useful macros
00123
00124    *** I2S HAL driver macros list ***
00125    ===================================
00126    [..]
00127        Callback registration:
00128
00129       (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
00130           allows the user to configure dynamically the driver callbacks.
00131           Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
00132
00133           Function HAL_I2S_RegisterCallback() allows to register following callbacks:
00134             (++) TxCpltCallback        : I2S Tx Completed callback
00135             (++) RxCpltCallback        : I2S Rx Completed callback
00136             (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
00137             (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
00138             (++) ErrorCallback         : I2S Error callback
00139             (++) MspInitCallback       : I2S Msp Init callback
00140             (++) MspDeInitCallback     : I2S Msp DeInit callback
00141           This function takes as parameters the HAL peripheral handle, the Callback ID
00142           and a pointer to the user callback function.
00143
00144
00145       (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
00146           weak function.
00147           HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
00148           and the Callback ID.
00149           This function allows to reset following callbacks:
00150             (++) TxCpltCallback        : I2S Tx Completed callback
00151             (++) RxCpltCallback        : I2S Rx Completed callback
00152             (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
00153             (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
00154             (++) ErrorCallback         : I2S Error callback
00155             (++) MspInitCallback       : I2S Msp Init callback
00156             (++) MspDeInitCallback     : I2S Msp DeInit callback
00157
00158        [..]
00159        By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
00160        all callbacks are set to the corresponding weak functions:
00161        examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
00162        Exception done for MspInit and MspDeInit functions that are
00163        reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
00164        these callbacks are null (not registered beforehand).
00165        If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
00166        keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00167
00168        [..]
00169        Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
00170        Exception done MspInit/MspDeInit functions that can be registered/unregistered
00171        in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
00172        thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00173        Then, the user first registers the MspInit/MspDeInit user callbacks
00174        using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
00175        or HAL_I2S_Init() function.
00176
00177        [..]
00178        When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
00179        not defined, the callback registering feature is not available
00180        and weak (surcharged) callbacks are used.
00181
00182   @endverbatim
00183
00184   */
00185
00186 /* Includes ------------------------------------------------------------------*/
00187 #include "stm32g0xx_hal.h"
00188
00189 #ifdef HAL_I2S_MODULE_ENABLED
00190
00191 #if defined(SPI_I2S_SUPPORT)
00192 /** @addtogroup STM32G0xx_HAL_Driver
00193   * @{
00194   */
00195
00196 /** @defgroup I2S I2S
00197   * @brief I2S HAL module driver
00198   * @{
00199   */
00200
00201 /* Private typedef -----------------------------------------------------------*/
00202 /* Private define ------------------------------------------------------------*/
00203 #define I2S_TIMEOUT_FLAG          100U         /*!< Timeout 100 ms            */
00204 /* Private macro -------------------------------------------------------------*/
00205 /* Private variables ---------------------------------------------------------*/
00206 /* Private function prototypes -----------------------------------------------*/
00207 /** @defgroup I2S_Private_Functions I2S Private Functions
00208   * @{
00209   */
00210 static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
00211 static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00212 static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
00213 static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00214 static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
00215 static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
00216 static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
00217 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
00218                                                         uint32_t Timeout);
00219 /**
00220   * @}
00221   */
00222
00223 /* Exported functions ---------------------------------------------------------*/
00224
00225 /** @defgroup I2S_Exported_Functions I2S Exported Functions
00226   * @{
00227   */
00228
00229 /** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00230   *  @brief    Initialization and Configuration functions
00231   *
00232 @verbatim
00233  ===============================================================================
00234               ##### Initialization and de-initialization functions #####
00235  ===============================================================================
00236     [..]  This subsection provides a set of functions allowing to initialize and
00237           de-initialize the I2Sx peripheral in simplex mode:
00238
00239       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00240           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00241
00242       (+) Call the function HAL_I2S_Init() to configure the selected device with
00243           the selected configuration:
00244         (++) Mode
00245         (++) Standard
00246         (++) Data Format
00247         (++) MCLK Output
00248         (++) Audio frequency
00249         (++) Polarity
00250
00251      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00252           of the selected I2Sx peripheral.
00253   @endverbatim
00254   * @{
00255   */
00256
00257 /**
00258   * @brief  Initializes the I2S according to the specified parameters
00259   *         in the I2S_InitTypeDef and create the associated handle.
00260   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00261   *         the configuration information for I2S module
00262   * @retval HAL status
00263   */
00264 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00265 {
00266   uint32_t i2sdiv;
00267   uint32_t i2sodd;
00268   uint32_t packetlength;
00269   uint32_t tmp;
00270   uint32_t i2sclk;
00271
00272   /* Check the I2S handle allocation */
00273   if (hi2s == NULL)
00274   {
00275     return HAL_ERROR;
00276   }
00277
00278   /* Check the I2S parameters */
00279   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00280   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00281   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00282   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00283   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00284   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00285   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00286
00287   if (hi2s->State == HAL_I2S_STATE_RESET)
00288   {
00289     /* Allocate lock resource and initialize it */
00290     hi2s->Lock = HAL_UNLOCKED;
00291
00292 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00293     /* Init the I2S Callback settings */
00294     hi2s->TxCpltCallback       = HAL_I2S_TxCpltCallback;          /* Legacy weak TxCpltCallback       */
00295     hi2s->RxCpltCallback       = HAL_I2S_RxCpltCallback;          /* Legacy weak RxCpltCallback       */
00296     hi2s->TxHalfCpltCallback   = HAL_I2S_TxHalfCpltCallback;      /* Legacy weak TxHalfCpltCallback   */
00297     hi2s->RxHalfCpltCallback   = HAL_I2S_RxHalfCpltCallback;      /* Legacy weak RxHalfCpltCallback   */
00298     hi2s->ErrorCallback        = HAL_I2S_ErrorCallback;           /* Legacy weak ErrorCallback        */
00299
00300     if (hi2s->MspInitCallback == NULL)
00301     {
00302       hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit  */
00303     }
00304
00305     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00306     hi2s->MspInitCallback(hi2s);
00307 #else
00308     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00309     HAL_I2S_MspInit(hi2s);
00310 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00311   }
00312
00313   hi2s->State = HAL_I2S_STATE_BUSY;
00314
00315   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
00316   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00317   CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00318                                       SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00319                                       SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
00320   hi2s->Instance->I2SPR = 0x0002U;
00321
00322   /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
00323   /* If the requested audio frequency is not the default, compute the prescaler */
00324   if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
00325   {
00326     /* Check the frame length (For the Prescaler computing) ********************/
00327     if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
00328     {
00329       /* Packet length is 16 bits */
00330       packetlength = 16U;
00331     }
00332     else
00333     {
00334       /* Packet length is 32 bits */
00335       packetlength = 32U;
00336     }
00337
00338     /* I2S standard */
00339     if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
00340     {
00341       /* In I2S standard packet length is multiplied by 2 */
00342       packetlength = packetlength * 2U;
00343     }
00344
00345 #if defined (RCC_PERIPHCLK_I2S2)
00346     if (hi2s->Instance == SPI1)
00347     {
00348       /* Get the source clock value: based on System Clock value */
00349       i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S1);
00350     }
00351     else /* SPI2 case */
00352     {
00353       /* Get the source clock value: based on System Clock value */
00354       i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2);
00355     }
00356 #else
00357     /* Get the source clock value: based on System Clock value */
00358     i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S1);
00359 #endif /* RCC_PERIPHCLK_I2S2 */
00360     /* Compute the Real divider depending on the MCLK output state, with a floating point */
00361     if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00362     {
00363       /* MCLK output is enabled */
00364       if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00365       {
00366         tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00367       }
00368       else
00369       {
00370         tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00371       }
00372     }
00373     else
00374     {
00375       /* MCLK output is disabled */
00376       tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00377     }
00378
00379     /* Remove the flatting point */
00380     tmp = tmp / 10U;
00381
00382     /* Check the parity of the divider */
00383     i2sodd = (uint32_t)(tmp & (uint32_t)1U);
00384
00385     /* Compute the i2sdiv prescaler */
00386     i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
00387
00388     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00389     i2sodd = (uint32_t)(i2sodd << 8U);
00390   }
00391   else
00392   {
00393     /* Set the default values */
00394     i2sdiv = 2U;
00395     i2sodd = 0U;
00396   }
00397
00398   /* Test if the divider is 1 or 0 or greater than 0xFF */
00399   if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00400   {
00401     /* Set the error code and execute error callback*/
00402     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
00403     return  HAL_ERROR;
00404   }
00405
00406   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
00407
00408   /* Write to SPIx I2SPR register the computed value */
00409   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
00410
00411   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00412   /* And configure the I2S with the I2S_InitStruct values                      */
00413   MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
00414                                        SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
00415                                        SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00416                                        SPI_I2SCFGR_I2SE  | SPI_I2SCFGR_I2SMOD), \
00417              (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
00418               hi2s->Init.Standard | hi2s->Init.DataFormat | \
00419               hi2s->Init.CPOL));
00420
00421 #if defined(SPI_I2SCFGR_ASTRTEN)
00422   if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
00423   {
00424     /* Write to SPIx I2SCFGR */
00425     SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
00426   }
00427 #endif /* SPI_I2SCFGR_ASTRTEN */
00428
00429   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00430   hi2s->State     = HAL_I2S_STATE_READY;
00431
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @brief DeInitializes the I2S peripheral
00437   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00438   *         the configuration information for I2S module
00439   * @retval HAL status
00440   */
00441 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
00442 {
00443   /* Check the I2S handle allocation */
00444   if (hi2s == NULL)
00445   {
00446     return HAL_ERROR;
00447   }
00448
00449   /* Check the parameters */
00450   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00451
00452   hi2s->State = HAL_I2S_STATE_BUSY;
00453
00454   /* Disable the I2S Peripheral Clock */
00455   __HAL_I2S_DISABLE(hi2s);
00456
00457 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00458   if (hi2s->MspDeInitCallback == NULL)
00459   {
00460     hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit  */
00461   }
00462
00463   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00464   hi2s->MspDeInitCallback(hi2s);
00465 #else
00466   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00467   HAL_I2S_MspDeInit(hi2s);
00468 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00469
00470   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00471   hi2s->State     = HAL_I2S_STATE_RESET;
00472
00473   /* Release Lock */
00474   __HAL_UNLOCK(hi2s);
00475
00476   return HAL_OK;
00477 }
00478
00479 /**
00480   * @brief I2S MSP Init
00481   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00482   *         the configuration information for I2S module
00483   * @retval None
00484   */
00485 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
00486 {
00487   /* Prevent unused argument(s) compilation warning */
00488   UNUSED(hi2s);
00489
00490   /* NOTE : This function Should not be modified, when the callback is needed,
00491             the HAL_I2S_MspInit could be implemented in the user file
00492    */
00493 }
00494
00495 /**
00496   * @brief I2S MSP DeInit
00497   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00498   *         the configuration information for I2S module
00499   * @retval None
00500   */
00501 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
00502 {
00503   /* Prevent unused argument(s) compilation warning */
00504   UNUSED(hi2s);
00505
00506   /* NOTE : This function Should not be modified, when the callback is needed,
00507             the HAL_I2S_MspDeInit could be implemented in the user file
00508    */
00509 }
00510
00511 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00512 /**
00513   * @brief  Register a User I2S Callback
00514   *         To be used instead of the weak predefined callback
00515   * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
00516   *                the configuration information for the specified I2S.
00517   * @param  CallbackID ID of the callback to be registered
00518   * @param  pCallback pointer to the Callback function
00519   * @retval HAL status
00520   */
00521 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
00522                                            pI2S_CallbackTypeDef pCallback)
00523 {
00524   HAL_StatusTypeDef status = HAL_OK;
00525
00526   if (pCallback == NULL)
00527   {
00528     /* Update the error code */
00529     hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
00530
00531     return HAL_ERROR;
00532   }
00533   /* Process locked */
00534   __HAL_LOCK(hi2s);
00535
00536   if (HAL_I2S_STATE_READY == hi2s->State)
00537   {
00538     switch (CallbackID)
00539     {
00540       case HAL_I2S_TX_COMPLETE_CB_ID :
00541         hi2s->TxCpltCallback = pCallback;
00542         break;
00543
00544       case HAL_I2S_RX_COMPLETE_CB_ID :
00545         hi2s->RxCpltCallback = pCallback;
00546         break;
00547
00548       case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
00549         hi2s->TxHalfCpltCallback = pCallback;
00550         break;
00551
00552       case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
00553         hi2s->RxHalfCpltCallback = pCallback;
00554         break;
00555
00556       case HAL_I2S_ERROR_CB_ID :
00557         hi2s->ErrorCallback = pCallback;
00558         break;
00559
00560       case HAL_I2S_MSPINIT_CB_ID :
00561         hi2s->MspInitCallback = pCallback;
00562         break;
00563
00564       case HAL_I2S_MSPDEINIT_CB_ID :
00565         hi2s->MspDeInitCallback = pCallback;
00566         break;
00567
00568       default :
00569         /* Update the error code */
00570         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00571
00572         /* Return error status */
00573         status =  HAL_ERROR;
00574         break;
00575     }
00576   }
00577   else if (HAL_I2S_STATE_RESET == hi2s->State)
00578   {
00579     switch (CallbackID)
00580     {
00581       case HAL_I2S_MSPINIT_CB_ID :
00582         hi2s->MspInitCallback = pCallback;
00583         break;
00584
00585       case HAL_I2S_MSPDEINIT_CB_ID :
00586         hi2s->MspDeInitCallback = pCallback;
00587         break;
00588
00589       default :
00590         /* Update the error code */
00591         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00592
00593         /* Return error status */
00594         status =  HAL_ERROR;
00595         break;
00596     }
00597   }
00598   else
00599   {
00600     /* Update the error code */
00601     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00602
00603     /* Return error status */
00604     status =  HAL_ERROR;
00605   }
00606
00607   /* Release Lock */
00608   __HAL_UNLOCK(hi2s);
00609   return status;
00610 }
00611
00612 /**
00613   * @brief  Unregister an I2S Callback
00614   *         I2S callback is redirected to the weak predefined callback
00615   * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
00616   *                the configuration information for the specified I2S.
00617   * @param  CallbackID ID of the callback to be unregistered
00618   * @retval HAL status
00619   */
00620 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
00621 {
00622   HAL_StatusTypeDef status = HAL_OK;
00623
00624   /* Process locked */
00625   __HAL_LOCK(hi2s);
00626
00627   if (HAL_I2S_STATE_READY == hi2s->State)
00628   {
00629     switch (CallbackID)
00630     {
00631       case HAL_I2S_TX_COMPLETE_CB_ID :
00632         hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback;                /* Legacy weak TxCpltCallback       */
00633         break;
00634
00635       case HAL_I2S_RX_COMPLETE_CB_ID :
00636         hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback;                /* Legacy weak RxCpltCallback       */
00637         break;
00638
00639       case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
00640         hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback   */
00641         break;
00642
00643       case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
00644         hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback   */
00645         break;
00646
00647       case HAL_I2S_ERROR_CB_ID :
00648         hi2s->ErrorCallback = HAL_I2S_ErrorCallback;                  /* Legacy weak ErrorCallback        */
00649         break;
00650
00651       case HAL_I2S_MSPINIT_CB_ID :
00652         hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
00653         break;
00654
00655       case HAL_I2S_MSPDEINIT_CB_ID :
00656         hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
00657         break;
00658
00659       default :
00660         /* Update the error code */
00661         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00662
00663         /* Return error status */
00664         status =  HAL_ERROR;
00665         break;
00666     }
00667   }
00668   else if (HAL_I2S_STATE_RESET == hi2s->State)
00669   {
00670     switch (CallbackID)
00671     {
00672       case HAL_I2S_MSPINIT_CB_ID :
00673         hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
00674         break;
00675
00676       case HAL_I2S_MSPDEINIT_CB_ID :
00677         hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
00678         break;
00679
00680       default :
00681         /* Update the error code */
00682         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00683
00684         /* Return error status */
00685         status =  HAL_ERROR;
00686         break;
00687     }
00688   }
00689   else
00690   {
00691     /* Update the error code */
00692     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
00693
00694     /* Return error status */
00695     status =  HAL_ERROR;
00696   }
00697
00698   /* Release Lock */
00699   __HAL_UNLOCK(hi2s);
00700   return status;
00701 }
00702 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00703 /**
00704   * @}
00705   */
00706
00707 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
00708   *  @brief Data transfers functions
00709   *
00710 @verbatim
00711  ===============================================================================
00712                       ##### IO operation functions #####
00713  ===============================================================================
00714     [..]
00715     This subsection provides a set of functions allowing to manage the I2S data
00716     transfers.
00717
00718     (#) There are two modes of transfer:
00719        (++) Blocking mode : The communication is performed in the polling mode.
00720             The status of all data processing is returned by the same function
00721             after finishing transfer.
00722        (++) No-Blocking mode : The communication is performed using Interrupts
00723             or DMA. These functions return the status of the transfer startup.
00724             The end of the data processing will be indicated through the
00725             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00726             using DMA mode.
00727
00728     (#) Blocking mode functions are :
00729         (++) HAL_I2S_Transmit()
00730         (++) HAL_I2S_Receive()
00731
00732     (#) No-Blocking mode functions with Interrupt are :
00733         (++) HAL_I2S_Transmit_IT()
00734         (++) HAL_I2S_Receive_IT()
00735
00736     (#) No-Blocking mode functions with DMA are :
00737         (++) HAL_I2S_Transmit_DMA()
00738         (++) HAL_I2S_Receive_DMA()
00739
00740     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00741         (++) HAL_I2S_TxCpltCallback()
00742         (++) HAL_I2S_RxCpltCallback()
00743         (++) HAL_I2S_ErrorCallback()
00744
00745 @endverbatim
00746   * @{
00747   */
00748
00749 /**
00750   * @brief  Transmit an amount of data in blocking mode
00751   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00752   *         the configuration information for I2S module
00753   * @param  pData a 16-bit pointer to data buffer.
00754   * @param  Size number of data sample to be sent:
00755   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00756   *         configuration phase, the Size parameter means the number of 16-bit data length
00757   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00758   *         the Size parameter means the number of 24-bit or 32-bit data length.
00759   * @param  Timeout Timeout duration
00760   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00761   *         between Master and Slave(example: audio streaming).
00762   * @retval HAL status
00763   */
00764 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00765 {
00766   uint32_t tmpreg_cfgr;
00767
00768   if ((pData == NULL) || (Size == 0U))
00769   {
00770     return  HAL_ERROR;
00771   }
00772
00773   /* Process Locked */
00774   __HAL_LOCK(hi2s);
00775
00776   if (hi2s->State != HAL_I2S_STATE_READY)
00777   {
00778     __HAL_UNLOCK(hi2s);
00779     return HAL_BUSY;
00780   }
00781
00782   /* Set state and reset error code */
00783   hi2s->State = HAL_I2S_STATE_BUSY_TX;
00784   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00785   hi2s->pTxBuffPtr = pData;
00786
00787   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00788
00789   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
00790   {
00791     hi2s->TxXferSize = (Size << 1U);
00792     hi2s->TxXferCount = (Size << 1U);
00793   }
00794   else
00795   {
00796     hi2s->TxXferSize = Size;
00797     hi2s->TxXferCount = Size;
00798   }
00799
00800   tmpreg_cfgr = hi2s->Instance->I2SCFGR;
00801
00802   /* Check if the I2S is already enabled */
00803   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00804   {
00805     /* Enable I2S peripheral */
00806     __HAL_I2S_ENABLE(hi2s);
00807   }
00808
00809   /* Wait until TXE flag is set */
00810   if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
00811   {
00812     /* Set the error code */
00813     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00814     hi2s->State = HAL_I2S_STATE_READY;
00815     __HAL_UNLOCK(hi2s);
00816     return HAL_ERROR;
00817   }
00818
00819   while (hi2s->TxXferCount > 0U)
00820   {
00821     hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
00822     hi2s->pTxBuffPtr++;
00823     hi2s->TxXferCount--;
00824
00825     /* Wait until TXE flag is set */
00826     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
00827     {
00828       /* Set the error code */
00829       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00830       hi2s->State = HAL_I2S_STATE_READY;
00831       __HAL_UNLOCK(hi2s);
00832       return HAL_ERROR;
00833     }
00834
00835     /* Check if an underrun occurs */
00836     if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
00837     {
00838       /* Clear underrun flag */
00839       __HAL_I2S_CLEAR_UDRFLAG(hi2s);
00840
00841       /* Set the error code */
00842       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
00843     }
00844   }
00845
00846   /* Check if Slave mode is selected */
00847   if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
00848       || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
00849   {
00850     /* Wait until Busy flag is reset */
00851     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
00852     {
00853       /* Set the error code */
00854       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00855       hi2s->State = HAL_I2S_STATE_READY;
00856       __HAL_UNLOCK(hi2s);
00857       return HAL_ERROR;
00858     }
00859   }
00860
00861   hi2s->State = HAL_I2S_STATE_READY;
00862   __HAL_UNLOCK(hi2s);
00863   return HAL_OK;
00864 }
00865
00866 /**
00867   * @brief  Receive an amount of data in blocking mode
00868   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00869   *         the configuration information for I2S module
00870   * @param  pData a 16-bit pointer to data buffer.
00871   * @param  Size number of data sample to be sent:
00872   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00873   *         configuration phase, the Size parameter means the number of 16-bit data length
00874   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00875   *         the Size parameter means the number of 24-bit or 32-bit data length.
00876   * @param  Timeout Timeout duration
00877   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00878   *         between Master and Slave(example: audio streaming).
00879   * @note   In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
00880   *         in continuous way and as the I2S is not disabled at the end of the I2S transaction.
00881   * @retval HAL status
00882   */
00883 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00884 {
00885   uint32_t tmpreg_cfgr;
00886
00887   if ((pData == NULL) || (Size == 0U))
00888   {
00889     return  HAL_ERROR;
00890   }
00891
00892   /* Process Locked */
00893   __HAL_LOCK(hi2s);
00894
00895   if (hi2s->State != HAL_I2S_STATE_READY)
00896   {
00897     __HAL_UNLOCK(hi2s);
00898     return HAL_BUSY;
00899   }
00900
00901   /* Set state and reset error code */
00902   hi2s->State = HAL_I2S_STATE_BUSY_RX;
00903   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00904   hi2s->pRxBuffPtr = pData;
00905
00906   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00907
00908   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
00909   {
00910     hi2s->RxXferSize = (Size << 1U);
00911     hi2s->RxXferCount = (Size << 1U);
00912   }
00913   else
00914   {
00915     hi2s->RxXferSize = Size;
00916     hi2s->RxXferCount = Size;
00917   }
00918
00919   /* Check if the I2S is already enabled */
00920   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00921   {
00922     /* Enable I2S peripheral */
00923     __HAL_I2S_ENABLE(hi2s);
00924   }
00925
00926   /* Check if Master Receiver mode is selected */
00927   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00928   {
00929     /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00930     access to the SPI_SR register. */
00931     __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00932   }
00933
00934   /* Receive data */
00935   while (hi2s->RxXferCount > 0U)
00936   {
00937     /* Wait until RXNE flag is set */
00938     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
00939     {
00940       /* Set the error code */
00941       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00942       hi2s->State = HAL_I2S_STATE_READY;
00943       __HAL_UNLOCK(hi2s);
00944       return HAL_ERROR;
00945     }
00946
00947     (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
00948     hi2s->pRxBuffPtr++;
00949     hi2s->RxXferCount--;
00950
00951     /* Check if an overrun occurs */
00952     if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00953     {
00954       /* Clear overrun flag */
00955       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00956
00957       /* Set the error code */
00958       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
00959     }
00960   }
00961
00962   hi2s->State = HAL_I2S_STATE_READY;
00963   __HAL_UNLOCK(hi2s);
00964   return HAL_OK;
00965 }
00966
00967 /**
00968   * @brief  Transmit an amount of data in non-blocking mode with Interrupt
00969   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
00970   *         the configuration information for I2S module
00971   * @param  pData a 16-bit pointer to data buffer.
00972   * @param  Size number of data sample to be sent:
00973   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00974   *         configuration phase, the Size parameter means the number of 16-bit data length
00975   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00976   *         the Size parameter means the number of 24-bit or 32-bit data length.
00977   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00978   *         between Master and Slave(example: audio streaming).
00979   * @retval HAL status
00980   */
00981 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00982 {
00983   uint32_t tmpreg_cfgr;
00984
00985   if ((pData == NULL) || (Size == 0U))
00986   {
00987     return  HAL_ERROR;
00988   }
00989
00990   /* Process Locked */
00991   __HAL_LOCK(hi2s);
00992
00993   if (hi2s->State != HAL_I2S_STATE_READY)
00994   {
00995     __HAL_UNLOCK(hi2s);
00996     return HAL_BUSY;
00997   }
00998
00999   /* Set state and reset error code */
01000   hi2s->State = HAL_I2S_STATE_BUSY_TX;
01001   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01002   hi2s->pTxBuffPtr = pData;
01003
01004   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
01005
01006   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
01007   {
01008     hi2s->TxXferSize = (Size << 1U);
01009     hi2s->TxXferCount = (Size << 1U);
01010   }
01011   else
01012   {
01013     hi2s->TxXferSize = Size;
01014     hi2s->TxXferCount = Size;
01015   }
01016
01017   /* Enable TXE and ERR interrupt */
01018   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01019
01020   /* Check if the I2S is already enabled */
01021   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
01022   {
01023     /* Enable I2S peripheral */
01024     __HAL_I2S_ENABLE(hi2s);
01025   }
01026
01027   __HAL_UNLOCK(hi2s);
01028   return HAL_OK;
01029 }
01030
01031 /**
01032   * @brief  Receive an amount of data in non-blocking mode with Interrupt
01033   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01034   *         the configuration information for I2S module
01035   * @param  pData a 16-bit pointer to the Receive data buffer.
01036   * @param  Size number of data sample to be sent:
01037   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01038   *         configuration phase, the Size parameter means the number of 16-bit data length
01039   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01040   *         the Size parameter means the number of 24-bit or 32-bit data length.
01041   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01042   *         between Master and Slave(example: audio streaming).
01043   * @note   It is recommended to use DMA for the I2S receiver to avoid de-synchronization
01044   * between Master and Slave otherwise the I2S interrupt should be optimized.
01045   * @retval HAL status
01046   */
01047 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01048 {
01049   uint32_t tmpreg_cfgr;
01050
01051   if ((pData == NULL) || (Size == 0U))
01052   {
01053     return  HAL_ERROR;
01054   }
01055
01056   /* Process Locked */
01057   __HAL_LOCK(hi2s);
01058
01059   if (hi2s->State != HAL_I2S_STATE_READY)
01060   {
01061     __HAL_UNLOCK(hi2s);
01062     return HAL_BUSY;
01063   }
01064
01065   /* Set state and reset error code */
01066   hi2s->State = HAL_I2S_STATE_BUSY_RX;
01067   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01068   hi2s->pRxBuffPtr = pData;
01069
01070   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
01071
01072   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
01073   {
01074     hi2s->RxXferSize = (Size << 1U);
01075     hi2s->RxXferCount = (Size << 1U);
01076   }
01077   else
01078   {
01079     hi2s->RxXferSize = Size;
01080     hi2s->RxXferCount = Size;
01081   }
01082
01083   /* Enable RXNE and ERR interrupt */
01084   __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01085
01086   /* Check if the I2S is already enabled */
01087   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
01088   {
01089     /* Enable I2S peripheral */
01090     __HAL_I2S_ENABLE(hi2s);
01091   }
01092
01093   __HAL_UNLOCK(hi2s);
01094   return HAL_OK;
01095 }
01096
01097 /**
01098   * @brief  Transmit an amount of data in non-blocking mode with DMA
01099   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01100   *         the configuration information for I2S module
01101   * @param  pData a 16-bit pointer to the Transmit data buffer.
01102   * @param  Size number of data sample to be sent:
01103   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01104   *         configuration phase, the Size parameter means the number of 16-bit data length
01105   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01106   *         the Size parameter means the number of 24-bit or 32-bit data length.
01107   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01108   *         between Master and Slave(example: audio streaming).
01109   * @retval HAL status
01110   */
01111 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01112 {
01113   uint32_t tmpreg_cfgr;
01114
01115   if ((pData == NULL) || (Size == 0U))
01116   {
01117     return  HAL_ERROR;
01118   }
01119
01120   /* Process Locked */
01121   __HAL_LOCK(hi2s);
01122
01123   if (hi2s->State != HAL_I2S_STATE_READY)
01124   {
01125     __HAL_UNLOCK(hi2s);
01126     return HAL_BUSY;
01127   }
01128
01129   /* Set state and reset error code */
01130   hi2s->State = HAL_I2S_STATE_BUSY_TX;
01131   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01132   hi2s->pTxBuffPtr = pData;
01133
01134   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
01135
01136   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
01137   {
01138     hi2s->TxXferSize = (Size << 1U);
01139     hi2s->TxXferCount = (Size << 1U);
01140   }
01141   else
01142   {
01143     hi2s->TxXferSize = Size;
01144     hi2s->TxXferCount = Size;
01145   }
01146
01147   /* Set the I2S Tx DMA Half transfer complete callback */
01148   hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
01149
01150   /* Set the I2S Tx DMA transfer complete callback */
01151   hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
01152
01153   /* Set the DMA error callback */
01154   hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
01155
01156   /* Enable the Tx DMA Stream/Channel */
01157   if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
01158                                  (uint32_t)hi2s->pTxBuffPtr,
01159                                  (uint32_t)&hi2s->Instance->DR,
01160                                  hi2s->TxXferSize))
01161   {
01162     /* Update SPI error code */
01163     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01164     hi2s->State = HAL_I2S_STATE_READY;
01165
01166     __HAL_UNLOCK(hi2s);
01167     return HAL_ERROR;
01168   }
01169
01170   /* Check if the I2S is already enabled */
01171   if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
01172   {
01173     /* Enable I2S peripheral */
01174     __HAL_I2S_ENABLE(hi2s);
01175   }
01176
01177   /* Check if the I2S Tx request is already enabled */
01178   if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
01179   {
01180     /* Enable Tx DMA Request */
01181     SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01182   }
01183
01184   __HAL_UNLOCK(hi2s);
01185   return HAL_OK;
01186 }
01187
01188 /**
01189   * @brief  Receive an amount of data in non-blocking mode with DMA
01190   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01191   *         the configuration information for I2S module
01192   * @param  pData a 16-bit pointer to the Receive data buffer.
01193   * @param  Size number of data sample to be sent:
01194   * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
01195   *         configuration phase, the Size parameter means the number of 16-bit data length
01196   *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
01197   *         the Size parameter means the number of 24-bit or 32-bit data length.
01198   * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
01199   *         between Master and Slave(example: audio streaming).
01200   * @retval HAL status
01201   */
01202 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
01203 {
01204   uint32_t tmpreg_cfgr;
01205
01206   if ((pData == NULL) || (Size == 0U))
01207   {
01208     return  HAL_ERROR;
01209   }
01210
01211   /* Process Locked */
01212   __HAL_LOCK(hi2s);
01213
01214   if (hi2s->State != HAL_I2S_STATE_READY)
01215   {
01216     __HAL_UNLOCK(hi2s);
01217     return HAL_BUSY;
01218   }
01219
01220   /* Set state and reset error code */
01221   hi2s->State = HAL_I2S_STATE_BUSY_RX;
01222   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
01223   hi2s->pRxBuffPtr = pData;
01224
01225   tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
01226
01227   if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
01228   {
01229     hi2s->RxXferSize = (Size << 1U);
01230     hi2s->RxXferCount = (Size << 1U);
01231   }
01232   else
01233   {
01234     hi2s->RxXferSize = Size;
01235     hi2s->RxXferCount = Size;
01236   }
01237
01238   /* Set the I2S Rx DMA Half transfer complete callback */
01239   hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
01240
01241   /* Set the I2S Rx DMA transfer complete callback */
01242   hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
01243
01244   /* Set the DMA error callback */
01245   hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
01246
01247   /* Check if Master Receiver mode is selected */
01248   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
01249   {
01250     /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
01251     access to the SPI_SR register. */
01252     __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01253   }
01254
01255   /* Enable the Rx DMA Stream/Channel */
01256   if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
01257                                  hi2s->RxXferSize))
01258   {
01259     /* Update SPI error code */
01260     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01261     hi2s->State = HAL_I2S_STATE_READY;
01262
01263     __HAL_UNLOCK(hi2s);
01264     return HAL_ERROR;
01265   }
01266
01267   /* Check if the I2S is already enabled */
01268   if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
01269   {
01270     /* Enable I2S peripheral */
01271     __HAL_I2S_ENABLE(hi2s);
01272   }
01273
01274   /* Check if the I2S Rx request is already enabled */
01275   if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
01276   {
01277     /* Enable Rx DMA Request */
01278     SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01279   }
01280
01281   __HAL_UNLOCK(hi2s);
01282   return HAL_OK;
01283 }
01284
01285 /**
01286   * @brief  Pauses the audio DMA Stream/Channel playing from the Media.
01287   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01288   *         the configuration information for I2S module
01289   * @retval HAL status
01290   */
01291 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
01292 {
01293   /* Process Locked */
01294   __HAL_LOCK(hi2s);
01295
01296   if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
01297   {
01298     /* Disable the I2S DMA Tx request */
01299     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01300   }
01301   else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
01302   {
01303     /* Disable the I2S DMA Rx request */
01304     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01305   }
01306   else
01307   {
01308     /* nothing to do */
01309   }
01310
01311   /* Process Unlocked */
01312   __HAL_UNLOCK(hi2s);
01313
01314   return HAL_OK;
01315 }
01316
01317 /**
01318   * @brief  Resumes the audio DMA Stream/Channel playing from the Media.
01319   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01320   *         the configuration information for I2S module
01321   * @retval HAL status
01322   */
01323 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
01324 {
01325   /* Process Locked */
01326   __HAL_LOCK(hi2s);
01327
01328   if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
01329   {
01330     /* Enable the I2S DMA Tx request */
01331     SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01332   }
01333   else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
01334   {
01335     /* Enable the I2S DMA Rx request */
01336     SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01337   }
01338   else
01339   {
01340     /* nothing to do */
01341   }
01342
01343   /* If the I2S peripheral is still not enabled, enable it */
01344   if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
01345   {
01346     /* Enable I2S peripheral */
01347     __HAL_I2S_ENABLE(hi2s);
01348   }
01349
01350   /* Process Unlocked */
01351   __HAL_UNLOCK(hi2s);
01352
01353   return HAL_OK;
01354 }
01355
01356 /**
01357   * @brief  Stops the audio DMA Stream/Channel playing from the Media.
01358   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01359   *         the configuration information for I2S module
01360   * @retval HAL status
01361   */
01362 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
01363 {
01364   HAL_StatusTypeDef errorcode = HAL_OK;
01365   /* The Lock is not implemented on this API to allow the user application
01366      to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
01367      when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
01368      and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
01369      */
01370
01371   if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
01372   {
01373     /* Abort the I2S DMA tx Stream/Channel */
01374     if (hi2s->hdmatx != NULL)
01375     {
01376       /* Disable the I2S DMA tx Stream/Channel */
01377       if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
01378       {
01379         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01380         errorcode = HAL_ERROR;
01381       }
01382     }
01383
01384     /* Wait until TXE flag is set */
01385     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
01386     {
01387       /* Set the error code */
01388       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
01389       hi2s->State = HAL_I2S_STATE_READY;
01390       errorcode   = HAL_ERROR;
01391     }
01392
01393     /* Wait until BSY flag is Reset */
01394     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
01395     {
01396       /* Set the error code */
01397       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
01398       hi2s->State = HAL_I2S_STATE_READY;
01399       errorcode   = HAL_ERROR;
01400     }
01401
01402     /* Disable I2S peripheral */
01403     __HAL_I2S_DISABLE(hi2s);
01404
01405     /* Clear UDR flag */
01406     __HAL_I2S_CLEAR_UDRFLAG(hi2s);
01407
01408     /* Disable the I2S Tx DMA requests */
01409     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01410
01411   }
01412
01413   else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
01414   {
01415     /* Abort the I2S DMA rx Stream/Channel */
01416     if (hi2s->hdmarx != NULL)
01417     {
01418       /* Disable the I2S DMA rx Stream/Channel */
01419       if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
01420       {
01421         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01422         errorcode = HAL_ERROR;
01423       }
01424     }
01425
01426     /* Disable I2S peripheral */
01427     __HAL_I2S_DISABLE(hi2s);
01428
01429     /* Clear OVR flag */
01430     __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01431
01432     /* Disable the I2S Rx DMA request */
01433     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01434
01435     if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
01436     {
01437       /* Set the error code */
01438       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
01439
01440       /* Set the I2S State ready */
01441       hi2s->State = HAL_I2S_STATE_READY;
01442       errorcode = HAL_ERROR;
01443     }
01444     else
01445     {
01446       /* Read DR to Flush RX Data */
01447       READ_REG((hi2s->Instance)->DR);
01448     }
01449   }
01450
01451   hi2s->State = HAL_I2S_STATE_READY;
01452
01453   return errorcode;
01454 }
01455
01456 /**
01457   * @brief  This function handles I2S interrupt request.
01458   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01459   *         the configuration information for I2S module
01460   * @retval None
01461   */
01462 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
01463 {
01464   uint32_t itsource = hi2s->Instance->CR2;
01465   uint32_t itflag   = hi2s->Instance->SR;
01466
01467   /* I2S in mode Receiver ------------------------------------------------*/
01468   if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
01469       (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
01470   {
01471     I2S_Receive_IT(hi2s);
01472     return;
01473   }
01474
01475   /* I2S in mode Tramitter -----------------------------------------------*/
01476   if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
01477   {
01478     I2S_Transmit_IT(hi2s);
01479     return;
01480   }
01481
01482   /* I2S interrupt error -------------------------------------------------*/
01483   if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
01484   {
01485     /* I2S Overrun error interrupt occurred ---------------------------------*/
01486     if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
01487     {
01488       /* Disable RXNE and ERR interrupt */
01489       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01490
01491       /* Set the error code and execute error callback*/
01492       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
01493     }
01494
01495     /* I2S Underrun error interrupt occurred --------------------------------*/
01496     if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
01497     {
01498       /* Disable TXE and ERR interrupt */
01499       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01500
01501       /* Set the error code and execute error callback*/
01502       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
01503     }
01504
01505     /* Set the I2S State ready */
01506     hi2s->State = HAL_I2S_STATE_READY;
01507
01508     /* Call user error callback */
01509 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01510     hi2s->ErrorCallback(hi2s);
01511 #else
01512     HAL_I2S_ErrorCallback(hi2s);
01513 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01514   }
01515 }
01516
01517 /**
01518   * @brief  Tx Transfer Half completed callbacks
01519   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01520   *         the configuration information for I2S module
01521   * @retval None
01522   */
01523 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01524 {
01525   /* Prevent unused argument(s) compilation warning */
01526   UNUSED(hi2s);
01527
01528   /* NOTE : This function Should not be modified, when the callback is needed,
01529             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
01530    */
01531 }
01532
01533 /**
01534   * @brief  Tx Transfer completed callbacks
01535   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01536   *         the configuration information for I2S module
01537   * @retval None
01538   */
01539 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
01540 {
01541   /* Prevent unused argument(s) compilation warning */
01542   UNUSED(hi2s);
01543
01544   /* NOTE : This function Should not be modified, when the callback is needed,
01545             the HAL_I2S_TxCpltCallback could be implemented in the user file
01546    */
01547 }
01548
01549 /**
01550   * @brief  Rx Transfer half completed callbacks
01551   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01552   *         the configuration information for I2S module
01553   * @retval None
01554   */
01555 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01556 {
01557   /* Prevent unused argument(s) compilation warning */
01558   UNUSED(hi2s);
01559
01560   /* NOTE : This function Should not be modified, when the callback is needed,
01561             the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
01562    */
01563 }
01564
01565 /**
01566   * @brief  Rx Transfer completed callbacks
01567   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01568   *         the configuration information for I2S module
01569   * @retval None
01570   */
01571 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
01572 {
01573   /* Prevent unused argument(s) compilation warning */
01574   UNUSED(hi2s);
01575
01576   /* NOTE : This function Should not be modified, when the callback is needed,
01577             the HAL_I2S_RxCpltCallback could be implemented in the user file
01578    */
01579 }
01580
01581 /**
01582   * @brief  I2S error callbacks
01583   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01584   *         the configuration information for I2S module
01585   * @retval None
01586   */
01587 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
01588 {
01589   /* Prevent unused argument(s) compilation warning */
01590   UNUSED(hi2s);
01591
01592   /* NOTE : This function Should not be modified, when the callback is needed,
01593             the HAL_I2S_ErrorCallback could be implemented in the user file
01594    */
01595 }
01596
01597 /**
01598   * @}
01599   */
01600
01601 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
01602   *  @brief   Peripheral State functions
01603   *
01604 @verbatim
01605  ===============================================================================
01606                       ##### Peripheral State and Errors functions #####
01607  ===============================================================================
01608     [..]
01609     This subsection permits to get in run-time the status of the peripheral
01610     and the data flow.
01611
01612 @endverbatim
01613   * @{
01614   */
01615
01616 /**
01617   * @brief  Return the I2S state
01618   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01619   *         the configuration information for I2S module
01620   * @retval HAL state
01621   */
01622 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
01623 {
01624   return hi2s->State;
01625 }
01626
01627 /**
01628   * @brief  Return the I2S error code
01629   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01630   *         the configuration information for I2S module
01631   * @retval I2S Error Code
01632   */
01633 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
01634 {
01635   return hi2s->ErrorCode;
01636 }
01637 /**
01638   * @}
01639   */
01640
01641 /**
01642   * @}
01643   */
01644
01645 /** @addtogroup I2S_Private_Functions I2S Private Functions
01646   * @{
01647   */
01648 /**
01649   * @brief  DMA I2S transmit process complete callback
01650   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01651   *                the configuration information for the specified DMA module.
01652   * @retval None
01653   */
01654 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
01655 {
01656   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01657
01658   /* if DMA is configured in DMA_NORMAL Mode */
01659   if (hdma->Init.Mode == DMA_NORMAL)
01660   {
01661     /* Disable Tx DMA Request */
01662     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
01663
01664     hi2s->TxXferCount = 0U;
01665     hi2s->State = HAL_I2S_STATE_READY;
01666   }
01667   /* Call user Tx complete callback */
01668 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01669   hi2s->TxCpltCallback(hi2s);
01670 #else
01671   HAL_I2S_TxCpltCallback(hi2s);
01672 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01673 }
01674
01675 /**
01676   * @brief  DMA I2S transmit process half complete callback
01677   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01678   *                the configuration information for the specified DMA module.
01679   * @retval None
01680   */
01681 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01682 {
01683   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01684
01685   /* Call user Tx half complete callback */
01686 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01687   hi2s->TxHalfCpltCallback(hi2s);
01688 #else
01689   HAL_I2S_TxHalfCpltCallback(hi2s);
01690 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01691 }
01692
01693 /**
01694   * @brief  DMA I2S receive process complete callback
01695   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01696   *                the configuration information for the specified DMA module.
01697   * @retval None
01698   */
01699 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
01700 {
01701   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01702
01703   /* if DMA is configured in DMA_NORMAL Mode */
01704   if (hdma->Init.Mode == DMA_NORMAL)
01705   {
01706     /* Disable Rx DMA Request */
01707     CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
01708     hi2s->RxXferCount = 0U;
01709     hi2s->State = HAL_I2S_STATE_READY;
01710   }
01711   /* Call user Rx complete callback */
01712 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01713   hi2s->RxCpltCallback(hi2s);
01714 #else
01715   HAL_I2S_RxCpltCallback(hi2s);
01716 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01717 }
01718
01719 /**
01720   * @brief  DMA I2S receive process half complete callback
01721   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01722   *                the configuration information for the specified DMA module.
01723   * @retval None
01724   */
01725 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01726 {
01727   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01728
01729   /* Call user Rx half complete callback */
01730 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01731   hi2s->RxHalfCpltCallback(hi2s);
01732 #else
01733   HAL_I2S_RxHalfCpltCallback(hi2s);
01734 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01735 }
01736
01737 /**
01738   * @brief  DMA I2S communication error callback
01739   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
01740   *                the configuration information for the specified DMA module.
01741   * @retval None
01742   */
01743 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
01744 {
01745   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
01746
01747   /* Disable Rx and Tx DMA Request */
01748   CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
01749   hi2s->TxXferCount = 0U;
01750   hi2s->RxXferCount = 0U;
01751
01752   hi2s->State = HAL_I2S_STATE_READY;
01753
01754   /* Set the error code and execute error callback*/
01755   SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
01756   /* Call user error callback */
01757 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01758   hi2s->ErrorCallback(hi2s);
01759 #else
01760   HAL_I2S_ErrorCallback(hi2s);
01761 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01762 }
01763
01764 /**
01765   * @brief  Transmit an amount of data in non-blocking mode with Interrupt
01766   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01767   *         the configuration information for I2S module
01768   * @retval None
01769   */
01770 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
01771 {
01772   /* Transmit data */
01773   hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
01774   hi2s->pTxBuffPtr++;
01775   hi2s->TxXferCount--;
01776
01777   if (hi2s->TxXferCount == 0U)
01778   {
01779     /* Disable TXE and ERR interrupt */
01780     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01781
01782     hi2s->State = HAL_I2S_STATE_READY;
01783     /* Call user Tx complete callback */
01784 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01785     hi2s->TxCpltCallback(hi2s);
01786 #else
01787     HAL_I2S_TxCpltCallback(hi2s);
01788 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01789   }
01790 }
01791
01792 /**
01793   * @brief  Receive an amount of data in non-blocking mode with Interrupt
01794   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01795   *         the configuration information for I2S module
01796   * @retval None
01797   */
01798 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
01799 {
01800   /* Receive data */
01801   (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
01802   hi2s->pRxBuffPtr++;
01803   hi2s->RxXferCount--;
01804
01805   if (hi2s->RxXferCount == 0U)
01806   {
01807     /* Disable RXNE and ERR interrupt */
01808     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01809
01810     hi2s->State = HAL_I2S_STATE_READY;
01811     /* Call user Rx complete callback */
01812 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
01813     hi2s->RxCpltCallback(hi2s);
01814 #else
01815     HAL_I2S_RxCpltCallback(hi2s);
01816 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
01817   }
01818 }
01819
01820 /**
01821   * @brief  This function handles I2S Communication Timeout.
01822   * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
01823   *         the configuration information for I2S module
01824   * @param  Flag Flag checked
01825   * @param  State Value of the flag expected
01826   * @param  Timeout Duration of the timeout
01827   * @retval HAL status
01828   */
01829 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
01830                                                        uint32_t Timeout)
01831 {
01832   uint32_t tickstart;
01833
01834   /* Get tick */
01835   tickstart = HAL_GetTick();
01836
01837   /* Wait until flag is set to status*/
01838   while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
01839   {
01840     if (Timeout != HAL_MAX_DELAY)
01841     {
01842       if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
01843       {
01844         /* Set the I2S State ready */
01845         hi2s->State = HAL_I2S_STATE_READY;
01846
01847         /* Process Unlocked */
01848         __HAL_UNLOCK(hi2s);
01849
01850         return HAL_TIMEOUT;
01851       }
01852     }
01853   }
01854   return HAL_OK;
01855 }
01856
01857 /**
01858   * @}
01859   */
01860
01861 /**
01862   * @}
01863   */
01864
01865 /**
01866   * @}
01867   */
01868 #endif /* SPI_I2S_SUPPORT */
01869
01870 #endif /* HAL_I2S_MODULE_ENABLED */
01871
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_i2s.h Source File

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stm32g0xx_hal_i2s.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_i2s.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2S HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_I2S_H
00021 #define STM32G0xx_HAL_I2S_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 #if defined(SPI_I2S_SUPPORT)
00031 /** @addtogroup STM32G0xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup I2S
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup I2S_Exported_Types I2S Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief I2S Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Mode;                /*!< Specifies the I2S operating mode.
00050                                      This parameter can be a value of @ref I2S_Mode */
00051
00052   uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
00053                                      This parameter can be a value of @ref I2S_Standard */
00054
00055   uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
00056                                      This parameter can be a value of @ref I2S_Data_Format */
00057
00058   uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
00059                                      This parameter can be a value of @ref I2S_MCLK_Output */
00060
00061   uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
00062                                      This parameter can be a value of @ref I2S_Audio_Frequency */
00063
00064   uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
00065                                      This parameter can be a value of @ref I2S_Clock_Polarity */
00066 } I2S_InitTypeDef;
00067
00068 /**
00069   * @brief  HAL State structures definition
00070   */
00071 typedef enum
00072 {
00073   HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
00074   HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
00075   HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
00076   HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
00077   HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
00078   HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
00079   HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
00080 } HAL_I2S_StateTypeDef;
00081
00082 /**
00083   * @brief I2S handle Structure definition
00084   */
00085 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
00086 typedef struct __I2S_HandleTypeDef
00087 #else
00088 typedef struct
00089 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00090 {
00091   SPI_TypeDef                *Instance;    /*!< I2S registers base address */
00092
00093   I2S_InitTypeDef            Init;         /*!< I2S communication parameters */
00094
00095   uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
00096
00097   __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size */
00098
00099   __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter */
00100
00101   uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
00102
00103   __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size */
00104
00105   __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
00106                                               (This field is initialized at the
00107                                                same value as transfer size at the
00108                                                beginning of the transfer and
00109                                                decremented when a sample is received
00110                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00111   DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters */
00112
00113   DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters */
00114
00115   __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object */
00116
00117   __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state */
00118
00119   __IO uint32_t              ErrorCode;    /*!< I2S Error code
00120                                                 This parameter can be a value of @ref I2S_Error */
00121
00122 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00123   void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
00124   void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
00125   void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
00126   void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
00127   void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
00128   void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
00129   void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
00130
00131 #endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
00132 } I2S_HandleTypeDef;
00133
00134 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00135 /**
00136   * @brief  HAL I2S Callback ID enumeration definition
00137   */
00138 typedef enum
00139 {
00140   HAL_I2S_TX_COMPLETE_CB_ID             = 0x00U,    /*!< I2S Tx Completed callback ID         */
00141   HAL_I2S_RX_COMPLETE_CB_ID             = 0x01U,    /*!< I2S Rx Completed callback ID         */
00142   HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< I2S Tx Half Completed callback ID    */
00143   HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< I2S Rx Half Completed callback ID    */
00144   HAL_I2S_ERROR_CB_ID                   = 0x06U,    /*!< I2S Error callback ID                */
00145   HAL_I2S_MSPINIT_CB_ID                 = 0x07U,    /*!< I2S Msp Init callback ID             */
00146   HAL_I2S_MSPDEINIT_CB_ID               = 0x08U     /*!< I2S Msp DeInit callback ID           */
00147
00148 } HAL_I2S_CallbackIDTypeDef;
00149
00150 /**
00151   * @brief  HAL I2S Callback pointer definition
00152   */
00153 typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
00154
00155 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00156 /**
00157   * @}
00158   */
00159
00160 /* Exported constants --------------------------------------------------------*/
00161 /** @defgroup I2S_Exported_Constants I2S Exported Constants
00162   * @{
00163   */
00164 /** @defgroup I2S_Error I2S Error
00165   * @{
00166   */
00167 #define HAL_I2S_ERROR_NONE               (0x00000000U)  /*!< No error                    */
00168 #define HAL_I2S_ERROR_TIMEOUT            (0x00000001U)  /*!< Timeout error               */
00169 #define HAL_I2S_ERROR_OVR                (0x00000002U)  /*!< OVR error                   */
00170 #define HAL_I2S_ERROR_UDR                (0x00000004U)  /*!< UDR error                   */
00171 #define HAL_I2S_ERROR_DMA                (0x00000008U)  /*!< DMA transfer error          */
00172 #define HAL_I2S_ERROR_PRESCALER          (0x00000010U)  /*!< Prescaler Calculation error */
00173 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00174 #define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000020U)  /*!< Invalid Callback error      */
00175 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00176 #define HAL_I2S_ERROR_BUSY_LINE_RX       (0x00000040U)  /*!< Busy Rx Line error          */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup I2S_Mode I2S Mode
00182   * @{
00183   */
00184 #define I2S_MODE_SLAVE_TX                (0x00000000U)
00185 #define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
00186 #define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
00187 #define I2S_MODE_MASTER_RX               ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup I2S_Standard I2S Standard
00193   * @{
00194   */
00195 #define I2S_STANDARD_PHILIPS             (0x00000000U)
00196 #define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
00197 #define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
00198 #define I2S_STANDARD_PCM_SHORT           ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
00199 #define I2S_STANDARD_PCM_LONG            ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup I2S_Data_Format I2S Data Format
00205   * @{
00206   */
00207 #define I2S_DATAFORMAT_16B               (0x00000000U)
00208 #define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
00209 #define I2S_DATAFORMAT_24B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
00210 #define I2S_DATAFORMAT_32B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup I2S_MCLK_Output I2S MCLK Output
00216   * @{
00217   */
00218 #define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SPR_MCKOE)
00219 #define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
00225   * @{
00226   */
00227 #define I2S_AUDIOFREQ_192K               (192000U)
00228 #define I2S_AUDIOFREQ_96K                (96000U)
00229 #define I2S_AUDIOFREQ_48K                (48000U)
00230 #define I2S_AUDIOFREQ_44K                (44100U)
00231 #define I2S_AUDIOFREQ_32K                (32000U)
00232 #define I2S_AUDIOFREQ_22K                (22050U)
00233 #define I2S_AUDIOFREQ_16K                (16000U)
00234 #define I2S_AUDIOFREQ_11K                (11025U)
00235 #define I2S_AUDIOFREQ_8K                 (8000U)
00236 #define I2S_AUDIOFREQ_DEFAULT            (2U)
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
00242   * @{
00243   */
00244 #define I2S_CPOL_LOW                     (0x00000000U)
00245 #define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
00251   * @{
00252   */
00253 #define I2S_IT_TXE                       SPI_CR2_TXEIE
00254 #define I2S_IT_RXNE                      SPI_CR2_RXNEIE
00255 #define I2S_IT_ERR                       SPI_CR2_ERRIE
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup I2S_Flags_Definition I2S Flags Definition
00261   * @{
00262   */
00263 #define I2S_FLAG_TXE                     SPI_SR_TXE
00264 #define I2S_FLAG_RXNE                    SPI_SR_RXNE
00265
00266 #define I2S_FLAG_UDR                     SPI_SR_UDR
00267 #define I2S_FLAG_OVR                     SPI_SR_OVR
00268 #define I2S_FLAG_FRE                     SPI_SR_FRE
00269
00270 #define I2S_FLAG_CHSIDE                  SPI_SR_CHSIDE
00271 #define I2S_FLAG_BSY                     SPI_SR_BSY
00272
00273 #define I2S_FLAG_MASK                   (SPI_SR_RXNE\
00274                                          | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
00275 /**
00276   * @}
00277   */
00278
00279 /**
00280   * @}
00281   */
00282
00283 /* Exported macros -----------------------------------------------------------*/
00284 /** @defgroup I2S_Exported_macros I2S Exported Macros
00285   * @{
00286   */
00287
00288 /** @brief  Reset I2S handle state
00289   * @param  __HANDLE__ specifies the I2S Handle.
00290   * @retval None
00291   */
00292 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00293 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
00294                                                                     (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
00295                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00296                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00297                                                                   } while(0)
00298 #else
00299 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
00300 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00301
00302 /** @brief  Enable the specified SPI peripheral (in I2S mode).
00303   * @param  __HANDLE__ specifies the I2S Handle.
00304   * @retval None
00305   */
00306 #define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
00307
00308 /** @brief  Disable the specified SPI peripheral (in I2S mode).
00309   * @param  __HANDLE__ specifies the I2S Handle.
00310   * @retval None
00311   */
00312 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
00313
00314 /** @brief  Enable the specified I2S interrupts.
00315   * @param  __HANDLE__ specifies the I2S Handle.
00316   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00317   *         This parameter can be one of the following values:
00318   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00319   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00320   *            @arg I2S_IT_ERR: Error interrupt enable
00321   * @retval None
00322   */
00323 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
00324
00325 /** @brief  Disable the specified I2S interrupts.
00326   * @param  __HANDLE__ specifies the I2S Handle.
00327   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00328   *         This parameter can be one of the following values:
00329   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00330   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00331   *            @arg I2S_IT_ERR: Error interrupt enable
00332   * @retval None
00333   */
00334 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
00335
00336 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
00337   * @param  __HANDLE__ specifies the I2S Handle.
00338   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00339   * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
00340   *          This parameter can be one of the following values:
00341   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00342   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00343   *            @arg I2S_IT_ERR: Error interrupt enable
00344   * @retval The new state of __IT__ (TRUE or FALSE).
00345   */
00346 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
00347                                                               & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00348
00349 /** @brief  Checks whether the specified I2S flag is set or not.
00350   * @param  __HANDLE__ specifies the I2S Handle.
00351   * @param  __FLAG__ specifies the flag to check.
00352   *         This parameter can be one of the following values:
00353   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00354   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00355   *            @arg I2S_FLAG_UDR: Underrun flag
00356   *            @arg I2S_FLAG_OVR: Overrun flag
00357   *            @arg I2S_FLAG_FRE: Frame error flag
00358   *            @arg I2S_FLAG_CHSIDE: Channel Side flag
00359   *            @arg I2S_FLAG_BSY: Busy flag
00360   * @retval The new state of __FLAG__ (TRUE or FALSE).
00361   */
00362 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00363
00364 /** @brief Clears the I2S OVR pending flag.
00365   * @param  __HANDLE__ specifies the I2S Handle.
00366   * @retval None
00367   */
00368 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
00369                                                 __IO uint32_t tmpreg_ovr = 0x00U; \
00370                                                 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
00371                                                 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
00372                                                 UNUSED(tmpreg_ovr); \
00373                                               }while(0U)
00374 /** @brief Clears the I2S UDR pending flag.
00375   * @param  __HANDLE__ specifies the I2S Handle.
00376   * @retval None
00377   */
00378 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
00379                                                 __IO uint32_t tmpreg_udr = 0x00U;\
00380                                                 tmpreg_udr = ((__HANDLE__)->Instance->SR);\
00381                                                 UNUSED(tmpreg_udr); \
00382                                               }while(0U)
00383 /** @brief Flush the I2S DR Register.
00384   * @param  __HANDLE__ specifies the I2S Handle.
00385   * @retval None
00386   */
00387 #define __HAL_I2S_FLUSH_RX_DR(__HANDLE__)  do{\
00388                                                 __IO uint32_t tmpreg_dr = 0x00U;\
00389                                                 tmpreg_dr = ((__HANDLE__)->Instance->DR);\
00390                                                 UNUSED(tmpreg_dr); \
00391                                               }while(0U)
00392 /**
00393   * @}
00394   */
00395
00396 /* Exported functions --------------------------------------------------------*/
00397 /** @addtogroup I2S_Exported_Functions
00398   * @{
00399   */
00400
00401 /** @addtogroup I2S_Exported_Functions_Group1
00402   * @{
00403   */
00404 /* Initialization/de-initialization functions  ********************************/
00405 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
00406 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
00407 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
00408 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
00409
00410 /* Callbacks Register/UnRegister functions  ***********************************/
00411 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
00412 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
00413                                            pI2S_CallbackTypeDef pCallback);
00414 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
00415 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup I2S_Exported_Functions_Group2
00421   * @{
00422   */
00423 /* I/O operation functions  ***************************************************/
00424 /* Blocking mode: Polling */
00425 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00426 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00427
00428 /* Non-Blocking mode: Interrupt */
00429 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00430 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00431 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00432
00433 /* Non-Blocking mode: DMA */
00434 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00435 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00436
00437 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00438 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00439 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00440
00441 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00442 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00443 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
00444 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00445 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
00446 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
00447 /**
00448   * @}
00449   */
00450
00451 /** @addtogroup I2S_Exported_Functions_Group3
00452   * @{
00453   */
00454 /* Peripheral Control and State functions  ************************************/
00455 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
00456 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
00457 /**
00458   * @}
00459   */
00460
00461 /**
00462   * @}
00463   */
00464
00465 /* Private types -------------------------------------------------------------*/
00466 /* Private variables ---------------------------------------------------------*/
00467 /* Private constants ---------------------------------------------------------*/
00468 /* Private macros ------------------------------------------------------------*/
00469 /** @defgroup I2S_Private_Macros I2S Private Macros
00470   * @{
00471   */
00472
00473 /** @brief  Check whether the specified SPI flag is set or not.
00474   * @param  __SR__  copy of I2S SR register.
00475   * @param  __FLAG__ specifies the flag to check.
00476   *         This parameter can be one of the following values:
00477   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00478   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00479   *            @arg I2S_FLAG_UDR: Underrun error flag
00480   *            @arg I2S_FLAG_OVR: Overrun flag
00481   *            @arg I2S_FLAG_CHSIDE: Channel side flag
00482   *            @arg I2S_FLAG_BSY: Busy flag
00483   * @retval SET or RESET.
00484   */
00485 #define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
00486                                                     & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
00487
00488 /** @brief  Check whether the specified SPI Interrupt is set or not.
00489   * @param  __CR2__  copy of I2S CR2 register.
00490   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00491   *         This parameter can be one of the following values:
00492   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00493   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00494   *            @arg I2S_IT_ERR: Error interrupt enable
00495   * @retval SET or RESET.
00496   */
00497 #define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__)\
00498                                                             & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00499
00500 /** @brief  Checks if I2S Mode parameter is in allowed range.
00501   * @param  __MODE__ specifies the I2S Mode.
00502   *         This parameter can be a value of @ref I2S_Mode
00503   * @retval None
00504   */
00505 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
00506                                ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
00507                                ((__MODE__) == I2S_MODE_MASTER_TX) || \
00508                                ((__MODE__) == I2S_MODE_MASTER_RX))
00509
00510 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
00511                                        ((__STANDARD__) == I2S_STANDARD_MSB)       || \
00512                                        ((__STANDARD__) == I2S_STANDARD_LSB)       || \
00513                                        ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
00514                                        ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
00515
00516 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
00517                                         ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
00518                                         ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
00519                                         ((__FORMAT__) == I2S_DATAFORMAT_32B))
00520
00521 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
00522                                         ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
00523
00524 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
00525                                       ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
00526                                      ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
00527
00528 /** @brief  Checks if I2S Serial clock steady state parameter is in allowed range.
00529   * @param  __CPOL__ specifies the I2S serial clock steady state.
00530   *         This parameter can be a value of @ref I2S_Clock_Polarity
00531   * @retval None
00532   */
00533 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
00534                                ((__CPOL__) == I2S_CPOL_HIGH))
00535
00536 /**
00537   * @}
00538   */
00539
00540 /**
00541   * @}
00542   */
00543
00544 /**
00545   * @}
00546   */
00547 #endif /* SPI_I2S_SUPPORT */
00548
00549 #ifdef __cplusplus
00550 }
00551 #endif
00552
00553 #endif /* STM32G0xx_HAL_I2S_H */
00554
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_irda.c Source File

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stm32g0xx_hal_irda.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @brief   IRDA HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the IrDA (Infrared Data Association) Peripheral
00008   *          (IRDA)
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *           + Peripheral Control functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2018 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                         ##### How to use this driver #####
00028   ==============================================================================
00029   [..]
00030     The IRDA HAL driver can be used as follows:
00031
00032     (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
00033     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
00034         in setting the associated USART or UART in IRDA mode:
00035         (++) Enable the USARTx/UARTx interface clock.
00036         (++) USARTx/UARTx pins configuration:
00037             (+++) Enable the clock for the USARTx/UARTx GPIOs.
00038             (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
00039         (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00040              and HAL_IRDA_Receive_IT() APIs):
00041             (+++) Configure the USARTx/UARTx interrupt priority.
00042             (+++) Enable the NVIC USARTx/UARTx IRQ handle.
00043             (+++) The specific IRDA interrupts (Transmission complete interrupt,
00044                   RXNE interrupt and Error Interrupts) will be managed using the macros
00045                   __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00046
00047         (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00048              and HAL_IRDA_Receive_DMA() APIs):
00049             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00050             (+++) Enable the DMAx interface clock.
00051             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00052             (+++) Configure the DMA Tx/Rx channel.
00053             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00054             (+++) Configure the priority and enable the NVIC for the transfer
00055                   complete interrupt on the DMA Tx/Rx channel.
00056
00057     (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
00058         the normal or low power mode and the clock prescaler in the hirda handle Init structure.
00059
00060     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00061         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00062              by calling the customized HAL_IRDA_MspInit() API.
00063
00064          -@@- The specific IRDA interrupts (Transmission complete interrupt,
00065              RXNE interrupt and Error Interrupts) will be managed using the macros
00066              __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00067
00068     (#) Three operation modes are available within this driver :
00069
00070      *** Polling mode IO operation ***
00071      =================================
00072      [..]
00073        (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00074        (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00075
00076      *** Interrupt mode IO operation ***
00077      ===================================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
00080        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00082        (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
00083        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00084             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00085        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00086             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00087
00088      *** DMA mode IO operation ***
00089      ==============================
00090      [..]
00091        (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00092        (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
00093             add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
00094        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00095             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00096        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00097        (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
00098             add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
00099        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00100             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00101        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00102             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00103
00104      *** IRDA HAL driver macros list ***
00105      ====================================
00106      [..]
00107        Below the list of most used macros in IRDA HAL driver.
00108
00109        (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00110        (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00111        (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
00112        (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
00113        (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
00114        (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
00115        (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
00116
00117      [..]
00118        (@) You can refer to the IRDA HAL driver header file for more useful macros
00119
00120     ##### Callback registration #####
00121     ==================================
00122
00123     [..]
00124     The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
00125     allows the user to configure dynamically the driver callbacks.
00126
00127     [..]
00128     Use Function HAL_IRDA_RegisterCallback() to register a user callback.
00129     Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
00130     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00131     (+) TxCpltCallback            : Tx Complete Callback.
00132     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00133     (+) RxCpltCallback            : Rx Complete Callback.
00134     (+) ErrorCallback             : Error Callback.
00135     (+) AbortCpltCallback         : Abort Complete Callback.
00136     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00137     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00138     (+) MspInitCallback           : IRDA MspInit.
00139     (+) MspDeInitCallback         : IRDA MspDeInit.
00140     This function takes as parameters the HAL peripheral handle, the Callback ID
00141     and a pointer to the user callback function.
00142
00143     [..]
00144     Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
00145     weak (surcharged) function.
00146     HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00147     and the Callback ID.
00148     This function allows to reset following callbacks:
00149     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00150     (+) TxCpltCallback            : Tx Complete Callback.
00151     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00152     (+) RxCpltCallback            : Rx Complete Callback.
00153     (+) ErrorCallback             : Error Callback.
00154     (+) AbortCpltCallback         : Abort Complete Callback.
00155     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00156     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00157     (+) MspInitCallback           : IRDA MspInit.
00158     (+) MspDeInitCallback         : IRDA MspDeInit.
00159
00160     [..]
00161     By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
00162     all callbacks are set to the corresponding weak (surcharged) functions:
00163     examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
00164     Exception done for MspInit and MspDeInit functions that are respectively
00165     reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
00166     and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
00167     If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
00168     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00169
00170     [..]
00171     Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
00172     Exception done MspInit/MspDeInit that can be registered/unregistered
00173     in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
00174     MspInit/DeInit callbacks can be used during the Init/DeInit.
00175     In that case first register the MspInit/MspDeInit user callbacks
00176     using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
00177     or HAL_IRDA_Init() function.
00178
00179     [..]
00180     When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
00181     not defined, the callback registration feature is not available
00182     and weak (surcharged) callbacks are used.
00183
00184   @endverbatim
00185   ******************************************************************************
00186   */
00187
00188 /* Includes ------------------------------------------------------------------*/
00189 #include "stm32g0xx_hal.h"
00190
00191 /** @addtogroup STM32G0xx_HAL_Driver
00192   * @{
00193   */
00194
00195 /** @defgroup IRDA IRDA
00196   * @brief HAL IRDA module driver
00197   * @{
00198   */
00199
00200 #ifdef HAL_IRDA_MODULE_ENABLED
00201
00202 /* Private typedef -----------------------------------------------------------*/
00203 /* Private define ------------------------------------------------------------*/
00204 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00205   * @{
00206   */
00207 #define IRDA_TEACK_REACK_TIMEOUT            1000U                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
00208
00209 #define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
00210                                      | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
00211
00212 #define USART_BRR_MIN    0x10U        /*!< USART BRR minimum authorized value */
00213
00214 #define USART_BRR_MAX    0x0000FFFFU  /*!< USART BRR maximum authorized value */
00215 /**
00216   * @}
00217   */
00218
00219 /* Private macros ------------------------------------------------------------*/
00220 /** @defgroup IRDA_Private_Macros IRDA Private Macros
00221   * @{
00222   */
00223 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
00224   * @param  __PCLK__ IRDA clock source.
00225   * @param  __BAUD__ Baud rate set by the user.
00226   * @param  __PRESCALER__ IRDA clock prescaler value.
00227   * @retval Division result
00228   */
00229 #define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)  ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
00230                                                                   + ((__BAUD__)/2U)) / (__BAUD__))
00231 /**
00232   * @}
00233   */
00234
00235 /* Private variables ---------------------------------------------------------*/
00236 /* Private function prototypes -----------------------------------------------*/
00237 /** @addtogroup IRDA_Private_Functions
00238   * @{
00239   */
00240 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00241 void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
00242 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00243 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
00244 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
00245 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
00246                                                      uint32_t Tickstart, uint32_t Timeout);
00247 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
00248 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
00249 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00250 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00251 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00252 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00253 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00254 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00255 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00256 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00257 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00258 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00259 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00260 static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00261 static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00262 /**
00263   * @}
00264   */
00265
00266 /* Exported functions --------------------------------------------------------*/
00267
00268 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
00269   * @{
00270   */
00271
00272 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00273   *  @brief    Initialization and Configuration functions
00274   *
00275 @verbatim
00276   ==============================================================================
00277               ##### Initialization and Configuration functions #####
00278   ==============================================================================
00279   [..]
00280   This subsection provides a set of functions allowing to initialize the USARTx
00281   in asynchronous IRDA mode.
00282   (+) For the asynchronous mode only these parameters can be configured:
00283       (++) Baud Rate
00284       (++) Word Length
00285       (++) Parity: If the parity is enabled, then the MSB bit of the data written
00286            in the data register is transmitted but is changed by the parity bit.
00287       (++) Power mode
00288       (++) Prescaler setting
00289       (++) Receiver/transmitter modes
00290
00291   [..]
00292   The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
00293   (details for the procedures are available in reference manual).
00294
00295 @endverbatim
00296
00297   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00298   8-bit or 9-bit), the possible IRDA frame formats are listed in the
00299   following table.
00300
00301     Table 1. IRDA frame format.
00302     +-----------------------------------------------------------------------+
00303     |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
00304     |---------|---------|-----------|---------------------------------------|
00305     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00306     |---------|---------|-----------|---------------------------------------|
00307     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00308     |---------|---------|-----------|---------------------------------------|
00309     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00310     |---------|---------|-----------|---------------------------------------|
00311     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00312     |---------|---------|-----------|---------------------------------------|
00313     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00314     |---------|---------|-----------|---------------------------------------|
00315     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00316     +-----------------------------------------------------------------------+
00317
00318   * @{
00319   */
00320
00321 /**
00322   * @brief Initialize the IRDA mode according to the specified
00323   *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
00324   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00325   *               the configuration information for the specified IRDA module.
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00329 {
00330   /* Check the IRDA handle allocation */
00331   if (hirda == NULL)
00332   {
00333     return HAL_ERROR;
00334   }
00335
00336   /* Check the USART/UART associated to the IRDA handle */
00337   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00338
00339   if (hirda->gState == HAL_IRDA_STATE_RESET)
00340   {
00341     /* Allocate lock resource and initialize it */
00342     hirda->Lock = HAL_UNLOCKED;
00343
00344 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00345     IRDA_InitCallbacksToDefault(hirda);
00346
00347     if (hirda->MspInitCallback == NULL)
00348     {
00349       hirda->MspInitCallback = HAL_IRDA_MspInit;
00350     }
00351
00352     /* Init the low level hardware */
00353     hirda->MspInitCallback(hirda);
00354 #else
00355     /* Init the low level hardware : GPIO, CLOCK */
00356     HAL_IRDA_MspInit(hirda);
00357 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00358   }
00359
00360   hirda->gState = HAL_IRDA_STATE_BUSY;
00361
00362   /* Disable the Peripheral to update the configuration registers */
00363   __HAL_IRDA_DISABLE(hirda);
00364
00365   /* Set the IRDA Communication parameters */
00366   if (IRDA_SetConfig(hirda) == HAL_ERROR)
00367   {
00368     return HAL_ERROR;
00369   }
00370
00371   /* In IRDA mode, the following bits must be kept cleared:
00372   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00373   - SCEN and HDSEL bits in the USART_CR3 register.*/
00374   CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
00375   CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
00376
00377   /* set the UART/USART in IRDA mode */
00378   hirda->Instance->CR3 |= USART_CR3_IREN;
00379
00380   /* Enable the Peripheral */
00381   __HAL_IRDA_ENABLE(hirda);
00382
00383   /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
00384   return (IRDA_CheckIdleState(hirda));
00385 }
00386
00387 /**
00388   * @brief DeInitialize the IRDA peripheral.
00389   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00390   *               the configuration information for the specified IRDA module.
00391   * @retval HAL status
00392   */
00393 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00394 {
00395   /* Check the IRDA handle allocation */
00396   if (hirda == NULL)
00397   {
00398     return HAL_ERROR;
00399   }
00400
00401   /* Check the USART/UART associated to the IRDA handle */
00402   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00403
00404   hirda->gState = HAL_IRDA_STATE_BUSY;
00405
00406   /* DeInit the low level hardware */
00407 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00408   if (hirda->MspDeInitCallback == NULL)
00409   {
00410     hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
00411   }
00412   /* DeInit the low level hardware */
00413   hirda->MspDeInitCallback(hirda);
00414 #else
00415   HAL_IRDA_MspDeInit(hirda);
00416 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00417   /* Disable the Peripheral */
00418   __HAL_IRDA_DISABLE(hirda);
00419
00420   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00421   hirda->gState    = HAL_IRDA_STATE_RESET;
00422   hirda->RxState   = HAL_IRDA_STATE_RESET;
00423
00424   /* Process Unlock */
00425   __HAL_UNLOCK(hirda);
00426
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief Initialize the IRDA MSP.
00432   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00433   *               the configuration information for the specified IRDA module.
00434   * @retval None
00435   */
00436 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00437 {
00438   /* Prevent unused argument(s) compilation warning */
00439   UNUSED(hirda);
00440
00441   /* NOTE: This function should not be modified, when the callback is needed,
00442            the HAL_IRDA_MspInit can be implemented in the user file
00443    */
00444 }
00445
00446 /**
00447   * @brief DeInitialize the IRDA MSP.
00448   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00449   *               the configuration information for the specified IRDA module.
00450   * @retval None
00451   */
00452 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00453 {
00454   /* Prevent unused argument(s) compilation warning */
00455   UNUSED(hirda);
00456
00457   /* NOTE: This function should not be modified, when the callback is needed,
00458            the HAL_IRDA_MspDeInit can be implemented in the user file
00459    */
00460 }
00461
00462 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00463 /**
00464   * @brief  Register a User IRDA Callback
00465   *         To be used instead of the weak predefined callback
00466   * @param  hirda irda handle
00467   * @param  CallbackID ID of the callback to be registered
00468   *         This parameter can be one of the following values:
00469   *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00470   *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
00471   *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00472   *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
00473   *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
00474   *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00475   *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00476   *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00477   *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
00478   *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
00479   * @param  pCallback pointer to the Callback function
00480   * @retval HAL status
00481   */
00482 HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
00483                                             pIRDA_CallbackTypeDef pCallback)
00484 {
00485   HAL_StatusTypeDef status = HAL_OK;
00486
00487   if (pCallback == NULL)
00488   {
00489     /* Update the error code */
00490     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00491
00492     return HAL_ERROR;
00493   }
00494   /* Process locked */
00495   __HAL_LOCK(hirda);
00496
00497   if (hirda->gState == HAL_IRDA_STATE_READY)
00498   {
00499     switch (CallbackID)
00500     {
00501       case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
00502         hirda->TxHalfCpltCallback = pCallback;
00503         break;
00504
00505       case HAL_IRDA_TX_COMPLETE_CB_ID :
00506         hirda->TxCpltCallback = pCallback;
00507         break;
00508
00509       case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
00510         hirda->RxHalfCpltCallback = pCallback;
00511         break;
00512
00513       case HAL_IRDA_RX_COMPLETE_CB_ID :
00514         hirda->RxCpltCallback = pCallback;
00515         break;
00516
00517       case HAL_IRDA_ERROR_CB_ID :
00518         hirda->ErrorCallback = pCallback;
00519         break;
00520
00521       case HAL_IRDA_ABORT_COMPLETE_CB_ID :
00522         hirda->AbortCpltCallback = pCallback;
00523         break;
00524
00525       case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
00526         hirda->AbortTransmitCpltCallback = pCallback;
00527         break;
00528
00529       case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
00530         hirda->AbortReceiveCpltCallback = pCallback;
00531         break;
00532
00533       case HAL_IRDA_MSPINIT_CB_ID :
00534         hirda->MspInitCallback = pCallback;
00535         break;
00536
00537       case HAL_IRDA_MSPDEINIT_CB_ID :
00538         hirda->MspDeInitCallback = pCallback;
00539         break;
00540
00541       default :
00542         /* Update the error code */
00543         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00544
00545         /* Return error status */
00546         status =  HAL_ERROR;
00547         break;
00548     }
00549   }
00550   else if (hirda->gState == HAL_IRDA_STATE_RESET)
00551   {
00552     switch (CallbackID)
00553     {
00554       case HAL_IRDA_MSPINIT_CB_ID :
00555         hirda->MspInitCallback = pCallback;
00556         break;
00557
00558       case HAL_IRDA_MSPDEINIT_CB_ID :
00559         hirda->MspDeInitCallback = pCallback;
00560         break;
00561
00562       default :
00563         /* Update the error code */
00564         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00565
00566         /* Return error status */
00567         status =  HAL_ERROR;
00568         break;
00569     }
00570   }
00571   else
00572   {
00573     /* Update the error code */
00574     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00575
00576     /* Return error status */
00577     status =  HAL_ERROR;
00578   }
00579
00580   /* Release Lock */
00581   __HAL_UNLOCK(hirda);
00582
00583   return status;
00584 }
00585
00586 /**
00587   * @brief  Unregister an IRDA callback
00588   *         IRDA callback is redirected to the weak predefined callback
00589   * @param  hirda irda handle
00590   * @param  CallbackID ID of the callback to be unregistered
00591   *         This parameter can be one of the following values:
00592   *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00593   *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
00594   *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00595   *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
00596   *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
00597   *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00598   *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00599   *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00600   *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
00601   *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
00602   * @retval HAL status
00603   */
00604 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
00605 {
00606   HAL_StatusTypeDef status = HAL_OK;
00607
00608   /* Process locked */
00609   __HAL_LOCK(hirda);
00610
00611   if (HAL_IRDA_STATE_READY == hirda->gState)
00612   {
00613     switch (CallbackID)
00614     {
00615       case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
00616         hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
00617         break;
00618
00619       case HAL_IRDA_TX_COMPLETE_CB_ID :
00620         hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
00621         break;
00622
00623       case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
00624         hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
00625         break;
00626
00627       case HAL_IRDA_RX_COMPLETE_CB_ID :
00628         hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
00629         break;
00630
00631       case HAL_IRDA_ERROR_CB_ID :
00632         hirda->ErrorCallback = HAL_IRDA_ErrorCallback;                         /* Legacy weak ErrorCallback          */
00633         break;
00634
00635       case HAL_IRDA_ABORT_COMPLETE_CB_ID :
00636         hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
00637         break;
00638
00639       case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
00640         hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
00641                                                                                   AbortTransmitCpltCallback          */
00642         break;
00643
00644       case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
00645         hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback;   /* Legacy weak
00646                                                                                   AbortReceiveCpltCallback           */
00647         break;
00648
00649       case HAL_IRDA_MSPINIT_CB_ID :
00650         hirda->MspInitCallback = HAL_IRDA_MspInit;                             /* Legacy weak MspInitCallback        */
00651         break;
00652
00653       case HAL_IRDA_MSPDEINIT_CB_ID :
00654         hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
00655         break;
00656
00657       default :
00658         /* Update the error code */
00659         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00660
00661         /* Return error status */
00662         status =  HAL_ERROR;
00663         break;
00664     }
00665   }
00666   else if (HAL_IRDA_STATE_RESET == hirda->gState)
00667   {
00668     switch (CallbackID)
00669     {
00670       case HAL_IRDA_MSPINIT_CB_ID :
00671         hirda->MspInitCallback = HAL_IRDA_MspInit;
00672         break;
00673
00674       case HAL_IRDA_MSPDEINIT_CB_ID :
00675         hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
00676         break;
00677
00678       default :
00679         /* Update the error code */
00680         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00681
00682         /* Return error status */
00683         status =  HAL_ERROR;
00684         break;
00685     }
00686   }
00687   else
00688   {
00689     /* Update the error code */
00690     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00691
00692     /* Return error status */
00693     status =  HAL_ERROR;
00694   }
00695
00696   /* Release Lock */
00697   __HAL_UNLOCK(hirda);
00698
00699   return status;
00700 }
00701 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00702
00703 /**
00704   * @}
00705   */
00706
00707 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00708   *  @brief   IRDA Transmit and Receive functions
00709   *
00710 @verbatim
00711  ===============================================================================
00712                          ##### IO operation functions #####
00713  ===============================================================================
00714   [..]
00715     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00716
00717   [..]
00718     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00719     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00720     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00721     While receiving data, transmission should be avoided as the data to be transmitted
00722     could be corrupted.
00723
00724   [..]
00725     (#) There are two modes of transfer:
00726         (++) Blocking mode: the communication is performed in polling mode.
00727              The HAL status of all data processing is returned by the same function
00728              after finishing transfer.
00729         (++) Non-Blocking mode: the communication is performed using Interrupts
00730              or DMA, these API's return the HAL status.
00731              The end of the data processing will be indicated through the
00732              dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00733              using DMA mode.
00734              The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00735              will be executed respectively at the end of the Transmit or Receive process
00736              The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00737
00738     (#) Blocking mode APIs are :
00739         (++) HAL_IRDA_Transmit()
00740         (++) HAL_IRDA_Receive()
00741
00742     (#) Non Blocking mode APIs with Interrupt are :
00743         (++) HAL_IRDA_Transmit_IT()
00744         (++) HAL_IRDA_Receive_IT()
00745         (++) HAL_IRDA_IRQHandler()
00746
00747     (#) Non Blocking mode functions with DMA are :
00748         (++) HAL_IRDA_Transmit_DMA()
00749         (++) HAL_IRDA_Receive_DMA()
00750         (++) HAL_IRDA_DMAPause()
00751         (++) HAL_IRDA_DMAResume()
00752         (++) HAL_IRDA_DMAStop()
00753
00754     (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
00755         (++) HAL_IRDA_TxHalfCpltCallback()
00756         (++) HAL_IRDA_TxCpltCallback()
00757         (++) HAL_IRDA_RxHalfCpltCallback()
00758         (++) HAL_IRDA_RxCpltCallback()
00759         (++) HAL_IRDA_ErrorCallback()
00760
00761     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00762         (++) HAL_IRDA_Abort()
00763         (++) HAL_IRDA_AbortTransmit()
00764         (++) HAL_IRDA_AbortReceive()
00765         (++) HAL_IRDA_Abort_IT()
00766         (++) HAL_IRDA_AbortTransmit_IT()
00767         (++) HAL_IRDA_AbortReceive_IT()
00768
00769     (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00770         (++) HAL_IRDA_AbortCpltCallback()
00771         (++) HAL_IRDA_AbortTransmitCpltCallback()
00772         (++) HAL_IRDA_AbortReceiveCpltCallback()
00773
00774     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00775         Errors are handled as follows :
00776         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00777              to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
00778              in Interrupt mode reception .
00779              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
00780              to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
00781              Transfer is kept ongoing on IRDA side.
00782              If user wants to abort it, Abort services should be called by user.
00783         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00784              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00785              Error code is set to allow user to identify error type, and
00786              HAL_IRDA_ErrorCallback() user callback is executed.
00787
00788 @endverbatim
00789   * @{
00790   */
00791
00792 /**
00793   * @brief Send an amount of data in blocking mode.
00794   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00795   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
00796   *        of u16 available through pData.
00797   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00798   *               the configuration information for the specified IRDA module.
00799   * @param pData Pointer to data buffer (u8 or u16 data elements).
00800   * @param Size Amount of data elements (u8 or u16) to be sent.
00801   * @param Timeout Specify timeout value.
00802   * @retval HAL status
00803   */
00804 /**
00805   * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00806   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
00807   *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
00808   *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
00809   */
00810 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
00811 {
00812   const uint8_t  *pdata8bits;
00813   const uint16_t *pdata16bits;
00814   uint32_t tickstart;
00815
00816   /* Check that a Tx process is not already ongoing */
00817   if (hirda->gState == HAL_IRDA_STATE_READY)
00818   {
00819     if ((pData == NULL) || (Size == 0U))
00820     {
00821       return  HAL_ERROR;
00822     }
00823
00824     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
00825        should be aligned on a u16 frontier, as data to be filled into TDR will be
00826        handled through a u16 cast. */
00827     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00828     {
00829       if ((((uint32_t)pData) & 1U) != 0U)
00830       {
00831         return  HAL_ERROR;
00832       }
00833     }
00834
00835     /* Process Locked */
00836     __HAL_LOCK(hirda);
00837
00838     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00839     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00840
00841     /* Init tickstart for timeout management */
00842     tickstart = HAL_GetTick();
00843
00844     hirda->TxXferSize = Size;
00845     hirda->TxXferCount = Size;
00846
00847     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
00848     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00849     {
00850       pdata8bits  = NULL;
00851       pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
00852     }
00853     else
00854     {
00855       pdata8bits  = pData;
00856       pdata16bits = NULL;
00857     }
00858
00859     while (hirda->TxXferCount > 0U)
00860     {
00861       hirda->TxXferCount--;
00862
00863       if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00864       {
00865         return HAL_TIMEOUT;
00866       }
00867       if (pdata8bits == NULL)
00868       {
00869         hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
00870         pdata16bits++;
00871       }
00872       else
00873       {
00874         hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
00875         pdata8bits++;
00876       }
00877     }
00878
00879     if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00880     {
00881       return HAL_TIMEOUT;
00882     }
00883
00884     /* At end of Tx process, restore hirda->gState to Ready */
00885     hirda->gState = HAL_IRDA_STATE_READY;
00886
00887     /* Process Unlocked */
00888     __HAL_UNLOCK(hirda);
00889
00890     return HAL_OK;
00891   }
00892   else
00893   {
00894     return HAL_BUSY;
00895   }
00896 }
00897
00898 /**
00899   * @brief Receive an amount of data in blocking mode.
00900   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00901   *        the received data is handled as a set of u16. In this case, Size must reflect the number
00902   *        of u16 available through pData.
00903   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00904   *                the configuration information for the specified IRDA module.
00905   * @param pData Pointer to data buffer (u8 or u16 data elements).
00906   * @param Size Amount of data elements (u8 or u16) to be received.
00907   * @param Timeout Specify timeout value.
00908   * @retval HAL status
00909   */
00910 /**
00911   * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00912   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
00913   *         (as received data will be handled using u16 pointer cast). Depending on compilation chain,
00914   *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
00915   */
00916 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00917 {
00918   uint8_t  *pdata8bits;
00919   uint16_t *pdata16bits;
00920   uint16_t uhMask;
00921   uint32_t tickstart;
00922
00923   /* Check that a Rx process is not already ongoing */
00924   if (hirda->RxState == HAL_IRDA_STATE_READY)
00925   {
00926     if ((pData == NULL) || (Size == 0U))
00927     {
00928       return  HAL_ERROR;
00929     }
00930
00931     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
00932        should be aligned on a u16 frontier, as data to be received from RDR will be
00933        handled through a u16 cast. */
00934     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00935     {
00936       if ((((uint32_t)pData) & 1U) != 0U)
00937       {
00938         return  HAL_ERROR;
00939       }
00940     }
00941
00942     /* Process Locked */
00943     __HAL_LOCK(hirda);
00944
00945     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00946     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00947
00948     /* Init tickstart for timeout management */
00949     tickstart = HAL_GetTick();
00950
00951     hirda->RxXferSize = Size;
00952     hirda->RxXferCount = Size;
00953
00954     /* Computation of the mask to apply to RDR register
00955        of the UART associated to the IRDA */
00956     IRDA_MASK_COMPUTATION(hirda);
00957     uhMask = hirda->Mask;
00958
00959     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00960     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00961     {
00962       pdata8bits  = NULL;
00963       pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
00964     }
00965     else
00966     {
00967       pdata8bits  = pData;
00968       pdata16bits = NULL;
00969     }
00970
00971     /* Check data remaining to be received */
00972     while (hirda->RxXferCount > 0U)
00973     {
00974       hirda->RxXferCount--;
00975
00976       if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00977       {
00978         return HAL_TIMEOUT;
00979       }
00980       if (pdata8bits == NULL)
00981       {
00982         *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
00983         pdata16bits++;
00984       }
00985       else
00986       {
00987         *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
00988         pdata8bits++;
00989       }
00990     }
00991
00992     /* At end of Rx process, restore hirda->RxState to Ready */
00993     hirda->RxState = HAL_IRDA_STATE_READY;
00994
00995     /* Process Unlocked */
00996     __HAL_UNLOCK(hirda);
00997
00998     return HAL_OK;
00999   }
01000   else
01001   {
01002     return HAL_BUSY;
01003   }
01004 }
01005
01006 /**
01007   * @brief Send an amount of data in interrupt mode.
01008   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01009   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
01010   *        of u16 available through pData.
01011   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01012   *                the configuration information for the specified IRDA module.
01013   * @param pData Pointer to data buffer (u8 or u16 data elements).
01014   * @param Size Amount of data elements (u8 or u16) to be sent.
01015   * @retval HAL status
01016   */
01017 /**
01018   * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01019   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
01020   *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
01021   *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
01022   */
01023 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
01024 {
01025   /* Check that a Tx process is not already ongoing */
01026   if (hirda->gState == HAL_IRDA_STATE_READY)
01027   {
01028     if ((pData == NULL) || (Size == 0U))
01029     {
01030       return HAL_ERROR;
01031     }
01032
01033     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01034        should be aligned on a u16 frontier, as data to be filled into TDR will be
01035        handled through a u16 cast. */
01036     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
01037     {
01038       if ((((uint32_t)pData) & 1U) != 0U)
01039       {
01040         return  HAL_ERROR;
01041       }
01042     }
01043
01044     /* Process Locked */
01045     __HAL_LOCK(hirda);
01046
01047     hirda->pTxBuffPtr = pData;
01048     hirda->TxXferSize = Size;
01049     hirda->TxXferCount = Size;
01050
01051     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01052     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
01053
01054     /* Process Unlocked */
01055     __HAL_UNLOCK(hirda);
01056
01057     /* Enable the IRDA Transmit Data Register Empty Interrupt */
01058     SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01059
01060     return HAL_OK;
01061   }
01062   else
01063   {
01064     return HAL_BUSY;
01065   }
01066 }
01067
01068 /**
01069   * @brief Receive an amount of data in interrupt mode.
01070   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01071   *        the received data is handled as a set of u16. In this case, Size must reflect the number
01072   *        of u16 available through pData.
01073   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01074   *                the configuration information for the specified IRDA module.
01075   * @param pData Pointer to data buffer (u8 or u16 data elements).
01076   * @param Size Amount of data elements (u8 or u16) to be received.
01077   * @retval HAL status
01078   */
01079 /**
01080   * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01081   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
01082   *         (as received data will be handled using u16 pointer cast). Depending on compilation chain,
01083   *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
01084   */
01085 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01086 {
01087   /* Check that a Rx process is not already ongoing */
01088   if (hirda->RxState == HAL_IRDA_STATE_READY)
01089   {
01090     if ((pData == NULL) || (Size == 0U))
01091     {
01092       return HAL_ERROR;
01093     }
01094
01095     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01096        should be aligned on a u16 frontier, as data to be received from RDR will be
01097        handled through a u16 cast. */
01098     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
01099     {
01100       if ((((uint32_t)pData) & 1U) != 0U)
01101       {
01102         return  HAL_ERROR;
01103       }
01104     }
01105
01106     /* Process Locked */
01107     __HAL_LOCK(hirda);
01108
01109     hirda->pRxBuffPtr = pData;
01110     hirda->RxXferSize = Size;
01111     hirda->RxXferCount = Size;
01112
01113     /* Computation of the mask to apply to the RDR register
01114        of the UART associated to the IRDA */
01115     IRDA_MASK_COMPUTATION(hirda);
01116
01117     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01118     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
01119
01120     /* Process Unlocked */
01121     __HAL_UNLOCK(hirda);
01122
01123     if (hirda->Init.Parity != IRDA_PARITY_NONE)
01124     {
01125       /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
01126       SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01127     }
01128     else
01129     {
01130       /* Enable the IRDA Data Register not empty Interrupts */
01131       SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
01132     }
01133
01134     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01135     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01136
01137     return HAL_OK;
01138   }
01139   else
01140   {
01141     return HAL_BUSY;
01142   }
01143 }
01144
01145 /**
01146   * @brief Send an amount of data in DMA mode.
01147   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01148   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
01149   *        of u16 available through pData.
01150   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
01151   *               the configuration information for the specified IRDA module.
01152   * @param pData pointer to data buffer (u8 or u16 data elements).
01153   * @param Size Amount of data elements (u8 or u16) to be sent.
01154   * @retval HAL status
01155   */
01156 /**
01157   * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01158   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
01159   *         (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
01160   *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
01161   */
01162 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
01163 {
01164   /* Check that a Tx process is not already ongoing */
01165   if (hirda->gState == HAL_IRDA_STATE_READY)
01166   {
01167     if ((pData == NULL) || (Size == 0U))
01168     {
01169       return HAL_ERROR;
01170     }
01171
01172     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01173        should be aligned on a u16 frontier, as data copy into TDR will be
01174        handled by DMA from a u16 frontier. */
01175     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
01176     {
01177       if ((((uint32_t)pData) & 1U) != 0U)
01178       {
01179         return  HAL_ERROR;
01180       }
01181     }
01182
01183     /* Process Locked */
01184     __HAL_LOCK(hirda);
01185
01186     hirda->pTxBuffPtr = pData;
01187     hirda->TxXferSize = Size;
01188     hirda->TxXferCount = Size;
01189
01190     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01191     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
01192
01193     /* Set the IRDA DMA transfer complete callback */
01194     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
01195
01196     /* Set the IRDA DMA half transfer complete callback */
01197     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
01198
01199     /* Set the DMA error callback */
01200     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
01201
01202     /* Set the DMA abort callback */
01203     hirda->hdmatx->XferAbortCallback = NULL;
01204
01205     /* Enable the IRDA transmit DMA channel */
01206     if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK)
01207     {
01208       /* Clear the TC flag in the ICR register */
01209       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
01210
01211       /* Process Unlocked */
01212       __HAL_UNLOCK(hirda);
01213
01214       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01215          in the USART CR3 register */
01216       SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01217
01218       return HAL_OK;
01219     }
01220     else
01221     {
01222       /* Set error code to DMA */
01223       hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01224
01225       /* Process Unlocked */
01226       __HAL_UNLOCK(hirda);
01227
01228       /* Restore hirda->gState to ready */
01229       hirda->gState = HAL_IRDA_STATE_READY;
01230
01231       return HAL_ERROR;
01232     }
01233   }
01234   else
01235   {
01236     return HAL_BUSY;
01237   }
01238 }
01239
01240 /**
01241   * @brief Receive an amount of data in DMA mode.
01242   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01243   *        the received data is handled as a set of u16. In this case, Size must reflect the number
01244   *        of u16 available through pData.
01245   * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
01246   *         the parity bit (MSB position).
01247   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
01248   *               the configuration information for the specified IRDA module.
01249   * @param pData Pointer to data buffer (u8 or u16 data elements).
01250   * @param Size Amount of data elements (u8 or u16) to be received.
01251   * @retval HAL status
01252   */
01253 /**
01254   * @note   When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01255   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
01256   *         (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
01257   *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
01258   */
01259 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01260 {
01261   /* Check that a Rx process is not already ongoing */
01262   if (hirda->RxState == HAL_IRDA_STATE_READY)
01263   {
01264     if ((pData == NULL) || (Size == 0U))
01265     {
01266       return HAL_ERROR;
01267     }
01268
01269     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01270        should be aligned on a u16 frontier, as data copy from RDR will be
01271        handled by DMA from a u16 frontier. */
01272     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
01273     {
01274       if ((((uint32_t)pData) & 1U) != 0U)
01275       {
01276         return  HAL_ERROR;
01277       }
01278     }
01279
01280     /* Process Locked */
01281     __HAL_LOCK(hirda);
01282
01283     hirda->pRxBuffPtr = pData;
01284     hirda->RxXferSize = Size;
01285
01286     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01287     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
01288
01289     /* Set the IRDA DMA transfer complete callback */
01290     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
01291
01292     /* Set the IRDA DMA half transfer complete callback */
01293     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
01294
01295     /* Set the DMA error callback */
01296     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
01297
01298     /* Set the DMA abort callback */
01299     hirda->hdmarx->XferAbortCallback = NULL;
01300
01301     /* Enable the DMA channel */
01302     if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK)
01303     {
01304       /* Process Unlocked */
01305       __HAL_UNLOCK(hirda);
01306
01307       if (hirda->Init.Parity != IRDA_PARITY_NONE)
01308       {
01309         /* Enable the UART Parity Error Interrupt */
01310         SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01311       }
01312
01313       /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01314       SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01315
01316       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01317          in the USART CR3 register */
01318       SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01319
01320       return HAL_OK;
01321     }
01322     else
01323     {
01324       /* Set error code to DMA */
01325       hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01326
01327       /* Process Unlocked */
01328       __HAL_UNLOCK(hirda);
01329
01330       /* Restore hirda->RxState to ready */
01331       hirda->RxState = HAL_IRDA_STATE_READY;
01332
01333       return HAL_ERROR;
01334     }
01335   }
01336   else
01337   {
01338     return HAL_BUSY;
01339   }
01340 }
01341
01342
01343 /**
01344   * @brief Pause the DMA Transfer.
01345   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01346   *                the configuration information for the specified IRDA module.
01347   * @retval HAL status
01348   */
01349 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
01350 {
01351   /* Process Locked */
01352   __HAL_LOCK(hirda);
01353
01354   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01355   {
01356     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01357     {
01358       /* Disable the IRDA DMA Tx request */
01359       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01360     }
01361   }
01362   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01363   {
01364     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01365     {
01366       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01367       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01368       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01369
01370       /* Disable the IRDA DMA Rx request */
01371       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01372     }
01373   }
01374
01375   /* Process Unlocked */
01376   __HAL_UNLOCK(hirda);
01377
01378   return HAL_OK;
01379 }
01380
01381 /**
01382   * @brief Resume the DMA Transfer.
01383   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01384   *                the configuration information for the specified UART module.
01385   * @retval HAL status
01386   */
01387 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
01388 {
01389   /* Process Locked */
01390   __HAL_LOCK(hirda);
01391
01392   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01393   {
01394     /* Enable the IRDA DMA Tx request */
01395     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01396   }
01397   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01398   {
01399     /* Clear the Overrun flag before resuming the Rx transfer*/
01400     __HAL_IRDA_CLEAR_OREFLAG(hirda);
01401
01402     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
01403     if (hirda->Init.Parity != IRDA_PARITY_NONE)
01404     {
01405       SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01406     }
01407     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01408
01409     /* Enable the IRDA DMA Rx request */
01410     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01411   }
01412
01413   /* Process Unlocked */
01414   __HAL_UNLOCK(hirda);
01415
01416   return HAL_OK;
01417 }
01418
01419 /**
01420   * @brief Stop the DMA Transfer.
01421   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01422   *                the configuration information for the specified UART module.
01423   * @retval HAL status
01424   */
01425 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
01426 {
01427   /* The Lock is not implemented on this API to allow the user application
01428      to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
01429      HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
01430      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01431      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01432      the stream and the corresponding call back is executed. */
01433
01434   /* Stop IRDA DMA Tx request if ongoing */
01435   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01436   {
01437     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01438     {
01439       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01440
01441       /* Abort the IRDA DMA Tx channel */
01442       if (hirda->hdmatx != NULL)
01443       {
01444         if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01445         {
01446           if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01447           {
01448             /* Set error code to DMA */
01449             hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01450
01451             return HAL_TIMEOUT;
01452           }
01453         }
01454       }
01455
01456       IRDA_EndTxTransfer(hirda);
01457     }
01458   }
01459
01460   /* Stop IRDA DMA Rx request if ongoing */
01461   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01462   {
01463     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01464     {
01465       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01466
01467       /* Abort the IRDA DMA Rx channel */
01468       if (hirda->hdmarx != NULL)
01469       {
01470         if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01471         {
01472           if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01473           {
01474             /* Set error code to DMA */
01475             hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01476
01477             return HAL_TIMEOUT;
01478           }
01479         }
01480       }
01481
01482       IRDA_EndRxTransfer(hirda);
01483     }
01484   }
01485
01486   return HAL_OK;
01487 }
01488
01489 /**
01490   * @brief  Abort ongoing transfers (blocking mode).
01491   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01492   *               the configuration information for the specified UART module.
01493   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01494   *         This procedure performs following operations :
01495   *           - Disable IRDA Interrupts (Tx and Rx)
01496   *           - Disable the DMA transfer in the peripheral register (if enabled)
01497   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01498   *           - Set handle State to READY
01499   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01500   * @retval HAL status
01501   */
01502 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
01503 {
01504   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01505   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
01506                                    USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01507   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01508
01509   /* Disable the IRDA DMA Tx request if enabled */
01510   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01511   {
01512     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01513
01514     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01515     if (hirda->hdmatx != NULL)
01516     {
01517       /* Set the IRDA DMA Abort callback to Null.
01518          No call back execution at end of DMA abort procedure */
01519       hirda->hdmatx->XferAbortCallback = NULL;
01520
01521       if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01522       {
01523         if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01524         {
01525           /* Set error code to DMA */
01526           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01527
01528           return HAL_TIMEOUT;
01529         }
01530       }
01531     }
01532   }
01533
01534   /* Disable the IRDA DMA Rx request if enabled */
01535   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01536   {
01537     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01538
01539     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01540     if (hirda->hdmarx != NULL)
01541     {
01542       /* Set the IRDA DMA Abort callback to Null.
01543          No call back execution at end of DMA abort procedure */
01544       hirda->hdmarx->XferAbortCallback = NULL;
01545
01546       if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01547       {
01548         if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01549         {
01550           /* Set error code to DMA */
01551           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01552
01553           return HAL_TIMEOUT;
01554         }
01555       }
01556     }
01557   }
01558
01559   /* Reset Tx and Rx transfer counters */
01560   hirda->TxXferCount = 0U;
01561   hirda->RxXferCount = 0U;
01562
01563   /* Clear the Error flags in the ICR register */
01564   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01565
01566   /* Restore hirda->gState and hirda->RxState to Ready */
01567   hirda->gState  = HAL_IRDA_STATE_READY;
01568   hirda->RxState = HAL_IRDA_STATE_READY;
01569
01570   /* Reset Handle ErrorCode to No Error */
01571   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01572
01573   return HAL_OK;
01574 }
01575
01576 /**
01577   * @brief  Abort ongoing Transmit transfer (blocking mode).
01578   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01579   *               the configuration information for the specified UART module.
01580   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01581   *         This procedure performs following operations :
01582   *           - Disable IRDA Interrupts (Tx)
01583   *           - Disable the DMA transfer in the peripheral register (if enabled)
01584   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01585   *           - Set handle State to READY
01586   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01587   * @retval HAL status
01588   */
01589 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
01590 {
01591   /* Disable TXEIE and TCIE interrupts */
01592   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01593
01594   /* Disable the IRDA DMA Tx request if enabled */
01595   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01596   {
01597     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01598
01599     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01600     if (hirda->hdmatx != NULL)
01601     {
01602       /* Set the IRDA DMA Abort callback to Null.
01603          No call back execution at end of DMA abort procedure */
01604       hirda->hdmatx->XferAbortCallback = NULL;
01605
01606       if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01607       {
01608         if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01609         {
01610           /* Set error code to DMA */
01611           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01612
01613           return HAL_TIMEOUT;
01614         }
01615       }
01616     }
01617   }
01618
01619   /* Reset Tx transfer counter */
01620   hirda->TxXferCount = 0U;
01621
01622   /* Restore hirda->gState to Ready */
01623   hirda->gState = HAL_IRDA_STATE_READY;
01624
01625   return HAL_OK;
01626 }
01627
01628 /**
01629   * @brief  Abort ongoing Receive transfer (blocking mode).
01630   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01631   *               the configuration information for the specified UART module.
01632   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01633   *         This procedure performs following operations :
01634   *           - Disable IRDA Interrupts (Rx)
01635   *           - Disable the DMA transfer in the peripheral register (if enabled)
01636   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01637   *           - Set handle State to READY
01638   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01639   * @retval HAL status
01640   */
01641 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
01642 {
01643   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01644   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
01645   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01646
01647   /* Disable the IRDA DMA Rx request if enabled */
01648   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01649   {
01650     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01651
01652     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01653     if (hirda->hdmarx != NULL)
01654     {
01655       /* Set the IRDA DMA Abort callback to Null.
01656          No call back execution at end of DMA abort procedure */
01657       hirda->hdmarx->XferAbortCallback = NULL;
01658
01659       if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01660       {
01661         if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01662         {
01663           /* Set error code to DMA */
01664           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01665
01666           return HAL_TIMEOUT;
01667         }
01668       }
01669     }
01670   }
01671
01672   /* Reset Rx transfer counter */
01673   hirda->RxXferCount = 0U;
01674
01675   /* Clear the Error flags in the ICR register */
01676   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01677
01678   /* Restore hirda->RxState to Ready */
01679   hirda->RxState = HAL_IRDA_STATE_READY;
01680
01681   return HAL_OK;
01682 }
01683
01684 /**
01685   * @brief  Abort ongoing transfers (Interrupt mode).
01686   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01687   *               the configuration information for the specified UART module.
01688   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01689   *         This procedure performs following operations :
01690   *           - Disable IRDA Interrupts (Tx and Rx)
01691   *           - Disable the DMA transfer in the peripheral register (if enabled)
01692   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01693   *           - Set handle State to READY
01694   *           - At abort completion, call user abort complete callback
01695   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01696   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01697   * @retval HAL status
01698   */
01699 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
01700 {
01701   uint32_t abortcplt = 1U;
01702
01703   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01704   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
01705                                    USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01706   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01707
01708   /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
01709      before any call to DMA Abort functions */
01710   /* DMA Tx Handle is valid */
01711   if (hirda->hdmatx != NULL)
01712   {
01713     /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
01714        Otherwise, set it to NULL */
01715     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01716     {
01717       hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
01718     }
01719     else
01720     {
01721       hirda->hdmatx->XferAbortCallback = NULL;
01722     }
01723   }
01724   /* DMA Rx Handle is valid */
01725   if (hirda->hdmarx != NULL)
01726   {
01727     /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
01728        Otherwise, set it to NULL */
01729     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01730     {
01731       hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
01732     }
01733     else
01734     {
01735       hirda->hdmarx->XferAbortCallback = NULL;
01736     }
01737   }
01738
01739   /* Disable the IRDA DMA Tx request if enabled */
01740   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01741   {
01742     /* Disable DMA Tx at UART level */
01743     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01744
01745     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01746     if (hirda->hdmatx != NULL)
01747     {
01748       /* IRDA Tx DMA Abort callback has already been initialised :
01749          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01750
01751       /* Abort DMA TX */
01752       if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01753       {
01754         hirda->hdmatx->XferAbortCallback = NULL;
01755       }
01756       else
01757       {
01758         abortcplt = 0U;
01759       }
01760     }
01761   }
01762
01763   /* Disable the IRDA DMA Rx request if enabled */
01764   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01765   {
01766     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01767
01768     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01769     if (hirda->hdmarx != NULL)
01770     {
01771       /* IRDA Rx DMA Abort callback has already been initialised :
01772          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01773
01774       /* Abort DMA RX */
01775       if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01776       {
01777         hirda->hdmarx->XferAbortCallback = NULL;
01778         abortcplt = 1U;
01779       }
01780       else
01781       {
01782         abortcplt = 0U;
01783       }
01784     }
01785   }
01786
01787   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01788   if (abortcplt == 1U)
01789   {
01790     /* Reset Tx and Rx transfer counters */
01791     hirda->TxXferCount = 0U;
01792     hirda->RxXferCount = 0U;
01793
01794     /* Reset errorCode */
01795     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01796
01797     /* Clear the Error flags in the ICR register */
01798     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01799
01800     /* Restore hirda->gState and hirda->RxState to Ready */
01801     hirda->gState  = HAL_IRDA_STATE_READY;
01802     hirda->RxState = HAL_IRDA_STATE_READY;
01803
01804     /* As no DMA to be aborted, call directly user Abort complete callback */
01805 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01806     /* Call registered Abort complete callback */
01807     hirda->AbortCpltCallback(hirda);
01808 #else
01809     /* Call legacy weak Abort complete callback */
01810     HAL_IRDA_AbortCpltCallback(hirda);
01811 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01812   }
01813
01814   return HAL_OK;
01815 }
01816
01817 /**
01818   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01819   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01820   *               the configuration information for the specified UART module.
01821   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01822   *         This procedure performs following operations :
01823   *           - Disable IRDA Interrupts (Tx)
01824   *           - Disable the DMA transfer in the peripheral register (if enabled)
01825   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01826   *           - Set handle State to READY
01827   *           - At abort completion, call user abort complete callback
01828   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01829   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01830   * @retval HAL status
01831   */
01832 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
01833 {
01834   /* Disable TXEIE and TCIE interrupts */
01835   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01836
01837   /* Disable the IRDA DMA Tx request if enabled */
01838   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01839   {
01840     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01841
01842     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01843     if (hirda->hdmatx != NULL)
01844     {
01845       /* Set the IRDA DMA Abort callback :
01846          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01847       hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
01848
01849       /* Abort DMA TX */
01850       if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01851       {
01852         /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
01853         hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
01854       }
01855     }
01856     else
01857     {
01858       /* Reset Tx transfer counter */
01859       hirda->TxXferCount = 0U;
01860
01861       /* Restore hirda->gState to Ready */
01862       hirda->gState = HAL_IRDA_STATE_READY;
01863
01864       /* As no DMA to be aborted, call directly user Abort complete callback */
01865 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01866       /* Call registered Abort Transmit Complete Callback */
01867       hirda->AbortTransmitCpltCallback(hirda);
01868 #else
01869       /* Call legacy weak Abort Transmit Complete Callback */
01870       HAL_IRDA_AbortTransmitCpltCallback(hirda);
01871 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01872     }
01873   }
01874   else
01875   {
01876     /* Reset Tx transfer counter */
01877     hirda->TxXferCount = 0U;
01878
01879     /* Restore hirda->gState to Ready */
01880     hirda->gState = HAL_IRDA_STATE_READY;
01881
01882     /* As no DMA to be aborted, call directly user Abort complete callback */
01883 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01884     /* Call registered Abort Transmit Complete Callback */
01885     hirda->AbortTransmitCpltCallback(hirda);
01886 #else
01887     /* Call legacy weak Abort Transmit Complete Callback */
01888     HAL_IRDA_AbortTransmitCpltCallback(hirda);
01889 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01890   }
01891
01892   return HAL_OK;
01893 }
01894
01895 /**
01896   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01897   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01898   *               the configuration information for the specified UART module.
01899   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01900   *         This procedure performs following operations :
01901   *           - Disable IRDA Interrupts (Rx)
01902   *           - Disable the DMA transfer in the peripheral register (if enabled)
01903   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01904   *           - Set handle State to READY
01905   *           - At abort completion, call user abort complete callback
01906   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01907   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01908   * @retval HAL status
01909   */
01910 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
01911 {
01912   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01913   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
01914   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01915
01916   /* Disable the IRDA DMA Rx request if enabled */
01917   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01918   {
01919     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01920
01921     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01922     if (hirda->hdmarx != NULL)
01923     {
01924       /* Set the IRDA DMA Abort callback :
01925          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01926       hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
01927
01928       /* Abort DMA RX */
01929       if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01930       {
01931         /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01932         hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01933       }
01934     }
01935     else
01936     {
01937       /* Reset Rx transfer counter */
01938       hirda->RxXferCount = 0U;
01939
01940       /* Clear the Error flags in the ICR register */
01941       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01942
01943       /* Restore hirda->RxState to Ready */
01944       hirda->RxState = HAL_IRDA_STATE_READY;
01945
01946       /* As no DMA to be aborted, call directly user Abort complete callback */
01947 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01948       /* Call registered Abort Receive Complete Callback */
01949       hirda->AbortReceiveCpltCallback(hirda);
01950 #else
01951       /* Call legacy weak Abort Receive Complete Callback */
01952       HAL_IRDA_AbortReceiveCpltCallback(hirda);
01953 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01954     }
01955   }
01956   else
01957   {
01958     /* Reset Rx transfer counter */
01959     hirda->RxXferCount = 0U;
01960
01961     /* Clear the Error flags in the ICR register */
01962     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01963
01964     /* Restore hirda->RxState to Ready */
01965     hirda->RxState = HAL_IRDA_STATE_READY;
01966
01967     /* As no DMA to be aborted, call directly user Abort complete callback */
01968 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01969     /* Call registered Abort Receive Complete Callback */
01970     hirda->AbortReceiveCpltCallback(hirda);
01971 #else
01972     /* Call legacy weak Abort Receive Complete Callback */
01973     HAL_IRDA_AbortReceiveCpltCallback(hirda);
01974 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01975   }
01976
01977   return HAL_OK;
01978 }
01979
01980 /**
01981   * @brief Handle IRDA interrupt request.
01982   * @param hirda  Pointer to a IRDA_HandleTypeDef structure that contains
01983   *               the configuration information for the specified IRDA module.
01984   * @retval None
01985   */
01986 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
01987 {
01988   uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
01989   uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
01990   uint32_t cr3its;
01991   uint32_t errorflags;
01992   uint32_t errorcode;
01993
01994   /* If no error occurs */
01995   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01996   if (errorflags == 0U)
01997   {
01998     /* IRDA in mode Receiver ---------------------------------------------------*/
01999     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
02000     {
02001       IRDA_Receive_IT(hirda);
02002       return;
02003     }
02004   }
02005
02006   /* If some errors occur */
02007   cr3its = READ_REG(hirda->Instance->CR3);
02008   if ((errorflags != 0U)
02009       && (((cr3its & USART_CR3_EIE) != 0U)
02010           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
02011   {
02012     /* IRDA parity error interrupt occurred -------------------------------------*/
02013     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02014     {
02015       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
02016
02017       hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
02018     }
02019
02020     /* IRDA frame error interrupt occurred --------------------------------------*/
02021     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02022     {
02023       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
02024
02025       hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
02026     }
02027
02028     /* IRDA noise error interrupt occurred --------------------------------------*/
02029     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02030     {
02031       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
02032
02033       hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
02034     }
02035
02036     /* IRDA Over-Run interrupt occurred -----------------------------------------*/
02037     if (((isrflags & USART_ISR_ORE) != 0U) &&
02038         (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
02039     {
02040       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
02041
02042       hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
02043     }
02044
02045     /* Call IRDA Error Call back function if need be --------------------------*/
02046     if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
02047     {
02048       /* IRDA in mode Receiver ---------------------------------------------------*/
02049       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
02050       {
02051         IRDA_Receive_IT(hirda);
02052       }
02053
02054       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
02055          consider error as blocking */
02056       errorcode = hirda->ErrorCode;
02057       if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
02058           ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
02059       {
02060         /* Blocking error : transfer is aborted
02061            Set the IRDA state ready to be able to start again the process,
02062            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
02063         IRDA_EndRxTransfer(hirda);
02064
02065         /* Disable the IRDA DMA Rx request if enabled */
02066         if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
02067         {
02068           CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
02069
02070           /* Abort the IRDA DMA Rx channel */
02071           if (hirda->hdmarx != NULL)
02072           {
02073             /* Set the IRDA DMA Abort callback :
02074                will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
02075             hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
02076
02077             /* Abort DMA RX */
02078             if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
02079             {
02080               /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
02081               hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
02082             }
02083           }
02084           else
02085           {
02086 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02087             /* Call registered user error callback */
02088             hirda->ErrorCallback(hirda);
02089 #else
02090             /* Call legacy weak user error callback */
02091             HAL_IRDA_ErrorCallback(hirda);
02092 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02093           }
02094         }
02095         else
02096         {
02097 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02098           /* Call registered user error callback */
02099           hirda->ErrorCallback(hirda);
02100 #else
02101           /* Call legacy weak user error callback */
02102           HAL_IRDA_ErrorCallback(hirda);
02103 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02104         }
02105       }
02106       else
02107       {
02108         /* Non Blocking error : transfer could go on.
02109            Error is notified to user through user error callback */
02110 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02111         /* Call registered user error callback */
02112         hirda->ErrorCallback(hirda);
02113 #else
02114         /* Call legacy weak user error callback */
02115         HAL_IRDA_ErrorCallback(hirda);
02116 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02117         hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02118       }
02119     }
02120     return;
02121
02122   } /* End if some error occurs */
02123
02124   /* IRDA in mode Transmitter ------------------------------------------------*/
02125   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U))
02126   {
02127     IRDA_Transmit_IT(hirda);
02128     return;
02129   }
02130
02131   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
02132   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02133   {
02134     IRDA_EndTransmit_IT(hirda);
02135     return;
02136   }
02137
02138 }
02139
02140 /**
02141   * @brief  Tx Transfer completed callback.
02142   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02143   *               the configuration information for the specified IRDA module.
02144   * @retval None
02145   */
02146 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
02147 {
02148   /* Prevent unused argument(s) compilation warning */
02149   UNUSED(hirda);
02150
02151   /* NOTE : This function should not be modified, when the callback is needed,
02152             the HAL_IRDA_TxCpltCallback can be implemented in the user file.
02153    */
02154 }
02155
02156 /**
02157   * @brief  Tx Half Transfer completed callback.
02158   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02159   *               the configuration information for the specified USART module.
02160   * @retval None
02161   */
02162 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
02163 {
02164   /* Prevent unused argument(s) compilation warning */
02165   UNUSED(hirda);
02166
02167   /* NOTE : This function should not be modified, when the callback is needed,
02168             the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
02169    */
02170 }
02171
02172 /**
02173   * @brief  Rx Transfer completed callback.
02174   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02175   *               the configuration information for the specified IRDA module.
02176   * @retval None
02177   */
02178 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
02179 {
02180   /* Prevent unused argument(s) compilation warning */
02181   UNUSED(hirda);
02182
02183   /* NOTE : This function should not be modified, when the callback is needed,
02184             the HAL_IRDA_RxCpltCallback can be implemented in the user file.
02185    */
02186 }
02187
02188 /**
02189   * @brief  Rx Half Transfer complete callback.
02190   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02191   *               the configuration information for the specified IRDA module.
02192   * @retval None
02193   */
02194 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
02195 {
02196   /* Prevent unused argument(s) compilation warning */
02197   UNUSED(hirda);
02198
02199   /* NOTE : This function should not be modified, when the callback is needed,
02200             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
02201    */
02202 }
02203
02204 /**
02205   * @brief  IRDA error callback.
02206   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02207   *               the configuration information for the specified IRDA module.
02208   * @retval None
02209   */
02210 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
02211 {
02212   /* Prevent unused argument(s) compilation warning */
02213   UNUSED(hirda);
02214
02215   /* NOTE : This function should not be modified, when the callback is needed,
02216             the HAL_IRDA_ErrorCallback can be implemented in the user file.
02217    */
02218 }
02219
02220 /**
02221   * @brief  IRDA Abort Complete callback.
02222   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02223   *               the configuration information for the specified IRDA module.
02224   * @retval None
02225   */
02226 __weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
02227 {
02228   /* Prevent unused argument(s) compilation warning */
02229   UNUSED(hirda);
02230
02231   /* NOTE : This function should not be modified, when the callback is needed,
02232             the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
02233    */
02234 }
02235
02236 /**
02237   * @brief  IRDA Abort Complete callback.
02238   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02239   *               the configuration information for the specified IRDA module.
02240   * @retval None
02241   */
02242 __weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
02243 {
02244   /* Prevent unused argument(s) compilation warning */
02245   UNUSED(hirda);
02246
02247   /* NOTE : This function should not be modified, when the callback is needed,
02248             the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
02249    */
02250 }
02251
02252 /**
02253   * @brief  IRDA Abort Receive Complete callback.
02254   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02255   *               the configuration information for the specified IRDA module.
02256   * @retval None
02257   */
02258 __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
02259 {
02260   /* Prevent unused argument(s) compilation warning */
02261   UNUSED(hirda);
02262
02263   /* NOTE : This function should not be modified, when the callback is needed,
02264             the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
02265    */
02266 }
02267
02268 /**
02269   * @}
02270   */
02271
02272 /** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
02273   *  @brief   IRDA State and Errors functions
02274   *
02275 @verbatim
02276   ==============================================================================
02277             ##### Peripheral State and Error functions #####
02278   ==============================================================================
02279   [..]
02280     This subsection provides a set of functions allowing to return the State of IrDA
02281     communication process and also return Peripheral Errors occurred during communication process
02282      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
02283          of the IRDA peripheral handle.
02284      (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
02285          communication.
02286
02287 @endverbatim
02288   * @{
02289   */
02290
02291 /**
02292   * @brief Return the IRDA handle state.
02293   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02294   *                the configuration information for the specified IRDA module.
02295   * @retval HAL state
02296   */
02297 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
02298 {
02299   /* Return IRDA handle state */
02300   uint32_t temp1;
02301   uint32_t temp2;
02302   temp1 = (uint32_t)hirda->gState;
02303   temp2 = (uint32_t)hirda->RxState;
02304
02305   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
02306 }
02307
02308 /**
02309   * @brief Return the IRDA handle error code.
02310   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02311   *               the configuration information for the specified IRDA module.
02312   * @retval IRDA Error Code
02313   */
02314 uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
02315 {
02316   return hirda->ErrorCode;
02317 }
02318
02319 /**
02320   * @}
02321   */
02322
02323 /**
02324   * @}
02325   */
02326
02327 /** @defgroup IRDA_Private_Functions IRDA Private Functions
02328   * @{
02329   */
02330
02331 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02332 /**
02333   * @brief  Initialize the callbacks to their default values.
02334   * @param  hirda IRDA handle.
02335   * @retval none
02336   */
02337 void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
02338 {
02339   /* Init the IRDA Callback settings */
02340   hirda->TxHalfCpltCallback        = HAL_IRDA_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02341   hirda->TxCpltCallback            = HAL_IRDA_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02342   hirda->RxHalfCpltCallback        = HAL_IRDA_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02343   hirda->RxCpltCallback            = HAL_IRDA_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02344   hirda->ErrorCallback             = HAL_IRDA_ErrorCallback;             /* Legacy weak ErrorCallback             */
02345   hirda->AbortCpltCallback         = HAL_IRDA_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02346   hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02347   hirda->AbortReceiveCpltCallback  = HAL_IRDA_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02348
02349 }
02350 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02351
02352 /**
02353   * @brief Configure the IRDA peripheral.
02354   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02355   *               the configuration information for the specified IRDA module.
02356   * @retval HAL status
02357   */
02358 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
02359 {
02360   uint32_t tmpreg;
02361   IRDA_ClockSourceTypeDef clocksource;
02362   HAL_StatusTypeDef ret = HAL_OK;
02363   static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
02364   uint32_t pclk;
02365
02366   /* Check the communication parameters */
02367   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
02368   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
02369   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
02370   assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
02371   assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
02372   assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
02373   assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler));
02374
02375   /*-------------------------- USART CR1 Configuration -----------------------*/
02376   /* Configure the IRDA Word Length, Parity and transfer Mode:
02377      Set the M bits according to hirda->Init.WordLength value
02378      Set PCE and PS bits according to hirda->Init.Parity value
02379      Set TE and RE bits according to hirda->Init.Mode value */
02380   tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
02381
02382   MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
02383
02384   /*-------------------------- USART CR3 Configuration -----------------------*/
02385   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
02386
02387   /*--------------------- USART clock PRESC Configuration ----------------*/
02388   /* Configure
02389   * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */
02390   MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
02391
02392   /*-------------------------- USART GTPR Configuration ----------------------*/
02393   MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
02394
02395   /*-------------------------- USART BRR Configuration -----------------------*/
02396   IRDA_GETCLOCKSOURCE(hirda, clocksource);
02397   tmpreg =   0U;
02398   switch (clocksource)
02399   {
02400     case IRDA_CLOCKSOURCE_PCLK1:
02401       pclk = HAL_RCC_GetPCLK1Freq();
02402       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02403       break;
02404     case IRDA_CLOCKSOURCE_HSI:
02405       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02406       break;
02407     case IRDA_CLOCKSOURCE_SYSCLK:
02408       pclk = HAL_RCC_GetSysClockFreq();
02409       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02410       break;
02411     case IRDA_CLOCKSOURCE_LSE:
02412       tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02413       break;
02414     default:
02415       ret = HAL_ERROR;
02416       break;
02417   }
02418
02419   /* USARTDIV must be greater than or equal to 0d16 */
02420   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
02421   {
02422     hirda->Instance->BRR = (uint16_t)tmpreg;
02423   }
02424   else
02425   {
02426     ret = HAL_ERROR;
02427   }
02428
02429   return ret;
02430 }
02431
02432 /**
02433   * @brief Check the IRDA Idle State.
02434   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02435   *               the configuration information for the specified IRDA module.
02436   * @retval HAL status
02437   */
02438 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
02439 {
02440   uint32_t tickstart;
02441
02442   /* Initialize the IRDA ErrorCode */
02443   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02444
02445   /* Init tickstart for timeout management */
02446   tickstart = HAL_GetTick();
02447
02448   /* Check if the Transmitter is enabled */
02449   if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02450   {
02451     /* Wait until TEACK flag is set */
02452     if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
02453     {
02454       /* Timeout occurred */
02455       return HAL_TIMEOUT;
02456     }
02457   }
02458   /* Check if the Receiver is enabled */
02459   if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02460   {
02461     /* Wait until REACK flag is set */
02462     if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
02463     {
02464       /* Timeout occurred */
02465       return HAL_TIMEOUT;
02466     }
02467   }
02468
02469   /* Initialize the IRDA state*/
02470   hirda->gState  = HAL_IRDA_STATE_READY;
02471   hirda->RxState = HAL_IRDA_STATE_READY;
02472
02473   /* Process Unlocked */
02474   __HAL_UNLOCK(hirda);
02475
02476   return HAL_OK;
02477 }
02478
02479 /**
02480   * @brief  Handle IRDA Communication Timeout. It waits
02481   *         until a flag is no longer in the specified status.
02482   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02483   *               the configuration information for the specified IRDA module.
02484   * @param  Flag Specifies the IRDA flag to check.
02485   * @param  Status The actual Flag status (SET or RESET)
02486   * @param  Tickstart Tick start value
02487   * @param  Timeout Timeout duration
02488   * @retval HAL status
02489   */
02490 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
02491                                                      uint32_t Tickstart, uint32_t Timeout)
02492 {
02493   /* Wait until flag is set */
02494   while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
02495   {
02496     /* Check for the Timeout */
02497     if (Timeout != HAL_MAX_DELAY)
02498     {
02499       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02500       {
02501         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
02502            interrupts for the interrupt process */
02503         CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
02504         CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02505
02506         hirda->gState  = HAL_IRDA_STATE_READY;
02507         hirda->RxState = HAL_IRDA_STATE_READY;
02508
02509         /* Process Unlocked */
02510         __HAL_UNLOCK(hirda);
02511         return HAL_TIMEOUT;
02512       }
02513     }
02514   }
02515   return HAL_OK;
02516 }
02517
02518
02519 /**
02520   * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
02521   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02522   *               the configuration information for the specified IRDA module.
02523   * @retval None
02524   */
02525 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
02526 {
02527   /* Disable TXEIE and TCIE interrupts */
02528   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02529
02530   /* At end of Tx process, restore hirda->gState to Ready */
02531   hirda->gState = HAL_IRDA_STATE_READY;
02532 }
02533
02534
02535 /**
02536   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02537   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02538   *               the configuration information for the specified IRDA module.
02539   * @retval None
02540   */
02541 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
02542 {
02543   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02544   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02545   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02546
02547   /* At end of Rx process, restore hirda->RxState to Ready */
02548   hirda->RxState = HAL_IRDA_STATE_READY;
02549 }
02550
02551
02552 /**
02553   * @brief  DMA IRDA transmit process complete callback.
02554   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02555   *              the configuration information for the specified DMA module.
02556   * @retval None
02557   */
02558 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02559 {
02560   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02561
02562   /* DMA Normal mode */
02563   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02564   {
02565     hirda->TxXferCount = 0U;
02566
02567     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02568        in the IRDA CR3 register */
02569     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
02570
02571     /* Enable the IRDA Transmit Complete Interrupt */
02572     SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02573   }
02574   /* DMA Circular mode */
02575   else
02576   {
02577 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02578     /* Call registered Tx complete callback */
02579     hirda->TxCpltCallback(hirda);
02580 #else
02581     /* Call legacy weak Tx complete callback */
02582     HAL_IRDA_TxCpltCallback(hirda);
02583 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02584   }
02585
02586 }
02587
02588 /**
02589   * @brief  DMA IRDA transmit process half complete callback.
02590   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02591   *              the configuration information for the specified DMA module.
02592   * @retval None
02593   */
02594 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
02595 {
02596   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02597
02598 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02599   /* Call registered Tx Half complete callback */
02600   hirda->TxHalfCpltCallback(hirda);
02601 #else
02602   /* Call legacy weak Tx complete callback */
02603   HAL_IRDA_TxHalfCpltCallback(hirda);
02604 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02605 }
02606
02607 /**
02608   * @brief  DMA IRDA receive process complete callback.
02609   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02610   *               the configuration information for the specified DMA module.
02611   * @retval None
02612   */
02613 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02614 {
02615   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02616
02617   /* DMA Normal mode */
02618   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02619   {
02620     hirda->RxXferCount = 0U;
02621
02622     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02623     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
02624     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02625
02626     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02627        in the IRDA CR3 register */
02628     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
02629
02630     /* At end of Rx process, restore hirda->RxState to Ready */
02631     hirda->RxState = HAL_IRDA_STATE_READY;
02632   }
02633
02634 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02635   /* Call registered Rx complete callback */
02636   hirda->RxCpltCallback(hirda);
02637 #else
02638   /* Call legacy weak Rx complete callback */
02639   HAL_IRDA_RxCpltCallback(hirda);
02640 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02641 }
02642
02643 /**
02644   * @brief DMA IRDA receive process half complete callback.
02645   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
02646   *              the configuration information for the specified DMA module.
02647   * @retval None
02648   */
02649 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
02650 {
02651   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02652
02653 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02654   /*Call registered Rx Half complete callback*/
02655   hirda->RxHalfCpltCallback(hirda);
02656 #else
02657   /* Call legacy weak Rx Half complete callback */
02658   HAL_IRDA_RxHalfCpltCallback(hirda);
02659 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02660 }
02661
02662 /**
02663   * @brief DMA IRDA communication error callback.
02664   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
02665   *              the configuration information for the specified DMA module.
02666   * @retval None
02667   */
02668 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
02669 {
02670   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02671
02672   /* Stop IRDA DMA Tx request if ongoing */
02673   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02674   {
02675     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
02676     {
02677       hirda->TxXferCount = 0U;
02678       IRDA_EndTxTransfer(hirda);
02679     }
02680   }
02681
02682   /* Stop IRDA DMA Rx request if ongoing */
02683   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02684   {
02685     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
02686     {
02687       hirda->RxXferCount = 0U;
02688       IRDA_EndRxTransfer(hirda);
02689     }
02690   }
02691
02692   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
02693 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02694   /* Call registered user error callback */
02695   hirda->ErrorCallback(hirda);
02696 #else
02697   /* Call legacy weak user error callback */
02698   HAL_IRDA_ErrorCallback(hirda);
02699 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02700 }
02701
02702 /**
02703   * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
02704   *         (To be called at end of DMA Abort procedure following error occurrence).
02705   * @param  hdma DMA handle.
02706   * @retval None
02707   */
02708 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02709 {
02710   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02711   hirda->RxXferCount = 0U;
02712   hirda->TxXferCount = 0U;
02713
02714 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02715   /* Call registered user error callback */
02716   hirda->ErrorCallback(hirda);
02717 #else
02718   /* Call legacy weak user error callback */
02719   HAL_IRDA_ErrorCallback(hirda);
02720 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02721 }
02722
02723 /**
02724   * @brief  DMA IRDA Tx communication abort callback, when initiated by user
02725   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02726   * @note   When this callback is executed, User Abort complete call back is called only if no
02727   *         Abort still ongoing for Rx DMA Handle.
02728   * @param  hdma DMA handle.
02729   * @retval None
02730   */
02731 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02732 {
02733   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02734
02735   hirda->hdmatx->XferAbortCallback = NULL;
02736
02737   /* Check if an Abort process is still ongoing */
02738   if (hirda->hdmarx != NULL)
02739   {
02740     if (hirda->hdmarx->XferAbortCallback != NULL)
02741     {
02742       return;
02743     }
02744   }
02745
02746   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02747   hirda->TxXferCount = 0U;
02748   hirda->RxXferCount = 0U;
02749
02750   /* Reset errorCode */
02751   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02752
02753   /* Clear the Error flags in the ICR register */
02754   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02755
02756   /* Restore hirda->gState and hirda->RxState to Ready */
02757   hirda->gState  = HAL_IRDA_STATE_READY;
02758   hirda->RxState = HAL_IRDA_STATE_READY;
02759
02760   /* Call user Abort complete callback */
02761 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02762   /* Call registered Abort complete callback */
02763   hirda->AbortCpltCallback(hirda);
02764 #else
02765   /* Call legacy weak Abort complete callback */
02766   HAL_IRDA_AbortCpltCallback(hirda);
02767 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02768 }
02769
02770
02771 /**
02772   * @brief  DMA IRDA Rx communication abort callback, when initiated by user
02773   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02774   * @note   When this callback is executed, User Abort complete call back is called only if no
02775   *         Abort still ongoing for Tx DMA Handle.
02776   * @param  hdma DMA handle.
02777   * @retval None
02778   */
02779 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02780 {
02781   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02782
02783   hirda->hdmarx->XferAbortCallback = NULL;
02784
02785   /* Check if an Abort process is still ongoing */
02786   if (hirda->hdmatx != NULL)
02787   {
02788     if (hirda->hdmatx->XferAbortCallback != NULL)
02789     {
02790       return;
02791     }
02792   }
02793
02794   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02795   hirda->TxXferCount = 0U;
02796   hirda->RxXferCount = 0U;
02797
02798   /* Reset errorCode */
02799   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02800
02801   /* Clear the Error flags in the ICR register */
02802   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02803
02804   /* Restore hirda->gState and hirda->RxState to Ready */
02805   hirda->gState  = HAL_IRDA_STATE_READY;
02806   hirda->RxState = HAL_IRDA_STATE_READY;
02807
02808   /* Call user Abort complete callback */
02809 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02810   /* Call registered Abort complete callback */
02811   hirda->AbortCpltCallback(hirda);
02812 #else
02813   /* Call legacy weak Abort complete callback */
02814   HAL_IRDA_AbortCpltCallback(hirda);
02815 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02816 }
02817
02818
02819 /**
02820   * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
02821   *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
02822   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02823   *         and leads to user Tx Abort Complete callback execution).
02824   * @param  hdma DMA handle.
02825   * @retval None
02826   */
02827 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02828 {
02829   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02830
02831   hirda->TxXferCount = 0U;
02832
02833   /* Restore hirda->gState to Ready */
02834   hirda->gState = HAL_IRDA_STATE_READY;
02835
02836   /* Call user Abort complete callback */
02837 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02838   /* Call registered Abort Transmit Complete Callback */
02839   hirda->AbortTransmitCpltCallback(hirda);
02840 #else
02841   /* Call legacy weak Abort Transmit Complete Callback */
02842   HAL_IRDA_AbortTransmitCpltCallback(hirda);
02843 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02844 }
02845
02846 /**
02847   * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
02848   *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
02849   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02850   *         and leads to user Rx Abort Complete callback execution).
02851   * @param  hdma DMA handle.
02852   * @retval None
02853   */
02854 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02855 {
02856   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02857
02858   hirda->RxXferCount = 0U;
02859
02860   /* Clear the Error flags in the ICR register */
02861   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02862
02863   /* Restore hirda->RxState to Ready */
02864   hirda->RxState = HAL_IRDA_STATE_READY;
02865
02866   /* Call user Abort complete callback */
02867 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02868   /* Call registered Abort Receive Complete Callback */
02869   hirda->AbortReceiveCpltCallback(hirda);
02870 #else
02871   /* Call legacy weak Abort Receive Complete Callback */
02872   HAL_IRDA_AbortReceiveCpltCallback(hirda);
02873 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02874 }
02875
02876 /**
02877   * @brief  Send an amount of data in interrupt mode.
02878   * @note   Function is called under interruption only, once
02879   *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
02880   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02881   *               the configuration information for the specified IRDA module.
02882   * @retval None
02883   */
02884 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
02885 {
02886   const uint16_t *tmp;
02887
02888   /* Check that a Tx process is ongoing */
02889   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02890   {
02891     if (hirda->TxXferCount == 0U)
02892     {
02893       /* Disable the IRDA Transmit Data Register Empty Interrupt */
02894       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02895
02896       /* Enable the IRDA Transmit Complete Interrupt */
02897       SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02898     }
02899     else
02900     {
02901       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02902       {
02903         tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
02904         hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
02905         hirda->pTxBuffPtr += 2U;
02906       }
02907       else
02908       {
02909         hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
02910         hirda->pTxBuffPtr++;
02911       }
02912       hirda->TxXferCount--;
02913     }
02914   }
02915 }
02916
02917 /**
02918   * @brief  Wrap up transmission in non-blocking mode.
02919   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02920   *               the configuration information for the specified IRDA module.
02921   * @retval None
02922   */
02923 static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
02924 {
02925   /* Disable the IRDA Transmit Complete Interrupt */
02926   CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02927
02928   /* Tx process is ended, restore hirda->gState to Ready */
02929   hirda->gState = HAL_IRDA_STATE_READY;
02930
02931 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02932   /* Call registered Tx complete callback */
02933   hirda->TxCpltCallback(hirda);
02934 #else
02935   /* Call legacy weak Tx complete callback */
02936   HAL_IRDA_TxCpltCallback(hirda);
02937 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02938 }
02939
02940 /**
02941   * @brief  Receive an amount of data in interrupt mode.
02942   * @note   Function is called under interruption only, once
02943   *         interruptions have been enabled by HAL_IRDA_Receive_IT()
02944   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02945   *               the configuration information for the specified IRDA module.
02946   * @retval None
02947   */
02948 static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
02949 {
02950   uint16_t *tmp;
02951   uint16_t  uhMask = hirda->Mask;
02952   uint16_t  uhdata;
02953
02954   /* Check that a Rx process is ongoing */
02955   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02956   {
02957     uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
02958     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02959     {
02960       tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
02961       *tmp = (uint16_t)(uhdata & uhMask);
02962       hirda->pRxBuffPtr  += 2U;
02963     }
02964     else
02965     {
02966       *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
02967       hirda->pRxBuffPtr++;
02968     }
02969
02970     hirda->RxXferCount--;
02971     if (hirda->RxXferCount == 0U)
02972     {
02973       /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
02974       CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02975
02976       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
02977       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02978
02979       /* Rx process is completed, restore hirda->RxState to Ready */
02980       hirda->RxState = HAL_IRDA_STATE_READY;
02981
02982 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02983       /* Call registered Rx complete callback */
02984       hirda->RxCpltCallback(hirda);
02985 #else
02986       /* Call legacy weak Rx complete callback */
02987       HAL_IRDA_RxCpltCallback(hirda);
02988 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02989     }
02990   }
02991   else
02992   {
02993     /* Clear RXNE interrupt flag */
02994     __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
02995   }
02996 }
02997
02998 /**
02999   * @}
03000   */
03001
03002 #endif /* HAL_IRDA_MODULE_ENABLED */
03003 /**
03004   * @}
03005   */
03006
03007 /**
03008   * @}
03009   */
03010
03011
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_irda.h Source File

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stm32g0xx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_IRDA_H
00021 #define STM32G0xx_HAL_IRDA_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup IRDA
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief IRDA Init Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00049                                            The baud rate register is computed using the following formula:
00050                                               Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
00051                                            where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
00052
00053   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00054                                            This parameter can be a value of @ref IRDAEx_Word_Length */
00055
00056   uint32_t Parity;                    /*!< Specifies the parity mode.
00057                                            This parameter can be a value of @ref IRDA_Parity
00058                                            @note When parity is enabled, the computed parity is inserted
00059                                                  at the MSB position of the transmitted data (9th bit when
00060                                                  the word length is set to 9 data bits; 8th bit when the
00061                                                  word length is set to 8 data bits). */
00062
00063   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00064                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00065
00066   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
00067                                            to achieve low-power frequency.
00068                                            @note Prescaler value 0 is forbidden */
00069
00070   uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
00071                                            This parameter can be a value of @ref IRDA_Low_Power */
00072
00073   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the IRDA clock source.
00074                                            This parameter can be a value of @ref IRDA_ClockPrescaler. */
00075
00076 } IRDA_InitTypeDef;
00077
00078 /**
00079   * @brief HAL IRDA State definition
00080   * @note  HAL IRDA State value is a combination of 2 different substates:
00081   *        gState and RxState (see @ref IRDA_State_Definition).
00082   *        - gState contains IRDA state information related to global Handle management
00083   *          and also information related to Tx operations.
00084   *          gState value coding follow below described bitmap :
00085   *          b7-b6  Error information
00086   *             00 : No Error
00087   *             01 : (Not Used)
00088   *             10 : Timeout
00089   *             11 : Error
00090   *          b5     Peripheral initialization status
00091   *             0  : Reset (Peripheral not initialized)
00092   *             1  : Init done (Peripheral initialized. HAL IRDA Init function already called)
00093   *          b4-b3  (not used)
00094   *             xx : Should be set to 00
00095   *          b2     Intrinsic process state
00096   *             0  : Ready
00097   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00098   *          b1     (not used)
00099   *             x  : Should be set to 0
00100   *          b0     Tx state
00101   *             0  : Ready (no Tx operation ongoing)
00102   *             1  : Busy (Tx operation ongoing)
00103   *        - RxState contains information related to Rx operations.
00104   *          RxState value coding follow below described bitmap :
00105   *          b7-b6  (not used)
00106   *             xx : Should be set to 00
00107   *          b5     Peripheral initialization status
00108   *             0  : Reset (Peripheral not initialized)
00109   *             1  : Init done (Peripheral initialized)
00110   *          b4-b2  (not used)
00111   *            xxx : Should be set to 000
00112   *          b1     Rx state
00113   *             0  : Ready (no Rx operation ongoing)
00114   *             1  : Busy (Rx operation ongoing)
00115   *          b0     (not used)
00116   *             x  : Should be set to 0.
00117   */
00118 typedef uint32_t HAL_IRDA_StateTypeDef;
00119
00120 /**
00121   * @brief IRDA clock sources definition
00122   */
00123 typedef enum
00124 {
00125   IRDA_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source         */
00126   IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source           */
00127   IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source        */
00128   IRDA_CLOCKSOURCE_LSE        = 0x10U,    /*!< LSE clock source           */
00129   IRDA_CLOCKSOURCE_UNDEFINED  = 0x20U     /*!< Undefined clock source     */
00130 } IRDA_ClockSourceTypeDef;
00131
00132 /**
00133   * @brief  IRDA handle Structure definition
00134   */
00135 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00136 typedef struct __IRDA_HandleTypeDef
00137 #else
00138 typedef struct
00139 #endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00140 {
00141   USART_TypeDef            *Instance;        /*!< USART registers base address       */
00142
00143   IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
00144
00145   const uint8_t            *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
00146
00147   uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
00148
00149   __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
00150
00151   uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
00152
00153   uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
00154
00155   __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
00156
00157   uint16_t                 Mask;             /*!< USART RX RDR register mask         */
00158
00159   DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
00160
00161   DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
00162
00163   HAL_LockTypeDef          Lock;             /*!< Locking object                     */
00164
00165   __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
00166                                                   and also related to Tx operations.
00167                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00168
00169   __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
00170                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00171
00172   __IO uint32_t            ErrorCode;        /*!< IRDA Error code                    */
00173
00174 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00175   void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
00176
00177   void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
00178
00179   void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
00180
00181   void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
00182
00183   void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
00184
00185   void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
00186
00187   void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
00188
00189   void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
00190
00191
00192   void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
00193
00194   void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
00195 #endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00196
00197 } IRDA_HandleTypeDef;
00198
00199 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00200 /**
00201   * @brief  HAL IRDA Callback ID enumeration definition
00202   */
00203 typedef enum
00204 {
00205   HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
00206   HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
00207   HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
00208   HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
00209   HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
00210   HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
00211   HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
00212   HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
00213
00214   HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
00215   HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
00216
00217 } HAL_IRDA_CallbackIDTypeDef;
00218
00219 /**
00220   * @brief  HAL IRDA Callback pointer definition
00221   */
00222 typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
00223
00224 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /* Exported constants --------------------------------------------------------*/
00231 /** @defgroup IRDA_Exported_Constants IRDA Exported Constants
00232   * @{
00233   */
00234
00235 /** @defgroup IRDA_State_Definition IRDA State Code Definition
00236   * @{
00237   */
00238 #define HAL_IRDA_STATE_RESET                0x00000000U   /*!< Peripheral is not initialized
00239                                                                Value is allowed for gState and RxState */
00240 #define HAL_IRDA_STATE_READY                0x00000020U   /*!< Peripheral Initialized and ready for use
00241                                                                Value is allowed for gState and RxState */
00242 #define HAL_IRDA_STATE_BUSY                 0x00000024U   /*!< An internal process is ongoing
00243                                                                Value is allowed for gState only */
00244 #define HAL_IRDA_STATE_BUSY_TX              0x00000021U   /*!< Data Transmission process is ongoing
00245                                                                Value is allowed for gState only */
00246 #define HAL_IRDA_STATE_BUSY_RX              0x00000022U   /*!< Data Reception process is ongoing
00247                                                                Value is allowed for RxState only */
00248 #define HAL_IRDA_STATE_BUSY_TX_RX           0x00000023U   /*!< Data Transmission and Reception process is ongoing
00249                                                                Not to be used for neither gState nor RxState.
00250                                                                Value is result of combination (Or) between
00251                                                                gState and RxState values */
00252 #define HAL_IRDA_STATE_TIMEOUT              0x000000A0U   /*!< Timeout state
00253                                                                Value is allowed for gState only */
00254 #define HAL_IRDA_STATE_ERROR                0x000000E0U   /*!< Error
00255                                                                Value is allowed for gState only */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup IRDA_Error_Definition IRDA Error Code Definition
00261   * @{
00262   */
00263 #define HAL_IRDA_ERROR_NONE                 (0x00000000U)          /*!< No error                */
00264 #define HAL_IRDA_ERROR_PE                   (0x00000001U)          /*!< Parity error            */
00265 #define HAL_IRDA_ERROR_NE                   (0x00000002U)          /*!< Noise error             */
00266 #define HAL_IRDA_ERROR_FE                   (0x00000004U)          /*!< frame error             */
00267 #define HAL_IRDA_ERROR_ORE                  (0x00000008U)          /*!< Overrun error           */
00268 #define HAL_IRDA_ERROR_DMA                  (0x00000010U)          /*!< DMA transfer error      */
00269 #define HAL_IRDA_ERROR_BUSY                 (0x00000020U)          /*!< Busy Error              */
00270 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00271 #define HAL_IRDA_ERROR_INVALID_CALLBACK     (0x00000040U)          /*!< Invalid Callback error  */
00272 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup IRDA_Parity IRDA Parity
00278   * @{
00279   */
00280 #define IRDA_PARITY_NONE                    0x00000000U                      /*!< No parity   */
00281 #define IRDA_PARITY_EVEN                    USART_CR1_PCE                    /*!< Even parity */
00282 #define IRDA_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00288   * @{
00289   */
00290 #define IRDA_MODE_RX                        USART_CR1_RE                   /*!< RX mode        */
00291 #define IRDA_MODE_TX                        USART_CR1_TE                   /*!< TX mode        */
00292 #define IRDA_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)   /*!< RX and TX mode */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup IRDA_Low_Power IRDA Low Power
00298   * @{
00299   */
00300 #define IRDA_POWERMODE_NORMAL               0x00000000U       /*!< IRDA normal power mode */
00301 #define IRDA_POWERMODE_LOWPOWER             USART_CR3_IRLP    /*!< IRDA low power mode    */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
00307   * @{
00308   */
00309 #define IRDA_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00310 #define IRDA_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00311 #define IRDA_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00312 #define IRDA_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00313 #define IRDA_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00314 #define IRDA_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00315 #define IRDA_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00316 #define IRDA_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00317 #define IRDA_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00318 #define IRDA_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00319 #define IRDA_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00320 #define IRDA_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup IRDA_State IRDA State
00326   * @{
00327   */
00328 #define IRDA_STATE_DISABLE                  0x00000000U     /*!< IRDA disabled  */
00329 #define IRDA_STATE_ENABLE                   USART_CR1_UE    /*!< IRDA enabled   */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup IRDA_Mode IRDA Mode
00335   * @{
00336   */
00337 #define IRDA_MODE_DISABLE                   0x00000000U      /*!< Associated UART disabled in IRDA mode */
00338 #define IRDA_MODE_ENABLE                    USART_CR3_IREN   /*!< Associated UART enabled in IRDA mode  */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup IRDA_One_Bit IRDA One Bit Sampling
00344   * @{
00345   */
00346 #define IRDA_ONE_BIT_SAMPLE_DISABLE         0x00000000U       /*!< One-bit sampling disabled */
00347 #define IRDA_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT  /*!< One-bit sampling enabled  */
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
00353   * @{
00354   */
00355 #define IRDA_DMA_TX_DISABLE                 0x00000000U       /*!< IRDA DMA TX disabled */
00356 #define IRDA_DMA_TX_ENABLE                  USART_CR3_DMAT    /*!< IRDA DMA TX enabled  */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup IRDA_DMA_Rx IRDA DMA Rx
00362   * @{
00363   */
00364 #define IRDA_DMA_RX_DISABLE                 0x00000000U       /*!< IRDA DMA RX disabled */
00365 #define IRDA_DMA_RX_ENABLE                  USART_CR3_DMAR    /*!< IRDA DMA RX enabled  */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
00371   * @{
00372   */
00373 #define IRDA_AUTOBAUD_REQUEST            USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
00374 #define IRDA_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00375 #define IRDA_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup IRDA_Flags IRDA Flags
00381   *        Elements values convention: 0xXXXX
00382   *           - 0xXXXX  : Flag mask in the ISR register
00383   * @{
00384   */
00385 #define IRDA_FLAG_REACK                     USART_ISR_REACK         /*!< IRDA receive enable acknowledge flag      */
00386 #define IRDA_FLAG_TEACK                     USART_ISR_TEACK         /*!< IRDA transmit enable acknowledge flag     */
00387 #define IRDA_FLAG_BUSY                      USART_ISR_BUSY          /*!< IRDA busy flag                            */
00388 #define IRDA_FLAG_ABRF                      USART_ISR_ABRF          /*!< IRDA auto Baud rate flag                  */
00389 #define IRDA_FLAG_ABRE                      USART_ISR_ABRE          /*!< IRDA auto Baud rate error                 */
00390 #define IRDA_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< IRDA transmit data register empty         */
00391 #define IRDA_FLAG_TC                        USART_ISR_TC            /*!< IRDA transmission complete                */
00392 #define IRDA_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< IRDA read data register not empty         */
00393 #define IRDA_FLAG_ORE                       USART_ISR_ORE           /*!< IRDA overrun error                        */
00394 #define IRDA_FLAG_NE                        USART_ISR_NE            /*!< IRDA noise error                          */
00395 #define IRDA_FLAG_FE                        USART_ISR_FE            /*!< IRDA frame error                          */
00396 #define IRDA_FLAG_PE                        USART_ISR_PE            /*!< IRDA parity error                         */
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
00402   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00403   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00404   *           - XX  : Interrupt source register (2bits)
00405   *                 - 01: CR1 register
00406   *                 - 10: CR2 register
00407   *                 - 11: CR3 register
00408   *           - ZZZZ  : Flag position in the ISR register(4bits)
00409   * @{
00410   */
00411 #define IRDA_IT_PE                          0x0028U     /*!< IRDA Parity error interruption                 */
00412 #define IRDA_IT_TXE                         0x0727U     /*!< IRDA Transmit data register empty interruption */
00413 #define IRDA_IT_TC                          0x0626U     /*!< IRDA Transmission complete interruption        */
00414 #define IRDA_IT_RXNE                        0x0525U     /*!< IRDA Read data register not empty interruption */
00415 #define IRDA_IT_IDLE                        0x0424U     /*!< IRDA Idle interruption                         */
00416
00417 /*       Elements values convention: 000000000XXYYYYYb
00418              - YYYYY  : Interrupt source position in the XX register (5bits)
00419              - XX  : Interrupt source register (2bits)
00420                    - 01: CR1 register
00421                    - 10: CR2 register
00422                    - 11: CR3 register */
00423 #define IRDA_IT_ERR                         0x0060U       /*!< IRDA Error interruption        */
00424
00425 /*       Elements values convention: 0000ZZZZ00000000b
00426              - ZZZZ  : Flag position in the ISR register(4bits) */
00427 #define IRDA_IT_ORE                         0x0300U      /*!< IRDA Overrun error interruption */
00428 #define IRDA_IT_NE                          0x0200U      /*!< IRDA Noise error interruption   */
00429 #define IRDA_IT_FE                          0x0100U      /*!< IRDA Frame error interruption   */
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
00435   * @{
00436   */
00437 #define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00438 #define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00439 #define IRDA_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag  */
00440 #define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00441 #define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00442 #define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00443 /**
00444   * @}
00445   */
00446
00447 /** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
00448   * @{
00449   */
00450 #define IRDA_IT_MASK  0x001FU  /*!< IRDA Interruptions flags mask  */
00451 #define IRDA_CR_MASK  0x00E0U  /*!< IRDA control register mask     */
00452 #define IRDA_CR_POS   5U       /*!< IRDA control register position */
00453 #define IRDA_ISR_MASK 0x1F00U  /*!< IRDA ISR register mask         */
00454 #define IRDA_ISR_POS  8U       /*!< IRDA ISR register position     */
00455 /**
00456   * @}
00457   */
00458
00459 /**
00460   * @}
00461   */
00462
00463 /* Exported macros -----------------------------------------------------------*/
00464 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00465   * @{
00466   */
00467
00468 /** @brief  Reset IRDA handle state.
00469   * @param  __HANDLE__ IRDA handle.
00470   * @retval None
00471   */
00472 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00473 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00474                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00475                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00476                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00477                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00478                                                      } while(0U)
00479 #else
00480 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00481                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00482                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00483                                                      } while(0U)
00484 #endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
00485
00486 /** @brief  Flush the IRDA DR register.
00487   * @param  __HANDLE__ specifies the IRDA Handle.
00488   * @retval None
00489   */
00490 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
00491   do{                                                                    \
00492     SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
00493     SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
00494   } while(0U)
00495
00496 /** @brief  Clear the specified IRDA pending flag.
00497   * @param  __HANDLE__ specifies the IRDA Handle.
00498   * @param  __FLAG__ specifies the flag to check.
00499   *          This parameter can be any combination of the following values:
00500   *            @arg @ref IRDA_CLEAR_PEF
00501   *            @arg @ref IRDA_CLEAR_FEF
00502   *            @arg @ref IRDA_CLEAR_NEF
00503   *            @arg @ref IRDA_CLEAR_OREF
00504   *            @arg @ref IRDA_CLEAR_TCF
00505   *            @arg @ref IRDA_CLEAR_IDLEF
00506   * @retval None
00507   */
00508 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00509
00510 /** @brief  Clear the IRDA PE pending flag.
00511   * @param  __HANDLE__ specifies the IRDA Handle.
00512   * @retval None
00513   */
00514 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
00515
00516
00517 /** @brief  Clear the IRDA FE pending flag.
00518   * @param  __HANDLE__ specifies the IRDA Handle.
00519   * @retval None
00520   */
00521 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
00522
00523 /** @brief  Clear the IRDA NE pending flag.
00524   * @param  __HANDLE__ specifies the IRDA Handle.
00525   * @retval None
00526   */
00527 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
00528
00529 /** @brief  Clear the IRDA ORE pending flag.
00530   * @param  __HANDLE__ specifies the IRDA Handle.
00531   * @retval None
00532   */
00533 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
00534
00535 /** @brief  Clear the IRDA IDLE pending flag.
00536   * @param  __HANDLE__ specifies the IRDA Handle.
00537   * @retval None
00538   */
00539 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
00540
00541 /** @brief  Check whether the specified IRDA flag is set or not.
00542   * @param  __HANDLE__ specifies the IRDA Handle.
00543   * @param  __FLAG__ specifies the flag to check.
00544   *        This parameter can be one of the following values:
00545   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
00546   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
00547   *            @arg @ref IRDA_FLAG_BUSY  Busy flag
00548   *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
00549   *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
00550   *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
00551   *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
00552   *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
00553   *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
00554   *            @arg @ref IRDA_FLAG_NE    Noise Error flag
00555   *            @arg @ref IRDA_FLAG_FE    Framing Error flag
00556   *            @arg @ref IRDA_FLAG_PE    Parity Error flag
00557   * @retval The new state of __FLAG__ (TRUE or FALSE).
00558   */
00559 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00560
00561
00562 /** @brief  Enable the specified IRDA interrupt.
00563   * @param  __HANDLE__ specifies the IRDA Handle.
00564   * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
00565   *          This parameter can be one of the following values:
00566   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00567   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00568   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00569   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00570   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00571   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00572   * @retval None
00573   */
00574 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
00575                                                            ((__HANDLE__)->Instance->CR1 |= (1U << \
00576                                                                ((__INTERRUPT__) & IRDA_IT_MASK))):\
00577                                                            ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
00578                                                            ((__HANDLE__)->Instance->CR2 |= (1U << \
00579                                                                ((__INTERRUPT__) & IRDA_IT_MASK))):\
00580                                                            ((__HANDLE__)->Instance->CR3 |= (1U << \
00581                                                                ((__INTERRUPT__) & IRDA_IT_MASK))))
00582
00583 /** @brief  Disable the specified IRDA interrupt.
00584   * @param  __HANDLE__ specifies the IRDA Handle.
00585   * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
00586   *          This parameter can be one of the following values:
00587   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00588   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00589   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00590   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00591   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00592   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00593   * @retval None
00594   */
00595 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
00596                                                            ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
00597                                                                ((__INTERRUPT__) & IRDA_IT_MASK))): \
00598                                                            ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
00599                                                            ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
00600                                                                ((__INTERRUPT__) & IRDA_IT_MASK))): \
00601                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
00602                                                                ((__INTERRUPT__) & IRDA_IT_MASK))))
00603
00604 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00605   * @param  __HANDLE__ specifies the IRDA Handle.
00606   * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
00607   *          This parameter can be one of the following values:
00608   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00609   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00610   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00611   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00612   *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
00613   *            @arg @ref IRDA_IT_NE Noise Error interrupt
00614   *            @arg @ref IRDA_IT_FE Framing Error interrupt
00615   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00616   * @retval The new state of __IT__ (SET or RESET).
00617   */
00618 #define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
00619   ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
00620
00621 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
00622   * @param  __HANDLE__ specifies the IRDA Handle.
00623   * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
00624   *          This parameter can be one of the following values:
00625   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00626   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00627   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00628   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00629   *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
00630   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00631   * @retval The new state of __IT__ (SET or RESET).
00632   */
00633 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                                                          \
00634   ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__)  \
00635       & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3))           \
00636      & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
00637
00638 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
00639   * @param  __HANDLE__ specifies the IRDA Handle.
00640   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00641   *                       to clear the corresponding interrupt
00642   *          This parameter can be one of the following values:
00643   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
00644   *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
00645   *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
00646   *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
00647   *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
00648   * @retval None
00649   */
00650 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00651
00652
00653 /** @brief  Set a specific IRDA request flag.
00654   * @param  __HANDLE__ specifies the IRDA Handle.
00655   * @param  __REQ__ specifies the request flag to set
00656   *          This parameter can be one of the following values:
00657   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
00658   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
00659   *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
00660   * @retval None
00661   */
00662 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00663
00664 /** @brief  Enable the IRDA one bit sample method.
00665   * @param  __HANDLE__ specifies the IRDA Handle.
00666   * @retval None
00667   */
00668 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00669
00670 /** @brief  Disable the IRDA one bit sample method.
00671   * @param  __HANDLE__ specifies the IRDA Handle.
00672   * @retval None
00673   */
00674 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
00675                                                        &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00676
00677 /** @brief  Enable UART/USART associated to IRDA Handle.
00678   * @param  __HANDLE__ specifies the IRDA Handle.
00679   * @retval None
00680   */
00681 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00682
00683 /** @brief  Disable UART/USART associated to IRDA Handle.
00684   * @param  __HANDLE__ specifies the IRDA Handle.
00685   * @retval None
00686   */
00687 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00688
00689 /**
00690   * @}
00691   */
00692
00693 /* Private macros --------------------------------------------------------*/
00694 /** @addtogroup IRDA_Private_Macros
00695   * @{
00696   */
00697
00698 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
00699   * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
00700   * @retval True or False
00701   */
00702 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
00703
00704 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
00705   * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
00706   * @retval True or False
00707   */
00708 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
00709
00710 /** @brief Ensure that IRDA frame parity is valid.
00711   * @param __PARITY__ IRDA frame parity.
00712   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00713   */
00714 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
00715                                     ((__PARITY__) == IRDA_PARITY_EVEN) || \
00716                                     ((__PARITY__) == IRDA_PARITY_ODD))
00717
00718 /** @brief Ensure that IRDA communication mode is valid.
00719   * @param __MODE__ IRDA communication mode.
00720   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00721   */
00722 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
00723                                         & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
00724
00725 /** @brief Ensure that IRDA power mode is valid.
00726   * @param __MODE__ IRDA power mode.
00727   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00728   */
00729 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
00730                                      ((__MODE__) == IRDA_POWERMODE_NORMAL))
00731
00732 /** @brief Ensure that IRDA clock Prescaler is valid.
00733   * @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
00734   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00735   */
00736 #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
00737                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
00738                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
00739                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
00740                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
00741                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
00742                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
00743                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
00744                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
00745                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
00746                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
00747                                                     ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
00748
00749 /** @brief Ensure that IRDA state is valid.
00750   * @param __STATE__ IRDA state mode.
00751   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00752   */
00753 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
00754                                   ((__STATE__) == IRDA_STATE_ENABLE))
00755
00756 /** @brief Ensure that IRDA associated UART/USART mode is valid.
00757   * @param __MODE__ IRDA associated UART/USART mode.
00758   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00759   */
00760 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
00761                                  ((__MODE__) == IRDA_MODE_ENABLE))
00762
00763 /** @brief Ensure that IRDA sampling rate is valid.
00764   * @param __ONEBIT__ IRDA sampling rate.
00765   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00766   */
00767 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
00768                                                  ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
00769
00770 /** @brief Ensure that IRDA DMA TX mode is valid.
00771   * @param __DMATX__ IRDA DMA TX mode.
00772   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
00773   */
00774 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
00775                                        ((__DMATX__) == IRDA_DMA_TX_ENABLE))
00776
00777 /** @brief Ensure that IRDA DMA RX mode is valid.
00778   * @param __DMARX__ IRDA DMA RX mode.
00779   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
00780   */
00781 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
00782                                    ((__DMARX__) == IRDA_DMA_RX_ENABLE))
00783
00784 /** @brief Ensure that IRDA request is valid.
00785   * @param __PARAM__ IRDA request.
00786   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00787   */
00788 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
00789                                               ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
00790                                               ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
00791 /**
00792   * @}
00793   */
00794
00795 /* Include IRDA HAL Extended module */
00796 #include "stm32g0xx_hal_irda_ex.h"
00797
00798 /* Exported functions --------------------------------------------------------*/
00799 /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
00800   * @{
00801   */
00802
00803 /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00804   * @{
00805   */
00806
00807 /* Initialization and de-initialization functions  ****************************/
00808 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00809 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00810 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00811 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00812
00813 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00814 /* Callbacks Register/UnRegister functions  ***********************************/
00815 HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
00816                                             pIRDA_CallbackTypeDef pCallback);
00817 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
00818 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00819
00820 /**
00821   * @}
00822   */
00823
00824 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
00825   * @{
00826   */
00827
00828 /* IO operation functions *****************************************************/
00829 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
00830 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00831 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
00832 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00833 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
00834 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00835 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00836 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00837 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00838 /* Transfer Abort functions */
00839 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
00840 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
00841 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
00842 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
00843 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
00844 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
00845
00846 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00847 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00848 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00849 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00850 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00851 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00852 void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
00853 void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
00854 void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
00855
00856 /**
00857   * @}
00858   */
00859
00860 /* Peripheral Control functions  ************************************************/
00861
00862 /** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
00863   * @{
00864   */
00865
00866 /* Peripheral State and Error functions ***************************************/
00867 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
00868 uint32_t              HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
00869
00870 /**
00871   * @}
00872   */
00873
00874 /**
00875   * @}
00876   */
00877
00878 /**
00879   * @}
00880   */
00881
00882 /**
00883   * @}
00884   */
00885
00886 #ifdef __cplusplus
00887 }
00888 #endif
00889
00890 #endif /* STM32G0xx_HAL_IRDA_H */
00891
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_irda_ex.h Source File

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stm32g0xx_hal_irda_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_irda_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_IRDA_EX_H
00021 #define STM32G0xx_HAL_IRDA_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup IRDAEx IRDAEx
00035   * @brief IRDA Extended HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup IRDAEx_Word_Length IRDAEx Word Length
00046   * @{
00047   */
00048 #define IRDA_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long frame */
00049 #define IRDA_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long frame */
00050 #define IRDA_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long frame */
00051 /**
00052   * @}
00053   */
00054
00055 /**
00056   * @}
00057   */
00058
00059 /* Exported macros -----------------------------------------------------------*/
00060
00061 /* Private macros ------------------------------------------------------------*/
00062
00063 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
00064   * @{
00065   */
00066
00067 /** @brief  Report the IRDA clock source.
00068   * @param  __HANDLE__ specifies the IRDA Handle.
00069   * @param  __CLOCKSOURCE__ output variable.
00070   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
00071   */
00072 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00073 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00074   do {                                                        \
00075     if((__HANDLE__)->Instance == USART1)                      \
00076     {                                                         \
00077       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00078       {                                                       \
00079         case RCC_USART1CLKSOURCE_PCLK1:                       \
00080           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00081           break;                                              \
00082         case RCC_USART1CLKSOURCE_HSI:                         \
00083           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00084           break;                                              \
00085         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00086           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00087           break;                                              \
00088         case RCC_USART1CLKSOURCE_LSE:                         \
00089           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00090           break;                                              \
00091         default:                                              \
00092           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00093           break;                                              \
00094       }                                                       \
00095     }                                                         \
00096     else if((__HANDLE__)->Instance == USART2)                 \
00097     {                                                         \
00098       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00099       {                                                       \
00100         case RCC_USART2CLKSOURCE_PCLK1:                       \
00101           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00102           break;                                              \
00103         case RCC_USART2CLKSOURCE_HSI:                         \
00104           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00105           break;                                              \
00106         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00107           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00108           break;                                              \
00109         case RCC_USART2CLKSOURCE_LSE:                         \
00110           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00111           break;                                              \
00112         default:                                              \
00113           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00114           break;                                              \
00115       }                                                       \
00116     }                                                         \
00117     else if((__HANDLE__)->Instance == USART3)                 \
00118     {                                                         \
00119       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00120       {                                                       \
00121         case RCC_USART3CLKSOURCE_PCLK1:                       \
00122           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00123           break;                                              \
00124         case RCC_USART3CLKSOURCE_HSI:                         \
00125           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00126           break;                                              \
00127         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00128           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00129           break;                                              \
00130         case RCC_USART3CLKSOURCE_LSE:                         \
00131           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00132           break;                                              \
00133         default:                                              \
00134           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00135           break;                                              \
00136       }                                                       \
00137     }                                                         \
00138     else                                                      \
00139     {                                                         \
00140       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
00141     }                                                         \
00142   } while(0U)
00143 #elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
00144 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00145   do {                                                        \
00146     if((__HANDLE__)->Instance == USART1)                      \
00147     {                                                         \
00148       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00149       {                                                       \
00150         case RCC_USART1CLKSOURCE_PCLK1:                       \
00151           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00152           break;                                              \
00153         case RCC_USART1CLKSOURCE_HSI:                         \
00154           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00155           break;                                              \
00156         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00157           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00158           break;                                              \
00159         case RCC_USART1CLKSOURCE_LSE:                         \
00160           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00161           break;                                              \
00162         default:                                              \
00163           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00164           break;                                              \
00165       }                                                       \
00166     }                                                         \
00167     else if((__HANDLE__)->Instance == USART2)                 \
00168     {                                                         \
00169       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00170       {                                                       \
00171         case RCC_USART2CLKSOURCE_PCLK1:                       \
00172           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00173           break;                                              \
00174         case RCC_USART2CLKSOURCE_HSI:                         \
00175           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00176           break;                                              \
00177         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00178           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00179           break;                                              \
00180         case RCC_USART2CLKSOURCE_LSE:                         \
00181           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00182           break;                                              \
00183         default:                                              \
00184           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00185           break;                                              \
00186       }                                                       \
00187     }                                                         \
00188     else                                                      \
00189     {                                                         \
00190       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
00191     }                                                         \
00192   } while(0U)
00193 #else
00194 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00195   do {                                                        \
00196     if((__HANDLE__)->Instance == USART1)                      \
00197     {                                                         \
00198       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00199       {                                                       \
00200         case RCC_USART1CLKSOURCE_PCLK1:                       \
00201           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00202           break;                                              \
00203         case RCC_USART1CLKSOURCE_HSI:                         \
00204           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00205           break;                                              \
00206         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00207           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00208           break;                                              \
00209         case RCC_USART1CLKSOURCE_LSE:                         \
00210           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00211           break;                                              \
00212         default:                                              \
00213           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00214           break;                                              \
00215       }                                                       \
00216     }                                                         \
00217     else                                                      \
00218     {                                                         \
00219       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
00220     }                                                         \
00221   } while(0U)
00222 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00223
00224 /** @brief  Compute the mask to apply to retrieve the received data
00225   *         according to the word length and to the parity bits activation.
00226   * @param  __HANDLE__ specifies the IRDA Handle.
00227   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
00228   */
00229 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
00230   do {                                                                \
00231     if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)          \
00232     {                                                                 \
00233       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00234       {                                                               \
00235         (__HANDLE__)->Mask = 0x01FFU ;                                \
00236       }                                                               \
00237       else                                                            \
00238       {                                                               \
00239         (__HANDLE__)->Mask = 0x00FFU ;                                \
00240       }                                                               \
00241     }                                                                 \
00242     else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)     \
00243     {                                                                 \
00244       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00245       {                                                               \
00246         (__HANDLE__)->Mask = 0x00FFU ;                                \
00247       }                                                               \
00248       else                                                            \
00249       {                                                               \
00250         (__HANDLE__)->Mask = 0x007FU ;                                \
00251       }                                                               \
00252     }                                                                 \
00253     else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)     \
00254     {                                                                 \
00255       if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
00256       {                                                               \
00257         (__HANDLE__)->Mask = 0x007FU ;                                \
00258       }                                                               \
00259       else                                                            \
00260       {                                                               \
00261         (__HANDLE__)->Mask = 0x003FU ;                                \
00262       }                                                               \
00263     }                                                                 \
00264     else                                                              \
00265     {                                                                 \
00266       (__HANDLE__)->Mask = 0x0000U;                                   \
00267     }                                                                 \
00268   } while(0U)
00269
00270 /** @brief Ensure that IRDA frame length is valid.
00271   * @param __LENGTH__ IRDA frame length.
00272   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00273   */
00274 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
00275                                          ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
00276                                          ((__LENGTH__) == IRDA_WORDLENGTH_9B))
00277 /**
00278   * @}
00279   */
00280
00281 /* Exported functions --------------------------------------------------------*/
00282
00283 /**
00284   * @}
00285   */
00286
00287 /**
00288   * @}
00289   */
00290
00291 #ifdef __cplusplus
00292 }
00293 #endif
00294
00295 #endif /* STM32G0xx_HAL_IRDA_EX_H */
00296
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_iwdg.c Source File

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stm32g0xx_hal_iwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @brief   IWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00008   *           + Initialization and Start functions
00009   *           + IO operation functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2018 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   ==============================================================================
00024                     ##### IWDG Generic features #####
00025   ==============================================================================
00026   [..]
00027     (+) The IWDG can be started by either software or hardware (configurable
00028         through option byte).
00029
00030     (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
00031         active even if the main clock fails.
00032
00033     (+) Once the IWDG is started, the LSI is forced ON and both cannot be
00034         disabled. The counter starts counting down from the reset value (0xFFF).
00035         When it reaches the end of count value (0x000) a reset signal is
00036         generated (IWDG reset).
00037
00038     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
00039         the IWDG_RLR value is reloaded into the counter and the watchdog reset
00040         is prevented.
00041
00042     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00043         in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
00044         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00045         reset occurs.
00046
00047     (+) Debug mode: When the microcontroller enters debug mode (core halted),
00048         the IWDG counter either continues to work normally or stops, depending
00049         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
00050         __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
00051
00052     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00053          The IWDG timeout may vary due to LSI clock frequency dispersion.
00054          STM32G0xx devices provide the capability to measure the LSI clock
00055          frequency (LSI clock is internally connected to TIM16 CH1 input capture).
00056          The measured value can be used to have an IWDG timeout with an
00057          acceptable accuracy.
00058
00059     [..] Default timeout value (necessary for IWDG_SR status register update):
00060          Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
00061          This frequency being subject to variations as mentioned above, the
00062          default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
00063          below) may become too short or too long.
00064          In such cases, this default timeout value can be tuned by redefining
00065          the constant LSI_VALUE at user-application level (based, for instance,
00066          on the measured LSI clock frequency as explained above).
00067
00068                      ##### How to use this driver #####
00069   ==============================================================================
00070   [..]
00071     (#) Use IWDG using HAL_IWDG_Init() function to :
00072       (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
00073            clock is forced ON and IWDG counter starts counting down.
00074       (++) Enable write access to configuration registers:
00075           IWDG_PR, IWDG_RLR and IWDG_WINR.
00076       (++) Configure the IWDG prescaler and counter reload value. This reload
00077            value will be loaded in the IWDG counter each time the watchdog is
00078            reloaded, then the IWDG will start counting down from this value.
00079       (++) Depending on window parameter:
00080         (+++) If Window Init parameter is same as Window register value,
00081              nothing more is done but reload counter value in order to exit
00082              function with exact time base.
00083         (+++) Else modify Window register. This will automatically reload
00084              watchdog counter.
00085       (++) Wait for status flags to be reset.
00086
00087     (#) Then the application program must refresh the IWDG counter at regular
00088         intervals during normal operation to prevent an MCU reset, using
00089         HAL_IWDG_Refresh() function.
00090
00091      *** IWDG HAL driver macros list ***
00092      ====================================
00093      [..]
00094        Below the list of most used macros in IWDG HAL driver:
00095       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00096       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
00097           the reload register
00098
00099   @endverbatim
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32g0xx_hal.h"
00104
00105 /** @addtogroup STM32G0xx_HAL_Driver
00106   * @{
00107   */
00108
00109 #ifdef HAL_IWDG_MODULE_ENABLED
00110 /** @addtogroup IWDG
00111   * @brief IWDG HAL module driver.
00112   * @{
00113   */
00114
00115 /* Private typedef -----------------------------------------------------------*/
00116 /* Private define ------------------------------------------------------------*/
00117 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00118   * @{
00119   */
00120 /* Status register needs up to 5 LSI clock periods divided by the clock
00121    prescaler to be updated. The number of LSI clock periods is upper-rounded to
00122    6 for the timeout value calculation.
00123    The timeout value is calculated using the highest prescaler (256) and
00124    the LSI_VALUE constant. The value of this constant can be changed by the user
00125    to take into account possible LSI clock period variations.
00126    The timeout value is multiplied by 1000 to be converted in milliseconds.
00127    LSI startup time is also considered here by adding LSI_STARTUP_TIME
00128    converted in milliseconds. */
00129 #define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
00130 #define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
00131 /**
00132   * @}
00133   */
00134
00135 /* Private macro -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private function prototypes -----------------------------------------------*/
00138 /* Exported functions --------------------------------------------------------*/
00139
00140 /** @addtogroup IWDG_Exported_Functions
00141   * @{
00142   */
00143
00144 /** @addtogroup IWDG_Exported_Functions_Group1
00145   *  @brief    Initialization and Start functions.
00146   *
00147 @verbatim
00148  ===============================================================================
00149           ##### Initialization and Start functions #####
00150  ===============================================================================
00151  [..]  This section provides functions allowing to:
00152       (+) Initialize the IWDG according to the specified parameters in the
00153           IWDG_InitTypeDef of associated handle.
00154       (+) Manage Window option.
00155       (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
00156           is reloaded in order to exit function with correct time base.
00157
00158 @endverbatim
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  Initialize the IWDG according to the specified parameters in the
00164   *         IWDG_InitTypeDef and start watchdog. Before exiting function,
00165   *         watchdog is refreshed in order to have correct time base.
00166   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00167   *                the configuration information for the specified IWDG module.
00168   * @retval HAL status
00169   */
00170 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00171 {
00172   uint32_t tickstart;
00173
00174   /* Check the IWDG handle allocation */
00175   if (hiwdg == NULL)
00176   {
00177     return HAL_ERROR;
00178   }
00179
00180   /* Check the parameters */
00181   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00182   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00183   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00184   assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
00185
00186   /* Enable IWDG. LSI is turned on automatically */
00187   __HAL_IWDG_START(hiwdg);
00188
00189   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
00190   0x5555 in KR */
00191   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00192
00193   /* Write to IWDG registers the Prescaler & Reload values to work with */
00194   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
00195   hiwdg->Instance->RLR = hiwdg->Init.Reload;
00196
00197   /* Check pending flag, if previous update not done, return timeout */
00198   tickstart = HAL_GetTick();
00199
00200   /* Wait for register to be updated */
00201   while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
00202   {
00203     if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
00204     {
00205       if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
00206       {
00207         return HAL_TIMEOUT;
00208       }
00209     }
00210   }
00211
00212   /* If window parameter is different than current value, modify window
00213   register */
00214   if (hiwdg->Instance->WINR != hiwdg->Init.Window)
00215   {
00216     /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
00217     even if window feature is disabled, Watchdog will be reloaded by writing
00218     windows register */
00219     hiwdg->Instance->WINR = hiwdg->Init.Window;
00220   }
00221   else
00222   {
00223     /* Reload IWDG counter with value defined in the reload register */
00224     __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00225   }
00226
00227   /* Return function status */
00228   return HAL_OK;
00229 }
00230
00231
00232 /**
00233   * @}
00234   */
00235
00236
00237 /** @addtogroup IWDG_Exported_Functions_Group2
00238   *  @brief   IO operation functions
00239   *
00240 @verbatim
00241  ===============================================================================
00242                       ##### IO operation functions #####
00243  ===============================================================================
00244  [..]  This section provides functions allowing to:
00245       (+) Refresh the IWDG.
00246
00247 @endverbatim
00248   * @{
00249   */
00250
00251 /**
00252   * @brief  Refresh the IWDG.
00253   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00254   *                the configuration information for the specified IWDG module.
00255   * @retval HAL status
00256   */
00257 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00258 {
00259   /* Reload IWDG counter with value defined in the reload register */
00260   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00261
00262   /* Return function status */
00263   return HAL_OK;
00264 }
00265
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 #endif /* HAL_IWDG_MODULE_ENABLED */
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_iwdg.h Source File

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stm32g0xx_hal_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_IWDG_H
00021 #define STM32G0xx_HAL_IWDG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup IWDG IWDG
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  IWDG Init structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00049                             This parameter can be a value of @ref IWDG_Prescaler */
00050
00051   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00052                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00053
00054   uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
00055                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00056
00057 } IWDG_InitTypeDef;
00058
00059 /**
00060   * @brief  IWDG Handle Structure definition
00061   */
00062 typedef struct
00063 {
00064   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00065
00066   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00067 } IWDG_HandleTypeDef;
00068
00069
00070 /**
00071   * @}
00072   */
00073
00074 /* Exported constants --------------------------------------------------------*/
00075 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00076   * @{
00077   */
00078
00079 /** @defgroup IWDG_Prescaler IWDG Prescaler
00080   * @{
00081   */
00082 #define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
00083 #define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
00084 #define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
00085 #define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
00086 #define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
00087 #define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
00088 #define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup IWDG_Window_option IWDG Window option
00094   * @{
00095   */
00096 #define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /* Exported macros -----------------------------------------------------------*/
00106 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00107   * @{
00108   */
00109
00110 /**
00111   * @brief  Enable the IWDG peripheral.
00112   * @param  __HANDLE__  IWDG handle
00113   * @retval None
00114   */
00115 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00116
00117 /**
00118   * @brief  Reload IWDG counter with value defined in the reload register
00119   *         (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
00120   * @param  __HANDLE__  IWDG handle
00121   * @retval None
00122   */
00123 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00124
00125 /**
00126   * @}
00127   */
00128
00129 /* Exported functions --------------------------------------------------------*/
00130 /** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
00131   * @{
00132   */
00133
00134 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
00135   * @{
00136   */
00137 /* Initialization/Start functions  ********************************************/
00138 HAL_StatusTypeDef     HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00144   * @{
00145   */
00146 /* I/O operation functions ****************************************************/
00147 HAL_StatusTypeDef     HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00148 /**
00149   * @}
00150   */
00151
00152 /**
00153   * @}
00154   */
00155
00156 /* Private constants ---------------------------------------------------------*/
00157 /** @defgroup IWDG_Private_Constants IWDG Private Constants
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  IWDG Key Register BitMask
00163   */
00164 #define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
00165 #define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
00166 #define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
00167 #define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /* Private macros ------------------------------------------------------------*/
00174 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00175   * @{
00176   */
00177
00178 /**
00179   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00180   * @param  __HANDLE__  IWDG handle
00181   * @retval None
00182   */
00183 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00184
00185 /**
00186   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00187   * @param  __HANDLE__  IWDG handle
00188   * @retval None
00189   */
00190 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00191
00192 /**
00193   * @brief  Check IWDG prescaler value.
00194   * @param  __PRESCALER__  IWDG prescaler value
00195   * @retval None
00196   */
00197 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00198                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00199                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00200                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00201                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00202                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00203                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00204
00205 /**
00206   * @brief  Check IWDG reload value.
00207   * @param  __RELOAD__  IWDG reload value
00208   * @retval None
00209   */
00210 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
00211
00212 /**
00213   * @brief  Check IWDG window value.
00214   * @param  __WINDOW__  IWDG window value
00215   * @retval None
00216   */
00217 #define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
00218
00219
00220 /**
00221   * @}
00222   */
00223
00224 /**
00225   * @}
00226   */
00227
00228 /**
00229   * @}
00230   */
00231
00232
00233 #ifdef __cplusplus
00234 }
00235 #endif
00236
00237 #endif /* STM32G0xx_HAL_IWDG_H */
Generated on Mon Jun 6 2022 10:29:01 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_lptim.c Source File

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stm32g0xx_hal_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_lptim.c
00004   * @author  MCD Application Team
00005   * @brief   LPTIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Low Power Timer (LPTIM) peripheral:
00008   *           + Initialization and de-initialization functions.
00009   *           + Start/Stop operation functions in polling mode.
00010   *           + Start/Stop operation functions in interrupt mode.
00011   *           + Reading operation functions.
00012   *           + Peripheral State functions.
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2018 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                      ##### How to use this driver #####
00028   ==============================================================================
00029     [..]
00030       The LPTIM HAL driver can be used as follows:
00031
00032       (#)Initialize the LPTIM low level resources by implementing the
00033         HAL_LPTIM_MspInit():
00034          (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
00035          (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
00036              (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
00037              (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
00038              (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
00039
00040       (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
00041          configures mainly:
00042          (++) The instance: LPTIM1 or LPTIM2.
00043          (++) Clock: the counter clock.
00044              (+++) Source   : it can be either the ULPTIM input (IN1) or one of
00045                               the internal clock; (APB, LSE, LSI or MSI).
00046              (+++) Prescaler: select the clock divider.
00047          (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
00048                as counter clock source.
00049              (+++) Polarity:   polarity of the active edge for the counter unit
00050                                if the ULPTIM input is selected.
00051              (+++) SampleTime: clock sampling time to configure the clock glitch
00052                                filter.
00053          (++) Trigger: How the counter start.
00054              (+++) Source: trigger can be software or one of the hardware triggers.
00055              (+++) ActiveEdge : only for hardware trigger.
00056              (+++) SampleTime : trigger sampling time to configure the trigger
00057                                 glitch filter.
00058          (++) OutputPolarity : 2 opposite polarities are possible.
00059          (++) UpdateMode: specifies whether the update of the autoreload and
00060               the compare values is done immediately or after the end of current
00061               period.
00062          (++) Input1Source: Source selected for input1 (GPIO or comparator output).
00063          (++) Input2Source: Source selected for input2 (GPIO or comparator output).
00064               Input2 is used only for encoder feature so is used only for LPTIM1 instance.
00065
00066       (#)Six modes are available:
00067
00068          (++) PWM Mode: To generate a PWM signal with specified period and pulse,
00069          call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
00070          mode.
00071
00072          (++) One Pulse Mode: To generate pulse with specified width in response
00073          to a stimulus, call HAL_LPTIM_OnePulse_Start() or
00074          HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
00075
00076          (++) Set once Mode: In this mode, the output changes the level (from
00077          low level to high level if the output polarity is configured high, else
00078          the opposite) when a compare match occurs. To start this mode, call
00079          HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
00080          interruption mode.
00081
00082          (++) Encoder Mode: To use the encoder interface call
00083          HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
00084          interruption mode. Only available for LPTIM1 instance.
00085
00086          (++) Time out Mode: an active edge on one selected trigger input rests
00087          the counter. The first trigger event will start the timer, any
00088          successive trigger event will reset the counter and the timer will
00089          restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
00090          HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
00091
00092          (++) Counter Mode: counter can be used to count external events on
00093          the LPTIM Input1 or it can be used to count internal clock cycles.
00094          To start this mode, call HAL_LPTIM_Counter_Start() or
00095          HAL_LPTIM_Counter_Start_IT() for interruption mode.
00096
00097
00098       (#) User can stop any process by calling the corresponding API:
00099           HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
00100           already started in interruption mode.
00101
00102       (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
00103
00104     *** Callback registration ***
00105   =============================================
00106   [..]
00107   The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
00108   allows the user to configure dynamically the driver callbacks.
00109   [..]
00110   Use Function HAL_LPTIM_RegisterCallback() to register a callback.
00111   HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
00112   the Callback ID and a pointer to the user callback function.
00113   [..]
00114   Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
00115   default weak function.
00116   HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
00117   and the Callback ID.
00118   [..]
00119   These functions allow to register/unregister following callbacks:
00120
00121     (+) MspInitCallback         : LPTIM Base Msp Init Callback.
00122     (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
00123     (+) CompareMatchCallback    : Compare match Callback.
00124     (+) AutoReloadMatchCallback : Auto-reload match Callback.
00125     (+) TriggerCallback         : External trigger event detection Callback.
00126     (+) CompareWriteCallback    : Compare register write complete Callback.
00127     (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
00128     (+) DirectionUpCallback     : Up-counting direction change Callback.
00129     (+) DirectionDownCallback   : Down-counting direction change Callback.
00130
00131   [..]
00132   By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
00133   all interrupt callbacks are set to the corresponding weak functions:
00134   examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
00135
00136   [..]
00137   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
00138   functionalities in the Init/DeInit only when these callbacks are null
00139   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
00140   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00141
00142   [..]
00143   Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
00144   Exception done MspInit/MspDeInit that can be registered/unregistered
00145   in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
00146   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00147   In that case first register the MspInit/MspDeInit user callbacks
00148   using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
00149
00150   [..]
00151   When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
00152   not defined, the callback registration feature is not available and all callbacks
00153   are set to the corresponding weak functions.
00154
00155   @endverbatim
00156   ******************************************************************************
00157   */
00158
00159 /* Includes ------------------------------------------------------------------*/
00160 #include "stm32g0xx_hal.h"
00161
00162 /** @addtogroup STM32G0xx_HAL_Driver
00163   * @{
00164   */
00165
00166 /** @defgroup LPTIM LPTIM
00167   * @brief LPTIM HAL module driver.
00168   * @{
00169   */
00170
00171 #ifdef HAL_LPTIM_MODULE_ENABLED
00172
00173 #if defined (LPTIM1) || defined (LPTIM2)
00174
00175 /* Private typedef -----------------------------------------------------------*/
00176 /* Private define ------------------------------------------------------------*/
00177 /** @addtogroup LPTIM_Private_Constants
00178   * @{
00179   */
00180 #define TIMEOUT                                     1000UL /* Timeout is 1s */
00181 /**
00182   * @}
00183   */
00184
00185 /* Private macro -------------------------------------------------------------*/
00186 /** @addtogroup LPTIM_Private_Macros
00187   * @{
00188   */
00189 #if defined(LPTIM2)
00190 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \
00191   (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())
00192
00193 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \
00194   (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())
00195 #else
00196 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()
00197
00198 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()
00199 #endif /* LPTIM2 */
00200 /**
00201   * @}
00202   */
00203
00204 /* Private variables ---------------------------------------------------------*/
00205 /* Private function prototypes -----------------------------------------------*/
00206 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00207 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
00208 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00209 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
00210
00211 /* Exported functions --------------------------------------------------------*/
00212
00213 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00214   * @{
00215   */
00216
00217 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
00218   *  @brief    Initialization and Configuration functions.
00219   *
00220 @verbatim
00221   ==============================================================================
00222               ##### Initialization and de-initialization functions #####
00223   ==============================================================================
00224     [..]  This section provides functions allowing to:
00225       (+) Initialize the LPTIM according to the specified parameters in the
00226           LPTIM_InitTypeDef and initialize the associated handle.
00227       (+) DeInitialize the LPTIM peripheral.
00228       (+) Initialize the LPTIM MSP.
00229       (+) DeInitialize the LPTIM MSP.
00230
00231 @endverbatim
00232   * @{
00233   */
00234
00235 /**
00236   * @brief  Initialize the LPTIM according to the specified parameters in the
00237   *         LPTIM_InitTypeDef and initialize the associated handle.
00238   * @param  hlptim LPTIM handle
00239   * @retval HAL status
00240   */
00241 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
00242 {
00243   uint32_t tmpcfgr;
00244
00245   /* Check the LPTIM handle allocation */
00246   if (hlptim == NULL)
00247   {
00248     return HAL_ERROR;
00249   }
00250
00251   /* Check the parameters */
00252   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00253
00254   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
00255   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
00256   if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
00257       || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
00258   {
00259     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00260     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
00261   }
00262   assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
00263   if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
00264   {
00265     assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
00266     assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
00267   }
00268   assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
00269   assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
00270   assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
00271
00272   if (hlptim->State == HAL_LPTIM_STATE_RESET)
00273   {
00274     /* Allocate lock resource and initialize it */
00275     hlptim->Lock = HAL_UNLOCKED;
00276
00277 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00278     /* Reset interrupt callbacks to legacy weak callbacks */
00279     LPTIM_ResetCallback(hlptim);
00280
00281     if (hlptim->MspInitCallback == NULL)
00282     {
00283       hlptim->MspInitCallback = HAL_LPTIM_MspInit;
00284     }
00285
00286     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00287     hlptim->MspInitCallback(hlptim);
00288 #else
00289     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00290     HAL_LPTIM_MspInit(hlptim);
00291 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00292   }
00293
00294   /* Change the LPTIM state */
00295   hlptim->State = HAL_LPTIM_STATE_BUSY;
00296
00297   /* Get the LPTIMx CFGR value */
00298   tmpcfgr = hlptim->Instance->CFGR;
00299
00300   if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
00301       || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
00302   {
00303     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
00304   }
00305   if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
00306   {
00307     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
00308   }
00309
00310   /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
00311   tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
00312                           LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
00313
00314   /* Set initialization parameters */
00315   tmpcfgr |= (hlptim->Init.Clock.Source    |
00316               hlptim->Init.Clock.Prescaler |
00317               hlptim->Init.OutputPolarity  |
00318               hlptim->Init.UpdateMode      |
00319               hlptim->Init.CounterSource);
00320
00321   /* Glitch filters for internal triggers and  external inputs are configured
00322    * only if an internal clock source is provided to the LPTIM
00323    */
00324   if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
00325   {
00326     tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
00327                 hlptim->Init.UltraLowPowerClock.SampleTime);
00328   }
00329
00330   /* Configure LPTIM external clock polarity and digital filter */
00331   if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
00332       || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
00333   {
00334     tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
00335                 hlptim->Init.UltraLowPowerClock.SampleTime);
00336   }
00337
00338   /* Configure LPTIM external trigger */
00339   if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
00340   {
00341     /* Enable External trigger and set the trigger source */
00342     tmpcfgr |= (hlptim->Init.Trigger.Source     |
00343                 hlptim->Init.Trigger.ActiveEdge |
00344                 hlptim->Init.Trigger.SampleTime);
00345   }
00346
00347   /* Write to LPTIMx CFGR */
00348   hlptim->Instance->CFGR = tmpcfgr;
00349
00350   /* Configure LPTIM input sources */
00351   if (hlptim->Instance == LPTIM1)
00352   {
00353     /* Check LPTIM Input1 and Input2 sources */
00354     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
00355     assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
00356
00357     /* Configure LPTIM Input1 and Input2 sources */
00358     hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
00359   }
00360   else
00361   {
00362     /* Check LPTIM2 Input1 source */
00363     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
00364
00365     /* Configure LPTIM2 Input1 source */
00366     hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
00367   }
00368
00369   /* Change the LPTIM state */
00370   hlptim->State = HAL_LPTIM_STATE_READY;
00371
00372   /* Return function status */
00373   return HAL_OK;
00374 }
00375
00376 /**
00377   * @brief  DeInitialize the LPTIM peripheral.
00378   * @param  hlptim LPTIM handle
00379   * @retval HAL status
00380   */
00381 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
00382 {
00383   /* Check the LPTIM handle allocation */
00384   if (hlptim == NULL)
00385   {
00386     return HAL_ERROR;
00387   }
00388
00389   /* Change the LPTIM state */
00390   hlptim->State = HAL_LPTIM_STATE_BUSY;
00391
00392   /* Disable the LPTIM Peripheral Clock */
00393   __HAL_LPTIM_DISABLE(hlptim);
00394
00395   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00396   {
00397     return HAL_TIMEOUT;
00398   }
00399
00400 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00401   if (hlptim->MspDeInitCallback == NULL)
00402   {
00403     hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
00404   }
00405
00406   /* DeInit the low level hardware: CLOCK, NVIC.*/
00407   hlptim->MspDeInitCallback(hlptim);
00408 #else
00409   /* DeInit the low level hardware: CLOCK, NVIC.*/
00410   HAL_LPTIM_MspDeInit(hlptim);
00411 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00412
00413   /* Change the LPTIM state */
00414   hlptim->State = HAL_LPTIM_STATE_RESET;
00415
00416   /* Release Lock */
00417   __HAL_UNLOCK(hlptim);
00418
00419   /* Return function status */
00420   return HAL_OK;
00421 }
00422
00423 /**
00424   * @brief  Initialize the LPTIM MSP.
00425   * @param  hlptim LPTIM handle
00426   * @retval None
00427   */
00428 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
00429 {
00430   /* Prevent unused argument(s) compilation warning */
00431   UNUSED(hlptim);
00432
00433   /* NOTE : This function should not be modified, when the callback is needed,
00434             the HAL_LPTIM_MspInit could be implemented in the user file
00435    */
00436 }
00437
00438 /**
00439   * @brief  DeInitialize LPTIM MSP.
00440   * @param  hlptim LPTIM handle
00441   * @retval None
00442   */
00443 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
00444 {
00445   /* Prevent unused argument(s) compilation warning */
00446   UNUSED(hlptim);
00447
00448   /* NOTE : This function should not be modified, when the callback is needed,
00449             the HAL_LPTIM_MspDeInit could be implemented in the user file
00450    */
00451 }
00452
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
00458   *  @brief   Start-Stop operation functions.
00459   *
00460 @verbatim
00461   ==============================================================================
00462                 ##### LPTIM Start Stop operation functions #####
00463   ==============================================================================
00464     [..]  This section provides functions allowing to:
00465       (+) Start the PWM mode.
00466       (+) Stop the PWM mode.
00467       (+) Start the One pulse mode.
00468       (+) Stop the One pulse mode.
00469       (+) Start the Set once mode.
00470       (+) Stop the Set once mode.
00471       (+) Start the Encoder mode.
00472       (+) Stop the Encoder mode.
00473       (+) Start the Timeout mode.
00474       (+) Stop the Timeout mode.
00475       (+) Start the Counter mode.
00476       (+) Stop the Counter mode.
00477
00478
00479 @endverbatim
00480   * @{
00481   */
00482
00483 /**
00484   * @brief  Start the LPTIM PWM generation.
00485   * @param  hlptim LPTIM handle
00486   * @param  Period Specifies the Autoreload value.
00487   *         This parameter must be a value between 0x0001 and 0xFFFF.
00488   * @param  Pulse Specifies the compare value.
00489   *         This parameter must be a value between 0x0000 and 0xFFFF.
00490   * @retval HAL status
00491   */
00492 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00493 {
00494   /* Check the parameters */
00495   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00496   assert_param(IS_LPTIM_PERIOD(Period));
00497   assert_param(IS_LPTIM_PULSE(Pulse));
00498
00499   /* Set the LPTIM state */
00500   hlptim->State = HAL_LPTIM_STATE_BUSY;
00501
00502   /* Reset WAVE bit to set PWM mode */
00503   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00504
00505   /* Enable the Peripheral */
00506   __HAL_LPTIM_ENABLE(hlptim);
00507
00508   /* Clear flag */
00509   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00510
00511   /* Load the period value in the autoreload register */
00512   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00513
00514   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00515   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00516   {
00517     return HAL_TIMEOUT;
00518   }
00519
00520   /* Clear flag */
00521   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00522
00523   /* Load the pulse value in the compare register */
00524   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00525
00526   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00527   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00528   {
00529     return HAL_TIMEOUT;
00530   }
00531
00532   /* Start timer in continuous mode */
00533   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00534
00535   /* Change the LPTIM state */
00536   hlptim->State = HAL_LPTIM_STATE_READY;
00537
00538   /* Return function status */
00539   return HAL_OK;
00540 }
00541
00542 /**
00543   * @brief  Stop the LPTIM PWM generation.
00544   * @param  hlptim LPTIM handle
00545   * @retval HAL status
00546   */
00547 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
00548 {
00549   /* Check the parameters */
00550   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00551
00552   /* Change the LPTIM state */
00553   hlptim->State = HAL_LPTIM_STATE_BUSY;
00554
00555   /* Disable the Peripheral */
00556   __HAL_LPTIM_DISABLE(hlptim);
00557
00558   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00559   {
00560     return HAL_TIMEOUT;
00561   }
00562
00563   /* Change the LPTIM state */
00564   hlptim->State = HAL_LPTIM_STATE_READY;
00565
00566   /* Return function status */
00567   return HAL_OK;
00568 }
00569
00570 /**
00571   * @brief  Start the LPTIM PWM generation in interrupt mode.
00572   * @param  hlptim LPTIM handle
00573   * @param  Period Specifies the Autoreload value.
00574   *         This parameter must be a value between 0x0001 and 0xFFFF
00575   * @param  Pulse Specifies the compare value.
00576   *         This parameter must be a value between 0x0000 and 0xFFFF
00577   * @retval HAL status
00578   */
00579 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00580 {
00581   /* Check the parameters */
00582   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00583   assert_param(IS_LPTIM_PERIOD(Period));
00584   assert_param(IS_LPTIM_PULSE(Pulse));
00585
00586   /* Set the LPTIM state */
00587   hlptim->State = HAL_LPTIM_STATE_BUSY;
00588
00589   /* Reset WAVE bit to set PWM mode */
00590   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00591
00592   /* Enable the Peripheral */
00593   __HAL_LPTIM_ENABLE(hlptim);
00594
00595   /* Clear flag */
00596   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00597
00598   /* Load the period value in the autoreload register */
00599   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00600
00601   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00602   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00603   {
00604     return HAL_TIMEOUT;
00605   }
00606
00607   /* Clear flag */
00608   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00609
00610   /* Load the pulse value in the compare register */
00611   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00612
00613   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00614   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00615   {
00616     return HAL_TIMEOUT;
00617   }
00618
00619   /* Disable the Peripheral */
00620   __HAL_LPTIM_DISABLE(hlptim);
00621
00622   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00623   {
00624     return HAL_TIMEOUT;
00625   }
00626
00627   /* Enable Autoreload write complete interrupt */
00628   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00629
00630   /* Enable Compare write complete interrupt */
00631   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00632
00633   /* Enable Autoreload match interrupt */
00634   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00635
00636   /* Enable Compare match interrupt */
00637   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00638
00639   /* If external trigger source is used, then enable external trigger interrupt */
00640   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00641   {
00642     /* Enable external trigger interrupt */
00643     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00644   }
00645
00646   /* Enable the Peripheral */
00647   __HAL_LPTIM_ENABLE(hlptim);
00648
00649   /* Start timer in continuous mode */
00650   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00651
00652   /* Change the LPTIM state */
00653   hlptim->State = HAL_LPTIM_STATE_READY;
00654
00655   /* Return function status */
00656   return HAL_OK;
00657 }
00658
00659 /**
00660   * @brief  Stop the LPTIM PWM generation in interrupt mode.
00661   * @param  hlptim LPTIM handle
00662   * @retval HAL status
00663   */
00664 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00665 {
00666   /* Check the parameters */
00667   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00668
00669   /* Change the LPTIM state */
00670   hlptim->State = HAL_LPTIM_STATE_BUSY;
00671
00672   /* Disable the Peripheral */
00673   __HAL_LPTIM_DISABLE(hlptim);
00674
00675   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00676   {
00677     return HAL_TIMEOUT;
00678   }
00679
00680   /* Disable Autoreload write complete interrupt */
00681   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00682
00683   /* Disable Compare write complete interrupt */
00684   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00685
00686   /* Disable Autoreload match interrupt */
00687   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00688
00689   /* Disable Compare match interrupt */
00690   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00691
00692   /* If external trigger source is used, then disable external trigger interrupt */
00693   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00694   {
00695     /* Disable external trigger interrupt */
00696     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00697   }
00698
00699   /* Change the LPTIM state */
00700   hlptim->State = HAL_LPTIM_STATE_READY;
00701
00702   /* Return function status */
00703   return HAL_OK;
00704 }
00705
00706 /**
00707   * @brief  Start the LPTIM One pulse generation.
00708   * @param  hlptim LPTIM handle
00709   * @param  Period Specifies the Autoreload value.
00710   *         This parameter must be a value between 0x0001 and 0xFFFF.
00711   * @param  Pulse Specifies the compare value.
00712   *         This parameter must be a value between 0x0000 and 0xFFFF.
00713   * @retval HAL status
00714   */
00715 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00716 {
00717   /* Check the parameters */
00718   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00719   assert_param(IS_LPTIM_PERIOD(Period));
00720   assert_param(IS_LPTIM_PULSE(Pulse));
00721
00722   /* Set the LPTIM state */
00723   hlptim->State = HAL_LPTIM_STATE_BUSY;
00724
00725   /* Reset WAVE bit to set one pulse mode */
00726   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00727
00728   /* Enable the Peripheral */
00729   __HAL_LPTIM_ENABLE(hlptim);
00730
00731   /* Clear flag */
00732   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00733
00734   /* Load the period value in the autoreload register */
00735   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00736
00737   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00738   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00739   {
00740     return HAL_TIMEOUT;
00741   }
00742
00743   /* Clear flag */
00744   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00745
00746   /* Load the pulse value in the compare register */
00747   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00748
00749   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00750   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00751   {
00752     return HAL_TIMEOUT;
00753   }
00754
00755   /* Start timer in single (one shot) mode */
00756   __HAL_LPTIM_START_SINGLE(hlptim);
00757
00758   /* Change the LPTIM state */
00759   hlptim->State = HAL_LPTIM_STATE_READY;
00760
00761   /* Return function status */
00762   return HAL_OK;
00763 }
00764
00765 /**
00766   * @brief  Stop the LPTIM One pulse generation.
00767   * @param  hlptim LPTIM handle
00768   * @retval HAL status
00769   */
00770 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
00771 {
00772   /* Check the parameters */
00773   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00774
00775   /* Set the LPTIM state */
00776   hlptim->State = HAL_LPTIM_STATE_BUSY;
00777
00778   /* Disable the Peripheral */
00779   __HAL_LPTIM_DISABLE(hlptim);
00780
00781   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00782   {
00783     return HAL_TIMEOUT;
00784   }
00785
00786   /* Change the LPTIM state */
00787   hlptim->State = HAL_LPTIM_STATE_READY;
00788
00789   /* Return function status */
00790   return HAL_OK;
00791 }
00792
00793 /**
00794   * @brief  Start the LPTIM One pulse generation in interrupt mode.
00795   * @param  hlptim LPTIM handle
00796   * @param  Period Specifies the Autoreload value.
00797   *         This parameter must be a value between 0x0001 and 0xFFFF.
00798   * @param  Pulse Specifies the compare value.
00799   *         This parameter must be a value between 0x0000 and 0xFFFF.
00800   * @retval HAL status
00801   */
00802 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00803 {
00804   /* Check the parameters */
00805   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00806   assert_param(IS_LPTIM_PERIOD(Period));
00807   assert_param(IS_LPTIM_PULSE(Pulse));
00808
00809   /* Set the LPTIM state */
00810   hlptim->State = HAL_LPTIM_STATE_BUSY;
00811
00812   /* Reset WAVE bit to set one pulse mode */
00813   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00814
00815   /* Enable the Peripheral */
00816   __HAL_LPTIM_ENABLE(hlptim);
00817
00818   /* Clear flag */
00819   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00820
00821   /* Load the period value in the autoreload register */
00822   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00823
00824   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00825   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00826   {
00827     return HAL_TIMEOUT;
00828   }
00829
00830   /* Clear flag */
00831   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00832
00833   /* Load the pulse value in the compare register */
00834   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00835
00836   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00837   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00838   {
00839     return HAL_TIMEOUT;
00840   }
00841
00842   /* Disable the Peripheral */
00843   __HAL_LPTIM_DISABLE(hlptim);
00844
00845   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00846   {
00847     return HAL_TIMEOUT;
00848   }
00849
00850   /* Enable Autoreload write complete interrupt */
00851   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00852
00853   /* Enable Compare write complete interrupt */
00854   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00855
00856   /* Enable Autoreload match interrupt */
00857   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00858
00859   /* Enable Compare match interrupt */
00860   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00861
00862   /* If external trigger source is used, then enable external trigger interrupt */
00863   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00864   {
00865     /* Enable external trigger interrupt */
00866     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00867   }
00868
00869   /* Enable the Peripheral */
00870   __HAL_LPTIM_ENABLE(hlptim);
00871
00872   /* Start timer in single (one shot) mode */
00873   __HAL_LPTIM_START_SINGLE(hlptim);
00874
00875   /* Change the LPTIM state */
00876   hlptim->State = HAL_LPTIM_STATE_READY;
00877
00878   /* Return function status */
00879   return HAL_OK;
00880 }
00881
00882 /**
00883   * @brief  Stop the LPTIM One pulse generation in interrupt mode.
00884   * @param  hlptim LPTIM handle
00885   * @retval HAL status
00886   */
00887 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00888 {
00889   /* Check the parameters */
00890   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00891
00892   /* Set the LPTIM state */
00893   hlptim->State = HAL_LPTIM_STATE_BUSY;
00894
00895
00896   /* Disable the Peripheral */
00897   __HAL_LPTIM_DISABLE(hlptim);
00898
00899   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00900   {
00901     return HAL_TIMEOUT;
00902   }
00903
00904   /* Disable Autoreload write complete interrupt */
00905   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00906
00907   /* Disable Compare write complete interrupt */
00908   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00909
00910   /* Disable Autoreload match interrupt */
00911   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00912
00913   /* Disable Compare match interrupt */
00914   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00915
00916   /* If external trigger source is used, then disable external trigger interrupt */
00917   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00918   {
00919     /* Disable external trigger interrupt */
00920     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00921   }
00922
00923   /* Change the LPTIM state */
00924   hlptim->State = HAL_LPTIM_STATE_READY;
00925
00926   /* Return function status */
00927   return HAL_OK;
00928 }
00929
00930 /**
00931   * @brief  Start the LPTIM in Set once mode.
00932   * @param  hlptim LPTIM handle
00933   * @param  Period Specifies the Autoreload value.
00934   *         This parameter must be a value between 0x0001 and 0xFFFF.
00935   * @param  Pulse Specifies the compare value.
00936   *         This parameter must be a value between 0x0000 and 0xFFFF.
00937   * @retval HAL status
00938   */
00939 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00940 {
00941   /* Check the parameters */
00942   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00943   assert_param(IS_LPTIM_PERIOD(Period));
00944   assert_param(IS_LPTIM_PULSE(Pulse));
00945
00946   /* Set the LPTIM state */
00947   hlptim->State = HAL_LPTIM_STATE_BUSY;
00948
00949   /* Set WAVE bit to enable the set once mode */
00950   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00951
00952   /* Enable the Peripheral */
00953   __HAL_LPTIM_ENABLE(hlptim);
00954
00955   /* Clear flag */
00956   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00957
00958   /* Load the period value in the autoreload register */
00959   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00960
00961   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00962   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00963   {
00964     return HAL_TIMEOUT;
00965   }
00966
00967   /* Clear flag */
00968   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00969
00970   /* Load the pulse value in the compare register */
00971   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00972
00973   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00974   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00975   {
00976     return HAL_TIMEOUT;
00977   }
00978
00979   /* Start timer in single (one shot) mode */
00980   __HAL_LPTIM_START_SINGLE(hlptim);
00981
00982   /* Change the LPTIM state */
00983   hlptim->State = HAL_LPTIM_STATE_READY;
00984
00985   /* Return function status */
00986   return HAL_OK;
00987 }
00988
00989 /**
00990   * @brief  Stop the LPTIM Set once mode.
00991   * @param  hlptim LPTIM handle
00992   * @retval HAL status
00993   */
00994 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
00995 {
00996   /* Check the parameters */
00997   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00998
00999   /* Set the LPTIM state */
01000   hlptim->State = HAL_LPTIM_STATE_BUSY;
01001
01002   /* Disable the Peripheral */
01003   __HAL_LPTIM_DISABLE(hlptim);
01004
01005   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01006   {
01007     return HAL_TIMEOUT;
01008   }
01009
01010   /* Change the LPTIM state */
01011   hlptim->State = HAL_LPTIM_STATE_READY;
01012
01013   /* Return function status */
01014   return HAL_OK;
01015 }
01016
01017 /**
01018   * @brief  Start the LPTIM Set once mode in interrupt mode.
01019   * @param  hlptim LPTIM handle
01020   * @param  Period Specifies the Autoreload value.
01021   *         This parameter must be a value between 0x0000 and 0xFFFF.
01022   * @param  Pulse Specifies the compare value.
01023   *         This parameter must be a value between 0x0000 and 0xFFFF.
01024   * @retval HAL status
01025   */
01026 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
01027 {
01028   /* Check the parameters */
01029   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01030   assert_param(IS_LPTIM_PERIOD(Period));
01031   assert_param(IS_LPTIM_PULSE(Pulse));
01032
01033   /* Set the LPTIM state */
01034   hlptim->State = HAL_LPTIM_STATE_BUSY;
01035
01036   /* Set WAVE bit to enable the set once mode */
01037   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
01038
01039   /* Enable the Peripheral */
01040   __HAL_LPTIM_ENABLE(hlptim);
01041
01042   /* Clear flag */
01043   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01044
01045   /* Load the period value in the autoreload register */
01046   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01047
01048   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01049   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01050   {
01051     return HAL_TIMEOUT;
01052   }
01053
01054   /* Clear flag */
01055   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01056
01057   /* Load the pulse value in the compare register */
01058   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
01059
01060   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01061   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01062   {
01063     return HAL_TIMEOUT;
01064   }
01065
01066   /* Disable the Peripheral */
01067   __HAL_LPTIM_DISABLE(hlptim);
01068
01069   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01070   {
01071     return HAL_TIMEOUT;
01072   }
01073
01074   /* Enable Autoreload write complete interrupt */
01075   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01076
01077   /* Enable Compare write complete interrupt */
01078   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
01079
01080   /* Enable Autoreload match interrupt */
01081   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01082
01083   /* Enable Compare match interrupt */
01084   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01085
01086   /* If external trigger source is used, then enable external trigger interrupt */
01087   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
01088   {
01089     /* Enable external trigger interrupt */
01090     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
01091   }
01092
01093   /* Enable the Peripheral */
01094   __HAL_LPTIM_ENABLE(hlptim);
01095
01096   /* Start timer in single (one shot) mode */
01097   __HAL_LPTIM_START_SINGLE(hlptim);
01098
01099   /* Change the LPTIM state */
01100   hlptim->State = HAL_LPTIM_STATE_READY;
01101
01102   /* Return function status */
01103   return HAL_OK;
01104 }
01105
01106 /**
01107   * @brief  Stop the LPTIM Set once mode in interrupt mode.
01108   * @param  hlptim LPTIM handle
01109   * @retval HAL status
01110   */
01111 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01112 {
01113   /* Check the parameters */
01114   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01115
01116   /* Set the LPTIM state */
01117   hlptim->State = HAL_LPTIM_STATE_BUSY;
01118
01119   /* Disable the Peripheral */
01120   __HAL_LPTIM_DISABLE(hlptim);
01121
01122   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01123   {
01124     return HAL_TIMEOUT;
01125   }
01126
01127   /* Disable Autoreload write complete interrupt */
01128   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01129
01130   /* Disable Compare write complete interrupt */
01131   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
01132
01133   /* Disable Autoreload match interrupt */
01134   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01135
01136   /* Disable Compare match interrupt */
01137   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01138
01139   /* If external trigger source is used, then disable external trigger interrupt */
01140   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
01141   {
01142     /* Disable external trigger interrupt */
01143     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
01144   }
01145
01146   /* Change the LPTIM state */
01147   hlptim->State = HAL_LPTIM_STATE_READY;
01148
01149   /* Return function status */
01150   return HAL_OK;
01151 }
01152
01153 /**
01154   * @brief  Start the Encoder interface.
01155   * @param  hlptim LPTIM handle
01156   * @param  Period Specifies the Autoreload value.
01157   *         This parameter must be a value between 0x0001 and 0xFFFF.
01158   * @retval HAL status
01159   */
01160 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01161 {
01162   uint32_t          tmpcfgr;
01163
01164   /* Check the parameters */
01165   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01166   assert_param(IS_LPTIM_PERIOD(Period));
01167   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
01168   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01169   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01170
01171   /* Set the LPTIM state */
01172   hlptim->State = HAL_LPTIM_STATE_BUSY;
01173
01174   /* Get the LPTIMx CFGR value */
01175   tmpcfgr = hlptim->Instance->CFGR;
01176
01177   /* Clear CKPOL bits */
01178   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01179
01180   /* Set Input polarity */
01181   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01182
01183   /* Write to LPTIMx CFGR */
01184   hlptim->Instance->CFGR = tmpcfgr;
01185
01186   /* Set ENC bit to enable the encoder interface */
01187   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01188
01189   /* Enable the Peripheral */
01190   __HAL_LPTIM_ENABLE(hlptim);
01191
01192   /* Clear flag */
01193   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01194
01195   /* Load the period value in the autoreload register */
01196   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01197
01198   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01199   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01200   {
01201     return HAL_TIMEOUT;
01202   }
01203
01204   /* Start timer in continuous mode */
01205   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01206
01207   /* Change the LPTIM state */
01208   hlptim->State = HAL_LPTIM_STATE_READY;
01209
01210   /* Return function status */
01211   return HAL_OK;
01212 }
01213
01214 /**
01215   * @brief  Stop the Encoder interface.
01216   * @param  hlptim LPTIM handle
01217   * @retval HAL status
01218   */
01219 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
01220 {
01221   /* Check the parameters */
01222   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01223
01224   /* Set the LPTIM state */
01225   hlptim->State = HAL_LPTIM_STATE_BUSY;
01226
01227   /* Disable the Peripheral */
01228   __HAL_LPTIM_DISABLE(hlptim);
01229
01230   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01231   {
01232     return HAL_TIMEOUT;
01233   }
01234
01235   /* Reset ENC bit to disable the encoder interface */
01236   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01237
01238   /* Change the LPTIM state */
01239   hlptim->State = HAL_LPTIM_STATE_READY;
01240
01241   /* Return function status */
01242   return HAL_OK;
01243 }
01244
01245 /**
01246   * @brief  Start the Encoder interface in interrupt mode.
01247   * @param  hlptim LPTIM handle
01248   * @param  Period Specifies the Autoreload value.
01249   *         This parameter must be a value between 0x0000 and 0xFFFF.
01250   * @retval HAL status
01251   */
01252 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01253 {
01254   uint32_t          tmpcfgr;
01255
01256   /* Check the parameters */
01257   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01258   assert_param(IS_LPTIM_PERIOD(Period));
01259   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
01260   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01261   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01262
01263   /* Set the LPTIM state */
01264   hlptim->State = HAL_LPTIM_STATE_BUSY;
01265
01266   /* Configure edge sensitivity for encoder mode */
01267   /* Get the LPTIMx CFGR value */
01268   tmpcfgr = hlptim->Instance->CFGR;
01269
01270   /* Clear CKPOL bits */
01271   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01272
01273   /* Set Input polarity */
01274   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01275
01276   /* Write to LPTIMx CFGR */
01277   hlptim->Instance->CFGR = tmpcfgr;
01278
01279   /* Set ENC bit to enable the encoder interface */
01280   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01281
01282   /* Enable the Peripheral */
01283   __HAL_LPTIM_ENABLE(hlptim);
01284
01285   /* Clear flag */
01286   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01287
01288   /* Load the period value in the autoreload register */
01289   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01290
01291   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01292   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01293   {
01294     return HAL_TIMEOUT;
01295   }
01296
01297   /* Disable the Peripheral */
01298   __HAL_LPTIM_DISABLE(hlptim);
01299
01300   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01301   {
01302     return HAL_TIMEOUT;
01303   }
01304
01305   /* Enable "switch to down direction" interrupt */
01306   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
01307
01308   /* Enable "switch to up direction" interrupt */
01309   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
01310
01311   /* Enable the Peripheral */
01312   __HAL_LPTIM_ENABLE(hlptim);
01313
01314   /* Start timer in continuous mode */
01315   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01316
01317   /* Change the LPTIM state */
01318   hlptim->State = HAL_LPTIM_STATE_READY;
01319
01320   /* Return function status */
01321   return HAL_OK;
01322 }
01323
01324 /**
01325   * @brief  Stop the Encoder interface in interrupt mode.
01326   * @param  hlptim LPTIM handle
01327   * @retval HAL status
01328   */
01329 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01330 {
01331   /* Check the parameters */
01332   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01333
01334   /* Set the LPTIM state */
01335   hlptim->State = HAL_LPTIM_STATE_BUSY;
01336
01337   /* Disable the Peripheral */
01338   __HAL_LPTIM_DISABLE(hlptim);
01339
01340   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01341   {
01342     return HAL_TIMEOUT;
01343   }
01344
01345   /* Reset ENC bit to disable the encoder interface */
01346   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01347
01348   /* Disable "switch to down direction" interrupt */
01349   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
01350
01351   /* Disable "switch to up direction" interrupt */
01352   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
01353
01354   /* Change the LPTIM state */
01355   hlptim->State = HAL_LPTIM_STATE_READY;
01356
01357   /* Return function status */
01358   return HAL_OK;
01359 }
01360
01361 /**
01362   * @brief  Start the Timeout function.
01363   * @note   The first trigger event will start the timer, any successive
01364   *         trigger event will reset the counter and the timer restarts.
01365   * @param  hlptim LPTIM handle
01366   * @param  Period Specifies the Autoreload value.
01367   *         This parameter must be a value between 0x0001 and 0xFFFF.
01368   * @param  Timeout Specifies the TimeOut value to reset the counter.
01369   *         This parameter must be a value between 0x0000 and 0xFFFF.
01370   * @retval HAL status
01371   */
01372 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01373 {
01374   /* Check the parameters */
01375   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01376   assert_param(IS_LPTIM_PERIOD(Period));
01377   assert_param(IS_LPTIM_PULSE(Timeout));
01378
01379   /* Set the LPTIM state */
01380   hlptim->State = HAL_LPTIM_STATE_BUSY;
01381
01382   /* Set TIMOUT bit to enable the timeout function */
01383   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01384
01385   /* Enable the Peripheral */
01386   __HAL_LPTIM_ENABLE(hlptim);
01387
01388   /* Clear flag */
01389   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01390
01391   /* Load the period value in the autoreload register */
01392   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01393
01394   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01395   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01396   {
01397     return HAL_TIMEOUT;
01398   }
01399
01400   /* Clear flag */
01401   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01402
01403   /* Load the Timeout value in the compare register */
01404   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01405
01406   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01407   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01408   {
01409     return HAL_TIMEOUT;
01410   }
01411
01412   /* Start timer in continuous mode */
01413   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01414
01415   /* Change the LPTIM state */
01416   hlptim->State = HAL_LPTIM_STATE_READY;
01417
01418   /* Return function status */
01419   return HAL_OK;
01420 }
01421
01422 /**
01423   * @brief  Stop the Timeout function.
01424   * @param  hlptim LPTIM handle
01425   * @retval HAL status
01426   */
01427 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
01428 {
01429   /* Check the parameters */
01430   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01431
01432   /* Set the LPTIM state */
01433   hlptim->State = HAL_LPTIM_STATE_BUSY;
01434
01435   /* Disable the Peripheral */
01436   __HAL_LPTIM_DISABLE(hlptim);
01437
01438   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01439   {
01440     return HAL_TIMEOUT;
01441   }
01442
01443   /* Reset TIMOUT bit to enable the timeout function */
01444   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01445
01446   /* Change the LPTIM state */
01447   hlptim->State = HAL_LPTIM_STATE_READY;
01448
01449   /* Return function status */
01450   return HAL_OK;
01451 }
01452
01453 /**
01454   * @brief  Start the Timeout function in interrupt mode.
01455   * @note   The first trigger event will start the timer, any successive
01456   *         trigger event will reset the counter and the timer restarts.
01457   * @param  hlptim LPTIM handle
01458   * @param  Period Specifies the Autoreload value.
01459   *         This parameter must be a value between 0x0001 and 0xFFFF.
01460   * @param  Timeout Specifies the TimeOut value to reset the counter.
01461   *         This parameter must be a value between 0x0000 and 0xFFFF.
01462   * @retval HAL status
01463   */
01464 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01465 {
01466   /* Check the parameters */
01467   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01468   assert_param(IS_LPTIM_PERIOD(Period));
01469   assert_param(IS_LPTIM_PULSE(Timeout));
01470
01471   /* Set the LPTIM state */
01472   hlptim->State = HAL_LPTIM_STATE_BUSY;
01473
01474   /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
01475   __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
01476
01477   /* Set TIMOUT bit to enable the timeout function */
01478   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01479
01480   /* Enable the Peripheral */
01481   __HAL_LPTIM_ENABLE(hlptim);
01482
01483   /* Clear flag */
01484   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01485
01486   /* Load the period value in the autoreload register */
01487   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01488
01489   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01490   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01491   {
01492     return HAL_TIMEOUT;
01493   }
01494
01495   /* Clear flag */
01496   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01497
01498   /* Load the Timeout value in the compare register */
01499   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01500
01501   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01502   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01503   {
01504     return HAL_TIMEOUT;
01505   }
01506
01507   /* Disable the Peripheral */
01508   __HAL_LPTIM_DISABLE(hlptim);
01509
01510   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01511   {
01512     return HAL_TIMEOUT;
01513   }
01514
01515   /* Enable Compare match interrupt */
01516   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01517
01518   /* Enable the Peripheral */
01519   __HAL_LPTIM_ENABLE(hlptim);
01520
01521   /* Start timer in continuous mode */
01522   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01523
01524   /* Change the LPTIM state */
01525   hlptim->State = HAL_LPTIM_STATE_READY;
01526
01527   /* Return function status */
01528   return HAL_OK;
01529 }
01530
01531 /**
01532   * @brief  Stop the Timeout function in interrupt mode.
01533   * @param  hlptim LPTIM handle
01534   * @retval HAL status
01535   */
01536 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01537 {
01538   /* Check the parameters */
01539   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01540
01541
01542   /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
01543   __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
01544
01545   /* Set the LPTIM state */
01546   hlptim->State = HAL_LPTIM_STATE_BUSY;
01547
01548   /* Disable the Peripheral */
01549   __HAL_LPTIM_DISABLE(hlptim);
01550
01551   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01552   {
01553     return HAL_TIMEOUT;
01554   }
01555
01556   /* Reset TIMOUT bit to enable the timeout function */
01557   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01558
01559   /* Disable Compare match interrupt */
01560   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01561
01562   /* Change the LPTIM state */
01563   hlptim->State = HAL_LPTIM_STATE_READY;
01564
01565   /* Return function status */
01566   return HAL_OK;
01567 }
01568
01569 /**
01570   * @brief  Start the Counter mode.
01571   * @param  hlptim LPTIM handle
01572   * @param  Period Specifies the Autoreload value.
01573   *         This parameter must be a value between 0x0001 and 0xFFFF.
01574   * @retval HAL status
01575   */
01576 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01577 {
01578   /* Check the parameters */
01579   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01580   assert_param(IS_LPTIM_PERIOD(Period));
01581
01582   /* Set the LPTIM state */
01583   hlptim->State = HAL_LPTIM_STATE_BUSY;
01584
01585   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01586   if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
01587       && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01588   {
01589     /* Check if clock is prescaled */
01590     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01591     /* Set clock prescaler to 0 */
01592     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01593   }
01594
01595   /* Enable the Peripheral */
01596   __HAL_LPTIM_ENABLE(hlptim);
01597
01598   /* Clear flag */
01599   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01600
01601   /* Load the period value in the autoreload register */
01602   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01603
01604   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01605   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01606   {
01607     return HAL_TIMEOUT;
01608   }
01609
01610   /* Start timer in continuous mode */
01611   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01612
01613   /* Change the LPTIM state */
01614   hlptim->State = HAL_LPTIM_STATE_READY;
01615
01616   /* Return function status */
01617   return HAL_OK;
01618 }
01619
01620 /**
01621   * @brief  Stop the Counter mode.
01622   * @param  hlptim LPTIM handle
01623   * @retval HAL status
01624   */
01625 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
01626 {
01627   /* Check the parameters */
01628   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01629
01630   /* Set the LPTIM state */
01631   hlptim->State = HAL_LPTIM_STATE_BUSY;
01632
01633   /* Disable the Peripheral */
01634   __HAL_LPTIM_DISABLE(hlptim);
01635
01636   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01637   {
01638     return HAL_TIMEOUT;
01639   }
01640
01641   /* Change the LPTIM state */
01642   hlptim->State = HAL_LPTIM_STATE_READY;
01643
01644   /* Return function status */
01645   return HAL_OK;
01646 }
01647
01648 /**
01649   * @brief  Start the Counter mode in interrupt mode.
01650   * @param  hlptim LPTIM handle
01651   * @param  Period Specifies the Autoreload value.
01652   *         This parameter must be a value between 0x0001 and 0xFFFF.
01653   * @retval HAL status
01654   */
01655 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01656 {
01657   /* Check the parameters */
01658   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01659   assert_param(IS_LPTIM_PERIOD(Period));
01660
01661   /* Set the LPTIM state */
01662   hlptim->State = HAL_LPTIM_STATE_BUSY;
01663
01664   /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
01665   __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
01666
01667   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01668   if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
01669       && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01670   {
01671     /* Check if clock is prescaled */
01672     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01673     /* Set clock prescaler to 0 */
01674     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01675   }
01676
01677   /* Enable the Peripheral */
01678   __HAL_LPTIM_ENABLE(hlptim);
01679
01680   /* Clear flag */
01681   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01682
01683   /* Load the period value in the autoreload register */
01684   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01685
01686   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01687   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01688   {
01689     return HAL_TIMEOUT;
01690   }
01691
01692   /* Disable the Peripheral */
01693   __HAL_LPTIM_DISABLE(hlptim);
01694
01695   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01696   {
01697     return HAL_TIMEOUT;
01698   }
01699
01700   /* Enable Autoreload write complete interrupt */
01701   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01702
01703   /* Enable Autoreload match interrupt */
01704   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01705
01706   /* Enable the Peripheral */
01707   __HAL_LPTIM_ENABLE(hlptim);
01708
01709   /* Start timer in continuous mode */
01710   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01711
01712   /* Change the LPTIM state */
01713   hlptim->State = HAL_LPTIM_STATE_READY;
01714
01715   /* Return function status */
01716   return HAL_OK;
01717 }
01718
01719 /**
01720   * @brief  Stop the Counter mode in interrupt mode.
01721   * @param  hlptim LPTIM handle
01722   * @retval HAL status
01723   */
01724 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01725 {
01726   /* Check the parameters */
01727   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01728
01729
01730   /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
01731   __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
01732
01733   /* Set the LPTIM state */
01734   hlptim->State = HAL_LPTIM_STATE_BUSY;
01735
01736   /* Disable the Peripheral */
01737   __HAL_LPTIM_DISABLE(hlptim);
01738
01739   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01740   {
01741     return HAL_TIMEOUT;
01742   }
01743
01744   /* Disable Autoreload write complete interrupt */
01745   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01746
01747   /* Disable Autoreload match interrupt */
01748   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01749   /* Change the LPTIM state */
01750   hlptim->State = HAL_LPTIM_STATE_READY;
01751
01752   /* Return function status */
01753   return HAL_OK;
01754 }
01755
01756 /**
01757   * @}
01758   */
01759
01760 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
01761   *  @brief  Read operation functions.
01762   *
01763 @verbatim
01764   ==============================================================================
01765                   ##### LPTIM Read operation functions #####
01766   ==============================================================================
01767 [..]  This section provides LPTIM Reading functions.
01768       (+) Read the counter value.
01769       (+) Read the period (Auto-reload) value.
01770       (+) Read the pulse (Compare)value.
01771 @endverbatim
01772   * @{
01773   */
01774
01775 /**
01776   * @brief  Return the current counter value.
01777   * @param  hlptim LPTIM handle
01778   * @retval Counter value.
01779   */
01780 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
01781 {
01782   /* Check the parameters */
01783   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01784
01785   return (hlptim->Instance->CNT);
01786 }
01787
01788 /**
01789   * @brief  Return the current Autoreload (Period) value.
01790   * @param  hlptim LPTIM handle
01791   * @retval Autoreload value.
01792   */
01793 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
01794 {
01795   /* Check the parameters */
01796   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01797
01798   return (hlptim->Instance->ARR);
01799 }
01800
01801 /**
01802   * @brief  Return the current Compare (Pulse) value.
01803   * @param  hlptim LPTIM handle
01804   * @retval Compare value.
01805   */
01806 uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim)
01807 {
01808   /* Check the parameters */
01809   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01810
01811   return (hlptim->Instance->CMP);
01812 }
01813
01814 /**
01815   * @}
01816   */
01817
01818 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
01819   *  @brief  LPTIM  IRQ handler.
01820   *
01821 @verbatim
01822   ==============================================================================
01823                       ##### LPTIM IRQ handler and callbacks  #####
01824   ==============================================================================
01825 [..]  This section provides LPTIM IRQ handler and callback functions called within
01826       the IRQ handler:
01827    (+) LPTIM interrupt request handler
01828    (+) Compare match Callback
01829    (+) Auto-reload match Callback
01830    (+) External trigger event detection Callback
01831    (+) Compare register write complete Callback
01832    (+) Auto-reload register write complete Callback
01833    (+) Up-counting direction change Callback
01834    (+) Down-counting direction change Callback
01835
01836 @endverbatim
01837   * @{
01838   */
01839
01840 /**
01841   * @brief  Handle LPTIM interrupt request.
01842   * @param  hlptim LPTIM handle
01843   * @retval None
01844   */
01845 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
01846 {
01847   /* Compare match interrupt */
01848   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
01849   {
01850     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
01851     {
01852       /* Clear Compare match flag */
01853       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
01854
01855       /* Compare match Callback */
01856 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01857       hlptim->CompareMatchCallback(hlptim);
01858 #else
01859       HAL_LPTIM_CompareMatchCallback(hlptim);
01860 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01861     }
01862   }
01863
01864   /* Autoreload match interrupt */
01865   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
01866   {
01867     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
01868     {
01869       /* Clear Autoreload match flag */
01870       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
01871
01872       /* Autoreload match Callback */
01873 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01874       hlptim->AutoReloadMatchCallback(hlptim);
01875 #else
01876       HAL_LPTIM_AutoReloadMatchCallback(hlptim);
01877 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01878     }
01879   }
01880
01881   /* Trigger detected interrupt */
01882   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
01883   {
01884     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
01885     {
01886       /* Clear Trigger detected flag */
01887       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
01888
01889       /* Trigger detected callback */
01890 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01891       hlptim->TriggerCallback(hlptim);
01892 #else
01893       HAL_LPTIM_TriggerCallback(hlptim);
01894 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01895     }
01896   }
01897
01898   /* Compare write interrupt */
01899   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
01900   {
01901     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
01902     {
01903       /* Clear Compare write flag */
01904       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01905
01906       /* Compare write Callback */
01907 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01908       hlptim->CompareWriteCallback(hlptim);
01909 #else
01910       HAL_LPTIM_CompareWriteCallback(hlptim);
01911 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01912     }
01913   }
01914
01915   /* Autoreload write interrupt */
01916   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
01917   {
01918     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
01919     {
01920       /* Clear Autoreload write flag */
01921       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01922
01923       /* Autoreload write Callback */
01924 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01925       hlptim->AutoReloadWriteCallback(hlptim);
01926 #else
01927       HAL_LPTIM_AutoReloadWriteCallback(hlptim);
01928 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01929     }
01930   }
01931
01932   /* Direction counter changed from Down to Up interrupt */
01933   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
01934   {
01935     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
01936     {
01937       /* Clear Direction counter changed from Down to Up flag */
01938       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
01939
01940       /* Direction counter changed from Down to Up Callback */
01941 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01942       hlptim->DirectionUpCallback(hlptim);
01943 #else
01944       HAL_LPTIM_DirectionUpCallback(hlptim);
01945 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01946     }
01947   }
01948
01949   /* Direction counter changed from Up to Down interrupt */
01950   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
01951   {
01952     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
01953     {
01954       /* Clear Direction counter changed from Up to Down flag */
01955       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
01956
01957       /* Direction counter changed from Up to Down Callback */
01958 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01959       hlptim->DirectionDownCallback(hlptim);
01960 #else
01961       HAL_LPTIM_DirectionDownCallback(hlptim);
01962 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01963     }
01964   }
01965 }
01966
01967 /**
01968   * @brief  Compare match callback in non-blocking mode.
01969   * @param  hlptim LPTIM handle
01970   * @retval None
01971   */
01972 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
01973 {
01974   /* Prevent unused argument(s) compilation warning */
01975   UNUSED(hlptim);
01976
01977   /* NOTE : This function should not be modified, when the callback is needed,
01978             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
01979    */
01980 }
01981
01982 /**
01983   * @brief  Autoreload match callback in non-blocking mode.
01984   * @param  hlptim LPTIM handle
01985   * @retval None
01986   */
01987 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
01988 {
01989   /* Prevent unused argument(s) compilation warning */
01990   UNUSED(hlptim);
01991
01992   /* NOTE : This function should not be modified, when the callback is needed,
01993             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
01994    */
01995 }
01996
01997 /**
01998   * @brief  Trigger detected callback in non-blocking mode.
01999   * @param  hlptim LPTIM handle
02000   * @retval None
02001   */
02002 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
02003 {
02004   /* Prevent unused argument(s) compilation warning */
02005   UNUSED(hlptim);
02006
02007   /* NOTE : This function should not be modified, when the callback is needed,
02008             the HAL_LPTIM_TriggerCallback could be implemented in the user file
02009    */
02010 }
02011
02012 /**
02013   * @brief  Compare write callback in non-blocking mode.
02014   * @param  hlptim LPTIM handle
02015   * @retval None
02016   */
02017 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
02018 {
02019   /* Prevent unused argument(s) compilation warning */
02020   UNUSED(hlptim);
02021
02022   /* NOTE : This function should not be modified, when the callback is needed,
02023             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
02024    */
02025 }
02026
02027 /**
02028   * @brief  Autoreload write callback in non-blocking mode.
02029   * @param  hlptim LPTIM handle
02030   * @retval None
02031   */
02032 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
02033 {
02034   /* Prevent unused argument(s) compilation warning */
02035   UNUSED(hlptim);
02036
02037   /* NOTE : This function should not be modified, when the callback is needed,
02038             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
02039    */
02040 }
02041
02042 /**
02043   * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
02044   * @param  hlptim LPTIM handle
02045   * @retval None
02046   */
02047 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
02048 {
02049   /* Prevent unused argument(s) compilation warning */
02050   UNUSED(hlptim);
02051
02052   /* NOTE : This function should not be modified, when the callback is needed,
02053             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
02054    */
02055 }
02056
02057 /**
02058   * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
02059   * @param  hlptim LPTIM handle
02060   * @retval None
02061   */
02062 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
02063 {
02064   /* Prevent unused argument(s) compilation warning */
02065   UNUSED(hlptim);
02066
02067   /* NOTE : This function should not be modified, when the callback is needed,
02068             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
02069    */
02070 }
02071
02072 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
02073 /**
02074   * @brief  Register a User LPTIM callback to be used instead of the weak predefined callback
02075   * @param hlptim LPTIM handle
02076   * @param CallbackID ID of the callback to be registered
02077   *        This parameter can be one of the following values:
02078   *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
02079   *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
02080   *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
02081   *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
02082   *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
02083   *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
02084   *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
02085   *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
02086   *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
02087   * @param pCallback pointer to the callback function
02088   * @retval status
02089   */
02090 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef        *hlptim,
02091                                              HAL_LPTIM_CallbackIDTypeDef CallbackID,
02092                                              pLPTIM_CallbackTypeDef      pCallback)
02093 {
02094   HAL_StatusTypeDef status = HAL_OK;
02095
02096   if (pCallback == NULL)
02097   {
02098     return HAL_ERROR;
02099   }
02100
02101   /* Process locked */
02102   __HAL_LOCK(hlptim);
02103
02104   if (hlptim->State == HAL_LPTIM_STATE_READY)
02105   {
02106     switch (CallbackID)
02107     {
02108       case HAL_LPTIM_MSPINIT_CB_ID :
02109         hlptim->MspInitCallback = pCallback;
02110         break;
02111
02112       case HAL_LPTIM_MSPDEINIT_CB_ID :
02113         hlptim->MspDeInitCallback = pCallback;
02114         break;
02115
02116       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
02117         hlptim->CompareMatchCallback = pCallback;
02118         break;
02119
02120       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
02121         hlptim->AutoReloadMatchCallback = pCallback;
02122         break;
02123
02124       case HAL_LPTIM_TRIGGER_CB_ID :
02125         hlptim->TriggerCallback = pCallback;
02126         break;
02127
02128       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
02129         hlptim->CompareWriteCallback = pCallback;
02130         break;
02131
02132       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
02133         hlptim->AutoReloadWriteCallback = pCallback;
02134         break;
02135
02136       case HAL_LPTIM_DIRECTION_UP_CB_ID :
02137         hlptim->DirectionUpCallback = pCallback;
02138         break;
02139
02140       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
02141         hlptim->DirectionDownCallback = pCallback;
02142         break;
02143
02144       default :
02145         /* Return error status */
02146         status =  HAL_ERROR;
02147         break;
02148     }
02149   }
02150   else if (hlptim->State == HAL_LPTIM_STATE_RESET)
02151   {
02152     switch (CallbackID)
02153     {
02154       case HAL_LPTIM_MSPINIT_CB_ID :
02155         hlptim->MspInitCallback = pCallback;
02156         break;
02157
02158       case HAL_LPTIM_MSPDEINIT_CB_ID :
02159         hlptim->MspDeInitCallback = pCallback;
02160         break;
02161
02162       default :
02163         /* Return error status */
02164         status =  HAL_ERROR;
02165         break;
02166     }
02167   }
02168   else
02169   {
02170     /* Return error status */
02171     status =  HAL_ERROR;
02172   }
02173
02174   /* Release Lock */
02175   __HAL_UNLOCK(hlptim);
02176
02177   return status;
02178 }
02179
02180 /**
02181   * @brief  Unregister a LPTIM callback
02182   *         LLPTIM callback is redirected to the weak predefined callback
02183   * @param hlptim LPTIM handle
02184   * @param CallbackID ID of the callback to be unregistered
02185   *        This parameter can be one of the following values:
02186   *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
02187   *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
02188   *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
02189   *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
02190   *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
02191   *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
02192   *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
02193   *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
02194   *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
02195   * @retval status
02196   */
02197 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlptim,
02198                                                HAL_LPTIM_CallbackIDTypeDef CallbackID)
02199 {
02200   HAL_StatusTypeDef status = HAL_OK;
02201
02202   /* Process locked */
02203   __HAL_LOCK(hlptim);
02204
02205   if (hlptim->State == HAL_LPTIM_STATE_READY)
02206   {
02207     switch (CallbackID)
02208     {
02209       case HAL_LPTIM_MSPINIT_CB_ID :
02210         /* Legacy weak MspInit Callback */
02211         hlptim->MspInitCallback = HAL_LPTIM_MspInit;
02212         break;
02213
02214       case HAL_LPTIM_MSPDEINIT_CB_ID :
02215         /* Legacy weak Msp DeInit Callback */
02216         hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
02217         break;
02218
02219       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
02220         /* Legacy weak Compare match Callback */
02221         hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
02222         break;
02223
02224       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
02225         /* Legacy weak Auto-reload match Callback */
02226         hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
02227         break;
02228
02229       case HAL_LPTIM_TRIGGER_CB_ID :
02230         /* Legacy weak External trigger event detection Callback */
02231         hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
02232         break;
02233
02234       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
02235         /* Legacy weak Compare register write complete Callback */
02236         hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
02237         break;
02238
02239       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
02240         /* Legacy weak Auto-reload register write complete Callback */
02241         hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
02242         break;
02243
02244       case HAL_LPTIM_DIRECTION_UP_CB_ID :
02245         /* Legacy weak Up-counting direction change Callback */
02246         hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
02247         break;
02248
02249       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
02250         /* Legacy weak Down-counting direction change Callback */
02251         hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
02252         break;
02253
02254       default :
02255         /* Return error status */
02256         status =  HAL_ERROR;
02257         break;
02258     }
02259   }
02260   else if (hlptim->State == HAL_LPTIM_STATE_RESET)
02261   {
02262     switch (CallbackID)
02263     {
02264       case HAL_LPTIM_MSPINIT_CB_ID :
02265         /* Legacy weak MspInit Callback */
02266         hlptim->MspInitCallback = HAL_LPTIM_MspInit;
02267         break;
02268
02269       case HAL_LPTIM_MSPDEINIT_CB_ID :
02270         /* Legacy weak Msp DeInit Callback */
02271         hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
02272         break;
02273
02274       default :
02275         /* Return error status */
02276         status =  HAL_ERROR;
02277         break;
02278     }
02279   }
02280   else
02281   {
02282     /* Return error status */
02283     status =  HAL_ERROR;
02284   }
02285
02286   /* Release Lock */
02287   __HAL_UNLOCK(hlptim);
02288
02289   return status;
02290 }
02291 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
02292
02293 /**
02294   * @}
02295   */
02296
02297 /** @defgroup LPTIM_Group5 Peripheral State functions
02298   *  @brief   Peripheral State functions.
02299   *
02300 @verbatim
02301   ==============================================================================
02302                       ##### Peripheral State functions #####
02303   ==============================================================================
02304     [..]
02305     This subsection permits to get in run-time the status of the peripheral.
02306
02307 @endverbatim
02308   * @{
02309   */
02310
02311 /**
02312   * @brief  Return the LPTIM handle state.
02313   * @param  hlptim LPTIM handle
02314   * @retval HAL state
02315   */
02316 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
02317 {
02318   /* Return LPTIM handle state */
02319   return hlptim->State;
02320 }
02321
02322 /**
02323   * @}
02324   */
02325
02326
02327 /**
02328   * @}
02329   */
02330
02331 /* Private functions ---------------------------------------------------------*/
02332
02333 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
02334   * @{
02335   */
02336 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
02337 /**
02338   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
02339   * @param  lptim pointer to a LPTIM_HandleTypeDef structure that contains
02340   *                the configuration information for LPTIM module.
02341   * @retval None
02342   */
02343 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
02344 {
02345   /* Reset the LPTIM callback to the legacy weak callbacks */
02346   lptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;
02347   lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
02348   lptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;
02349   lptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;
02350   lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
02351   lptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;
02352   lptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;
02353 }
02354 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
02355
02356 /**
02357   * @brief  LPTimer Wait for flag set
02358   * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
02359   *                the configuration information for LPTIM module.
02360   * @param  flag   The lptim flag
02361   * @retval HAL status
02362   */
02363 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
02364 {
02365   HAL_StatusTypeDef result = HAL_OK;
02366   uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
02367   do
02368   {
02369     count--;
02370     if (count == 0UL)
02371     {
02372       result = HAL_TIMEOUT;
02373     }
02374   } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
02375
02376   return result;
02377 }
02378
02379 /**
02380   * @brief  Disable LPTIM HW instance.
02381   * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
02382   *                the configuration information for LPTIM module.
02383   * @note   The following sequence is required to solve LPTIM disable HW limitation.
02384   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
02385   *         stuck in LPTIM interrupt when entering Stop mode" section.
02386   * @retval None
02387   */
02388 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
02389 {
02390   uint32_t tmpclksource = 0;
02391   uint32_t tmpIER;
02392   uint32_t tmpCFGR;
02393   uint32_t tmpCMP;
02394   uint32_t tmpARR;
02395   uint32_t primask_bit;
02396   uint32_t tmpCFGR2;
02397
02398   /* Enter critical section */
02399   primask_bit = __get_PRIMASK();
02400   __set_PRIMASK(1) ;
02401
02402   /*********** Save LPTIM Config ***********/
02403   /* Save LPTIM source clock */
02404   switch ((uint32_t)hlptim->Instance)
02405   {
02406     case LPTIM1_BASE:
02407       tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
02408       break;
02409 #if defined(LPTIM2)
02410     case LPTIM2_BASE:
02411       tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
02412       break;
02413 #endif /* LPTIM2 */
02414     default:
02415       break;
02416   }
02417
02418   /* Save LPTIM configuration registers */
02419   tmpIER = hlptim->Instance->IER;
02420   tmpCFGR = hlptim->Instance->CFGR;
02421   tmpCMP = hlptim->Instance->CMP;
02422   tmpARR = hlptim->Instance->ARR;
02423   tmpCFGR2 = hlptim->Instance->CFGR2;
02424
02425   /*********** Reset LPTIM ***********/
02426   switch ((uint32_t)hlptim->Instance)
02427   {
02428     case LPTIM1_BASE:
02429       __HAL_RCC_LPTIM1_FORCE_RESET();
02430       __HAL_RCC_LPTIM1_RELEASE_RESET();
02431       break;
02432 #if defined(LPTIM2)
02433     case LPTIM2_BASE:
02434       __HAL_RCC_LPTIM2_FORCE_RESET();
02435       __HAL_RCC_LPTIM2_RELEASE_RESET();
02436       break;
02437 #endif /* LPTIM2 */
02438     default:
02439       break;
02440   }
02441
02442   /*********** Restore LPTIM Config ***********/
02443   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
02444   {
02445     /* Force LPTIM source kernel clock from APB */
02446     switch ((uint32_t)hlptim->Instance)
02447     {
02448       case LPTIM1_BASE:
02449         __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
02450         break;
02451 #if defined(LPTIM2)
02452       case LPTIM2_BASE:
02453         __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1);
02454         break;
02455 #endif /* LPTIM2 */
02456       default:
02457         break;
02458     }
02459
02460     if (tmpCMP != 0UL)
02461     {
02462       /* Restore CMP register (LPTIM should be enabled first) */
02463       hlptim->Instance->CR |= LPTIM_CR_ENABLE;
02464       hlptim->Instance->CMP = tmpCMP;
02465
02466       /* Wait for the completion of the write operation to the LPTIM_CMP register */
02467       if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
02468       {
02469         hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
02470       }
02471       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
02472     }
02473
02474     if (tmpARR != 0UL)
02475     {
02476       /* Restore ARR register (LPTIM should be enabled first) */
02477       hlptim->Instance->CR |= LPTIM_CR_ENABLE;
02478       hlptim->Instance->ARR = tmpARR;
02479
02480       /* Wait for the completion of the write operation to the LPTIM_ARR register */
02481       if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
02482       {
02483         hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
02484       }
02485
02486       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
02487     }
02488
02489     /* Restore LPTIM source kernel clock */
02490     switch ((uint32_t)hlptim->Instance)
02491     {
02492       case LPTIM1_BASE:
02493         __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
02494         break;
02495 #if defined(LPTIM2)
02496       case LPTIM2_BASE:
02497         __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
02498         break;
02499 #endif /* LPTIM2 */
02500       default:
02501         break;
02502     }
02503   }
02504
02505   /* Restore configuration registers (LPTIM should be disabled first) */
02506   hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
02507   hlptim->Instance->IER = tmpIER;
02508   hlptim->Instance->CFGR = tmpCFGR;
02509   hlptim->Instance->CFGR2 = tmpCFGR2;
02510
02511   /* Exit critical section: restore previous priority mask */
02512   __set_PRIMASK(primask_bit);
02513 }
02514 /**
02515   * @}
02516   */
02517 #endif /* LPTIM1 || LPTIM2 */
02518
02519 #endif /* HAL_LPTIM_MODULE_ENABLED */
02520 /**
02521   * @}
02522   */
02523
02524 /**
02525   * @}
02526   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_lptim.h Source File

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stm32g0xx_hal_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_lptim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPTIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_LPTIM_H
00021 #define STM32G0xx_HAL_LPTIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 #if defined (LPTIM1) || defined (LPTIM2)
00035
00036 /** @addtogroup LPTIM
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
00042   * @{
00043   */
00044 #define LPTIM_EXTI_LINE_LPTIM1  EXTI_IMR1_IM29  /*!< External interrupt line 29 Connected to the LPTIM1 EXTI Line */
00045 #define LPTIM_EXTI_LINE_LPTIM2  EXTI_IMR1_IM30  /*!< External interrupt line 30 Connected to the LPTIM2 EXTI Line */
00046
00047 /**
00048   * @brief  LPTIM Clock configuration definition
00049   */
00050 typedef struct
00051 {
00052   uint32_t Source;         /*!< Selects the clock source.
00053                            This parameter can be a value of @ref LPTIM_Clock_Source   */
00054
00055   uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
00056                            This parameter can be a value of @ref LPTIM_Clock_Prescaler */
00057
00058 } LPTIM_ClockConfigTypeDef;
00059
00060 /**
00061   * @brief  LPTIM Clock configuration definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
00066                            if the ULPTIM input is selected.
00067                            Note: This parameter is used only when Ultra low power clock source is used.
00068                            Note: If the polarity is configured on 'both edges', an auxiliary clock
00069                            (one of the Low power oscillator) must be active.
00070                            This parameter can be a value of @ref LPTIM_Clock_Polarity */
00071
00072   uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
00073                            Note: This parameter is used only when Ultra low power clock source is used.
00074                            This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
00075
00076 } LPTIM_ULPClockConfigTypeDef;
00077
00078 /**
00079   * @brief  LPTIM Trigger configuration definition
00080   */
00081 typedef struct
00082 {
00083   uint32_t Source;        /*!< Selects the Trigger source.
00084                           This parameter can be a value of @ref LPTIM_Trigger_Source */
00085
00086   uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
00087                           Note: This parameter is used only when an external trigger is used.
00088                           This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
00089
00090   uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
00091                           Note: This parameter is used only when an external trigger is used.
00092                           This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
00093 } LPTIM_TriggerConfigTypeDef;
00094
00095 /**
00096   * @brief  LPTIM Initialization Structure definition
00097   */
00098 typedef struct
00099 {
00100   LPTIM_ClockConfigTypeDef     Clock;             /*!< Specifies the clock parameters */
00101
00102   LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
00103
00104   LPTIM_TriggerConfigTypeDef   Trigger;           /*!< Specifies the Trigger parameters */
00105
00106   uint32_t                     OutputPolarity;    /*!< Specifies the Output polarity.
00107                                                   This parameter can be a value of @ref LPTIM_Output_Polarity */
00108
00109   uint32_t                     UpdateMode;        /*!< Specifies whether the update of the autoreload and the compare
00110                                                   values is done immediately or after the end of current period.
00111                                                   This parameter can be a value of @ref LPTIM_Updating_Mode */
00112
00113   uint32_t                     CounterSource;     /*!< Specifies whether the counter is incremented each internal event
00114                                                   or each external event.
00115                                                   This parameter can be a value of @ref LPTIM_Counter_Source */
00116
00117   uint32_t                     Input1Source;      /*!< Specifies source selected for input1 (GPIO or comparator output).
00118                                                   This parameter can be a value of @ref LPTIM_Input1_Source */
00119
00120   uint32_t                     Input2Source;      /*!< Specifies source selected for input2 (GPIO or comparator output).
00121                                                   Note: This parameter is used only for encoder feature so is used only
00122                                                   for LPTIM1 instance.
00123                                                   This parameter can be a value of @ref LPTIM_Input2_Source */
00124 } LPTIM_InitTypeDef;
00125
00126 /**
00127   * @brief  HAL LPTIM State structure definition
00128   */
00129 typedef enum
00130 {
00131   HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00132   HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00133   HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
00134   HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
00135   HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */
00136 } HAL_LPTIM_StateTypeDef;
00137
00138 /**
00139   * @brief  LPTIM handle Structure definition
00140   */
00141 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00142 typedef struct __LPTIM_HandleTypeDef
00143 #else
00144 typedef struct
00145 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00146 {
00147   LPTIM_TypeDef                 *Instance;         /*!< Register base address     */
00148
00149   LPTIM_InitTypeDef              Init;             /*!< LPTIM required parameters */
00150
00151   HAL_StatusTypeDef              Status;           /*!< LPTIM peripheral status   */
00152
00153   HAL_LockTypeDef                Lock;             /*!< LPTIM locking object      */
00154
00155   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
00156
00157 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00158   void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< LPTIM Base Msp Init Callback                 */
00159   void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);          /*!< LPTIM Base Msp DeInit Callback               */
00160   void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare match Callback                       */
00161   void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload match Callback                   */
00162   void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< External trigger event detection Callback    */
00163   void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare register write complete Callback     */
00164   void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload register write complete Callback */
00165   void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Up-counting direction change Callback        */
00166   void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim);      /*!< Down-counting direction change Callback      */
00167 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00168 } LPTIM_HandleTypeDef;
00169
00170 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00171 /**
00172   * @brief  HAL LPTIM Callback ID enumeration definition
00173   */
00174 typedef enum
00175 {
00176   HAL_LPTIM_MSPINIT_CB_ID          = 0x00U,    /*!< LPTIM Base Msp Init Callback ID                  */
00177   HAL_LPTIM_MSPDEINIT_CB_ID        = 0x01U,    /*!< LPTIM Base Msp DeInit Callback ID                */
00178   HAL_LPTIM_COMPARE_MATCH_CB_ID    = 0x02U,    /*!< Compare match Callback ID                        */
00179   HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,    /*!< Auto-reload match Callback ID                    */
00180   HAL_LPTIM_TRIGGER_CB_ID          = 0x04U,    /*!< External trigger event detection Callback ID     */
00181   HAL_LPTIM_COMPARE_WRITE_CB_ID    = 0x05U,    /*!< Compare register write complete Callback ID      */
00182   HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U,    /*!< Auto-reload register write complete Callback ID  */
00183   HAL_LPTIM_DIRECTION_UP_CB_ID     = 0x07U,    /*!< Up-counting direction change Callback ID         */
00184   HAL_LPTIM_DIRECTION_DOWN_CB_ID   = 0x08U,    /*!< Down-counting direction change Callback ID       */
00185 } HAL_LPTIM_CallbackIDTypeDef;
00186
00187 /**
00188   * @brief  HAL TIM Callback pointer definition
00189   */
00190 typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< pointer to the LPTIM callback function */
00191
00192 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00193 /**
00194   * @}
00195   */
00196
00197 /* Exported constants --------------------------------------------------------*/
00198 /** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
00199   * @{
00200   */
00201
00202 /** @defgroup LPTIM_Clock_Source LPTIM Clock Source
00203   * @{
00204   */
00205 #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        0x00000000U
00206 #define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
00212   * @{
00213   */
00214 #define LPTIM_PRESCALER_DIV1                    0x00000000U
00215 #define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
00216 #define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
00217 #define LPTIM_PRESCALER_DIV8                    (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
00218 #define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
00219 #define LPTIM_PRESCALER_DIV32                   (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
00220 #define LPTIM_PRESCALER_DIV64                   (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
00221 #define LPTIM_PRESCALER_DIV128                  LPTIM_CFGR_PRESC
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
00227   * @{
00228   */
00229
00230 #define LPTIM_OUTPUTPOLARITY_HIGH               0x00000000U
00231 #define LPTIM_OUTPUTPOLARITY_LOW                LPTIM_CFGR_WAVPOL
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
00237   * @{
00238   */
00239 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  0x00000000U
00240 #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
00241 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
00242 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
00248   * @{
00249   */
00250 #define LPTIM_CLOCKPOLARITY_RISING              0x00000000U
00251 #define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
00252 #define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
00258   * @{
00259   */
00260 #define LPTIM_TRIGSOURCE_SOFTWARE               0x0000FFFFU
00261 #define LPTIM_TRIGSOURCE_0                      0x00000000U
00262 #define LPTIM_TRIGSOURCE_1                      LPTIM_CFGR_TRIGSEL_0
00263 #define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
00264 #define LPTIM_TRIGSOURCE_3                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
00265 #define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
00266 #define LPTIM_TRIGSOURCE_5                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
00267 #define LPTIM_TRIGSOURCE_6                      (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
00268 #define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
00274   * @{
00275   */
00276 #define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
00277 #define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
00278 #define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
00284   * @{
00285   */
00286 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  0x00000000U
00287 #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
00288 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
00289 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
00295   * @{
00296   */
00297
00298 #define LPTIM_UPDATE_IMMEDIATE                  0x00000000U
00299 #define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup LPTIM_Counter_Source LPTIM Counter Source
00305   * @{
00306   */
00307
00308 #define LPTIM_COUNTERSOURCE_INTERNAL            0x00000000U
00309 #define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
00315   * @{
00316   */
00317
00318 #define LPTIM_INPUT1SOURCE_GPIO          0x00000000U                                   /*!< For LPTIM1 and LPTIM2 */
00319 #define LPTIM_INPUT1SOURCE_COMP1         LPTIM_CFGR2_IN1SEL_0                          /*!< For LPTIM1 and LPTIM2 */
00320 #define LPTIM_INPUT1SOURCE_COMP2         LPTIM_CFGR2_IN1SEL_1                          /*!< For LPTIM2 */
00321 #define LPTIM_INPUT1SOURCE_COMP1_COMP2   (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
00327   * @{
00328   */
00329
00330 #define LPTIM_INPUT2SOURCE_GPIO         0x00000000U                    /*!< For LPTIM1 */
00331 #define LPTIM_INPUT2SOURCE_COMP2        LPTIM_CFGR2_IN2SEL_0           /*!< For LPTIM1 */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
00337   * @{
00338   */
00339
00340 #define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
00341 #define LPTIM_FLAG_UP                            LPTIM_ISR_UP
00342 #define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
00343 #define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
00344 #define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
00345 #define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
00346 #define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
00352   * @{
00353   */
00354 #define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
00355 #define LPTIM_IT_UP                              LPTIM_IER_UPIE
00356 #define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
00357 #define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
00358 #define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
00359 #define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
00360 #define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 /* Exported macros -----------------------------------------------------------*/
00370 /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
00371   * @{
00372   */
00373
00374 /** @brief Reset LPTIM handle state.
00375   * @param  __HANDLE__ LPTIM handle
00376   * @retval None
00377   */
00378 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00379 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
00380                                                         (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
00381                                                         (__HANDLE__)->MspInitCallback   = NULL;                  \
00382                                                         (__HANDLE__)->MspDeInitCallback = NULL;                  \
00383                                                       } while(0)
00384 #else
00385 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
00386 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00387
00388 /**
00389   * @brief  Enable the LPTIM peripheral.
00390   * @param  __HANDLE__ LPTIM handle
00391   * @retval None
00392   */
00393 #define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
00394
00395 /**
00396   * @brief  Disable the LPTIM peripheral.
00397   * @param  __HANDLE__ LPTIM handle
00398   * @note   The following sequence is required to solve LPTIM disable HW limitation.
00399   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
00400   *         stuck in LPTIM interrupt when entering Stop mode" section.
00401   * @note   Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
00402   *         check for TIMEOUT.
00403   * @retval None
00404   */
00405 #define __HAL_LPTIM_DISABLE(__HANDLE__)   LPTIM_Disable(__HANDLE__)
00406
00407 /**
00408   * @brief  Start the LPTIM peripheral in Continuous mode.
00409   * @param  __HANDLE__ LPTIM handle
00410   * @retval None
00411   */
00412 #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
00413 /**
00414   * @brief  Start the LPTIM peripheral in single mode.
00415   * @param  __HANDLE__ LPTIM handle
00416   * @retval None
00417   */
00418 #define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
00419
00420 /**
00421   * @brief  Reset the LPTIM Counter register in synchronous mode.
00422   * @param  __HANDLE__ LPTIM handle
00423   * @retval None
00424   */
00425 #define __HAL_LPTIM_RESET_COUNTER(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_COUNTRST)
00426
00427 /**
00428   * @brief  Reset after read of the LPTIM Counter register in asynchronous mode.
00429   * @param  __HANDLE__ LPTIM handle
00430   * @retval None
00431   */
00432 #define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_RSTARE)
00433
00434 /**
00435   * @brief  Write the passed parameter in the Autoreload register.
00436   * @param  __HANDLE__ LPTIM handle
00437   * @param  __VALUE__ Autoreload value
00438   * @retval None
00439   * @note   The ARR register can only be modified when the LPTIM instance is enabled.
00440   */
00441 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
00442
00443 /**
00444   * @brief  Write the passed parameter in the Compare register.
00445   * @param  __HANDLE__ LPTIM handle
00446   * @param  __VALUE__ Compare value
00447   * @retval None
00448   * @note   The CMP register can only be modified when the LPTIM instance is enabled.
00449   */
00450 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
00451
00452 /**
00453   * @brief  Check whether the specified LPTIM flag is set or not.
00454   * @param  __HANDLE__ LPTIM handle
00455   * @param  __FLAG__ LPTIM flag to check
00456   *            This parameter can be a value of:
00457   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00458   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00459   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00460   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00461   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00462   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00463   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00464   * @retval The state of the specified flag (SET or RESET).
00465   */
00466 #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
00467
00468 /**
00469   * @brief  Clear the specified LPTIM flag.
00470   * @param  __HANDLE__ LPTIM handle.
00471   * @param  __FLAG__ LPTIM flag to clear.
00472   *            This parameter can be a value of:
00473   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00474   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00475   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00476   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00477   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00478   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00479   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00480   * @retval None.
00481   */
00482 #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
00483
00484 /**
00485   * @brief  Enable the specified LPTIM interrupt.
00486   * @param  __HANDLE__ LPTIM handle.
00487   * @param  __INTERRUPT__ LPTIM interrupt to set.
00488   *            This parameter can be a value of:
00489   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00490   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00491   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00492   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00493   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00494   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00495   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00496   * @retval None.
00497   * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
00498   */
00499 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
00500
00501 /**
00502   * @brief  Disable the specified LPTIM interrupt.
00503   * @param  __HANDLE__ LPTIM handle.
00504   * @param  __INTERRUPT__ LPTIM interrupt to set.
00505   *            This parameter can be a value of:
00506   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00507   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00508   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00509   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00510   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00511   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00512   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00513   * @retval None.
00514   * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
00515   */
00516 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
00517
00518 /**
00519   * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
00520   * @param  __HANDLE__ LPTIM handle.
00521   * @param  __INTERRUPT__ LPTIM interrupt to check.
00522   *            This parameter can be a value of:
00523   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00524   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00525   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00526   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00527   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00528   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00529   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00530   * @retval Interrupt status.
00531   */
00532
00533 #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
00534                                                                 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00535
00536 /**
00537   * @brief  Enable the LPTIM1 EXTI line in interrupt mode.
00538   * @retval None
00539   */
00540 #define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()            (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
00541
00542 /**
00543   * @brief  Disable the LPTIM1 EXTI line in interrupt mode.
00544   * @retval None
00545   */
00546 #define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()           (EXTI->IMR1\
00547                                                         &= ~(LPTIM_EXTI_LINE_LPTIM1))
00548
00549 /**
00550   * @brief  Enable the LPTIM1 EXTI line in event mode.
00551   * @retval None
00552   */
00553 #define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)
00554
00555 /**
00556   * @brief  Disable the LPTIM1 EXTI line in event mode.
00557   * @retval None
00558   */
00559 #define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT()        (EXTI->EMR1\
00560                                                         &= ~(LPTIM_EXTI_LINE_LPTIM1))
00561
00562 /**
00563   * @brief  Enable the LPTIM2 EXTI line in interrupt mode.
00564   * @retval None
00565   */
00566 #define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()            (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
00567
00568 /**
00569   * @brief  Disable the LPTIM2 EXTI line in interrupt mode.
00570   * @retval None
00571   */
00572 #define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()           (EXTI->IMR1\
00573                                                         &= ~(LPTIM_EXTI_LINE_LPTIM2))
00574
00575 /**
00576   * @brief  Enable the LPTIM2 EXTI line in event mode.
00577   * @retval None
00578   */
00579 #define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)
00580
00581 /**
00582   * @brief  Disable the LPTIM2 EXTI line in event mode.
00583   * @retval None
00584   */
00585 #define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT()        (EXTI->EMR1\
00586                                                         &= ~(LPTIM_EXTI_LINE_LPTIM2))
00587
00588 /**
00589   * @}
00590   */
00591
00592 /* Exported functions --------------------------------------------------------*/
00593 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00594   * @{
00595   */
00596
00597 /** @addtogroup LPTIM_Exported_Functions_Group1
00598   *  @brief    Initialization and Configuration functions.
00599   * @{
00600   */
00601 /* Initialization/de-initialization functions  ********************************/
00602 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
00603 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
00604
00605 /* MSP functions  *************************************************************/
00606 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
00607 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
00608 /**
00609   * @}
00610   */
00611
00612 /** @addtogroup LPTIM_Exported_Functions_Group2
00613   *  @brief   Start-Stop operation functions.
00614   * @{
00615   */
00616 /* Start/Stop operation functions  *********************************************/
00617 /* ################################# PWM Mode ################################*/
00618 /* Blocking mode: Polling */
00619 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00620 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
00621 /* Non-Blocking mode: Interrupt */
00622 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00623 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00624
00625 /* ############################# One Pulse Mode ##############################*/
00626 /* Blocking mode: Polling */
00627 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00628 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
00629 /* Non-Blocking mode: Interrupt */
00630 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00631 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00632
00633 /* ############################## Set once Mode ##############################*/
00634 /* Blocking mode: Polling */
00635 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00636 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
00637 /* Non-Blocking mode: Interrupt */
00638 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00639 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00640
00641 /* ############################### Encoder Mode ##############################*/
00642 /* Blocking mode: Polling */
00643 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00644 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
00645 /* Non-Blocking mode: Interrupt */
00646 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00647 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00648
00649 /* ############################# Time out  Mode ##############################*/
00650 /* Blocking mode: Polling */
00651 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00652 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
00653 /* Non-Blocking mode: Interrupt */
00654 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00655 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00656
00657 /* ############################## Counter Mode ###############################*/
00658 /* Blocking mode: Polling */
00659 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00660 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
00661 /* Non-Blocking mode: Interrupt */
00662 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00663 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00664 /**
00665   * @}
00666   */
00667
00668 /** @addtogroup LPTIM_Exported_Functions_Group3
00669   *  @brief  Read operation functions.
00670   * @{
00671   */
00672 /* Reading operation functions ************************************************/
00673 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
00674 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
00675 uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim);
00676 /**
00677   * @}
00678   */
00679
00680 /** @addtogroup LPTIM_Exported_Functions_Group4
00681   *  @brief  LPTIM IRQ handler and callback functions.
00682   * @{
00683   */
00684 /* LPTIM IRQ functions  *******************************************************/
00685 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
00686
00687 /* CallBack functions  ********************************************************/
00688 void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
00689 void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
00690 void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
00691 void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
00692 void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
00693 void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
00694 void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
00695
00696 /* Callbacks Register/UnRegister functions  ***********************************/
00697 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00698 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
00699                                              pLPTIM_CallbackTypeDef pCallback);
00700 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
00701 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00702 /**
00703   * @}
00704   */
00705
00706 /** @addtogroup LPTIM_Group5
00707   *  @brief   Peripheral State functions.
00708   * @{
00709   */
00710 /* Peripheral State functions  ************************************************/
00711 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
00712 /**
00713   * @}
00714   */
00715
00716 /**
00717   * @}
00718   */
00719
00720 /* Private types -------------------------------------------------------------*/
00721 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00722   * @{
00723   */
00724
00725 /**
00726   * @}
00727   */
00728
00729 /* Private variables ---------------------------------------------------------*/
00730 /** @defgroup LPTIM_Private_Variables LPTIM Private Variables
00731   * @{
00732   */
00733
00734 /**
00735   * @}
00736   */
00737
00738 /* Private constants ---------------------------------------------------------*/
00739 /** @defgroup LPTIM_Private_Constants LPTIM Private Constants
00740   * @{
00741   */
00742
00743 /**
00744   * @}
00745   */
00746
00747 /* Private macros ------------------------------------------------------------*/
00748 /** @defgroup LPTIM_Private_Macros LPTIM Private Macros
00749   * @{
00750   */
00751
00752 #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
00753                                                  ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
00754
00755
00756 #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
00757                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
00758                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
00759                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
00760                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
00761                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
00762                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
00763                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
00764
00765 #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
00766
00767 #define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
00768                                                  ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
00769
00770 #define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
00771                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
00772                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
00773                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
00774
00775 #define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
00776                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
00777                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
00778
00779 #define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00780                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00781                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00782                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00783                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00784                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00785                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
00786                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
00787                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_7))
00788
00789 #define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
00790                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
00791                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
00792
00793 #define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
00794                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
00795                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
00796                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
00797
00798 #define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
00799                                                  ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
00800
00801 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
00802                                                  ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
00803
00804 #define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((0x00000001UL <= (__AUTORELOAD__)) &&\
00805                                                  ((__AUTORELOAD__) <= 0x0000FFFFUL))
00806
00807 #define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)
00808
00809 #define IS_LPTIM_PERIOD(__PERIOD__)             ((0x00000001UL <= (__PERIOD__)) &&\
00810                                                  ((__PERIOD__) <= 0x0000FFFFUL))
00811
00812 #define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)
00813
00814 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)  \
00815   ((((__INSTANCE__) == LPTIM1) &&                       \
00816     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00817      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
00818    ||                                                   \
00819    (((__INSTANCE__) == LPTIM2) &&                       \
00820     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00821      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
00822      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
00823      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
00824
00825 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
00826   (((__INSTANCE__) == LPTIM1) &&                       \
00827    (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
00828     ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
00829
00830 /**
00831   * @}
00832   */
00833
00834 /* Private functions ---------------------------------------------------------*/
00835 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00836   * @{
00837   */
00838 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
00839 /**
00840   * @}
00841   */
00842
00843 /**
00844   * @}
00845   */
00846
00847 #endif /* LPTIM1 || LPTIM2 */
00848 /**
00849   * @}
00850   */
00851
00852 #ifdef __cplusplus
00853 }
00854 #endif
00855
00856 #endif /* STM32G0xx_HAL_LPTIM_H */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pcd.c Source File

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stm32g0xx_hal_pcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @brief   PCD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2018 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                     ##### How to use this driver #####
00027   ==============================================================================
00028     [..]
00029       The PCD HAL driver can be used as follows:
00030
00031      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00032          PCD_HandleTypeDef  hpcd;
00033
00034      (#) Fill parameters of Init structure in HCD handle
00035
00036      (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
00037
00038      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00039          (##) Enable the PCD/USB Low Level interface clock using
00040               (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
00041
00042          (##) Initialize the related GPIO clocks
00043          (##) Configure PCD pin-out
00044          (##) Configure PCD NVIC interrupt
00045
00046      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00047          (##) hpcd.pData = pdev;
00048
00049      (#)Enable PCD transmission and reception:
00050          (##) HAL_PCD_Start();
00051
00052   @endverbatim
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32g0xx_hal.h"
00058
00059 /** @addtogroup STM32G0xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup PCD PCD
00064   * @brief PCD HAL module driver
00065   * @{
00066   */
00067
00068 #ifdef HAL_PCD_MODULE_ENABLED
00069
00070 #if defined (USB_DRD_FS)
00071
00072 /* Private types -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private constants ---------------------------------------------------------*/
00075 /* Private macros ------------------------------------------------------------*/
00076 /** @defgroup PCD_Private_Macros PCD Private Macros
00077   * @{
00078   */
00079 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00080 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00081 /**
00082   * @}
00083   */
00084
00085 /* Private functions prototypes ----------------------------------------------*/
00086 /** @defgroup PCD_Private_Functions PCD Private Functions
00087   * @{
00088   */
00089
00090 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
00091 #if (USE_USB_DOUBLE_BUFFER == 1U)
00092 static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
00093 static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
00094 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Exported functions --------------------------------------------------------*/
00101 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00102   * @{
00103   */
00104
00105 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00106   *  @brief    Initialization and Configuration functions
00107   *
00108 @verbatim
00109  ===============================================================================
00110             ##### Initialization and de-initialization functions #####
00111  ===============================================================================
00112     [..]  This section provides functions allowing to:
00113
00114 @endverbatim
00115   * @{
00116   */
00117
00118 /**
00119   * @brief  Initializes the PCD according to the specified
00120   *         parameters in the PCD_InitTypeDef and initialize the associated handle.
00121   * @param  hpcd PCD handle
00122   * @retval HAL status
00123   */
00124 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00125 {
00126   uint8_t i;
00127
00128   /* Check the PCD handle allocation */
00129   if (hpcd == NULL)
00130   {
00131     return HAL_ERROR;
00132   }
00133
00134   /* Check the parameters */
00135   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00136
00137   if (hpcd->State == HAL_PCD_STATE_RESET)
00138   {
00139     /* Allocate lock resource and initialize it */
00140     hpcd->Lock = HAL_UNLOCKED;
00141
00142 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00143     hpcd->SOFCallback = HAL_PCD_SOFCallback;
00144     hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
00145     hpcd->ResetCallback = HAL_PCD_ResetCallback;
00146     hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
00147     hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
00148     hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
00149     hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
00150     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
00151     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
00152     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
00153     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
00154     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
00155     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
00156
00157     if (hpcd->MspInitCallback == NULL)
00158     {
00159       hpcd->MspInitCallback = HAL_PCD_MspInit;
00160     }
00161
00162     /* Init the low level hardware */
00163     hpcd->MspInitCallback(hpcd);
00164 #else
00165     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00166     HAL_PCD_MspInit(hpcd);
00167 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
00168   }
00169
00170   hpcd->State = HAL_PCD_STATE_BUSY;
00171
00172   /* DMA Not supported for FS instance, Force to Zero */
00173   hpcd->Init.dma_enable = 0U;
00174
00175   /* Disable the Interrupts */
00176   __HAL_PCD_DISABLE(hpcd);
00177
00178   /* Init endpoints structures */
00179   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00180   {
00181     /* Init ep structure */
00182     hpcd->IN_ep[i].is_in = 1U;
00183     hpcd->IN_ep[i].num = i;
00184     hpcd->IN_ep[i].tx_fifo_num = i;
00185     /* Control until ep is activated */
00186     hpcd->IN_ep[i].type = EP_TYPE_CTRL;
00187     hpcd->IN_ep[i].maxpacket = 0U;
00188     hpcd->IN_ep[i].xfer_buff = 0U;
00189     hpcd->IN_ep[i].xfer_len = 0U;
00190   }
00191
00192   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00193   {
00194     hpcd->OUT_ep[i].is_in = 0U;
00195     hpcd->OUT_ep[i].num = i;
00196     /* Control until ep is activated */
00197     hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
00198     hpcd->OUT_ep[i].maxpacket = 0U;
00199     hpcd->OUT_ep[i].xfer_buff = 0U;
00200     hpcd->OUT_ep[i].xfer_len = 0U;
00201   }
00202
00203   /* Init Device */
00204   (void)USB_DevInit(hpcd->Instance, hpcd->Init);
00205
00206   hpcd->USB_Address = 0U;
00207   hpcd->State = HAL_PCD_STATE_READY;
00208
00209   /* Activate LPM */
00210   if (hpcd->Init.lpm_enable == 1U)
00211   {
00212     (void)HAL_PCDEx_ActivateLPM(hpcd);
00213   }
00214
00215   return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  DeInitializes the PCD peripheral.
00220   * @param  hpcd PCD handle
00221   * @retval HAL status
00222   */
00223 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00224 {
00225   /* Check the PCD handle allocation */
00226   if (hpcd == NULL)
00227   {
00228     return HAL_ERROR;
00229   }
00230
00231   hpcd->State = HAL_PCD_STATE_BUSY;
00232
00233   /* Stop Device */
00234   if (USB_StopDevice(hpcd->Instance) != HAL_OK)
00235   {
00236     return HAL_ERROR;
00237   }
00238
00239 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00240   if (hpcd->MspDeInitCallback == NULL)
00241   {
00242     hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
00243   }
00244
00245   /* DeInit the low level hardware */
00246   hpcd->MspDeInitCallback(hpcd);
00247 #else
00248   /* DeInit the low level hardware: CLOCK, NVIC.*/
00249   HAL_PCD_MspDeInit(hpcd);
00250 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00251
00252   hpcd->State = HAL_PCD_STATE_RESET;
00253
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  Initializes the PCD MSP.
00259   * @param  hpcd PCD handle
00260   * @retval None
00261   */
00262 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00263 {
00264   /* Prevent unused argument(s) compilation warning */
00265   UNUSED(hpcd);
00266
00267   /* NOTE : This function should not be modified, when the callback is needed,
00268             the HAL_PCD_MspInit could be implemented in the user file
00269    */
00270 }
00271
00272 /**
00273   * @brief  DeInitializes PCD MSP.
00274   * @param  hpcd PCD handle
00275   * @retval None
00276   */
00277 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00278 {
00279   /* Prevent unused argument(s) compilation warning */
00280   UNUSED(hpcd);
00281
00282   /* NOTE : This function should not be modified, when the callback is needed,
00283             the HAL_PCD_MspDeInit could be implemented in the user file
00284    */
00285 }
00286
00287 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00288 /**
00289   * @brief  Register a User USB PCD Callback
00290   *         To be used instead of the weak predefined callback
00291   * @param  hpcd USB PCD handle
00292   * @param  CallbackID ID of the callback to be registered
00293   *         This parameter can be one of the following values:
00294   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
00295   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
00296   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
00297   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
00298   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
00299   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
00300   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
00301   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
00302   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
00303   * @param  pCallback pointer to the Callback function
00304   * @retval HAL status
00305   */
00306 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
00307                                            HAL_PCD_CallbackIDTypeDef CallbackID,
00308                                            pPCD_CallbackTypeDef pCallback)
00309 {
00310   HAL_StatusTypeDef status = HAL_OK;
00311
00312   if (pCallback == NULL)
00313   {
00314     /* Update the error code */
00315     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00316     return HAL_ERROR;
00317   }
00318   /* Process locked */
00319   __HAL_LOCK(hpcd);
00320
00321   if (hpcd->State == HAL_PCD_STATE_READY)
00322   {
00323     switch (CallbackID)
00324     {
00325       case HAL_PCD_SOF_CB_ID :
00326         hpcd->SOFCallback = pCallback;
00327         break;
00328
00329       case HAL_PCD_SETUPSTAGE_CB_ID :
00330         hpcd->SetupStageCallback = pCallback;
00331         break;
00332
00333       case HAL_PCD_RESET_CB_ID :
00334         hpcd->ResetCallback = pCallback;
00335         break;
00336
00337       case HAL_PCD_SUSPEND_CB_ID :
00338         hpcd->SuspendCallback = pCallback;
00339         break;
00340
00341       case HAL_PCD_RESUME_CB_ID :
00342         hpcd->ResumeCallback = pCallback;
00343         break;
00344
00345       case HAL_PCD_CONNECT_CB_ID :
00346         hpcd->ConnectCallback = pCallback;
00347         break;
00348
00349       case HAL_PCD_DISCONNECT_CB_ID :
00350         hpcd->DisconnectCallback = pCallback;
00351         break;
00352
00353       case HAL_PCD_MSPINIT_CB_ID :
00354         hpcd->MspInitCallback = pCallback;
00355         break;
00356
00357       case HAL_PCD_MSPDEINIT_CB_ID :
00358         hpcd->MspDeInitCallback = pCallback;
00359         break;
00360
00361       default :
00362         /* Update the error code */
00363         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00364         /* Return error status */
00365         status =  HAL_ERROR;
00366         break;
00367     }
00368   }
00369   else if (hpcd->State == HAL_PCD_STATE_RESET)
00370   {
00371     switch (CallbackID)
00372     {
00373       case HAL_PCD_MSPINIT_CB_ID :
00374         hpcd->MspInitCallback = pCallback;
00375         break;
00376
00377       case HAL_PCD_MSPDEINIT_CB_ID :
00378         hpcd->MspDeInitCallback = pCallback;
00379         break;
00380
00381       default :
00382         /* Update the error code */
00383         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00384         /* Return error status */
00385         status =  HAL_ERROR;
00386         break;
00387     }
00388   }
00389   else
00390   {
00391     /* Update the error code */
00392     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00393     /* Return error status */
00394     status =  HAL_ERROR;
00395   }
00396
00397   /* Release Lock */
00398   __HAL_UNLOCK(hpcd);
00399   return status;
00400 }
00401
00402 /**
00403   * @brief  Unregister an USB PCD Callback
00404   *         USB PCD callback is redirected to the weak predefined callback
00405   * @param  hpcd USB PCD handle
00406   * @param  CallbackID ID of the callback to be unregistered
00407   *         This parameter can be one of the following values:
00408   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
00409   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
00410   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
00411   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
00412   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
00413   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
00414   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
00415   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
00416   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
00417   * @retval HAL status
00418   */
00419 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
00420 {
00421   HAL_StatusTypeDef status = HAL_OK;
00422
00423   /* Process locked */
00424   __HAL_LOCK(hpcd);
00425
00426   /* Setup Legacy weak Callbacks  */
00427   if (hpcd->State == HAL_PCD_STATE_READY)
00428   {
00429     switch (CallbackID)
00430     {
00431       case HAL_PCD_SOF_CB_ID :
00432         hpcd->SOFCallback = HAL_PCD_SOFCallback;
00433         break;
00434
00435       case HAL_PCD_SETUPSTAGE_CB_ID :
00436         hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
00437         break;
00438
00439       case HAL_PCD_RESET_CB_ID :
00440         hpcd->ResetCallback = HAL_PCD_ResetCallback;
00441         break;
00442
00443       case HAL_PCD_SUSPEND_CB_ID :
00444         hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
00445         break;
00446
00447       case HAL_PCD_RESUME_CB_ID :
00448         hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
00449         break;
00450
00451       case HAL_PCD_CONNECT_CB_ID :
00452         hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
00453         break;
00454
00455       case HAL_PCD_DISCONNECT_CB_ID :
00456         hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
00457         break;
00458
00459       case HAL_PCD_MSPINIT_CB_ID :
00460         hpcd->MspInitCallback = HAL_PCD_MspInit;
00461         break;
00462
00463       case HAL_PCD_MSPDEINIT_CB_ID :
00464         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
00465         break;
00466
00467       default :
00468         /* Update the error code */
00469         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00470
00471         /* Return error status */
00472         status =  HAL_ERROR;
00473         break;
00474     }
00475   }
00476   else if (hpcd->State == HAL_PCD_STATE_RESET)
00477   {
00478     switch (CallbackID)
00479     {
00480       case HAL_PCD_MSPINIT_CB_ID :
00481         hpcd->MspInitCallback = HAL_PCD_MspInit;
00482         break;
00483
00484       case HAL_PCD_MSPDEINIT_CB_ID :
00485         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
00486         break;
00487
00488       default :
00489         /* Update the error code */
00490         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00491
00492         /* Return error status */
00493         status =  HAL_ERROR;
00494         break;
00495     }
00496   }
00497   else
00498   {
00499     /* Update the error code */
00500     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00501
00502     /* Return error status */
00503     status =  HAL_ERROR;
00504   }
00505
00506   /* Release Lock */
00507   __HAL_UNLOCK(hpcd);
00508   return status;
00509 }
00510
00511 /**
00512   * @brief  Register USB PCD Data OUT Stage Callback
00513   *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
00514   * @param  hpcd PCD handle
00515   * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
00519                                                        pPCD_DataOutStageCallbackTypeDef pCallback)
00520 {
00521   HAL_StatusTypeDef status = HAL_OK;
00522
00523   if (pCallback == NULL)
00524   {
00525     /* Update the error code */
00526     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00527
00528     return HAL_ERROR;
00529   }
00530
00531   /* Process locked */
00532   __HAL_LOCK(hpcd);
00533
00534   if (hpcd->State == HAL_PCD_STATE_READY)
00535   {
00536     hpcd->DataOutStageCallback = pCallback;
00537   }
00538   else
00539   {
00540     /* Update the error code */
00541     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00542
00543     /* Return error status */
00544     status =  HAL_ERROR;
00545   }
00546
00547   /* Release Lock */
00548   __HAL_UNLOCK(hpcd);
00549
00550   return status;
00551 }
00552
00553 /**
00554   * @brief  Unregister the USB PCD Data OUT Stage Callback
00555   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
00556   * @param  hpcd PCD handle
00557   * @retval HAL status
00558   */
00559 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
00560 {
00561   HAL_StatusTypeDef status = HAL_OK;
00562
00563   /* Process locked */
00564   __HAL_LOCK(hpcd);
00565
00566   if (hpcd->State == HAL_PCD_STATE_READY)
00567   {
00568     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
00569   }
00570   else
00571   {
00572     /* Update the error code */
00573     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00574
00575     /* Return error status */
00576     status =  HAL_ERROR;
00577   }
00578
00579   /* Release Lock */
00580   __HAL_UNLOCK(hpcd);
00581
00582   return status;
00583 }
00584
00585 /**
00586   * @brief  Register USB PCD Data IN Stage Callback
00587   *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
00588   * @param  hpcd PCD handle
00589   * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
00590   * @retval HAL status
00591   */
00592 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
00593                                                       pPCD_DataInStageCallbackTypeDef pCallback)
00594 {
00595   HAL_StatusTypeDef status = HAL_OK;
00596
00597   if (pCallback == NULL)
00598   {
00599     /* Update the error code */
00600     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00601
00602     return HAL_ERROR;
00603   }
00604
00605   /* Process locked */
00606   __HAL_LOCK(hpcd);
00607
00608   if (hpcd->State == HAL_PCD_STATE_READY)
00609   {
00610     hpcd->DataInStageCallback = pCallback;
00611   }
00612   else
00613   {
00614     /* Update the error code */
00615     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00616
00617     /* Return error status */
00618     status =  HAL_ERROR;
00619   }
00620
00621   /* Release Lock */
00622   __HAL_UNLOCK(hpcd);
00623
00624   return status;
00625 }
00626
00627 /**
00628   * @brief  Unregister the USB PCD Data IN Stage Callback
00629   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
00630   * @param  hpcd PCD handle
00631   * @retval HAL status
00632   */
00633 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
00634 {
00635   HAL_StatusTypeDef status = HAL_OK;
00636
00637   /* Process locked */
00638   __HAL_LOCK(hpcd);
00639
00640   if (hpcd->State == HAL_PCD_STATE_READY)
00641   {
00642     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
00643   }
00644   else
00645   {
00646     /* Update the error code */
00647     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00648
00649     /* Return error status */
00650     status =  HAL_ERROR;
00651   }
00652
00653   /* Release Lock */
00654   __HAL_UNLOCK(hpcd);
00655
00656   return status;
00657 }
00658
00659 /**
00660   * @brief  Register USB PCD Iso OUT incomplete Callback
00661   *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
00662   * @param  hpcd PCD handle
00663   * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
00664   * @retval HAL status
00665   */
00666 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
00667                                                        pPCD_IsoOutIncpltCallbackTypeDef pCallback)
00668 {
00669   HAL_StatusTypeDef status = HAL_OK;
00670
00671   if (pCallback == NULL)
00672   {
00673     /* Update the error code */
00674     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00675
00676     return HAL_ERROR;
00677   }
00678
00679   /* Process locked */
00680   __HAL_LOCK(hpcd);
00681
00682   if (hpcd->State == HAL_PCD_STATE_READY)
00683   {
00684     hpcd->ISOOUTIncompleteCallback = pCallback;
00685   }
00686   else
00687   {
00688     /* Update the error code */
00689     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00690
00691     /* Return error status */
00692     status =  HAL_ERROR;
00693   }
00694
00695   /* Release Lock */
00696   __HAL_UNLOCK(hpcd);
00697
00698   return status;
00699 }
00700
00701 /**
00702   * @brief  Unregister the USB PCD Iso OUT incomplete Callback
00703   *         USB PCD Iso OUT incomplete Callback is redirected
00704   *         to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
00705   * @param  hpcd PCD handle
00706   * @retval HAL status
00707   */
00708 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
00709 {
00710   HAL_StatusTypeDef status = HAL_OK;
00711
00712   /* Process locked */
00713   __HAL_LOCK(hpcd);
00714
00715   if (hpcd->State == HAL_PCD_STATE_READY)
00716   {
00717     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
00718   }
00719   else
00720   {
00721     /* Update the error code */
00722     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00723
00724     /* Return error status */
00725     status =  HAL_ERROR;
00726   }
00727
00728   /* Release Lock */
00729   __HAL_UNLOCK(hpcd);
00730
00731   return status;
00732 }
00733
00734 /**
00735   * @brief  Register USB PCD Iso IN incomplete Callback
00736   *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
00737   * @param  hpcd PCD handle
00738   * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
00739   * @retval HAL status
00740   */
00741 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
00742                                                       pPCD_IsoInIncpltCallbackTypeDef pCallback)
00743 {
00744   HAL_StatusTypeDef status = HAL_OK;
00745
00746   if (pCallback == NULL)
00747   {
00748     /* Update the error code */
00749     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00750
00751     return HAL_ERROR;
00752   }
00753
00754   /* Process locked */
00755   __HAL_LOCK(hpcd);
00756
00757   if (hpcd->State == HAL_PCD_STATE_READY)
00758   {
00759     hpcd->ISOINIncompleteCallback = pCallback;
00760   }
00761   else
00762   {
00763     /* Update the error code */
00764     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00765
00766     /* Return error status */
00767     status =  HAL_ERROR;
00768   }
00769
00770   /* Release Lock */
00771   __HAL_UNLOCK(hpcd);
00772
00773   return status;
00774 }
00775
00776 /**
00777   * @brief  Unregister the USB PCD Iso IN incomplete Callback
00778   *         USB PCD Iso IN incomplete Callback is redirected
00779   *         to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
00780   * @param  hpcd PCD handle
00781   * @retval HAL status
00782   */
00783 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
00784 {
00785   HAL_StatusTypeDef status = HAL_OK;
00786
00787   /* Process locked */
00788   __HAL_LOCK(hpcd);
00789
00790   if (hpcd->State == HAL_PCD_STATE_READY)
00791   {
00792     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
00793   }
00794   else
00795   {
00796     /* Update the error code */
00797     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00798
00799     /* Return error status */
00800     status =  HAL_ERROR;
00801   }
00802
00803   /* Release Lock */
00804   __HAL_UNLOCK(hpcd);
00805
00806   return status;
00807 }
00808
00809 /**
00810   * @brief  Register USB PCD BCD Callback
00811   *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
00812   * @param  hpcd PCD handle
00813   * @param  pCallback pointer to the USB PCD BCD Callback function
00814   * @retval HAL status
00815   */
00816 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
00817 {
00818   HAL_StatusTypeDef status = HAL_OK;
00819
00820   if (pCallback == NULL)
00821   {
00822     /* Update the error code */
00823     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00824
00825     return HAL_ERROR;
00826   }
00827
00828   /* Process locked */
00829   __HAL_LOCK(hpcd);
00830
00831   if (hpcd->State == HAL_PCD_STATE_READY)
00832   {
00833     hpcd->BCDCallback = pCallback;
00834   }
00835   else
00836   {
00837     /* Update the error code */
00838     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00839
00840     /* Return error status */
00841     status =  HAL_ERROR;
00842   }
00843
00844   /* Release Lock */
00845   __HAL_UNLOCK(hpcd);
00846
00847   return status;
00848 }
00849
00850 /**
00851   * @brief  Unregister the USB PCD BCD Callback
00852   *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
00853   * @param  hpcd PCD handle
00854   * @retval HAL status
00855   */
00856 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
00857 {
00858   HAL_StatusTypeDef status = HAL_OK;
00859
00860   /* Process locked */
00861   __HAL_LOCK(hpcd);
00862
00863   if (hpcd->State == HAL_PCD_STATE_READY)
00864   {
00865     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
00866   }
00867   else
00868   {
00869     /* Update the error code */
00870     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00871
00872     /* Return error status */
00873     status =  HAL_ERROR;
00874   }
00875
00876   /* Release Lock */
00877   __HAL_UNLOCK(hpcd);
00878
00879   return status;
00880 }
00881
00882 /**
00883   * @brief  Register USB PCD LPM Callback
00884   *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
00885   * @param  hpcd PCD handle
00886   * @param  pCallback pointer to the USB PCD LPM Callback function
00887   * @retval HAL status
00888   */
00889 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
00890 {
00891   HAL_StatusTypeDef status = HAL_OK;
00892
00893   if (pCallback == NULL)
00894   {
00895     /* Update the error code */
00896     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00897
00898     return HAL_ERROR;
00899   }
00900
00901   /* Process locked */
00902   __HAL_LOCK(hpcd);
00903
00904   if (hpcd->State == HAL_PCD_STATE_READY)
00905   {
00906     hpcd->LPMCallback = pCallback;
00907   }
00908   else
00909   {
00910     /* Update the error code */
00911     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00912
00913     /* Return error status */
00914     status =  HAL_ERROR;
00915   }
00916
00917   /* Release Lock */
00918   __HAL_UNLOCK(hpcd);
00919
00920   return status;
00921 }
00922
00923 /**
00924   * @brief  Unregister the USB PCD LPM Callback
00925   *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
00926   * @param  hpcd PCD handle
00927   * @retval HAL status
00928   */
00929 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
00930 {
00931   HAL_StatusTypeDef status = HAL_OK;
00932
00933   /* Process locked */
00934   __HAL_LOCK(hpcd);
00935
00936   if (hpcd->State == HAL_PCD_STATE_READY)
00937   {
00938     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
00939   }
00940   else
00941   {
00942     /* Update the error code */
00943     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00944
00945     /* Return error status */
00946     status =  HAL_ERROR;
00947   }
00948
00949   /* Release Lock */
00950   __HAL_UNLOCK(hpcd);
00951
00952   return status;
00953 }
00954 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00955
00956 /**
00957   * @}
00958   */
00959
00960 /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
00961   *  @brief   Data transfers functions
00962   *
00963 @verbatim
00964  ===============================================================================
00965                       ##### IO operation functions #####
00966  ===============================================================================
00967     [..]
00968     This subsection provides a set of functions allowing to manage the PCD data
00969     transfers.
00970
00971 @endverbatim
00972   * @{
00973   */
00974
00975 /**
00976   * @brief  Start the USB device
00977   * @param  hpcd PCD handle
00978   * @retval HAL status
00979   */
00980 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00981 {
00982   __HAL_LOCK(hpcd);
00983   __HAL_PCD_ENABLE(hpcd);
00984   (void)USB_DevConnect(hpcd->Instance);
00985   __HAL_UNLOCK(hpcd);
00986
00987   return HAL_OK;
00988 }
00989
00990 /**
00991   * @brief  Stop the USB device.
00992   * @param  hpcd PCD handle
00993   * @retval HAL status
00994   */
00995 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00996 {
00997   __HAL_LOCK(hpcd);
00998   __HAL_PCD_DISABLE(hpcd);
00999   (void)USB_DevDisconnect(hpcd->Instance);
01000   __HAL_UNLOCK(hpcd);
01001
01002   return HAL_OK;
01003 }
01004
01005
01006 /**
01007   * @brief  This function handles PCD interrupt request.
01008   * @param  hpcd PCD handle
01009   * @retval HAL status
01010   */
01011 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
01012 {
01013   uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
01014
01015   /* check if this is an USB pending IT */
01016   if ((SYSCFG->IT_LINE_SR[8] & (0x1U << 2)) == 0U)
01017   {
01018     return;
01019   }
01020
01021   if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
01022   {
01023     /* servicing of the endpoint correct transfer interrupt */
01024     /* clear of the CTR flag into the sub */
01025     (void)PCD_EP_ISR_Handler(hpcd);
01026
01027     return;
01028   }
01029
01030   if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
01031   {
01032     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
01033
01034 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01035     hpcd->ResetCallback(hpcd);
01036 #else
01037     HAL_PCD_ResetCallback(hpcd);
01038 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01039
01040     (void)HAL_PCD_SetAddress(hpcd, 0U);
01041
01042     return;
01043   }
01044
01045   if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
01046   {
01047     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
01048
01049     return;
01050   }
01051
01052   if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
01053   {
01054     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
01055
01056     return;
01057   }
01058
01059   if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
01060   {
01061     hpcd->Instance->CNTR &= ~(USB_CNTR_SUSPRDY);
01062     hpcd->Instance->CNTR &= ~(USB_CNTR_SUSPEN);
01063
01064     if (hpcd->LPM_State == LPM_L1)
01065     {
01066       hpcd->LPM_State = LPM_L0;
01067 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01068       hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
01069 #else
01070       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
01071 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01072     }
01073
01074 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01075     hpcd->ResumeCallback(hpcd);
01076 #else
01077     HAL_PCD_ResumeCallback(hpcd);
01078 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01079
01080     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
01081
01082     return;
01083   }
01084
01085   if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
01086   {
01087     /* Force low-power mode in the macrocell */
01088     hpcd->Instance->CNTR |= USB_CNTR_SUSPEN;
01089
01090     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
01091     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
01092
01093     hpcd->Instance->CNTR |= USB_CNTR_SUSPRDY;
01094
01095 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01096     hpcd->SuspendCallback(hpcd);
01097 #else
01098     HAL_PCD_SuspendCallback(hpcd);
01099 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01100
01101     return;
01102   }
01103
01104   /* Handle LPM Interrupt */
01105   if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ)
01106   {
01107     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
01108     if (hpcd->LPM_State == LPM_L0)
01109     {
01110       /* Force suspend and low-power mode before going to L1 state*/
01111       hpcd->Instance->CNTR |= USB_CNTR_SUSPRDY;
01112       hpcd->Instance->CNTR |= USB_CNTR_SUSPEN;
01113
01114       hpcd->LPM_State = LPM_L1;
01115       hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
01116 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01117       hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
01118 #else
01119       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
01120 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01121     }
01122     else
01123     {
01124 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01125       hpcd->SuspendCallback(hpcd);
01126 #else
01127       HAL_PCD_SuspendCallback(hpcd);
01128 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01129     }
01130
01131     return;
01132   }
01133
01134   if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
01135   {
01136     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
01137
01138 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01139     hpcd->SOFCallback(hpcd);
01140 #else
01141     HAL_PCD_SOFCallback(hpcd);
01142 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01143
01144     return;
01145   }
01146
01147   if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
01148   {
01149     /* clear ESOF flag in ISTR */
01150     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
01151
01152     return;
01153   }
01154 }
01155
01156
01157 /**
01158   * @brief  Data OUT stage callback.
01159   * @param  hpcd PCD handle
01160   * @param  epnum endpoint number
01161   * @retval None
01162   */
01163 __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01164 {
01165   /* Prevent unused argument(s) compilation warning */
01166   UNUSED(hpcd);
01167   UNUSED(epnum);
01168
01169   /* NOTE : This function should not be modified, when the callback is needed,
01170             the HAL_PCD_DataOutStageCallback could be implemented in the user file
01171    */
01172 }
01173
01174 /**
01175   * @brief  Data IN stage callback
01176   * @param  hpcd PCD handle
01177   * @param  epnum endpoint number
01178   * @retval None
01179   */
01180 __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01181 {
01182   /* Prevent unused argument(s) compilation warning */
01183   UNUSED(hpcd);
01184   UNUSED(epnum);
01185
01186   /* NOTE : This function should not be modified, when the callback is needed,
01187             the HAL_PCD_DataInStageCallback could be implemented in the user file
01188    */
01189 }
01190 /**
01191   * @brief  Setup stage callback
01192   * @param  hpcd PCD handle
01193   * @retval None
01194   */
01195 __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
01196 {
01197   /* Prevent unused argument(s) compilation warning */
01198   UNUSED(hpcd);
01199
01200   /* NOTE : This function should not be modified, when the callback is needed,
01201             the HAL_PCD_SetupStageCallback could be implemented in the user file
01202    */
01203 }
01204
01205 /**
01206   * @brief  USB Start Of Frame callback.
01207   * @param  hpcd PCD handle
01208   * @retval None
01209   */
01210 __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
01211 {
01212   /* Prevent unused argument(s) compilation warning */
01213   UNUSED(hpcd);
01214
01215   /* NOTE : This function should not be modified, when the callback is needed,
01216             the HAL_PCD_SOFCallback could be implemented in the user file
01217    */
01218 }
01219
01220 /**
01221   * @brief  USB Reset callback.
01222   * @param  hpcd PCD handle
01223   * @retval None
01224   */
01225 __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
01226 {
01227   /* Prevent unused argument(s) compilation warning */
01228   UNUSED(hpcd);
01229
01230   /* NOTE : This function should not be modified, when the callback is needed,
01231             the HAL_PCD_ResetCallback could be implemented in the user file
01232    */
01233 }
01234
01235 /**
01236   * @brief  Suspend event callback.
01237   * @param  hpcd PCD handle
01238   * @retval None
01239   */
01240 __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
01241 {
01242   /* Prevent unused argument(s) compilation warning */
01243   UNUSED(hpcd);
01244
01245   /* NOTE : This function should not be modified, when the callback is needed,
01246             the HAL_PCD_SuspendCallback could be implemented in the user file
01247    */
01248 }
01249
01250 /**
01251   * @brief  Resume event callback.
01252   * @param  hpcd PCD handle
01253   * @retval None
01254   */
01255 __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
01256 {
01257   /* Prevent unused argument(s) compilation warning */
01258   UNUSED(hpcd);
01259
01260   /* NOTE : This function should not be modified, when the callback is needed,
01261             the HAL_PCD_ResumeCallback could be implemented in the user file
01262    */
01263 }
01264
01265 /**
01266   * @brief  Incomplete ISO OUT callback.
01267   * @param  hpcd PCD handle
01268   * @param  epnum endpoint number
01269   * @retval None
01270   */
01271 __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01272 {
01273   /* Prevent unused argument(s) compilation warning */
01274   UNUSED(hpcd);
01275   UNUSED(epnum);
01276
01277   /* NOTE : This function should not be modified, when the callback is needed,
01278             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
01279    */
01280 }
01281
01282 /**
01283   * @brief  Incomplete ISO IN callback.
01284   * @param  hpcd PCD handle
01285   * @param  epnum endpoint number
01286   * @retval None
01287   */
01288 __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01289 {
01290   /* Prevent unused argument(s) compilation warning */
01291   UNUSED(hpcd);
01292   UNUSED(epnum);
01293
01294   /* NOTE : This function should not be modified, when the callback is needed,
01295             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
01296    */
01297 }
01298
01299 /**
01300   * @brief  Connection event callback.
01301   * @param  hpcd PCD handle
01302   * @retval None
01303   */
01304 __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
01305 {
01306   /* Prevent unused argument(s) compilation warning */
01307   UNUSED(hpcd);
01308
01309   /* NOTE : This function should not be modified, when the callback is needed,
01310             the HAL_PCD_ConnectCallback could be implemented in the user file
01311    */
01312 }
01313
01314 /**
01315   * @brief  Disconnection event callback.
01316   * @param  hpcd PCD handle
01317   * @retval None
01318   */
01319 __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
01320 {
01321   /* Prevent unused argument(s) compilation warning */
01322   UNUSED(hpcd);
01323
01324   /* NOTE : This function should not be modified, when the callback is needed,
01325             the HAL_PCD_DisconnectCallback could be implemented in the user file
01326    */
01327 }
01328
01329 /**
01330   * @}
01331   */
01332
01333 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
01334   *  @brief   management functions
01335   *
01336 @verbatim
01337  ===============================================================================
01338                       ##### Peripheral Control functions #####
01339  ===============================================================================
01340     [..]
01341     This subsection provides a set of functions allowing to control the PCD data
01342     transfers.
01343
01344 @endverbatim
01345   * @{
01346   */
01347
01348 /**
01349   * @brief  Connect the USB device
01350   * @param  hpcd PCD handle
01351   * @retval HAL status
01352   */
01353 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
01354 {
01355   __HAL_LOCK(hpcd);
01356   (void)USB_DevConnect(hpcd->Instance);
01357   __HAL_UNLOCK(hpcd);
01358
01359   return HAL_OK;
01360 }
01361
01362 /**
01363   * @brief  Disconnect the USB device.
01364   * @param  hpcd PCD handle
01365   * @retval HAL status
01366   */
01367 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
01368 {
01369   __HAL_LOCK(hpcd);
01370   (void)USB_DevDisconnect(hpcd->Instance);
01371   __HAL_UNLOCK(hpcd);
01372
01373   return HAL_OK;
01374 }
01375
01376 /**
01377   * @brief  Set the USB Device address.
01378   * @param  hpcd PCD handle
01379   * @param  address new device address
01380   * @retval HAL status
01381   */
01382 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
01383 {
01384   __HAL_LOCK(hpcd);
01385   hpcd->USB_Address = address;
01386   (void)USB_SetDevAddress(hpcd->Instance, address);
01387   __HAL_UNLOCK(hpcd);
01388
01389   return HAL_OK;
01390 }
01391 /**
01392   * @brief  Open and configure an endpoint.
01393   * @param  hpcd PCD handle
01394   * @param  ep_addr endpoint address
01395   * @param  ep_mps endpoint max packet size
01396   * @param  ep_type endpoint type
01397   * @retval HAL status
01398   */
01399 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
01400                                   uint16_t ep_mps, uint8_t ep_type)
01401 {
01402   HAL_StatusTypeDef  ret = HAL_OK;
01403   PCD_EPTypeDef *ep;
01404
01405   if ((ep_addr & 0x80U) == 0x80U)
01406   {
01407     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01408     ep->is_in = 1U;
01409   }
01410   else
01411   {
01412     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01413     ep->is_in = 0U;
01414   }
01415
01416   ep->num = ep_addr & EP_ADDR_MSK;
01417   ep->maxpacket = ep_mps;
01418   ep->type = ep_type;
01419
01420   if (ep->is_in != 0U)
01421   {
01422     /* Assign a Tx FIFO */
01423     ep->tx_fifo_num = ep->num;
01424   }
01425   /* Set initial data PID. */
01426   if (ep_type == EP_TYPE_BULK)
01427   {
01428     ep->data_pid_start = 0U;
01429   }
01430
01431   __HAL_LOCK(hpcd);
01432   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
01433   __HAL_UNLOCK(hpcd);
01434
01435   return ret;
01436 }
01437
01438 /**
01439   * @brief  Deactivate an endpoint.
01440   * @param  hpcd PCD handle
01441   * @param  ep_addr endpoint address
01442   * @retval HAL status
01443   */
01444 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01445 {
01446   PCD_EPTypeDef *ep;
01447
01448   if ((ep_addr & 0x80U) == 0x80U)
01449   {
01450     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01451     ep->is_in = 1U;
01452   }
01453   else
01454   {
01455     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01456     ep->is_in = 0U;
01457   }
01458   ep->num   = ep_addr & EP_ADDR_MSK;
01459
01460   __HAL_LOCK(hpcd);
01461   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
01462   __HAL_UNLOCK(hpcd);
01463   return HAL_OK;
01464 }
01465
01466
01467 /**
01468   * @brief  Receive an amount of data.
01469   * @param  hpcd PCD handle
01470   * @param  ep_addr endpoint address
01471   * @param  pBuf pointer to the reception buffer
01472   * @param  len amount of data to be received
01473   * @retval HAL status
01474   */
01475 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01476 {
01477   PCD_EPTypeDef *ep;
01478
01479   ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01480
01481   /*setup and start the Xfer */
01482   ep->xfer_buff = pBuf;
01483   ep->xfer_len = len;
01484   ep->xfer_count = 0U;
01485   ep->is_in = 0U;
01486   ep->num = ep_addr & EP_ADDR_MSK;
01487
01488   if ((ep_addr & EP_ADDR_MSK) == 0U)
01489   {
01490     (void)USB_EP0StartXfer(hpcd->Instance, ep);
01491   }
01492   else
01493   {
01494     (void)USB_EPStartXfer(hpcd->Instance, ep);
01495   }
01496
01497   return HAL_OK;
01498 }
01499
01500 /**
01501   * @brief  Get Received Data Size
01502   * @param  hpcd PCD handle
01503   * @param  ep_addr endpoint address
01504   * @retval Data Size
01505   */
01506 uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01507 {
01508   return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
01509 }
01510 /**
01511   * @brief  Send an amount of data
01512   * @param  hpcd PCD handle
01513   * @param  ep_addr endpoint address
01514   * @param  pBuf pointer to the transmission buffer
01515   * @param  len amount of data to be sent
01516   * @retval HAL status
01517   */
01518 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01519 {
01520   PCD_EPTypeDef *ep;
01521
01522   ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01523
01524   /*setup and start the Xfer */
01525   ep->xfer_buff = pBuf;
01526   ep->xfer_len = len;
01527   ep->xfer_fill_db = 1U;
01528   ep->xfer_len_db = len;
01529   ep->xfer_count = 0U;
01530   ep->is_in = 1U;
01531   ep->num = ep_addr & EP_ADDR_MSK;
01532
01533   if ((ep_addr & EP_ADDR_MSK) == 0U)
01534   {
01535     (void)USB_EP0StartXfer(hpcd->Instance, ep);
01536   }
01537   else
01538   {
01539     (void)USB_EPStartXfer(hpcd->Instance, ep);
01540   }
01541
01542   return HAL_OK;
01543 }
01544
01545 /**
01546   * @brief  Set a STALL condition over an endpoint
01547   * @param  hpcd PCD handle
01548   * @param  ep_addr endpoint address
01549   * @retval HAL status
01550   */
01551 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01552 {
01553   PCD_EPTypeDef *ep;
01554
01555   if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
01556   {
01557     return HAL_ERROR;
01558   }
01559
01560   if ((0x80U & ep_addr) == 0x80U)
01561   {
01562     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01563     ep->is_in = 1U;
01564   }
01565   else
01566   {
01567     ep = &hpcd->OUT_ep[ep_addr];
01568     ep->is_in = 0U;
01569   }
01570
01571   ep->is_stall = 1U;
01572   ep->num = ep_addr & EP_ADDR_MSK;
01573
01574   __HAL_LOCK(hpcd);
01575
01576   (void)USB_EPSetStall(hpcd->Instance, ep);
01577
01578   __HAL_UNLOCK(hpcd);
01579
01580   return HAL_OK;
01581 }
01582
01583 /**
01584   * @brief  Clear a STALL condition over in an endpoint
01585   * @param  hpcd PCD handle
01586   * @param  ep_addr endpoint address
01587   * @retval HAL status
01588   */
01589 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01590 {
01591   PCD_EPTypeDef *ep;
01592
01593   if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
01594   {
01595     return HAL_ERROR;
01596   }
01597
01598   if ((0x80U & ep_addr) == 0x80U)
01599   {
01600     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01601     ep->is_in = 1U;
01602   }
01603   else
01604   {
01605     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01606     ep->is_in = 0U;
01607   }
01608
01609   ep->is_stall = 0U;
01610   ep->num = ep_addr & EP_ADDR_MSK;
01611
01612   __HAL_LOCK(hpcd);
01613   (void)USB_EPClearStall(hpcd->Instance, ep);
01614   __HAL_UNLOCK(hpcd);
01615
01616   return HAL_OK;
01617 }
01618
01619 /**
01620    * @brief  Abort an USB EP transaction.
01621    * @param  hpcd PCD handle
01622    * @param  ep_addr endpoint address
01623    * @retval HAL status
01624    */
01625 HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01626 {
01627   HAL_StatusTypeDef ret;
01628   PCD_EPTypeDef *ep;
01629
01630   if ((0x80U & ep_addr) == 0x80U)
01631   {
01632     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01633   }
01634   else
01635   {
01636     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01637   }
01638
01639   /* Stop Xfer */
01640   ret = USB_EPStopXfer(hpcd->Instance, ep);
01641
01642   return ret;
01643 }
01644
01645 /**
01646   * @brief  Flush an endpoint
01647   * @param  hpcd PCD handle
01648   * @param  ep_addr endpoint address
01649   * @retval HAL status
01650   */
01651 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01652 {
01653   /* Prevent unused argument(s) compilation warning */
01654   UNUSED(hpcd);
01655   UNUSED(ep_addr);
01656
01657   return HAL_OK;
01658 }
01659
01660 /**
01661   * @brief  Activate remote wakeup signalling
01662   * @param  hpcd PCD handle
01663   * @retval HAL status
01664   */
01665 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01666 {
01667   return (USB_ActivateRemoteWakeup(hpcd->Instance));
01668 }
01669
01670 /**
01671   * @brief  De-activate remote wakeup signalling.
01672   * @param  hpcd PCD handle
01673   * @retval HAL status
01674   */
01675 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01676 {
01677   return (USB_DeActivateRemoteWakeup(hpcd->Instance));
01678 }
01679
01680 /**
01681   * @}
01682   */
01683
01684 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01685   *  @brief   Peripheral State functions
01686   *
01687 @verbatim
01688  ===============================================================================
01689                       ##### Peripheral State functions #####
01690  ===============================================================================
01691     [..]
01692     This subsection permits to get in run-time the status of the peripheral
01693     and the data flow.
01694
01695 @endverbatim
01696   * @{
01697   */
01698
01699 /**
01700   * @brief  Return the PCD handle state.
01701   * @param  hpcd PCD handle
01702   * @retval HAL state
01703   */
01704 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01705 {
01706   return hpcd->State;
01707 }
01708
01709 /**
01710   * @}
01711   */
01712
01713 /**
01714   * @}
01715   */
01716
01717 /* Private functions ---------------------------------------------------------*/
01718 /** @addtogroup PCD_Private_Functions
01719   * @{
01720   */
01721
01722
01723 /**
01724   * @brief  This function handles PCD Endpoint interrupt request.
01725   * @param  hpcd PCD handle
01726   * @retval HAL status
01727   */
01728 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
01729 {
01730   PCD_EPTypeDef *ep;
01731   uint16_t count;
01732   uint16_t wIstr;
01733   uint16_t wEPVal;
01734   uint16_t TxPctSize;
01735   uint8_t epindex;
01736
01737 #if (USE_USB_DOUBLE_BUFFER != 1U)
01738   count = 0U;
01739 #endif /* USE_USB_DOUBLE_BUFFER */
01740
01741   /* stay in loop while pending interrupts */
01742   while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
01743   {
01744     wIstr = (uint16_t)hpcd->Instance->ISTR;
01745
01746     /* extract highest priority endpoint number */
01747     epindex = (uint8_t)(wIstr & USB_ISTR_IDN);
01748
01749     if (epindex == 0U)
01750     {
01751       /* Decode and service control endpoint interrupt */
01752
01753       /* DIR bit = origin of the interrupt */
01754       if ((wIstr & USB_ISTR_DIR) == 0U)
01755       {
01756         /* DIR = 0 */
01757
01758         /* DIR = 0 => IN  int */
01759         /* DIR = 0 implies that (EP_CTR_TX = 1) always */
01760         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01761         ep = &hpcd->IN_ep[0];
01762
01763         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01764         ep->xfer_buff += ep->xfer_count;
01765
01766         /* TX COMPLETE */
01767 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01768         hpcd->DataInStageCallback(hpcd, 0U);
01769 #else
01770         HAL_PCD_DataInStageCallback(hpcd, 0U);
01771 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01772
01773         if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
01774         {
01775           hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
01776           hpcd->USB_Address = 0U;
01777         }
01778       }
01779       else
01780       {
01781         /* DIR = 1 */
01782
01783         /* DIR = 1 & CTR_RX => SETUP or OUT int */
01784         /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
01785         ep = &hpcd->OUT_ep[0];
01786         wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
01787
01788         if ((wEPVal & USB_EP_SETUP) != 0U)
01789         {
01790           /* Get SETUP Packet */
01791           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01792
01793           USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
01794                       ep->pmaadress, (uint16_t)ep->xfer_count);
01795
01796           /* SETUP bit kept frozen while CTR_RX = 1 */
01797           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01798
01799           /* Process SETUP Packet*/
01800 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01801           hpcd->SetupStageCallback(hpcd);
01802 #else
01803           HAL_PCD_SetupStageCallback(hpcd);
01804 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01805         }
01806         else if ((wEPVal & USB_EP_VTRX) != 0U)
01807         {
01808           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01809
01810           /* Get Control Data OUT Packet */
01811           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01812
01813           if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
01814           {
01815             USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
01816                         ep->pmaadress, (uint16_t)ep->xfer_count);
01817
01818             ep->xfer_buff += ep->xfer_count;
01819
01820             /* Process Control Data OUT Packet */
01821 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01822             hpcd->DataOutStageCallback(hpcd, 0U);
01823 #else
01824             HAL_PCD_DataOutStageCallback(hpcd, 0U);
01825 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01826           }
01827
01828           wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
01829
01830           if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
01831           {
01832             PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
01833             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
01834           }
01835         }
01836       }
01837     }
01838     else
01839     {
01840       /* Decode and service non control endpoints interrupt */
01841       /* process related endpoint register */
01842       wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, epindex);
01843
01844       if ((wEPVal & USB_EP_VTRX) != 0U)
01845       {
01846         /* clear int flag */
01847         PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
01848         ep = &hpcd->OUT_ep[epindex];
01849
01850         /* OUT Single Buffering */
01851         if (ep->doublebuffer == 0U)
01852         {
01853           count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01854
01855           if (count != 0U)
01856           {
01857             USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
01858           }
01859         }
01860 #if (USE_USB_DOUBLE_BUFFER == 1U)
01861         else
01862         {
01863           /* manage double buffer bulk out */
01864           if (ep->type == EP_TYPE_BULK)
01865           {
01866             count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
01867           }
01868           else /* manage double buffer iso out */
01869           {
01870             /* free EP OUT Buffer */
01871             PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
01872
01873             if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
01874             {
01875               /* read from endpoint BUF0Addr buffer */
01876               count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
01877
01878               if (count != 0U)
01879               {
01880                 USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
01881               }
01882             }
01883             else
01884             {
01885               /* read from endpoint BUF1Addr buffer */
01886               count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
01887
01888               if (count != 0U)
01889               {
01890                 USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
01891               }
01892             }
01893           }
01894         }
01895 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01896
01897         /* multi-packet on the NON control OUT endpoint */
01898         ep->xfer_count += count;
01899         ep->xfer_buff += count;
01900
01901         if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
01902         {
01903           /* RX COMPLETE */
01904 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01905           hpcd->DataOutStageCallback(hpcd, ep->num);
01906 #else
01907           HAL_PCD_DataOutStageCallback(hpcd, ep->num);
01908 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01909         }
01910         else
01911         {
01912           (void) USB_EPStartXfer(hpcd->Instance, ep);
01913         }
01914       }
01915
01916       if ((wEPVal & USB_EP_VTTX) != 0U)
01917       {
01918         ep = &hpcd->IN_ep[epindex];
01919
01920         /* clear int flag */
01921         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
01922
01923         if (ep->type == EP_TYPE_ISOC)
01924         {
01925           ep->xfer_len = 0U;
01926
01927 #if (USE_USB_DOUBLE_BUFFER == 1U)
01928           if (ep->doublebuffer != 0U)
01929           {
01930             if ((wEPVal & USB_EP_DTOG_TX) != 0U)
01931             {
01932               PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
01933             }
01934             else
01935             {
01936               PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
01937             }
01938           }
01939 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01940
01941           /* TX COMPLETE */
01942 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01943           hpcd->DataInStageCallback(hpcd, ep->num);
01944 #else
01945           HAL_PCD_DataInStageCallback(hpcd, ep->num);
01946 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01947         }
01948         else
01949         {
01950           /* Manage Single Buffer Transaction */
01951           if ((wEPVal & USB_EP_KIND) == 0U)
01952           {
01953             /* multi-packet on the NON control IN endpoint */
01954             TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01955
01956             if (ep->xfer_len > TxPctSize)
01957             {
01958               ep->xfer_len -= TxPctSize;
01959             }
01960             else
01961             {
01962               ep->xfer_len = 0U;
01963             }
01964
01965             /* Zero Length Packet? */
01966             if (ep->xfer_len == 0U)
01967             {
01968               /* TX COMPLETE */
01969 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01970               hpcd->DataInStageCallback(hpcd, ep->num);
01971 #else
01972               HAL_PCD_DataInStageCallback(hpcd, ep->num);
01973 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01974             }
01975             else
01976             {
01977               /* Transfer is not yet Done */
01978               ep->xfer_buff += TxPctSize;
01979               ep->xfer_count += TxPctSize;
01980               (void)USB_EPStartXfer(hpcd->Instance, ep);
01981             }
01982           }
01983 #if (USE_USB_DOUBLE_BUFFER == 1U)
01984           /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
01985           else
01986           {
01987             (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
01988           }
01989 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
01990         }
01991       }
01992     }
01993   }
01994
01995   return HAL_OK;
01996 }
01997
01998
01999 #if (USE_USB_DOUBLE_BUFFER == 1U)
02000 /**
02001   * @brief  Manage double buffer bulk out transaction from ISR
02002   * @param  hpcd PCD handle
02003   * @param  ep current endpoint handle
02004   * @param  wEPVal Last snapshot of EPRx register value taken in ISR
02005   * @retval HAL status
02006   */
02007 static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
02008                                       PCD_EPTypeDef *ep, uint16_t wEPVal)
02009 {
02010   uint16_t count;
02011
02012   /* Manage Buffer0 OUT */
02013   if ((wEPVal & USB_EP_DTOG_RX) != 0U)
02014   {
02015     /* Get count of received Data on buffer0 */
02016     count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
02017
02018     if (ep->xfer_len >= count)
02019     {
02020       ep->xfer_len -= count;
02021     }
02022     else
02023     {
02024       ep->xfer_len = 0U;
02025     }
02026
02027     if (ep->xfer_len == 0U)
02028     {
02029       /* set NAK to OUT endpoint since double buffer is enabled */
02030       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
02031     }
02032
02033     /* Check if Buffer1 is in blocked state which requires to toggle */
02034     if ((wEPVal & USB_EP_DTOG_TX) != 0U)
02035     {
02036       PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
02037     }
02038
02039     if (count != 0U)
02040     {
02041       USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
02042     }
02043   }
02044   /* Manage Buffer 1 DTOG_RX=0 */
02045   else
02046   {
02047     /* Get count of received data */
02048     count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
02049
02050     if (ep->xfer_len >= count)
02051     {
02052       ep->xfer_len -= count;
02053     }
02054     else
02055     {
02056       ep->xfer_len = 0U;
02057     }
02058
02059     if (ep->xfer_len == 0U)
02060     {
02061       /* set NAK on the current endpoint */
02062       PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
02063     }
02064
02065     /*Need to FreeUser Buffer*/
02066     if ((wEPVal & USB_EP_DTOG_TX) == 0U)
02067     {
02068       PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
02069     }
02070
02071     if (count != 0U)
02072     {
02073       USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
02074     }
02075   }
02076
02077   return count;
02078 }
02079
02080
02081 /**
02082   * @brief  Manage double buffer bulk IN transaction from ISR
02083   * @param  hpcd PCD handle
02084   * @param  ep current endpoint handle
02085   * @param  wEPVal Last snapshot of EPRx register value taken in ISR
02086   * @retval HAL status
02087   */
02088 static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
02089                                                 PCD_EPTypeDef *ep, uint16_t wEPVal)
02090 {
02091   uint32_t len;
02092   uint16_t TxPctSize;
02093
02094   /* Data Buffer0 ACK received */
02095   if ((wEPVal & USB_EP_DTOG_TX) != 0U)
02096   {
02097     /* multi-packet on the NON control IN endpoint */
02098     TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
02099
02100     if (ep->xfer_len > TxPctSize)
02101     {
02102       ep->xfer_len -= TxPctSize;
02103     }
02104     else
02105     {
02106       ep->xfer_len = 0U;
02107     }
02108
02109     /* Transfer is completed */
02110     if (ep->xfer_len == 0U)
02111     {
02112       PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
02113       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
02114
02115       /* TX COMPLETE */
02116 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
02117       hpcd->DataInStageCallback(hpcd, ep->num);
02118 #else
02119       HAL_PCD_DataInStageCallback(hpcd, ep->num);
02120 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
02121
02122       if ((wEPVal & USB_EP_DTOG_RX) != 0U)
02123       {
02124         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
02125       }
02126     }
02127     else /* Transfer is not yet Done */
02128     {
02129       /* need to Free USB Buff */
02130       if ((wEPVal & USB_EP_DTOG_RX) != 0U)
02131       {
02132         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
02133       }
02134
02135       /* Still there is data to Fill in the next Buffer */
02136       if (ep->xfer_fill_db == 1U)
02137       {
02138         ep->xfer_buff += TxPctSize;
02139         ep->xfer_count += TxPctSize;
02140
02141         /* Calculate the len of the new buffer to fill */
02142         if (ep->xfer_len_db >= ep->maxpacket)
02143         {
02144           len = ep->maxpacket;
02145           ep->xfer_len_db -= len;
02146         }
02147         else if (ep->xfer_len_db == 0U)
02148         {
02149           len = TxPctSize;
02150           ep->xfer_fill_db = 0U;
02151         }
02152         else
02153         {
02154           ep->xfer_fill_db = 0U;
02155           len = ep->xfer_len_db;
02156           ep->xfer_len_db = 0U;
02157         }
02158
02159         /* Write remaining Data to Buffer */
02160         /* Set the Double buffer counter for pma buffer1 */
02161         PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
02162
02163         /* Copy user buffer to USB PMA */
02164         USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr0, (uint16_t)len);
02165       }
02166     }
02167   }
02168   else /* Data Buffer1 ACK received */
02169   {
02170     /* multi-packet on the NON control IN endpoint */
02171     TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
02172
02173     if (ep->xfer_len >= TxPctSize)
02174     {
02175       ep->xfer_len -= TxPctSize;
02176     }
02177     else
02178     {
02179       ep->xfer_len = 0U;
02180     }
02181
02182     /* Transfer is completed */
02183     if (ep->xfer_len == 0U)
02184     {
02185       PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
02186       PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
02187
02188       /* TX COMPLETE */
02189 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
02190       hpcd->DataInStageCallback(hpcd, ep->num);
02191 #else
02192       HAL_PCD_DataInStageCallback(hpcd, ep->num);
02193 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
02194
02195       /* need to Free USB Buff */
02196       if ((wEPVal & USB_EP_DTOG_RX) == 0U)
02197       {
02198         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
02199       }
02200     }
02201     else /* Transfer is not yet Done */
02202     {
02203       /* need to Free USB Buff */
02204       if ((wEPVal & USB_EP_DTOG_RX) == 0U)
02205       {
02206         PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
02207       }
02208
02209       /* Still there is data to Fill in the next Buffer */
02210       if (ep->xfer_fill_db == 1U)
02211       {
02212         ep->xfer_buff += TxPctSize;
02213         ep->xfer_count += TxPctSize;
02214
02215         /* Calculate the len of the new buffer to fill */
02216         if (ep->xfer_len_db >= ep->maxpacket)
02217         {
02218           len = ep->maxpacket;
02219           ep->xfer_len_db -= len;
02220         }
02221         else if (ep->xfer_len_db == 0U)
02222         {
02223           len = TxPctSize;
02224           ep->xfer_fill_db = 0U;
02225         }
02226         else
02227         {
02228           len = ep->xfer_len_db;
02229           ep->xfer_len_db = 0U;
02230           ep->xfer_fill_db = 0;
02231         }
02232
02233         /* Set the Double buffer counter for pmabuffer1 */
02234         PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
02235
02236         /* Copy the user buffer to USB PMA */
02237         USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr1, (uint16_t)len);
02238       }
02239     }
02240   }
02241
02242   /*enable endpoint IN*/
02243   PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
02244
02245   return HAL_OK;
02246 }
02247 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
02248
02249
02250
02251 /**
02252   * @}
02253   */
02254 #endif /* defined (USB_DRD_FS) */
02255 #endif /* HAL_PCD_MODULE_ENABLED */
02256
02257 /**
02258   * @}
02259   */
02260
02261 /**
02262   * @}
02263   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pcd.h Source File

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stm32g0xx_hal_pcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_PCD_H
00021 #define STM32G0xx_HAL_PCD_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_ll_usb.h"
00029
00030 #if defined (USB_DRD_FS)
00031
00032 /** @addtogroup STM32G0xx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup PCD
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup PCD_Exported_Types PCD Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  PCD State structure definition
00047   */
00048 typedef enum
00049 {
00050   HAL_PCD_STATE_RESET   = 0x00,
00051   HAL_PCD_STATE_READY   = 0x01,
00052   HAL_PCD_STATE_ERROR   = 0x02,
00053   HAL_PCD_STATE_BUSY    = 0x03,
00054   HAL_PCD_STATE_TIMEOUT = 0x04
00055 } PCD_StateTypeDef;
00056
00057 /* Device LPM suspend state */
00058 typedef enum
00059 {
00060   LPM_L0 = 0x00, /* on */
00061   LPM_L1 = 0x01, /* LPM L1 sleep */
00062   LPM_L2 = 0x02, /* suspend */
00063   LPM_L3 = 0x03, /* off */
00064 } PCD_LPM_StateTypeDef;
00065
00066 typedef enum
00067 {
00068   PCD_LPM_L0_ACTIVE = 0x00, /* on */
00069   PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
00070 } PCD_LPM_MsgTypeDef;
00071
00072 typedef enum
00073 {
00074   PCD_BCD_ERROR                     = 0xFF,
00075   PCD_BCD_CONTACT_DETECTION         = 0xFE,
00076   PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
00077   PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
00078   PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
00079   PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
00080
00081 } PCD_BCD_MsgTypeDef;
00082
00083 typedef USB_DRD_TypeDef        PCD_TypeDef;
00084 typedef USB_DRD_CfgTypeDef     PCD_InitTypeDef;
00085 typedef USB_DRD_EPTypeDef      PCD_EPTypeDef;
00086
00087 /**
00088   * @brief  PCD Handle Structure definition
00089   */
00090 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00091 typedef struct __PCD_HandleTypeDef
00092 #else
00093 typedef struct
00094 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00095 {
00096   PCD_TypeDef             *Instance;   /*!< Register base address             */
00097   PCD_InitTypeDef         Init;        /*!< PCD required parameters           */
00098   __IO uint8_t            USB_Address; /*!< USB Address                       */
00099   PCD_EPTypeDef           IN_ep[8];   /*!< IN endpoint parameters             */
00100   PCD_EPTypeDef           OUT_ep[8];  /*!< OUT endpoint parameters            */
00101   HAL_LockTypeDef         Lock;        /*!< PCD peripheral status             */
00102   __IO PCD_StateTypeDef   State;       /*!< PCD communication state           */
00103   __IO  uint32_t          ErrorCode;   /*!< PCD Error code                    */
00104   uint32_t                Setup[12];   /*!< Setup packet buffer               */
00105   PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                         */
00106   uint32_t                BESL;
00107
00108
00109   uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
00110                                        This parameter can be set to ENABLE or DISABLE        */
00111
00112   uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
00113                                        This parameter can be set to ENABLE or DISABLE        */
00114   void                    *pData;      /*!< Pointer to upper stack Handler */
00115
00116 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00117   void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
00118   void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
00119   void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
00120   void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
00121   void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
00122   void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
00123   void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
00124
00125   void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
00126   void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
00127   void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
00128   void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
00129   void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
00130   void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
00131
00132   void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
00133   void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
00134 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00135 } PCD_HandleTypeDef;
00136
00137 /**
00138   * @}
00139   */
00140
00141 /* Include PCD HAL Extended module */
00142 #include "stm32g0xx_hal_pcd_ex.h"
00143
00144 /* Exported constants --------------------------------------------------------*/
00145 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00146   * @{
00147   */
00148
00149 /** @defgroup PCD_Speed PCD Speed
00150   * @{
00151   */
00152 #define PCD_SPEED_FULL               USBD_FS_SPEED
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup PCD_PHY_Module PCD PHY Module
00158   * @{
00159   */
00160 #define PCD_PHY_ULPI                 1U
00161 #define PCD_PHY_EMBEDDED             2U
00162 #define PCD_PHY_UTMI                 3U
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup PCD_Error_Code_definition PCD Error Code definition
00168   * @brief  PCD Error Code definition
00169   * @{
00170   */
00171 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00172 #define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
00173 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00174
00175 /**
00176   * @}
00177   */
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported macros -----------------------------------------------------------*/
00184 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00185   *  @brief macros to handle interrupts and specific clock configurations
00186   * @{
00187   */
00188
00189
00190 #define __HAL_PCD_ENABLE(__HANDLE__)                              (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
00191 #define __HAL_PCD_DISABLE(__HANDLE__)                             (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
00192 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)             ((USB_ReadInterrupts((__HANDLE__)->Instance)\
00193                                                                     & (__INTERRUPT__)) == (__INTERRUPT__))
00194
00195 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)           (((__HANDLE__)->Instance->ISTR)\
00196                                                                    &= (uint16_t)(~(__INTERRUPT__)))
00197
00198 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                         EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE
00199 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                        EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE)
00200
00201
00202 /**
00203   * @}
00204   */
00205
00206 /* Exported functions --------------------------------------------------------*/
00207 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00208   * @{
00209   */
00210
00211 /* Initialization/de-initialization functions  ********************************/
00212 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00213   * @{
00214   */
00215 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00216 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
00217 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00218 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00219
00220 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00221 /** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
00222   * @brief  HAL USB OTG PCD Callback ID enumeration definition
00223   * @{
00224   */
00225 typedef enum
00226 {
00227   HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
00228   HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
00229   HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
00230   HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
00231   HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
00232   HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
00233   HAL_PCD_DISCONNECT_CB_ID   = 0x07,      /*!< USB PCD Disconnect callback ID   */
00234
00235   HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
00236   HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
00237
00238 } HAL_PCD_CallbackIDTypeDef;
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
00244   * @brief  HAL USB OTG PCD Callback pointer definition
00245   * @{
00246   */
00247
00248 typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
00249 typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
00250 typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
00251 typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
00252 typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
00253 typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
00254 typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
00255
00256 /**
00257   * @}
00258   */
00259
00260 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
00261                                            pPCD_CallbackTypeDef pCallback);
00262
00263 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
00264
00265 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
00266                                                        pPCD_DataOutStageCallbackTypeDef pCallback);
00267
00268 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
00269
00270 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
00271                                                       pPCD_DataInStageCallbackTypeDef pCallback);
00272
00273 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
00274
00275 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
00276                                                        pPCD_IsoOutIncpltCallbackTypeDef pCallback);
00277
00278 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
00279
00280 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
00281                                                       pPCD_IsoInIncpltCallbackTypeDef pCallback);
00282
00283 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
00284
00285 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
00286 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
00287
00288 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
00289 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
00290 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00291 /**
00292   * @}
00293   */
00294
00295 /* I/O operation functions  ***************************************************/
00296 /* Non-Blocking mode: Interrupt */
00297 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
00298   * @{
00299   */
00300 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00301 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00302 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00303
00304 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00305 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00306 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00307 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00308 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00309 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00310 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00311
00312 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00313 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00314 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00315 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00316 /**
00317   * @}
00318   */
00319
00320 /* Peripheral Control functions  **********************************************/
00321 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00322   * @{
00323   */
00324 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00325 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00326 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00327 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00328 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00329 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00330 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00331 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00332 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00333 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00334 HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00335 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00336 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00337 uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00338 /**
00339   * @}
00340   */
00341
00342 /* Peripheral State functions  ************************************************/
00343 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00344   * @{
00345   */
00346 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00347 /**
00348   * @}
00349   */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /* Private constants ---------------------------------------------------------*/
00356 /** @defgroup PCD_Private_Constants PCD Private Constants
00357   * @{
00358   */
00359 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
00360   * @{
00361   */
00362
00363
00364 #define USB_WAKEUP_EXTI_LINE                                          (0x1U << 4)  /*!< USB FS EXTI Line WakeUp Interrupt */
00365
00366
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup PCD_EP0_MPS PCD EP0 MPS
00372   * @{
00373   */
00374 #define PCD_EP0MPS_64                                                 EP_MPS_64
00375 #define PCD_EP0MPS_32                                                 EP_MPS_32
00376 #define PCD_EP0MPS_16                                                 EP_MPS_16
00377 #define PCD_EP0MPS_08                                                 EP_MPS_8
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup PCD_ENDP PCD ENDP
00383   * @{
00384   */
00385 #define PCD_ENDP0                                                     0U
00386 #define PCD_ENDP1                                                     1U
00387 #define PCD_ENDP2                                                     2U
00388 #define PCD_ENDP3                                                     3U
00389 #define PCD_ENDP4                                                     4U
00390 #define PCD_ENDP5                                                     5U
00391 #define PCD_ENDP6                                                     6U
00392 #define PCD_ENDP7                                                     7U
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
00398   * @{
00399   */
00400 #define PCD_SNG_BUF                                                   0U
00401 #define PCD_DBL_BUF                                                   1U
00402 /**
00403   * @}
00404   */
00405
00406 /**
00407   * @}
00408   */
00409
00410 /* Private macros ------------------------------------------------------------*/
00411 /** @defgroup PCD_Private_Macros PCD Private Macros
00412   * @{
00413   */
00414 /* SetENDPOINT */
00415 #define PCD_SET_ENDPOINT                       USB_DRD_SET_CHEP
00416
00417 /* GetENDPOINT Register value*/
00418 #define PCD_GET_ENDPOINT                       USB_DRD_GET_CHEP
00419
00420 /* ENDPOINT transfer */
00421 #define USB_EP0StartXfer                       USB_EPStartXfer
00422
00423 /**
00424   * @brief free buffer used from the application realizing it to the line
00425   *         toggles bit SW_BUF in the double buffered endpoint register
00426   * @param USBx USB device.
00427   * @param   bEpNum, bDir
00428   * @retval None
00429   */
00430 #define PCD_FREE_USER_BUFFER                   USB_DRD_FREE_USER_BUFFER
00431
00432 /**
00433   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
00434   * @param  USBx USB peripheral instance register address.
00435   * @param  bEpNum Endpoint Number.
00436   * @param  wState new state
00437   * @retval None
00438   */
00439 #define PCD_SET_EP_TX_STATUS                   USB_DRD_SET_CHEP_TX_STATUS
00440
00441 /**
00442   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
00443   * @param  USBx USB peripheral instance register address.
00444   * @param  bEpNum Endpoint Number.
00445   * @param  wState new state
00446   * @retval None
00447   */
00448 #define PCD_SET_EP_RX_STATUS                   USB_DRD_SET_CHEP_RX_STATUS
00449
00450 /**
00451   * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
00452   * @param  USBx USB peripheral instance register address.
00453   * @param  bEpNum Endpoint Number.
00454   * @retval None
00455   */
00456 #define PCD_SET_EP_KIND                        USB_DRD_SET_CHEP_KIND
00457 #define PCD_CLEAR_EP_KIND                      USB_DRD_CLEAR_CHEP_KIND
00458 #define PCD_SET_BULK_EP_DBUF                   PCD_SET_EP_KIND
00459 #define PCD_CLEAR_BULK_EP_DBUF                 PCD_CLEAR_EP_KIND
00460
00461
00462 /**
00463   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
00464   * @param  USBx USB peripheral instance register address.
00465   * @param  bEpNum Endpoint Number.
00466   * @retval None
00467   */
00468 #define PCD_CLEAR_RX_EP_CTR                    USB_DRD_CLEAR_RX_CHEP_CTR
00469 #define PCD_CLEAR_TX_EP_CTR                    USB_DRD_CLEAR_TX_CHEP_CTR
00470 /**
00471   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
00472   * @param  USBx USB peripheral instance register address.
00473   * @param  bEpNum Endpoint Number.
00474   * @retval None
00475   */
00476 #define PCD_RX_DTOG                            USB_DRD_RX_DTOG
00477 #define PCD_TX_DTOG                            USB_DRD_TX_DTOG
00478 /**
00479   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
00480   * @param  USBx USB peripheral instance register address.
00481   * @param  bEpNum Endpoint Number.
00482   * @retval None
00483   */
00484 #define PCD_CLEAR_RX_DTOG                      USB_DRD_CLEAR_RX_DTOG
00485 #define PCD_CLEAR_TX_DTOG                      USB_DRD_CLEAR_TX_DTOG
00486
00487 /**
00488   * @brief  Sets address in an endpoint register.
00489   * @param  USBx USB peripheral instance register address.
00490   * @param  bEpNum Endpoint Number.
00491   * @param  bAddr Address.
00492   * @retval None
00493   */
00494 #define PCD_SET_EP_ADDRESS                     USB_DRD_SET_CHEP_ADDRESS
00495
00496 /**
00497   * @brief  sets address of the tx/rx buffer.
00498   * @param  USBx USB peripheral instance register address.
00499   * @param  bEpNum Endpoint Number.
00500   * @param  wAddr address to be set (must be word aligned).
00501   * @retval None
00502   */
00503 #define PCD_SET_EP_TX_ADDRESS                  USB_DRD_SET_CHEP_TX_ADDRESS
00504 #define PCD_SET_EP_RX_ADDRESS                  USB_DRD_SET_CHEP_RX_ADDRESS
00505
00506 /**
00507   * @brief  sets counter for the tx/rx buffer.
00508   * @param  USBx USB peripheral instance register address.
00509   * @param  bEpNum Endpoint Number.
00510   * @param  wCount Counter value.
00511   * @retval None
00512   */
00513 #define PCD_SET_EP_TX_CNT                      USB_DRD_SET_CHEP_TX_CNT
00514 #define PCD_SET_EP_RX_CNT                      USB_DRD_SET_CHEP_RX_CNT
00515
00516 /**
00517   * @brief  gets counter of the tx buffer.
00518   * @param  USBx USB peripheral instance register address.
00519   * @param  bEpNum Endpoint Number.
00520   * @retval Counter value
00521   */
00522 #define PCD_GET_EP_TX_CNT                      USB_DRD_GET_CHEP_TX_CNT
00523
00524 /**
00525   * @brief  gets counter of the rx buffer.
00526   * @param  Instance USB peripheral instance register address.
00527   * @param  bEpNum channel Number.
00528   * @retval Counter value
00529   */
00530 __STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum)
00531 {
00532   UNUSED(Instance);
00533   __IO uint32_t count = 10U;
00534
00535   /* WA: few cycles for RX PMA descriptor to update */
00536   while (count > 0U)
00537   {
00538     count--;
00539   }
00540
00541   return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bEpNum));
00542 }
00543
00544 /**
00545   * @brief  Sets addresses in a double buffer endpoint.
00546   * @param  USBx USB peripheral instance register address.
00547   * @param  bEpNum Endpoint Number.
00548   * @param  wBuf0Addr: buffer 0 address.
00549   * @param  wBuf1Addr = buffer 1 address.
00550   * @retval None
00551   */
00552 #define PCD_SET_EP_DBUF_ADDR                   USB_DRD_SET_CHEP_DBUF_ADDR
00553
00554 /**
00555   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00556   * @param  USBx USB peripheral instance register address.
00557   * @param  bEpNum Endpoint Number.
00558   * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
00559   *         EP_DBUF_IN  = IN
00560   * @param  wCount: Counter value
00561   * @retval None
00562   */
00563 #define PCD_SET_EP_DBUF0_CNT                   USB_DRD_SET_CHEP_DBUF0_CNT
00564 #define PCD_SET_EP_DBUF1_CNT                   USB_DRD_SET_CHEP_DBUF1_CNT
00565 #define PCD_SET_EP_DBUF_CNT                    USB_DRD_SET_CHEP_DBUF_CNT
00566
00567 /**
00568   * @brief  gets counter of the rx buffer0.
00569   * @param  Instance USB peripheral instance register address.
00570   * @param  bEpNum channel Number.
00571   * @retval Counter value
00572   */
00573 __STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum)
00574 {
00575   UNUSED(Instance);
00576   __IO uint32_t count = 10U;
00577
00578   /* WA: few cycles for RX PMA descriptor to update */
00579   while (count > 0U)
00580   {
00581     count--;
00582   }
00583
00584   return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bEpNum));
00585 }
00586
00587 /**
00588   * @brief  gets counter of the rx buffer1.
00589   * @param  Instance USB peripheral instance register address.
00590   * @param  bEpNum channel Number.
00591   * @retval Counter value
00592   */
00593 __STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum)
00594 {
00595   UNUSED(Instance);
00596   __IO uint32_t count = 10U;
00597
00598   /* WA: few cycles for RX PMA descriptor to update */
00599   while (count > 0U)
00600   {
00601     count--;
00602   }
00603
00604   return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum));
00605 }
00606
00607 /**
00608   * @}
00609   */
00610
00611 /**
00612   * @}
00613   */
00614
00615 /**
00616   * @}
00617   */
00618 #endif /* defined (USB_DRD_FS) */
00619
00620 #ifdef __cplusplus
00621 }
00622 #endif
00623
00624 #endif /* STM32G0xx_HAL_PCD_H */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pcd_ex.c Source File

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stm32g0xx_hal_pcd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @brief   PCD Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Extended features functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2018 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32g0xx_hal.h"
00025
00026 /** @addtogroup STM32G0xx_HAL_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup PCDEx PCDEx
00031   * @brief PCD Extended HAL module driver
00032   * @{
00033   */
00034
00035 #ifdef HAL_PCD_MODULE_ENABLED
00036
00037 #if defined (USB_DRD_FS)
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /* Private macros ------------------------------------------------------------*/
00042 /* Private functions ---------------------------------------------------------*/
00043 /* Exported functions --------------------------------------------------------*/
00044
00045 /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
00046   * @{
00047   */
00048
00049 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00050   * @brief    PCDEx control functions
00051   *
00052 @verbatim
00053  ===============================================================================
00054                  ##### Extended features functions #####
00055  ===============================================================================
00056     [..]  This section provides functions allowing to:
00057       (+) Update FIFO configuration
00058
00059 @endverbatim
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  Configure PMA for EP
00065   * @param  hpcd  Device instance
00066   * @param  ep_addr endpoint address
00067   * @param  ep_kind endpoint Kind
00068   *                  USB_SNG_BUF: Single Buffer used
00069   *                  USB_DBL_BUF: Double Buffer used
00070   * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
00071   *                   this parameter is 16-bit value providing the address
00072   *                   in PMA allocated to endpoint.
00073   *                   In case of double buffer endpoint this parameter
00074   *                   is a 32-bit value providing the endpoint buffer 0 address
00075   *                   in the LSB part of 32-bit value and endpoint buffer 1 address
00076   *                   in the MSB part of 32-bit value.
00077   * @retval HAL status
00078   */
00079
00080 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
00081                                        uint16_t ep_kind, uint32_t pmaadress)
00082 {
00083   PCD_EPTypeDef *ep;
00084
00085   /* initialize ep structure*/
00086   if ((0x80U & ep_addr) == 0x80U)
00087   {
00088     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
00089   }
00090   else
00091   {
00092     ep = &hpcd->OUT_ep[ep_addr];
00093   }
00094
00095   /* Here we check if the endpoint is single or double Buffer*/
00096   if (ep_kind == PCD_SNG_BUF)
00097   {
00098     /* Single Buffer */
00099     ep->doublebuffer = 0U;
00100     /* Configure the PMA */
00101     ep->pmaadress = (uint16_t)pmaadress;
00102   }
00103 #if (USE_USB_DOUBLE_BUFFER == 1U)
00104   else /* USB_DBL_BUF */
00105   {
00106     /* Double Buffer Endpoint */
00107     ep->doublebuffer = 1U;
00108     /* Configure the PMA */
00109     ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
00110     ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
00111   }
00112 #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
00113
00114   return HAL_OK;
00115 }
00116
00117 /**
00118   * @brief  Activate BatteryCharging feature.
00119   * @param  hpcd PCD handle
00120   * @retval HAL status
00121   */
00122 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
00123 {
00124   USB_DRD_TypeDef *USBx = hpcd->Instance;
00125   hpcd->battery_charging_active = 1U;
00126
00127   /* Enable BCD feature */
00128   USBx->BCDR |= USB_BCDR_BCDEN;
00129
00130   /* Enable DCD : Data Contact Detect */
00131   USBx->BCDR &= ~(USB_BCDR_PDEN);
00132   USBx->BCDR &= ~(USB_BCDR_SDEN);
00133   USBx->BCDR |= USB_BCDR_DCDEN;
00134
00135   return HAL_OK;
00136 }
00137
00138 /**
00139   * @brief  Deactivate BatteryCharging feature.
00140   * @param  hpcd PCD handle
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
00144 {
00145   USB_DRD_TypeDef *USBx = hpcd->Instance;
00146   hpcd->battery_charging_active = 0U;
00147
00148   /* Disable BCD feature */
00149   USBx->BCDR &= ~(USB_BCDR_BCDEN);
00150
00151   return HAL_OK;
00152 }
00153
00154 /**
00155   * @brief  Handle BatteryCharging Process.
00156   * @param  hpcd PCD handle
00157   * @retval HAL status
00158   */
00159 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
00160 {
00161   USB_DRD_TypeDef *USBx = hpcd->Instance;
00162   uint32_t tickstart = HAL_GetTick();
00163
00164   /* Wait for Min DCD Timeout */
00165   HAL_Delay(300U);
00166
00167   /* Data Pin Contact ? Check Detect flag */
00168   if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
00169   {
00170 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00171     hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
00172 #else
00173     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
00174 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00175   }
00176   /* Primary detection: checks if connected to Standard Downstream Port
00177   (without charging capability) */
00178   USBx->BCDR &= ~(USB_BCDR_DCDEN);
00179   HAL_Delay(50U);
00180   USBx->BCDR |= (USB_BCDR_PDEN);
00181   HAL_Delay(50U);
00182
00183   /* If Charger detect ? */
00184   if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
00185   {
00186     /* Start secondary detection to check connection to Charging Downstream
00187     Port or Dedicated Charging Port */
00188     USBx->BCDR &= ~(USB_BCDR_PDEN);
00189     HAL_Delay(50U);
00190     USBx->BCDR |= (USB_BCDR_SDEN);
00191     HAL_Delay(50U);
00192
00193     /* If CDP ? */
00194     if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
00195     {
00196       /* Dedicated Downstream Port DCP */
00197 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00198       hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00199 #else
00200       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00201 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00202     }
00203     else
00204     {
00205       /* Charging Downstream Port CDP */
00206 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00207       hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00208 #else
00209       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00210 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00211     }
00212   }
00213   else /* NO */
00214   {
00215     /* Standard Downstream Port */
00216 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00217     hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00218 #else
00219     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00220 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00221   }
00222
00223   /* Battery Charging capability discovery finished Start Enumeration */
00224   (void)HAL_PCDEx_DeActivateBCD(hpcd);
00225
00226   /* Check for the Timeout, else start USB Device */
00227   if ((HAL_GetTick() - tickstart) > 1000U)
00228   {
00229 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00230     hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
00231 #else
00232     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
00233 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00234   }
00235   else
00236   {
00237 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00238     hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00239 #else
00240     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00241 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00242   }
00243 }
00244
00245
00246 /**
00247   * @brief  Activate LPM feature.
00248   * @param  hpcd PCD handle
00249   * @retval HAL status
00250   */
00251 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00252 {
00253
00254   USB_DRD_TypeDef *USBx = hpcd->Instance;
00255   hpcd->lpm_active = 1U;
00256   hpcd->LPM_State = LPM_L0;
00257
00258   USBx->LPMCSR |= USB_LPMCSR_LMPEN;
00259   USBx->LPMCSR |= USB_LPMCSR_LPMACK;
00260
00261   return HAL_OK;
00262 }
00263
00264 /**
00265   * @brief  Deactivate LPM feature.
00266   * @param  hpcd PCD handle
00267   * @retval HAL status
00268   */
00269 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00270 {
00271   USB_DRD_TypeDef *USBx = hpcd->Instance;
00272
00273   hpcd->lpm_active = 0U;
00274
00275   USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
00276   USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
00277
00278   return HAL_OK;
00279 }
00280
00281
00282
00283 /**
00284   * @brief  Send LPM message to user layer callback.
00285   * @param  hpcd PCD handle
00286   * @param  msg LPM message
00287   * @retval HAL status
00288   */
00289 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
00290 {
00291   /* Prevent unused argument(s) compilation warning */
00292   UNUSED(hpcd);
00293   UNUSED(msg);
00294
00295   /* NOTE : This function should not be modified, when the callback is needed,
00296             the HAL_PCDEx_LPM_Callback could be implemented in the user file
00297    */
00298 }
00299
00300 /**
00301   * @brief  Send BatteryCharging message to user layer callback.
00302   * @param  hpcd PCD handle
00303   * @param  msg LPM message
00304   * @retval HAL status
00305   */
00306 __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
00307 {
00308   /* Prevent unused argument(s) compilation warning */
00309   UNUSED(hpcd);
00310   UNUSED(msg);
00311
00312   /* NOTE : This function should not be modified, when the callback is needed,
00313             the HAL_PCDEx_BCD_Callback could be implemented in the user file
00314    */
00315 }
00316
00317 /**
00318   * @}
00319   */
00320
00321 /**
00322   * @}
00323   */
00324 #endif /* defined (USB_DRD_FS) */
00325 #endif /* HAL_PCD_MODULE_ENABLED */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pcd_ex.h Source File

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  • Drivers
  • STM32G0xx_HAL_Driver
  • Inc
stm32g0xx_hal_pcd_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_PCD_EX_H
00021 #define STM32G0xx_HAL_PCD_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif /* __cplusplus */
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 #if defined (USB_DRD_FS)
00031 /** @addtogroup STM32G0xx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup PCDEx
00036   * @{
00037   */
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /* Exported macros -----------------------------------------------------------*/
00041 /* Exported functions --------------------------------------------------------*/
00042 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00043   * @{
00044   */
00045 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00046   * @{
00047   */
00048
00049
00050
00051 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
00052                                        uint16_t ep_kind, uint32_t pmaadress);
00053
00054
00055 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
00056 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
00057
00058
00059 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
00060 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
00061 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
00062
00063 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
00064 void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
00065
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081 #endif /* defined (USB_DRD_FS) */
00082
00083 #ifdef __cplusplus
00084 }
00085 #endif /* __cplusplus */
00086
00087
00088 #endif /* STM32G0xx_HAL_PCD_EX_H */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pwr.c Source File

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stm32g0xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2018 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32g0xx_hal.h"
00026
00027 /** @addtogroup STM32G0xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @addtogroup PWR
00032   * @{
00033   */
00034
00035 #ifdef HAL_PWR_MODULE_ENABLED
00036
00037 /* Private typedef -----------------------------------------------------------*/
00038 /* Private define ------------------------------------------------------------*/
00039 /** @defgroup PWR_Private_Defines PWR Private Defines
00040   * @{
00041   */
00042
00043 /**
00044   * @}
00045   */
00046
00047 /* Private macro -------------------------------------------------------------*/
00048 /* Private variables ---------------------------------------------------------*/
00049 /* Private function prototypes -----------------------------------------------*/
00050 /* Exported functions --------------------------------------------------------*/
00051 /** @addtogroup PWR_Exported_Functions  PWR Exported Functions
00052   * @{
00053   */
00054
00055 /** @addtogroup PWR_Exported_Functions_Group1  Initialization and de-initialization functions
00056   * @brief  Initialization and de-initialization functions
00057   *
00058 @verbatim
00059  ===============================================================================
00060               ##### Initialization and de-initialization functions #####
00061  ===============================================================================
00062     [..]
00063
00064 @endverbatim
00065   * @{
00066   */
00067
00068 /**
00069   * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
00070             values.
00071   * @retval None
00072   */
00073 void HAL_PWR_DeInit(void)
00074 {
00075   __HAL_RCC_PWR_FORCE_RESET();
00076   __HAL_RCC_PWR_RELEASE_RESET();
00077 }
00078
00079 /**
00080   * @}
00081   */
00082
00083 /** @addtogroup PWR_Exported_Functions_Group2  Peripheral Control functions
00084   *  @brief Low Power modes configuration functions
00085   *
00086 @verbatim
00087
00088  ===============================================================================
00089                  ##### Peripheral Control functions #####
00090  ===============================================================================
00091
00092     [..]
00093     *** WakeUp pin configuration ***
00094     ================================
00095     [..]
00096       (+) WakeUp pins are used to wakeup the system from Standby mode or
00097           Shutdown mode. WakeUp pins polarity can be set to configure event
00098           detection on high level (rising edge) or low level (falling edge).
00099
00100     *** Low Power mode configuration ***
00101     =====================================
00102     [..]
00103       The devices feature 7 low-power modes:
00104       (+) Low-power run mode: core and peripherals are running at low frequency.
00105           Regulator is in low power mode.
00106       (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running,
00107           regulator is main mode.
00108       (+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running
00109           and regulator in low power mode.
00110       (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is
00111            main mode.
00112       (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator
00113           off, low power regulator on.
00114       (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is
00115           disable.
00116       (+) Shutdown mode: all clocks are stopped except LSE, regulator is
00117           disable.
00118
00119    *** Low-power run mode ***
00120    ==========================
00121     [..]
00122       (+) Entry: (from main run mode)
00123           (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after
00124                having decreased the system clock below 2 MHz.
00125       (+) Exit:
00126           (++) clear LPR bit then wait for REGLPF bit to be reset with
00127                HAL_PWREx_DisableLowPowerRunMode() API. Only then can the
00128                system clock frequency be increased above 2 MHz.
00129
00130    *** Sleep mode / Low-power sleep mode ***
00131    =========================================
00132     [..]
00133       (+) Entry:
00134           The Sleep & Low-power Sleep modes are entered through
00135           HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator
00136           is forced to low-power mode and if exit is interrupt or event
00137           triggered.
00138           (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
00139           (++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low
00140                power mode). In this case, the system clock frequency must have
00141                been decreased below 2 MHz beforehand.
00142           (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction
00143           (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction
00144       (+) WFI Exit:
00145         (++) Any interrupt enabled in nested vectored interrupt controller (NVIC)
00146       (+) WFE Exit:
00147         (++) Any wakeup event if cortex is configured with SEVONPEND = 0
00148         (++) Interrupt even when disabled in NVIC if cortex is configured with
00149              SEVONPEND = 1
00150     [..]  When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event,
00151           the MCU is in Low-power Run mode.
00152
00153    *** Stop 0 & Stop 1 modes ***
00154    =============================
00155     [..]
00156       (+) Entry:
00157           The Stop modes are entered through the following APIs:
00158           (++) HAL_PWR_EnterSTOPMode() with following settings:
00159               (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode.
00160               (+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode.
00161       (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
00162           (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
00163           (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
00164       (+) WFI Exit:
00165           (++) Any EXTI line (internal or external) configured in interrupt mode
00166                with corresponding interrupt enable in NVIC
00167       (+) WFE Exit:
00168           (++) Any EXTI line (internal or external) configured in event mode if
00169                cortex is configured with SEVONPEND = 0
00170           (++) Any EXTI line configured in interrupt mode (even if the
00171                corresponding EXTI Interrupt vector is disabled in the NVIC) if
00172                cortex is configured with SEVONPEND = 0. The interrupt source can
00173                be external interrupts or peripherals with wakeup capability.
00174     [..]  When exiting Stop, the MCU is either in Run mode or in Low-power Run mode
00175           depending on the LPR bit setting.
00176
00177    *** Standby mode ***
00178    ====================
00179     [..] In Standby mode, it is possible to keep backup SRAM content (defined as
00180          full SRAM) keeping low power regulator on. This is achievable by setting
00181          Ram retention bit calling HAL_PWREx_EnableSRAMRetention API. This increases
00182          power consumption.
00183          Its also possible to define I/O states using APIs:
00184          HAL_PWREx_EnableGPIOPullUp, HAL_PWREx_EnableGPIOPullDown &
00185          HAL_PWREx_EnablePullUpPullDownConfig
00186       (+) Entry:
00187           (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by
00188                setting SLEEPDEEP in Cortex control register.
00189       (+) Exit:
00190           (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
00191                tamper event (internal & external), LSE CSS detection, reset on
00192                NRST pin, IWDG reset & BOR reset.
00193     [..] Exiting Standby generates a power reset: Cortex is reset and execute
00194          Reset handler vector, all registers in the Vcore domain are set to
00195          their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG,
00196          and Standby/Shutdown modes control) are not impacted.
00197
00198     *** Shutdown mode ***
00199    ======================
00200     [..]
00201       In Shutdown mode,
00202         voltage regulator is disabled, all clocks are off except LSE, RRS bit is
00203         cleared. SRAM and registers contents are lost except for backup domain
00204         registers.
00205       (+) Entry:
00206           (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API,
00207                by setting SLEEPDEEP in Cortex control register.
00208       (+) Exit:
00209           (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
00210                tamper event (internal & external), LSE CSS detection, reset on
00211                NRST pin.
00212     [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute
00213          Reset handler vector, all registers are set to their reset value but ones
00214          in backup domain.
00215
00216 @endverbatim
00217   * @{
00218   */
00219
00220 /**
00221   * @brief  Enable access to the backup domain
00222   *         (RTC & TAMP registers, backup registers, RCC BDCR register).
00223   * @note   After reset, the backup domain is protected against
00224   *         possible unwanted write accesses. All RTC & TAMP registers (backup
00225   *         registers included) and RCC BDCR register are concerned.
00226   * @retval None
00227   */
00228 void HAL_PWR_EnableBkUpAccess(void)
00229 {
00230   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00231 }
00232
00233
00234 /**
00235   * @brief  Disable access to the backup domain
00236   * @retval None
00237   */
00238 void HAL_PWR_DisableBkUpAccess(void)
00239 {
00240   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00241 }
00242
00243 /**
00244   * @brief  Enable the WakeUp PINx functionality.
00245   * @param  WakeUpPinPolarity Specifies which Wake-Up pin to enable.
00246   *         This parameter can be one of the following legacy values which set
00247   *         the default polarity i.e. detection on high level (rising edge):
00248   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*),
00249   *                     PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
00250   *         or one of the following value where the user can explicitly specify
00251   *         the enabled pin and the chosen polarity:
00252   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
00253   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
00254   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW (*)
00255   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00256   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*)
00257   *           @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
00258   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00259   * @note (*) availability depends on devices
00260   * @retval None
00261   */
00262 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
00263 {
00264   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
00265
00266   /* Specifies the Wake-Up pin polarity for the event detection
00267     (rising or falling edge) */
00268   MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
00269
00270   /* Enable wake-up pin */
00271   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
00272 }
00273
00274
00275 /**
00276   * @brief  Disable the WakeUp PINx functionality.
00277   * @param  WakeUpPinx Specifies the Power Wake-Up pin to disable.
00278   *         This parameter can be one of the following values:
00279   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2,PWR_WAKEUP_PIN3(*),
00280   *                     PWR_WAKEUP_PIN4,PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
00281   * @note (*) availability depends on devices
00282   * @retval None
00283   */
00284 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00285 {
00286   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00287
00288   CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
00289 }
00290
00291
00292 /**
00293   * @brief  Enter Sleep or Low-power Sleep mode.
00294   * @note   In Sleep/Low-power Sleep mode, all I/O pins keep the same state as
00295   *         in Run mode.
00296   * @param  Regulator Specifies the regulator state in Sleep/Low-power Sleep
00297   *         mode. This parameter can be one of the following values:
00298   *           @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
00299   *           @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator
00300   *                     in low-power mode)
00301   * @note   Low-power Sleep mode is entered from Low-power Run mode only. In
00302   *         case Regulator parameter is set to Low Power but MCU is in Run mode,
00303   *         we will first enter in Low-power Run mode. Therefore, user should
00304   *         take care that HCLK frequency is less than 2 MHz.
00305   * @note   When exiting Low-power Sleep mode, the MCU is in Low-power Run mode.
00306   *         To switch back to Run mode, user must call
00307   *         HAL_PWREx_DisableLowPowerRunMode() API.
00308   * @param  SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE
00309   *         instruction. This parameter can be one of the following values:
00310   *           @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep
00311   *                     mode with WFI instruction
00312   *           @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep
00313   *                     mode with WFE instruction
00314   * @note   When WFI entry is used, tick interrupt have to be disabled if not
00315   *         desired as the interrupt wake up source.
00316   * @retval None
00317   */
00318 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00319 {
00320   /* Check the parameters */
00321   assert_param(IS_PWR_REGULATOR(Regulator));
00322   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00323
00324   /* Set Regulator parameter */
00325   if (Regulator != PWR_MAINREGULATOR_ON)
00326   {
00327     /* If in run mode, first move to low-power run mode.
00328        The system clock frequency must be below 2 MHz at this point. */
00329     if ((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u)
00330     {
00331       HAL_PWREx_EnableLowPowerRunMode();
00332     }
00333   }
00334   else
00335   {
00336     /* If in low-power run mode at this point, exit it */
00337     if ((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u)
00338     {
00339       if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
00340       {
00341         return ;
00342       }
00343     }
00344   }
00345
00346   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00347   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00348
00349   /* Select SLEEP mode entry -------------------------------------------------*/
00350   if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
00351   {
00352     /* Request Wait For Interrupt */
00353     __WFI();
00354   }
00355   else
00356   {
00357     /* Request Wait For Event */
00358     __SEV();
00359     __WFE();
00360     __WFE();
00361   }
00362 }
00363
00364
00365 /**
00366   * @brief  Enter Stop mode
00367   * @note   This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with
00368   *         legacy code running on devices where only "Stop mode" is mentioned
00369   *         with main or low power regulator ON.
00370   * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
00371   * @note   All clocks in the VCORE domain are stopped; the PLL, the HSI and the
00372   *         HSE oscillators are disabled. Some peripherals with the wakeup
00373   *         capability can switch on the HSI to receive a frame, and switch off
00374   *         the HSI after receiving the frame if it is not a wakeup frame.
00375   *         SRAM and register contents are preserved.
00376   *         The BOR is available.
00377   *         The voltage regulator can be configured either in normal (Stop 0) or
00378   *         low-power mode (Stop 1).
00379   * @note   When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a
00380   *         wakeup event, the HSI RC oscillator is selected as system clock
00381   * @note   When the voltage regulator operates in low power mode (Stop 1),
00382   *         an additional startup delay is incurred when waking up. By keeping
00383   *         the internal regulator ON during Stop mode (Stop 0), the consumption
00384   *         is higher although the startup time is reduced.
00385   * @param  Regulator Specifies the regulator state in Stop mode
00386   *         This parameter can be one of the following values:
00387   *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
00388   *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power
00389   *                                                regulator ON)
00390   * @param  STOPEntry Specifies Stop 0 or Stop 1 mode is entered with WFI or
00391   *         WFE instruction. This parameter can be one of the following values:
00392   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI
00393   *                                         instruction.
00394   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE
00395   *                                         instruction.
00396   * @retval None
00397   */
00398 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00399 {
00400   /* Check the parameters */
00401   assert_param(IS_PWR_REGULATOR(Regulator));
00402   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00403
00404   if (Regulator != PWR_MAINREGULATOR_ON)
00405   {
00406     /* Stop mode with Low-Power Regulator */
00407     MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1);
00408   }
00409   else
00410   {
00411     /* Stop mode with Main Regulator */
00412     MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
00413   }
00414
00415   /* Set SLEEPDEEP bit of Cortex System Control Register */
00416   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00417
00418   /* Select Stop mode entry --------------------------------------------------*/
00419   if (STOPEntry == PWR_STOPENTRY_WFI)
00420   {
00421     /* Request Wait For Interrupt */
00422     __WFI();
00423   }
00424   else
00425   {
00426     /* Request Wait For Event */
00427     __SEV();
00428     __WFE();
00429     __WFE();
00430   }
00431
00432   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00433   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00434 }
00435
00436
00437 /**
00438   * @brief  Enter Standby mode.
00439   * @note   In Standby mode, the PLL, the HSI and the HSE oscillators are
00440   *         switched off. The voltage regulator is disabled. SRAM and register
00441   *         contents are lost except for registers in the Backup domain and
00442   *         Standby circuitry. BOR is available.
00443   * @note   The I/Os can be configured either with a pull-up or pull-down or can
00444   *         be kept in analog state.
00445   *         HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown()
00446   *         respectively enable Pull Up and PullDown state.
00447   *         HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown()
00448   *         disable the same. These states are effective in Standby mode only if
00449   *         APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00450   * @note   Sram content can be kept setting RRS through HAL_PWREx_EnableSRAMRetention()
00451   * @retval None
00452   */
00453 void HAL_PWR_EnterSTANDBYMode(void)
00454 {
00455   /* Set Stand-by mode */
00456   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
00457
00458   /* Set SLEEPDEEP bit of Cortex System Control Register */
00459   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00460
00461   /* This option is used to ensure that store operations are completed */
00462 #if defined ( __CC_ARM)
00463   __force_stores();
00464 #endif /* __CC_ARM */
00465
00466   /* Request Wait For Interrupt */
00467   __WFI();
00468 }
00469
00470
00471 /**
00472   * @brief  Enable Sleep-On-Exit Cortex feature
00473   * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
00474   *         processor enters SLEEP or DEEPSLEEP mode when an interruption
00475   *         handling is over returning to thread mode. Setting this bit is
00476   *         useful when the processor is expected to run only on interruptions
00477   *         handling.
00478   * @retval None
00479   */
00480 void HAL_PWR_EnableSleepOnExit(void)
00481 {
00482   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00483   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00484 }
00485
00486
00487 /**
00488   * @brief  Disable Sleep-On-Exit Cortex feature
00489   * @note   Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
00490   *         processor enters SLEEP or DEEPSLEEP mode when an interruption
00491   *         handling is over.
00492   * @retval None
00493   */
00494 void HAL_PWR_DisableSleepOnExit(void)
00495 {
00496   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00497   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00498 }
00499
00500
00501 /**
00502   * @brief  Enable Cortex Sev On Pending feature.
00503   * @note   Set SEVONPEND bit of SCR register. When this bit is set, enabled
00504   *         events and all interrupts, including disabled ones can wakeup
00505   *         processor from WFE.
00506   * @retval None
00507   */
00508 void HAL_PWR_EnableSEVOnPend(void)
00509 {
00510   /* Set SEVONPEND bit of Cortex System Control Register */
00511   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00512 }
00513
00514
00515 /**
00516   * @brief  Disable Cortex Sev On Pending feature.
00517   * @note   Clear SEVONPEND bit of SCR register. When this bit is clear, only
00518   *         enable interrupts or events can wakeup processor from WFE
00519   * @retval None
00520   */
00521 void HAL_PWR_DisableSEVOnPend(void)
00522 {
00523   /* Clear SEVONPEND bit of Cortex System Control Register */
00524   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00525 }
00526
00527 /**
00528   * @}
00529   */
00530
00531 /**
00532   * @}
00533   */
00534
00535 #endif /* HAL_PWR_MODULE_ENABLED */
00536 /**
00537   * @}
00538   */
00539
00540 /**
00541   * @}
00542   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pwr.h Source File

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stm32g0xx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_PWR_H
00021 #define STM32G0xx_HAL_PWR_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup PWR PWR
00035   * @brief PWR HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup PWR_Exported_Types PWR Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @}
00046   */
00047
00048 /* Exported constants --------------------------------------------------------*/
00049 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00050   * @{
00051   */
00052
00053 /** @defgroup PWR_WakeUp_Pins  PWR WakeUp pins
00054   * @{
00055   */
00056 #define PWR_WAKEUP_PIN1                     PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level detection) */
00057 #define PWR_WAKEUP_PIN2                     PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level detection) */
00058 #if defined(PWR_CR3_EWUP3)
00059 #define PWR_WAKEUP_PIN3                     PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level detection) */
00060 #endif /* PWR_CR3_EWUP3 */
00061 #define PWR_WAKEUP_PIN4                     PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level detection) */
00062 #if defined(PWR_CR3_EWUP5)
00063 #define PWR_WAKEUP_PIN5                     PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level detection) */
00064 #endif /* PWR_CR3_EWUP5 */
00065 #define PWR_WAKEUP_PIN6                     PWR_CR3_EWUP6  /*!< Wakeup pin 6 (with high level detection) */
00066 #define PWR_WAKEUP_PIN1_HIGH                PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level detection) */
00067 #define PWR_WAKEUP_PIN2_HIGH                PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level detection) */
00068 #if defined(PWR_CR3_EWUP3)
00069 #define PWR_WAKEUP_PIN3_HIGH                PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level detection) */
00070 #endif /* PWR_CR3_EWUP3 */
00071 #define PWR_WAKEUP_PIN4_HIGH                PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level detection) */
00072 #if defined(PWR_CR3_EWUP5)
00073 #define PWR_WAKEUP_PIN5_HIGH                PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level detection) */
00074 #endif /* PWR_CR3_EWUP5*/
00075 #define PWR_WAKEUP_PIN6_HIGH                PWR_CR3_EWUP6  /*!< Wakeup pin 6 (with high level detection) */
00076 #define PWR_WAKEUP_PIN1_LOW                 ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level detection) */
00077 #define PWR_WAKEUP_PIN2_LOW                 ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level detection) */
00078 #if defined(PWR_CR3_EWUP3)
00079 #define PWR_WAKEUP_PIN3_LOW                 ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level detection) */
00080 #endif /* PWR_CR3_EWUP3 */
00081 #define PWR_WAKEUP_PIN4_LOW                 ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level detection) */
00082 #if defined(PWR_CR3_EWUP5)
00083 #define PWR_WAKEUP_PIN5_LOW                 ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level detection) */
00084 #endif /* PWR_CR3_EWUP5 */
00085 #define PWR_WAKEUP_PIN6_LOW                 ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6) /*!< Wakeup pin 6 (with low level detection) */
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup PWR_Low_Power_Mode_Selection  PWR Low Power Mode Selection
00091   * @{
00092   */
00093 #define PWR_LOWPOWERMODE_STOP0              (0x00000000u)                       /*!< Stop 0: stop mode with main regulator */
00094 #define PWR_LOWPOWERMODE_STOP1              (PWR_CR1_LPMS_0)                    /*!< Stop 1: stop mode with low power regulator */
00095 #define PWR_LOWPOWERMODE_STANDBY            (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)   /*!< Standby mode */
00096 #if defined(PWR_SHDW_SUPPORT)
00097 #define PWR_LOWPOWERMODE_SHUTDOWN           (PWR_CR1_LPMS_2)                    /*!< Shutdown mode */
00098 #endif /* PWR_SHDW_SUPPORT */
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
00104   * @{
00105   */
00106 #define PWR_MAINREGULATOR_ON                (0x00000000u)  /*!< Regulator in main mode      */
00107 #define PWR_LOWPOWERREGULATOR_ON            PWR_CR1_LPR    /*!< Regulator in low-power mode */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
00113   * @{
00114   */
00115 #define PWR_SLEEPENTRY_WFI                  ((uint8_t)0x01u)        /*!< Wait For Interruption instruction to enter Sleep mode */
00116 #define PWR_SLEEPENTRY_WFE                  ((uint8_t)0x02u)        /*!< Wait For Event instruction to enter Sleep mode        */
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
00122   * @{
00123   */
00124 #define PWR_STOPENTRY_WFI                   ((uint8_t)0x01u)        /*!< Wait For Interruption instruction to enter Stop mode */
00125 #define PWR_STOPENTRY_WFE                   ((uint8_t)0x02u)        /*!< Wait For Event instruction to enter Stop mode        */
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup PWR_Flag  PWR Status Flags
00131   * @brief  Elements values convention: 0000 00XX 000Y YYYYb
00132   *           - Y YYYY  : Flag position in the XX register (5 bits)
00133   *           - XX  : Status register (2 bits)
00134   *                 - 01: SR1 register
00135   *                 - 10: SR2 register
00136   *         The only exception is PWR_FLAG_WU, encompassing all
00137   *         wake-up flags and set to PWR_SR1_WUF.
00138   * @{
00139   */
00140 #define PWR_FLAG_WUF1                       (0x00010000u | PWR_SR1_WUF1)      /*!< Wakeup event on wakeup pin 1 */
00141 #define PWR_FLAG_WUF2                       (0x00010000u | PWR_SR1_WUF2)      /*!< Wakeup event on wakeup pin 2 */
00142 #if defined(PWR_CR3_EWUP3)
00143 #define PWR_FLAG_WUF3                       (0x00010000u | PWR_SR1_WUF3)      /*!< Wakeup event on wakeup pin 3 */
00144 #endif /* PWR_CR3_EWUP3 */
00145 #define PWR_FLAG_WUF4                       (0x00010000u | PWR_SR1_WUF4)      /*!< Wakeup event on wakeup pin 4 */
00146 #if defined(PWR_CR3_EWUP5)
00147 #define PWR_FLAG_WUF5                       (0x00010000u | PWR_SR1_WUF5)      /*!< Wakeup event on wakeup pin 5 */
00148 #endif /* PWR_CR3_EWUP5 */
00149 #define PWR_FLAG_WUF6                       (0x00010000u | PWR_SR1_WUF6)      /*!< Wakeup event on wakeup pin 6 */
00150 #define PWR_FLAG_WUF                        (0x00010000u | PWR_SR1_WUF)       /*!< Wakeup event on all wakeup pin  */
00151 #define PWR_FLAG_SB                         (0x00010000u | PWR_SR1_SBF)       /*!< Standby flag */
00152 #define PWR_FLAG_WUFI                       (0x00010000u | PWR_SR1_WUFI)      /*!< Wakeup on internal wakeup line */
00153 #define PWR_FLAG_FLASH_READY                (0x00020000u | PWR_SR2_FLASH_RDY) /*!< Flash ready */
00154 #define PWR_FLAG_REGLPS                     (0x00020000u | PWR_SR2_REGLPS)    /*!< Regulator Low Power started */
00155 #define PWR_FLAG_REGLPF                     (0x00020000u | PWR_SR2_REGLPF)    /*!< Regulator Low Power flag */
00156 #if defined(PWR_PVD_SUPPORT)
00157 #define PWR_FLAG_PVDO                       (0x00020000u | PWR_SR2_PVDO)      /*!< Power Voltage Detector output */
00158 #endif /* PWR_PVD_SUPPORT */
00159 #if defined(PWR_PVM_SUPPORT)
00160 #define PWR_FLAG_PVMO_USB                   (0x00020000u | PWR_SR2_PVMO_USB)  /*!< Power Voltage Monitoring output */
00161 #endif /* PWR_PVM_SUPPORT */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /**
00168   * @}
00169   */
00170
00171 /* Exported macros -----------------------------------------------------------*/
00172 /** @defgroup PWR_Exported_Macros  PWR Exported Macros
00173   * @{
00174   */
00175 /** @brief  Check whether or not a specific PWR flag is set.
00176   * @param  __FLAG__  specifies the flag to check.
00177   *         This parameter can be one a combination of following values:
00178   *            @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event
00179   *                  was received from the WKUP pin 1.
00180   *            @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event
00181   *                  was received from the WKUP pin 2.
00182   *            @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event
00183   *                  was received from the WKUP pin 3. (*)
00184   *            @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event
00185   *                  was received from the WKUP pin 4.
00186   *            @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event
00187   *                  was received from the WKUP pin 5. (*)
00188   *            @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event
00189   *                  was received from the WKUP pin 6.
00190   *            @arg PWR_FLAG_SB: StandBy Flag. Indicates that the system
00191   *                  entered StandBy mode.
00192   *            @arg PWR_FLAG_WUFI: Wake-Up Flag Internal. Set when a wakeup is
00193   *                 detected on the internal wakeup line.
00194   *         OR a combination of following values:
00195   *            @arg PWR_FLAG_FLASH_READY: Flash is ready. Indicates whether flash
00196   *                 can be used or not
00197   *            @arg PWR_FLAG_REGLPS: Low Power Regulator Started. Indicates whether
00198   *                 or not the low-power regulator is ready.
00199   *            @arg PWR_FLAG_REGLPF: Low Power Regulator Flag. Indicates whether the
00200   *                 regulator is ready in main mode or is in low-power mode.
00201   * @if defined(STM32G081xx)
00202   *            @arg PWR_FLAG_PVDO: Power Voltage Detector Output. Indicates whether
00203   *                 VDD voltage is below or above the selected PVD threshold.
00204   * @endif
00205   * @retval The new state of __FLAG__ (TRUE or FALSE).
00206   */
00207 #define __HAL_PWR_GET_FLAG(__FLAG__)        (((__FLAG__) & 0x00010000u) ?\
00208                                              ((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\
00209                                              ((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)))
00210
00211 /** @brief  Clear a specific PWR flag.
00212   * @param  __FLAG__  specifies the flag to clear.
00213   *         This parameter can be a combination of following values:
00214   *            @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event
00215   *                  was received from the WKUP pin 1.
00216   *            @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event
00217   *                  was received from the WKUP pin 2.
00218   *            @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event
00219   *                  was received from the WKUP pin 3. (*)
00220   *            @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event
00221   *                  was received from the WKUP pin 4.
00222   *            @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event
00223   *                  was received from the WKUP pin 5. (*)
00224   *            @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event
00225   *                  was received from the WKUP pin 6.
00226   *            @arg PWR_FLAG_WUF: Encompasses all Wake Up Flags.
00227   *            @arg PWR_FLAG_SB: Standby Flag. Indicates that the system
00228   *                  entered Standby mode.
00229   * @retval None
00230   */
00231 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)      (PWR->SCR = (__FLAG__))
00232
00233 /**
00234   * @}
00235   */
00236
00237 /* Private constants-------------------------------------------------------*/
00238 /** @defgroup PWR_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
00239   * @{
00240   */
00241 #define PWR_WUP_POLARITY_SHIFT              0x08u   /*!< Internal constant used to retrieve wakeup pin polariry */
00242 /**
00243   * @}
00244   */
00245
00246 /* Private macros --------------------------------------------------------*/
00247 /** @defgroup PWR_Private_Macros  PWR Private Macros
00248   * @{
00249   */
00250
00251 #define IS_PWR_WAKEUP_PIN(PIN)                    ((((PIN) & ((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) != 0x00000000u) && \
00252                                                    (((PIN) & ~((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) == 0x00000000u))
00253
00254 #define IS_PWR_REGULATOR(REGULATOR)               (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
00255                                                    ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00256
00257 #define IS_PWR_SLEEP_ENTRY(ENTRY)                 (((ENTRY) == PWR_SLEEPENTRY_WFI) || \
00258                                                    ((ENTRY) == PWR_SLEEPENTRY_WFE))
00259
00260 #define IS_PWR_STOP_ENTRY(ENTRY)                  (((ENTRY) == PWR_STOPENTRY_WFI) || \
00261                                                    ((ENTRY) == PWR_STOPENTRY_WFE))
00262 /**
00263   * @}
00264   */
00265
00266 /* Include PWR HAL Extended module */
00267 #include "stm32g0xx_hal_pwr_ex.h"
00268
00269 /* Exported functions --------------------------------------------------------*/
00270 /** @defgroup PWR_Exported_Functions  PWR Exported Functions
00271   * @{
00272   */
00273
00274 /** @defgroup PWR_Exported_Functions_Group1  Initialization and de-initialization functions
00275   * @{
00276   */
00277
00278 /* Initialization and de-initialization functions *******************************/
00279 void              HAL_PWR_DeInit(void);
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup PWR_Exported_Functions_Group2  Peripheral Control functions
00285   * @{
00286   */
00287 /* Peripheral Control functions  ************************************************/
00288 void              HAL_PWR_EnableBkUpAccess(void);
00289 void              HAL_PWR_DisableBkUpAccess(void);
00290
00291 /* WakeUp pins configuration functions ****************************************/
00292 void              HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
00293 void              HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00294
00295 /* Low Power modes configuration functions ************************************/
00296 void              HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00297 void              HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00298 void              HAL_PWR_EnterSTANDBYMode(void);
00299 void              HAL_PWR_EnableSleepOnExit(void);
00300 void              HAL_PWR_DisableSleepOnExit(void);
00301 void              HAL_PWR_EnableSEVOnPend(void);
00302 void              HAL_PWR_DisableSEVOnPend(void);
00303
00304 /**
00305   * @}
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 /**
00317   * @}
00318   */
00319
00320 #ifdef __cplusplus
00321 }
00322 #endif
00323
00324
00325 #endif /* STM32G0xx_HAL_PWR_H */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pwr_ex.c Source File

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stm32g0xx_hal_pwr_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Extended Initialization and de-initialization functions
00009   *           + Extended Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2018 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32g0xx_hal.h"
00026
00027 /** @addtogroup STM32G0xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @addtogroup PWREx
00032   * @{
00033   */
00034
00035 #ifdef HAL_PWR_MODULE_ENABLED
00036
00037 /* Private typedef -----------------------------------------------------------*/
00038 /* Private define ------------------------------------------------------------*/
00039 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
00040   * @{
00041   */
00042
00043 #if defined(PWR_PVD_SUPPORT)
00044 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00045   * @{
00046   */
00047 #define PVD_MODE_IT           0x00010000U  /*!< Mask for interruption yielded
00048                                                 by PVD threshold crossing     */
00049 #define PVD_MODE_EVT          0x00020000U  /*!< Mask for event yielded
00050                                                 by PVD threshold crossing     */
00051 #define PVD_RISING_EDGE       0x00000001U  /*!< Mask for rising edge set as
00052                                                 PVD trigger                   */
00053 #define PVD_FALLING_EDGE      0x00000002U  /*!< Mask for falling edge set as
00054                                                 PVD trigger                   */
00055 /**
00056   * @}
00057   */
00058 #endif /* PWR_PVD_SUPPORT */
00059
00060 /** @defgroup PWREx_TimeOut_Value  PWREx Flag Setting Time Out Value
00061   * @{
00062   */
00063 #define PWR_REGLPF_SETTING_DELAY_6_US       6u  /*!< REGLPF should rise in about 5 us plus
00064                                                      2 APB clock. Taking in account max Sysclk at
00065                                                      2 MHz, and rounded to upper value */
00066
00067 #define PWR_VOSF_SETTING_DELAY_6_US         6u  /*!< VOSF should rise in about 5 us plus
00068                                                      2 APB clock. Taking in account max Sysclk at
00069                                                      16 MHz, and rounded to upper value */
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup PWREx_Gpio_Pin_Number  PWREx Gpio Pin Number
00075   * @{
00076   */
00077 #define PWR_GPIO_PIN_NB                     16u  /*!< Number of gpio pin in bank */
00078 /**
00079   * @}
00080   */
00081
00082 /**
00083   * @}
00084   */
00085
00086 /* Private macro -------------------------------------------------------------*/
00087 /* Private variables ---------------------------------------------------------*/
00088 /* Private function prototypes -----------------------------------------------*/
00089 /* Exported functions --------------------------------------------------------*/
00090 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
00091   * @{
00092   */
00093
00094 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
00095   *  @brief   Extended Peripheral Control functions
00096   *
00097 @verbatim
00098  ===============================================================================
00099   ##### Extended Peripheral Initialization and de-initialization functions #####
00100  ===============================================================================
00101     [..]
00102      *** PVD configuration ***
00103     =========================
00104     [..]
00105       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00106           threshold selected by the PVD Level (PVDRT[2:0] & PVDFT[2:0] bits in
00107           PWR CR2 register).
00108       (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
00109           than the PVD threshold. This event is internally connected to the EXTI
00110           line 16 and can generate an interrupt if enabled.
00111       (+) The PVD is stopped in Standby & Shutdown mode.
00112
00113      *** PVM configuration ***
00114     =========================
00115     [..]
00116
00117 @endverbatim
00118   * @{
00119   */
00120
00121 /**
00122   * @brief  Enable battery charging.
00123   * @note   When VDD is present, charge the external battery on VBAT through an
00124   *         internal resistor.
00125   * @param  ResistorSelection specifies the resistor impedance.
00126   *         This parameter can be one of the following values:
00127   *           @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor
00128   *           @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
00129   * @retval None
00130   */
00131 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
00132 {
00133   uint32_t tmpreg;
00134   assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
00135
00136   /* Specify resistor selection and enable battery charging */
00137   tmpreg = (PWR->CR4 & ~PWR_CR4_VBRS);
00138   PWR->CR4 = (tmpreg | ResistorSelection | PWR_CR4_VBE);
00139 }
00140
00141
00142 /**
00143   * @brief Disable battery charging.
00144   * @retval None
00145   */
00146 void HAL_PWREx_DisableBatteryCharging(void)
00147 {
00148   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
00149 }
00150
00151 #if defined(PWR_CR3_ENB_ULP)
00152 /**
00153   * @brief  Enable POR Monitor sampling mode.
00154   * @note   When entering ultra low power modes (standby, shutdown) this feature
00155   *         can be enabled to reduce further consumption: Power On Reset monitor
00156   *         is then set in sampling mode, and no more in always on mode.
00157   * @retval None
00158   */
00159 void HAL_PWREx_EnablePORMonitorSampling(void)
00160 {
00161   PWR->CR3 |= PWR_CR3_ENB_ULP;
00162 }
00163
00164
00165 /**
00166   * @brief  Disable POR Monitor sampling mode.
00167   * @retval None
00168   */
00169 void HAL_PWREx_DisablePORMonitorSampling(void)
00170 {
00171   PWR->CR3 &= ~PWR_CR3_ENB_ULP;
00172 }
00173 #endif /* PWR_CR3_ENB_ULP */
00174
00175 #if defined(PWR_PVD_SUPPORT)
00176 /**
00177   * @brief  Configure the Power Voltage Detector (PVD).
00178   * @param  sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the
00179             PVD configuration information: threshold levels, operating mode.
00180   * @note   Refer to the electrical characteristics of your device datasheet for
00181   *         more details about the voltage thresholds corresponding to each
00182   *         detection level.
00183   * @note   User should take care that rising threshold is higher than falling
00184   *         one in order to avoid having always PVDO output set.
00185   * @retval HAL_OK
00186   */
00187 HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00188 {
00189   /* Check the parameters */
00190   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00191   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00192
00193   /* Set PVD level bits only according to PVDLevel value */
00194   MODIFY_REG(PWR->CR2, (PWR_CR2_PVDFT | PWR_CR2_PVDRT), sConfigPVD->PVDLevel);
00195
00196   /* Clear any previous config, in case no event or IT mode is selected */
00197   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00198   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00199   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00200   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00201
00202   /* Configure interrupt mode */
00203   if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00204   {
00205     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00206   }
00207
00208   /* Configure event mode */
00209   if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00210   {
00211     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00212   }
00213
00214   /* Configure the edge */
00215   if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00216   {
00217     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00218   }
00219
00220   if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00221   {
00222     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00223   }
00224
00225   return HAL_OK;
00226 }
00227
00228
00229 /**
00230   * @brief  Enable the Power Voltage Detector (PVD).
00231   * @retval None
00232   */
00233 void HAL_PWREx_EnablePVD(void)
00234 {
00235   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00236 }
00237
00238
00239 /**
00240   * @brief  Disable the Power Voltage Detector (PVD).
00241   * @retval None
00242   */
00243 void HAL_PWREx_DisablePVD(void)
00244 {
00245   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00246 }
00247 #endif /* PWR_PVD_SUPPORT */
00248
00249 #if defined(PWR_PVM_SUPPORT)
00250 /**
00251   * @brief Enable VDDUSB supply.
00252   * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
00253   * @retval None
00254   */
00255 void HAL_PWREx_EnableVddUSB(void)
00256 {
00257   SET_BIT(PWR->CR2, PWR_CR2_USV);
00258 }
00259
00260 /**
00261   * @brief Disable VDDUSB supply.
00262   * @retval None
00263   */
00264 void HAL_PWREx_DisableVddUSB(void)
00265 {
00266   CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
00267 }
00268 #endif /* PWR_PVM_SUPPORT */
00269
00270 #if defined(PWR_CR2_IOSV)
00271 /**
00272   * @brief Enable VDDIO2 supply.
00273   * @note  Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
00274   * @retval None
00275   */
00276 void HAL_PWREx_EnableVddIO2(void)
00277 {
00278   SET_BIT(PWR->CR2, PWR_CR2_IOSV);
00279 }
00280
00281
00282 /**
00283   * @brief Disable VDDIO2 supply.
00284   * @retval None
00285   */
00286 void HAL_PWREx_DisableVddIO2(void)
00287 {
00288   CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
00289 }
00290 #endif /* PWR_CR2_IOSV */
00291
00292 #if defined (PWR_PVM_SUPPORT)
00293 /**
00294   * @brief Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)
00295   * @retval None
00296   */
00297 void HAL_PWREx_EnablePVMUSB(void)
00298 {
00299   SET_BIT(PWR->CR2, PWR_PVM_USB);
00300 }
00301
00302 /**
00303   * @brief Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2)
00304   * @retval None
00305   */
00306 void HAL_PWREx_DisablePVMUSB(void)
00307 {
00308   CLEAR_BIT(PWR->CR2, PWR_PVM_USB);
00309 }
00310 #endif /* PWR_PVM_SUPPORT */
00311
00312 #if defined(PWR_PVM_SUPPORT)
00313 /**
00314   * @brief Configure the Peripheral Voltage Monitoring (PVM).
00315   * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
00316   *        PVM configuration information.
00317   * @note The API configures a single PVM according to the information contained
00318   *       in the input structure. To configure several PVMs, the API must be singly
00319   *       called for each PVM used.
00320   * @note Refer to the electrical characteristics of your device datasheet for
00321   *         more details about the voltage thresholds corresponding to each
00322   *         detection level and to each monitored supply.
00323   * @retval HAL status
00324   */
00325 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
00326 {
00327   HAL_StatusTypeDef status = HAL_OK;
00328
00329   /* Check the parameters */
00330   assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
00331   assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
00332
00333   /* Configure EXTI 34 interrupts if so required:
00334      scan through PVMType to detect which PVMx is set and
00335      configure the corresponding EXTI line accordingly. */
00336   switch (sConfigPVM->PVMType)
00337   {
00338     case PWR_PVM_USB:
00339       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00340       __HAL_PWR_PVM_EXTI_DISABLE_EVENT();
00341       __HAL_PWR_PVM_EXTI_DISABLE_IT();
00342       __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE();
00343       __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE();
00344
00345       /* Configure interrupt mode */
00346       if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00347       {
00348         __HAL_PWR_PVM_EXTI_ENABLE_IT();
00349       }
00350
00351       /* Configure event mode */
00352       if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00353       {
00354         __HAL_PWR_PVM_EXTI_ENABLE_EVENT();
00355       }
00356
00357       /* Configure the edge */
00358       if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00359       {
00360         __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE();
00361       }
00362
00363       if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00364       {
00365         __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE();
00366       }
00367       break;
00368
00369     default:
00370       status = HAL_ERROR;
00371       break;
00372   }
00373
00374   return status;
00375 }
00376 #endif /* PWR_PVM_SUPPORT */
00377 /**
00378   * @brief  Enable Internal Wake-up Line.
00379   * @retval None
00380   */
00381 void HAL_PWREx_EnableInternalWakeUpLine(void)
00382 {
00383   SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
00384 }
00385
00386 /**
00387   * @brief  Disable Internal Wake-up Line.
00388   * @retval None
00389   */
00390 void HAL_PWREx_DisableInternalWakeUpLine(void)
00391 {
00392   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
00393 }
00394
00395 /**
00396   * @brief  Enable GPIO pull-up state in Standby and Shutdown modes.
00397   * @note   Set the relevant PUy bit of PWR_PUCRx register to configure the I/O in
00398   *         pull-up state in Standby and Shutdown modes.
00399   * @note   This state is effective in Standby and Shutdown modes only if APC bit
00400   *         is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00401   * @note   The configuration is lost when exiting the Shutdown mode due to the
00402   *         power-on reset, maintained when exiting the Standby mode.
00403   * @note   To avoid any conflict at Standby and Shutdown modes exits, the corresponding
00404   *         PDy bit of PWR_PDCRx register is cleared unless it is reserved.
00405   * @param  GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F
00406   *         to select the GPIO peripheral.
00407   * @param  GPIONumber Specify the I/O pins numbers.
00408   *         This parameter can be one of the following values:
00409   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less
00410   *         I/O pins are available) or the logical OR of several of them to set
00411   *         several bits for a given port in a single API call.
00412   * @retval HAL Status
00413   */
00414 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00415 {
00416   HAL_StatusTypeDef status = HAL_OK;
00417
00418   assert_param(IS_PWR_GPIO(GPIO));
00419   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00420
00421   switch (GPIO)
00422   {
00423     case PWR_GPIO_A:
00424       SET_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14));
00425       CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13));
00426       break;
00427
00428     case PWR_GPIO_B:
00429       SET_BIT(PWR->PUCRB, GPIONumber);
00430       CLEAR_BIT(PWR->PDCRB, GPIONumber);
00431       break;
00432
00433     case PWR_GPIO_C:
00434       SET_BIT(PWR->PUCRC, GPIONumber);
00435       CLEAR_BIT(PWR->PDCRC, GPIONumber);
00436       break;
00437
00438     case PWR_GPIO_D:
00439       SET_BIT(PWR->PUCRD, GPIONumber);
00440       CLEAR_BIT(PWR->PDCRD, GPIONumber);
00441       break;
00442
00443 #if defined(GPI0E)
00444     case PWR_GPIO_E:
00445       SET_BIT(PWR->PUCRE, GPIONumber);
00446       CLEAR_BIT(PWR->PDCRE, GPIONumber);
00447       break;
00448 #endif /* GPI0E */
00449     case PWR_GPIO_F:
00450       SET_BIT(PWR->PUCRF, GPIONumber);
00451       CLEAR_BIT(PWR->PDCRF, GPIONumber);
00452       break;
00453
00454     default:
00455       status = HAL_ERROR;
00456       break;
00457   }
00458
00459   return status;
00460 }
00461
00462
00463 /**
00464   * @brief  Disable GPIO pull-up state in Standby mode and Shutdown modes.
00465   * @note   Reset the relevant PUy bit of PWR_PUCRx register used to configure the I/O
00466   *         in pull-up state in Standby and Shutdown modes.
00467   * @param  GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F
00468   *         to select the GPIO peripheral.
00469   * @param  GPIONumber Specify the I/O pins numbers.
00470   *         This parameter can be one of the following values:
00471   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less
00472   *         I/O pins are available) or the logical OR of several of them to reset
00473   *         several bits for a given port in a single API call.
00474   * @retval HAL Status
00475   */
00476 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00477 {
00478   HAL_StatusTypeDef status = HAL_OK;
00479
00480   assert_param(IS_PWR_GPIO(GPIO));
00481   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00482
00483   switch (GPIO)
00484   {
00485     case PWR_GPIO_A:
00486       CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14));
00487       break;
00488
00489     case PWR_GPIO_B:
00490       CLEAR_BIT(PWR->PUCRB, GPIONumber);
00491       break;
00492
00493     case PWR_GPIO_C:
00494       CLEAR_BIT(PWR->PUCRC, GPIONumber);
00495       break;
00496
00497     case PWR_GPIO_D:
00498       CLEAR_BIT(PWR->PUCRD, GPIONumber);
00499       break;
00500
00501 #if defined(GPI0E)
00502     case PWR_GPIO_E:
00503       CLEAR_BIT(PWR->PUCRE, GPIONumber);
00504       break;
00505 #endif /* GPI0E */
00506     case PWR_GPIO_F:
00507       CLEAR_BIT(PWR->PUCRF, GPIONumber);
00508       break;
00509
00510     default:
00511       status = HAL_ERROR;
00512       break;
00513   }
00514
00515   return status;
00516 }
00517
00518
00519 /**
00520   * @brief  Enable GPIO pull-down state in Standby and Shutdown modes.
00521   * @note   Set the relevant PDy bit of PWR_PDCRx register to configure the I/O in
00522   *         pull-down state in Standby and Shutdown modes.
00523   * @note   This state is effective in Standby and Shutdown modes only if APC bit
00524   *         is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00525   * @note   The configuration is lost when exiting the Shutdown mode due to the
00526   *         power-on reset, maintained when exiting the Standby mode.
00527   * @note   To avoid any conflict at Standby and Shutdown modes exits, the corresponding
00528   *         PUy bit of PWR_PUCRx register is cleared unless it is reserved.
00529   * @param  GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F
00530   *         to select the GPIO peripheral.
00531   * @param  GPIONumber Specify the I/O pins numbers.
00532   *         This parameter can be one of the following values:
00533   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less
00534   *         I/O pins are available) or the logical OR of several of them to set
00535   *         several bits for a given port in a single API call.
00536   * @retval HAL Status
00537   */
00538 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
00539 {
00540   HAL_StatusTypeDef status = HAL_OK;
00541
00542   assert_param(IS_PWR_GPIO(GPIO));
00543   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00544
00545   switch (GPIO)
00546   {
00547     case PWR_GPIO_A:
00548       SET_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13));
00549       CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14));
00550       break;
00551
00552     case PWR_GPIO_B:
00553       SET_BIT(PWR->PDCRB, GPIONumber);
00554       CLEAR_BIT(PWR->PUCRB, GPIONumber);
00555       break;
00556
00557     case PWR_GPIO_C:
00558       SET_BIT(PWR->PDCRC, GPIONumber);
00559       CLEAR_BIT(PWR->PUCRC, GPIONumber);
00560       break;
00561
00562     case PWR_GPIO_D:
00563       SET_BIT(PWR->PDCRD, GPIONumber);
00564       CLEAR_BIT(PWR->PUCRD, GPIONumber);
00565       break;
00566
00567 #if defined(GPIOE)
00568     case PWR_GPIO_E:
00569       SET_BIT(PWR->PDCRE, GPIONumber);
00570       CLEAR_BIT(PWR->PUCRE, GPIONumber);
00571       break;
00572 #endif /* GPI0E */
00573     case PWR_GPIO_F:
00574       SET_BIT(PWR->PDCRF, GPIONumber);
00575       CLEAR_BIT(PWR->PUCRF, GPIONumber);
00576       break;
00577
00578     default:
00579       status = HAL_ERROR;
00580       break;
00581   }
00582
00583   return status;
00584 }
00585
00586
00587 /**
00588   * @brief  Disable GPIO pull-down state in Standby and Shutdown modes.
00589   * @note   Reset the relevant PDy bit of PWR_PDCRx register used to configure the I/O
00590   *         in pull-down state in Standby and Shutdown modes.
00591   * @param  GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F
00592   *         to select the GPIO peripheral.
00593   * @param  GPIONumber Specify the I/O pins numbers.
00594   *         This parameter can be one of the following values:
00595   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less
00596   *         I/O pins are available) or the logical OR of several of them to reset
00597   *         several bits for a given port in a single API call.
00598   * @retval HAL Status
00599   */
00600 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
00601 {
00602   HAL_StatusTypeDef status = HAL_OK;
00603
00604   assert_param(IS_PWR_GPIO(GPIO));
00605   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00606
00607   switch (GPIO)
00608   {
00609     case PWR_GPIO_A:
00610       CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13));
00611       break;
00612
00613     case PWR_GPIO_B:
00614       CLEAR_BIT(PWR->PDCRB, GPIONumber);
00615       break;
00616
00617     case PWR_GPIO_C:
00618       CLEAR_BIT(PWR->PDCRC, GPIONumber);
00619       break;
00620
00621     case PWR_GPIO_D:
00622       CLEAR_BIT(PWR->PDCRD, GPIONumber);
00623       break;
00624
00625 #if defined(GPIOE)
00626     case PWR_GPIO_E:
00627       CLEAR_BIT(PWR->PDCRE, GPIONumber);
00628       break;
00629 #endif /* GPI0E */
00630     case PWR_GPIO_F:
00631       CLEAR_BIT(PWR->PDCRF, GPIONumber);
00632       break;
00633
00634     default:
00635       status = HAL_ERROR;
00636       break;
00637   }
00638
00639   return status;
00640 }
00641
00642
00643 /**
00644   * @brief  Enable pull-up and pull-down configuration.
00645   * @note   When APC bit is set, the I/O pull-up and pull-down configurations defined in
00646   *         PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
00647   * @note   Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
00648   *         PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
00649   *         HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() APIs ensure there
00650   *         is no conflict when setting PUy or PDy bit.
00651   * @retval None
00652   */
00653 void HAL_PWREx_EnablePullUpPullDownConfig(void)
00654 {
00655   SET_BIT(PWR->CR3, PWR_CR3_APC);
00656 }
00657
00658 /**
00659   * @brief  Disable pull-up and pull-down configuration.
00660   * @note   When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
00661   *         PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
00662   * @retval None
00663   */
00664 void HAL_PWREx_DisablePullUpPullDownConfig(void)
00665 {
00666   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
00667 }
00668
00669 #if defined(PWR_CR3_RRS)
00670 /**
00671   * @brief Enable SRAM content retention in Standby mode.
00672   * @note  When RRS bit is set, SRAM is powered by the low-power regulator in
00673   *         Standby mode and its content is kept.
00674   * @retval None
00675   */
00676 void HAL_PWREx_EnableSRAMRetention(void)
00677 {
00678   SET_BIT(PWR->CR3, PWR_CR3_RRS);
00679 }
00680
00681
00682 /**
00683   * @brief Disable SRAM content retention in Standby mode.
00684   * @note  When RRS bit is reset, SRAM is powered off in Standby mode
00685   *        and its content is lost.
00686   * @retval None
00687   */
00688 void HAL_PWREx_DisableSRAMRetention(void)
00689 {
00690   CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
00691 }
00692 #endif /* PWR_CR3_RRS */
00693
00694 /**
00695   * @brief  Enable Flash Power Down.
00696   * @note   This API allows to enable flash power down capabilities in low power
00697   *         run, low power sleep and stop modes.
00698   * @param  PowerMode this can be a combination of following values:
00699   *           @arg @ref PWR_FLASHPD_LPRUN
00700   *           @arg @ref PWR_FLASHPD_LPSLEEP
00701   *           @arg @ref PWR_FLASHPD_STOP
00702   * @retval None
00703   */
00704 void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)
00705 {
00706   assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
00707
00708   PWR->CR1 |= PowerMode;
00709 }
00710
00711
00712 /**
00713   * @brief  Disable Flash Power Down.
00714   * @note   This API allows to disable flash power down capabilities in low power
00715   *         run, low power sleep and stop modes.
00716   * @param  PowerMode this can be a combination of following values:
00717   *           @arg @ref PWR_FLASHPD_LPRUN
00718   *           @arg @ref PWR_FLASHPD_LPSLEEP
00719   *           @arg @ref PWR_FLASHPD_STOP
00720   * @retval None
00721   */
00722 void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode)
00723 {
00724   assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
00725
00726   PWR->CR1 &= ~PowerMode;
00727 }
00728
00729
00730 /**
00731   * @brief   Return Voltage Scaling Range.
00732   * @retval  VOS bit field:
00733   *         @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1
00734   *         @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2
00735   */
00736 uint32_t HAL_PWREx_GetVoltageRange(void)
00737 {
00738   return (PWR->CR1 & PWR_CR1_VOS);
00739 }
00740
00741
00742 /**
00743   * @brief Configure the main regulator output voltage.
00744   * @param  VoltageScaling specifies the regulator output voltage to achieve
00745   *         a tradeoff between performance and power consumption.
00746   *         This parameter can be one of the following values:
00747   *          @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
00748   *                                                typical output voltage at 1.2 V,
00749   *                                                system frequency up to 64 MHz.
00750   *          @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
00751   *                                                typical output voltage at 1.0 V,
00752   *                                                system frequency up to 16 MHz.
00753   * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
00754   *        a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
00755   *        When moving from Range 2 to Range 1, the system frequency can be increased to
00756   *        a value up to 64 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
00757   * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be
00758   *        cleared before returning the status. If the flag is not cleared within
00759   *        6 microseconds, HAL_TIMEOUT status is reported.
00760   * @retval HAL Status
00761   */
00762 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
00763 {
00764   uint32_t wait_loop_index;
00765
00766   assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
00767
00768   /* Modify voltage scaling range */
00769   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
00770
00771   /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
00772   if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
00773   {
00774     /* Set timeout value */
00775     wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
00776
00777     /* Wait until VOSF is reset */
00778     while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
00779     {
00780       if (wait_loop_index != 0U)
00781       {
00782         wait_loop_index--;
00783       }
00784       else
00785       {
00786         return HAL_TIMEOUT;
00787       }
00788     }
00789   }
00790
00791   return HAL_OK;
00792 }
00793
00794
00795
00796 /**
00797   * @brief Enter Low-power Run mode
00798   * @note  System clock frequency has to be decreased below 2 MHz before entering
00799   *        low power run mode
00800   * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.
00801   * @retval None
00802   */
00803 void HAL_PWREx_EnableLowPowerRunMode(void)
00804 {
00805   /* Set Regulator parameter */
00806   SET_BIT(PWR->CR1, PWR_CR1_LPR);
00807 }
00808
00809
00810 /**
00811   * @brief Exit Low-power Run mode.
00812   * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
00813   *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
00814   *        returns HAL_TIMEOUT status). The system clock frequency can then be
00815   *        increased above 2 MHz.
00816   * @retval HAL Status
00817   */
00818 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
00819 {
00820   uint32_t wait_loop_index = ((PWR_REGLPF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
00821
00822   /* Clear LPR bit */
00823   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
00824
00825   /* Wait until REGLPF is reset */
00826   while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
00827   {
00828     if (wait_loop_index != 0U)
00829     {
00830       wait_loop_index--;
00831     }
00832     else
00833     {
00834       return HAL_TIMEOUT;
00835     }
00836   }
00837
00838   return HAL_OK;
00839 }
00840
00841
00842 #if defined(PWR_SHDW_SUPPORT)
00843 /**
00844   * @brief  Enter Shutdown mode.
00845   * @note   In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched
00846   *         off. The voltage regulator is disabled and Vcore domain is powered off.
00847   *         SRAM and registers contents are lost except for registers in the Backup domain.
00848   *         The BOR is not available.
00849   * @note   The I/Os can be configured either with a pull-up or pull-down or can
00850   *         be kept in analog state.
00851   *         HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown()
00852   *         respectively enable Pull Up and PullDown state.
00853   *         HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown()
00854   *         disable the same. These states are effective in Standby mode only if
00855   *         APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00856   * @retval None
00857
00858   * @retval None
00859   */
00860 void HAL_PWREx_EnterSHUTDOWNMode(void)
00861 {
00862   /* Set Shutdown mode */
00863   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN);
00864
00865   /* Set SLEEPDEEP bit of Cortex System Control Register */
00866   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00867
00868   /* This option is used to ensure that store operations are completed */
00869 #if defined ( __CC_ARM)
00870   __force_stores();
00871 #endif /* __CC_ARM */
00872
00873   /* Request Wait For Interrupt */
00874   __WFI();
00875 }
00876 #endif /* PWR_SHDW_SUPPORT */
00877
00878 #if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT)
00879 /**
00880   * @brief  This function handles the PWR PVD interrupt request.
00881   * @note   This API should be called under the PVD_IRQHandler().
00882   * @retval None
00883   */
00884 void HAL_PWREx_PVD_PVM_IRQHandler(void)
00885 {
00886   /* Check PWR PVD exti Rising flag */
00887   if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U)
00888   {
00889     /* Clear PVD exti pending bit */
00890     __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG();
00891
00892     /* PWR PVD interrupt rising user callback */
00893     HAL_PWREx_PVD_PVM_Rising_Callback();
00894   }
00895
00896   /* Check PWR exti fallling flag */
00897   if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U)
00898   {
00899     /* Clear PVD exti pending bit */
00900     __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG();
00901
00902     /* PWR PVD interrupt falling user callback */
00903     HAL_PWREx_PVD_PVM_Falling_Callback();
00904   }
00905
00906   /* Check PWR PVM exti Rising flag */
00907   if (__HAL_PWR_PVM_EXTI_GET_RISING_FLAG() != 0x0U)
00908   {
00909     /* Clear PVM exti pending bit */
00910     __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG();
00911
00912     /* PWR PVD PVM interrupt rising user callback */
00913     HAL_PWREx_PVD_PVM_Rising_Callback();
00914   }
00915
00916   /* Check PWR PVM exti fallling flag */
00917   if (__HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() != 0x0U)
00918   {
00919     /* Clear PVM exti pending bit */
00920     __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG();
00921
00922     /* PWR PVM interrupt falling user callback */
00923     HAL_PWREx_PVD_PVM_Falling_Callback();
00924   }
00925 }
00926
00927 /**
00928   * @brief  PWR PVD interrupt rising callback
00929   * @retval None
00930   */
00931 __weak void HAL_PWREx_PVD_PVM_Rising_Callback(void)
00932 {
00933   /* NOTE : This function should not be modified; when the callback is needed,
00934             the HAL_PWR_PVD_Rising_Callback can be implemented in the user file
00935   */
00936 }
00937
00938 /**
00939   * @brief  PWR PVD interrupt Falling callback
00940   * @retval None
00941   */
00942 __weak void HAL_PWREx_PVD_PVM_Falling_Callback(void)
00943 {
00944   /* NOTE : This function should not be modified; when the callback is needed,
00945             the HAL_PWR_PVD_Falling_Callback can be implemented in the user file
00946   */
00947 }
00948 #elif defined(PWR_PVD_SUPPORT)
00949 /**
00950   * @brief  This function handles the PWR PVD interrupt request.
00951   * @note   This API should be called under the PVD_IRQHandler().
00952   * @retval None
00953   */
00954 void HAL_PWREx_PVD_IRQHandler(void)
00955 {
00956   /* Check PWR exti Rising flag */
00957   if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U)
00958   {
00959     /* Clear PVD exti pending bit */
00960     __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG();
00961
00962     /* PWR PVD interrupt rising user callback */
00963     HAL_PWREx_PVD_Rising_Callback();
00964   }
00965
00966   /* Check PWR exti fallling flag */
00967   if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U)
00968   {
00969     /* Clear PVD exti pending bit */
00970     __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG();
00971
00972     /* PWR PVD interrupt falling user callback */
00973     HAL_PWREx_PVD_Falling_Callback();
00974   }
00975 }
00976
00977 /**
00978   * @brief  PWR PVD interrupt rising callback
00979   * @retval None
00980   */
00981 __weak void HAL_PWREx_PVD_Rising_Callback(void)
00982 {
00983   /* NOTE : This function should not be modified; when the callback is needed,
00984             the HAL_PWR_PVD_Rising_Callback can be implemented in the user file
00985   */
00986 }
00987
00988 /**
00989   * @brief  PWR PVD interrupt Falling callback
00990   * @retval None
00991   */
00992 __weak void HAL_PWREx_PVD_Falling_Callback(void)
00993 {
00994   /* NOTE : This function should not be modified; when the callback is needed,
00995             the HAL_PWR_PVD_Falling_Callback can be implemented in the user file
00996   */
00997 }
00998
00999 #endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */
01000
01001 /**
01002   * @}
01003   */
01004
01005 /**
01006   * @}
01007   */
01008
01009 #endif /* HAL_PWR_MODULE_ENABLED */
01010 /**
01011   * @}
01012   */
01013
01014 /**
01015   * @}
01016   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_pwr_ex.h Source File

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stm32g0xx_hal_pwr_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_PWR_EX_H
00021 #define STM32G0xx_HAL_PWR_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup PWREx PWREx
00035   * @brief PWR Extended HAL module driver
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
00041   * @{
00042   */
00043
00044 #if defined(PWR_PVM_SUPPORT)
00045 /**
00046   * @brief  PWR PVM configuration structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.
00051                            This parameter can be a value of @ref PWREx_PVM_Type.
00052                            @arg @ref PWR_PVM_USB Peripheral Voltage Monitoring USB enable */
00053
00054   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00055                            This parameter can be a value of @ref PWREx_PVM_Mode. */
00056 } PWR_PVMTypeDef;
00057 #endif /* PWR_PVM_SUPPORT */
00058
00059 #if defined(PWR_PVD_SUPPORT)
00060 /**
00061   * @brief  PWR PVD configuration structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t PVDLevel;    /*!< PVDLevel: Specifies the PVD detection level.
00066                               This parameter can be a value or a combination of
00067                               @ref PWR_PVD_detection_level. */
00068
00069   uint32_t Mode;        /*!< Mode: Specifies the operating mode for the selected pins.
00070                               This parameter can be a value of @ref PWR_PVD_Mode. */
00071 } PWR_PVDTypeDef;
00072 #endif /* PWR_PVD_SUPPORT */
00073
00074 /**
00075   * @}
00076   */
00077 /* Exported constants --------------------------------------------------------*/
00078 /** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
00079   * @{
00080   */
00081 #if defined(PWR_PVD_SUPPORT)
00082 /** @defgroup PWR_PVD_detection_level  Programmable Voltage Detection levels
00083   * @note   see datasheet for selection voltage value
00084   * @{
00085   */
00086 #define PWR_PVDLEVEL_RISING_0               (0x00000000u)                                           /*!< PVD threshold level 0 for rising detection */
00087 #define PWR_PVDLEVEL_RISING_1               (PWR_CR2_PVDRT_0)                                       /*!< PVD threshold level 1 for rising detection */
00088 #define PWR_PVDLEVEL_RISING_2               (PWR_CR2_PVDRT_1)                                       /*!< PVD threshold level 2 for rising detection */
00089 #define PWR_PVDLEVEL_RISING_3               (PWR_CR2_PVDRT_0 | PWR_CR2_PVDRT_1)                     /*!< PVD threshold level 3 for rising detection */
00090 #define PWR_PVDLEVEL_RISING_4               (PWR_CR2_PVDRT_2)                                       /*!< PVD threshold level 4 for rising detection */
00091 #define PWR_PVDLEVEL_RISING_5               (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0)                     /*!< PVD threshold level 5 for rising detection */
00092 #define PWR_PVDLEVEL_RISING_6               (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1)                     /*!< PVD threshold level 6 for rising detection */
00093 #define PWR_PVDLEVEL_FALLING_0              (0x00000000u)                                           /*!< PVD threshold level 0 for falling detection */
00094 #define PWR_PVDLEVEL_FALLING_1              (PWR_CR2_PVDFT_0)                                       /*!< PVD threshold level 1 for falling detection */
00095 #define PWR_PVDLEVEL_FALLING_2              (PWR_CR2_PVDFT_1)                                       /*!< PVD threshold level 2 for falling detection */
00096 #define PWR_PVDLEVEL_FALLING_3              (PWR_CR2_PVDFT_0 | PWR_CR2_PVDFT_1)                     /*!< PVD threshold level 3 for falling detection */
00097 #define PWR_PVDLEVEL_FALLING_4              (PWR_CR2_PVDFT_2)                                       /*!< PVD threshold level 4 for falling detection */
00098 #define PWR_PVDLEVEL_FALLING_5              (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0)                     /*!< PVD threshold level 5 for falling detection */
00099 #define PWR_PVDLEVEL_FALLING_6              (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1)                     /*!< PVD threshold level 6 for falling detection */
00100 #define PWR_PVDLEVEL_0                      (PWR_PVDLEVEL_RISING_0 | PWR_PVDLEVEL_FALLING_0)        /*!< same PVD threshold level 0 on rising & falling */
00101 #define PWR_PVDLEVEL_1                      (PWR_PVDLEVEL_RISING_1 | PWR_PVDLEVEL_FALLING_1)        /*!< same PVD threshold level 1 on rising & falling */
00102 #define PWR_PVDLEVEL_2                      (PWR_PVDLEVEL_RISING_2 | PWR_PVDLEVEL_FALLING_2)        /*!< same PVD threshold level 2 on rising & falling */
00103 #define PWR_PVDLEVEL_3                      (PWR_PVDLEVEL_RISING_3 | PWR_PVDLEVEL_FALLING_3)        /*!< same PVD threshold level 3 on rising & falling */
00104 #define PWR_PVDLEVEL_4                      (PWR_PVDLEVEL_RISING_4 | PWR_PVDLEVEL_FALLING_4)        /*!< same PVD threshold level 4 on rising & falling */
00105 #define PWR_PVDLEVEL_5                      (PWR_PVDLEVEL_RISING_5 | PWR_PVDLEVEL_FALLING_5)        /*!< same PVD threshold level 5 on rising & falling */
00106 #define PWR_PVDLEVEL_6                      (PWR_PVDLEVEL_RISING_6 | PWR_PVDLEVEL_FALLING_6)        /*!< same PVD threshold level 6 on rising & falling */
00107 #define PWR_PVDLEVEL_7                      (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)   /*!< External input analog voltage (compared internally to VREFINT) */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
00113   * @{
00114   */
00115 #define PWR_PVD_MODE_NORMAL                 (0x00000000u)  /*!< basic mode is used */
00116 #define PWR_PVD_MODE_IT_RISING              (0x00010001u)  /*!< External Interrupt Mode with Rising edge trigger detection */
00117 #define PWR_PVD_MODE_IT_FALLING             (0x00010002u)  /*!< External Interrupt Mode with Falling edge trigger detection */
00118 #define PWR_PVD_MODE_IT_RISING_FALLING      (0x00010003u)  /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00119 #define PWR_PVD_MODE_EVENT_RISING           (0x00020001u)  /*!< Event Mode with Rising edge trigger detection */
00120 #define PWR_PVD_MODE_EVENT_FALLING          (0x00020002u)  /*!< Event Mode with Falling edge trigger detection */
00121 #define PWR_PVD_MODE_EVENT_RISING_FALLING   (0x00020003u)  /*!< Event Mode with Rising/Falling edge trigger detection */
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
00127   * @{
00128   */
00129 #define PWR_EXTI_LINE_PVD                   (EXTI_IMR1_IM16)  /*!< External interrupt line 16 connected to PVD */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
00135   * @{
00136   */
00137 #define PWR_EVENT_LINE_PVD                  (EXTI_EMR1_EM16)  /*!< Event line 16 connected to PVD */
00138 /**
00139   * @}
00140   */
00141 #endif /* PWR_PVD_SUPPORT */
00142
00143 #if defined(PWR_PVM_SUPPORT)
00144 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
00145   * @{
00146   */
00147 #define PWR_PVM_USB                  PWR_CR2_PVMEN_USB  /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */
00148 /**
00149   * @}
00150   */
00151 /** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
00152   * @{
00153   */
00154 #define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
00155 #define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
00156 #define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
00157 #define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00158 #define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
00159 #define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
00160 #define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
00161 /**
00162   * @}
00163   */
00164 /** @defgroup PWR_PVM_EXTI_LINE  PWR PVM external interrupt line
00165   * @{
00166   */
00167 #define PWR_EXTI_LINE_PVM                   (EXTI_IMR2_IM34)  /*!< External interrupt line 34 connected to PVM */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup PWR_PVM_EVENT_LINE  PWR PVM event line
00173   * @{
00174   */
00175 #define PWR_EVENT_LINE_PVM                  (EXTI_EMR2_EM34)  /*!< Event line 34 connected to PVM */
00176 /**
00177   * @}
00178   */
00179 #endif /* PWR_PVM_SUPPORT */
00180
00181 /** @defgroup PWREx_VBAT_Battery_Charging_Selection  PWR battery charging resistor selection
00182   * @{
00183   */
00184 #define PWR_BATTERY_CHARGING_RESISTOR_5     (0x00000000u)   /*!< VBAT charging through a 5 kOhms resistor   */
00185 #define PWR_BATTERY_CHARGING_RESISTOR_1_5   PWR_CR4_VBRS    /*!< VBAT charging through a 1.5 kOhms resistor */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup PWREx_GPIO_Bit_Number  GPIO bit position
00191   * @brief    for I/O pull up/down setting in standby/shutdown mode
00192   * @{
00193   */
00194 #define PWR_GPIO_BIT_0                      PWR_PUCRB_PU0   /*!< GPIO port I/O pin 0  */
00195 #define PWR_GPIO_BIT_1                      PWR_PUCRB_PU1   /*!< GPIO port I/O pin 1  */
00196 #define PWR_GPIO_BIT_2                      PWR_PUCRB_PU2   /*!< GPIO port I/O pin 2  */
00197 #define PWR_GPIO_BIT_3                      PWR_PUCRB_PU3   /*!< GPIO port I/O pin 3  */
00198 #define PWR_GPIO_BIT_4                      PWR_PUCRB_PU4   /*!< GPIO port I/O pin 4  */
00199 #define PWR_GPIO_BIT_5                      PWR_PUCRB_PU5   /*!< GPIO port I/O pin 5  */
00200 #define PWR_GPIO_BIT_6                      PWR_PUCRB_PU6   /*!< GPIO port I/O pin 6  */
00201 #define PWR_GPIO_BIT_7                      PWR_PUCRB_PU7   /*!< GPIO port I/O pin 7  */
00202 #define PWR_GPIO_BIT_8                      PWR_PUCRB_PU8   /*!< GPIO port I/O pin 8  */
00203 #define PWR_GPIO_BIT_9                      PWR_PUCRB_PU9   /*!< GPIO port I/O pin 9  */
00204 #define PWR_GPIO_BIT_10                     PWR_PUCRB_PU10  /*!< GPIO port I/O pin 10 */
00205 #define PWR_GPIO_BIT_11                     PWR_PUCRB_PU11  /*!< GPIO port I/O pin 11 */
00206 #define PWR_GPIO_BIT_12                     PWR_PUCRB_PU12  /*!< GPIO port I/O pin 12 */
00207 #define PWR_GPIO_BIT_13                     PWR_PUCRB_PU13  /*!< GPIO port I/O pin 13 */
00208 #define PWR_GPIO_BIT_14                     PWR_PUCRB_PU14  /*!< GPIO port I/O pin 14 */
00209 #define PWR_GPIO_BIT_15                     PWR_PUCRB_PU15  /*!< GPIO port I/O pin 15 */
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup PWREx_GPIO_Port  GPIO Port
00215   * @{
00216   */
00217 #define PWR_GPIO_A                          (0x00000000u)  /*!< GPIO port A */
00218 #define PWR_GPIO_B                          (0x00000001u)  /*!< GPIO port B */
00219 #define PWR_GPIO_C                          (0x00000002u)  /*!< GPIO port C */
00220 #define PWR_GPIO_D                          (0x00000003u)  /*!< GPIO port D */
00221 #if defined (GPIOE)
00222 #define PWR_GPIO_E                          (0x00000004u)  /*!< GPIO port E */
00223 #endif /* GPIOE */
00224 #define PWR_GPIO_F                          (0x00000005u)  /*!< GPIO port F */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup PWREx_Flash_PowerDown  Flash Power Down modes
00230   * @{
00231   */
00232 #define PWR_FLASHPD_LPRUN                   PWR_CR1_FPD_LPRUN  /*!< Enable Flash power down in low power run mode */
00233 #define PWR_FLASHPD_LPSLEEP                 PWR_CR1_FPD_LPSLP  /*!< Enable Flash power down in low power sleep mode */
00234 #define PWR_FLASHPD_STOP                    PWR_CR1_FPD_STOP   /*!< Enable Flash power down in stop mode */
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
00240   * @{
00241   */
00242 #define PWR_REGULATOR_VOLTAGE_SCALE1        PWR_CR1_VOS_0  /*!< Voltage scaling range 1 */
00243 #define PWR_REGULATOR_VOLTAGE_SCALE2        PWR_CR1_VOS_1  /*!< Voltage scaling range 2 */
00244 /**
00245   * @}
00246   */
00247
00248 /** @addtogroup PWR_Flag  PWR Status Flags
00249   * @brief  Elements values convention: 0000 00XX 000Y YYYYb
00250   *           - Y YYYY  : Flag position in the XX register (5 bits)
00251   *           - XX  : Status register (2 bits)
00252   *                 - 01: SR1 register
00253   *                 - 10: SR2 register
00254   *         The only exception is PWR_FLAG_WU, encompassing all
00255   *         wake-up flags and set to PWR_SR1_WUF.
00256   * @{
00257   */
00258 #if defined(PWR_PVM_SUPPORT)
00259 #define PWR_FLAG_PVMOUSB                    (0x00020000u | PWR_SR2_PVMO_USB)   /*!< USB Peripheral Voltage Monitoring output */
00260 #endif /* PWR_PVM_SUPPORT */
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /* Exported macros -----------------------------------------------------------*/
00270 /** @addtogroup PWREx_Exported_Macros  PWR Extended Exported Macros
00271   * @{
00272   */
00273 #if defined(PWR_PVD_SUPPORT)
00274 /**
00275   * @brief Enable the PVD Extended Interrupt Line.
00276   * @retval None
00277   */
00278 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()            SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
00279
00280 /**
00281   * @brief Disable the PVD Extended Interrupt Line.
00282   * @retval None
00283   */
00284 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()           CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
00285
00286 /**
00287   * @brief Enable the PVD Event Line.
00288   * @retval None
00289   */
00290 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()         SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
00291
00292 /**
00293   * @brief Disable the PVD Event Line.
00294   * @retval None
00295   */
00296 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()        CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
00297
00298 /**
00299   * @brief Enable the PVD Extended Interrupt Rising Trigger.
00300   * @retval None
00301   */
00302 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00303
00304 /**
00305   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00306   * @retval None
00307   */
00308 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00309
00310 /**
00311   * @brief Enable the PVD Extended Interrupt Falling Trigger.
00312   * @retval None
00313   */
00314 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00315
00316 /**
00317   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00318   * @retval None
00319   */
00320 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00321
00322 /**
00323   * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
00324   * @retval None
00325   */
00326 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00327   do {                                                   \
00328     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
00329     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
00330   } while(0U)
00331
00332 /**
00333   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00334   * @retval None
00335   */
00336 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00337   do {                                                    \
00338     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
00339     __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
00340   } while(0U)
00341
00342 /**
00343   * @brief  Generate a Software interrupt on selected EXTI line.
00344   * @retval None
00345   */
00346 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()        SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
00347
00348 /**
00349   * @brief Check whether or not the PVD EXTI interrupt Rising flag is set.
00350   * @retval EXTI PVD Line Status.
00351   */
00352 #define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG()      (EXTI->RPR1 & PWR_EXTI_LINE_PVD)
00353
00354 /**
00355   * @brief Check whether or not the PVD EXTI interrupt Falling flag is set.
00356   * @retval EXTI PVD Line Status.
00357   */
00358 #define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG()     (EXTI->FPR1 & PWR_EXTI_LINE_PVD)
00359
00360 /**
00361   * @brief Clear the PVD EXTI interrupt Rising flag.
00362   * @retval None
00363   */
00364 #define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG()    WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD)
00365
00366 /**
00367   * @brief Clear the PVD EXTI interrupt Falling flag.
00368   * @retval None
00369   */
00370 #define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG()   WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD)
00371 #endif /* PWR_PVD_SUPPORT */
00372
00373 #if defined(PWR_PVM_SUPPORT)
00374 /**
00375   * @brief Enable the PVM Extended Interrupt Line.
00376   * @retval None
00377   */
00378 #define __HAL_PWR_PVM_EXTI_ENABLE_IT()            SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)
00379
00380 /**
00381   * @brief Disable the PVM Extended Interrupt Line.
00382   * @retval None
00383   */
00384 #define __HAL_PWR_PVM_EXTI_DISABLE_IT()           CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)
00385
00386 /**
00387   * @brief Enable the PVM Event Line.
00388   * @retval None
00389   */
00390 #define __HAL_PWR_PVM_EXTI_ENABLE_EVENT()         SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)
00391
00392 /**
00393   * @brief Disable the PVM Event Line.
00394   * @retval None
00395   */
00396 #define __HAL_PWR_PVM_EXTI_DISABLE_EVENT()        CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)
00397
00398 /**
00399   * @brief Enable the PVM Extended Interrupt Rising Trigger.
00400   * @retval None
00401   */
00402 #define __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)
00403
00404 /**
00405   * @brief Disable the PVM Extended Interrupt Rising Trigger.
00406   * @retval None
00407   */
00408 #define __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)
00409
00410 /**
00411   * @brief Enable the PVM Extended Interrupt Falling Trigger.
00412   * @retval None
00413   */
00414 #define __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)
00415
00416 /**
00417   * @brief Disable the PVM Extended Interrupt Falling Trigger.
00418   * @retval None
00419   */
00420 #define __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)
00421
00422 /**
00423   * @brief  Enable the PVM Extended Interrupt Rising & Falling Trigger.
00424   * @retval None
00425   */
00426 #define __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00427   do {                                                   \
00428     __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE();             \
00429     __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE();            \
00430   } while(0U)
00431
00432 /**
00433   * @brief Disable the PVM Extended Interrupt Rising & Falling Trigger.
00434   * @retval None
00435   */
00436 #define __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00437   do {                                                    \
00438     __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE();             \
00439     __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE();            \
00440   } while(0U)
00441
00442 /**
00443   * @brief  Generate a Software interrupt on selected EXTI line.
00444   * @retval None
00445   */
00446 #define __HAL_PWR_PVM_EXTI_GENERATE_SWIT()        SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM)
00447
00448 /**
00449   * @brief Check whether or not the PVM EXTI interrupt Rising flag is set.
00450   * @retval EXTI PVM Line Status.
00451   */
00452 #define __HAL_PWR_PVM_EXTI_GET_RISING_FLAG()      (EXTI->RPR2 & PWR_EXTI_LINE_PVM)
00453
00454 /**
00455   * @brief Check whether or not the PVM EXTI interrupt Falling flag is set.
00456   * @retval EXTI PVM Line Status.
00457   */
00458 #define __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG()     (EXTI->FPR2 & PWR_EXTI_LINE_PVM)
00459
00460 /**
00461   * @brief Clear the PVM EXTI interrupt Rising flag.
00462   * @retval None
00463   */
00464 #define __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG()    WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM)
00465
00466 /**
00467   * @brief Clear the PVM EXTI interrupt Falling flag.
00468   * @retval None
00469   */
00470 #define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG()   WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM)
00471 #endif /* PWR_PVM_SUPPORT */
00472 /**
00473   * @}
00474   */
00475
00476 /* Private define ------------------------------------------------------------*/
00477 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
00478   * @{
00479   */
00480
00481 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
00482   * @{
00483   */
00484 #define PVM_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVM threshold crossing */
00485 #define PVM_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVM threshold crossing        */
00486 #define PVM_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVM trigger                 */
00487 #define PVM_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVM trigger                */
00488 /**
00489   * @}
00490   */
00491
00492 /**
00493   * @}
00494   */
00495 /* Private macros ------------------------------------------------------------*/
00496 /** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
00497   * @{
00498   */
00499
00500 #define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) || \
00501                                                       ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
00502
00503 #define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__)  ((((__BIT_NUMBER__) & 0x0000FFFFu) != 0x00u) && \
00504                                                  (((__BIT_NUMBER__) & 0xFFFF0000u) == 0x00u))
00505 #if defined (GPIOE)
00506 #define IS_PWR_GPIO(__GPIO__)               (((__GPIO__) == PWR_GPIO_A) || \
00507                                              ((__GPIO__) == PWR_GPIO_B) || \
00508                                              ((__GPIO__) == PWR_GPIO_C) || \
00509                                              ((__GPIO__) == PWR_GPIO_D) || \
00510                                              ((__GPIO__) == PWR_GPIO_E) || \
00511                                              ((__GPIO__) == PWR_GPIO_F))
00512 #else
00513 #define IS_PWR_GPIO(__GPIO__)               (((__GPIO__) == PWR_GPIO_A) || \
00514                                              ((__GPIO__) == PWR_GPIO_B) || \
00515                                              ((__GPIO__) == PWR_GPIO_C) || \
00516                                              ((__GPIO__) == PWR_GPIO_D) || \
00517                                              ((__GPIO__) == PWR_GPIO_F))
00518 #endif /* GPIOE */
00519
00520 #define IS_PWR_FLASH_POWERDOWN(__MODE__)    ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \
00521                                              (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0x00u))
00522
00523 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00524                                              ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
00525
00526 #if defined(PWR_PVD_SUPPORT)
00527 #define IS_PWR_PVD_LEVEL(LEVEL)                   (((LEVEL) & ~(PWR_CR2_PVDRT | PWR_CR2_PVDFT)) == 0x00000000u)
00528
00529 #define IS_PWR_PVD_MODE(MODE)                     (((MODE) == PWR_PVD_MODE_NORMAL)              || \
00530                                                    ((MODE) == PWR_PVD_MODE_IT_RISING)           || \
00531                                                    ((MODE) == PWR_PVD_MODE_IT_FALLING)          || \
00532                                                    ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   || \
00533                                                    ((MODE) == PWR_PVD_MODE_EVENT_RISING)        || \
00534                                                    ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       || \
00535                                                    ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
00536 #endif /* PWR_PVD_SUPPORT */
00537
00538 #if defined(PWR_PVM_SUPPORT)
00539 #define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB)
00540
00541 #define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
00542                                 ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
00543                                 ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
00544                                 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
00545                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
00546                                 ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
00547                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
00548 #endif /* PWR_PVM_SUPPORT */
00549 /**
00550   * @}
00551   */
00552
00553 /* Exported functions --------------------------------------------------------*/
00554 /** @defgroup PWREx_Exported_Functions  PWR Extended Exported Functions
00555   * @{
00556   */
00557
00558 /** @defgroup PWREx_Exported_Functions_Group1  Extended Peripheral Control functions
00559   * @{
00560   */
00561
00562 /* Peripheral Control functions  **********************************************/
00563 void              HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
00564 void              HAL_PWREx_DisableBatteryCharging(void);
00565 #if defined(PWR_CR3_ENB_ULP)
00566 void              HAL_PWREx_EnablePORMonitorSampling(void);
00567 void              HAL_PWREx_DisablePORMonitorSampling(void);
00568 #endif /* PWR_CR3_ENB_ULP */
00569 void              HAL_PWREx_EnableInternalWakeUpLine(void);
00570 void              HAL_PWREx_DisableInternalWakeUpLine(void);
00571 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00572 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00573 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00574 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00575 void              HAL_PWREx_EnablePullUpPullDownConfig(void);
00576 void              HAL_PWREx_DisablePullUpPullDownConfig(void);
00577 #if defined(PWR_CR3_RRS)
00578 void              HAL_PWREx_EnableSRAMRetention(void);
00579 void              HAL_PWREx_DisableSRAMRetention(void);
00580 #endif /* PWR_CR3_RRS */
00581 void              HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
00582 void              HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
00583 uint32_t          HAL_PWREx_GetVoltageRange(void);
00584 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00585 #if defined(PWR_PVD_SUPPORT)
00586 /* Power voltage detection configuration functions ****************************/
00587 HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00588 void              HAL_PWREx_EnablePVD(void);
00589 void              HAL_PWREx_DisablePVD(void);
00590 #endif /* PWR_PVD_SUPPORT */
00591 #if defined(PWR_PVM_SUPPORT)
00592 /* Power voltage monitoring configuration functions ***************************/
00593 void HAL_PWREx_EnableVddIO2(void);
00594 void HAL_PWREx_DisableVddIO2(void);
00595 void HAL_PWREx_EnableVddUSB(void);
00596 void HAL_PWREx_DisableVddUSB(void);
00597 void HAL_PWREx_EnablePVMUSB(void);
00598 void HAL_PWREx_DisablePVMUSB(void);
00599 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
00600 #endif /* PWR_PVM_SUPPORT */
00601
00602 /* Low Power modes configuration functions ************************************/
00603 void              HAL_PWREx_EnableLowPowerRunMode(void);
00604 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
00605 #if defined(PWR_SHDW_SUPPORT)
00606 void              HAL_PWREx_EnterSHUTDOWNMode(void);
00607 #endif /* PWR_SHDW_SUPPORT */
00608
00609 #if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT)
00610 void              HAL_PWREx_PVD_PVM_IRQHandler(void);
00611 void              HAL_PWREx_PVD_PVM_Rising_Callback(void);
00612 void              HAL_PWREx_PVD_PVM_Falling_Callback(void);
00613 #elif defined(PWR_PVD_SUPPORT)
00614 void              HAL_PWREx_PVD_IRQHandler(void);
00615 void              HAL_PWREx_PVD_Rising_Callback(void);
00616 void              HAL_PWREx_PVD_Falling_Callback(void);
00617 #endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */
00618
00619 /**
00620   * @}
00621   */
00622
00623 /**
00624   * @}
00625   */
00626
00627 /**
00628   * @}
00629   */
00630
00631 /**
00632   * @}
00633   */
00634
00635 #ifdef __cplusplus
00636 }
00637 #endif
00638
00639
00640 #endif /* STM32G0xx_HAL_PWR_EX_H */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rcc.c Source File

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stm32g0xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                       ##### RCC specific features #####
00014   ==============================================================================
00015     [..]
00016       After reset the device is running from High Speed Internal oscillator
00017       (from 8 MHz to reach 16MHz) with Flash 0 wait state. Flash prefetch buffer,
00018       D-Cache and I-Cache are disabled, and all peripherals are off except internal
00019       SRAM, Flash and JTAG.
00020
00021       (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses:
00022           all peripherals mapped on these buses are running at HSI speed.
00023       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00024       (+) All GPIOs are in analog mode, except the JTAG pins which
00025           are assigned to be used for debug purpose.
00026
00027     [..]
00028       Once the device started from reset, the user application has to:
00029       (+) Configure the clock source to be used to drive the System clock
00030           (if the application needs higher frequency/performance)
00031       (+) Configure the System clock frequency and Flash settings
00032       (+) Configure the AHB and APB buses prescalers
00033       (+) Enable the clock for the peripheral(s) to be used
00034       (+) Configure the clock source(s) for peripherals which clocks are not
00035           derived from the System clock (RTC, ADC, RNG, HSTIM)
00036
00037   @endverbatim
00038   ******************************************************************************
00039   * @attention
00040   *
00041   * Copyright (c) 2018 STMicroelectronics.
00042   * All rights reserved.
00043   *
00044   * This software is licensed under terms that can be found in the LICENSE file in
00045   * the root directory of this software component.
00046   * If no LICENSE file comes with this software, it is provided AS-IS.
00047   ******************************************************************************
00048   */
00049
00050 /* Includes ------------------------------------------------------------------*/
00051 #include "stm32g0xx_hal.h"
00052
00053 /** @addtogroup STM32G0xx_HAL_Driver
00054   * @{
00055   */
00056
00057 /** @defgroup RCC RCC
00058   * @brief RCC HAL module driver
00059   * @{
00060   */
00061
00062 #ifdef HAL_RCC_MODULE_ENABLED
00063
00064 /* Private typedef -----------------------------------------------------------*/
00065 /* Private define ------------------------------------------------------------*/
00066 /** @defgroup RCC_Private_Constants RCC Private Constants
00067   * @{
00068   */
00069 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
00070 #define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms (minimum Tick + 1) */
00071 #define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms (minimum Tick + 1) */
00072 #define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms (minimum Tick + 1) */
00073
00074 #if defined(RCC_HSI48_SUPPORT)
00075 #define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms (minimum Tick + 1) */
00076 #endif /* RCC_HSI48_SUPPORT */
00077 #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s    */
00078
00079 #define PLLSOURCE_NONE             (0U)
00080 /**
00081   * @}
00082   */
00083
00084 /* Private macro -------------------------------------------------------------*/
00085 /** @defgroup RCC_Private_Macros RCC Private Macros
00086   * @{
00087   */
00088 #define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
00089 #define MCO1_GPIO_PORT        GPIOA
00090 #define MCO1_PIN              GPIO_PIN_8
00091
00092 #if defined(RCC_MCO2_SUPPORT)
00093 #define MCO2_CLK_ENABLE()    __HAL_RCC_GPIOA_CLK_ENABLE()
00094 #define MCO2_GPIO_PORT        GPIOA
00095 #define MCO2_PIN              GPIO_PIN_10
00096 #endif /* RCC_MCO2_SUPPORT */
00097
00098 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
00099   (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
00100 /**
00101   * @}
00102   */
00103
00104 /* Private variables ---------------------------------------------------------*/
00105 /** @defgroup RCC_Private_Variables RCC Private Variables
00106   * @{
00107   */
00108
00109 /**
00110   * @}
00111   */
00112
00113 /* Private function prototypes -----------------------------------------------*/
00114 /* Exported functions --------------------------------------------------------*/
00115
00116 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00117   * @{
00118   */
00119
00120 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00121   *  @brief    Initialization and Configuration functions
00122   *
00123   @verbatim
00124  ===============================================================================
00125            ##### Initialization and de-initialization functions #####
00126  ===============================================================================
00127     [..]
00128       This section provides functions allowing to configure the internal and external oscillators
00129       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB)
00130
00131     [..] Internal/external clock and PLL configuration
00132          (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
00133              the PLL as System clock source.
00134
00135          (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
00136              clock source.
00137
00138          (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
00139              through the PLL as System clock source. Can be used also optionally as RTC clock source.
00140
00141          (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
00142
00143          (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks:
00144            (++) The first output (R) is used to generate the high speed system clock (up to 64MHz).
00145            (++) The second output(Q) is used to generate the clock for the random analog generator and HStim.
00146            (++) The Third output (P) is used to generate the clock for the Analog to Digital Converter and I2S.
00147
00148          (+) CSS (Clock security system): once enabled, if a HSE or LSE clock failure occurs
00149             (HSE used directly or through PLL as System clock source), the System clock
00150              is automatically switched respectively to HSI or LSI and an interrupt is generated
00151              if enabled. The interrupt is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt)
00152              exception vector.
00153
00154          (+) MCOx (microcontroller clock output):
00155              (++) MCO1 used to output LSI, HSI48(*), HSI, LSE, HSE or main PLL clock (through a configurable prescaler) on PA8 pin.
00156              (++) MCO2(*) used to output LSI, HSI48(*), HSI, LSE, HSE, main PLLR clock, PLLQ clock, PLLP clock, RTC clock or RTC_Wakeup (through a configurable prescaler) on PA10 pin.
00157                  (*) available on certain devices only
00158
00159     [..] System, AHB and APB buses clocks configuration
00160          (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
00161              HSE, LSI, LSE and main PLL.
00162              The AHB clock (HCLK) is derived from System clock through configurable
00163              prescaler and used to clock the CPU, memory and peripherals mapped
00164              on AHB bus (DMA, GPIO...).and APB (PCLK1) clock is derived
00165              from AHB clock through configurable prescalers and used to clock
00166              the peripherals mapped on these buses. You can use
00167              "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00168
00169          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
00170
00171             (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
00172                 divided by 2 to 31.
00173                 You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
00174                  to configure this clock.
00175
00176             (+@) RNG(*) requires a frequency equal or lower than 48 MHz.
00177                  This clock is derived from the main PLL or HSI or System clock.
00178                  (*) available on certain devices only
00179
00180             (+@) IWDG clock which is always the LSI clock.
00181
00182
00183          (+) The maximum frequency of the SYSCLK, HCLK, PCLK is 64 MHz.
00184              Depending on the device voltage range, the maximum frequency should be
00185              adapted accordingly.
00186
00187   @endverbatim
00188
00189      (++)  Table 1. HCLK clock frequency.
00190      (++)  +-------------------------------------------------------+
00191      (++)  | Latency         |    HCLK clock frequency (MHz)       |
00192      (++)  |                 |-------------------------------------|
00193      (++)  |                 | voltage range 1  | voltage range 2  |
00194      (++)  |                 |      1.2 V       |     1.0 V        |
00195      (++)  |-----------------|------------------|------------------|
00196      (++)  |0WS(1 CPU cycles)|  HCLK <= 24      |  HCLK <= 8       |
00197      (++)  |-----------------|------------------|------------------|
00198      (++)  |1WS(2 CPU cycles)|  HCLK <= 48      |  HCLK <= 16      |
00199      (++)  |-----------------|------------------|------------------|
00200      (++)  |2WS(3 CPU cycles)|  HCLK <= 64      |           -      |
00201      (++)  |-----------------|------------------|------------------|
00202    * @{
00203   */
00204
00205 /**
00206   * @brief  Reset the RCC clock configuration to the default reset state.
00207   * @note   The default reset state of the clock configuration is given below:
00208   *            - HSI ON and used as system clock source
00209   *            - HSE, PLL OFF
00210   *            - AHB and APB prescaler set to 1.
00211   *            - CSS, MCO1 OFF
00212   *            - All interrupts disabled
00213   * @note   This function does not modify the configuration of the
00214   *            - Peripheral clocks
00215   *            - LSI, LSE and RTC clocks
00216   * @retval HAL status
00217   */
00218 HAL_StatusTypeDef HAL_RCC_DeInit(void)
00219 {
00220   uint32_t tickstart;
00221
00222   /* Get Start Tick*/
00223   tickstart = HAL_GetTick();
00224
00225   /* Set HSION bit to the reset value */
00226   SET_BIT(RCC->CR, RCC_CR_HSION);
00227
00228   /* Wait till HSI is ready */
00229   while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
00230   {
00231     if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00232     {
00233       return HAL_TIMEOUT;
00234     }
00235   }
00236
00237   /* Set HSITRIM[6:0] bits to the reset value */
00238   RCC->ICSCR = RCC_ICSCR_HSITRIM_6;
00239
00240   /* Get Start Tick*/
00241   tickstart = HAL_GetTick();
00242
00243   /* Reset CFGR register (HSI is selected as system clock source) */
00244   RCC->CFGR = 0x00000000u;
00245
00246   /* Wait till HSI is ready */
00247   while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
00248   {
00249     if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00250     {
00251       return HAL_TIMEOUT;
00252     }
00253   }
00254
00255   /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */
00256   RCC->CR = RCC_CR_HSION;
00257
00258   /* Then again to HSEBYP in case bypass was enabled */
00259   RCC->CR = RCC_CR_HSION;
00260
00261   /* Get Start Tick*/
00262   tickstart = HAL_GetTick();
00263
00264   /* Wait till PLL is ready */
00265   while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
00266   {
00267     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00268     {
00269       return HAL_TIMEOUT;
00270     }
00271   }
00272
00273   /* once PLL is OFF, reset PLLCFGR register to default value */
00274   RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4;
00275
00276   /* Disable all interrupts */
00277   RCC->CIER = 0x00000000u;
00278
00279   /* Clear all flags */
00280   RCC->CICR = 0xFFFFFFFFu;
00281
00282   /* Update the SystemCoreClock global variable */
00283   SystemCoreClock = HSI_VALUE;
00284
00285   /* Adapt Systick interrupt period */
00286   if (HAL_InitTick(uwTickPrio) != HAL_OK)
00287   {
00288     return HAL_ERROR;
00289   }
00290   else
00291   {
00292     return HAL_OK;
00293   }
00294 }
00295
00296 /**
00297   * @brief  Initialize the RCC Oscillators according to the specified parameters in the
00298   *         @ref RCC_OscInitTypeDef.
00299   * @param  RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that
00300   *         contains the configuration information for the RCC Oscillators.
00301   * @note   The PLL is not disabled when used as system clock.
00302   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00303   *         supported by this function. User should request a transition to HSE Off
00304   *         first and then to HSE On or HSE Bypass.
00305   * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not
00306   *         supported by this function. User should request a transition to LSE Off
00307   *         first and then to LSE On or LSE Bypass.
00308   * @retval HAL status
00309   */
00310 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00311 {
00312   uint32_t tickstart;
00313   uint32_t temp_sysclksrc;
00314   uint32_t temp_pllckcfg;
00315
00316   /* Check Null pointer */
00317   if (RCC_OscInitStruct == NULL)
00318   {
00319     return HAL_ERROR;
00320   }
00321
00322   /* Check the parameters */
00323   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00324
00325   /*------------------------------- HSE Configuration ------------------------*/
00326   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00327   {
00328     /* Check the parameters */
00329     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00330
00331     temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00332     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
00333
00334     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
00335     if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
00336         || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
00337     {
00338       if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00339       {
00340         return HAL_ERROR;
00341       }
00342     }
00343     else
00344     {
00345       /* Set the new HSE configuration ---------------------------------------*/
00346       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00347
00348       /* Check the HSE State */
00349       if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00350       {
00351         /* Get Start Tick*/
00352         tickstart = HAL_GetTick();
00353
00354         /* Wait till HSE is ready */
00355         while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
00356         {
00357           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00358           {
00359             return HAL_TIMEOUT;
00360           }
00361         }
00362       }
00363       else
00364       {
00365         /* Get Start Tick*/
00366         tickstart = HAL_GetTick();
00367
00368         /* Wait till HSE is disabled */
00369         while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
00370         {
00371           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00372           {
00373             return HAL_TIMEOUT;
00374           }
00375         }
00376       }
00377     }
00378   }
00379   /*----------------------------- HSI Configuration --------------------------*/
00380   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00381   {
00382     /* Check the parameters */
00383     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00384     assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00385     assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
00386
00387     /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
00388     temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00389     temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
00390     if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
00391         || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
00392     {
00393       /* When HSI is used as system clock or as PLL input clock it can not be disabled */
00394       if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
00395       {
00396         return HAL_ERROR;
00397       }
00398       /* Otherwise, just the calibration is allowed */
00399       else
00400       {
00401         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00402         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00403
00404         if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
00405         {
00406           /* Adjust the HSI16 division factor */
00407           __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
00408
00409           /* Update the SystemCoreClock global variable with HSISYS value  */
00410           SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
00411         }
00412
00413         /* Adapt Systick interrupt period */
00414         if (HAL_InitTick(uwTickPrio) != HAL_OK)
00415         {
00416           return HAL_ERROR;
00417         }
00418       }
00419     }
00420     else
00421     {
00422       /* Check the HSI State */
00423       if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
00424       {
00425         /* Configure the HSI16 division factor */
00426         __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
00427
00428         /* Enable the Internal High Speed oscillator (HSI16). */
00429         __HAL_RCC_HSI_ENABLE();
00430
00431         /* Get Start Tick*/
00432         tickstart = HAL_GetTick();
00433
00434         /* Wait till HSI is ready */
00435         while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
00436         {
00437           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00438           {
00439             return HAL_TIMEOUT;
00440           }
00441         }
00442
00443         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00444         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00445       }
00446       else
00447       {
00448         /* Disable the Internal High Speed oscillator (HSI16). */
00449         __HAL_RCC_HSI_DISABLE();
00450
00451         /* Get Start Tick*/
00452         tickstart = HAL_GetTick();
00453
00454         /* Wait till HSI is disabled */
00455         while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
00456         {
00457           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00458           {
00459             return HAL_TIMEOUT;
00460           }
00461         }
00462       }
00463     }
00464   }
00465   /*------------------------------ LSI Configuration -------------------------*/
00466   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00467   {
00468     /* Check the parameters */
00469     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00470
00471     /* Check if LSI is used as system clock */
00472     if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
00473     {
00474       /* When LSI is used as system clock it will not be disabled */
00475       if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
00476       {
00477         return HAL_ERROR;
00478       }
00479     }
00480     else
00481     {
00482       /* Check the LSI State */
00483       if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
00484       {
00485         /* Enable the Internal Low Speed oscillator (LSI). */
00486         __HAL_RCC_LSI_ENABLE();
00487
00488         /* Get Start Tick*/
00489         tickstart = HAL_GetTick();
00490
00491         /* Wait till LSI is ready */
00492         while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
00493         {
00494           if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
00495           {
00496             return HAL_TIMEOUT;
00497           }
00498         }
00499       }
00500       else
00501       {
00502         /* Disable the Internal Low Speed oscillator (LSI). */
00503         __HAL_RCC_LSI_DISABLE();
00504
00505         /* Get Start Tick*/
00506         tickstart = HAL_GetTick();
00507
00508         /* Wait till LSI is disabled */
00509         while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
00510         {
00511           if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
00512           {
00513             return HAL_TIMEOUT;
00514           }
00515         }
00516       }
00517     }
00518   }
00519   /*------------------------------ LSE Configuration -------------------------*/
00520   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00521   {
00522     FlagStatus       pwrclkchanged = RESET;
00523
00524     /* Check the parameters */
00525     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00526
00527     /* When the LSE is used as system clock, it is not allowed disable it */
00528     if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
00529     {
00530       if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
00531       {
00532         return HAL_ERROR;
00533       }
00534     }
00535     else
00536     {
00537       /* Update LSE configuration in Backup Domain control register    */
00538       /* Requires to enable write access to Backup Domain of necessary */
00539       if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
00540       {
00541         __HAL_RCC_PWR_CLK_ENABLE();
00542         pwrclkchanged = SET;
00543       }
00544
00545       if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
00546       {
00547         /* Enable write access to Backup domain */
00548         SET_BIT(PWR->CR1, PWR_CR1_DBP);
00549
00550         /* Wait for Backup domain Write protection disable */
00551         tickstart = HAL_GetTick();
00552
00553         while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
00554         {
00555           if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00556           {
00557             return HAL_TIMEOUT;
00558           }
00559         }
00560       }
00561
00562       /* Set the new LSE configuration -----------------------------------------*/
00563       __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00564
00565       /* Check the LSE State */
00566       if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
00567       {
00568         /* Get Start Tick*/
00569         tickstart = HAL_GetTick();
00570
00571         /* Wait till LSE is ready */
00572         while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
00573         {
00574           if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00575           {
00576             return HAL_TIMEOUT;
00577           }
00578         }
00579       }
00580       else
00581       {
00582         /* Get Start Tick*/
00583         tickstart = HAL_GetTick();
00584
00585         /* Wait till LSE is disabled */
00586         while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
00587         {
00588           if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00589           {
00590             return HAL_TIMEOUT;
00591           }
00592         }
00593       }
00594
00595       /* Restore clock configuration if changed */
00596       if (pwrclkchanged == SET)
00597       {
00598         __HAL_RCC_PWR_CLK_DISABLE();
00599       }
00600     }
00601   }
00602 #if defined(RCC_HSI48_SUPPORT)
00603   /*------------------------------ HSI48 Configuration -----------------------*/
00604   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
00605   {
00606     /* Check the parameters */
00607     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
00608
00609     /* Check the LSI State */
00610     if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
00611     {
00612       /* Enable the Internal Low Speed oscillator (HSI48). */
00613       __HAL_RCC_HSI48_ENABLE();
00614
00615       /* Get Start Tick*/
00616       tickstart = HAL_GetTick();
00617
00618       /* Wait till HSI48 is ready */
00619       while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U)
00620       {
00621         if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
00622         {
00623           return HAL_TIMEOUT;
00624         }
00625       }
00626     }
00627     else
00628     {
00629       /* Disable the Internal Low Speed oscillator (HSI48). */
00630       __HAL_RCC_HSI48_DISABLE();
00631
00632       /* Get Start Tick*/
00633       tickstart = HAL_GetTick();
00634
00635       /* Wait till HSI48 is disabled */
00636       while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U)
00637       {
00638         if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
00639         {
00640           return HAL_TIMEOUT;
00641         }
00642       }
00643     }
00644   }
00645 #endif /* RCC_HSI48_SUPPORT */
00646   /*-------------------------------- PLL Configuration -----------------------*/
00647   /* Check the parameters */
00648   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00649
00650   if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
00651   {
00652     /* Check if the PLL is used as system clock or not */
00653     if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00654     {
00655       if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
00656       {
00657         /* Check the parameters */
00658         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00659         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00660         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00661         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00662 #if defined(RCC_PLLQ_SUPPORT)
00663         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00664 #endif /* RCC_PLLQ_SUPPORT */
00665         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
00666
00667         /* Disable the main PLL. */
00668         __HAL_RCC_PLL_DISABLE();
00669
00670         /* Get Start Tick*/
00671         tickstart = HAL_GetTick();
00672
00673         /* Wait till PLL is ready */
00674         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
00675         {
00676           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00677           {
00678             return HAL_TIMEOUT;
00679           }
00680         }
00681
00682         /* Configure the main PLL clock source, multiplication and division factors. */
00683         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00684                              RCC_OscInitStruct->PLL.PLLM,
00685                              RCC_OscInitStruct->PLL.PLLN,
00686                              RCC_OscInitStruct->PLL.PLLP,
00687 #if defined(RCC_PLLQ_SUPPORT)
00688                              RCC_OscInitStruct->PLL.PLLQ,
00689 #endif /* RCC_PLLQ_SUPPORT */
00690                              RCC_OscInitStruct->PLL.PLLR);
00691
00692         /* Enable the main PLL. */
00693         __HAL_RCC_PLL_ENABLE();
00694
00695         /* Enable PLLR Clock output. */
00696         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
00697
00698         /* Get Start Tick*/
00699         tickstart = HAL_GetTick();
00700
00701         /* Wait till PLL is ready */
00702         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
00703         {
00704           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00705           {
00706             return HAL_TIMEOUT;
00707           }
00708         }
00709       }
00710       else
00711       {
00712         /* Disable the main PLL. */
00713         __HAL_RCC_PLL_DISABLE();
00714
00715         /* Get Start Tick*/
00716         tickstart = HAL_GetTick();
00717
00718         /* Wait till PLL is disabled */
00719         while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
00720         {
00721           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00722           {
00723             return HAL_TIMEOUT;
00724           }
00725         }
00726         /* Unselect main PLL clock source and disable main PLL outputs to save power */
00727 #if defined(RCC_PLLQ_SUPPORT)
00728         RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
00729 #else
00730         RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN);
00731 #endif /* RCC_PLLQ_SUPPORT */
00732       }
00733     }
00734     else
00735     {
00736       /* Check if there is a request to disable the PLL used as System clock source */
00737       if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
00738       {
00739         return HAL_ERROR;
00740       }
00741       else
00742       {
00743         /* Do not return HAL_ERROR if request repeats the current configuration */
00744         temp_pllckcfg = RCC->PLLCFGR;
00745         if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
00746             (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
00747             (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
00748             (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
00749 #if defined (RCC_PLLQ_SUPPORT)
00750             (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
00751 #endif /* RCC_PLLQ_SUPPORT */
00752             (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
00753         {
00754           return HAL_ERROR;
00755         }
00756       }
00757     }
00758   }
00759   return HAL_OK;
00760 }
00761
00762 /**
00763   * @brief  Initialize the CPU, AHB and APB buses clocks according to the specified
00764   *         parameters in the RCC_ClkInitStruct.
00765   * @param  RCC_ClkInitStruct  pointer to a @ref RCC_ClkInitTypeDef structure that
00766   *         contains the configuration information for the RCC peripheral.
00767   * @param  FLatency  FLASH Latency
00768   *          This parameter can be one of the following values:
00769   *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle
00770   *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle
00771   *
00772   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00773   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
00774   *
00775   * @note   The HSI is used by default as system clock source after
00776   *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,
00777   *         the HSI frequency is set to 8 Mhz, then it reaches its default value 16 MHz.
00778   *
00779   * @note   The HSI can be selected as system clock source after
00780   *         from STOP modes or in case of failure of the HSE used directly or indirectly
00781   *         as system clock (if the Clock Security System CSS is enabled).
00782   *
00783   * @note   The LSI can be selected as system clock source after
00784   *         in case of failure of the LSE used directly or indirectly
00785   *         as system clock (if the Clock Security System LSECSS is enabled).
00786   *
00787   * @note   A switch from one clock source to another occurs only if the target
00788   *         clock source is ready (clock stable after startup delay or PLL locked).
00789   *         If a clock source which is not yet ready is selected, the switch will
00790   *         occur when the clock source is ready.
00791   *
00792   * @note   You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
00793   *         currently used as system clock source.
00794   *
00795   * @note   Depending on the device voltage range, the software has to set correctly
00796   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
00797   *         (for more details refer to section above "Initialization/de-initialization functions")
00798   * @retval None
00799   */
00800 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00801 {
00802   uint32_t tickstart;
00803
00804   /* Check Null pointer */
00805   if (RCC_ClkInitStruct == NULL)
00806   {
00807     return HAL_ERROR;
00808   }
00809
00810   /* Check the parameters */
00811   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00812   assert_param(IS_FLASH_LATENCY(FLatency));
00813
00814   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00815     must be correctly programmed according to the frequency of the FLASH clock
00816     (HCLK) and the supply voltage of the device. */
00817
00818   /* Increasing the number of wait states because of higher CPU frequency */
00819   if (FLatency > __HAL_FLASH_GET_LATENCY())
00820   {
00821     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00822     __HAL_FLASH_SET_LATENCY(FLatency);
00823
00824     /* Check that the new number of wait states is taken into account to access the Flash
00825     memory by polling the FLASH_ACR register */
00826     tickstart = HAL_GetTick();
00827
00828     while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00829     {
00830       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00831       {
00832         return HAL_TIMEOUT;
00833       }
00834     }
00835   }
00836
00837   /*-------------------------- HCLK Configuration --------------------------*/
00838   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00839   {
00840     /* Set the highest APB divider in order to ensure that we do not go through
00841        a non-spec phase whatever we decrease or increase HCLK. */
00842     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00843     {
00844       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
00845     }
00846
00847     /* Set the new HCLK clock divider */
00848     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00849     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00850   }
00851
00852   /*------------------------- SYSCLK Configuration ---------------------------*/
00853   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00854   {
00855     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00856
00857     /* HSE is selected as System Clock Source */
00858     if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00859     {
00860       /* Check the HSE ready flag */
00861       if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
00862       {
00863         return HAL_ERROR;
00864       }
00865     }
00866     /* PLL is selected as System Clock Source */
00867     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00868     {
00869       /* Check the PLL ready flag */
00870       if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
00871       {
00872         return HAL_ERROR;
00873       }
00874     }
00875     /* HSI is selected as System Clock Source */
00876     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
00877     {
00878       /* Check the HSI ready flag */
00879       if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
00880       {
00881         return HAL_ERROR;
00882       }
00883     }
00884     /* LSI is selected as System Clock Source */
00885     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
00886     {
00887       /* Check the LSI ready flag */
00888       if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
00889       {
00890         return HAL_ERROR;
00891       }
00892     }
00893     /* LSE is selected as System Clock Source */
00894     else
00895     {
00896       /* Check the LSE ready flag */
00897       if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
00898       {
00899         return HAL_ERROR;
00900       }
00901     }
00902     MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
00903
00904     /* Get Start Tick*/
00905     tickstart = HAL_GetTick();
00906
00907     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
00908     {
00909       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00910       {
00911         return HAL_TIMEOUT;
00912       }
00913     }
00914   }
00915
00916   /* Decreasing the number of wait states because of lower CPU frequency */
00917   if (FLatency < __HAL_FLASH_GET_LATENCY())
00918   {
00919     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00920     __HAL_FLASH_SET_LATENCY(FLatency);
00921
00922     /* Check that the new number of wait states is taken into account to access the Flash
00923     memory by polling the FLASH_ACR register */
00924     tickstart = HAL_GetTick();
00925
00926     while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00927     {
00928       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00929       {
00930         return HAL_TIMEOUT;
00931       }
00932     }
00933   }
00934
00935   /*-------------------------- PCLK1 Configuration ---------------------------*/
00936   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00937   {
00938     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
00939     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
00940   }
00941
00942   /* Update the SystemCoreClock global variable */
00943   SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
00944
00945   /* Configure the source of time base considering new system clocks settings*/
00946   return HAL_InitTick(uwTickPrio);
00947 }
00948
00949 /**
00950   * @}
00951   */
00952
00953 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
00954   *  @brief   RCC clocks control functions
00955   *
00956 @verbatim
00957  ===============================================================================
00958                       ##### Peripheral Control functions #####
00959  ===============================================================================
00960     [..]
00961     This subsection provides a set of functions allowing to:
00962
00963     (+) Output clock to MCO pin.
00964     (+) Retrieve current clock frequencies.
00965     (+) Enable the Clock Security System.
00966
00967 @endverbatim
00968   * @{
00969   */
00970
00971 /**
00972   * @brief  Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PA10)(*).
00973   * @note   PA8, PA10(*) should be configured in alternate function mode.
00974   * @param  RCC_MCOx  specifies the output direction for the clock source.
00975   *          For STM32G0xx family this parameter can have only one value:
00976   *            @arg @ref RCC_MCO1  Clock source to output on MCO1 pin(PA8).
00977   *            @arg @ref RCC_MCO2  Clock source to output on MCO2 pin(PA10)(*).
00978   * @param  RCC_MCOSource  specifies the clock source to output.
00979   *          This parameter can be one of the following values:
00980   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO
00981   *            @arg @ref RCC_MCO1SOURCE_SYSCLK   system  clock selected as MCO source
00982   *            @arg @ref RCC_MCO1SOURCE_HSI48    HSI48 clock selected as MCO source for devices with HSI48(*)
00983   *            @arg @ref RCC_MCO1SOURCE_HSI      HSI clock selected as MCO source
00984   *            @arg @ref RCC_MCO1SOURCE_HSE      HSE clock selected as MCO sourcee
00985   *            @arg @ref RCC_MCO1SOURCE_PLLCLK   main PLLR clock selected as MCO source
00986   *            @arg @ref RCC_MCO1SOURCE_LSI      LSI clock selected as MCO source
00987   *            @arg @ref RCC_MCO1SOURCE_LSE      LSE clock selected as MCO source
00988   *            @arg @ref RCC_MCO1SOURCE_PLLPCLK  PLLP clock selected as MCO1 source(*)
00989   *            @arg @ref RCC_MCO1SOURCE_PLLQCLK  PLLQ clock selected as MCO1 source(*)
00990   *            @arg @ref RCC_MCO1SOURCE_RTCCLK   RTC clock selected as MCO1 source(*)
00991   *            @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*)
00992   *            @arg @ref RCC_MCO2SOURCE_NOCLOCK  MCO2 output disabled, no clock on MCO2(*)
00993   *            @arg @ref RCC_MCO2SOURCE_SYSCLK   system  clock selected as MCO2 source(*)
00994   *            @arg @ref RCC_MCO2SOURCE_HSI48    HSI48 clock selected as MCO2 source for devices with HSI48(*)
00995   *            @arg @ref RCC_MCO2SOURCE_HSI      HSI clock selected as MCO2 source(*)
00996   *            @arg @ref RCC_MCO2SOURCE_HSE      HSE clock selected as MCO2 source(*)
00997   *            @arg @ref RCC_MCO2SOURCE_PLLCLK   main PLLR clock selected as MCO2 source(*)
00998   *            @arg @ref RCC_MCO2SOURCE_LSI      LSI clock selected as MCO2 source(*)
00999   *            @arg @ref RCC_MCO2SOURCE_LSE      LSE clock selected as MCO2 source(*)
01000   *            @arg @ref RCC_MCO2SOURCE_PLLPCLK  PLLP clock selected as MCO2 source(*)
01001   *            @arg @ref RCC_MCO2SOURCE_PLLQCLK  PLLQ clock selected as MCO2 source(*)
01002   *            @arg @ref RCC_MCO2SOURCE_RTCCLK   RTC clock selected as MCO2 source(*)
01003   *            @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_Wakeup selected as MCO2 source(*)
01004   * @param  RCC_MCODiv  specifies the MCO prescaler.
01005   *          This parameter can be one of the following values:
01006   *            @arg @ref RCC_MCODIV_1     no division applied to MCO clock
01007   *            @arg @ref RCC_MCODIV_2     division by 2 applied to MCO clock
01008   *            @arg @ref RCC_MCODIV_4     division by 4 applied to MCO clock
01009   *            @arg @ref RCC_MCODIV_8     division by 8 applied to MCO clock
01010   *            @arg @ref RCC_MCODIV_16    division by 16 applied to MCO clock
01011   *            @arg @ref RCC_MCODIV_32    division by 32 applied to MCO clock
01012   *            @arg @ref RCC_MCODIV_64    division by 64 applied to MCO clock
01013   *            @arg @ref RCC_MCODIV_128   division by 128 applied to MCO clock
01014   *            @arg @ref RCC_MCO2DIV_1    no division applied to MCO2 clock(*)
01015   *            @arg @ref RCC_MCO2DIV_2    division by 2 applied to MCO2 clock(*)
01016   *            @arg @ref RCC_MCO2DIV_4    division by 4 applied to MCO2 clock(*)
01017   *            @arg @ref RCC_MCO2DIV_8    division by 8 applied to MCO2 clock(*)
01018   *            @arg @ref RCC_MCO2DIV_16   division by 16 applied to MCO2 clock(*)
01019   *            @arg @ref RCC_MCO2DIV_32   division by 32 applied to MCO2 clock(*)
01020   *            @arg @ref RCC_MCO2DIV_64   division by 64 applied to MCO2 clock(*)
01021   *            @arg @ref RCC_MCO2DIV_128  division by 128 applied to MCO2 clock(*)
01022   *            @arg @ref RCC_MCO2DIV_256  division by 256 applied to MCO2 clock(*)
01023   *            @arg @ref RCC_MCO2DIV_512  division by 512 applied to MCO2 clock(*)
01024   *            @arg @ref RCC_MCO2DIV_1024 division by 1024 applied to MCO2 clock(*)
01025   *
01026   * (*) Feature not available on all devices of the family
01027   * @retval None
01028   */
01029 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
01030 {
01031   GPIO_InitTypeDef GPIO_InitStruct;
01032
01033   /* Check the parameters */
01034   assert_param(IS_RCC_MCO(RCC_MCOx));
01035
01036   /* Common GPIO init parameters */
01037   GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
01038   GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
01039   GPIO_InitStruct.Pull      = GPIO_NOPULL;
01040
01041   if (RCC_MCOx == RCC_MCO1)
01042   {
01043     assert_param(IS_RCC_MCODIV(RCC_MCODiv));
01044     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
01045     /* MCO1 Clock Enable */
01046     MCO1_CLK_ENABLE();
01047     /* Configure the MCO1 pin in alternate function mode */
01048     GPIO_InitStruct.Pin = MCO1_PIN;
01049     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
01050     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
01051     /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
01052     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
01053   }
01054 #if defined(RCC_MCO2_SUPPORT)
01055   else if (RCC_MCOx == RCC_MCO2)
01056   {
01057     assert_param(IS_RCC_MCO2DIV(RCC_MCODiv));
01058     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
01059     /* MCO2 Clock Enable */
01060     MCO2_CLK_ENABLE();
01061     /* Configure the MCO2 pin in alternate function mode */
01062     GPIO_InitStruct.Pin       = MCO2_PIN;
01063     GPIO_InitStruct.Alternate = GPIO_AF3_MCO2;
01064     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
01065     /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
01066     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), (RCC_MCOSource | RCC_MCODiv));
01067   }
01068 #endif /* RCC_MCO2_SUPPORT */
01069 }
01070
01071 /**
01072   * @brief  Return the SYSCLK frequency.
01073   *
01074   * @note   The system frequency computed by this function is not the real
01075   *         frequency in the chip. It is calculated based on the predefined
01076   *         constant and the selected clock source:
01077   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE/HSIDIV(*)
01078   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
01079   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
01080   *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
01081   * @note     If SYSCLK source is LSI, function returns values based on LSI_VALUE(***)
01082   * @note     If SYSCLK source is LSE, function returns values based on LSE_VALUE(****)
01083   * @note     (*) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
01084   *               16 MHz) but the real value may vary depending on the variations
01085   *               in voltage and temperature.
01086   * @note     (**) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
01087   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
01088   *                frequency of the crystal used. Otherwise, this function may
01089   *                have wrong result.
01090   * @note     (***) LSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
01091   *               32768 Hz).
01092   * @note     (****) LSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
01093   *               32000 Hz).
01094   *
01095   * @note   The result of this function could be not correct when using fractional
01096   *         value for HSE crystal.
01097   *
01098   * @note   This function can be used by the user application to compute the
01099   *         baudrate for the communication peripherals or configure other parameters.
01100   *
01101   * @note   Each time SYSCLK changes, this function must be called to update the
01102   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
01103   *
01104   *
01105   * @retval SYSCLK frequency
01106   */
01107 uint32_t HAL_RCC_GetSysClockFreq(void)
01108 {
01109   uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
01110   uint32_t sysclockfreq;
01111
01112   if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
01113   {
01114     /* HSISYS can be derived for HSI16 */
01115     hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
01116
01117     /* HSI used as system clock source */
01118     sysclockfreq = (HSI_VALUE / hsidiv);
01119   }
01120   else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
01121   {
01122     /* HSE used as system clock source */
01123     sysclockfreq = HSE_VALUE;
01124   }
01125   else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
01126   {
01127     /* PLL used as system clock  source */
01128
01129     /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
01130     SYSCLK = PLL_VCO / PLLR
01131     */
01132     pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
01133     pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
01134
01135     switch (pllsource)
01136     {
01137       case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01138         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
01139         break;
01140
01141       case RCC_PLLSOURCE_HSI:  /* HSI16 used as PLL clock source */
01142       default:                 /* HSI16 used as PLL clock source */
01143         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
01144         break;
01145     }
01146     pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
01147     sysclockfreq = pllvco / pllr;
01148   }
01149   else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
01150   {
01151     /* LSE used as system clock source */
01152     sysclockfreq = LSE_VALUE;
01153   }
01154   else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
01155   {
01156     /* LSI used as system clock source */
01157     sysclockfreq = LSI_VALUE;
01158   }
01159   else
01160   {
01161     sysclockfreq = 0U;
01162   }
01163
01164   return sysclockfreq;
01165 }
01166
01167 /**
01168   * @brief  Return the HCLK frequency.
01169   * @note   Each time HCLK changes, this function must be called to update the
01170   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
01171   *
01172   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
01173   * @retval HCLK frequency in Hz
01174   */
01175 uint32_t HAL_RCC_GetHCLKFreq(void)
01176 {
01177   return SystemCoreClock;
01178 }
01179
01180 /**
01181   * @brief  Return the PCLK1 frequency.
01182   * @note   Each time PCLK1 changes, this function must be called to update the
01183   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
01184   * @retval PCLK1 frequency in Hz
01185   */
01186 uint32_t HAL_RCC_GetPCLK1Freq(void)
01187 {
01188   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01189   return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
01190 }
01191
01192 /**
01193   * @brief  Configure the RCC_OscInitStruct according to the internal
01194   *         RCC configuration registers.
01195   * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
01196   *         will be configured.
01197   * @retval None
01198   */
01199 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01200 {
01201   /* Check the parameters */
01202   assert_param(RCC_OscInitStruct != (void *)NULL);
01203
01204   /* Set all possible values for the Oscillator type parameter ---------------*/
01205 #if defined(RCC_HSI48_SUPPORT)
01206   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \
01207                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
01208 #else
01209   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \
01210                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
01211 #endif /* RCC_HSI48_SUPPORT */
01212
01213   /* Get the HSE configuration -----------------------------------------------*/
01214   if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01215   {
01216     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01217   }
01218   else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
01219   {
01220     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01221   }
01222   else
01223   {
01224     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01225   }
01226
01227   /* Get the HSI configuration -----------------------------------------------*/
01228   if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
01229   {
01230     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01231   }
01232   else
01233   {
01234     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01235   }
01236   RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
01237   RCC_OscInitStruct->HSIDiv = (RCC->CR & RCC_CR_HSIDIV);
01238
01239   /* Get the LSE configuration -----------------------------------------------*/
01240   if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01241   {
01242     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01243   }
01244   else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01245   {
01246     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01247   }
01248   else
01249   {
01250     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01251   }
01252
01253   /* Get the LSI configuration -----------------------------------------------*/
01254   if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
01255   {
01256     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01257   }
01258   else
01259   {
01260     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01261   }
01262
01263 #if defined(RCC_HSI48_SUPPORT)
01264   /* Get the HSI48 configuration ---------------------------------------------*/
01265   if (READ_BIT(RCC->CR, RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
01266   {
01267     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
01268   }
01269   else
01270   {
01271     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
01272   }
01273 #endif /* RCC_HSI48_SUPPORT */
01274
01275   /* Get the PLL configuration -----------------------------------------------*/
01276   if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
01277   {
01278     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01279   }
01280   else
01281   {
01282     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01283   }
01284   RCC_OscInitStruct->PLL.PLLSource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
01285   RCC_OscInitStruct->PLL.PLLM = (RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
01286   RCC_OscInitStruct->PLL.PLLN = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
01287   RCC_OscInitStruct->PLL.PLLP = (RCC->PLLCFGR & RCC_PLLCFGR_PLLP);
01288 #if defined(RCC_PLLQ_SUPPORT)
01289   RCC_OscInitStruct->PLL.PLLQ = (RCC->PLLCFGR & RCC_PLLCFGR_PLLQ);
01290 #endif /* RCC_PLLQ_SUPPORT */
01291   RCC_OscInitStruct->PLL.PLLR = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR);
01292 }
01293
01294 /**
01295   * @brief  Configure the RCC_ClkInitStruct according to the internal
01296   *         RCC configuration registers.
01297   * @param  RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that
01298   *                           will be configured.
01299   * @param  pFLatency         Pointer on the Flash Latency.
01300   * @retval None
01301   */
01302 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01303 {
01304   /* Check the parameters */
01305   assert_param(RCC_ClkInitStruct != (void *)NULL);
01306   assert_param(pFLatency != (void *)NULL);
01307
01308   /* Set all possible values for the Clock type parameter --------------------*/
01309   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
01310
01311   /* Get the SYSCLK configuration --------------------------------------------*/
01312   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01313
01314   /* Get the HCLK configuration ----------------------------------------------*/
01315   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
01316
01317   /* Get the APB1 configuration ----------------------------------------------*/
01318   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
01319
01320
01321   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01322   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01323 }
01324
01325 /**
01326   * @brief  Enable the Clock Security System.
01327   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
01328   *         is automatically disabled and an interrupt is generated to inform the
01329   *         software about the failure (Clock Security System Interrupt, CSSI),
01330   *         allowing the MCU to perform rescue operations. The CSSI is linked to
01331   *         the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
01332   * @note   The Clock Security System can only be cleared by reset.
01333   * @retval None
01334   */
01335 void HAL_RCC_EnableCSS(void)
01336 {
01337   SET_BIT(RCC->CR, RCC_CR_CSSON) ;
01338 }
01339
01340 /**
01341   * @brief  Enable the LSE Clock Security System.
01342   * @note   If a failure is detected on the LSE oscillator clock, this oscillator
01343   *         is automatically disabled and an interrupt is generated to inform the
01344   *         software about the failure (Clock Security System Interrupt, CSSI),
01345   *         allowing the MCU to perform rescue operations. The CSSI is linked to
01346   *         the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
01347   * @note   The LSE Clock Security System Detection bit (LSECSSD in BDCR) can only be
01348   *         cleared by a backup domain reset.
01349   * @retval None
01350   */
01351 void HAL_RCC_EnableLSECSS(void)
01352 {
01353   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01354 }
01355
01356 /**
01357   * @brief  Disable the LSE Clock Security System.
01358   * @note   After LSE failure detection, the software must disable LSECSSON
01359   * @note   The Clock Security System can only be cleared by reset otherwise.
01360   * @retval None
01361   */
01362 void HAL_RCC_DisableLSECSS(void)
01363 {
01364   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01365 }
01366
01367 /**
01368   * @brief Handle the RCC Clock Security System interrupt request.
01369   * @note  This API should be called under the NMI_Handler().
01370   * @retval None
01371   */
01372 void HAL_RCC_NMI_IRQHandler(void)
01373 {
01374   uint32_t itflag = RCC->CIFR;
01375
01376   /* Clear interrupt flags related to CSS */
01377   RCC->CICR = (itflag & (RCC_CIFR_CSSF | RCC_CIFR_LSECSSF));
01378
01379   /* Check RCC CSSF interrupt flag  */
01380   if ((itflag & RCC_CIFR_CSSF) != 0x00u)
01381   {
01382     /* RCC Clock Security System interrupt user callback */
01383     HAL_RCC_CSSCallback();
01384   }
01385
01386   /* Check RCC LSECSSF interrupt flag  */
01387   if ((itflag & RCC_CIFR_LSECSSF) != 0x00u)
01388   {
01389     /* RCC Clock Security System interrupt user callback */
01390     HAL_RCC_LSECSSCallback();
01391   }
01392 }
01393
01394 /**
01395   * @brief Handle the RCC HSE Clock Security System interrupt callback.
01396   * @retval none
01397   */
01398 __weak void HAL_RCC_CSSCallback(void)
01399 {
01400   /* NOTE : This function should not be modified, when the callback is needed,
01401             the @ref HAL_RCC_CSSCallback should be implemented in the user file
01402    */
01403 }
01404
01405 /**
01406   * @brief  RCC LSE Clock Security System interrupt callback.
01407   * @retval none
01408   */
01409 __weak void HAL_RCC_LSECSSCallback(void)
01410 {
01411   /* NOTE : This function should not be modified, when the callback is needed,
01412             the HAL_RCC_LSECSSCallback should be implemented in the user file
01413    */
01414 }
01415
01416 /**
01417   * @brief  Get and clear reset flags
01418   * @note   Once reset flags are retrieved, this API is clearing them in order
01419   *         to isolate next reset reason.
01420   * @retval can be a combination of @ref RCC_Reset_Flag
01421   */
01422 uint32_t HAL_RCC_GetResetSource(void)
01423 {
01424   uint32_t reset;
01425
01426   /* Get all reset flags */
01427   reset = RCC->CSR & RCC_RESET_FLAG_ALL;
01428
01429   /* Clear Reset flags */
01430   RCC->CSR |= RCC_CSR_RMVF;
01431
01432   return reset;
01433 }
01434
01435 /**
01436   * @}
01437   */
01438
01439 /**
01440   * @}
01441   */
01442
01443 #endif /* HAL_RCC_MODULE_ENABLED */
01444 /**
01445   * @}
01446   */
01447
01448 /**
01449   * @}
01450   */
01451
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STM32G0C1xx HAL User Manual: stm32g0xx_hal_rcc.h Source File

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stm32g0xx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rcc.h
00004   * @author  MCD Application Team
00005    * @brief   Header file of RCC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G0xx_HAL_RCC_H
00020 #define STM32G0xx_HAL_RCC_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g0xx_hal_def.h"
00028 #include "stm32g0xx_ll_rcc.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup RCC
00035   * @{
00036   */
00037
00038 /* Private constants ---------------------------------------------------------*/
00039 /** @addtogroup RCC_Private_Constants
00040   * @{
00041   */
00042 /* Defines used for Flags */
00043 #define CR_REG_INDEX              1U
00044 #define BDCR_REG_INDEX            2U
00045 #define CSR_REG_INDEX             3U
00046 #if defined(RCC_HSI48_SUPPORT)
00047 #define CRRCR_REG_INDEX           4U
00048 #endif /* RCC_HSI48_SUPPORT */
00049
00050 #define RCC_FLAG_MASK             0x1FU
00051
00052 /* Define used for IS_RCC_CLOCKTYPE() */
00053 #define RCC_CLOCKTYPE_ALL              (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1)  /*!< All clocktype to configure */
00054 /**
00055   * @}
00056   */
00057
00058 /* Private macros ------------------------------------------------------------*/
00059 /** @addtogroup RCC_Private_Macros
00060   * @{
00061   */
00062
00063 #if defined(RCC_HSI48_SUPPORT)
00064 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)                                     \
00065   (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
00066    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)     || \
00067    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)     || \
00068    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
00069    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)     || \
00070    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
00071 #else
00072 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)                                 \
00073   (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
00074    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
00075    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
00076    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
00077    (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
00078 #endif /* RCC_HSI48_SUPPORT */
00079
00080 #define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
00081                               ((__HSE__) == RCC_HSE_BYPASS))
00082
00083 #define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
00084                               ((__LSE__) == RCC_LSE_BYPASS))
00085
00086 #define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
00087
00088 #if defined(RCC_HSI48_SUPPORT)
00089 #define IS_RCC_HSI48(__HSI48__)  (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
00090 #endif /* RCC_HSI48_SUPPORT */
00091
00092 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U)
00093
00094 #define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1)  || ((__DIV__) == RCC_HSI_DIV2) || \
00095                                 ((__DIV__) == RCC_HSI_DIV4)  || ((__DIV__) == RCC_HSI_DIV8) || \
00096                                 ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \
00097                                 ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128))
00098
00099 #define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
00100
00101 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
00102                              ((__PLL__) == RCC_PLL_ON))
00103
00104 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
00105                                       ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
00106                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
00107
00108 #define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || ((__VALUE__) == RCC_PLLM_DIV2) || \
00109                                       ((__VALUE__) == RCC_PLLM_DIV3) || ((__VALUE__) == RCC_PLLM_DIV4) || \
00110                                       ((__VALUE__) == RCC_PLLM_DIV5) || ((__VALUE__) == RCC_PLLM_DIV6) || \
00111                                       ((__VALUE__) == RCC_PLLM_DIV7) || ((__VALUE__) == RCC_PLLM_DIV8))
00112
00113 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
00114
00115 #define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
00116
00117 #if defined(RCC_PLLQ_SUPPORT)
00118 #define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
00119 #endif /* RCC_PLLQ_SUPPORT */
00120
00121 #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
00122
00123 #define IS_RCC_CLOCKTYPE(__CLK__)  ((((__CLK__)\
00124                                       & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
00125
00126 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI)  || \
00127                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE)  || \
00128                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE)  || \
00129                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI)  || \
00130                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
00131
00132 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
00133                                ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
00134                                ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
00135                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
00136                                ((__HCLK__) == RCC_SYSCLK_DIV512))
00137
00138 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
00139                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
00140                                ((__PCLK__) == RCC_HCLK_DIV16))
00141
00142 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
00143                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
00144                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
00145                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
00146
00147 #if defined(RCC_MCO2_SUPPORT)
00148 #define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) )
00149 #else
00150 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
00151 #endif /* RCC_MCO2_SUPPORT */
00152
00153 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00154 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
00155                                        ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || \
00156                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI)   || \
00157                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \
00158                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSE)   || \
00159                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
00160                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSI)    || \
00161                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSE)     || \
00162                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \
00163                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \
00164                                        ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK)  || \
00165                                        ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP))
00166 #elif defined(STM32G0B0xx)
00167 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
00168                                        ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || \
00169                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
00170                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
00171                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
00172                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
00173                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSE)     || \
00174                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \
00175                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \
00176                                        ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK)  || \
00177                                        ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP))
00178 #else
00179 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
00180                                        ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || \
00181                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
00182                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
00183                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
00184                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
00185                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
00186 #endif /* STM32G0C1xx || STM32G0B1xx */
00187
00188 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00189 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)  || ((__DIV__) == RCC_MCODIV_2)   || \
00190                                 ((__DIV__) == RCC_MCODIV_4)  || ((__DIV__) == RCC_MCODIV_8)   || \
00191                                 ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32)  || \
00192                                 ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128) || \
00193                                 ((__DIV__) == RCC_MCODIV_256)|| ((__DIV__) == RCC_MCODIV_512) || \
00194                                 ((__DIV__) == RCC_MCODIV_1024))
00195 #else
00196 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)  || ((__DIV__) == RCC_MCODIV_2)   || \
00197                                 ((__DIV__) == RCC_MCODIV_4)  || ((__DIV__) == RCC_MCODIV_8)   || \
00198                                 ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32)  || \
00199                                 ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128))
00200 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00201
00202 #if defined(RCC_MCO2_SUPPORT)
00203 #if defined(RCC_HSI48_SUPPORT)
00204 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \
00205                                        ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK)  || \
00206                                        ((__SOURCE__) == RCC_MCO2SOURCE_HSI48)   || \
00207                                        ((__SOURCE__) == RCC_MCO2SOURCE_HSI)     || \
00208                                        ((__SOURCE__) == RCC_MCO2SOURCE_HSE)     || \
00209                                        ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK)  || \
00210                                        ((__SOURCE__) == RCC_MCO2SOURCE_LSI)     || \
00211                                        ((__SOURCE__) == RCC_MCO2SOURCE_LSE)     || \
00212                                        ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \
00213                                        ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \
00214                                        ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK)  || \
00215                                        ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP))
00216 #else
00217 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \
00218                                        ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK)  || \
00219                                        ((__SOURCE__) == RCC_MCO2SOURCE_HSI)     || \
00220                                        ((__SOURCE__) == RCC_MCO2SOURCE_HSE)     || \
00221                                        ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK)  || \
00222                                        ((__SOURCE__) == RCC_MCO2SOURCE_LSI)     || \
00223                                        ((__SOURCE__) == RCC_MCO2SOURCE_LSE)     || \
00224                                        ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \
00225                                        ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \
00226                                        ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK)  || \
00227                                        ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP))
00228 #endif /* RCC_HSI48_SUPPORT */
00229 #define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1)  || ((__DIV__) == RCC_MCO2DIV_2)  || \
00230                                  ((__DIV__) == RCC_MCO2DIV_4)  || ((__DIV__) == RCC_MCO2DIV_8)  || \
00231                                  ((__DIV__) == RCC_MCO2DIV_16) || ((__DIV__) == RCC_MCO2DIV_32) || \
00232                                  ((__DIV__) == RCC_MCO2DIV_64) || ((__DIV__) == RCC_MCO2DIV_128)|| \
00233                                  ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512)|| \
00234                                  ((__DIV__) == RCC_MCO2DIV_1024))
00235
00236 #endif /* RCC_MCO2_SUPPORT */
00237
00238 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
00239                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
00240                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
00241                                      ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
00242
00243 /**
00244   * @}
00245   */
00246
00247 /* Exported types ------------------------------------------------------------*/
00248 /** @defgroup RCC_Exported_Types RCC Exported Types
00249   * @{
00250   */
00251
00252 /**
00253   * @brief  RCC PLL configuration structure definition
00254   */
00255 typedef struct
00256 {
00257   uint32_t PLLState;   /*!< The new state of the PLL.
00258                             This parameter can be a value of @ref RCC_PLL_Config                      */
00259
00260   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
00261                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */
00262
00263   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
00264                             This parameter must be a value of @ref RCC_PLLM_Clock_Divider                  */
00265
00266   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
00267                             This parameter must be a number between Min_Data = 8 and Max_Data = 86    */
00268
00269   uint32_t PLLP;       /*!< PLLP: PLL Division factor.
00270                             User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ.
00271                             This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
00272
00273 #if defined(RCC_PLLQ_SUPPORT)
00274   uint32_t PLLQ;       /*!< PLLQ: PLL Division factor.
00275                             User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ.
00276                             This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */
00277 #endif /* RCC_PLLQ_SUPPORT */
00278
00279   uint32_t PLLR;       /*!< PLLR: PLL Division for the main system clock.
00280                             User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ.
00281                             This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */
00282
00283 } RCC_PLLInitTypeDef;
00284
00285 /**
00286   * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
00287   */
00288 typedef struct
00289 {
00290   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00291                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */
00292
00293   uint32_t HSEState;             /*!< The new state of the HSE.
00294                                       This parameter can be a value of @ref RCC_HSE_Config                        */
00295
00296   uint32_t LSEState;             /*!< The new state of the LSE.
00297                                       This parameter can be a value of @ref RCC_LSE_Config                        */
00298
00299   uint32_t HSIState;             /*!< The new state of the HSI.
00300                                       This parameter can be a value of @ref RCC_HSI_Config                        */
00301
00302   uint32_t HSIDiv;               /*!< The division factor of the HSI16.
00303                                       This parameter can be a value of @ref RCC_HSI_Div                           */
00304
00305   uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
00306                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00307
00308   uint32_t LSIState;             /*!< The new state of the LSI.
00309                                       This parameter can be a value of @ref RCC_LSI_Config                        */
00310
00311 #if defined(RCC_HSI48_SUPPORT)
00312   uint32_t HSI48State;             /*!< The new state of the HSI48 (only applicable to STM32G0C1xx/STM32G0B1xx/STM32G0B0xx devices).
00313                                         This parameter can be a value of @ref RCC_HSI48_Config */
00314
00315 #endif /* RCC_HSI48_SUPPORT */
00316
00317   RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */
00318
00319 } RCC_OscInitTypeDef;
00320
00321 /**
00322   * @brief  RCC System, AHB and APB buses clock configuration structure definition
00323   */
00324 typedef struct
00325 {
00326   uint32_t ClockType;             /*!< The clock to be configured.
00327                                        This parameter can be a combination of @ref RCC_System_Clock_Type      */
00328
00329   uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
00330                                        This parameter can be a value of @ref RCC_System_Clock_Source    */
00331
00332   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00333                                        This parameter can be a value of @ref RCC_AHB_Clock_Source       */
00334
00335   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00336                                        This parameter can be a value of @ref RCC_APB1_Clock_Source */
00337
00338
00339 } RCC_ClkInitTypeDef;
00340
00341 /**
00342   * @}
00343   */
00344
00345 /* Exported constants --------------------------------------------------------*/
00346 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00347   * @{
00348   */
00349
00350 /** @defgroup RCC_Timeout_Value Timeout Values
00351   * @{
00352   */
00353 #define RCC_DBP_TIMEOUT_VALUE          2U                   /* 2 ms (minimum Tick + 1)  */
00354 #define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT  /* LSE timeout in ms        */
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup RCC_Oscillator_Type Oscillator Type
00360   * @{
00361   */
00362 #define RCC_OSCILLATORTYPE_NONE        0x00000000U   /*!< Oscillator configuration unchanged */
00363 #define RCC_OSCILLATORTYPE_HSE         0x00000001U   /*!< HSE to configure */
00364 #define RCC_OSCILLATORTYPE_HSI         0x00000002U   /*!< HSI to configure */
00365 #define RCC_OSCILLATORTYPE_LSE         0x00000004U   /*!< LSE to configure */
00366 #define RCC_OSCILLATORTYPE_LSI         0x00000008U   /*!< LSI to configure */
00367 #if defined(RCC_HSI48_SUPPORT)
00368 #define RCC_OSCILLATORTYPE_HSI48       0x00000020U   /*!< HSI48 to configure */
00369 #endif /* RCC_HSI48_SUPPORT */
00370
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup RCC_HSE_Config HSE Config
00376   * @{
00377   */
00378 #define RCC_HSE_OFF                    0x00000000U                                /*!< HSE clock deactivation */
00379 #define RCC_HSE_ON                     RCC_CR_HSEON                               /*!< HSE clock activation */
00380 #define RCC_HSE_BYPASS                 (RCC_CR_HSEBYP | RCC_CR_HSEON)             /*!< External clock source for HSE clock */
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup RCC_LSE_Config LSE Config
00386   * @{
00387   */
00388 #define RCC_LSE_OFF                    0x00000000U                                    /*!< LSE clock deactivation */
00389 #define RCC_LSE_ON                     RCC_BDCR_LSEON                                 /*!< LSE clock activation */
00390 #define RCC_LSE_BYPASS                 (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)             /*!< External clock source for LSE clock */
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup RCC_HSI_Config HSI Config
00396   * @{
00397   */
00398 #define RCC_HSI_OFF                    0x00000000U            /*!< HSI clock deactivation */
00399 #define RCC_HSI_ON                     RCC_CR_HSION           /*!< HSI clock activation */
00400
00401 #define RCC_HSICALIBRATION_DEFAULT     64U                    /*!< Default HSI calibration trimming value */
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup RCC_HSI_Div HSI Div
00407   * @{
00408   */
00409 #define RCC_HSI_DIV1                   0x00000000U                                        /*!< HSI clock is not divided */
00410 #define RCC_HSI_DIV2                   RCC_CR_HSIDIV_0                                    /*!< HSI clock is divided by 2 */
00411 #define RCC_HSI_DIV4                   RCC_CR_HSIDIV_1                                    /*!< HSI clock is divided by 4 */
00412 #define RCC_HSI_DIV8                   (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)                  /*!< HSI clock is divided by 8 */
00413 #define RCC_HSI_DIV16                  RCC_CR_HSIDIV_2                                    /*!< HSI clock is divided by 16 */
00414 #define RCC_HSI_DIV32                  (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0)                  /*!< HSI clock is divided by 32 */
00415 #define RCC_HSI_DIV64                  (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1)                  /*!< HSI clock is divided by 64 */
00416 #define RCC_HSI_DIV128                 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0)  /*!< HSI clock is divided by 128 */
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup RCC_LSI_Config LSI Config
00422   * @{
00423   */
00424 #define RCC_LSI_OFF                    0x00000000U            /*!< LSI clock deactivation */
00425 #define RCC_LSI_ON                     RCC_CSR_LSION          /*!< LSI clock activation */
00426 /**
00427   * @}
00428   */
00429
00430 #if defined(RCC_HSI48_SUPPORT)
00431 /** @defgroup RCC_HSI48_Config HSI48 Config
00432   * @{
00433   */
00434 #define RCC_HSI48_OFF                  0x00000000U       /*!< HSI48 clock deactivation */
00435 #define RCC_HSI48_ON                   RCC_CR_HSI48ON    /*!< HSI48 clock activation */
00436 /**
00437   * @}
00438   */
00439 #endif /* RCC_HSI48_SUPPORT */
00440
00441 /** @defgroup RCC_PLL_Config PLL Config
00442   * @{
00443   */
00444 #define RCC_PLL_NONE                   0x00000000U /*!< PLL configuration unchanged */
00445 #define RCC_PLL_OFF                    0x00000001U /*!< PLL deactivation */
00446 #define RCC_PLL_ON                     0x00000002U /*!< PLL activation */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
00452   * @{
00453   */
00454 #define RCC_PLLM_DIV1                  0x00000000U                                                    /*!< PLLM division factor = 8  */
00455 #define RCC_PLLM_DIV2                  RCC_PLLCFGR_PLLM_0                                             /*!< PLLM division factor = 2  */
00456 #define RCC_PLLM_DIV3                  RCC_PLLCFGR_PLLM_1                                             /*!< PLLM division factor = 3  */
00457 #define RCC_PLLM_DIV4                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)                      /*!< PLLM division factor = 4  */
00458 #define RCC_PLLM_DIV5                  RCC_PLLCFGR_PLLM_2                                             /*!< PLLM division factor = 5  */
00459 #define RCC_PLLM_DIV6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)                      /*!< PLLM division factor = 6  */
00460 #define RCC_PLLM_DIV7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)                      /*!< PLLM division factor = 7  */
00461 #define RCC_PLLM_DIV8                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0)  /*!< PLLM division factor = 8  */
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
00467   * @{
00468   */
00469 #define RCC_PLLP_DIV2                  RCC_PLLCFGR_PLLP_0                                                                                       /*!< PLLP division factor = 2  */
00470 #define RCC_PLLP_DIV3                  RCC_PLLCFGR_PLLP_1                                                                                       /*!< PLLP division factor = 3  */
00471 #define RCC_PLLP_DIV4                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)                                                                /*!< PLLP division factor = 4  */
00472 #define RCC_PLLP_DIV5                  RCC_PLLCFGR_PLLP_2                                                                                       /*!< PLLP division factor = 5  */
00473 #define RCC_PLLP_DIV6                  (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)                                                                /*!< PLLP division factor = 6  */
00474 #define RCC_PLLP_DIV7                  (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)                                                                /*!< PLLP division factor = 7  */
00475 #define RCC_PLLP_DIV8                  (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)                                           /*!< PLLP division factor = 8  */
00476 #define RCC_PLLP_DIV9                  RCC_PLLCFGR_PLLP_3                                                                                       /*!< PLLP division factor = 9  */
00477 #define RCC_PLLP_DIV10                 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0)                                                                /*!< PLLP division factor = 10 */
00478 #define RCC_PLLP_DIV11                 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1)                                                                /*!< PLLP division factor = 11 */
00479 #define RCC_PLLP_DIV12                 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)                                           /*!< PLLP division factor = 12 */
00480 #define RCC_PLLP_DIV13                 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2)                                                                /*!< PLLP division factor = 13 */
00481 #define RCC_PLLP_DIV14                 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)                                           /*!< PLLP division factor = 14 */
00482 #define RCC_PLLP_DIV15                 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)                                           /*!< PLLP division factor = 15 */
00483 #define RCC_PLLP_DIV16                 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)                      /*!< PLLP division factor = 16 */
00484 #define RCC_PLLP_DIV17                 RCC_PLLCFGR_PLLP_4                                                                                       /*!< PLLP division factor = 17 */
00485 #define RCC_PLLP_DIV18                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0)                                                                /*!< PLLP division factor = 18 */
00486 #define RCC_PLLP_DIV19                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1)                                                                /*!< PLLP division factor = 19 */
00487 #define RCC_PLLP_DIV20                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)                                           /*!< PLLP division factor = 20 */
00488 #define RCC_PLLP_DIV21                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2)                                                                /*!< PLLP division factor = 21 */
00489 #define RCC_PLLP_DIV22                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)                                           /*!< PLLP division factor = 22 */
00490 #define RCC_PLLP_DIV23                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)                                           /*!< PLLP division factor = 23 */
00491 #define RCC_PLLP_DIV24                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)                      /*!< PLLP division factor = 24 */
00492 #define RCC_PLLP_DIV25                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3)                                                                /*!< PLLP division factor = 25 */
00493 #define RCC_PLLP_DIV26                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0)                                           /*!< PLLP division factor = 26 */
00494 #define RCC_PLLP_DIV27                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1)                                           /*!< PLLP division factor = 27 */
00495 #define RCC_PLLP_DIV28                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)                      /*!< PLLP division factor = 28 */
00496 #define RCC_PLLP_DIV29                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2)                                           /*!< PLLP division factor = 29 */
00497 #define RCC_PLLP_DIV30                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0)                      /*!< PLLP division factor = 30 */
00498 #define RCC_PLLP_DIV31                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1)                      /*!< PLLP division factor = 31 */
00499 #define RCC_PLLP_DIV32                 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 32 */
00500 /**
00501   * @}
00502   */
00503
00504 #if defined(RCC_PLLQ_SUPPORT)
00505 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
00506   * @{
00507   */
00508 #define RCC_PLLQ_DIV2                  RCC_PLLCFGR_PLLQ_0                                             /*!< PLLQ division factor = 2 */
00509 #define RCC_PLLQ_DIV3                  RCC_PLLCFGR_PLLQ_1                                             /*!< PLLQ division factor = 3 */
00510 #define RCC_PLLQ_DIV4                  (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0)                      /*!< PLLQ division factor = 4 */
00511 #define RCC_PLLQ_DIV5                  RCC_PLLCFGR_PLLQ_2                                             /*!< PLLQ division factor = 5 */
00512 #define RCC_PLLQ_DIV6                  (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0)                      /*!< PLLQ division factor = 6 */
00513 #define RCC_PLLQ_DIV7                  (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1)                      /*!< PLLQ division factor = 7 */
00514 #define RCC_PLLQ_DIV8                  (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0)  /*!< PLLQ division factor = 8 */
00515 /**  * @}
00516   */
00517 #endif /* RCC_PLLQ_SUPPORT */
00518
00519 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
00520   * @{
00521   */
00522 #define RCC_PLLR_DIV2                  RCC_PLLCFGR_PLLR_0                                             /*!< PLLR division factor = 2 */
00523 #define RCC_PLLR_DIV3                  RCC_PLLCFGR_PLLR_1                                             /*!< PLLR division factor = 3 */
00524 #define RCC_PLLR_DIV4                  (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0)                      /*!< PLLR division factor = 4 */
00525 #define RCC_PLLR_DIV5                  RCC_PLLCFGR_PLLR_2                                             /*!< PLLR division factor = 5 */
00526 #define RCC_PLLR_DIV6                  (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0)                      /*!< PLLR division factor = 6 */
00527 #define RCC_PLLR_DIV7                  (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1)                      /*!< PLLR division factor = 7 */
00528 #define RCC_PLLR_DIV8                  (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 8 */
00529 /**  * @}
00530   */
00531
00532 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
00533   * @{
00534   */
00535 #define RCC_PLLSOURCE_NONE             0x00000000U             /*!< No clock selected as PLL entry clock source  */
00536 #define RCC_PLLSOURCE_HSI              RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */
00537 #define RCC_PLLSOURCE_HSE              RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
00543   * @{
00544   */
00545 #define RCC_PLLPCLK                 RCC_PLLCFGR_PLLPEN      /*!< PLLPCLK selection from main PLL */
00546 #if defined(RCC_PLLQ_SUPPORT)
00547 #define RCC_PLLQCLK                 RCC_PLLCFGR_PLLQEN      /*!< PLLQCLK selection from main PLL */
00548 #endif /* RCC_PLLQ_SUPPORT */
00549 #define RCC_PLLRCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLRCLK selection from main PLL */
00550
00551 /**
00552   * @}
00553   */
00554
00555 /** @defgroup RCC_System_Clock_Type System Clock Type
00556   * @{
00557   */
00558 #define RCC_CLOCKTYPE_SYSCLK           0x00000001U  /*!< SYSCLK to configure */
00559 #define RCC_CLOCKTYPE_HCLK             0x00000002U  /*!< HCLK to configure */
00560 #define RCC_CLOCKTYPE_PCLK1            0x00000004U  /*!< PCLK1 to configure */
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup RCC_System_Clock_Source System Clock Source
00566   * @{
00567   */
00568 #define RCC_SYSCLKSOURCE_HSI           0x00000000U                       /*!< HSI selection as system clock */
00569 #define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_0                     /*!< HSE selection as system clock */
00570 #define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_1                     /*!< PLL selection as system clock */
00571 #define RCC_SYSCLKSOURCE_LSI           (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)   /*!< LSI selection as system clock */
00572 #define RCC_SYSCLKSOURCE_LSE           RCC_CFGR_SW_2                     /*!< LSE selection as system clock */
00573 /**
00574   * @}
00575   */
00576
00577 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00578   * @{
00579   */
00580 #define RCC_SYSCLKSOURCE_STATUS_HSI    0x00000000U                       /*!< HSI used as system clock */
00581 #define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_0                    /*!< HSE used as system clock */
00582 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_1                    /*!< PLL used as system clock */
00583 #define RCC_SYSCLKSOURCE_STATUS_LSI    (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */
00584 #define RCC_SYSCLKSOURCE_STATUS_LSE    RCC_CFGR_SWS_2                    /*!< LSE used as system clock */
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
00590   * @{
00591   */
00592 #define RCC_SYSCLK_DIV1                0x00000000U                                                             /*!< SYSCLK not divided */
00593 #define RCC_SYSCLK_DIV2                RCC_CFGR_HPRE_3                                                         /*!< SYSCLK divided by 2 */
00594 #define RCC_SYSCLK_DIV4                (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)                                     /*!< SYSCLK divided by 4 */
00595 #define RCC_SYSCLK_DIV8                (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)                                     /*!< SYSCLK divided by 8 */
00596 #define RCC_SYSCLK_DIV16               (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)                   /*!< SYSCLK divided by 16 */
00597 #define RCC_SYSCLK_DIV64               (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)                                     /*!< SYSCLK divided by 64 */
00598 #define RCC_SYSCLK_DIV128              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)                   /*!< SYSCLK divided by 128 */
00599 #define RCC_SYSCLK_DIV256              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)                   /*!< SYSCLK divided by 256 */
00600 #define RCC_SYSCLK_DIV512              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
00601 /**
00602   * @}
00603   */
00604
00605 /** @defgroup RCC_APB1_Clock_Source APB Clock Source
00606   * @{
00607   */
00608 #define RCC_HCLK_DIV1                  0x00000000U                                           /*!< HCLK not divided */
00609 #define RCC_HCLK_DIV2                  RCC_CFGR_PPRE_2                                       /*!< HCLK divided by 2 */
00610 #define RCC_HCLK_DIV4                  (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)                   /*!< HCLK divided by 4 */
00611 #define RCC_HCLK_DIV8                  (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)                   /*!< HCLK divided by 8 */
00612 #define RCC_HCLK_DIV16                 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
00613 /**
00614   * @}
00615   */
00616
00617 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
00618   * @{
00619   */
00620 #define RCC_RTCCLKSOURCE_NONE          0x00000000U            /*!< No clock configured for RTC */
00621 #define RCC_RTCCLKSOURCE_LSE           RCC_BDCR_RTCSEL_0      /*!< LSE oscillator clock used as RTC clock */
00622 #define RCC_RTCCLKSOURCE_LSI           RCC_BDCR_RTCSEL_1      /*!< LSI oscillator clock used as RTC clock */
00623 #define RCC_RTCCLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL        /*!< HSE oscillator clock divided by 32 used as RTC clock */
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup RCC_MCO_Index MCO Index
00629   * @{
00630   */
00631 #define RCC_MCO1                       0x00000000U
00632 #if defined(RCC_MCO2_SUPPORT)
00633 #define RCC_MCO2                       0x00000001U            /*!< MCO2 index */
00634 #endif /* RCC_MCO2_SUPPORT */
00635
00636 #define RCC_MCO                        RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
00642   * @{
00643   */
00644 #define RCC_MCO1SOURCE_NOCLOCK         0x00000000U                            /*!< MCO1 output disabled, no clock on MCO1 */
00645 #define RCC_MCO1SOURCE_SYSCLK          RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
00646 #if defined(RCC_HSI48_SUPPORT)
00647 #define RCC_MCO1SOURCE_HSI48           RCC_CFGR_MCOSEL_1                      /*!< HSI48 selection as MCO1 source */
00648 #endif /* RCC_HSI48_SUPPORT */
00649 #define RCC_MCO1SOURCE_HSI             (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
00650 #define RCC_MCO1SOURCE_HSE             RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
00651 #define RCC_MCO1SOURCE_PLLCLK          (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */
00652 #define RCC_MCO1SOURCE_LSI             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
00653 #define RCC_MCO1SOURCE_LSE             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
00654 #if defined(RCC_CFGR_MCOSEL_3)
00655 #define RCC_MCO1SOURCE_PLLPCLK         RCC_CFGR_MCOSEL_3                       /*!< PLLPCLK selection as MCO1 source */
00656 #define RCC_MCO1SOURCE_PLLQCLK         (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)   /*!< PLLQCLK selection as MCO1 source */
00657 #define RCC_MCO1SOURCE_RTCCLK          (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)   /*!< RTCCLK selection as MCO1 source */
00658 #define RCC_MCO1SOURCE_RTC_WKUP        (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */
00659 #endif /* RCC_CFGR_MCOSEL_3 */
00660 /**
00661   * @}
00662   */
00663
00664 /** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler
00665   * @{
00666   */
00667 #define RCC_MCODIV_1                   0x00000000U                                                 /*!< MCO not divided */
00668 #define RCC_MCODIV_2                   RCC_CFGR_MCOPRE_0                                           /*!< MCO divided by 2 */
00669 #define RCC_MCODIV_4                   RCC_CFGR_MCOPRE_1                                           /*!< MCO divided by 4 */
00670 #define RCC_MCODIV_8                   (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)                     /*!< MCO divided by 8 */
00671 #define RCC_MCODIV_16                  RCC_CFGR_MCOPRE_2                                           /*!< MCO divided by 16 */
00672 #define RCC_MCODIV_32                  (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)                     /*!< MCO divided by 32 */
00673 #define RCC_MCODIV_64                  (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)                     /*!< MCO divided by 64 */
00674 #define RCC_MCODIV_128                 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */
00675 #if defined(RCC_CFGR_MCOPRE_3)
00676 #define RCC_MCODIV_256                 RCC_CFGR_MCOPRE_3                                           /*!< MCO divided by 256 */
00677 #define RCC_MCODIV_512                (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)                      /*!< MCO divided by 512 */
00678 #define RCC_MCODIV_1024               (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)                      /*!< MCO divided by 1024 */
00679 #endif /* RCC_CFGR_MCOSEL_3 */
00680 /**
00681   * @}
00682   */
00683
00684 #if defined(RCC_MCO2_SUPPORT)
00685 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
00686   * @{
00687   */
00688 #define RCC_MCO2SOURCE_NOCLOCK         0x00000000U                              /*!< MCO2 output disabled, no clock on MCO2 */
00689 #define RCC_MCO2SOURCE_SYSCLK          RCC_CFGR_MCO2SEL_0                       /*!< SYSCLK selection as MCO2 source */
00690 #if defined(RCC_HSI48_SUPPORT)
00691 #define RCC_MCO2SOURCE_HSI48           RCC_CFGR_MCO2SEL_1                       /*!< HSI48 selection as MCO2 source */
00692 #endif /* RCC_HSI48_SUPPORT */
00693 #define RCC_MCO2SOURCE_HSI             (RCC_CFGR_MCO2SEL_1| RCC_CFGR_MCO2SEL_0) /*!< HSI selection as MCO2 source */
00694 #define RCC_MCO2SOURCE_HSE             RCC_CFGR_MCO2SEL_2                       /*!< HSE selection as MCO2 source */
00695 #define RCC_MCO2SOURCE_PLLCLK          (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_0)  /*!< PLLCLK selection as MCO2 source */
00696 #define RCC_MCO2SOURCE_LSI             (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1)  /*!< LSI selection as MCO2 source */
00697 #define RCC_MCO2SOURCE_LSE             (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */
00698 #define RCC_MCO2SOURCE_PLLPCLK         RCC_CFGR_MCO2SEL_3                       /*!< PLLPCLK selection as MCO2 source */
00699 #define RCC_MCO2SOURCE_PLLQCLK         (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0)  /*!< PLLQCLK selection as MCO2 source */
00700 #define RCC_MCO2SOURCE_RTCCLK          (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1)  /*!< RTCCLK selection as MCO2 source */
00701 #define RCC_MCO2SOURCE_RTC_WKUP        (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */
00702 /**
00703   * @}
00704   */
00705
00706 /** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler
00707   * @{
00708   */
00709 #define RCC_MCO2DIV_1                  0x00000000U                                                    /*!< MCO2 not divided */
00710 #define RCC_MCO2DIV_2                  RCC_CFGR_MCO2PRE_0                                             /*!< MCO2 divided by 2 */
00711 #define RCC_MCO2DIV_4                  RCC_CFGR_MCO2PRE_1                                             /*!< MCO2 divided by 4 */
00712 #define RCC_MCO2DIV_8                  (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 8 */
00713 #define RCC_MCO2DIV_16                 RCC_CFGR_MCO2PRE_2                                             /*!< MCO2 divided by 16 */
00714 #define RCC_MCO2DIV_32                 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 32 */
00715 #define RCC_MCO2DIV_64                 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)                      /*!< MCO2 divided by 64 */
00716 #define RCC_MCO2DIV_128                (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */
00717 #define RCC_MCO2DIV_256                RCC_CFGR_MCO2PRE_3                                             /*!< MCO2 divided by 256 */
00718 #define RCC_MCO2DIV_512                (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 512 */
00719 #define RCC_MCO2DIV_1024               (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)                      /*!< MCO2 divided by 1024 */
00720 /**
00721   * @}
00722   */
00723 #endif /* RCC_MCO2_SUPPORT */
00724
00725 /** @defgroup RCC_Interrupt Interrupts
00726   * @{
00727   */
00728 #define RCC_IT_LSIRDY                  RCC_CIFR_LSIRDYF            /*!< LSI Ready Interrupt flag */
00729 #define RCC_IT_LSERDY                  RCC_CIFR_LSERDYF            /*!< LSE Ready Interrupt flag */
00730 #define RCC_IT_HSIRDY                  RCC_CIFR_HSIRDYF            /*!< HSI Ready Interrupt flag */
00731 #define RCC_IT_HSERDY                  RCC_CIFR_HSERDYF            /*!< HSE Ready Interrupt flag */
00732 #define RCC_IT_PLLRDY                  RCC_CIFR_PLLRDYF            /*!< PLL Ready Interrupt flag */
00733 #define RCC_IT_CSS                     RCC_CIFR_CSSF               /*!< HSE Clock Security System Interrupt flag */
00734 #define RCC_IT_LSECSS                  RCC_CIFR_LSECSSF            /*!< LSE Clock Security System Interrupt flag */
00735 #if defined(RCC_HSI48_SUPPORT)
00736 #define RCC_IT_HSI48RDY                RCC_CIFR_HSI48RDYF          /*!< HSI48 Ready Interrupt flag */
00737 #endif /* RCC_HSI48_SUPPORT */
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup RCC_Flag Flags
00743   *        Elements values convention: XXXYYYYYb
00744   *           - YYYYY  : Flag position in the register
00745   *           - XXX  : Register index
00746   *                 - 001: CR register
00747   *                 - 010: BDCR register
00748   *                 - 011: CSR register
00749   * @{
00750   */
00751 /* Flags in the CR register */
00752 #define RCC_FLAG_HSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)  /*!< HSI Ready flag */
00753 #define RCC_FLAG_HSERDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)  /*!< HSE Ready flag */
00754 #define RCC_FLAG_PLLRDY                ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)  /*!< PLL Ready flag */
00755
00756 #if defined(RCC_HSI48_SUPPORT)
00757 /* Flags in the CR register */
00758 #define RCC_FLAG_HSI48RDY              ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
00759 #endif /* RCC_HSI48_SUPPORT */
00760
00761 /* Flags in the BDCR register */
00762 #define RCC_FLAG_LSERDY                ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)  /*!< LSE Ready flag */
00763 #define RCC_FLAG_LSECSSD               ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
00764
00765 /* Flags in the CSR register */
00766 #define RCC_FLAG_LSIRDY                ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)    /*!< LSI Ready flag */
00767 #define RCC_FLAG_OBLRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)   /*!< Option Byte Loader reset flag */
00768 #define RCC_FLAG_PINRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)   /*!< PIN reset flag */
00769 #define RCC_FLAG_PWRRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos)   /*!< BOR or POR/PDR reset flag */
00770 #define RCC_FLAG_SFTRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)   /*!< Software Reset flag */
00771 #define RCC_FLAG_IWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)  /*!< Independent Watchdog reset flag */
00772 #define RCC_FLAG_WWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)  /*!< Window watchdog reset flag */
00773 #define RCC_FLAG_LPWRRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)  /*!< Low-Power reset flag */
00774
00775 /**
00776   * @}
00777   */
00778
00779 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration
00780   * @{
00781   */
00782 #define RCC_LSEDRIVE_LOW                 0x00000000U            /*!< LSE low drive capability */
00783 #define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
00784 #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
00785 #define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup RCC_Reset_Flag Reset Flag
00791   * @{
00792   */
00793 #define RCC_RESET_FLAG_OBL             RCC_CSR_OBLRSTF    /*!< Option Byte Loader reset flag */
00794 #define RCC_RESET_FLAG_PIN             RCC_CSR_PINRSTF    /*!< PIN reset flag */
00795 #define RCC_RESET_FLAG_PWR             RCC_CSR_PWRRSTF    /*!< BOR or POR/PDR reset flag */
00796 #define RCC_RESET_FLAG_SW              RCC_CSR_SFTRSTF    /*!< Software Reset flag */
00797 #define RCC_RESET_FLAG_IWDG            RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
00798 #define RCC_RESET_FLAG_WWDG            RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
00799 #define RCC_RESET_FLAG_LPWR            RCC_CSR_LPWRRSTF   /*!< Low power reset flag */
00800 #define RCC_RESET_FLAG_ALL             (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \
00801                                         RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \
00802                                         RCC_RESET_FLAG_LPWR)
00803 /**
00804   * @}
00805   */
00806
00807 /**
00808   * @}
00809   */
00810
00811 /* Exported macros -----------------------------------------------------------*/
00812
00813 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00814   * @{
00815   */
00816
00817 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
00818   * @brief  Enable or disable the AHB peripheral clock.
00819   * @note   After reset, the peripheral clock (used for registers read/write access)
00820   *         is disabled and the application software has to enable this clock before
00821   *         using it.
00822   * @{
00823   */
00824
00825 #define __HAL_RCC_DMA1_CLK_ENABLE()            do { \
00826                                                     __IO uint32_t tmpreg; \
00827                                                     SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
00828    /* Delay after an RCC peripheral clock enabling */ \
00829                                                     tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
00830                                                     UNUSED(tmpreg); \
00831                                                   } while(0U)
00832
00833 #if defined(DMA2)
00834 #define __HAL_RCC_DMA2_CLK_ENABLE()            do { \
00835                                                     __IO uint32_t tmpreg; \
00836                                                     SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
00837    /* Delay after an RCC peripheral clock enabling */ \
00838                                                     tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
00839                                                     UNUSED(tmpreg); \
00840                                                   } while(0U)
00841
00842 #endif /* DMA2 */
00843
00844
00845 #define __HAL_RCC_FLASH_CLK_ENABLE()           do { \
00846                                                     __IO uint32_t tmpreg; \
00847                                                     SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
00848    /* Delay after an RCC peripheral clock enabling */ \
00849                                                     tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
00850                                                     UNUSED(tmpreg); \
00851                                                   } while(0U)
00852
00853 #define __HAL_RCC_CRC_CLK_ENABLE()             do { \
00854                                                     __IO uint32_t tmpreg; \
00855                                                     SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
00856    /* Delay after an RCC peripheral clock enabling */ \
00857                                                     tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
00858                                                     UNUSED(tmpreg); \
00859                                                   } while(0U)
00860
00861 #if defined(RNG)
00862 #define __HAL_RCC_RNG_CLK_ENABLE()             do { \
00863                                                     __IO uint32_t tmpreg; \
00864                                                     SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
00865    /* Delay after an RCC peripheral clock enabling */ \
00866                                                     tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
00867                                                     UNUSED(tmpreg); \
00868                                                   } while(0U)
00869 #endif /* RNG */
00870
00871 #if defined(AES)
00872 #define __HAL_RCC_AES_CLK_ENABLE()             do { \
00873                                                     __IO uint32_t tmpreg; \
00874                                                     SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
00875    /* Delay after an RCC peripheral clock enabling */ \
00876                                                     tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
00877                                                     UNUSED(tmpreg); \
00878                                                   } while(0U)
00879 #endif /* AES */
00880
00881 #define __HAL_RCC_DMA1_CLK_DISABLE()           CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
00882 #if defined(DMA2)
00883 #define __HAL_RCC_DMA2_CLK_DISABLE()           CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)
00884 #endif /* DMA2 */
00885 #define __HAL_RCC_FLASH_CLK_DISABLE()          CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN)
00886 #define __HAL_RCC_CRC_CLK_DISABLE()            CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
00887 #if defined(RNG)
00888 #define __HAL_RCC_RNG_CLK_DISABLE()            CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN)
00889 #endif /* RNG */
00890 #if defined(AES)
00891 #define __HAL_RCC_AES_CLK_DISABLE()            CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN)
00892 #endif /* AES */
00893 /**
00894   * @}
00895   */
00896
00897 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable
00898   * @brief  Enable or disable the IO Ports clock.
00899   * @note   After reset, the IO ports clock (used for registers read/write access)
00900   *         is disabled and the application software has to enable this clock before
00901   *         using it.
00902   * @{
00903   */
00904
00905 #define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \
00906                                                     __IO uint32_t tmpreg; \
00907                                                     SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
00908    /* Delay after an RCC peripheral clock enabling */ \
00909                                                     tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
00910                                                     UNUSED(tmpreg); \
00911                                                   } while(0U)
00912
00913 #define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \
00914                                                     __IO uint32_t tmpreg; \
00915                                                     SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
00916    /* Delay after an RCC peripheral clock enabling */ \
00917                                                     tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
00918                                                     UNUSED(tmpreg); \
00919                                                   } while(0U)
00920
00921 #define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \
00922                                                     __IO uint32_t tmpreg; \
00923                                                     SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
00924    /* Delay after an RCC peripheral clock enabling */ \
00925                                                     tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
00926                                                     UNUSED(tmpreg); \
00927                                                   } while(0U)
00928
00929 #define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \
00930                                                     __IO uint32_t tmpreg; \
00931                                                     SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
00932    /* Delay after an RCC peripheral clock enabling */ \
00933                                                     tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
00934                                                     UNUSED(tmpreg); \
00935                                                   } while(0U)
00936
00937 #if defined(GPIOE)
00938 #define __HAL_RCC_GPIOE_CLK_ENABLE()           do { \
00939                                                     __IO uint32_t tmpreg; \
00940                                                     SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
00941    /* Delay after an RCC peripheral clock enabling */ \
00942                                                     tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
00943                                                     UNUSED(tmpreg); \
00944                                                   } while(0U)
00945 #endif /* GPIOE */
00946
00947 #define __HAL_RCC_GPIOF_CLK_ENABLE()           do { \
00948                                                     __IO uint32_t tmpreg; \
00949                                                     SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
00950    /* Delay after an RCC peripheral clock enabling */ \
00951                                                     tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
00952                                                     UNUSED(tmpreg); \
00953                                                   } while(0U)
00954
00955 #define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
00956 #define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
00957 #define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
00958 #define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN)
00959 #if defined(GPIOE)
00960 #define __HAL_RCC_GPIOE_CLK_DISABLE()          CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN)
00961 #endif /* GPIOE */
00962 #define __HAL_RCC_GPIOF_CLK_DISABLE()          CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN)
00963
00964 /**
00965   * @}
00966   */
00967
00968 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
00969   * @brief  Enable or disable the APB1 peripheral clock.
00970   * @note   After reset, the peripheral clock (used for registers read/write access)
00971   *         is disabled and the application software has to enable this clock before
00972   *         using it.
00973   * @{
00974   */
00975 #if defined(TIM2)
00976 #define __HAL_RCC_TIM2_CLK_ENABLE()            do { \
00977                                                     __IO uint32_t tmpreg; \
00978                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
00979    /* Delay after an RCC peripheral clock enabling */ \
00980                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
00981                                                     UNUSED(tmpreg); \
00982                                                   } while(0U)
00983 #endif /* TIM2 */
00984
00985 #define __HAL_RCC_TIM3_CLK_ENABLE()            do { \
00986                                                     __IO uint32_t tmpreg; \
00987                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
00988    /* Delay after an RCC peripheral clock enabling */ \
00989                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
00990                                                     UNUSED(tmpreg); \
00991                                                   } while(0U)
00992
00993 #if defined(TIM4)
00994 #define __HAL_RCC_TIM4_CLK_ENABLE()            do { \
00995                                                     __IO uint32_t tmpreg; \
00996                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
00997    /* Delay after an RCC peripheral clock enabling */ \
00998                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
00999                                                     UNUSED(tmpreg); \
01000                                                   } while(0U)
01001 #endif /* TIM4 */
01002
01003 #define __HAL_RCC_TIM6_CLK_ENABLE()            do { \
01004                                                     __IO uint32_t tmpreg; \
01005                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
01006    /* Delay after an RCC peripheral clock enabling */ \
01007                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
01008                                                     UNUSED(tmpreg); \
01009                                                   } while(0U)
01010
01011 #define __HAL_RCC_TIM7_CLK_ENABLE()            do { \
01012                                                     __IO uint32_t tmpreg; \
01013                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
01014    /* Delay after an RCC peripheral clock enabling */ \
01015                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
01016                                                     UNUSED(tmpreg); \
01017                                                   } while(0U)
01018
01019 #if defined(CRS)
01020 #define __HAL_RCC_CRS_CLK_ENABLE()             do { \
01021                                                     __IO uint32_t tmpreg; \
01022                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
01023    /* Delay after an RCC peripheral clock enabling */ \
01024                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
01025                                                     UNUSED(tmpreg); \
01026                                                   } while(0)
01027 #endif /* CRS */
01028
01029 #define __HAL_RCC_RTCAPB_CLK_ENABLE()          do { \
01030                                                     __IO uint32_t tmpreg; \
01031                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
01032    /* Delay after an RCC peripheral clock enabling */ \
01033                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
01034                                                     UNUSED(tmpreg); \
01035                                                   } while(0U)
01036
01037 #define __HAL_RCC_WWDG_CLK_ENABLE()            do { \
01038                                                     __IO uint32_t tmpreg; \
01039                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
01040    /* Delay after an RCC peripheral clock enabling */ \
01041                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
01042                                                     UNUSED(tmpreg); \
01043                                                   } while(0U)
01044
01045 #define __HAL_RCC_SPI2_CLK_ENABLE()            do { \
01046                                                     __IO uint32_t tmpreg; \
01047                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
01048    /* Delay after an RCC peripheral clock enabling */ \
01049                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
01050                                                     UNUSED(tmpreg); \
01051                                                   } while(0U)
01052 #if defined(SPI3)
01053 #define __HAL_RCC_SPI3_CLK_ENABLE()            do { \
01054                                                     __IO uint32_t tmpreg; \
01055                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
01056    /* Delay after an RCC peripheral clock enabling */ \
01057                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
01058                                                     UNUSED(tmpreg); \
01059                                                   } while(0U)
01060 #endif /* SPI3 */
01061
01062 #define __HAL_RCC_USART2_CLK_ENABLE()          do { \
01063                                                     __IO uint32_t tmpreg; \
01064                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
01065    /* Delay after an RCC peripheral clock enabling */ \
01066                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
01067                                                     UNUSED(tmpreg); \
01068                                                   } while(0U)
01069
01070 #define __HAL_RCC_USART3_CLK_ENABLE()          do { \
01071                                                     __IO uint32_t tmpreg; \
01072                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
01073    /* Delay after an RCC peripheral clock enabling */ \
01074                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
01075                                                     UNUSED(tmpreg); \
01076                                                   } while(0U)
01077
01078 #define __HAL_RCC_USART4_CLK_ENABLE()           do { \
01079                                                      __IO uint32_t tmpreg; \
01080                                                      SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
01081     /* Delay after an RCC peripheral clock enabling */ \
01082                                                      tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
01083                                                      UNUSED(tmpreg); \
01084                                                    } while(0U)
01085
01086 #if defined(USART5)
01087 #define __HAL_RCC_USART5_CLK_ENABLE()           do { \
01088                                                      __IO uint32_t tmpreg; \
01089                                                      SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
01090     /* Delay after an RCC peripheral clock enabling */ \
01091                                                      tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
01092                                                      UNUSED(tmpreg); \
01093                                                    } while(0U)
01094 #endif /* USART5 */
01095
01096 #if defined(USART6)
01097 #define __HAL_RCC_USART6_CLK_ENABLE()           do { \
01098                                                      __IO uint32_t tmpreg; \
01099                                                      SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
01100     /* Delay after an RCC peripheral clock enabling */ \
01101                                                      tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
01102                                                      UNUSED(tmpreg); \
01103                                                    } while(0U)
01104 #endif /* USART6 */
01105
01106 #if defined(LPUART1)
01107 #define __HAL_RCC_LPUART1_CLK_ENABLE()         do { \
01108                                                     __IO uint32_t tmpreg; \
01109                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
01110    /* Delay after an RCC peripheral clock enabling */ \
01111                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
01112                                                     UNUSED(tmpreg); \
01113                                                   } while(0U)
01114 #endif /* LPUART1 */
01115
01116 #if defined(LPUART2)
01117 #define __HAL_RCC_LPUART2_CLK_ENABLE()         do { \
01118                                                     __IO uint32_t tmpreg; \
01119                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
01120    /* Delay after an RCC peripheral clock enabling */ \
01121                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
01122                                                     UNUSED(tmpreg); \
01123                                                   } while(0U)
01124 #endif /* LPUART2 */
01125
01126 #define __HAL_RCC_I2C1_CLK_ENABLE()            do { \
01127                                                     __IO uint32_t tmpreg; \
01128                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
01129    /* Delay after an RCC peripheral clock enabling */ \
01130                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
01131                                                     UNUSED(tmpreg); \
01132                                                   } while(0U)
01133
01134 #define __HAL_RCC_I2C2_CLK_ENABLE()            do { \
01135                                                     __IO uint32_t tmpreg; \
01136                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
01137    /* Delay after an RCC peripheral clock enabling */ \
01138                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
01139                                                     UNUSED(tmpreg); \
01140                                                   } while(0U)
01141
01142 #if defined(I2C3)
01143 #define __HAL_RCC_I2C3_CLK_ENABLE()            do { \
01144                                                     __IO uint32_t tmpreg; \
01145                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
01146    /* Delay after an RCC peripheral clock enabling */ \
01147                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
01148                                                     UNUSED(tmpreg); \
01149                                                   } while(0U)
01150 #endif /* I2C3 */
01151
01152 #if defined(CEC)
01153 #define __HAL_RCC_CEC_CLK_ENABLE()             do { \
01154                                                     __IO uint32_t tmpreg; \
01155                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
01156    /* Delay after an RCC peripheral clock enabling */ \
01157                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
01158                                                     UNUSED(tmpreg); \
01159                                                   } while(0U)
01160 #endif /* CEC */
01161
01162 #if defined(UCPD1)
01163 #define __HAL_RCC_UCPD1_CLK_ENABLE()             do { \
01164                                                       __IO uint32_t tmpreg; \
01165                                                       SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
01166      /* Delay after an RCC peripheral clock enabling */ \
01167                                                       tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
01168                                                       UNUSED(tmpreg); \
01169                                                     } while(0U)
01170 #endif /* UCPD1 */
01171
01172 #if defined(UCPD2)
01173 #define __HAL_RCC_UCPD2_CLK_ENABLE()             do { \
01174                                                       __IO uint32_t tmpreg; \
01175                                                       SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
01176      /* Delay after an RCC peripheral clock enabling */ \
01177                                                       tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
01178                                                       UNUSED(tmpreg); \
01179                                                     } while(0U)
01180 #endif /* UCPD2 */
01181
01182 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
01183 #define __HAL_RCC_USB_CLK_ENABLE()               do { \
01184                                                       __IO uint32_t tmpreg; \
01185                                                       SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
01186      /* Delay after an RCC peripheral clock enabling */ \
01187                                                       tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
01188                                                       UNUSED(tmpreg); \
01189                                                     } while(0U)
01190 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
01191
01192 #if defined(FDCAN1) || defined(FDCAN2)
01193 #define __HAL_RCC_FDCAN_CLK_ENABLE()            do { \
01194                                                      __IO uint32_t tmpreg; \
01195                                                      SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
01196     /* Delay after an RCC peripheral clock enabling */ \
01197                                                      tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
01198                                                      UNUSED(tmpreg); \
01199                                                    } while(0)
01200 #endif /* FDCAN1 || FDCAN2 */
01201
01202 #define __HAL_RCC_DBGMCU_CLK_ENABLE()             do { \
01203                                                        __IO uint32_t tmpreg; \
01204                                                        SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
01205       /* Delay after an RCC peripheral clock enabling */ \
01206                                                        tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
01207                                                        UNUSED(tmpreg); \
01208                                                      } while(0U)
01209
01210 #define __HAL_RCC_PWR_CLK_ENABLE()             do { \
01211                                                     __IO uint32_t tmpreg; \
01212                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
01213    /* Delay after an RCC peripheral clock enabling */ \
01214                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
01215                                                     UNUSED(tmpreg); \
01216                                                   } while(0U)
01217
01218 #if defined(DAC1)
01219 #define __HAL_RCC_DAC1_CLK_ENABLE()            do { \
01220                                                     __IO uint32_t tmpreg; \
01221                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
01222    /* Delay after an RCC peripheral clock enabling */ \
01223                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
01224                                                     UNUSED(tmpreg); \
01225                                                   } while(0U)
01226 #endif /* DAC1 */
01227
01228 #if defined(LPTIM2)
01229 #define __HAL_RCC_LPTIM2_CLK_ENABLE()          do { \
01230                                                     __IO uint32_t tmpreg; \
01231                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
01232    /* Delay after an RCC peripheral clock enabling */ \
01233                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
01234                                                     UNUSED(tmpreg); \
01235                                                   } while(0U)
01236 #endif /* LPTIM2 */
01237
01238 #if defined(LPTIM1)
01239 #define __HAL_RCC_LPTIM1_CLK_ENABLE()          do { \
01240                                                     __IO uint32_t tmpreg; \
01241                                                     SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
01242    /* Delay after an RCC peripheral clock enabling */ \
01243                                                     tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
01244                                                     UNUSED(tmpreg); \
01245                                                   } while(0U)
01246 #endif /* LPTIM1 */
01247
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
01253   * @brief  Enable or disable the APB2 peripheral clock.
01254   * @note   After reset, the peripheral clock (used for registers read/write access)
01255   *         is disabled and the application software has to enable this clock before
01256   *         using it.
01257   * @{
01258   */
01259
01260 #define __HAL_RCC_SYSCFG_CLK_ENABLE()          do { \
01261                                                     __IO uint32_t tmpreg; \
01262                                                     SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
01263    /* Delay after an RCC peripheral clock enabling */ \
01264                                                     tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
01265                                                     UNUSED(tmpreg); \
01266                                                   } while(0U)
01267
01268 #define __HAL_RCC_TIM1_CLK_ENABLE()            do { \
01269                                                     __IO uint32_t tmpreg; \
01270                                                     SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
01271    /* Delay after an RCC peripheral clock enabling */ \
01272                                                     tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
01273                                                     UNUSED(tmpreg); \
01274                                                   } while(0U)
01275
01276 #define __HAL_RCC_SPI1_CLK_ENABLE()            do { \
01277                                                     __IO uint32_t tmpreg; \
01278                                                     SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
01279    /* Delay after an RCC peripheral clock enabling */ \
01280                                                     tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
01281                                                     UNUSED(tmpreg); \
01282                                                   } while(0U)
01283
01284 #define __HAL_RCC_USART1_CLK_ENABLE()          do { \
01285                                                     __IO uint32_t tmpreg; \
01286                                                     SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
01287    /* Delay after an RCC peripheral clock enabling */ \
01288                                                     tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
01289                                                     UNUSED(tmpreg); \
01290                                                   } while(0U)
01291
01292 #define __HAL_RCC_TIM14_CLK_ENABLE()            do { \
01293                                                      __IO uint32_t tmpreg; \
01294                                                      SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
01295     /* Delay after an RCC peripheral clock enabling */ \
01296                                                      tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
01297                                                      UNUSED(tmpreg); \
01298                                                    } while(0U)
01299
01300 #if defined(TIM15)
01301 #define __HAL_RCC_TIM15_CLK_ENABLE()           do { \
01302                                                     __IO uint32_t tmpreg; \
01303                                                     SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
01304    /* Delay after an RCC peripheral clock enabling */ \
01305                                                     tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
01306                                                     UNUSED(tmpreg); \
01307                                                   } while(0U)
01308 #endif /* TIM15 */
01309
01310 #define __HAL_RCC_TIM16_CLK_ENABLE()           do { \
01311                                                     __IO uint32_t tmpreg; \
01312                                                     SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
01313    /* Delay after an RCC peripheral clock enabling */ \
01314                                                     tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
01315                                                     UNUSED(tmpreg); \
01316                                                   } while(0U)
01317
01318 #define __HAL_RCC_TIM17_CLK_ENABLE()           do { \
01319                                                     __IO uint32_t tmpreg; \
01320                                                     SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
01321    /* Delay after an RCC peripheral clock enabling */ \
01322                                                     tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
01323                                                     UNUSED(tmpreg); \
01324                                                   } while(0U)
01325
01326 #define __HAL_RCC_ADC_CLK_ENABLE()           do { \
01327                                                   __IO uint32_t tmpreg; \
01328                                                   SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
01329  /* Delay after an RCC peripheral clock enabling */ \
01330                                                   tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
01331                                                   UNUSED(tmpreg); \
01332                                                 } while(0U)
01333
01334 #if defined(TIM2)
01335 #define __HAL_RCC_TIM2_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
01336 #endif /* TIM2 */
01337 #define __HAL_RCC_TIM3_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)
01338 #if defined(TIM4)
01339 #define __HAL_RCC_TIM4_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN)
01340 #endif /* TIM4 */
01341 #if defined(TIM6)
01342 #define __HAL_RCC_TIM6_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN)
01343 #endif /* TIM6 */
01344 #if defined(TIM7)
01345 #define __HAL_RCC_TIM7_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN)
01346 #endif /* TIM7 */
01347 #if defined(CRS)
01348 #define __HAL_RCC_CRS_CLK_DISABLE()            CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN);
01349 #endif /* CRS */
01350 #define __HAL_RCC_RTCAPB_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN)
01351 #define __HAL_RCC_SPI2_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN)
01352 #if defined(SPI3)
01353 #define __HAL_RCC_SPI3_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN)
01354 #endif /* SPI3 */
01355 #define __HAL_RCC_USART2_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN)
01356 #if defined(USART3)
01357 #define __HAL_RCC_USART3_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN)
01358 #endif /* USART3 */
01359 #if defined(USART4)
01360 #define __HAL_RCC_USART4_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN)
01361 #endif /* USART4 */
01362 #if defined(USART5)
01363 #define __HAL_RCC_USART5_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN)
01364 #endif /* USART5 */
01365 #if defined(USART6)
01366 #define __HAL_RCC_USART6_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN)
01367 #endif /* USART6 */
01368 #if defined(LPUART1)
01369 #define __HAL_RCC_LPUART1_CLK_DISABLE()        CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)
01370 #endif /* LPUART1 */
01371 #if defined(LPUART2)
01372 #define __HAL_RCC_LPUART2_CLK_DISABLE()        CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)
01373 #endif /* LPUART2 */
01374 #define __HAL_RCC_I2C1_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN)
01375 #define __HAL_RCC_I2C2_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN)
01376 #if defined(I2C3)
01377 #define __HAL_RCC_I2C3_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN)
01378 #endif /* I2C3 */
01379 #if defined(CEC)
01380 #define __HAL_RCC_CEC_CLK_DISABLE()            CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN)
01381 #endif /* CEC */
01382 #if defined(UCPD1)
01383 #define __HAL_RCC_UCPD1_CLK_DISABLE()          CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN)
01384 #endif /* UCPD1 */
01385 #if defined(UCPD2)
01386 #define __HAL_RCC_UCPD2_CLK_DISABLE()          CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN)
01387 #endif /* UCPD2 */
01388 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
01389 #define __HAL_RCC_USB_CLK_DISABLE()             CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN)
01390 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
01391 #if defined(FDCAN1) || defined(FDCAN2)
01392 #define __HAL_RCC_FDCAN_CLK_DISABLE()          CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN)
01393 #endif /* FDCAN1 || FDCAN2 */
01394 #define __HAL_RCC_DBGMCU_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)
01395 #define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)
01396 #if defined(DAC1)
01397 #define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN)
01398 #endif /* DAC1 */
01399 #if defined(LPTIM1)
01400 #define __HAL_RCC_LPTIM1_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN)
01401 #endif /* LPTIM1 */
01402 #if defined(LPTIM2)
01403 #define __HAL_RCC_LPTIM2_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN)
01404 #endif /* LPTIM2 */
01405 #define __HAL_RCC_SYSCFG_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN)
01406 #define __HAL_RCC_TIM1_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)
01407 #define __HAL_RCC_SPI1_CLK_DISABLE()           CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN)
01408 #define __HAL_RCC_USART1_CLK_DISABLE()         CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN)
01409 #define __HAL_RCC_TIM14_CLK_DISABLE()          CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN)
01410 #if defined(TIM15)
01411 #define __HAL_RCC_TIM15_CLK_DISABLE()          CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN)
01412 #endif /* TIM15 */
01413 #define __HAL_RCC_TIM16_CLK_DISABLE()          CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN)
01414 #define __HAL_RCC_TIM17_CLK_DISABLE()          CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN)
01415 #define __HAL_RCC_ADC_CLK_DISABLE()            CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN)
01416
01417 /**
01418   * @}
01419   */
01420
01421 /** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status
01422   * @brief  Check whether the AHB peripheral clock is enabled or not.
01423   * @note   After reset, the peripheral clock (used for registers read/write access)
01424   *         is disabled and the application software has to enable this clock before
01425   *         using it.
01426   * @{
01427   */
01428
01429 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)  != RESET)
01430 #if defined(DMA2)
01431 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)  != RESET)
01432 #endif /* DMA2 */
01433 #define __HAL_RCC_FLASH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET)
01434 #define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)   != RESET)
01435 #if defined(RNG)
01436 #define __HAL_RCC_RNG_IS_CLK_ENABLED()         (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN)   != RESET)
01437 #endif /* RNG */
01438 #if defined(AES)
01439 #define __HAL_RCC_AES_IS_CLK_ENABLED()         (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN)   != RESET)
01440 #endif /* AES */
01441
01442 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)  == RESET)
01443 #if defined(DMA2)
01444 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)  == RESET)
01445 #endif /* DMA2 */
01446 #define __HAL_RCC_FLASH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET)
01447 #define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)   == RESET)
01448 #if defined(RNG)
01449 #define __HAL_RCC_RNG_IS_CLK_DISABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN)   == RESET)
01450 #endif /* RNG */
01451 #if defined(AES)
01452 #define __HAL_RCC_AES_IS_CLK_DISABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN)   == RESET)
01453 #endif /* AES */
01454 /**
01455   * @}
01456   */
01457
01458 /** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status
01459   * @brief  Check whether the IO Port clock is enabled or not.
01460   * @note   After reset, the peripheral clock (used for registers read/write access)
01461   *         is disabled and the application software has to enable this clock before
01462   *         using it.
01463   * @{
01464   */
01465 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
01466 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
01467 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
01468 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET)
01469 #if defined(GPIOE)
01470 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET)
01471 #endif /* GPIOE */
01472 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET)
01473
01474
01475 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET)
01476 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET)
01477 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET)
01478 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET)
01479 #if defined(GPIOE)
01480 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET)
01481 #endif /* GPIOE */
01482 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET)
01483
01484 /**
01485   * @}
01486   */
01487
01488 /** @defgroup RCC_APB1_Clock_Enabled_Disabled_Status APB1 Peripheral Clock Enabled or Disabled Status
01489   * @brief  Check whether the APB1 peripheral clock is enabled or not.
01490   * @note   After reset, the peripheral clock (used for registers read/write access)
01491   *         is disabled and the application software has to enable this clock before
01492   *         using it.
01493   * @{
01494   */
01495
01496 #if defined(TIM2)
01497 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)   != 0U)
01498 #endif /* TIM2 */
01499 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)   != 0U)
01500 #if defined(TIM4)
01501 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN)   != 0U)
01502 #endif /* TIM4 */
01503 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN)   != 0U)
01504 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN)   != 0U)
01505 #if defined(CRS)
01506 #define __HAL_RCC_CRS_IS_CLK_ENABLED()         (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN)    != 0U)
01507 #endif /* CRS */
01508 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U)
01509 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN)   != 0U)
01510 #if defined(FDCAN1) || defined(FDCAN2)
01511 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN)  != 0U)
01512 #endif /* FDCAN1 || FDCAN2 */
01513 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
01514 #define __HAL_RCC_USB_IS_CLK_ENABLED()         (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN)  != 0U)
01515 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
01516 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN)   != 0U)
01517 #if defined(SPI3)
01518 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN)   != 0U)
01519 #endif /* SPI3 */
01520 #define __HAL_RCC_USART2_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U)
01521 #define __HAL_RCC_USART3_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U)
01522 #define __HAL_RCC_USART4_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U)
01523 #if defined(USART5)
01524 #define __HAL_RCC_USART5_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U)
01525 #endif /* USART5 */
01526 #if defined(USART6)
01527 #define __HAL_RCC_USART6_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U)
01528 #endif /* USART6 */
01529 #if defined(LPUART1)
01530 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U)
01531 #endif /* LPUART1 */
01532 #if defined(LPUART2)
01533 #define __HAL_RCC_LPUART2_IS_CLK_ENABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U)
01534 #endif /* LPUART2 */
01535 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN)   != 0U)
01536 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN)   != 0U)
01537 #if defined(I2C3)
01538 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN)   != 0U)
01539 #endif /* I2C3 */
01540 #if defined(CEC)
01541 #define __HAL_RCC_CEC_IS_CLK_ENABLED()         (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN)    != 0U)
01542 #endif /* CEC */
01543 #if defined(UCPD1)
01544 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN)  != 0U)
01545 #endif /* UCPD1 */
01546 #if defined(UCPD2)
01547 #define __HAL_RCC_UCPD2_IS_CLK_ENABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN)  != 0U)
01548 #endif /* UCPD2 */
01549 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)    != 0U)
01550 #define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)    != 0U)
01551 #if defined(DAC1)
01552 #define __HAL_RCC_DAC1_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN)   != 0U)
01553 #endif /* DAC1 */
01554 #if defined(LPTIM2)
01555 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U)
01556 #endif /* LPTIM2 */
01557 #if defined(LPTIM1)
01558 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U)
01559 #endif /* LPTIM1 */
01560 #if defined(TIM2)
01561 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)   == 0U)
01562 #endif /* TIM2 */
01563 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)   == 0U)
01564 #if defined(TIM4)
01565 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN)   == 0U)
01566 #endif /* TIM4 */
01567 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN)   == 0U)
01568 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN)   == 0U)
01569 #if defined(CRS)
01570 #define __HAL_RCC_CRS_IS_CLK_DISABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN)    == 0U)
01571 #endif /* CRS */
01572 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U)
01573 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN)   == 0U)
01574 #if defined(FDCAN1) || defined(FDCAN2)
01575 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN)  == 0U)
01576 #endif /* FDCAN1 || FDCAN2 */
01577 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
01578 #define __HAL_RCC_USB_IS_CLK_DISABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN)  == 0U)
01579 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
01580 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN)   == 0U)
01581 #if defined(SPI3)
01582 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN)   == 0U)
01583 #endif /* SPI3 */
01584 #define __HAL_RCC_USART2_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U)
01585 #define __HAL_RCC_USART3_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U)
01586 #define __HAL_RCC_USART4_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U)
01587 #if defined(USART5)
01588 #define __HAL_RCC_USART5_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U)
01589 #endif /* USART5 */
01590 #if defined(USART6)
01591 #define __HAL_RCC_USART6_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U)
01592 #endif /* USART6 */
01593 #if defined(LPUART1)
01594 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED()    (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U)
01595 #endif /* LPUART1 */
01596 #if defined(LPUART2)
01597 #define __HAL_RCC_LPUART2_IS_CLK_DISABLED()    (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U)
01598 #endif /* LPUART2 */
01599 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN)   == 0U)
01600 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN)   == 0U)
01601 #if defined(I2C3)
01602 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN)   == 0U)
01603 #endif /* I2C3 */
01604 #if defined(CEC)
01605 #define __HAL_RCC_CEC_IS_CLK_DISABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN)    == 0U)
01606 #endif /* CEC */
01607 #if defined(UCPD1)
01608 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN)  == 0U)
01609 #endif /* UCPD1 */
01610 #if defined(UCPD2)
01611 #define __HAL_RCC_UCPD2_IS_CLK_DISABLED()      (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN)  == 0U)
01612 #endif /* UCPD2 */
01613 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)    == 0U)
01614 #define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)    == 0U)
01615 #if defined(DAC1)
01616 #define __HAL_RCC_DAC1_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN)   == 0U)
01617 #endif /* DAC1 */
01618 #if defined(LPTIM2)
01619 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U)
01620 #endif /* LPTIM2 */
01621 #if defined(LPTIM1)
01622 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U)
01623 #endif /* LPTIM1 */
01624
01625 /**
01626   * @}
01627   */
01628
01629 /** @defgroup RCC_APB2_Clock_Enabled_Disabled_Status APB2 Peripheral Clock Enabled or Disabled Status
01630   * @brief  Check whether the APB2 peripheral clock is enabled or not.
01631   * @note   After reset, the peripheral clock (used for registers read/write access)
01632   *         is disabled and the application software has to enable this clock before
01633   *         using it.
01634   * @{
01635   */
01636
01637 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U)
01638 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)   != 0U)
01639 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN)   != 0U)
01640 #define __HAL_RCC_USART1_IS_CLK_ENABLED()      (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U)
01641 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()       (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN)  != 0U)
01642 #if defined(TIM15)
01643 #define __HAL_RCC_TIM15_IS_CLK_ENABLED()       (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN)  != 0U)
01644 #endif /* TIM15 */
01645 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()       (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN)  != 0U)
01646 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()       (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN)  != 0U)
01647 #define __HAL_RCC_ADC_IS_CLK_ENABLED()         (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN)    != 0U)
01648
01649 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U)
01650 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)   == 0U)
01651 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN)   == 0U)
01652 #define __HAL_RCC_USART1_IS_CLK_DISABLED()     (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U)
01653 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()      (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN)  == 0U)
01654 #if defined(TIM15)
01655 #define __HAL_RCC_TIM15_IS_CLK_DISABLED()      (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN)  == 0U)
01656 #endif /* TIM15 */
01657 #define __HAL_RCC_TIM16_IS_CLK_DISABLED()      (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN)  == 0U)
01658 #define __HAL_RCC_TIM17_IS_CLK_DISABLED()      (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN)  == 0U)
01659 #define __HAL_RCC_ADC_IS_CLK_DISABLED()        (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN)    == 0U)
01660
01661 /**
01662   * @}
01663   */
01664
01665 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
01666   * @brief  Force or release AHB1 peripheral reset.
01667   * @{
01668   */
01669 #define __HAL_RCC_AHB_FORCE_RESET()            WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU)
01670 #define __HAL_RCC_DMA1_FORCE_RESET()           SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)
01671 #if defined(DMA2)
01672 #define __HAL_RCC_DMA2_FORCE_RESET()           SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)
01673 #endif /* DMA2 */
01674 #define __HAL_RCC_FLASH_FORCE_RESET()          SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
01675 #define __HAL_RCC_CRC_FORCE_RESET()            SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
01676 #if defined(RNG)
01677 #define __HAL_RCC_RNG_FORCE_RESET()            SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)
01678 #endif /* RNG */
01679 #if defined(AES)
01680 #define __HAL_RCC_AES_FORCE_RESET()            SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)
01681 #endif /* AES */
01682
01683 #define __HAL_RCC_AHB_RELEASE_RESET()          WRITE_REG(RCC->AHBRSTR, 0x00000000U)
01684 #define __HAL_RCC_DMA1_RELEASE_RESET()         CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)
01685 #if defined(DMA2)
01686 #define __HAL_RCC_DMA2_RELEASE_RESET()         CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)
01687 #endif /* DMA2 */
01688 #define __HAL_RCC_FLASH_RELEASE_RESET()        CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
01689 #define __HAL_RCC_CRC_RELEASE_RESET()          CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
01690 #if defined(RNG)
01691 #define __HAL_RCC_RNG_RELEASE_RESET()          CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)
01692 #endif /* RNG */
01693 #if defined(AES)
01694 #define __HAL_RCC_AES_RELEASE_RESET()          CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)
01695 #endif /* AES */
01696 /**
01697   * @}
01698   */
01699
01700 /** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset
01701   * @brief  Force or release IO Port reset.
01702   * @{
01703   */
01704 #define __HAL_RCC_IOP_FORCE_RESET()            WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU)
01705 #define __HAL_RCC_GPIOA_FORCE_RESET()          SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
01706 #define __HAL_RCC_GPIOB_FORCE_RESET()          SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
01707 #define __HAL_RCC_GPIOC_FORCE_RESET()          SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
01708 #define __HAL_RCC_GPIOD_FORCE_RESET()          SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)
01709 #if defined(GPIOE)
01710 #define __HAL_RCC_GPIOE_FORCE_RESET()          SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)
01711 #endif /* GPIOE */
01712 #define __HAL_RCC_GPIOF_FORCE_RESET()          SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)
01713
01714 #define __HAL_RCC_IOP_RELEASE_RESET()          WRITE_REG(RCC->IOPRSTR, 0x00000000U)
01715 #define __HAL_RCC_GPIOA_RELEASE_RESET()        CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
01716 #define __HAL_RCC_GPIOB_RELEASE_RESET()        CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
01717 #define __HAL_RCC_GPIOC_RELEASE_RESET()        CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
01718 #define __HAL_RCC_GPIOD_RELEASE_RESET()        CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)
01719 #if defined(GPIOE)
01720 #define __HAL_RCC_GPIOE_RELEASE_RESET()        CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)
01721 #endif /* GPIOE */
01722 #define __HAL_RCC_GPIOF_RELEASE_RESET()        CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)
01723
01724 /**
01725   * @}
01726   */
01727
01728 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
01729   * @brief  Force or release APB1 peripheral reset.
01730   * @{
01731   */
01732 #define __HAL_RCC_APB1_FORCE_RESET()           WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU)
01733
01734 #if defined(TIM2)
01735 #define __HAL_RCC_TIM2_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)
01736 #endif /* TIM2 */
01737 #define __HAL_RCC_TIM3_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)
01738 #if defined(TIM4)
01739 #define __HAL_RCC_TIM4_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)
01740 #endif /* TIM4 */
01741 #define __HAL_RCC_TIM6_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)
01742 #define __HAL_RCC_TIM7_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)
01743 #if defined(CRS)
01744 #define __HAL_RCC_CRS_FORCE_RESET()            SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)
01745 #endif /* CRS */
01746 #define __HAL_RCC_SPI2_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)
01747 #if defined(SPI3)
01748 #define __HAL_RCC_SPI3_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)
01749 #endif /* SPI3 */
01750 #define __HAL_RCC_USART2_FORCE_RESET()         SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)
01751 #define __HAL_RCC_USART3_FORCE_RESET()         SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)
01752 #define __HAL_RCC_USART4_FORCE_RESET()         SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)
01753 #if defined(USART5)
01754 #define __HAL_RCC_USART5_FORCE_RESET()         SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)
01755 #endif /* USART5 */
01756 #if defined(USART6)
01757 #define __HAL_RCC_USART6_FORCE_RESET()         SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)
01758 #endif /* USART6 */
01759 #if defined(LPUART1)
01760 #define __HAL_RCC_LPUART1_FORCE_RESET()        SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)
01761 #endif /* LPUART1 */
01762 #if defined(LPUART2)
01763 #define __HAL_RCC_LPUART2_FORCE_RESET()        SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)
01764 #endif /* LPUART2 */
01765 #define __HAL_RCC_I2C1_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)
01766 #define __HAL_RCC_I2C2_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)
01767 #if defined(I2C3)
01768 #define __HAL_RCC_I2C3_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)
01769 #endif /* I2C3 */
01770 #if defined(CEC)
01771 #define __HAL_RCC_CEC_FORCE_RESET()            SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)
01772 #endif /* CEC */
01773 #if defined(UCPD1)
01774 #define __HAL_RCC_UCPD1_FORCE_RESET()          SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)
01775 #endif /* UCPD1 */
01776 #if defined(UCPD2)
01777 #define __HAL_RCC_UCPD2_FORCE_RESET()          SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)
01778 #endif /* UCPD2 */
01779 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
01780 #define __HAL_RCC_USB_FORCE_RESET()            SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)
01781 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
01782 #if defined(FDCAN1) || defined(FDCAN2)
01783 #define __HAL_RCC_FDCAN_FORCE_RESET()          SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)
01784 #endif /* FDCAN1 || FDCAN2 */
01785 #define __HAL_RCC_DBGMCU_FORCE_RESET()         SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
01786 #define __HAL_RCC_PWR_FORCE_RESET()            SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
01787 #if defined(DAC1)
01788 #define __HAL_RCC_DAC1_FORCE_RESET()           SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)
01789 #endif /* DAC1 */
01790 #if defined(LPTIM2)
01791 #define __HAL_RCC_LPTIM2_FORCE_RESET()         SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)
01792 #endif /* LPTIM2 */
01793 #if defined(LPTIM1)
01794 #define __HAL_RCC_LPTIM1_FORCE_RESET()         SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)
01795 #endif /* LPTIM1 */
01796 #define __HAL_RCC_APB1_RELEASE_RESET()         WRITE_REG(RCC->APBRSTR1, 0x00000000U)
01797 #if defined(TIM2)
01798 #define __HAL_RCC_TIM2_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)
01799 #endif /* TIM2 */
01800 #define __HAL_RCC_TIM3_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)
01801 #if defined(TIM4)
01802 #define __HAL_RCC_TIM4_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)
01803 #endif /* TIM4 */
01804 #define __HAL_RCC_TIM6_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)
01805 #define __HAL_RCC_TIM7_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)
01806 #if defined(CRS)
01807 #define __HAL_RCC_CRS_RELEASE_RESET()          CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)
01808 #endif /* CRS */
01809 #define __HAL_RCC_SPI2_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)
01810 #if defined(SPI3)
01811 #define __HAL_RCC_SPI3_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)
01812 #endif /* SPI3 */
01813 #define __HAL_RCC_USART2_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)
01814 #define __HAL_RCC_USART3_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)
01815 #define __HAL_RCC_USART4_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)
01816 #if defined(USART5)
01817 #define __HAL_RCC_USART5_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)
01818 #endif /* USART5 */
01819 #if defined(USART6)
01820 #define __HAL_RCC_USART6_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)
01821 #endif /* USART6 */
01822 #if defined(LPUART1)
01823 #define __HAL_RCC_LPUART1_RELEASE_RESET()      CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)
01824 #endif /* LPUART1 */
01825 #if defined(LPUART2)
01826 #define __HAL_RCC_LPUART2_RELEASE_RESET()      CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)
01827 #endif /* LPUART2 */
01828 #define __HAL_RCC_I2C1_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)
01829 #define __HAL_RCC_I2C2_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)
01830 #if defined(I2C3)
01831 #define __HAL_RCC_I2C3_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)
01832 #endif /* I2C3 */
01833 #if defined(CEC)
01834 #define __HAL_RCC_CEC_RELEASE_RESET()          CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)
01835 #endif /* CEC */
01836 #if defined(UCPD1)
01837 #define __HAL_RCC_UCPD1_RELEASE_RESET()        CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)
01838 #endif /* UCPD1 */
01839 #if defined(UCPD2)
01840 #define __HAL_RCC_UCPD2_RELEASE_RESET()        CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)
01841 #endif /* UCPD2 */
01842 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
01843 #define __HAL_RCC_USB_RELEASE_RESET()          CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)
01844 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
01845 #if defined(FDCAN1) || defined(FDCAN2)
01846 #define __HAL_RCC_FDCAN_RELEASE_RESET()        CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)
01847 #endif /* FDCAN1 || FDCAN2 */
01848 #define __HAL_RCC_DBGMCU_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
01849 #define __HAL_RCC_PWR_RELEASE_RESET()          CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
01850 #if defined(DAC1)
01851 #define __HAL_RCC_DAC1_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)
01852 #endif /* DAC1 */
01853 #if defined(LPTIM2)
01854 #define __HAL_RCC_LPTIM2_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)
01855 #endif /* LPTIM2 */
01856 #if defined(LPTIM1)
01857 #define __HAL_RCC_LPTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)
01858 #endif /* LPTIM1 */
01859 /**
01860   * @}
01861   */
01862
01863 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
01864   * @brief  Force or release APB2 peripheral reset.
01865   * @{
01866   */
01867 #define __HAL_RCC_APB2_FORCE_RESET()           WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU)
01868 #define __HAL_RCC_SYSCFG_FORCE_RESET()         SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
01869 #define __HAL_RCC_TIM1_FORCE_RESET()           SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
01870 #define __HAL_RCC_SPI1_FORCE_RESET()           SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
01871 #define __HAL_RCC_USART1_FORCE_RESET()         SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
01872 #define __HAL_RCC_TIM14_FORCE_RESET()          SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
01873 #if defined(TIM15)
01874 #define __HAL_RCC_TIM15_FORCE_RESET()          SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)
01875 #endif /* TIM15 */
01876 #define __HAL_RCC_TIM16_FORCE_RESET()          SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)
01877 #define __HAL_RCC_TIM17_FORCE_RESET()          SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)
01878 #define __HAL_RCC_ADC_FORCE_RESET()            SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
01879
01880 #define __HAL_RCC_APB2_RELEASE_RESET()         WRITE_REG(RCC->APBRSTR2, 0x00U)
01881 #define __HAL_RCC_SYSCFG_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
01882 #define __HAL_RCC_TIM1_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
01883 #define __HAL_RCC_SPI1_RELEASE_RESET()         CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
01884 #define __HAL_RCC_USART1_RELEASE_RESET()       CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
01885 #define __HAL_RCC_TIM14_RELEASE_RESET()        CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
01886 #if defined(TIM15)
01887 #define __HAL_RCC_TIM15_RELEASE_RESET()        CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)
01888 #endif /* TIM15 */
01889 #define __HAL_RCC_TIM16_RELEASE_RESET()        CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)
01890 #define __HAL_RCC_TIM17_RELEASE_RESET()        CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)
01891 #define __HAL_RCC_ADC_RELEASE_RESET()          CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
01892
01893 /**
01894   * @}
01895   */
01896
01897 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripherals Clock Sleep Enable Disable
01898   * @brief  Enable or disable the AHB peripherals clock during Low Power (Sleep) mode.
01899   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01900   *         power consumption.
01901   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01902   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01903   * @{
01904   */
01905
01906 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
01907 #if defined(DMA2)
01908 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
01909 #endif /* DMA2 */
01910 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
01911 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
01912 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
01913 #if defined(RNG)
01914 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
01915 #endif /* RNG */
01916 #if defined(AES)
01917 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
01918 #endif /* AES */
01919 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
01920 #if defined(DMA2)
01921 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
01922 #endif /* DMA2 */
01923 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
01924 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
01925 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
01926 #if defined(RNG)
01927 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
01928 #endif /* RNG */
01929 #if defined(AES)
01930 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
01931 #endif /* AES */
01932
01933 /**
01934   * @}
01935   */
01936
01937 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable
01938   * @brief  Enable or disable the IOPORT clock during Low Power (Sleep) mode.
01939   * @note   IOPORT clock gating in SLEEP mode can be used to further reduce
01940   *         power consumption.
01941   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01942   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01943   * @{
01944   */
01945
01946 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)
01947 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)
01948 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)
01949 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)
01950 #if defined(GPIOE)
01951 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)
01952 #endif /* GPIOE */
01953 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()     SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)
01954
01955 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)
01956 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)
01957 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)
01958 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)
01959 #if defined(GPIOE)
01960 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)
01961 #endif /* GPIOE */
01962 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)
01963 /**
01964   *   @}
01965   */
01966
01967 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
01968   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
01969   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01970   *         power consumption.
01971   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01972   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01973   * @{
01974   */
01975 #if defined(TIM2)
01976 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
01977 #endif /* TIM2 */
01978 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
01979 #if defined(TIM4)
01980 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
01981 #endif /* TIM4 */
01982 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
01983 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
01984 #if defined(CRS)
01985 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
01986 #endif /* CRS */
01987 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
01988 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
01989 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
01990 #if defined(SPI3)
01991 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
01992 #endif /* SPI3 */
01993 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
01994 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)
01995 #define __HAL_RCC_USART4_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)
01996 #if defined(USART5)
01997 #define __HAL_RCC_USART5_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)
01998 #endif /* USART5 */
01999 #if defined(USART6)
02000 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)
02001 #endif /* USART6 */
02002 #if defined(LPUART1)
02003 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)
02004 #endif /* LPUART1 */
02005 #if defined(LPUART2)
02006 #define __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)
02007 #endif /* LPUART2 */
02008 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
02009 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
02010 #if defined(I2C3)
02011 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)
02012 #endif /* I2C3 */
02013 #if defined(CEC)
02014 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)
02015 #endif /* CEC */
02016 #if defined(UCPD1)
02017 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)
02018 #endif /* UCPD1 */
02019 #if defined(UCPD2)
02020 #define __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)
02021 #endif /* UCPD2 */
02022 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
02023 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
02024 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
02025 #if defined(FDCAN1) || defined(FDCAN2)
02026 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)
02027 #endif /* FDCAN1 || FDCAN2 */
02028 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)
02029 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)
02030 #if defined(DAC1)
02031 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)
02032 #endif /* DAC1 */
02033 #if defined(LPTIM2)
02034 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)
02035 #endif /* LPTIM2 */
02036 #if defined(LPTIM1)
02037 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)
02038 #endif /* LPTIM1 */
02039 #if defined(TIM2)
02040 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
02041 #endif /* TIM2 */
02042 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
02043 #if defined(TIM4)
02044 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
02045 #endif /* TIM4 */
02046 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
02047 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
02048 #if defined(CRS)
02049 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
02050 #endif /* CRS */
02051 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
02052 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
02053 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
02054 #if defined(SPI3)
02055 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
02056 #endif /* TIM2 */
02057 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
02058 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)
02059 #define __HAL_RCC_USART4_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)
02060 #if defined(USART5)
02061 #define __HAL_RCC_USART5_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)
02062 #endif /* USART5 */
02063 #if defined(USART6)
02064 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)
02065 #endif /* USART6 */
02066 #if defined(LPUART1)
02067 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)
02068 #endif /* LPUART1 */
02069 #if defined(LPUART2)
02070 #define __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)
02071 #endif /* LPUART2 */
02072 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
02073 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
02074 #if defined(I2C3)
02075 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)
02076 #endif /* I2C3 */
02077 #if defined(CEC)
02078 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)
02079 #endif /* CEC */
02080 #if defined(UCPD1)
02081 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)
02082 #endif /* UCPD1 */
02083 #if defined(UCPD2)
02084 #define __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)
02085 #endif /* UCPD2 */
02086 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
02087 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
02088 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
02089 #if defined(FDCAN1) || defined(FDCAN2)
02090 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)
02091 #endif /* FDCAN1) || FDCAN2 */
02092 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)
02093 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)
02094 #if defined(DAC1)
02095 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)
02096 #endif /* DAC1 */
02097 #if defined(LPTIM2)
02098 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)
02099 #endif /* LPTIM2 */
02100 #if defined(LPTIM1)
02101 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)
02102 #endif /* LPTIM1 */
02103 /**
02104   * @}
02105   */
02106
02107 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
02108   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
02109   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02110   *         power consumption.
02111   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02112   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02113   * @{
02114   */
02115
02116 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)
02117 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)
02118 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)
02119 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)
02120 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)
02121 #if defined(TIM15)
02122 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)
02123 #endif /* TIM15 */
02124 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)
02125 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)
02126 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)
02127
02128 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)
02129 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)
02130 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)
02131 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)
02132 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)
02133 #if defined(TIM15)
02134 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)
02135 #endif /* TIM15 */
02136 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)
02137 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)
02138 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)
02139
02140 /**
02141   * @}
02142   */
02143
02144 /** @defgroup RCC_AHB_Clock_Sleep_Enabled_Disabled_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
02145   * @brief  Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
02146   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02147   *         power consumption.
02148   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02149   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02150   * @{
02151   */
02152
02153 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
02154 #if defined(DMA2)
02155 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) != RESET)
02156 #endif /* DMA2 */
02157 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET)
02158 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
02159 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)  != RESET)
02160 #if defined(RNG)
02161 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)  != RESET)
02162 #endif /* RNG */
02163 #if defined(AES)
02164 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)  != RESET)
02165 #endif /* AES */
02166 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)  == RESET)
02167 #if defined(DMA2)
02168 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)  == RESET)
02169 #endif /* DMA2 */
02170 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET)
02171 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)  == RESET)
02172 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)   == RESET)
02173 #if defined(RNG)
02174 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)   == RESET)
02175 #endif /* RNG */
02176 #if defined(AES)
02177 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)   == RESET)
02178 #endif /* AES */
02179
02180 /**
02181   * @}
02182   */
02183
02184 /** @defgroup RCC_IOPORT_Clock_Sleep_Enabled_Disabled_Status IOPORT Clock Sleep Enabled or Disabled Status
02185   * @brief  Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not.
02186   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02187   *         power consumption.
02188   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02189   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02190   * @{
02191   */
02192
02193
02194 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET)
02195 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET)
02196 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET)
02197 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET)
02198 #if defined(GPIOE)
02199 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)!= RESET)
02200 #endif /* GPIOE */
02201 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET)
02202
02203
02204
02205 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET)
02206 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET)
02207 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET)
02208 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET)
02209 #if defined(GPIOE)
02210 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET)
02211 #endif /* GPIOE */
02212 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET)
02213
02214 /**
02215   * @}
02216   */
02217
02218 /** @defgroup RCC_APB1_Clock_Sleep_Enabled_Disabled_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
02219   * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
02220   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02221   *         power consumption.
02222   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02223   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02224   * @{
02225   */
02226 #if defined(TIM2)
02227 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)   != RESET)
02228 #endif /* TIM2 */
02229 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)   != RESET)
02230 #if defined(TIM4)
02231 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)   != RESET)
02232 #endif /* TIM4 */
02233 #if defined(TIM6)
02234 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)   != RESET)
02235 #endif /* TIM6 */
02236 #if defined(TIM7)
02237 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)   != RESET)
02238 #endif /* TIM7 */
02239 #if defined(CRS)
02240 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)    != RESET)
02241 #endif /* CRS */
02242 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET)
02243 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)   != RESET)
02244 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)   != RESET)
02245 #if defined(SPI3)
02246 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)   != RESET)
02247 #endif /* SPI3 */
02248 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET)
02249 #if defined(USART3)
02250 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET)
02251 #endif /* USART3 */
02252 #if defined(USART4)
02253 #define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET)
02254 #endif /* USART4 */
02255 #if defined(USART5)
02256 #define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) != RESET)
02257 #endif /* USART5 */
02258 #if defined(USART6)
02259 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) != RESET)
02260 #endif /* USART6 */
02261 #if defined(LPUART1)
02262 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)!= RESET)
02263 #endif /* LPUART1 */
02264 #if defined(LPUART2)
02265 #define __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)!= RESET)
02266 #endif /* LPUART2 */
02267 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)   != RESET)
02268 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)   != RESET)
02269 #if defined(I2C3)
02270 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)   != RESET)
02271 #endif /* I2C3 */
02272 #if defined(CEC)
02273 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)    != RESET)
02274 #endif /* CEC */
02275 #if defined(UCPD1)
02276 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)  != RESET)
02277 #endif /* UCPD1 */
02278 #if defined(UCPD2)
02279 #define __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)  != RESET)
02280 #endif /* UCPD2 */
02281 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
02282 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)  != RESET)
02283 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
02284 #if defined(FDCAN1) || defined(FDCAN2)
02285 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)  != RESET)
02286 #endif /* FDCAN1 || FDCAN2 */
02287 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)    != RESET)
02288 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)    != RESET)
02289 #if defined(DAC1)
02290 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)   != RESET)
02291 #endif /* DAC1 */
02292 #if defined(LPTIM2)
02293 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) != RESET)
02294 #endif /* LPTIM2 */
02295 #if defined(LPTIM1)
02296 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) != RESET)
02297 #endif /* LPTIM1 */
02298 #if defined(TIM2)
02299 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)   == RESET)
02300 #endif /* TIM2 */
02301 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)   == RESET)
02302 #if defined(TIM4)
02303 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)   == RESET)
02304 #endif /* TIM4 */
02305 #if defined(TIM6)
02306 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)   == RESET)
02307 #endif /* TIM6 */
02308 #if defined(TIM7)
02309 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)   == RESET)
02310 #endif /* TIM7 */
02311 #if defined(CRS)
02312 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)    == RESET)
02313 #endif /* CRS */
02314 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET)
02315 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)   == RESET)
02316 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)   == RESET)
02317 #if defined(SPI3)
02318 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)   == RESET)
02319 #endif /* SPI3 */
02320 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET)
02321 #if defined(USART3)
02322 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET)
02323 #endif /* USART3 */
02324 #if defined(USART4)
02325 #define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET)
02326 #endif /* USART4 */
02327 #if defined(USART5)
02328 #define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) == RESET)
02329 #endif /* USART5 */
02330 #if defined(USART6)
02331 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) == RESET)
02332 #endif /* USART6 */
02333 #if defined(LPUART1)
02334 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)== RESET)
02335 #endif /* LPUART1 */
02336 #if defined(LPUART2)
02337 #define __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)== RESET)
02338 #endif /* LPUART2 */
02339 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)   == RESET)
02340 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)   == RESET)
02341 #if defined(I2C3)
02342 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)   == RESET)
02343 #endif /* I2C3 */
02344 #if defined(CEC)
02345 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)    == RESET)
02346 #endif /* CEC */
02347 #if defined(UCPD1)
02348 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)  == RESET)
02349 #endif /* UCPD1 */
02350 #if defined(UCPD2)
02351 #define __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)  == RESET)
02352 #endif /* UCPD2 */
02353 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
02354 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)  == RESET)
02355 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
02356 #if defined(FDCAN1) || defined(FDCAN2)
02357 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)  == RESET)
02358 #endif /* FDCAN1 || FDCAN2 */
02359 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)    == RESET)
02360 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)    == RESET)
02361 #if defined(DAC1)
02362 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)   == RESET)
02363 #endif /* DAC1 */
02364 #if defined(LPTIM2)
02365 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) == RESET)
02366 #endif /* LPTIM2 */
02367 #if defined(LPTIM1)
02368 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) == RESET)
02369 #endif /* LPTIM1 */
02370
02371 /**
02372   * @}
02373   */
02374
02375 /** @defgroup RCC_APB2_Clock_Sleep_Enabled_Disabled_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
02376   * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
02377   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02378   *         power consumption.
02379   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02380   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02381   * @{
02382   */
02383
02384 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET)
02385 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)   != RESET)
02386 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)   != RESET)
02387 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET)
02388 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)  != RESET)
02389 #if defined(TIM15)
02390 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)  != RESET)
02391 #endif /* TIM15 */
02392 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)  != RESET)
02393 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)  != RESET)
02394 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)    != RESET)
02395
02396
02397 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET)
02398 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)   == RESET)
02399 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)   == RESET)
02400 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET)
02401 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)  == RESET)
02402 #if defined(TIM15)
02403 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)  == RESET)
02404 #endif /* TIM15 */
02405 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)  == RESET)
02406 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)  == RESET)
02407 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)    == RESET)
02408
02409
02410 /**
02411   * @}
02412   */
02413
02414 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
02415   * @{
02416   */
02417
02418 /** @brief  Macros to force or release the Backup domain reset.
02419   * @note   This function resets the RTC peripheral (including the backup registers)
02420   *         and the RTC clock source selection in RCC_CSR register.
02421   * @note   The BKPSRAM is not affected by this reset.
02422   * @retval None
02423   */
02424 #define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
02425
02426 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
02427
02428 /**
02429   * @}
02430   */
02431
02432 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
02433   * @{
02434   */
02435
02436 /** @brief  Macros to enable or disable the RTC clock.
02437   * @note   As the RTC is in the Backup domain and write access is denied to
02438   *         this domain after reset, you have to enable write access using
02439   *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC
02440   *         (to be done once after reset).
02441   * @note   These macros must be used after the RTC clock source was selected.
02442   * @retval None
02443   */
02444 #define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
02445
02446 #define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
02447
02448 /**
02449   * @}
02450   */
02451
02452 /** @defgroup RCC_Clock_Configuration RCC Clock Configuration
02453   * @{
02454   */
02455
02456 /** @brief  Macros to enable the Internal High Speed oscillator (HSI).
02457   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
02458   *         It is used (enabled by hardware) as system clock source after startup
02459   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
02460   *         of the HSE used directly or indirectly as system clock (if the Clock
02461   *         Security System CSS is enabled).
02462   * @note   After enabling the HSI, the application software should wait on HSIRDY
02463   *         flag to be set indicating that HSI clock is stable and can be used as
02464   *         system clock source.
02465   *         This parameter can be: ENABLE or DISABLE.
02466   * @retval None
02467   */
02468 #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
02469
02470 /** @brief  Macros to disable the Internal High Speed oscillator (HSI).
02471   * @note   HSI can not be stopped if it is used as system clock source. In this case,
02472   *         you have to select another source of the system clock then stop the HSI.
02473   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
02474   *         clock cycles.
02475   * @retval None
02476   */
02477 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
02478
02479 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
02480   * @note   The calibration is used to compensate for the variations in voltage
02481   *         and temperature that influence the frequency of the internal HSI RC.
02482   * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value
02483   *         (default is RCC_HSICALIBRATION_DEFAULT).
02484   *         This parameter must be a number between 0 and 127.
02485   * @retval None
02486   */
02487 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
02488   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
02489
02490 /**
02491   * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
02492   *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
02493   * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
02494   *           speed because of the HSI startup time.
02495   * @note     The enable of this function has not effect on the HSION bit.
02496   *           This parameter can be: ENABLE or DISABLE.
02497   * @retval None
02498   */
02499 #define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
02500
02501 #define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
02502
02503 /** @brief  Macro to configure the HSISYS clock.
02504   * @param  __HSIDIV__ specifies the HSI16 division factor.
02505   *          This parameter can be one of the following values:
02506   *            @arg @ref RCC_HSI_DIV1   HSI clock source is divided by 1
02507   *            @arg @ref RCC_HSI_DIV2   HSI clock source is divided by 2
02508   *            @arg @ref RCC_HSI_DIV4   HSI clock source is divided by 4
02509   *            @arg @ref RCC_HSI_DIV8   HSI clock source is divided by 8
02510   *            @arg @ref RCC_HSI_DIV16  HSI clock source is divided by 16
02511   *            @arg @ref RCC_HSI_DIV32  HSI clock source is divided by 32
02512   *            @arg @ref RCC_HSI_DIV64  HSI clock source is divided by 64
02513   *            @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128
02514   */
02515 #define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \
02516   MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__))
02517
02518 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
02519   * @note   After enabling the LSI, the application software should wait on
02520   *         LSIRDY flag to be set indicating that LSI clock is stable and can
02521   *         be used to clock the IWDG and/or the RTC.
02522   * @note   LSI can not be disabled if the IWDG is running.
02523   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
02524   *         clock cycles.
02525   * @retval None
02526   */
02527 #define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
02528
02529 #define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
02530
02531 /**
02532   * @brief  Macro to configure the External High Speed oscillator (HSE).
02533   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
02534   *         supported by this macro. User should request a transition to HSE Off
02535   *         first and then HSE On or HSE Bypass.
02536   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
02537   *         software should wait on HSERDY flag to be set indicating that HSE clock
02538   *         is stable and can be used to clock the PLL and/or system clock.
02539   * @note   HSE state can not be changed if it is used directly or through the
02540   *         PLL as system clock. In this case, you have to select another source
02541   *         of the system clock then change the HSE state (ex. disable it).
02542   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
02543   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
02544   *         was previously enabled you have to enable it again after calling this
02545   *         function.
02546   * @param  __STATE__  specifies the new state of the HSE.
02547   *         This parameter can be one of the following values:
02548   *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after
02549   *                              6 HSE oscillator clock cycles.
02550   *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
02551   *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.
02552   * @retval None
02553   */
02554 #define __HAL_RCC_HSE_CONFIG(__STATE__)  do {                                        \
02555                                               if((__STATE__) == RCC_HSE_ON)          \
02556                                               {                                      \
02557                                                 SET_BIT(RCC->CR, RCC_CR_HSEON);      \
02558                                               }                                      \
02559                                               else if((__STATE__) == RCC_HSE_BYPASS) \
02560                                               {                                      \
02561                                                 SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
02562                                                 SET_BIT(RCC->CR, RCC_CR_HSEON);      \
02563                                               }                                      \
02564                                               else                                   \
02565                                               {                                      \
02566                                                 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
02567                                                 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
02568                                               }                                      \
02569                                             } while(0U)
02570
02571 /**
02572   * @brief  Macro to configure the External Low Speed oscillator (LSE).
02573   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
02574   *         supported by this macro. User should request a transition to LSE Off
02575   *         first and then LSE On or LSE Bypass.
02576   * @note   As the LSE is in the Backup domain and write access is denied to
02577   *         this domain after reset, you have to enable write access using
02578   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
02579   *         (to be done once after reset).
02580   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
02581   *         software should wait on LSERDY flag to be set indicating that LSE clock
02582   *         is stable and can be used to clock the RTC.
02583   * @param  __STATE__  specifies the new state of the LSE.
02584   *         This parameter can be one of the following values:
02585   *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after
02586   *                              6 LSE oscillator clock cycles.
02587   *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
02588   *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.
02589   * @retval None
02590   */
02591 #define __HAL_RCC_LSE_CONFIG(__STATE__)  do {                                          \
02592                                               if((__STATE__) == RCC_LSE_ON)            \
02593                                               {                                        \
02594                                                 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
02595                                               }                                        \
02596                                               else if((__STATE__) == RCC_LSE_BYPASS)   \
02597                                               {                                        \
02598                                                 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
02599                                                 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
02600                                               }                                        \
02601                                               else                                     \
02602                                               {                                        \
02603                                                 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
02604                                                 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
02605                                               }                                        \
02606                                             } while(0U)
02607
02608 #if defined(RCC_HSI48_SUPPORT)
02609 /** @brief  Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
02610   * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
02611   * @note   After enabling the HSI48, the application software should wait on HSI48RDY
02612   *         flag to be set indicating that HSI48 clock is stable.
02613   *         This parameter can be: ENABLE or DISABLE.
02614   * @retval None
02615   */
02616 #define __HAL_RCC_HSI48_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSI48ON)
02617
02618 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON)
02619
02620 #endif /* RCC_HSI48_SUPPORT */
02621
02622 /**
02623   * @}
02624   */
02625
02626 /** @addtogroup RCC_RTC_Clock_Configuration
02627   * @{
02628   */
02629
02630 /** @brief  Macros to configure the RTC clock (RTCCLK).
02631   * @note   As the RTC clock configuration bits are in the Backup domain and write
02632   *         access is denied to this domain after reset, you have to enable write
02633   *         access using the Power Backup Access macro before to configure
02634   *         the RTC clock source (to be done once after reset).
02635   * @note   Once the RTC clock is configured it cannot be changed unless the
02636   *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
02637   *         a Power On Reset (POR).
02638   *
02639   * @param  __RTC_CLKSOURCE__  specifies the RTC clock source.
02640   *         This parameter can be one of the following values:
02641   *            @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
02642   *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
02643   *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
02644   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
02645   *
02646   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
02647   *         work in STOP and STANDBY modes, and can be used as wakeup source.
02648   *         However, when the HSE clock is used as RTC clock source, the RTC
02649   *         cannot be used in STOP and STANDBY modes.
02650   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
02651   *         RTC clock source).
02652   * @retval None
02653   */
02654 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  \
02655   MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
02656
02657
02658 /** @brief Macro to get the RTC clock source.
02659   * @retval The returned value can be one of the following:
02660   *            @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
02661   *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
02662   *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
02663   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
02664   */
02665 #define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
02666
02667 /** @brief  Macros to enable or disable the main PLL.
02668   * @note   After enabling the main PLL, the application software should wait on
02669   *         PLLRDY flag to be set indicating that PLL clock is stable and can
02670   *         be used as system clock source.
02671   * @note   The main PLL can not be disabled if it is used as system clock source
02672   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
02673   * @retval None
02674   */
02675
02676 /**
02677   * @}
02678   */
02679
02680 /** @addtogroup RCC_Clock_Configuration
02681   * @{
02682   */
02683
02684 #define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLLON)
02685
02686 #define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
02687
02688 /** @brief  Macro to configure the PLL clock source.
02689   * @note   This function must be used only when the main PLL is disabled.
02690   * @param  __PLLSOURCE__  specifies the PLL entry clock source.
02691   *         This parameter can be one of the following values:
02692   *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
02693   *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
02694   *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
02695   * @retval None
02696   *
02697   */
02698 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
02699   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
02700
02701 /** @brief  Macro to configure the PLL multiplication factor.
02702   * @note   This function must be used only when the main PLL is disabled.
02703   * @param  __PLLM__  specifies the division factor for PLL VCO input clock
02704   *         This parameter must be a value of RCC_PLLM_Clock_Divider.
02705   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02706   *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
02707   *         of 16 MHz to limit PLL jitter.
02708   * @retval None
02709   *
02710   */
02711 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
02712   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
02713
02714 /**
02715   * @brief  Macro to configure the main PLL clock source, multiplication and division factors.
02716   * @note   This function must be used only when the main PLL is disabled.
02717   *
02718   * @param  __PLLSOURCE__  specifies the PLL entry clock source.
02719   *         This parameter can be one of the following values:
02720   *           @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
02721   *           @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
02722   *           @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
02723   *
02724   * @param  __PLLM__  specifies the division factor for PLL VCO input clock.
02725   *         This parameter must be a value of RCC_PLLM_Clock_Divider.
02726   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02727   *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
02728   *         of 16 MHz to limit PLL jitter.
02729   *
02730   * @param  __PLLN__  specifies the multiplication factor for PLL VCO output clock.
02731   *         This parameter must be a number between 8 and 86.
02732   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
02733   *         output frequency is between 64 and 344 MHz.
02734   *
02735   * @param  __PLLP__  specifies the division factor for ADC clock.
02736   *         This parameter must be a value of @ref RCC_PLLP_Clock_Divider.
02737   *
02738   * @param  __PLLQ__  specifies the division factor for RBG & HS Timers clocks.(1)
02739   *         This parameter must be a value of @ref RCC_PLLQ_Clock_Divider
02740   * @note   (1)__PLLQ__ parameter availability depends on devices
02741   * @note   If the USB FS is used in your application, you have to set the
02742   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
02743   *         the RNG needs a frequency lower than or equal to 48 MHz to work
02744   *         correctly.
02745   *
02746   * @param  __PLLR__  specifies the division factor for the main system clock.
02747   *         This parameter must be a value of RCC_PLLR_Clock_Divider
02748   * @note   You have to set the PLL parameters correctly to not exceed 64MHZ.
02749   * @retval None
02750   */
02751 #if defined(RCC_PLLQ_SUPPORT)
02752 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
02753   MODIFY_REG(RCC->PLLCFGR,                                                   \
02754              (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |     \
02755               RCC_PLLCFGR_PLLP   | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR),     \
02756              ((uint32_t) (__PLLSOURCE__)                      |             \
02757               (uint32_t) (__PLLM__)                           |             \
02758               (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) |             \
02759               (uint32_t) (__PLLP__)                           |             \
02760               (uint32_t) (__PLLQ__)                           |             \
02761               (uint32_t) (__PLLR__)))
02762 #else
02763 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \
02764   MODIFY_REG(RCC->PLLCFGR,                                                   \
02765              (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |     \
02766               RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLR),                          \
02767              ((uint32_t) (__PLLSOURCE__)                     |              \
02768               (uint32_t) (__PLLM__)                           |              \
02769               (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) |              \
02770               (uint32_t) (__PLLP__)                           |              \
02771               (uint32_t) (__PLLR__)))
02772 #endif /* RCC_PLLQ_SUPPORT */
02773 /** @brief  Macro to get the oscillator used as PLL clock source.
02774   * @retval The oscillator used as PLL clock source. The returned value can be one
02775   *         of the following:
02776   *              @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source.
02777   *              @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source.
02778   *              @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source.
02779   */
02780 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
02781
02782 /**
02783   * @brief  Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
02784   * @note   Enabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime
02785   *         without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot
02786   *         be stopped if used as System Clock.
02787   * @note   (*) RCC_PLLQCLK availability depends on devices
02788   * @param  __PLLCLOCKOUT__ specifies the PLL clock to be output.
02789   *          This parameter can be one or a combination of the following values:
02790   *            @arg @ref RCC_PLLPCLK  This clock is used to generate the clock for the ADC.
02791   * @if defined(STM32G081xx)
02792   *            @arg @ref RCC_PLLQCLK  This Clock is used to generate the clock for the High Speed Timers,
02793   *                                  and the random analog generator (<=48 MHz).
02794   * @endif
02795   *            @arg @ref RCC_PLLRCLK  This Clock is used to generate the high speed system clock (up to 64MHz)
02796   * @retval None
02797   */
02798 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
02799
02800 /**
02801   * @brief  Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
02802   * @note   Disabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime
02803   *         without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot
02804   *         be stopped if used as System Clock.
02805   * @note   (*) RCC_PLLQCLK availability depends on devices
02806   * @param  __PLLCLOCKOUT__  specifies the PLL clock to be output.
02807   *          This parameter can be one or a combination of the following values:
02808   *            @arg @ref RCC_PLLPCLK  This clock may be used to generate the clock for the ADC, I2S1.
02809   * @if defined(STM32G081xx)
02810   *            @arg @ref RCC_PLLQCLK This Clock may be used to generate the clock for the High Speed Timers,
02811   *             and RNG (<=48 MHz).
02812   * @endif
02813   *            @arg @ref RCC_PLLRCLK  This Clock is used to generate the high speed system clock (up to 64MHz)
02814   * @retval None
02815   */
02816 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
02817
02818 /**
02819   * @brief  Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
02820   * @param  __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
02821   *          This parameter can be one of the following values:
02822   *            @arg RCC_PLLPCLK This clock may be used to generate the clock for ADC, I2S1.
02823   * @if defined(STM32G081xx)
02824   *            @arg RCC_PLLQCLK This Clock may be used to generate the clock for the HS Timers,
02825   *                                   the RNG (<=48 MHz).
02826   * @endif
02827   *            @arg @ref RCC_PLLRCLK  This Clock is used to generate the high speed system clock (up to 64MHz)
02828   * @retval SET / RESET
02829   * @note   (*) RCC_PLLQCLK availability depends on devices
02830   */
02831 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
02832
02833 /**
02834   * @brief  Macro to configure the system clock source.
02835   * @param  __SYSCLKSOURCE__ specifies the system clock source.
02836   *          This parameter can be one of the following values:
02837   *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
02838   *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
02839   *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
02840   *              @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source.
02841   *              @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source.
02842   * @retval None
02843   */
02844 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
02845   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
02846
02847 /** @brief  Macro to get the clock source used as system clock.
02848   * @retval The clock source used as system clock. The returned value can be one
02849   *         of the following:
02850   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock.
02851   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock.
02852   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock.
02853   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source.
02854   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source.
02855   */
02856 #define __HAL_RCC_GET_SYSCLK_SOURCE()         (RCC->CFGR & RCC_CFGR_SWS)
02857
02858 /**
02859   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
02860   * @note   As the LSE is in the Backup domain and write access is denied to
02861   *         this domain after reset, you have to enable write access using
02862   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
02863   *         (to be done once after reset).
02864   * @param  __LSEDRIVE__ specifies the new state of the LSE drive capability.
02865   *          This parameter can be one of the following values:
02866   *            @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
02867   *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
02868   *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
02869   *            @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
02870   * @retval None
02871   */
02872 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
02873   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
02874
02875 /** @brief  Macro to configure the Microcontroller output clock.
02876   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
02877   *          This parameter can be one of the following values:
02878   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled
02879   *            @arg @ref RCC_MCO1SOURCE_SYSCLK System  clock selected as MCO source
02880   *            @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
02881   *            @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
02882   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source
02883   *            @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
02884   *            @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
02885   *            @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP output clock selected as MCO source
02886   *            @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ output clock selected as MCO source
02887   *            @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO source
02888   *            @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source
02889   @if STM32G0C1xx
02890   *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
02891   @endif
02892   * @param  __MCODIV__ specifies the MCO clock prescaler.
02893   *          This parameter can be one of the following values:
02894   *            @arg @ref RCC_MCODIV_1    MCO clock source is divided by 1
02895   *            @arg @ref RCC_MCODIV_2    MCO clock source is divided by 2
02896   *            @arg @ref RCC_MCODIV_4    MCO clock source is divided by 4
02897   *            @arg @ref RCC_MCODIV_8    MCO clock source is divided by 8
02898   *            @arg @ref RCC_MCODIV_16   MCO clock source is divided by 16
02899   *            @arg @ref RCC_MCODIV_32   MCO clock source is divided by 32
02900   *            @arg @ref RCC_MCODIV_64   MCO clock source is divided by 64
02901   *            @arg @ref RCC_MCODIV_128  MCO clock source is divided by 128
02902   @if STM32G0C1xx
02903   *            @arg @ref RCC_MCODIV_256  MCO clock source is divided by 256
02904   *            @arg @ref RCC_MCODIV_512  MCO clock source is divided by 512
02905   *            @arg @ref RCC_MCODIV_1024 MCO clock source is divided by 1024
02906   @endif
02907   */
02908 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
02909   MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
02910
02911 #if defined(RCC_MCO2_SUPPORT)
02912 /** @brief  Macro to configure the Microcontroller output clock 2.
02913   * @param  __MCOCLKSOURCE__ specifies the MCO2 clock source.
02914   *          This parameter can be one of the following values:
02915   *            @arg @ref RCC_MCO2SOURCE_NOCLOCK  MCO2 output disabled
02916   *            @arg @ref RCC_MCO2SOURCE_SYSCLK System  clock selected as MCO source
02917   *            @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source
02918   *            @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 sourcee
02919   *            @arg @ref RCC_MCO2SOURCE_PLLCLK  Main PLL clock selected as MCO2 source
02920   *            @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source
02921   *            @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source
02922   *            @arg @ref RCC_MCO2SOURCE_PLLPCLK PLLP output clock selected as MCO2 source
02923   *            @arg @ref RCC_MCO2SOURCE_PLLQCLK PLLQ output clock selected as MCO2 source
02924   *            @arg @ref RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source
02925   *            @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO2 source
02926   @if STM32G0C1xx
02927   *            @arg @ref RCC_MCO2SOURCE_HSI48  HSI48 clock selected as MCO2 source for devices with HSI48
02928   @endif
02929   * @param  __MCODIV__ specifies the MCO clock prescaler.
02930   *          This parameter can be one of the following values:
02931   *            @arg @ref RCC_MCO2DIV_1     MCO2 clock source is divided by 1
02932   *            @arg @ref RCC_MCO2DIV_2     MCO2 clock source is divided by 2
02933   *            @arg @ref RCC_MCO2DIV_4     MCO2 clock source is divided by 4
02934   *            @arg @ref RCC_MCO2DIV_8     MCO2 clock source is divided by 8
02935   *            @arg @ref RCC_MCO2DIV_16    MCO2 clock source is divided by 16
02936   *            @arg @ref RCC_MCO2DIV_32    MCO2 clock source is divided by 32
02937   *            @arg @ref RCC_MCO2DIV_64    MCO2 clock source is divided by 64
02938   *            @arg @ref RCC_MCO2DIV_128   MCO2 clock source is divided by 128
02939   *            @arg @ref RCC_MCO2DIV_256   MCO2 clock source is divided by 256
02940   *            @arg @ref RCC_MCO2DIV_512   MCO2 clock source is divided by 512
02941   *            @arg @ref RCC_MCO2DIV_1024  MCO2 clock source is divided by 1024
02942   */
02943 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
02944   MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
02945 #endif /* RCC_MCO2_SUPPORT */
02946
02947 /**
02948   * @}
02949   */
02950
02951 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
02952   * @brief macros to manage the specified RCC Flags and interrupts.
02953   * @{
02954   */
02955
02956 /** @brief  Enable RCC interrupt.
02957   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
02958   *         This parameter can be any combination of the following values:
02959   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
02960   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
02961   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
02962   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
02963   *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
02964   @if STM32G0C1xx
02965   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
02966   @endif
02967   * @retval None
02968   */
02969 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
02970
02971 /** @brief Disable RCC interrupt.
02972   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
02973   *         This parameter can be any combination of the following values:
02974   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
02975   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
02976   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
02977   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
02978   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
02979   @if STM32G0C1xx
02980   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
02981   @endif
02982   * @retval None
02983   */
02984 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
02985
02986 /** @brief  Clear RCC interrupt pending bits.
02987   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
02988   *         This parameter can be any combination of the following values:
02989   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
02990   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
02991   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
02992   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
02993   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
02994   *            @arg @ref RCC_IT_CSS     HSE Clock security system interrupt
02995   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
02996   @if STM32G0C1xx
02997   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
02998   @endif
02999   * @retval None
03000   */
03001 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
03002
03003 /** @brief  Check whether the RCC interrupt has occurred or not.
03004   * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
03005   *         This parameter can be one of the following values:
03006   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
03007   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
03008   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
03009   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
03010   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03011   *            @arg @ref RCC_IT_CSS     HSE Clock security system interrupt
03012   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03013   @if STM32G0C1xx
03014   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
03015   @endif
03016   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
03017   */
03018 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
03019
03020 /** @brief Set RMVF bit to clear the reset flags.
03021   *        The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST,
03022   *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
03023   * @retval None
03024   */
03025 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
03026
03027 /** @brief  Check whether the selected RCC flag is set or not.
03028   * @param  __FLAG__ specifies the flag to check.
03029   *         This parameter can be one of the following values:
03030   *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
03031   *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
03032   *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready
03033   *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
03034   *            @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
03035   *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
03036   @if STM32G0C1xx
03037   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
03038   @endif
03039   *            @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset
03040   *            @arg @ref RCC_FLAG_OBLRST OBLRST reset
03041   *            @arg @ref RCC_FLAG_PINRST Pin reset
03042   *            @arg @ref RCC_FLAG_SFTRST Software reset
03043   *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
03044   *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
03045   *            @arg @ref RCC_FLAG_LPWRRST Low Power reset
03046   * @retval The new state of __FLAG__ (TRUE or FALSE).
03047   */
03048 #if defined(RCC_HSI48_SUPPORT)
03049 #define __HAL_RCC_GET_FLAG(__FLAG__)                                      \
03050   (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR :                    \
03051       ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR :              \
03052        ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR :                \
03053         ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) &  \
03054      (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
03055 #else
03056 #define __HAL_RCC_GET_FLAG(__FLAG__)                                    \
03057   (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR :                  \
03058       ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR :              \
03059        ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \
03060      (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
03061 #endif /* RCC_HSI48_SUPPORT */
03062
03063 /**
03064   * @}
03065   */
03066
03067 /**
03068   * @}
03069   */
03070
03071 /* Include RCC HAL Extended module */
03072 #include "stm32g0xx_hal_rcc_ex.h"
03073
03074 /* Exported functions --------------------------------------------------------*/
03075 /** @addtogroup RCC_Exported_Functions
03076   * @{
03077   */
03078
03079
03080 /** @addtogroup RCC_Exported_Functions_Group1
03081   * @{
03082   */
03083
03084 /* Initialization and de-initialization functions  ******************************/
03085 HAL_StatusTypeDef HAL_RCC_DeInit(void);
03086 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
03087 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
03088
03089 /**
03090   * @}
03091   */
03092
03093 /** @addtogroup RCC_Exported_Functions_Group2
03094   * @{
03095   */
03096
03097 /* Peripheral Control functions  ************************************************/
03098 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
03099 void              HAL_RCC_EnableCSS(void);
03100 void              HAL_RCC_EnableLSECSS(void);
03101 void              HAL_RCC_DisableLSECSS(void);
03102 uint32_t          HAL_RCC_GetSysClockFreq(void);
03103 uint32_t          HAL_RCC_GetHCLKFreq(void);
03104 uint32_t          HAL_RCC_GetPCLK1Freq(void);
03105 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
03106 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
03107 uint32_t          HAL_RCC_GetResetSource(void);
03108 /* LSE & HSE CSS NMI IRQ handler */
03109 void              HAL_RCC_NMI_IRQHandler(void);
03110 /* User Callbacks in non blocking mode (IT mode) */
03111 void              HAL_RCC_CSSCallback(void);
03112 void              HAL_RCC_LSECSSCallback(void);
03113
03114 /**
03115   * @}
03116   */
03117
03118 /**
03119   * @}
03120   */
03121
03122 /**
03123   * @}
03124   */
03125
03126 /**
03127   * @}
03128   */
03129
03130 #ifdef __cplusplus
03131 }
03132 #endif
03133
03134 #endif /* STM32G0xx_HAL_RCC_H */
03135
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rcc_ex.c Source File

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stm32g0xx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities RCC extended peripheral:
00008   *           + Extended Peripheral Control functions
00009   *           + Extended Clock management functions
00010   *           + Extended Clock Recovery System Control functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file in
00019   * the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32g0xx_hal.h"
00026
00027 /** @addtogroup STM32G0xx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup RCCEx RCCEx
00032   * @brief RCC Extended HAL module driver
00033   * @{
00034   */
00035
00036 #ifdef HAL_RCC_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private defines -----------------------------------------------------------*/
00040 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
00041   * @{
00042   */
00043 #define PLL_TIMEOUT_VALUE        100U /* 100 ms (minimum Tick + 1)  */
00044
00045 #define LSCO_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
00046 #define LSCO_GPIO_PORT        GPIOA
00047 #define LSCO_PIN              GPIO_PIN_2
00048 /**
00049   * @}
00050   */
00051
00052 /* Private macros ------------------------------------------------------------*/
00053 /* Private variables ---------------------------------------------------------*/
00054 /* Private function prototypes -----------------------------------------------*/
00055 /* Exported functions --------------------------------------------------------*/
00056
00057 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
00058   * @{
00059   */
00060
00061 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00062   * @brief  Extended Peripheral Control functions
00063   *
00064 @verbatim
00065  ===============================================================================
00066                 ##### Extended Peripheral Control functions  #####
00067  ===============================================================================
00068     [..]
00069     This subsection provides a set of functions allowing to control the RCC Clocks
00070     frequencies.
00071     [..]
00072     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00073         select the RTC clock source; in this case the Backup domain will be reset in
00074         order to modify the RTC Clock source, as consequence RTC registers (including
00075         the backup registers) and RCC_BDCR register are set to their reset values.
00076
00077 @endverbatim
00078   * @{
00079   */
00080 /**
00081   * @brief  Initialize the RCC extended peripherals clocks according to the specified
00082   *         parameters in the @ref RCC_PeriphCLKInitTypeDef.
00083   * @param  PeriphClkInit  pointer to a @ref RCC_PeriphCLKInitTypeDef structure that
00084   *         contains a field PeriphClockSelection which can be a combination of the following values:
00085   *            @arg @ref RCC_PERIPHCLK_RTC     RTC peripheral clock
00086   *            @arg @ref RCC_PERIPHCLK_ADC     ADC peripheral clock
00087   *            @arg @ref RCC_PERIPHCLK_I2C1    I2C1 peripheral clock
00088   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock (2)
00089   *            @arg @ref RCC_PERIPHCLK_I2S1    I2S1 peripheral clock
00090   *            @arg @ref RCC_PERIPHCLK_I2S2    I2S2 peripheral clock (1)
00091   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
00092   *            @arg @ref RCC_PERIPHCLK_CEC     CEC peripheral clock     (1)
00093   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock  (1)
00094   *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock  (1)
00095   *            @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock (1)
00096   *            @arg @ref RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock (1)
00097   *            @arg @ref RCC_PERIPHCLK_RNG     RNG peripheral clock     (1)
00098   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock    (1)(2)
00099   *            @arg @ref RCC_PERIPHCLK_TIM15   TIM15 peripheral clock   (1)(2)
00100   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock     (2)
00101   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock     (2)
00102   *            @arg @ref RCC_PERIPHCLK_FDCAN   FDCAN peripheral clock   (1)
00103   *            @arg @ref RCC_PERIPHCLK_USB     USB peripheral clock     (1)
00104   *
00105   * @note   (1) Peripherals are not available on all devices
00106   * @note   (2) Peripherals clock selection is not available on all devices
00107   * @note   Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
00108   *         the RTC clock source: in this case the access to Backup domain is enabled.
00109   *
00110   * @retval HAL status
00111   */
00112 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00113 {
00114   uint32_t tmpregister;
00115   uint32_t tickstart;
00116   HAL_StatusTypeDef ret    = HAL_OK;   /* Intermediate status */
00117   HAL_StatusTypeDef status = HAL_OK;   /* Final status */
00118
00119   /* Check the parameters */
00120   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00121
00122   /*-------------------------- RTC clock source configuration ----------------------*/
00123   if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
00124   {
00125     FlagStatus       pwrclkchanged = RESET;
00126
00127     /* Check for RTC Parameters used to output RTCCLK */
00128     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
00129
00130     /* Enable Power Clock */
00131     if (__HAL_RCC_PWR_IS_CLK_DISABLED())
00132     {
00133       __HAL_RCC_PWR_CLK_ENABLE();
00134       pwrclkchanged = SET;
00135     }
00136
00137     /* Enable write access to Backup domain */
00138     SET_BIT(PWR->CR1, PWR_CR1_DBP);
00139
00140     /* Wait for Backup domain Write protection disable */
00141     tickstart = HAL_GetTick();
00142
00143     while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
00144     {
00145       if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00146       {
00147         ret = HAL_TIMEOUT;
00148         break;
00149       }
00150     }
00151
00152     if (ret == HAL_OK)
00153     {
00154       /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
00155       tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
00156
00157       /* Reset the Backup domain only if the RTC Clock source selection is modified */
00158       if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
00159       {
00160         /* Store the content of BDCR register before the reset of Backup Domain */
00161         tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
00162         /* RTC Clock selection can be changed only if the Backup Domain is reset */
00163         __HAL_RCC_BACKUPRESET_FORCE();
00164         __HAL_RCC_BACKUPRESET_RELEASE();
00165         /* Restore the Content of BDCR register */
00166         RCC->BDCR = tmpregister;
00167       }
00168
00169       /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
00170       if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
00171       {
00172         /* Get Start Tick*/
00173         tickstart = HAL_GetTick();
00174
00175         /* Wait till LSE is ready */
00176         while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
00177         {
00178           if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00179           {
00180             ret = HAL_TIMEOUT;
00181             break;
00182           }
00183         }
00184       }
00185
00186       if (ret == HAL_OK)
00187       {
00188         /* Apply new RTC clock source selection */
00189         __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00190       }
00191       else
00192       {
00193         /* set overall return value */
00194         status = ret;
00195       }
00196     }
00197     else
00198     {
00199       /* set overall return value */
00200       status = ret;
00201     }
00202
00203     /* Restore clock configuration if changed */
00204     if (pwrclkchanged == SET)
00205     {
00206       __HAL_RCC_PWR_CLK_DISABLE();
00207     }
00208   }
00209
00210   /*-------------------------- USART1 clock source configuration -------------------*/
00211   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
00212   {
00213     /* Check the parameters */
00214     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
00215
00216     /* Configure the USART1 clock source */
00217     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
00218   }
00219
00220 #if defined(RCC_CCIPR_USART2SEL)
00221   /*-------------------------- USART2 clock source configuration -------------------*/
00222   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
00223   {
00224     /* Check the parameters */
00225     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
00226
00227     /* Configure the USART2 clock source */
00228     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
00229   }
00230 #endif /* RCC_CCIPR_USART2SEL */
00231
00232 #if defined(RCC_CCIPR_USART3SEL)
00233   /*-------------------------- USART3 clock source configuration -------------------*/
00234   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
00235   {
00236     /* Check the parameters */
00237     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
00238
00239     /* Configure the USART3 clock source */
00240     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
00241   }
00242 #endif /* RCC_CCIPR_USART3SEL */
00243
00244 #if defined(LPUART1)
00245   /*-------------------------- LPUART1 clock source configuration ------------------*/
00246   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
00247   {
00248     /* Check the parameters */
00249     assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
00250
00251     /* Configure the LPUART1 clock source */
00252     __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
00253   }
00254 #endif /* LPUART1 */
00255
00256 #if defined(LPUART2)
00257   /*-------------------------- LPUART2 clock source configuration ------------------*/
00258   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2)
00259   {
00260     /* Check the parameters */
00261     assert_param(IS_RCC_LPUART2CLKSOURCE(PeriphClkInit->Lpuart2ClockSelection));
00262
00263     /* Configure the LPUART clock source */
00264     __HAL_RCC_LPUART2_CONFIG(PeriphClkInit->Lpuart2ClockSelection);
00265   }
00266 #endif /* LPUART2 */
00267
00268 #if defined(RCC_CCIPR_LPTIM1SEL)
00269   /*-------------------------- LPTIM1 clock source configuration -------------------*/
00270   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
00271   {
00272     assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
00273     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
00274   }
00275 #endif /* RCC_CCIPR_LPTIM1SEL */
00276
00277 #if defined(RCC_CCIPR_LPTIM2SEL)
00278   /*-------------------------- LPTIM2 clock source configuration -------------------*/
00279   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
00280   {
00281     assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
00282     __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
00283   }
00284 #endif /* RCC_CCIPR_LPTIM2SEL */
00285
00286   /*-------------------------- I2C1 clock source configuration ---------------------*/
00287   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
00288   {
00289     /* Check the parameters */
00290     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
00291
00292     /* Configure the I2C1 clock source */
00293     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
00294   }
00295
00296 #if defined(RCC_CCIPR_I2C2SEL)
00297   /*-------------------------- I2C2 clock source configuration ---------------------*/
00298   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
00299   {
00300     /* Check the parameters */
00301     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
00302
00303     /* Configure the I2C2 clock source */
00304     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
00305   }
00306 #endif /* (RCC_CCIPR_I2C2SEL */
00307
00308 #if defined(RNG)
00309   /*-------------------------- RNG clock source configuration ----------------------*/
00310   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
00311   {
00312     assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
00313     __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
00314
00315     if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
00316     {
00317       /* Enable PLLQCLK output */
00318       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
00319     }
00320   }
00321 #endif /* RNG */
00322   /*-------------------------- ADC clock source configuration ----------------------*/
00323   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
00324   {
00325     /* Check the parameters */
00326     assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
00327
00328     /* Configure the ADC interface clock source */
00329     __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
00330
00331     if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC)
00332     {
00333       /* Enable PLLPCLK output */
00334       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
00335     }
00336   }
00337
00338 #if defined(CEC)
00339   /*-------------------------- CEC clock source configuration ---------------------*/
00340   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
00341   {
00342     /* Check the parameters */
00343     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
00344
00345     /* Configure the CEC clock source */
00346     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
00347   }
00348 #endif /* CEC */
00349
00350 #if defined(RCC_CCIPR_TIM1SEL)
00351   /*-------------------------- TIM1 clock source configuration ---------------------*/
00352   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
00353   {
00354     /* Check the parameters */
00355     assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
00356
00357     /* Configure the TIM1 clock source */
00358     __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
00359
00360     if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL)
00361     {
00362       /* Enable PLLQCLK output */
00363       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
00364     }
00365   }
00366 #endif /* RCC_CCIPR_TIM1SEL */
00367
00368 #if defined(RCC_CCIPR_TIM15SEL)
00369   /*-------------------------- TIM15 clock source configuration ---------------------*/
00370   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
00371   {
00372     /* Check the parameters */
00373     assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
00374
00375     /* Configure the TIM15 clock source */
00376     __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
00377
00378     if (PeriphClkInit->Tim15ClockSelection == RCC_TIM15CLKSOURCE_PLL)
00379     {
00380       /* Enable PLLQCLK output */
00381       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
00382     }
00383   }
00384 #endif /* RCC_CCIPR_TIM15SEL */
00385
00386   /*-------------------------- I2S1 clock source configuration ---------------------*/
00387   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
00388   {
00389     /* Check the parameters */
00390     assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
00391
00392     /* Configure the I2S1 clock source */
00393     __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
00394
00395     if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL)
00396     {
00397       /* Enable PLLPCLK output */
00398       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
00399     }
00400   }
00401
00402 #if defined(RCC_CCIPR2_I2S2SEL)
00403   /*-------------------------- I2S2 clock source configuration ---------------------*/
00404   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
00405   {
00406     /* Check the parameters */
00407     assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
00408
00409     /* Configure the I2S2 clock source */
00410     __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
00411
00412     if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL)
00413     {
00414       /* Enable PLLPCLK output */
00415       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
00416     }
00417   }
00418 #endif /* RCC_CCIPR2_I2S2SEL */
00419
00420 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)  || defined(STM32G0B0xx)
00421   /*-------------------------- USB clock source configuration ---------------------*/
00422   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
00423   {
00424     /* Check the parameters */
00425     assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
00426
00427     /* Configure the USB clock source */
00428     __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
00429
00430     if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
00431     {
00432       /* Enable PLLQCLK output */
00433       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
00434     }
00435   }
00436 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00437
00438 #if defined(FDCAN1) || defined(FDCAN2)
00439   /*-------------------------- FDCAN clock source configuration ---------------------*/
00440   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
00441   {
00442     /* Check the parameters */
00443     assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
00444
00445     /* Configure the FDCAN clock source */
00446     __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
00447
00448     if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
00449     {
00450       /* Enable PLLQCLK output */
00451       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
00452     }
00453   }
00454 #endif /* FDCAN1 || FDCAN2 */
00455
00456   return status;
00457 }
00458
00459 /**
00460   * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
00461   * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
00462   *         returns the configuration information for the Extended Peripherals
00463   *         clocks: I2C1, I2S1, USART1, RTC, ADC,
00464   *         LPTIM1 (1), LPTIM2 (1), TIM1 (2), TIM15 (1)(2), USART2 (2), LPUART1 (1), CEC (1) and RNG (1)
00465   * @note (1) Peripheral is not available on all devices
00466   * @note (2) Peripheral clock selection is not available on all devices
00467   * @retval None
00468   */
00469 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00470 {
00471   /* Set all possible values for the extended clock type parameter------------*/
00472   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2S1 | \
00473                                         RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_RTC ;
00474
00475 #if defined(RCC_CCIPR_LPTIM1SEL) && defined(RCC_CCIPR_LPTIM2SEL)
00476   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM1;
00477 #endif /* RCC_CCIPR_LPTIM1SEL && RCC_CCIPR_LPTIM2SEL */
00478 #if defined(RCC_CCIPR_RNGSEL)
00479   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_RNG;
00480 #endif /* RCC_CCIPR_RNGSEL */
00481 #if defined(RCC_CCIPR_LPUART1SEL)
00482   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_LPUART1;
00483 #endif /* RCC_CCIPR_LPUART1SEL */
00484 #if defined(RCC_CCIPR_LPUART2SEL)
00485   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_LPUART2;
00486 #endif /* RCC_CCIPR_LPUART2SEL */
00487 #if defined(RCC_CCIPR_CECSEL)
00488   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_CEC;
00489 #endif /* RCC_CCIPR_CECSEL */
00490 #if defined(RCC_CCIPR_TIM1SEL)
00491   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_TIM1;
00492 #endif /* RCC_CCIPR_TIM1SEL */
00493 #if defined(RCC_CCIPR_TIM15SEL)
00494   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_TIM15;
00495 #endif /* RCC_CCIPR_TIM15SEL */
00496 #if defined(RCC_CCIPR_USART2SEL)
00497   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_USART2;
00498 #endif /* RCC_CCIPR_USART2SEL */
00499 #if defined(RCC_CCIPR_USART3SEL)
00500   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_USART3;
00501 #endif /* RCC_CCIPR_USART3SEL */
00502 #if defined(RCC_CCIPR_I2C2SEL)
00503   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_I2C2;
00504 #endif /* RCC_CCIPR_I2C2SEL */
00505 #if defined(RCC_CCIPR2_I2S2SEL)
00506   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_I2S2;
00507 #endif /* RCC_CCIPR2_I2S2SEL */
00508 #if defined(RCC_CCIPR2_USBSEL)
00509   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_USB;
00510 #endif /* RCC_CCIPR2_USBSEL */
00511 #if defined(RCC_CCIPR2_FDCANSEL)
00512   PeriphClkInit->PeriphClockSelection |=  RCC_PERIPHCLK_FDCAN;
00513 #endif /* RCC_CCIPR_FDCANSEL */
00514   /* Get the USART1 clock source ---------------------------------------------*/
00515   PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
00516 #if defined(RCC_CCIPR_USART2SEL)
00517   /* Get the USART2 clock source ---------------------------------------------*/
00518   PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
00519 #endif /* RCC_CCIPR_USART2SEL */
00520 #if defined(RCC_CCIPR_USART3SEL)
00521   /* Get the USART3 clock source ---------------------------------------------*/
00522   PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();
00523 #endif /* RCC_CCIPR_USART3SEL */
00524 #if defined(RCC_CCIPR_LPUART1SEL)
00525   /* Get the LPUART1 clock source --------------------------------------------*/
00526   PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
00527 #endif /* RCC_CCIPR_LPUART1SEL */
00528 #if defined(RCC_CCIPR_LPUART2SEL)
00529   /* Get the LPUART2 clock source --------------------------------------------*/
00530   PeriphClkInit->Lpuart2ClockSelection = __HAL_RCC_GET_LPUART2_SOURCE();
00531 #endif /* RCC_CCIPR_LPUART2SEL */
00532   /* Get the I2C1 clock source -----------------------------------------------*/
00533   PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
00534 #if defined(RCC_CCIPR_I2C2SEL)
00535   /* Get the I2C2 clock source -----------------------------------------------*/
00536   PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();
00537 #endif /* RCC_CCIPR_I2C2SEL */
00538 #if defined(RCC_CCIPR_LPTIM1SEL)
00539   /* Get the LPTIM1 clock source ---------------------------------------------*/
00540   PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();
00541 #endif /* RCC_CCIPR_LPTIM1SEL */
00542 #if defined(RCC_CCIPR_LPTIM2SEL)
00543   /* Get the LPTIM2 clock source ---------------------------------------------*/
00544   PeriphClkInit->Lptim2ClockSelection  = __HAL_RCC_GET_LPTIM2_SOURCE();
00545 #endif /* RCC_CCIPR_LPTIM2SEL */
00546 #if defined(RCC_CCIPR_TIM1SEL)
00547   /* Get the TIM1 clock source ---------------------------------------------*/
00548   PeriphClkInit->Tim1ClockSelection  = __HAL_RCC_GET_TIM1_SOURCE();
00549 #endif /* RCC_CCIPR_TIM1SEL */
00550 #if defined(RCC_CCIPR_TIM15SEL)
00551   /* Get the TIM15 clock source ---------------------------------------------*/
00552   PeriphClkInit->Tim15ClockSelection  = __HAL_RCC_GET_TIM15_SOURCE();
00553 #endif /* RCC_CCIPR_TIM15SEL */
00554   /* Get the RTC clock source ------------------------------------------------*/
00555   PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
00556 #if defined(RCC_CCIPR_RNGSEL)
00557   /* Get the RNG clock source ------------------------------------------------*/
00558   PeriphClkInit->RngClockSelection     = __HAL_RCC_GET_RNG_SOURCE();
00559 #endif  /* RCC_CCIPR_RNGSEL */
00560   /* Get the ADC clock source -----------------------------------------------*/
00561   PeriphClkInit->AdcClockSelection     = __HAL_RCC_GET_ADC_SOURCE();
00562 #if defined(RCC_CCIPR_CECSEL)
00563   /* Get the CEC clock source -----------------------------------------------*/
00564   PeriphClkInit->CecClockSelection     = __HAL_RCC_GET_CEC_SOURCE();
00565 #endif  /* RCC_CCIPR_CECSEL */
00566 #if defined(RCC_CCIPR2_USBSEL)
00567   /* Get the USB clock source -----------------------------------------------*/
00568   PeriphClkInit->UsbClockSelection     = __HAL_RCC_GET_USB_SOURCE();
00569 #endif  /* RCC_CCIPR2_USBSEL */
00570 #if defined(RCC_CCIPR2_FDCANSEL)
00571   /* Get the FDCAN clock source -----------------------------------------------*/
00572   PeriphClkInit->FdcanClockSelection     = __HAL_RCC_GET_FDCAN_SOURCE();
00573 #endif  /* RCC_CCIPR2_FDCANSEL */
00574   /* Get the I2S1 clock source -----------------------------------------------*/
00575   PeriphClkInit->I2s1ClockSelection    = __HAL_RCC_GET_I2S1_SOURCE();
00576 #if defined(RCC_CCIPR2_I2S2SEL)
00577   /* Get the I2S2 clock source -----------------------------------------------*/
00578   PeriphClkInit->I2s2ClockSelection    = __HAL_RCC_GET_I2S2_SOURCE();
00579 #endif /* RCC_CCIPR2_I2S2SEL */
00580 }
00581
00582 /**
00583   * @brief  Return the peripheral clock frequency for peripherals with clock source from PLL
00584   * @note   Return 0 if peripheral clock identifier not managed by this API
00585   * @param  PeriphClk  Peripheral clock identifier
00586   *         This parameter can be one of the following values:
00587   *            @arg @ref RCC_PERIPHCLK_RTC     RTC peripheral clock
00588   *            @arg @ref RCC_PERIPHCLK_ADC     ADC peripheral clock
00589   *            @arg @ref RCC_PERIPHCLK_I2C1    I2C1 peripheral clock
00590   *            @arg @ref RCC_PERIPHCLK_I2C2    I2C2 peripheral clock (1)
00591   *            @arg @ref RCC_PERIPHCLK_I2S1    I2S1 peripheral clock
00592   *            @arg @ref RCC_PERIPHCLK_I2S2    I2S2 peripheral clock (1)
00593   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
00594   *            @arg @ref RCC_PERIPHCLK_USART2  USART2 peripheral clock (1)(2)
00595   *            @arg @ref RCC_PERIPHCLK_USART3  USART3 peripheral clock (1)
00596   *            @arg @ref RCC_PERIPHCLK_RNG     RNG peripheral clock    (1)
00597   *            @arg @ref RCC_PERIPHCLK_TIM15   TIM15 peripheral clock  (1)(2)
00598   *            @arg @ref RCC_PERIPHCLK_TIM1    TIM1 peripheral clock   (1)(2)
00599   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock (1)
00600   *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock (1)
00601   *            @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock(1)
00602   *            @arg @ref RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock(1)
00603   *            @arg @ref RCC_PERIPHCLK_CEC     CEC peripheral clock    (1)
00604   *            @arg @ref RCC_PERIPHCLK_FDCAN    FDCAN peripheral clock (1)
00605   *            @arg @ref RCC_PERIPHCLK_USB      USB peripheral clock   (1)
00606   * @note   (1) Peripheral not available on all devices
00607   * @note   (2) Peripheral Clock configuration not available on all devices
00608   * @retval Frequency in Hz
00609   */
00610 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
00611 {
00612   uint32_t frequency = 0U;
00613   uint32_t srcclk;
00614   uint32_t pllvco;
00615   uint32_t plln;
00616 #if defined(RCC_CCIPR_RNGSEL)
00617   uint32_t rngclk;
00618   uint32_t rngdiv;
00619 #endif /* RCC_CCIPR_RNGSEL */
00620   /* Check the parameters */
00621   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
00622
00623   if (PeriphClk == RCC_PERIPHCLK_RTC)
00624   {
00625     /* Get the current RTC source */
00626     srcclk = __HAL_RCC_GET_RTC_SOURCE();
00627
00628     /* Check if LSE is ready and if RTC clock selection is LSE */
00629     if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
00630     {
00631       frequency = LSE_VALUE;
00632     }
00633     /* Check if LSI is ready and if RTC clock selection is LSI */
00634     else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
00635     {
00636       frequency = LSI_VALUE;
00637     }
00638     /* Check if HSE is ready  and if RTC clock selection is HSI_DIV32*/
00639     else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
00640     {
00641       frequency = HSE_VALUE / 32U;
00642     }
00643     /* Clock not enabled for RTC*/
00644     else
00645     {
00646       /* Nothing to do as frequency already initialized to 0U */
00647     }
00648   }
00649   else
00650   {
00651     /* Other external peripheral clock source than RTC */
00652
00653     /* Compute PLL clock input */
00654     if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)  /* HSI ? */
00655     {
00656       pllvco = HSI_VALUE;
00657     }
00658     else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)  /* HSE ? */
00659     {
00660       pllvco = HSE_VALUE;
00661     }
00662     else /* No source */
00663     {
00664       pllvco = 0U;
00665     }
00666
00667     /* f(PLL Source) / PLLM */
00668     pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
00669
00670     switch (PeriphClk)
00671     {
00672 #if defined(RCC_CCIPR_RNGSEL)
00673       case RCC_PERIPHCLK_RNG:
00674
00675         srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL);
00676         if (srcclk == RCC_RNGCLKSOURCE_HSI_DIV8)  /* HSI_DIV8 ? */
00677         {
00678           rngclk = HSI_VALUE / 8U;
00679         }
00680         else if (srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */
00681         {
00682           /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
00683           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
00684           rngclk = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U);
00685         }
00686         else if (srcclk == RCC_RNGCLKSOURCE_SYSCLK) /* SYSCLK ? */
00687         {
00688           rngclk = HAL_RCC_GetSysClockFreq();
00689         }
00690         else /* No clock source */
00691         {
00692           rngclk = 0U;
00693         }
00694
00695         rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos));
00696         frequency = (rngclk / rngdiv);
00697
00698         break;
00699 #endif  /* RCC_CCIPR_RNGSEL */
00700       case RCC_PERIPHCLK_USART1:
00701         /* Get the current USART1 source */
00702         srcclk = __HAL_RCC_GET_USART1_SOURCE();
00703
00704         if (srcclk == RCC_USART1CLKSOURCE_PCLK1)            /* PCLK1 ? */
00705         {
00706           frequency = HAL_RCC_GetPCLK1Freq();
00707         }
00708         else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)     /* SYSCLK ? */
00709         {
00710           frequency = HAL_RCC_GetSysClockFreq();
00711         }
00712         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
00713         {
00714           frequency = HSI_VALUE;
00715         }
00716         else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
00717         {
00718           frequency = LSE_VALUE;
00719         }
00720         /* Clock not enabled for USART1 */
00721         else
00722         {
00723           /* Nothing to do as frequency already initialized to 0U */
00724         }
00725         break;
00726 #if defined(RCC_CCIPR_USART2SEL)
00727       case RCC_PERIPHCLK_USART2:
00728         /* Get the current USART2 source */
00729         srcclk = __HAL_RCC_GET_USART2_SOURCE();
00730
00731         if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
00732         {
00733           frequency = HAL_RCC_GetPCLK1Freq();
00734         }
00735         else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
00736         {
00737           frequency = HAL_RCC_GetSysClockFreq();
00738         }
00739         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
00740         {
00741           frequency = HSI_VALUE;
00742         }
00743         else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
00744         {
00745           frequency = LSE_VALUE;
00746         }
00747         /* Clock not enabled for USART2 */
00748         else
00749         {
00750           /* Nothing to do as frequency already initialized to 0U */
00751         }
00752         break;
00753 #endif /* RCC_CCIPR_USART2SEL */
00754
00755 #if defined(RCC_CCIPR_USART3SEL)
00756       case RCC_PERIPHCLK_USART3:
00757         /* Get the current USART3 source */
00758         srcclk = __HAL_RCC_GET_USART3_SOURCE();
00759
00760         if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
00761         {
00762           frequency = HAL_RCC_GetPCLK1Freq();
00763         }
00764         else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
00765         {
00766           frequency = HAL_RCC_GetSysClockFreq();
00767         }
00768         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
00769         {
00770           frequency = HSI_VALUE;
00771         }
00772         else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
00773         {
00774           frequency = LSE_VALUE;
00775         }
00776         /* Clock not enabled for USART3 */
00777         else
00778         {
00779           /* Nothing to do as frequency already initialized to 0U */
00780         }
00781         break;
00782 #endif /* RCC_CCIPR_USART3SEL */
00783
00784 #if defined(RCC_CCIPR_CECSEL)
00785       case RCC_PERIPHCLK_CEC:
00786         /* Get the current CEC source */
00787         srcclk = __HAL_RCC_GET_CEC_SOURCE();
00788
00789         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_CECCLKSOURCE_HSI_DIV488))
00790         {
00791           frequency = (HSI_VALUE / 488U);
00792         }
00793         else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE))
00794         {
00795           frequency = LSE_VALUE;
00796         }
00797         /* Clock not enabled for CEC */
00798         else
00799         {
00800           /* Nothing to do as frequency already initialized to 0U */
00801         }
00802         break;
00803 #endif /* RCC_CCIPR_CECSEL */
00804
00805 #if defined(RCC_CCIPR_LPUART1SEL)
00806       case RCC_PERIPHCLK_LPUART1:
00807         /* Get the current LPUART1 source */
00808         srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
00809
00810         if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
00811         {
00812           frequency = HAL_RCC_GetPCLK1Freq();
00813         }
00814         else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
00815         {
00816           frequency = HAL_RCC_GetSysClockFreq();
00817         }
00818         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
00819         {
00820           frequency = HSI_VALUE;
00821         }
00822         else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
00823         {
00824           frequency = LSE_VALUE;
00825         }
00826         /* Clock not enabled for LPUART1 */
00827         else
00828         {
00829           /* Nothing to do as frequency already initialized to 0U */
00830         }
00831         break;
00832 #endif /* RCC_CCIPR_LPUART1SEL */
00833
00834 #if defined(RCC_CCIPR_LPUART2SEL)
00835       case RCC_PERIPHCLK_LPUART2:
00836         /* Get the current LPUART2 source */
00837         srcclk = __HAL_RCC_GET_LPUART2_SOURCE();
00838
00839         if (srcclk == RCC_LPUART2CLKSOURCE_PCLK1)
00840         {
00841           frequency = HAL_RCC_GetPCLK1Freq();
00842         }
00843         else if (srcclk == RCC_LPUART2CLKSOURCE_SYSCLK)
00844         {
00845           frequency = HAL_RCC_GetSysClockFreq();
00846         }
00847         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART2CLKSOURCE_HSI))
00848         {
00849           frequency = HSI_VALUE;
00850         }
00851         else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART2CLKSOURCE_LSE))
00852         {
00853           frequency = LSE_VALUE;
00854         }
00855         /* Clock not enabled for LPUART2 */
00856         else
00857         {
00858           /* Nothing to do as frequency already initialized to 0U */
00859         }
00860         break;
00861 #endif /* RCC_CCIPR_LPUART2SEL */
00862
00863       case RCC_PERIPHCLK_ADC:
00864
00865         srcclk = __HAL_RCC_GET_ADC_SOURCE();
00866
00867         if (srcclk == RCC_ADCCLKSOURCE_SYSCLK)
00868         {
00869           frequency = HAL_RCC_GetSysClockFreq();
00870         }
00871         else if (srcclk == RCC_ADCCLKSOURCE_HSI)
00872         {
00873           frequency = HSI_VALUE;
00874         }
00875         else if (srcclk == RCC_ADCCLKSOURCE_PLLADC)
00876         {
00877           if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U)
00878           {
00879             /* f(PLLP) = f(VCO input) * PLLN / PLLP */
00880             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
00881             frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U);
00882           }
00883         }
00884         /* Clock not enabled for ADC */
00885         else
00886         {
00887           /* Nothing to do as frequency already initialized to 0U */
00888         }
00889         break;
00890
00891       case RCC_PERIPHCLK_I2C1:
00892         /* Get the current I2C1 source */
00893         srcclk = __HAL_RCC_GET_I2C1_SOURCE();
00894
00895         if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
00896         {
00897           frequency = HAL_RCC_GetPCLK1Freq();
00898         }
00899         else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
00900         {
00901           frequency = HAL_RCC_GetSysClockFreq();
00902         }
00903         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
00904         {
00905           frequency = HSI_VALUE;
00906         }
00907         /* Clock not enabled for I2C1 */
00908         else
00909         {
00910           /* Nothing to do as frequency already initialized to 0U */
00911         }
00912         break;
00913
00914 #if defined(RCC_CCIPR_I2C2SEL)
00915       case RCC_PERIPHCLK_I2C2:
00916         /* Get the current I2C2 source */
00917         srcclk = __HAL_RCC_GET_I2C2_SOURCE();
00918
00919         if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
00920         {
00921           frequency = HAL_RCC_GetPCLK1Freq();
00922         }
00923         else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
00924         {
00925           frequency = HAL_RCC_GetSysClockFreq();
00926         }
00927         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
00928         {
00929           frequency = HSI_VALUE;
00930         }
00931         /* Clock not enabled for I2C2 */
00932         else
00933         {
00934           /* Nothing to do as frequency already initialized to 0U */
00935         }
00936         break;
00937 #endif /* RCC_CCIPR_I2C2SEL */
00938
00939       case RCC_PERIPHCLK_I2S1:
00940         /* Get the current I2S1 source */
00941         srcclk = __HAL_RCC_GET_I2S1_SOURCE();
00942
00943         if (srcclk == RCC_I2S1CLKSOURCE_PLL)
00944         {
00945           if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U)
00946           {
00947             /* f(PLLP) = f(VCO input) * PLLN / PLLP */
00948             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
00949             frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U);
00950           }
00951         }
00952         else if (srcclk == RCC_I2S1CLKSOURCE_SYSCLK)
00953         {
00954           frequency = HAL_RCC_GetSysClockFreq();
00955         }
00956         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S1CLKSOURCE_HSI))
00957         {
00958           frequency = HSI_VALUE;
00959         }
00960         else if (srcclk == RCC_I2S1CLKSOURCE_EXT)
00961         {
00962           /* External clock used.*/
00963           frequency = EXTERNAL_I2S1_CLOCK_VALUE;
00964         }
00965         /* Clock not enabled for I2S1 */
00966         else
00967         {
00968           /* Nothing to do as frequency already initialized to 0U */
00969         }
00970         break;
00971
00972 #if defined(RCC_CCIPR2_I2S2SEL)
00973       case RCC_PERIPHCLK_I2S2:
00974         /* Get the current I2S2 source */
00975         srcclk = __HAL_RCC_GET_I2S2_SOURCE();
00976
00977         if (srcclk == RCC_I2S2CLKSOURCE_PLL)
00978         {
00979           if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U)
00980           {
00981             /* f(PLLP) = f(VCO input) * PLLN / PLLP */
00982             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
00983             frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U);
00984           }
00985         }
00986         else if (srcclk == RCC_I2S2CLKSOURCE_SYSCLK)
00987         {
00988           frequency = HAL_RCC_GetSysClockFreq();
00989         }
00990         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S2CLKSOURCE_HSI))
00991         {
00992           frequency = HSI_VALUE;
00993         }
00994         else if (srcclk == RCC_I2S2CLKSOURCE_EXT)
00995         {
00996           /* External clock used.*/
00997           frequency = EXTERNAL_I2S2_CLOCK_VALUE;
00998         }
00999         /* Clock not enabled for I2S2 */
01000         else
01001         {
01002           /* Nothing to do as frequency already initialized to 0U */
01003         }
01004         break;
01005 #endif /* RCC_CCIPR2_I2S2SEL */
01006
01007 #if defined(RCC_CCIPR_LPTIM1SEL)
01008       case RCC_PERIPHCLK_LPTIM1:
01009         /* Get the current LPTIM1 source */
01010         srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
01011
01012         if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK1)
01013         {
01014           frequency = HAL_RCC_GetPCLK1Freq();
01015         }
01016         else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
01017         {
01018           frequency = LSI_VALUE;
01019         }
01020         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
01021         {
01022           frequency = HSI_VALUE;
01023         }
01024         else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
01025         {
01026           frequency = LSE_VALUE;
01027         }
01028         /* Clock not enabled for LPTIM1 */
01029         else
01030         {
01031           /* Nothing to do as frequency already initialized to 0U */
01032         }
01033         break;
01034 #endif /* RCC_CCIPR_LPTIM1SEL */
01035
01036 #if defined(RCC_CCIPR_LPTIM2SEL)
01037       case RCC_PERIPHCLK_LPTIM2:
01038         /* Get the current LPTIM2 source */
01039         srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
01040
01041         if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
01042         {
01043           frequency = HAL_RCC_GetPCLK1Freq();
01044         }
01045         else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI))
01046         {
01047           frequency = LSI_VALUE;
01048         }
01049         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI))
01050         {
01051           frequency = HSI_VALUE;
01052         }
01053         else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE))
01054         {
01055           frequency = LSE_VALUE;
01056         }
01057         /* Clock not enabled for LPTIM2 */
01058         else
01059         {
01060           /* Nothing to do as frequency already initialized to 0U */
01061         }
01062         break;
01063 #endif /* RCC_CCIPR_LPTIM2SEL */
01064
01065 #if defined(RCC_CCIPR_TIM1SEL)
01066       case RCC_PERIPHCLK_TIM1:
01067
01068         srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL);
01069
01070         if (srcclk == RCC_TIM1CLKSOURCE_PLL) /* PLL ? */
01071         {
01072           if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U)
01073           {
01074             /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01075             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01076             frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U);
01077           }
01078         }
01079         else if (srcclk == RCC_TIM1CLKSOURCE_PCLK1) /* PCLK1 ? */
01080         {
01081           frequency = HAL_RCC_GetPCLK1Freq();
01082         }
01083         else /* No clock source */
01084         {
01085           /* Nothing to do as frequency already initialized to 0U */
01086         }
01087         break;
01088 #endif /* RCC_CCIPR_TIM1SEL */
01089
01090 #if defined(RCC_CCIPR_TIM15SEL)
01091       case RCC_PERIPHCLK_TIM15:
01092
01093         srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL);
01094
01095         if (srcclk == RCC_TIM15CLKSOURCE_PLL) /* PLL ? */
01096         {
01097           if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U)
01098           {
01099             /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01100             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01101             frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U);
01102           }
01103         }
01104         else if (srcclk == RCC_TIM15CLKSOURCE_PCLK1) /* PCLK1 ? */
01105         {
01106           frequency = HAL_RCC_GetPCLK1Freq();
01107         }
01108         else /* No clock source */
01109         {
01110           /* Nothing to do as frequency already initialized to 0U */
01111         }
01112         break;
01113 #endif /* RCC_CCIPR_TIM15SEL */
01114
01115 #if defined(RCC_CCIPR2_USBSEL)
01116       case RCC_PERIPHCLK_USB:
01117
01118         srcclk = READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL);
01119
01120         if (srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */
01121         {
01122           if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U)
01123           {
01124             /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01125             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01126             frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U);
01127           }
01128         }
01129 #if defined(RCC_HSI48_SUPPORT)
01130         else if (srcclk == RCC_USBCLKSOURCE_HSI48) /* HSI48 ? */
01131         {
01132           if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48))
01133           {
01134             frequency = HSI48_VALUE;
01135           }
01136         }
01137 #endif /* RCC_HSI48_SUPPORT */
01138         else if (srcclk == RCC_USBCLKSOURCE_HSE)
01139         {
01140           if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBCLKSOURCE_HSE))
01141           {
01142             frequency = HSE_VALUE;
01143           }
01144         }
01145         else /* No clock source */
01146         {
01147           /* Nothing to do as frequency already initialized to 0U */
01148         }
01149         break;
01150 #endif /* RCC_CCIPR2_USBSEL */
01151
01152 #if defined(RCC_CCIPR2_FDCANSEL)
01153       case RCC_PERIPHCLK_FDCAN:
01154
01155         srcclk = READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL);
01156
01157         if (srcclk == RCC_FDCANCLKSOURCE_PLL) /* PLL ? */
01158         {
01159           if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U)
01160           {
01161             /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
01162             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
01163             frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U);
01164           }
01165         }
01166         else if (srcclk == RCC_FDCANCLKSOURCE_PCLK1) /* PCLK1 ? */
01167         {
01168           frequency = HAL_RCC_GetPCLK1Freq();
01169         }
01170         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCANCLKSOURCE_HSE))
01171         {
01172           frequency = HSE_VALUE;
01173         }
01174         else /* No clock source */
01175         {
01176           /* Nothing to do as frequency already initialized to 0U */
01177         }
01178         break;
01179 #endif /* RCC_CCIPR2_FDCANSEL */
01180
01181       default:
01182         break;
01183     }
01184   }
01185
01186   return (frequency);
01187 }
01188
01189 /**
01190   * @}
01191   */
01192
01193 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
01194   *  @brief  Extended Clock management functions
01195   *
01196 @verbatim
01197  ===============================================================================
01198                 ##### Extended clock management functions  #####
01199  ===============================================================================
01200     [..]
01201     This subsection provides a set of functions allowing to control the
01202     activation or deactivation of LSE CSS, Low speed clock output and
01203     clock after wake-up from STOP mode.
01204 @endverbatim
01205   * @{
01206   */
01207
01208 /**
01209   * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).
01210   * @param  LSCOSource  specifies the Low Speed clock source to output.
01211   *          This parameter can be one of the following values:
01212   *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
01213   *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
01214   * @retval None
01215   */
01216 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
01217 {
01218   GPIO_InitTypeDef GPIO_InitStruct;
01219   FlagStatus       pwrclkchanged = RESET;
01220   FlagStatus       backupchanged = RESET;
01221
01222   /* Check the parameters */
01223   assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
01224
01225   /* LSCO Pin Clock Enable */
01226   LSCO_CLK_ENABLE();
01227
01228   /* Configure the LSCO pin in analog mode */
01229   GPIO_InitStruct.Pin = LSCO_PIN;
01230   GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
01231   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
01232   GPIO_InitStruct.Pull = GPIO_NOPULL;
01233   HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
01234
01235   /* Update LSCOSEL clock source in Backup Domain control register */
01236   if (__HAL_RCC_PWR_IS_CLK_DISABLED())
01237   {
01238     __HAL_RCC_PWR_CLK_ENABLE();
01239     pwrclkchanged = SET;
01240   }
01241   if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01242   {
01243     HAL_PWR_EnableBkUpAccess();
01244     backupchanged = SET;
01245   }
01246
01247   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
01248
01249   if (backupchanged == SET)
01250   {
01251     HAL_PWR_DisableBkUpAccess();
01252   }
01253   if (pwrclkchanged == SET)
01254   {
01255     __HAL_RCC_PWR_CLK_DISABLE();
01256   }
01257 }
01258
01259 /**
01260   * @brief  Disable the Low Speed clock output.
01261   * @retval None
01262   */
01263 void HAL_RCCEx_DisableLSCO(void)
01264 {
01265   FlagStatus       pwrclkchanged = RESET;
01266   FlagStatus       backupchanged = RESET;
01267
01268   /* Update LSCOEN bit in Backup Domain control register */
01269   if (__HAL_RCC_PWR_IS_CLK_DISABLED())
01270   {
01271     __HAL_RCC_PWR_CLK_ENABLE();
01272     pwrclkchanged = SET;
01273   }
01274   if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01275   {
01276     /* Enable access to the backup domain */
01277     HAL_PWR_EnableBkUpAccess();
01278     backupchanged = SET;
01279   }
01280
01281   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01282
01283   /* Restore previous configuration */
01284   if (backupchanged == SET)
01285   {
01286     /* Disable access to the backup domain */
01287     HAL_PWR_DisableBkUpAccess();
01288   }
01289   if (pwrclkchanged == SET)
01290   {
01291     __HAL_RCC_PWR_CLK_DISABLE();
01292   }
01293 }
01294
01295 /**
01296   * @}
01297   */
01298
01299 #if defined(CRS)
01300
01301 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
01302   * @brief  Extended Clock Recovery System Control functions
01303   *
01304 @verbatim
01305  ===============================================================================
01306                 ##### Extended Clock Recovery System Control functions  #####
01307  ===============================================================================
01308     [..]
01309       For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
01310
01311       (#) In System clock config, HSI48 needs to be enabled
01312
01313       (#) Enable CRS clock in IP MSP init which will use CRS functions
01314
01315       (#) Call CRS functions as follows:
01316           (##) Prepare synchronization configuration necessary for HSI48 calibration
01317               (+++) Default values can be set for frequency Error Measurement (reload and error limit)
01318                         and also HSI48 oscillator smooth trimming.
01319               (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
01320                         directly reload value with target and synchronization frequencies values
01321           (##) Call function HAL_RCCEx_CRSConfig which
01322               (+++) Resets CRS registers to their default values.
01323               (+++) Configures CRS registers with synchronization configuration
01324               (+++) Enables automatic calibration and frequency error counter feature
01325            Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
01326            periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
01327            provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
01328            precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
01329            should be used as SYNC signal.
01330
01331           (##) A polling function is provided to wait for complete synchronization
01332               (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
01333               (+++) According to CRS status, user can decide to adjust again the calibration or continue
01334                         application if synchronization is OK
01335
01336       (#) User can retrieve information related to synchronization in calling function
01337             HAL_RCCEx_CRSGetSynchronizationInfo()
01338
01339       (#) Regarding synchronization status and synchronization information, user can try a new calibration
01340            in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
01341            Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
01342            it means that the actual frequency is lower than the target (and so, that the TRIM value should be
01343            incremented), while when it is detected during the upcounting phase it means that the actual frequency
01344            is higher (and that the TRIM value should be decremented).
01345
01346       (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
01347           through CRS Handler (CRS_IRQn/CRS_IRQHandler)
01348               (++) Call function HAL_RCCEx_CRSConfig()
01349               (++) Enable CRS_IRQn (thanks to NVIC functions)
01350               (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
01351               (++) Implement CRS status management in the following user callbacks called from
01352                    HAL_RCCEx_CRS_IRQHandler():
01353                    (+++) HAL_RCCEx_CRS_SyncOkCallback()
01354                    (+++) HAL_RCCEx_CRS_SyncWarnCallback()
01355                    (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
01356                    (+++) HAL_RCCEx_CRS_ErrorCallback()
01357
01358       (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
01359           This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
01360
01361 @endverbatim
01362   * @{
01363   */
01364
01365 /**
01366   * @brief  Start automatic synchronization for polling mode
01367   * @param  pInit Pointer on RCC_CRSInitTypeDef structure
01368   * @retval None
01369   */
01370 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
01371 {
01372   uint32_t value;  /* no init needed */
01373
01374   /* Check the parameters */
01375   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
01376   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
01377   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
01378   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
01379   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
01380   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
01381
01382   /* CONFIGURATION */
01383
01384   /* Before configuration, reset CRS registers to their default values*/
01385   __HAL_RCC_CRS_FORCE_RESET();
01386   __HAL_RCC_CRS_RELEASE_RESET();
01387
01388   /* Set the SYNCDIV[2:0] bits according to Prescaler value */
01389   /* Set the SYNCSRC[1:0] bits according to Source value */
01390   /* Set the SYNCSPOL bit according to Polarity value */
01391   value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
01392   /* Set the RELOAD[15:0] bits according to ReloadValue value */
01393   value |= pInit->ReloadValue;
01394   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
01395   value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
01396   WRITE_REG(CRS->CFGR, value);
01397
01398   /* Adjust HSI48 oscillator smooth trimming */
01399   /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */
01400   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
01401
01402   /* START AUTOMATIC SYNCHRONIZATION*/
01403
01404   /* Enable Automatic trimming & Frequency error counter */
01405   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
01406 }
01407
01408 /**
01409   * @brief  Generate the software synchronization event
01410   * @retval None
01411   */
01412 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
01413 {
01414   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
01415 }
01416
01417 /**
01418   * @brief  Return synchronization info
01419   * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
01420   * @retval None
01421   */
01422 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
01423 {
01424   /* Check the parameter */
01425   assert_param(pSynchroInfo != (void *)NULL);
01426
01427   /* Get the reload value */
01428   pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
01429
01430   /* Get HSI48 oscillator smooth trimming */
01431   pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
01432
01433   /* Get Frequency error capture */
01434   pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
01435
01436   /* Get Frequency error direction */
01437   pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
01438 }
01439
01440 /**
01441   * @brief Wait for CRS Synchronization status.
01442   * @param Timeout  Duration of the timeout
01443   * @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
01444   *        frequency.
01445   * @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
01446   * @retval Combination of Synchronization status
01447   *          This parameter can be a combination of the following values:
01448   *            @arg @ref RCC_CRS_TIMEOUT
01449   *            @arg @ref RCC_CRS_SYNCOK
01450   *            @arg @ref RCC_CRS_SYNCWARN
01451   *            @arg @ref RCC_CRS_SYNCERR
01452   *            @arg @ref RCC_CRS_SYNCMISS
01453   *            @arg @ref RCC_CRS_TRIMOVF
01454   */
01455 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
01456 {
01457   uint32_t crsstatus = RCC_CRS_NONE;
01458   uint32_t tickstart;
01459
01460   /* Get timeout */
01461   tickstart = HAL_GetTick();
01462
01463   /* Wait for CRS flag or timeout detection */
01464   do
01465   {
01466     if (Timeout != HAL_MAX_DELAY)
01467     {
01468       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01469       {
01470         crsstatus = RCC_CRS_TIMEOUT;
01471       }
01472     }
01473     /* Check CRS SYNCOK flag  */
01474     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
01475     {
01476       /* CRS SYNC event OK */
01477       crsstatus |= RCC_CRS_SYNCOK;
01478
01479       /* Clear CRS SYNC event OK bit */
01480       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
01481     }
01482
01483     /* Check CRS SYNCWARN flag  */
01484     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
01485     {
01486       /* CRS SYNC warning */
01487       crsstatus |= RCC_CRS_SYNCWARN;
01488
01489       /* Clear CRS SYNCWARN bit */
01490       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
01491     }
01492
01493     /* Check CRS TRIM overflow flag  */
01494     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
01495     {
01496       /* CRS SYNC Error */
01497       crsstatus |= RCC_CRS_TRIMOVF;
01498
01499       /* Clear CRS Error bit */
01500       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
01501     }
01502
01503     /* Check CRS Error flag  */
01504     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
01505     {
01506       /* CRS SYNC Error */
01507       crsstatus |= RCC_CRS_SYNCERR;
01508
01509       /* Clear CRS Error bit */
01510       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
01511     }
01512
01513     /* Check CRS SYNC Missed flag  */
01514     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
01515     {
01516       /* CRS SYNC Missed */
01517       crsstatus |= RCC_CRS_SYNCMISS;
01518
01519       /* Clear CRS SYNC Missed bit */
01520       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
01521     }
01522
01523     /* Check CRS Expected SYNC flag  */
01524     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
01525     {
01526       /* frequency error counter reached a zero value */
01527       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
01528     }
01529   } while (RCC_CRS_NONE == crsstatus);
01530
01531   return crsstatus;
01532 }
01533
01534 /**
01535   * @brief Handle the Clock Recovery System interrupt request.
01536   * @retval None
01537   */
01538 void HAL_RCCEx_CRS_IRQHandler(void)
01539 {
01540   uint32_t crserror = RCC_CRS_NONE;
01541   /* Get current IT flags and IT sources values */
01542   uint32_t itflags = READ_REG(CRS->ISR);
01543   uint32_t itsources = READ_REG(CRS->CR);
01544
01545   /* Check CRS SYNCOK flag  */
01546   if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
01547   {
01548     /* Clear CRS SYNC event OK flag */
01549     WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
01550
01551     /* user callback */
01552     HAL_RCCEx_CRS_SyncOkCallback();
01553   }
01554   /* Check CRS SYNCWARN flag  */
01555   else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
01556   {
01557     /* Clear CRS SYNCWARN flag */
01558     WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
01559
01560     /* user callback */
01561     HAL_RCCEx_CRS_SyncWarnCallback();
01562   }
01563   /* Check CRS Expected SYNC flag  */
01564   else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
01565   {
01566     /* frequency error counter reached a zero value */
01567     WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
01568
01569     /* user callback */
01570     HAL_RCCEx_CRS_ExpectedSyncCallback();
01571   }
01572   /* Check CRS Error flags  */
01573   else
01574   {
01575     if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
01576     {
01577       if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
01578       {
01579         crserror |= RCC_CRS_SYNCERR;
01580       }
01581       if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
01582       {
01583         crserror |= RCC_CRS_SYNCMISS;
01584       }
01585       if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
01586       {
01587         crserror |= RCC_CRS_TRIMOVF;
01588       }
01589
01590       /* Clear CRS Error flags */
01591       WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
01592
01593       /* user error callback */
01594       HAL_RCCEx_CRS_ErrorCallback(crserror);
01595     }
01596   }
01597 }
01598
01599 /**
01600   * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
01601   * @retval none
01602   */
01603 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
01604 {
01605   /* NOTE : This function should not be modified, when the callback is needed,
01606             the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
01607    */
01608 }
01609
01610 /**
01611   * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
01612   * @retval none
01613   */
01614 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
01615 {
01616   /* NOTE : This function should not be modified, when the callback is needed,
01617             the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
01618    */
01619 }
01620
01621 /**
01622   * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
01623   * @retval none
01624   */
01625 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
01626 {
01627   /* NOTE : This function should not be modified, when the callback is needed,
01628             the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
01629    */
01630 }
01631
01632 /**
01633   * @brief  RCCEx Clock Recovery System Error interrupt callback.
01634   * @param  Error Combination of Error status.
01635   *         This parameter can be a combination of the following values:
01636   *           @arg @ref RCC_CRS_SYNCERR
01637   *           @arg @ref RCC_CRS_SYNCMISS
01638   *           @arg @ref RCC_CRS_TRIMOVF
01639   * @retval none
01640   */
01641 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
01642 {
01643   /* Prevent unused argument(s) compilation warning */
01644   UNUSED(Error);
01645
01646   /* NOTE : This function should not be modified, when the callback is needed,
01647             the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
01648    */
01649 }
01650
01651 /**
01652   * @}
01653   */
01654
01655 #endif /* CRS */
01656
01657 /**
01658   * @}
01659   */
01660
01661
01662 /**
01663   * @}
01664   */
01665
01666 /**
01667   * @}
01668   */
01669
01670 #endif /* HAL_RCC_MODULE_ENABLED */
01671 /**
01672   * @}
01673   */
01674
01675 /**
01676   * @}
01677   */
01678
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rcc_ex.h Source File

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stm32g0xx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G0xx_HAL_RCC_EX_H
00020 #define STM32G0xx_HAL_RCC_EX_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g0xx_hal_def.h"
00028
00029 /** @addtogroup STM32G0xx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup RCCEx
00034   * @{
00035   */
00036
00037 /* Exported types ------------------------------------------------------------*/
00038
00039 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  RCC extended clocks structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
00049                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00050
00051   uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
00052                                         This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00053 #if defined(RCC_CCIPR_USART2SEL)
00054   uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
00055                                         This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
00056 #endif /* RCC_CCIPR_USART2SEL */
00057
00058 #if defined(RCC_CCIPR_USART3SEL)
00059   uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.
00060                                         This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
00061 #endif /* RCC_CCIPR_USART3SEL */
00062
00063 #if defined(LPUART1)
00064   uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source
00065                                         This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
00066 #endif /* LPUART1 */
00067
00068 #if defined(LPUART2)
00069   uint32_t Lpuart2ClockSelection;  /*!< Specifies LPUART2 clock source
00070                                         This parameter can be a value of @ref RCCEx_LPUART2_Clock_Source */
00071 #endif /* LPUART2 */
00072
00073   uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source
00074                                         This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
00075
00076 #if defined(RCC_CCIPR_I2C2SEL)
00077   uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source
00078                                         This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00079 #endif /* RCC_CCIPR_I2C2SEL */
00080
00081   uint32_t I2s1ClockSelection;     /*!< Specifies I2S1 clock source
00082                                         This parameter can be a value of @ref RCCEx_I2S1_Clock_Source */
00083 #if defined(RCC_CCIPR2_I2S2SEL)
00084   uint32_t I2s2ClockSelection;     /*!< Specifies I2S2 clock source
00085                                         This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
00086 #endif /* RCC_CCIPR2_I2S2SEL */
00087 #if defined(RCC_CCIPR_LPTIM1SEL)
00088   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
00089                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
00090 #endif /* RCC_CCIPR_LPTIM1SEL */
00091 #if defined(RCC_CCIPR_LPTIM2SEL)
00092   uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source
00093                                         This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
00094 #endif /* RCC_CCIPR_LPTIM2SEL */
00095 #if defined(RNG)
00096   uint32_t RngClockSelection;      /*!< Specifies RNG clock source
00097                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
00098 #endif /* RNG */
00099   uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source
00100                                         This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
00101 #if defined(CEC)
00102   uint32_t CecClockSelection;      /*!< Specifies CEC Clock clock source
00103                                         This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
00104 #endif /* CEC */
00105 #if defined(RCC_CCIPR_TIM1SEL)
00106   uint32_t Tim1ClockSelection;     /*!< Specifies TIM1 Clock clock source
00107                                          This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
00108 #endif /* RCC_CCIPR_TIM1SEL */
00109 #if defined(RCC_CCIPR_TIM15SEL)
00110   uint32_t Tim15ClockSelection;    /*!< Specifies TIM15 Clock clock source
00111                                          This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
00112 #endif /* RCC_CCIPR_TIM15SEL */
00113   uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.
00114                                         This parameter can be a value of @ref RCC_RTC_Clock_Source */
00115 #if defined(RCC_CCIPR2_USBSEL)
00116   uint32_t UsbClockSelection;      /*!< Specifies USB Clock clock source
00117                                         This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00118 #endif /* RCC_CCIPR2_USBSEL */
00119 #if defined(FDCAN1) || defined(FDCAN2)
00120   uint32_t FdcanClockSelection;    /*!< Specifies FDCAN Clock clock source
00121                                         This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */
00122 #endif /* FDCAN1 || FDCAN2 */
00123 } RCC_PeriphCLKInitTypeDef;
00124
00125 #if defined(CRS)
00126
00127 /**
00128   * @brief RCC_CRS Init structure definition
00129   */
00130 typedef struct
00131 {
00132   uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
00133                                        This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
00134
00135   uint32_t Source;                /*!< Specifies the SYNC signal source.
00136                                        This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
00137
00138   uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
00139                                        This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
00140
00141   uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
00142                                        It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
00143                                        This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
00144
00145   uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
00146                                        This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
00147
00148   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
00149                                        This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
00150
00151 } RCC_CRSInitTypeDef;
00152
00153 /**
00154   * @brief RCC_CRS Synchronization structure definition
00155   */
00156 typedef struct
00157 {
00158   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
00159                                        This parameter must be a number between 0 and 0xFFFF */
00160
00161   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
00162                                        This parameter must be a number between 0 and 0x7F */
00163
00164   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
00165                                        value latched in the time of the last SYNC event.
00166                                        This parameter must be a number between 0 and 0xFFFF */
00167
00168   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
00169                                        frequency error counter latched in the time of the last SYNC event.
00170                                        It shows whether the actual frequency is below or above the target.
00171                                        This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
00172
00173 } RCC_CRSSynchroInfoTypeDef;
00174
00175 #endif /* CRS */
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported constants --------------------------------------------------------*/
00181 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
00182   * @{
00183   */
00184
00185 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
00186   * @{
00187   */
00188 #define RCC_LSCOSOURCE_LSI             0x00000000U           /*!< LSI selection for low speed clock output */
00189 #define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock output */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
00195   * @{
00196   */
00197 #define RCC_PERIPHCLK_USART1           0x00000001U
00198 #if defined(RCC_CCIPR_USART2SEL)
00199 #define RCC_PERIPHCLK_USART2           0x00000002U
00200 #endif /* RCC_CCIPR_USART2SEL */
00201 #if defined(RCC_CCIPR_USART3SEL)
00202 #define RCC_PERIPHCLK_USART3           0x00000004U
00203 #endif /* RCC_CCIPR_USART3SEL */
00204 #if defined(LPUART1)
00205 #define RCC_PERIPHCLK_LPUART1          0x00000010U
00206 #endif /* LPUART1 */
00207 #define RCC_PERIPHCLK_I2C1             0x00000020U
00208 #if defined(RCC_CCIPR_I2C2SEL)
00209 #define RCC_PERIPHCLK_I2C2             0x00000040U
00210 #endif /* RCC_CCIPR_I2C2SEL */
00211 #if defined(RCC_CCIPR_LPTIM1SEL)
00212 #define RCC_PERIPHCLK_LPTIM1           0x00000200U
00213 #endif /* RCC_CCIPR_LPTIM1SEL */
00214 #if defined(RCC_CCIPR_LPTIM2SEL)
00215 #define RCC_PERIPHCLK_LPTIM2           0x00000400U
00216 #endif /* RCC_CCIPR_LPTIM2SEL */
00217 #define RCC_PERIPHCLK_I2S1             0x00000800U
00218 #if defined(LPUART2)
00219 #define RCC_PERIPHCLK_LPUART2          0x00001000U
00220 #endif /* LPUART2 */
00221 #if defined(RCC_CCIPR2_I2S2SEL)
00222 #define RCC_PERIPHCLK_I2S2             0x00002000U
00223 #endif /* RCC_CCIPR2_I2S2SEL */
00224 #define RCC_PERIPHCLK_ADC              0x00004000U
00225 #define RCC_PERIPHCLK_RTC              0x00020000U
00226 #if defined(RCC_CCIPR_RNGSEL)
00227 #define RCC_PERIPHCLK_RNG              0x00040000U
00228 #endif /* RCC_CCIPR_RNGSEL */
00229 #if defined(RCC_CCIPR_CECSEL)
00230 #define RCC_PERIPHCLK_CEC              0x00080000U
00231 #endif /* RCC_CCIPR_CECSEL */
00232 #if defined(RCC_CCIPR_TIM1SEL)
00233 #define RCC_PERIPHCLK_TIM1             0x00200000U
00234 #endif /* RCC_CCIPR_TIM1SEL */
00235 #if defined(RCC_CCIPR_TIM15SEL)
00236 #define RCC_PERIPHCLK_TIM15            0x00400000U
00237 #endif /* RCC_CCIPR_TIM15SEL */
00238 #if defined(RCC_CCIPR2_USBSEL)
00239 #define RCC_PERIPHCLK_USB              0x01000000U
00240 #endif /* RCC_CCIPR2_USBSEL */
00241 #if defined(FDCAN1) || defined(FDCAN2)
00242 #define RCC_PERIPHCLK_FDCAN            0x02000000U
00243 #endif /* FDCAN1 || FDCAN2 */
00244 /**
00245   * @}
00246   */
00247
00248
00249 /** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source
00250   * @{
00251   */
00252 #define RCC_USART1CLKSOURCE_PCLK1      0x00000000U                                      /*!< APB clock selected as USART1 clock */
00253 #define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0                            /*!< SYSCLK clock selected as USART1 clock */
00254 #define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1                            /*!< HSI clock selected as USART1 clock */
00255 #define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)  /*!< LSE clock selected as USART1 clock */
00256 /**
00257   * @}
00258   */
00259
00260 #if defined(RCC_CCIPR_USART2SEL)
00261 /** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source
00262   * @{
00263   */
00264 #define RCC_USART2CLKSOURCE_PCLK1      0x00000000U                                      /*!< APB clock selected as USART2 clock */
00265 #define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0                            /*!< SYSCLK clock selected as USART2 clock */
00266 #define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1                            /*!< HSI clock selected as USART2 clock */
00267 #define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)  /*!< LSE clock selected as USART2 clock */
00268 /**
00269   * @}
00270   */
00271 #endif /* RCC_CCIPR_USART2SEL */
00272 #if defined(RCC_CCIPR_USART3SEL)
00273 /** @defgroup RCCEx_USART3_Clock_Source RCC USART3 Clock Source
00274   * @{
00275   */
00276 #define RCC_USART3CLKSOURCE_PCLK1      0x00000000U                                      /*!< APB clock selected as USART3 clock */
00277 #define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0                            /*!< SYSCLK clock selected as USART3 clock */
00278 #define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1                            /*!< HSI clock selected as USART3 clock */
00279 #define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)  /*!< LSE clock selected as USART3 clock */
00280 /**
00281   * @}
00282   */
00283 #endif /* RCC_CCIPR_USART3SEL */
00284
00285 #if defined(LPUART1)
00286 /** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART1 Clock Source
00287   * @{
00288   */
00289 #define RCC_LPUART1CLKSOURCE_PCLK1     0x00000000U                                        /*!< APB clock selected as LPUART1 clock */
00290 #define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0                             /*!< SYSCLK clock selected as LPUART1 clock */
00291 #define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1                             /*!< HSI clock selected as LPUART1 clock */
00292 #define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)  /*!< LSE clock selected as LPUART1 clock */
00293 /**
00294   * @}
00295   */
00296 #endif /* LPUART1 */
00297
00298 #if defined(LPUART2)
00299 /** @defgroup RCCEx_LPUART2_Clock_Source RCC LPUART2 Clock Source
00300   * @{
00301   */
00302 #define RCC_LPUART2CLKSOURCE_PCLK1     0x00000000U                                        /*!< APB clock selected as LPUART2 clock */
00303 #define RCC_LPUART2CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART2SEL_0                             /*!< SYSCLK clock selected as LPUART2 clock */
00304 #define RCC_LPUART2CLKSOURCE_HSI       RCC_CCIPR_LPUART2SEL_1                             /*!< HSI clock selected as LPUART2 clock */
00305 #define RCC_LPUART2CLKSOURCE_LSE       (RCC_CCIPR_LPUART2SEL_0 | RCC_CCIPR_LPUART2SEL_1)  /*!< LSE clock selected as LPUART2 clock */
00306 /**
00307   * @}
00308   */
00309 #endif /* LPUART2 */
00310
00311 /** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source
00312   * @{
00313   */
00314 #define RCC_I2C1CLKSOURCE_PCLK1        0x00000000U                                      /*!< APB clock selected as I2C1 clock */
00315 #define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0                              /*!< SYSCLK clock selected as I2C1 clock */
00316 #define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1                              /*!< HSI clock selected as I2C1 clock */
00317 /**
00318   * @}
00319   */
00320
00321 #if defined(RCC_CCIPR_I2C2SEL)
00322 /** @defgroup RCCEx_I2C2_Clock_Source RCC I2C2 Clock Source
00323   * @{
00324   */
00325 #define RCC_I2C2CLKSOURCE_PCLK1        0x00000000U                                      /*!< APB clock selected as I2C2 clock */
00326 #define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0                              /*!< SYSCLK clock selected as I2C2 clock */
00327 #define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1                              /*!< HSI clock selected as I2C2 clock */
00328 /**
00329   * @}
00330   */
00331 #endif /* RCC_CCIPR_I2C2SEL */
00332
00333 /** @defgroup RCCEx_I2S1_Clock_Source RCC I2S1 Clock Source
00334   * @{
00335   */
00336 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00337 #define RCC_I2S1CLKSOURCE_SYSCLK       0x00000000U                                      /*!< SYSCLK clock selected as I2S1 clock */
00338 #define RCC_I2S1CLKSOURCE_PLL          RCC_CCIPR2_I2S1SEL_0                             /*!< PLL "P" selected as I2S1 clock */
00339 #define RCC_I2S1CLKSOURCE_HSI          RCC_CCIPR2_I2S1SEL_1                             /*!< HSI clock selected as I2S1 clock */
00340 #define RCC_I2S1CLKSOURCE_EXT          RCC_CCIPR2_I2S1SEL                               /*!< External I2S clock source selected as I2S1 clock */
00341 #else
00342 #define RCC_I2S1CLKSOURCE_SYSCLK       0x00000000U                                     /*!< SYSCLK clock selected as I2S1 clock */
00343 #define RCC_I2S1CLKSOURCE_PLL          RCC_CCIPR_I2S1SEL_0                             /*!< PLL "P" selected as I2S1 clock */
00344 #define RCC_I2S1CLKSOURCE_HSI          RCC_CCIPR_I2S1SEL_1                             /*!< HSI clock selected as I2S1 clock */
00345 #define RCC_I2S1CLKSOURCE_EXT          RCC_CCIPR_I2S1SEL                               /*!< External I2S clock source selected as I2S1 clock */
00346 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00347 /**
00348   * @}
00349   */
00350
00351 #if defined(RCC_CCIPR2_I2S2SEL)
00352 /** @defgroup RCCEx_I2S2_Clock_Source RCC I2S2 Clock Source
00353   * @{
00354   */
00355 #define RCC_I2S2CLKSOURCE_SYSCLK       0x00000000U                                      /*!< SYSCLK clock selected as I2S2 clock */
00356 #define RCC_I2S2CLKSOURCE_PLL          RCC_CCIPR2_I2S2SEL_0                             /*!< PLL "P" selected as I2S2 clock */
00357 #define RCC_I2S2CLKSOURCE_HSI          RCC_CCIPR2_I2S2SEL_1                             /*!< HSI clock selected as I2S2 clock */
00358 #define RCC_I2S2CLKSOURCE_EXT          RCC_CCIPR2_I2S2SEL                               /*!< External I2S clock source selected as I2S2 clock */
00359 /**
00360   * @}
00361   */
00362 #endif  /* RCC_CCIPR2_I2S2SEL */
00363
00364 #if defined(RCC_CCIPR_LPTIM1SEL)
00365 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
00366   * @{
00367   */
00368 #define RCC_LPTIM1CLKSOURCE_PCLK1      0x00000000U               /*!< APB clock selected as LPTimer 1 clock */
00369 #define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0     /*!< LSI clock selected as LPTimer 1 clock */
00370 #define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1     /*!< HSI clock selected as LPTimer 1 clock */
00371 #define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL       /*!< LSE clock selected as LPTimer 1 clock */
00372 /**
00373   * @}
00374   */
00375 #endif /* RCC_CCIPR_LPTIM1SEL */
00376
00377 #if defined(RCC_CCIPR_LPTIM2SEL)
00378 /** @defgroup RCCEx_LPTIM2_Clock_Source RCC LPTIM2 Clock Source
00379   * @{
00380   */
00381 #define RCC_LPTIM2CLKSOURCE_PCLK1      0x00000000U               /*!< APB clock selected as LPTimer 2 clock */
00382 #define RCC_LPTIM2CLKSOURCE_LSI        RCC_CCIPR_LPTIM2SEL_0     /*!< LSI clock selected as LPTimer 2 clock */
00383 #define RCC_LPTIM2CLKSOURCE_HSI        RCC_CCIPR_LPTIM2SEL_1     /*!< HSI clock selected as LPTimer 2 clock */
00384 #define RCC_LPTIM2CLKSOURCE_LSE        RCC_CCIPR_LPTIM2SEL       /*!< LSE clock selected as LPTimer 2 clock */
00385 /**
00386   * @}
00387   */
00388 #endif /* RCC_CCIPR_LPTIM2SEL */
00389
00390 #if defined(RNG)
00391 /** @defgroup RCCEx_RNG_Clock_Source RCC RNG Clock Source
00392   * @{
00393   */
00394 #define RCC_RNGCLKSOURCE_NONE          0x00000000U                             /*!< No clock selected */
00395 #define RCC_RNGCLKSOURCE_HSI_DIV8      RCC_CCIPR_RNGSEL_0                      /*!< HSI oscillator divided by 8 clock selected as RNG clock */
00396 #define RCC_RNGCLKSOURCE_SYSCLK        RCC_CCIPR_RNGSEL_1                      /*!< SYSCLK selected as RNG clock */
00397 #define RCC_RNGCLKSOURCE_PLL           (RCC_CCIPR_RNGSEL_0|RCC_CCIPR_RNGSEL_1) /*!< PLL "Q" selected as RNG clock */
00398
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup RCCEx_RNG_Division_factor RCC RNG Division factor
00404   * @{
00405   */
00406 #define RCC_RNGCLK_DIV1           0x00000000U                              /*!< RNG clock not divided  */
00407 #define RCC_RNGCLK_DIV2           RCC_CCIPR_RNGDIV_0                       /*!< RNG clock divided by 2 */
00408 #define RCC_RNGCLK_DIV4           RCC_CCIPR_RNGDIV_1                       /*!< RNG clock divided by 4 */
00409 #define RCC_RNGCLK_DIV8           (RCC_CCIPR_RNGDIV_0|RCC_CCIPR_RNGDIV_1)  /*!< RNG clock divided by 8 */
00410
00411 /**
00412   * @}
00413   */
00414 #endif /* RNG */
00415
00416 #if defined(FDCAN1) || defined(FDCAN2)
00417 /** @defgroup RCCEx_FDCAN_Clock_Source RCC FDCAN Clock Source
00418   * @{
00419   */
00420 #define RCC_FDCANCLKSOURCE_PCLK1        0x00000000U                        /*!< PCLK1 selected as FDCAN clock */
00421 #define RCC_FDCANCLKSOURCE_PLL          RCC_CCIPR2_FDCANSEL_0              /*!< PLL "Q" selected as FDCAN clock */
00422 #define RCC_FDCANCLKSOURCE_HSE          RCC_CCIPR2_FDCANSEL_1              /*!< HSE oscillator clock selected as FDCAN clock */
00423
00424 /**
00425   * @}
00426   */
00427 #endif /* FDCAN1 || FDCAN2 */
00428
00429 #if defined(RCC_CCIPR2_USBSEL)
00430 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
00431   * @{
00432   */
00433 #if defined(RCC_HSI48_SUPPORT)
00434 #define RCC_USBCLKSOURCE_HSI48         0x00000000U            /*!< HSI48 oscillator clock selected as USB clock */
00435 #endif /* RCC_HSI48_SUPPORT */
00436 #define RCC_USBCLKSOURCE_HSE           RCC_CCIPR2_USBSEL_0  /*!< HSE oscillator clock selected as USB clock */
00437 #define RCC_USBCLKSOURCE_PLL           RCC_CCIPR2_USBSEL_1  /*!< PLL "Q" selected as USB clock */
00438 /**
00439   * @}
00440   */
00441 #endif /* RCC_CCIPR2_USBSEL */
00442
00443 /** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source
00444   * @{
00445   */
00446
00447 #define RCC_ADCCLKSOURCE_SYSCLK       0x00000000U             /*!< SYSCLK used as ADC clock */
00448 #define RCC_ADCCLKSOURCE_PLLADC       RCC_CCIPR_ADCSEL_0      /*!< PLL "P" (PLLADC) used as ADC clock */
00449 #define RCC_ADCCLKSOURCE_HSI          RCC_CCIPR_ADCSEL_1      /*!< HSI used as ADC clock */
00450 /**
00451   * @}
00452   */
00453
00454 #if defined(CEC)
00455 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
00456   * @{
00457   */
00458 #define RCC_CECCLKSOURCE_HSI_DIV488          0x00000000U      /*!< HSI oscillator clock divided by 488 used as default CEC clock */
00459 #define RCC_CECCLKSOURCE_LSE                 RCC_CCIPR_CECSEL /*!< LSE oscillator clock  used as CEC clock */
00460 /**
00461   * @}
00462   */
00463 #endif /* CEC */
00464
00465 #if defined(RCC_CCIPR_TIM1SEL)
00466 /** @defgroup RCCEx_TIM1_Clock_Source RCC TIM1 Clock Source
00467   * @{
00468   */
00469 #define RCC_TIM1CLKSOURCE_PCLK1       0x00000000U             /*!< APB clock selected as Timer 1 clock */
00470 #define RCC_TIM1CLKSOURCE_PLL         RCC_CCIPR_TIM1SEL       /*!< PLL "Q" clock selected as Timer 1 clock */
00471 /**
00472   * @}
00473   */
00474 #endif /* RCC_CCIPR_TIM1SEL */
00475
00476 #if defined(RCC_CCIPR_TIM15SEL)
00477 /** @defgroup RCCEx_TIM15_Clock_Source RCC TIM15 Clock Source
00478   * @{
00479   */
00480 #define RCC_TIM15CLKSOURCE_PCLK1      0x00000000U             /*!< APB clock selected as Timer 15 clock */
00481 #define RCC_TIM15CLKSOURCE_PLL        RCC_CCIPR_TIM15SEL      /*!< PLL "Q" clock selected as Timer 15 clock */
00482
00483 /**
00484   * @}
00485   */
00486 #endif /* RCC_CCIPR_TIM15SEL */
00487
00488 #if defined(CRS)
00489
00490 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
00491   * @{
00492   */
00493 #define RCC_CRS_NONE                   0x00000000U
00494 #define RCC_CRS_TIMEOUT                0x00000001U
00495 #define RCC_CRS_SYNCOK                 0x00000002U
00496 #define RCC_CRS_SYNCWARN               0x00000004U
00497 #define RCC_CRS_SYNCERR                0x00000008U
00498 #define RCC_CRS_SYNCMISS               0x00000010U
00499 #define RCC_CRS_TRIMOVF                0x00000020U
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
00505   * @{
00506   */
00507 #define RCC_CRS_SYNC_SOURCE_GPIO       0x00000000U             /*!< Synchro Signal source GPIO */
00508 #define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00509 #define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00510 /**
00511   * @}
00512   */
00513
00514 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
00515   * @{
00516   */
00517 #define RCC_CRS_SYNC_DIV1        0x00000000U                               /*!< Synchro Signal not divided (default) */
00518 #define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00519 #define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00520 #define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00521 #define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00522 #define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00523 #define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00524 #define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
00530   * @{
00531   */
00532 #define RCC_CRS_SYNC_POLARITY_RISING   0x00000000U         /*!< Synchro Active on rising edge (default) */
00533 #define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL    /*!< Synchro Active on falling edge */
00534 /**
00535   * @}
00536   */
00537
00538 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
00539   * @{
00540   */
00541 #define RCC_CRS_RELOADVALUE_DEFAULT    0x0000BB7FU   /*!< The reset value of the RELOAD field corresponds
00542                                                           to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
00543 /**
00544   * @}
00545   */
00546
00547 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
00548   * @{
00549   */
00550 #define RCC_CRS_ERRORLIMIT_DEFAULT     0x00000022U   /*!< Default Frequency error limit */
00551 /**
00552   * @}
00553   */
00554
00555 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
00556   * @{
00557   */
00558 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval.
00559                                                           The trimming step is specified in the product datasheet. A higher TRIM value
00560                                                           corresponds to a higher output frequency */
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
00566   * @{
00567   */
00568 #define RCC_CRS_FREQERRORDIR_UP        0x00000000U   /*!< Upcounting direction, the actual frequency is above the target */
00569 #define RCC_CRS_FREQERRORDIR_DOWN      CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
00570 /**
00571   * @}
00572   */
00573
00574 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
00575   * @{
00576   */
00577 #define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
00578 #define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
00579 #define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
00580 #define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
00581 #define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
00582 #define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
00583 #define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE           /*!< Trimming overflow or underflow */
00584
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
00590   * @{
00591   */
00592 #define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
00593 #define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
00594 #define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
00595 #define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
00596 #define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
00597 #define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
00598 #define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
00599
00600 /**
00601   * @}
00602   */
00603
00604 #endif /* CRS */
00605
00606 /**
00607   * @}
00608   */
00609
00610 /* Exported macros -----------------------------------------------------------*/
00611 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
00612   * @{
00613   */
00614
00615
00616 /** @brief  Macro to configure the I2C1 clock (I2C1CLK).
00617   *
00618   * @param  __I2C1_CLKSOURCE__  specifies the I2C1 clock source.
00619   *          This parameter can be one of the following values:
00620   *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
00621   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
00622   */
00623 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
00624   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
00625
00626 /** @brief  Macro to get the I2C1 clock source.
00627   * @retval The clock source can be one of the following values:
00628   *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
00629   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
00630   */
00631 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
00632
00633 #if defined(RCC_CCIPR_I2C2SEL)
00634 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
00635   *
00636   * @param  __I2C2_CLKSOURCE__  specifies the I2C2 clock source.
00637   *          This parameter can be one of the following values:
00638   *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
00639   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
00640   */
00641 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
00642   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
00643
00644 /** @brief  Macro to get the I2C2 clock source.
00645   * @retval The clock source can be one of the following values:
00646   *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
00647   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
00648   */
00649 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
00650 #endif /* RCC_CCIPR_I2C2SEL */
00651
00652 /** @brief  Macro to configure the I2S1 clock (I2S1CLK).
00653   *
00654   * @param  __I2S1_CLKSOURCE__  specifies the I2S1 clock source.
00655   *          This parameter can be one of the following values:
00656   *            @arg @ref RCC_I2S1CLKSOURCE_SYSCLK  System Clock selected as I2S1 clock
00657   *            @arg @ref RCC_I2S1CLKSOURCE_PLL     PLLP Clock selected as I2S1 clock
00658   *            @arg @ref RCC_I2S1CLKSOURCE_HSI     HSI Clock selected as I2S1 clock
00659   *            @arg @ref RCC_I2S1CLKSOURCE_EXT     External clock selected as I2S1 clock
00660   */
00661 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00662 #define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \
00663   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))
00664 #else
00665 #define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \
00666   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))
00667 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00668 /** @brief  Macro to get the I2S1 clock source.
00669   * @retval The clock source can be one of the following values:
00670   *            @arg @ref RCC_I2S1CLKSOURCE_SYSCLK  System Clock selected as I2S1 clock
00671   *            @arg @ref RCC_I2S1CLKSOURCE_PLL     PLLP Clock selected as I2S1 clock
00672   *            @arg @ref RCC_I2S1CLKSOURCE_HSI     HSI Clock selected as I2S1 clock
00673   *            @arg @ref RCC_I2S1CLKSOURCE_EXT     External clock selected as I2S1 clock
00674   */
00675 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00676 #define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL)))
00677 #else
00678 #define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S1SEL)))
00679 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00680
00681 #if defined(RCC_CCIPR2_I2S2SEL)
00682 /** @brief  Macro to configure the I2S2 clock (I2S2CLK).
00683   *
00684   * @param  __I2S2_CLKSOURCE__  specifies the I2S2 clock source.
00685   *          This parameter can be one of the following values:
00686   *            @arg @ref RCC_I2S2CLKSOURCE_SYSCLK  System Clock selected as I2S2 clock
00687   *            @arg @ref RCC_I2S2CLKSOURCE_PLL     PLLP Clock selected as I2S2 clock
00688   *            @arg @ref RCC_I2S2CLKSOURCE_HSI     HSI Clock selected as I2S2 clock
00689   *            @arg @ref RCC_I2S2CLKSOURCE_EXT     External clock selected as I2S2 clock
00690   */
00691 #define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) \
00692   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__))
00693
00694 /** @brief  Macro to get the I2S2 clock source.
00695   * @retval The clock source can be one of the following values:
00696   *            @arg @ref RCC_I2S2CLKSOURCE_SYSCLK  System Clock selected as I2S2 clock
00697   *            @arg @ref RCC_I2S2CLKSOURCE_PLL     PLLP Clock selected as I2S2 clock
00698   *            @arg @ref RCC_I2S2CLKSOURCE_HSI     HSI Clock selected as I2S2 clock
00699   *            @arg @ref RCC_I2S2CLKSOURCE_EXT     External clock selected as I2S2 clock
00700   */
00701 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL)))
00702 #endif /* RCC_CCIPR2_I2S2SEL */
00703
00704 /** @brief  Macro to configure the USART1 clock (USART1CLK).
00705   *
00706   * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
00707   *          This parameter can be one of the following values:
00708   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1   PCLK1 selected as USART1 clock
00709   *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
00710   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
00711   *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
00712   */
00713 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
00714   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
00715
00716 /** @brief  Macro to get the USART1 clock source.
00717   * @retval The clock source can be one of the following values:
00718   *            @arg @ref RCC_USART1CLKSOURCE_PCLK1   PCLK1 selected as USART1 clock
00719   *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
00720   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
00721   *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
00722   */
00723 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
00724
00725 #if defined(RCC_CCIPR_USART2SEL)
00726 /** @brief  Macro to configure the USART2 clock (USART2CLK).
00727   *
00728   * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
00729   *          This parameter can be one of the following values:
00730   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1   PCLK1 selected as USART2 clock
00731   *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
00732   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
00733   *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
00734   */
00735 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
00736   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
00737
00738 /** @brief  Macro to get the USART2 clock source.
00739   * @retval The clock source can be one of the following values:
00740   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1   PCLK1 selected as USART2 clock
00741   *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
00742   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
00743   *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
00744   */
00745 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
00746 #endif /* RCC_CCIPR_USART2SEL */
00747
00748 #if defined(RCC_CCIPR_USART3SEL)
00749 /** @brief  Macro to configure the USART3 clock (USART3CLK).
00750   *
00751   * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
00752   *          This parameter can be one of the following values:
00753   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1   PCLK1 selected as USART3 clock
00754   *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
00755   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
00756   *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
00757   */
00758 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
00759   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
00760
00761 /** @brief  Macro to get the USART3 clock source.
00762   * @retval The clock source can be one of the following values:
00763   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1   PCLK1 selected as USART3 clock
00764   *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
00765   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
00766   *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
00767   */
00768 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
00769 #endif /* RCC_CCIPR_USART3SEL */
00770
00771 #if defined(RCC_CCIPR_LPUART1SEL)
00772 /** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
00773   *
00774   * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
00775   *          This parameter can be one of the following values:
00776   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1   PCLK1 selected as LPUART1 clock
00777   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
00778   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
00779   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
00780   */
00781 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
00782   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
00783
00784 /** @brief  Macro to get the LPUART1 clock source.
00785   * @retval The clock source can be one of the following values:
00786   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
00787   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
00788   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
00789   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
00790   */
00791 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
00792 #endif /* RCC_CCIPR_LPUART1SEL */
00793
00794 #if defined(RCC_CCIPR_LPUART2SEL)
00795 /** @brief  Macro to configure the LPUART2 clock (LPUART2CLK).
00796   *
00797   * @param  __LPUART2_CLKSOURCE__ specifies the LPUART2 clock source.
00798   *          This parameter can be one of the following values:
00799   *            @arg @ref RCC_LPUART2CLKSOURCE_PCLK1   PCLK1 selected as LPUART2 clock
00800   *            @arg @ref RCC_LPUART2CLKSOURCE_HSI  HSI selected as LPUART2 clock
00801   *            @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK  System Clock selected as LPUART2 clock
00802   *            @arg @ref RCC_LPUART2CLKSOURCE_LSE  LSE selected as LPUART2 clock
00803   */
00804 #define __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) \
00805   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__))
00806
00807 /** @brief  Macro to get the LPUART2 clock source.
00808   * @retval The clock source can be one of the following values:
00809   *            @arg @ref RCC_LPUART2CLKSOURCE_PCLK1  PCLK1 selected as LPUART2 clock
00810   *            @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock
00811   *            @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock
00812   *            @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock
00813   */
00814 #define __HAL_RCC_GET_LPUART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART2SEL)))
00815 #endif /* RCC_CCIPR_LPUART2SEL */
00816
00817 #if defined(RCC_CCIPR_LPTIM1SEL)
00818 /** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
00819   *
00820   * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
00821   *          This parameter can be one of the following values:
00822   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPTIM1 clock
00823   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI  selected as LPTIM1 clock
00824   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI  selected as LPTIM1 clock
00825   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE  selected as LPTIM1 clock
00826   */
00827 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
00828   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
00829
00830 /** @brief  Macro to get the LPTIM1 clock source.
00831   * @retval The clock source can be one of the following values:
00832   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
00833   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock
00834   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock
00835   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock
00836   */
00837 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
00838 #endif /* RCC_CCIPR_LPTIM1SEL */
00839
00840 #if defined(RCC_CCIPR_LPTIM2SEL)
00841 /** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).
00842   *
00843   * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
00844   *          This parameter can be one of the following values:
00845   *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK1 selected as LPTIM2 clock
00846   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI  selected as LPTIM2 clock
00847   *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  LSI  selected as LPTIM2 clock
00848   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE  selected as LPTIM2 clock
00849   */
00850 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
00851   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
00852
00853 /** @brief  Macro to get the LPTIM2 clock source.
00854   * @retval The clock source can be one of the following values:
00855   *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK1 selected as LPTIM2 clock
00856   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPTIM2 clock
00857   *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  System Clock selected as LPTIM2 clock
00858   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPTIM2 clock
00859   */
00860 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
00861 #endif /* RCC_CCIPR_LPTIM2SEL */
00862
00863 #if defined(CEC)
00864 /** @brief  Macro to configure the CEC clock (CECCLK).
00865   *
00866   * @param  __CEC_CLKSOURCE__ specifies the CEC clock source.
00867   *          This parameter can be one of the following values:
00868   *            @arg @ref RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 selected as CEC clock
00869   *            @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
00870   */
00871 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
00872   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
00873
00874 /** @brief  Macro to get the CEC clock source.
00875   * @retval The clock source can be one of the following values:
00876   *            @arg @ref RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 Clock selected as CEC clock
00877   *            @arg @ref RCC_CECCLKSOURCE_LSE  LSE selected as CEC clock
00878   */
00879 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CECSEL)))
00880 #endif /* CEC */
00881
00882 #if defined(RNG)
00883 /** @brief  Macro to configure the RNG clock.
00884   *
00885   *
00886   * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
00887   *         This parameter can be one of the following values:
00888   *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock
00889   *            @arg @ref RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divided by 8 selected as RNG clock
00890   *            @arg @ref RCC_RNGCLKSOURCE_SYSCLK System Clock selected as RNG clock
00891   *            @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock
00892   */
00893 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
00894   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__))
00895
00896 /** @brief  Macro to get the RNG clock.
00897   * @retval The clock source can be one of the following values:
00898   *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock
00899   *            @arg @ref RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divide by 8 selected as RNG clock
00900   *            @arg @ref RCC_RNGCLKSOURCE_SYSCLK System clock selected as RNG clock
00901   *            @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock
00902   */
00903 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL)))
00904
00905 /** @brief  Macro to configure the RNG clock.
00906   *
00907   *
00908   * @param  __RNG_CLKDIV__ specifies the RNG clock division factor.
00909   *         This parameter can be one of the following values:
00910   *            @arg @ref RCC_RNGCLK_DIV1  RNG Clock not divided
00911   *            @arg @ref RCC_RNGCLK_DIV2  RNG Clock divided by 2
00912   *            @arg @ref RCC_RNGCLK_DIV4  RNG Clock divided by 4
00913   *            @arg @ref RCC_RNGCLK_DIV8  RNG Clock divided by 8
00914   */
00915 #define __HAL_RCC_RNGDIV_CONFIG(__RNG_CLKDIV__) \
00916   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__))
00917
00918 /** @brief  Macro to get the RNG clock division factor.
00919   * @retval The division factor can be one of the following values:
00920   *            @arg @ref RCC_RNGCLK_DIV1   RNG Clock not divided
00921   *            @arg @ref RCC_RNGCLK_DIV2   RNG Clock divided by 2
00922   *            @arg @ref RCC_RNGCLK_DIV4   RNG Clock divided by 4
00923   *            @arg @ref RCC_RNGCLK_DIV8   RNG Clock divided by 8
00924   */
00925 #define __HAL_RCC_GET_RNG_DIV() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)))
00926 #endif /* RNG */
00927
00928 /** @brief  Macro to configure the ADC interface clock
00929   * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
00930   *         This parameter can be one of the following values:
00931   *            @arg @ref RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock
00932   *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
00933   *            @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock
00934   */
00935 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
00936   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
00937
00938 /** @brief  Macro to get the ADC clock source.
00939   * @retval The clock source can be one of the following values:
00940   *            @arg @ref RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock
00941   *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
00942   *            @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock
00943   */
00944 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
00945
00946 #if defined(RCC_CCIPR_TIM1SEL)
00947 /** @brief  Macro to configure the TIM1 interface clock
00948   * @param  __TIM1_CLKSOURCE__ specifies the TIM1 digital interface clock source.
00949   *         This parameter can be one of the following values:
00950   *            @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock
00951   *            @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock
00952   */
00953 #define __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) \
00954   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__))
00955
00956 /** @brief  Macro to get the TIM1 clock source.
00957   * @retval The clock source can be one of the following values:
00958   *            @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock
00959   *            @arg @ref RCC_TIM1CLKSOURCE_PCLK1  System Clock selected as TIM1 clock
00960   */
00961 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL)))
00962 #endif /* RCC_CCIPR_TIM1SEL */
00963
00964 #if defined(RCC_CCIPR_TIM15SEL)
00965 /** @brief  Macro to configure the TIM15 interface clock
00966   * @param  __TIM15_CLKSOURCE__ specifies the TIM15 digital interface clock source.
00967   *         This parameter can be one of the following values:
00968   *            @arg RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock
00969   *            @arg RCC_TIM15CLKSOURCE_PCLK1  System Clock selected as TIM15 clock
00970   */
00971 #define __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) \
00972   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__))
00973
00974 /** @brief  Macro to get the TIM15 clock source.
00975   * @retval The clock source can be one of the following values:
00976   *            @arg @ref RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock
00977   *            @arg @ref RCC_TIM15CLKSOURCE_PCLK1  System Clock selected as TIM15 clock
00978   */
00979 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL)))
00980 #endif /* RCC_CCIPR_TIM15SEL */
00981
00982 #if defined(RCC_CCIPR2_USBSEL)
00983 /** @brief  Macro to configure the USB interface clock
00984   * @param  __USB_CLKSOURCE__ specifies the USB digital interface clock source.
00985   *         This parameter can be one of the following values:
00986   *            @arg @ref RCC_USBCLKSOURCE_PLL    PLLQ Output Clock selected as USB clock (*)
00987   *            @arg @ref RCC_USBCLKSOURCE_HSE    HSE Output Clock selected as USB clock
00988   *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 Clock selected as USB clock (*)
00989   *  (*) Feature not available on all devices
00990   */
00991 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
00992   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__))
00993
00994 /** @brief  Macro to get the USB clock source.
00995   * @retval The clock source can be one of the following values:
00996   *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 Clock selected as USB clock
00997   *            @arg @ref RCC_USBCLKSOURCE_HSE    HSE Output Clock selected as USB clock
00998   *            @arg @ref RCC_USBCLKSOURCE_PLL    PLLQ Output Clock selected as USB clock
00999   */
01000 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL)))
01001 #endif /* RCC_CCIPR2_USBSEL */
01002
01003 #if defined(FDCAN1) || defined(FDCAN2)
01004 /** @brief  Macro to configure the FDCAN interface clock
01005   * @param  __FDCAN_CLKSOURCE__ specifies the FDCAN digital interface clock source.
01006   *         This parameter can be one of the following values:
01007   *            @arg RCC_FDCANCLKSOURCE_PLL    PLLQ Output Clock selected as FDCAN clock
01008   *            @arg RCC_FDCANCLKSOURCE_PCLK1  System Clock selected as FDCAN clock
01009   *            @arg RCC_FDCANCLKSOURCE_HSE    HSE Clock selected as FDCAN clock
01010   */
01011 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \
01012   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
01013
01014 /** @brief  Macro to get the FDCAN clock source.
01015   * @retval The clock source can be one of the following values:
01016   *            @arg @ref RCC_FDCANCLKSOURCE_PLL    PLLQ Output Clock selected as FDCAN clock
01017   *            @arg @ref RCC_FDCANCLKSOURCE_PCLK1  System Clock selected as FDCAN clock
01018   *            @arg @ref RCC_FDCANCLKSOURCE_HSE    HSE Clock selected as FDCAN clock
01019   */
01020 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL)))
01021 #endif /* FDCAN1 || FDCAN2 */
01022
01023 #if defined(CRS)
01024
01025 /**
01026   * @brief  Enable the specified CRS interrupts.
01027   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
01028   *          This parameter can be any combination of the following values:
01029   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01030   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01031   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01032   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01033   * @retval None
01034   */
01035 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
01036
01037 /**
01038   * @brief  Disable the specified CRS interrupts.
01039   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
01040   *          This parameter can be any combination of the following values:
01041   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01042   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01043   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01044   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01045   * @retval None
01046   */
01047 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
01048
01049 /** @brief  Check whether the CRS interrupt has occurred or not.
01050   * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
01051   *         This parameter can be one of the following values:
01052   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01053   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01054   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01055   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01056   * @retval The new state of __INTERRUPT__ (SET or RESET).
01057   */
01058 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
01059
01060 /** @brief  Clear the CRS interrupt pending bits
01061   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01062   *         This parameter can be any combination of the following values:
01063   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01064   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01065   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01066   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01067   *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
01068   *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
01069   *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
01070   */
01071 /* CRS IT Error Mask */
01072 #define  RCC_CRS_IT_ERROR_MASK                 (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
01073
01074 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
01075                                                     if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
01076                                                     { \
01077                                                       WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
01078                                                     } \
01079                                                     else \
01080                                                     { \
01081                                                       WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
01082                                                     } \
01083                                                   } while(0)
01084
01085 /**
01086   * @brief  Check whether the specified CRS flag is set or not.
01087   * @param  __FLAG__ specifies the flag to check.
01088   *          This parameter can be one of the following values:
01089   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01090   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01091   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01092   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01093   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01094   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01095   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01096   * @retval The new state of _FLAG_ (TRUE or FALSE).
01097   */
01098 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
01099
01100 /**
01101   * @brief  Clear the CRS specified FLAG.
01102   * @param __FLAG__ specifies the flag to clear.
01103   *          This parameter can be one of the following values:
01104   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01105   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01106   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01107   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01108   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01109   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01110   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01111   * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
01112   * @retval None
01113   */
01114
01115 /* CRS Flag Error Mask */
01116 #define RCC_CRS_FLAG_ERROR_MASK                (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
01117
01118 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
01119                                                     if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
01120                                                     { \
01121                                                       WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
01122                                                     } \
01123                                                     else \
01124                                                     { \
01125                                                       WRITE_REG(CRS->ICR, (__FLAG__)); \
01126                                                     } \
01127                                                   } while(0)
01128
01129 #endif /* CRS */
01130
01131 /**
01132   * @}
01133   */
01134
01135 #if defined(CRS)
01136
01137 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
01138   * @{
01139   */
01140 /**
01141   * @brief  Enable the oscillator clock for frequency error counter.
01142   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
01143   * @retval None
01144   */
01145 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
01146
01147 /**
01148   * @brief  Disable the oscillator clock for frequency error counter.
01149   * @retval None
01150   */
01151 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
01152
01153 /**
01154   * @brief  Enable the automatic hardware adjustment of TRIM bits.
01155   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
01156   * @retval None
01157   */
01158 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
01159
01160 /**
01161   * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
01162   * @retval None
01163   */
01164 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
01165
01166 /**
01167   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
01168   * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
01169   *             of the synchronization source after prescaling. It is then decreased by one in order to
01170   *             reach the expected synchronization on the zero value. The formula is the following:
01171   *             RELOAD = (fTARGET / fSYNC) -1
01172   * @param  __FTARGET__ Target frequency (value in Hz)
01173   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
01174   * @retval None
01175   */
01176 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
01177
01178 /**
01179   * @}
01180   */
01181
01182 #endif /* CRS */
01183
01184 /* Exported functions --------------------------------------------------------*/
01185 /** @addtogroup RCCEx_Exported_Functions
01186   * @{
01187   */
01188
01189 /** @addtogroup RCCEx_Exported_Functions_Group1
01190   * @{
01191   */
01192
01193 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01194 void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01195 uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
01196
01197 /**
01198   * @}
01199   */
01200
01201 /** @addtogroup RCCEx_Exported_Functions_Group2
01202   * @{
01203   */
01204
01205 void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
01206 void              HAL_RCCEx_DisableLSCO(void);
01207
01208 /**
01209   * @}
01210   */
01211
01212 #if defined(CRS)
01213
01214 /** @addtogroup RCCEx_Exported_Functions_Group3
01215   * @{
01216   */
01217
01218 void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
01219 void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
01220 void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
01221 uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
01222 void              HAL_RCCEx_CRS_IRQHandler(void);
01223 void              HAL_RCCEx_CRS_SyncOkCallback(void);
01224 void              HAL_RCCEx_CRS_SyncWarnCallback(void);
01225 void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
01226 void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
01227
01228 /**
01229   * @}
01230   */
01231
01232 #endif /* CRS */
01233
01234 /**
01235   * @}
01236   */
01237
01238 /* Private macros ------------------------------------------------------------*/
01239 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
01240   * @{
01241   */
01242
01243 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
01244                                        ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
01245
01246 #if defined(STM32G0C1xx)
01247
01248 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01249   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01250    (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01251    (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01252    (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01253    (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \
01254    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01255    (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01256    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01257    (((__SELECTION__) & RCC_PERIPHCLK_I2S2)    == RCC_PERIPHCLK_I2S2)    || \
01258    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01259    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01260    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01261    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01262    (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01263    (((__SELECTION__) & RCC_PERIPHCLK_CEC)     == RCC_PERIPHCLK_CEC)     || \
01264    (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)   == RCC_PERIPHCLK_FDCAN)   || \
01265    (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
01266    (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1)    || \
01267    (((__SELECTION__) & RCC_PERIPHCLK_TIM15)   == RCC_PERIPHCLK_TIM15))
01268
01269 #elif defined(STM32G0B1xx)
01270
01271 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01272   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01273    (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01274    (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01275    (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01276    (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \
01277    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01278    (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01279    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01280    (((__SELECTION__) & RCC_PERIPHCLK_I2S2)    == RCC_PERIPHCLK_I2S2)    || \
01281    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01282    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01283    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01284    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01285    (((__SELECTION__) & RCC_PERIPHCLK_CEC)     == RCC_PERIPHCLK_CEC)     || \
01286    (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)   == RCC_PERIPHCLK_FDCAN)   || \
01287    (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
01288    (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1)    || \
01289    (((__SELECTION__) & RCC_PERIPHCLK_TIM15)   == RCC_PERIPHCLK_TIM15))
01290
01291 #elif defined(STM32G0B0xx)
01292
01293 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01294   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01295    (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01296    (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01297    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01298    (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01299    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01300    (((__SELECTION__) & RCC_PERIPHCLK_I2S2)    == RCC_PERIPHCLK_I2S2)    || \
01301    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01302    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01303    (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB))
01304
01305 #elif defined(STM32G081xx)
01306 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01307   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01308    (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01309    (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01310    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01311    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01312    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01313    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01314    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01315    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01316    (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01317    (((__SELECTION__) & RCC_PERIPHCLK_CEC)     == RCC_PERIPHCLK_CEC)     || \
01318    (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1)    || \
01319    (((__SELECTION__) & RCC_PERIPHCLK_TIM15)   == RCC_PERIPHCLK_TIM15))
01320 #elif defined(STM32G071xx)
01321
01322 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01323   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01324    (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01325    (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01326    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01327    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01328    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01329    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01330    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01331    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01332    (((__SELECTION__) & RCC_PERIPHCLK_CEC)     == RCC_PERIPHCLK_CEC)     || \
01333    (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1)    || \
01334    (((__SELECTION__) & RCC_PERIPHCLK_TIM15)   == RCC_PERIPHCLK_TIM15))
01335
01336 #elif defined(STM32G070xx)
01337
01338 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01339   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01340    (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01341    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01342    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01343    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01344    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC))
01345
01346 #elif defined(STM32G061xx)
01347
01348 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01349   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01350    (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01351    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01352    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01353    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01354    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01355    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01356    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01357    (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01358    (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1)    || \
01359    (((__SELECTION__) & RCC_PERIPHCLK_TIM15)   == RCC_PERIPHCLK_TIM15))
01360
01361 #elif defined(STM32G051xx)
01362
01363 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01364   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01365    (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01366    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01367    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01368    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01369    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01370    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01371    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01372    (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1)    || \
01373    (((__SELECTION__) & RCC_PERIPHCLK_TIM15)   == RCC_PERIPHCLK_TIM15))
01374
01375 #elif defined(STM32G041xx)
01376
01377 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01378   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01379    (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01380    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01381    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01382    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01383    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01384    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01385    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01386    (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01387    (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1))
01388
01389 #elif defined(STM32G031xx)
01390
01391 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01392   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01393    (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01394    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01395    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01396    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01397    (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01398    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01399    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01400    (((__SELECTION__) & RCC_PERIPHCLK_TIM1)    == RCC_PERIPHCLK_TIM1))
01401
01402 #elif defined(STM32G030xx) || defined(STM32G050xx)
01403
01404 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01405   ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01406    (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01407    (((__SELECTION__) & RCC_PERIPHCLK_I2S1)    == RCC_PERIPHCLK_I2S1)    || \
01408    (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01409    (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC))
01410 #endif /* STM32G0C1xx */
01411
01412 #define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \
01413   (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1)  || \
01414    ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
01415    ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
01416    ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
01417
01418 #if defined(RCC_CCIPR_USART2SEL)
01419 #define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \
01420   (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
01421    ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
01422    ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
01423    ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
01424 #endif /* RCC_CCIPR_USART2SEL */
01425
01426 #if defined(RCC_CCIPR_USART3SEL)
01427 #define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \
01428   (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
01429    ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
01430    ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
01431    ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
01432 #endif /* RCC_CCIPR_USART3SEL */
01433
01434 #if defined(LPUART1)
01435 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \
01436   (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
01437    ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
01438    ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
01439    ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
01440 #endif /* LPUART1 */
01441
01442 #if defined(LPUART2)
01443 #define IS_RCC_LPUART2CLKSOURCE(__SOURCE__)  \
01444   (((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1)  || \
01445    ((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \
01446    ((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE)    || \
01447    ((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI))
01448 #endif /* LPUART2 */
01449
01450 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \
01451   (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1)   || \
01452    ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)  || \
01453    ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
01454
01455 #if defined(RCC_CCIPR_I2C2SEL)
01456 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \
01457   (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1)   || \
01458    ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)  || \
01459    ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
01460
01461 #endif /* RCC_CCIPR_I2C2SEL */
01462
01463 #define IS_RCC_I2S1CLKSOURCE(__SOURCE__)   \
01464   (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \
01465    ((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL)   || \
01466    ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI)   || \
01467    ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT))
01468
01469 #if defined(RCC_CCIPR2_I2S2SEL)
01470 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__)   \
01471   (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \
01472    ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL)   || \
01473    ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI)   || \
01474    ((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT))
01475 #endif /* RCC_CCIPR2_I2S2SEL */
01476
01477 #if defined(RCC_CCIPR_LPTIM1SEL)
01478 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__)  \
01479   (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \
01480    ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
01481    ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
01482    ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
01483 #endif /* RCC_CCIPR_LPTIM1SEL */
01484
01485 #if defined(RCC_CCIPR_LPTIM2SEL)
01486 #define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__)  \
01487   (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \
01488    ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
01489    ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
01490    ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
01491 #endif /* RCC_CCIPR_LPTIM2SEL */
01492
01493 #define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
01494   (((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC)  || \
01495    ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)  || \
01496    ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI))
01497
01498 #if defined(RNG)
01499 #define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
01500   (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)         || \
01501    ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8)     || \
01502    ((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK)       || \
01503    ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
01504 #define IS_RCC_RNGDIV(__DIV__)  \
01505   (((__DIV__) == RCC_RNGCLK_DIV1) || \
01506    ((__DIV__) == RCC_RNGCLK_DIV2) || \
01507    ((__DIV__) == RCC_RNGCLK_DIV4) || \
01508    ((__DIV__) == RCC_RNGCLK_DIV8))
01509 #endif /* RNG */
01510
01511 #if defined(CEC)
01512 #define IS_RCC_CECCLKSOURCE(__SOURCE__)  \
01513   (((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \
01514    ((__SOURCE__) == RCC_CECCLKSOURCE_LSE))
01515 #endif /* CEC */
01516
01517 #if defined(FDCAN1) || defined(FDCAN2)
01518 #define IS_RCC_FDCANCLKSOURCE(__SOURCE__)  \
01519   (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \
01520    ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \
01521    ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
01522
01523 #endif /* FDCAN1 */
01524
01525 #if defined(RCC_HSI48_SUPPORT)
01526 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
01527   (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \
01528    ((__SOURCE__) == RCC_USBCLKSOURCE_HSE)  || \
01529    ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
01530 #else
01531 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
01532   (((__SOURCE__) == RCC_USBCLKSOURCE_HSE)|| \
01533    ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
01534 #endif /* RCC_HSI48_SUPPORT */
01535
01536 #if defined(RCC_CCIPR_TIM1SEL)
01537 #define IS_RCC_TIM1CLKSOURCE(__SOURCE__)  \
01538   (((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL)     || \
01539    ((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1))
01540 #endif /* RCC_CCIPR_TIM1SEL */
01541
01542 #if defined(RCC_CCIPR_TIM15SEL)
01543 #define IS_RCC_TIM15CLKSOURCE(__SOURCE__)  \
01544   (((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL)     || \
01545    ((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1))
01546 #endif /* RCC_CCIPR_TIM15SEL */
01547
01548 #if defined(CRS)
01549
01550 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
01551                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
01552                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
01553
01554 #define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
01555                                             ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
01556                                             ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
01557                                             ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
01558
01559 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
01560                                                 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
01561
01562 #define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
01563
01564 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
01565
01566 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU))
01567
01568 #define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
01569                                             ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
01570
01571 #endif /* CRS */
01572
01573 /**
01574   * @}
01575   */
01576
01577 /**
01578   * @}
01579   */
01580
01581 /**
01582   * @}
01583   */
01584
01585 #ifdef __cplusplus
01586 }
01587 #endif
01588
01589 #endif /* STM32G0xx_HAL_RCC_EX_H */
01590
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rng.c Source File

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stm32g0xx_hal_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rng.c
00004   * @author  MCD Application Team
00005   * @brief   RNG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Random Number Generator (RNG) peripheral:
00008   *           + Initialization and configuration functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                      ##### How to use this driver #####
00026   ==============================================================================
00027   [..]
00028       The RNG HAL driver can be used as follows:
00029
00030       (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
00031           in HAL_RNG_MspInit().
00032       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
00033       (#) Wait until the 32 bit Random Number Generator contains a valid
00034           random data using (polling/interrupt) mode.
00035       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
00036
00037     ##### Callback registration #####
00038     ==================================
00039
00040     [..]
00041     The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
00042     allows the user to configure dynamically the driver callbacks.
00043
00044     [..]
00045     Use Function HAL_RNG_RegisterCallback() to register a user callback.
00046     Function HAL_RNG_RegisterCallback() allows to register following callbacks:
00047     (+) ErrorCallback             : RNG Error Callback.
00048     (+) MspInitCallback           : RNG MspInit.
00049     (+) MspDeInitCallback         : RNG MspDeInit.
00050     This function takes as parameters the HAL peripheral handle, the Callback ID
00051     and a pointer to the user callback function.
00052
00053     [..]
00054     Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
00055     weak (surcharged) function.
00056     HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00057     and the Callback ID.
00058     This function allows to reset following callbacks:
00059     (+) ErrorCallback             : RNG Error Callback.
00060     (+) MspInitCallback           : RNG MspInit.
00061     (+) MspDeInitCallback         : RNG MspDeInit.
00062
00063     [..]
00064     For specific callback ReadyDataCallback, use dedicated register callbacks:
00065     respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
00066
00067     [..]
00068     By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
00069     all callbacks are set to the corresponding weak (surcharged) functions:
00070     example HAL_RNG_ErrorCallback().
00071     Exception done for MspInit and MspDeInit functions that are respectively
00072     reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
00073     and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
00074     If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
00075     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00076
00077     [..]
00078     Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
00079     Exception done MspInit/MspDeInit that can be registered/unregistered
00080     in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
00081     MspInit/DeInit callbacks can be used during the Init/DeInit.
00082     In that case first register the MspInit/MspDeInit user callbacks
00083     using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
00084     or HAL_RNG_Init() function.
00085
00086     [..]
00087     When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
00088     not defined, the callback registration feature is not available
00089     and weak (surcharged) callbacks are used.
00090
00091   @endverbatim
00092   ******************************************************************************
00093   */
00094
00095 /* Includes ------------------------------------------------------------------*/
00096 #include "stm32g0xx_hal.h"
00097
00098 /** @addtogroup STM32G0xx_HAL_Driver
00099   * @{
00100   */
00101
00102 #if defined (RNG)
00103
00104 /** @addtogroup RNG
00105   * @brief RNG HAL module driver.
00106   * @{
00107   */
00108
00109 #ifdef HAL_RNG_MODULE_ENABLED
00110
00111 /* Private types -------------------------------------------------------------*/
00112 /* Private defines -----------------------------------------------------------*/
00113 /* Private variables ---------------------------------------------------------*/
00114 /* Private constants ---------------------------------------------------------*/
00115 /** @defgroup RNG_Private_Constants RNG Private Constants
00116   * @{
00117   */
00118 #define RNG_TIMEOUT_VALUE     2U
00119 /**
00120   * @}
00121   */
00122 /* Private macros ------------------------------------------------------------*/
00123 /* Private functions prototypes ----------------------------------------------*/
00124 /* Private functions ---------------------------------------------------------*/
00125 /* Exported functions --------------------------------------------------------*/
00126
00127 /** @addtogroup RNG_Exported_Functions
00128   * @{
00129   */
00130
00131 /** @addtogroup RNG_Exported_Functions_Group1
00132   *  @brief   Initialization and configuration functions
00133   *
00134 @verbatim
00135  ===============================================================================
00136           ##### Initialization and configuration functions #####
00137  ===============================================================================
00138     [..]  This section provides functions allowing to:
00139       (+) Initialize the RNG according to the specified parameters
00140           in the RNG_InitTypeDef and create the associated handle
00141       (+) DeInitialize the RNG peripheral
00142       (+) Initialize the RNG MSP
00143       (+) DeInitialize RNG MSP
00144
00145 @endverbatim
00146   * @{
00147   */
00148
00149 /**
00150   * @brief  Initializes the RNG peripheral and creates the associated handle.
00151   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00152   *                the configuration information for RNG.
00153   * @retval HAL status
00154   */
00155 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
00156 {
00157   /* Check the RNG handle allocation */
00158   if (hrng == NULL)
00159   {
00160     return HAL_ERROR;
00161   }
00162   /* Check the parameters */
00163   assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
00164   assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
00165
00166 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00167   if (hrng->State == HAL_RNG_STATE_RESET)
00168   {
00169     /* Allocate lock resource and initialize it */
00170     hrng->Lock = HAL_UNLOCKED;
00171
00172     hrng->ReadyDataCallback  = HAL_RNG_ReadyDataCallback;  /* Legacy weak ReadyDataCallback  */
00173     hrng->ErrorCallback      = HAL_RNG_ErrorCallback;      /* Legacy weak ErrorCallback      */
00174
00175     if (hrng->MspInitCallback == NULL)
00176     {
00177       hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit  */
00178     }
00179
00180     /* Init the low level hardware */
00181     hrng->MspInitCallback(hrng);
00182   }
00183 #else
00184   if (hrng->State == HAL_RNG_STATE_RESET)
00185   {
00186     /* Allocate lock resource and initialize it */
00187     hrng->Lock = HAL_UNLOCKED;
00188
00189     /* Init the low level hardware */
00190     HAL_RNG_MspInit(hrng);
00191   }
00192 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00193
00194   /* Change RNG peripheral state */
00195   hrng->State = HAL_RNG_STATE_BUSY;
00196
00197   /* Clock Error Detection Configuration */
00198   MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
00199
00200   /* Enable the RNG Peripheral */
00201   __HAL_RNG_ENABLE(hrng);
00202
00203   /* Initialize the RNG state */
00204   hrng->State = HAL_RNG_STATE_READY;
00205
00206   /* Initialise the error code */
00207   hrng->ErrorCode = HAL_RNG_ERROR_NONE;
00208
00209   /* Return function status */
00210   return HAL_OK;
00211 }
00212
00213 /**
00214   * @brief  DeInitializes the RNG peripheral.
00215   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00216   *                the configuration information for RNG.
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
00220 {
00221   /* Check the RNG handle allocation */
00222   if (hrng == NULL)
00223   {
00224     return HAL_ERROR;
00225   }
00226
00227   /* Clear Clock Error Detection bit */
00228   CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
00229   /* Disable the RNG Peripheral */
00230   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
00231
00232   /* Clear RNG interrupt status flags */
00233   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
00234
00235 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00236   if (hrng->MspDeInitCallback == NULL)
00237   {
00238     hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit  */
00239   }
00240
00241   /* DeInit the low level hardware */
00242   hrng->MspDeInitCallback(hrng);
00243 #else
00244   /* DeInit the low level hardware */
00245   HAL_RNG_MspDeInit(hrng);
00246 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00247
00248   /* Update the RNG state */
00249   hrng->State = HAL_RNG_STATE_RESET;
00250
00251   /* Initialise the error code */
00252   hrng->ErrorCode = HAL_RNG_ERROR_NONE;
00253
00254   /* Release Lock */
00255   __HAL_UNLOCK(hrng);
00256
00257   /* Return the function status */
00258   return HAL_OK;
00259 }
00260
00261 /**
00262   * @brief  Initializes the RNG MSP.
00263   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00264   *                the configuration information for RNG.
00265   * @retval None
00266   */
00267 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
00268 {
00269   /* Prevent unused argument(s) compilation warning */
00270   UNUSED(hrng);
00271   /* NOTE : This function should not be modified. When the callback is needed,
00272             function HAL_RNG_MspInit must be implemented in the user file.
00273    */
00274 }
00275
00276 /**
00277   * @brief  DeInitializes the RNG MSP.
00278   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00279   *                the configuration information for RNG.
00280   * @retval None
00281   */
00282 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
00283 {
00284   /* Prevent unused argument(s) compilation warning */
00285   UNUSED(hrng);
00286   /* NOTE : This function should not be modified. When the callback is needed,
00287             function HAL_RNG_MspDeInit must be implemented in the user file.
00288    */
00289 }
00290
00291 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00292 /**
00293   * @brief  Register a User RNG Callback
00294   *         To be used instead of the weak predefined callback
00295   * @param  hrng RNG handle
00296   * @param  CallbackID ID of the callback to be registered
00297   *         This parameter can be one of the following values:
00298   *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
00299   *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
00300   *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
00301   * @param  pCallback pointer to the Callback function
00302   * @retval HAL status
00303   */
00304 HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
00305                                            pRNG_CallbackTypeDef pCallback)
00306 {
00307   HAL_StatusTypeDef status = HAL_OK;
00308
00309   if (pCallback == NULL)
00310   {
00311     /* Update the error code */
00312     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00313     return HAL_ERROR;
00314   }
00315   /* Process locked */
00316   __HAL_LOCK(hrng);
00317
00318   if (HAL_RNG_STATE_READY == hrng->State)
00319   {
00320     switch (CallbackID)
00321     {
00322       case HAL_RNG_ERROR_CB_ID :
00323         hrng->ErrorCallback = pCallback;
00324         break;
00325
00326       case HAL_RNG_MSPINIT_CB_ID :
00327         hrng->MspInitCallback = pCallback;
00328         break;
00329
00330       case HAL_RNG_MSPDEINIT_CB_ID :
00331         hrng->MspDeInitCallback = pCallback;
00332         break;
00333
00334       default :
00335         /* Update the error code */
00336         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00337         /* Return error status */
00338         status =  HAL_ERROR;
00339         break;
00340     }
00341   }
00342   else if (HAL_RNG_STATE_RESET == hrng->State)
00343   {
00344     switch (CallbackID)
00345     {
00346       case HAL_RNG_MSPINIT_CB_ID :
00347         hrng->MspInitCallback = pCallback;
00348         break;
00349
00350       case HAL_RNG_MSPDEINIT_CB_ID :
00351         hrng->MspDeInitCallback = pCallback;
00352         break;
00353
00354       default :
00355         /* Update the error code */
00356         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00357         /* Return error status */
00358         status =  HAL_ERROR;
00359         break;
00360     }
00361   }
00362   else
00363   {
00364     /* Update the error code */
00365     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00366     /* Return error status */
00367     status =  HAL_ERROR;
00368   }
00369
00370   /* Release Lock */
00371   __HAL_UNLOCK(hrng);
00372   return status;
00373 }
00374
00375 /**
00376   * @brief  Unregister an RNG Callback
00377   *         RNG callback is redirected to the weak predefined callback
00378   * @param  hrng RNG handle
00379   * @param  CallbackID ID of the callback to be unregistered
00380   *         This parameter can be one of the following values:
00381   *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
00382   *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
00383   *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
00387 {
00388   HAL_StatusTypeDef status = HAL_OK;
00389
00390   /* Process locked */
00391   __HAL_LOCK(hrng);
00392
00393   if (HAL_RNG_STATE_READY == hrng->State)
00394   {
00395     switch (CallbackID)
00396     {
00397       case HAL_RNG_ERROR_CB_ID :
00398         hrng->ErrorCallback = HAL_RNG_ErrorCallback;          /* Legacy weak ErrorCallback  */
00399         break;
00400
00401       case HAL_RNG_MSPINIT_CB_ID :
00402         hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
00403         break;
00404
00405       case HAL_RNG_MSPDEINIT_CB_ID :
00406         hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspDeInit  */
00407         break;
00408
00409       default :
00410         /* Update the error code */
00411         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00412         /* Return error status */
00413         status =  HAL_ERROR;
00414         break;
00415     }
00416   }
00417   else if (HAL_RNG_STATE_RESET == hrng->State)
00418   {
00419     switch (CallbackID)
00420     {
00421       case HAL_RNG_MSPINIT_CB_ID :
00422         hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
00423         break;
00424
00425       case HAL_RNG_MSPDEINIT_CB_ID :
00426         hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspInit  */
00427         break;
00428
00429       default :
00430         /* Update the error code */
00431         hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00432         /* Return error status */
00433         status =  HAL_ERROR;
00434         break;
00435     }
00436   }
00437   else
00438   {
00439     /* Update the error code */
00440     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00441     /* Return error status */
00442     status =  HAL_ERROR;
00443   }
00444
00445   /* Release Lock */
00446   __HAL_UNLOCK(hrng);
00447   return status;
00448 }
00449
00450 /**
00451   * @brief  Register Data Ready RNG Callback
00452   *         To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
00453   * @param  hrng RNG handle
00454   * @param  pCallback pointer to the Data Ready Callback function
00455   * @retval HAL status
00456   */
00457 HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
00458 {
00459   HAL_StatusTypeDef status = HAL_OK;
00460
00461   if (pCallback == NULL)
00462   {
00463     /* Update the error code */
00464     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00465     return HAL_ERROR;
00466   }
00467   /* Process locked */
00468   __HAL_LOCK(hrng);
00469
00470   if (HAL_RNG_STATE_READY == hrng->State)
00471   {
00472     hrng->ReadyDataCallback = pCallback;
00473   }
00474   else
00475   {
00476     /* Update the error code */
00477     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00478     /* Return error status */
00479     status =  HAL_ERROR;
00480   }
00481
00482   /* Release Lock */
00483   __HAL_UNLOCK(hrng);
00484   return status;
00485 }
00486
00487 /**
00488   * @brief  UnRegister the Data Ready RNG Callback
00489   *         Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
00490   * @param  hrng RNG handle
00491   * @retval HAL status
00492   */
00493 HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
00494 {
00495   HAL_StatusTypeDef status = HAL_OK;
00496
00497   /* Process locked */
00498   __HAL_LOCK(hrng);
00499
00500   if (HAL_RNG_STATE_READY == hrng->State)
00501   {
00502     hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback  */
00503   }
00504   else
00505   {
00506     /* Update the error code */
00507     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00508     /* Return error status */
00509     status =  HAL_ERROR;
00510   }
00511
00512   /* Release Lock */
00513   __HAL_UNLOCK(hrng);
00514   return status;
00515 }
00516
00517 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00518
00519 /**
00520   * @}
00521   */
00522
00523 /** @addtogroup RNG_Exported_Functions_Group2
00524   *  @brief   Peripheral Control functions
00525   *
00526 @verbatim
00527  ===============================================================================
00528                       ##### Peripheral Control functions #####
00529  ===============================================================================
00530     [..]  This section provides functions allowing to:
00531       (+) Get the 32 bit Random number
00532       (+) Get the 32 bit Random number with interrupt enabled
00533       (+) Handle RNG interrupt request
00534
00535 @endverbatim
00536   * @{
00537   */
00538
00539 /**
00540   * @brief  Generates a 32-bit random number.
00541   * @note   This function checks value of RNG_FLAG_DRDY flag to know if valid
00542   *         random number is available in the DR register (RNG_FLAG_DRDY flag set
00543   *         whenever a random number is available through the RNG_DR register).
00544   *         After transitioning from 0 to 1 (random number available),
00545   *         RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
00546   *         four words from the RNG_DR register, i.e. further function calls
00547   *         will immediately return a new u32 random number (additional words are
00548   *         available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
00549   * @note   When no more random number data is available in DR register, RNG_FLAG_DRDY
00550   *         flag is automatically cleared.
00551   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00552   *                the configuration information for RNG.
00553   * @param  random32bit pointer to generated random number variable if successful.
00554   * @retval HAL status
00555   */
00556
00557 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
00558 {
00559   uint32_t tickstart;
00560   HAL_StatusTypeDef status = HAL_OK;
00561
00562   /* Process Locked */
00563   __HAL_LOCK(hrng);
00564
00565   /* Check RNG peripheral state */
00566   if (hrng->State == HAL_RNG_STATE_READY)
00567   {
00568     /* Change RNG peripheral state */
00569     hrng->State = HAL_RNG_STATE_BUSY;
00570
00571     /* Get tick */
00572     tickstart = HAL_GetTick();
00573
00574     /* Check if data register contains valid random data */
00575     while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00576     {
00577       if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
00578       {
00579         /* New check to avoid false timeout detection in case of preemption */
00580         if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00581         {
00582           hrng->State = HAL_RNG_STATE_READY;
00583           hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
00584           /* Process Unlocked */
00585           __HAL_UNLOCK(hrng);
00586           return HAL_ERROR;
00587         }
00588       }
00589     }
00590
00591     /* Get a 32bit Random number */
00592     hrng->RandomNumber = hrng->Instance->DR;
00593     *random32bit = hrng->RandomNumber;
00594
00595     hrng->State = HAL_RNG_STATE_READY;
00596   }
00597   else
00598   {
00599     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00600     status = HAL_ERROR;
00601   }
00602
00603   /* Process Unlocked */
00604   __HAL_UNLOCK(hrng);
00605
00606   return status;
00607 }
00608
00609 /**
00610   * @brief  Generates a 32-bit random number in interrupt mode.
00611   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00612   *                the configuration information for RNG.
00613   * @retval HAL status
00614   */
00615 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
00616 {
00617   HAL_StatusTypeDef status = HAL_OK;
00618
00619   /* Process Locked */
00620   __HAL_LOCK(hrng);
00621
00622   /* Check RNG peripheral state */
00623   if (hrng->State == HAL_RNG_STATE_READY)
00624   {
00625     /* Change RNG peripheral state */
00626     hrng->State = HAL_RNG_STATE_BUSY;
00627
00628     /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00629     __HAL_RNG_ENABLE_IT(hrng);
00630   }
00631   else
00632   {
00633     /* Process Unlocked */
00634     __HAL_UNLOCK(hrng);
00635
00636     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00637     status = HAL_ERROR;
00638   }
00639
00640   return status;
00641 }
00642
00643 /**
00644   * @brief  Handles RNG interrupt request.
00645   * @note   In the case of a clock error, the RNG is no more able to generate
00646   *         random numbers because the PLL48CLK clock is not correct. User has
00647   *         to check that the clock controller is correctly configured to provide
00648   *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
00649   *         The clock error has no impact on the previously generated
00650   *         random numbers, and the RNG_DR register contents can be used.
00651   * @note   In the case of a seed error, the generation of random numbers is
00652   *         interrupted as long as the SECS bit is '1'. If a number is
00653   *         available in the RNG_DR register, it must not be used because it may
00654   *         not have enough entropy. In this case, it is recommended to clear the
00655   *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
00656   *         the RNG peripheral to reinitialize and restart the RNG.
00657   * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
00658   *         or CEIS are set.
00659   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00660   *                the configuration information for RNG.
00661   * @retval None
00662
00663   */
00664 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
00665 {
00666   uint32_t rngclockerror = 0U;
00667
00668   /* RNG clock error interrupt occurred */
00669   if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
00670   {
00671     /* Update the error code */
00672     hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
00673     rngclockerror = 1U;
00674   }
00675   else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
00676   {
00677     /* Update the error code */
00678     hrng->ErrorCode = HAL_RNG_ERROR_SEED;
00679     rngclockerror = 1U;
00680   }
00681   else
00682   {
00683     /* Nothing to do */
00684   }
00685
00686   if (rngclockerror == 1U)
00687   {
00688     /* Change RNG peripheral state */
00689     hrng->State = HAL_RNG_STATE_ERROR;
00690
00691 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00692     /* Call registered Error callback */
00693     hrng->ErrorCallback(hrng);
00694 #else
00695     /* Call legacy weak Error callback */
00696     HAL_RNG_ErrorCallback(hrng);
00697 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00698
00699     /* Clear the clock error flag */
00700     __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
00701
00702     return;
00703   }
00704
00705   /* Check RNG data ready interrupt occurred */
00706   if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
00707   {
00708     /* Generate random number once, so disable the IT */
00709     __HAL_RNG_DISABLE_IT(hrng);
00710
00711     /* Get the 32bit Random number (DRDY flag automatically cleared) */
00712     hrng->RandomNumber = hrng->Instance->DR;
00713
00714     if (hrng->State != HAL_RNG_STATE_ERROR)
00715     {
00716       /* Change RNG peripheral state */
00717       hrng->State = HAL_RNG_STATE_READY;
00718       /* Process Unlocked */
00719       __HAL_UNLOCK(hrng);
00720
00721 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00722       /* Call registered Data Ready callback */
00723       hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
00724 #else
00725       /* Call legacy weak Data Ready callback */
00726       HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
00727 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00728     }
00729   }
00730 }
00731
00732 /**
00733   * @brief  Read latest generated random number.
00734   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00735   *                the configuration information for RNG.
00736   * @retval random value
00737   */
00738 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
00739 {
00740   return (hrng->RandomNumber);
00741 }
00742
00743 /**
00744   * @brief  Data Ready callback in non-blocking mode.
00745   * @note   When RNG_FLAG_DRDY flag value is set, first random number has been read
00746   *         from DR register in IRQ Handler and is provided as callback parameter.
00747   *         Depending on valid data available in the conditioning output buffer,
00748   *         additional words can be read by the application from DR register till
00749   *         DRDY bit remains high.
00750   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00751   *                the configuration information for RNG.
00752   * @param  random32bit generated random number.
00753   * @retval None
00754   */
00755 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
00756 {
00757   /* Prevent unused argument(s) compilation warning */
00758   UNUSED(hrng);
00759   UNUSED(random32bit);
00760   /* NOTE : This function should not be modified. When the callback is needed,
00761             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
00762    */
00763 }
00764
00765 /**
00766   * @brief  RNG error callbacks.
00767   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00768   *                the configuration information for RNG.
00769   * @retval None
00770   */
00771 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
00772 {
00773   /* Prevent unused argument(s) compilation warning */
00774   UNUSED(hrng);
00775   /* NOTE : This function should not be modified. When the callback is needed,
00776             function HAL_RNG_ErrorCallback must be implemented in the user file.
00777    */
00778 }
00779 /**
00780   * @}
00781   */
00782
00783
00784 /** @addtogroup RNG_Exported_Functions_Group3
00785   *  @brief   Peripheral State functions
00786   *
00787 @verbatim
00788  ===============================================================================
00789                       ##### Peripheral State functions #####
00790  ===============================================================================
00791     [..]
00792     This subsection permits to get in run-time the status of the peripheral
00793     and the data flow.
00794
00795 @endverbatim
00796   * @{
00797   */
00798
00799 /**
00800   * @brief  Returns the RNG state.
00801   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00802   *                the configuration information for RNG.
00803   * @retval HAL state
00804   */
00805 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
00806 {
00807   return hrng->State;
00808 }
00809
00810 /**
00811   * @brief  Return the RNG handle error code.
00812   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00813   * @retval RNG Error Code
00814   */
00815 uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
00816 {
00817   /* Return RNG Error Code */
00818   return hrng->ErrorCode;
00819 }
00820 /**
00821   * @}
00822   */
00823
00824 /**
00825   * @}
00826   */
00827
00828
00829 #endif /* HAL_RNG_MODULE_ENABLED */
00830 /**
00831   * @}
00832   */
00833
00834 #endif /* RNG */
00835
00836 /**
00837   * @}
00838   */
00839
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rng.h Source File

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stm32g0xx_hal_rng.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rng.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_RNG_H
00021 #define STM32G0xx_HAL_RNG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 #if defined (RNG)
00035
00036 /** @defgroup RNG RNG
00037   * @brief RNG HAL module driver
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042
00043 /** @defgroup RNG_Exported_Types RNG Exported Types
00044   * @{
00045   */
00046
00047 /** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
00048   * @{
00049   */
00050 typedef struct
00051 {
00052   uint32_t                    ClockErrorDetection; /*!< CED Clock error detection */
00053 } RNG_InitTypeDef;
00054
00055 /**
00056   * @}
00057   */
00058
00059 /** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
00060   * @{
00061   */
00062 typedef enum
00063 {
00064   HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
00065   HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
00066   HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
00067   HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
00068   HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
00069
00070 } HAL_RNG_StateTypeDef;
00071
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
00077   * @{
00078   */
00079 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00080 typedef struct  __RNG_HandleTypeDef
00081 #else
00082 typedef struct
00083 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00084 {
00085   RNG_TypeDef                 *Instance;    /*!< Register base address   */
00086
00087   RNG_InitTypeDef             Init;         /*!< RNG configuration parameters */
00088
00089   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
00090
00091   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
00092
00093   __IO  uint32_t              ErrorCode;    /*!< RNG Error code          */
00094
00095   uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
00096
00097 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00098   void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
00099   void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
00100
00101   void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
00102   void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
00103 #endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
00104
00105 } RNG_HandleTypeDef;
00106
00107 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00108 /**
00109   * @brief  HAL RNG Callback ID enumeration definition
00110   */
00111 typedef enum
00112 {
00113   HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
00114
00115   HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
00116   HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
00117
00118 } HAL_RNG_CallbackIDTypeDef;
00119
00120 /**
00121   * @brief  HAL RNG Callback pointer definition
00122   */
00123 typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
00124 typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
00125
00126 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00127
00128 /**
00129   * @}
00130   */
00131
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported constants --------------------------------------------------------*/
00137 /** @defgroup RNG_Exported_Constants RNG Exported Constants
00138   * @{
00139   */
00140
00141 /** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
00142   * @{
00143   */
00144 #define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
00145 #define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
00146 #define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
00152   * @{
00153   */
00154 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
00155 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
00156 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
00162   * @{
00163   */
00164 #define RNG_CED_ENABLE          0x00000000U /*!< Clock error detection Enabled  */
00165 #define RNG_CED_DISABLE         RNG_CR_CED  /*!< Clock error detection Disabled */
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup RNG_Error_Definition   RNG Error Definition
00171   * @{
00172   */
00173 #define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error          */
00174 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00175 #define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
00176 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00177 #define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error     */
00178 #define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
00179 #define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
00180 #define  HAL_RNG_ERROR_CLOCK            0x00000010U    /*!< Clock error       */
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /* Exported macros -----------------------------------------------------------*/
00190 /** @defgroup RNG_Exported_Macros RNG Exported Macros
00191   * @{
00192   */
00193
00194 /** @brief Reset RNG handle state
00195   * @param  __HANDLE__ RNG Handle
00196   * @retval None
00197   */
00198 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00199 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00200                                                        (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
00201                                                        (__HANDLE__)->MspInitCallback = NULL;            \
00202                                                        (__HANDLE__)->MspDeInitCallback = NULL;          \
00203                                                     } while(0U)
00204 #else
00205 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
00206 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00207
00208 /**
00209   * @brief  Enables the RNG peripheral.
00210   * @param  __HANDLE__ RNG Handle
00211   * @retval None
00212   */
00213 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
00214
00215 /**
00216   * @brief  Disables the RNG peripheral.
00217   * @param  __HANDLE__ RNG Handle
00218   * @retval None
00219   */
00220 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
00221
00222 /**
00223   * @brief  Check the selected RNG flag status.
00224   * @param  __HANDLE__ RNG Handle
00225   * @param  __FLAG__ RNG flag
00226   *          This parameter can be one of the following values:
00227   *            @arg RNG_FLAG_DRDY:  Data ready
00228   *            @arg RNG_FLAG_CECS:  Clock error current status
00229   *            @arg RNG_FLAG_SECS:  Seed error current status
00230   * @retval The new state of __FLAG__ (SET or RESET).
00231   */
00232 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00233
00234 /**
00235   * @brief  Clears the selected RNG flag status.
00236   * @param  __HANDLE__ RNG handle
00237   * @param  __FLAG__ RNG flag to clear
00238   * @note   WARNING: This is a dummy macro for HAL code alignment,
00239   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
00240   * @retval None
00241   */
00242 #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
00243
00244 /**
00245   * @brief  Enables the RNG interrupts.
00246   * @param  __HANDLE__ RNG Handle
00247   * @retval None
00248   */
00249 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
00250
00251 /**
00252   * @brief  Disables the RNG interrupts.
00253   * @param  __HANDLE__ RNG Handle
00254   * @retval None
00255   */
00256 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
00257
00258 /**
00259   * @brief  Checks whether the specified RNG interrupt has occurred or not.
00260   * @param  __HANDLE__ RNG Handle
00261   * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
00262   *         This parameter can be one of the following values:
00263   *            @arg RNG_IT_DRDY: Data ready interrupt
00264   *            @arg RNG_IT_CEI: Clock error interrupt
00265   *            @arg RNG_IT_SEI: Seed error interrupt
00266   * @retval The new state of __INTERRUPT__ (SET or RESET).
00267   */
00268 #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00269
00270 /**
00271   * @brief  Clear the RNG interrupt status flags.
00272   * @param  __HANDLE__ RNG Handle
00273   * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
00274   *          This parameter can be one of the following values:
00275   *            @arg RNG_IT_CEI: Clock error interrupt
00276   *            @arg RNG_IT_SEI: Seed error interrupt
00277   * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
00278   * @retval None
00279   */
00280 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
00281
00282 /**
00283   * @}
00284   */
00285
00286 /* Exported functions --------------------------------------------------------*/
00287 /** @defgroup RNG_Exported_Functions RNG Exported Functions
00288   * @{
00289   */
00290
00291 /** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
00292   * @{
00293   */
00294 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
00295 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
00296 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
00297 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
00298
00299 /* Callbacks Register/UnRegister functions  ***********************************/
00300 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00301 HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
00302                                            pRNG_CallbackTypeDef pCallback);
00303 HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
00304
00305 HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
00306 HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
00307 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
00314   * @{
00315   */
00316 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
00317 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
00318 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
00319
00320 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
00321 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
00322 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
00323
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
00329   * @{
00330   */
00331 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
00332 uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /* Private macros ------------------------------------------------------------*/
00342 /** @defgroup RNG_Private_Macros RNG Private Macros
00343   * @{
00344   */
00345 #define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
00346                        ((IT) == RNG_IT_SEI))
00347
00348 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
00349                            ((FLAG) == RNG_FLAG_CECS) || \
00350                            ((FLAG) == RNG_FLAG_SECS))
00351
00352 /**
00353   * @brief Verify the RNG Clock Error Detection mode.
00354   * @param __MODE__ RNG Clock Error Detection mode
00355   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00356   */
00357 #define IS_RNG_CED(__MODE__)   (((__MODE__) == RNG_CED_ENABLE) || \
00358                                 ((__MODE__) == RNG_CED_DISABLE))
00359 /**
00360   * @}
00361   */
00362
00363 /**
00364   * @}
00365   */
00366
00367 #endif /* RNG */
00368
00369 /**
00370   * @}
00371   */
00372
00373 #ifdef __cplusplus
00374 }
00375 #endif
00376
00377
00378 #endif /* STM32G0xx_HAL_RNG_H */
00379
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rtc.c Source File

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stm32g0xx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real-Time Clock (RTC) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + Calendar (Time and Date) configuration
00010   *           + Alarms (Alarm A and Alarm B) configuration
00011   *           + WakeUp Timer configuration
00012   *           + TimeStamp configuration
00013   *           + Tampers configuration
00014   *           + Backup Data Registers configuration
00015   *           + RTC Tamper and TimeStamp Pins Selection
00016   *           + Interrupts and flags management
00017   *
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * Copyright (c) 2018 STMicroelectronics.
00022   * All rights reserved.
00023   *
00024   * This software is licensed under terms that can be found in the LICENSE file
00025   * in the root directory of this software component.
00026   * If no LICENSE file comes with this software, it is provided AS-IS.
00027   *
00028   ******************************************************************************
00029   @verbatim
00030   ===============================================================================
00031                           ##### RTC Operating Condition #####
00032   ===============================================================================
00033   [..] The real-time clock (RTC) and the RTC backup registers can be powered
00034        from the VBAT voltage when the main VDD supply is powered off.
00035        To retain the content of the RTC backup registers and supply the RTC
00036        when VDD is turned off, VBAT pin can be connected to an optional
00037        standby voltage supplied by a battery or by another source.
00038
00039                    ##### Backup Domain Reset #####
00040  ===============================================================================
00041   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00042        to their reset values.
00043        A backup domain reset is generated when one of the following events occurs:
00044     (+) Software reset, triggered by setting the BDRST bit in the
00045         RCC Backup domain control register (RCC_BDCR).
00046     (+) VDD or VBAT power on, if both supplies have previously been powered off.
00047     (+) Tamper detection event resets all data backup registers.
00048
00049                    ##### Backup Domain Access #####
00050   =============================================================================
00051   [..] After reset, the backup domain (RTC registers and RTC backup data registers)
00052        is protected against possible unwanted write accesses.
00053   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00054     (+) Enable the Power Controller (PWR) APB1 interface clock using the
00055         __HAL_RCC_PWR_CLK_ENABLE() function.
00056     (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00057     (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
00058     (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
00059
00060   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00061     (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
00062         PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
00063     (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
00064
00065                   ##### How to use RTC Driver #####
00066  ===================================================================
00067   [..]
00068     (+) Enable the RTC domain access (see description in the section above).
00069     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00070         format using the HAL_RTC_Init() function.
00071
00072   *** Time and Date configuration ***
00073   ===================================
00074   [..]
00075     (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00076         and HAL_RTC_SetDate() functions.
00077     (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00078
00079   *** Alarm configuration ***
00080   ===========================
00081   [..]
00082     (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00083             You can also configure the RTC Alarm with interrupt mode using the
00084             HAL_RTC_SetAlarm_IT() function.
00085     (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00086
00087                   ##### RTC and low power modes #####
00088   ==================================================================
00089   [..] The MCU can be woken up from a low power mode by an RTC alternate
00090        function.
00091   [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00092        RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00093        These RTC alternate functions can wake up the system from the Stop and
00094        Standby low power modes.
00095   [..] The system can also wake up from low power modes without depending
00096        on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00097        or the RTC wakeup events.
00098   [..] The RTC provides a programmable time base for waking up from the
00099        Stop or Standby mode at regular intervals.
00100        Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
00101        is LSE or LSI.
00102
00103   *** Callback registration ***
00104   =============================================
00105
00106   [..]
00107   The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
00108   allows the user to configure dynamically the driver callbacks.
00109   Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
00110
00111   [..]
00112   Function HAL_RTC_RegisterCallback() allows to register following callbacks:
00113     (+) AlarmAEventCallback          :  RTC Alarm A Event callback.
00114     (+) AlarmBEventCallback          :  RTC Alarm B Event callback.
00115     (+) TimeStampEventCallback       :  RTC TimeStamp Event callback.
00116     (+) WakeUpTimerEventCallback     :  RTC WakeUpTimer Event callback.
00117     (+) Tamper1EventCallback         :  RTC Tamper1Event callback.
00118     (+) Tamper2EventCallback         :  RTC Tamper2Event callback.
00119     (+) Tamper3EventCallback         :  RTC Tamper3Event callback. (*)
00120     (+) InternalTamper3EventCallback :  RTC Internal Tamper 3 Event callback.
00121     (+) InternalTamper4EventCallback :  RTC Internal Tamper 4 Event callback.
00122     (+) InternalTamper5EventCallback :  RTC Internal Tamper 5 Event callback.
00123     (+) InternalTamper6EventCallback :  RTC Internal Tamper 6 Event callback.
00124     (+) MspInitCallback              :  RTC MspInit.
00125     (+) MspDeInitCallback            :  RTC MspDeInit.
00126   This function takes as parameters the HAL peripheral handle, the Callback ID
00127   and a pointer to the user callback function.
00128
00129   Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
00130   weak function.
00131   HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00132   and the Callback ID.
00133   This function allows to reset following callbacks:
00134     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
00135     (+) AlarmBEventCallback          : RTC Alarm B Event callback.
00136     (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
00137     (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
00138     (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
00139     (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
00140     (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.(*)
00141     (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Event callback.
00142     (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Event callback.
00143     (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Event callback.
00144     (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Event callback.
00145     (+) MspInitCallback              : RTC MspInit callback.
00146     (+) MspDeInitCallback            : RTC MspDeInit callback.
00147
00148   [..]
00149   By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
00150   all callbacks are set to the corresponding weak functions :
00151   examples AlarmAEventCallback(), WakeUpTimerEventCallback().
00152   Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
00153   in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
00154   (not registered beforehand).
00155   If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
00156   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00157
00158   [..]
00159   Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
00160   Exception done MspInit/MspDeInit that can be registered/unregistered
00161   in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
00162   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00163   In that case first register the MspInit/MspDeInit user callbacks
00164   using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
00165   or HAL_RTC_Init() function.
00166
00167   [..]
00168   When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
00169   not defined, the callback registration feature is not available and all callbacks
00170   are set to the corresponding weak functions.
00171
00172    @endverbatim
00173
00174   ******************************************************************************
00175   */
00176
00177 /* Includes ------------------------------------------------------------------*/
00178 #include "stm32g0xx_hal.h"
00179
00180 /** @addtogroup STM32G0xx_HAL_Driver
00181   * @{
00182   */
00183
00184
00185 /** @addtogroup RTC
00186   * @brief RTC HAL module driver
00187   * @{
00188   */
00189
00190 #ifdef HAL_RTC_MODULE_ENABLED
00191
00192 /* Private typedef -----------------------------------------------------------*/
00193 /* Private define ------------------------------------------------------------*/
00194 /* Private macro -------------------------------------------------------------*/
00195 /* Private variables ---------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /* Exported functions --------------------------------------------------------*/
00198
00199 /** @addtogroup RTC_Exported_Functions
00200   * @{
00201   */
00202
00203 /** @addtogroup RTC_Exported_Functions_Group1
00204  *  @brief    Initialization and Configuration functions
00205  *
00206 @verbatim
00207  ===============================================================================
00208               ##### Initialization and de-initialization functions #####
00209  ===============================================================================
00210    [..] This section provides functions allowing to initialize and configure the
00211          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00212          RTC registers Write protection, enter and exit the RTC initialization mode,
00213          RTC registers synchronization check and reference clock detection enable.
00214          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00215              It is split into 2 programmable prescalers to minimize power consumption.
00216              (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
00217              (++) When both prescalers are used, it is recommended to configure the
00218                  asynchronous prescaler to a high value to minimize power consumption.
00219          (#) All RTC registers are Write protected. Writing to the RTC registers
00220              is enabled by writing a key into the Write Protection register, RTC_WPR.
00221          (#) To configure the RTC Calendar, user application should enter
00222              initialization mode. In this mode, the calendar counter is stopped
00223              and its value can be updated. When the initialization sequence is
00224              complete, the calendar restarts counting after 4 RTCCLK cycles.
00225          (#) To read the calendar through the shadow registers after Calendar
00226              initialization, calendar update or after wakeup from low power modes
00227              the software must first clear the RSF flag. The software must then
00228              wait until it is set again before reading the calendar, which means
00229              that the calendar registers have been correctly copied into the
00230              RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
00231              implements the above software sequence (RSF clear and RSF check).
00232
00233 @endverbatim
00234   * @{
00235   */
00236
00237 /**
00238   * @brief  Initialize the RTC peripheral
00239   * @param  hrtc RTC handle
00240   * @retval HAL status
00241   */
00242 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00243 {
00244   HAL_StatusTypeDef status = HAL_ERROR;
00245
00246   /* Check the RTC peripheral state */
00247   if(hrtc != NULL)
00248   {
00249     /* Check the parameters */
00250     assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00251     assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00252     assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00253     assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00254     assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
00255     assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
00256     assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00257     assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00258     assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp));
00259
00260     if(hrtc->State == HAL_RTC_STATE_RESET)
00261     {
00262       /* Allocate lock resource and initialize it */
00263       hrtc->Lock = HAL_UNLOCKED;
00264
00265       /* Process TAMP peripheral offset from RTC one */
00266       hrtc->TampOffset = (TAMP_BASE - RTC_BASE);
00267
00268 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00269       hrtc->AlarmAEventCallback          =  HAL_RTC_AlarmAEventCallback;        /* Legacy weak AlarmAEventCallback      */
00270       hrtc->AlarmBEventCallback          =  HAL_RTCEx_AlarmBEventCallback;      /* Legacy weak AlarmBEventCallback      */
00271       hrtc->TimeStampEventCallback       =  HAL_RTCEx_TimeStampEventCallback;   /* Legacy weak TimeStampEventCallback   */
00272       hrtc->WakeUpTimerEventCallback     =  HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
00273       hrtc->Tamper1EventCallback         =  HAL_RTCEx_Tamper1EventCallback;     /* Legacy weak Tamper1EventCallback     */
00274       hrtc->Tamper2EventCallback         =  HAL_RTCEx_Tamper2EventCallback;     /* Legacy weak Tamper2EventCallback     */
00275 #if defined(TAMP_CR1_TAMP3E)
00276       hrtc->Tamper3EventCallback         =  HAL_RTCEx_Tamper3EventCallback;     /* Legacy weak Tamper3EventCallback     */
00277 #endif /* TAMP_CR1_TAMP3E */
00278       hrtc->InternalTamper3EventCallback =  HAL_RTCEx_InternalTamper3EventCallback;   /*!< Legacy weak InternalTamper3EventCallback */
00279       hrtc->InternalTamper4EventCallback =  HAL_RTCEx_InternalTamper4EventCallback;   /*!< Legacy weak InternalTamper4EventCallback */
00280       hrtc->InternalTamper5EventCallback =  HAL_RTCEx_InternalTamper5EventCallback;   /*!< Legacy weak InternalTamper5EventCallback */
00281       hrtc->InternalTamper6EventCallback =  HAL_RTCEx_InternalTamper6EventCallback;   /*!< Legacy weak InternalTamper6EventCallback */
00282
00283       if(hrtc->MspInitCallback == NULL)
00284       {
00285         hrtc->MspInitCallback = HAL_RTC_MspInit;
00286       }
00287
00288       /* Init the low level hardware */
00289       hrtc->MspInitCallback(hrtc);
00290
00291       if(hrtc->MspDeInitCallback == NULL)
00292       {
00293         hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00294       }
00295 #else
00296       /* Initialize RTC MSP */
00297       HAL_RTC_MspInit(hrtc);
00298 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00299     }
00300
00301     /* Set RTC state */
00302     hrtc->State = HAL_RTC_STATE_BUSY;
00303
00304     /* Check whether the calendar needs to be initialized */
00305     if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
00306     {
00307       /* Disable the write protection for RTC registers */
00308       __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00309
00310       /* Enter Initialization mode */
00311       status = RTC_EnterInitMode(hrtc);
00312
00313       if(status == HAL_OK)
00314       {
00315         /* Clear RTC_CR FMT, OSEL and POL Bits */
00316         hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
00317         /* Set RTC_CR register */
00318         hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
00319
00320         /* Configure the RTC PRER */
00321         hrtc->Instance->PRER = (hrtc->Init.SynchPrediv);
00322         hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
00323
00324         /* Exit Initialization mode */
00325         status = RTC_ExitInitMode(hrtc);
00326       }
00327
00328       if (status == HAL_OK)
00329       {
00330         hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU |RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN);
00331         hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
00332       }
00333
00334       /* Enable the write protection for RTC registers */
00335       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00336     }
00337     else
00338     {
00339       /* The calendar is already initialized */
00340       status = HAL_OK;
00341     }
00342
00343     if (status == HAL_OK)
00344     {
00345       hrtc->State = HAL_RTC_STATE_READY;
00346     }
00347   }
00348
00349   return status;
00350 }
00351
00352 /**
00353   * @brief  DeInitialize the RTC peripheral.
00354   * @note   This function does not reset the RTC Backup Data registers.
00355   * @param  hrtc RTC handle
00356   * @retval HAL status
00357   */
00358 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00359 {
00360   HAL_StatusTypeDef status;
00361   uint32_t tickstart;
00362
00363   /* Check the parameters */
00364   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00365
00366   /* Set RTC state */
00367   hrtc->State = HAL_RTC_STATE_BUSY;
00368
00369   /* Disable the write protection for RTC registers */
00370   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00371
00372   /* Enter Initialization mode */
00373   status = RTC_EnterInitMode(hrtc);
00374   if(status == HAL_OK)
00375   {
00376     /* Reset TR, DR and CR registers */
00377     hrtc->Instance->TR = 0x00000000U;
00378     hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00379     /* Reset All CR bits except CR[2:0] */
00380     hrtc->Instance->CR &= RTC_CR_WUCKSEL;
00381
00382     tickstart = HAL_GetTick();
00383
00384     /* Wait till WUTWF flag is set and if Time out is reached exit */
00385     while(((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U)
00386     {
00387       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00388       {
00389         /* Enable the write protection for RTC registers */
00390         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00391
00392         /* Set RTC state */
00393         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00394
00395         return HAL_TIMEOUT;
00396       }
00397     }
00398
00399     /* Reset all RTC CR register bits */
00400     hrtc->Instance->CR &= 0x00000000U;
00401     hrtc->Instance->WUTR = RTC_WUTR_WUT;
00402     hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
00403     hrtc->Instance->ALRMAR = 0x00000000U;
00404     hrtc->Instance->ALRMBR = 0x00000000U;
00405     hrtc->Instance->SHIFTR = 0x00000000U;
00406     hrtc->Instance->CALR = 0x00000000U;
00407     hrtc->Instance->ALRMASSR = 0x00000000U;
00408     hrtc->Instance->ALRMBSSR = 0x00000000U;
00409
00410     /* Exit initialization mode */
00411     status = RTC_ExitInitMode(hrtc);
00412   }
00413
00414   /* Enable the write protection for RTC registers */
00415   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00416
00417   if (status == HAL_OK)
00418    {
00419 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00420      if(hrtc->MspDeInitCallback == NULL)
00421      {
00422        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00423      }
00424
00425     /* DeInit the low level hardware: CLOCK, NVIC.*/
00426     hrtc->MspDeInitCallback(hrtc);
00427
00428 #else
00429     /* De-Initialize RTC MSP */
00430     HAL_RTC_MspDeInit(hrtc);
00431 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00432
00433     hrtc->State = HAL_RTC_STATE_RESET;
00434    }
00435
00436    /* Release Lock */
00437    __HAL_UNLOCK(hrtc);
00438
00439    return status;
00440 }
00441
00442 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00443 /**
00444   * @brief  Register a User RTC Callback
00445   *         To be used instead of the weak predefined callback
00446   * @param  hrtc RTC handle
00447   * @param  CallbackID ID of the callback to be registered
00448   *         This parameter can be one of the following values:
00449   *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
00450   *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
00451   *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
00452   *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
00453   *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
00454   *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
00455   *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID (*)
00456   *          @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
00457   *          @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
00458   *          @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
00459   *          @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
00460   *          @arg @ref HAL_RTC_MSPINIT_CB_ID                Msp Init callback ID
00461   *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID              Msp DeInit callback ID
00462   * @param  pCallback pointer to the Callback function
00463   * @retval HAL status
00464   */
00465 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
00466 {
00467   HAL_StatusTypeDef status = HAL_OK;
00468
00469   if(pCallback == NULL)
00470   {
00471     return HAL_ERROR;
00472   }
00473
00474   /* Process locked */
00475   __HAL_LOCK(hrtc);
00476
00477   if(HAL_RTC_STATE_READY == hrtc->State)
00478   {
00479     switch (CallbackID)
00480     {
00481     case HAL_RTC_ALARM_A_EVENT_CB_ID :
00482       hrtc->AlarmAEventCallback = pCallback;
00483       break;
00484
00485     case HAL_RTC_ALARM_B_EVENT_CB_ID :
00486       hrtc->AlarmBEventCallback = pCallback;
00487       break;
00488
00489     case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
00490       hrtc->TimeStampEventCallback = pCallback;
00491       break;
00492
00493     case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
00494       hrtc->WakeUpTimerEventCallback = pCallback;
00495       break;
00496
00497     case HAL_RTC_TAMPER1_EVENT_CB_ID :
00498       hrtc->Tamper1EventCallback = pCallback;
00499       break;
00500
00501     case HAL_RTC_TAMPER2_EVENT_CB_ID :
00502       hrtc->Tamper2EventCallback = pCallback;
00503       break;
00504
00505 #if defined(TAMP_CR1_TAMP3E)
00506     case HAL_RTC_TAMPER3_EVENT_CB_ID :
00507       hrtc->Tamper3EventCallback = pCallback;
00508       break;
00509 #endif /* TAMP_CR1_TAMP3E */
00510
00511     case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
00512       hrtc->InternalTamper3EventCallback = pCallback;
00513       break;
00514
00515     case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
00516       hrtc->InternalTamper4EventCallback = pCallback;
00517       break;
00518
00519     case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
00520       hrtc->InternalTamper5EventCallback = pCallback;
00521       break;
00522
00523     case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
00524        hrtc->InternalTamper6EventCallback = pCallback;
00525       break;
00526
00527    case HAL_RTC_MSPINIT_CB_ID :
00528       hrtc->MspInitCallback = pCallback;
00529       break;
00530
00531    case HAL_RTC_MSPDEINIT_CB_ID :
00532       hrtc->MspDeInitCallback = pCallback;
00533       break;
00534
00535     default :
00536      /* Return error status */
00537       status =  HAL_ERROR;
00538       break;
00539     }
00540   }
00541   else if(HAL_RTC_STATE_RESET == hrtc->State)
00542   {
00543     switch (CallbackID)
00544     {
00545     case HAL_RTC_MSPINIT_CB_ID :
00546       hrtc->MspInitCallback = pCallback;
00547       break;
00548
00549    case HAL_RTC_MSPDEINIT_CB_ID :
00550       hrtc->MspDeInitCallback = pCallback;
00551       break;
00552
00553     default :
00554      /* Return error status */
00555       status =  HAL_ERROR;
00556       break;
00557     }
00558   }
00559   else
00560   {
00561     /* Return error status */
00562     status =  HAL_ERROR;
00563   }
00564
00565   /* Release Lock */
00566   __HAL_UNLOCK(hrtc);
00567
00568   return status;
00569 }
00570
00571 /**
00572   * @brief  Unregister an RTC Callback
00573   *         RTC callback is redirected to the weak predefined callback
00574   * @param  hrtc RTC handle
00575   * @param  CallbackID ID of the callback to be unregistered
00576   *         This parameter can be one of the following values:
00577   *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
00578   *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
00579   *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
00580   *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
00581   *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
00582   *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
00583   *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID (*)
00584   *          @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID
00585   *          @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID
00586   *          @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID
00587   *          @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID
00588   *          @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
00589   *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
00590   * @retval HAL status
00591   */
00592 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
00593 {
00594   HAL_StatusTypeDef status = HAL_OK;
00595
00596   /* Process locked */
00597   __HAL_LOCK(hrtc);
00598
00599   if(HAL_RTC_STATE_READY == hrtc->State)
00600   {
00601     switch (CallbackID)
00602     {
00603     case HAL_RTC_ALARM_A_EVENT_CB_ID :
00604       hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;         /* Legacy weak AlarmAEventCallback    */
00605       break;
00606
00607     case HAL_RTC_ALARM_B_EVENT_CB_ID :
00608       hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;          /* Legacy weak AlarmBEventCallback */
00609       break;
00610
00611     case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
00612       hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;    /* Legacy weak TimeStampEventCallback    */
00613       break;
00614
00615     case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
00616       hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
00617       break;
00618
00619     case HAL_RTC_TAMPER1_EVENT_CB_ID :
00620       hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;         /* Legacy weak Tamper1EventCallback   */
00621       break;
00622
00623     case HAL_RTC_TAMPER2_EVENT_CB_ID :
00624       hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;         /* Legacy weak Tamper2EventCallback         */
00625       break;
00626
00627 #if defined(TAMP_CR1_TAMP3E)
00628     case HAL_RTC_TAMPER3_EVENT_CB_ID :
00629       hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;         /* Legacy weak Tamper3EventCallback         */
00630       break;
00631 #endif /* TAMP_CR1_TAMP3E */
00632
00633     case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
00634       hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback;        /* Legacy weak InternalTamper3EventCallback         */
00635       break;
00636
00637     case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
00638       hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback;        /* Legacy weak InternalTamper4EventCallback         */
00639       break;
00640
00641     case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
00642       hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback;        /* Legacy weak InternalTamper5EventCallback         */
00643       break;
00644
00645     case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
00646       hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback;        /* Legacy weak InternalTamper6EventCallback         */
00647       break;
00648
00649
00650     case HAL_RTC_MSPINIT_CB_ID :
00651       hrtc->MspInitCallback = HAL_RTC_MspInit;
00652       break;
00653
00654     case HAL_RTC_MSPDEINIT_CB_ID :
00655       hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00656       break;
00657
00658     default :
00659      /* Return error status */
00660       status =  HAL_ERROR;
00661       break;
00662     }
00663   }
00664   else if(HAL_RTC_STATE_RESET == hrtc->State)
00665   {
00666     switch (CallbackID)
00667     {
00668     case HAL_RTC_MSPINIT_CB_ID :
00669       hrtc->MspInitCallback = HAL_RTC_MspInit;
00670       break;
00671
00672     case HAL_RTC_MSPDEINIT_CB_ID :
00673       hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00674       break;
00675
00676     default :
00677      /* Return error status */
00678       status =  HAL_ERROR;
00679       break;
00680     }
00681   }
00682   else
00683   {
00684     /* Return error status */
00685     status =  HAL_ERROR;
00686   }
00687
00688   /* Release Lock */
00689   __HAL_UNLOCK(hrtc);
00690
00691   return status;
00692 }
00693 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00694
00695 /**
00696   * @brief  Initialize the RTC MSP.
00697   * @param  hrtc RTC handle
00698   * @retval None
00699   */
00700 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
00701 {
00702   /* Prevent unused argument(s) compilation warning */
00703   UNUSED(hrtc);
00704
00705   /* NOTE : This function should not be modified, when the callback is needed,
00706             the HAL_RTC_MspInit could be implemented in the user file
00707    */
00708 }
00709
00710 /**
00711   * @brief  DeInitialize the RTC MSP.
00712   * @param  hrtc RTC handle
00713   * @retval None
00714   */
00715 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
00716 {
00717   /* Prevent unused argument(s) compilation warning */
00718   UNUSED(hrtc);
00719
00720   /* NOTE : This function should not be modified, when the callback is needed,
00721             the HAL_RTC_MspDeInit could be implemented in the user file
00722    */
00723 }
00724
00725 /**
00726   * @}
00727   */
00728
00729 /** @addtogroup RTC_Exported_Functions_Group2
00730  *  @brief   RTC Time and Date functions
00731  *
00732 @verbatim
00733  ===============================================================================
00734                  ##### RTC Time and Date functions #####
00735  ===============================================================================
00736
00737  [..] This section provides functions allowing to configure Time and Date features
00738
00739 @endverbatim
00740   * @{
00741   */
00742
00743 /**
00744   * @brief  Set RTC current time.
00745   * @param  hrtc RTC handle
00746   * @param  sTime Pointer to Time structure
00747   * @param  Format Specifies the format of the entered parameters.
00748   *          This parameter can be one of the following values:
00749   *            @arg RTC_FORMAT_BIN: Binary data format
00750   *            @arg RTC_FORMAT_BCD: BCD data format
00751   * @retval HAL status
00752   */
00753 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00754 {
00755   uint32_t tmpreg;
00756   HAL_StatusTypeDef status;
00757
00758  /* Check the parameters */
00759   assert_param(IS_RTC_FORMAT(Format));
00760   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00761   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00762
00763   /* Process Locked */
00764   __HAL_LOCK(hrtc);
00765
00766   hrtc->State = HAL_RTC_STATE_BUSY;
00767
00768   /* Disable the write protection for RTC registers */
00769   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00770
00771   /* Enter Initialization mode */
00772   status = RTC_EnterInitMode(hrtc);
00773   if(status == HAL_OK)
00774   {
00775     if(Format == RTC_FORMAT_BIN)
00776     {
00777     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
00778       {
00779         assert_param(IS_RTC_HOUR12(sTime->Hours));
00780         assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00781       }
00782       else
00783       {
00784         sTime->TimeFormat = 0x00U;
00785         assert_param(IS_RTC_HOUR24(sTime->Hours));
00786       }
00787       assert_param(IS_RTC_MINUTES(sTime->Minutes));
00788       assert_param(IS_RTC_SECONDS(sTime->Seconds));
00789
00790       tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \
00791                           ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \
00792                           ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \
00793                           (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos));
00794     }
00795     else
00796     {
00797     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
00798       {
00799         assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
00800         assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00801       }
00802       else
00803       {
00804         sTime->TimeFormat = 0x00U;
00805         assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00806       }
00807       assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00808       assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00809       tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \
00810                 ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \
00811                 ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \
00812                 ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos));
00813     }
00814
00815     /* Set the RTC_TR register */
00816     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00817
00818     /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
00819     hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
00820
00821     /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
00822     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
00823
00824     /* Exit Initialization mode */
00825     status = RTC_ExitInitMode(hrtc);
00826   }
00827
00828   /* Enable the write protection for RTC registers */
00829   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00830
00831   if (status == HAL_OK)
00832   {
00833    hrtc->State = HAL_RTC_STATE_READY;
00834   }
00835
00836   /* Process Unlocked */
00837   __HAL_UNLOCK(hrtc);
00838
00839   return status;
00840 }
00841
00842 /**
00843   * @brief  Get RTC current time.
00844   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
00845   *        value in second fraction ratio with time unit following generic formula:
00846   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
00847   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
00848   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00849   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00850   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
00851   *        to ensure consistency between the time and date values.
00852   * @param  hrtc RTC handle
00853   * @param  sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
00854   *                with input format (BIN or BCD), also SubSeconds field returning the
00855   *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
00856   *                factor to be used for second fraction ratio computation.
00857   * @param  Format Specifies the format of the entered parameters.
00858   *          This parameter can be one of the following values:
00859   *            @arg RTC_FORMAT_BIN: Binary data format
00860   *            @arg RTC_FORMAT_BCD: BCD data format
00861   * @retval HAL status
00862   */
00863 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00864 {
00865   uint32_t tmpreg;
00866
00867   /* Check the parameters */
00868   assert_param(IS_RTC_FORMAT(Format));
00869
00870   /* Get subseconds structure field from the corresponding register*/
00871   sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
00872
00873   /* Get SecondFraction structure field from the corresponding register field*/
00874   sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
00875
00876   /* Get the TR register */
00877   tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
00878
00879   /* Fill the structure fields with the read parameters */
00880   sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);
00881   sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
00882   sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
00883   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos);
00884
00885   /* Check the input parameters format */
00886   if(Format == RTC_FORMAT_BIN)
00887   {
00888     /* Convert the time structure parameters to Binary format */
00889     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
00890     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
00891     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
00892   }
00893
00894   return HAL_OK;
00895 }
00896
00897 /**
00898   * @brief  Set RTC current date.
00899   * @param  hrtc RTC handle
00900   * @param  sDate Pointer to date structure
00901   * @param  Format specifies the format of the entered parameters.
00902   *          This parameter can be one of the following values:
00903   *            @arg RTC_FORMAT_BIN: Binary data format
00904   *            @arg RTC_FORMAT_BCD: BCD data format
00905   * @retval HAL status
00906   */
00907 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00908 {
00909   uint32_t datetmpreg;
00910   HAL_StatusTypeDef status;
00911
00912  /* Check the parameters */
00913   assert_param(IS_RTC_FORMAT(Format));
00914
00915  /* Process Locked */
00916  __HAL_LOCK(hrtc);
00917
00918   hrtc->State = HAL_RTC_STATE_BUSY;
00919
00920   if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
00921   {
00922     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
00923   }
00924
00925   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
00926
00927   if(Format == RTC_FORMAT_BIN)
00928   {
00929     assert_param(IS_RTC_YEAR(sDate->Year));
00930     assert_param(IS_RTC_MONTH(sDate->Month));
00931     assert_param(IS_RTC_DATE(sDate->Date));
00932
00933    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year)  << RTC_DR_YU_Pos) | \
00934                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \
00935                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)  << RTC_DR_DU_Pos) | \
00936                  ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos));
00937   }
00938   else
00939   {
00940     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
00941     assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
00942     assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
00943
00944     datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \
00945                   (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \
00946                   (((uint32_t)sDate->Date) << RTC_DR_DU_Pos)| \
00947                   (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos));
00948   }
00949
00950   /* Disable the write protection for RTC registers */
00951   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00952
00953   /* Enter Initialization mode */
00954   status = RTC_EnterInitMode(hrtc);
00955   if(status == HAL_OK)
00956   {
00957     /* Set the RTC_DR register */
00958     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
00959
00960     /* Exit Initialization mode */
00961     status = RTC_ExitInitMode(hrtc);
00962   }
00963
00964   /* Enable the write protection for RTC registers */
00965   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00966
00967   if (status == HAL_OK)
00968   {
00969     hrtc->State = HAL_RTC_STATE_READY;
00970   }
00971
00972   /* Process Unlocked */
00973   __HAL_UNLOCK(hrtc);
00974
00975   return status;
00976 }
00977
00978 /**
00979   * @brief  Get RTC current date.
00980   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00981   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00982   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
00983   * @param  hrtc RTC handle
00984   * @param  sDate Pointer to Date structure
00985   * @param  Format Specifies the format of the entered parameters.
00986   *          This parameter can be one of the following values:
00987   *            @arg RTC_FORMAT_BIN:  Binary data format
00988   *            @arg RTC_FORMAT_BCD:  BCD data format
00989   * @retval HAL status
00990   */
00991 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00992 {
00993   uint32_t datetmpreg;
00994
00995   /* Check the parameters */
00996   assert_param(IS_RTC_FORMAT(Format));
00997
00998   /* Get the DR register */
00999   datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
01000
01001   /* Fill the structure fields with the read parameters */
01002   sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos);
01003   sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
01004   sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos);
01005   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos);
01006
01007   /* Check the input parameters format */
01008   if(Format == RTC_FORMAT_BIN)
01009   {
01010     /* Convert the date structure parameters to Binary format */
01011     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
01012     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
01013     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
01014   }
01015   return HAL_OK;
01016 }
01017
01018 /**
01019   * @}
01020   */
01021
01022 /** @addtogroup RTC_Exported_Functions_Group3
01023  *  @brief   RTC Alarm functions
01024  *
01025 @verbatim
01026  ===============================================================================
01027                  ##### RTC Alarm functions #####
01028  ===============================================================================
01029
01030  [..] This section provides functions allowing to configure Alarm feature
01031
01032 @endverbatim
01033   * @{
01034   */
01035 /**
01036   * @brief  Set the specified RTC Alarm.
01037   * @param  hrtc RTC handle
01038   * @param  sAlarm Pointer to Alarm structure
01039   * @param  Format Specifies the format of the entered parameters.
01040   *          This parameter can be one of the following values:
01041   *             @arg RTC_FORMAT_BIN: Binary data format
01042   *             @arg RTC_FORMAT_BCD: BCD data format
01043   * @retval HAL status
01044   */
01045 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01046 {
01047   uint32_t tickstart;
01048   uint32_t tmpreg;
01049   uint32_t subsecondtmpreg;
01050
01051   /* Check the parameters */
01052   assert_param(IS_RTC_FORMAT(Format));
01053   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01054   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01055   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01056   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01057   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01058
01059   /* Process Locked */
01060   __HAL_LOCK(hrtc);
01061
01062   hrtc->State = HAL_RTC_STATE_BUSY;
01063
01064   if(Format == RTC_FORMAT_BIN)
01065   {
01066     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01067     {
01068       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01069       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01070     }
01071     else
01072     {
01073       sAlarm->AlarmTime.TimeFormat = 0x00U;
01074       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01075     }
01076     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01077     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01078
01079     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01080     {
01081       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01082     }
01083     else
01084     {
01085       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01086     }
01087
01088     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
01089               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01090               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
01091               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
01092               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
01093               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01094               ((uint32_t)sAlarm->AlarmMask));
01095   }
01096   else
01097   {
01098     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01099     {
01100       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01101       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01102     }
01103     else
01104     {
01105       sAlarm->AlarmTime.TimeFormat = 0x00U;
01106       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01107     }
01108
01109     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01110     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01111
01112     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01113     {
01114       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01115     }
01116     else
01117     {
01118       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01119     }
01120
01121     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
01122               ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01123               ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
01124               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
01125               ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
01126               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01127               ((uint32_t)sAlarm->AlarmMask));
01128   }
01129
01130   /* Configure the Alarm A or Alarm B Sub Second registers */
01131   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01132
01133   /* Disable the write protection for RTC registers */
01134   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01135
01136   /* Configure the Alarm register */
01137   if(sAlarm->Alarm == RTC_ALARM_A)
01138   {
01139     /* Disable the Alarm A interrupt */
01140     __HAL_RTC_ALARMA_DISABLE(hrtc);
01141
01142     /* In case of interrupt mode is used, the interrupt source must disabled */
01143     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01144
01145     tickstart = HAL_GetTick();
01146     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01147     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01148     {
01149       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01150       {
01151         /* Enable the write protection for RTC registers */
01152         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01153
01154         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01155
01156         /* Process Unlocked */
01157         __HAL_UNLOCK(hrtc);
01158
01159         return HAL_TIMEOUT;
01160       }
01161     }
01162
01163     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01164     /* Configure the Alarm A Sub Second register */
01165     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01166     /* Configure the Alarm state: Enable Alarm */
01167     __HAL_RTC_ALARMA_ENABLE(hrtc);
01168   }
01169   else
01170   {
01171     /* Disable the Alarm B interrupt */
01172     __HAL_RTC_ALARMB_DISABLE(hrtc);
01173
01174     /* In case of interrupt mode is used, the interrupt source must disabled */
01175     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
01176
01177     tickstart = HAL_GetTick();
01178     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01179     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01180     {
01181       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01182       {
01183         /* Enable the write protection for RTC registers */
01184         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01185
01186         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01187
01188         /* Process Unlocked */
01189         __HAL_UNLOCK(hrtc);
01190
01191         return HAL_TIMEOUT;
01192       }
01193     }
01194
01195     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01196     /* Configure the Alarm B Sub Second register */
01197     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01198     /* Configure the Alarm state: Enable Alarm */
01199     __HAL_RTC_ALARMB_ENABLE(hrtc);
01200   }
01201
01202   /* Enable the write protection for RTC registers */
01203   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01204
01205   /* Change RTC state */
01206   hrtc->State = HAL_RTC_STATE_READY;
01207
01208   /* Process Unlocked */
01209   __HAL_UNLOCK(hrtc);
01210
01211   return HAL_OK;
01212 }
01213
01214 /**
01215   * @brief  Set the specified RTC Alarm with Interrupt.
01216   * @note   The Alarm register can only be written when the corresponding Alarm
01217   *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
01218   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
01219   * @param  hrtc RTC handle
01220   * @param  sAlarm Pointer to Alarm structure
01221   * @param  Format Specifies the format of the entered parameters.
01222   *          This parameter can be one of the following values:
01223   *             @arg RTC_FORMAT_BIN: Binary data format
01224   *             @arg RTC_FORMAT_BCD: BCD data format
01225   * @retval HAL status
01226   */
01227 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01228 {
01229   uint32_t tickstart;
01230   uint32_t tmpreg;
01231   uint32_t subsecondtmpreg;
01232
01233   /* Check the parameters */
01234   assert_param(IS_RTC_FORMAT(Format));
01235   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01236   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01237   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01238   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01239   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01240
01241   /* Process Locked */
01242   __HAL_LOCK(hrtc);
01243
01244   hrtc->State = HAL_RTC_STATE_BUSY;
01245
01246   if(Format == RTC_FORMAT_BIN)
01247   {
01248     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01249     {
01250       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01251       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01252     }
01253     else
01254     {
01255       sAlarm->AlarmTime.TimeFormat = 0x00U;
01256       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01257     }
01258     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01259     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01260
01261     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01262     {
01263       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01264     }
01265     else
01266     {
01267       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01268     }
01269     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
01270               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01271               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
01272               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
01273               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
01274               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01275               ((uint32_t)sAlarm->AlarmMask));
01276   }
01277   else
01278   {
01279     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01280     {
01281       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01282       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01283     }
01284     else
01285     {
01286       sAlarm->AlarmTime.TimeFormat = 0x00U;
01287       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01288     }
01289
01290     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01291     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01292
01293     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01294     {
01295       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01296     }
01297     else
01298     {
01299       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01300     }
01301     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
01302               ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
01303               ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
01304               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
01305               ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
01306               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01307               ((uint32_t)sAlarm->AlarmMask));
01308   }
01309   /* Configure the Alarm A or Alarm B Sub Second registers */
01310   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01311
01312   /* Disable the write protection for RTC registers */
01313   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01314
01315   /* Configure the Alarm register */
01316   if(sAlarm->Alarm == RTC_ALARM_A)
01317   {
01318     /* Disable the Alarm A interrupt */
01319     __HAL_RTC_ALARMA_DISABLE(hrtc);
01320
01321     /* Clear flag alarm A */
01322     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01323
01324     tickstart = HAL_GetTick();
01325     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01326     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01327     {
01328       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01329       {
01330         /* Enable the write protection for RTC registers */
01331         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01332
01333         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01334
01335         /* Process Unlocked */
01336         __HAL_UNLOCK(hrtc);
01337
01338         return HAL_TIMEOUT;
01339       }
01340     }
01341
01342     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01343     /* Configure the Alarm A Sub Second register */
01344     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01345     /* Configure the Alarm state: Enable Alarm */
01346     __HAL_RTC_ALARMA_ENABLE(hrtc);
01347     /* Configure the Alarm interrupt */
01348     __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
01349   }
01350   else
01351   {
01352     /* Disable the Alarm B interrupt */
01353     __HAL_RTC_ALARMB_DISABLE(hrtc);
01354
01355     /* Clear flag alarm B */
01356     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_CLEAR_ALRBF);
01357
01358     tickstart = HAL_GetTick();
01359     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01360     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01361     {
01362       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01363       {
01364         /* Enable the write protection for RTC registers */
01365         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01366
01367         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01368
01369         /* Process Unlocked */
01370         __HAL_UNLOCK(hrtc);
01371
01372         return HAL_TIMEOUT;
01373       }
01374     }
01375
01376     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01377     /* Configure the Alarm B Sub Second register */
01378     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01379     /* Configure the Alarm state: Enable Alarm */
01380     __HAL_RTC_ALARMB_ENABLE(hrtc);
01381     /* Configure the Alarm interrupt */
01382     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
01383   }
01384
01385   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01386   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01387
01388   /* Enable the write protection for RTC registers */
01389   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01390
01391   hrtc->State = HAL_RTC_STATE_READY;
01392
01393   /* Process Unlocked */
01394   __HAL_UNLOCK(hrtc);
01395
01396   return HAL_OK;
01397 }
01398
01399 /**
01400   * @brief  Deactivate the specified RTC Alarm.
01401   * @param  hrtc RTC handle
01402   * @param  Alarm Specifies the Alarm.
01403   *          This parameter can be one of the following values:
01404   *            @arg RTC_ALARM_A:  AlarmA
01405   *            @arg RTC_ALARM_B:  AlarmB
01406   * @retval HAL status
01407   */
01408 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01409 {
01410   uint32_t tickstart;
01411
01412   /* Check the parameters */
01413   assert_param(IS_RTC_ALARM(Alarm));
01414
01415   /* Process Locked */
01416   __HAL_LOCK(hrtc);
01417
01418   hrtc->State = HAL_RTC_STATE_BUSY;
01419
01420   /* Disable the write protection for RTC registers */
01421   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01422
01423   if(Alarm == RTC_ALARM_A)
01424   {
01425     /* AlarmA */
01426     __HAL_RTC_ALARMA_DISABLE(hrtc);
01427
01428     /* In case of interrupt mode is used, the interrupt source must disabled */
01429     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01430
01431     tickstart = HAL_GetTick();
01432
01433     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01434     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01435     {
01436       if( (HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
01437       {
01438         /* Enable the write protection for RTC registers */
01439         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01440
01441         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01442
01443         /* Process Unlocked */
01444         __HAL_UNLOCK(hrtc);
01445
01446         return HAL_TIMEOUT;
01447       }
01448     }
01449   }
01450   else
01451   {
01452     /* AlarmB */
01453     __HAL_RTC_ALARMB_DISABLE(hrtc);
01454
01455     /* In case of interrupt mode is used, the interrupt source must disabled */
01456     __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
01457
01458     tickstart = HAL_GetTick();
01459
01460     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01461     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01462     {
01463       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01464       {
01465         /* Enable the write protection for RTC registers */
01466         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01467
01468         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01469
01470         /* Process Unlocked */
01471         __HAL_UNLOCK(hrtc);
01472
01473         return HAL_TIMEOUT;
01474       }
01475     }
01476   }
01477   /* Enable the write protection for RTC registers */
01478   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01479
01480   hrtc->State = HAL_RTC_STATE_READY;
01481
01482   /* Process Unlocked */
01483   __HAL_UNLOCK(hrtc);
01484
01485   return HAL_OK;
01486 }
01487
01488 /**
01489   * @brief  Get the RTC Alarm value and masks.
01490   * @param  hrtc RTC handle
01491   * @param  sAlarm Pointer to Date structure
01492   * @param  Alarm Specifies the Alarm.
01493   *          This parameter can be one of the following values:
01494   *             @arg RTC_ALARM_A: AlarmA
01495   *             @arg RTC_ALARM_B: AlarmB
01496   * @param  Format Specifies the format of the entered parameters.
01497   *          This parameter can be one of the following values:
01498   *             @arg RTC_FORMAT_BIN: Binary data format
01499   *             @arg RTC_FORMAT_BCD: BCD data format
01500   * @retval HAL status
01501   */
01502 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01503 {
01504   uint32_t tmpreg;
01505   uint32_t subsecondtmpreg;
01506
01507   /* Check the parameters */
01508   assert_param(IS_RTC_FORMAT(Format));
01509   assert_param(IS_RTC_ALARM(Alarm));
01510
01511   if(Alarm == RTC_ALARM_A)
01512   {
01513     /* AlarmA */
01514     sAlarm->Alarm = RTC_ALARM_A;
01515
01516     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
01517     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
01518
01519     /* Fill the structure with the read parameters */
01520     sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos);
01521     sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos);
01522     sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos);
01523     sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos);
01524     sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01525     sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos);
01526     sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01527     sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01528   }
01529   else
01530   {
01531     sAlarm->Alarm = RTC_ALARM_B;
01532
01533     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
01534     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01535
01536     /* Fill the structure with the read parameters */
01537     sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos);
01538     sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos);
01539     sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos);
01540     sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos);
01541     sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01542     sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos);
01543     sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL);
01544     sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01545   }
01546
01547   if(Format == RTC_FORMAT_BIN)
01548   {
01549     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01550     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01551     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01552     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01553   }
01554
01555   return HAL_OK;
01556 }
01557
01558 /**
01559   * @brief  Handle Alarm interrupt request.
01560   * @param  hrtc RTC handle
01561   * @retval None
01562   */
01563 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
01564 {
01565   /* Get the AlarmA interrupt source enable status */
01566   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
01567   {
01568     /* Get the pending status of the AlarmA Interrupt */
01569     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
01570     {
01571       /* Clear the AlarmA interrupt pending bit */
01572       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01573
01574 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01575       /* Call Compare Match registered Callback */
01576       hrtc->AlarmAEventCallback(hrtc);
01577 #else
01578       /* AlarmA callback */
01579       HAL_RTC_AlarmAEventCallback(hrtc);
01580 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01581     }
01582   }
01583
01584   /* Get the AlarmB interrupt source enable status */
01585   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U)
01586   {
01587     /* Get the pending status of the AlarmB Interrupt */
01588     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U)
01589     {
01590       /* Clear the AlarmB interrupt pending bit */
01591       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_CLEAR_ALRBF);
01592
01593 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01594       /* Call Compare Match registered Callback */
01595       hrtc->AlarmBEventCallback(hrtc);
01596 #else
01597       /* AlarmB callback */
01598       HAL_RTCEx_AlarmBEventCallback(hrtc);
01599 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01600     }
01601   }
01602
01603   /* Change RTC state */
01604   hrtc->State = HAL_RTC_STATE_READY;
01605 }
01606
01607 /**
01608   * @brief  Alarm A callback.
01609   * @param  hrtc RTC handle
01610   * @retval None
01611   */
01612 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01613 {
01614   /* Prevent unused argument(s) compilation warning */
01615   UNUSED(hrtc);
01616
01617   /* NOTE : This function should not be modified, when the callback is needed,
01618             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01619    */
01620 }
01621
01622 /**
01623   * @brief  Handle AlarmA Polling request.
01624   * @param  hrtc RTC handle
01625   * @param  Timeout Timeout duration
01626   * @retval HAL status
01627   */
01628 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01629 {
01630
01631   uint32_t tickstart = HAL_GetTick();
01632
01633   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
01634   {
01635     if(Timeout != HAL_MAX_DELAY)
01636     {
01637       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01638       {
01639         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01640         return HAL_TIMEOUT;
01641       }
01642     }
01643   }
01644
01645   /* Clear the Alarm interrupt pending bit */
01646   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01647
01648   /* Change RTC state */
01649   hrtc->State = HAL_RTC_STATE_READY;
01650
01651   return HAL_OK;
01652 }
01653
01654 /**
01655   * @}
01656   */
01657
01658 /** @addtogroup RTC_Exported_Functions_Group4
01659  *  @brief   Peripheral Control functions
01660  *
01661 @verbatim
01662  ===============================================================================
01663                      ##### Peripheral Control functions #####
01664  ===============================================================================
01665     [..]
01666     This subsection provides functions allowing to
01667       (+) Wait for RTC Time and Date Synchronization
01668
01669 @endverbatim
01670   * @{
01671   */
01672
01673 /**
01674   * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01675   *         synchronized with RTC APB clock.
01676   * @note   The RTC Resynchronization mode is write protected, use the
01677   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01678   * @note   To read the calendar through the shadow registers after Calendar
01679   *         initialization, calendar update or after wakeup from low power modes
01680   *         the software must first clear the RSF flag.
01681   *         The software must then wait until it is set again before reading
01682   *         the calendar, which means that the calendar registers have been
01683   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01684   * @param  hrtc RTC handle
01685   * @retval HAL status
01686   */
01687 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
01688 {
01689   uint32_t tickstart;
01690
01691   /* Clear RSF flag */
01692   hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK;
01693
01694   tickstart = HAL_GetTick();
01695
01696   /* Wait the registers to be synchronised */
01697   while((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U)
01698   {
01699     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01700     {
01701       return HAL_TIMEOUT;
01702     }
01703   }
01704
01705   return HAL_OK;
01706 }
01707
01708 /**
01709   * @}
01710   */
01711
01712 /** @addtogroup RTC_Exported_Functions_Group5
01713  *  @brief   Peripheral State functions
01714  *
01715 @verbatim
01716  ===============================================================================
01717                      ##### Peripheral State functions #####
01718  ===============================================================================
01719     [..]
01720     This subsection provides functions allowing to
01721       (+) Get RTC state
01722
01723 @endverbatim
01724   * @{
01725   */
01726 /**
01727   * @brief  Return the RTC handle state.
01728   * @param  hrtc RTC handle
01729   * @retval HAL state
01730   */
01731 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
01732 {
01733   /* Return RTC handle state */
01734   return hrtc->State;
01735 }
01736
01737 /**
01738   * @}
01739   */
01740 /**
01741   * @}
01742   */
01743
01744 /** @addtogroup RTC_Private_Functions
01745   * @{
01746   */
01747 /**
01748   * @brief  Enter the RTC Initialization mode.
01749   * @note   The RTC Initialization mode is write protected, use the
01750   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01751   * @param  hrtc RTC handle
01752   * @retval HAL status
01753   */
01754 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
01755 {
01756   uint32_t tickstart;
01757   HAL_StatusTypeDef status = HAL_OK;
01758
01759   /* Check if the Initialization mode is set */
01760   if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
01761   {
01762     /* Set the Initialization mode */
01763     SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
01764
01765     tickstart = HAL_GetTick();
01766     /* Wait till RTC is in INIT state and if Time out is reached exit */
01767     while(((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
01768     {
01769       if((HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
01770       {
01771         status = HAL_TIMEOUT;
01772         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01773       }
01774     }
01775   }
01776
01777   return status;
01778 }
01779
01780 /**
01781   * @brief  Exit the RTC Initialization mode.
01782   * @param  hrtc RTC handle
01783   * @retval HAL status
01784   */
01785 HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
01786 {
01787   HAL_StatusTypeDef status = HAL_OK;
01788
01789   /* Exit Initialization mode */
01790   CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
01791
01792   /* If CR_BYPSHAD bit = 0, wait for synchro */
01793   if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
01794   {
01795     if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01796     {
01797       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01798       status = HAL_TIMEOUT;
01799     }
01800   }
01801   else /* WA 2.7.1 Calendar initialization may fail in case of consecutive INIT mode entry.
01802           Please look at STM32G0 Errata sheet on the internet for details. */
01803   {
01804     /* Clear BYPSHAD bit */
01805     CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
01806     if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01807     {
01808       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01809       status = HAL_TIMEOUT;
01810     }
01811     /* Restore BYPSHAD bit */
01812     SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
01813   }
01814
01815   return status;
01816 }
01817 /**
01818   * @brief  Convert a 2 digit decimal to BCD format.
01819   * @param  Value Byte to be converted
01820   * @retval Converted byte
01821   */
01822 uint8_t RTC_ByteToBcd2(uint8_t Value)
01823 {
01824   uint32_t bcdhigh = 0U;
01825   uint8_t Param = Value;
01826
01827   while(Param >= 10U)
01828   {
01829     bcdhigh++;
01830     Param -= 10U;
01831   }
01832
01833   return  ((uint8_t)(bcdhigh << 4U) | Param);
01834 }
01835
01836 /**
01837   * @brief  Convert from 2 digit BCD to Binary.
01838   * @param  Value BCD value to be converted
01839   * @retval Converted word
01840   */
01841 uint8_t RTC_Bcd2ToByte(uint8_t Value)
01842 {
01843   uint32_t tmp;
01844   tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U;
01845   return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
01846 }
01847
01848 /**
01849   * @brief  Daylight Saving Time, Add one hour to the calendar in one single operation
01850   *         without going through the initialization procedure.
01851   * @param  hrtc RTC handle
01852   * @retval None
01853   */
01854 void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
01855 {
01856   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01857   SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H);
01858   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01859 }
01860
01861 /**
01862   * @brief  Daylight Saving Time, Subtract one hour from the calendar in one
01863   *         single operation without going through the initialization procedure.
01864   * @param  hrtc RTC handle
01865   * @retval None
01866   */
01867 void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
01868 {
01869   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01870   SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H);
01871   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01872 }
01873
01874 /**
01875   * @brief  Daylight Saving Time, Set the store operation bit.
01876   * @note   It can be used by the software in order to memorize the DST status.
01877   * @param  hrtc RTC handle
01878   * @retval None
01879   */
01880 void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
01881 {
01882   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01883   SET_BIT(hrtc->Instance->CR, RTC_CR_BKP);
01884   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01885 }
01886
01887 /**
01888   * @brief  Daylight Saving Time, Clear the store operation bit.
01889   * @param  hrtc RTC handle
01890   * @retval None
01891   */
01892 void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
01893 {
01894   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01895   CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP);
01896   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01897 }
01898
01899 /**
01900   * @brief  Daylight Saving Time, Read the store operation bit.
01901   * @param  hrtc RTC handle
01902   * @retval operation see RTC_StoreOperation_Definitions
01903   */
01904 uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
01905 {
01906   return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);
01907 }
01908
01909 /**
01910   * @}
01911   */
01912
01913 #endif /* HAL_RTC_MODULE_ENABLED */
01914 /**
01915   * @}
01916   */
01917
01918 /**
01919   * @}
01920   */
01921
01922
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rtc.h Source File

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stm32g0xx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_RTC_H
00021 #define STM32G0xx_HAL_RTC_H
00022
00023 #ifdef __cplusplus
00024  extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup RTC RTC
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup RTC_Exported_Types RTC Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  HAL State structures definition
00045   */
00046 typedef enum
00047 {
00048   HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
00049   HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
00050   HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
00051   HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
00052   HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
00053
00054 }HAL_RTCStateTypeDef;
00055
00056 /**
00057   * @brief  RTC Configuration Structure definition
00058   */
00059 typedef struct
00060 {
00061   uint32_t HourFormat;        /*!< Specifies the RTC Hour Format.
00062                                  This parameter can be a value of @ref RTC_Hour_Formats */
00063
00064   uint32_t AsynchPrediv;      /*!< Specifies the RTC Asynchronous Predivider value.
00065                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00066
00067   uint32_t SynchPrediv;       /*!< Specifies the RTC Synchronous Predivider value.
00068                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
00069
00070   uint32_t OutPut;            /*!< Specifies which signal will be routed to the RTC output.
00071                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
00072
00073   uint32_t OutPutRemap;       /*!< Specifies the remap for RTC output.
00074                                  This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
00075
00076   uint32_t OutPutPolarity;    /*!< Specifies the polarity of the output signal.
00077                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00078
00079   uint32_t OutPutType;        /*!< Specifies the RTC Output Pin mode.
00080                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00081
00082   uint32_t OutPutPullUp;      /*!< Specifies the RTC Output Pull-Up mode.
00083                                  This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
00084 }RTC_InitTypeDef;
00085
00086 /**
00087   * @brief  RTC Time structure definition
00088   */
00089 typedef struct
00090 {
00091   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00092                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00093                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
00094
00095   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00096                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00097
00098   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00099                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00100
00101   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00102                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00103
00104   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
00105                                  This parameter corresponds to a time unit range between [0-1] Second
00106                                  with [1 Sec / SecondFraction +1] granularity */
00107
00108   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
00109                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
00110                                  This parameter corresponds to a time unit range between [0-1] Second
00111                                  with [1 Sec / SecondFraction +1] granularity.
00112                                  This field will be used only by HAL_RTC_GetTime function */
00113
00114   uint32_t DayLightSaving;  /*!< This interface is deprecated. To manage Daylight Saving Time,
00115                                  please use HAL_RTC_DST_xxx functions */
00116
00117   uint32_t StoreOperation;  /*!< This interface is deprecated. To manage Daylight Saving Time,
00118                                  please use HAL_RTC_DST_xxx functions */
00119 }RTC_TimeTypeDef;
00120
00121 /**
00122   * @brief  RTC Date structure definition
00123   */
00124 typedef struct
00125 {
00126   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00127                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00128
00129   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00130                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00131
00132   uint8_t Date;     /*!< Specifies the RTC Date.
00133                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00134
00135   uint8_t Year;     /*!< Specifies the RTC Date Year.
00136                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00137
00138 }RTC_DateTypeDef;
00139
00140 /**
00141   * @brief  RTC Alarm structure definition
00142   */
00143 typedef struct
00144 {
00145   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00146
00147   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00148                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00149
00150   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00151                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00152
00153   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00154                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00155
00156   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00157                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00158                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00159
00160   uint32_t Alarm;                /*!< Specifies the alarm .
00161                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00162 }RTC_AlarmTypeDef;
00163
00164 /**
00165   * @brief  RTC Handle Structure definition
00166   */
00167 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00168 typedef struct __RTC_HandleTypeDef
00169 #else
00170 typedef struct
00171 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00172 {
00173   RTC_TypeDef               *Instance;  /*!< Register base address    */
00174
00175   uint32_t                  TampOffset; /*!< Offset to TAMP instance  */
00176
00177   RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
00178
00179   HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
00180
00181   __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
00182
00183 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00184   void  (* AlarmAEventCallback)      ( struct __RTC_HandleTypeDef * hrtc);           /*!< RTC Alarm A Event callback            */
00185
00186   void  (* AlarmBEventCallback)      ( struct __RTC_HandleTypeDef * hrtc);           /*!< RTC Alarm B Event callback            */
00187
00188   void  (* TimeStampEventCallback)   ( struct __RTC_HandleTypeDef * hrtc);           /*!< RTC TimeStamp Event callback          */
00189
00190   void  (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc);           /*!< RTC WakeUpTimer Event callback        */
00191
00192   void  (* Tamper1EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);           /*!< RTC Tamper 1 Event callback           */
00193
00194   void  (* Tamper2EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);           /*!< RTC Tamper 2 Event callback           */
00195
00196 #if defined(TAMP_CR1_TAMP3E)
00197   void  (* Tamper3EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);           /*!< RTC Tamper 3 Event callback           */
00198 #endif /* TAMP_CR1_TAMP3E */
00199
00200   void  (* InternalTamper3EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);   /*!< RTC Internal Tamper 3 Event callback  */
00201
00202   void  (* InternalTamper4EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);   /*!< RTC Internal Tamper 4 Event callback  */
00203
00204   void  (* InternalTamper5EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);   /*!< RTC Internal Tamper 5 Event callback  */
00205
00206   void  (* InternalTamper6EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);   /*!< RTC Internal Tamper 6 Event callback  */
00207
00208
00209   void  (* MspInitCallback)         ( struct __RTC_HandleTypeDef * hrtc);   /*!< RTC Msp Init callback              */
00210
00211   void  (* MspDeInitCallback)       ( struct __RTC_HandleTypeDef * hrtc);   /*!< RTC Msp DeInit callback            */
00212
00213 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00214
00215 }RTC_HandleTypeDef;
00216
00217 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00218 /**
00219   * @brief  HAL RTC Callback ID enumeration definition
00220   */
00221 typedef enum
00222 {
00223   HAL_RTC_ALARM_A_EVENT_CB_ID           = 0x00U,    /*!< RTC Alarm A Event Callback ID      */
00224   HAL_RTC_ALARM_B_EVENT_CB_ID           = 0x01U,    /*!< RTC Alarm B Event Callback ID      */
00225   HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 0x02U,    /*!< RTC TimeStamp Event Callback ID    */
00226   HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 0x03U,    /*!< RTC WakeUp Timer Event Callback ID */
00227   HAL_RTC_TAMPER1_EVENT_CB_ID           = 0x04U,    /*!< RTC Tamper 1 Callback ID           */
00228   HAL_RTC_TAMPER2_EVENT_CB_ID           = 0x05U,    /*!< RTC Tamper 2 Callback ID           */
00229 #if defined(TAMP_CR1_TAMP3E)
00230   HAL_RTC_TAMPER3_EVENT_CB_ID           = 0x06U,    /*!< RTC Tamper 3 Callback ID           */
00231 #endif /* TAMP_CR1_TAMP3E */
00232   HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID  = 0x09U,    /*!< RTC Internal Tamper 3 Callback ID  */
00233   HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID  = 0x0AU,    /*!< RTC Internal Tamper 4 Callback ID  */
00234   HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID  = 0x0BU,    /*!< RTC Internal Tamper 5 Callback ID  */
00235   HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID  = 0x0CU,    /*!< RTC Internal Tamper 6 Callback ID  */
00236   HAL_RTC_MSPINIT_CB_ID                 = 0x0EU,    /*!< RTC Msp Init callback ID           */
00237   HAL_RTC_MSPDEINIT_CB_ID               = 0x0FU     /*!< RTC Msp DeInit callback ID         */
00238 }HAL_RTC_CallbackIDTypeDef;
00239
00240 /**
00241   * @brief  HAL RTC Callback pointer definition
00242   */
00243 typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
00244 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /* Exported constants --------------------------------------------------------*/
00251 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00252   * @{
00253   */
00254
00255 /** @defgroup RTC_Hour_Formats RTC Hour Formats
00256   * @{
00257   */
00258 #define RTC_HOURFORMAT_24                   0x00000000u
00259 #define RTC_HOURFORMAT_12                   RTC_CR_FMT
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
00265   * @{
00266   */
00267 #define RTC_OUTPUT_DISABLE                  0x00000000u
00268 #define RTC_OUTPUT_ALARMA                   RTC_CR_OSEL_0
00269 #define RTC_OUTPUT_ALARMB                   RTC_CR_OSEL_1
00270 #define RTC_OUTPUT_WAKEUP                   RTC_CR_OSEL
00271 #define RTC_OUTPUT_TAMPER                   RTC_CR_TAMPOE
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00277   * @{
00278   */
00279 #define RTC_OUTPUT_POLARITY_HIGH            0x00000000u
00280 #define RTC_OUTPUT_POLARITY_LOW             RTC_CR_POL
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00286   * @{
00287   */
00288 #define RTC_OUTPUT_TYPE_PUSHPULL            0x00000000u
00289 #define RTC_OUTPUT_TYPE_OPENDRAIN           RTC_CR_TAMPALRM_TYPE
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
00295   * @{
00296   */
00297 #define RTC_OUTPUT_PULLUP_NONE              0x00000000u
00298 #define RTC_OUTPUT_PULLUP_ON                RTC_CR_TAMPALRM_PU
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
00304   * @{
00305   */
00306 #define RTC_OUTPUT_REMAP_NONE               0x00000000u
00307 #define RTC_OUTPUT_REMAP_POS1               RTC_CR_OUT2EN
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00313   * @{
00314   */
00315 #define RTC_HOURFORMAT12_AM                 0x0u
00316 #define RTC_HOURFORMAT12_PM                 0x1u
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
00322   * @{
00323   */
00324 #define RTC_DAYLIGHTSAVING_SUB1H            RTC_CR_SUB1H
00325 #define RTC_DAYLIGHTSAVING_ADD1H            RTC_CR_ADD1H
00326 #define RTC_DAYLIGHTSAVING_NONE             0x00000000u
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
00332   * @{
00333   */
00334 #define RTC_STOREOPERATION_RESET            0x00000000u
00335 #define RTC_STOREOPERATION_SET              RTC_CR_BKP
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
00341   * @{
00342   */
00343 #define RTC_FORMAT_BIN                      0x00000000u
00344 #define RTC_FORMAT_BCD                      0x00000001u
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
00350   * @{
00351   */
00352
00353 /* Coded in BCD format */
00354 #define RTC_MONTH_JANUARY                   ((uint8_t)0x01U)
00355 #define RTC_MONTH_FEBRUARY                  ((uint8_t)0x02U)
00356 #define RTC_MONTH_MARCH                     ((uint8_t)0x03U)
00357 #define RTC_MONTH_APRIL                     ((uint8_t)0x04U)
00358 #define RTC_MONTH_MAY                       ((uint8_t)0x05U)
00359 #define RTC_MONTH_JUNE                      ((uint8_t)0x06U)
00360 #define RTC_MONTH_JULY                      ((uint8_t)0x07U)
00361 #define RTC_MONTH_AUGUST                    ((uint8_t)0x08U)
00362 #define RTC_MONTH_SEPTEMBER                 ((uint8_t)0x09U)
00363 #define RTC_MONTH_OCTOBER                   ((uint8_t)0x10U)
00364 #define RTC_MONTH_NOVEMBER                  ((uint8_t)0x11U)
00365 #define RTC_MONTH_DECEMBER                  ((uint8_t)0x12U)
00366
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00372   * @{
00373   */
00374 #define RTC_WEEKDAY_MONDAY                  ((uint8_t)0x01U)
00375 #define RTC_WEEKDAY_TUESDAY                 ((uint8_t)0x02U)
00376 #define RTC_WEEKDAY_WEDNESDAY               ((uint8_t)0x03U)
00377 #define RTC_WEEKDAY_THURSDAY                ((uint8_t)0x04U)
00378 #define RTC_WEEKDAY_FRIDAY                  ((uint8_t)0x05U)
00379 #define RTC_WEEKDAY_SATURDAY                ((uint8_t)0x06U)
00380 #define RTC_WEEKDAY_SUNDAY                  ((uint8_t)0x07U)
00381
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
00387   * @{
00388   */
00389 #define RTC_ALARMDATEWEEKDAYSEL_DATE        0x00000000u
00390 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY     RTC_ALRMAR_WDSEL
00391
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
00397   * @{
00398   */
00399 #define RTC_ALARMMASK_NONE                  0x00000000u
00400 #define RTC_ALARMMASK_DATEWEEKDAY           RTC_ALRMAR_MSK4
00401 #define RTC_ALARMMASK_HOURS                 RTC_ALRMAR_MSK3
00402 #define RTC_ALARMMASK_MINUTES               RTC_ALRMAR_MSK2
00403 #define RTC_ALARMMASK_SECONDS               RTC_ALRMAR_MSK1
00404 #define RTC_ALARMMASK_ALL                   (RTC_ALARMMASK_NONE | RTC_ALARMMASK_DATEWEEKDAY | \
00405                                             RTC_ALARMMASK_HOURS | RTC_ALARMMASK_MINUTES     | \
00406                                             RTC_ALARMMASK_SECONDS)
00407
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00413   * @{
00414   */
00415 #define RTC_ALARM_A                         RTC_CR_ALRAE
00416 #define RTC_ALARM_B                         RTC_CR_ALRBE
00417
00418 /**
00419   * @}
00420   */
00421
00422
00423   /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00424   * @{
00425   */
00426 #define RTC_ALARMSUBSECONDMASK_ALL          0x00000000u                                                              /*!< All Alarm SS fields are masked.
00427                                                                                                                           There is no comparison on sub seconds
00428                                                                                                                           for Alarm */
00429 #define RTC_ALARMSUBSECONDMASK_SS14_1       RTC_ALRMASSR_MASKSS_0                                                    /*!< SS[14:1] not used in Alarm
00430                                                                                                                           comparison. Only SS[0] is compared.    */
00431 #define RTC_ALARMSUBSECONDMASK_SS14_2       RTC_ALRMASSR_MASKSS_1                                                    /*!< SS[14:2] not used in Alarm
00432                                                                                                                           comparison. Only SS[1:0] are compared  */
00433 #define RTC_ALARMSUBSECONDMASK_SS14_3       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)                          /*!< SS[14:3] not used in Alarm
00434                                                                                                                           comparison. Only SS[2:0] are compared  */
00435 #define RTC_ALARMSUBSECONDMASK_SS14_4       RTC_ALRMASSR_MASKSS_2                                                    /*!< SS[14:4] not used in Alarm
00436                                                                                                                           comparison. Only SS[3:0] are compared  */
00437 #define RTC_ALARMSUBSECONDMASK_SS14_5       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)                          /*!< SS[14:5] not used in Alarm
00438                                                                                                                           comparison. Only SS[4:0] are compared  */
00439 #define RTC_ALARMSUBSECONDMASK_SS14_6       (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)                          /*!< SS[14:6] not used in Alarm
00440                                                                                                                           comparison. Only SS[5:0] are compared  */
00441 #define RTC_ALARMSUBSECONDMASK_SS14_7       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)  /*!< SS[14:7] not used in Alarm
00442                                                                                                                           comparison. Only SS[6:0] are compared  */
00443 #define RTC_ALARMSUBSECONDMASK_SS14_8       RTC_ALRMASSR_MASKSS_3                                                    /*!< SS[14:8] not used in Alarm
00444                                                                                                                           comparison. Only SS[7:0] are compared  */
00445 #define RTC_ALARMSUBSECONDMASK_SS14_9       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:9] not used in Alarm
00446                                                                                                                           comparison. Only SS[8:0] are compared  */
00447 #define RTC_ALARMSUBSECONDMASK_SS14_10      (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:10] not used in Alarm
00448                                                                                                                           comparison. Only SS[9:0] are compared  */
00449 #define RTC_ALARMSUBSECONDMASK_SS14_11      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:11] not used in Alarm
00450                                                                                                                           comparison. Only SS[10:0] are compared */
00451 #define RTC_ALARMSUBSECONDMASK_SS14_12      (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:12] not used in Alarm
00452                                                                                                                           comparison.Only SS[11:0] are compared  */
00453 #define RTC_ALARMSUBSECONDMASK_SS14_13      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:13] not used in Alarm
00454                                                                                                                           comparison. Only SS[12:0] are compared */
00455 #define RTC_ALARMSUBSECONDMASK_SS14         (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14] not used in Alarm
00456                                                                                                                           comparison.Only SS[13:0] are compared  */
00457 #define RTC_ALARMSUBSECONDMASK_NONE         RTC_ALRMASSR_MASKSS                                                      /*!< SS[14:0] are compared and must match
00458                                                                                                                           to activate alarm. */
00459 /**
00460   * @}
00461   */
00462
00463 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00464   * @{
00465   */
00466 #define RTC_IT_TS                           RTC_CR_TSIE        /*!< Enable Timestamp Interrupt    */
00467 #define RTC_IT_WUT                          RTC_CR_WUTIE       /*!< Enable Wakeup timer Interrupt */
00468 #define RTC_IT_ALRA                         RTC_CR_ALRAIE      /*!< Enable Alarm A Interrupt      */
00469 #define RTC_IT_ALRB                         RTC_CR_ALRBIE      /*!< Enable Alarm B Interrupt      */
00470 /**
00471   * @}
00472   */
00473
00474 /** @defgroup RTC_Flag_Mask    RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
00475   * @{
00476   */
00477 #define RTC_FLAG_MASK                       0x001Fu        /*!< RTC flags mask (5bits) */
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00483   *        Elements values convention: 000000XX000YYYYYb
00484   *           - YYYYY  : Interrupt flag position in the XX register (5bits)
00485   *           - XX  : Interrupt status register (2bits)
00486   *                 - 01: ICSR register
00487   *                 - 10: SR or SCR or MISR or SMISR registers
00488   * @{
00489   */
00490 #define RTC_FLAG_RECALPF                    (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
00491 #define RTC_FLAG_INITF                      (0x00000100U | RTC_ICSR_INITF_Pos)   /*!< Initialization flag */
00492 #define RTC_FLAG_RSF                        (0x00000100U | RTC_ICSR_RSF_Pos)     /*!< Registers synchronization flag */
00493 #define RTC_FLAG_INITS                      (0x00000100U | RTC_ICSR_INITS_Pos)   /*!< Initialization status flag */
00494 #define RTC_FLAG_SHPF                       (0x00000100U | RTC_ICSR_SHPF_Pos)    /*!< Shift operation pending flag */
00495 #define RTC_FLAG_WUTWF                      (0x00000100U | RTC_ICSR_WUTWF_Pos)   /*!< Wakeup timer write flag */
00496 #define RTC_FLAG_ALRBWF                     (0x00000100U | RTC_ICSR_ALRBWF_Pos)  /*!< Alarm B write flag */
00497 #define RTC_FLAG_ALRAWF                     (0x00000100U | RTC_ICSR_ALRAWF_Pos)  /*!< Alarm A write flag */
00498 #define RTC_FLAG_ITSF                       (0x00000200U | RTC_SR_ITSF_Pos)      /*!< Internal Time-stamp flag */
00499 #define RTC_FLAG_TSOVF                      (0x00000200U | RTC_SR_TSOVF_Pos)     /*!< Time-stamp overflow flag */
00500 #define RTC_FLAG_TSF                        (0x00000200U | RTC_SR_TSF_Pos)       /*!< Time-stamp flag */
00501 #define RTC_FLAG_WUTF                       (0x00000200U | RTC_SR_WUTF_Pos)      /*!< Wakeup timer flag */
00502 #define RTC_FLAG_ALRBF                      (0x00000200U | RTC_SR_ALRBF_Pos)     /*!< Alarm B flag */
00503 #define RTC_FLAG_ALRAF                      (0x00000200U | RTC_SR_ALRAF_Pos)     /*!< Alarm A flag */
00504 /**
00505   * @}
00506   */
00507
00508 /** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
00509   * @{
00510   */
00511 #define RTC_CLEAR_ITSF                      RTC_SCR_CITSF    /*!< Clear Internal Time-stamp flag */
00512 #define RTC_CLEAR_TSOVF                     RTC_SCR_CTSOVF   /*!< Clear Time-stamp overflow flag */
00513 #define RTC_CLEAR_TSF                       RTC_SCR_CTSF     /*!< Clear Time-stamp flag */
00514 #define RTC_CLEAR_WUTF                      RTC_SCR_CWUTF    /*!< Clear Wakeup timer flag */
00515 #define RTC_CLEAR_ALRBF                     RTC_SCR_CALRBF   /*!< Clear Alarm B flag */
00516 #define RTC_CLEAR_ALRAF                     RTC_SCR_CALRAF   /*!< Clear Alarm A flag */
00517 /**
00518   * @}
00519   */
00520
00521 /**
00522   * @}
00523   */
00524
00525 /* Exported macros -----------------------------------------------------------*/
00526 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00527   * @{
00528   */
00529
00530 /** @brief Reset RTC handle state
00531   * @param  __HANDLE__ RTC handle.
00532   * @retval None
00533   */
00534 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00535 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
00536                                                       (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
00537                                                       (__HANDLE__)->MspInitCallback = NULL;\
00538                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00539                                                      }while(0)
00540 #else
00541 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00542 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00543
00544 /**
00545   * @brief  Disable the write protection for RTC registers.
00546   * @param  __HANDLE__ specifies the RTC handle.
00547   * @retval None
00548   */
00549 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
00550                         do{                                       \
00551                             (__HANDLE__)->Instance->WPR = 0xCAU;   \
00552                             (__HANDLE__)->Instance->WPR = 0x53U;   \
00553                           } while(0U)
00554
00555 /**
00556   * @brief  Enable the write protection for RTC registers.
00557   * @param  __HANDLE__ specifies the RTC handle.
00558   * @retval None
00559   */
00560 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
00561                         do{                                       \
00562                             (__HANDLE__)->Instance->WPR = 0xFFU;   \
00563                           } while(0U)
00564
00565 /**
00566   * @brief  Check whether the RTC Calendar is initialized.
00567   * @param  __HANDLE__ specifies the RTC handle.
00568   * @retval None
00569   */
00570 #define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__)  (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
00571
00572 /**
00573   * @brief  Add 1 hour (summer time change).
00574   * @note   This interface is deprecated.
00575   *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
00576   * @param  __HANDLE__ specifies the RTC handle.
00577   * @param  __BKP__ Backup
00578   *         This parameter can be:
00579   *            @arg @ref RTC_STOREOPERATION_RESET
00580   *            @arg @ref RTC_STOREOPERATION_SET
00581   * @retval None
00582   */
00583 #define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)                         \
00584                         do {                                                              \
00585                             __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
00586                             SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H);            \
00587                             MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
00588                             __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
00589                         } while(0);
00590
00591 /**
00592   * @brief  Subtract 1 hour (winter time change).
00593   * @note   This interface is deprecated.
00594   *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
00595   * @param  __HANDLE__ specifies the RTC handle.
00596   * @param  __BKP__ Backup
00597   *         This parameter can be:
00598   *            @arg @ref RTC_STOREOPERATION_RESET
00599   *            @arg @ref RTC_STOREOPERATION_SET
00600   * @retval None
00601   */
00602 #define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)                         \
00603                         do {                                                              \
00604                             __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
00605                             SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H);            \
00606                             MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
00607                             __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
00608                         } while(0);
00609
00610  /**
00611   * @brief  Enable the RTC ALARMA peripheral.
00612   * @param  __HANDLE__ specifies the RTC handle.
00613   * @retval None
00614   */
00615 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00616
00617 /**
00618   * @brief  Disable the RTC ALARMA peripheral.
00619   * @param  __HANDLE__ specifies the RTC handle.
00620   * @retval None
00621   */
00622 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00623
00624 /**
00625   * @brief  Enable the RTC ALARMB peripheral.
00626   * @param  __HANDLE__ specifies the RTC handle.
00627   * @retval None
00628   */
00629 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00630
00631 /**
00632   * @brief  Disable the RTC ALARMB peripheral.
00633   * @param  __HANDLE__ specifies the RTC handle.
00634   * @retval None
00635   */
00636 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00637
00638 /**
00639   * @brief  Enable the RTC Alarm interrupt.
00640   * @param  __HANDLE__ specifies the RTC handle.
00641   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00642   *          This parameter can be any combination of the following values:
00643   *             @arg @ref RTC_IT_ALRA Alarm A interrupt, @ref RTC_Interrupts_Definitions
00644   *             @arg @ref RTC_IT_ALRB Alarm B interrupt
00645   * @retval None
00646   */
00647 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00648
00649 /**
00650   * @brief  Disable the RTC Alarm interrupt.
00651   * @param  __HANDLE__ specifies the RTC handle.
00652   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00653   *         This parameter can be any combination of the following values:
00654   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00655   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00656   * @retval None
00657   */
00658 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00659
00660 /**
00661   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00662   * @param  __HANDLE__ specifies the RTC handle.
00663   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00664   *         This parameter can be:
00665   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00666   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00667   * @retval None
00668   */
00669 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR)& ((__INTERRUPT__)>> 12U)) != 0U)? 1U : 0U)
00670
00671 /**
00672   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
00673   * @param  __HANDLE__ specifies the RTC handle.
00674   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00675   *         This parameter can be:
00676   *            @arg @ref RTC_IT_ALRA Alarm A interrupt
00677   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
00678   * @retval None
00679   */
00680 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00681
00682 /**
00683   * @brief  Get the selected RTC Alarms flag status.
00684   * @param  __HANDLE__ specifies the RTC handle.
00685   * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
00686   *         This parameter can be:
00687   *            @arg @ref RTC_FLAG_ALRAF
00688   *            @arg @ref RTC_FLAG_ALRBF
00689   *            @arg @ref RTC_FLAG_ALRAWF
00690   *            @arg @ref RTC_FLAG_ALRBWF
00691   * @retval None
00692   */
00693 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
00694
00695 /**
00696   * @brief  Clear the RTC Alarms pending flags.
00697   * @param  __HANDLE__ specifies the RTC handle.
00698   * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
00699   *          This parameter can be:
00700   *             @arg @ref RTC_FLAG_ALRAF
00701   *             @arg @ref RTC_FLAG_ALRBF
00702   * @retval None
00703   */
00704 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)   (((__FLAG__) == RTC_FLAG_ALRAF) ? (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ALRAF)) : \
00705                                                             (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ALRBF)))
00706
00707 /**
00708   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
00709   * @retval None
00710   */
00711 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00712
00713 /**
00714   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
00715   * @retval None
00716   */
00717 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00718
00719 /**
00720   * @brief  Enable event on the RTC Alarm associated Exti line.
00721   * @retval None.
00722   */
00723 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00724
00725 /**
00726   * @brief  Disable event on the RTC Alarm associated Exti line.
00727   * @retval None.
00728   */
00729 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00730
00731 /**
00732   * @}
00733   */
00734
00735 /* Include RTC HAL Extended module */
00736 #include "stm32g0xx_hal_rtc_ex.h"
00737
00738 /* Exported functions --------------------------------------------------------*/
00739 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00740   * @{
00741   */
00742
00743 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
00744   * @{
00745   */
00746 /* Initialization and de-initialization functions  ****************************/
00747 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00748 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00749
00750 void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00751 void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00752
00753 /* Callbacks Register/UnRegister functions  ***********************************/
00754 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00755 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
00756 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
00757 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00758
00759 /**
00760   * @}
00761   */
00762
00763 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
00764   * @{
00765   */
00766 /* RTC Time and Date functions ************************************************/
00767 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00768 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00769 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00770 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00771 void              HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
00772 void              HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
00773 void              HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
00774 void              HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
00775 uint32_t          HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
00776 /**
00777   * @}
00778   */
00779
00780 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
00781   * @{
00782   */
00783 /* RTC Alarm functions ********************************************************/
00784 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00785 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00786 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00787 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00788 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00789 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00790 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00791 /**
00792   * @}
00793   */
00794
00795 /** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
00796   * @{
00797   */
00798 /* Peripheral Control functions ***********************************************/
00799 HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
00800 /**
00801   * @}
00802   */
00803
00804 /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
00805   * @{
00806   */
00807 /* Peripheral State functions *************************************************/
00808 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00809 /**
00810   * @}
00811   */
00812
00813 /**
00814   * @}
00815   */
00816
00817 /* Private types -------------------------------------------------------------*/
00818 /* Private variables ---------------------------------------------------------*/
00819 /* Private constants ---------------------------------------------------------*/
00820 /** @defgroup RTC_Private_Constants RTC Private Constants
00821   * @{
00822   */
00823 /* Masks Definition */
00824 #define RTC_TR_RESERVED_MASK                (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
00825                                             RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
00826                                             RTC_TR_SU)
00827 #define RTC_DR_RESERVED_MASK                (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
00828                                             RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
00829                                             RTC_DR_DU)
00830 #define RTC_INIT_MASK                       0xFFFFFFFFu
00831 #define RTC_RSF_MASK                        (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
00832
00833 #define RTC_TIMEOUT_VALUE                   1000u
00834
00835 #define RTC_EXTI_LINE_ALARM_EVENT           EXTI_IMR1_IM19  /*!< External interrupt line 19 Connected to the RTC Alarm event */
00836
00837 /**
00838   * @}
00839   */
00840
00841 /* Private macros ------------------------------------------------------------*/
00842 /** @defgroup RTC_Private_Macros RTC Private Macros
00843   * @{
00844   */
00845
00846 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
00847   * @{
00848   */
00849 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
00850                                 ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
00851                                 ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
00852                                 ((OUTPUT) == RTC_OUTPUT_WAKEUP)  || \
00853                                 ((OUTPUT) == RTC_OUTPUT_TAMPER))
00854
00855 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
00856                                         ((FORMAT) == RTC_HOURFORMAT_24))
00857
00858 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
00859                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
00860
00861 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
00862                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
00863
00864 #define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
00865                                     ((TYPE) == RTC_OUTPUT_PULLUP_ON))
00866
00867 #define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
00868                                       ((REMAP) == RTC_OUTPUT_REMAP_POS1))
00869
00870 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
00871                                   ((PM) == RTC_HOURFORMAT12_PM))
00872
00873 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
00874                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
00875                                       ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
00876
00877 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
00878                                            ((OPERATION) == RTC_STOREOPERATION_SET))
00879
00880 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
00881                                ((FORMAT) == RTC_FORMAT_BCD))
00882
00883 #define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99u)
00884
00885 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1u) && ((MONTH) <= 12u))
00886
00887 #define IS_RTC_DATE(DATE)              (((DATE) >= 1u) && ((DATE) <= 31u))
00888
00889 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00890                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00891                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00892                                  ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00893                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00894                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00895                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00896
00897 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
00898
00899 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00900                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00901                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00902                                                     ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00903                                                     ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00904                                                     ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00905                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00906
00907 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
00908                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
00909
00910 #define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)
00911
00912 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || \
00913                                   ((ALARM) == RTC_ALARM_B))
00914
00915 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
00916
00917 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
00918                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
00919                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
00920                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
00921                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
00922                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
00923                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
00924                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
00925                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
00926                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
00927                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
00928                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
00929                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
00930                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
00931                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
00932                                               ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
00933
00934 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7Fu)
00935
00936 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFFu)
00937
00938 #define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0u) && ((HOUR) <= 12u))
00939
00940 #define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23u)
00941
00942 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59u)
00943
00944 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59u)
00945
00946 /**
00947   * @}
00948   */
00949
00950 /**
00951   * @}
00952   */
00953
00954 /* Private functions -------------------------------------------------------------*/
00955 /** @defgroup RTC_Private_Functions RTC Private Functions
00956   * @{
00957   */
00958 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
00959 HAL_StatusTypeDef  RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
00960 uint8_t            RTC_ByteToBcd2(uint8_t Value);
00961 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
00962 /**
00963   * @}
00964   */
00965
00966
00967 /**
00968   * @}
00969   */
00970
00971 /**
00972   * @}
00973   */
00974
00975 #ifdef __cplusplus
00976 }
00977 #endif
00978
00979 #endif /* STM32G0xx_HAL_RTC_H */
00980
00981
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rtc_ex.c Source File

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stm32g0xx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real Time Clock (RTC) Extended peripheral:
00008   *           + RTC Time Stamp functions
00009   *           + RTC Tamper functions
00010   *           + RTC Wake-up functions
00011   *           + Extended Control functions
00012   *           + Extended RTC features functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2018 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026   ==============================================================================
00027                   ##### How to use this driver #####
00028   ==============================================================================
00029   [..]
00030     (+) Enable the RTC domain access.
00031     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00032         format using the HAL_RTC_Init() function.
00033
00034   *** RTC Wakeup configuration ***
00035   ================================
00036   [..]
00037     (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
00038         function. You can also configure the RTC Wakeup timer with interrupt mode
00039         using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00040     (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
00041         function.
00042
00043   *** Outputs configuration ***
00044   =============================
00045   [..]  The RTC has 2 different outputs:
00046     (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
00047         and WaKeUp signals.
00048         To output the selected RTC signal, use the HAL_RTC_Init() function.
00049     (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
00050         To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
00051     (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
00052         the RTC_OR register.
00053     (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
00054         automatically configured in output alternate function.
00055
00056   *** Smooth digital Calibration configuration ***
00057   ================================================
00058   [..]
00059     (+) Configure the RTC Original Digital Calibration Value and the corresponding
00060         calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
00061         function.
00062
00063   *** TimeStamp configuration ***
00064   ===============================
00065   [..]
00066     (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
00067         You can also configure the RTC TimeStamp with interrupt mode using the
00068         HAL_RTCEx_SetTimeStamp_IT() function.
00069     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00070         function.
00071
00072   *** Internal TimeStamp configuration ***
00073   ===============================
00074   [..]
00075     (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
00076         User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
00077     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00078         function.
00079
00080    *** Tamper configuration ***
00081    ============================
00082    [..]
00083      (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
00084          or Level according to the Tamper filter (if equal to 0 Edge else Level)
00085          value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
00086          Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
00087          with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
00088      (+) The default configuration of the Tamper erases the backup registers. To avoid
00089          erase, enable the NoErase field on the RTC_TAMPCR register.
00090      (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to
00091          perform TAMP base address offset calculation.
00092      (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization
00093          by setting ClockEnable inti field to RTC_CLOCK_DISABLE.
00094      (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using
00095          setting Interrupt field.
00096
00097    *** Backup Data Registers configuration ***
00098    ===========================================
00099    [..]
00100      (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
00101          function.
00102      (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
00103          function.
00104      (+) Before calling those functions you have to call HAL_RTC_Init() in order to
00105          perform TAMP base address offset calculation.
00106
00107    @endverbatim
00108   ******************************************************************************
00109   */
00110
00111 /* Includes ------------------------------------------------------------------*/
00112 #include "stm32g0xx_hal.h"
00113
00114 /** @addtogroup STM32G0xx_HAL_Driver
00115   * @{
00116   */
00117
00118 /** @addtogroup RTCEx
00119   * @brief RTC Extended HAL module driver
00120   * @{
00121   */
00122
00123 #ifdef HAL_RTC_MODULE_ENABLED
00124
00125 /* Private typedef -----------------------------------------------------------*/
00126 /* Private define ------------------------------------------------------------*/
00127 /* Private macro -------------------------------------------------------------*/
00128 /* Private variables ---------------------------------------------------------*/
00129 /* Private function prototypes -----------------------------------------------*/
00130 /* Exported functions --------------------------------------------------------*/
00131
00132 /** @addtogroup RTCEx_Exported_Functions
00133   * @{
00134   */
00135
00136
00137 /** @addtogroup RTCEx_Exported_Functions_Group1
00138  *  @brief   RTC TimeStamp and Tamper functions
00139   *
00140 @verbatim
00141  ===============================================================================
00142                  ##### RTC TimeStamp and Tamper functions #####
00143  ===============================================================================
00144
00145  [..] This section provides functions allowing to configure TimeStamp feature
00146
00147 @endverbatim
00148   * @{
00149   */
00150
00151 /**
00152   * @brief  Set TimeStamp.
00153   * @note   This API must be called before enabling the TimeStamp feature.
00154   * @param  hrtc RTC handle
00155   * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
00156   *         activated.
00157   *          This parameter can be one of the following values:
00158   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00159   *                                        rising edge of the related pin.
00160   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00161   *                                         falling edge of the related pin.
00162   * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.
00163   *          This parameter can be one of the following values:
00164   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00165   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00166   *               compatibility, this parameter is required.
00167   * @retval HAL status
00168   */
00169 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00170 {
00171   uint32_t tmpreg;
00172
00173   /* Check the parameters */
00174   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00175   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00176
00177   /* Prevent unused argument(s) compilation warning if no assert_param check */
00178   UNUSED(RTC_TimeStampPin);
00179
00180   /* Process Locked */
00181   __HAL_LOCK(hrtc);
00182
00183   hrtc->State = HAL_RTC_STATE_BUSY;
00184
00185   /* Get the RTC_CR register and clear the bits to be configured */
00186   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00187
00188   tmpreg|= TimeStampEdge;
00189
00190   /* Disable the write protection for RTC registers */
00191   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00192
00193   /* Configure the Time Stamp TSEDGE and Enable bits */
00194   hrtc->Instance->CR = (uint32_t)tmpreg;
00195
00196   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00197
00198   /* Enable the write protection for RTC registers */
00199   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00200
00201   /* Change RTC state */
00202   hrtc->State = HAL_RTC_STATE_READY;
00203
00204   /* Process Unlocked */
00205   __HAL_UNLOCK(hrtc);
00206
00207   return HAL_OK;
00208 }
00209
00210 /**
00211   * @brief  Set TimeStamp with Interrupt.
00212   * @note   This API must be called before enabling the TimeStamp feature.
00213   * @param  hrtc RTC handle
00214   * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
00215   *         activated.
00216   *          This parameter can be one of the following values:
00217   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00218   *                                        rising edge of the related pin.
00219   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00220   *                                         falling edge of the related pin.
00221   * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
00222   *          This parameter can be one of the following values:
00223   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00224   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00225   *               compatibility, this parameter is required.
00226   * @retval HAL status
00227   */
00228 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00229 {
00230   uint32_t tmpreg;
00231
00232   /* Check the parameters */
00233   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00234   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00235
00236   /* Prevent unused argument(s) compilation warning if no assert_param check */
00237   UNUSED(RTC_TimeStampPin);
00238
00239   /* Process Locked */
00240   __HAL_LOCK(hrtc);
00241
00242   hrtc->State = HAL_RTC_STATE_BUSY;
00243
00244   /* Get the RTC_CR register and clear the bits to be configured */
00245   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00246
00247   tmpreg |= TimeStampEdge;
00248
00249   /* Disable the write protection for RTC registers */
00250   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00251
00252   /* Configure the Time Stamp TSEDGE and Enable bits */
00253   hrtc->Instance->CR = (uint32_t)tmpreg;
00254
00255   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00256
00257   /* Enable IT timestamp */
00258   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
00259
00260   /* Enable the write protection for RTC registers */
00261   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00262
00263   /* RTC timestamp Interrupt Configuration: EXTI configuration */
00264   __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
00265
00266   hrtc->State = HAL_RTC_STATE_READY;
00267
00268   /* Process Unlocked */
00269   __HAL_UNLOCK(hrtc);
00270
00271   return HAL_OK;
00272 }
00273
00274 /**
00275   * @brief  Deactivate TimeStamp.
00276   * @param  hrtc RTC handle
00277   * @retval HAL status
00278   */
00279 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00280 {
00281   uint32_t tmpreg;
00282
00283   /* Process Locked */
00284   __HAL_LOCK(hrtc);
00285
00286   hrtc->State = HAL_RTC_STATE_BUSY;
00287
00288   /* Disable the write protection for RTC registers */
00289   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00290
00291   /* In case of interrupt mode is used, the interrupt source must disabled */
00292   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
00293
00294   /* Get the RTC_CR register and clear the bits to be configured */
00295   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00296
00297   /* Configure the Time Stamp TSEDGE and Enable bits */
00298   hrtc->Instance->CR = (uint32_t)tmpreg;
00299
00300   /* Enable the write protection for RTC registers */
00301   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00302
00303   hrtc->State = HAL_RTC_STATE_READY;
00304
00305   /* Process Unlocked */
00306   __HAL_UNLOCK(hrtc);
00307
00308   return HAL_OK;
00309 }
00310
00311 /**
00312   * @brief  Set Internal TimeStamp.
00313   * @note   This API must be called before enabling the internal TimeStamp feature.
00314   * @param  hrtc RTC handle
00315   * @retval HAL status
00316   */
00317 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00318 {
00319   /* Process Locked */
00320   __HAL_LOCK(hrtc);
00321
00322   hrtc->State = HAL_RTC_STATE_BUSY;
00323
00324   /* Disable the write protection for RTC registers */
00325   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00326
00327   /* Configure the internal Time Stamp Enable bits */
00328   __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
00329
00330   /* Enable the write protection for RTC registers */
00331   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00332
00333   /* Change RTC state */
00334   hrtc->State = HAL_RTC_STATE_READY;
00335
00336   /* Process Unlocked */
00337   __HAL_UNLOCK(hrtc);
00338
00339   return HAL_OK;
00340 }
00341
00342 /**
00343   * @brief  Deactivate Internal TimeStamp.
00344   * @param  hrtc RTC handle
00345   * @retval HAL status
00346   */
00347 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00348 {
00349   /* Process Locked */
00350   __HAL_LOCK(hrtc);
00351
00352   hrtc->State = HAL_RTC_STATE_BUSY;
00353
00354   /* Disable the write protection for RTC registers */
00355   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00356
00357   /* Configure the internal Time Stamp Enable bits */
00358   __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
00359
00360   /* Enable the write protection for RTC registers */
00361   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00362
00363   hrtc->State = HAL_RTC_STATE_READY;
00364
00365   /* Process Unlocked */
00366   __HAL_UNLOCK(hrtc);
00367
00368   return HAL_OK;
00369 }
00370
00371 /**
00372   * @brief  Get the RTC TimeStamp value.
00373   * @param  hrtc RTC handle
00374   * @param  sTimeStamp Pointer to Time structure
00375   * @param  sTimeStampDate Pointer to Date structure
00376   * @param  Format specifies the format of the entered parameters.
00377   *          This parameter can be one of the following values:
00378   *             @arg RTC_FORMAT_BIN: Binary data format
00379   *             @arg RTC_FORMAT_BCD: BCD data format
00380   * @retval HAL status
00381   */
00382 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
00383 {
00384   uint32_t tmptime, tmpdate;
00385
00386   /* Check the parameters */
00387   assert_param(IS_RTC_FORMAT(Format));
00388
00389   /* Get the TimeStamp time and date registers values */
00390   tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
00391   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
00392
00393   /* Fill the Time structure fields with the read parameters */
00394   sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TSTR_HU_Pos);
00395   sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >>RTC_TSTR_MNU_Pos);
00396   sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TSTR_SU_Pos);
00397   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> RTC_TSTR_PM_Pos);
00398   sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
00399
00400   /* Fill the Date structure fields with the read parameters */
00401   sTimeStampDate->Year = 0U;
00402   sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> RTC_TSDR_MU_Pos);
00403   sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
00404   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> RTC_TSDR_WDU_Pos);
00405
00406   /* Check the input parameters format */
00407   if(Format == RTC_FORMAT_BIN)
00408   {
00409     /* Convert the TimeStamp structure parameters to Binary format */
00410     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00411     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00412     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00413
00414     /* Convert the DateTimeStamp structure parameters to Binary format */
00415     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00416     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00417     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00418   }
00419
00420   /* Clear the TIMESTAMP Flags */
00421   __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
00422   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00423
00424   return HAL_OK;
00425 }
00426
00427 /**
00428   * @brief  TimeStamp callback.
00429   * @param  hrtc RTC handle
00430   * @retval None
00431   */
00432 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
00433 {
00434   /* Prevent unused argument(s) compilation warning */
00435   UNUSED(hrtc);
00436
00437   /* NOTE : This function should not be modified, when the callback is needed,
00438             the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
00439   */
00440 }
00441
00442
00443 /**
00444   * @brief  Handle TimeStamp interrupt request.
00445   * @param  hrtc RTC handle
00446   * @retval None
00447   */
00448 void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
00449 {
00450   /* Get the TimeStamp interrupt source enable status */
00451   if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U)
00452   {
00453 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00454     /* Call TimeStampEvent registered Callback */
00455     hrtc->TimeStampEventCallback(hrtc);
00456 #else
00457     /* TIMESTAMP callback */
00458     HAL_RTCEx_TimeStampEventCallback(hrtc);
00459 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00460
00461     /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/
00462     WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF);
00463   }
00464
00465   /* Change RTC state */
00466   hrtc->State = HAL_RTC_STATE_READY;
00467 }
00468
00469
00470 /**
00471   * @brief  Handle TimeStamp polling request.
00472   * @param  hrtc RTC handle
00473   * @param  Timeout Timeout duration
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00477 {
00478   uint32_t tickstart = HAL_GetTick();
00479
00480   while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U)
00481   {
00482     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U)
00483     {
00484       /* Clear the TIMESTAMP OverRun Flag */
00485       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00486
00487       /* Change TIMESTAMP state */
00488       hrtc->State = HAL_RTC_STATE_ERROR;
00489
00490       return HAL_ERROR;
00491     }
00492
00493     if(Timeout != HAL_MAX_DELAY)
00494     {
00495       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
00496       {
00497         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00498         return HAL_TIMEOUT;
00499       }
00500     }
00501   }
00502
00503   /* Change RTC state */
00504   hrtc->State = HAL_RTC_STATE_READY;
00505
00506   return HAL_OK;
00507 }
00508
00509 /**
00510   * @}
00511   */
00512
00513 /** @addtogroup RTCEx_Exported_Functions_Group2
00514   * @brief    RTC Wake-up functions
00515   *
00516 @verbatim
00517  ===============================================================================
00518                         ##### RTC Wake-up functions #####
00519  ===============================================================================
00520
00521  [..] This section provides functions allowing to configure Wake-up feature
00522
00523 @endverbatim
00524   * @{
00525   */
00526
00527 /**
00528   * @brief  Set wake up timer.
00529   * @param  hrtc RTC handle
00530   * @param  WakeUpCounter Wake up counter
00531   * @param  WakeUpClock Wake up clock
00532   * @retval HAL status
00533   */
00534 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00535 {
00536   uint32_t tickstart;
00537
00538   /* Check the parameters */
00539   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00540   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00541
00542   /* Process Locked */
00543   __HAL_LOCK(hrtc);
00544
00545   hrtc->State = HAL_RTC_STATE_BUSY;
00546
00547   /* Disable the write protection for RTC registers */
00548   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00549
00550   /* Clear WUTE in RTC_CR to disable the wakeup timer */
00551   CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
00552
00553   /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
00554      counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
00555      calendar initialization mode. */
00556   if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
00557   {
00558     tickstart = HAL_GetTick();
00559     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
00560     {
00561       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00562       {
00563         /* Enable the write protection for RTC registers */
00564         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00565
00566         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00567
00568         /* Process Unlocked */
00569         __HAL_UNLOCK(hrtc);
00570
00571         return HAL_TIMEOUT;
00572       }
00573     }
00574   }
00575
00576   /* Clear the Wakeup Timer clock source bits in CR register */
00577   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
00578
00579   /* Configure the clock source */
00580   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
00581
00582   /* Configure the Wakeup Timer counter */
00583   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
00584
00585    /* Enable the Wakeup Timer */
00586   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
00587
00588   /* Enable the write protection for RTC registers */
00589   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00590
00591   hrtc->State = HAL_RTC_STATE_READY;
00592
00593   /* Process Unlocked */
00594   __HAL_UNLOCK(hrtc);
00595
00596   return HAL_OK;
00597 }
00598
00599 /**
00600   * @brief  Set wake up timer with interrupt.
00601   * @param  hrtc RTC handle
00602   * @param  WakeUpCounter Wake up counter
00603   * @param  WakeUpClock Wake up clock
00604   * @retval HAL status
00605   */
00606 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00607 {
00608   uint32_t tickstart;
00609
00610   /* Check the parameters */
00611   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00612   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00613
00614   /* Process Locked */
00615   __HAL_LOCK(hrtc);
00616
00617   hrtc->State = HAL_RTC_STATE_BUSY;
00618
00619   /* Disable the write protection for RTC registers */
00620   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00621
00622   /* Disable the Wake-Up timer */
00623   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00624
00625   /* Clear flag Wake-Up */
00626   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
00627
00628   /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
00629      counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
00630      calendar initialization mode. */
00631   if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
00632   {
00633     tickstart = HAL_GetTick();
00634     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
00635     {
00636       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00637       {
00638         /* Enable the write protection for RTC registers */
00639         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00640
00641         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00642
00643         /* Process Unlocked */
00644         __HAL_UNLOCK(hrtc);
00645
00646         return HAL_TIMEOUT;
00647       }
00648     }
00649   }
00650
00651   /* Configure the Wakeup Timer counter */
00652   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
00653
00654   /* Clear the Wakeup Timer clock source bits in CR register */
00655   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
00656
00657   /* Configure the clock source */
00658   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
00659
00660   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
00661   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
00662
00663   /* Configure the Interrupt in the RTC_CR register */
00664   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
00665
00666   /* Enable the Wakeup Timer */
00667   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
00668
00669   /* Enable the write protection for RTC registers */
00670   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00671
00672   hrtc->State = HAL_RTC_STATE_READY;
00673
00674   /* Process Unlocked */
00675   __HAL_UNLOCK(hrtc);
00676
00677   return HAL_OK;
00678 }
00679
00680 /**
00681   * @brief  Deactivate wake up timer counter.
00682   * @param  hrtc RTC handle
00683   * @retval HAL status
00684   */
00685 HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
00686 {
00687   uint32_t tickstart;
00688
00689   /* Process Locked */
00690   __HAL_LOCK(hrtc);
00691
00692   hrtc->State = HAL_RTC_STATE_BUSY;
00693
00694   /* Disable the write protection for RTC registers */
00695   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00696
00697   /* Disable the Wakeup Timer */
00698   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00699
00700   /* In case of interrupt mode is used, the interrupt source must disabled */
00701   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
00702
00703   tickstart = HAL_GetTick();
00704   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00705   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
00706   {
00707     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00708     {
00709       /* Enable the write protection for RTC registers */
00710       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00711
00712       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00713
00714       /* Process Unlocked */
00715       __HAL_UNLOCK(hrtc);
00716
00717       return HAL_TIMEOUT;
00718     }
00719   }
00720
00721   /* Enable the write protection for RTC registers */
00722   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00723
00724   hrtc->State = HAL_RTC_STATE_READY;
00725
00726   /* Process Unlocked */
00727   __HAL_UNLOCK(hrtc);
00728
00729   return HAL_OK;
00730 }
00731
00732 /**
00733   * @brief  Get wake up timer counter.
00734   * @param  hrtc RTC handle
00735   * @retval Counter value
00736   */
00737 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
00738 {
00739   /* Get the counter value */
00740   return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
00741 }
00742
00743 /**
00744   * @brief  Handle Wake Up Timer interrupt request.
00745   * @param  hrtc RTC handle
00746   * @retval None
00747   */
00748 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
00749 {
00750     /* Get the pending status of the WAKEUPTIMER Interrupt */
00751     if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
00752     {
00753       /* Clear the WAKEUPTIMER interrupt pending bit */
00754       __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
00755
00756 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00757       /* Call WakeUpTimerEvent registered Callback */
00758       hrtc->WakeUpTimerEventCallback(hrtc);
00759 #else
00760       /* WAKEUPTIMER callback */
00761       HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
00762 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00763     }
00764
00765   /* Change RTC state */
00766   hrtc->State = HAL_RTC_STATE_READY;
00767 }
00768
00769 /**
00770   * @brief  Wake Up Timer callback.
00771   * @param  hrtc RTC handle
00772   * @retval None
00773   */
00774 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
00775 {
00776   /* Prevent unused argument(s) compilation warning */
00777   UNUSED(hrtc);
00778
00779   /* NOTE : This function should not be modified, when the callback is needed,
00780             the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
00781    */
00782 }
00783
00784
00785 /**
00786   * @brief  Handle Wake Up Timer Polling.
00787   * @param  hrtc RTC handle
00788   * @param  Timeout Timeout duration
00789   * @retval HAL status
00790   */
00791 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00792 {
00793   uint32_t tickstart = HAL_GetTick();
00794
00795   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U)
00796   {
00797     if(Timeout != HAL_MAX_DELAY)
00798     {
00799       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
00800       {
00801         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00802         return HAL_TIMEOUT;
00803       }
00804     }
00805   }
00806
00807   /* Clear the WAKEUPTIMER Flag */
00808   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
00809
00810   /* Change RTC state */
00811   hrtc->State = HAL_RTC_STATE_READY;
00812
00813   return HAL_OK;
00814 }
00815
00816 /**
00817   * @}
00818   */
00819
00820
00821 /** @addtogroup RTCEx_Exported_Functions_Group3
00822   * @brief    Extended Peripheral Control functions
00823   *
00824 @verbatim
00825  ===============================================================================
00826               ##### Extended Peripheral Control functions #####
00827  ===============================================================================
00828     [..]
00829     This subsection provides functions allowing to
00830       (+) Write a data in a specified RTC Backup data register
00831       (+) Read a data in a specified RTC Backup data register
00832       (+) Set the Coarse calibration parameters.
00833       (+) Deactivate the Coarse calibration parameters
00834       (+) Set the Smooth calibration parameters.
00835       (+) Configure the Synchronization Shift Control Settings.
00836       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
00837       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
00838       (+) Enable the RTC reference clock detection.
00839       (+) Disable the RTC reference clock detection.
00840       (+) Enable the Bypass Shadow feature.
00841       (+) Disable the Bypass Shadow feature.
00842
00843 @endverbatim
00844   * @{
00845   */
00846
00847
00848
00849 /**
00850   * @brief  Set the Smooth calibration parameters.
00851   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
00852   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
00853   *         SmoothCalibMinusPulsesValue must be equal to 0.
00854   * @param  hrtc RTC handle
00855   * @param  SmoothCalibPeriod Select the Smooth Calibration Period.
00856   *          This parameter can be can be one of the following values :
00857   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
00858   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
00859   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
00860   * @param  SmoothCalibPlusPulses Select to Set or reset the CALP bit.
00861   *          This parameter can be one of the following values:
00862   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
00863   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
00864   * @param  SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
00865   *          This parameter can be one any value from 0 to 0x000001FF.
00866   * @retval HAL status
00867   */
00868 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
00869 {
00870   uint32_t tickstart;
00871
00872   /* Check the parameters */
00873   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
00874   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
00875   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
00876
00877   /* Process Locked */
00878   __HAL_LOCK(hrtc);
00879
00880   hrtc->State = HAL_RTC_STATE_BUSY;
00881
00882   /* Disable the write protection for RTC registers */
00883   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00884
00885   /* check if a calibration is pending*/
00886   if((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
00887   {
00888     tickstart = HAL_GetTick();
00889
00890     /* check if a calibration is pending*/
00891     while((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
00892     {
00893       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00894       {
00895         /* Enable the write protection for RTC registers */
00896         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00897
00898         /* Change RTC state */
00899         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00900
00901         /* Process Unlocked */
00902         __HAL_UNLOCK(hrtc);
00903
00904         return HAL_TIMEOUT;
00905       }
00906     }
00907   }
00908
00909   /* Configure the Smooth calibration settings */
00910   hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
00911
00912   /* Enable the write protection for RTC registers */
00913   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00914
00915   /* Change RTC state */
00916   hrtc->State = HAL_RTC_STATE_READY;
00917
00918   /* Process Unlocked */
00919   __HAL_UNLOCK(hrtc);
00920
00921   return HAL_OK;
00922 }
00923
00924 /**
00925   * @brief  Configure the Synchronization Shift Control Settings.
00926   * @note   When REFCKON is set, firmware must not write to Shift control register.
00927   * @param  hrtc RTC handle
00928   * @param  ShiftAdd1S Select to add or not 1 second to the time calendar.
00929   *          This parameter can be one of the following values:
00930   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
00931   *             @arg RTC_SHIFTADD1S_RESET: No effect.
00932   * @param  ShiftSubFS Select the number of Second Fractions to substitute.
00933   *          This parameter can be one any value from 0 to 0x7FFF.
00934   * @retval HAL status
00935   */
00936 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
00937 {
00938   uint32_t tickstart;
00939
00940   /* Check the parameters */
00941   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
00942   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
00943
00944   /* Process Locked */
00945   __HAL_LOCK(hrtc);
00946
00947   hrtc->State = HAL_RTC_STATE_BUSY;
00948
00949   /* Disable the write protection for RTC registers */
00950   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00951
00952     tickstart = HAL_GetTick();
00953
00954     /* Wait until the shift is completed*/
00955     while((hrtc->Instance->ICSR & RTC_ICSR_SHPF) != 0U)
00956     {
00957       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00958       {
00959         /* Enable the write protection for RTC registers */
00960         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00961
00962         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00963
00964         /* Process Unlocked */
00965         __HAL_UNLOCK(hrtc);
00966
00967         return HAL_TIMEOUT;
00968       }
00969     }
00970
00971     /* Check if the reference clock detection is disabled */
00972     if((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U)
00973     {
00974       /* Configure the Shift settings */
00975       hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
00976
00977       /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00978       if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
00979       {
00980         if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00981         {
00982           /* Enable the write protection for RTC registers */
00983           __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00984
00985           hrtc->State = HAL_RTC_STATE_ERROR;
00986
00987           /* Process Unlocked */
00988           __HAL_UNLOCK(hrtc);
00989
00990           return HAL_ERROR;
00991         }
00992       }
00993     }
00994     else
00995     {
00996       /* Enable the write protection for RTC registers */
00997       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00998
00999       /* Change RTC state */
01000       hrtc->State = HAL_RTC_STATE_ERROR;
01001
01002       /* Process Unlocked */
01003       __HAL_UNLOCK(hrtc);
01004
01005       return HAL_ERROR;
01006     }
01007
01008   /* Enable the write protection for RTC registers */
01009   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01010
01011   /* Change RTC state */
01012   hrtc->State = HAL_RTC_STATE_READY;
01013
01014   /* Process Unlocked */
01015   __HAL_UNLOCK(hrtc);
01016
01017   return HAL_OK;
01018 }
01019
01020 /**
01021   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01022   * @param  hrtc RTC handle
01023   * @param  CalibOutput Select the Calibration output Selection .
01024   *          This parameter can be one of the following values:
01025   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
01026   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
01027   * @retval HAL status
01028   */
01029 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
01030 {
01031   /* Check the parameters */
01032   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
01033
01034   /* Process Locked */
01035   __HAL_LOCK(hrtc);
01036
01037   hrtc->State = HAL_RTC_STATE_BUSY;
01038
01039   /* Disable the write protection for RTC registers */
01040   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01041
01042   /* Clear flags before config */
01043   hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
01044
01045   /* Configure the RTC_CR register */
01046   hrtc->Instance->CR |= (uint32_t)CalibOutput;
01047
01048   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
01049
01050   /* Enable the write protection for RTC registers */
01051   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01052
01053   /* Change RTC state */
01054   hrtc->State = HAL_RTC_STATE_READY;
01055
01056   /* Process Unlocked */
01057   __HAL_UNLOCK(hrtc);
01058
01059   return HAL_OK;
01060 }
01061
01062 /**
01063   * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01064   * @param  hrtc RTC handle
01065   * @retval HAL status
01066   */
01067 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
01068 {
01069   /* Process Locked */
01070   __HAL_LOCK(hrtc);
01071
01072   hrtc->State = HAL_RTC_STATE_BUSY;
01073
01074   /* Disable the write protection for RTC registers */
01075   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01076
01077   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
01078
01079   /* Enable the write protection for RTC registers */
01080   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01081
01082   /* Change RTC state */
01083   hrtc->State = HAL_RTC_STATE_READY;
01084
01085   /* Process Unlocked */
01086   __HAL_UNLOCK(hrtc);
01087
01088   return HAL_OK;
01089 }
01090
01091 /**
01092   * @brief  Enable the RTC reference clock detection.
01093   * @param  hrtc RTC handle
01094   * @retval HAL status
01095   */
01096 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
01097 {
01098   HAL_StatusTypeDef status;
01099
01100   /* Process Locked */
01101   __HAL_LOCK(hrtc);
01102
01103   hrtc->State = HAL_RTC_STATE_BUSY;
01104
01105   /* Disable the write protection for RTC registers */
01106   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01107
01108   /* Enter Initialization mode */
01109   status = RTC_EnterInitMode(hrtc);
01110   if(status == HAL_OK)
01111   {
01112     /* Enable clockref detection */
01113     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
01114
01115     /* Exit Initialization mode */
01116     status = RTC_ExitInitMode(hrtc);
01117   }
01118
01119   /* Enable the write protection for RTC registers */
01120   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01121
01122   if (status == HAL_OK)
01123   {
01124   hrtc->State = HAL_RTC_STATE_READY;
01125   }
01126
01127   /* Process Unlocked */
01128   __HAL_UNLOCK(hrtc);
01129
01130   return status;
01131 }
01132
01133 /**
01134   * @brief  Disable the RTC reference clock detection.
01135   * @param  hrtc RTC handle
01136   * @retval HAL status
01137   */
01138 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
01139 {
01140   HAL_StatusTypeDef status;
01141
01142   /* Process Locked */
01143   __HAL_LOCK(hrtc);
01144
01145   hrtc->State = HAL_RTC_STATE_BUSY;
01146
01147   /* Disable the write protection for RTC registers */
01148   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01149
01150   /* Enter Initialization mode */
01151   status = RTC_EnterInitMode(hrtc);
01152   if (status == HAL_OK)
01153   {
01154     /* Disable clockref detection */
01155     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
01156
01157     /* Exit Initialization mode */
01158     status = RTC_ExitInitMode(hrtc);
01159   }
01160
01161   /* Enable the write protection for RTC registers */
01162   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01163
01164   if (status == HAL_OK)
01165   {
01166   hrtc->State = HAL_RTC_STATE_READY;
01167   }
01168
01169   /* Process Unlocked */
01170   __HAL_UNLOCK(hrtc);
01171
01172   return status;
01173 }
01174
01175 /**
01176   * @brief  Enable the Bypass Shadow feature.
01177   * @note   When the Bypass Shadow is enabled the calendar value are taken
01178   *         directly from the Calendar counter.
01179   * @param  hrtc RTC handle
01180   * @retval HAL status
01181   */
01182 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
01183 {
01184   /* Process Locked */
01185   __HAL_LOCK(hrtc);
01186
01187   hrtc->State = HAL_RTC_STATE_BUSY;
01188
01189   /* Disable the write protection for RTC registers */
01190   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01191
01192   /* Set the BYPSHAD bit */
01193   hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
01194
01195   /* Enable the write protection for RTC registers */
01196   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01197
01198   /* Change RTC state */
01199   hrtc->State = HAL_RTC_STATE_READY;
01200
01201   /* Process Unlocked */
01202   __HAL_UNLOCK(hrtc);
01203
01204   return HAL_OK;
01205 }
01206
01207 /**
01208   * @brief  Disable the Bypass Shadow feature.
01209   * @note   When the Bypass Shadow is enabled the calendar value are taken
01210   *         directly from the Calendar counter.
01211   * @param  hrtc RTC handle
01212   * @retval HAL status
01213   */
01214 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
01215 {
01216   /* Process Locked */
01217   __HAL_LOCK(hrtc);
01218
01219   hrtc->State = HAL_RTC_STATE_BUSY;
01220
01221   /* Disable the write protection for RTC registers */
01222   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01223
01224   /* Reset the BYPSHAD bit */
01225   hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
01226
01227   /* Enable the write protection for RTC registers */
01228   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01229
01230   /* Change RTC state */
01231   hrtc->State = HAL_RTC_STATE_READY;
01232
01233   /* Process Unlocked */
01234   __HAL_UNLOCK(hrtc);
01235
01236   return HAL_OK;
01237 }
01238
01239 /**
01240   * @}
01241   */
01242
01243 /** @addtogroup RTCEx_Exported_Functions_Group4
01244   * @brief    Extended features functions
01245   *
01246 @verbatim
01247  ===============================================================================
01248                  ##### Extended features functions #####
01249  ===============================================================================
01250     [..]  This section provides functions allowing to:
01251       (+) RTC Alarm B callback
01252       (+) RTC Poll for Alarm B request
01253
01254 @endverbatim
01255   * @{
01256   */
01257
01258 /**
01259   * @brief  Alarm B callback.
01260   * @param  hrtc RTC handle
01261   * @retval None
01262   */
01263 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
01264 {
01265   /* Prevent unused argument(s) compilation warning */
01266   UNUSED(hrtc);
01267
01268   /* NOTE : This function should not be modified, when the callback is needed,
01269             the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
01270    */
01271 }
01272
01273 /**
01274   * @brief  Handle Alarm B Polling request.
01275   * @param  hrtc RTC handle
01276   * @param  Timeout Timeout duration
01277   * @retval HAL status
01278   */
01279 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01280 {
01281   uint32_t tickstart = HAL_GetTick();
01282
01283   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U)
01284   {
01285     if(Timeout != HAL_MAX_DELAY)
01286     {
01287       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01288       {
01289         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01290         return HAL_TIMEOUT;
01291       }
01292     }
01293   }
01294
01295   /* Clear the Alarm Flag */
01296   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01297
01298   /* Change RTC state */
01299   hrtc->State = HAL_RTC_STATE_READY;
01300
01301   return HAL_OK;
01302 }
01303
01304 /**
01305   * @}
01306   */
01307
01308 /** @addtogroup RTCEx_Exported_Functions_Group5
01309   * @brief      Extended RTC Tamper functions
01310   *
01311 @verbatim
01312   ==============================================================================
01313                          ##### Tamper functions #####
01314   ==============================================================================
01315   [..]
01316    (+) Before calling any tamper or internal tamper function, you have to call first
01317        HAL_RTC_Init() function.
01318    (+) In that ine you can select to output tamper event on RTC pin.
01319   [..]
01320    (+) Enable the Tamper and configure the Tamper filter count, trigger Edge
01321        or Level according to the Tamper filter (if equal to 0 Edge else Level)
01322        value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
01323        Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function.
01324        You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
01325    (+) The default configuration of the Tamper erases the backup registers. To avoid
01326        erase, enable the NoErase field on the TAMP_TAMPCR register.
01327   [..]
01328    (+) Enable Internal Tamper and configure it with interrupt, timestamp using
01329        the HAL_RTCEx_SetInternalTamper() function.
01330
01331 @endverbatim
01332   * @{
01333   */
01334
01335
01336 /**
01337   * @brief  Set Tamper
01338   * @param  hrtc RTC handle
01339   * @param  sTamper Pointer to Tamper Structure.
01340   * @retval HAL status
01341   */
01342 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
01343 {
01344   uint32_t tmpreg;
01345   /* Process TAMP instance pointer */
01346   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01347
01348   /* Check the parameters */
01349   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
01350   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
01351   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
01352   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
01353   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
01354   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
01355   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
01356   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
01357   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
01358
01359   /* Configuration register 2 */
01360   tmpreg = tamp->CR2;
01361   tmpreg &= ~((sTamper->Tamper << 24) | (sTamper->Tamper << 16) | (sTamper->Tamper));
01362
01363   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
01364   {
01365     tmpreg |= (sTamper->Tamper << 24);
01366   }
01367
01368   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
01369   {
01370     tmpreg |= (sTamper->Tamper << 16);
01371   }
01372
01373   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
01374   {
01375     tmpreg |= sTamper->Tamper;
01376   }
01377   tamp->CR2 = tmpreg;
01378
01379   /* Filter control register */
01380   tamp->FLTCR = (sTamper->Filter) | (sTamper->SamplingFrequency) | \
01381                  (sTamper->PrechargeDuration) | (sTamper->TamperPullUp);
01382
01383   /* timestamp on tamper */
01384   if((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection))
01385   {
01386     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01387     tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS);
01388     hrtc->Instance->CR = (tmpreg | (sTamper->TimeStampOnTamperDetection));
01389     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01390   }
01391
01392   /* Control register 1 */
01393   tamp->CR1 |= (sTamper->Tamper);
01394
01395   return HAL_OK;
01396 }
01397
01398
01399 /**
01400   * @brief  Set Tamper in IT mode
01401   * @param  hrtc RTC handle
01402   * @param  sTamper Pointer to Tamper Structure.
01403   * @retval HAL status
01404   */
01405 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
01406 {
01407   uint32_t tmpreg;
01408   /* Process TAMP instance pointer */
01409   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01410
01411   /* Check the parameters */
01412   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
01413   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
01414   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
01415   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
01416   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
01417   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
01418   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
01419   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
01420   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
01421
01422   /* Configuration register 2 */
01423   tmpreg = tamp->CR2;
01424   tmpreg &= ~((sTamper->Tamper << 24) | (sTamper->Tamper << 16) | (sTamper->Tamper));
01425
01426   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
01427   {
01428     tmpreg |= (sTamper->Tamper << 24);
01429   }
01430
01431   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
01432   {
01433     tmpreg |= (sTamper->Tamper << 16);
01434   }
01435
01436   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
01437   {
01438     tmpreg |= sTamper->Tamper;
01439   }
01440   tamp->CR2 = tmpreg;
01441
01442   /* Filter control register */
01443   tamp->FLTCR = (sTamper->Filter) | (sTamper->SamplingFrequency) | \
01444                  (sTamper->PrechargeDuration) | (sTamper->TamperPullUp);
01445
01446   /* timestamp on tamper */
01447   if((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection))
01448   {
01449     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01450     tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS);
01451     hrtc->Instance->CR = (tmpreg | (sTamper->TimeStampOnTamperDetection));
01452     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01453   }
01454
01455   /* RTC Tamper Interrupt Configuration: EXTI configuration */
01456   __HAL_RTC_TAMPER_EXTI_ENABLE_IT();
01457
01458   /* Interrupt enable register */
01459   tamp->IER |= sTamper->Tamper;
01460
01461   /* Control register 1 */
01462   tamp->CR1 |= (sTamper->Tamper);
01463
01464   return HAL_OK;
01465 }
01466
01467
01468
01469 /**
01470   * @brief  Deactivate Tamper.
01471   * @param  hrtc RTC handle
01472   * @param  Tamper Selected tamper pin.
01473   *         This parameter can be a combination of the following values:
01474   *         @arg RTC_TAMPER_1
01475   *         @arg RTC_TAMPER_2
01476   * @retval HAL status
01477   */
01478 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
01479 {
01480   /* Process TAMP instance pointer */
01481   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01482
01483   assert_param(IS_RTC_TAMPER(Tamper));
01484
01485   /* Disable the selected Tamper pin */
01486   tamp->CR1 &= ~Tamper;
01487
01488   /* Clear tamper mask/noerase/trigger configuration */
01489   tamp->CR2 &= ~((Tamper << 24) | (Tamper << 16) | Tamper);
01490
01491   /* Clear tamper interrupt mode configuration */
01492   tamp->IER &= ~Tamper;
01493
01494   return HAL_OK;
01495 }
01496
01497
01498 /**
01499   * @brief  Tamper event polling.
01500   * @param  hrtc RTC handle
01501   * @param  Tamper Selected tamper pin.
01502   *         This parameter can be a combination of the following values:
01503   *         @arg RTC_TAMPER_1
01504   *         @arg RTC_TAMPER_2
01505   *         @arg RTC_TAMPER_3 (*)
01506   * @param  Timeout Timeout duration
01507   * @retval HAL status
01508   */
01509 HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
01510 {
01511   /* Process TAMP instance pointer */
01512   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01513
01514   assert_param(IS_RTC_TAMPER(Tamper));
01515
01516   uint32_t tickstart = HAL_GetTick();
01517
01518   /* Get the status of the Interrupt */
01519   while((tamp->SR & Tamper) != Tamper)
01520   {
01521     if(Timeout != HAL_MAX_DELAY)
01522     {
01523       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01524       {
01525         return HAL_TIMEOUT;
01526       }
01527     }
01528   }
01529
01530   /* Clear the Tamper Flag */
01531   tamp->SCR = Tamper;
01532
01533   return HAL_OK;
01534 }
01535
01536
01537 /**
01538   * @brief  Set Internal Tamper in interrupt mode
01539   * @param  hrtc RTC handle
01540   * @param  sIntTamper Pointer to Internal Tamper Structure.
01541   * @retval HAL status
01542   */
01543 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef* sIntTamper)
01544 {
01545   /* Process TAMP instance pointer */
01546   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01547
01548   uint32_t tmpreg;
01549
01550   /* Check the parameters */
01551   assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
01552   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
01553
01554   /* timestamp on internal tamper */
01555   if((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sIntTamper->TimeStampOnTamperDetection))
01556   {
01557     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01558     tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS);
01559     hrtc->Instance->CR = (tmpreg | (sIntTamper->TimeStampOnTamperDetection));
01560     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01561   }
01562
01563   /* Control register 1 */
01564   tamp->CR1 |= (sIntTamper->IntTamper);
01565
01566   return HAL_OK;
01567 }
01568
01569
01570 /**
01571   * @brief  Set Internal Tamper
01572   * @param  hrtc RTC handle
01573   * @param  sIntTamper Pointer to Internal Tamper Structure.
01574   * @retval HAL status
01575   */
01576 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef* sIntTamper)
01577 {
01578   /* Process TAMP instance pointer */
01579   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01580
01581   uint32_t tmpreg;
01582
01583   /* Check the parameters */
01584   assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
01585   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
01586
01587   /* timestamp on internal tamper */
01588   if((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sIntTamper->TimeStampOnTamperDetection))
01589   {
01590     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01591     tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS);
01592     hrtc->Instance->CR = (tmpreg | (sIntTamper->TimeStampOnTamperDetection));
01593     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01594   }
01595
01596   /* RTC Tamper Interrupt Configuration: EXTI configuration */
01597   __HAL_RTC_TAMPER_EXTI_ENABLE_IT();
01598
01599   /* Interrupt enable register */
01600   tamp->IER |= sIntTamper->IntTamper;
01601
01602   /* Control register 1 */
01603   tamp->CR1 |= (sIntTamper->IntTamper);
01604
01605   return HAL_OK;
01606 }
01607
01608 /**
01609   * @brief  Deactivate Internal Tamper.
01610   * @param  hrtc RTC handle
01611   * @param  IntTamper Selected internal tamper event.
01612   *          This parameter can be any combination of existing internal tampers.
01613   * @retval HAL status
01614   */
01615 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
01616 {
01617   /* Process TAMP instance pointer */
01618   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01619
01620   assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
01621
01622   /* Disable the selected Tamper pin */
01623   tamp->CR1 &= ~IntTamper;
01624
01625   /* Clear internal tamper interrupt mode configuration */
01626   tamp->IER &= ~IntTamper;
01627
01628   return HAL_OK;
01629 }
01630
01631
01632 /**
01633   * @brief  Internal Tamper event polling.
01634   * @param  hrtc RTC handle
01635   * @param  IntTamper selected tamper.
01636   *          This parameter can be any combination of existing internal tampers.
01637   * @param  Timeout Timeout duration
01638   * @retval HAL status
01639   */
01640 HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout)
01641 {
01642   /* Process TAMP instance pointer */
01643   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01644
01645   assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
01646
01647   uint32_t tickstart = HAL_GetTick();
01648
01649   /* Get the status of the Interrupt */
01650   while((tamp->SR & IntTamper) != IntTamper)
01651   {
01652     if(Timeout != HAL_MAX_DELAY)
01653     {
01654       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01655       {
01656         return HAL_TIMEOUT;
01657       }
01658     }
01659   }
01660
01661   /* Clear the Tamper Flag */
01662   tamp->SCR = IntTamper;
01663
01664   return HAL_OK;
01665 }
01666
01667
01668 /**
01669   * @brief  Handle Tamper interrupt request.
01670   * @param  hrtc RTC handle
01671   * @retval None
01672   */
01673 void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
01674 {
01675   uint32_t tmp;
01676   /* Process TAMP instance pointer */
01677   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01678
01679   /* Get interrupt status */
01680   tmp = tamp->MISR;
01681
01682   /* Immediately clear flags */
01683   tamp->SCR = tmp;
01684
01685   /* Check Tamper1 status */
01686   if((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
01687   {
01688 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01689       /* Call Tamper 1 Event registered Callback */
01690       hrtc->Tamper1EventCallback(hrtc);
01691 #else
01692     /* Tamper1 callback */
01693     HAL_RTCEx_Tamper1EventCallback(hrtc);
01694 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01695   }
01696
01697   /* Check Tamper2 status */
01698   if((tmp & RTC_TAMPER_2) == RTC_TAMPER_2)
01699   {
01700 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01701       /* Call Tamper 2 Event registered Callback */
01702       hrtc->Tamper2EventCallback(hrtc);
01703 #else
01704     /* Tamper2 callback */
01705     HAL_RTCEx_Tamper2EventCallback(hrtc);
01706 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01707   }
01708
01709 #if defined(TAMP_CR1_TAMP3E)
01710   /* Check Tamper3 status */
01711   if((tmp & RTC_TAMPER_3) == RTC_TAMPER_3)
01712   {
01713 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01714       /* Call Tamper 3 Event registered Callback */
01715       hrtc->Tamper3EventCallback(hrtc);
01716 #else
01717     /* Tamper3 callback */
01718     HAL_RTCEx_Tamper3EventCallback(hrtc);
01719 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01720   }
01721 #endif /* TAMP_CR1_TAMP3E */
01722
01723   /* Check Internal Tamper3 status */
01724   if((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
01725   {
01726 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01727       /* Call Internal Tamper 3 Event registered Callback */
01728       hrtc->InternalTamper3EventCallback(hrtc);
01729 #else
01730     /* Internal Tamper3 callback */
01731     HAL_RTCEx_InternalTamper3EventCallback(hrtc);
01732 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01733   }
01734
01735   /* Check Internal Tamper4 status */
01736   if((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4)
01737   {
01738 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01739       /* Call Internal Tamper 4 Event registered Callback */
01740       hrtc->InternalTamper4EventCallback(hrtc);
01741 #else
01742     /* Internal Tamper4 callback */
01743     HAL_RTCEx_InternalTamper4EventCallback(hrtc);
01744 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01745   }
01746
01747   /* Check Internal Tamper5 status */
01748   if((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5)
01749   {
01750 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01751       /* Call Internal Tamper 5 Event registered Callback */
01752       hrtc->InternalTamper5EventCallback(hrtc);
01753 #else
01754     /* Internal Tamper5 callback */
01755     HAL_RTCEx_InternalTamper5EventCallback(hrtc);
01756 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01757   }
01758
01759   /* Check Internal Tamper6 status */
01760   if((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6)
01761   {
01762 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01763       /* Call Internal Tamper 6 Event registered Callback */
01764       hrtc->InternalTamper6EventCallback(hrtc);
01765 #else
01766     /* Internal Tamper6 callback */
01767     HAL_RTCEx_InternalTamper6EventCallback(hrtc);
01768 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01769   }
01770
01771 }
01772
01773
01774 /**
01775   * @brief  Tamper 1 callback.
01776   * @param  hrtc RTC handle
01777   * @retval None
01778   */
01779 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
01780 {
01781   /* Prevent unused argument(s) compilation warning */
01782   UNUSED(hrtc);
01783
01784   /* NOTE : This function should not be modified, when the callback is needed,
01785             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
01786    */
01787 }
01788
01789
01790 /**
01791   * @brief  Tamper 2 callback.
01792   * @param  hrtc RTC handle
01793   * @retval None
01794   */
01795 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
01796 {
01797   /* Prevent unused argument(s) compilation warning */
01798   UNUSED(hrtc);
01799
01800   /* NOTE : This function should not be modified, when the callback is needed,
01801             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
01802    */
01803 }
01804
01805 #if defined(TAMP_CR1_TAMP3E)
01806 /**
01807   * @brief  Tamper 3 callback.
01808   * @param  hrtc RTC handle
01809   * @retval None
01810   */
01811 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
01812 {
01813   /* Prevent unused argument(s) compilation warning */
01814   UNUSED(hrtc);
01815
01816   /* NOTE : This function should not be modified, when the callback is needed,
01817             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
01818    */
01819 }
01820 #endif /* TAMP_CR1_TAMP3E */
01821
01822 /**
01823   * @brief  Internal Tamper 3 callback.
01824   * @param  hrtc RTC handle
01825   * @retval None
01826   */
01827 __weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc)
01828 {
01829   /* Prevent unused argument(s) compilation warning */
01830   UNUSED(hrtc);
01831
01832   /* NOTE : This function should not be modified, when the callback is needed,
01833             the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file
01834    */
01835 }
01836
01837
01838 /**
01839   * @brief  Internal Tamper 4 callback.
01840   * @param  hrtc RTC handle
01841   * @retval None
01842   */
01843 __weak void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc)
01844 {
01845   /* Prevent unused argument(s) compilation warning */
01846   UNUSED(hrtc);
01847
01848   /* NOTE : This function should not be modified, when the callback is needed,
01849             the HAL_RTCEx_InternalTamper4EventCallback could be implemented in the user file
01850    */
01851 }
01852
01853
01854 /**
01855   * @brief  Internal Tamper 5 callback.
01856   * @param  hrtc RTC handle
01857   * @retval None
01858   */
01859 __weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc)
01860 {
01861   /* Prevent unused argument(s) compilation warning */
01862   UNUSED(hrtc);
01863
01864   /* NOTE : This function should not be modified, when the callback is needed,
01865             the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file
01866    */
01867 }
01868
01869
01870 /**
01871   * @brief  Internal Tamper 6 callback.
01872   * @param  hrtc RTC handle
01873   * @retval None
01874   */
01875 __weak void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc)
01876 {
01877   /* Prevent unused argument(s) compilation warning */
01878   UNUSED(hrtc);
01879
01880   /* NOTE : This function should not be modified, when the callback is needed,
01881             the HAL_RTCEx_InternalTamper6EventCallback could be implemented in the user file
01882    */
01883 }
01884
01885
01886
01887 /**
01888   * @}
01889   */
01890
01891
01892 /** @addtogroup RTCEx_Exported_Functions_Group6
01893   * @brief      Extended RTC Backup register functions
01894   *
01895 @verbatim
01896   ===============================================================================
01897              ##### Extended RTC Backup register functions #####
01898   ===============================================================================
01899   [..]
01900    (+) Before calling any tamper or internal tamper function, you have to call first
01901        HAL_RTC_Init() function.
01902    (+) In that ine you can select to output tamper event on RTC pin.
01903   [..]
01904    This subsection provides functions allowing to
01905    (+) Write a data in a specified RTC Backup data register
01906    (+) Read a data in a specified RTC Backup data register
01907 @endverbatim
01908   * @{
01909   */
01910
01911
01912 /**
01913   * @brief  Write a data in a specified RTC Backup data register.
01914   * @param  hrtc RTC handle
01915   * @param  BackupRegister: RTC Backup data Register number.
01916   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 4
01917   *          specify the register.
01918   * @param  Data Data to be written in the specified Backup data register.
01919   * @retval None
01920   */
01921 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
01922 {
01923   uint32_t tmp;
01924   /* Process TAMP instance pointer */
01925   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01926
01927   /* Check the parameters */
01928   assert_param(IS_RTC_BKP(BackupRegister));
01929
01930   tmp = (uint32_t)&(tamp->BKP0R);
01931   tmp += (BackupRegister * 4U);
01932
01933   /* Write the specified register */
01934   *(__IO uint32_t *)tmp = (uint32_t)Data;
01935 }
01936
01937
01938 /**
01939   * @brief  Reads data from the specified RTC Backup data Register.
01940   * @param  hrtc RTC handle
01941   * @param  BackupRegister  RTC Backup data Register number.
01942   *         This parameter can be: RTC_BKP_DRx where x can be from 0 to 4
01943   *         specify the register.
01944   * @retval Read value
01945   */
01946 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
01947 {
01948   uint32_t tmp ;
01949   /* Process TAMP instance pointer */
01950   TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset);
01951
01952   /* Check the parameters */
01953   assert_param(IS_RTC_BKP(BackupRegister));
01954
01955   tmp = (uint32_t)&(tamp->BKP0R);
01956   tmp += (BackupRegister * 4U);
01957
01958   /* Read the specified register */
01959   return (*(__IO uint32_t *)tmp);
01960 }
01961
01962
01963 /**
01964   * @}
01965   */
01966
01967 /**
01968   * @}
01969   */
01970
01971 #endif /* HAL_RTC_MODULE_ENABLED */
01972 /**
01973   * @}
01974   */
01975
01976
01977 /**
01978   * @}
01979   */
01980
01981
01982
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_rtc_ex.h Source File

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stm32g0xx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_RTC_EX_H
00021 #define STM32G0xx_HAL_RTC_EX_H
00022
00023 #ifdef __cplusplus
00024  extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @defgroup RTCEx RTCEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00040   * @{
00041   */
00042
00043 /** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition
00044   * @{
00045   */
00046 typedef struct
00047 {
00048   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00049                                              This parameter can be a value of @ref RTCEx_Tamper_Pins */
00050
00051   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00052                                              This parameter can be a value of @ref RTCEx_Tamper_Trigger */
00053
00054   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
00055                                              This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
00056
00057   uint32_t MaskFlag;                    /*!< Specifies the Tamper Flag masking.
00058                                              This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
00059
00060   uint32_t Filter;                      /*!< Specifies the TAMP Filter Tamper.
00061                                              This parameter can be a value of @ref RTCEx_Tamper_Filter */
00062
00063   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00064                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies */
00065
00066   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00067                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration */
00068
00069   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00070                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */
00071
00072   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00073                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00074 }RTC_TamperTypeDef;
00075 /**
00076   * @}
00077   */
00078
00079
00080 /** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
00081   * @{
00082   */
00083 typedef struct
00084 {
00085   uint32_t IntTamper;                   /*!< Specifies the Internal Tamper Pin.
00086                                              This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
00087
00088   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00089                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00090 } RTC_InternalTamperTypeDef;
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00101   * @{
00102   */
00103
00104 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
00105   * @{
00106   */
00107 #define RTC_TIMESTAMPEDGE_RISING        0x00000000u
00108 #define RTC_TIMESTAMPEDGE_FALLING       RTC_CR_TSEDGE
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
00114   * @{
00115   */
00116 #define RTC_TIMESTAMPPIN_DEFAULT              0x00000000u
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
00122   * @{
00123   */
00124 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000u
00125 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         RTC_CR_WUCKSEL_0
00126 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         RTC_CR_WUCKSEL_1
00127 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
00128 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      RTC_CR_WUCKSEL_2
00129 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
00135   * @{
00136   */
00137 #define RTC_SMOOTHCALIB_PERIOD_32SEC   0x00000000u              /*!< If RTCCLK = 32768 Hz, Smooth calibation
00138                                                                      period is 32s,  else 2exp20 RTCCLK pulses */
00139 #define RTC_SMOOTHCALIB_PERIOD_16SEC   RTC_CALR_CALW16          /*!< If RTCCLK = 32768 Hz, Smooth calibation
00140                                                                      period is 16s, else 2exp19 RTCCLK pulses */
00141 #define RTC_SMOOTHCALIB_PERIOD_8SEC    RTC_CALR_CALW8           /*!< If RTCCLK = 32768 Hz, Smooth calibation
00142                                                                      period is 8s, else 2exp18 RTCCLK pulses */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
00148   * @{
00149   */
00150 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    RTC_CALR_CALP            /*!< The number of RTCCLK pulses added
00151                                                                         during a X -second window = Y - CALM[8:0]
00152                                                                         with Y = 512, 256, 128 when X = 32, 16, 8 */
00153 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  0x00000000u              /*!< The number of RTCCLK pulses subbstited
00154                                                                         during a 32-second window = CALM[8:0] */
00155
00156 /**
00157   * @}
00158   */
00159  /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
00160   * @{
00161   */
00162 #define RTC_CALIBOUTPUT_512HZ            0x00000000u
00163 #define RTC_CALIBOUTPUT_1HZ              RTC_CR_COSEL
00164
00165 /**
00166   * @}
00167   */
00168
00169
00170 /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
00171   * @{
00172   */
00173 #define RTC_SHIFTADD1S_RESET      0x00000000u
00174 #define RTC_SHIFTADD1S_SET        RTC_SHIFTR_ADD1S
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup RTCEx_Tamper_Pins  RTCEx Tamper Pins Definition
00180   * @{
00181   */
00182 #define RTC_TAMPER_1                        TAMP_CR1_TAMP1E
00183 #define RTC_TAMPER_2                        TAMP_CR1_TAMP2E
00184 #if defined(TAMP_CR1_TAMP3E)
00185 #define RTC_TAMPER_3                        TAMP_CR1_TAMP3E
00186 #define RTC_TAMPER_ALL                      (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)
00187 #else
00188 #define RTC_TAMPER_ALL                      (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E)
00189 #endif /* TAMP_CR1_TAMP3E */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup RTCEx_Internal_Tamper_Pins  RTCEx Internal Tamper Pins Definition
00195   * @{
00196   */
00197 #define RTC_INT_TAMPER_3                    TAMP_CR1_ITAMP3E
00198 #define RTC_INT_TAMPER_4                    TAMP_CR1_ITAMP4E
00199 #define RTC_INT_TAMPER_5                    TAMP_CR1_ITAMP5E
00200 #define RTC_INT_TAMPER_6                    TAMP_CR1_ITAMP6E
00201 #define RTC_INT_TAMPER_ALL                  (TAMP_CR1_ITAMP3E | TAMP_CR1_ITAMP4E | \
00202                                              TAMP_CR1_ITAMP5E | TAMP_CR1_ITAMP6E)
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup RTCEx_Tamper_Trigger  RTCEx Tamper Trigger
00208   * @{
00209   */
00210 #define RTC_TAMPERTRIGGER_RISINGEDGE        0x00u
00211 #define RTC_TAMPERTRIGGER_FALLINGEDGE       0x01u
00212 #define RTC_TAMPERTRIGGER_LOWLEVEL          RTC_TAMPERTRIGGER_RISINGEDGE
00213 #define RTC_TAMPERTRIGGER_HIGHLEVEL         RTC_TAMPERTRIGGER_FALLINGEDGE
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup RTCEx_Tamper_MaskFlag  RTCEx Tamper MaskFlag
00219   * @{
00220   */
00221 #define RTC_TAMPERMASK_FLAG_DISABLE         0x00u
00222 #define RTC_TAMPERMASK_FLAG_ENABLE          0x01u
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup RTCEx_Tamper_EraseBackUp  RTCEx Tamper EraseBackUp
00228 * @{
00229 */
00230 #define RTC_TAMPER_ERASE_BACKUP_ENABLE      0x00u
00231 #define RTC_TAMPER_ERASE_BACKUP_DISABLE     0x01u
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup RTCEx_Tamper_Filter  RTCEx Tamper Filter
00237   * @{
00238   */
00239 #define RTC_TAMPERFILTER_DISABLE            0x00000000U             /*!< Tamper filter is disabled */
00240 #define RTC_TAMPERFILTER_2SAMPLE           TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2
00241                                                                          consecutive samples at the active level */
00242 #define RTC_TAMPERFILTER_4SAMPLE           TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4
00243                                                                          consecutive samples at the active level */
00244 #define RTC_TAMPERFILTER_8SAMPLE           TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8
00245                                                                          consecutive samples at the active level */
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup RTCEx_Tamper_Sampling_Frequencies  RTCEx Tamper Sampling Frequencies
00251   * @{
00252   */
00253 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000U                                     /*!< Each of the tamper inputs are sampled
00254                                                                                                       with a frequency =  RTCCLK / 32768 */
00255 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled
00256                                                                                                       with a frequency =  RTCCLK / 16384 */
00257 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled
00258                                                                                                       with a frequency =  RTCCLK / 8192  */
00259 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
00260                                                                                                       with a frequency =  RTCCLK / 4096  */
00261 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled
00262                                                                                                       with a frequency =  RTCCLK / 2048  */
00263 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
00264                                                                                                       with a frequency =  RTCCLK / 1024  */
00265 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
00266                                                                                                       with a frequency =  RTCCLK / 512   */
00267 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
00268                                                   TAMP_FLTCR_TAMPFREQ_2)                         /*!< Each of the tamper inputs are sampled
00269                                                                                                       with a frequency =  RTCCLK / 256   */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration  RTCEx Tamper Pin Precharge Duration
00275   * @{
00276   */
00277 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000U                                       /*!< Tamper pins are pre-charged before
00278                                                                                                         sampling during 1 RTCCLK cycle  */
00279 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0                             /*!< Tamper pins are pre-charged before
00280                                                                                                         sampling during 2 RTCCLK cycles */
00281 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1                             /*!< Tamper pins are pre-charged before
00282                                                                                                         sampling during 4 RTCCLK cycles */
00283 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK     (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)   /*!< Tamper pins are pre-charged before
00284                                                                                                         sampling during 8 RTCCLK cycles */
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup RTCEx_Tamper_Pull_UP  RTCEx Tamper Pull UP
00290   * @{
00291   */
00292 #define RTC_TAMPER_PULLUP_ENABLE           0x00000000u           /*!< Tamper pins are pre-charged before sampling */
00293 #define RTC_TAMPER_PULLUP_DISABLE          TAMP_FLTCR_TAMPPUDIS  /*!< Tamper pins pre-charge is disabled          */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions
00299   * @{
00300   */
00301 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000u    /*!< TimeStamp on Tamper Detection event is not saved */
00302 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_CR_TAMPTS  /*!< TimeStamp on Tamper Detection event saved        */
00303 /**
00304   * @}
00305   */
00306
00307
00308 /** @defgroup RTCEx_Internal_Tamper_Interrupt  RTCEx Internal Tamper Interrupt
00309   * @{
00310   */
00311 #define RTC_IT_TAMP1                       TAMP_IER_TAMP1IE     /*!< Tamper 1 Interrupt */
00312 #define RTC_IT_TAMP2                       TAMP_IER_TAMP2IE     /*!< Tamper 2 Interrupt */
00313 #if defined(TAMP_CR1_TAMP3E)
00314 #define RTC_IT_TAMP3                       TAMP_IER_TAMP3IE     /*!< Tamper 3 Interrupt */
00315 #define RTC_IT_TAMPALL                     (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE)
00316 #else
00317 #define RTC_IT_TAMPALL                     (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE)
00318 #endif /* TAMP_CR1_TAMP3E */
00319
00320 #define RTC_IT_INT_TAMP3                   TAMP_IER_ITAMP3IE
00321 #define RTC_IT_INT_TAMP4                   TAMP_IER_ITAMP4IE
00322 #define RTC_IT_INT_TAMP5                   TAMP_IER_ITAMP5IE
00323 #define RTC_IT_INT_TAMP6                   TAMP_IER_ITAMP6IE
00324 #define RTC_IT_INT_TAMPALL                 (RTC_IT_INT_TAMP3 | RTC_IT_INT_TAMP4 | \
00325                                             RTC_IT_INT_TAMP5 | RTC_IT_INT_TAMP6)
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup RTCEx_Flags  RTCEx Flags
00331   * @{
00332   */
00333 #define RTC_FLAG_TAMP1                     TAMP_SR_TAMP1F
00334 #define RTC_FLAG_TAMP2                     TAMP_SR_TAMP2F
00335 #if defined(TAMP_CR1_TAMP3E)
00336 #define RTC_FLAG_TAMP3                     TAMP_SR_TAMP3F
00337 #define RTC_FLAG_TAMPALL                  (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3)
00338 #else
00339 #define RTC_FLAG_TAMPALL                  (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2)
00340 #endif /* TAMP_CR1_TAMP3E */
00341 #define RTC_FLAG_INT_TAMP3                 TAMP_SR_ITAMP3F
00342 #define RTC_FLAG_INT_TAMP4                 TAMP_SR_ITAMP4F
00343 #define RTC_FLAG_INT_TAMP5                 TAMP_SR_ITAMP5F
00344 #define RTC_FLAG_INT_TAMP6                 TAMP_SR_ITAMP6F
00345 #define RTC_FLAG_INT_TAMPALL               (RTC_FLAG_INT_TAMP3 | RTC_FLAG_INT_TAMP4 | \
00346                                             RTC_FLAG_INT_TAMP5 | RTC_FLAG_INT_TAMP6)
00347 /**
00348   * @}
00349   */
00350
00351
00352 /** @defgroup RTCEx_Backup_Registers  RTCEx Backup Registers Definition
00353   * @{
00354   */
00355 #define RTC_BKP_NUMBER                     0x00000005u
00356 #define RTC_BKP_DR0                        0x00000000u
00357 #define RTC_BKP_DR1                        0x00000001u
00358 #define RTC_BKP_DR2                        0x00000002u
00359 #define RTC_BKP_DR3                        0x00000003u
00360 #define RTC_BKP_DR4                        0x00000004u
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368
00369 /* Exported macros -----------------------------------------------------------*/
00370 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00371   * @{
00372   */
00373
00374 /** @brief  Clear the specified RTC pending flag.
00375   * @param  __HANDLE__ specifies the RTC Handle.
00376   * @param  __FLAG__ specifies the flag to check.
00377   *          This parameter can be any combination of the following values:
00378   *            @arg @ref RTC_CLEAR_ITSF               Clear Internal Time-stamp flag
00379   *            @arg @ref RTC_CLEAR_TSOVF              Clear Time-stamp overflow flag
00380   *            @arg @ref RTC_CLEAR_TSF                Clear Time-stamp flag
00381   *            @arg @ref RTC_CLEAR_WUTF               Clear Wakeup timer flag
00382   *            @arg @ref RTC_CLEAR_ALRBF              Clear Alarm B flag
00383   *            @arg @ref RTC_CLEAR_ALRAF              Clear Alarm A flag
00384   * @retval None
00385   */
00386 #define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->SCR |= (__FLAG__))
00387
00388 /** @brief  Check whether the specified RTC flag is set or not.
00389   * @param  __HANDLE__ specifies the RTC Handle.
00390   * @param  __FLAG__ specifies the flag to check.
00391   *          This parameter can be:
00392   *            @arg @ref RTC_FLAG_RECALPF             Recalibration pending Flag
00393   *            @arg @ref RTC_FLAG_INITF               Initialization flag
00394   *            @arg @ref RTC_FLAG_RSF                 Registers synchronization flag
00395   *            @arg @ref RTC_FLAG_INITS               Initialization status flag
00396   *            @arg @ref RTC_FLAG_SHPF                Shift operation pending flag
00397   *            @arg @ref RTC_FLAG_WUTWF               Wakeup timer write flag
00398   *            @arg @ref RTC_FLAG_ALRBWF              Alarm B write flag
00399   *            @arg @ref RTC_FLAG_ALRAWF              Alarm A write flag
00400   *            @arg @ref RTC_FLAG_ITSF                Internal Time-stamp flag
00401   *            @arg @ref RTC_FLAG_TSOVF               Time-stamp overflow flag
00402   *            @arg @ref RTC_FLAG_TSF                 Time-stamp flag
00403   *            @arg @ref RTC_FLAG_WUTF                Wakeup timer flag
00404   *            @arg @ref RTC_FLAG_ALRBF               Alarm B flag
00405   *            @arg @ref RTC_FLAG_ALRAF               Alarm A flag
00406   * @retval None
00407   */
00408 #define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)    (((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U) :\
00409                                                      ((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U))
00410
00411 /* ---------------------------------WAKEUPTIMER---------------------------------*/
00412 /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
00413   * @{
00414   */
00415 /**
00416   * @brief  Enable the RTC WakeUp Timer peripheral.
00417   * @param  __HANDLE__ specifies the RTC handle.
00418   * @retval None
00419   */
00420 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00421
00422 /**
00423   * @brief  Disable the RTC WakeUp Timer peripheral.
00424   * @param  __HANDLE__ specifies the RTC handle.
00425   * @retval None
00426   */
00427 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00428
00429 /**
00430   * @brief  Enable the RTC WakeUpTimer interrupt.
00431   * @param  __HANDLE__ specifies the RTC handle.
00432   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
00433   *         This parameter can be:
00434   *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
00435   * @retval None
00436   */
00437 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00438
00439 /**
00440   * @brief  Disable the RTC WakeUpTimer interrupt.
00441   * @param  __HANDLE__ specifies the RTC handle.
00442   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
00443   *         This parameter can be:
00444   *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
00445   * @retval None
00446   */
00447 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00448
00449 /**
00450   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00451   * @param  __HANDLE__ specifies the RTC handle.
00452   * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
00453   *         This parameter can be:
00454   *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
00455   * @retval None
00456   */
00457 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U)
00458
00459 /**
00460   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
00461   * @param  __HANDLE__ specifies the RTC handle.
00462   * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
00463   *         This parameter can be:
00464   *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
00465   * @retval None
00466   */
00467 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00468
00469 /**
00470   * @brief  Get the selected RTC WakeUpTimers flag status.
00471   * @param  __HANDLE__ specifies the RTC handle.
00472   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
00473   *          This parameter can be:
00474   *             @arg @ref RTC_FLAG_WUTF
00475   *             @arg @ref RTC_FLAG_WUTWF
00476   * @retval None
00477   */
00478 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
00479
00480 /**
00481   * @brief  Clear the RTC Wake Up timers pending flags.
00482   * @param  __HANDLE__ specifies the RTC handle.
00483   * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
00484   *         This parameter can be:
00485   *            @arg @ref RTC_FLAG_WUTF
00486   * @retval None
00487   */
00488 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
00489
00490 /* WAKE-UP TIMER EXTI */
00491 /* ------------------ */
00492 /**
00493   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
00494   * @retval None
00495   */
00496 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00497
00498 /**
00499   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
00500   * @retval None
00501   */
00502 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00503
00504 /**
00505   * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
00506   * @retval None.
00507   */
00508 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00509
00510 /**
00511   * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
00512   * @retval None.
00513   */
00514 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00515
00516 /**
00517   * @}
00518   */
00519
00520 /* ---------------------------------TIMESTAMP---------------------------------*/
00521 /** @defgroup RTCEx_Timestamp RTC Timestamp
00522   * @{
00523   */
00524 /**
00525   * @brief  Enable the RTC TimeStamp peripheral.
00526   * @param  __HANDLE__ specifies the RTC handle.
00527   * @retval None
00528   */
00529 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
00530
00531 /**
00532   * @brief  Disable the RTC TimeStamp peripheral.
00533   * @param  __HANDLE__ specifies the RTC handle.
00534   * @retval None
00535   */
00536 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
00537
00538 /**
00539   * @brief  Enable the RTC TimeStamp interrupt.
00540   * @param  __HANDLE__ specifies the RTC handle.
00541   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
00542   *         This parameter can be:
00543   *            @arg @ref RTC_IT_TS TimeStamp interrupt
00544   * @retval None
00545   */
00546 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00547
00548 /**
00549   * @brief  Disable the RTC TimeStamp interrupt.
00550   * @param  __HANDLE__ specifies the RTC handle.
00551   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
00552   *         This parameter can be:
00553   *            @arg @ref RTC_IT_TS TimeStamp interrupt
00554   * @retval None
00555   */
00556 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00557
00558 /**
00559   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
00560   * @param  __HANDLE__ specifies the RTC handle.
00561   * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
00562   *         This parameter can be:
00563   *            @arg @ref RTC_IT_TS TimeStamp interrupt
00564   * @retval None
00565   */
00566 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->SR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1U : 0U)
00567
00568 /**
00569   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
00570   * @param  __HANDLE__ specifies the RTC handle.
00571   * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
00572   *         This parameter can be:
00573   *            @arg @ref RTC_IT_TS TimeStamp interrupt
00574   * @retval None
00575   */
00576 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00577
00578 /**
00579   * @brief  Get the selected RTC TimeStamps flag status.
00580   * @param  __HANDLE__ specifies the RTC handle.
00581   * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
00582   *         This parameter can be:
00583   *            @arg @ref RTC_FLAG_TSF
00584   *            @arg @ref RTC_FLAG_TSOVF
00585   * @retval None
00586   */
00587 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
00588
00589 /**
00590   * @brief  Clear the RTC Time Stamps pending flags.
00591   * @param  __HANDLE__ specifies the RTC handle.
00592   * @param  __FLAG__ specifies the RTC TimeStamp Flag to clear.
00593   *          This parameter can be:
00594   *             @arg @ref RTC_FLAG_TSF
00595   *             @arg @ref RTC_FLAG_TSOVF
00596   * @retval None
00597   */
00598 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
00599
00600 /**
00601   * @brief  Enable interrupt on the RTC Timestamp associated Exti line.
00602   * @retval None
00603   */
00604 #define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
00605
00606 /**
00607   * @brief  Disable interrupt on the RTC Timestamp associated Exti line.
00608   * @retval None
00609   */
00610 #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
00611
00612 /**
00613   * @brief  Enable event on the RTC Timestamp associated Exti line.
00614   * @retval None
00615   */
00616 #define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
00617
00618 /**
00619   * @brief  Disable event on the RTC Timestamp associated Exti line.
00620   * @retval None
00621   */
00622 #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
00623
00624 /**
00625   * @brief  Enable the RTC internal TimeStamp peripheral.
00626   * @param  __HANDLE__ specifies the RTC handle.
00627   * @retval None
00628   */
00629 #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
00630
00631 /**
00632   * @brief  Disable the RTC internal TimeStamp peripheral.
00633   * @param  __HANDLE__ specifies the RTC handle.
00634   * @retval None
00635   */
00636 #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
00637
00638 /**
00639   * @brief  Get the selected RTC Internal Time Stamps flag status.
00640   * @param  __HANDLE__ specifies the RTC handle.
00641   * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
00642   *         This parameter can be:
00643   *            @arg @ref RTC_FLAG_ITSF
00644   * @retval None
00645   */
00646 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
00647
00648 /**
00649   * @brief  Clear the RTC Internal Time Stamps pending flags.
00650   * @param  __HANDLE__ specifies the RTC handle.
00651   * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
00652   * This parameter can be:
00653   *             @arg @ref RTC_FLAG_ITSF
00654   * @retval None
00655   */
00656 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
00657
00658 /**
00659   * @brief  Enable the RTC TimeStamp on Tamper detection.
00660   * @param  __HANDLE__ specifies the RTC handle.
00661   * @retval None
00662   */
00663 #define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))
00664
00665 /**
00666   * @brief  Disable the RTC TimeStamp on Tamper detection.
00667   * @param  __HANDLE__ specifies the RTC handle.
00668   * @retval None
00669   */
00670 #define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))
00671
00672 /**
00673   * @brief  Enable the RTC Tamper detection output.
00674   * @param  __HANDLE__ specifies the RTC handle.
00675   * @retval None
00676   */
00677 #define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
00678
00679 /**
00680   * @brief  Disable the RTC Tamper detection output.
00681   * @param  __HANDLE__ specifies the RTC handle.
00682   * @retval None
00683   */
00684 #define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
00685
00686
00687 /**
00688   * @}
00689   */
00690
00691
00692 /* ------------------------------Calibration----------------------------------*/
00693 /** @defgroup RTCEx_Calibration RTC Calibration
00694   * @{
00695   */
00696
00697 /**
00698   * @brief  Enable the RTC calibration output.
00699   * @param  __HANDLE__ specifies the RTC handle.
00700   * @retval None
00701   */
00702 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
00703
00704 /**
00705   * @brief  Disable the calibration output.
00706   * @param  __HANDLE__ specifies the RTC handle.
00707   * @retval None
00708   */
00709 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
00710
00711
00712 /**
00713   * @brief  Enable the clock reference detection.
00714   * @param  __HANDLE__ specifies the RTC handle.
00715   * @retval None
00716   */
00717 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
00718
00719 /**
00720   * @brief  Disable the clock reference detection.
00721   * @param  __HANDLE__ specifies the RTC handle.
00722   * @retval None
00723   */
00724 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
00725
00726
00727 /**
00728   * @brief  Get the selected RTC shift operations flag status.
00729   * @param  __HANDLE__ specifies the RTC handle.
00730   * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
00731   *          This parameter can be:
00732   *             @arg @ref RTC_FLAG_SHPF
00733   * @retval None
00734   */
00735 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
00736 /**
00737   * @}
00738   */
00739
00740
00741 /* ------------------------------Tamper----------------------------------*/
00742 /** @defgroup RTCEx_Tamper RTCEx tamper
00743   * @{
00744   */
00745 /**
00746   * @brief  Enable the TAMP Tamper input detection.
00747   * @param  __HANDLE__ specifies the RTC handle.
00748   * @param  __TAMPER__ specifies the RTC Tamper source to be enabled.
00749   *         This parameter can be any combination of the following values:
00750   *            @arg  RTC_ALL_TAMPER: All tampers
00751   *            @arg  RTC_TAMPER_1: Tamper1
00752   *            @arg  RTC_TAMPER_2: Tamper2
00753   *            @arg  RTC_TAMPER_3: Tamper3 (*)
00754   * @retval None
00755   */
00756 #define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__)           (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 |= (__TAMPER__))
00757
00758 /**
00759   * @brief  Disable the TAMP Tamper input detection.
00760   * @param  __HANDLE__ specifies the TAMP handle.
00761   * @param  __TAMPER__ specifies the TAMP Tamper sources to be enabled.
00762   *         This parameter can be any combination of the following values:
00763   *            @arg  RTC_ALL_TAMPER: All tampers
00764   *            @arg  RTC_TAMPER_1: Tamper1
00765   *            @arg  RTC_TAMPER_2: Tamper2
00766   *            @arg  RTC_TAMPER_3: Tamper3 (*)
00767   */
00768 #define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__)           (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 &= ~(__TAMPER__))
00769
00770
00771 /**************************************************************************************************/
00772 /**
00773   * @brief  Enable the TAMP Tamper interrupt.
00774   * @param  __HANDLE__ specifies the TAMP handle.
00775   * @param  __INTERRUPT__ specifies the TAMP Tamper interrupt sources to be enabled.
00776   *          This parameter can be any combination of the following values:
00777   *             @arg  RTC_IT_TAMPALL: All tampers interrupts
00778   *             @arg  RTC_IT_TAMP1: Tamper1 interrupt
00779   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
00780   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00781   * @retval None
00782   */
00783 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER |= (__INTERRUPT__))
00784
00785 /**
00786   * @brief  Disable the TAMP Tamper interrupt.
00787   * @param  __HANDLE__ specifies the TAMP handle.
00788   * @param  __INTERRUPT__ specifies the TAMP Tamper interrupt sources to be disabled.
00789   *         This parameter can be any combination of the following values:
00790   *            @arg  RTC_IT_TAMPALL: All tampers interrupts
00791   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00792   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00793   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00794   * @retval None
00795   */
00796 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER &= ~(__INTERRUPT__))
00797
00798
00799 /**************************************************************************************************/
00800 /**
00801   * @brief  Check whether the specified TAMP Tamper interrupt has occurred or not.
00802   * @param  __HANDLE__ specifies the TAMP handle.
00803   * @param  __INTERRUPT__ specifies the TAMP Tamper interrupt to check.
00804   *         This parameter can be:
00805   *            @arg  RTC_IT_TAMPALL: All tampers interrupts
00806   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00807   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00808   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00809   *            @arg  RTC_IT_INT_TAMP3: Internal Tamper3 interrupt
00810   *            @arg  RTC_IT_INT_TAMP4: Internal Tamper4 interrupt
00811   *            @arg  RTC_IT_INT_TAMP5: Internal Tamper5 interrupt
00812   *            @arg  RTC_IT_INT_TAMP6: Internal Tamper6 interrupt
00813   * @retval None
00814   */
00815 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)     ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00816
00817
00818 /**
00819   * @brief  Check whether the specified TAMP Tamper interrupt has been enabled or not.
00820   * @param  __HANDLE__ specifies the TAMP handle.
00821   * @param  __INTERRUPT__ specifies the TAMP Tamper interrupt source to check.
00822   *         This parameter can be:
00823   *            @arg  RTC_IT_TAMPALL: All tampers interrupts
00824   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00825   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00826   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00827   *            @arg  RTC_IT_INT_TAMPALL: All internal tampers interrupts
00828   *            @arg  RTC_IT_INT_TAMP3: Internal Tamper3 interrupt
00829   *            @arg  RTC_IT_INT_TAMP4: Internal Tamper4 interrupt
00830   *            @arg  RTC_IT_INT_TAMP5: Internal Tamper5 interrupt
00831   *            @arg  RTC_IT_INT_TAMP6: Internal Tamper6 interrupt
00832   * @retval None
00833   */
00834 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00835
00836
00837 /**
00838   * @brief  Get the selected TAMP Tampers flag status.
00839   * @param  __HANDLE__ specifies the TAMP handle.
00840   * @param  __FLAG__ specifies the TAMP Tamper Flag is pending or not.
00841   *          This parameter can be:
00842   *             @arg RTC_FLAG_TAMP1: Tamper1 flag
00843   *             @arg RTC_FLAG_TAMP2: Tamper2 flag
00844   *             @arg RTC_FLAG_TAMP3: Tamper3 flag (*)
00845   *             @arg RTC_FLAG_INT_TAMP3: Internal Tamper3 flag
00846   *             @arg RTC_FLAG_INT_TAMP4: Internal Tamper4 flag
00847   *             @arg RTC_FLAG_INT_TAMP5: Internal Tamper5 flag
00848   *             @arg RTC_FLAG_INT_TAMP6: Internal Tamper6 flag
00849   * @retval None
00850   */
00851 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__FLAG__)) != 0U)
00852
00853 /**
00854   * @brief  Clear the TAMP Tampers pending flags.
00855   * @param  __HANDLE__ specifies the TAMP handle.
00856   * @param  __FLAG__ specifies the TAMP Tamper Flag to clear.
00857   *          This parameter can be:
00858   *             @arg RTC_FLAG_TAMPALL: All Tamper flags
00859   *             @arg RTC_FLAG_TAMP1: Tamper1 flag
00860   *             @arg RTC_FLAG_TAMP2: Tamper2 flag
00861   *             @arg RTC_FLAG_TAMP3: Tamper3 flag (*)
00862   *             @arg RTC_FLAG_INT_TAMP3: Internal Tamper3 flag
00863   *             @arg RTC_FLAG_INT_TAMP4: Internal Tamper4 flag
00864   *             @arg RTC_FLAG_INT_TAMP5: Internal Tamper5 flag
00865   *             @arg RTC_FLAG_INT_TAMP6: Internal Tamper6 flag
00866   * @retval None
00867   */
00868 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SCR) |= (__FLAG__))
00869
00870 /**
00871   * @brief  Enable interrupt on the TAMP associated Exti line.
00872   * @retval None
00873   */
00874 #define __HAL_RTC_TAMPER_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
00875
00876 /**
00877   * @brief  Disable interrupt on the TAMP associated Exti line.
00878   * @retval None
00879   */
00880 #define __HAL_RTC_TAMPER_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
00881
00882 /**
00883   * @brief  Enable event on the TAMP associated Exti line.
00884   * @retval None
00885   */
00886 #define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
00887
00888 /**
00889   * @brief  Disable event on the TAMP associated Exti line.
00890   * @retval None
00891   */
00892 #define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
00893
00894 /**
00895   * @}
00896   */
00897
00898 /**
00899   * @}
00900   */
00901
00902 /* Exported functions --------------------------------------------------------*/
00903 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00904   * @{
00905   */
00906
00907 /* RTC TimeStamp functions *****************************************/
00908 /** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions
00909  * @{
00910  */
00911
00912 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00913 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00914 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
00915 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
00916 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
00917 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
00918
00919 void              HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
00920 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00921 void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
00922 /**
00923   * @}
00924   */
00925
00926
00927 /* RTC Wake-up functions ******************************************************/
00928 /** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
00929  * @{
00930  */
00931
00932 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00933 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00934 HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
00935 uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
00936 void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
00937 void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
00938 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00939 /**
00940   * @}
00941   */
00942
00943 /* Extended Control functions ************************************************/
00944 /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
00945  * @{
00946  */
00947
00948 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
00949 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
00950 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
00951 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
00952 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
00953 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
00954 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
00955 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
00956 /**
00957   * @}
00958   */
00959
00960 /* Extended RTC features functions *******************************************/
00961 /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
00962  * @{
00963  */
00964
00965 void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
00966 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00967 /**
00968   * @}
00969   */
00970
00971 /** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions
00972  * @{
00973  */
00974 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00975 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00976 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
00977 HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout);
00978 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef* sIntTamper);
00979 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef* sIntTamper);
00980 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
00981 HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);
00982 void              HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
00983 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
00984 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
00985 #if defined(TAMP_CR1_TAMP3E)
00986 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
00987 #endif /* TAMP_CR1_TAMP3E */
00988 void              HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
00989 void              HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
00990 void              HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
00991 void              HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
00992 /**
00993   * @}
00994   */
00995
00996 /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions
00997  * @{
00998  */
00999 void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
01000 uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
01001 /**
01002   * @}
01003   */
01004
01005
01006 /**
01007   * @}
01008   */
01009
01010 /* Private types -------------------------------------------------------------*/
01011 /* Private variables ---------------------------------------------------------*/
01012 /* Private constants ---------------------------------------------------------*/
01013 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
01014   * @{
01015   */
01016 #define RTC_EXTI_LINE_TIMESTAMP_EVENT         EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC Time Stamp events */
01017 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC Wakeup event */
01018 #define RTC_EXTI_LINE_TAMPER_EVENT            EXTI_IMR1_IM21 /*!< External interrupt line 19 Connected to the RTC tamper events*/
01019
01020 /**
01021   * @}
01022   */
01023
01024 /* Private macros ------------------------------------------------------------*/
01025 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
01026   * @{
01027   */
01028
01029 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
01030   * @{
01031   */
01032 #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
01033                                  ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
01034
01035
01036 #define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
01037
01038
01039
01040 #define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
01041                                                               ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
01042
01043 #define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE)    (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
01044                                                       ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
01045
01046
01047 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
01048                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
01049                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
01050                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
01051                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
01052                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
01053
01054 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= RTC_WUTR_WUT)
01055
01056 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
01057                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
01058                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
01059
01060 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
01061                                         ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
01062
01063 #define IS_RTC_TAMPER(__TAMPER__)                ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
01064                                                    (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))
01065
01066 #define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)   ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
01067                                                    (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))
01068
01069 #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__)       (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)  || \
01070                                                    ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
01071                                                    ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)    || \
01072                                                    ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
01073
01074 #define IS_RTC_TAMPER_ERASE_MODE(__MODE__)       (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
01075                                                    ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
01076
01077 #define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)  (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
01078                                                    ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
01079
01080 #define IS_RTC_TAMPER_FILTER(__FILTER__)         (((__FILTER__) == RTC_TAMPERFILTER_DISABLE)  || \
01081                                                    ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
01082                                                    ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
01083                                                    ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
01084
01085 #define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)    (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
01086                                                    ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
01087                                                    ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
01088                                                    ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
01089                                                    ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
01090                                                    ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
01091                                                    ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
01092                                                    ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
01093
01094 #define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)   (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
01095                                                            ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
01096                                                            ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
01097                                                            ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
01098
01099 #define IS_RTC_TAMPER_PULLUP_STATE(__STATE__)    (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
01100                                                    ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
01101
01102 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
01103                                                               ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
01104
01105 #define IS_RTC_BKP(__BKP__)                      ((__BKP__) < RTC_BKP_NUMBER)
01106
01107
01108 /** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTCEx Smooth calib Minus pulses Definitions
01109   * @{
01110   */
01111 #define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
01112 /**
01113   * @}
01114   */
01115
01116
01117 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
01118                                  ((SEL) == RTC_SHIFTADD1S_SET))
01119
01120
01121
01122 /** @defgroup RTCEx_Subtract_Fraction_Of_Second_Value RTCEx Subtract Fraction Of Second Value
01123   * @{
01124   */
01125 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
01126 /**
01127   * @}
01128   */
01129 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
01130                                       ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
01131
01132 /**
01133   * @}
01134   */
01135
01136 /**
01137   * @}
01138   */
01139
01140
01141
01142 /**
01143   * @}
01144   */
01145
01146 /**
01147   * @}
01148   */
01149
01150 #ifdef __cplusplus
01151 }
01152 #endif
01153
01154 #endif /* STM32G0xx_HAL_RTC_EX_H */
01155
01156
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smartcard.c Source File

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stm32g0xx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the SMARTCARD peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Error functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2018 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                         ##### How to use this driver #####
00027   ==============================================================================
00028   [..]
00029     The SMARTCARD HAL driver can be used as follows:
00030
00031     (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
00032     (#) Associate a USART to the SMARTCARD handle hsmartcard.
00033     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00034         (++) Enable the USARTx interface clock.
00035         (++) USART pins configuration:
00036              (+++) Enable the clock for the USART GPIOs.
00037              (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
00038         (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00039              and HAL_SMARTCARD_Receive_IT() APIs):
00040              (+++) Configure the USARTx interrupt priority.
00041              (+++) Enable the NVIC USART IRQ handle.
00042         (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00043              and HAL_SMARTCARD_Receive_DMA() APIs):
00044              (+++) Declare a DMA handle structure for the Tx/Rx channel.
00045              (+++) Enable the DMAx interface clock.
00046              (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00047              (+++) Configure the DMA Tx/Rx channel.
00048              (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00049              (+++) Configure the priority and enable the NVIC for the transfer complete
00050                    interrupt on the DMA Tx/Rx channel.
00051
00052     (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
00053         the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
00054         error enabling or disabling in the hsmartcard handle Init structure.
00055
00056     (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
00057         in the hsmartcard handle AdvancedInit structure.
00058
00059     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00060         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00061              by calling the customized HAL_SMARTCARD_MspInit() API.
00062         [..]
00063         (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
00064              RXNE interrupt and Error Interrupts) will be managed using the macros
00065              __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00066
00067     [..]
00068     [..] Three operation modes are available within this driver :
00069
00070      *** Polling mode IO operation ***
00071      =================================
00072      [..]
00073        (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00074        (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00075
00076      *** Interrupt mode IO operation ***
00077      ===================================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
00080        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00082        (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
00083        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00084             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00085        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00086             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00087
00088      *** DMA mode IO operation ***
00089      ==============================
00090      [..]
00091        (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00092        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00093             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00094        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00095        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00096             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00097        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00098             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00099
00100      *** SMARTCARD HAL driver macros list ***
00101      ========================================
00102      [..]
00103        Below the list of most used macros in SMARTCARD HAL driver.
00104
00105        (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
00106        (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00107        (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00108        (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00109        (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
00110
00111      [..]
00112        (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00113
00114     ##### Callback registration #####
00115     ==================================
00116
00117     [..]
00118     The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
00119     allows the user to configure dynamically the driver callbacks.
00120
00121     [..]
00122     Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
00123     Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
00124     (+) TxCpltCallback            : Tx Complete Callback.
00125     (+) RxCpltCallback            : Rx Complete Callback.
00126     (+) ErrorCallback             : Error Callback.
00127     (+) AbortCpltCallback         : Abort Complete Callback.
00128     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00129     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00130     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00131     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00132     (+) MspInitCallback           : SMARTCARD MspInit.
00133     (+) MspDeInitCallback         : SMARTCARD MspDeInit.
00134     This function takes as parameters the HAL peripheral handle, the Callback ID
00135     and a pointer to the user callback function.
00136
00137     [..]
00138     Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
00139     weak (surcharged) function.
00140     HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00141     and the Callback ID.
00142     This function allows to reset following callbacks:
00143     (+) TxCpltCallback            : Tx Complete Callback.
00144     (+) RxCpltCallback            : Rx Complete Callback.
00145     (+) ErrorCallback             : Error Callback.
00146     (+) AbortCpltCallback         : Abort Complete Callback.
00147     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00148     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00149     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00150     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00151     (+) MspInitCallback           : SMARTCARD MspInit.
00152     (+) MspDeInitCallback         : SMARTCARD MspDeInit.
00153
00154     [..]
00155     By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
00156     all callbacks are set to the corresponding weak (surcharged) functions:
00157     examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
00158     Exception done for MspInit and MspDeInit functions that are respectively
00159     reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
00160     and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
00161     If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
00162     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00163
00164     [..]
00165     Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
00166     Exception done MspInit/MspDeInit that can be registered/unregistered
00167     in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
00168     MspInit/DeInit callbacks can be used during the Init/DeInit.
00169     In that case first register the MspInit/MspDeInit user callbacks
00170     using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
00171     or HAL_SMARTCARD_Init() function.
00172
00173     [..]
00174     When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
00175     not defined, the callback registration feature is not available
00176     and weak (surcharged) callbacks are used.
00177
00178
00179   @endverbatim
00180   ******************************************************************************
00181   */
00182
00183 /* Includes ------------------------------------------------------------------*/
00184 #include "stm32g0xx_hal.h"
00185
00186 /** @addtogroup STM32G0xx_HAL_Driver
00187   * @{
00188   */
00189
00190 /** @defgroup SMARTCARD SMARTCARD
00191   * @brief HAL SMARTCARD module driver
00192   * @{
00193   */
00194
00195 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00196
00197 /* Private typedef -----------------------------------------------------------*/
00198 /* Private define ------------------------------------------------------------*/
00199 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00200   * @{
00201   */
00202 #define SMARTCARD_TEACK_REACK_TIMEOUT  1000U       /*!< SMARTCARD TX or RX enable acknowledge time-out value */
00203
00204 #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
00205                                       USART_CR1_RE | USART_CR1_OVER8| \
00206                                       USART_CR1_FIFOEN))  /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
00207
00208 #define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
00209                                           USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
00210
00211 #define USART_CR2_FIELDS  ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
00212                                       USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
00213
00214 #define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
00215                                       USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
00216
00217 #define USART_BRR_MIN  0x10U        /*!< USART BRR minimum authorized value */
00218
00219 #define USART_BRR_MAX  0x0000FFFFU  /*!< USART BRR maximum authorized value */
00220 /**
00221   * @}
00222   */
00223
00224 /* Private macros ------------------------------------------------------------*/
00225 /* Private variables ---------------------------------------------------------*/
00226 /* Private function prototypes -----------------------------------------------*/
00227 /** @addtogroup SMARTCARD_Private_Functions
00228   * @{
00229   */
00230 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00231 void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
00232 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00233 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00234 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00235 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
00236 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
00237                                                           FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00238 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00239 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00240 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00241 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00242 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00243 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00244 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00245 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00246 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00247 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00248 static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
00249 static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
00250 static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00251 static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
00252 static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
00253 /**
00254   * @}
00255   */
00256
00257 /* Exported functions --------------------------------------------------------*/
00258
00259 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00260   * @{
00261   */
00262
00263 /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00264   * @brief    Initialization and Configuration functions
00265   *
00266 @verbatim
00267   ==============================================================================
00268               ##### Initialization and Configuration functions #####
00269   ==============================================================================
00270   [..]
00271   This subsection provides a set of functions allowing to initialize the USARTx
00272   associated to the SmartCard.
00273   (+) These parameters can be configured:
00274       (++) Baud Rate
00275       (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
00276       (++) Receiver/transmitter modes
00277       (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
00278       (++) Prescaler value
00279       (++) Guard bit time
00280       (++) NACK enabling or disabling on transmission error
00281
00282   (+) The following advanced features can be configured as well:
00283       (++) TX and/or RX pin level inversion
00284       (++) data logical level inversion
00285       (++) RX and TX pins swap
00286       (++) RX overrun detection disabling
00287       (++) DMA disabling on RX error
00288       (++) MSB first on communication line
00289       (++) Time out enabling (and if activated, timeout value)
00290       (++) Block length
00291       (++) Auto-retry counter
00292   [..]
00293   The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
00294   (details for the procedures are available in reference manual).
00295
00296 @endverbatim
00297
00298   The USART frame format is given in the following table:
00299
00300     Table 1. USART frame format.
00301     +---------------------------------------------------------------+
00302     | M1M0 bits |  PCE bit  |            USART frame                |
00303     |-----------------------|---------------------------------------|
00304     |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
00305     +---------------------------------------------------------------+
00306
00307
00308   * @{
00309   */
00310
00311 /**
00312   * @brief  Initialize the SMARTCARD mode according to the specified
00313   *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
00314   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00315   *                    the configuration information for the specified SMARTCARD module.
00316   * @retval HAL status
00317   */
00318 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
00319 {
00320   /* Check the SMARTCARD handle allocation */
00321   if (hsmartcard == NULL)
00322   {
00323     return HAL_ERROR;
00324   }
00325
00326   /* Check the USART associated to the SMARTCARD handle */
00327   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00328
00329   if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00330   {
00331     /* Allocate lock resource and initialize it */
00332     hsmartcard->Lock = HAL_UNLOCKED;
00333
00334 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00335     SMARTCARD_InitCallbacksToDefault(hsmartcard);
00336
00337     if (hsmartcard->MspInitCallback == NULL)
00338     {
00339       hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
00340     }
00341
00342     /* Init the low level hardware */
00343     hsmartcard->MspInitCallback(hsmartcard);
00344 #else
00345     /* Init the low level hardware : GPIO, CLOCK */
00346     HAL_SMARTCARD_MspInit(hsmartcard);
00347 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00348   }
00349
00350   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00351
00352   /* Disable the Peripheral to set smartcard mode */
00353   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00354
00355   /* In SmartCard mode, the following bits must be kept cleared:
00356   - LINEN in the USART_CR2 register,
00357   - HDSEL and IREN  bits in the USART_CR3 register.*/
00358   CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
00359   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
00360
00361   /* set the USART in SMARTCARD mode */
00362   SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
00363
00364   /* Set the SMARTCARD Communication parameters */
00365   if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
00366   {
00367     return HAL_ERROR;
00368   }
00369
00370   /* Set the SMARTCARD transmission completion indication */
00371   SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
00372
00373   if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
00374   {
00375     SMARTCARD_AdvFeatureConfig(hsmartcard);
00376   }
00377
00378   /* Enable the Peripheral */
00379   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00380
00381   /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
00382   return (SMARTCARD_CheckIdleState(hsmartcard));
00383 }
00384
00385 /**
00386   * @brief  DeInitialize the SMARTCARD peripheral.
00387   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00388   *                    the configuration information for the specified SMARTCARD module.
00389   * @retval HAL status
00390   */
00391 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00392 {
00393   /* Check the SMARTCARD handle allocation */
00394   if (hsmartcard == NULL)
00395   {
00396     return HAL_ERROR;
00397   }
00398
00399   /* Check the USART/UART associated to the SMARTCARD handle */
00400   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00401
00402   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00403
00404   /* Disable the Peripheral */
00405   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00406
00407   WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
00408   WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
00409   WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
00410   WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
00411   WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
00412
00413   /* DeInit the low level hardware */
00414 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00415   if (hsmartcard->MspDeInitCallback == NULL)
00416   {
00417     hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
00418   }
00419   /* DeInit the low level hardware */
00420   hsmartcard->MspDeInitCallback(hsmartcard);
00421 #else
00422   HAL_SMARTCARD_MspDeInit(hsmartcard);
00423 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00424
00425   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00426   hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
00427   hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
00428
00429   /* Process Unlock */
00430   __HAL_UNLOCK(hsmartcard);
00431
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @brief  Initialize the SMARTCARD MSP.
00437   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00438   *                    the configuration information for the specified SMARTCARD module.
00439   * @retval None
00440   */
00441 __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
00442 {
00443   /* Prevent unused argument(s) compilation warning */
00444   UNUSED(hsmartcard);
00445
00446   /* NOTE : This function should not be modified, when the callback is needed,
00447             the HAL_SMARTCARD_MspInit can be implemented in the user file
00448    */
00449 }
00450
00451 /**
00452   * @brief  DeInitialize the SMARTCARD MSP.
00453   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00454   *                    the configuration information for the specified SMARTCARD module.
00455   * @retval None
00456   */
00457 __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00458 {
00459   /* Prevent unused argument(s) compilation warning */
00460   UNUSED(hsmartcard);
00461
00462   /* NOTE : This function should not be modified, when the callback is needed,
00463             the HAL_SMARTCARD_MspDeInit can be implemented in the user file
00464    */
00465 }
00466
00467 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00468 /**
00469   * @brief  Register a User SMARTCARD Callback
00470   *         To be used instead of the weak predefined callback
00471   * @param  hsmartcard smartcard handle
00472   * @param  CallbackID ID of the callback to be registered
00473   *         This parameter can be one of the following values:
00474   *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
00475   *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
00476   *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
00477   *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00478   *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00479   *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00480   *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00481   *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00482   *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
00483   *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
00484   * @param  pCallback pointer to the Callback function
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
00488                                                  HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
00489                                                  pSMARTCARD_CallbackTypeDef pCallback)
00490 {
00491   HAL_StatusTypeDef status = HAL_OK;
00492
00493   if (pCallback == NULL)
00494   {
00495     /* Update the error code */
00496     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00497
00498     return HAL_ERROR;
00499   }
00500   /* Process locked */
00501   __HAL_LOCK(hsmartcard);
00502
00503   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00504   {
00505     switch (CallbackID)
00506     {
00507
00508       case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
00509         hsmartcard->TxCpltCallback = pCallback;
00510         break;
00511
00512       case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
00513         hsmartcard->RxCpltCallback = pCallback;
00514         break;
00515
00516       case HAL_SMARTCARD_ERROR_CB_ID :
00517         hsmartcard->ErrorCallback = pCallback;
00518         break;
00519
00520       case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
00521         hsmartcard->AbortCpltCallback = pCallback;
00522         break;
00523
00524       case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
00525         hsmartcard->AbortTransmitCpltCallback = pCallback;
00526         break;
00527
00528       case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
00529         hsmartcard->AbortReceiveCpltCallback = pCallback;
00530         break;
00531
00532       case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
00533         hsmartcard->RxFifoFullCallback = pCallback;
00534         break;
00535
00536       case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
00537         hsmartcard->TxFifoEmptyCallback = pCallback;
00538         break;
00539
00540       case HAL_SMARTCARD_MSPINIT_CB_ID :
00541         hsmartcard->MspInitCallback = pCallback;
00542         break;
00543
00544       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00545         hsmartcard->MspDeInitCallback = pCallback;
00546         break;
00547
00548       default :
00549         /* Update the error code */
00550         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00551
00552         /* Return error status */
00553         status =  HAL_ERROR;
00554         break;
00555     }
00556   }
00557   else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00558   {
00559     switch (CallbackID)
00560     {
00561       case HAL_SMARTCARD_MSPINIT_CB_ID :
00562         hsmartcard->MspInitCallback = pCallback;
00563         break;
00564
00565       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00566         hsmartcard->MspDeInitCallback = pCallback;
00567         break;
00568
00569       default :
00570         /* Update the error code */
00571         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00572
00573         /* Return error status */
00574         status =  HAL_ERROR;
00575         break;
00576     }
00577   }
00578   else
00579   {
00580     /* Update the error code */
00581     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00582
00583     /* Return error status */
00584     status =  HAL_ERROR;
00585   }
00586
00587   /* Release Lock */
00588   __HAL_UNLOCK(hsmartcard);
00589
00590   return status;
00591 }
00592
00593 /**
00594   * @brief  Unregister an SMARTCARD callback
00595   *         SMARTCARD callback is redirected to the weak predefined callback
00596   * @param  hsmartcard smartcard handle
00597   * @param  CallbackID ID of the callback to be unregistered
00598   *         This parameter can be one of the following values:
00599   *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
00600   *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
00601   *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
00602   *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00603   *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00604   *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00605   *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00606   *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00607   *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
00608   *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
00609   * @retval HAL status
00610   */
00611 HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
00612                                                    HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
00613 {
00614   HAL_StatusTypeDef status = HAL_OK;
00615
00616   /* Process locked */
00617   __HAL_LOCK(hsmartcard);
00618
00619   if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
00620   {
00621     switch (CallbackID)
00622     {
00623       case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
00624         hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback;                 /* Legacy weak TxCpltCallback */
00625         break;
00626
00627       case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
00628         hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback;                 /* Legacy weak RxCpltCallback */
00629         break;
00630
00631       case HAL_SMARTCARD_ERROR_CB_ID :
00632         hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback;                   /* Legacy weak ErrorCallback  */
00633         break;
00634
00635       case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
00636         hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback;           /* Legacy weak AbortCpltCallback */
00637         break;
00638
00639       case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
00640         hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
00641                                                                                             AbortTransmitCpltCallback*/
00642         break;
00643
00644       case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
00645         hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak
00646                                                                                            AbortReceiveCpltCallback */
00647         break;
00648
00649       case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
00650         hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback */
00651         break;
00652
00653       case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
00654         hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback;    /* Legacy weak TxFifoEmptyCallback */
00655         break;
00656
00657       case HAL_SMARTCARD_MSPINIT_CB_ID :
00658         hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;                       /* Legacy weak MspInitCallback  */
00659         break;
00660
00661       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00662         hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;                   /* Legacy weak MspDeInitCallback */
00663         break;
00664
00665       default :
00666         /* Update the error code */
00667         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00668
00669         /* Return error status */
00670         status =  HAL_ERROR;
00671         break;
00672     }
00673   }
00674   else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
00675   {
00676     switch (CallbackID)
00677     {
00678       case HAL_SMARTCARD_MSPINIT_CB_ID :
00679         hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
00680         break;
00681
00682       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00683         hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
00684         break;
00685
00686       default :
00687         /* Update the error code */
00688         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00689
00690         /* Return error status */
00691         status =  HAL_ERROR;
00692         break;
00693     }
00694   }
00695   else
00696   {
00697     /* Update the error code */
00698     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00699
00700     /* Return error status */
00701     status =  HAL_ERROR;
00702   }
00703
00704   /* Release Lock */
00705   __HAL_UNLOCK(hsmartcard);
00706
00707   return status;
00708 }
00709 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00716   * @brief    SMARTCARD Transmit and Receive functions
00717   *
00718 @verbatim
00719   ==============================================================================
00720                          ##### IO operation functions #####
00721   ==============================================================================
00722   [..]
00723     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00724
00725   [..]
00726     Smartcard is a single wire half duplex communication protocol.
00727     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00728     defined in the ISO 7816-3 standard. The USART should be configured as:
00729     (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00730     (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00731
00732   [..]
00733     (#) There are two modes of transfer:
00734         (##) Blocking mode: The communication is performed in polling mode.
00735              The HAL status of all data processing is returned by the same function
00736              after finishing transfer.
00737         (##) Non-Blocking mode: The communication is performed using Interrupts
00738              or DMA, the relevant API's return the HAL status.
00739              The end of the data processing will be indicated through the
00740              dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00741              using DMA mode.
00742         (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00743              will be executed respectively at the end of the Transmit or Receive process
00744              The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
00745              error is detected.
00746
00747     (#) Blocking mode APIs are :
00748         (##) HAL_SMARTCARD_Transmit()
00749         (##) HAL_SMARTCARD_Receive()
00750
00751     (#) Non Blocking mode APIs with Interrupt are :
00752         (##) HAL_SMARTCARD_Transmit_IT()
00753         (##) HAL_SMARTCARD_Receive_IT()
00754         (##) HAL_SMARTCARD_IRQHandler()
00755
00756     (#) Non Blocking mode functions with DMA are :
00757         (##) HAL_SMARTCARD_Transmit_DMA()
00758         (##) HAL_SMARTCARD_Receive_DMA()
00759
00760     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00761         (##) HAL_SMARTCARD_TxCpltCallback()
00762         (##) HAL_SMARTCARD_RxCpltCallback()
00763         (##) HAL_SMARTCARD_ErrorCallback()
00764
00765   [..]
00766     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00767         (##) HAL_SMARTCARD_Abort()
00768         (##) HAL_SMARTCARD_AbortTransmit()
00769         (##) HAL_SMARTCARD_AbortReceive()
00770         (##) HAL_SMARTCARD_Abort_IT()
00771         (##) HAL_SMARTCARD_AbortTransmit_IT()
00772         (##) HAL_SMARTCARD_AbortReceive_IT()
00773
00774     (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
00775         a set of Abort Complete Callbacks are provided:
00776         (##) HAL_SMARTCARD_AbortCpltCallback()
00777         (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
00778         (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
00779
00780     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00781         Errors are handled as follows :
00782        (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00783            to be evaluated by user : this concerns Frame Error,
00784            Parity Error or Noise Error in Interrupt mode reception .
00785            Received character is then retrieved and stored in Rx buffer,
00786            Error code is set to allow user to identify error type,
00787            and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
00788            If user wants to abort it, Abort services should be called by user.
00789        (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00790            This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
00791            mode reception and all errors in DMA mode.
00792            Error code is set to allow user to identify error type,
00793            and HAL_SMARTCARD_ErrorCallback() user callback is executed.
00794
00795 @endverbatim
00796   * @{
00797   */
00798
00799 /**
00800   * @brief  Send an amount of data in blocking mode.
00801   * @note   When FIFO mode is enabled, writing a data in the TDR register adds one
00802   *         data to the TXFIFO. Write operations to the TDR register are performed
00803   *         when TXFNF flag is set. From hardware perspective, TXFNF flag and
00804   *         TXE are mapped on the same bit-field.
00805   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00806   *                    the configuration information for the specified SMARTCARD module.
00807   * @param  pData pointer to data buffer.
00808   * @param  Size amount of data to be sent.
00809   * @param  Timeout  Timeout duration.
00810   * @retval HAL status
00811   */
00812 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
00813                                          uint32_t Timeout)
00814 {
00815   uint32_t tickstart;
00816   const uint8_t  *ptmpdata = pData;
00817
00818   /* Check that a Tx process is not already ongoing */
00819   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00820   {
00821     if ((ptmpdata == NULL) || (Size == 0U))
00822     {
00823       return  HAL_ERROR;
00824     }
00825
00826     /* Process Locked */
00827     __HAL_LOCK(hsmartcard);
00828
00829     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00830
00831     /* Init tickstart for timeout management */
00832     tickstart = HAL_GetTick();
00833
00834     /* Disable the Peripheral first to update mode for TX master */
00835     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00836
00837     /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
00838        the bidirectional line to detect a NACK signal in case of parity error.
00839        Therefore, the receiver block must be enabled as well (RE bit must be set). */
00840     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
00841         && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
00842     {
00843       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00844     }
00845     /* Enable Tx */
00846     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00847
00848     /* Enable the Peripheral */
00849     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00850
00851     /* Perform a TX/RX FIFO Flush */
00852     __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
00853
00854     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00855     hsmartcard->TxXferSize = Size;
00856     hsmartcard->TxXferCount = Size;
00857
00858     while (hsmartcard->TxXferCount > 0U)
00859     {
00860       hsmartcard->TxXferCount--;
00861       if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00862       {
00863         return HAL_TIMEOUT;
00864       }
00865       hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
00866       ptmpdata++;
00867     }
00868     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
00869                                          tickstart, Timeout) != HAL_OK)
00870     {
00871       return HAL_TIMEOUT;
00872     }
00873
00874     /* Disable the Peripheral first to update mode */
00875     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00876     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
00877         && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
00878     {
00879       /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
00880          for Transmit phase. Disable this receiver block. */
00881       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00882     }
00883     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
00884         || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
00885     {
00886       /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
00887       __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
00888     }
00889     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00890
00891     /* At end of Tx process, restore hsmartcard->gState to Ready */
00892     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00893
00894     /* Process Unlocked */
00895     __HAL_UNLOCK(hsmartcard);
00896
00897     return HAL_OK;
00898   }
00899   else
00900   {
00901     return HAL_BUSY;
00902   }
00903 }
00904
00905 /**
00906   * @brief  Receive an amount of data in blocking mode.
00907   * @note   When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
00908   *         is not empty. Read operations from the RDR register are performed when
00909   *         RXFNE flag is set. From hardware perspective, RXFNE flag and
00910   *         RXNE are mapped on the same bit-field.
00911   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00912   *                    the configuration information for the specified SMARTCARD module.
00913   * @param  pData pointer to data buffer.
00914   * @param  Size amount of data to be received.
00915   * @param  Timeout Timeout duration.
00916   * @retval HAL status
00917   */
00918 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
00919                                         uint32_t Timeout)
00920 {
00921   uint32_t tickstart;
00922   uint8_t  *ptmpdata = pData;
00923
00924   /* Check that a Rx process is not already ongoing */
00925   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00926   {
00927     if ((ptmpdata == NULL) || (Size == 0U))
00928     {
00929       return  HAL_ERROR;
00930     }
00931
00932     /* Process Locked */
00933     __HAL_LOCK(hsmartcard);
00934
00935     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00936     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00937
00938     /* Init tickstart for timeout management */
00939     tickstart = HAL_GetTick();
00940
00941     hsmartcard->RxXferSize = Size;
00942     hsmartcard->RxXferCount = Size;
00943
00944     /* Check the remain data to be received */
00945     while (hsmartcard->RxXferCount > 0U)
00946     {
00947       hsmartcard->RxXferCount--;
00948
00949       if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00950       {
00951         return HAL_TIMEOUT;
00952       }
00953       *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
00954       ptmpdata++;
00955     }
00956
00957     /* At end of Rx process, restore hsmartcard->RxState to Ready */
00958     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00959
00960     /* Process Unlocked */
00961     __HAL_UNLOCK(hsmartcard);
00962
00963     return HAL_OK;
00964   }
00965   else
00966   {
00967     return HAL_BUSY;
00968   }
00969 }
00970
00971 /**
00972   * @brief  Send an amount of data in interrupt mode.
00973   * @note   When FIFO mode is disabled, USART interrupt is generated whenever
00974   *         USART_TDR register is empty, i.e one interrupt per data to transmit.
00975   * @note   When FIFO mode is enabled, USART interrupt is generated whenever
00976   *         TXFIFO threshold reached. In that case the interrupt rate depends on
00977   *         TXFIFO threshold configuration.
00978   * @note   This function sets the hsmartcard->TxIsr function pointer according to
00979   *         the FIFO mode (data transmission processing depends on FIFO mode).
00980   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00981   *                    the configuration information for the specified SMARTCARD module.
00982   * @param  pData pointer to data buffer.
00983   * @param  Size amount of data to be sent.
00984   * @retval HAL status
00985   */
00986 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
00987 {
00988   /* Check that a Tx process is not already ongoing */
00989   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00990   {
00991     if ((pData == NULL) || (Size == 0U))
00992     {
00993       return HAL_ERROR;
00994     }
00995
00996     /* Process Locked */
00997     __HAL_LOCK(hsmartcard);
00998
00999     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01000     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
01001
01002     hsmartcard->pTxBuffPtr  = pData;
01003     hsmartcard->TxXferSize  = Size;
01004     hsmartcard->TxXferCount = Size;
01005     hsmartcard->TxISR       = NULL;
01006
01007     /* Disable the Peripheral first to update mode for TX master */
01008     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01009
01010     /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
01011        the bidirectional line to detect a NACK signal in case of parity error.
01012        Therefore, the receiver block must be enabled as well (RE bit must be set). */
01013     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
01014         && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
01015     {
01016       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
01017     }
01018     /* Enable Tx */
01019     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
01020
01021     /* Enable the Peripheral */
01022     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01023
01024     /* Perform a TX/RX FIFO Flush */
01025     __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
01026
01027     /* Configure Tx interrupt processing */
01028     if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
01029     {
01030       /* Set the Tx ISR function pointer */
01031       hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN;
01032
01033       /* Process Unlocked */
01034       __HAL_UNLOCK(hsmartcard);
01035
01036       /* Enable the SMARTCARD Error Interrupt: (Frame error) */
01037       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01038
01039       /* Enable the TX FIFO threshold interrupt */
01040       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01041     }
01042     else
01043     {
01044       /* Set the Tx ISR function pointer */
01045       hsmartcard->TxISR = SMARTCARD_TxISR;
01046
01047       /* Process Unlocked */
01048       __HAL_UNLOCK(hsmartcard);
01049
01050       /* Enable the SMARTCARD Error Interrupt: (Frame error) */
01051       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01052
01053       /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
01054       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01055     }
01056
01057     return HAL_OK;
01058   }
01059   else
01060   {
01061     return HAL_BUSY;
01062   }
01063 }
01064
01065 /**
01066   * @brief  Receive an amount of data in interrupt mode.
01067   * @note   When FIFO mode is disabled, USART interrupt is generated whenever
01068   *         USART_RDR register can be read, i.e one interrupt per data to receive.
01069   * @note   When FIFO mode is enabled, USART interrupt is generated whenever
01070   *         RXFIFO threshold reached. In that case the interrupt rate depends on
01071   *         RXFIFO threshold configuration.
01072   * @note   This function sets the hsmartcard->RxIsr function pointer according to
01073   *         the FIFO mode (data reception processing depends on FIFO mode).
01074   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01075   *                    the configuration information for the specified SMARTCARD module.
01076   * @param  pData pointer to data buffer.
01077   * @param  Size amount of data to be received.
01078   * @retval HAL status
01079   */
01080 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01081 {
01082   /* Check that a Rx process is not already ongoing */
01083   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01084   {
01085     if ((pData == NULL) || (Size == 0U))
01086     {
01087       return HAL_ERROR;
01088     }
01089
01090     /* Process Locked */
01091     __HAL_LOCK(hsmartcard);
01092
01093     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01094     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
01095
01096     hsmartcard->pRxBuffPtr = pData;
01097     hsmartcard->RxXferSize = Size;
01098     hsmartcard->RxXferCount = Size;
01099
01100     /* Configure Rx interrupt processing */
01101     if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess))
01102     {
01103       /* Set the Rx ISR function pointer */
01104       hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN;
01105
01106       /* Process Unlocked */
01107       __HAL_UNLOCK(hsmartcard);
01108
01109       /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */
01110       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01111       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
01112     }
01113     else
01114     {
01115       /* Set the Rx ISR function pointer */
01116       hsmartcard->RxISR = SMARTCARD_RxISR;
01117
01118       /* Process Unlocked */
01119       __HAL_UNLOCK(hsmartcard);
01120
01121       /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
01122       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01123     }
01124
01125     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01126     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01127
01128     return HAL_OK;
01129   }
01130   else
01131   {
01132     return HAL_BUSY;
01133   }
01134 }
01135
01136 /**
01137   * @brief  Send an amount of data in DMA mode.
01138   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01139   *                    the configuration information for the specified SMARTCARD module.
01140   * @param  pData pointer to data buffer.
01141   * @param  Size amount of data to be sent.
01142   * @retval HAL status
01143   */
01144 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
01145 {
01146   /* Check that a Tx process is not already ongoing */
01147   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01148   {
01149     if ((pData == NULL) || (Size == 0U))
01150     {
01151       return HAL_ERROR;
01152     }
01153
01154     /* Process Locked */
01155     __HAL_LOCK(hsmartcard);
01156
01157     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
01158
01159     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01160     hsmartcard->pTxBuffPtr = pData;
01161     hsmartcard->TxXferSize = Size;
01162     hsmartcard->TxXferCount = Size;
01163
01164     /* Disable the Peripheral first to update mode for TX master */
01165     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01166
01167     /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
01168        the bidirectional line to detect a NACK signal in case of parity error.
01169        Therefore, the receiver block must be enabled as well (RE bit must be set). */
01170     if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
01171         && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
01172     {
01173       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
01174     }
01175     /* Enable Tx */
01176     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
01177
01178     /* Enable the Peripheral */
01179     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01180
01181     /* Perform a TX/RX FIFO Flush */
01182     __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
01183
01184     /* Set the SMARTCARD DMA transfer complete callback */
01185     hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
01186
01187     /* Set the SMARTCARD error callback */
01188     hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
01189
01190     /* Set the DMA abort callback */
01191     hsmartcard->hdmatx->XferAbortCallback = NULL;
01192
01193     /* Enable the SMARTCARD transmit DMA channel */
01194     if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
01195                          Size) == HAL_OK)
01196     {
01197       /* Clear the TC flag in the ICR register */
01198       CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
01199
01200       /* Process Unlocked */
01201       __HAL_UNLOCK(hsmartcard);
01202
01203       /* Enable the UART Error Interrupt: (Frame error) */
01204       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01205
01206       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01207          in the SMARTCARD associated USART CR3 register */
01208       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01209
01210       return HAL_OK;
01211     }
01212     else
01213     {
01214       /* Set error code to DMA */
01215       hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01216
01217       /* Process Unlocked */
01218       __HAL_UNLOCK(hsmartcard);
01219
01220       /* Restore hsmartcard->State to ready */
01221       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01222
01223       return HAL_ERROR;
01224     }
01225   }
01226   else
01227   {
01228     return HAL_BUSY;
01229   }
01230 }
01231
01232 /**
01233   * @brief  Receive an amount of data in DMA mode.
01234   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01235   *                    the configuration information for the specified SMARTCARD module.
01236   * @param  pData pointer to data buffer.
01237   * @param  Size amount of data to be received.
01238   * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
01239   *         the received data contain the parity bit (MSB position).
01240   * @retval HAL status
01241   */
01242 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01243 {
01244   /* Check that a Rx process is not already ongoing */
01245   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01246   {
01247     if ((pData == NULL) || (Size == 0U))
01248     {
01249       return HAL_ERROR;
01250     }
01251
01252     /* Process Locked */
01253     __HAL_LOCK(hsmartcard);
01254
01255     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01256     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
01257
01258     hsmartcard->pRxBuffPtr = pData;
01259     hsmartcard->RxXferSize = Size;
01260
01261     /* Set the SMARTCARD DMA transfer complete callback */
01262     hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
01263
01264     /* Set the SMARTCARD DMA error callback */
01265     hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
01266
01267     /* Set the DMA abort callback */
01268     hsmartcard->hdmarx->XferAbortCallback = NULL;
01269
01270     /* Enable the DMA channel */
01271     if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
01272                          Size) == HAL_OK)
01273     {
01274       /* Process Unlocked */
01275       __HAL_UNLOCK(hsmartcard);
01276
01277       /* Enable the SMARTCARD Parity Error Interrupt */
01278       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01279
01280       /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01281       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01282
01283       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01284          in the SMARTCARD associated USART CR3 register */
01285       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01286
01287       return HAL_OK;
01288     }
01289     else
01290     {
01291       /* Set error code to DMA */
01292       hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01293
01294       /* Process Unlocked */
01295       __HAL_UNLOCK(hsmartcard);
01296
01297       /* Restore hsmartcard->State to ready */
01298       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01299
01300       return HAL_ERROR;
01301     }
01302   }
01303   else
01304   {
01305     return HAL_BUSY;
01306   }
01307 }
01308
01309 /**
01310   * @brief  Abort ongoing transfers (blocking mode).
01311   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01312   *                    the configuration information for the specified SMARTCARD module.
01313   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01314   *         This procedure performs following operations :
01315   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01316   *           - Disable the DMA transfer in the peripheral register (if enabled)
01317   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01318   *           - Set handle State to READY
01319   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01320   * @retval HAL status
01321   */
01322 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
01323 {
01324   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
01325      ERR (Frame error, noise error, overrun error) interrupts */
01326   CLEAR_BIT(hsmartcard->Instance->CR1,
01327             (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
01328              USART_CR1_EOBIE));
01329   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01330
01331   /* Disable the SMARTCARD DMA Tx request if enabled */
01332   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01333   {
01334     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01335
01336     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01337     if (hsmartcard->hdmatx != NULL)
01338     {
01339       /* Set the SMARTCARD DMA Abort callback to Null.
01340          No call back execution at end of DMA abort procedure */
01341       hsmartcard->hdmatx->XferAbortCallback = NULL;
01342
01343       if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
01344       {
01345         if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01346         {
01347           /* Set error code to DMA */
01348           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01349
01350           return HAL_TIMEOUT;
01351         }
01352       }
01353     }
01354   }
01355
01356   /* Disable the SMARTCARD DMA Rx request if enabled */
01357   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01358   {
01359     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01360
01361     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01362     if (hsmartcard->hdmarx != NULL)
01363     {
01364       /* Set the SMARTCARD DMA Abort callback to Null.
01365          No call back execution at end of DMA abort procedure */
01366       hsmartcard->hdmarx->XferAbortCallback = NULL;
01367
01368       if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
01369       {
01370         if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01371         {
01372           /* Set error code to DMA */
01373           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01374
01375           return HAL_TIMEOUT;
01376         }
01377       }
01378     }
01379   }
01380
01381   /* Reset Tx and Rx transfer counters */
01382   hsmartcard->TxXferCount = 0U;
01383   hsmartcard->RxXferCount = 0U;
01384
01385   /* Clear the Error flags in the ICR register */
01386   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01387                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
01388                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01389
01390   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01391   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01392   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01393
01394   /* Reset Handle ErrorCode to No Error */
01395   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01396
01397   return HAL_OK;
01398 }
01399
01400 /**
01401   * @brief  Abort ongoing Transmit transfer (blocking mode).
01402   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01403   *                    the configuration information for the specified SMARTCARD module.
01404   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01405   *         This procedure performs following operations :
01406   *           - Disable SMARTCARD Interrupts (Tx)
01407   *           - Disable the DMA transfer in the peripheral register (if enabled)
01408   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01409   *           - Set handle State to READY
01410   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01411   * @retval HAL status
01412   */
01413 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
01414 {
01415   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01416   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01417   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01418
01419   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01420   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01421   {
01422     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01423     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01424   }
01425
01426   /* Disable the SMARTCARD DMA Tx request if enabled */
01427   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01428   {
01429     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01430
01431     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01432     if (hsmartcard->hdmatx != NULL)
01433     {
01434       /* Set the SMARTCARD DMA Abort callback to Null.
01435          No call back execution at end of DMA abort procedure */
01436       hsmartcard->hdmatx->XferAbortCallback = NULL;
01437
01438       if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
01439       {
01440         if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01441         {
01442           /* Set error code to DMA */
01443           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01444
01445           return HAL_TIMEOUT;
01446         }
01447       }
01448     }
01449   }
01450
01451   /* Reset Tx transfer counter */
01452   hsmartcard->TxXferCount = 0U;
01453
01454   /* Clear the Error flags in the ICR register */
01455   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01456
01457   /* Restore hsmartcard->gState to Ready */
01458   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01459
01460   return HAL_OK;
01461 }
01462
01463 /**
01464   * @brief  Abort ongoing Receive transfer (blocking mode).
01465   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01466   *                    the configuration information for the specified SMARTCARD module.
01467   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01468   *         This procedure performs following operations :
01469   *           - Disable SMARTCARD Interrupts (Rx)
01470   *           - Disable the DMA transfer in the peripheral register (if enabled)
01471   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01472   *           - Set handle State to READY
01473   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01474   * @retval HAL status
01475   */
01476 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
01477 {
01478   /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01479   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
01480                                         USART_CR1_EOBIE));
01481   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01482
01483   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01484   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01485   {
01486     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01487     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01488   }
01489
01490   /* Disable the SMARTCARD DMA Rx request if enabled */
01491   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01492   {
01493     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01494
01495     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01496     if (hsmartcard->hdmarx != NULL)
01497     {
01498       /* Set the SMARTCARD DMA Abort callback to Null.
01499          No call back execution at end of DMA abort procedure */
01500       hsmartcard->hdmarx->XferAbortCallback = NULL;
01501
01502       if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
01503       {
01504         if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01505         {
01506           /* Set error code to DMA */
01507           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01508
01509           return HAL_TIMEOUT;
01510         }
01511       }
01512     }
01513   }
01514
01515   /* Reset Rx transfer counter */
01516   hsmartcard->RxXferCount = 0U;
01517
01518   /* Clear the Error flags in the ICR register */
01519   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01520                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
01521                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01522
01523   /* Restore hsmartcard->RxState to Ready */
01524   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01525
01526   return HAL_OK;
01527 }
01528
01529 /**
01530   * @brief  Abort ongoing transfers (Interrupt mode).
01531   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01532   *                    the configuration information for the specified SMARTCARD module.
01533   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01534   *         This procedure performs following operations :
01535   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01536   *           - Disable the DMA transfer in the peripheral register (if enabled)
01537   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01538   *           - Set handle State to READY
01539   *           - At abort completion, call user abort complete callback
01540   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01541   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01542   * @retval HAL status
01543   */
01544 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01545 {
01546   uint32_t abortcplt = 1U;
01547
01548   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
01549      ERR (Frame error, noise error, overrun error) interrupts */
01550   CLEAR_BIT(hsmartcard->Instance->CR1,
01551             (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
01552              USART_CR1_EOBIE));
01553   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01554
01555   /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
01556      DMA Abort complete callbacks should be initialised before any call
01557      to DMA Abort functions */
01558   /* DMA Tx Handle is valid */
01559   if (hsmartcard->hdmatx != NULL)
01560   {
01561     /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
01562        Otherwise, set it to NULL */
01563     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01564     {
01565       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
01566     }
01567     else
01568     {
01569       hsmartcard->hdmatx->XferAbortCallback = NULL;
01570     }
01571   }
01572   /* DMA Rx Handle is valid */
01573   if (hsmartcard->hdmarx != NULL)
01574   {
01575     /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
01576        Otherwise, set it to NULL */
01577     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01578     {
01579       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
01580     }
01581     else
01582     {
01583       hsmartcard->hdmarx->XferAbortCallback = NULL;
01584     }
01585   }
01586
01587   /* Disable the SMARTCARD DMA Tx request if enabled */
01588   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01589   {
01590     /* Disable DMA Tx at UART level */
01591     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01592
01593     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01594     if (hsmartcard->hdmatx != NULL)
01595     {
01596       /* SMARTCARD Tx DMA Abort callback has already been initialised :
01597          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01598
01599       /* Abort DMA TX */
01600       if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01601       {
01602         hsmartcard->hdmatx->XferAbortCallback = NULL;
01603       }
01604       else
01605       {
01606         abortcplt = 0U;
01607       }
01608     }
01609   }
01610
01611   /* Disable the SMARTCARD DMA Rx request if enabled */
01612   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01613   {
01614     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01615
01616     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01617     if (hsmartcard->hdmarx != NULL)
01618     {
01619       /* SMARTCARD Rx DMA Abort callback has already been initialised :
01620          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01621
01622       /* Abort DMA RX */
01623       if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01624       {
01625         hsmartcard->hdmarx->XferAbortCallback = NULL;
01626         abortcplt = 1U;
01627       }
01628       else
01629       {
01630         abortcplt = 0U;
01631       }
01632     }
01633   }
01634
01635   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01636   if (abortcplt == 1U)
01637   {
01638     /* Reset Tx and Rx transfer counters */
01639     hsmartcard->TxXferCount = 0U;
01640     hsmartcard->RxXferCount = 0U;
01641
01642     /* Clear ISR function pointers */
01643     hsmartcard->RxISR = NULL;
01644     hsmartcard->TxISR = NULL;
01645
01646     /* Reset errorCode */
01647     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01648
01649     /* Clear the Error flags in the ICR register */
01650     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01651                                SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
01652                                SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01653
01654     /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01655     hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01656     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01657
01658     /* As no DMA to be aborted, call directly user Abort complete callback */
01659 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01660     /* Call registered Abort complete callback */
01661     hsmartcard->AbortCpltCallback(hsmartcard);
01662 #else
01663     /* Call legacy weak Abort complete callback */
01664     HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
01665 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01666   }
01667
01668   return HAL_OK;
01669 }
01670
01671 /**
01672   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01673   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01674   *                    the configuration information for the specified SMARTCARD module.
01675   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01676   *         This procedure performs following operations :
01677   *           - Disable SMARTCARD Interrupts (Tx)
01678   *           - Disable the DMA transfer in the peripheral register (if enabled)
01679   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01680   *           - Set handle State to READY
01681   *           - At abort completion, call user abort complete callback
01682   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01683   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01684   * @retval HAL status
01685   */
01686 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01687 {
01688   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01689   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01690   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01691
01692   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01693   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01694   {
01695     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01696     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01697   }
01698
01699   /* Disable the SMARTCARD DMA Tx request if enabled */
01700   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01701   {
01702     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01703
01704     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01705     if (hsmartcard->hdmatx != NULL)
01706     {
01707       /* Set the SMARTCARD DMA Abort callback :
01708          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01709       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
01710
01711       /* Abort DMA TX */
01712       if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01713       {
01714         /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01715         hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01716       }
01717     }
01718     else
01719     {
01720       /* Reset Tx transfer counter */
01721       hsmartcard->TxXferCount = 0U;
01722
01723       /* Clear TxISR function pointers */
01724       hsmartcard->TxISR = NULL;
01725
01726       /* Restore hsmartcard->gState to Ready */
01727       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01728
01729       /* As no DMA to be aborted, call directly user Abort complete callback */
01730 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01731       /* Call registered Abort Transmit Complete Callback */
01732       hsmartcard->AbortTransmitCpltCallback(hsmartcard);
01733 #else
01734       /* Call legacy weak Abort Transmit Complete Callback */
01735       HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01736 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01737     }
01738   }
01739   else
01740   {
01741     /* Reset Tx transfer counter */
01742     hsmartcard->TxXferCount = 0U;
01743
01744     /* Clear TxISR function pointers */
01745     hsmartcard->TxISR = NULL;
01746
01747     /* Clear the Error flags in the ICR register */
01748     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01749
01750     /* Restore hsmartcard->gState to Ready */
01751     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01752
01753     /* As no DMA to be aborted, call directly user Abort complete callback */
01754 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01755     /* Call registered Abort Transmit Complete Callback */
01756     hsmartcard->AbortTransmitCpltCallback(hsmartcard);
01757 #else
01758     /* Call legacy weak Abort Transmit Complete Callback */
01759     HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01760 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01761   }
01762
01763   return HAL_OK;
01764 }
01765
01766 /**
01767   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01768   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01769   *                    the configuration information for the specified SMARTCARD module.
01770   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01771   *         This procedure performs following operations :
01772   *           - Disable SMARTCARD Interrupts (Rx)
01773   *           - Disable the DMA transfer in the peripheral register (if enabled)
01774   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01775   *           - Set handle State to READY
01776   *           - At abort completion, call user abort complete callback
01777   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01778   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01779   * @retval HAL status
01780   */
01781 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01782 {
01783   /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01784   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
01785                                         USART_CR1_EOBIE));
01786   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01787
01788   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01789   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01790   {
01791     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01792     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01793   }
01794
01795   /* Disable the SMARTCARD DMA Rx request if enabled */
01796   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01797   {
01798     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01799
01800     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01801     if (hsmartcard->hdmarx != NULL)
01802     {
01803       /* Set the SMARTCARD DMA Abort callback :
01804          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01805       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
01806
01807       /* Abort DMA RX */
01808       if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01809       {
01810         /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01811         hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01812       }
01813     }
01814     else
01815     {
01816       /* Reset Rx transfer counter */
01817       hsmartcard->RxXferCount = 0U;
01818
01819       /* Clear RxISR function pointer */
01820       hsmartcard->RxISR = NULL;
01821
01822       /* Clear the Error flags in the ICR register */
01823       __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01824                                  SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
01825                                  SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01826
01827       /* Restore hsmartcard->RxState to Ready */
01828       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01829
01830       /* As no DMA to be aborted, call directly user Abort complete callback */
01831 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01832       /* Call registered Abort Receive Complete Callback */
01833       hsmartcard->AbortReceiveCpltCallback(hsmartcard);
01834 #else
01835       /* Call legacy weak Abort Receive Complete Callback */
01836       HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01837 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01838     }
01839   }
01840   else
01841   {
01842     /* Reset Rx transfer counter */
01843     hsmartcard->RxXferCount = 0U;
01844
01845     /* Clear RxISR function pointer */
01846     hsmartcard->RxISR = NULL;
01847
01848     /* Clear the Error flags in the ICR register */
01849     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
01850                                SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
01851                                SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01852
01853     /* Restore hsmartcard->RxState to Ready */
01854     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01855
01856     /* As no DMA to be aborted, call directly user Abort complete callback */
01857 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01858     /* Call registered Abort Receive Complete Callback */
01859     hsmartcard->AbortReceiveCpltCallback(hsmartcard);
01860 #else
01861     /* Call legacy weak Abort Receive Complete Callback */
01862     HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01863 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01864   }
01865
01866   return HAL_OK;
01867 }
01868
01869 /**
01870   * @brief  Handle SMARTCARD interrupt requests.
01871   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01872   *                    the configuration information for the specified SMARTCARD module.
01873   * @retval None
01874   */
01875 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
01876 {
01877   uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
01878   uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
01879   uint32_t cr3its     = READ_REG(hsmartcard->Instance->CR3);
01880   uint32_t errorflags;
01881   uint32_t errorcode;
01882
01883   /* If no error occurs */
01884   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
01885   if (errorflags == 0U)
01886   {
01887     /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01888     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
01889         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01890             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
01891     {
01892       if (hsmartcard->RxISR != NULL)
01893       {
01894         hsmartcard->RxISR(hsmartcard);
01895       }
01896       return;
01897     }
01898   }
01899
01900   /* If some errors occur */
01901   if ((errorflags != 0U)
01902       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
01903            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
01904   {
01905     /* SMARTCARD parity error interrupt occurred -------------------------------------*/
01906     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
01907     {
01908       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
01909
01910       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
01911     }
01912
01913     /* SMARTCARD frame error interrupt occurred --------------------------------------*/
01914     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01915     {
01916       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
01917
01918       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
01919     }
01920
01921     /* SMARTCARD noise error interrupt occurred --------------------------------------*/
01922     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01923     {
01924       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
01925
01926       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
01927     }
01928
01929     /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
01930     if (((isrflags & USART_ISR_ORE) != 0U)
01931         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01932             || ((cr3its & USART_CR3_RXFTIE) != 0U)
01933             || ((cr3its & USART_CR3_EIE) != 0U)))
01934     {
01935       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
01936
01937       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
01938     }
01939
01940     /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
01941     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
01942     {
01943       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
01944
01945       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
01946     }
01947
01948     /* Call SMARTCARD Error Call back function if need be --------------------------*/
01949     if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
01950     {
01951       /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01952       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
01953           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01954               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
01955       {
01956         if (hsmartcard->RxISR != NULL)
01957         {
01958           hsmartcard->RxISR(hsmartcard);
01959         }
01960       }
01961
01962       /* If Error is to be considered as blocking :
01963           - Receiver Timeout error in Reception
01964           - Overrun error in Reception
01965           - any error occurs in DMA mode reception
01966       */
01967       errorcode = hsmartcard->ErrorCode;
01968       if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01969           || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
01970       {
01971         /* Blocking error : transfer is aborted
01972            Set the SMARTCARD state ready to be able to start again the process,
01973            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01974         SMARTCARD_EndRxTransfer(hsmartcard);
01975
01976         /* Disable the SMARTCARD DMA Rx request if enabled */
01977         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01978         {
01979           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01980
01981           /* Abort the SMARTCARD DMA Rx channel */
01982           if (hsmartcard->hdmarx != NULL)
01983           {
01984             /* Set the SMARTCARD DMA Abort callback :
01985                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01986             hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01987
01988             /* Abort DMA RX */
01989             if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01990             {
01991               /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01992               hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01993             }
01994           }
01995           else
01996           {
01997 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01998             /* Call registered user error callback */
01999             hsmartcard->ErrorCallback(hsmartcard);
02000 #else
02001             /* Call legacy weak user error callback */
02002             HAL_SMARTCARD_ErrorCallback(hsmartcard);
02003 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02004           }
02005         }
02006         else
02007         {
02008 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02009           /* Call registered user error callback */
02010           hsmartcard->ErrorCallback(hsmartcard);
02011 #else
02012           /* Call legacy weak user error callback */
02013           HAL_SMARTCARD_ErrorCallback(hsmartcard);
02014 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02015         }
02016       }
02017       /* other error type to be considered as blocking :
02018           - Frame error in Transmission
02019       */
02020       else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02021                && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
02022       {
02023         /* Blocking error : transfer is aborted
02024            Set the SMARTCARD state ready to be able to start again the process,
02025            Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
02026         SMARTCARD_EndTxTransfer(hsmartcard);
02027
02028         /* Disable the SMARTCARD DMA Tx request if enabled */
02029         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
02030         {
02031           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
02032
02033           /* Abort the SMARTCARD DMA Tx channel */
02034           if (hsmartcard->hdmatx != NULL)
02035           {
02036             /* Set the SMARTCARD DMA Abort callback :
02037                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
02038             hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
02039
02040             /* Abort DMA TX */
02041             if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
02042             {
02043               /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
02044               hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
02045             }
02046           }
02047           else
02048           {
02049 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02050             /* Call registered user error callback */
02051             hsmartcard->ErrorCallback(hsmartcard);
02052 #else
02053             /* Call legacy weak user error callback */
02054             HAL_SMARTCARD_ErrorCallback(hsmartcard);
02055 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02056           }
02057         }
02058         else
02059         {
02060 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02061           /* Call registered user error callback */
02062           hsmartcard->ErrorCallback(hsmartcard);
02063 #else
02064           /* Call legacy weak user error callback */
02065           HAL_SMARTCARD_ErrorCallback(hsmartcard);
02066 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02067         }
02068       }
02069       else
02070       {
02071         /* Non Blocking error : transfer could go on.
02072            Error is notified to user through user error callback */
02073 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02074         /* Call registered user error callback */
02075         hsmartcard->ErrorCallback(hsmartcard);
02076 #else
02077         /* Call legacy weak user error callback */
02078         HAL_SMARTCARD_ErrorCallback(hsmartcard);
02079 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02080         hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02081       }
02082     }
02083     return;
02084
02085   } /* End if some error occurs */
02086
02087   /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
02088   if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
02089   {
02090     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02091     __HAL_UNLOCK(hsmartcard);
02092 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02093     /* Call registered Rx complete callback */
02094     hsmartcard->RxCpltCallback(hsmartcard);
02095 #else
02096     /* Call legacy weak Rx complete callback */
02097     HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02098 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02099     /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
02100        to be available during HAL_SMARTCARD_RxCpltCallback() processing */
02101     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
02102     return;
02103   }
02104
02105   /* SMARTCARD in mode Transmitter ------------------------------------------------*/
02106   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02107       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02108           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02109   {
02110     if (hsmartcard->TxISR != NULL)
02111     {
02112       hsmartcard->TxISR(hsmartcard);
02113     }
02114     return;
02115   }
02116
02117   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
02118   if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
02119   {
02120     if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
02121     {
02122       SMARTCARD_EndTransmit_IT(hsmartcard);
02123       return;
02124     }
02125   }
02126
02127   /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/
02128   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02129   {
02130 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02131     /* Call registered Tx Fifo Empty Callback */
02132     hsmartcard->TxFifoEmptyCallback(hsmartcard);
02133 #else
02134     /* Call legacy weak Tx Fifo Empty Callback */
02135     HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard);
02136 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02137     return;
02138   }
02139
02140   /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/
02141   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02142   {
02143 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02144     /* Call registered Rx Fifo Full Callback */
02145     hsmartcard->RxFifoFullCallback(hsmartcard);
02146 #else
02147     /* Call legacy weak Rx Fifo Full Callback */
02148     HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard);
02149 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02150     return;
02151   }
02152 }
02153
02154 /**
02155   * @brief  Tx Transfer completed callback.
02156   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02157   *                    the configuration information for the specified SMARTCARD module.
02158   * @retval None
02159   */
02160 __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02161 {
02162   /* Prevent unused argument(s) compilation warning */
02163   UNUSED(hsmartcard);
02164
02165   /* NOTE : This function should not be modified, when the callback is needed,
02166             the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
02167    */
02168 }
02169
02170 /**
02171   * @brief  Rx Transfer completed callback.
02172   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02173   *                    the configuration information for the specified SMARTCARD module.
02174   * @retval None
02175   */
02176 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02177 {
02178   /* Prevent unused argument(s) compilation warning */
02179   UNUSED(hsmartcard);
02180
02181   /* NOTE : This function should not be modified, when the callback is needed,
02182             the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
02183    */
02184 }
02185
02186 /**
02187   * @brief  SMARTCARD error callback.
02188   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02189   *                    the configuration information for the specified SMARTCARD module.
02190   * @retval None
02191   */
02192 __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02193 {
02194   /* Prevent unused argument(s) compilation warning */
02195   UNUSED(hsmartcard);
02196
02197   /* NOTE : This function should not be modified, when the callback is needed,
02198             the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
02199    */
02200 }
02201
02202 /**
02203   * @brief  SMARTCARD Abort Complete callback.
02204   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02205   *                    the configuration information for the specified SMARTCARD module.
02206   * @retval None
02207   */
02208 __weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02209 {
02210   /* Prevent unused argument(s) compilation warning */
02211   UNUSED(hsmartcard);
02212
02213   /* NOTE : This function should not be modified, when the callback is needed,
02214             the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
02215    */
02216 }
02217
02218 /**
02219   * @brief  SMARTCARD Abort Complete callback.
02220   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02221   *                    the configuration information for the specified SMARTCARD module.
02222   * @retval None
02223   */
02224 __weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02225 {
02226   /* Prevent unused argument(s) compilation warning */
02227   UNUSED(hsmartcard);
02228
02229   /* NOTE : This function should not be modified, when the callback is needed,
02230             the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
02231    */
02232 }
02233
02234 /**
02235   * @brief  SMARTCARD Abort Receive Complete callback.
02236   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02237   *                    the configuration information for the specified SMARTCARD module.
02238   * @retval None
02239   */
02240 __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02241 {
02242   /* Prevent unused argument(s) compilation warning */
02243   UNUSED(hsmartcard);
02244
02245   /* NOTE : This function should not be modified, when the callback is needed,
02246             the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
02247    */
02248 }
02249
02250 /**
02251   * @}
02252   */
02253
02254 /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
02255   * @brief    SMARTCARD State and Errors functions
02256   *
02257 @verbatim
02258   ==============================================================================
02259                   ##### Peripheral State and Errors functions #####
02260   ==============================================================================
02261   [..]
02262     This subsection provides a set of functions allowing to return the State of SmartCard
02263     handle and also return Peripheral Errors occurred during communication process
02264      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
02265          of the SMARTCARD peripheral.
02266      (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
02267          communication.
02268
02269 @endverbatim
02270   * @{
02271   */
02272
02273 /**
02274   * @brief  Return the SMARTCARD handle state.
02275   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02276   *                    the configuration information for the specified SMARTCARD module.
02277   * @retval SMARTCARD handle state
02278   */
02279 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard)
02280 {
02281   /* Return SMARTCARD handle state */
02282   uint32_t temp1;
02283   uint32_t temp2;
02284   temp1 = (uint32_t)hsmartcard->gState;
02285   temp2 = (uint32_t)hsmartcard->RxState;
02286
02287   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
02288 }
02289
02290 /**
02291   * @brief  Return the SMARTCARD handle error code.
02292   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02293   *                    the configuration information for the specified SMARTCARD module.
02294   * @retval SMARTCARD handle Error Code
02295   */
02296 uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard)
02297 {
02298   return hsmartcard->ErrorCode;
02299 }
02300
02301 /**
02302   * @}
02303   */
02304
02305 /**
02306   * @}
02307   */
02308
02309 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
02310   * @{
02311   */
02312
02313 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02314 /**
02315   * @brief  Initialize the callbacks to their default values.
02316   * @param  hsmartcard SMARTCARD handle.
02317   * @retval none
02318   */
02319 void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
02320 {
02321   /* Init the SMARTCARD Callback settings */
02322   hsmartcard->TxCpltCallback            = HAL_SMARTCARD_TxCpltCallback;            /* Legacy weak TxCpltCallback    */
02323   hsmartcard->RxCpltCallback            = HAL_SMARTCARD_RxCpltCallback;            /* Legacy weak RxCpltCallback    */
02324   hsmartcard->ErrorCallback             = HAL_SMARTCARD_ErrorCallback;             /* Legacy weak ErrorCallback     */
02325   hsmartcard->AbortCpltCallback         = HAL_SMARTCARD_AbortCpltCallback;         /* Legacy weak AbortCpltCallback */
02326   hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
02327                                                                                       AbortTransmitCpltCallback     */
02328   hsmartcard->AbortReceiveCpltCallback  = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak
02329                                                                                       AbortReceiveCpltCallback      */
02330   hsmartcard->RxFifoFullCallback        = HAL_SMARTCARDEx_RxFifoFullCallback;      /* Legacy weak
02331                                                                                       RxFifoFullCallback            */
02332   hsmartcard->TxFifoEmptyCallback       = HAL_SMARTCARDEx_TxFifoEmptyCallback;     /* Legacy weak
02333                                                                                       TxFifoEmptyCallback           */
02334
02335 }
02336 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
02337
02338 /**
02339   * @brief  Configure the SMARTCARD associated USART peripheral.
02340   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02341   *                    the configuration information for the specified SMARTCARD module.
02342   * @retval HAL status
02343   */
02344 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
02345 {
02346   uint32_t tmpreg;
02347   SMARTCARD_ClockSourceTypeDef clocksource;
02348   HAL_StatusTypeDef ret = HAL_OK;
02349   static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
02350   uint32_t pclk;
02351
02352   /* Check the parameters */
02353   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
02354   assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
02355   assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
02356   assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
02357   assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
02358   assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
02359   assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
02360   assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
02361   assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
02362   assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
02363   assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
02364   assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
02365   assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
02366   assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler));
02367
02368   /*-------------------------- USART CR1 Configuration -----------------------*/
02369   /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
02370    * Oversampling is forced to 16 (OVER8 = 0).
02371    * Configure the Parity and Mode:
02372    *  set PS bit according to hsmartcard->Init.Parity value
02373    *  set TE and RE bits according to hsmartcard->Init.Mode value */
02374   tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
02375             ((uint32_t)hsmartcard->Init.WordLength));
02376   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02377
02378   /*-------------------------- USART CR2 Configuration -----------------------*/
02379   tmpreg = hsmartcard->Init.StopBits;
02380   /* Synchronous mode is activated by default */
02381   tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
02382   tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
02383   tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
02384   MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02385
02386   /*-------------------------- USART CR3 Configuration -----------------------*/
02387   /* Configure
02388    * - one-bit sampling method versus three samples' majority rule
02389    *   according to hsmartcard->Init.OneBitSampling
02390    * - NACK transmission in case of parity error according
02391    *   to hsmartcard->Init.NACKEnable
02392    * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
02393
02394   tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
02395   tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
02396   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
02397
02398   /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/
02399   /* Configure
02400   * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */
02401   MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler);
02402
02403   /*-------------------------- USART GTPR Configuration ----------------------*/
02404   tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
02405   MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
02406
02407   /*-------------------------- USART RTOR Configuration ----------------------*/
02408   tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
02409   if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
02410   {
02411     assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
02412     tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
02413   }
02414   MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
02415
02416   /*-------------------------- USART BRR Configuration -----------------------*/
02417   SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
02418   tmpreg =   0U;
02419   switch (clocksource)
02420   {
02421     case SMARTCARD_CLOCKSOURCE_PCLK1:
02422       pclk = HAL_RCC_GetPCLK1Freq();
02423       tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02424                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02425       break;
02426     case SMARTCARD_CLOCKSOURCE_HSI:
02427       tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02428                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02429       break;
02430     case SMARTCARD_CLOCKSOURCE_SYSCLK:
02431       pclk = HAL_RCC_GetSysClockFreq();
02432       tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02433                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02434       break;
02435     case SMARTCARD_CLOCKSOURCE_LSE:
02436       tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
02437                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02438       break;
02439     default:
02440       ret = HAL_ERROR;
02441       break;
02442   }
02443
02444   /* USARTDIV must be greater than or equal to 0d16 */
02445   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
02446   {
02447     hsmartcard->Instance->BRR = (uint16_t)tmpreg;
02448   }
02449   else
02450   {
02451     ret = HAL_ERROR;
02452   }
02453
02454   /* Initialize the number of data to process during RX/TX ISR execution */
02455   hsmartcard->NbTxDataToProcess = 1U;
02456   hsmartcard->NbRxDataToProcess = 1U;
02457
02458   /* Clear ISR function pointers */
02459   hsmartcard->RxISR   = NULL;
02460   hsmartcard->TxISR   = NULL;
02461
02462   return ret;
02463 }
02464
02465
02466 /**
02467   * @brief Configure the SMARTCARD associated USART peripheral advanced features.
02468   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02469   *                   the configuration information for the specified SMARTCARD module.
02470   * @retval None
02471   */
02472 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
02473 {
02474   /* Check whether the set of advanced features to configure is properly set */
02475   assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
02476
02477   /* if required, configure TX pin active level inversion */
02478   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
02479   {
02480     assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
02481     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
02482   }
02483
02484   /* if required, configure RX pin active level inversion */
02485   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
02486   {
02487     assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
02488     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
02489   }
02490
02491   /* if required, configure data inversion */
02492   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
02493   {
02494     assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
02495     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
02496   }
02497
02498   /* if required, configure RX/TX pins swap */
02499   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
02500   {
02501     assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
02502     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
02503   }
02504
02505   /* if required, configure RX overrun detection disabling */
02506   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
02507   {
02508     assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
02509     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
02510   }
02511
02512   /* if required, configure DMA disabling on reception error */
02513   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
02514   {
02515     assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
02516     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
02517   }
02518
02519   /* if required, configure MSB first on communication line */
02520   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
02521   {
02522     assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
02523     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
02524   }
02525
02526 }
02527
02528 /**
02529   * @brief Check the SMARTCARD Idle State.
02530   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02531   *                   the configuration information for the specified SMARTCARD module.
02532   * @retval HAL status
02533   */
02534 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
02535 {
02536   uint32_t tickstart;
02537
02538   /* Initialize the SMARTCARD ErrorCode */
02539   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02540
02541   /* Init tickstart for timeout management */
02542   tickstart = HAL_GetTick();
02543
02544   /* Check if the Transmitter is enabled */
02545   if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02546   {
02547     /* Wait until TEACK flag is set */
02548     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
02549                                          SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
02550     {
02551       /* Timeout occurred */
02552       return HAL_TIMEOUT;
02553     }
02554   }
02555   /* Check if the Receiver is enabled */
02556   if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02557   {
02558     /* Wait until REACK flag is set */
02559     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
02560                                          SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
02561     {
02562       /* Timeout occurred */
02563       return HAL_TIMEOUT;
02564     }
02565   }
02566
02567   /* Initialize the SMARTCARD states */
02568   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02569   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02570
02571   /* Process Unlocked */
02572   __HAL_UNLOCK(hsmartcard);
02573
02574   return HAL_OK;
02575 }
02576
02577 /**
02578   * @brief  Handle SMARTCARD Communication Timeout. It waits
02579   *         until a flag is no longer in the specified status.
02580   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02581   *                   the configuration information for the specified SMARTCARD module.
02582   * @param  Flag Specifies the SMARTCARD flag to check.
02583   * @param  Status The actual Flag status (SET or RESET).
02584   * @param  Tickstart Tick start value
02585   * @param  Timeout Timeout duration.
02586   * @retval HAL status
02587   */
02588 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
02589                                                           FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02590 {
02591   /* Wait until flag is set */
02592   while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
02593   {
02594     /* Check for the Timeout */
02595     if (Timeout != HAL_MAX_DELAY)
02596     {
02597       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02598       {
02599         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
02600            interrupts for the interrupt process */
02601         CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
02602         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02603
02604         hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02605         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02606
02607         /* Process Unlocked */
02608         __HAL_UNLOCK(hsmartcard);
02609         return HAL_TIMEOUT;
02610       }
02611     }
02612   }
02613   return HAL_OK;
02614 }
02615
02616
02617 /**
02618   * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
02619   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02620   *                    the configuration information for the specified SMARTCARD module.
02621   * @retval None
02622   */
02623 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
02624 {
02625   /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
02626   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02627   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02628
02629   /* At end of Tx process, restore hsmartcard->gState to Ready */
02630   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02631 }
02632
02633
02634 /**
02635   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02636   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02637   *                    the configuration information for the specified SMARTCARD module.
02638   * @retval None
02639   */
02640 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
02641 {
02642   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02643   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02644   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02645
02646   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02647   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02648 }
02649
02650
02651 /**
02652   * @brief  DMA SMARTCARD transmit process complete callback.
02653   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02654   *              the configuration information for the specified DMA module.
02655   * @retval None
02656   */
02657 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02658 {
02659   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02660   hsmartcard->TxXferCount = 0U;
02661
02662   /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02663   in the SMARTCARD associated USART CR3 register */
02664   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
02665
02666   /* Enable the SMARTCARD Transmit Complete Interrupt */
02667   __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02668 }
02669
02670 /**
02671   * @brief  DMA SMARTCARD receive process complete callback.
02672   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02673   *              the configuration information for the specified DMA module.
02674   * @retval None
02675   */
02676 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02677 {
02678   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02679   hsmartcard->RxXferCount = 0U;
02680
02681   /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02682   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
02683   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02684
02685   /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02686      in the SMARTCARD associated USART CR3 register */
02687   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
02688
02689   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02690   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02691
02692 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02693   /* Call registered Rx complete callback */
02694   hsmartcard->RxCpltCallback(hsmartcard);
02695 #else
02696   /* Call legacy weak Rx complete callback */
02697   HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02698 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02699 }
02700
02701 /**
02702   * @brief  DMA SMARTCARD communication error callback.
02703   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02704   *              the configuration information for the specified DMA module.
02705   * @retval None
02706   */
02707 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
02708 {
02709   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02710
02711   /* Stop SMARTCARD DMA Tx request if ongoing */
02712   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02713   {
02714     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
02715     {
02716       hsmartcard->TxXferCount = 0U;
02717       SMARTCARD_EndTxTransfer(hsmartcard);
02718     }
02719   }
02720
02721   /* Stop SMARTCARD DMA Rx request if ongoing */
02722   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02723   {
02724     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
02725     {
02726       hsmartcard->RxXferCount = 0U;
02727       SMARTCARD_EndRxTransfer(hsmartcard);
02728     }
02729   }
02730
02731   hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
02732 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02733   /* Call registered user error callback */
02734   hsmartcard->ErrorCallback(hsmartcard);
02735 #else
02736   /* Call legacy weak user error callback */
02737   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02738 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02739 }
02740
02741 /**
02742   * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
02743   *         (To be called at end of DMA Abort procedure following error occurrence).
02744   * @param  hdma DMA handle.
02745   * @retval None
02746   */
02747 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02748 {
02749   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02750   hsmartcard->RxXferCount = 0U;
02751   hsmartcard->TxXferCount = 0U;
02752
02753 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02754   /* Call registered user error callback */
02755   hsmartcard->ErrorCallback(hsmartcard);
02756 #else
02757   /* Call legacy weak user error callback */
02758   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02759 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02760 }
02761
02762 /**
02763   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
02764   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02765   * @note   When this callback is executed, User Abort complete call back is called only if no
02766   *         Abort still ongoing for Rx DMA Handle.
02767   * @param  hdma DMA handle.
02768   * @retval None
02769   */
02770 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02771 {
02772   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02773
02774   hsmartcard->hdmatx->XferAbortCallback = NULL;
02775
02776   /* Check if an Abort process is still ongoing */
02777   if (hsmartcard->hdmarx != NULL)
02778   {
02779     if (hsmartcard->hdmarx->XferAbortCallback != NULL)
02780     {
02781       return;
02782     }
02783   }
02784
02785   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02786   hsmartcard->TxXferCount = 0U;
02787   hsmartcard->RxXferCount = 0U;
02788
02789   /* Reset errorCode */
02790   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02791
02792   /* Clear the Error flags in the ICR register */
02793   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02794                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
02795                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02796
02797   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02798   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02799   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02800
02801 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02802   /* Call registered Abort complete callback */
02803   hsmartcard->AbortCpltCallback(hsmartcard);
02804 #else
02805   /* Call legacy weak Abort complete callback */
02806   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02807 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02808 }
02809
02810
02811 /**
02812   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
02813   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02814   * @note   When this callback is executed, User Abort complete call back is called only if no
02815   *         Abort still ongoing for Tx DMA Handle.
02816   * @param  hdma DMA handle.
02817   * @retval None
02818   */
02819 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02820 {
02821   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02822
02823   hsmartcard->hdmarx->XferAbortCallback = NULL;
02824
02825   /* Check if an Abort process is still ongoing */
02826   if (hsmartcard->hdmatx != NULL)
02827   {
02828     if (hsmartcard->hdmatx->XferAbortCallback != NULL)
02829     {
02830       return;
02831     }
02832   }
02833
02834   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02835   hsmartcard->TxXferCount = 0U;
02836   hsmartcard->RxXferCount = 0U;
02837
02838   /* Reset errorCode */
02839   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02840
02841   /* Clear the Error flags in the ICR register */
02842   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02843                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
02844                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02845
02846   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02847   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02848   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02849
02850 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02851   /* Call registered Abort complete callback */
02852   hsmartcard->AbortCpltCallback(hsmartcard);
02853 #else
02854   /* Call legacy weak Abort complete callback */
02855   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02856 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02857 }
02858
02859
02860 /**
02861   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
02862   *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
02863   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02864   *         and leads to user Tx Abort Complete callback execution).
02865   * @param  hdma DMA handle.
02866   * @retval None
02867   */
02868 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02869 {
02870   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02871
02872   hsmartcard->TxXferCount = 0U;
02873
02874   /* Clear the Error flags in the ICR register */
02875   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
02876
02877   /* Restore hsmartcard->gState to Ready */
02878   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02879
02880 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02881   /* Call registered Abort Transmit Complete Callback */
02882   hsmartcard->AbortTransmitCpltCallback(hsmartcard);
02883 #else
02884   /* Call legacy weak Abort Transmit Complete Callback */
02885   HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
02886 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02887 }
02888
02889 /**
02890   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
02891   *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
02892   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02893   *         and leads to user Rx Abort Complete callback execution).
02894   * @param  hdma DMA handle.
02895   * @retval None
02896   */
02897 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02898 {
02899   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02900
02901   hsmartcard->RxXferCount = 0U;
02902
02903   /* Clear the Error flags in the ICR register */
02904   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
02905                              SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
02906                              SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02907
02908   /* Restore hsmartcard->RxState to Ready */
02909   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02910
02911 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02912   /* Call registered Abort Receive Complete Callback */
02913   hsmartcard->AbortReceiveCpltCallback(hsmartcard);
02914 #else
02915   /* Call legacy weak Abort Receive Complete Callback */
02916   HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
02917 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02918 }
02919
02920 /**
02921   * @brief  Send an amount of data in non-blocking mode.
02922   * @note   Function called under interruption only, once
02923   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02924   *         and when the FIFO mode is disabled.
02925   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02926   *                    the configuration information for the specified SMARTCARD module.
02927   * @retval None
02928   */
02929 static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
02930 {
02931   /* Check that a Tx process is ongoing */
02932   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02933   {
02934     if (hsmartcard->TxXferCount == 0U)
02935     {
02936       /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02937       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02938
02939       /* Enable the SMARTCARD Transmit Complete Interrupt */
02940       __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02941     }
02942     else
02943     {
02944       hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
02945       hsmartcard->pTxBuffPtr++;
02946       hsmartcard->TxXferCount--;
02947     }
02948   }
02949 }
02950
02951 /**
02952   * @brief  Send an amount of data in non-blocking mode.
02953   * @note   Function called under interruption only, once
02954   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02955   *         and when the FIFO mode is enabled.
02956   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02957   *                    the configuration information for the specified SMARTCARD module.
02958   * @retval None
02959   */
02960 static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
02961 {
02962   uint16_t   nb_tx_data;
02963
02964   /* Check that a Tx process is ongoing */
02965   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02966   {
02967     for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
02968     {
02969       if (hsmartcard->TxXferCount == 0U)
02970       {
02971         /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02972         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02973
02974         /* Enable the SMARTCARD Transmit Complete Interrupt */
02975         __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02976       }
02977       else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
02978       {
02979         hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
02980         hsmartcard->pTxBuffPtr++;
02981         hsmartcard->TxXferCount--;
02982       }
02983       else
02984       {
02985         /* Nothing to do */
02986       }
02987     }
02988   }
02989 }
02990
02991 /**
02992   * @brief  Wrap up transmission in non-blocking mode.
02993   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02994   *                    the configuration information for the specified SMARTCARD module.
02995   * @retval None
02996   */
02997 static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02998 {
02999   /* Disable the SMARTCARD Transmit Complete Interrupt */
03000   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
03001
03002   /* Check if a receive process is ongoing or not. If not disable ERR IT */
03003   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
03004   {
03005     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
03006     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03007   }
03008
03009   /* Disable the Peripheral first to update mode */
03010   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
03011   if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
03012       && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
03013   {
03014     /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
03015        for Transmit phase. Disable this receiver block. */
03016     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
03017   }
03018   if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
03019       || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
03020   {
03021     /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
03022     __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
03023   }
03024   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
03025
03026   /* Tx process is ended, restore hsmartcard->gState to Ready */
03027   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
03028
03029   /* Clear TxISR function pointer */
03030   hsmartcard->TxISR = NULL;
03031
03032 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03033   /* Call registered Tx complete callback */
03034   hsmartcard->TxCpltCallback(hsmartcard);
03035 #else
03036   /* Call legacy weak Tx complete callback */
03037   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
03038 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03039 }
03040
03041 /**
03042   * @brief  Receive an amount of data in non-blocking mode.
03043   * @note   Function called under interruption only, once
03044   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
03045   *         and when the FIFO mode is disabled.
03046   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
03047   *                    the configuration information for the specified SMARTCARD module.
03048   * @retval None
03049   */
03050 static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
03051 {
03052   /* Check that a Rx process is ongoing */
03053   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
03054   {
03055     *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
03056     hsmartcard->pRxBuffPtr++;
03057
03058     hsmartcard->RxXferCount--;
03059     if (hsmartcard->RxXferCount == 0U)
03060     {
03061       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03062
03063       /* Check if a transmit process is ongoing or not. If not disable ERR IT */
03064       if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
03065       {
03066         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
03067         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03068       }
03069
03070       /* Disable the SMARTCARD Parity Error Interrupt */
03071       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
03072
03073       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
03074
03075       /* Clear RxISR function pointer */
03076       hsmartcard->RxISR = NULL;
03077
03078 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03079       /* Call registered Rx complete callback */
03080       hsmartcard->RxCpltCallback(hsmartcard);
03081 #else
03082       /* Call legacy weak Rx complete callback */
03083       HAL_SMARTCARD_RxCpltCallback(hsmartcard);
03084 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03085     }
03086   }
03087   else
03088   {
03089     /* Clear RXNE interrupt flag */
03090     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
03091   }
03092 }
03093
03094 /**
03095   * @brief  Receive an amount of data in non-blocking mode.
03096   * @note   Function called under interruption only, once
03097   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
03098   *         and when the FIFO mode is enabled.
03099   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
03100   *                    the configuration information for the specified SMARTCARD module.
03101   * @retval None
03102   */
03103 static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
03104 {
03105   uint16_t   nb_rx_data;
03106   uint16_t rxdatacount;
03107
03108   /* Check that a Rx process is ongoing */
03109   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
03110   {
03111     for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03112     {
03113       *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
03114       hsmartcard->pRxBuffPtr++;
03115
03116       hsmartcard->RxXferCount--;
03117       if (hsmartcard->RxXferCount == 0U)
03118       {
03119         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03120
03121         /* Check if a transmit process is ongoing or not. If not disable ERR IT */
03122         if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
03123         {
03124           /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
03125           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03126         }
03127
03128         /* Disable the SMARTCARD Parity Error Interrupt */
03129         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
03130
03131         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
03132
03133         /* Clear RxISR function pointer */
03134         hsmartcard->RxISR = NULL;
03135
03136 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03137         /* Call registered Rx complete callback */
03138         hsmartcard->RxCpltCallback(hsmartcard);
03139 #else
03140         /* Call legacy weak Rx complete callback */
03141         HAL_SMARTCARD_RxCpltCallback(hsmartcard);
03142 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03143       }
03144     }
03145
03146     /* When remaining number of bytes to receive is less than the RX FIFO
03147     threshold, next incoming frames are processed as if FIFO mode was
03148     disabled (i.e. one interrupt per received frame).
03149     */
03150     rxdatacount = hsmartcard->RxXferCount;
03151     if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess))
03152     {
03153       /* Disable the UART RXFT interrupt*/
03154       CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
03155
03156       /* Update the RxISR function pointer */
03157       hsmartcard->RxISR = SMARTCARD_RxISR;
03158
03159       /* Enable the UART Data Register Not Empty interrupt */
03160       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03161     }
03162   }
03163   else
03164   {
03165     /* Clear RXNE interrupt flag */
03166     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
03167   }
03168 }
03169
03170 /**
03171   * @}
03172   */
03173
03174 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
03175 /**
03176   * @}
03177   */
03178
03179 /**
03180   * @}
03181   */
03182
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smartcard.h Source File

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stm32g0xx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_SMARTCARD_H
00021 #define STM32G0xx_HAL_SMARTCARD_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SMARTCARD
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief SMARTCARD Init Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
00049                                            The baud rate register is computed using the following formula:
00050                                               Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
00051                                            where usart_ker_ckpres is the USART input clock divided by a prescaler */
00052
00053   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00054                                            This parameter @ref SMARTCARD_Word_Length can only be
00055                                            set to 9 (8 data + 1 parity bits). */
00056
00057   uint32_t StopBits;                  /*!< Specifies the number of stop bits.
00058                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
00059
00060   uint16_t Parity;                    /*!< Specifies the parity mode.
00061                                            This parameter can be a value of @ref SMARTCARD_Parity
00062                                            @note The parity is enabled by default (PCE is forced to 1).
00063                                                  Since the WordLength is forced to 8 bits + parity, M is
00064                                                  forced to 1 and the parity bit is the 9th bit. */
00065
00066   uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00067                                            This parameter can be a value of @ref SMARTCARD_Mode */
00068
00069   uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00070                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00071
00072   uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00073                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00074
00075   uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00076                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00077                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00078
00079   uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote
00080                                            is selected. Selecting the single sample method increases
00081                                            the receiver tolerance to clock deviations. This parameter can be a value
00082                                            of @ref SMARTCARD_OneBit_Sampling. */
00083
00084   uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler.
00085                                            This parameter can be any value from 0x01 to 0x1F. Prescaler value is
00086                                            multiplied by 2 to give the division factor of the source clock frequency */
00087
00088   uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
00089
00090   uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
00091                                            in case of parity error.
00092                                            This parameter can be a value of @ref SMARTCARD_NACK_Enable */
00093
00094   uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
00095                                             This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
00096
00097   uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
00098                                            it is used to implement the Character Wait Time (CWT) and
00099                                            Block Wait Time (BWT). It is coded over 24 bits. */
00100
00101   uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
00102                                            This parameter can be any value from 0x0 to 0xFF */
00103
00104   uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
00105                                             receive and transmit mode). When set to 0, retransmission is
00106                                             disabled. Otherwise, its maximum value is 7 (before signalling
00107                                             an error) */
00108
00109   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
00110                                            This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
00111
00112 } SMARTCARD_InitTypeDef;
00113
00114 /**
00115   * @brief  SMARTCARD advanced features initialization structure definition
00116   */
00117 typedef struct
00118 {
00119   uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
00120                                            advanced features may be initialized at the same time. This parameter
00121                                            can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
00122
00123   uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
00124                                            This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
00125
00126   uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
00127                                            This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
00128
00129   uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
00130                                            vs negative/inverted logic).
00131                                            This parameter can be a value of @ref SMARTCARD_Data_Inv */
00132
00133   uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
00134                                            This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
00135
00136   uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
00137                                            This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
00138
00139   uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
00140                                            This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
00141
00142   uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
00143                                            This parameter can be a value of @ref SMARTCARD_MSB_First */
00144
00145   uint16_t TxCompletionIndication;    /*!< Specifies which transmission completion indication is used: before (when
00146                                            relevant flag is available) or once guard time period has elapsed.
00147                                            This parameter can be a value
00148                                            of @ref SMARTCARDEx_Transmission_Completion_Indication. */
00149 } SMARTCARD_AdvFeatureInitTypeDef;
00150
00151 /**
00152   * @brief HAL SMARTCARD State definition
00153   * @note  HAL SMARTCARD State value is a combination of 2 different substates:
00154   *        gState and RxState (see @ref SMARTCARD_State_Definition).
00155   *        - gState contains SMARTCARD state information related to global Handle management
00156   *          and also information related to Tx operations.
00157   *          gState value coding follow below described bitmap :
00158   *          b7-b6  Error information
00159   *             00 : No Error
00160   *             01 : (Not Used)
00161   *             10 : Timeout
00162   *             11 : Error
00163   *          b5     Peripheral initialization status
00164   *             0  : Reset (Peripheral not initialized)
00165   *             1  : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
00166   *          b4-b3  (not used)
00167   *             xx : Should be set to 00
00168   *          b2     Intrinsic process state
00169   *             0  : Ready
00170   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00171   *          b1     (not used)
00172   *             x  : Should be set to 0
00173   *          b0     Tx state
00174   *             0  : Ready (no Tx operation ongoing)
00175   *             1  : Busy (Tx operation ongoing)
00176   *        - RxState contains information related to Rx operations.
00177   *          RxState value coding follow below described bitmap :
00178   *          b7-b6  (not used)
00179   *             xx : Should be set to 00
00180   *          b5     Peripheral initialization status
00181   *             0  : Reset (Peripheral not initialized)
00182   *             1  : Init done (Peripheral initialized)
00183   *          b4-b2  (not used)
00184   *            xxx : Should be set to 000
00185   *          b1     Rx state
00186   *             0  : Ready (no Rx operation ongoing)
00187   *             1  : Busy (Rx operation ongoing)
00188   *          b0     (not used)
00189   *             x  : Should be set to 0.
00190   */
00191 typedef uint32_t HAL_SMARTCARD_StateTypeDef;
00192
00193 /**
00194   * @brief  SMARTCARD handle Structure definition
00195   */
00196 typedef struct __SMARTCARD_HandleTypeDef
00197 {
00198   USART_TypeDef                     *Instance;             /*!< USART registers base address                          */
00199
00200   SMARTCARD_InitTypeDef             Init;                  /*!< SmartCard communication parameters                    */
00201
00202   SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */
00203
00204   const uint8_t                     *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
00205
00206   uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */
00207
00208   __IO uint16_t                     TxXferCount;           /*!< SmartCard Tx Transfer Counter                         */
00209
00210   uint8_t                           *pRxBuffPtr;           /*!< Pointer to SmartCard Rx transfer Buffer               */
00211
00212   uint16_t                          RxXferSize;            /*!< SmartCard Rx Transfer size                            */
00213
00214   __IO uint16_t                     RxXferCount;           /*!< SmartCard Rx Transfer Counter                         */
00215
00216   uint16_t                          NbRxDataToProcess;     /*!< Number of data to process during RX ISR execution     */
00217
00218   uint16_t                          NbTxDataToProcess;     /*!< Number of data to process during TX ISR execution     */
00219
00220   uint32_t                          FifoMode;              /*!< Specifies if the FIFO mode will be used.
00221                                                                 This parameter can be a value of
00222                                                                 @ref SMARTCARDEx_FIFO_mode.                           */
00223
00224   void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Rx IRQ handler                    */
00225
00226   void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Tx IRQ handler                    */
00227
00228   DMA_HandleTypeDef                 *hdmatx;               /*!< SmartCard Tx DMA Handle parameters                    */
00229
00230   DMA_HandleTypeDef                 *hdmarx;               /*!< SmartCard Rx DMA Handle parameters                    */
00231
00232   HAL_LockTypeDef                   Lock;                  /*!< Locking object                                        */
00233
00234   __IO HAL_SMARTCARD_StateTypeDef   gState;                /*!< SmartCard state information related to global
00235                                                                 Handle management and also related to Tx operations.
00236                                                                 This parameter can be a value
00237                                                                 of @ref HAL_SMARTCARD_StateTypeDef                    */
00238
00239   __IO HAL_SMARTCARD_StateTypeDef   RxState;               /*!< SmartCard state information related to Rx operations.
00240                                                                 This parameter can be a value
00241                                                                 of @ref HAL_SMARTCARD_StateTypeDef                    */
00242
00243   __IO uint32_t                     ErrorCode;             /*!< SmartCard Error code                                  */
00244
00245 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00246   void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Tx Complete Callback             */
00247
00248   void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Rx Complete Callback             */
00249
00250   void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);             /*!< SMARTCARD Error Callback                   */
00251
00252   void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Abort Complete Callback          */
00253
00254   void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
00255
00256   void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);  /*!< SMARTCARD Abort Receive Complete Callback  */
00257
00258   void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);        /*!< SMARTCARD Rx Fifo Full Callback            */
00259
00260   void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);       /*!< SMARTCARD Tx Fifo Empty Callback           */
00261
00262   void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);           /*!< SMARTCARD Msp Init callback                */
00263
00264   void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Msp DeInit callback              */
00265 #endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00266
00267 } SMARTCARD_HandleTypeDef;
00268
00269 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00270 /**
00271   * @brief  HAL SMARTCARD Callback ID enumeration definition
00272   */
00273 typedef enum
00274 {
00275   HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
00276   HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
00277   HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
00278   HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
00279   HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
00280   HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
00281   HAL_SMARTCARD_RX_FIFO_FULL_CB_ID            = 0x06U,    /*!< SMARTCARD Rx Fifo Full Callback ID            */
00282   HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID           = 0x07U,    /*!< SMARTCARD Tx Fifo Empty Callback ID           */
00283
00284   HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
00285   HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
00286
00287 } HAL_SMARTCARD_CallbackIDTypeDef;
00288
00289 /**
00290   * @brief  HAL SMARTCARD Callback pointer definition
00291   */
00292 typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard);  /*!< pointer to an SMARTCARD callback function */
00293
00294 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00295
00296 /**
00297   * @brief  SMARTCARD clock sources
00298   */
00299 typedef enum
00300 {
00301   SMARTCARD_CLOCKSOURCE_PCLK1     = 0x00U, /*!< PCLK1 clock source         */
00302   SMARTCARD_CLOCKSOURCE_HSI       = 0x02U, /*!< HSI clock source           */
00303   SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04U, /*!< SYSCLK clock source        */
00304   SMARTCARD_CLOCKSOURCE_LSE       = 0x08U, /*!< LSE clock source           */
00305   SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U  /*!< undefined clock source     */
00306 } SMARTCARD_ClockSourceTypeDef;
00307
00308 /**
00309   * @}
00310   */
00311
00312 /* Exported constants --------------------------------------------------------*/
00313 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
00314   * @{
00315   */
00316
00317 /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
00318   * @{
00319   */
00320 #define HAL_SMARTCARD_STATE_RESET            0x00000000U                     /*!< Peripheral is not initialized. Value
00321                                                                                   is allowed for gState and RxState */
00322 #define HAL_SMARTCARD_STATE_READY            0x00000020U                     /*!< Peripheral Initialized and ready for
00323                                                                                   use. Value is allowed for gState
00324                                                                                   and RxState                       */
00325 #define HAL_SMARTCARD_STATE_BUSY             0x00000024U                     /*!< an internal process is ongoing
00326                                                                                   Value is allowed for gState only  */
00327 #define HAL_SMARTCARD_STATE_BUSY_TX          0x00000021U                     /*!< Data Transmission process is ongoing
00328                                                                                   Value is allowed for gState only  */
00329 #define HAL_SMARTCARD_STATE_BUSY_RX          0x00000022U                     /*!< Data Reception process is ongoing
00330                                                                                   Value is allowed for RxState only */
00331 #define HAL_SMARTCARD_STATE_BUSY_TX_RX       0x00000023U                     /*!< Data Transmission and Reception
00332                                                                                   process is ongoing Not to be used for
00333                                                                                   neither gState nor RxState.
00334                                                                                   Value is result of combination (Or)
00335                                                                                   between gState and RxState values */
00336 #define HAL_SMARTCARD_STATE_TIMEOUT          0x000000A0U                     /*!< Timeout state
00337                                                                                   Value is allowed for gState only  */
00338 #define HAL_SMARTCARD_STATE_ERROR            0x000000E0U                     /*!< Error
00339                                                                                   Value is allowed for gState only  */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
00345   * @{
00346   */
00347 #define HAL_SMARTCARD_ERROR_NONE             (0x00000000U)         /*!< No error                */
00348 #define HAL_SMARTCARD_ERROR_PE               (0x00000001U)         /*!< Parity error            */
00349 #define HAL_SMARTCARD_ERROR_NE               (0x00000002U)         /*!< Noise error             */
00350 #define HAL_SMARTCARD_ERROR_FE               (0x00000004U)         /*!< frame error             */
00351 #define HAL_SMARTCARD_ERROR_ORE              (0x00000008U)         /*!< Overrun error           */
00352 #define HAL_SMARTCARD_ERROR_DMA              (0x00000010U)         /*!< DMA transfer error      */
00353 #define HAL_SMARTCARD_ERROR_RTO              (0x00000020U)         /*!< Receiver TimeOut error  */
00354 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00355 #define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)         /*!< Invalid Callback error  */
00356 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00362   * @{
00363   */
00364 #define SMARTCARD_WORDLENGTH_9B             USART_CR1_M0                    /*!< SMARTCARD frame length */
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00370   * @{
00371   */
00372 #define SMARTCARD_STOPBITS_0_5              USART_CR2_STOP_0                /*!< SMARTCARD frame with 0.5 stop bit  */
00373 #define SMARTCARD_STOPBITS_1_5              USART_CR2_STOP                  /*!< SMARTCARD frame with 1.5 stop bits */
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00379   * @{
00380   */
00381 #define SMARTCARD_PARITY_EVEN               USART_CR1_PCE                   /*!< SMARTCARD frame even parity */
00382 #define SMARTCARD_PARITY_ODD                (USART_CR1_PCE | USART_CR1_PS)  /*!< SMARTCARD frame odd parity  */
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
00388   * @{
00389   */
00390 #define SMARTCARD_MODE_RX                   USART_CR1_RE                    /*!< SMARTCARD RX mode        */
00391 #define SMARTCARD_MODE_TX                   USART_CR1_TE                    /*!< SMARTCARD TX mode        */
00392 #define SMARTCARD_MODE_TX_RX                (USART_CR1_TE |USART_CR1_RE)    /*!< SMARTCARD RX and TX mode */
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00398   * @{
00399   */
00400 #define SMARTCARD_POLARITY_LOW              0x00000000U                     /*!< SMARTCARD frame low polarity  */
00401 #define SMARTCARD_POLARITY_HIGH             USART_CR2_CPOL                  /*!< SMARTCARD frame high polarity */
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
00407   * @{
00408   */
00409 #define SMARTCARD_PHASE_1EDGE               0x00000000U                     /*!< SMARTCARD frame phase on first clock transition  */
00410 #define SMARTCARD_PHASE_2EDGE               USART_CR2_CPHA                  /*!< SMARTCARD frame phase on second clock transition */
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
00416   * @{
00417   */
00418 #define SMARTCARD_LASTBIT_DISABLE           0x00000000U                     /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
00419 #define SMARTCARD_LASTBIT_ENABLE            USART_CR2_LBCL                  /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
00425   * @{
00426   */
00427 #define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    0x00000000U                     /*!< SMARTCARD frame one-bit sample disabled */
00428 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     USART_CR3_ONEBIT                /*!< SMARTCARD frame one-bit sample enabled  */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
00434   * @{
00435   */
00436 #define SMARTCARD_NACK_DISABLE              0x00000000U                     /*!< SMARTCARD NACK transmission disabled  */
00437 #define SMARTCARD_NACK_ENABLE               USART_CR3_NACK                  /*!< SMARTCARD NACK transmission enabled */
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
00443   * @{
00444   */
00445 #define SMARTCARD_TIMEOUT_DISABLE           0x00000000U                     /*!< SMARTCARD receiver timeout disabled */
00446 #define SMARTCARD_TIMEOUT_ENABLE            USART_CR2_RTOEN                 /*!< SMARTCARD receiver timeout enabled  */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup SMARTCARD_ClockPrescaler  SMARTCARD Clock Prescaler
00452   * @{
00453   */
00454 #define SMARTCARD_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00455 #define SMARTCARD_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00456 #define SMARTCARD_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00457 #define SMARTCARD_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00458 #define SMARTCARD_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00459 #define SMARTCARD_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00460 #define SMARTCARD_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00461 #define SMARTCARD_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00462 #define SMARTCARD_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00463 #define SMARTCARD_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00464 #define SMARTCARD_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00465 #define SMARTCARD_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
00471   * @{
00472   */
00473 #define SMARTCARD_ADVFEATURE_TXINV_DISABLE  0x00000000U                  /*!< TX pin active level inversion disable */
00474 #define SMARTCARD_ADVFEATURE_TXINV_ENABLE   USART_CR2_TXINV              /*!< TX pin active level inversion enable  */
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
00480   * @{
00481   */
00482 #define SMARTCARD_ADVFEATURE_RXINV_DISABLE  0x00000000U                  /*!< RX pin active level inversion disable */
00483 #define SMARTCARD_ADVFEATURE_RXINV_ENABLE   USART_CR2_RXINV              /*!< RX pin active level inversion enable  */
00484 /**
00485   * @}
00486   */
00487
00488 /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
00489   * @{
00490   */
00491 #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  0x00000000U                /*!< Binary data inversion disable */
00492 #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   USART_CR2_DATAINV          /*!< Binary data inversion enable  */
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
00498   * @{
00499   */
00500 #define SMARTCARD_ADVFEATURE_SWAP_DISABLE   0x00000000U                  /*!< TX/RX pins swap disable */
00501 #define SMARTCARD_ADVFEATURE_SWAP_ENABLE    USART_CR2_SWAP               /*!< TX/RX pins swap enable  */
00502 /**
00503   * @}
00504   */
00505
00506 /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
00507   * @{
00508   */
00509 #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   0x00000000U                /*!< RX overrun enable  */
00510 #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  USART_CR3_OVRDIS           /*!< RX overrun disable */
00511 /**
00512   * @}
00513   */
00514
00515 /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
00516   * @{
00517   */
00518 #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   0x00000000U           /*!< DMA enable on Reception Error  */
00519 #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  USART_CR3_DDRE        /*!< DMA disable on Reception Error */
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
00525   * @{
00526   */
00527 #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      0x00000000U           /*!< Most significant bit sent/received first disable */
00528 #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       USART_CR2_MSBFIRST    /*!< Most significant bit sent/received first enable  */
00529 /**
00530   * @}
00531   */
00532
00533 /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
00534   * @{
00535   */
00536 #define SMARTCARD_RXDATA_FLUSH_REQUEST      USART_RQR_RXFRQ              /*!< Receive data flush request */
00537 #define SMARTCARD_TXDATA_FLUSH_REQUEST      USART_RQR_TXFRQ              /*!< Transmit data flush request */
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
00543   * @{
00544   */
00545 #define SMARTCARD_IT_MASK                   0x001FU   /*!< SMARTCARD interruptions flags mask  */
00546 #define SMARTCARD_CR_MASK                   0x00E0U   /*!< SMARTCARD control register mask     */
00547 #define SMARTCARD_CR_POS                    5U        /*!< SMARTCARD control register position */
00548 #define SMARTCARD_ISR_MASK                  0x1F00U   /*!< SMARTCARD ISR register mask         */
00549 #define SMARTCARD_ISR_POS                   8U        /*!< SMARTCARD ISR register position     */
00550 /**
00551   * @}
00552   */
00553
00554 /**
00555   * @}
00556   */
00557
00558 /* Exported macros -----------------------------------------------------------*/
00559 /** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
00560   * @{
00561   */
00562
00563 /** @brief  Reset SMARTCARD handle states.
00564   * @param  __HANDLE__ SMARTCARD handle.
00565   * @retval None
00566   */
00567 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00568 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00569                                                             (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
00570                                                             (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
00571                                                             (__HANDLE__)->MspInitCallback = NULL;                 \
00572                                                             (__HANDLE__)->MspDeInitCallback = NULL;               \
00573                                                           } while(0U)
00574 #else
00575 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00576                                                             (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
00577                                                             (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
00578                                                           } while(0U)
00579 #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
00580
00581 /** @brief  Flush the Smartcard Data registers.
00582   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00583   * @retval None
00584   */
00585 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                      \
00586   do{                                                                     \
00587     SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
00588     SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
00589   } while(0U)
00590
00591 /** @brief  Clear the specified SMARTCARD pending flag.
00592   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00593   * @param  __FLAG__ specifies the flag to check.
00594   *          This parameter can be any combination of the following values:
00595   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00596   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00597   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00598   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00599   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
00600   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00601   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
00602   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00603   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00604   *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
00605   * @retval None
00606   */
00607 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00608
00609 /** @brief  Clear the SMARTCARD PE pending flag.
00610   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00611   * @retval None
00612   */
00613 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
00614
00615 /** @brief  Clear the SMARTCARD FE pending flag.
00616   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00617   * @retval None
00618   */
00619 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
00620
00621 /** @brief  Clear the SMARTCARD NE pending flag.
00622   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00623   * @retval None
00624   */
00625 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
00626
00627 /** @brief  Clear the SMARTCARD ORE pending flag.
00628   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00629   * @retval None
00630   */
00631 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
00632
00633 /** @brief  Clear the SMARTCARD IDLE pending flag.
00634   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00635   * @retval None
00636   */
00637 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
00638
00639 /** @brief  Check whether the specified Smartcard flag is set or not.
00640   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00641   * @param  __FLAG__ specifies the flag to check.
00642   *        This parameter can be one of the following values:
00643   *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
00644   *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
00645   *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
00646   *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
00647   *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
00648   *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
00649   *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
00650   *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
00651   *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
00652   *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
00653   *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
00654   *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
00655   *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
00656   *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
00657   *            @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
00658   *            @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
00659   *            @arg @ref SMARTCARD_FLAG_TXFE  TXFIFO Empty flag
00660   *            @arg @ref SMARTCARD_FLAG_RXFF  RXFIFO Full flag
00661   *            @arg @ref SMARTCARD_FLAG_RXFT  SMARTCARD RXFIFO threshold flag
00662   *            @arg @ref SMARTCARD_FLAG_TXFT  SMARTCARD TXFIFO threshold flag
00663   * @retval The new state of __FLAG__ (TRUE or FALSE).
00664   */
00665 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00666
00667 /** @brief  Enable the specified SmartCard interrupt.
00668   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00669   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
00670   *          This parameter can be one of the following values:
00671   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00672   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00673   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00674   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00675   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before
00676   *                                          guard time interrupt (when interruption available)
00677   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00678   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00679   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00680   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00681   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00682   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00683   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00684   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00685   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00686   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00687   * @retval None
00688   */
00689 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00690                                                                   SMARTCARD_CR_POS) == 1U)?\
00691                                                                 ((__HANDLE__)->Instance->CR1 |= (1UL <<\
00692                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
00693                                                                 ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00694                                                                   SMARTCARD_CR_POS) == 2U)?\
00695                                                                 ((__HANDLE__)->Instance->CR2 |= (1UL <<\
00696                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00697                                                                 ((__HANDLE__)->Instance->CR3 |= (1UL <<\
00698                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00699
00700 /** @brief  Disable the specified SmartCard interrupt.
00701   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00702   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
00703   *          This parameter can be one of the following values:
00704   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00705   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00706   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00707   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00708   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard
00709   *                                          time interrupt (when interruption available)
00710   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00711   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00712   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00713   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00714   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00715   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00716   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00717   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00718   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00719   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00720   * @retval None
00721   */
00722 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00723                                                                   SMARTCARD_CR_POS) == 1U)?\
00724                                                                 ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
00725                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00726                                                                 ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00727                                                                   SMARTCARD_CR_POS) == 2U)?\
00728                                                                 ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
00729                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00730                                                                 ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
00731                                                                     ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00732
00733 /** @brief  Check whether the specified SmartCard interrupt has occurred or not.
00734   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00735   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to check.
00736   *          This parameter can be one of the following values:
00737   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00738   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00739   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00740   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00741   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time
00742   *                                          interrupt (when interruption available)
00743   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00744   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00745   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00746   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00747   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00748   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00749   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00750   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00751   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00752   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00753   * @retval The new state of __INTERRUPT__ (SET or RESET).
00754   */
00755 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
00756                                                            (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
00757                                                                & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
00758                                                            ? SET : RESET)
00759
00760 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
00761   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00762   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
00763   *          This parameter can be one of the following values:
00764   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00765   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00766   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00767   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00768   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time
00769   *                                          interrupt (when interruption available)
00770   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00771   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00772   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00773   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00774   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00775   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00776   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00777   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00778   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00779   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00780   * @retval The new state of __INTERRUPT__ (SET or RESET).
00781   */
00782 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00783                                                                        SMARTCARD_CR_POS) == 0x01U)?\
00784                                                                      (__HANDLE__)->Instance->CR1 : \
00785                                                                      (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
00786                                                                         SMARTCARD_CR_POS) == 0x02U)?\
00787                                                                       (__HANDLE__)->Instance->CR2 : \
00788                                                                       (__HANDLE__)->Instance->CR3)) &\
00789                                                                     (0x01UL << (((uint16_t)(__INTERRUPT__))\
00790                                                                                 & SMARTCARD_IT_MASK)))  != 0U)\
00791                                                                   ? SET : RESET)
00792
00793 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
00794   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00795   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00796   *                       to clear the corresponding interrupt.
00797   *          This parameter can be one of the following values:
00798   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00799   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00800   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00801   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00802   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
00803   *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
00804   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00805   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
00806   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00807   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00808   * @retval None
00809   */
00810 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
00811
00812 /** @brief  Set a specific SMARTCARD request flag.
00813   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00814   * @param  __REQ__ specifies the request flag to set
00815   *          This parameter can be one of the following values:
00816   *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
00817   *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
00818   * @retval None
00819   */
00820 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00821
00822 /** @brief  Enable the SMARTCARD one bit sample method.
00823   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00824   * @retval None
00825   */
00826 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00827
00828 /** @brief  Disable the SMARTCARD one bit sample method.
00829   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00830   * @retval None
00831   */
00832 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
00833                                                             &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00834
00835 /** @brief  Enable the USART associated to the SMARTCARD Handle.
00836   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00837   * @retval None
00838   */
00839 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00840
00841 /** @brief  Disable the USART associated to the SMARTCARD Handle
00842   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00843   * @retval None
00844   */
00845 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00846
00847 /**
00848   * @}
00849   */
00850
00851 /* Private macros -------------------------------------------------------------*/
00852 /** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
00853   * @{
00854   */
00855
00856
00857 /** @brief  Check the Baud rate range.
00858   * @note   The maximum Baud Rate is derived from the maximum clock on G0 (64 MHz)
00859   *         divided by the oversampling used on the SMARTCARD (i.e. 16).
00860   * @param  __BAUDRATE__ Baud rate set by the configuration function.
00861   * @retval Test result (TRUE or FALSE)
00862   */
00863 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
00864
00865 /** @brief  Check the block length range.
00866   * @note   The maximum SMARTCARD block length is 0xFF.
00867   * @param  __LENGTH__ block length.
00868   * @retval Test result (TRUE or FALSE)
00869   */
00870 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
00871
00872 /** @brief  Check the receiver timeout value.
00873   * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
00874   * @param  __TIMEOUTVALUE__ receiver timeout value.
00875   * @retval Test result (TRUE or FALSE)
00876   */
00877 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
00878
00879 /** @brief  Check the SMARTCARD autoretry counter value.
00880   * @note   The maximum number of retransmissions is 0x7.
00881   * @param  __COUNT__ number of retransmissions.
00882   * @retval Test result (TRUE or FALSE)
00883   */
00884 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
00885
00886 /** @brief Ensure that SMARTCARD frame length is valid.
00887   * @param __LENGTH__ SMARTCARD frame length.
00888   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00889   */
00890 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
00891
00892 /** @brief Ensure that SMARTCARD frame number of stop bits is valid.
00893   * @param __STOPBITS__ SMARTCARD frame number of stop bits.
00894   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00895   */
00896 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
00897                                              ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
00898
00899 /** @brief Ensure that SMARTCARD frame parity is valid.
00900   * @param __PARITY__ SMARTCARD frame parity.
00901   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00902   */
00903 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
00904                                          ((__PARITY__) == SMARTCARD_PARITY_ODD))
00905
00906 /** @brief Ensure that SMARTCARD communication mode is valid.
00907   * @param __MODE__ SMARTCARD communication mode.
00908   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00909   */
00910 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
00911
00912 /** @brief Ensure that SMARTCARD frame polarity is valid.
00913   * @param __CPOL__ SMARTCARD frame polarity.
00914   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00915   */
00916 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
00917                                          || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
00918
00919 /** @brief Ensure that SMARTCARD frame phase is valid.
00920   * @param __CPHA__ SMARTCARD frame phase.
00921   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00922   */
00923 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
00924
00925 /** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
00926   * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
00927   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00928   */
00929 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
00930                                            ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
00931
00932 /** @brief Ensure that SMARTCARD frame sampling is valid.
00933   * @param __ONEBIT__ SMARTCARD frame sampling.
00934   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00935   */
00936 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
00937                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
00938
00939 /** @brief Ensure that SMARTCARD NACK transmission setting is valid.
00940   * @param __NACK__ SMARTCARD NACK transmission setting.
00941   * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
00942   */
00943 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
00944                                      ((__NACK__) == SMARTCARD_NACK_DISABLE))
00945
00946 /** @brief Ensure that SMARTCARD receiver timeout setting is valid.
00947   * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
00948   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
00949   */
00950 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
00951                                            ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
00952
00953 /** @brief Ensure that SMARTCARD clock Prescaler is valid.
00954   * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
00955   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00956   */
00957 #define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
00958                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
00959                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
00960                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
00961                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
00962                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
00963                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
00964                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
00965                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
00966                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
00967                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
00968                                                          ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
00969
00970 /** @brief Ensure that SMARTCARD advanced features initialization is valid.
00971   * @param __INIT__ SMARTCARD advanced features initialization.
00972   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
00973   */
00974 #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
00975                                                                SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
00976                                                                SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
00977                                                                SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
00978                                                                SMARTCARD_ADVFEATURE_SWAP_INIT              | \
00979                                                                SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
00980                                                                SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
00981                                                                SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
00982
00983 /** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
00984   * @param __TXINV__ SMARTCARD frame TX inversion setting.
00985   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
00986   */
00987 #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
00988                                                   ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
00989
00990 /** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
00991   * @param __RXINV__ SMARTCARD frame RX inversion setting.
00992   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
00993   */
00994 #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
00995                                                   ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
00996
00997 /** @brief Ensure that SMARTCARD frame data inversion setting is valid.
00998   * @param __DATAINV__ SMARTCARD frame data inversion setting.
00999   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01000   */
01001 #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
01002                                                       ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
01003
01004 /** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
01005   * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
01006   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01007   */
01008 #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
01009                                                 ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
01010
01011 /** @brief Ensure that SMARTCARD frame overrun setting is valid.
01012   * @param __OVERRUN__ SMARTCARD frame overrun setting.
01013   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01014   */
01015 #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
01016                                            ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
01017
01018 /** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
01019   * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
01020   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01021   */
01022 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01023                                                        ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
01024
01025 /** @brief Ensure that SMARTCARD frame MSB first setting is valid.
01026   * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
01027   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01028   */
01029 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
01030                                                         ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
01031
01032 /** @brief Ensure that SMARTCARD request parameter is valid.
01033   * @param __PARAM__ SMARTCARD request parameter.
01034   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01035   */
01036 #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
01037                                                    ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
01038
01039 /**
01040   * @}
01041   */
01042
01043 /* Include SMARTCARD HAL Extended module */
01044 #include "stm32g0xx_hal_smartcard_ex.h"
01045
01046 /* Exported functions --------------------------------------------------------*/
01047 /** @addtogroup SMARTCARD_Exported_Functions
01048   * @{
01049   */
01050
01051 /* Initialization and de-initialization functions  ****************************/
01052 /** @addtogroup SMARTCARD_Exported_Functions_Group1
01053   * @{
01054   */
01055
01056 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
01057 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01058 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
01059 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01060
01061 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01062 /* Callbacks Register/UnRegister functions  ***********************************/
01063 HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
01064                                                  HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
01065                                                  pSMARTCARD_CallbackTypeDef pCallback);
01066 HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
01067                                                    HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
01068 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
01069
01070 /**
01071   * @}
01072   */
01073
01074 /* IO operation functions *****************************************************/
01075 /** @addtogroup SMARTCARD_Exported_Functions_Group2
01076   * @{
01077   */
01078
01079 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
01080                                          uint32_t Timeout);
01081 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
01082                                         uint32_t Timeout);
01083 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
01084 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01085 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
01086 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01087 /* Transfer Abort functions */
01088 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
01089 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
01090 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
01091 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01092 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01093 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01094
01095 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
01096 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01097 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01098 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01099 void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01100 void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01101 void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01102
01103 /**
01104   * @}
01105   */
01106
01107 /* Peripheral State and Error functions ***************************************/
01108 /** @addtogroup SMARTCARD_Exported_Functions_Group4
01109   * @{
01110   */
01111
01112 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard);
01113 uint32_t                   HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard);
01114
01115 /**
01116   * @}
01117   */
01118
01119 /**
01120   * @}
01121   */
01122
01123 /**
01124   * @}
01125   */
01126
01127 /**
01128   * @}
01129   */
01130
01131 #ifdef __cplusplus
01132 }
01133 #endif
01134
01135 #endif /* STM32G0xx_HAL_SMARTCARD_H */
01136
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smartcard_ex.c Source File

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stm32g0xx_hal_smartcard_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_smartcard_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides extended firmware functions to manage the following
00007   *          functionalities of the SmartCard.
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2018 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   =============================================================================
00024                ##### SMARTCARD peripheral extended features  #####
00025   =============================================================================
00026   [..]
00027   The Extended SMARTCARD HAL driver can be used as follows:
00028
00029     (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
00030         then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
00031         auto-retry counter,...) in the hsmartcard AdvancedInit structure.
00032
00033     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00034
00035         -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
00036             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00037             configured prior starting RX/TX transfers.
00038
00039   @endverbatim
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32g0xx_hal.h"
00045
00046 /** @addtogroup STM32G0xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup SMARTCARDEx SMARTCARDEx
00051   * @brief SMARTCARD Extended HAL module driver
00052   * @{
00053   */
00054 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
00059   * @{
00060   */
00061 /* UART RX FIFO depth */
00062 #define RX_FIFO_DEPTH 8U
00063
00064 /* UART TX FIFO depth */
00065 #define TX_FIFO_DEPTH 8U
00066 /**
00067   * @}
00068   */
00069
00070 /* Private macros ------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
00074
00075 /* Exported functions --------------------------------------------------------*/
00076 /** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
00077   * @{
00078   */
00079
00080 /** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
00081   * @brief    Extended control functions
00082   *
00083 @verbatim
00084   ===============================================================================
00085                       ##### Peripheral Control functions #####
00086   ===============================================================================
00087   [..]
00088   This subsection provides a set of functions allowing to initialize the SMARTCARD.
00089      (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
00090      (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
00091      (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
00092      (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
00093
00094 @endverbatim
00095   * @{
00096   */
00097
00098 /** @brief Update on the fly the SMARTCARD block length in RTOR register.
00099   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00100   *                    the configuration information for the specified SMARTCARD module.
00101   * @param BlockLength SMARTCARD block length (8-bit long at most)
00102   * @retval None
00103   */
00104 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
00105 {
00106   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
00107 }
00108
00109 /** @brief Update on the fly the receiver timeout value in RTOR register.
00110   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00111   *                    the configuration information for the specified SMARTCARD module.
00112   * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
00113   *                     value must be less or equal to 0x0FFFFFFFF.
00114   * @retval None
00115   */
00116 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
00117 {
00118   assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
00119   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
00120 }
00121
00122 /** @brief Enable the SMARTCARD receiver timeout feature.
00123   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00124   *                    the configuration information for the specified SMARTCARD module.
00125   * @retval HAL status
00126   */
00127 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00128 {
00129   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00130   {
00131     /* Process Locked */
00132     __HAL_LOCK(hsmartcard);
00133
00134     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00135
00136     /* Set the USART RTOEN bit */
00137     SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00138
00139     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00140
00141     /* Process Unlocked */
00142     __HAL_UNLOCK(hsmartcard);
00143
00144     return HAL_OK;
00145   }
00146   else
00147   {
00148     return HAL_BUSY;
00149   }
00150 }
00151
00152 /** @brief Disable the SMARTCARD receiver timeout feature.
00153   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00154   *                    the configuration information for the specified SMARTCARD module.
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00158 {
00159   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00160   {
00161     /* Process Locked */
00162     __HAL_LOCK(hsmartcard);
00163
00164     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00165
00166     /* Clear the USART RTOEN bit */
00167     CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00168
00169     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00170
00171     /* Process Unlocked */
00172     __HAL_UNLOCK(hsmartcard);
00173
00174     return HAL_OK;
00175   }
00176   else
00177   {
00178     return HAL_BUSY;
00179   }
00180 }
00181
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
00187   * @brief   SMARTCARD Transmit and Receive functions
00188   *
00189 @verbatim
00190  ===============================================================================
00191                       ##### IO operation functions #####
00192  ===============================================================================
00193     [..]
00194     This subsection provides a set of FIFO mode related callback functions.
00195
00196     (#) TX/RX Fifos Callbacks:
00197         (++) HAL_SMARTCARDEx_RxFifoFullCallback()
00198         (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
00199
00200 @endverbatim
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  SMARTCARD RX Fifo full callback.
00206   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00207   *                   the configuration information for the specified SMARTCARD module.
00208   * @retval None
00209   */
00210 __weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00211 {
00212   /* Prevent unused argument(s) compilation warning */
00213   UNUSED(hsmartcard);
00214
00215   /* NOTE : This function should not be modified, when the callback is needed,
00216             the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
00217    */
00218 }
00219
00220 /**
00221   * @brief  SMARTCARD TX Fifo empty callback.
00222   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00223   *                   the configuration information for the specified SMARTCARD module.
00224   * @retval None
00225   */
00226 __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00227 {
00228   /* Prevent unused argument(s) compilation warning */
00229   UNUSED(hsmartcard);
00230
00231   /* NOTE : This function should not be modified, when the callback is needed,
00232             the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
00233    */
00234 }
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
00241   *  @brief   SMARTCARD control functions
00242   *
00243 @verbatim
00244  ===============================================================================
00245                   ##### Peripheral FIFO Control functions #####
00246  ===============================================================================
00247     [..]
00248     This subsection provides a set of functions allowing to control the SMARTCARD
00249     FIFO feature.
00250      (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
00251      (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
00252      (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00253      (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00254 @endverbatim
00255   * @{
00256   */
00257
00258 /**
00259   * @brief  Enable the FIFO mode.
00260   * @param hsmartcard SMARTCARD handle.
00261   * @retval HAL status
00262   */
00263 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
00264 {
00265   uint32_t tmpcr1;
00266
00267   /* Check parameters */
00268   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00269
00270   /* Process Locked */
00271   __HAL_LOCK(hsmartcard);
00272
00273   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00274
00275   /* Save actual SMARTCARD configuration */
00276   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00277
00278   /* Disable SMARTCARD */
00279   __HAL_SMARTCARD_DISABLE(hsmartcard);
00280
00281   /* Enable FIFO mode */
00282   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00283   hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
00284
00285   /* Restore SMARTCARD configuration */
00286   WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
00287
00288   /* Determine the number of data to process during RX/TX ISR execution */
00289   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00290
00291   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00292
00293   /* Process Unlocked */
00294   __HAL_UNLOCK(hsmartcard);
00295
00296   return HAL_OK;
00297 }
00298
00299 /**
00300   * @brief  Disable the FIFO mode.
00301   * @param hsmartcard SMARTCARD handle.
00302   * @retval HAL status
00303   */
00304 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
00305 {
00306   uint32_t tmpcr1;
00307
00308   /* Check parameters */
00309   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00310
00311   /* Process Locked */
00312   __HAL_LOCK(hsmartcard);
00313
00314   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00315
00316   /* Save actual SMARTCARD configuration */
00317   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00318
00319   /* Disable SMARTCARD */
00320   __HAL_SMARTCARD_DISABLE(hsmartcard);
00321
00322   /* Enable FIFO mode */
00323   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00324   hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
00325
00326   /* Restore SMARTCARD configuration */
00327   WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
00328
00329   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00330
00331   /* Process Unlocked */
00332   __HAL_UNLOCK(hsmartcard);
00333
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @brief  Set the TXFIFO threshold.
00339   * @param hsmartcard      SMARTCARD handle.
00340   * @param Threshold  TX FIFO threshold value
00341   *          This parameter can be one of the following values:
00342   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
00343   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
00344   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
00345   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
00346   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
00347   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
00348   * @retval HAL status
00349   */
00350 HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
00351 {
00352   uint32_t tmpcr1;
00353
00354   /* Check parameters */
00355   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00356   assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
00357
00358   /* Process Locked */
00359   __HAL_LOCK(hsmartcard);
00360
00361   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00362
00363   /* Save actual SMARTCARD configuration */
00364   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00365
00366   /* Disable SMARTCARD */
00367   __HAL_SMARTCARD_DISABLE(hsmartcard);
00368
00369   /* Update TX threshold configuration */
00370   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00371
00372   /* Determine the number of data to process during RX/TX ISR execution */
00373   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00374
00375   /* Restore SMARTCARD configuration */
00376   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
00377
00378   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00379
00380   /* Process Unlocked */
00381   __HAL_UNLOCK(hsmartcard);
00382
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Set the RXFIFO threshold.
00388   * @param hsmartcard      SMARTCARD handle.
00389   * @param Threshold  RX FIFO threshold value
00390   *          This parameter can be one of the following values:
00391   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
00392   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
00393   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
00394   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
00395   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
00396   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
00400 {
00401   uint32_t tmpcr1;
00402
00403   /* Check parameters */
00404   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00405   assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hsmartcard);
00409
00410   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00411
00412   /* Save actual SMARTCARD configuration */
00413   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00414
00415   /* Disable SMARTCARD */
00416   __HAL_SMARTCARD_DISABLE(hsmartcard);
00417
00418   /* Update RX threshold configuration */
00419   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00420
00421   /* Determine the number of data to process during RX/TX ISR execution */
00422   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00423
00424   /* Restore SMARTCARD configuration */
00425   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
00426
00427   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00428
00429   /* Process Unlocked */
00430   __HAL_UNLOCK(hsmartcard);
00431
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @}
00437   */
00438
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SMARTCARDEx_Private_Functions  SMARTCARD Extended Private Functions
00444   * @{
00445   */
00446
00447 /**
00448   * @brief Calculate the number of data to process in RX/TX ISR.
00449   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00450   *       the USART configuration registers.
00451   * @param hsmartcard SMARTCARD handle.
00452   * @retval None
00453   */
00454 static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
00455 {
00456   uint8_t rx_fifo_depth;
00457   uint8_t tx_fifo_depth;
00458   uint8_t rx_fifo_threshold;
00459   uint8_t tx_fifo_threshold;
00460   /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
00461   static const uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00462   static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00463
00464   if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
00465   {
00466     hsmartcard->NbTxDataToProcess = 1U;
00467     hsmartcard->NbRxDataToProcess = 1U;
00468   }
00469   else
00470   {
00471     rx_fifo_depth = RX_FIFO_DEPTH;
00472     tx_fifo_depth = TX_FIFO_DEPTH;
00473     rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00474     tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00475     hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
00476                                     (uint16_t)denominator[tx_fifo_threshold];
00477     hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
00478                                     (uint16_t)denominator[rx_fifo_threshold];
00479   }
00480 }
00481
00482 /**
00483   * @}
00484   */
00485
00486 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00487
00488 /**
00489   * @}
00490   */
00491
00492 /**
00493   * @}
00494   */
00495
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smartcard_ex.h Source File

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stm32g0xx_hal_smartcard_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_smartcard_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_SMARTCARD_EX_H
00021 #define STM32G0xx_HAL_SMARTCARD_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SMARTCARDEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040
00041 /** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
00046   * @{
00047   */
00048 #define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
00049 #define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
00050 /**
00051   * @}
00052   */
00053
00054 /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
00055   * @{
00056   */
00057 #define SMARTCARD_ADVFEATURE_NO_INIT                 0x00000000U    /*!< No advanced feature initialization                  */
00058 #define SMARTCARD_ADVFEATURE_TXINVERT_INIT           0x00000001U    /*!< TX pin active level inversion                       */
00059 #define SMARTCARD_ADVFEATURE_RXINVERT_INIT           0x00000002U    /*!< RX pin active level inversion                       */
00060 #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         0x00000004U    /*!< Binary data inversion                               */
00061 #define SMARTCARD_ADVFEATURE_SWAP_INIT               0x00000008U    /*!< TX/RX pins swap                                     */
00062 #define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U    /*!< RX overrun disable                                  */
00063 #define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U    /*!< DMA disable on Reception Error                      */
00064 #define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           0x00000080U    /*!< Most significant bit sent/received first            */
00065 #define SMARTCARD_ADVFEATURE_TXCOMPLETION            0x00000100U    /*!< TX completion indication before of after guard time */
00066 /**
00067   * @}
00068   */
00069
00070 /** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
00071   * @brief    SMARTCARD FIFO mode
00072   * @{
00073   */
00074 #define SMARTCARD_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
00075 #define SMARTCARD_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
00081   * @brief    SMARTCARD TXFIFO level
00082   * @{
00083   */
00084 #define SMARTCARD_TXFIFO_THRESHOLD_1_8    0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00085 #define SMARTCARD_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                        /*!< TXFIFO reaches 1/4 of its depth */
00086 #define SMARTCARD_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                        /*!< TXFIFO reaches 1/2 of its depth */
00087 #define SMARTCARD_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)  /*!< TXFIFO reaches 3/4 of its depth */
00088 #define SMARTCARD_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                        /*!< TXFIFO reaches 7/8 of its depth */
00089 #define SMARTCARD_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)  /*!< TXFIFO becomes empty            */
00090 /**
00091   * @}
00092   */
00093
00094 /** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
00095   * @brief    SMARTCARD RXFIFO level
00096   * @{
00097   */
00098 #define SMARTCARD_RXFIFO_THRESHOLD_1_8   0x00000000U                                /*!< RXFIFO FIFO reaches 1/8 of its depth */
00099 #define SMARTCARD_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                        /*!< RXFIFO FIFO reaches 1/4 of its depth */
00100 #define SMARTCARD_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                        /*!< RXFIFO FIFO reaches 1/2 of its depth */
00101 #define SMARTCARD_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)  /*!< RXFIFO FIFO reaches 3/4 of its depth */
00102 #define SMARTCARD_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                        /*!< RXFIFO FIFO reaches 7/8 of its depth */
00103 #define SMARTCARD_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)  /*!< RXFIFO FIFO becomes full             */
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
00109   *        Elements values convention: 0xXXXX
00110   *           - 0xXXXX  : Flag mask in the ISR register
00111   * @{
00112   */
00113 #define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT         /*!< SMARTCARD transmission complete before guard time completion */
00114 #define SMARTCARD_FLAG_REACK          USART_ISR_REACK         /*!< SMARTCARD receive enable acknowledge flag  */
00115 #define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK         /*!< SMARTCARD transmit enable acknowledge flag */
00116 #define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY          /*!< SMARTCARD busy flag                        */
00117 #define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF          /*!< SMARTCARD end of block flag                */
00118 #define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF          /*!< SMARTCARD receiver timeout flag            */
00119 #define SMARTCARD_FLAG_TXE            USART_ISR_TXE_TXFNF     /*!< SMARTCARD transmit data register empty     */
00120 #define SMARTCARD_FLAG_TXFNF          USART_ISR_TXE_TXFNF     /*!< SMARTCARD TXFIFO not full                  */
00121 #define SMARTCARD_FLAG_TC             USART_ISR_TC            /*!< SMARTCARD transmission complete            */
00122 #define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE_RXFNE    /*!< SMARTCARD read data register not empty     */
00123 #define SMARTCARD_FLAG_RXFNE          USART_ISR_RXNE_RXFNE    /*!< SMARTCARD RXFIFO not empty                 */
00124 #define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE          /*!< SMARTCARD idle line detection              */
00125 #define SMARTCARD_FLAG_ORE            USART_ISR_ORE           /*!< SMARTCARD overrun error                    */
00126 #define SMARTCARD_FLAG_NE             USART_ISR_NE            /*!< SMARTCARD noise error                      */
00127 #define SMARTCARD_FLAG_FE             USART_ISR_FE            /*!< SMARTCARD frame error                      */
00128 #define SMARTCARD_FLAG_PE             USART_ISR_PE            /*!< SMARTCARD parity error                     */
00129 #define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE          /*!< SMARTCARD TXFIFO Empty flag                */
00130 #define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF          /*!< SMARTCARD RXFIFO Full flag                 */
00131 #define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT          /*!< SMARTCARD RXFIFO threshold flag            */
00132 #define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT          /*!< SMARTCARD TXFIFO threshold flag            */
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
00138   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00139   *           - YYYYY  : Interrupt source position in the XX register (5 bits)
00140   *           - XX  : Interrupt source register (2 bits)
00141   *                 - 01: CR1 register
00142   *                 - 10: CR2 register
00143   *                 - 11: CR3 register
00144   *           - ZZZZZ  : Flag position in the ISR register(5 bits)
00145   * @{
00146   */
00147 #define SMARTCARD_IT_PE                     0x0028U           /*!< SMARTCARD parity error interruption                 */
00148 #define SMARTCARD_IT_TXE                    0x0727U           /*!< SMARTCARD transmit data register empty interruption */
00149 #define SMARTCARD_IT_TXFNF                  0x0727U           /*!< SMARTCARD TX FIFO not full interruption             */
00150 #define SMARTCARD_IT_TC                     0x0626U           /*!< SMARTCARD transmission complete interruption        */
00151 #define SMARTCARD_IT_RXNE                   0x0525U           /*!< SMARTCARD read data register not empty interruption */
00152 #define SMARTCARD_IT_RXFNE                  0x0525U           /*!< SMARTCARD RXFIFO not empty interruption             */
00153 #define SMARTCARD_IT_IDLE                   0x0424U           /*!< SMARTCARD idle line detection interruption          */
00154
00155 #define SMARTCARD_IT_ERR                    0x0060U           /*!< SMARTCARD error interruption         */
00156 #define SMARTCARD_IT_ORE                    0x0300U           /*!< SMARTCARD overrun error interruption */
00157 #define SMARTCARD_IT_NE                     0x0200U           /*!< SMARTCARD noise error interruption   */
00158 #define SMARTCARD_IT_FE                     0x0100U           /*!< SMARTCARD frame error interruption   */
00159
00160 #define SMARTCARD_IT_EOB                    0x0C3BU           /*!< SMARTCARD end of block interruption     */
00161 #define SMARTCARD_IT_RTO                    0x0B3AU           /*!< SMARTCARD receiver timeout interruption */
00162 #define SMARTCARD_IT_TCBGT                  0x1978U           /*!< SMARTCARD transmission complete before guard time completion interruption */
00163
00164 #define SMARTCARD_IT_RXFF                    0x183FU          /*!< SMARTCARD RXFIFO full interruption                  */
00165 #define SMARTCARD_IT_TXFE                    0x173EU          /*!< SMARTCARD TXFIFO empty interruption                 */
00166 #define SMARTCARD_IT_RXFT                    0x1A7CU          /*!< SMARTCARD RXFIFO threshold reached interruption     */
00167 #define SMARTCARD_IT_TXFT                    0x1B77U          /*!< SMARTCARD TXFIFO threshold reached interruption     */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
00173   * @{
00174   */
00175 #define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
00176 #define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
00177 #define SMARTCARD_CLEAR_NEF                 USART_ICR_NECF    /*!< SMARTCARD noise error detected clear flag  */
00178 #define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
00179 #define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
00180 #define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< TXFIFO empty Clear Flag                    */
00181 #define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
00182 #define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
00183 #define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
00184 #define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
00185 /**
00186   * @}
00187   */
00188
00189 /**
00190   * @}
00191   */
00192 /* Exported macros -----------------------------------------------------------*/
00193 /* Private macros ------------------------------------------------------------*/
00194 /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
00195   * @{
00196   */
00197
00198 /** @brief  Report the SMARTCARD clock source.
00199   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00200   * @param  __CLOCKSOURCE__ output variable.
00201   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
00202   */
00203 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00204 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00205   do {                                                         \
00206     if((__HANDLE__)->Instance == USART1)                       \
00207     {                                                          \
00208       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00209       {                                                        \
00210         case RCC_USART1CLKSOURCE_PCLK1:                        \
00211           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00212           break;                                               \
00213         case RCC_USART1CLKSOURCE_HSI:                          \
00214           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00215           break;                                               \
00216         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00217           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00218           break;                                               \
00219         case RCC_USART1CLKSOURCE_LSE:                          \
00220           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00221           break;                                               \
00222         default:                                               \
00223           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00224           break;                                               \
00225       }                                                        \
00226     }                                                          \
00227     else if((__HANDLE__)->Instance == USART2)                  \
00228     {                                                          \
00229       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00230       {                                                        \
00231         case RCC_USART2CLKSOURCE_PCLK1:                        \
00232           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00233           break;                                               \
00234         case RCC_USART2CLKSOURCE_HSI:                          \
00235           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00236           break;                                               \
00237         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00238           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00239           break;                                               \
00240         case RCC_USART2CLKSOURCE_LSE:                          \
00241           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00242           break;                                               \
00243         default:                                               \
00244           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00245           break;                                               \
00246       }                                                        \
00247     }                                                          \
00248     else if((__HANDLE__)->Instance == USART3)                  \
00249     {                                                          \
00250       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00251       {                                                        \
00252         case RCC_USART3CLKSOURCE_PCLK1:                        \
00253           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00254           break;                                               \
00255         case RCC_USART3CLKSOURCE_HSI:                          \
00256           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00257           break;                                               \
00258         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00259           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00260           break;                                               \
00261         case RCC_USART3CLKSOURCE_LSE:                          \
00262           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00263           break;                                               \
00264         default:                                               \
00265           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00266           break;                                               \
00267       }                                                        \
00268     }                                                          \
00269     else                                                       \
00270     {                                                          \
00271       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
00272     }                                                          \
00273   } while(0U)
00274 #elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
00275 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00276   do {                                                         \
00277     if((__HANDLE__)->Instance == USART1)                       \
00278     {                                                          \
00279       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00280       {                                                        \
00281         case RCC_USART1CLKSOURCE_PCLK1:                        \
00282           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00283           break;                                               \
00284         case RCC_USART1CLKSOURCE_HSI:                          \
00285           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00286           break;                                               \
00287         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00288           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00289           break;                                               \
00290         case RCC_USART1CLKSOURCE_LSE:                          \
00291           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00292           break;                                               \
00293         default:                                               \
00294           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00295           break;                                               \
00296       }                                                        \
00297     }                                                          \
00298     else if((__HANDLE__)->Instance == USART2)                  \
00299     {                                                          \
00300       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00301       {                                                        \
00302         case RCC_USART2CLKSOURCE_PCLK1:                        \
00303           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00304           break;                                               \
00305         case RCC_USART2CLKSOURCE_HSI:                          \
00306           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00307           break;                                               \
00308         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00309           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00310           break;                                               \
00311         case RCC_USART2CLKSOURCE_LSE:                          \
00312           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00313           break;                                               \
00314         default:                                               \
00315           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00316           break;                                               \
00317       }                                                        \
00318     }                                                          \
00319     else                                                       \
00320     {                                                          \
00321       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
00322     }                                                          \
00323   } while(0U)
00324 #else
00325 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00326   do {                                                         \
00327     if((__HANDLE__)->Instance == USART1)                       \
00328     {                                                          \
00329       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00330       {                                                        \
00331         case RCC_USART1CLKSOURCE_PCLK1:                        \
00332           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00333           break;                                               \
00334         case RCC_USART1CLKSOURCE_HSI:                          \
00335           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00336           break;                                               \
00337         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00338           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00339           break;                                               \
00340         case RCC_USART1CLKSOURCE_LSE:                          \
00341           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00342           break;                                               \
00343         default:                                               \
00344           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00345           break;                                               \
00346       }                                                        \
00347     }                                                          \
00348     else                                                       \
00349     {                                                          \
00350       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
00351     }                                                          \
00352   } while(0U)
00353 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00354 /** @brief  Set the Transmission Completion flag
00355   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00356   * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
00357   *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
00358   *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
00359   * @retval None
00360   */
00361 #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
00362   do {                                                                                                       \
00363     if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
00364     {                                                                                                        \
00365       (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
00366     }                                                                                                        \
00367     else                                                                                                     \
00368     {                                                                                                        \
00369       assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
00370     }                                                                                                        \
00371   } while(0U)
00372
00373 /** @brief  Return the transmission completion flag.
00374   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00375   * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
00376   *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
00377   *        reported.
00378   * @retval Transmission completion flag
00379   */
00380 #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)  \
00381   (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
00382
00383
00384 /** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
00385   * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
00386   * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
00387   */
00388 #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
00389                                                               ((__TXCOMPLETE__) == SMARTCARD_TC))
00390
00391 /** @brief Ensure that SMARTCARD FIFO mode is valid.
00392   * @param __STATE__ SMARTCARD FIFO mode.
00393   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00394   */
00395 #define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
00396                                                 ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
00397
00398 /** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
00399   * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
00400   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00401   */
00402 #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
00403                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
00404                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
00405                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
00406                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
00407                                                       ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
00408
00409 /** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
00410   * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
00411   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00412   */
00413 #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
00414                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
00415                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
00416                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
00417                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
00418                                                       ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
00419
00420 /**
00421   * @}
00422   */
00423
00424 /* Exported functions --------------------------------------------------------*/
00425 /** @addtogroup SMARTCARDEx_Exported_Functions
00426   * @{
00427   */
00428
00429 /* Initialization and de-initialization functions  ****************************/
00430 /* IO operation methods *******************************************************/
00431
00432 /** @addtogroup SMARTCARDEx_Exported_Functions_Group1
00433   * @{
00434   */
00435
00436 /* Peripheral Control functions ***********************************************/
00437 void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
00438 void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
00439 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00440 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00441
00442 /**
00443   * @}
00444   */
00445
00446 /* Exported functions --------------------------------------------------------*/
00447 /** @addtogroup SMARTCARDEx_Exported_Functions_Group2
00448   * @{
00449   */
00450
00451 /* IO operation functions *****************************************************/
00452 void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00453 void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00454
00455 /**
00456   * @}
00457   */
00458
00459 /** @addtogroup SMARTCARDEx_Exported_Functions_Group3
00460   * @{
00461   */
00462
00463 /* Peripheral Control functions ***********************************************/
00464 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
00465 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
00466 HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
00467 HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
00468
00469 /**
00470   * @}
00471   */
00472
00473 /**
00474   * @}
00475   */
00476
00477 /* Private functions ---------------------------------------------------------*/
00478
00479 /**
00480   * @}
00481   */
00482
00483 /**
00484   * @}
00485   */
00486
00487 #ifdef __cplusplus
00488 }
00489 #endif
00490
00491 #endif /* STM32G0xx_HAL_SMARTCARD_EX_H */
00492
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smbus.c Source File

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stm32g0xx_hal_smbus.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_smbus.c
00004   * @author  MCD Application Team
00005   * @brief   SMBUS HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the System Management Bus (SMBus) peripheral,
00008   *          based on I2C principles of operation :
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2018 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025   ==============================================================================
00026                         ##### How to use this driver #####
00027   ==============================================================================
00028     [..]
00029     The SMBUS HAL driver can be used as follows:
00030
00031     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
00032         SMBUS_HandleTypeDef  hsmbus;
00033
00034     (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
00035         (##) Enable the SMBUSx interface clock
00036         (##) SMBUS pins configuration
00037             (+++) Enable the clock for the SMBUS GPIOs
00038             (+++) Configure SMBUS pins as alternate function open-drain
00039         (##) NVIC configuration if you need to use interrupt process
00040             (+++) Configure the SMBUSx interrupt priority
00041             (+++) Enable the NVIC SMBUS IRQ Channel
00042
00043     (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
00044         Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
00045         Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
00046
00047     (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
00048         (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00049              by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
00050
00051     (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
00052
00053     (#) For SMBUS IO operations, only one mode of operations is available within this driver
00054
00055     *** Interrupt mode IO operation ***
00056     ===================================
00057     [..]
00058       (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
00059           using HAL_SMBUS_Master_Transmit_IT()
00060       (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
00061            add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
00062       (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
00063           using HAL_SMBUS_Master_Receive_IT()
00064       (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
00065            add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
00066       (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
00067       (++) The associated previous transfer callback is called at the end of abort process
00068       (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
00069       (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
00070       (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
00071            using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
00072       (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
00073            add their own code to check the Address Match Code and the transmission direction
00074            request by master/host (Write/Read).
00075       (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
00076            add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
00077       (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
00078           using HAL_SMBUS_Slave_Transmit_IT()
00079       (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
00080            add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
00081       (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
00082           using HAL_SMBUS_Slave_Receive_IT()
00083       (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
00084            add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
00085       (+) Enable/Disable the SMBUS alert mode using
00086           HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
00087       (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
00088            add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00089            to check the Alert Error Code using function HAL_SMBUS_GetError()
00090       (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
00091       (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
00092            add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00093            to check the Error Code using function HAL_SMBUS_GetError()
00094
00095      *** SMBUS HAL driver macros list ***
00096      ==================================
00097      [..]
00098        Below the list of most used macros in SMBUS HAL driver.
00099
00100       (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
00101       (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
00102       (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
00103       (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
00104       (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
00105       (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
00106
00107      *** Callback registration ***
00108      =============================================
00109     [..]
00110      The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
00111      allows the user to configure dynamically the driver callbacks.
00112      Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
00113      to register an interrupt callback.
00114     [..]
00115      Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
00116        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00117        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00118        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00119        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00120        (+) ListenCpltCallback   : callback for end of listen mode.
00121        (+) ErrorCallback        : callback for error detection.
00122        (+) MspInitCallback      : callback for Msp Init.
00123        (+) MspDeInitCallback    : callback for Msp DeInit.
00124      This function takes as parameters the HAL peripheral handle, the Callback ID
00125      and a pointer to the user callback function.
00126     [..]
00127      For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
00128     [..]
00129      Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
00130      weak function.
00131      HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
00132      and the Callback ID.
00133      This function allows to reset following callbacks:
00134        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00135        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00136        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00137        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00138        (+) ListenCpltCallback   : callback for end of listen mode.
00139        (+) ErrorCallback        : callback for error detection.
00140        (+) MspInitCallback      : callback for Msp Init.
00141        (+) MspDeInitCallback    : callback for Msp DeInit.
00142     [..]
00143      For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
00144     [..]
00145      By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
00146      all callbacks are set to the corresponding weak functions:
00147      examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
00148      Exception done for MspInit and MspDeInit functions that are
00149      reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
00150      these callbacks are null (not registered beforehand).
00151      If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
00152      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00153     [..]
00154      Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
00155      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00156      in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
00157      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00158      Then, the user first registers the MspInit/MspDeInit user callbacks
00159      using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
00160      or HAL_SMBUS_Init() function.
00161     [..]
00162      When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
00163      not defined, the callback registration feature is not available and all callbacks
00164      are set to the corresponding weak functions.
00165
00166      [..]
00167        (@) You can refer to the SMBUS HAL driver header file for more useful macros
00168
00169   @endverbatim
00170   */
00171
00172 /* Includes ------------------------------------------------------------------*/
00173 #include "stm32g0xx_hal.h"
00174
00175 /** @addtogroup STM32G0xx_HAL_Driver
00176   * @{
00177   */
00178
00179 /** @defgroup SMBUS SMBUS
00180   * @brief SMBUS HAL module driver
00181   * @{
00182   */
00183
00184 #ifdef HAL_SMBUS_MODULE_ENABLED
00185
00186 /* Private typedef -----------------------------------------------------------*/
00187 /* Private constants ---------------------------------------------------------*/
00188 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
00189   * @{
00190   */
00191 #define TIMING_CLEAR_MASK   (0xF0FFFFFFUL)     /*!< SMBUS TIMING clear register Mask */
00192 #define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
00193 #define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
00194 #define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
00195 #define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
00196 #define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
00197 #define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
00198 #define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
00199 #define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
00200 #define MAX_NBYTE_SIZE      255U
00201 /**
00202   * @}
00203   */
00204
00205 /* Private macro -------------------------------------------------------------*/
00206 /* Private variables ---------------------------------------------------------*/
00207 /* Private function prototypes -----------------------------------------------*/
00208 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
00209   * @{
00210   */
00211 /* Private functions to handle flags during polling transfer */
00212 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
00213                                                       FlagStatus Status, uint32_t Timeout);
00214
00215 /* Private functions for SMBUS transfer IRQ handler */
00216 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
00217 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
00218 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
00219
00220 /* Private functions to centralize the enable/disable of Interrupts */
00221 static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
00222 static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
00223
00224 /* Private function to flush TXDR register */
00225 static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus);
00226
00227 /* Private function to handle start, restart or stop a transfer */
00228 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
00229                                  uint32_t Mode, uint32_t Request);
00230
00231 /* Private function to Convert Specific options */
00232 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
00233 /**
00234   * @}
00235   */
00236
00237 /* Exported functions --------------------------------------------------------*/
00238
00239 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
00240   * @{
00241   */
00242
00243 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00244   *  @brief    Initialization and Configuration functions
00245   *
00246 @verbatim
00247  ===============================================================================
00248               ##### Initialization and de-initialization functions #####
00249  ===============================================================================
00250     [..]  This subsection provides a set of functions allowing to initialize and
00251           deinitialize the SMBUSx peripheral:
00252
00253       (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
00254           all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
00255
00256       (+) Call the function HAL_SMBUS_Init() to configure the selected device with
00257           the selected configuration:
00258         (++) Clock Timing
00259         (++) Bus Timeout
00260         (++) Analog Filer mode
00261         (++) Own Address 1
00262         (++) Addressing mode (Master, Slave)
00263         (++) Dual Addressing mode
00264         (++) Own Address 2
00265         (++) Own Address 2 Mask
00266         (++) General call mode
00267         (++) Nostretch mode
00268         (++) Packet Error Check mode
00269         (++) Peripheral mode
00270
00271
00272       (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
00273           of the selected SMBUSx peripheral.
00274
00275       (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
00276           HAL_SMBUS_ConfigDigitalFilter().
00277
00278 @endverbatim
00279   * @{
00280   */
00281
00282 /**
00283   * @brief  Initialize the SMBUS according to the specified parameters
00284   *         in the SMBUS_InitTypeDef and initialize the associated handle.
00285   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00286   *                the configuration information for the specified SMBUS.
00287   * @retval HAL status
00288   */
00289 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
00290 {
00291   /* Check the SMBUS handle allocation */
00292   if (hsmbus == NULL)
00293   {
00294     return HAL_ERROR;
00295   }
00296
00297   /* Check the parameters */
00298   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00299   assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
00300   assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
00301   assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
00302   assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
00303   assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
00304   assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
00305   assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
00306   assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
00307   assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
00308   assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
00309
00310   if (hsmbus->State == HAL_SMBUS_STATE_RESET)
00311   {
00312     /* Allocate lock resource and initialize it */
00313     hsmbus->Lock = HAL_UNLOCKED;
00314
00315 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00316     hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00317     hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00318     hsmbus->SlaveTxCpltCallback  = HAL_SMBUS_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
00319     hsmbus->SlaveRxCpltCallback  = HAL_SMBUS_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
00320     hsmbus->ListenCpltCallback   = HAL_SMBUS_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
00321     hsmbus->ErrorCallback        = HAL_SMBUS_ErrorCallback;        /* Legacy weak ErrorCallback        */
00322     hsmbus->AddrCallback         = HAL_SMBUS_AddrCallback;         /* Legacy weak AddrCallback         */
00323
00324     if (hsmbus->MspInitCallback == NULL)
00325     {
00326       hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit  */
00327     }
00328
00329     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00330     hsmbus->MspInitCallback(hsmbus);
00331 #else
00332     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00333     HAL_SMBUS_MspInit(hsmbus);
00334 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00335   }
00336
00337   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00338
00339   /* Disable the selected SMBUS peripheral */
00340   __HAL_SMBUS_DISABLE(hsmbus);
00341
00342   /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
00343   /* Configure SMBUSx: Frequency range */
00344   hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
00345
00346   /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
00347   /* Configure SMBUSx: Bus Timeout  */
00348   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
00349   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
00350   hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
00351
00352   /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
00353   /* Configure SMBUSx: Own Address1 and ack own address1 mode */
00354   hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00355
00356   if (hsmbus->Init.OwnAddress1 != 0UL)
00357   {
00358     if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
00359     {
00360       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
00361     }
00362     else /* SMBUS_ADDRESSINGMODE_10BIT */
00363     {
00364       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
00365     }
00366   }
00367
00368   /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
00369   /* Configure SMBUSx: Addressing Master mode */
00370   if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
00371   {
00372     hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
00373   }
00374   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
00375   /* AUTOEND and NACK bit will be manage during Transfer process */
00376   hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00377
00378   /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
00379   /* Configure SMBUSx: Dual mode and Own Address2 */
00380   hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
00381                             (hsmbus->Init.OwnAddress2Masks << 8U));
00382
00383   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
00384   /* Configure SMBUSx: Generalcall and NoStretch mode */
00385   hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
00386                            hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
00387                            hsmbus->Init.AnalogFilter);
00388
00389   /* Enable Slave Byte Control only in case of Packet Error Check is enabled
00390      and SMBUS Peripheral is set in Slave mode */
00391   if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
00392       ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
00393        (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
00394   {
00395     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00396   }
00397
00398   /* Enable the selected SMBUS peripheral */
00399   __HAL_SMBUS_ENABLE(hsmbus);
00400
00401   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00402   hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
00403   hsmbus->State = HAL_SMBUS_STATE_READY;
00404
00405   return HAL_OK;
00406 }
00407
00408 /**
00409   * @brief  DeInitialize the SMBUS peripheral.
00410   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00411   *                the configuration information for the specified SMBUS.
00412   * @retval HAL status
00413   */
00414 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
00415 {
00416   /* Check the SMBUS handle allocation */
00417   if (hsmbus == NULL)
00418   {
00419     return HAL_ERROR;
00420   }
00421
00422   /* Check the parameters */
00423   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00424
00425   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00426
00427   /* Disable the SMBUS Peripheral Clock */
00428   __HAL_SMBUS_DISABLE(hsmbus);
00429
00430 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00431   if (hsmbus->MspDeInitCallback == NULL)
00432   {
00433     hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit  */
00434   }
00435
00436   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00437   hsmbus->MspDeInitCallback(hsmbus);
00438 #else
00439   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00440   HAL_SMBUS_MspDeInit(hsmbus);
00441 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00442
00443   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00444   hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
00445   hsmbus->State = HAL_SMBUS_STATE_RESET;
00446
00447   /* Release Lock */
00448   __HAL_UNLOCK(hsmbus);
00449
00450   return HAL_OK;
00451 }
00452
00453 /**
00454   * @brief Initialize the SMBUS MSP.
00455   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00456   *                the configuration information for the specified SMBUS.
00457   * @retval None
00458   */
00459 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
00460 {
00461   /* Prevent unused argument(s) compilation warning */
00462   UNUSED(hsmbus);
00463
00464   /* NOTE : This function should not be modified, when the callback is needed,
00465             the HAL_SMBUS_MspInit could be implemented in the user file
00466    */
00467 }
00468
00469 /**
00470   * @brief DeInitialize the SMBUS MSP.
00471   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00472   *                the configuration information for the specified SMBUS.
00473   * @retval None
00474   */
00475 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
00476 {
00477   /* Prevent unused argument(s) compilation warning */
00478   UNUSED(hsmbus);
00479
00480   /* NOTE : This function should not be modified, when the callback is needed,
00481             the HAL_SMBUS_MspDeInit could be implemented in the user file
00482    */
00483 }
00484
00485 /**
00486   * @brief  Configure Analog noise filter.
00487   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00488   *                the configuration information for the specified SMBUS.
00489   * @param  AnalogFilter This parameter can be one of the following values:
00490   *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
00491   *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
00492   * @retval HAL status
00493   */
00494 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
00495 {
00496   /* Check the parameters */
00497   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00498   assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
00499
00500   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00501   {
00502     /* Process Locked */
00503     __HAL_LOCK(hsmbus);
00504
00505     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00506
00507     /* Disable the selected SMBUS peripheral */
00508     __HAL_SMBUS_DISABLE(hsmbus);
00509
00510     /* Reset ANOFF bit */
00511     hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00512
00513     /* Set analog filter bit*/
00514     hsmbus->Instance->CR1 |= AnalogFilter;
00515
00516     __HAL_SMBUS_ENABLE(hsmbus);
00517
00518     hsmbus->State = HAL_SMBUS_STATE_READY;
00519
00520     /* Process Unlocked */
00521     __HAL_UNLOCK(hsmbus);
00522
00523     return HAL_OK;
00524   }
00525   else
00526   {
00527     return HAL_BUSY;
00528   }
00529 }
00530
00531 /**
00532   * @brief  Configure Digital noise filter.
00533   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00534   *                the configuration information for the specified SMBUS.
00535   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00536   * @retval HAL status
00537   */
00538 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
00539 {
00540   uint32_t tmpreg;
00541
00542   /* Check the parameters */
00543   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00544   assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
00545
00546   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00547   {
00548     /* Process Locked */
00549     __HAL_LOCK(hsmbus);
00550
00551     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00552
00553     /* Disable the selected SMBUS peripheral */
00554     __HAL_SMBUS_DISABLE(hsmbus);
00555
00556     /* Get the old register value */
00557     tmpreg = hsmbus->Instance->CR1;
00558
00559     /* Reset I2C DNF bits [11:8] */
00560     tmpreg &= ~(I2C_CR1_DNF);
00561
00562     /* Set I2Cx DNF coefficient */
00563     tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
00564
00565     /* Store the new register value */
00566     hsmbus->Instance->CR1 = tmpreg;
00567
00568     __HAL_SMBUS_ENABLE(hsmbus);
00569
00570     hsmbus->State = HAL_SMBUS_STATE_READY;
00571
00572     /* Process Unlocked */
00573     __HAL_UNLOCK(hsmbus);
00574
00575     return HAL_OK;
00576   }
00577   else
00578   {
00579     return HAL_BUSY;
00580   }
00581 }
00582
00583 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00584 /**
00585   * @brief  Register a User SMBUS Callback
00586   *         To be used instead of the weak predefined callback
00587   * @note   The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in
00588   *         HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
00589   *         HAL_SMBUS_MSPDEINIT_CB_ID.
00590   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00591   *                the configuration information for the specified SMBUS.
00592   * @param  CallbackID ID of the callback to be registered
00593   *         This parameter can be one of the following values:
00594   *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00595   *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00596   *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00597   *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00598   *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00599   *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
00600   *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
00601   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
00602   * @param  pCallback pointer to the Callback function
00603   * @retval HAL status
00604   */
00605 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
00606                                              HAL_SMBUS_CallbackIDTypeDef CallbackID,
00607                                              pSMBUS_CallbackTypeDef pCallback)
00608 {
00609   HAL_StatusTypeDef status = HAL_OK;
00610
00611   if (pCallback == NULL)
00612   {
00613     /* Update the error code */
00614     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00615
00616     return HAL_ERROR;
00617   }
00618
00619   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00620   {
00621     switch (CallbackID)
00622     {
00623       case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
00624         hsmbus->MasterTxCpltCallback = pCallback;
00625         break;
00626
00627       case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
00628         hsmbus->MasterRxCpltCallback = pCallback;
00629         break;
00630
00631       case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
00632         hsmbus->SlaveTxCpltCallback = pCallback;
00633         break;
00634
00635       case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
00636         hsmbus->SlaveRxCpltCallback = pCallback;
00637         break;
00638
00639       case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
00640         hsmbus->ListenCpltCallback = pCallback;
00641         break;
00642
00643       case HAL_SMBUS_ERROR_CB_ID :
00644         hsmbus->ErrorCallback = pCallback;
00645         break;
00646
00647       case HAL_SMBUS_MSPINIT_CB_ID :
00648         hsmbus->MspInitCallback = pCallback;
00649         break;
00650
00651       case HAL_SMBUS_MSPDEINIT_CB_ID :
00652         hsmbus->MspDeInitCallback = pCallback;
00653         break;
00654
00655       default :
00656         /* Update the error code */
00657         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00658
00659         /* Return error status */
00660         status =  HAL_ERROR;
00661         break;
00662     }
00663   }
00664   else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
00665   {
00666     switch (CallbackID)
00667     {
00668       case HAL_SMBUS_MSPINIT_CB_ID :
00669         hsmbus->MspInitCallback = pCallback;
00670         break;
00671
00672       case HAL_SMBUS_MSPDEINIT_CB_ID :
00673         hsmbus->MspDeInitCallback = pCallback;
00674         break;
00675
00676       default :
00677         /* Update the error code */
00678         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00679
00680         /* Return error status */
00681         status =  HAL_ERROR;
00682         break;
00683     }
00684   }
00685   else
00686   {
00687     /* Update the error code */
00688     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00689
00690     /* Return error status */
00691     status =  HAL_ERROR;
00692   }
00693
00694   return status;
00695 }
00696
00697 /**
00698   * @brief  Unregister an SMBUS Callback
00699   *         SMBUS callback is redirected to the weak predefined callback
00700   * @note   The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in
00701   *         HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
00702   *         HAL_SMBUS_MSPDEINIT_CB_ID
00703   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00704   *                the configuration information for the specified SMBUS.
00705   * @param  CallbackID ID of the callback to be unregistered
00706   *         This parameter can be one of the following values:
00707   *         This parameter can be one of the following values:
00708   *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00709   *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00710   *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00711   *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00712   *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00713   *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
00714   *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
00715   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
00716   * @retval HAL status
00717   */
00718 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
00719                                                HAL_SMBUS_CallbackIDTypeDef CallbackID)
00720 {
00721   HAL_StatusTypeDef status = HAL_OK;
00722
00723   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00724   {
00725     switch (CallbackID)
00726     {
00727       case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
00728         hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00729         break;
00730
00731       case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
00732         hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00733         break;
00734
00735       case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
00736         hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
00737         break;
00738
00739       case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
00740         hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
00741         break;
00742
00743       case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
00744         hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
00745         break;
00746
00747       case HAL_SMBUS_ERROR_CB_ID :
00748         hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback;               /* Legacy weak ErrorCallback        */
00749         break;
00750
00751       case HAL_SMBUS_MSPINIT_CB_ID :
00752         hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
00753         break;
00754
00755       case HAL_SMBUS_MSPDEINIT_CB_ID :
00756         hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
00757         break;
00758
00759       default :
00760         /* Update the error code */
00761         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00762
00763         /* Return error status */
00764         status =  HAL_ERROR;
00765         break;
00766     }
00767   }
00768   else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
00769   {
00770     switch (CallbackID)
00771     {
00772       case HAL_SMBUS_MSPINIT_CB_ID :
00773         hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
00774         break;
00775
00776       case HAL_SMBUS_MSPDEINIT_CB_ID :
00777         hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
00778         break;
00779
00780       default :
00781         /* Update the error code */
00782         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00783
00784         /* Return error status */
00785         status =  HAL_ERROR;
00786         break;
00787     }
00788   }
00789   else
00790   {
00791     /* Update the error code */
00792     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00793
00794     /* Return error status */
00795     status =  HAL_ERROR;
00796   }
00797
00798   return status;
00799 }
00800
00801 /**
00802   * @brief  Register the Slave Address Match SMBUS Callback
00803   *         To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
00804   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00805   *                the configuration information for the specified SMBUS.
00806   * @param  pCallback pointer to the Address Match Callback function
00807   * @retval HAL status
00808   */
00809 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
00810                                                  pSMBUS_AddrCallbackTypeDef pCallback)
00811 {
00812   HAL_StatusTypeDef status = HAL_OK;
00813
00814   if (pCallback == NULL)
00815   {
00816     /* Update the error code */
00817     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00818
00819     return HAL_ERROR;
00820   }
00821
00822   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00823   {
00824     hsmbus->AddrCallback = pCallback;
00825   }
00826   else
00827   {
00828     /* Update the error code */
00829     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00830
00831     /* Return error status */
00832     status =  HAL_ERROR;
00833   }
00834
00835   return status;
00836 }
00837
00838 /**
00839   * @brief  UnRegister the Slave Address Match SMBUS Callback
00840   *         Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
00841   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00842   *                the configuration information for the specified SMBUS.
00843   * @retval HAL status
00844   */
00845 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
00846 {
00847   HAL_StatusTypeDef status = HAL_OK;
00848
00849   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00850   {
00851     hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback  */
00852   }
00853   else
00854   {
00855     /* Update the error code */
00856     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00857
00858     /* Return error status */
00859     status =  HAL_ERROR;
00860   }
00861
00862   return status;
00863 }
00864
00865 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00866
00867 /**
00868   * @}
00869   */
00870
00871 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00872   *  @brief   Data transfers functions
00873   *
00874 @verbatim
00875  ===============================================================================
00876                       ##### IO operation functions #####
00877  ===============================================================================
00878     [..]
00879     This subsection provides a set of functions allowing to manage the SMBUS data
00880     transfers.
00881
00882     (#) Blocking mode function to check if device is ready for usage is :
00883         (++) HAL_SMBUS_IsDeviceReady()
00884
00885     (#) There is only one mode of transfer:
00886        (++) Non-Blocking mode : The communication is performed using Interrupts.
00887             These functions return the status of the transfer startup.
00888             The end of the data processing will be indicated through the
00889             dedicated SMBUS IRQ when using Interrupt mode.
00890
00891     (#) Non-Blocking mode functions with Interrupt are :
00892         (++) HAL_SMBUS_Master_Transmit_IT()
00893         (++) HAL_SMBUS_Master_Receive_IT()
00894         (++) HAL_SMBUS_Slave_Transmit_IT()
00895         (++) HAL_SMBUS_Slave_Receive_IT()
00896         (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
00897         (++) HAL_SMBUS_DisableListen_IT()
00898         (++) HAL_SMBUS_EnableAlert_IT()
00899         (++) HAL_SMBUS_DisableAlert_IT()
00900
00901     (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
00902         (++) HAL_SMBUS_MasterTxCpltCallback()
00903         (++) HAL_SMBUS_MasterRxCpltCallback()
00904         (++) HAL_SMBUS_SlaveTxCpltCallback()
00905         (++) HAL_SMBUS_SlaveRxCpltCallback()
00906         (++) HAL_SMBUS_AddrCallback()
00907         (++) HAL_SMBUS_ListenCpltCallback()
00908         (++) HAL_SMBUS_ErrorCallback()
00909
00910 @endverbatim
00911   * @{
00912   */
00913
00914 /**
00915   * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00916   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00917   *                the configuration information for the specified SMBUS.
00918   * @param  DevAddress Target device address: The device 7 bits address value
00919   *         in datasheet must be shifted to the left before calling the interface
00920   * @param  pData Pointer to data buffer
00921   * @param  Size Amount of data to be sent
00922   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
00923   * @retval HAL status
00924   */
00925 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
00926                                                uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00927 {
00928   uint32_t tmp;
00929
00930   /* Check the parameters */
00931   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00932
00933   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00934   {
00935     /* Process Locked */
00936     __HAL_LOCK(hsmbus);
00937
00938     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00939     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00940     /* Prepare transfer parameters */
00941     hsmbus->pBuffPtr = pData;
00942     hsmbus->XferCount = Size;
00943     hsmbus->XferOptions = XferOptions;
00944
00945     /* In case of Quick command, remove autoend mode */
00946     /* Manage the stop generation by software */
00947     if (hsmbus->pBuffPtr == NULL)
00948     {
00949       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00950     }
00951
00952     if (Size > MAX_NBYTE_SIZE)
00953     {
00954       hsmbus->XferSize = MAX_NBYTE_SIZE;
00955     }
00956     else
00957     {
00958       hsmbus->XferSize = Size;
00959     }
00960
00961     /* Send Slave Address */
00962     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00963     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
00964     {
00965       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
00966                            SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
00967                            SMBUS_GENERATE_START_WRITE);
00968     }
00969     else
00970     {
00971       /* If transfer direction not change, do not generate Restart Condition */
00972       /* Mean Previous state is same as current state */
00973
00974       /* Store current volatile XferOptions, misra rule */
00975       tmp = hsmbus->XferOptions;
00976
00977       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
00978           (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
00979       {
00980         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
00981                              SMBUS_NO_STARTSTOP);
00982       }
00983       /* Else transfer direction change, so generate Restart with new transfer direction */
00984       else
00985       {
00986         /* Convert OTHER_xxx XferOptions if any */
00987         SMBUS_ConvertOtherXferOptions(hsmbus);
00988
00989         /* Handle Transfer */
00990         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
00991                              hsmbus->XferOptions,
00992                              SMBUS_GENERATE_START_WRITE);
00993       }
00994
00995       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
00996       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00997       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
00998       {
00999         hsmbus->XferSize--;
01000         hsmbus->XferCount--;
01001       }
01002     }
01003
01004     /* Process Unlocked */
01005     __HAL_UNLOCK(hsmbus);
01006
01007     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01008               to avoid the risk of SMBUS interrupt handle execution before current
01009               process unlock */
01010     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
01011
01012     return HAL_OK;
01013   }
01014   else
01015   {
01016     return HAL_BUSY;
01017   }
01018 }
01019
01020 /**
01021   * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
01022   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01023   *                the configuration information for the specified SMBUS.
01024   * @param  DevAddress Target device address: The device 7 bits address value
01025   *         in datasheet must be shifted to the left before calling the interface
01026   * @param  pData Pointer to data buffer
01027   * @param  Size Amount of data to be sent
01028   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01029   * @retval HAL status
01030   */
01031 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
01032                                               uint16_t Size, uint32_t XferOptions)
01033 {
01034   uint32_t tmp;
01035
01036   /* Check the parameters */
01037   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01038
01039   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01040   {
01041     /* Process Locked */
01042     __HAL_LOCK(hsmbus);
01043
01044     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
01045     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01046
01047     /* Prepare transfer parameters */
01048     hsmbus->pBuffPtr = pData;
01049     hsmbus->XferCount = Size;
01050     hsmbus->XferOptions = XferOptions;
01051
01052     /* In case of Quick command, remove autoend mode */
01053     /* Manage the stop generation by software */
01054     if (hsmbus->pBuffPtr == NULL)
01055     {
01056       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
01057     }
01058
01059     if (Size > MAX_NBYTE_SIZE)
01060     {
01061       hsmbus->XferSize = MAX_NBYTE_SIZE;
01062     }
01063     else
01064     {
01065       hsmbus->XferSize = Size;
01066     }
01067
01068     /* Send Slave Address */
01069     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01070     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
01071     {
01072       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
01073                            SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
01074                            SMBUS_GENERATE_START_READ);
01075     }
01076     else
01077     {
01078       /* If transfer direction not change, do not generate Restart Condition */
01079       /* Mean Previous state is same as current state */
01080
01081       /* Store current volatile XferOptions, Misra rule */
01082       tmp = hsmbus->XferOptions;
01083
01084       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
01085           (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
01086       {
01087         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
01088                              SMBUS_NO_STARTSTOP);
01089       }
01090       /* Else transfer direction change, so generate Restart with new transfer direction */
01091       else
01092       {
01093         /* Convert OTHER_xxx XferOptions if any */
01094         SMBUS_ConvertOtherXferOptions(hsmbus);
01095
01096         /* Handle Transfer */
01097         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
01098                              hsmbus->XferOptions,
01099                              SMBUS_GENERATE_START_READ);
01100       }
01101     }
01102
01103     /* Process Unlocked */
01104     __HAL_UNLOCK(hsmbus);
01105
01106     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01107               to avoid the risk of SMBUS interrupt handle execution before current
01108               process unlock */
01109     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
01110
01111     return HAL_OK;
01112   }
01113   else
01114   {
01115     return HAL_BUSY;
01116   }
01117 }
01118
01119 /**
01120   * @brief  Abort a master/host SMBUS process communication with Interrupt.
01121   * @note   This abort can be called only if state is ready
01122   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01123   *                the configuration information for the specified SMBUS.
01124   * @param  DevAddress Target device address: The device 7 bits address value
01125   *         in datasheet must be shifted to the left before calling the interface
01126   * @retval HAL status
01127   */
01128 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
01129 {
01130   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01131   {
01132     /* Process Locked */
01133     __HAL_LOCK(hsmbus);
01134
01135     /* Keep the same state as previous */
01136     /* to perform as well the call of the corresponding end of transfer callback */
01137     if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01138     {
01139       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
01140     }
01141     else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01142     {
01143       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
01144     }
01145     else
01146     {
01147       /* Wrong usage of abort function */
01148       /* This function should be used only in case of abort monitored by master device */
01149       return HAL_ERROR;
01150     }
01151     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01152
01153     /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
01154     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
01155     SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
01156
01157     /* Process Unlocked */
01158     __HAL_UNLOCK(hsmbus);
01159
01160     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01161               to avoid the risk of SMBUS interrupt handle execution before current
01162               process unlock */
01163     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01164     {
01165       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
01166     }
01167     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01168     {
01169       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
01170     }
01171     else
01172     {
01173       /* Nothing to do */
01174     }
01175
01176     return HAL_OK;
01177   }
01178   else
01179   {
01180     return HAL_BUSY;
01181   }
01182 }
01183
01184 /**
01185   * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
01186   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01187   *                the configuration information for the specified SMBUS.
01188   * @param  pData Pointer to data buffer
01189   * @param  Size Amount of data to be sent
01190   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01191   * @retval HAL status
01192   */
01193 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
01194                                               uint32_t XferOptions)
01195 {
01196   /* Check the parameters */
01197   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01198
01199   if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01200   {
01201     if ((pData == NULL) || (Size == 0UL))
01202     {
01203       hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
01204       return HAL_ERROR;
01205     }
01206
01207     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
01208     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
01209
01210     /* Process Locked */
01211     __HAL_LOCK(hsmbus);
01212
01213     hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
01214     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01215
01216     /* Set SBC bit to manage Acknowledge at each bit */
01217     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
01218
01219     /* Enable Address Acknowledge */
01220     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01221
01222     /* Prepare transfer parameters */
01223     hsmbus->pBuffPtr = pData;
01224     hsmbus->XferCount = Size;
01225     hsmbus->XferOptions = XferOptions;
01226
01227     /* Convert OTHER_xxx XferOptions if any */
01228     SMBUS_ConvertOtherXferOptions(hsmbus);
01229
01230     if (Size > MAX_NBYTE_SIZE)
01231     {
01232       hsmbus->XferSize = MAX_NBYTE_SIZE;
01233     }
01234     else
01235     {
01236       hsmbus->XferSize = Size;
01237     }
01238
01239     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01240     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
01241     {
01242       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
01243                            SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
01244                            SMBUS_NO_STARTSTOP);
01245     }
01246     else
01247     {
01248       /* Set NBYTE to transmit */
01249       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
01250                            SMBUS_NO_STARTSTOP);
01251
01252       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01253       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01254       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
01255       {
01256         hsmbus->XferSize--;
01257         hsmbus->XferCount--;
01258       }
01259     }
01260
01261     /* Clear ADDR flag after prepare the transfer parameters */
01262     /* This action will generate an acknowledge to the HOST */
01263     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01264
01265     /* Process Unlocked */
01266     __HAL_UNLOCK(hsmbus);
01267
01268     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01269               to avoid the risk of SMBUS interrupt handle execution before current
01270               process unlock */
01271     /* REnable ADDR interrupt */
01272     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
01273
01274     return HAL_OK;
01275   }
01276   else
01277   {
01278     return HAL_BUSY;
01279   }
01280 }
01281
01282 /**
01283   * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
01284   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01285   *                the configuration information for the specified SMBUS.
01286   * @param  pData Pointer to data buffer
01287   * @param  Size Amount of data to be sent
01288   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01289   * @retval HAL status
01290   */
01291 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
01292                                              uint32_t XferOptions)
01293 {
01294   /* Check the parameters */
01295   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01296
01297   if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01298   {
01299     if ((pData == NULL) || (Size == 0UL))
01300     {
01301       hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
01302       return HAL_ERROR;
01303     }
01304
01305     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
01306     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
01307
01308     /* Process Locked */
01309     __HAL_LOCK(hsmbus);
01310
01311     hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
01312     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01313
01314     /* Set SBC bit to manage Acknowledge at each bit */
01315     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
01316
01317     /* Enable Address Acknowledge */
01318     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01319
01320     /* Prepare transfer parameters */
01321     hsmbus->pBuffPtr = pData;
01322     hsmbus->XferSize = Size;
01323     hsmbus->XferCount = Size;
01324     hsmbus->XferOptions = XferOptions;
01325
01326     /* Convert OTHER_xxx XferOptions if any */
01327     SMBUS_ConvertOtherXferOptions(hsmbus);
01328
01329     /* Set NBYTE to receive */
01330     /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
01331     /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
01332     /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
01333     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
01334     if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
01335     {
01336       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
01337                            SMBUS_NO_STARTSTOP);
01338     }
01339     else
01340     {
01341       SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
01342     }
01343
01344     /* Clear ADDR flag after prepare the transfer parameters */
01345     /* This action will generate an acknowledge to the HOST */
01346     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01347
01348     /* Process Unlocked */
01349     __HAL_UNLOCK(hsmbus);
01350
01351     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01352               to avoid the risk of SMBUS interrupt handle execution before current
01353               process unlock */
01354     /* REnable ADDR interrupt */
01355     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
01356
01357     return HAL_OK;
01358   }
01359   else
01360   {
01361     return HAL_BUSY;
01362   }
01363 }
01364
01365 /**
01366   * @brief  Enable the Address listen mode with Interrupt.
01367   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01368   *                the configuration information for the specified SMBUS.
01369   * @retval HAL status
01370   */
01371 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
01372 {
01373   hsmbus->State = HAL_SMBUS_STATE_LISTEN;
01374
01375   /* Enable the Address Match interrupt */
01376   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
01377
01378   return HAL_OK;
01379 }
01380
01381 /**
01382   * @brief  Disable the Address listen mode with Interrupt.
01383   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01384   *                the configuration information for the specified SMBUS.
01385   * @retval HAL status
01386   */
01387 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
01388 {
01389   /* Disable Address listen mode only if a transfer is not ongoing */
01390   if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
01391   {
01392     hsmbus->State = HAL_SMBUS_STATE_READY;
01393
01394     /* Disable the Address Match interrupt */
01395     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
01396
01397     return HAL_OK;
01398   }
01399   else
01400   {
01401     return HAL_BUSY;
01402   }
01403 }
01404
01405 /**
01406   * @brief  Enable the SMBUS alert mode with Interrupt.
01407   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01408   *                the configuration information for the specified SMBUSx peripheral.
01409   * @retval HAL status
01410   */
01411 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01412 {
01413   /* Enable SMBus alert */
01414   hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
01415
01416   /* Clear ALERT flag */
01417   __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
01418
01419   /* Enable Alert Interrupt */
01420   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
01421
01422   return HAL_OK;
01423 }
01424 /**
01425   * @brief  Disable the SMBUS alert mode with Interrupt.
01426   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01427   *                the configuration information for the specified SMBUSx peripheral.
01428   * @retval HAL status
01429   */
01430 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01431 {
01432   /* Enable SMBus alert */
01433   hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
01434
01435   /* Disable Alert Interrupt */
01436   SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
01437
01438   return HAL_OK;
01439 }
01440
01441 /**
01442   * @brief  Check if target device is ready for communication.
01443   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01444   *                the configuration information for the specified SMBUS.
01445   * @param  DevAddress Target device address: The device 7 bits address value
01446   *         in datasheet must be shifted to the left before calling the interface
01447   * @param  Trials Number of trials
01448   * @param  Timeout Timeout duration
01449   * @retval HAL status
01450   */
01451 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
01452                                           uint32_t Timeout)
01453 {
01454   uint32_t tickstart;
01455
01456   __IO uint32_t SMBUS_Trials = 0UL;
01457
01458   FlagStatus tmp1;
01459   FlagStatus tmp2;
01460
01461   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01462   {
01463     if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
01464     {
01465       return HAL_BUSY;
01466     }
01467
01468     /* Process Locked */
01469     __HAL_LOCK(hsmbus);
01470
01471     hsmbus->State = HAL_SMBUS_STATE_BUSY;
01472     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01473
01474     do
01475     {
01476       /* Generate Start */
01477       hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
01478
01479       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01480       /* Wait until STOPF flag is set or a NACK flag is set*/
01481       tickstart = HAL_GetTick();
01482
01483       tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01484       tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
01485
01486       while ((tmp1 == RESET) && (tmp2 == RESET))
01487       {
01488         if (Timeout != HAL_MAX_DELAY)
01489         {
01490           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01491           {
01492             /* Device is ready */
01493             hsmbus->State = HAL_SMBUS_STATE_READY;
01494
01495             /* Update SMBUS error code */
01496             hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
01497
01498             /* Process Unlocked */
01499             __HAL_UNLOCK(hsmbus);
01500             return HAL_ERROR;
01501           }
01502         }
01503
01504         tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01505         tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
01506       }
01507
01508       /* Check if the NACKF flag has not been set */
01509       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
01510       {
01511         /* Wait until STOPF flag is reset */
01512         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01513         {
01514           return HAL_ERROR;
01515         }
01516
01517         /* Clear STOP Flag */
01518         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01519
01520         /* Device is ready */
01521         hsmbus->State = HAL_SMBUS_STATE_READY;
01522
01523         /* Process Unlocked */
01524         __HAL_UNLOCK(hsmbus);
01525
01526         return HAL_OK;
01527       }
01528       else
01529       {
01530         /* Wait until STOPF flag is reset */
01531         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01532         {
01533           return HAL_ERROR;
01534         }
01535
01536         /* Clear NACK Flag */
01537         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01538
01539         /* Clear STOP Flag, auto generated with autoend*/
01540         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01541       }
01542
01543       /* Check if the maximum allowed number of trials has been reached */
01544       if (SMBUS_Trials == Trials)
01545       {
01546         /* Generate Stop */
01547         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01548
01549         /* Wait until STOPF flag is reset */
01550         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01551         {
01552           return HAL_ERROR;
01553         }
01554
01555         /* Clear STOP Flag */
01556         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01557       }
01558
01559       /* Increment Trials */
01560       SMBUS_Trials++;
01561     } while (SMBUS_Trials < Trials);
01562
01563     hsmbus->State = HAL_SMBUS_STATE_READY;
01564
01565     /* Update SMBUS error code */
01566     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
01567
01568     /* Process Unlocked */
01569     __HAL_UNLOCK(hsmbus);
01570
01571     return HAL_ERROR;
01572   }
01573   else
01574   {
01575     return HAL_BUSY;
01576   }
01577 }
01578 /**
01579   * @}
01580   */
01581
01582 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
01583   * @{
01584   */
01585
01586 /**
01587   * @brief  Handle SMBUS event interrupt request.
01588   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01589   *                the configuration information for the specified SMBUS.
01590   * @retval None
01591   */
01592 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01593 {
01594   /* Use a local variable to store the current ISR flags */
01595   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
01596   uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
01597   uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
01598
01599   /* SMBUS in mode Transmitter ---------------------------------------------------*/
01600   if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
01601                                            SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
01602       ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
01603        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
01604        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
01605        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
01606        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01607   {
01608     /* Slave mode selected */
01609     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01610     {
01611       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01612     }
01613     /* Master mode selected */
01614     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01615     {
01616       (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
01617     }
01618     else
01619     {
01620       /* Nothing to do */
01621     }
01622   }
01623
01624   /* SMBUS in mode Receiver ----------------------------------------------------*/
01625   if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
01626                                            SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
01627       ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
01628        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
01629        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
01630        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
01631        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01632   {
01633     /* Slave mode selected */
01634     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01635     {
01636       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01637     }
01638     /* Master mode selected */
01639     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01640     {
01641       (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
01642     }
01643     else
01644     {
01645       /* Nothing to do */
01646     }
01647   }
01648
01649   /* SMBUS in mode Listener Only --------------------------------------------------*/
01650   if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) ||
01651        (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) ||
01652        (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) &&
01653       ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) ||
01654        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
01655        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01656   {
01657     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01658     {
01659       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01660     }
01661   }
01662 }
01663
01664 /**
01665   * @brief  Handle SMBUS error interrupt request.
01666   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01667   *                the configuration information for the specified SMBUS.
01668   * @retval None
01669   */
01670 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01671 {
01672   SMBUS_ITErrorHandler(hsmbus);
01673 }
01674
01675 /**
01676   * @brief  Master Tx Transfer completed callback.
01677   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01678   *                the configuration information for the specified SMBUS.
01679   * @retval None
01680   */
01681 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01682 {
01683   /* Prevent unused argument(s) compilation warning */
01684   UNUSED(hsmbus);
01685
01686   /* NOTE : This function should not be modified, when the callback is needed,
01687             the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
01688    */
01689 }
01690
01691 /**
01692   * @brief  Master Rx Transfer completed callback.
01693   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01694   *                the configuration information for the specified SMBUS.
01695   * @retval None
01696   */
01697 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01698 {
01699   /* Prevent unused argument(s) compilation warning */
01700   UNUSED(hsmbus);
01701
01702   /* NOTE : This function should not be modified, when the callback is needed,
01703             the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
01704    */
01705 }
01706
01707 /** @brief  Slave Tx Transfer completed callback.
01708   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01709   *                the configuration information for the specified SMBUS.
01710   * @retval None
01711   */
01712 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01713 {
01714   /* Prevent unused argument(s) compilation warning */
01715   UNUSED(hsmbus);
01716
01717   /* NOTE : This function should not be modified, when the callback is needed,
01718             the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
01719    */
01720 }
01721
01722 /**
01723   * @brief  Slave Rx Transfer completed callback.
01724   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01725   *                the configuration information for the specified SMBUS.
01726   * @retval None
01727   */
01728 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01729 {
01730   /* Prevent unused argument(s) compilation warning */
01731   UNUSED(hsmbus);
01732
01733   /* NOTE : This function should not be modified, when the callback is needed,
01734             the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
01735    */
01736 }
01737
01738 /**
01739   * @brief  Slave Address Match callback.
01740   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01741   *                the configuration information for the specified SMBUS.
01742   * @param  TransferDirection Master request Transfer Direction (Write/Read)
01743   * @param  AddrMatchCode Address Match Code
01744   * @retval None
01745   */
01746 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
01747                                    uint16_t AddrMatchCode)
01748 {
01749   /* Prevent unused argument(s) compilation warning */
01750   UNUSED(hsmbus);
01751   UNUSED(TransferDirection);
01752   UNUSED(AddrMatchCode);
01753
01754   /* NOTE : This function should not be modified, when the callback is needed,
01755             the HAL_SMBUS_AddrCallback() could be implemented in the user file
01756    */
01757 }
01758
01759 /**
01760   * @brief  Listen Complete callback.
01761   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01762   *                the configuration information for the specified SMBUS.
01763   * @retval None
01764   */
01765 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01766 {
01767   /* Prevent unused argument(s) compilation warning */
01768   UNUSED(hsmbus);
01769
01770   /* NOTE : This function should not be modified, when the callback is needed,
01771             the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
01772    */
01773 }
01774
01775 /**
01776   * @brief  SMBUS error callback.
01777   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01778   *                the configuration information for the specified SMBUS.
01779   * @retval None
01780   */
01781 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
01782 {
01783   /* Prevent unused argument(s) compilation warning */
01784   UNUSED(hsmbus);
01785
01786   /* NOTE : This function should not be modified, when the callback is needed,
01787             the HAL_SMBUS_ErrorCallback() could be implemented in the user file
01788    */
01789 }
01790
01791 /**
01792   * @}
01793   */
01794
01795 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
01796   *  @brief   Peripheral State and Errors functions
01797   *
01798 @verbatim
01799  ===============================================================================
01800             ##### Peripheral State and Errors functions #####
01801  ===============================================================================
01802     [..]
01803     This subsection permits to get in run-time the status of the peripheral
01804     and the data flow.
01805
01806 @endverbatim
01807   * @{
01808   */
01809
01810 /**
01811   * @brief  Return the SMBUS handle state.
01812   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01813   *                the configuration information for the specified SMBUS.
01814   * @retval HAL state
01815   */
01816 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
01817 {
01818   /* Return SMBUS handle state */
01819   return hsmbus->State;
01820 }
01821
01822 /**
01823   * @brief  Return the SMBUS error code.
01824   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01825   *              the configuration information for the specified SMBUS.
01826   * @retval SMBUS Error Code
01827   */
01828 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
01829 {
01830   return hsmbus->ErrorCode;
01831 }
01832
01833 /**
01834   * @}
01835   */
01836
01837 /**
01838   * @}
01839   */
01840
01841 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
01842   *  @brief   Data transfers Private functions
01843   * @{
01844   */
01845
01846 /**
01847   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
01848   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01849   *                the configuration information for the specified SMBUS.
01850   * @param  StatusFlags Value of Interrupt Flags.
01851   * @retval HAL status
01852   */
01853 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
01854 {
01855   uint16_t DevAddress;
01856
01857   /* Process Locked */
01858   __HAL_LOCK(hsmbus);
01859
01860   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
01861   {
01862     /* Clear NACK Flag */
01863     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01864
01865     /* Set corresponding Error Code */
01866     /* No need to generate STOP, it is automatically done */
01867     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01868
01869     /* Flush TX register */
01870     SMBUS_Flush_TXDR(hsmbus);
01871
01872     /* Process Unlocked */
01873     __HAL_UNLOCK(hsmbus);
01874
01875     /* Call the Error callback to inform upper layer */
01876 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01877     hsmbus->ErrorCallback(hsmbus);
01878 #else
01879     HAL_SMBUS_ErrorCallback(hsmbus);
01880 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01881   }
01882   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
01883   {
01884     /* Check and treat errors if errors occurs during STOP process */
01885     SMBUS_ITErrorHandler(hsmbus);
01886
01887     /* Call the corresponding callback to inform upper layer of End of Transfer */
01888     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01889     {
01890       /* Disable Interrupt */
01891       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01892
01893       /* Clear STOP Flag */
01894       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01895
01896       /* Clear Configuration Register 2 */
01897       SMBUS_RESET_CR2(hsmbus);
01898
01899       /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
01900       /* Disable the selected SMBUS peripheral */
01901       __HAL_SMBUS_DISABLE(hsmbus);
01902
01903       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01904       hsmbus->State = HAL_SMBUS_STATE_READY;
01905
01906       /* Process Unlocked */
01907       __HAL_UNLOCK(hsmbus);
01908
01909       /* Re-enable the selected SMBUS peripheral */
01910       __HAL_SMBUS_ENABLE(hsmbus);
01911
01912       /* Call the corresponding callback to inform upper layer of End of Transfer */
01913 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01914       hsmbus->MasterTxCpltCallback(hsmbus);
01915 #else
01916       HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01917 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01918     }
01919     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01920     {
01921       /* Store Last receive data if any */
01922       if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
01923       {
01924         /* Read data from RXDR */
01925         *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
01926
01927         /* Increment Buffer pointer */
01928         hsmbus->pBuffPtr++;
01929
01930         if ((hsmbus->XferSize > 0U))
01931         {
01932           hsmbus->XferSize--;
01933           hsmbus->XferCount--;
01934         }
01935       }
01936
01937       /* Disable Interrupt */
01938       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01939
01940       /* Clear STOP Flag */
01941       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01942
01943       /* Clear Configuration Register 2 */
01944       SMBUS_RESET_CR2(hsmbus);
01945
01946       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01947       hsmbus->State = HAL_SMBUS_STATE_READY;
01948
01949       /* Process Unlocked */
01950       __HAL_UNLOCK(hsmbus);
01951
01952       /* Call the corresponding callback to inform upper layer of End of Transfer */
01953 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01954       hsmbus->MasterRxCpltCallback(hsmbus);
01955 #else
01956       HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01957 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01958     }
01959     else
01960     {
01961       /* Nothing to do */
01962     }
01963   }
01964   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
01965   {
01966     /* Read data from RXDR */
01967     *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
01968
01969     /* Increment Buffer pointer */
01970     hsmbus->pBuffPtr++;
01971
01972     /* Increment Size counter */
01973     hsmbus->XferSize--;
01974     hsmbus->XferCount--;
01975   }
01976   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
01977   {
01978     /* Write data to TXDR */
01979     hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
01980
01981     /* Increment Buffer pointer */
01982     hsmbus->pBuffPtr++;
01983
01984     /* Increment Size counter */
01985     hsmbus->XferSize--;
01986     hsmbus->XferCount--;
01987   }
01988   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
01989   {
01990     if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
01991     {
01992       DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
01993
01994       if (hsmbus->XferCount > MAX_NBYTE_SIZE)
01995       {
01996         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
01997                              (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
01998                              SMBUS_NO_STARTSTOP);
01999         hsmbus->XferSize = MAX_NBYTE_SIZE;
02000       }
02001       else
02002       {
02003         hsmbus->XferSize = hsmbus->XferCount;
02004         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
02005                              SMBUS_NO_STARTSTOP);
02006         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
02007         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
02008         if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
02009         {
02010           hsmbus->XferSize--;
02011           hsmbus->XferCount--;
02012         }
02013       }
02014     }
02015     else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
02016     {
02017       /* Call TxCpltCallback() if no stop mode is set */
02018       if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
02019       {
02020         /* Call the corresponding callback to inform upper layer of End of Transfer */
02021         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
02022         {
02023           /* Disable Interrupt */
02024           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02025           hsmbus->PreviousState = hsmbus->State;
02026           hsmbus->State = HAL_SMBUS_STATE_READY;
02027
02028           /* Process Unlocked */
02029           __HAL_UNLOCK(hsmbus);
02030
02031           /* Call the corresponding callback to inform upper layer of End of Transfer */
02032 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02033           hsmbus->MasterTxCpltCallback(hsmbus);
02034 #else
02035           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
02036 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02037         }
02038         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
02039         {
02040           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02041           hsmbus->PreviousState = hsmbus->State;
02042           hsmbus->State = HAL_SMBUS_STATE_READY;
02043
02044           /* Process Unlocked */
02045           __HAL_UNLOCK(hsmbus);
02046
02047           /* Call the corresponding callback to inform upper layer of End of Transfer */
02048 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02049           hsmbus->MasterRxCpltCallback(hsmbus);
02050 #else
02051           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
02052 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02053         }
02054         else
02055         {
02056           /* Nothing to do */
02057         }
02058       }
02059     }
02060     else
02061     {
02062       /* Nothing to do */
02063     }
02064   }
02065   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
02066   {
02067     if (hsmbus->XferCount == 0U)
02068     {
02069       /* Specific use case for Quick command */
02070       if (hsmbus->pBuffPtr == NULL)
02071       {
02072         /* Generate a Stop command */
02073         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
02074       }
02075       /* Call TxCpltCallback() if no stop mode is set */
02076       else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
02077       {
02078         /* No Generate Stop, to permit restart mode */
02079         /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
02080
02081         /* Call the corresponding callback to inform upper layer of End of Transfer */
02082         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
02083         {
02084           /* Disable Interrupt */
02085           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02086           hsmbus->PreviousState = hsmbus->State;
02087           hsmbus->State = HAL_SMBUS_STATE_READY;
02088
02089           /* Process Unlocked */
02090           __HAL_UNLOCK(hsmbus);
02091
02092           /* Call the corresponding callback to inform upper layer of End of Transfer */
02093 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02094           hsmbus->MasterTxCpltCallback(hsmbus);
02095 #else
02096           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
02097 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02098         }
02099         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
02100         {
02101           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02102           hsmbus->PreviousState = hsmbus->State;
02103           hsmbus->State = HAL_SMBUS_STATE_READY;
02104
02105           /* Process Unlocked */
02106           __HAL_UNLOCK(hsmbus);
02107
02108           /* Call the corresponding callback to inform upper layer of End of Transfer */
02109 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02110           hsmbus->MasterRxCpltCallback(hsmbus);
02111 #else
02112           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
02113 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02114         }
02115         else
02116         {
02117           /* Nothing to do */
02118         }
02119       }
02120       else
02121       {
02122         /* Nothing to do */
02123       }
02124     }
02125   }
02126   else
02127   {
02128     /* Nothing to do */
02129   }
02130
02131   /* Process Unlocked */
02132   __HAL_UNLOCK(hsmbus);
02133
02134   return HAL_OK;
02135 }
02136 /**
02137   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
02138   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02139   *                the configuration information for the specified SMBUS.
02140   * @param  StatusFlags Value of Interrupt Flags.
02141   * @retval HAL status
02142   */
02143 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
02144 {
02145   uint8_t TransferDirection;
02146   uint16_t SlaveAddrCode;
02147
02148   /* Process Locked */
02149   __HAL_LOCK(hsmbus);
02150
02151   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
02152   {
02153     /* Check that SMBUS transfer finished */
02154     /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
02155     /* Mean XferCount == 0*/
02156     /* So clear Flag NACKF only */
02157     if (hsmbus->XferCount == 0U)
02158     {
02159       /* Clear NACK Flag */
02160       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
02161
02162       /* Flush TX register */
02163       SMBUS_Flush_TXDR(hsmbus);
02164
02165       /* Process Unlocked */
02166       __HAL_UNLOCK(hsmbus);
02167     }
02168     else
02169     {
02170       /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
02171       /* Clear NACK Flag */
02172       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
02173
02174       /* Set HAL State to "Idle" State, mean to LISTEN state */
02175       /* So reset Slave Busy state */
02176       hsmbus->PreviousState = hsmbus->State;
02177       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
02178       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
02179
02180       /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
02181       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
02182
02183       /* Set ErrorCode corresponding to a Non-Acknowledge */
02184       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
02185
02186       /* Flush TX register */
02187       SMBUS_Flush_TXDR(hsmbus);
02188
02189       /* Process Unlocked */
02190       __HAL_UNLOCK(hsmbus);
02191
02192       /* Call the Error callback to inform upper layer */
02193 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02194       hsmbus->ErrorCallback(hsmbus);
02195 #else
02196       HAL_SMBUS_ErrorCallback(hsmbus);
02197 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02198     }
02199   }
02200   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
02201   {
02202     TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
02203     SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
02204
02205     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
02206     /* Other ADDRInterrupt will be treat in next Listen usecase */
02207     __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
02208
02209     /* Process Unlocked */
02210     __HAL_UNLOCK(hsmbus);
02211
02212     /* Call Slave Addr callback */
02213 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02214     hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
02215 #else
02216     HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
02217 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02218   }
02219   else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) ||
02220            (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
02221   {
02222     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
02223     {
02224       /* Read data from RXDR */
02225       *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02226
02227       /* Increment Buffer pointer */
02228       hsmbus->pBuffPtr++;
02229
02230       hsmbus->XferSize--;
02231       hsmbus->XferCount--;
02232
02233       if (hsmbus->XferCount == 1U)
02234       {
02235         /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
02236         /* or only the last Byte of Transfer */
02237         /* So reset the RELOAD bit mode */
02238         hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
02239         SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
02240       }
02241       else if (hsmbus->XferCount == 0U)
02242       {
02243         /* Last Byte is received, disable Interrupt */
02244         SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02245
02246         /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
02247         hsmbus->PreviousState = hsmbus->State;
02248         hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
02249
02250         /* Process Unlocked */
02251         __HAL_UNLOCK(hsmbus);
02252
02253         /* Call the corresponding callback to inform upper layer of End of Transfer */
02254 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02255         hsmbus->SlaveRxCpltCallback(hsmbus);
02256 #else
02257         HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
02258 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02259       }
02260       else
02261       {
02262         /* Set Reload for next Bytes */
02263         SMBUS_TransferConfig(hsmbus, 0, 1,
02264                              SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
02265                              SMBUS_NO_STARTSTOP);
02266
02267         /* Ack last Byte Read */
02268         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
02269       }
02270     }
02271     else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02272     {
02273       if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
02274       {
02275         if (hsmbus->XferCount > MAX_NBYTE_SIZE)
02276         {
02277           SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
02278                                (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
02279                                SMBUS_NO_STARTSTOP);
02280           hsmbus->XferSize = MAX_NBYTE_SIZE;
02281         }
02282         else
02283         {
02284           hsmbus->XferSize = hsmbus->XferCount;
02285           SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
02286                                SMBUS_NO_STARTSTOP);
02287           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
02288           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
02289           if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
02290           {
02291             hsmbus->XferSize--;
02292             hsmbus->XferCount--;
02293           }
02294         }
02295       }
02296     }
02297     else
02298     {
02299       /* Nothing to do */
02300     }
02301   }
02302   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
02303   {
02304     /* Write data to TXDR only if XferCount not reach "0" */
02305     /* A TXIS flag can be set, during STOP treatment      */
02306     /* Check if all Data have already been sent */
02307     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
02308     if (hsmbus->XferCount > 0U)
02309     {
02310       /* Write data to TXDR */
02311       hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
02312
02313       /* Increment Buffer pointer */
02314       hsmbus->pBuffPtr++;
02315
02316       hsmbus->XferCount--;
02317       hsmbus->XferSize--;
02318     }
02319
02320     if (hsmbus->XferCount == 0U)
02321     {
02322       /* Last Byte is Transmitted */
02323       /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
02324       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02325       hsmbus->PreviousState = hsmbus->State;
02326       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
02327
02328       /* Process Unlocked */
02329       __HAL_UNLOCK(hsmbus);
02330
02331       /* Call the corresponding callback to inform upper layer of End of Transfer */
02332 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02333       hsmbus->SlaveTxCpltCallback(hsmbus);
02334 #else
02335       HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
02336 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02337     }
02338   }
02339   else
02340   {
02341     /* Nothing to do */
02342   }
02343
02344   /* Check if STOPF is set */
02345   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
02346   {
02347     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
02348     {
02349       /* Store Last receive data if any */
02350       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
02351       {
02352         /* Read data from RXDR */
02353         *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02354
02355         /* Increment Buffer pointer */
02356         hsmbus->pBuffPtr++;
02357
02358         if ((hsmbus->XferSize > 0U))
02359         {
02360           hsmbus->XferSize--;
02361           hsmbus->XferCount--;
02362         }
02363       }
02364
02365       /* Disable RX and TX Interrupts */
02366       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
02367
02368       /* Disable ADDR Interrupt */
02369       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
02370
02371       /* Disable Address Acknowledge */
02372       hsmbus->Instance->CR2 |= I2C_CR2_NACK;
02373
02374       /* Clear Configuration Register 2 */
02375       SMBUS_RESET_CR2(hsmbus);
02376
02377       /* Clear STOP Flag */
02378       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
02379
02380       /* Clear ADDR flag */
02381       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
02382
02383       hsmbus->XferOptions = 0;
02384       hsmbus->PreviousState = hsmbus->State;
02385       hsmbus->State = HAL_SMBUS_STATE_READY;
02386
02387       /* Process Unlocked */
02388       __HAL_UNLOCK(hsmbus);
02389
02390       /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
02391 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02392       hsmbus->ListenCpltCallback(hsmbus);
02393 #else
02394       HAL_SMBUS_ListenCpltCallback(hsmbus);
02395 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02396     }
02397   }
02398
02399   /* Process Unlocked */
02400   __HAL_UNLOCK(hsmbus);
02401
02402   return HAL_OK;
02403 }
02404 /**
02405   * @brief  Manage the enabling of Interrupts.
02406   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02407   *                the configuration information for the specified SMBUS.
02408   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
02409   * @retval HAL status
02410   */
02411 static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
02412 {
02413   uint32_t tmpisr = 0UL;
02414
02415   if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
02416   {
02417     /* Enable ERR interrupt */
02418     tmpisr |= SMBUS_IT_ERRI;
02419   }
02420
02421   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
02422   {
02423     /* Enable ADDR, STOP interrupt */
02424     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
02425   }
02426
02427   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
02428   {
02429     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02430     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
02431   }
02432
02433   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
02434   {
02435     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02436     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
02437   }
02438
02439   /* Enable interrupts only at the end */
02440   /* to avoid the risk of SMBUS interrupt handle execution before */
02441   /* all interrupts requested done */
02442   __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
02443 }
02444 /**
02445   * @brief  Manage the disabling of Interrupts.
02446   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02447   *                the configuration information for the specified SMBUS.
02448   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
02449   * @retval HAL status
02450   */
02451 static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
02452 {
02453   uint32_t tmpisr = 0UL;
02454   uint32_t tmpstate = hsmbus->State;
02455
02456   if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
02457   {
02458     /* Disable ERR interrupt */
02459     tmpisr |= SMBUS_IT_ERRI;
02460   }
02461
02462   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
02463   {
02464     /* Disable TC, STOP, NACK and TXI interrupt */
02465     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
02466
02467     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02468         && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
02469     {
02470       /* Disable ERR interrupt */
02471       tmpisr |= SMBUS_IT_ERRI;
02472     }
02473
02474     if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
02475     {
02476       /* Disable STOP and NACK interrupt */
02477       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02478     }
02479   }
02480
02481   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
02482   {
02483     /* Disable TC, STOP, NACK and RXI interrupt */
02484     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
02485
02486     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02487         && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
02488     {
02489       /* Disable ERR interrupt */
02490       tmpisr |= SMBUS_IT_ERRI;
02491     }
02492
02493     if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
02494     {
02495       /* Disable STOP and NACK interrupt */
02496       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02497     }
02498   }
02499
02500   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
02501   {
02502     /* Disable ADDR, STOP and NACK interrupt */
02503     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02504
02505     if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02506     {
02507       /* Disable ERR interrupt */
02508       tmpisr |= SMBUS_IT_ERRI;
02509     }
02510   }
02511
02512   /* Disable interrupts only at the end */
02513   /* to avoid a breaking situation like at "t" time */
02514   /* all disable interrupts request are not done */
02515   __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
02516 }
02517
02518 /**
02519   * @brief  SMBUS interrupts error handler.
02520   * @param  hsmbus SMBUS handle.
02521   * @retval None
02522   */
02523 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
02524 {
02525   uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
02526   uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
02527   uint32_t tmpstate;
02528   uint32_t tmperror;
02529
02530   /* SMBUS Bus error interrupt occurred ------------------------------------*/
02531   if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
02532       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02533   {
02534     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
02535
02536     /* Clear BERR flag */
02537     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
02538   }
02539
02540   /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02541   if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
02542       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02543   {
02544     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
02545
02546     /* Clear OVR flag */
02547     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
02548   }
02549
02550   /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
02551   if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
02552       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02553   {
02554     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
02555
02556     /* Clear ARLO flag */
02557     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
02558   }
02559
02560   /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
02561   if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
02562       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02563   {
02564     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
02565
02566     /* Clear TIMEOUT flag */
02567     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
02568   }
02569
02570   /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
02571   if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
02572       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02573   {
02574     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
02575
02576     /* Clear ALERT flag */
02577     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
02578   }
02579
02580   /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
02581   if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
02582       ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02583   {
02584     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
02585
02586     /* Clear PEC error flag */
02587     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
02588   }
02589
02590   /* Flush TX register */
02591   SMBUS_Flush_TXDR(hsmbus);
02592
02593   /* Store current volatile hsmbus->ErrorCode, misra rule */
02594   tmperror = hsmbus->ErrorCode;
02595
02596   /* Call the Error Callback in case of Error detected */
02597   if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
02598   {
02599     /* Do not Reset the HAL state in case of ALERT error */
02600     if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
02601     {
02602       /* Store current volatile hsmbus->State, misra rule */
02603       tmpstate = hsmbus->State;
02604
02605       if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02606           || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
02607       {
02608         /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
02609         /* keep HAL_SMBUS_STATE_LISTEN if set */
02610         hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
02611         hsmbus->State = HAL_SMBUS_STATE_LISTEN;
02612       }
02613     }
02614
02615     /* Call the Error callback to inform upper layer */
02616 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02617     hsmbus->ErrorCallback(hsmbus);
02618 #else
02619     HAL_SMBUS_ErrorCallback(hsmbus);
02620 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02621   }
02622 }
02623
02624 /**
02625   * @brief  Handle SMBUS Communication Timeout.
02626   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02627   *                the configuration information for the specified SMBUS.
02628   * @param  Flag Specifies the SMBUS flag to check.
02629   * @param  Status The new Flag status (SET or RESET).
02630   * @param  Timeout Timeout duration
02631   * @retval HAL status
02632   */
02633 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
02634                                                       FlagStatus Status, uint32_t Timeout)
02635 {
02636   uint32_t tickstart = HAL_GetTick();
02637
02638   /* Wait until flag is set */
02639   while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
02640   {
02641     /* Check for the Timeout */
02642     if (Timeout != HAL_MAX_DELAY)
02643     {
02644       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
02645       {
02646         hsmbus->PreviousState = hsmbus->State;
02647         hsmbus->State = HAL_SMBUS_STATE_READY;
02648
02649         /* Update SMBUS error code */
02650         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
02651
02652         /* Process Unlocked */
02653         __HAL_UNLOCK(hsmbus);
02654
02655         return HAL_ERROR;
02656       }
02657     }
02658   }
02659
02660   return HAL_OK;
02661 }
02662
02663 /**
02664   * @brief  SMBUS Tx data register flush process.
02665   * @param  hsmbus SMBUS handle.
02666   * @retval None
02667   */
02668 static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus)
02669 {
02670   /* If a pending TXIS flag is set */
02671   /* Write a dummy data in TXDR to clear it */
02672   if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
02673   {
02674     hsmbus->Instance->TXDR = 0x00U;
02675   }
02676
02677   /* Flush TX register if not empty */
02678   if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET)
02679   {
02680     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE);
02681   }
02682 }
02683
02684 /**
02685   * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
02686   * @param  hsmbus SMBUS handle.
02687   * @param  DevAddress specifies the slave address to be programmed.
02688   * @param  Size specifies the number of bytes to be programmed.
02689   *   This parameter must be a value between 0 and 255.
02690   * @param  Mode New state of the SMBUS START condition generation.
02691   *   This parameter can be one or a combination  of the following values:
02692   *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
02693   *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
02694   *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
02695   *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
02696   * @param  Request New state of the SMBUS START condition generation.
02697   *   This parameter can be one of the following values:
02698   *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
02699   *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
02700   *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
02701   *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
02702   * @retval None
02703   */
02704 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
02705                                  uint32_t Mode, uint32_t Request)
02706 {
02707   /* Check the parameters */
02708   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
02709   assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
02710   assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
02711
02712   /* update CR2 register */
02713   MODIFY_REG(hsmbus->Instance->CR2,
02714              ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
02715                (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
02716                I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
02717              (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
02718                         (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
02719                         (uint32_t)Mode | (uint32_t)Request));
02720 }
02721
02722 /**
02723   * @brief  Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
02724   * @param  hsmbus SMBUS handle.
02725   * @retval None
02726   */
02727 static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
02728 {
02729   /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
02730   /* it request implicitly to generate a restart condition */
02731   /* set XferOptions to SMBUS_FIRST_FRAME                  */
02732   if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
02733   {
02734     hsmbus->XferOptions = SMBUS_FIRST_FRAME;
02735   }
02736   /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
02737   /* it request implicitly to generate a restart condition      */
02738   /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
02739   else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
02740   {
02741     hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
02742   }
02743   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
02744   /* it request implicitly to generate a restart condition             */
02745   /* then generate a stop condition at the end of transfer             */
02746   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
02747   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
02748   {
02749     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
02750   }
02751   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
02752   /* it request implicitly to generate a restart condition               */
02753   /* then generate a stop condition at the end of transfer               */
02754   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
02755   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
02756   {
02757     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
02758   }
02759   else
02760   {
02761     /* Nothing to do */
02762   }
02763 }
02764 /**
02765   * @}
02766   */
02767
02768 #endif /* HAL_SMBUS_MODULE_ENABLED */
02769 /**
02770   * @}
02771   */
02772
02773 /**
02774   * @}
02775   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smbus.h Source File

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stm32g0xx_hal_smbus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_smbus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMBUS HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_SMBUS_H
00021 #define STM32G0xx_HAL_SMBUS_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SMBUS
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
00040   * @{
00041   */
00042
00043 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
00044   * @brief  SMBUS Configuration Structure definition
00045   * @{
00046   */
00047 typedef struct
00048 {
00049   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
00050                                         This parameter calculated by referring to SMBUS initialization section
00051                                         in Reference manual */
00052   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
00053                                         This parameter can be a value of @ref SMBUS_Analog_Filter */
00054
00055   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
00056                                         This parameter can be a 7-bit or 10-bit address. */
00057
00058   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
00059                                         This parameter can be a value of @ref SMBUS_addressing_mode */
00060
00061   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
00062                                         This parameter can be a value of @ref SMBUS_dual_addressing_mode */
00063
00064   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
00065                                         This parameter can be a 7-bit address. */
00066
00067   uint32_t OwnAddress2Masks;       /*!< Specifies the acknowledge mask address second device own address
00068                                         if dual addressing mode is selected
00069                                         This parameter can be a value of @ref SMBUS_own_address2_masks. */
00070
00071   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
00072                                         This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
00073
00074   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
00075                                         This parameter can be a value of @ref SMBUS_nostretch_mode */
00076
00077   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
00078                                         This parameter can be a value of @ref SMBUS_packet_error_check_mode */
00079
00080   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
00081                                         This parameter can be a value of @ref SMBUS_peripheral_mode */
00082
00083   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
00084                                         (Enable bits and different timeout values)
00085                                         This parameter calculated by referring to SMBUS initialization section
00086                                         in Reference manual */
00087 } SMBUS_InitTypeDef;
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup HAL_state_definition HAL state definition
00093   * @brief  HAL State definition
00094   * @{
00095   */
00096 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
00097 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
00098 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
00099 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
00100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
00101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
00102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
00103 #define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
00104 #define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
00105 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)  /*!< Address Listen Mode is ongoing                */
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
00111   * @brief  SMBUS Error Code definition
00112   * @{
00113   */
00114 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
00115 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
00116 #define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
00117 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
00118 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
00119 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
00120 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
00121 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
00122 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
00123 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00124 #define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)  /*!< Invalid Callback error   */
00125 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00126 #define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
00132   * @brief  SMBUS handle Structure definition
00133   * @{
00134   */
00135 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00136 typedef struct __SMBUS_HandleTypeDef
00137 #else
00138 typedef struct
00139 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00140 {
00141   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
00142
00143   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
00144
00145   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
00146
00147   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
00148
00149   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
00150
00151   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
00152
00153   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
00154
00155   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
00156
00157   __IO uint32_t                State;           /*!< SMBUS communication state          */
00158
00159   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
00160
00161 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00162   void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00163   /*!< SMBUS Master Tx Transfer completed callback */
00164   void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00165   /*!< SMBUS Master Rx Transfer completed callback */
00166   void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00167   /*!< SMBUS Slave Tx Transfer completed callback  */
00168   void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00169   /*!< SMBUS Slave Rx Transfer completed callback  */
00170   void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00171   /*!< SMBUS Listen Complete callback              */
00172   void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00173   /*!< SMBUS Error callback                        */
00174
00175   void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00176   /*!< SMBUS Slave Address Match callback */
00177
00178   void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00179   /*!< SMBUS Msp Init callback                     */
00180   void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
00181   /*!< SMBUS Msp DeInit callback                   */
00182
00183 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00184 } SMBUS_HandleTypeDef;
00185
00186 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00187 /**
00188   * @brief  HAL SMBUS Callback ID enumeration definition
00189   */
00190 typedef enum
00191 {
00192   HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */
00193   HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */
00194   HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */
00195   HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */
00196   HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */
00197   HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */
00198
00199   HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */
00200   HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */
00201
00202 } HAL_SMBUS_CallbackIDTypeDef;
00203
00204 /**
00205   * @brief  HAL SMBUS Callback pointer definition
00206   */
00207 typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
00208 /*!< pointer to an SMBUS callback function */
00209 typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
00210                                             uint16_t AddrMatchCode);
00211 /*!< pointer to an SMBUS Address Match callback function */
00212
00213 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00214 /**
00215   * @}
00216   */
00217
00218 /**
00219   * @}
00220   */
00221 /* Exported constants --------------------------------------------------------*/
00222
00223 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
00224   * @{
00225   */
00226
00227 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
00228   * @{
00229   */
00230 #define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
00231 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
00237   * @{
00238   */
00239 #define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
00240 #define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
00246   * @{
00247   */
00248
00249 #define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
00250 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
00256   * @{
00257   */
00258
00259 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
00260 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
00261 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
00262 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
00263 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
00264 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
00265 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
00266 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
00267 /**
00268   * @}
00269   */
00270
00271
00272 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
00273   * @{
00274   */
00275 #define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
00276 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
00282   * @{
00283   */
00284 #define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
00285 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
00291   * @{
00292   */
00293 #define SMBUS_PEC_DISABLE                       (0x00000000U)
00294 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
00300   * @{
00301   */
00302 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
00303 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
00304 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
00310   * @{
00311   */
00312
00313 #define  SMBUS_SOFTEND_MODE                     (0x00000000U)
00314 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
00315 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
00316 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
00322   * @{
00323   */
00324
00325 #define  SMBUS_NO_STARTSTOP                     (0x00000000U)
00326 #define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
00327 #define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00328 #define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
00334   * @{
00335   */
00336
00337 /* List of XferOptions in usage of :
00338  * 1- Restart condition when direction change
00339  * 2- No Restart condition in other use cases
00340  */
00341 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
00342 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
00343 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
00344 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
00345 #define  SMBUS_FIRST_FRAME_WITH_PEC             ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
00346 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00347 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00348
00349 /* List of XferOptions in usage of :
00350  * 1- Restart condition in all use cases (direction change or not)
00351  */
00352 #define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
00353 #define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
00354 #define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
00355 #define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
00361   * @brief SMBUS Interrupt definition
00362   *        Elements values convention: 0xXXXXXXXX
00363   *           - XXXXXXXX  : Interrupt control mask
00364   * @{
00365   */
00366 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
00367 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
00368 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
00369 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
00370 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
00371 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
00372 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
00373 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
00374                                                  SMBUS_IT_NACKI | SMBUS_IT_TXI)
00375 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
00376                                                  SMBUS_IT_RXI)
00377 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
00378 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
00384   * @brief Flag definition
00385   *        Elements values convention: 0xXXXXYYYY
00386   *           - XXXXXXXX  : Flag mask
00387   * @{
00388   */
00389
00390 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
00391 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
00392 #define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
00393 #define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
00394 #define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
00395 #define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
00396 #define  SMBUS_FLAG_TC                          I2C_ISR_TC
00397 #define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
00398 #define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
00399 #define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
00400 #define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
00401 #define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
00402 #define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
00403 #define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
00404 #define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
00405 #define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
00406 /**
00407   * @}
00408   */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /* Exported macros ------------------------------------------------------------*/
00415 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
00416   * @{
00417   */
00418
00419 /** @brief  Reset SMBUS handle state.
00420   * @param  __HANDLE__ specifies the SMBUS Handle.
00421   * @retval None
00422   */
00423 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00424 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                               \
00425                                                                  (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
00426                                                                  (__HANDLE__)->MspInitCallback = NULL;            \
00427                                                                  (__HANDLE__)->MspDeInitCallback = NULL;          \
00428                                                                } while(0)
00429 #else
00430 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
00431 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00432
00433 /** @brief  Enable the specified SMBUS interrupts.
00434   * @param  __HANDLE__ specifies the SMBUS Handle.
00435   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00436   *        This parameter can be one of the following values:
00437   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00438   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00439   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00440   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00441   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00442   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00443   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00444   *
00445   * @retval None
00446   */
00447 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00448
00449 /** @brief  Disable the specified SMBUS interrupts.
00450   * @param  __HANDLE__ specifies the SMBUS Handle.
00451   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00452   *        This parameter can be one of the following values:
00453   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00454   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00455   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00456   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00457   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00458   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00459   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00460   *
00461   * @retval None
00462   */
00463 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00464
00465 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
00466   * @param  __HANDLE__ specifies the SMBUS Handle.
00467   * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
00468   *          This parameter can be one of the following values:
00469   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00470   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00471   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00472   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00473   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00474   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00475   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00476   *
00477   * @retval The new state of __IT__ (SET or RESET).
00478   */
00479 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
00480   ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00481
00482 /** @brief  Check whether the specified SMBUS flag is set or not.
00483   * @param  __HANDLE__ specifies the SMBUS Handle.
00484   * @param  __FLAG__ specifies the flag to check.
00485   *        This parameter can be one of the following values:
00486   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
00487   *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
00488   *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
00489   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00490   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00491   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00492   *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
00493   *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
00494   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00495   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00496   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00497   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00498   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00499   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00500   *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
00501   *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
00502   *
00503   * @retval The new state of __FLAG__ (SET or RESET).
00504   */
00505 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
00506 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
00507   (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
00508     ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
00509
00510 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
00511   * @param  __HANDLE__ specifies the SMBUS Handle.
00512   * @param  __FLAG__ specifies the flag to clear.
00513   *          This parameter can be any combination of the following values:
00514   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
00515   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00516   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00517   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00518   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00519   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00520   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00521   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00522   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00523   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00524   *
00525   * @retval None
00526   */
00527 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) == SMBUS_FLAG_TXE) ? \
00528                                                        ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
00529                                                        ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00530
00531 /** @brief  Enable the specified SMBUS peripheral.
00532   * @param  __HANDLE__ specifies the SMBUS Handle.
00533   * @retval None
00534   */
00535 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00536
00537 /** @brief  Disable the specified SMBUS peripheral.
00538   * @param  __HANDLE__ specifies the SMBUS Handle.
00539   * @retval None
00540   */
00541 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00542
00543 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
00544   * @param  __HANDLE__ specifies the SMBUS Handle.
00545   * @retval None
00546   */
00547 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00548
00549 /**
00550   * @}
00551   */
00552
00553
00554 /* Private constants ---------------------------------------------------------*/
00555
00556 /* Private macros ------------------------------------------------------------*/
00557 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
00558   * @{
00559   */
00560
00561 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
00562                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
00563
00564 #define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
00565
00566 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
00567                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
00568
00569 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
00570                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
00571
00572 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
00573                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
00574                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
00575                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
00576                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
00577                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
00578                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
00579                                                          ((MASK) == SMBUS_OA2_MASK07))
00580
00581 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
00582                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
00583
00584 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
00585                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
00586
00587 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
00588                                                          ((PEC) == SMBUS_PEC_ENABLE))
00589
00590 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
00591                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
00592                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
00593
00594 #define IS_SMBUS_TRANSFER_MODE(MODE)                 (((MODE) == SMBUS_RELOAD_MODE)                          || \
00595                                                       ((MODE) == SMBUS_AUTOEND_MODE)                         || \
00596                                                       ((MODE) == SMBUS_SOFTEND_MODE)                         || \
00597                                                       ((MODE) == SMBUS_SENDPEC_MODE)                         || \
00598                                                       ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
00599                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
00600                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
00601                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
00602                                                                   SMBUS_RELOAD_MODE )))
00603
00604
00605 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
00606                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
00607                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
00608                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))
00609
00610
00611 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)   (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
00612                                                       ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
00613                                                       ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
00614                                                       ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
00615                                                       ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
00616                                                       ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
00617                                                       ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
00618                                                       ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
00619
00620 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
00621                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
00622                                                           ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
00623                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
00624
00625 #define SMBUS_RESET_CR1(__HANDLE__)                    ((__HANDLE__)->Instance->CR1 &= \
00626                                                         (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
00627                                                                                I2C_CR1_PECEN)))
00628 #define SMBUS_RESET_CR2(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 &= \
00629                                                         (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
00630                                                                                I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
00631                                                                                I2C_CR2_RD_WRN)))
00632
00633 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
00634                                                            (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
00635                                                                        (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
00636                                                                       (~I2C_CR2_RD_WRN)) : \
00637                                                            (uint32_t)((((uint32_t)(__ADDRESS__) & \
00638                                                                         (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
00639                                                                        (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00640
00641 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
00642 #define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
00643 #define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00644 #define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
00645 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
00646
00647 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
00648                                                           ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
00649 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
00650
00651 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
00652 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
00653
00654 /**
00655   * @}
00656   */
00657
00658 /* Include SMBUS HAL Extended module */
00659 #include "stm32g0xx_hal_smbus_ex.h"
00660
00661 /* Exported functions --------------------------------------------------------*/
00662 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
00663   * @{
00664   */
00665
00666 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00667   * @{
00668   */
00669
00670 /* Initialization and de-initialization functions  ****************************/
00671 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
00672 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
00673 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
00674 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
00675 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
00676 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
00677
00678 /* Callbacks Register/UnRegister functions  ***********************************/
00679 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00680 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
00681                                              HAL_SMBUS_CallbackIDTypeDef CallbackID,
00682                                              pSMBUS_CallbackTypeDef pCallback);
00683 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
00684                                                HAL_SMBUS_CallbackIDTypeDef CallbackID);
00685
00686 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
00687                                                  pSMBUS_AddrCallbackTypeDef pCallback);
00688 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
00689 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00690 /**
00691   * @}
00692   */
00693
00694 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00695   * @{
00696   */
00697
00698 /* IO operation functions  *****************************************************/
00699 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
00700   * @{
00701   */
00702 /******* Blocking mode: Polling */
00703 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
00704                                           uint32_t Timeout);
00705 /**
00706   * @}
00707   */
00708
00709 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
00710   * @{
00711   */
00712 /******* Non-Blocking mode: Interrupt */
00713 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
00714                                                uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00715 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
00716                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00717 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
00718 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
00719                                               uint32_t XferOptions);
00720 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
00721                                              uint32_t XferOptions);
00722
00723 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00724 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00725 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00726 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00727 /**
00728   * @}
00729   */
00730
00731 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00732   * @{
00733   */
00734 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
00735 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00736 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00737 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00738 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00739 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00740 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00741 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00742 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00743 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
00744
00745 /**
00746   * @}
00747   */
00748
00749 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
00750   *  @{
00751   */
00752
00753 /* Peripheral State and Errors functions  **************************************************/
00754 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
00755 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
00756
00757 /**
00758   * @}
00759   */
00760
00761 /**
00762   * @}
00763   */
00764
00765 /* Private Functions ---------------------------------------------------------*/
00766 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
00767   * @{
00768   */
00769 /* Private functions are defined in stm32g0xx_hal_smbus.c file */
00770 /**
00771   * @}
00772   */
00773
00774 /**
00775   * @}
00776   */
00777
00778 /**
00779   * @}
00780   */
00781
00782 /**
00783   * @}
00784   */
00785
00786 #ifdef __cplusplus
00787 }
00788 #endif
00789
00790
00791 #endif /* STM32G0xx_HAL_SMBUS_H */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smbus_ex.c Source File

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stm32g0xx_hal_smbus_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_smbus_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SMBUS Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of SMBUS Extended peripheral:
00008   *           + Extended features functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2018 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   @verbatim
00022   ==============================================================================
00023                ##### SMBUS peripheral Extended features  #####
00024   ==============================================================================
00025
00026   [..] Comparing to other previous devices, the SMBUS interface for STM32G0xx
00027        devices contains the following additional features
00028
00029        (+) Disable or enable wakeup from Stop mode(s)
00030        (+) Disable or enable Fast Mode Plus
00031
00032                      ##### How to use this driver #####
00033   ==============================================================================
00034     (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
00035           (++) HAL_SMBUSEx_EnableWakeUp()
00036           (++) HAL_SMBUSEx_DisableWakeUp()
00037     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00038           (++) HAL_SMBUSEx_EnableFastModePlus()
00039           (++) HAL_SMBUSEx_DisableFastModePlus()
00040   @endverbatim
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32g0xx_hal.h"
00045
00046 /** @addtogroup STM32G0xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup SMBUSEx SMBUSEx
00051   * @brief SMBUS Extended HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_SMBUS_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /* Private macro -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private function prototypes -----------------------------------------------*/
00062 /* Private functions ---------------------------------------------------------*/
00063
00064 /** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
00065   * @{
00066   */
00067
00068 /** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
00069   * @brief    WakeUp Mode Functions
00070   *
00071 @verbatim
00072  ===============================================================================
00073                       ##### WakeUp Mode Functions #####
00074  ===============================================================================
00075     [..] This section provides functions allowing to:
00076       (+) Configure Wake Up Feature
00077
00078 @endverbatim
00079   * @{
00080   */
00081
00082 /**
00083   * @brief  Enable SMBUS wakeup from Stop mode(s).
00084   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00085   *                the configuration information for the specified SMBUSx peripheral.
00086   * @retval HAL status
00087   */
00088 HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
00089 {
00090   /* Check the parameters */
00091   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
00092
00093   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00094   {
00095     /* Process Locked */
00096     __HAL_LOCK(hsmbus);
00097
00098     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00099
00100     /* Disable the selected SMBUS peripheral */
00101     __HAL_SMBUS_DISABLE(hsmbus);
00102
00103     /* Enable wakeup from stop mode */
00104     hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
00105
00106     __HAL_SMBUS_ENABLE(hsmbus);
00107
00108     hsmbus->State = HAL_SMBUS_STATE_READY;
00109
00110     /* Process Unlocked */
00111     __HAL_UNLOCK(hsmbus);
00112
00113     return HAL_OK;
00114   }
00115   else
00116   {
00117     return HAL_BUSY;
00118   }
00119 }
00120
00121 /**
00122   * @brief  Disable SMBUS wakeup from Stop mode(s).
00123   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00124   *                the configuration information for the specified SMBUSx peripheral.
00125   * @retval HAL status
00126   */
00127 HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
00128 {
00129   /* Check the parameters */
00130   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
00131
00132   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00133   {
00134     /* Process Locked */
00135     __HAL_LOCK(hsmbus);
00136
00137     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00138
00139     /* Disable the selected SMBUS peripheral */
00140     __HAL_SMBUS_DISABLE(hsmbus);
00141
00142     /* Disable wakeup from stop mode */
00143     hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00144
00145     __HAL_SMBUS_ENABLE(hsmbus);
00146
00147     hsmbus->State = HAL_SMBUS_STATE_READY;
00148
00149     /* Process Unlocked */
00150     __HAL_UNLOCK(hsmbus);
00151
00152     return HAL_OK;
00153   }
00154   else
00155   {
00156     return HAL_BUSY;
00157   }
00158 }
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
00164   * @brief    Fast Mode Plus Functions
00165   *
00166 @verbatim
00167  ===============================================================================
00168                       ##### Fast Mode Plus Functions #####
00169  ===============================================================================
00170     [..] This section provides functions allowing to:
00171       (+) Configure Fast Mode Plus
00172
00173 @endverbatim
00174   * @{
00175   */
00176
00177 /**
00178   * @brief Enable the SMBUS fast mode plus driving capability.
00179   * @param ConfigFastModePlus Selects the pin.
00180   *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
00181   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00182   *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
00183   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00184   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00185   *        can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
00186   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
00187   *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
00188   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
00189   *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
00190   * @retval None
00191   */
00192 void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00193 {
00194   /* Check the parameter */
00195   assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
00196
00197   /* Enable SYSCFG clock */
00198   __HAL_RCC_SYSCFG_CLK_ENABLE();
00199
00200   /* Enable fast mode plus driving capability for selected pin */
00201   SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00202 }
00203
00204 /**
00205   * @brief Disable the SMBUS fast mode plus driving capability.
00206   * @param ConfigFastModePlus Selects the pin.
00207   *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
00208   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
00209   *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
00210   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00211   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00212   *        can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
00213   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
00214   *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
00215   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
00216   *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
00217   * @retval None
00218   */
00219 void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00220 {
00221   /* Check the parameter */
00222   assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
00223
00224   /* Enable SYSCFG clock */
00225   __HAL_RCC_SYSCFG_CLK_ENABLE();
00226
00227   /* Disable fast mode plus driving capability for selected pin */
00228   CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00229 }
00230
00231 /**
00232   * @}
00233   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242
00243 #endif /* HAL_SMBUS_MODULE_ENABLED */
00244 /**
00245   * @}
00246   */
00247
00248 /**
00249   * @}
00250   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_smbus_ex.h Source File

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stm32g0xx_hal_smbus_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_smbus_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMBUS HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_SMBUS_EX_H
00021 #define STM32G0xx_HAL_SMBUS_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SMBUSEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
00041   * @{
00042   */
00043
00044 /** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
00045   * @{
00046   */
00047 #define SMBUS_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
00048 #define SMBUS_FASTMODEPLUS_PA9            SYSCFG_CFGR1_I2C_PA9_FMP                        /*!< Enable Fast Mode Plus on PA9       */
00049 #define SMBUS_FASTMODEPLUS_PA10           SYSCFG_CFGR1_I2C_PA10_FMP                       /*!< Enable Fast Mode Plus on PA10      */
00050 #define SMBUS_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
00051 #define SMBUS_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
00052 #define SMBUS_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
00053 #define SMBUS_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
00054 #define SMBUS_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
00055 #define SMBUS_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
00056 #if defined(SYSCFG_CFGR1_I2C3_FMP)
00057 #define SMBUS_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
00058 #else
00059 #define SMBUS_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
00060 #endif /* SYSCFG_CFGR1_I2C3_FMP */
00061 /**
00062   * @}
00063   */
00064
00065 /**
00066   * @}
00067   */
00068
00069 /* Exported macro ------------------------------------------------------------*/
00070 /** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
00071   * @{
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Exported functions --------------------------------------------------------*/
00079 /** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
00080   * @{
00081   */
00082
00083 /** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
00084   * @{
00085   */
00086 /* Peripheral Control functions  ************************************************/
00087 HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
00088 HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
00089 /**
00090   * @}
00091   */
00092
00093 /** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
00094   * @{
00095   */
00096 void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00097 void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00098 /**
00099   * @}
00100   */
00101
00102 /**
00103   * @}
00104   */
00105
00106 /* Private constants ---------------------------------------------------------*/
00107 /** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
00108   * @{
00109   */
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Private macros ------------------------------------------------------------*/
00116 /** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
00117   * @{
00118   */
00119 #define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
00120                                            ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA9))  == SMBUS_FASTMODEPLUS_PA9)  || \
00121                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA10)) == SMBUS_FASTMODEPLUS_PA10) || \
00122                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6))  == SMBUS_FASTMODEPLUS_PB6)  || \
00123                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7))  == SMBUS_FASTMODEPLUS_PB7)  || \
00124                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8))  == SMBUS_FASTMODEPLUS_PB8)  || \
00125                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9))  == SMBUS_FASTMODEPLUS_PB9)  || \
00126                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
00127                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
00128                                             (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3)))
00129 /**
00130   * @}
00131   */
00132
00133 /* Private Functions ---------------------------------------------------------*/
00134 /** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
00135   * @{
00136   */
00137 /* Private functions are defined in stm32g0xx_hal_smbus_ex.c file */
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146 /**
00147   * @}
00148   */
00149
00150 #ifdef __cplusplus
00151 }
00152 #endif
00153
00154 #endif /* STM32G0xx_HAL_SMBUS_EX_H */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_spi.c Source File

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stm32g0xx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                         ##### How to use this driver #####
00026   ==============================================================================
00027     [..]
00028       The SPI HAL driver can be used as follows:
00029
00030       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00031           SPI_HandleTypeDef  hspi;
00032
00033       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00034           (##) Enable the SPIx interface clock
00035           (##) SPI pins configuration
00036               (+++) Enable the clock for the SPI GPIOs
00037               (+++) Configure these SPI pins as alternate function push-pull
00038           (##) NVIC configuration if you need to use interrupt process
00039               (+++) Configure the SPIx interrupt priority
00040               (+++) Enable the NVIC SPI IRQ handle
00041           (##) DMA Configuration if you need to use DMA process
00042               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
00043               (+++) Enable the DMAx clock
00044               (+++) Configure the DMA handle parameters
00045               (+++) Configure the DMA Tx or Rx Stream/Channel
00046               (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
00047               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
00048
00049       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00050           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00051
00052       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00053           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00054               by calling the customized HAL_SPI_MspInit() API.
00055      [..]
00056        Circular mode restriction:
00057       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
00058           (##) Master 2Lines RxOnly
00059           (##) Master 1Line Rx
00060       (#) The CRC feature is not managed when the DMA circular mode is enabled
00061       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00062           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00063      [..]
00064        Master Receive mode restriction:
00065       (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
00066           bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
00067           does not initiate a new transfer the following procedure has to be respected:
00068           (##) HAL_SPI_DeInit()
00069           (##) HAL_SPI_Init()
00070      [..]
00071        Callback registration:
00072
00073       (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
00074           allows the user to configure dynamically the driver callbacks.
00075           Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
00076
00077           Function HAL_SPI_RegisterCallback() allows to register following callbacks:
00078             (++) TxCpltCallback        : SPI Tx Completed callback
00079             (++) RxCpltCallback        : SPI Rx Completed callback
00080             (++) TxRxCpltCallback      : SPI TxRx Completed callback
00081             (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
00082             (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
00083             (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
00084             (++) ErrorCallback         : SPI Error callback
00085             (++) AbortCpltCallback     : SPI Abort callback
00086             (++) MspInitCallback       : SPI Msp Init callback
00087             (++) MspDeInitCallback     : SPI Msp DeInit callback
00088           This function takes as parameters the HAL peripheral handle, the Callback ID
00089           and a pointer to the user callback function.
00090
00091
00092       (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
00093           weak function.
00094           HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
00095           and the Callback ID.
00096           This function allows to reset following callbacks:
00097             (++) TxCpltCallback        : SPI Tx Completed callback
00098             (++) RxCpltCallback        : SPI Rx Completed callback
00099             (++) TxRxCpltCallback      : SPI TxRx Completed callback
00100             (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
00101             (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
00102             (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
00103             (++) ErrorCallback         : SPI Error callback
00104             (++) AbortCpltCallback     : SPI Abort callback
00105             (++) MspInitCallback       : SPI Msp Init callback
00106             (++) MspDeInitCallback     : SPI Msp DeInit callback
00107
00108        [..]
00109        By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
00110        all callbacks are set to the corresponding weak functions:
00111        examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
00112        Exception done for MspInit and MspDeInit functions that are
00113        reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
00114        these callbacks are null (not registered beforehand).
00115        If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
00116        keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00117
00118        [..]
00119        Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
00120        Exception done MspInit/MspDeInit functions that can be registered/unregistered
00121        in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
00122        thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00123        Then, the user first registers the MspInit/MspDeInit user callbacks
00124        using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
00125        or HAL_SPI_Init() function.
00126
00127        [..]
00128        When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
00129        not defined, the callback registering feature is not available
00130        and weak (surcharged) callbacks are used.
00131
00132      [..]
00133        Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
00134        the following table resume the max SPI frequency reached with data size 8bits/16bits,
00135          according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
00136
00137   @endverbatim
00138
00139   Additional table :
00140
00141        DataSize = SPI_DATASIZE_8BIT:
00142        +----------------------------------------------------------------------------------------------+
00143        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00144        | Process | Transfer mode  |---------------------|----------------------|----------------------|
00145        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00146        |==============================================================================================|
00147        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00148        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00149        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
00150        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00151        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00152        |=========|================|==========|==========|===========|==========|===========|==========|
00153        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
00154        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00155        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
00156        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00157        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
00158        |=========|================|==========|==========|===========|==========|===========|==========|
00159        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
00160        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00161        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
00162        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00163        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
00164        +----------------------------------------------------------------------------------------------+
00165
00166        DataSize = SPI_DATASIZE_16BIT:
00167        +----------------------------------------------------------------------------------------------+
00168        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00169        | Process | Transfer mode  |---------------------|----------------------|----------------------|
00170        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00171        |==============================================================================================|
00172        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00173        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00174        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
00175        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00176        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00177        |=========|================|==========|==========|===========|==========|===========|==========|
00178        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
00179        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00180        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
00181        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00182        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
00183        |=========|================|==========|==========|===========|==========|===========|==========|
00184        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
00185        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00186        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
00187        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00188        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
00189        +----------------------------------------------------------------------------------------------+
00190        @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
00191              SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
00192        @note
00193             (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
00194             (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
00195             (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
00196
00197   */
00198
00199 /* Includes ------------------------------------------------------------------*/
00200 #include "stm32g0xx_hal.h"
00201
00202 /** @addtogroup STM32G0xx_HAL_Driver
00203   * @{
00204   */
00205
00206 /** @defgroup SPI SPI
00207   * @brief SPI HAL module driver
00208   * @{
00209   */
00210 #ifdef HAL_SPI_MODULE_ENABLED
00211
00212 /* Private typedef -----------------------------------------------------------*/
00213 /* Private defines -----------------------------------------------------------*/
00214 /** @defgroup SPI_Private_Constants SPI Private Constants
00215   * @{
00216   */
00217 #define SPI_DEFAULT_TIMEOUT 100U
00218 /**
00219   * @}
00220   */
00221
00222 /* Private macros ------------------------------------------------------------*/
00223 /* Private variables ---------------------------------------------------------*/
00224 /* Private function prototypes -----------------------------------------------*/
00225 /** @defgroup SPI_Private_Functions SPI Private Functions
00226   * @{
00227   */
00228 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00229 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00230 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00231 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00232 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00233 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00234 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00235 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00236 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00237 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00238 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
00239                                                        uint32_t Timeout, uint32_t Tickstart);
00240 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
00241                                                        uint32_t Timeout, uint32_t Tickstart);
00242 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00243 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00244 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00245 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00246 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00247 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00248 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00249 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00250 #if (USE_SPI_CRC != 0U)
00251 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00252 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00253 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00254 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00255 #endif /* USE_SPI_CRC */
00256 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
00257 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
00258 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00259 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00260 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00261 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00262 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00263 /**
00264   * @}
00265   */
00266
00267 /* Exported functions --------------------------------------------------------*/
00268 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00269   * @{
00270   */
00271
00272 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00273   *  @brief    Initialization and Configuration functions
00274   *
00275 @verbatim
00276  ===============================================================================
00277               ##### Initialization and de-initialization functions #####
00278  ===============================================================================
00279     [..]  This subsection provides a set of functions allowing to initialize and
00280           de-initialize the SPIx peripheral:
00281
00282       (+) User must implement HAL_SPI_MspInit() function in which he configures
00283           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00284
00285       (+) Call the function HAL_SPI_Init() to configure the selected device with
00286           the selected configuration:
00287         (++) Mode
00288         (++) Direction
00289         (++) Data Size
00290         (++) Clock Polarity and Phase
00291         (++) NSS Management
00292         (++) BaudRate Prescaler
00293         (++) FirstBit
00294         (++) TIMode
00295         (++) CRC Calculation
00296         (++) CRC Polynomial if CRC enabled
00297         (++) CRC Length, used only with Data8 and Data16
00298         (++) FIFO reception threshold
00299
00300       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00301           of the selected SPIx peripheral.
00302
00303 @endverbatim
00304   * @{
00305   */
00306
00307 /**
00308   * @brief  Initialize the SPI according to the specified parameters
00309   *         in the SPI_InitTypeDef and initialize the associated handle.
00310   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00311   *               the configuration information for SPI module.
00312   * @retval HAL status
00313   */
00314 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00315 {
00316   uint32_t frxth;
00317
00318   /* Check the SPI handle allocation */
00319   if (hspi == NULL)
00320   {
00321     return HAL_ERROR;
00322   }
00323
00324   /* Check the parameters */
00325   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00326   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00327   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00328   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00329   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00330   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
00331   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00332   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00333   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00334   if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
00335   {
00336     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00337     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00338
00339     if (hspi->Init.Mode == SPI_MODE_MASTER)
00340     {
00341       assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00342     }
00343     else
00344     {
00345       /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
00346       hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
00347     }
00348   }
00349   else
00350   {
00351     assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00352
00353     /* Force polarity and phase to TI protocaol requirements */
00354     hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
00355     hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
00356   }
00357 #if (USE_SPI_CRC != 0U)
00358   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00359   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00360   {
00361     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00362     assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
00363   }
00364 #else
00365   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00366 #endif /* USE_SPI_CRC */
00367
00368   if (hspi->State == HAL_SPI_STATE_RESET)
00369   {
00370     /* Allocate lock resource and initialize it */
00371     hspi->Lock = HAL_UNLOCKED;
00372
00373 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00374     /* Init the SPI Callback settings */
00375     hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
00376     hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
00377     hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
00378     hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
00379     hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
00380     hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
00381     hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
00382     hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00383
00384     if (hspi->MspInitCallback == NULL)
00385     {
00386       hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
00387     }
00388
00389     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00390     hspi->MspInitCallback(hspi);
00391 #else
00392     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00393     HAL_SPI_MspInit(hspi);
00394 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00395   }
00396
00397   hspi->State = HAL_SPI_STATE_BUSY;
00398
00399   /* Disable the selected SPI peripheral */
00400   __HAL_SPI_DISABLE(hspi);
00401
00402   /* Align by default the rs fifo threshold on the data size */
00403   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00404   {
00405     frxth = SPI_RXFIFO_THRESHOLD_HF;
00406   }
00407   else
00408   {
00409     frxth = SPI_RXFIFO_THRESHOLD_QF;
00410   }
00411
00412   /* CRC calculation is valid only for 16Bit and 8 Bit */
00413   if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
00414   {
00415     /* CRC must be disabled */
00416     hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00417   }
00418
00419   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00420   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
00421   Communication speed, First bit and CRC calculation state */
00422   WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
00423                                   (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
00424                                   (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
00425                                   (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
00426                                   (hspi->Init.NSS & SPI_CR1_SSM) |
00427                                   (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
00428                                   (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
00429                                   (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
00430 #if (USE_SPI_CRC != 0U)
00431   /*---------------------------- SPIx CRCL Configuration -------------------*/
00432   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00433   {
00434     /* Align the CRC Length on the data size */
00435     if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
00436     {
00437       /* CRC Length aligned on the data size : value set by default */
00438       if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00439       {
00440         hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
00441       }
00442       else
00443       {
00444         hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
00445       }
00446     }
00447
00448     /* Configure : CRC Length */
00449     if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
00450     {
00451       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
00452     }
00453   }
00454 #endif /* USE_SPI_CRC */
00455
00456   /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
00457   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
00458                                   (hspi->Init.TIMode & SPI_CR2_FRF) |
00459                                   (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
00460                                   (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
00461                                   (frxth & SPI_CR2_FRXTH)));
00462
00463 #if (USE_SPI_CRC != 0U)
00464   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00465   /* Configure : CRC Polynomial */
00466   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00467   {
00468     WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
00469   }
00470 #endif /* USE_SPI_CRC */
00471
00472 #if defined(SPI_I2SCFGR_I2SMOD)
00473   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00474   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00475 #endif /* SPI_I2SCFGR_I2SMOD */
00476
00477   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00478   hspi->State     = HAL_SPI_STATE_READY;
00479
00480   return HAL_OK;
00481 }
00482
00483 /**
00484   * @brief  De-Initialize the SPI peripheral.
00485   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00486   *               the configuration information for SPI module.
00487   * @retval HAL status
00488   */
00489 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00490 {
00491   /* Check the SPI handle allocation */
00492   if (hspi == NULL)
00493   {
00494     return HAL_ERROR;
00495   }
00496
00497   /* Check SPI Instance parameter */
00498   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00499
00500   hspi->State = HAL_SPI_STATE_BUSY;
00501
00502   /* Disable the SPI Peripheral Clock */
00503   __HAL_SPI_DISABLE(hspi);
00504
00505 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00506   if (hspi->MspDeInitCallback == NULL)
00507   {
00508     hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
00509   }
00510
00511   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00512   hspi->MspDeInitCallback(hspi);
00513 #else
00514   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00515   HAL_SPI_MspDeInit(hspi);
00516 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00517
00518   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00519   hspi->State = HAL_SPI_STATE_RESET;
00520
00521   /* Release Lock */
00522   __HAL_UNLOCK(hspi);
00523
00524   return HAL_OK;
00525 }
00526
00527 /**
00528   * @brief  Initialize the SPI MSP.
00529   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00530   *               the configuration information for SPI module.
00531   * @retval None
00532   */
00533 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00534 {
00535   /* Prevent unused argument(s) compilation warning */
00536   UNUSED(hspi);
00537
00538   /* NOTE : This function should not be modified, when the callback is needed,
00539             the HAL_SPI_MspInit should be implemented in the user file
00540    */
00541 }
00542
00543 /**
00544   * @brief  De-Initialize the SPI MSP.
00545   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00546   *               the configuration information for SPI module.
00547   * @retval None
00548   */
00549 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00550 {
00551   /* Prevent unused argument(s) compilation warning */
00552   UNUSED(hspi);
00553
00554   /* NOTE : This function should not be modified, when the callback is needed,
00555             the HAL_SPI_MspDeInit should be implemented in the user file
00556    */
00557 }
00558
00559 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00560 /**
00561   * @brief  Register a User SPI Callback
00562   *         To be used instead of the weak predefined callback
00563   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
00564   *                the configuration information for the specified SPI.
00565   * @param  CallbackID ID of the callback to be registered
00566   * @param  pCallback pointer to the Callback function
00567   * @retval HAL status
00568   */
00569 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
00570                                            pSPI_CallbackTypeDef pCallback)
00571 {
00572   HAL_StatusTypeDef status = HAL_OK;
00573
00574   if (pCallback == NULL)
00575   {
00576     /* Update the error code */
00577     hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
00578
00579     return HAL_ERROR;
00580   }
00581   /* Process locked */
00582   __HAL_LOCK(hspi);
00583
00584   if (HAL_SPI_STATE_READY == hspi->State)
00585   {
00586     switch (CallbackID)
00587     {
00588       case HAL_SPI_TX_COMPLETE_CB_ID :
00589         hspi->TxCpltCallback = pCallback;
00590         break;
00591
00592       case HAL_SPI_RX_COMPLETE_CB_ID :
00593         hspi->RxCpltCallback = pCallback;
00594         break;
00595
00596       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
00597         hspi->TxRxCpltCallback = pCallback;
00598         break;
00599
00600       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
00601         hspi->TxHalfCpltCallback = pCallback;
00602         break;
00603
00604       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
00605         hspi->RxHalfCpltCallback = pCallback;
00606         break;
00607
00608       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
00609         hspi->TxRxHalfCpltCallback = pCallback;
00610         break;
00611
00612       case HAL_SPI_ERROR_CB_ID :
00613         hspi->ErrorCallback = pCallback;
00614         break;
00615
00616       case HAL_SPI_ABORT_CB_ID :
00617         hspi->AbortCpltCallback = pCallback;
00618         break;
00619
00620       case HAL_SPI_MSPINIT_CB_ID :
00621         hspi->MspInitCallback = pCallback;
00622         break;
00623
00624       case HAL_SPI_MSPDEINIT_CB_ID :
00625         hspi->MspDeInitCallback = pCallback;
00626         break;
00627
00628       default :
00629         /* Update the error code */
00630         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00631
00632         /* Return error status */
00633         status =  HAL_ERROR;
00634         break;
00635     }
00636   }
00637   else if (HAL_SPI_STATE_RESET == hspi->State)
00638   {
00639     switch (CallbackID)
00640     {
00641       case HAL_SPI_MSPINIT_CB_ID :
00642         hspi->MspInitCallback = pCallback;
00643         break;
00644
00645       case HAL_SPI_MSPDEINIT_CB_ID :
00646         hspi->MspDeInitCallback = pCallback;
00647         break;
00648
00649       default :
00650         /* Update the error code */
00651         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00652
00653         /* Return error status */
00654         status =  HAL_ERROR;
00655         break;
00656     }
00657   }
00658   else
00659   {
00660     /* Update the error code */
00661     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00662
00663     /* Return error status */
00664     status =  HAL_ERROR;
00665   }
00666
00667   /* Release Lock */
00668   __HAL_UNLOCK(hspi);
00669   return status;
00670 }
00671
00672 /**
00673   * @brief  Unregister an SPI Callback
00674   *         SPI callback is redirected to the weak predefined callback
00675   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
00676   *                the configuration information for the specified SPI.
00677   * @param  CallbackID ID of the callback to be unregistered
00678   * @retval HAL status
00679   */
00680 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
00681 {
00682   HAL_StatusTypeDef status = HAL_OK;
00683
00684   /* Process locked */
00685   __HAL_LOCK(hspi);
00686
00687   if (HAL_SPI_STATE_READY == hspi->State)
00688   {
00689     switch (CallbackID)
00690     {
00691       case HAL_SPI_TX_COMPLETE_CB_ID :
00692         hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
00693         break;
00694
00695       case HAL_SPI_RX_COMPLETE_CB_ID :
00696         hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
00697         break;
00698
00699       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
00700         hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
00701         break;
00702
00703       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
00704         hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
00705         break;
00706
00707       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
00708         hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
00709         break;
00710
00711       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
00712         hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
00713         break;
00714
00715       case HAL_SPI_ERROR_CB_ID :
00716         hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
00717         break;
00718
00719       case HAL_SPI_ABORT_CB_ID :
00720         hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00721         break;
00722
00723       case HAL_SPI_MSPINIT_CB_ID :
00724         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
00725         break;
00726
00727       case HAL_SPI_MSPDEINIT_CB_ID :
00728         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
00729         break;
00730
00731       default :
00732         /* Update the error code */
00733         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00734
00735         /* Return error status */
00736         status =  HAL_ERROR;
00737         break;
00738     }
00739   }
00740   else if (HAL_SPI_STATE_RESET == hspi->State)
00741   {
00742     switch (CallbackID)
00743     {
00744       case HAL_SPI_MSPINIT_CB_ID :
00745         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
00746         break;
00747
00748       case HAL_SPI_MSPDEINIT_CB_ID :
00749         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
00750         break;
00751
00752       default :
00753         /* Update the error code */
00754         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00755
00756         /* Return error status */
00757         status =  HAL_ERROR;
00758         break;
00759     }
00760   }
00761   else
00762   {
00763     /* Update the error code */
00764     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00765
00766     /* Return error status */
00767     status =  HAL_ERROR;
00768   }
00769
00770   /* Release Lock */
00771   __HAL_UNLOCK(hspi);
00772   return status;
00773 }
00774 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00775 /**
00776   * @}
00777   */
00778
00779 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00780   *  @brief   Data transfers functions
00781   *
00782 @verbatim
00783   ==============================================================================
00784                       ##### IO operation functions #####
00785  ===============================================================================
00786  [..]
00787     This subsection provides a set of functions allowing to manage the SPI
00788     data transfers.
00789
00790     [..] The SPI supports master and slave mode :
00791
00792     (#) There are two modes of transfer:
00793        (++) Blocking mode: The communication is performed in polling mode.
00794             The HAL status of all data processing is returned by the same function
00795             after finishing transfer.
00796        (++) No-Blocking mode: The communication is performed using Interrupts
00797             or DMA, These APIs return the HAL status.
00798             The end of the data processing will be indicated through the
00799             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00800             using DMA mode.
00801             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00802             will be executed respectively at the end of the transmit or Receive process
00803             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00804
00805     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00806         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00807
00808 @endverbatim
00809   * @{
00810   */
00811
00812 /**
00813   * @brief  Transmit an amount of data in blocking mode.
00814   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00815   *               the configuration information for SPI module.
00816   * @param  pData pointer to data buffer
00817   * @param  Size amount of data to be sent
00818   * @param  Timeout Timeout duration
00819   * @retval HAL status
00820   */
00821 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00822 {
00823   uint32_t tickstart;
00824   HAL_StatusTypeDef errorcode = HAL_OK;
00825   uint16_t initial_TxXferCount;
00826
00827   /* Check Direction parameter */
00828   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00829
00830   /* Process Locked */
00831   __HAL_LOCK(hspi);
00832
00833   /* Init tickstart for timeout management*/
00834   tickstart = HAL_GetTick();
00835   initial_TxXferCount = Size;
00836
00837   if (hspi->State != HAL_SPI_STATE_READY)
00838   {
00839     errorcode = HAL_BUSY;
00840     goto error;
00841   }
00842
00843   if ((pData == NULL) || (Size == 0U))
00844   {
00845     errorcode = HAL_ERROR;
00846     goto error;
00847   }
00848
00849   /* Set the transaction information */
00850   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00851   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00852   hspi->pTxBuffPtr  = (uint8_t *)pData;
00853   hspi->TxXferSize  = Size;
00854   hspi->TxXferCount = Size;
00855
00856   /*Init field not used in handle to zero */
00857   hspi->pRxBuffPtr  = (uint8_t *)NULL;
00858   hspi->RxXferSize  = 0U;
00859   hspi->RxXferCount = 0U;
00860   hspi->TxISR       = NULL;
00861   hspi->RxISR       = NULL;
00862
00863   /* Configure communication direction : 1Line */
00864   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
00865   {
00866     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
00867     __HAL_SPI_DISABLE(hspi);
00868     SPI_1LINE_TX(hspi);
00869   }
00870
00871 #if (USE_SPI_CRC != 0U)
00872   /* Reset CRC Calculation */
00873   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00874   {
00875     SPI_RESET_CRC(hspi);
00876   }
00877 #endif /* USE_SPI_CRC */
00878
00879   /* Check if the SPI is already enabled */
00880   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00881   {
00882     /* Enable SPI peripheral */
00883     __HAL_SPI_ENABLE(hspi);
00884   }
00885
00886   /* Transmit data in 16 Bit mode */
00887   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00888   {
00889     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
00890     {
00891       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00892       hspi->pTxBuffPtr += sizeof(uint16_t);
00893       hspi->TxXferCount--;
00894     }
00895     /* Transmit data in 16 Bit mode */
00896     while (hspi->TxXferCount > 0U)
00897     {
00898       /* Wait until TXE flag is set to send data */
00899       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00900       {
00901         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00902         hspi->pTxBuffPtr += sizeof(uint16_t);
00903         hspi->TxXferCount--;
00904       }
00905       else
00906       {
00907         /* Timeout management */
00908         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00909         {
00910           errorcode = HAL_TIMEOUT;
00911           goto error;
00912         }
00913       }
00914     }
00915   }
00916   /* Transmit data in 8 Bit mode */
00917   else
00918   {
00919     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
00920     {
00921       *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
00922       hspi->pTxBuffPtr += sizeof(uint8_t);
00923       hspi->TxXferCount--;
00924     }
00925     while (hspi->TxXferCount > 0U)
00926     {
00927       /* Wait until TXE flag is set to send data */
00928       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00929       {
00930         *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
00931         hspi->pTxBuffPtr += sizeof(uint8_t);
00932         hspi->TxXferCount--;
00933       }
00934       else
00935       {
00936         /* Timeout management */
00937         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00938         {
00939           errorcode = HAL_TIMEOUT;
00940           goto error;
00941         }
00942       }
00943     }
00944   }
00945 #if (USE_SPI_CRC != 0U)
00946   /* Enable CRC Transmission */
00947   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00948   {
00949     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00950   }
00951 #endif /* USE_SPI_CRC */
00952
00953   /* Check the end of the transaction */
00954   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
00955   {
00956     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00957   }
00958
00959   /* Clear overrun flag in 2 Lines communication mode because received is not read */
00960   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
00961   {
00962     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00963   }
00964
00965   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00966   {
00967     errorcode = HAL_ERROR;
00968   }
00969
00970 error:
00971   hspi->State = HAL_SPI_STATE_READY;
00972   /* Process Unlocked */
00973   __HAL_UNLOCK(hspi);
00974   return errorcode;
00975 }
00976
00977 /**
00978   * @brief  Receive an amount of data in blocking mode.
00979   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00980   *               the configuration information for SPI module.
00981   * @param  pData pointer to data buffer
00982   * @param  Size amount of data to be received
00983   * @param  Timeout Timeout duration
00984   * @retval HAL status
00985   */
00986 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00987 {
00988 #if (USE_SPI_CRC != 0U)
00989   __IO uint32_t tmpreg = 0U;
00990   __IO uint8_t  *ptmpreg8;
00991   __IO uint8_t  tmpreg8 = 0;
00992 #endif /* USE_SPI_CRC */
00993   uint32_t tickstart;
00994   HAL_StatusTypeDef errorcode = HAL_OK;
00995
00996   if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00997   {
00998     hspi->State = HAL_SPI_STATE_BUSY_RX;
00999     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01000     return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
01001   }
01002
01003   /* Process Locked */
01004   __HAL_LOCK(hspi);
01005
01006   /* Init tickstart for timeout management*/
01007   tickstart = HAL_GetTick();
01008
01009   if (hspi->State != HAL_SPI_STATE_READY)
01010   {
01011     errorcode = HAL_BUSY;
01012     goto error;
01013   }
01014
01015   if ((pData == NULL) || (Size == 0U))
01016   {
01017     errorcode = HAL_ERROR;
01018     goto error;
01019   }
01020
01021   /* Set the transaction information */
01022   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01023   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01024   hspi->pRxBuffPtr  = (uint8_t *)pData;
01025   hspi->RxXferSize  = Size;
01026   hspi->RxXferCount = Size;
01027
01028   /*Init field not used in handle to zero */
01029   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01030   hspi->TxXferSize  = 0U;
01031   hspi->TxXferCount = 0U;
01032   hspi->RxISR       = NULL;
01033   hspi->TxISR       = NULL;
01034
01035 #if (USE_SPI_CRC != 0U)
01036   /* Reset CRC Calculation */
01037   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01038   {
01039     SPI_RESET_CRC(hspi);
01040     /* this is done to handle the CRCNEXT before the latest data */
01041     hspi->RxXferCount--;
01042   }
01043 #endif /* USE_SPI_CRC */
01044
01045   /* Set the Rx Fifo threshold */
01046   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01047   {
01048     /* Set RX Fifo threshold according the reception data length: 16bit */
01049     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01050   }
01051   else
01052   {
01053     /* Set RX Fifo threshold according the reception data length: 8bit */
01054     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01055   }
01056
01057   /* Configure communication direction: 1Line */
01058   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01059   {
01060     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01061     __HAL_SPI_DISABLE(hspi);
01062     SPI_1LINE_RX(hspi);
01063   }
01064
01065   /* Check if the SPI is already enabled */
01066   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01067   {
01068     /* Enable SPI peripheral */
01069     __HAL_SPI_ENABLE(hspi);
01070   }
01071
01072   /* Receive data in 8 Bit mode */
01073   if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
01074   {
01075     /* Transfer loop */
01076     while (hspi->RxXferCount > 0U)
01077     {
01078       /* Check the RXNE flag */
01079       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
01080       {
01081         /* read the received data */
01082         (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01083         hspi->pRxBuffPtr += sizeof(uint8_t);
01084         hspi->RxXferCount--;
01085       }
01086       else
01087       {
01088         /* Timeout management */
01089         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01090         {
01091           errorcode = HAL_TIMEOUT;
01092           goto error;
01093         }
01094       }
01095     }
01096   }
01097   else
01098   {
01099     /* Transfer loop */
01100     while (hspi->RxXferCount > 0U)
01101     {
01102       /* Check the RXNE flag */
01103       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
01104       {
01105         *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01106         hspi->pRxBuffPtr += sizeof(uint16_t);
01107         hspi->RxXferCount--;
01108       }
01109       else
01110       {
01111         /* Timeout management */
01112         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01113         {
01114           errorcode = HAL_TIMEOUT;
01115           goto error;
01116         }
01117       }
01118     }
01119   }
01120
01121 #if (USE_SPI_CRC != 0U)
01122   /* Handle the CRC Transmission */
01123   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01124   {
01125     /* freeze the CRC before the latest data */
01126     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01127
01128     /* Read the latest data */
01129     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01130     {
01131       /* the latest data has not been received */
01132       errorcode = HAL_TIMEOUT;
01133       goto error;
01134     }
01135
01136     /* Receive last data in 16 Bit mode */
01137     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01138     {
01139       *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01140     }
01141     /* Receive last data in 8 Bit mode */
01142     else
01143     {
01144       (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01145     }
01146
01147     /* Wait the CRC data */
01148     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01149     {
01150       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01151       errorcode = HAL_TIMEOUT;
01152       goto error;
01153     }
01154
01155     /* Read CRC to Flush DR and RXNE flag */
01156     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
01157     {
01158       /* Read 16bit CRC */
01159       tmpreg = READ_REG(hspi->Instance->DR);
01160       /* To avoid GCC warning */
01161       UNUSED(tmpreg);
01162     }
01163     else
01164     {
01165       /* Initialize the 8bit temporary pointer */
01166       ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
01167       /* Read 8bit CRC */
01168       tmpreg8 = *ptmpreg8;
01169       /* To avoid GCC warning */
01170       UNUSED(tmpreg8);
01171
01172       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01173       {
01174         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01175         {
01176           /* Error on the CRC reception */
01177           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01178           errorcode = HAL_TIMEOUT;
01179           goto error;
01180         }
01181         /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
01182         tmpreg8 = *ptmpreg8;
01183         /* To avoid GCC warning */
01184         UNUSED(tmpreg8);
01185       }
01186     }
01187   }
01188 #endif /* USE_SPI_CRC */
01189
01190   /* Check the end of the transaction */
01191   if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
01192   {
01193     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01194   }
01195
01196 #if (USE_SPI_CRC != 0U)
01197   /* Check if CRC error occurred */
01198   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01199   {
01200     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01201     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01202   }
01203 #endif /* USE_SPI_CRC */
01204
01205   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01206   {
01207     errorcode = HAL_ERROR;
01208   }
01209
01210 error :
01211   hspi->State = HAL_SPI_STATE_READY;
01212   __HAL_UNLOCK(hspi);
01213   return errorcode;
01214 }
01215
01216 /**
01217   * @brief  Transmit and Receive an amount of data in blocking mode.
01218   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01219   *               the configuration information for SPI module.
01220   * @param  pTxData pointer to transmission data buffer
01221   * @param  pRxData pointer to reception data buffer
01222   * @param  Size amount of data to be sent and received
01223   * @param  Timeout Timeout duration
01224   * @retval HAL status
01225   */
01226 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
01227                                           uint32_t Timeout)
01228 {
01229   uint16_t             initial_TxXferCount;
01230   uint32_t             tmp_mode;
01231   HAL_SPI_StateTypeDef tmp_state;
01232   uint32_t             tickstart;
01233 #if (USE_SPI_CRC != 0U)
01234   __IO uint32_t tmpreg = 0U;
01235   uint32_t             spi_cr1;
01236   uint32_t             spi_cr2;
01237   __IO uint8_t  *ptmpreg8;
01238   __IO uint8_t  tmpreg8 = 0;
01239 #endif /* USE_SPI_CRC */
01240
01241   /* Variable used to alternate Rx and Tx during transfer */
01242   uint32_t             txallowed = 1U;
01243   HAL_StatusTypeDef    errorcode = HAL_OK;
01244
01245   /* Check Direction parameter */
01246   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01247
01248   /* Process Locked */
01249   __HAL_LOCK(hspi);
01250
01251   /* Init tickstart for timeout management*/
01252   tickstart = HAL_GetTick();
01253
01254   /* Init temporary variables */
01255   tmp_state           = hspi->State;
01256   tmp_mode            = hspi->Init.Mode;
01257   initial_TxXferCount = Size;
01258 #if (USE_SPI_CRC != 0U)
01259   spi_cr1             = READ_REG(hspi->Instance->CR1);
01260   spi_cr2             = READ_REG(hspi->Instance->CR2);
01261 #endif /* USE_SPI_CRC */
01262
01263   if (!((tmp_state == HAL_SPI_STATE_READY) || \
01264         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
01265   {
01266     errorcode = HAL_BUSY;
01267     goto error;
01268   }
01269
01270   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01271   {
01272     errorcode = HAL_ERROR;
01273     goto error;
01274   }
01275
01276   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01277   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01278   {
01279     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01280   }
01281
01282   /* Set the transaction information */
01283   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01284   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01285   hspi->RxXferCount = Size;
01286   hspi->RxXferSize  = Size;
01287   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01288   hspi->TxXferCount = Size;
01289   hspi->TxXferSize  = Size;
01290
01291   /*Init field not used in handle to zero */
01292   hspi->RxISR       = NULL;
01293   hspi->TxISR       = NULL;
01294
01295 #if (USE_SPI_CRC != 0U)
01296   /* Reset CRC Calculation */
01297   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01298   {
01299     SPI_RESET_CRC(hspi);
01300   }
01301 #endif /* USE_SPI_CRC */
01302
01303   /* Set the Rx Fifo threshold */
01304   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01305   {
01306     /* Set fiforxthreshold according the reception data length: 16bit */
01307     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01308   }
01309   else
01310   {
01311     /* Set fiforxthreshold according the reception data length: 8bit */
01312     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01313   }
01314
01315   /* Check if the SPI is already enabled */
01316   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01317   {
01318     /* Enable SPI peripheral */
01319     __HAL_SPI_ENABLE(hspi);
01320   }
01321
01322   /* Transmit and Receive data in 16 Bit mode */
01323   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01324   {
01325     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
01326     {
01327       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01328       hspi->pTxBuffPtr += sizeof(uint16_t);
01329       hspi->TxXferCount--;
01330     }
01331     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01332     {
01333       /* Check TXE flag */
01334       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
01335       {
01336         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01337         hspi->pTxBuffPtr += sizeof(uint16_t);
01338         hspi->TxXferCount--;
01339         /* Next Data is a reception (Rx). Tx not allowed */
01340         txallowed = 0U;
01341
01342 #if (USE_SPI_CRC != 0U)
01343         /* Enable CRC Transmission */
01344         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01345         {
01346           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01347           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
01348           {
01349             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01350           }
01351           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01352         }
01353 #endif /* USE_SPI_CRC */
01354       }
01355
01356       /* Check RXNE flag */
01357       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
01358       {
01359         *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01360         hspi->pRxBuffPtr += sizeof(uint16_t);
01361         hspi->RxXferCount--;
01362         /* Next Data is a Transmission (Tx). Tx is allowed */
01363         txallowed = 1U;
01364       }
01365       if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
01366       {
01367         errorcode = HAL_TIMEOUT;
01368         goto error;
01369       }
01370     }
01371   }
01372   /* Transmit and Receive data in 8 Bit mode */
01373   else
01374   {
01375     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
01376     {
01377       *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
01378       hspi->pTxBuffPtr += sizeof(uint8_t);
01379       hspi->TxXferCount--;
01380     }
01381     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01382     {
01383       /* Check TXE flag */
01384       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
01385       {
01386         *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
01387         hspi->pTxBuffPtr++;
01388         hspi->TxXferCount--;
01389         /* Next Data is a reception (Rx). Tx not allowed */
01390         txallowed = 0U;
01391
01392 #if (USE_SPI_CRC != 0U)
01393         /* Enable CRC Transmission */
01394         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01395         {
01396           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01397           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
01398           {
01399             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01400           }
01401           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01402         }
01403 #endif /* USE_SPI_CRC */
01404       }
01405
01406       /* Wait until RXNE flag is reset */
01407       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
01408       {
01409         (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01410         hspi->pRxBuffPtr++;
01411         hspi->RxXferCount--;
01412         /* Next Data is a Transmission (Tx). Tx is allowed */
01413         txallowed = 1U;
01414       }
01415       if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
01416       {
01417         errorcode = HAL_TIMEOUT;
01418         goto error;
01419       }
01420     }
01421   }
01422
01423 #if (USE_SPI_CRC != 0U)
01424   /* Read CRC from DR to close CRC calculation process */
01425   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01426   {
01427     /* Wait until TXE flag */
01428     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01429     {
01430       /* Error on the CRC reception */
01431       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01432       errorcode = HAL_TIMEOUT;
01433       goto error;
01434     }
01435     /* Read CRC */
01436     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
01437     {
01438       /* Read 16bit CRC */
01439       tmpreg = READ_REG(hspi->Instance->DR);
01440       /* To avoid GCC warning */
01441       UNUSED(tmpreg);
01442     }
01443     else
01444     {
01445       /* Initialize the 8bit temporary pointer */
01446       ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
01447       /* Read 8bit CRC */
01448       tmpreg8 = *ptmpreg8;
01449       /* To avoid GCC warning */
01450       UNUSED(tmpreg8);
01451
01452       if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
01453       {
01454         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01455         {
01456           /* Error on the CRC reception */
01457           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01458           errorcode = HAL_TIMEOUT;
01459           goto error;
01460         }
01461         /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
01462         tmpreg8 = *ptmpreg8;
01463         /* To avoid GCC warning */
01464         UNUSED(tmpreg8);
01465       }
01466     }
01467   }
01468
01469   /* Check if CRC error occurred */
01470   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01471   {
01472     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01473     /* Clear CRC Flag */
01474     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01475
01476     errorcode = HAL_ERROR;
01477   }
01478 #endif /* USE_SPI_CRC */
01479
01480   /* Check the end of the transaction */
01481   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
01482   {
01483     errorcode = HAL_ERROR;
01484     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01485   }
01486
01487 error :
01488   hspi->State = HAL_SPI_STATE_READY;
01489   __HAL_UNLOCK(hspi);
01490   return errorcode;
01491 }
01492
01493 /**
01494   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01495   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01496   *               the configuration information for SPI module.
01497   * @param  pData pointer to data buffer
01498   * @param  Size amount of data to be sent
01499   * @retval HAL status
01500   */
01501 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01502 {
01503   HAL_StatusTypeDef errorcode = HAL_OK;
01504
01505   /* Check Direction parameter */
01506   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01507
01508   /* Process Locked */
01509   __HAL_LOCK(hspi);
01510
01511   if ((pData == NULL) || (Size == 0U))
01512   {
01513     errorcode = HAL_ERROR;
01514     goto error;
01515   }
01516
01517   if (hspi->State != HAL_SPI_STATE_READY)
01518   {
01519     errorcode = HAL_BUSY;
01520     goto error;
01521   }
01522
01523   /* Set the transaction information */
01524   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01525   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01526   hspi->pTxBuffPtr  = (uint8_t *)pData;
01527   hspi->TxXferSize  = Size;
01528   hspi->TxXferCount = Size;
01529
01530   /* Init field not used in handle to zero */
01531   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01532   hspi->RxXferSize  = 0U;
01533   hspi->RxXferCount = 0U;
01534   hspi->RxISR       = NULL;
01535
01536   /* Set the function for IT treatment */
01537   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01538   {
01539     hspi->TxISR = SPI_TxISR_16BIT;
01540   }
01541   else
01542   {
01543     hspi->TxISR = SPI_TxISR_8BIT;
01544   }
01545
01546   /* Configure communication direction : 1Line */
01547   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01548   {
01549     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01550     __HAL_SPI_DISABLE(hspi);
01551     SPI_1LINE_TX(hspi);
01552   }
01553
01554 #if (USE_SPI_CRC != 0U)
01555   /* Reset CRC Calculation */
01556   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01557   {
01558     SPI_RESET_CRC(hspi);
01559   }
01560 #endif /* USE_SPI_CRC */
01561
01562   /* Enable TXE and ERR interrupt */
01563   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
01564
01565
01566   /* Check if the SPI is already enabled */
01567   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01568   {
01569     /* Enable SPI peripheral */
01570     __HAL_SPI_ENABLE(hspi);
01571   }
01572
01573 error :
01574   __HAL_UNLOCK(hspi);
01575   return errorcode;
01576 }
01577
01578 /**
01579   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01580   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01581   *               the configuration information for SPI module.
01582   * @param  pData pointer to data buffer
01583   * @param  Size amount of data to be sent
01584   * @retval HAL status
01585   */
01586 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01587 {
01588   HAL_StatusTypeDef errorcode = HAL_OK;
01589
01590   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01591   {
01592     hspi->State = HAL_SPI_STATE_BUSY_RX;
01593     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01594     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
01595   }
01596
01597   /* Process Locked */
01598   __HAL_LOCK(hspi);
01599
01600   if (hspi->State != HAL_SPI_STATE_READY)
01601   {
01602     errorcode = HAL_BUSY;
01603     goto error;
01604   }
01605
01606   if ((pData == NULL) || (Size == 0U))
01607   {
01608     errorcode = HAL_ERROR;
01609     goto error;
01610   }
01611
01612   /* Set the transaction information */
01613   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01614   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01615   hspi->pRxBuffPtr  = (uint8_t *)pData;
01616   hspi->RxXferSize  = Size;
01617   hspi->RxXferCount = Size;
01618
01619   /* Init field not used in handle to zero */
01620   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01621   hspi->TxXferSize  = 0U;
01622   hspi->TxXferCount = 0U;
01623   hspi->TxISR       = NULL;
01624
01625   /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
01626   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01627   {
01628     /* Set RX Fifo threshold according the reception data length: 16 bit */
01629     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01630     hspi->RxISR = SPI_RxISR_16BIT;
01631   }
01632   else
01633   {
01634     /* Set RX Fifo threshold according the reception data length: 8 bit */
01635     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01636     hspi->RxISR = SPI_RxISR_8BIT;
01637   }
01638
01639   /* Configure communication direction : 1Line */
01640   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01641   {
01642     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01643     __HAL_SPI_DISABLE(hspi);
01644     SPI_1LINE_RX(hspi);
01645   }
01646
01647 #if (USE_SPI_CRC != 0U)
01648   /* Reset CRC Calculation */
01649   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01650   {
01651     hspi->CRCSize = 1U;
01652     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01653     {
01654       hspi->CRCSize = 2U;
01655     }
01656     SPI_RESET_CRC(hspi);
01657   }
01658   else
01659   {
01660     hspi->CRCSize = 0U;
01661   }
01662 #endif /* USE_SPI_CRC */
01663
01664   /* Enable TXE and ERR interrupt */
01665   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
01666
01667   /* Note : The SPI must be enabled after unlocking current process
01668             to avoid the risk of SPI interrupt handle execution before current
01669             process unlock */
01670
01671   /* Check if the SPI is already enabled */
01672   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01673   {
01674     /* Enable SPI peripheral */
01675     __HAL_SPI_ENABLE(hspi);
01676   }
01677
01678 error :
01679   /* Process Unlocked */
01680   __HAL_UNLOCK(hspi);
01681   return errorcode;
01682 }
01683
01684 /**
01685   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01686   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01687   *               the configuration information for SPI module.
01688   * @param  pTxData pointer to transmission data buffer
01689   * @param  pRxData pointer to reception data buffer
01690   * @param  Size amount of data to be sent and received
01691   * @retval HAL status
01692   */
01693 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01694 {
01695   uint32_t             tmp_mode;
01696   HAL_SPI_StateTypeDef tmp_state;
01697   HAL_StatusTypeDef    errorcode = HAL_OK;
01698
01699   /* Check Direction parameter */
01700   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01701
01702   /* Process locked */
01703   __HAL_LOCK(hspi);
01704
01705   /* Init temporary variables */
01706   tmp_state           = hspi->State;
01707   tmp_mode            = hspi->Init.Mode;
01708
01709   if (!((tmp_state == HAL_SPI_STATE_READY) || \
01710         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
01711   {
01712     errorcode = HAL_BUSY;
01713     goto error;
01714   }
01715
01716   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01717   {
01718     errorcode = HAL_ERROR;
01719     goto error;
01720   }
01721
01722   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01723   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01724   {
01725     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01726   }
01727
01728   /* Set the transaction information */
01729   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01730   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01731   hspi->TxXferSize  = Size;
01732   hspi->TxXferCount = Size;
01733   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01734   hspi->RxXferSize  = Size;
01735   hspi->RxXferCount = Size;
01736
01737   /* Set the function for IT treatment */
01738   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01739   {
01740     hspi->RxISR     = SPI_2linesRxISR_16BIT;
01741     hspi->TxISR     = SPI_2linesTxISR_16BIT;
01742   }
01743   else
01744   {
01745     hspi->RxISR     = SPI_2linesRxISR_8BIT;
01746     hspi->TxISR     = SPI_2linesTxISR_8BIT;
01747   }
01748
01749 #if (USE_SPI_CRC != 0U)
01750   /* Reset CRC Calculation */
01751   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01752   {
01753     hspi->CRCSize = 1U;
01754     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01755     {
01756       hspi->CRCSize = 2U;
01757     }
01758     SPI_RESET_CRC(hspi);
01759   }
01760   else
01761   {
01762     hspi->CRCSize = 0U;
01763   }
01764 #endif /* USE_SPI_CRC */
01765
01766   /* Check if packing mode is enabled and if there is more than 2 data to receive */
01767   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
01768   {
01769     /* Set RX Fifo threshold according the reception data length: 16 bit */
01770     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01771   }
01772   else
01773   {
01774     /* Set RX Fifo threshold according the reception data length: 8 bit */
01775     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01776   }
01777
01778   /* Enable TXE, RXNE and ERR interrupt */
01779   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
01780
01781   /* Check if the SPI is already enabled */
01782   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01783   {
01784     /* Enable SPI peripheral */
01785     __HAL_SPI_ENABLE(hspi);
01786   }
01787
01788 error :
01789   /* Process Unlocked */
01790   __HAL_UNLOCK(hspi);
01791   return errorcode;
01792 }
01793
01794 /**
01795   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01796   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01797   *               the configuration information for SPI module.
01798   * @param  pData pointer to data buffer
01799   * @param  Size amount of data to be sent
01800   * @retval HAL status
01801   */
01802 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01803 {
01804   HAL_StatusTypeDef errorcode = HAL_OK;
01805
01806   /* Check tx dma handle */
01807   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
01808
01809   /* Check Direction parameter */
01810   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01811
01812   /* Process Locked */
01813   __HAL_LOCK(hspi);
01814
01815   if (hspi->State != HAL_SPI_STATE_READY)
01816   {
01817     errorcode = HAL_BUSY;
01818     goto error;
01819   }
01820
01821   if ((pData == NULL) || (Size == 0U))
01822   {
01823     errorcode = HAL_ERROR;
01824     goto error;
01825   }
01826
01827   /* Set the transaction information */
01828   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01829   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01830   hspi->pTxBuffPtr  = (uint8_t *)pData;
01831   hspi->TxXferSize  = Size;
01832   hspi->TxXferCount = Size;
01833
01834   /* Init field not used in handle to zero */
01835   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01836   hspi->TxISR       = NULL;
01837   hspi->RxISR       = NULL;
01838   hspi->RxXferSize  = 0U;
01839   hspi->RxXferCount = 0U;
01840
01841   /* Configure communication direction : 1Line */
01842   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01843   {
01844     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01845     __HAL_SPI_DISABLE(hspi);
01846     SPI_1LINE_TX(hspi);
01847   }
01848
01849 #if (USE_SPI_CRC != 0U)
01850   /* Reset CRC Calculation */
01851   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01852   {
01853     SPI_RESET_CRC(hspi);
01854   }
01855 #endif /* USE_SPI_CRC */
01856
01857   /* Set the SPI TxDMA Half transfer complete callback */
01858   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01859
01860   /* Set the SPI TxDMA transfer complete callback */
01861   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01862
01863   /* Set the DMA error callback */
01864   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01865
01866   /* Set the DMA AbortCpltCallback */
01867   hspi->hdmatx->XferAbortCallback = NULL;
01868
01869   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01870   /* Packing mode is enabled only if the DMA setting is HALWORD */
01871   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01872   {
01873     /* Check the even/odd of the data size + crc if enabled */
01874     if ((hspi->TxXferCount & 0x1U) == 0U)
01875     {
01876       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01877       hspi->TxXferCount = (hspi->TxXferCount >> 1U);
01878     }
01879     else
01880     {
01881       SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01882       hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
01883     }
01884   }
01885
01886   /* Enable the Tx DMA Stream/Channel */
01887   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
01888                                  hspi->TxXferCount))
01889   {
01890     /* Update SPI error code */
01891     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
01892     errorcode = HAL_ERROR;
01893
01894     hspi->State = HAL_SPI_STATE_READY;
01895     goto error;
01896   }
01897
01898   /* Check if the SPI is already enabled */
01899   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01900   {
01901     /* Enable SPI peripheral */
01902     __HAL_SPI_ENABLE(hspi);
01903   }
01904
01905   /* Enable the SPI Error Interrupt Bit */
01906   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
01907
01908   /* Enable Tx DMA Request */
01909   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01910
01911 error :
01912   /* Process Unlocked */
01913   __HAL_UNLOCK(hspi);
01914   return errorcode;
01915 }
01916
01917 /**
01918   * @brief  Receive an amount of data in non-blocking mode with DMA.
01919   * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
01920   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01921   *               the configuration information for SPI module.
01922   * @param  pData pointer to data buffer
01923   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
01924   * @param  Size amount of data to be sent
01925   * @retval HAL status
01926   */
01927 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01928 {
01929   HAL_StatusTypeDef errorcode = HAL_OK;
01930
01931   /* Check rx dma handle */
01932   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
01933
01934   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01935   {
01936     hspi->State = HAL_SPI_STATE_BUSY_RX;
01937
01938     /* Check tx dma handle */
01939     assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
01940
01941     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01942     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
01943   }
01944
01945   /* Process Locked */
01946   __HAL_LOCK(hspi);
01947
01948   if (hspi->State != HAL_SPI_STATE_READY)
01949   {
01950     errorcode = HAL_BUSY;
01951     goto error;
01952   }
01953
01954   if ((pData == NULL) || (Size == 0U))
01955   {
01956     errorcode = HAL_ERROR;
01957     goto error;
01958   }
01959
01960   /* Set the transaction information */
01961   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01962   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01963   hspi->pRxBuffPtr  = (uint8_t *)pData;
01964   hspi->RxXferSize  = Size;
01965   hspi->RxXferCount = Size;
01966
01967   /*Init field not used in handle to zero */
01968   hspi->RxISR       = NULL;
01969   hspi->TxISR       = NULL;
01970   hspi->TxXferSize  = 0U;
01971   hspi->TxXferCount = 0U;
01972
01973   /* Configure communication direction : 1Line */
01974   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01975   {
01976     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
01977     __HAL_SPI_DISABLE(hspi);
01978     SPI_1LINE_RX(hspi);
01979   }
01980
01981 #if (USE_SPI_CRC != 0U)
01982   /* Reset CRC Calculation */
01983   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01984   {
01985     SPI_RESET_CRC(hspi);
01986   }
01987 #endif /* USE_SPI_CRC */
01988
01989
01990   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01991   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01992   {
01993     /* Set RX Fifo threshold according the reception data length: 16bit */
01994     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01995   }
01996   else
01997   {
01998     /* Set RX Fifo threshold according the reception data length: 8bit */
01999     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02000
02001     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02002     {
02003       /* Set RX Fifo threshold according the reception data length: 16bit */
02004       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02005
02006       if ((hspi->RxXferCount & 0x1U) == 0x0U)
02007       {
02008         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02009         hspi->RxXferCount = hspi->RxXferCount >> 1U;
02010       }
02011       else
02012       {
02013         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02014         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
02015       }
02016     }
02017   }
02018
02019   /* Set the SPI RxDMA Half transfer complete callback */
02020   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
02021
02022   /* Set the SPI Rx DMA transfer complete callback */
02023   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
02024
02025   /* Set the DMA error callback */
02026   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
02027
02028   /* Set the DMA AbortCpltCallback */
02029   hspi->hdmarx->XferAbortCallback = NULL;
02030
02031   /* Enable the Rx DMA Stream/Channel  */
02032   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
02033                                  hspi->RxXferCount))
02034   {
02035     /* Update SPI error code */
02036     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02037     errorcode = HAL_ERROR;
02038
02039     hspi->State = HAL_SPI_STATE_READY;
02040     goto error;
02041   }
02042
02043   /* Check if the SPI is already enabled */
02044   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02045   {
02046     /* Enable SPI peripheral */
02047     __HAL_SPI_ENABLE(hspi);
02048   }
02049
02050   /* Enable the SPI Error Interrupt Bit */
02051   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
02052
02053   /* Enable Rx DMA Request */
02054   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
02055
02056 error:
02057   /* Process Unlocked */
02058   __HAL_UNLOCK(hspi);
02059   return errorcode;
02060 }
02061
02062 /**
02063   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
02064   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02065   *               the configuration information for SPI module.
02066   * @param  pTxData pointer to transmission data buffer
02067   * @param  pRxData pointer to reception data buffer
02068   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
02069   * @param  Size amount of data to be sent
02070   * @retval HAL status
02071   */
02072 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
02073                                               uint16_t Size)
02074 {
02075   uint32_t             tmp_mode;
02076   HAL_SPI_StateTypeDef tmp_state;
02077   HAL_StatusTypeDef errorcode = HAL_OK;
02078
02079   /* Check rx & tx dma handles */
02080   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
02081   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
02082
02083   /* Check Direction parameter */
02084   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
02085
02086   /* Process locked */
02087   __HAL_LOCK(hspi);
02088
02089   /* Init temporary variables */
02090   tmp_state           = hspi->State;
02091   tmp_mode            = hspi->Init.Mode;
02092
02093   if (!((tmp_state == HAL_SPI_STATE_READY) ||
02094         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
02095   {
02096     errorcode = HAL_BUSY;
02097     goto error;
02098   }
02099
02100   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
02101   {
02102     errorcode = HAL_ERROR;
02103     goto error;
02104   }
02105
02106   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
02107   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
02108   {
02109     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
02110   }
02111
02112   /* Set the transaction information */
02113   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
02114   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
02115   hspi->TxXferSize  = Size;
02116   hspi->TxXferCount = Size;
02117   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
02118   hspi->RxXferSize  = Size;
02119   hspi->RxXferCount = Size;
02120
02121   /* Init field not used in handle to zero */
02122   hspi->RxISR       = NULL;
02123   hspi->TxISR       = NULL;
02124
02125 #if (USE_SPI_CRC != 0U)
02126   /* Reset CRC Calculation */
02127   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02128   {
02129     SPI_RESET_CRC(hspi);
02130   }
02131 #endif /* USE_SPI_CRC */
02132
02133   /* Reset the threshold bit */
02134   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
02135
02136   /* The packing mode management is enabled by the DMA settings according the spi data size */
02137   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
02138   {
02139     /* Set fiforxthreshold according the reception data length: 16bit */
02140     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02141   }
02142   else
02143   {
02144     /* Set RX Fifo threshold according the reception data length: 8bit */
02145     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02146
02147     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02148     {
02149       if ((hspi->TxXferSize & 0x1U) == 0x0U)
02150       {
02151         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
02152         hspi->TxXferCount = hspi->TxXferCount >> 1U;
02153       }
02154       else
02155       {
02156         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
02157         hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
02158       }
02159     }
02160
02161     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02162     {
02163       /* Set RX Fifo threshold according the reception data length: 16bit */
02164       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02165
02166       if ((hspi->RxXferCount & 0x1U) == 0x0U)
02167       {
02168         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02169         hspi->RxXferCount = hspi->RxXferCount >> 1U;
02170       }
02171       else
02172       {
02173         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02174         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
02175       }
02176     }
02177   }
02178
02179   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
02180   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
02181   {
02182     /* Set the SPI Rx DMA Half transfer complete callback */
02183     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
02184     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
02185   }
02186   else
02187   {
02188     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
02189     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
02190     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
02191   }
02192
02193   /* Set the DMA error callback */
02194   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
02195
02196   /* Set the DMA AbortCpltCallback */
02197   hspi->hdmarx->XferAbortCallback = NULL;
02198
02199   /* Enable the Rx DMA Stream/Channel  */
02200   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
02201                                  hspi->RxXferCount))
02202   {
02203     /* Update SPI error code */
02204     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02205     errorcode = HAL_ERROR;
02206
02207     hspi->State = HAL_SPI_STATE_READY;
02208     goto error;
02209   }
02210
02211   /* Enable Rx DMA Request */
02212   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
02213
02214   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
02215   is performed in DMA reception complete callback  */
02216   hspi->hdmatx->XferHalfCpltCallback = NULL;
02217   hspi->hdmatx->XferCpltCallback     = NULL;
02218   hspi->hdmatx->XferErrorCallback    = NULL;
02219   hspi->hdmatx->XferAbortCallback    = NULL;
02220
02221   /* Enable the Tx DMA Stream/Channel  */
02222   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
02223                                  hspi->TxXferCount))
02224   {
02225     /* Update SPI error code */
02226     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02227     errorcode = HAL_ERROR;
02228
02229     hspi->State = HAL_SPI_STATE_READY;
02230     goto error;
02231   }
02232
02233   /* Check if the SPI is already enabled */
02234   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02235   {
02236     /* Enable SPI peripheral */
02237     __HAL_SPI_ENABLE(hspi);
02238   }
02239   /* Enable the SPI Error Interrupt Bit */
02240   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
02241
02242   /* Enable Tx DMA Request */
02243   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02244
02245 error :
02246   /* Process Unlocked */
02247   __HAL_UNLOCK(hspi);
02248   return errorcode;
02249 }
02250
02251 /**
02252   * @brief  Abort ongoing transfer (blocking mode).
02253   * @param  hspi SPI handle.
02254   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02255   *         started in Interrupt or DMA mode.
02256   *         This procedure performs following operations :
02257   *           - Disable SPI Interrupts (depending of transfer direction)
02258   *           - Disable the DMA transfer in the peripheral register (if enabled)
02259   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
02260   *           - Set handle State to READY
02261   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
02262   * @retval HAL status
02263   */
02264 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
02265 {
02266   HAL_StatusTypeDef errorcode;
02267   __IO uint32_t count;
02268   __IO uint32_t resetcount;
02269
02270   /* Initialized local variable  */
02271   errorcode = HAL_OK;
02272   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02273   count = resetcount;
02274
02275   /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
02276   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
02277
02278   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
02279   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
02280   {
02281     hspi->TxISR = SPI_AbortTx_ISR;
02282     /* Wait HAL_SPI_STATE_ABORT state */
02283     do
02284     {
02285       if (count == 0U)
02286       {
02287         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02288         break;
02289       }
02290       count--;
02291     } while (hspi->State != HAL_SPI_STATE_ABORT);
02292     /* Reset Timeout Counter */
02293     count = resetcount;
02294   }
02295
02296   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
02297   {
02298     hspi->RxISR = SPI_AbortRx_ISR;
02299     /* Wait HAL_SPI_STATE_ABORT state */
02300     do
02301     {
02302       if (count == 0U)
02303       {
02304         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02305         break;
02306       }
02307       count--;
02308     } while (hspi->State != HAL_SPI_STATE_ABORT);
02309     /* Reset Timeout Counter */
02310     count = resetcount;
02311   }
02312
02313   /* Disable the SPI DMA Tx request if enabled */
02314   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02315   {
02316     /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
02317     if (hspi->hdmatx != NULL)
02318     {
02319       /* Set the SPI DMA Abort callback :
02320       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02321       hspi->hdmatx->XferAbortCallback = NULL;
02322
02323       /* Abort DMA Tx Handle linked to SPI Peripheral */
02324       if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
02325       {
02326         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02327       }
02328
02329       /* Disable Tx DMA Request */
02330       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
02331
02332       if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02333       {
02334         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02335       }
02336
02337       /* Disable SPI Peripheral */
02338       __HAL_SPI_DISABLE(hspi);
02339
02340       /* Empty the FRLVL fifo */
02341       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02342       {
02343         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02344       }
02345     }
02346   }
02347
02348   /* Disable the SPI DMA Rx request if enabled */
02349   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02350   {
02351     /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
02352     if (hspi->hdmarx != NULL)
02353     {
02354       /* Set the SPI DMA Abort callback :
02355       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02356       hspi->hdmarx->XferAbortCallback = NULL;
02357
02358       /* Abort DMA Rx Handle linked to SPI Peripheral */
02359       if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
02360       {
02361         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02362       }
02363
02364       /* Disable peripheral */
02365       __HAL_SPI_DISABLE(hspi);
02366
02367       /* Control the BSY flag */
02368       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02369       {
02370         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02371       }
02372
02373       /* Empty the FRLVL fifo */
02374       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02375       {
02376         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02377       }
02378
02379       /* Disable Rx DMA Request */
02380       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
02381     }
02382   }
02383   /* Reset Tx and Rx transfer counters */
02384   hspi->RxXferCount = 0U;
02385   hspi->TxXferCount = 0U;
02386
02387   /* Check error during Abort procedure */
02388   if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02389   {
02390     /* return HAL_Error in case of error during Abort procedure */
02391     errorcode = HAL_ERROR;
02392   }
02393   else
02394   {
02395     /* Reset errorCode */
02396     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02397   }
02398
02399   /* Clear the Error flags in the SR register */
02400   __HAL_SPI_CLEAR_OVRFLAG(hspi);
02401   __HAL_SPI_CLEAR_FREFLAG(hspi);
02402
02403   /* Restore hspi->state to ready */
02404   hspi->State = HAL_SPI_STATE_READY;
02405
02406   return errorcode;
02407 }
02408
02409 /**
02410   * @brief  Abort ongoing transfer (Interrupt mode).
02411   * @param  hspi SPI handle.
02412   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02413   *         started in Interrupt or DMA mode.
02414   *         This procedure performs following operations :
02415   *           - Disable SPI Interrupts (depending of transfer direction)
02416   *           - Disable the DMA transfer in the peripheral register (if enabled)
02417   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02418   *           - Set handle State to READY
02419   *           - At abort completion, call user abort complete callback
02420   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02421   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02422   * @retval HAL status
02423   */
02424 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
02425 {
02426   HAL_StatusTypeDef errorcode;
02427   uint32_t abortcplt ;
02428   __IO uint32_t count;
02429   __IO uint32_t resetcount;
02430
02431   /* Initialized local variable  */
02432   errorcode = HAL_OK;
02433   abortcplt = 1U;
02434   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02435   count = resetcount;
02436
02437   /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
02438   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
02439
02440   /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
02441   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
02442   {
02443     hspi->TxISR = SPI_AbortTx_ISR;
02444     /* Wait HAL_SPI_STATE_ABORT state */
02445     do
02446     {
02447       if (count == 0U)
02448       {
02449         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02450         break;
02451       }
02452       count--;
02453     } while (hspi->State != HAL_SPI_STATE_ABORT);
02454     /* Reset Timeout Counter */
02455     count = resetcount;
02456   }
02457
02458   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
02459   {
02460     hspi->RxISR = SPI_AbortRx_ISR;
02461     /* Wait HAL_SPI_STATE_ABORT state */
02462     do
02463     {
02464       if (count == 0U)
02465       {
02466         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02467         break;
02468       }
02469       count--;
02470     } while (hspi->State != HAL_SPI_STATE_ABORT);
02471     /* Reset Timeout Counter */
02472     count = resetcount;
02473   }
02474
02475   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
02476      before any call to DMA Abort functions */
02477   /* DMA Tx Handle is valid */
02478   if (hspi->hdmatx != NULL)
02479   {
02480     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
02481        Otherwise, set it to NULL */
02482     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02483     {
02484       hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
02485     }
02486     else
02487     {
02488       hspi->hdmatx->XferAbortCallback = NULL;
02489     }
02490   }
02491   /* DMA Rx Handle is valid */
02492   if (hspi->hdmarx != NULL)
02493   {
02494     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
02495        Otherwise, set it to NULL */
02496     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02497     {
02498       hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
02499     }
02500     else
02501     {
02502       hspi->hdmarx->XferAbortCallback = NULL;
02503     }
02504   }
02505
02506   /* Disable the SPI DMA Tx request if enabled */
02507   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02508   {
02509     /* Abort the SPI DMA Tx Stream/Channel */
02510     if (hspi->hdmatx != NULL)
02511     {
02512       /* Abort DMA Tx Handle linked to SPI Peripheral */
02513       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
02514       {
02515         hspi->hdmatx->XferAbortCallback = NULL;
02516         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02517       }
02518       else
02519       {
02520         abortcplt = 0U;
02521       }
02522     }
02523   }
02524   /* Disable the SPI DMA Rx request if enabled */
02525   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02526   {
02527     /* Abort the SPI DMA Rx Stream/Channel */
02528     if (hspi->hdmarx != NULL)
02529     {
02530       /* Abort DMA Rx Handle linked to SPI Peripheral */
02531       if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
02532       {
02533         hspi->hdmarx->XferAbortCallback = NULL;
02534         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02535       }
02536       else
02537       {
02538         abortcplt = 0U;
02539       }
02540     }
02541   }
02542
02543   if (abortcplt == 1U)
02544   {
02545     /* Reset Tx and Rx transfer counters */
02546     hspi->RxXferCount = 0U;
02547     hspi->TxXferCount = 0U;
02548
02549     /* Check error during Abort procedure */
02550     if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02551     {
02552       /* return HAL_Error in case of error during Abort procedure */
02553       errorcode = HAL_ERROR;
02554     }
02555     else
02556     {
02557       /* Reset errorCode */
02558       hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02559     }
02560
02561     /* Clear the Error flags in the SR register */
02562     __HAL_SPI_CLEAR_OVRFLAG(hspi);
02563     __HAL_SPI_CLEAR_FREFLAG(hspi);
02564
02565     /* Restore hspi->State to Ready */
02566     hspi->State = HAL_SPI_STATE_READY;
02567
02568     /* As no DMA to be aborted, call directly user Abort complete callback */
02569 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02570     hspi->AbortCpltCallback(hspi);
02571 #else
02572     HAL_SPI_AbortCpltCallback(hspi);
02573 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02574   }
02575
02576   return errorcode;
02577 }
02578
02579 /**
02580   * @brief  Pause the DMA Transfer.
02581   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02582   *               the configuration information for the specified SPI module.
02583   * @retval HAL status
02584   */
02585 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
02586 {
02587   /* Process Locked */
02588   __HAL_LOCK(hspi);
02589
02590   /* Disable the SPI DMA Tx & Rx requests */
02591   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02592
02593   /* Process Unlocked */
02594   __HAL_UNLOCK(hspi);
02595
02596   return HAL_OK;
02597 }
02598
02599 /**
02600   * @brief  Resume the DMA Transfer.
02601   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02602   *               the configuration information for the specified SPI module.
02603   * @retval HAL status
02604   */
02605 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
02606 {
02607   /* Process Locked */
02608   __HAL_LOCK(hspi);
02609
02610   /* Enable the SPI DMA Tx & Rx requests */
02611   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02612
02613   /* Process Unlocked */
02614   __HAL_UNLOCK(hspi);
02615
02616   return HAL_OK;
02617 }
02618
02619 /**
02620   * @brief  Stop the DMA Transfer.
02621   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02622   *               the configuration information for the specified SPI module.
02623   * @retval HAL status
02624   */
02625 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
02626 {
02627   HAL_StatusTypeDef errorcode = HAL_OK;
02628   /* The Lock is not implemented on this API to allow the user application
02629      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
02630      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
02631      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
02632      */
02633
02634   /* Abort the SPI DMA tx Stream/Channel  */
02635   if (hspi->hdmatx != NULL)
02636   {
02637     if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
02638     {
02639       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02640       errorcode = HAL_ERROR;
02641     }
02642   }
02643   /* Abort the SPI DMA rx Stream/Channel  */
02644   if (hspi->hdmarx != NULL)
02645   {
02646     if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
02647     {
02648       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02649       errorcode = HAL_ERROR;
02650     }
02651   }
02652
02653   /* Disable the SPI DMA Tx & Rx requests */
02654   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02655   hspi->State = HAL_SPI_STATE_READY;
02656   return errorcode;
02657 }
02658
02659 /**
02660   * @brief  Handle SPI interrupt request.
02661   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02662   *               the configuration information for the specified SPI module.
02663   * @retval None
02664   */
02665 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
02666 {
02667   uint32_t itsource = hspi->Instance->CR2;
02668   uint32_t itflag   = hspi->Instance->SR;
02669
02670   /* SPI in mode Receiver ----------------------------------------------------*/
02671   if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
02672       (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
02673   {
02674     hspi->RxISR(hspi);
02675     return;
02676   }
02677
02678   /* SPI in mode Transmitter -------------------------------------------------*/
02679   if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
02680   {
02681     hspi->TxISR(hspi);
02682     return;
02683   }
02684
02685   /* SPI in Error Treatment --------------------------------------------------*/
02686   if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
02687        || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
02688   {
02689     /* SPI Overrun error interrupt occurred ----------------------------------*/
02690     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
02691     {
02692       if (hspi->State != HAL_SPI_STATE_BUSY_TX)
02693       {
02694         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
02695         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02696       }
02697       else
02698       {
02699         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02700         return;
02701       }
02702     }
02703
02704     /* SPI Mode Fault error interrupt occurred -------------------------------*/
02705     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
02706     {
02707       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
02708       __HAL_SPI_CLEAR_MODFFLAG(hspi);
02709     }
02710
02711     /* SPI Frame error interrupt occurred ------------------------------------*/
02712     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
02713     {
02714       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
02715       __HAL_SPI_CLEAR_FREFLAG(hspi);
02716     }
02717
02718     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02719     {
02720       /* Disable all interrupts */
02721       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
02722
02723       hspi->State = HAL_SPI_STATE_READY;
02724       /* Disable the SPI DMA requests if enabled */
02725       if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
02726       {
02727         CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
02728
02729         /* Abort the SPI DMA Rx channel */
02730         if (hspi->hdmarx != NULL)
02731         {
02732           /* Set the SPI DMA Abort callback :
02733           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02734           hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
02735           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
02736           {
02737             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02738           }
02739         }
02740         /* Abort the SPI DMA Tx channel */
02741         if (hspi->hdmatx != NULL)
02742         {
02743           /* Set the SPI DMA Abort callback :
02744           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02745           hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
02746           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
02747           {
02748             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02749           }
02750         }
02751       }
02752       else
02753       {
02754         /* Call user error callback */
02755 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02756         hspi->ErrorCallback(hspi);
02757 #else
02758         HAL_SPI_ErrorCallback(hspi);
02759 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02760       }
02761     }
02762     return;
02763   }
02764 }
02765
02766 /**
02767   * @brief  Tx Transfer completed callback.
02768   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02769   *               the configuration information for SPI module.
02770   * @retval None
02771   */
02772 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
02773 {
02774   /* Prevent unused argument(s) compilation warning */
02775   UNUSED(hspi);
02776
02777   /* NOTE : This function should not be modified, when the callback is needed,
02778             the HAL_SPI_TxCpltCallback should be implemented in the user file
02779    */
02780 }
02781
02782 /**
02783   * @brief  Rx Transfer completed callback.
02784   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02785   *               the configuration information for SPI module.
02786   * @retval None
02787   */
02788 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
02789 {
02790   /* Prevent unused argument(s) compilation warning */
02791   UNUSED(hspi);
02792
02793   /* NOTE : This function should not be modified, when the callback is needed,
02794             the HAL_SPI_RxCpltCallback should be implemented in the user file
02795    */
02796 }
02797
02798 /**
02799   * @brief  Tx and Rx Transfer completed callback.
02800   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02801   *               the configuration information for SPI module.
02802   * @retval None
02803   */
02804 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
02805 {
02806   /* Prevent unused argument(s) compilation warning */
02807   UNUSED(hspi);
02808
02809   /* NOTE : This function should not be modified, when the callback is needed,
02810             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
02811    */
02812 }
02813
02814 /**
02815   * @brief  Tx Half Transfer completed callback.
02816   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02817   *               the configuration information for SPI module.
02818   * @retval None
02819   */
02820 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02821 {
02822   /* Prevent unused argument(s) compilation warning */
02823   UNUSED(hspi);
02824
02825   /* NOTE : This function should not be modified, when the callback is needed,
02826             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
02827    */
02828 }
02829
02830 /**
02831   * @brief  Rx Half Transfer completed callback.
02832   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02833   *               the configuration information for SPI module.
02834   * @retval None
02835   */
02836 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02837 {
02838   /* Prevent unused argument(s) compilation warning */
02839   UNUSED(hspi);
02840
02841   /* NOTE : This function should not be modified, when the callback is needed,
02842             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
02843    */
02844 }
02845
02846 /**
02847   * @brief  Tx and Rx Half Transfer callback.
02848   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02849   *               the configuration information for SPI module.
02850   * @retval None
02851   */
02852 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02853 {
02854   /* Prevent unused argument(s) compilation warning */
02855   UNUSED(hspi);
02856
02857   /* NOTE : This function should not be modified, when the callback is needed,
02858             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
02859    */
02860 }
02861
02862 /**
02863   * @brief  SPI error callback.
02864   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02865   *               the configuration information for SPI module.
02866   * @retval None
02867   */
02868 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
02869 {
02870   /* Prevent unused argument(s) compilation warning */
02871   UNUSED(hspi);
02872
02873   /* NOTE : This function should not be modified, when the callback is needed,
02874             the HAL_SPI_ErrorCallback should be implemented in the user file
02875    */
02876   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
02877             and user can use HAL_SPI_GetError() API to check the latest error occurred
02878    */
02879 }
02880
02881 /**
02882   * @brief  SPI Abort Complete callback.
02883   * @param  hspi SPI handle.
02884   * @retval None
02885   */
02886 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
02887 {
02888   /* Prevent unused argument(s) compilation warning */
02889   UNUSED(hspi);
02890
02891   /* NOTE : This function should not be modified, when the callback is needed,
02892             the HAL_SPI_AbortCpltCallback can be implemented in the user file.
02893    */
02894 }
02895
02896 /**
02897   * @}
02898   */
02899
02900 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
02901   * @brief   SPI control functions
02902   *
02903 @verbatim
02904  ===============================================================================
02905                       ##### Peripheral State and Errors functions #####
02906  ===============================================================================
02907     [..]
02908     This subsection provides a set of functions allowing to control the SPI.
02909      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
02910      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
02911 @endverbatim
02912   * @{
02913   */
02914
02915 /**
02916   * @brief  Return the SPI handle state.
02917   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02918   *               the configuration information for SPI module.
02919   * @retval SPI state
02920   */
02921 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
02922 {
02923   /* Return SPI handle state */
02924   return hspi->State;
02925 }
02926
02927 /**
02928   * @brief  Return the SPI error code.
02929   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02930   *               the configuration information for SPI module.
02931   * @retval SPI error code in bitmap format
02932   */
02933 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
02934 {
02935   /* Return SPI ErrorCode */
02936   return hspi->ErrorCode;
02937 }
02938
02939 /**
02940   * @}
02941   */
02942
02943 /**
02944   * @}
02945   */
02946
02947 /** @addtogroup SPI_Private_Functions
02948   * @brief   Private functions
02949   * @{
02950   */
02951
02952 /**
02953   * @brief  DMA SPI transmit process complete callback.
02954   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02955   *               the configuration information for the specified DMA module.
02956   * @retval None
02957   */
02958 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02959 {
02960   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
02961   uint32_t tickstart;
02962
02963   /* Init tickstart for timeout management*/
02964   tickstart = HAL_GetTick();
02965
02966   /* DMA Normal Mode */
02967   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02968   {
02969     /* Disable ERR interrupt */
02970     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02971
02972     /* Disable Tx DMA Request */
02973     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02974
02975     /* Check the end of the transaction */
02976     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02977     {
02978       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02979     }
02980
02981     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
02982     if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
02983     {
02984       __HAL_SPI_CLEAR_OVRFLAG(hspi);
02985     }
02986
02987     hspi->TxXferCount = 0U;
02988     hspi->State = HAL_SPI_STATE_READY;
02989
02990     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02991     {
02992       /* Call user error callback */
02993 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02994       hspi->ErrorCallback(hspi);
02995 #else
02996       HAL_SPI_ErrorCallback(hspi);
02997 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02998       return;
02999     }
03000   }
03001   /* Call user Tx complete callback */
03002 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03003   hspi->TxCpltCallback(hspi);
03004 #else
03005   HAL_SPI_TxCpltCallback(hspi);
03006 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03007 }
03008
03009 /**
03010   * @brief  DMA SPI receive process complete callback.
03011   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03012   *               the configuration information for the specified DMA module.
03013   * @retval None
03014   */
03015 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
03016 {
03017   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03018   uint32_t tickstart;
03019 #if (USE_SPI_CRC != 0U)
03020   __IO uint32_t tmpreg = 0U;
03021   __IO uint8_t  *ptmpreg8;
03022   __IO uint8_t  tmpreg8 = 0;
03023 #endif /* USE_SPI_CRC */
03024
03025   /* Init tickstart for timeout management*/
03026   tickstart = HAL_GetTick();
03027
03028   /* DMA Normal Mode */
03029   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
03030   {
03031     /* Disable ERR interrupt */
03032     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03033
03034 #if (USE_SPI_CRC != 0U)
03035     /* CRC handling */
03036     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03037     {
03038       /* Wait until RXNE flag */
03039       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03040       {
03041         /* Error on the CRC reception */
03042         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03043       }
03044       /* Read CRC */
03045       if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
03046       {
03047         /* Read 16bit CRC */
03048         tmpreg = READ_REG(hspi->Instance->DR);
03049         /* To avoid GCC warning */
03050         UNUSED(tmpreg);
03051       }
03052       else
03053       {
03054         /* Initialize the 8bit temporary pointer */
03055         ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03056         /* Read 8bit CRC */
03057         tmpreg8 = *ptmpreg8;
03058         /* To avoid GCC warning */
03059         UNUSED(tmpreg8);
03060
03061         if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
03062         {
03063           if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03064           {
03065             /* Error on the CRC reception */
03066             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03067           }
03068           /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
03069           tmpreg8 = *ptmpreg8;
03070           /* To avoid GCC warning */
03071           UNUSED(tmpreg8);
03072         }
03073       }
03074     }
03075 #endif /* USE_SPI_CRC */
03076
03077     /* Check if we are in Master RX 2 line mode */
03078     if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
03079     {
03080       /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
03081       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03082     }
03083     else
03084     {
03085       /* Normal case */
03086       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
03087     }
03088
03089     /* Check the end of the transaction */
03090     if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03091     {
03092       hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
03093     }
03094
03095     hspi->RxXferCount = 0U;
03096     hspi->State = HAL_SPI_STATE_READY;
03097
03098 #if (USE_SPI_CRC != 0U)
03099     /* Check if CRC error occurred */
03100     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
03101     {
03102       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03103       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03104     }
03105 #endif /* USE_SPI_CRC */
03106
03107     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03108     {
03109       /* Call user error callback */
03110 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03111       hspi->ErrorCallback(hspi);
03112 #else
03113       HAL_SPI_ErrorCallback(hspi);
03114 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03115       return;
03116     }
03117   }
03118   /* Call user Rx complete callback */
03119 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03120   hspi->RxCpltCallback(hspi);
03121 #else
03122   HAL_SPI_RxCpltCallback(hspi);
03123 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03124 }
03125
03126 /**
03127   * @brief  DMA SPI transmit receive process complete callback.
03128   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03129   *               the configuration information for the specified DMA module.
03130   * @retval None
03131   */
03132 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
03133 {
03134   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03135   uint32_t tickstart;
03136 #if (USE_SPI_CRC != 0U)
03137   __IO uint32_t tmpreg = 0U;
03138   __IO uint8_t  *ptmpreg8;
03139   __IO uint8_t  tmpreg8 = 0;
03140 #endif /* USE_SPI_CRC */
03141
03142   /* Init tickstart for timeout management*/
03143   tickstart = HAL_GetTick();
03144
03145   /* DMA Normal Mode */
03146   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
03147   {
03148     /* Disable ERR interrupt */
03149     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03150
03151 #if (USE_SPI_CRC != 0U)
03152     /* CRC handling */
03153     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03154     {
03155       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
03156       {
03157         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
03158                                           tickstart) != HAL_OK)
03159         {
03160           /* Error on the CRC reception */
03161           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03162         }
03163         /* Initialize the 8bit temporary pointer */
03164         ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03165         /* Read 8bit CRC */
03166         tmpreg8 = *ptmpreg8;
03167         /* To avoid GCC warning */
03168         UNUSED(tmpreg8);
03169       }
03170       else
03171       {
03172         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03173         {
03174           /* Error on the CRC reception */
03175           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03176         }
03177         /* Read CRC to Flush DR and RXNE flag */
03178         tmpreg = READ_REG(hspi->Instance->DR);
03179         /* To avoid GCC warning */
03180         UNUSED(tmpreg);
03181       }
03182     }
03183 #endif /* USE_SPI_CRC */
03184
03185     /* Check the end of the transaction */
03186     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03187     {
03188       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03189     }
03190
03191     /* Disable Rx/Tx DMA Request */
03192     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03193
03194     hspi->TxXferCount = 0U;
03195     hspi->RxXferCount = 0U;
03196     hspi->State = HAL_SPI_STATE_READY;
03197
03198 #if (USE_SPI_CRC != 0U)
03199     /* Check if CRC error occurred */
03200     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
03201     {
03202       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03203       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03204     }
03205 #endif /* USE_SPI_CRC */
03206
03207     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03208     {
03209       /* Call user error callback */
03210 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03211       hspi->ErrorCallback(hspi);
03212 #else
03213       HAL_SPI_ErrorCallback(hspi);
03214 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03215       return;
03216     }
03217   }
03218   /* Call user TxRx complete callback */
03219 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03220   hspi->TxRxCpltCallback(hspi);
03221 #else
03222   HAL_SPI_TxRxCpltCallback(hspi);
03223 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03224 }
03225
03226 /**
03227   * @brief  DMA SPI half transmit process complete callback.
03228   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03229   *               the configuration information for the specified DMA module.
03230   * @retval None
03231   */
03232 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
03233 {
03234   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03235
03236   /* Call user Tx half complete callback */
03237 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03238   hspi->TxHalfCpltCallback(hspi);
03239 #else
03240   HAL_SPI_TxHalfCpltCallback(hspi);
03241 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03242 }
03243
03244 /**
03245   * @brief  DMA SPI half receive process complete callback
03246   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03247   *               the configuration information for the specified DMA module.
03248   * @retval None
03249   */
03250 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
03251 {
03252   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03253
03254   /* Call user Rx half complete callback */
03255 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03256   hspi->RxHalfCpltCallback(hspi);
03257 #else
03258   HAL_SPI_RxHalfCpltCallback(hspi);
03259 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03260 }
03261
03262 /**
03263   * @brief  DMA SPI half transmit receive process complete callback.
03264   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03265   *               the configuration information for the specified DMA module.
03266   * @retval None
03267   */
03268 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
03269 {
03270   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03271
03272   /* Call user TxRx half complete callback */
03273 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03274   hspi->TxRxHalfCpltCallback(hspi);
03275 #else
03276   HAL_SPI_TxRxHalfCpltCallback(hspi);
03277 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03278 }
03279
03280 /**
03281   * @brief  DMA SPI communication error callback.
03282   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03283   *               the configuration information for the specified DMA module.
03284   * @retval None
03285   */
03286 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
03287 {
03288   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03289
03290   /* Stop the disable DMA transfer on SPI side */
03291   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03292
03293   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
03294   hspi->State = HAL_SPI_STATE_READY;
03295   /* Call user error callback */
03296 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03297   hspi->ErrorCallback(hspi);
03298 #else
03299   HAL_SPI_ErrorCallback(hspi);
03300 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03301 }
03302
03303 /**
03304   * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
03305   *         (To be called at end of DMA Abort procedure following error occurrence).
03306   * @param  hdma DMA handle.
03307   * @retval None
03308   */
03309 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
03310 {
03311   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03312   hspi->RxXferCount = 0U;
03313   hspi->TxXferCount = 0U;
03314
03315   /* Call user error callback */
03316 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03317   hspi->ErrorCallback(hspi);
03318 #else
03319   HAL_SPI_ErrorCallback(hspi);
03320 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03321 }
03322
03323 /**
03324   * @brief  DMA SPI Tx communication abort callback, when initiated by user
03325   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03326   * @note   When this callback is executed, User Abort complete call back is called only if no
03327   *         Abort still ongoing for Rx DMA Handle.
03328   * @param  hdma DMA handle.
03329   * @retval None
03330   */
03331 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03332 {
03333   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03334
03335   hspi->hdmatx->XferAbortCallback = NULL;
03336
03337   /* Disable Tx DMA Request */
03338   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
03339
03340   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03341   {
03342     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03343   }
03344
03345   /* Disable SPI Peripheral */
03346   __HAL_SPI_DISABLE(hspi);
03347
03348   /* Empty the FRLVL fifo */
03349   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03350   {
03351     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03352   }
03353
03354   /* Check if an Abort process is still ongoing */
03355   if (hspi->hdmarx != NULL)
03356   {
03357     if (hspi->hdmarx->XferAbortCallback != NULL)
03358     {
03359       return;
03360     }
03361   }
03362
03363   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03364   hspi->RxXferCount = 0U;
03365   hspi->TxXferCount = 0U;
03366
03367   /* Check no error during Abort procedure */
03368   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03369   {
03370     /* Reset errorCode */
03371     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03372   }
03373
03374   /* Clear the Error flags in the SR register */
03375   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03376   __HAL_SPI_CLEAR_FREFLAG(hspi);
03377
03378   /* Restore hspi->State to Ready */
03379   hspi->State  = HAL_SPI_STATE_READY;
03380
03381   /* Call user Abort complete callback */
03382 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03383   hspi->AbortCpltCallback(hspi);
03384 #else
03385   HAL_SPI_AbortCpltCallback(hspi);
03386 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03387 }
03388
03389 /**
03390   * @brief  DMA SPI Rx communication abort callback, when initiated by user
03391   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03392   * @note   When this callback is executed, User Abort complete call back is called only if no
03393   *         Abort still ongoing for Tx DMA Handle.
03394   * @param  hdma DMA handle.
03395   * @retval None
03396   */
03397 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03398 {
03399   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03400
03401   /* Disable SPI Peripheral */
03402   __HAL_SPI_DISABLE(hspi);
03403
03404   hspi->hdmarx->XferAbortCallback = NULL;
03405
03406   /* Disable Rx DMA Request */
03407   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
03408
03409   /* Control the BSY flag */
03410   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03411   {
03412     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03413   }
03414
03415   /* Empty the FRLVL fifo */
03416   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03417   {
03418     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03419   }
03420
03421   /* Check if an Abort process is still ongoing */
03422   if (hspi->hdmatx != NULL)
03423   {
03424     if (hspi->hdmatx->XferAbortCallback != NULL)
03425     {
03426       return;
03427     }
03428   }
03429
03430   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03431   hspi->RxXferCount = 0U;
03432   hspi->TxXferCount = 0U;
03433
03434   /* Check no error during Abort procedure */
03435   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03436   {
03437     /* Reset errorCode */
03438     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03439   }
03440
03441   /* Clear the Error flags in the SR register */
03442   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03443   __HAL_SPI_CLEAR_FREFLAG(hspi);
03444
03445   /* Restore hspi->State to Ready */
03446   hspi->State  = HAL_SPI_STATE_READY;
03447
03448   /* Call user Abort complete callback */
03449 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03450   hspi->AbortCpltCallback(hspi);
03451 #else
03452   HAL_SPI_AbortCpltCallback(hspi);
03453 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03454 }
03455
03456 /**
03457   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03458   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03459   *               the configuration information for SPI module.
03460   * @retval None
03461   */
03462 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03463 {
03464   /* Receive data in packing mode */
03465   if (hspi->RxXferCount > 1U)
03466   {
03467     *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03468     hspi->pRxBuffPtr += sizeof(uint16_t);
03469     hspi->RxXferCount -= 2U;
03470     if (hspi->RxXferCount == 1U)
03471     {
03472       /* Set RX Fifo threshold according the reception data length: 8bit */
03473       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
03474     }
03475   }
03476   /* Receive data in 8 Bit mode */
03477   else
03478   {
03479     *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
03480     hspi->pRxBuffPtr++;
03481     hspi->RxXferCount--;
03482   }
03483
03484   /* Check end of the reception */
03485   if (hspi->RxXferCount == 0U)
03486   {
03487 #if (USE_SPI_CRC != 0U)
03488     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03489     {
03490       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
03491       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
03492       return;
03493     }
03494 #endif /* USE_SPI_CRC */
03495
03496     /* Disable RXNE  and ERR interrupt */
03497     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03498
03499     if (hspi->TxXferCount == 0U)
03500     {
03501       SPI_CloseRxTx_ISR(hspi);
03502     }
03503   }
03504 }
03505
03506 #if (USE_SPI_CRC != 0U)
03507 /**
03508   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03509   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03510   *               the configuration information for SPI module.
03511   * @retval None
03512   */
03513 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
03514 {
03515   __IO uint8_t  *ptmpreg8;
03516   __IO uint8_t  tmpreg8 = 0;
03517
03518   /* Initialize the 8bit temporary pointer */
03519   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03520   /* Read 8bit CRC to flush Data Register */
03521   tmpreg8 = *ptmpreg8;
03522   /* To avoid GCC warning */
03523   UNUSED(tmpreg8);
03524
03525   hspi->CRCSize--;
03526
03527   /* Check end of the reception */
03528   if (hspi->CRCSize == 0U)
03529   {
03530     /* Disable RXNE and ERR interrupt */
03531     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03532
03533     if (hspi->TxXferCount == 0U)
03534     {
03535       SPI_CloseRxTx_ISR(hspi);
03536     }
03537   }
03538 }
03539 #endif /* USE_SPI_CRC */
03540
03541 /**
03542   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
03543   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03544   *               the configuration information for SPI module.
03545   * @retval None
03546   */
03547 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03548 {
03549   /* Transmit data in packing Bit mode */
03550   if (hspi->TxXferCount >= 2U)
03551   {
03552     hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03553     hspi->pTxBuffPtr += sizeof(uint16_t);
03554     hspi->TxXferCount -= 2U;
03555   }
03556   /* Transmit data in 8 Bit mode */
03557   else
03558   {
03559     *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
03560     hspi->pTxBuffPtr++;
03561     hspi->TxXferCount--;
03562   }
03563
03564   /* Check the end of the transmission */
03565   if (hspi->TxXferCount == 0U)
03566   {
03567 #if (USE_SPI_CRC != 0U)
03568     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03569     {
03570       /* Set CRC Next Bit to send CRC */
03571       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03572       /* Disable TXE interrupt */
03573       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03574       return;
03575     }
03576 #endif /* USE_SPI_CRC */
03577
03578     /* Disable TXE interrupt */
03579     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03580
03581     if (hspi->RxXferCount == 0U)
03582     {
03583       SPI_CloseRxTx_ISR(hspi);
03584     }
03585   }
03586 }
03587
03588 /**
03589   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
03590   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03591   *               the configuration information for SPI module.
03592   * @retval None
03593   */
03594 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03595 {
03596   /* Receive data in 16 Bit mode */
03597   *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03598   hspi->pRxBuffPtr += sizeof(uint16_t);
03599   hspi->RxXferCount--;
03600
03601   if (hspi->RxXferCount == 0U)
03602   {
03603 #if (USE_SPI_CRC != 0U)
03604     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03605     {
03606       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
03607       return;
03608     }
03609 #endif /* USE_SPI_CRC */
03610
03611     /* Disable RXNE interrupt */
03612     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03613
03614     if (hspi->TxXferCount == 0U)
03615     {
03616       SPI_CloseRxTx_ISR(hspi);
03617     }
03618   }
03619 }
03620
03621 #if (USE_SPI_CRC != 0U)
03622 /**
03623   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
03624   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03625   *               the configuration information for SPI module.
03626   * @retval None
03627   */
03628 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
03629 {
03630   __IO uint32_t tmpreg = 0U;
03631
03632   /* Read 16bit CRC to flush Data Register */
03633   tmpreg = READ_REG(hspi->Instance->DR);
03634   /* To avoid GCC warning */
03635   UNUSED(tmpreg);
03636
03637   /* Disable RXNE interrupt */
03638   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03639
03640   SPI_CloseRxTx_ISR(hspi);
03641 }
03642 #endif /* USE_SPI_CRC */
03643
03644 /**
03645   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
03646   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03647   *               the configuration information for SPI module.
03648   * @retval None
03649   */
03650 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03651 {
03652   /* Transmit data in 16 Bit mode */
03653   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03654   hspi->pTxBuffPtr += sizeof(uint16_t);
03655   hspi->TxXferCount--;
03656
03657   /* Enable CRC Transmission */
03658   if (hspi->TxXferCount == 0U)
03659   {
03660 #if (USE_SPI_CRC != 0U)
03661     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03662     {
03663       /* Set CRC Next Bit to send CRC */
03664       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03665       /* Disable TXE interrupt */
03666       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03667       return;
03668     }
03669 #endif /* USE_SPI_CRC */
03670
03671     /* Disable TXE interrupt */
03672     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03673
03674     if (hspi->RxXferCount == 0U)
03675     {
03676       SPI_CloseRxTx_ISR(hspi);
03677     }
03678   }
03679 }
03680
03681 #if (USE_SPI_CRC != 0U)
03682 /**
03683   * @brief  Manage the CRC 8-bit receive in Interrupt context.
03684   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03685   *               the configuration information for SPI module.
03686   * @retval None
03687   */
03688 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
03689 {
03690   __IO uint8_t  *ptmpreg8;
03691   __IO uint8_t  tmpreg8 = 0;
03692
03693   /* Initialize the 8bit temporary pointer */
03694   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03695   /* Read 8bit CRC to flush Data Register */
03696   tmpreg8 = *ptmpreg8;
03697   /* To avoid GCC warning */
03698   UNUSED(tmpreg8);
03699
03700   hspi->CRCSize--;
03701
03702   if (hspi->CRCSize == 0U)
03703   {
03704     SPI_CloseRx_ISR(hspi);
03705   }
03706 }
03707 #endif /* USE_SPI_CRC */
03708
03709 /**
03710   * @brief  Manage the receive 8-bit in Interrupt context.
03711   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03712   *               the configuration information for SPI module.
03713   * @retval None
03714   */
03715 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03716 {
03717   *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
03718   hspi->pRxBuffPtr++;
03719   hspi->RxXferCount--;
03720
03721 #if (USE_SPI_CRC != 0U)
03722   /* Enable CRC Transmission */
03723   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
03724   {
03725     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03726   }
03727 #endif /* USE_SPI_CRC */
03728
03729   if (hspi->RxXferCount == 0U)
03730   {
03731 #if (USE_SPI_CRC != 0U)
03732     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03733     {
03734       hspi->RxISR =  SPI_RxISR_8BITCRC;
03735       return;
03736     }
03737 #endif /* USE_SPI_CRC */
03738     SPI_CloseRx_ISR(hspi);
03739   }
03740 }
03741
03742 #if (USE_SPI_CRC != 0U)
03743 /**
03744   * @brief  Manage the CRC 16-bit receive in Interrupt context.
03745   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03746   *               the configuration information for SPI module.
03747   * @retval None
03748   */
03749 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
03750 {
03751   __IO uint32_t tmpreg = 0U;
03752
03753   /* Read 16bit CRC to flush Data Register */
03754   tmpreg = READ_REG(hspi->Instance->DR);
03755   /* To avoid GCC warning */
03756   UNUSED(tmpreg);
03757
03758   /* Disable RXNE and ERR interrupt */
03759   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03760
03761   SPI_CloseRx_ISR(hspi);
03762 }
03763 #endif /* USE_SPI_CRC */
03764
03765 /**
03766   * @brief  Manage the 16-bit receive in Interrupt context.
03767   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03768   *               the configuration information for SPI module.
03769   * @retval None
03770   */
03771 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03772 {
03773   *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03774   hspi->pRxBuffPtr += sizeof(uint16_t);
03775   hspi->RxXferCount--;
03776
03777 #if (USE_SPI_CRC != 0U)
03778   /* Enable CRC Transmission */
03779   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
03780   {
03781     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03782   }
03783 #endif /* USE_SPI_CRC */
03784
03785   if (hspi->RxXferCount == 0U)
03786   {
03787 #if (USE_SPI_CRC != 0U)
03788     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03789     {
03790       hspi->RxISR = SPI_RxISR_16BITCRC;
03791       return;
03792     }
03793 #endif /* USE_SPI_CRC */
03794     SPI_CloseRx_ISR(hspi);
03795   }
03796 }
03797
03798 /**
03799   * @brief  Handle the data 8-bit transmit in Interrupt mode.
03800   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03801   *               the configuration information for SPI module.
03802   * @retval None
03803   */
03804 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03805 {
03806   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
03807   hspi->pTxBuffPtr++;
03808   hspi->TxXferCount--;
03809
03810   if (hspi->TxXferCount == 0U)
03811   {
03812 #if (USE_SPI_CRC != 0U)
03813     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03814     {
03815       /* Enable CRC Transmission */
03816       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03817     }
03818 #endif /* USE_SPI_CRC */
03819     SPI_CloseTx_ISR(hspi);
03820   }
03821 }
03822
03823 /**
03824   * @brief  Handle the data 16-bit transmit in Interrupt mode.
03825   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03826   *               the configuration information for SPI module.
03827   * @retval None
03828   */
03829 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03830 {
03831   /* Transmit data in 16 Bit mode */
03832   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03833   hspi->pTxBuffPtr += sizeof(uint16_t);
03834   hspi->TxXferCount--;
03835
03836   if (hspi->TxXferCount == 0U)
03837   {
03838 #if (USE_SPI_CRC != 0U)
03839     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03840     {
03841       /* Enable CRC Transmission */
03842       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03843     }
03844 #endif /* USE_SPI_CRC */
03845     SPI_CloseTx_ISR(hspi);
03846   }
03847 }
03848
03849 /**
03850   * @brief  Handle SPI Communication Timeout.
03851   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03852   *              the configuration information for SPI module.
03853   * @param  Flag SPI flag to check
03854   * @param  State flag state to check
03855   * @param  Timeout Timeout duration
03856   * @param  Tickstart tick start value
03857   * @retval HAL status
03858   */
03859 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
03860                                                        uint32_t Timeout, uint32_t Tickstart)
03861 {
03862   __IO uint32_t count;
03863   uint32_t tmp_timeout;
03864   uint32_t tmp_tickstart;
03865
03866   /* Adjust Timeout value  in case of end of transfer */
03867   tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
03868   tmp_tickstart = HAL_GetTick();
03869
03870   /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
03871   count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
03872
03873   while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
03874   {
03875     if (Timeout != HAL_MAX_DELAY)
03876     {
03877       if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
03878       {
03879         /* Disable the SPI and reset the CRC: the CRC value should be cleared
03880            on both master and slave sides in order to resynchronize the master
03881            and slave for their respective CRC calculation */
03882
03883         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03884         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03885
03886         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03887                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03888         {
03889           /* Disable SPI peripheral */
03890           __HAL_SPI_DISABLE(hspi);
03891         }
03892
03893         /* Reset CRC Calculation */
03894         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03895         {
03896           SPI_RESET_CRC(hspi);
03897         }
03898
03899         hspi->State = HAL_SPI_STATE_READY;
03900
03901         /* Process Unlocked */
03902         __HAL_UNLOCK(hspi);
03903
03904         return HAL_TIMEOUT;
03905       }
03906       /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
03907       if (count == 0U)
03908       {
03909         tmp_timeout = 0U;
03910       }
03911       count--;
03912     }
03913   }
03914
03915   return HAL_OK;
03916 }
03917
03918 /**
03919   * @brief  Handle SPI FIFO Communication Timeout.
03920   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03921   *              the configuration information for SPI module.
03922   * @param  Fifo Fifo to check
03923   * @param  State Fifo state to check
03924   * @param  Timeout Timeout duration
03925   * @param  Tickstart tick start value
03926   * @retval HAL status
03927   */
03928 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
03929                                                        uint32_t Timeout, uint32_t Tickstart)
03930 {
03931   __IO uint32_t count;
03932   uint32_t tmp_timeout;
03933   uint32_t tmp_tickstart;
03934   __IO uint8_t  *ptmpreg8;
03935   __IO uint8_t  tmpreg8 = 0;
03936
03937   /* Adjust Timeout value  in case of end of transfer */
03938   tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
03939   tmp_tickstart = HAL_GetTick();
03940
03941   /* Initialize the 8bit temporary pointer */
03942   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
03943
03944   /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
03945   count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
03946
03947   while ((hspi->Instance->SR & Fifo) != State)
03948   {
03949     if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
03950     {
03951       /* Flush Data Register by a blank read */
03952       tmpreg8 = *ptmpreg8;
03953       /* To avoid GCC warning */
03954       UNUSED(tmpreg8);
03955     }
03956
03957     if (Timeout != HAL_MAX_DELAY)
03958     {
03959       if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
03960       {
03961         /* Disable the SPI and reset the CRC: the CRC value should be cleared
03962            on both master and slave sides in order to resynchronize the master
03963            and slave for their respective CRC calculation */
03964
03965         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03966         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03967
03968         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03969                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03970         {
03971           /* Disable SPI peripheral */
03972           __HAL_SPI_DISABLE(hspi);
03973         }
03974
03975         /* Reset CRC Calculation */
03976         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03977         {
03978           SPI_RESET_CRC(hspi);
03979         }
03980
03981         hspi->State = HAL_SPI_STATE_READY;
03982
03983         /* Process Unlocked */
03984         __HAL_UNLOCK(hspi);
03985
03986         return HAL_TIMEOUT;
03987       }
03988       /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
03989       if (count == 0U)
03990       {
03991         tmp_timeout = 0U;
03992       }
03993       count--;
03994     }
03995   }
03996
03997   return HAL_OK;
03998 }
03999
04000 /**
04001   * @brief  Handle the check of the RX transaction complete.
04002   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04003   *               the configuration information for SPI module.
04004   * @param  Timeout Timeout duration
04005   * @param  Tickstart tick start value
04006   * @retval HAL status
04007   */
04008 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
04009 {
04010   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
04011                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
04012   {
04013     /* Disable SPI peripheral */
04014     __HAL_SPI_DISABLE(hspi);
04015   }
04016
04017   /* Control the BSY flag */
04018   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
04019   {
04020     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04021     return HAL_TIMEOUT;
04022   }
04023
04024   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
04025                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
04026   {
04027     /* Empty the FRLVL fifo */
04028     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
04029     {
04030       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04031       return HAL_TIMEOUT;
04032     }
04033   }
04034   return HAL_OK;
04035 }
04036
04037 /**
04038   * @brief  Handle the check of the RXTX or TX transaction complete.
04039   * @param  hspi SPI handle
04040   * @param  Timeout Timeout duration
04041   * @param  Tickstart tick start value
04042   * @retval HAL status
04043   */
04044 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
04045 {
04046   /* Control if the TX fifo is empty */
04047   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
04048   {
04049     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04050     return HAL_TIMEOUT;
04051   }
04052
04053   /* Control the BSY flag */
04054   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
04055   {
04056     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04057     return HAL_TIMEOUT;
04058   }
04059
04060   /* Control if the RX fifo is empty */
04061   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
04062   {
04063     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04064     return HAL_TIMEOUT;
04065   }
04066
04067   return HAL_OK;
04068 }
04069
04070 /**
04071   * @brief  Handle the end of the RXTX transaction.
04072   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04073   *               the configuration information for SPI module.
04074   * @retval None
04075   */
04076 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
04077 {
04078   uint32_t tickstart;
04079
04080   /* Init tickstart for timeout management */
04081   tickstart = HAL_GetTick();
04082
04083   /* Disable ERR interrupt */
04084   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
04085
04086   /* Check the end of the transaction */
04087   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
04088   {
04089     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04090   }
04091
04092 #if (USE_SPI_CRC != 0U)
04093   /* Check if CRC error occurred */
04094   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
04095   {
04096     hspi->State = HAL_SPI_STATE_READY;
04097     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
04098     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
04099     /* Call user error callback */
04100 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04101     hspi->ErrorCallback(hspi);
04102 #else
04103     HAL_SPI_ErrorCallback(hspi);
04104 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04105   }
04106   else
04107   {
04108 #endif /* USE_SPI_CRC */
04109     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
04110     {
04111       if (hspi->State == HAL_SPI_STATE_BUSY_RX)
04112       {
04113         hspi->State = HAL_SPI_STATE_READY;
04114         /* Call user Rx complete callback */
04115 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04116         hspi->RxCpltCallback(hspi);
04117 #else
04118         HAL_SPI_RxCpltCallback(hspi);
04119 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04120       }
04121       else
04122       {
04123         hspi->State = HAL_SPI_STATE_READY;
04124         /* Call user TxRx complete callback */
04125 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04126         hspi->TxRxCpltCallback(hspi);
04127 #else
04128         HAL_SPI_TxRxCpltCallback(hspi);
04129 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04130       }
04131     }
04132     else
04133     {
04134       hspi->State = HAL_SPI_STATE_READY;
04135       /* Call user error callback */
04136 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04137       hspi->ErrorCallback(hspi);
04138 #else
04139       HAL_SPI_ErrorCallback(hspi);
04140 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04141     }
04142 #if (USE_SPI_CRC != 0U)
04143   }
04144 #endif /* USE_SPI_CRC */
04145 }
04146
04147 /**
04148   * @brief  Handle the end of the RX transaction.
04149   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04150   *               the configuration information for SPI module.
04151   * @retval None
04152   */
04153 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
04154 {
04155   /* Disable RXNE and ERR interrupt */
04156   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
04157
04158   /* Check the end of the transaction */
04159   if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04160   {
04161     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04162   }
04163   hspi->State = HAL_SPI_STATE_READY;
04164
04165 #if (USE_SPI_CRC != 0U)
04166   /* Check if CRC error occurred */
04167   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
04168   {
04169     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
04170     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
04171     /* Call user error callback */
04172 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04173     hspi->ErrorCallback(hspi);
04174 #else
04175     HAL_SPI_ErrorCallback(hspi);
04176 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04177   }
04178   else
04179   {
04180 #endif /* USE_SPI_CRC */
04181     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
04182     {
04183       /* Call user Rx complete callback */
04184 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04185       hspi->RxCpltCallback(hspi);
04186 #else
04187       HAL_SPI_RxCpltCallback(hspi);
04188 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04189     }
04190     else
04191     {
04192       /* Call user error callback */
04193 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04194       hspi->ErrorCallback(hspi);
04195 #else
04196       HAL_SPI_ErrorCallback(hspi);
04197 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04198     }
04199 #if (USE_SPI_CRC != 0U)
04200   }
04201 #endif /* USE_SPI_CRC */
04202 }
04203
04204 /**
04205   * @brief  Handle the end of the TX transaction.
04206   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04207   *               the configuration information for SPI module.
04208   * @retval None
04209   */
04210 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
04211 {
04212   uint32_t tickstart;
04213
04214   /* Init tickstart for timeout management*/
04215   tickstart = HAL_GetTick();
04216
04217   /* Disable TXE and ERR interrupt */
04218   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
04219
04220   /* Check the end of the transaction */
04221   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
04222   {
04223     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04224   }
04225
04226   /* Clear overrun flag in 2 Lines communication mode because received is not read */
04227   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
04228   {
04229     __HAL_SPI_CLEAR_OVRFLAG(hspi);
04230   }
04231
04232   hspi->State = HAL_SPI_STATE_READY;
04233   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
04234   {
04235     /* Call user error callback */
04236 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04237     hspi->ErrorCallback(hspi);
04238 #else
04239     HAL_SPI_ErrorCallback(hspi);
04240 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04241   }
04242   else
04243   {
04244     /* Call user Rx complete callback */
04245 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04246     hspi->TxCpltCallback(hspi);
04247 #else
04248     HAL_SPI_TxCpltCallback(hspi);
04249 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04250   }
04251 }
04252
04253 /**
04254   * @brief  Handle abort a Rx transaction.
04255   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04256   *               the configuration information for SPI module.
04257   * @retval None
04258   */
04259 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
04260 {
04261   __IO uint32_t count;
04262
04263   /* Disable SPI Peripheral */
04264   __HAL_SPI_DISABLE(hspi);
04265
04266   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
04267
04268   /* Disable RXNEIE interrupt */
04269   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
04270
04271   /* Check RXNEIE is disabled */
04272   do
04273   {
04274     if (count == 0U)
04275     {
04276       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04277       break;
04278     }
04279     count--;
04280   } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
04281
04282   /* Control the BSY flag */
04283   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04284   {
04285     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04286   }
04287
04288   /* Empty the FRLVL fifo */
04289   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04290   {
04291     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04292   }
04293
04294   hspi->State = HAL_SPI_STATE_ABORT;
04295 }
04296
04297 /**
04298   * @brief  Handle abort a Tx or Rx/Tx transaction.
04299   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04300   *               the configuration information for SPI module.
04301   * @retval None
04302   */
04303 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
04304 {
04305   __IO uint32_t count;
04306
04307   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
04308
04309   /* Disable TXEIE interrupt */
04310   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
04311
04312   /* Check TXEIE is disabled */
04313   do
04314   {
04315     if (count == 0U)
04316     {
04317       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04318       break;
04319     }
04320     count--;
04321   } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
04322
04323   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04324   {
04325     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04326   }
04327
04328   /* Disable SPI Peripheral */
04329   __HAL_SPI_DISABLE(hspi);
04330
04331   /* Empty the FRLVL fifo */
04332   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04333   {
04334     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04335   }
04336
04337   /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
04338   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
04339   {
04340     /* Disable RXNEIE interrupt */
04341     CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
04342
04343     /* Check RXNEIE is disabled */
04344     do
04345     {
04346       if (count == 0U)
04347       {
04348         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04349         break;
04350       }
04351       count--;
04352     } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
04353
04354     /* Control the BSY flag */
04355     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04356     {
04357       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04358     }
04359
04360     /* Empty the FRLVL fifo */
04361     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04362     {
04363       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04364     }
04365   }
04366   hspi->State = HAL_SPI_STATE_ABORT;
04367 }
04368
04369 /**
04370   * @}
04371   */
04372
04373 #endif /* HAL_SPI_MODULE_ENABLED */
04374
04375 /**
04376   * @}
04377   */
04378
04379 /**
04380   * @}
04381   */
04382
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_spi.h Source File

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stm32g0xx_hal_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_SPI_H
00021 #define STM32G0xx_HAL_SPI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SPI
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup SPI_Exported_Types SPI Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  SPI Configuration Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t Mode;                /*!< Specifies the SPI operating mode.
00049                                      This parameter can be a value of @ref SPI_Mode */
00050
00051   uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
00052                                      This parameter can be a value of @ref SPI_Direction */
00053
00054   uint32_t DataSize;            /*!< Specifies the SPI data size.
00055                                      This parameter can be a value of @ref SPI_Data_Size */
00056
00057   uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
00058                                      This parameter can be a value of @ref SPI_Clock_Polarity */
00059
00060   uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
00061                                      This parameter can be a value of @ref SPI_Clock_Phase */
00062
00063   uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
00064                                      hardware (NSS pin) or by software using the SSI bit.
00065                                      This parameter can be a value of @ref SPI_Slave_Select_management */
00066
00067   uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
00068                                      used to configure the transmit and receive SCK clock.
00069                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
00070                                      @note The communication clock is derived from the master
00071                                      clock. The slave clock does not need to be set. */
00072
00073   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00074                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00075
00076   uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
00077                                      This parameter can be a value of @ref SPI_TI_mode */
00078
00079   uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
00080                                      This parameter can be a value of @ref SPI_CRC_Calculation */
00081
00082   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
00083                                      This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
00084
00085   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
00086                                      CRC Length is only used with Data8 and Data16, not other data size
00087                                      This parameter can be a value of @ref SPI_CRC_length */
00088
00089   uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
00090                                      This parameter can be a value of @ref SPI_NSSP_Mode
00091                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
00092                                      it takes effect only if the SPI interface is configured as Motorola SPI
00093                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
00094                                      CPOL setting is ignored).. */
00095 } SPI_InitTypeDef;
00096
00097 /**
00098   * @brief  HAL SPI State structure definition
00099   */
00100 typedef enum
00101 {
00102   HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
00103   HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00104   HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00105   HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
00106   HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
00107   HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
00108   HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
00109   HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
00110 } HAL_SPI_StateTypeDef;
00111
00112 /**
00113   * @brief  SPI handle Structure definition
00114   */
00115 typedef struct __SPI_HandleTypeDef
00116 {
00117   SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
00118
00119   SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
00120
00121   uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
00122
00123   uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
00124
00125   __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
00126
00127   uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
00128
00129   uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
00130
00131   __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
00132
00133   uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
00134
00135   void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
00136
00137   void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
00138
00139   DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
00140
00141   DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
00142
00143   HAL_LockTypeDef            Lock;           /*!< Locking object                           */
00144
00145   __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
00146
00147   __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
00148
00149 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00150   void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */
00151   void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */
00152   void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */
00153   void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */
00154   void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */
00155   void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */
00156   void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */
00157   void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */
00158   void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */
00159   void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */
00160
00161 #endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
00162 } SPI_HandleTypeDef;
00163
00164 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00165 /**
00166   * @brief  HAL SPI Callback ID enumeration definition
00167   */
00168 typedef enum
00169 {
00170   HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */
00171   HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */
00172   HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */
00173   HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */
00174   HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */
00175   HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */
00176   HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */
00177   HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */
00178   HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */
00179   HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */
00180
00181 } HAL_SPI_CallbackIDTypeDef;
00182
00183 /**
00184   * @brief  HAL SPI Callback pointer definition
00185   */
00186 typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
00187
00188 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00189 /**
00190   * @}
00191   */
00192
00193 /* Exported constants --------------------------------------------------------*/
00194 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00195   * @{
00196   */
00197
00198 /** @defgroup SPI_Error_Code SPI Error Code
00199   * @{
00200   */
00201 #define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
00202 #define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
00203 #define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
00204 #define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
00205 #define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
00206 #define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
00207 #define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
00208 #define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
00209 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00210 #define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */
00211 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup SPI_Mode SPI Mode
00217   * @{
00218   */
00219 #define SPI_MODE_SLAVE                  (0x00000000U)
00220 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup SPI_Direction SPI Direction Mode
00226   * @{
00227   */
00228 #define SPI_DIRECTION_2LINES            (0x00000000U)
00229 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
00230 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup SPI_Data_Size SPI Data Size
00236   * @{
00237   */
00238 #define SPI_DATASIZE_4BIT               (0x00000300U)
00239 #define SPI_DATASIZE_5BIT               (0x00000400U)
00240 #define SPI_DATASIZE_6BIT               (0x00000500U)
00241 #define SPI_DATASIZE_7BIT               (0x00000600U)
00242 #define SPI_DATASIZE_8BIT               (0x00000700U)
00243 #define SPI_DATASIZE_9BIT               (0x00000800U)
00244 #define SPI_DATASIZE_10BIT              (0x00000900U)
00245 #define SPI_DATASIZE_11BIT              (0x00000A00U)
00246 #define SPI_DATASIZE_12BIT              (0x00000B00U)
00247 #define SPI_DATASIZE_13BIT              (0x00000C00U)
00248 #define SPI_DATASIZE_14BIT              (0x00000D00U)
00249 #define SPI_DATASIZE_15BIT              (0x00000E00U)
00250 #define SPI_DATASIZE_16BIT              (0x00000F00U)
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00256   * @{
00257   */
00258 #define SPI_POLARITY_LOW                (0x00000000U)
00259 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00265   * @{
00266   */
00267 #define SPI_PHASE_1EDGE                 (0x00000000U)
00268 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
00274   * @{
00275   */
00276 #define SPI_NSS_SOFT                    SPI_CR1_SSM
00277 #define SPI_NSS_HARD_INPUT              (0x00000000U)
00278 #define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
00284   * @{
00285   */
00286 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
00287 #define SPI_NSS_PULSE_DISABLE           (0x00000000U)
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00293   * @{
00294   */
00295 #define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
00296 #define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
00297 #define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
00298 #define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
00299 #define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
00300 #define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
00301 #define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
00302 #define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
00308   * @{
00309   */
00310 #define SPI_FIRSTBIT_MSB                (0x00000000U)
00311 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup SPI_TI_mode SPI TI Mode
00317   * @{
00318   */
00319 #define SPI_TIMODE_DISABLE              (0x00000000U)
00320 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00326   * @{
00327   */
00328 #define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
00329 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup SPI_CRC_length SPI CRC Length
00335   * @{
00336   * This parameter can be one of the following values:
00337   *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
00338   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
00339   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
00340   */
00341 #define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
00342 #define SPI_CRC_LENGTH_8BIT             (0x00000001U)
00343 #define SPI_CRC_LENGTH_16BIT            (0x00000002U)
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
00349   * @{
00350   * This parameter can be one of the following values:
00351   *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
00352   *          RXNE event is generated if the FIFO
00353   *          level is greater or equal to 1/4(8-bits).
00354   *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
00355   *          level is greater or equal to 1/2(16 bits). */
00356 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
00357 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
00358 #define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
00364   * @{
00365   */
00366 #define SPI_IT_TXE                      SPI_CR2_TXEIE
00367 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
00368 #define SPI_IT_ERR                      SPI_CR2_ERRIE
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup SPI_Flags_definition SPI Flags Definition
00374   * @{
00375   */
00376 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
00377 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
00378 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
00379 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
00380 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
00381 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
00382 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
00383 #define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
00384 #define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
00385 #define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
00386                                          | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
00392   * @{
00393   */
00394 #define SPI_FTLVL_EMPTY                 (0x00000000U)
00395 #define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
00396 #define SPI_FTLVL_HALF_FULL             (0x00001000U)
00397 #define SPI_FTLVL_FULL                  (0x00001800U)
00398
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
00404   * @{
00405   */
00406 #define SPI_FRLVL_EMPTY                 (0x00000000U)
00407 #define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
00408 #define SPI_FRLVL_HALF_FULL             (0x00000400U)
00409 #define SPI_FRLVL_FULL                  (0x00000600U)
00410 /**
00411   * @}
00412   */
00413
00414 /**
00415   * @}
00416   */
00417
00418 /* Exported macros -----------------------------------------------------------*/
00419 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00420   * @{
00421   */
00422
00423 /** @brief  Reset SPI handle state.
00424   * @param  __HANDLE__ specifies the SPI Handle.
00425   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00426   * @retval None
00427   */
00428 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00429 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
00430                                                                     (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
00431                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00432                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00433                                                                   } while(0)
00434 #else
00435 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00436 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00437
00438 /** @brief  Enable the specified SPI interrupts.
00439   * @param  __HANDLE__ specifies the SPI Handle.
00440   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00441   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00442   *         This parameter can be one of the following values:
00443   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00444   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00445   *            @arg SPI_IT_ERR: Error interrupt enable
00446   * @retval None
00447   */
00448 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
00449
00450 /** @brief  Disable the specified SPI interrupts.
00451   * @param  __HANDLE__ specifies the SPI handle.
00452   *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
00453   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00454   *         This parameter can be one of the following values:
00455   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00456   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00457   *            @arg SPI_IT_ERR: Error interrupt enable
00458   * @retval None
00459   */
00460 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
00461
00462 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00463   * @param  __HANDLE__ specifies the SPI Handle.
00464   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00465   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00466   *          This parameter can be one of the following values:
00467   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00468   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00469   *            @arg SPI_IT_ERR: Error interrupt enable
00470   * @retval The new state of __IT__ (TRUE or FALSE).
00471   */
00472 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
00473                                                               & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00474
00475 /** @brief  Check whether the specified SPI flag is set or not.
00476   * @param  __HANDLE__ specifies the SPI Handle.
00477   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00478   * @param  __FLAG__ specifies the flag to check.
00479   *         This parameter can be one of the following values:
00480   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00481   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00482   *            @arg SPI_FLAG_CRCERR: CRC error flag
00483   *            @arg SPI_FLAG_MODF: Mode fault flag
00484   *            @arg SPI_FLAG_OVR: Overrun flag
00485   *            @arg SPI_FLAG_BSY: Busy flag
00486   *            @arg SPI_FLAG_FRE: Frame format error flag
00487   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00488   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00489   * @retval The new state of __FLAG__ (TRUE or FALSE).
00490   */
00491 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00492
00493 /** @brief  Clear the SPI CRCERR pending flag.
00494   * @param  __HANDLE__ specifies the SPI Handle.
00495   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00496   * @retval None
00497   */
00498 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
00499
00500 /** @brief  Clear the SPI MODF pending flag.
00501   * @param  __HANDLE__ specifies the SPI Handle.
00502   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00503   * @retval None
00504   */
00505 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
00506   do{                                                    \
00507     __IO uint32_t tmpreg_modf = 0x00U;                   \
00508     tmpreg_modf = (__HANDLE__)->Instance->SR;            \
00509     CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
00510     UNUSED(tmpreg_modf);                                 \
00511   } while(0U)
00512
00513 /** @brief  Clear the SPI OVR pending flag.
00514   * @param  __HANDLE__ specifies the SPI Handle.
00515   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00516   * @retval None
00517   */
00518 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
00519   do{                                              \
00520     __IO uint32_t tmpreg_ovr = 0x00U;              \
00521     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
00522     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
00523     UNUSED(tmpreg_ovr);                            \
00524   } while(0U)
00525
00526 /** @brief  Clear the SPI FRE pending flag.
00527   * @param  __HANDLE__ specifies the SPI Handle.
00528   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00529   * @retval None
00530   */
00531 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
00532   do{                                              \
00533     __IO uint32_t tmpreg_fre = 0x00U;              \
00534     tmpreg_fre = (__HANDLE__)->Instance->SR;       \
00535     UNUSED(tmpreg_fre);                            \
00536   }while(0U)
00537
00538 /** @brief  Enable the SPI peripheral.
00539   * @param  __HANDLE__ specifies the SPI Handle.
00540   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00541   * @retval None
00542   */
00543 #define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00544
00545 /** @brief  Disable the SPI peripheral.
00546   * @param  __HANDLE__ specifies the SPI Handle.
00547   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00548   * @retval None
00549   */
00550 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00551
00552 /**
00553   * @}
00554   */
00555
00556 /* Private macros ------------------------------------------------------------*/
00557 /** @defgroup SPI_Private_Macros SPI Private Macros
00558   * @{
00559   */
00560
00561 /** @brief  Set the SPI transmit-only mode.
00562   * @param  __HANDLE__ specifies the SPI Handle.
00563   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00564   * @retval None
00565   */
00566 #define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
00567
00568 /** @brief  Set the SPI receive-only mode.
00569   * @param  __HANDLE__ specifies the SPI Handle.
00570   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00571   * @retval None
00572   */
00573 #define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
00574
00575 /** @brief  Reset the CRC calculation of the SPI.
00576   * @param  __HANDLE__ specifies the SPI Handle.
00577   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00578   * @retval None
00579   */
00580 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
00581                                        SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
00582
00583 /** @brief  Check whether the specified SPI flag is set or not.
00584   * @param  __SR__  copy of SPI SR register.
00585   * @param  __FLAG__ specifies the flag to check.
00586   *         This parameter can be one of the following values:
00587   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00588   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00589   *            @arg SPI_FLAG_CRCERR: CRC error flag
00590   *            @arg SPI_FLAG_MODF: Mode fault flag
00591   *            @arg SPI_FLAG_OVR: Overrun flag
00592   *            @arg SPI_FLAG_BSY: Busy flag
00593   *            @arg SPI_FLAG_FRE: Frame format error flag
00594   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00595   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00596   * @retval SET or RESET.
00597   */
00598 #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
00599                                           ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
00600
00601 /** @brief  Check whether the specified SPI Interrupt is set or not.
00602   * @param  __CR2__  copy of SPI CR2 register.
00603   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00604   *         This parameter can be one of the following values:
00605   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00606   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00607   *            @arg SPI_IT_ERR: Error interrupt enable
00608   * @retval SET or RESET.
00609   */
00610 #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
00611                                                      (__INTERRUPT__)) ? SET : RESET)
00612
00613 /** @brief  Checks if SPI Mode parameter is in allowed range.
00614   * @param  __MODE__ specifies the SPI Mode.
00615   *         This parameter can be a value of @ref SPI_Mode
00616   * @retval None
00617   */
00618 #define IS_SPI_MODE(__MODE__)      (((__MODE__) == SPI_MODE_SLAVE)   || \
00619                                     ((__MODE__) == SPI_MODE_MASTER))
00620
00621 /** @brief  Checks if SPI Direction Mode parameter is in allowed range.
00622   * @param  __MODE__ specifies the SPI Direction Mode.
00623   *         This parameter can be a value of @ref SPI_Direction
00624   * @retval None
00625   */
00626 #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
00627                                     ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
00628                                     ((__MODE__) == SPI_DIRECTION_1LINE))
00629
00630 /** @brief  Checks if SPI Direction Mode parameter is 2 lines.
00631   * @param  __MODE__ specifies the SPI Direction Mode.
00632   * @retval None
00633   */
00634 #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
00635
00636 /** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
00637   * @param  __MODE__ specifies the SPI Direction Mode.
00638   * @retval None
00639   */
00640 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
00641                                                     ((__MODE__) == SPI_DIRECTION_1LINE))
00642
00643 /** @brief  Checks if SPI Data Size parameter is in allowed range.
00644   * @param  __DATASIZE__ specifies the SPI Data Size.
00645   *         This parameter can be a value of @ref SPI_Data_Size
00646   * @retval None
00647   */
00648 #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
00649                                        ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
00650                                        ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
00651                                        ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
00652                                        ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
00653                                        ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
00654                                        ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
00655                                        ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \
00656                                        ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \
00657                                        ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \
00658                                        ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \
00659                                        ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \
00660                                        ((__DATASIZE__) == SPI_DATASIZE_4BIT))
00661
00662 /** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
00663   * @param  __CPOL__ specifies the SPI serial clock steady state.
00664   *         This parameter can be a value of @ref SPI_Clock_Polarity
00665   * @retval None
00666   */
00667 #define IS_SPI_CPOL(__CPOL__)      (((__CPOL__) == SPI_POLARITY_LOW) || \
00668                                     ((__CPOL__) == SPI_POLARITY_HIGH))
00669
00670 /** @brief  Checks if SPI Clock Phase parameter is in allowed range.
00671   * @param  __CPHA__ specifies the SPI Clock Phase.
00672   *         This parameter can be a value of @ref SPI_Clock_Phase
00673   * @retval None
00674   */
00675 #define IS_SPI_CPHA(__CPHA__)      (((__CPHA__) == SPI_PHASE_1EDGE) || \
00676                                     ((__CPHA__) == SPI_PHASE_2EDGE))
00677
00678 /** @brief  Checks if SPI Slave Select parameter is in allowed range.
00679   * @param  __NSS__ specifies the SPI Slave Select management parameter.
00680   *         This parameter can be a value of @ref SPI_Slave_Select_management
00681   * @retval None
00682   */
00683 #define IS_SPI_NSS(__NSS__)        (((__NSS__) == SPI_NSS_SOFT)       || \
00684                                     ((__NSS__) == SPI_NSS_HARD_INPUT) || \
00685                                     ((__NSS__) == SPI_NSS_HARD_OUTPUT))
00686
00687 /** @brief  Checks if SPI NSS Pulse parameter is in allowed range.
00688   * @param  __NSSP__ specifies the SPI NSS Pulse Mode parameter.
00689   *         This parameter can be a value of @ref SPI_NSSP_Mode
00690   * @retval None
00691   */
00692 #define IS_SPI_NSSP(__NSSP__)      (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
00693                                     ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
00694
00695 /** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
00696   * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.
00697   *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
00698   * @retval None
00699   */
00700 #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
00701                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
00702                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
00703                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
00704                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
00705                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
00706                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
00707                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
00708
00709 /** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
00710   * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
00711   *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
00712   * @retval None
00713   */
00714 #define IS_SPI_FIRST_BIT(__BIT__)  (((__BIT__) == SPI_FIRSTBIT_MSB) || \
00715                                     ((__BIT__) == SPI_FIRSTBIT_LSB))
00716
00717 /** @brief  Checks if SPI TI mode parameter is in allowed range.
00718   * @param  __MODE__ specifies the SPI TI mode.
00719   *         This parameter can be a value of @ref SPI_TI_mode
00720   * @retval None
00721   */
00722 #define IS_SPI_TIMODE(__MODE__)    (((__MODE__) == SPI_TIMODE_DISABLE) || \
00723                                     ((__MODE__) == SPI_TIMODE_ENABLE))
00724
00725 /** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
00726   * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.
00727   *         This parameter can be a value of @ref SPI_CRC_Calculation
00728   * @retval None
00729   */
00730 #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
00731                                                  ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
00732
00733 /** @brief  Checks if SPI CRC length is in allowed range.
00734   * @param  __LENGTH__ specifies the SPI CRC length.
00735   *         This parameter can be a value of @ref SPI_CRC_length
00736   * @retval None
00737   */
00738 #define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
00739                                        ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)     || \
00740                                        ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
00741
00742 /** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
00743   * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
00744   *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535
00745   * @retval None
00746   */
00747 #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U)    && \
00748                                                ((__POLYNOMIAL__) <= 0xFFFFU) && \
00749                                               (((__POLYNOMIAL__)&0x1U) != 0U))
00750
00751 /** @brief  Checks if DMA handle is valid.
00752   * @param  __HANDLE__ specifies a DMA Handle.
00753   * @retval None
00754   */
00755 #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
00756
00757 /**
00758   * @}
00759   */
00760
00761 /* Include SPI HAL Extended module */
00762 #include "stm32g0xx_hal_spi_ex.h"
00763
00764 /* Exported functions --------------------------------------------------------*/
00765 /** @addtogroup SPI_Exported_Functions
00766   * @{
00767   */
00768
00769 /** @addtogroup SPI_Exported_Functions_Group1
00770   * @{
00771   */
00772 /* Initialization/de-initialization functions  ********************************/
00773 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00774 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
00775 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00776 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00777
00778 /* Callbacks Register/UnRegister functions  ***********************************/
00779 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00780 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
00781                                            pSPI_CallbackTypeDef pCallback);
00782 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
00783 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00784 /**
00785   * @}
00786   */
00787
00788 /** @addtogroup SPI_Exported_Functions_Group2
00789   * @{
00790   */
00791 /* I/O operation functions  ***************************************************/
00792 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00793 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00794 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
00795                                           uint32_t Timeout);
00796 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00797 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00798 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00799                                              uint16_t Size);
00800 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00801 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00802 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00803                                               uint16_t Size);
00804 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00805 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00806 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00807 /* Transfer Abort functions */
00808 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
00809 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
00810
00811 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00812 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00813 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00814 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00815 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00816 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00817 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00818 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00819 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
00820 /**
00821   * @}
00822   */
00823
00824 /** @addtogroup SPI_Exported_Functions_Group3
00825   * @{
00826   */
00827 /* Peripheral State and Error functions ***************************************/
00828 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00829 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00830 /**
00831   * @}
00832   */
00833
00834 /**
00835   * @}
00836   */
00837
00838 /**
00839   * @}
00840   */
00841
00842 /**
00843   * @}
00844   */
00845
00846 #ifdef __cplusplus
00847 }
00848 #endif
00849
00850 #endif /* STM32G0xx_HAL_SPI_H */
00851
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_spi_ex.c Source File

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stm32g0xx_hal_spi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_spi_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          SPI peripheral extended functionalities :
00008   *           + IO operation functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2018 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32g0xx_hal.h"
00025
00026 /** @addtogroup STM32G0xx_HAL_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup SPIEx SPIEx
00031   * @brief SPI Extended HAL module driver
00032   * @{
00033   */
00034 #ifdef HAL_SPI_MODULE_ENABLED
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private defines -----------------------------------------------------------*/
00038 /** @defgroup SPIEx_Private_Constants SPIEx Private Constants
00039   * @{
00040   */
00041 #define SPI_FIFO_SIZE       4UL
00042 /**
00043   * @}
00044   */
00045
00046 /* Private macros ------------------------------------------------------------*/
00047 /* Private variables ---------------------------------------------------------*/
00048 /* Private function prototypes -----------------------------------------------*/
00049 /* Exported functions --------------------------------------------------------*/
00050
00051 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
00052   * @{
00053   */
00054
00055 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
00056   *  @brief   Data transfers functions
00057   *
00058 @verbatim
00059   ==============================================================================
00060                       ##### IO operation functions #####
00061  ===============================================================================
00062  [..]
00063     This subsection provides a set of extended functions to manage the SPI
00064     data transfers.
00065
00066     (#) Rx data flush function:
00067         (++) HAL_SPIEx_FlushRxFifo()
00068
00069 @endverbatim
00070   * @{
00071   */
00072
00073 /**
00074   * @brief  Flush the RX fifo.
00075   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00076   *               the configuration information for the specified SPI module.
00077   * @retval HAL status
00078   */
00079 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
00080 {
00081   __IO uint32_t tmpreg;
00082   uint8_t  count = 0U;
00083   while ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
00084   {
00085     count++;
00086     tmpreg = hspi->Instance->DR;
00087     UNUSED(tmpreg); /* To avoid GCC warning */
00088     if (count == SPI_FIFO_SIZE)
00089     {
00090       return HAL_TIMEOUT;
00091     }
00092   }
00093   return HAL_OK;
00094 }
00095
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 #endif /* HAL_SPI_MODULE_ENABLED */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /**
00111   * @}
00112   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_spi_ex.h Source File

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stm32g0xx_hal_spi_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_spi_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_SPI_EX_H
00021 #define STM32G0xx_HAL_SPI_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup SPIEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /* Exported macros -----------------------------------------------------------*/
00041 /* Exported functions --------------------------------------------------------*/
00042 /** @addtogroup SPIEx_Exported_Functions
00043   * @{
00044   */
00045
00046 /* Initialization and de-initialization functions  ****************************/
00047 /* IO operation functions *****************************************************/
00048 /** @addtogroup SPIEx_Exported_Functions_Group1
00049   * @{
00050   */
00051 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
00052 /**
00053   * @}
00054   */
00055
00056 /**
00057   * @}
00058   */
00059
00060 /**
00061   * @}
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068 #ifdef __cplusplus
00069 }
00070 #endif
00071
00072 #endif /* STM32G0xx_HAL_SPI_EX_H */
00073
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_tim.c Source File

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stm32g0xx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer (TIM) peripheral:
00008   *           + TIM Time Base Initialization
00009   *           + TIM Time Base Start
00010   *           + TIM Time Base Start Interruption
00011   *           + TIM Time Base Start DMA
00012   *           + TIM Output Compare/PWM Initialization
00013   *           + TIM Output Compare/PWM Channel Configuration
00014   *           + TIM Output Compare/PWM  Start
00015   *           + TIM Output Compare/PWM  Start Interruption
00016   *           + TIM Output Compare/PWM Start DMA
00017   *           + TIM Input Capture Initialization
00018   *           + TIM Input Capture Channel Configuration
00019   *           + TIM Input Capture Start
00020   *           + TIM Input Capture Start Interruption
00021   *           + TIM Input Capture Start DMA
00022   *           + TIM One Pulse Initialization
00023   *           + TIM One Pulse Channel Configuration
00024   *           + TIM One Pulse Start
00025   *           + TIM Encoder Interface Initialization
00026   *           + TIM Encoder Interface Start
00027   *           + TIM Encoder Interface Start Interruption
00028   *           + TIM Encoder Interface Start DMA
00029   *           + Commutation Event configuration with Interruption and DMA
00030   *           + TIM OCRef clear configuration
00031   *           + TIM External Clock configuration
00032   ******************************************************************************
00033   * @attention
00034   *
00035   * Copyright (c) 2018 STMicroelectronics.
00036   * All rights reserved.
00037   *
00038   * This software is licensed under terms that can be found in the LICENSE file
00039   * in the root directory of this software component.
00040   * If no LICENSE file comes with this software, it is provided AS-IS.
00041   *
00042   ******************************************************************************
00043   @verbatim
00044   ==============================================================================
00045                       ##### TIMER Generic features #####
00046   ==============================================================================
00047   [..] The Timer features include:
00048        (#) 16-bit up, down, up/down auto-reload counter.
00049        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00050            counter clock frequency either by any factor between 1 and 65536.
00051        (#) Up to 4 independent channels for:
00052            (++) Input Capture
00053            (++) Output Compare
00054            (++) PWM generation (Edge and Center-aligned Mode)
00055            (++) One-pulse mode output
00056        (#) Synchronization circuit to control the timer with external signals and to interconnect
00057             several timers together.
00058        (#) Supports incremental encoder for positioning purposes
00059
00060             ##### How to use this driver #####
00061   ==============================================================================
00062     [..]
00063      (#) Initialize the TIM low level resources by implementing the following functions
00064          depending on the selected feature:
00065            (++) Time Base : HAL_TIM_Base_MspInit()
00066            (++) Input Capture : HAL_TIM_IC_MspInit()
00067            (++) Output Compare : HAL_TIM_OC_MspInit()
00068            (++) PWM generation : HAL_TIM_PWM_MspInit()
00069            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00070            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00071
00072      (#) Initialize the TIM low level resources :
00073         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00074         (##) TIM pins configuration
00075             (+++) Enable the clock for the TIM GPIOs using the following function:
00076              __HAL_RCC_GPIOx_CLK_ENABLE();
00077             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00078
00079      (#) The external Clock can be configured, if needed (the default clock is the
00080          internal clock from the APBx), using the following function:
00081          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00082          any start function.
00083
00084      (#) Configure the TIM in the desired functioning mode using one of the
00085        Initialization function of this driver:
00086        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00087        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00088             Output Compare signal.
00089        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00090             PWM signal.
00091        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00092             external signal.
00093        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00094             in One Pulse Mode.
00095        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00096
00097      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00098            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00099            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00100            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00101            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00102            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00103            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00104
00105      (#) The DMA Burst is managed with the two following functions:
00106          HAL_TIM_DMABurst_WriteStart()
00107          HAL_TIM_DMABurst_ReadStart()
00108
00109     *** Callback registration ***
00110   =============================================
00111
00112   [..]
00113   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
00114   allows the user to configure dynamically the driver callbacks.
00115
00116   [..]
00117   Use Function HAL_TIM_RegisterCallback() to register a callback.
00118   HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
00119   the Callback ID and a pointer to the user callback function.
00120
00121   [..]
00122   Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
00123   weak function.
00124   HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
00125   and the Callback ID.
00126
00127   [..]
00128   These functions allow to register/unregister following callbacks:
00129     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
00130     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
00131     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
00132     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
00133     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
00134     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
00135     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
00136     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
00137     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
00138     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
00139     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
00140     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
00141     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
00142     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
00143     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
00144     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
00145     (+) TriggerCallback                   : TIM Trigger Callback.
00146     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
00147     (+) IC_CaptureCallback                : TIM Input Capture Callback.
00148     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
00149     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
00150     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
00151     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
00152     (+) ErrorCallback                     : TIM Error Callback.
00153     (+) CommutationCallback               : TIM Commutation Callback.
00154     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
00155     (+) BreakCallback                     : TIM Break Callback.
00156     (+) Break2Callback                    : TIM Break2 Callback.
00157
00158   [..]
00159 By default, after the Init and when the state is HAL_TIM_STATE_RESET
00160 all interrupt callbacks are set to the corresponding weak functions:
00161   examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
00162
00163   [..]
00164   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
00165   functionalities in the Init / DeInit only when these callbacks are null
00166   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
00167     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
00168
00169   [..]
00170     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
00171     Exception done MspInit / MspDeInit that can be registered / unregistered
00172     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
00173     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
00174   In that case first register the MspInit/MspDeInit user callbacks
00175       using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
00176
00177   [..]
00178       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
00179       not defined, the callback registration feature is not available and all callbacks
00180       are set to the corresponding weak functions.
00181
00182   @endverbatim
00183   ******************************************************************************
00184   */
00185
00186 /* Includes ------------------------------------------------------------------*/
00187 #include "stm32g0xx_hal.h"
00188
00189 /** @addtogroup STM32G0xx_HAL_Driver
00190   * @{
00191   */
00192
00193 /** @defgroup TIM TIM
00194   * @brief TIM HAL module driver
00195   * @{
00196   */
00197
00198 #ifdef HAL_TIM_MODULE_ENABLED
00199
00200 /* Private typedef -----------------------------------------------------------*/
00201 /* Private define ------------------------------------------------------------*/
00202 /** @addtogroup TIM_Private_Constants
00203   * @{
00204   */
00205 #define TIMx_OR1_OCREF_CLR 0x00000001U
00206 /**
00207   * @}
00208   */
00209
00210 /* Private macros ------------------------------------------------------------*/
00211 /* Private variables ---------------------------------------------------------*/
00212 /* Private function prototypes -----------------------------------------------*/
00213 /** @addtogroup TIM_Private_Functions
00214   * @{
00215   */
00216 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00217 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00218 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00219 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00220 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
00221 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00222 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00223                               uint32_t TIM_ICFilter);
00224 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00225 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00226                               uint32_t TIM_ICFilter);
00227 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00228                               uint32_t TIM_ICFilter);
00229 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
00230 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00231 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
00232 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
00233 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00234 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
00235 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00236                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig);
00237 /**
00238   * @}
00239   */
00240 /* Exported functions --------------------------------------------------------*/
00241
00242 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00243   * @{
00244   */
00245
00246 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
00247   *  @brief    Time Base functions
00248   *
00249 @verbatim
00250   ==============================================================================
00251               ##### Time Base functions #####
00252   ==============================================================================
00253   [..]
00254     This section provides functions allowing to:
00255     (+) Initialize and configure the TIM base.
00256     (+) De-initialize the TIM base.
00257     (+) Start the Time Base.
00258     (+) Stop the Time Base.
00259     (+) Start the Time Base and enable interrupt.
00260     (+) Stop the Time Base and disable interrupt.
00261     (+) Start the Time Base and enable DMA transfer.
00262     (+) Stop the Time Base and disable DMA transfer.
00263
00264 @endverbatim
00265   * @{
00266   */
00267 /**
00268   * @brief  Initializes the TIM Time base Unit according to the specified
00269   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00270   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
00271   *         requires a timer reset to avoid unexpected direction
00272   *         due to DIR bit readonly in center aligned mode.
00273   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
00274   * @param  htim TIM Base handle
00275   * @retval HAL status
00276   */
00277 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00278 {
00279   /* Check the TIM handle allocation */
00280   if (htim == NULL)
00281   {
00282     return HAL_ERROR;
00283   }
00284
00285   /* Check the parameters */
00286   assert_param(IS_TIM_INSTANCE(htim->Instance));
00287   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00288   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00289   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
00290   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00291
00292   if (htim->State == HAL_TIM_STATE_RESET)
00293   {
00294     /* Allocate lock resource and initialize it */
00295     htim->Lock = HAL_UNLOCKED;
00296
00297 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00298     /* Reset interrupt callbacks to legacy weak callbacks */
00299     TIM_ResetCallback(htim);
00300
00301     if (htim->Base_MspInitCallback == NULL)
00302     {
00303       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
00304     }
00305     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00306     htim->Base_MspInitCallback(htim);
00307 #else
00308     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00309     HAL_TIM_Base_MspInit(htim);
00310 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00311   }
00312
00313   /* Set the TIM state */
00314   htim->State = HAL_TIM_STATE_BUSY;
00315
00316   /* Set the Time Base configuration */
00317   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00318
00319   /* Initialize the DMA burst operation state */
00320   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
00321
00322   /* Initialize the TIM channels state */
00323   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
00324   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
00325
00326   /* Initialize the TIM state*/
00327   htim->State = HAL_TIM_STATE_READY;
00328
00329   return HAL_OK;
00330 }
00331
00332 /**
00333   * @brief  DeInitializes the TIM Base peripheral
00334   * @param  htim TIM Base handle
00335   * @retval HAL status
00336   */
00337 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00338 {
00339   /* Check the parameters */
00340   assert_param(IS_TIM_INSTANCE(htim->Instance));
00341
00342   htim->State = HAL_TIM_STATE_BUSY;
00343
00344   /* Disable the TIM Peripheral Clock */
00345   __HAL_TIM_DISABLE(htim);
00346
00347 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00348   if (htim->Base_MspDeInitCallback == NULL)
00349   {
00350     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
00351   }
00352   /* DeInit the low level hardware */
00353   htim->Base_MspDeInitCallback(htim);
00354 #else
00355   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00356   HAL_TIM_Base_MspDeInit(htim);
00357 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00358
00359   /* Change the DMA burst operation state */
00360   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
00361
00362   /* Change the TIM channels state */
00363   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
00364   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
00365
00366   /* Change TIM state */
00367   htim->State = HAL_TIM_STATE_RESET;
00368
00369   /* Release Lock */
00370   __HAL_UNLOCK(htim);
00371
00372   return HAL_OK;
00373 }
00374
00375 /**
00376   * @brief  Initializes the TIM Base MSP.
00377   * @param  htim TIM Base handle
00378   * @retval None
00379   */
00380 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00381 {
00382   /* Prevent unused argument(s) compilation warning */
00383   UNUSED(htim);
00384
00385   /* NOTE : This function should not be modified, when the callback is needed,
00386             the HAL_TIM_Base_MspInit could be implemented in the user file
00387    */
00388 }
00389
00390 /**
00391   * @brief  DeInitializes TIM Base MSP.
00392   * @param  htim TIM Base handle
00393   * @retval None
00394   */
00395 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00396 {
00397   /* Prevent unused argument(s) compilation warning */
00398   UNUSED(htim);
00399
00400   /* NOTE : This function should not be modified, when the callback is needed,
00401             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00402    */
00403 }
00404
00405
00406 /**
00407   * @brief  Starts the TIM Base generation.
00408   * @param  htim TIM Base handle
00409   * @retval HAL status
00410   */
00411 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00412 {
00413   uint32_t tmpsmcr;
00414
00415   /* Check the parameters */
00416   assert_param(IS_TIM_INSTANCE(htim->Instance));
00417
00418   /* Check the TIM state */
00419   if (htim->State != HAL_TIM_STATE_READY)
00420   {
00421     return HAL_ERROR;
00422   }
00423
00424   /* Set the TIM state */
00425   htim->State = HAL_TIM_STATE_BUSY;
00426
00427   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00428   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00429   {
00430     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00431     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00432     {
00433       __HAL_TIM_ENABLE(htim);
00434     }
00435   }
00436   else
00437   {
00438     __HAL_TIM_ENABLE(htim);
00439   }
00440
00441   /* Return function status */
00442   return HAL_OK;
00443 }
00444
00445 /**
00446   * @brief  Stops the TIM Base generation.
00447   * @param  htim TIM Base handle
00448   * @retval HAL status
00449   */
00450 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00451 {
00452   /* Check the parameters */
00453   assert_param(IS_TIM_INSTANCE(htim->Instance));
00454
00455   /* Disable the Peripheral */
00456   __HAL_TIM_DISABLE(htim);
00457
00458   /* Set the TIM state */
00459   htim->State = HAL_TIM_STATE_READY;
00460
00461   /* Return function status */
00462   return HAL_OK;
00463 }
00464
00465 /**
00466   * @brief  Starts the TIM Base generation in interrupt mode.
00467   * @param  htim TIM Base handle
00468   * @retval HAL status
00469   */
00470 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00471 {
00472   uint32_t tmpsmcr;
00473
00474   /* Check the parameters */
00475   assert_param(IS_TIM_INSTANCE(htim->Instance));
00476
00477   /* Check the TIM state */
00478   if (htim->State != HAL_TIM_STATE_READY)
00479   {
00480     return HAL_ERROR;
00481   }
00482
00483   /* Set the TIM state */
00484   htim->State = HAL_TIM_STATE_BUSY;
00485
00486   /* Enable the TIM Update interrupt */
00487   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00488
00489   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00490   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00491   {
00492     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00493     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00494     {
00495       __HAL_TIM_ENABLE(htim);
00496     }
00497   }
00498   else
00499   {
00500     __HAL_TIM_ENABLE(htim);
00501   }
00502
00503   /* Return function status */
00504   return HAL_OK;
00505 }
00506
00507 /**
00508   * @brief  Stops the TIM Base generation in interrupt mode.
00509   * @param  htim TIM Base handle
00510   * @retval HAL status
00511   */
00512 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00513 {
00514   /* Check the parameters */
00515   assert_param(IS_TIM_INSTANCE(htim->Instance));
00516
00517   /* Disable the TIM Update interrupt */
00518   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00519
00520   /* Disable the Peripheral */
00521   __HAL_TIM_DISABLE(htim);
00522
00523   /* Set the TIM state */
00524   htim->State = HAL_TIM_STATE_READY;
00525
00526   /* Return function status */
00527   return HAL_OK;
00528 }
00529
00530 /**
00531   * @brief  Starts the TIM Base generation in DMA mode.
00532   * @param  htim TIM Base handle
00533   * @param  pData The source Buffer address.
00534   * @param  Length The length of data to be transferred from memory to peripheral.
00535   * @retval HAL status
00536   */
00537 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
00538 {
00539   uint32_t tmpsmcr;
00540
00541   /* Check the parameters */
00542   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00543
00544   /* Set the TIM state */
00545   if (htim->State == HAL_TIM_STATE_BUSY)
00546   {
00547     return HAL_BUSY;
00548   }
00549   else if (htim->State == HAL_TIM_STATE_READY)
00550   {
00551     if ((pData == NULL) || (Length == 0U))
00552     {
00553       return HAL_ERROR;
00554     }
00555     else
00556     {
00557       htim->State = HAL_TIM_STATE_BUSY;
00558     }
00559   }
00560   else
00561   {
00562     return HAL_ERROR;
00563   }
00564
00565   /* Set the DMA Period elapsed callbacks */
00566   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00567   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
00568
00569   /* Set the DMA error callback */
00570   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00571
00572   /* Enable the DMA channel */
00573   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
00574                        Length) != HAL_OK)
00575   {
00576     /* Return error status */
00577     return HAL_ERROR;
00578   }
00579
00580   /* Enable the TIM Update DMA request */
00581   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00582
00583   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00584   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00585   {
00586     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00587     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00588     {
00589       __HAL_TIM_ENABLE(htim);
00590     }
00591   }
00592   else
00593   {
00594     __HAL_TIM_ENABLE(htim);
00595   }
00596
00597   /* Return function status */
00598   return HAL_OK;
00599 }
00600
00601 /**
00602   * @brief  Stops the TIM Base generation in DMA mode.
00603   * @param  htim TIM Base handle
00604   * @retval HAL status
00605   */
00606 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00607 {
00608   /* Check the parameters */
00609   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00610
00611   /* Disable the TIM Update DMA request */
00612   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00613
00614   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
00615
00616   /* Disable the Peripheral */
00617   __HAL_TIM_DISABLE(htim);
00618
00619   /* Set the TIM state */
00620   htim->State = HAL_TIM_STATE_READY;
00621
00622   /* Return function status */
00623   return HAL_OK;
00624 }
00625
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
00631   *  @brief    TIM Output Compare functions
00632   *
00633 @verbatim
00634   ==============================================================================
00635                   ##### TIM Output Compare functions #####
00636   ==============================================================================
00637   [..]
00638     This section provides functions allowing to:
00639     (+) Initialize and configure the TIM Output Compare.
00640     (+) De-initialize the TIM Output Compare.
00641     (+) Start the TIM Output Compare.
00642     (+) Stop the TIM Output Compare.
00643     (+) Start the TIM Output Compare and enable interrupt.
00644     (+) Stop the TIM Output Compare and disable interrupt.
00645     (+) Start the TIM Output Compare and enable DMA transfer.
00646     (+) Stop the TIM Output Compare and disable DMA transfer.
00647
00648 @endverbatim
00649   * @{
00650   */
00651 /**
00652   * @brief  Initializes the TIM Output Compare according to the specified
00653   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
00654   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
00655   *         requires a timer reset to avoid unexpected direction
00656   *         due to DIR bit readonly in center aligned mode.
00657   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
00658   * @param  htim TIM Output Compare handle
00659   * @retval HAL status
00660   */
00661 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
00662 {
00663   /* Check the TIM handle allocation */
00664   if (htim == NULL)
00665   {
00666     return HAL_ERROR;
00667   }
00668
00669   /* Check the parameters */
00670   assert_param(IS_TIM_INSTANCE(htim->Instance));
00671   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00672   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00673   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
00674   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00675
00676   if (htim->State == HAL_TIM_STATE_RESET)
00677   {
00678     /* Allocate lock resource and initialize it */
00679     htim->Lock = HAL_UNLOCKED;
00680
00681 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00682     /* Reset interrupt callbacks to legacy weak callbacks */
00683     TIM_ResetCallback(htim);
00684
00685     if (htim->OC_MspInitCallback == NULL)
00686     {
00687       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
00688     }
00689     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00690     htim->OC_MspInitCallback(htim);
00691 #else
00692     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00693     HAL_TIM_OC_MspInit(htim);
00694 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00695   }
00696
00697   /* Set the TIM state */
00698   htim->State = HAL_TIM_STATE_BUSY;
00699
00700   /* Init the base time for the Output Compare */
00701   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00702
00703   /* Initialize the DMA burst operation state */
00704   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
00705
00706   /* Initialize the TIM channels state */
00707   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
00708   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
00709
00710   /* Initialize the TIM state*/
00711   htim->State = HAL_TIM_STATE_READY;
00712
00713   return HAL_OK;
00714 }
00715
00716 /**
00717   * @brief  DeInitializes the TIM peripheral
00718   * @param  htim TIM Output Compare handle
00719   * @retval HAL status
00720   */
00721 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00722 {
00723   /* Check the parameters */
00724   assert_param(IS_TIM_INSTANCE(htim->Instance));
00725
00726   htim->State = HAL_TIM_STATE_BUSY;
00727
00728   /* Disable the TIM Peripheral Clock */
00729   __HAL_TIM_DISABLE(htim);
00730
00731 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00732   if (htim->OC_MspDeInitCallback == NULL)
00733   {
00734     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
00735   }
00736   /* DeInit the low level hardware */
00737   htim->OC_MspDeInitCallback(htim);
00738 #else
00739   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00740   HAL_TIM_OC_MspDeInit(htim);
00741 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00742
00743   /* Change the DMA burst operation state */
00744   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
00745
00746   /* Change the TIM channels state */
00747   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
00748   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
00749
00750   /* Change TIM state */
00751   htim->State = HAL_TIM_STATE_RESET;
00752
00753   /* Release Lock */
00754   __HAL_UNLOCK(htim);
00755
00756   return HAL_OK;
00757 }
00758
00759 /**
00760   * @brief  Initializes the TIM Output Compare MSP.
00761   * @param  htim TIM Output Compare handle
00762   * @retval None
00763   */
00764 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00765 {
00766   /* Prevent unused argument(s) compilation warning */
00767   UNUSED(htim);
00768
00769   /* NOTE : This function should not be modified, when the callback is needed,
00770             the HAL_TIM_OC_MspInit could be implemented in the user file
00771    */
00772 }
00773
00774 /**
00775   * @brief  DeInitializes TIM Output Compare MSP.
00776   * @param  htim TIM Output Compare handle
00777   * @retval None
00778   */
00779 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00780 {
00781   /* Prevent unused argument(s) compilation warning */
00782   UNUSED(htim);
00783
00784   /* NOTE : This function should not be modified, when the callback is needed,
00785             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00786    */
00787 }
00788
00789 /**
00790   * @brief  Starts the TIM Output Compare signal generation.
00791   * @param  htim TIM Output Compare handle
00792   * @param  Channel TIM Channel to be enabled
00793   *          This parameter can be one of the following values:
00794   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00795   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00796   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00797   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00798   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00799   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00800   * @retval HAL status
00801   */
00802 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00803 {
00804   uint32_t tmpsmcr;
00805
00806   /* Check the parameters */
00807   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00808
00809   /* Check the TIM channel state */
00810   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
00811   {
00812     return HAL_ERROR;
00813   }
00814
00815   /* Set the TIM channel state */
00816   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00817
00818   /* Enable the Output compare channel */
00819   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00820
00821   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00822   {
00823     /* Enable the main output */
00824     __HAL_TIM_MOE_ENABLE(htim);
00825   }
00826
00827   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00828   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00829   {
00830     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00831     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00832     {
00833       __HAL_TIM_ENABLE(htim);
00834     }
00835   }
00836   else
00837   {
00838     __HAL_TIM_ENABLE(htim);
00839   }
00840
00841   /* Return function status */
00842   return HAL_OK;
00843 }
00844
00845 /**
00846   * @brief  Stops the TIM Output Compare signal generation.
00847   * @param  htim TIM Output Compare handle
00848   * @param  Channel TIM Channel to be disabled
00849   *          This parameter can be one of the following values:
00850   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00851   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00852   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00853   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00854   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00855   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00856   * @retval HAL status
00857   */
00858 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00859 {
00860   /* Check the parameters */
00861   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00862
00863   /* Disable the Output compare channel */
00864   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00865
00866   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00867   {
00868     /* Disable the Main Output */
00869     __HAL_TIM_MOE_DISABLE(htim);
00870   }
00871
00872   /* Disable the Peripheral */
00873   __HAL_TIM_DISABLE(htim);
00874
00875   /* Set the TIM channel state */
00876   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
00877
00878   /* Return function status */
00879   return HAL_OK;
00880 }
00881
00882 /**
00883   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00884   * @param  htim TIM Output Compare handle
00885   * @param  Channel TIM Channel to be enabled
00886   *          This parameter can be one of the following values:
00887   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00888   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00889   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00890   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00891   * @retval HAL status
00892   */
00893 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00894 {
00895   HAL_StatusTypeDef status = HAL_OK;
00896   uint32_t tmpsmcr;
00897
00898   /* Check the parameters */
00899   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00900
00901   /* Check the TIM channel state */
00902   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
00903   {
00904     return HAL_ERROR;
00905   }
00906
00907   /* Set the TIM channel state */
00908   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00909
00910   switch (Channel)
00911   {
00912     case TIM_CHANNEL_1:
00913     {
00914       /* Enable the TIM Capture/Compare 1 interrupt */
00915       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00916       break;
00917     }
00918
00919     case TIM_CHANNEL_2:
00920     {
00921       /* Enable the TIM Capture/Compare 2 interrupt */
00922       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00923       break;
00924     }
00925
00926     case TIM_CHANNEL_3:
00927     {
00928       /* Enable the TIM Capture/Compare 3 interrupt */
00929       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00930       break;
00931     }
00932
00933     case TIM_CHANNEL_4:
00934     {
00935       /* Enable the TIM Capture/Compare 4 interrupt */
00936       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00937       break;
00938     }
00939
00940     default:
00941       status = HAL_ERROR;
00942       break;
00943   }
00944
00945   if (status == HAL_OK)
00946   {
00947     /* Enable the Output compare channel */
00948     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00949
00950     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00951     {
00952       /* Enable the main output */
00953       __HAL_TIM_MOE_ENABLE(htim);
00954     }
00955
00956     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00957     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00958     {
00959       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00960       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00961       {
00962         __HAL_TIM_ENABLE(htim);
00963       }
00964     }
00965     else
00966     {
00967       __HAL_TIM_ENABLE(htim);
00968     }
00969   }
00970
00971   /* Return function status */
00972   return status;
00973 }
00974
00975 /**
00976   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00977   * @param  htim TIM Output Compare handle
00978   * @param  Channel TIM Channel to be disabled
00979   *          This parameter can be one of the following values:
00980   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00981   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00982   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00983   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00984   * @retval HAL status
00985   */
00986 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00987 {
00988   HAL_StatusTypeDef status = HAL_OK;
00989
00990   /* Check the parameters */
00991   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00992
00993   switch (Channel)
00994   {
00995     case TIM_CHANNEL_1:
00996     {
00997       /* Disable the TIM Capture/Compare 1 interrupt */
00998       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00999       break;
01000     }
01001
01002     case TIM_CHANNEL_2:
01003     {
01004       /* Disable the TIM Capture/Compare 2 interrupt */
01005       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01006       break;
01007     }
01008
01009     case TIM_CHANNEL_3:
01010     {
01011       /* Disable the TIM Capture/Compare 3 interrupt */
01012       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01013       break;
01014     }
01015
01016     case TIM_CHANNEL_4:
01017     {
01018       /* Disable the TIM Capture/Compare 4 interrupt */
01019       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01020       break;
01021     }
01022
01023     default:
01024       status = HAL_ERROR;
01025       break;
01026   }
01027
01028   if (status == HAL_OK)
01029   {
01030     /* Disable the Output compare channel */
01031     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01032
01033     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01034     {
01035       /* Disable the Main Output */
01036       __HAL_TIM_MOE_DISABLE(htim);
01037     }
01038
01039     /* Disable the Peripheral */
01040     __HAL_TIM_DISABLE(htim);
01041
01042     /* Set the TIM channel state */
01043     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01044   }
01045
01046   /* Return function status */
01047   return status;
01048 }
01049
01050 /**
01051   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
01052   * @param  htim TIM Output Compare handle
01053   * @param  Channel TIM Channel to be enabled
01054   *          This parameter can be one of the following values:
01055   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01056   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01057   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01058   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01059   * @param  pData The source Buffer address.
01060   * @param  Length The length of data to be transferred from memory to TIM peripheral
01061   * @retval HAL status
01062   */
01063 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
01064                                        uint16_t Length)
01065 {
01066   HAL_StatusTypeDef status = HAL_OK;
01067   uint32_t tmpsmcr;
01068
01069   /* Check the parameters */
01070   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01071
01072   /* Set the TIM channel state */
01073   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
01074   {
01075     return HAL_BUSY;
01076   }
01077   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
01078   {
01079     if ((pData == NULL) || (Length == 0U))
01080     {
01081       return HAL_ERROR;
01082     }
01083     else
01084     {
01085       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01086     }
01087   }
01088   else
01089   {
01090     return HAL_ERROR;
01091   }
01092
01093   switch (Channel)
01094   {
01095     case TIM_CHANNEL_1:
01096     {
01097       /* Set the DMA compare callbacks */
01098       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01099       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01100
01101       /* Set the DMA error callback */
01102       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01103
01104       /* Enable the DMA channel */
01105       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
01106                            Length) != HAL_OK)
01107       {
01108         /* Return error status */
01109         return HAL_ERROR;
01110       }
01111
01112       /* Enable the TIM Capture/Compare 1 DMA request */
01113       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01114       break;
01115     }
01116
01117     case TIM_CHANNEL_2:
01118     {
01119       /* Set the DMA compare callbacks */
01120       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01121       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01122
01123       /* Set the DMA error callback */
01124       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01125
01126       /* Enable the DMA channel */
01127       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
01128                            Length) != HAL_OK)
01129       {
01130         /* Return error status */
01131         return HAL_ERROR;
01132       }
01133
01134       /* Enable the TIM Capture/Compare 2 DMA request */
01135       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01136       break;
01137     }
01138
01139     case TIM_CHANNEL_3:
01140     {
01141       /* Set the DMA compare callbacks */
01142       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01143       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01144
01145       /* Set the DMA error callback */
01146       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01147
01148       /* Enable the DMA channel */
01149       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
01150                            Length) != HAL_OK)
01151       {
01152         /* Return error status */
01153         return HAL_ERROR;
01154       }
01155       /* Enable the TIM Capture/Compare 3 DMA request */
01156       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01157       break;
01158     }
01159
01160     case TIM_CHANNEL_4:
01161     {
01162       /* Set the DMA compare callbacks */
01163       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01164       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01165
01166       /* Set the DMA error callback */
01167       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01168
01169       /* Enable the DMA channel */
01170       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
01171                            Length) != HAL_OK)
01172       {
01173         /* Return error status */
01174         return HAL_ERROR;
01175       }
01176       /* Enable the TIM Capture/Compare 4 DMA request */
01177       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01178       break;
01179     }
01180
01181     default:
01182       status = HAL_ERROR;
01183       break;
01184   }
01185
01186   if (status == HAL_OK)
01187   {
01188     /* Enable the Output compare channel */
01189     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01190
01191     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01192     {
01193       /* Enable the main output */
01194       __HAL_TIM_MOE_ENABLE(htim);
01195     }
01196
01197     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01198     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01199     {
01200       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01201       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01202       {
01203         __HAL_TIM_ENABLE(htim);
01204       }
01205     }
01206     else
01207     {
01208       __HAL_TIM_ENABLE(htim);
01209     }
01210   }
01211
01212   /* Return function status */
01213   return status;
01214 }
01215
01216 /**
01217   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
01218   * @param  htim TIM Output Compare handle
01219   * @param  Channel TIM Channel to be disabled
01220   *          This parameter can be one of the following values:
01221   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01222   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01223   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01224   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01225   * @retval HAL status
01226   */
01227 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01228 {
01229   HAL_StatusTypeDef status = HAL_OK;
01230
01231   /* Check the parameters */
01232   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01233
01234   switch (Channel)
01235   {
01236     case TIM_CHANNEL_1:
01237     {
01238       /* Disable the TIM Capture/Compare 1 DMA request */
01239       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01240       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01241       break;
01242     }
01243
01244     case TIM_CHANNEL_2:
01245     {
01246       /* Disable the TIM Capture/Compare 2 DMA request */
01247       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01248       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01249       break;
01250     }
01251
01252     case TIM_CHANNEL_3:
01253     {
01254       /* Disable the TIM Capture/Compare 3 DMA request */
01255       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01256       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01257       break;
01258     }
01259
01260     case TIM_CHANNEL_4:
01261     {
01262       /* Disable the TIM Capture/Compare 4 interrupt */
01263       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01264       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01265       break;
01266     }
01267
01268     default:
01269       status = HAL_ERROR;
01270       break;
01271   }
01272
01273   if (status == HAL_OK)
01274   {
01275     /* Disable the Output compare channel */
01276     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01277
01278     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01279     {
01280       /* Disable the Main Output */
01281       __HAL_TIM_MOE_DISABLE(htim);
01282     }
01283
01284     /* Disable the Peripheral */
01285     __HAL_TIM_DISABLE(htim);
01286
01287     /* Set the TIM channel state */
01288     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01289   }
01290
01291   /* Return function status */
01292   return status;
01293 }
01294
01295 /**
01296   * @}
01297   */
01298
01299 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
01300   *  @brief    TIM PWM functions
01301   *
01302 @verbatim
01303   ==============================================================================
01304                           ##### TIM PWM functions #####
01305   ==============================================================================
01306   [..]
01307     This section provides functions allowing to:
01308     (+) Initialize and configure the TIM PWM.
01309     (+) De-initialize the TIM PWM.
01310     (+) Start the TIM PWM.
01311     (+) Stop the TIM PWM.
01312     (+) Start the TIM PWM and enable interrupt.
01313     (+) Stop the TIM PWM and disable interrupt.
01314     (+) Start the TIM PWM and enable DMA transfer.
01315     (+) Stop the TIM PWM and disable DMA transfer.
01316
01317 @endverbatim
01318   * @{
01319   */
01320 /**
01321   * @brief  Initializes the TIM PWM Time Base according to the specified
01322   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
01323   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01324   *         requires a timer reset to avoid unexpected direction
01325   *         due to DIR bit readonly in center aligned mode.
01326   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
01327   * @param  htim TIM PWM handle
01328   * @retval HAL status
01329   */
01330 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
01331 {
01332   /* Check the TIM handle allocation */
01333   if (htim == NULL)
01334   {
01335     return HAL_ERROR;
01336   }
01337
01338   /* Check the parameters */
01339   assert_param(IS_TIM_INSTANCE(htim->Instance));
01340   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01341   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01342   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
01343   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01344
01345   if (htim->State == HAL_TIM_STATE_RESET)
01346   {
01347     /* Allocate lock resource and initialize it */
01348     htim->Lock = HAL_UNLOCKED;
01349
01350 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01351     /* Reset interrupt callbacks to legacy weak callbacks */
01352     TIM_ResetCallback(htim);
01353
01354     if (htim->PWM_MspInitCallback == NULL)
01355     {
01356       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
01357     }
01358     /* Init the low level hardware : GPIO, CLOCK, NVIC */
01359     htim->PWM_MspInitCallback(htim);
01360 #else
01361     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01362     HAL_TIM_PWM_MspInit(htim);
01363 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01364   }
01365
01366   /* Set the TIM state */
01367   htim->State = HAL_TIM_STATE_BUSY;
01368
01369   /* Init the base time for the PWM */
01370   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01371
01372   /* Initialize the DMA burst operation state */
01373   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
01374
01375   /* Initialize the TIM channels state */
01376   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
01377   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
01378
01379   /* Initialize the TIM state*/
01380   htim->State = HAL_TIM_STATE_READY;
01381
01382   return HAL_OK;
01383 }
01384
01385 /**
01386   * @brief  DeInitializes the TIM peripheral
01387   * @param  htim TIM PWM handle
01388   * @retval HAL status
01389   */
01390 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01391 {
01392   /* Check the parameters */
01393   assert_param(IS_TIM_INSTANCE(htim->Instance));
01394
01395   htim->State = HAL_TIM_STATE_BUSY;
01396
01397   /* Disable the TIM Peripheral Clock */
01398   __HAL_TIM_DISABLE(htim);
01399
01400 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01401   if (htim->PWM_MspDeInitCallback == NULL)
01402   {
01403     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
01404   }
01405   /* DeInit the low level hardware */
01406   htim->PWM_MspDeInitCallback(htim);
01407 #else
01408   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01409   HAL_TIM_PWM_MspDeInit(htim);
01410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01411
01412   /* Change the DMA burst operation state */
01413   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
01414
01415   /* Change the TIM channels state */
01416   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
01417   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
01418
01419   /* Change TIM state */
01420   htim->State = HAL_TIM_STATE_RESET;
01421
01422   /* Release Lock */
01423   __HAL_UNLOCK(htim);
01424
01425   return HAL_OK;
01426 }
01427
01428 /**
01429   * @brief  Initializes the TIM PWM MSP.
01430   * @param  htim TIM PWM handle
01431   * @retval None
01432   */
01433 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01434 {
01435   /* Prevent unused argument(s) compilation warning */
01436   UNUSED(htim);
01437
01438   /* NOTE : This function should not be modified, when the callback is needed,
01439             the HAL_TIM_PWM_MspInit could be implemented in the user file
01440    */
01441 }
01442
01443 /**
01444   * @brief  DeInitializes TIM PWM MSP.
01445   * @param  htim TIM PWM handle
01446   * @retval None
01447   */
01448 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01449 {
01450   /* Prevent unused argument(s) compilation warning */
01451   UNUSED(htim);
01452
01453   /* NOTE : This function should not be modified, when the callback is needed,
01454             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01455    */
01456 }
01457
01458 /**
01459   * @brief  Starts the PWM signal generation.
01460   * @param  htim TIM handle
01461   * @param  Channel TIM Channels to be enabled
01462   *          This parameter can be one of the following values:
01463   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01464   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01465   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01466   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01467   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01468   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01469   * @retval HAL status
01470   */
01471 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01472 {
01473   uint32_t tmpsmcr;
01474
01475   /* Check the parameters */
01476   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01477
01478   /* Check the TIM channel state */
01479   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
01480   {
01481     return HAL_ERROR;
01482   }
01483
01484   /* Set the TIM channel state */
01485   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01486
01487   /* Enable the Capture compare channel */
01488   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01489
01490   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01491   {
01492     /* Enable the main output */
01493     __HAL_TIM_MOE_ENABLE(htim);
01494   }
01495
01496   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01497   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01498   {
01499     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01500     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01501     {
01502       __HAL_TIM_ENABLE(htim);
01503     }
01504   }
01505   else
01506   {
01507     __HAL_TIM_ENABLE(htim);
01508   }
01509
01510   /* Return function status */
01511   return HAL_OK;
01512 }
01513
01514 /**
01515   * @brief  Stops the PWM signal generation.
01516   * @param  htim TIM PWM handle
01517   * @param  Channel TIM Channels to be disabled
01518   *          This parameter can be one of the following values:
01519   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01520   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01521   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01522   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01523   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01524   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01525   * @retval HAL status
01526   */
01527 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01528 {
01529   /* Check the parameters */
01530   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01531
01532   /* Disable the Capture compare channel */
01533   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01534
01535   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01536   {
01537     /* Disable the Main Output */
01538     __HAL_TIM_MOE_DISABLE(htim);
01539   }
01540
01541   /* Disable the Peripheral */
01542   __HAL_TIM_DISABLE(htim);
01543
01544   /* Set the TIM channel state */
01545   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01546
01547   /* Return function status */
01548   return HAL_OK;
01549 }
01550
01551 /**
01552   * @brief  Starts the PWM signal generation in interrupt mode.
01553   * @param  htim TIM PWM handle
01554   * @param  Channel TIM Channel to be enabled
01555   *          This parameter can be one of the following values:
01556   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01557   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01558   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01559   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01560   * @retval HAL status
01561   */
01562 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01563 {
01564   HAL_StatusTypeDef status = HAL_OK;
01565   uint32_t tmpsmcr;
01566
01567   /* Check the parameters */
01568   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01569
01570   /* Check the TIM channel state */
01571   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
01572   {
01573     return HAL_ERROR;
01574   }
01575
01576   /* Set the TIM channel state */
01577   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01578
01579   switch (Channel)
01580   {
01581     case TIM_CHANNEL_1:
01582     {
01583       /* Enable the TIM Capture/Compare 1 interrupt */
01584       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01585       break;
01586     }
01587
01588     case TIM_CHANNEL_2:
01589     {
01590       /* Enable the TIM Capture/Compare 2 interrupt */
01591       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01592       break;
01593     }
01594
01595     case TIM_CHANNEL_3:
01596     {
01597       /* Enable the TIM Capture/Compare 3 interrupt */
01598       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01599       break;
01600     }
01601
01602     case TIM_CHANNEL_4:
01603     {
01604       /* Enable the TIM Capture/Compare 4 interrupt */
01605       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01606       break;
01607     }
01608
01609     default:
01610       status = HAL_ERROR;
01611       break;
01612   }
01613
01614   if (status == HAL_OK)
01615   {
01616     /* Enable the Capture compare channel */
01617     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01618
01619     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01620     {
01621       /* Enable the main output */
01622       __HAL_TIM_MOE_ENABLE(htim);
01623     }
01624
01625     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01626     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01627     {
01628       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01629       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01630       {
01631         __HAL_TIM_ENABLE(htim);
01632       }
01633     }
01634     else
01635     {
01636       __HAL_TIM_ENABLE(htim);
01637     }
01638   }
01639
01640   /* Return function status */
01641   return status;
01642 }
01643
01644 /**
01645   * @brief  Stops the PWM signal generation in interrupt mode.
01646   * @param  htim TIM PWM handle
01647   * @param  Channel TIM Channels to be disabled
01648   *          This parameter can be one of the following values:
01649   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01650   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01651   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01652   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01653   * @retval HAL status
01654   */
01655 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01656 {
01657   HAL_StatusTypeDef status = HAL_OK;
01658
01659   /* Check the parameters */
01660   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01661
01662   switch (Channel)
01663   {
01664     case TIM_CHANNEL_1:
01665     {
01666       /* Disable the TIM Capture/Compare 1 interrupt */
01667       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01668       break;
01669     }
01670
01671     case TIM_CHANNEL_2:
01672     {
01673       /* Disable the TIM Capture/Compare 2 interrupt */
01674       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01675       break;
01676     }
01677
01678     case TIM_CHANNEL_3:
01679     {
01680       /* Disable the TIM Capture/Compare 3 interrupt */
01681       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01682       break;
01683     }
01684
01685     case TIM_CHANNEL_4:
01686     {
01687       /* Disable the TIM Capture/Compare 4 interrupt */
01688       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01689       break;
01690     }
01691
01692     default:
01693       status = HAL_ERROR;
01694       break;
01695   }
01696
01697   if (status == HAL_OK)
01698   {
01699     /* Disable the Capture compare channel */
01700     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01701
01702     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01703     {
01704       /* Disable the Main Output */
01705       __HAL_TIM_MOE_DISABLE(htim);
01706     }
01707
01708     /* Disable the Peripheral */
01709     __HAL_TIM_DISABLE(htim);
01710
01711     /* Set the TIM channel state */
01712     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01713   }
01714
01715   /* Return function status */
01716   return status;
01717 }
01718
01719 /**
01720   * @brief  Starts the TIM PWM signal generation in DMA mode.
01721   * @param  htim TIM PWM handle
01722   * @param  Channel TIM Channels to be enabled
01723   *          This parameter can be one of the following values:
01724   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01725   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01726   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01727   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01728   * @param  pData The source Buffer address.
01729   * @param  Length The length of data to be transferred from memory to TIM peripheral
01730   * @retval HAL status
01731   */
01732 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
01733                                         uint16_t Length)
01734 {
01735   HAL_StatusTypeDef status = HAL_OK;
01736   uint32_t tmpsmcr;
01737
01738   /* Check the parameters */
01739   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01740
01741   /* Set the TIM channel state */
01742   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
01743   {
01744     return HAL_BUSY;
01745   }
01746   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
01747   {
01748     if ((pData == NULL) || (Length == 0U))
01749     {
01750       return HAL_ERROR;
01751     }
01752     else
01753     {
01754       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01755     }
01756   }
01757   else
01758   {
01759     return HAL_ERROR;
01760   }
01761
01762   switch (Channel)
01763   {
01764     case TIM_CHANNEL_1:
01765     {
01766       /* Set the DMA compare callbacks */
01767       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01768       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01769
01770       /* Set the DMA error callback */
01771       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01772
01773       /* Enable the DMA channel */
01774       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
01775                            Length) != HAL_OK)
01776       {
01777         /* Return error status */
01778         return HAL_ERROR;
01779       }
01780
01781       /* Enable the TIM Capture/Compare 1 DMA request */
01782       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01783       break;
01784     }
01785
01786     case TIM_CHANNEL_2:
01787     {
01788       /* Set the DMA compare callbacks */
01789       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01790       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01791
01792       /* Set the DMA error callback */
01793       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01794
01795       /* Enable the DMA channel */
01796       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
01797                            Length) != HAL_OK)
01798       {
01799         /* Return error status */
01800         return HAL_ERROR;
01801       }
01802       /* Enable the TIM Capture/Compare 2 DMA request */
01803       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01804       break;
01805     }
01806
01807     case TIM_CHANNEL_3:
01808     {
01809       /* Set the DMA compare callbacks */
01810       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01811       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01812
01813       /* Set the DMA error callback */
01814       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01815
01816       /* Enable the DMA channel */
01817       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
01818                            Length) != HAL_OK)
01819       {
01820         /* Return error status */
01821         return HAL_ERROR;
01822       }
01823       /* Enable the TIM Output Capture/Compare 3 request */
01824       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01825       break;
01826     }
01827
01828     case TIM_CHANNEL_4:
01829     {
01830       /* Set the DMA compare callbacks */
01831       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01832       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01833
01834       /* Set the DMA error callback */
01835       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01836
01837       /* Enable the DMA channel */
01838       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
01839                            Length) != HAL_OK)
01840       {
01841         /* Return error status */
01842         return HAL_ERROR;
01843       }
01844       /* Enable the TIM Capture/Compare 4 DMA request */
01845       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01846       break;
01847     }
01848
01849     default:
01850       status = HAL_ERROR;
01851       break;
01852   }
01853
01854   if (status == HAL_OK)
01855   {
01856     /* Enable the Capture compare channel */
01857     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01858
01859     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01860     {
01861       /* Enable the main output */
01862       __HAL_TIM_MOE_ENABLE(htim);
01863     }
01864
01865     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01866     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01867     {
01868       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01869       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01870       {
01871         __HAL_TIM_ENABLE(htim);
01872       }
01873     }
01874     else
01875     {
01876       __HAL_TIM_ENABLE(htim);
01877     }
01878   }
01879
01880   /* Return function status */
01881   return status;
01882 }
01883
01884 /**
01885   * @brief  Stops the TIM PWM signal generation in DMA mode.
01886   * @param  htim TIM PWM handle
01887   * @param  Channel TIM Channels to be disabled
01888   *          This parameter can be one of the following values:
01889   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01890   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01891   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01892   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01893   * @retval HAL status
01894   */
01895 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01896 {
01897   HAL_StatusTypeDef status = HAL_OK;
01898
01899   /* Check the parameters */
01900   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01901
01902   switch (Channel)
01903   {
01904     case TIM_CHANNEL_1:
01905     {
01906       /* Disable the TIM Capture/Compare 1 DMA request */
01907       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01908       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01909       break;
01910     }
01911
01912     case TIM_CHANNEL_2:
01913     {
01914       /* Disable the TIM Capture/Compare 2 DMA request */
01915       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01916       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01917       break;
01918     }
01919
01920     case TIM_CHANNEL_3:
01921     {
01922       /* Disable the TIM Capture/Compare 3 DMA request */
01923       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01924       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01925       break;
01926     }
01927
01928     case TIM_CHANNEL_4:
01929     {
01930       /* Disable the TIM Capture/Compare 4 interrupt */
01931       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01932       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01933       break;
01934     }
01935
01936     default:
01937       status = HAL_ERROR;
01938       break;
01939   }
01940
01941   if (status == HAL_OK)
01942   {
01943     /* Disable the Capture compare channel */
01944     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01945
01946     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01947     {
01948       /* Disable the Main Output */
01949       __HAL_TIM_MOE_DISABLE(htim);
01950     }
01951
01952     /* Disable the Peripheral */
01953     __HAL_TIM_DISABLE(htim);
01954
01955     /* Set the TIM channel state */
01956     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01957   }
01958
01959   /* Return function status */
01960   return status;
01961 }
01962
01963 /**
01964   * @}
01965   */
01966
01967 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
01968   *  @brief    TIM Input Capture functions
01969   *
01970 @verbatim
01971   ==============================================================================
01972               ##### TIM Input Capture functions #####
01973   ==============================================================================
01974  [..]
01975    This section provides functions allowing to:
01976    (+) Initialize and configure the TIM Input Capture.
01977    (+) De-initialize the TIM Input Capture.
01978    (+) Start the TIM Input Capture.
01979    (+) Stop the TIM Input Capture.
01980    (+) Start the TIM Input Capture and enable interrupt.
01981    (+) Stop the TIM Input Capture and disable interrupt.
01982    (+) Start the TIM Input Capture and enable DMA transfer.
01983    (+) Stop the TIM Input Capture and disable DMA transfer.
01984
01985 @endverbatim
01986   * @{
01987   */
01988 /**
01989   * @brief  Initializes the TIM Input Capture Time base according to the specified
01990   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
01991   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01992   *         requires a timer reset to avoid unexpected direction
01993   *         due to DIR bit readonly in center aligned mode.
01994   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
01995   * @param  htim TIM Input Capture handle
01996   * @retval HAL status
01997   */
01998 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01999 {
02000   /* Check the TIM handle allocation */
02001   if (htim == NULL)
02002   {
02003     return HAL_ERROR;
02004   }
02005
02006   /* Check the parameters */
02007   assert_param(IS_TIM_INSTANCE(htim->Instance));
02008   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02009   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02010   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
02011   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02012
02013   if (htim->State == HAL_TIM_STATE_RESET)
02014   {
02015     /* Allocate lock resource and initialize it */
02016     htim->Lock = HAL_UNLOCKED;
02017
02018 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02019     /* Reset interrupt callbacks to legacy weak callbacks */
02020     TIM_ResetCallback(htim);
02021
02022     if (htim->IC_MspInitCallback == NULL)
02023     {
02024       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
02025     }
02026     /* Init the low level hardware : GPIO, CLOCK, NVIC */
02027     htim->IC_MspInitCallback(htim);
02028 #else
02029     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02030     HAL_TIM_IC_MspInit(htim);
02031 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02032   }
02033
02034   /* Set the TIM state */
02035   htim->State = HAL_TIM_STATE_BUSY;
02036
02037   /* Init the base time for the input capture */
02038   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02039
02040   /* Initialize the DMA burst operation state */
02041   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
02042
02043   /* Initialize the TIM channels state */
02044   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
02045   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
02046
02047   /* Initialize the TIM state*/
02048   htim->State = HAL_TIM_STATE_READY;
02049
02050   return HAL_OK;
02051 }
02052
02053 /**
02054   * @brief  DeInitializes the TIM peripheral
02055   * @param  htim TIM Input Capture handle
02056   * @retval HAL status
02057   */
02058 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
02059 {
02060   /* Check the parameters */
02061   assert_param(IS_TIM_INSTANCE(htim->Instance));
02062
02063   htim->State = HAL_TIM_STATE_BUSY;
02064
02065   /* Disable the TIM Peripheral Clock */
02066   __HAL_TIM_DISABLE(htim);
02067
02068 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02069   if (htim->IC_MspDeInitCallback == NULL)
02070   {
02071     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
02072   }
02073   /* DeInit the low level hardware */
02074   htim->IC_MspDeInitCallback(htim);
02075 #else
02076   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
02077   HAL_TIM_IC_MspDeInit(htim);
02078 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02079
02080   /* Change the DMA burst operation state */
02081   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
02082
02083   /* Change the TIM channels state */
02084   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
02085   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
02086
02087   /* Change TIM state */
02088   htim->State = HAL_TIM_STATE_RESET;
02089
02090   /* Release Lock */
02091   __HAL_UNLOCK(htim);
02092
02093   return HAL_OK;
02094 }
02095
02096 /**
02097   * @brief  Initializes the TIM Input Capture MSP.
02098   * @param  htim TIM Input Capture handle
02099   * @retval None
02100   */
02101 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
02102 {
02103   /* Prevent unused argument(s) compilation warning */
02104   UNUSED(htim);
02105
02106   /* NOTE : This function should not be modified, when the callback is needed,
02107             the HAL_TIM_IC_MspInit could be implemented in the user file
02108    */
02109 }
02110
02111 /**
02112   * @brief  DeInitializes TIM Input Capture MSP.
02113   * @param  htim TIM handle
02114   * @retval None
02115   */
02116 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
02117 {
02118   /* Prevent unused argument(s) compilation warning */
02119   UNUSED(htim);
02120
02121   /* NOTE : This function should not be modified, when the callback is needed,
02122             the HAL_TIM_IC_MspDeInit could be implemented in the user file
02123    */
02124 }
02125
02126 /**
02127   * @brief  Starts the TIM Input Capture measurement.
02128   * @param  htim TIM Input Capture handle
02129   * @param  Channel TIM Channels to be enabled
02130   *          This parameter can be one of the following values:
02131   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02132   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02133   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02134   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02135   * @retval HAL status
02136   */
02137 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02138 {
02139   uint32_t tmpsmcr;
02140   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
02141   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
02142
02143   /* Check the parameters */
02144   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02145
02146   /* Check the TIM channel state */
02147   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
02148       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
02149   {
02150     return HAL_ERROR;
02151   }
02152
02153   /* Set the TIM channel state */
02154   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02155   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02156
02157   /* Enable the Input Capture channel */
02158   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
02159
02160   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
02161   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
02162   {
02163     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
02164     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
02165     {
02166       __HAL_TIM_ENABLE(htim);
02167     }
02168   }
02169   else
02170   {
02171     __HAL_TIM_ENABLE(htim);
02172   }
02173
02174   /* Return function status */
02175   return HAL_OK;
02176 }
02177
02178 /**
02179   * @brief  Stops the TIM Input Capture measurement.
02180   * @param  htim TIM Input Capture handle
02181   * @param  Channel TIM Channels to be disabled
02182   *          This parameter can be one of the following values:
02183   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02184   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02185   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02186   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02187   * @retval HAL status
02188   */
02189 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02190 {
02191   /* Check the parameters */
02192   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02193
02194   /* Disable the Input Capture channel */
02195   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02196
02197   /* Disable the Peripheral */
02198   __HAL_TIM_DISABLE(htim);
02199
02200   /* Set the TIM channel state */
02201   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02202   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02203
02204   /* Return function status */
02205   return HAL_OK;
02206 }
02207
02208 /**
02209   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
02210   * @param  htim TIM Input Capture handle
02211   * @param  Channel TIM Channels to be enabled
02212   *          This parameter can be one of the following values:
02213   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02214   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02215   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02216   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02217   * @retval HAL status
02218   */
02219 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02220 {
02221   HAL_StatusTypeDef status = HAL_OK;
02222   uint32_t tmpsmcr;
02223
02224   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
02225   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
02226
02227   /* Check the parameters */
02228   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02229
02230   /* Check the TIM channel state */
02231   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
02232       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
02233   {
02234     return HAL_ERROR;
02235   }
02236
02237   /* Set the TIM channel state */
02238   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02239   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02240
02241   switch (Channel)
02242   {
02243     case TIM_CHANNEL_1:
02244     {
02245       /* Enable the TIM Capture/Compare 1 interrupt */
02246       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02247       break;
02248     }
02249
02250     case TIM_CHANNEL_2:
02251     {
02252       /* Enable the TIM Capture/Compare 2 interrupt */
02253       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02254       break;
02255     }
02256
02257     case TIM_CHANNEL_3:
02258     {
02259       /* Enable the TIM Capture/Compare 3 interrupt */
02260       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
02261       break;
02262     }
02263
02264     case TIM_CHANNEL_4:
02265     {
02266       /* Enable the TIM Capture/Compare 4 interrupt */
02267       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
02268       break;
02269     }
02270
02271     default:
02272       status = HAL_ERROR;
02273       break;
02274   }
02275
02276   if (status == HAL_OK)
02277   {
02278     /* Enable the Input Capture channel */
02279     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
02280
02281     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
02282     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
02283     {
02284       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
02285       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
02286       {
02287         __HAL_TIM_ENABLE(htim);
02288       }
02289     }
02290     else
02291     {
02292       __HAL_TIM_ENABLE(htim);
02293     }
02294   }
02295
02296   /* Return function status */
02297   return status;
02298 }
02299
02300 /**
02301   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
02302   * @param  htim TIM Input Capture handle
02303   * @param  Channel TIM Channels to be disabled
02304   *          This parameter can be one of the following values:
02305   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02306   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02307   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02308   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02309   * @retval HAL status
02310   */
02311 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02312 {
02313   HAL_StatusTypeDef status = HAL_OK;
02314
02315   /* Check the parameters */
02316   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02317
02318   switch (Channel)
02319   {
02320     case TIM_CHANNEL_1:
02321     {
02322       /* Disable the TIM Capture/Compare 1 interrupt */
02323       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02324       break;
02325     }
02326
02327     case TIM_CHANNEL_2:
02328     {
02329       /* Disable the TIM Capture/Compare 2 interrupt */
02330       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02331       break;
02332     }
02333
02334     case TIM_CHANNEL_3:
02335     {
02336       /* Disable the TIM Capture/Compare 3 interrupt */
02337       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
02338       break;
02339     }
02340
02341     case TIM_CHANNEL_4:
02342     {
02343       /* Disable the TIM Capture/Compare 4 interrupt */
02344       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
02345       break;
02346     }
02347
02348     default:
02349       status = HAL_ERROR;
02350       break;
02351   }
02352
02353   if (status == HAL_OK)
02354   {
02355     /* Disable the Input Capture channel */
02356     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02357
02358     /* Disable the Peripheral */
02359     __HAL_TIM_DISABLE(htim);
02360
02361     /* Set the TIM channel state */
02362     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02363     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02364   }
02365
02366   /* Return function status */
02367   return status;
02368 }
02369
02370 /**
02371   * @brief  Starts the TIM Input Capture measurement in DMA mode.
02372   * @param  htim TIM Input Capture handle
02373   * @param  Channel TIM Channels to be enabled
02374   *          This parameter can be one of the following values:
02375   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02376   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02377   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02378   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02379   * @param  pData The destination Buffer address.
02380   * @param  Length The length of data to be transferred from TIM peripheral to memory.
02381   * @retval HAL status
02382   */
02383 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
02384 {
02385   HAL_StatusTypeDef status = HAL_OK;
02386   uint32_t tmpsmcr;
02387
02388   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
02389   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
02390
02391   /* Check the parameters */
02392   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02393   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02394
02395   /* Set the TIM channel state */
02396   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
02397       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
02398   {
02399     return HAL_BUSY;
02400   }
02401   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
02402            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
02403   {
02404     if ((pData == NULL) || (Length == 0U))
02405     {
02406       return HAL_ERROR;
02407     }
02408     else
02409     {
02410       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02411       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
02412     }
02413   }
02414   else
02415   {
02416     return HAL_ERROR;
02417   }
02418
02419   /* Enable the Input Capture channel */
02420   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
02421
02422   switch (Channel)
02423   {
02424     case TIM_CHANNEL_1:
02425     {
02426       /* Set the DMA capture callbacks */
02427       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02428       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02429
02430       /* Set the DMA error callback */
02431       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02432
02433       /* Enable the DMA channel */
02434       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
02435                            Length) != HAL_OK)
02436       {
02437         /* Return error status */
02438         return HAL_ERROR;
02439       }
02440       /* Enable the TIM Capture/Compare 1 DMA request */
02441       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02442       break;
02443     }
02444
02445     case TIM_CHANNEL_2:
02446     {
02447       /* Set the DMA capture callbacks */
02448       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02449       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02450
02451       /* Set the DMA error callback */
02452       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02453
02454       /* Enable the DMA channel */
02455       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
02456                            Length) != HAL_OK)
02457       {
02458         /* Return error status */
02459         return HAL_ERROR;
02460       }
02461       /* Enable the TIM Capture/Compare 2  DMA request */
02462       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02463       break;
02464     }
02465
02466     case TIM_CHANNEL_3:
02467     {
02468       /* Set the DMA capture callbacks */
02469       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
02470       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02471
02472       /* Set the DMA error callback */
02473       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
02474
02475       /* Enable the DMA channel */
02476       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
02477                            Length) != HAL_OK)
02478       {
02479         /* Return error status */
02480         return HAL_ERROR;
02481       }
02482       /* Enable the TIM Capture/Compare 3  DMA request */
02483       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
02484       break;
02485     }
02486
02487     case TIM_CHANNEL_4:
02488     {
02489       /* Set the DMA capture callbacks */
02490       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
02491       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02492
02493       /* Set the DMA error callback */
02494       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
02495
02496       /* Enable the DMA channel */
02497       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
02498                            Length) != HAL_OK)
02499       {
02500         /* Return error status */
02501         return HAL_ERROR;
02502       }
02503       /* Enable the TIM Capture/Compare 4  DMA request */
02504       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
02505       break;
02506     }
02507
02508     default:
02509       status = HAL_ERROR;
02510       break;
02511   }
02512
02513   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
02514   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
02515   {
02516     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
02517     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
02518     {
02519       __HAL_TIM_ENABLE(htim);
02520     }
02521   }
02522   else
02523   {
02524     __HAL_TIM_ENABLE(htim);
02525   }
02526
02527   /* Return function status */
02528   return status;
02529 }
02530
02531 /**
02532   * @brief  Stops the TIM Input Capture measurement in DMA mode.
02533   * @param  htim TIM Input Capture handle
02534   * @param  Channel TIM Channels to be disabled
02535   *          This parameter can be one of the following values:
02536   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02537   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02538   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02539   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02540   * @retval HAL status
02541   */
02542 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02543 {
02544   HAL_StatusTypeDef status = HAL_OK;
02545
02546   /* Check the parameters */
02547   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02548   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02549
02550   /* Disable the Input Capture channel */
02551   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02552
02553   switch (Channel)
02554   {
02555     case TIM_CHANNEL_1:
02556     {
02557       /* Disable the TIM Capture/Compare 1 DMA request */
02558       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02559       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
02560       break;
02561     }
02562
02563     case TIM_CHANNEL_2:
02564     {
02565       /* Disable the TIM Capture/Compare 2 DMA request */
02566       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02567       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
02568       break;
02569     }
02570
02571     case TIM_CHANNEL_3:
02572     {
02573       /* Disable the TIM Capture/Compare 3  DMA request */
02574       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
02575       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
02576       break;
02577     }
02578
02579     case TIM_CHANNEL_4:
02580     {
02581       /* Disable the TIM Capture/Compare 4  DMA request */
02582       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
02583       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
02584       break;
02585     }
02586
02587     default:
02588       status = HAL_ERROR;
02589       break;
02590   }
02591
02592   if (status == HAL_OK)
02593   {
02594     /* Disable the Peripheral */
02595     __HAL_TIM_DISABLE(htim);
02596
02597     /* Set the TIM channel state */
02598     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02599     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
02600   }
02601
02602   /* Return function status */
02603   return status;
02604 }
02605 /**
02606   * @}
02607   */
02608
02609 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
02610   *  @brief    TIM One Pulse functions
02611   *
02612 @verbatim
02613   ==============================================================================
02614                         ##### TIM One Pulse functions #####
02615   ==============================================================================
02616   [..]
02617     This section provides functions allowing to:
02618     (+) Initialize and configure the TIM One Pulse.
02619     (+) De-initialize the TIM One Pulse.
02620     (+) Start the TIM One Pulse.
02621     (+) Stop the TIM One Pulse.
02622     (+) Start the TIM One Pulse and enable interrupt.
02623     (+) Stop the TIM One Pulse and disable interrupt.
02624     (+) Start the TIM One Pulse and enable DMA transfer.
02625     (+) Stop the TIM One Pulse and disable DMA transfer.
02626
02627 @endverbatim
02628   * @{
02629   */
02630 /**
02631   * @brief  Initializes the TIM One Pulse Time Base according to the specified
02632   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
02633   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
02634   *         requires a timer reset to avoid unexpected direction
02635   *         due to DIR bit readonly in center aligned mode.
02636   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
02637   * @note   When the timer instance is initialized in One Pulse mode, timer
02638   *         channels 1 and channel 2 are reserved and cannot be used for other
02639   *         purpose.
02640   * @param  htim TIM One Pulse handle
02641   * @param  OnePulseMode Select the One pulse mode.
02642   *         This parameter can be one of the following values:
02643   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
02644   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
02645   * @retval HAL status
02646   */
02647 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
02648 {
02649   /* Check the TIM handle allocation */
02650   if (htim == NULL)
02651   {
02652     return HAL_ERROR;
02653   }
02654
02655   /* Check the parameters */
02656   assert_param(IS_TIM_INSTANCE(htim->Instance));
02657   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02658   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02659   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
02660   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
02661   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02662
02663   if (htim->State == HAL_TIM_STATE_RESET)
02664   {
02665     /* Allocate lock resource and initialize it */
02666     htim->Lock = HAL_UNLOCKED;
02667
02668 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02669     /* Reset interrupt callbacks to legacy weak callbacks */
02670     TIM_ResetCallback(htim);
02671
02672     if (htim->OnePulse_MspInitCallback == NULL)
02673     {
02674       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
02675     }
02676     /* Init the low level hardware : GPIO, CLOCK, NVIC */
02677     htim->OnePulse_MspInitCallback(htim);
02678 #else
02679     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02680     HAL_TIM_OnePulse_MspInit(htim);
02681 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02682   }
02683
02684   /* Set the TIM state */
02685   htim->State = HAL_TIM_STATE_BUSY;
02686
02687   /* Configure the Time base in the One Pulse Mode */
02688   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02689
02690   /* Reset the OPM Bit */
02691   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02692
02693   /* Configure the OPM Mode */
02694   htim->Instance->CR1 |= OnePulseMode;
02695
02696   /* Initialize the DMA burst operation state */
02697   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
02698
02699   /* Initialize the TIM channels state */
02700   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02701   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02702   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02703   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02704
02705   /* Initialize the TIM state*/
02706   htim->State = HAL_TIM_STATE_READY;
02707
02708   return HAL_OK;
02709 }
02710
02711 /**
02712   * @brief  DeInitializes the TIM One Pulse
02713   * @param  htim TIM One Pulse handle
02714   * @retval HAL status
02715   */
02716 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02717 {
02718   /* Check the parameters */
02719   assert_param(IS_TIM_INSTANCE(htim->Instance));
02720
02721   htim->State = HAL_TIM_STATE_BUSY;
02722
02723   /* Disable the TIM Peripheral Clock */
02724   __HAL_TIM_DISABLE(htim);
02725
02726 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02727   if (htim->OnePulse_MspDeInitCallback == NULL)
02728   {
02729     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
02730   }
02731   /* DeInit the low level hardware */
02732   htim->OnePulse_MspDeInitCallback(htim);
02733 #else
02734   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02735   HAL_TIM_OnePulse_MspDeInit(htim);
02736 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02737
02738   /* Change the DMA burst operation state */
02739   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
02740
02741   /* Set the TIM channel state */
02742   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
02743   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
02744   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
02745   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
02746
02747   /* Change TIM state */
02748   htim->State = HAL_TIM_STATE_RESET;
02749
02750   /* Release Lock */
02751   __HAL_UNLOCK(htim);
02752
02753   return HAL_OK;
02754 }
02755
02756 /**
02757   * @brief  Initializes the TIM One Pulse MSP.
02758   * @param  htim TIM One Pulse handle
02759   * @retval None
02760   */
02761 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02762 {
02763   /* Prevent unused argument(s) compilation warning */
02764   UNUSED(htim);
02765
02766   /* NOTE : This function should not be modified, when the callback is needed,
02767             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02768    */
02769 }
02770
02771 /**
02772   * @brief  DeInitializes TIM One Pulse MSP.
02773   * @param  htim TIM One Pulse handle
02774   * @retval None
02775   */
02776 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02777 {
02778   /* Prevent unused argument(s) compilation warning */
02779   UNUSED(htim);
02780
02781   /* NOTE : This function should not be modified, when the callback is needed,
02782             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02783    */
02784 }
02785
02786 /**
02787   * @brief  Starts the TIM One Pulse signal generation.
02788   * @note Though OutputChannel parameter is deprecated and ignored by the function
02789   *        it has been kept to avoid HAL_TIM API compatibility break.
02790   * @note The pulse output channel is determined when calling
02791   *       @ref HAL_TIM_OnePulse_ConfigChannel().
02792   * @param  htim TIM One Pulse handle
02793   * @param  OutputChannel See note above
02794   * @retval HAL status
02795   */
02796 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02797 {
02798   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
02799   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
02800   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
02801   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
02802
02803   /* Prevent unused argument(s) compilation warning */
02804   UNUSED(OutputChannel);
02805
02806   /* Check the TIM channels state */
02807   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
02808       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
02809       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
02810       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
02811   {
02812     return HAL_ERROR;
02813   }
02814
02815   /* Set the TIM channels state */
02816   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
02817   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
02818   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
02819   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
02820
02821   /* Enable the Capture compare and the Input Capture channels
02822     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02823     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02824     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02825     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02826
02827     No need to enable the counter, it's enabled automatically by hardware
02828     (the counter starts in response to a stimulus and generate a pulse */
02829
02830   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02831   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02832
02833   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02834   {
02835     /* Enable the main output */
02836     __HAL_TIM_MOE_ENABLE(htim);
02837   }
02838
02839   /* Return function status */
02840   return HAL_OK;
02841 }
02842
02843 /**
02844   * @brief  Stops the TIM One Pulse signal generation.
02845   * @note Though OutputChannel parameter is deprecated and ignored by the function
02846   *        it has been kept to avoid HAL_TIM API compatibility break.
02847   * @note The pulse output channel is determined when calling
02848   *       @ref HAL_TIM_OnePulse_ConfigChannel().
02849   * @param  htim TIM One Pulse handle
02850   * @param  OutputChannel See note above
02851   * @retval HAL status
02852   */
02853 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02854 {
02855   /* Prevent unused argument(s) compilation warning */
02856   UNUSED(OutputChannel);
02857
02858   /* Disable the Capture compare and the Input Capture channels
02859   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02860   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02861   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02862   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02863
02864   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02865   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02866
02867   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02868   {
02869     /* Disable the Main Output */
02870     __HAL_TIM_MOE_DISABLE(htim);
02871   }
02872
02873   /* Disable the Peripheral */
02874   __HAL_TIM_DISABLE(htim);
02875
02876   /* Set the TIM channels state */
02877   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02878   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02879   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02880   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02881
02882   /* Return function status */
02883   return HAL_OK;
02884 }
02885
02886 /**
02887   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02888   * @note Though OutputChannel parameter is deprecated and ignored by the function
02889   *        it has been kept to avoid HAL_TIM API compatibility break.
02890   * @note The pulse output channel is determined when calling
02891   *       @ref HAL_TIM_OnePulse_ConfigChannel().
02892   * @param  htim TIM One Pulse handle
02893   * @param  OutputChannel See note above
02894   * @retval HAL status
02895   */
02896 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02897 {
02898   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
02899   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
02900   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
02901   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
02902
02903   /* Prevent unused argument(s) compilation warning */
02904   UNUSED(OutputChannel);
02905
02906   /* Check the TIM channels state */
02907   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
02908       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
02909       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
02910       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
02911   {
02912     return HAL_ERROR;
02913   }
02914
02915   /* Set the TIM channels state */
02916   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
02917   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
02918   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
02919   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
02920
02921   /* Enable the Capture compare and the Input Capture channels
02922     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02923     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02924     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02925     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02926
02927     No need to enable the counter, it's enabled automatically by hardware
02928     (the counter starts in response to a stimulus and generate a pulse */
02929
02930   /* Enable the TIM Capture/Compare 1 interrupt */
02931   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02932
02933   /* Enable the TIM Capture/Compare 2 interrupt */
02934   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02935
02936   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02937   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02938
02939   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02940   {
02941     /* Enable the main output */
02942     __HAL_TIM_MOE_ENABLE(htim);
02943   }
02944
02945   /* Return function status */
02946   return HAL_OK;
02947 }
02948
02949 /**
02950   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02951   * @note Though OutputChannel parameter is deprecated and ignored by the function
02952   *        it has been kept to avoid HAL_TIM API compatibility break.
02953   * @note The pulse output channel is determined when calling
02954   *       @ref HAL_TIM_OnePulse_ConfigChannel().
02955   * @param  htim TIM One Pulse handle
02956   * @param  OutputChannel See note above
02957   * @retval HAL status
02958   */
02959 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02960 {
02961   /* Prevent unused argument(s) compilation warning */
02962   UNUSED(OutputChannel);
02963
02964   /* Disable the TIM Capture/Compare 1 interrupt */
02965   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02966
02967   /* Disable the TIM Capture/Compare 2 interrupt */
02968   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02969
02970   /* Disable the Capture compare and the Input Capture channels
02971   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02972   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02973   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02974   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02975   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02976   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02977
02978   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02979   {
02980     /* Disable the Main Output */
02981     __HAL_TIM_MOE_DISABLE(htim);
02982   }
02983
02984   /* Disable the Peripheral */
02985   __HAL_TIM_DISABLE(htim);
02986
02987   /* Set the TIM channels state */
02988   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02989   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02990   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02991   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02992
02993   /* Return function status */
02994   return HAL_OK;
02995 }
02996
02997 /**
02998   * @}
02999   */
03000
03001 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
03002   *  @brief    TIM Encoder functions
03003   *
03004 @verbatim
03005   ==============================================================================
03006                           ##### TIM Encoder functions #####
03007   ==============================================================================
03008   [..]
03009     This section provides functions allowing to:
03010     (+) Initialize and configure the TIM Encoder.
03011     (+) De-initialize the TIM Encoder.
03012     (+) Start the TIM Encoder.
03013     (+) Stop the TIM Encoder.
03014     (+) Start the TIM Encoder and enable interrupt.
03015     (+) Stop the TIM Encoder and disable interrupt.
03016     (+) Start the TIM Encoder and enable DMA transfer.
03017     (+) Stop the TIM Encoder and disable DMA transfer.
03018
03019 @endverbatim
03020   * @{
03021   */
03022 /**
03023   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
03024   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
03025   *         requires a timer reset to avoid unexpected direction
03026   *         due to DIR bit readonly in center aligned mode.
03027   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
03028   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
03029   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
03030   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
03031   * @note   When the timer instance is initialized in Encoder mode, timer
03032   *         channels 1 and channel 2 are reserved and cannot be used for other
03033   *         purpose.
03034   * @param  htim TIM Encoder Interface handle
03035   * @param  sConfig TIM Encoder Interface configuration structure
03036   * @retval HAL status
03037   */
03038 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
03039 {
03040   uint32_t tmpsmcr;
03041   uint32_t tmpccmr1;
03042   uint32_t tmpccer;
03043
03044   /* Check the TIM handle allocation */
03045   if (htim == NULL)
03046   {
03047     return HAL_ERROR;
03048   }
03049
03050   /* Check the parameters */
03051   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03052   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
03053   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
03054   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
03055   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
03056   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
03057   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
03058   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
03059   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
03060   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
03061   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
03062   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
03063   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
03064   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
03065
03066   if (htim->State == HAL_TIM_STATE_RESET)
03067   {
03068     /* Allocate lock resource and initialize it */
03069     htim->Lock = HAL_UNLOCKED;
03070
03071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03072     /* Reset interrupt callbacks to legacy weak callbacks */
03073     TIM_ResetCallback(htim);
03074
03075     if (htim->Encoder_MspInitCallback == NULL)
03076     {
03077       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
03078     }
03079     /* Init the low level hardware : GPIO, CLOCK, NVIC */
03080     htim->Encoder_MspInitCallback(htim);
03081 #else
03082     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
03083     HAL_TIM_Encoder_MspInit(htim);
03084 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03085   }
03086
03087   /* Set the TIM state */
03088   htim->State = HAL_TIM_STATE_BUSY;
03089
03090   /* Reset the SMS and ECE bits */
03091   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
03092
03093   /* Configure the Time base in the Encoder Mode */
03094   TIM_Base_SetConfig(htim->Instance, &htim->Init);
03095
03096   /* Get the TIMx SMCR register value */
03097   tmpsmcr = htim->Instance->SMCR;
03098
03099   /* Get the TIMx CCMR1 register value */
03100   tmpccmr1 = htim->Instance->CCMR1;
03101
03102   /* Get the TIMx CCER register value */
03103   tmpccer = htim->Instance->CCER;
03104
03105   /* Set the encoder Mode */
03106   tmpsmcr |= sConfig->EncoderMode;
03107
03108   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
03109   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
03110   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
03111
03112   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
03113   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
03114   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
03115   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
03116   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
03117
03118   /* Set the TI1 and the TI2 Polarities */
03119   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
03120   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
03121   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
03122
03123   /* Write to TIMx SMCR */
03124   htim->Instance->SMCR = tmpsmcr;
03125
03126   /* Write to TIMx CCMR1 */
03127   htim->Instance->CCMR1 = tmpccmr1;
03128
03129   /* Write to TIMx CCER */
03130   htim->Instance->CCER = tmpccer;
03131
03132   /* Initialize the DMA burst operation state */
03133   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
03134
03135   /* Set the TIM channels state */
03136   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03137   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03138   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03139   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03140
03141   /* Initialize the TIM state*/
03142   htim->State = HAL_TIM_STATE_READY;
03143
03144   return HAL_OK;
03145 }
03146
03147
03148 /**
03149   * @brief  DeInitializes the TIM Encoder interface
03150   * @param  htim TIM Encoder Interface handle
03151   * @retval HAL status
03152   */
03153 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
03154 {
03155   /* Check the parameters */
03156   assert_param(IS_TIM_INSTANCE(htim->Instance));
03157
03158   htim->State = HAL_TIM_STATE_BUSY;
03159
03160   /* Disable the TIM Peripheral Clock */
03161   __HAL_TIM_DISABLE(htim);
03162
03163 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03164   if (htim->Encoder_MspDeInitCallback == NULL)
03165   {
03166     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
03167   }
03168   /* DeInit the low level hardware */
03169   htim->Encoder_MspDeInitCallback(htim);
03170 #else
03171   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
03172   HAL_TIM_Encoder_MspDeInit(htim);
03173 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03174
03175   /* Change the DMA burst operation state */
03176   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
03177
03178   /* Set the TIM channels state */
03179   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
03180   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
03181   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
03182   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
03183
03184   /* Change TIM state */
03185   htim->State = HAL_TIM_STATE_RESET;
03186
03187   /* Release Lock */
03188   __HAL_UNLOCK(htim);
03189
03190   return HAL_OK;
03191 }
03192
03193 /**
03194   * @brief  Initializes the TIM Encoder Interface MSP.
03195   * @param  htim TIM Encoder Interface handle
03196   * @retval None
03197   */
03198 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
03199 {
03200   /* Prevent unused argument(s) compilation warning */
03201   UNUSED(htim);
03202
03203   /* NOTE : This function should not be modified, when the callback is needed,
03204             the HAL_TIM_Encoder_MspInit could be implemented in the user file
03205    */
03206 }
03207
03208 /**
03209   * @brief  DeInitializes TIM Encoder Interface MSP.
03210   * @param  htim TIM Encoder Interface handle
03211   * @retval None
03212   */
03213 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
03214 {
03215   /* Prevent unused argument(s) compilation warning */
03216   UNUSED(htim);
03217
03218   /* NOTE : This function should not be modified, when the callback is needed,
03219             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
03220    */
03221 }
03222
03223 /**
03224   * @brief  Starts the TIM Encoder Interface.
03225   * @param  htim TIM Encoder Interface handle
03226   * @param  Channel TIM Channels to be enabled
03227   *          This parameter can be one of the following values:
03228   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03229   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03230   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03231   * @retval HAL status
03232   */
03233 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
03234 {
03235   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
03236   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
03237   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
03238   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
03239
03240   /* Check the parameters */
03241   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03242
03243   /* Set the TIM channel(s) state */
03244   if (Channel == TIM_CHANNEL_1)
03245   {
03246     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03247         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
03248     {
03249       return HAL_ERROR;
03250     }
03251     else
03252     {
03253       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03254       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03255     }
03256   }
03257   else if (Channel == TIM_CHANNEL_2)
03258   {
03259     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
03260         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
03261     {
03262       return HAL_ERROR;
03263     }
03264     else
03265     {
03266       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03267       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03268     }
03269   }
03270   else
03271   {
03272     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03273         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
03274         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03275         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
03276     {
03277       return HAL_ERROR;
03278     }
03279     else
03280     {
03281       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03282       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03283       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03284       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03285     }
03286   }
03287
03288   /* Enable the encoder interface channels */
03289   switch (Channel)
03290   {
03291     case TIM_CHANNEL_1:
03292     {
03293       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03294       break;
03295     }
03296
03297     case TIM_CHANNEL_2:
03298     {
03299       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03300       break;
03301     }
03302
03303     default :
03304     {
03305       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03306       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03307       break;
03308     }
03309   }
03310   /* Enable the Peripheral */
03311   __HAL_TIM_ENABLE(htim);
03312
03313   /* Return function status */
03314   return HAL_OK;
03315 }
03316
03317 /**
03318   * @brief  Stops the TIM Encoder Interface.
03319   * @param  htim TIM Encoder Interface handle
03320   * @param  Channel TIM Channels to be disabled
03321   *          This parameter can be one of the following values:
03322   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03323   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03324   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03325   * @retval HAL status
03326   */
03327 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
03328 {
03329   /* Check the parameters */
03330   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03331
03332   /* Disable the Input Capture channels 1 and 2
03333     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
03334   switch (Channel)
03335   {
03336     case TIM_CHANNEL_1:
03337     {
03338       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03339       break;
03340     }
03341
03342     case TIM_CHANNEL_2:
03343     {
03344       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03345       break;
03346     }
03347
03348     default :
03349     {
03350       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03351       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03352       break;
03353     }
03354   }
03355
03356   /* Disable the Peripheral */
03357   __HAL_TIM_DISABLE(htim);
03358
03359   /* Set the TIM channel(s) state */
03360   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
03361   {
03362     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03363     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03364   }
03365   else
03366   {
03367     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03368     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03369     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03370     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03371   }
03372
03373   /* Return function status */
03374   return HAL_OK;
03375 }
03376
03377 /**
03378   * @brief  Starts the TIM Encoder Interface in interrupt mode.
03379   * @param  htim TIM Encoder Interface handle
03380   * @param  Channel TIM Channels to be enabled
03381   *          This parameter can be one of the following values:
03382   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03383   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03384   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03385   * @retval HAL status
03386   */
03387 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
03388 {
03389   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
03390   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
03391   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
03392   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
03393
03394   /* Check the parameters */
03395   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03396
03397   /* Set the TIM channel(s) state */
03398   if (Channel == TIM_CHANNEL_1)
03399   {
03400     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03401         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
03402     {
03403       return HAL_ERROR;
03404     }
03405     else
03406     {
03407       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03408       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03409     }
03410   }
03411   else if (Channel == TIM_CHANNEL_2)
03412   {
03413     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
03414         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
03415     {
03416       return HAL_ERROR;
03417     }
03418     else
03419     {
03420       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03421       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03422     }
03423   }
03424   else
03425   {
03426     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03427         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
03428         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
03429         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
03430     {
03431       return HAL_ERROR;
03432     }
03433     else
03434     {
03435       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03436       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03437       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03438       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03439     }
03440   }
03441
03442   /* Enable the encoder interface channels */
03443   /* Enable the capture compare Interrupts 1 and/or 2 */
03444   switch (Channel)
03445   {
03446     case TIM_CHANNEL_1:
03447     {
03448       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03449       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
03450       break;
03451     }
03452
03453     case TIM_CHANNEL_2:
03454     {
03455       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03456       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
03457       break;
03458     }
03459
03460     default :
03461     {
03462       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03463       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03464       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
03465       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
03466       break;
03467     }
03468   }
03469
03470   /* Enable the Peripheral */
03471   __HAL_TIM_ENABLE(htim);
03472
03473   /* Return function status */
03474   return HAL_OK;
03475 }
03476
03477 /**
03478   * @brief  Stops the TIM Encoder Interface in interrupt mode.
03479   * @param  htim TIM Encoder Interface handle
03480   * @param  Channel TIM Channels to be disabled
03481   *          This parameter can be one of the following values:
03482   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03483   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03484   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03485   * @retval HAL status
03486   */
03487 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
03488 {
03489   /* Check the parameters */
03490   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03491
03492   /* Disable the Input Capture channels 1 and 2
03493     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
03494   if (Channel == TIM_CHANNEL_1)
03495   {
03496     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03497
03498     /* Disable the capture compare Interrupts 1 */
03499     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
03500   }
03501   else if (Channel == TIM_CHANNEL_2)
03502   {
03503     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03504
03505     /* Disable the capture compare Interrupts 2 */
03506     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
03507   }
03508   else
03509   {
03510     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03511     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03512
03513     /* Disable the capture compare Interrupts 1 and 2 */
03514     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
03515     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
03516   }
03517
03518   /* Disable the Peripheral */
03519   __HAL_TIM_DISABLE(htim);
03520
03521   /* Set the TIM channel(s) state */
03522   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
03523   {
03524     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03525     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03526   }
03527   else
03528   {
03529     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03530     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03531     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03532     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03533   }
03534
03535   /* Return function status */
03536   return HAL_OK;
03537 }
03538
03539 /**
03540   * @brief  Starts the TIM Encoder Interface in DMA mode.
03541   * @param  htim TIM Encoder Interface handle
03542   * @param  Channel TIM Channels to be enabled
03543   *          This parameter can be one of the following values:
03544   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03545   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03546   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03547   * @param  pData1 The destination Buffer address for IC1.
03548   * @param  pData2 The destination Buffer address for IC2.
03549   * @param  Length The length of data to be transferred from TIM peripheral to memory.
03550   * @retval HAL status
03551   */
03552 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
03553                                             uint32_t *pData2, uint16_t Length)
03554 {
03555   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
03556   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
03557   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
03558   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
03559
03560   /* Check the parameters */
03561   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03562
03563   /* Set the TIM channel(s) state */
03564   if (Channel == TIM_CHANNEL_1)
03565   {
03566     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
03567         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
03568     {
03569       return HAL_BUSY;
03570     }
03571     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
03572              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
03573     {
03574       if ((pData1 == NULL) || (Length == 0U))
03575       {
03576         return HAL_ERROR;
03577       }
03578       else
03579       {
03580         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03581         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03582       }
03583     }
03584     else
03585     {
03586       return HAL_ERROR;
03587     }
03588   }
03589   else if (Channel == TIM_CHANNEL_2)
03590   {
03591     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
03592         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
03593     {
03594       return HAL_BUSY;
03595     }
03596     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
03597              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
03598     {
03599       if ((pData2 == NULL) || (Length == 0U))
03600       {
03601         return HAL_ERROR;
03602       }
03603       else
03604       {
03605         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03606         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03607       }
03608     }
03609     else
03610     {
03611       return HAL_ERROR;
03612     }
03613   }
03614   else
03615   {
03616     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
03617         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
03618         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
03619         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
03620     {
03621       return HAL_BUSY;
03622     }
03623     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
03624              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
03625              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
03626              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
03627     {
03628       if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
03629       {
03630         return HAL_ERROR;
03631       }
03632       else
03633       {
03634         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03635         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03636         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
03637         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
03638       }
03639     }
03640     else
03641     {
03642       return HAL_ERROR;
03643     }
03644   }
03645
03646   switch (Channel)
03647   {
03648     case TIM_CHANNEL_1:
03649     {
03650       /* Set the DMA capture callbacks */
03651       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03652       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03653
03654       /* Set the DMA error callback */
03655       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03656
03657       /* Enable the DMA channel */
03658       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
03659                            Length) != HAL_OK)
03660       {
03661         /* Return error status */
03662         return HAL_ERROR;
03663       }
03664       /* Enable the TIM Input Capture DMA request */
03665       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
03666
03667       /* Enable the Capture compare channel */
03668       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03669
03670       /* Enable the Peripheral */
03671       __HAL_TIM_ENABLE(htim);
03672
03673       break;
03674     }
03675
03676     case TIM_CHANNEL_2:
03677     {
03678       /* Set the DMA capture callbacks */
03679       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03680       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03681
03682       /* Set the DMA error callback */
03683       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
03684       /* Enable the DMA channel */
03685       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
03686                            Length) != HAL_OK)
03687       {
03688         /* Return error status */
03689         return HAL_ERROR;
03690       }
03691       /* Enable the TIM Input Capture  DMA request */
03692       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
03693
03694       /* Enable the Capture compare channel */
03695       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03696
03697       /* Enable the Peripheral */
03698       __HAL_TIM_ENABLE(htim);
03699
03700       break;
03701     }
03702
03703     default:
03704     {
03705       /* Set the DMA capture callbacks */
03706       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03707       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03708
03709       /* Set the DMA error callback */
03710       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03711
03712       /* Enable the DMA channel */
03713       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
03714                            Length) != HAL_OK)
03715       {
03716         /* Return error status */
03717         return HAL_ERROR;
03718       }
03719
03720       /* Set the DMA capture callbacks */
03721       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03722       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03723
03724       /* Set the DMA error callback */
03725       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03726
03727       /* Enable the DMA channel */
03728       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
03729                            Length) != HAL_OK)
03730       {
03731         /* Return error status */
03732         return HAL_ERROR;
03733       }
03734
03735       /* Enable the TIM Input Capture  DMA request */
03736       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
03737       /* Enable the TIM Input Capture  DMA request */
03738       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
03739
03740       /* Enable the Capture compare channel */
03741       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03742       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03743
03744       /* Enable the Peripheral */
03745       __HAL_TIM_ENABLE(htim);
03746
03747       break;
03748     }
03749   }
03750
03751   /* Return function status */
03752   return HAL_OK;
03753 }
03754
03755 /**
03756   * @brief  Stops the TIM Encoder Interface in DMA mode.
03757   * @param  htim TIM Encoder Interface handle
03758   * @param  Channel TIM Channels to be enabled
03759   *          This parameter can be one of the following values:
03760   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03761   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03762   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03763   * @retval HAL status
03764   */
03765 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
03766 {
03767   /* Check the parameters */
03768   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
03769
03770   /* Disable the Input Capture channels 1 and 2
03771     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
03772   if (Channel == TIM_CHANNEL_1)
03773   {
03774     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03775
03776     /* Disable the capture compare DMA Request 1 */
03777     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
03778     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
03779   }
03780   else if (Channel == TIM_CHANNEL_2)
03781   {
03782     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03783
03784     /* Disable the capture compare DMA Request 2 */
03785     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
03786     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
03787   }
03788   else
03789   {
03790     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03791     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03792
03793     /* Disable the capture compare DMA Request 1 and 2 */
03794     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
03795     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
03796     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
03797     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
03798   }
03799
03800   /* Disable the Peripheral */
03801   __HAL_TIM_DISABLE(htim);
03802
03803   /* Set the TIM channel(s) state */
03804   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
03805   {
03806     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03807     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
03808   }
03809   else
03810   {
03811     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03812     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03813     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
03814     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
03815   }
03816
03817   /* Return function status */
03818   return HAL_OK;
03819 }
03820
03821 /**
03822   * @}
03823   */
03824 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
03825   *  @brief    TIM IRQ handler management
03826   *
03827 @verbatim
03828   ==============================================================================
03829                         ##### IRQ handler management #####
03830   ==============================================================================
03831   [..]
03832     This section provides Timer IRQ handler function.
03833
03834 @endverbatim
03835   * @{
03836   */
03837 /**
03838   * @brief  This function handles TIM interrupts requests.
03839   * @param  htim TIM  handle
03840   * @retval None
03841   */
03842 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
03843 {
03844   /* Capture compare 1 event */
03845   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
03846   {
03847     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
03848     {
03849       {
03850         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
03851         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
03852
03853         /* Input capture event */
03854         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
03855         {
03856 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03857           htim->IC_CaptureCallback(htim);
03858 #else
03859           HAL_TIM_IC_CaptureCallback(htim);
03860 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03861         }
03862         /* Output compare event */
03863         else
03864         {
03865 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03866           htim->OC_DelayElapsedCallback(htim);
03867           htim->PWM_PulseFinishedCallback(htim);
03868 #else
03869           HAL_TIM_OC_DelayElapsedCallback(htim);
03870           HAL_TIM_PWM_PulseFinishedCallback(htim);
03871 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03872         }
03873         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03874       }
03875     }
03876   }
03877   /* Capture compare 2 event */
03878   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
03879   {
03880     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
03881     {
03882       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
03883       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
03884       /* Input capture event */
03885       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
03886       {
03887 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03888         htim->IC_CaptureCallback(htim);
03889 #else
03890         HAL_TIM_IC_CaptureCallback(htim);
03891 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03892       }
03893       /* Output compare event */
03894       else
03895       {
03896 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03897         htim->OC_DelayElapsedCallback(htim);
03898         htim->PWM_PulseFinishedCallback(htim);
03899 #else
03900         HAL_TIM_OC_DelayElapsedCallback(htim);
03901         HAL_TIM_PWM_PulseFinishedCallback(htim);
03902 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03903       }
03904       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03905     }
03906   }
03907   /* Capture compare 3 event */
03908   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
03909   {
03910     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
03911     {
03912       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
03913       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
03914       /* Input capture event */
03915       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
03916       {
03917 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03918         htim->IC_CaptureCallback(htim);
03919 #else
03920         HAL_TIM_IC_CaptureCallback(htim);
03921 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03922       }
03923       /* Output compare event */
03924       else
03925       {
03926 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03927         htim->OC_DelayElapsedCallback(htim);
03928         htim->PWM_PulseFinishedCallback(htim);
03929 #else
03930         HAL_TIM_OC_DelayElapsedCallback(htim);
03931         HAL_TIM_PWM_PulseFinishedCallback(htim);
03932 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03933       }
03934       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03935     }
03936   }
03937   /* Capture compare 4 event */
03938   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
03939   {
03940     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
03941     {
03942       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
03943       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
03944       /* Input capture event */
03945       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
03946       {
03947 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03948         htim->IC_CaptureCallback(htim);
03949 #else
03950         HAL_TIM_IC_CaptureCallback(htim);
03951 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03952       }
03953       /* Output compare event */
03954       else
03955       {
03956 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03957         htim->OC_DelayElapsedCallback(htim);
03958         htim->PWM_PulseFinishedCallback(htim);
03959 #else
03960         HAL_TIM_OC_DelayElapsedCallback(htim);
03961         HAL_TIM_PWM_PulseFinishedCallback(htim);
03962 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03963       }
03964       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03965     }
03966   }
03967   /* TIM Update event */
03968   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
03969   {
03970     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
03971     {
03972       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
03973 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03974       htim->PeriodElapsedCallback(htim);
03975 #else
03976       HAL_TIM_PeriodElapsedCallback(htim);
03977 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03978     }
03979   }
03980   /* TIM Break input event */
03981   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
03982   {
03983     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
03984     {
03985       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
03986 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03987       htim->BreakCallback(htim);
03988 #else
03989       HAL_TIMEx_BreakCallback(htim);
03990 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03991     }
03992   }
03993   /* TIM Break2 input event */
03994   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
03995   {
03996     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
03997     {
03998       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
03999 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04000       htim->Break2Callback(htim);
04001 #else
04002       HAL_TIMEx_Break2Callback(htim);
04003 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04004     }
04005   }
04006   /* TIM Trigger detection event */
04007   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
04008   {
04009     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
04010     {
04011       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
04012 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04013       htim->TriggerCallback(htim);
04014 #else
04015       HAL_TIM_TriggerCallback(htim);
04016 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04017     }
04018   }
04019   /* TIM commutation event */
04020   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
04021   {
04022     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
04023     {
04024       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
04025 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
04026       htim->CommutationCallback(htim);
04027 #else
04028       HAL_TIMEx_CommutCallback(htim);
04029 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
04030     }
04031   }
04032 }
04033
04034 /**
04035   * @}
04036   */
04037
04038 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
04039   *  @brief    TIM Peripheral Control functions
04040   *
04041 @verbatim
04042   ==============================================================================
04043                    ##### Peripheral Control functions #####
04044   ==============================================================================
04045  [..]
04046    This section provides functions allowing to:
04047       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
04048       (+) Configure External Clock source.
04049       (+) Configure Complementary channels, break features and dead time.
04050       (+) Configure Master and the Slave synchronization.
04051       (+) Configure the DMA Burst Mode.
04052
04053 @endverbatim
04054   * @{
04055   */
04056
04057 /**
04058   * @brief  Initializes the TIM Output Compare Channels according to the specified
04059   *         parameters in the TIM_OC_InitTypeDef.
04060   * @param  htim TIM Output Compare handle
04061   * @param  sConfig TIM Output Compare configuration structure
04062   * @param  Channel TIM Channels to configure
04063   *          This parameter can be one of the following values:
04064   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04065   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04066   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04067   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04068   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
04069   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
04070   * @retval HAL status
04071   */
04072 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
04073                                            const TIM_OC_InitTypeDef *sConfig,
04074                                            uint32_t Channel)
04075 {
04076   HAL_StatusTypeDef status = HAL_OK;
04077
04078   /* Check the parameters */
04079   assert_param(IS_TIM_CHANNELS(Channel));
04080   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
04081   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
04082
04083   /* Process Locked */
04084   __HAL_LOCK(htim);
04085
04086   switch (Channel)
04087   {
04088     case TIM_CHANNEL_1:
04089     {
04090       /* Check the parameters */
04091       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04092
04093       /* Configure the TIM Channel 1 in Output Compare */
04094       TIM_OC1_SetConfig(htim->Instance, sConfig);
04095       break;
04096     }
04097
04098     case TIM_CHANNEL_2:
04099     {
04100       /* Check the parameters */
04101       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04102
04103       /* Configure the TIM Channel 2 in Output Compare */
04104       TIM_OC2_SetConfig(htim->Instance, sConfig);
04105       break;
04106     }
04107
04108     case TIM_CHANNEL_3:
04109     {
04110       /* Check the parameters */
04111       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04112
04113       /* Configure the TIM Channel 3 in Output Compare */
04114       TIM_OC3_SetConfig(htim->Instance, sConfig);
04115       break;
04116     }
04117
04118     case TIM_CHANNEL_4:
04119     {
04120       /* Check the parameters */
04121       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04122
04123       /* Configure the TIM Channel 4 in Output Compare */
04124       TIM_OC4_SetConfig(htim->Instance, sConfig);
04125       break;
04126     }
04127
04128     case TIM_CHANNEL_5:
04129     {
04130       /* Check the parameters */
04131       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
04132
04133       /* Configure the TIM Channel 5 in Output Compare */
04134       TIM_OC5_SetConfig(htim->Instance, sConfig);
04135       break;
04136     }
04137
04138     case TIM_CHANNEL_6:
04139     {
04140       /* Check the parameters */
04141       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
04142
04143       /* Configure the TIM Channel 6 in Output Compare */
04144       TIM_OC6_SetConfig(htim->Instance, sConfig);
04145       break;
04146     }
04147
04148     default:
04149       status = HAL_ERROR;
04150       break;
04151   }
04152
04153   __HAL_UNLOCK(htim);
04154
04155   return status;
04156 }
04157
04158 /**
04159   * @brief  Initializes the TIM Input Capture Channels according to the specified
04160   *         parameters in the TIM_IC_InitTypeDef.
04161   * @param  htim TIM IC handle
04162   * @param  sConfig TIM Input Capture configuration structure
04163   * @param  Channel TIM Channel to configure
04164   *          This parameter can be one of the following values:
04165   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04166   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04167   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04168   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04169   * @retval HAL status
04170   */
04171 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
04172 {
04173   HAL_StatusTypeDef status = HAL_OK;
04174
04175   /* Check the parameters */
04176   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04177   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
04178   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
04179   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
04180   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
04181
04182   /* Process Locked */
04183   __HAL_LOCK(htim);
04184
04185   if (Channel == TIM_CHANNEL_1)
04186   {
04187     /* TI1 Configuration */
04188     TIM_TI1_SetConfig(htim->Instance,
04189                       sConfig->ICPolarity,
04190                       sConfig->ICSelection,
04191                       sConfig->ICFilter);
04192
04193     /* Reset the IC1PSC Bits */
04194     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
04195
04196     /* Set the IC1PSC value */
04197     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
04198   }
04199   else if (Channel == TIM_CHANNEL_2)
04200   {
04201     /* TI2 Configuration */
04202     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04203
04204     TIM_TI2_SetConfig(htim->Instance,
04205                       sConfig->ICPolarity,
04206                       sConfig->ICSelection,
04207                       sConfig->ICFilter);
04208
04209     /* Reset the IC2PSC Bits */
04210     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
04211
04212     /* Set the IC2PSC value */
04213     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
04214   }
04215   else if (Channel == TIM_CHANNEL_3)
04216   {
04217     /* TI3 Configuration */
04218     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04219
04220     TIM_TI3_SetConfig(htim->Instance,
04221                       sConfig->ICPolarity,
04222                       sConfig->ICSelection,
04223                       sConfig->ICFilter);
04224
04225     /* Reset the IC3PSC Bits */
04226     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
04227
04228     /* Set the IC3PSC value */
04229     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
04230   }
04231   else if (Channel == TIM_CHANNEL_4)
04232   {
04233     /* TI4 Configuration */
04234     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04235
04236     TIM_TI4_SetConfig(htim->Instance,
04237                       sConfig->ICPolarity,
04238                       sConfig->ICSelection,
04239                       sConfig->ICFilter);
04240
04241     /* Reset the IC4PSC Bits */
04242     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
04243
04244     /* Set the IC4PSC value */
04245     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
04246   }
04247   else
04248   {
04249     status = HAL_ERROR;
04250   }
04251
04252   __HAL_UNLOCK(htim);
04253
04254   return status;
04255 }
04256
04257 /**
04258   * @brief  Initializes the TIM PWM  channels according to the specified
04259   *         parameters in the TIM_OC_InitTypeDef.
04260   * @param  htim TIM PWM handle
04261   * @param  sConfig TIM PWM configuration structure
04262   * @param  Channel TIM Channels to be configured
04263   *          This parameter can be one of the following values:
04264   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04265   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04266   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04267   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04268   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
04269   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
04270   * @retval HAL status
04271   */
04272 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
04273                                             const TIM_OC_InitTypeDef *sConfig,
04274                                             uint32_t Channel)
04275 {
04276   HAL_StatusTypeDef status = HAL_OK;
04277
04278   /* Check the parameters */
04279   assert_param(IS_TIM_CHANNELS(Channel));
04280   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
04281   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
04282   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
04283
04284   /* Process Locked */
04285   __HAL_LOCK(htim);
04286
04287   switch (Channel)
04288   {
04289     case TIM_CHANNEL_1:
04290     {
04291       /* Check the parameters */
04292       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04293
04294       /* Configure the Channel 1 in PWM mode */
04295       TIM_OC1_SetConfig(htim->Instance, sConfig);
04296
04297       /* Set the Preload enable bit for channel1 */
04298       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
04299
04300       /* Configure the Output Fast mode */
04301       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
04302       htim->Instance->CCMR1 |= sConfig->OCFastMode;
04303       break;
04304     }
04305
04306     case TIM_CHANNEL_2:
04307     {
04308       /* Check the parameters */
04309       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04310
04311       /* Configure the Channel 2 in PWM mode */
04312       TIM_OC2_SetConfig(htim->Instance, sConfig);
04313
04314       /* Set the Preload enable bit for channel2 */
04315       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
04316
04317       /* Configure the Output Fast mode */
04318       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
04319       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
04320       break;
04321     }
04322
04323     case TIM_CHANNEL_3:
04324     {
04325       /* Check the parameters */
04326       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04327
04328       /* Configure the Channel 3 in PWM mode */
04329       TIM_OC3_SetConfig(htim->Instance, sConfig);
04330
04331       /* Set the Preload enable bit for channel3 */
04332       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
04333
04334       /* Configure the Output Fast mode */
04335       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
04336       htim->Instance->CCMR2 |= sConfig->OCFastMode;
04337       break;
04338     }
04339
04340     case TIM_CHANNEL_4:
04341     {
04342       /* Check the parameters */
04343       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04344
04345       /* Configure the Channel 4 in PWM mode */
04346       TIM_OC4_SetConfig(htim->Instance, sConfig);
04347
04348       /* Set the Preload enable bit for channel4 */
04349       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
04350
04351       /* Configure the Output Fast mode */
04352       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
04353       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
04354       break;
04355     }
04356
04357     case TIM_CHANNEL_5:
04358     {
04359       /* Check the parameters */
04360       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
04361
04362       /* Configure the Channel 5 in PWM mode */
04363       TIM_OC5_SetConfig(htim->Instance, sConfig);
04364
04365       /* Set the Preload enable bit for channel5*/
04366       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
04367
04368       /* Configure the Output Fast mode */
04369       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
04370       htim->Instance->CCMR3 |= sConfig->OCFastMode;
04371       break;
04372     }
04373
04374     case TIM_CHANNEL_6:
04375     {
04376       /* Check the parameters */
04377       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
04378
04379       /* Configure the Channel 6 in PWM mode */
04380       TIM_OC6_SetConfig(htim->Instance, sConfig);
04381
04382       /* Set the Preload enable bit for channel6 */
04383       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
04384
04385       /* Configure the Output Fast mode */
04386       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
04387       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
04388       break;
04389     }
04390
04391     default:
04392       status = HAL_ERROR;
04393       break;
04394   }
04395
04396   __HAL_UNLOCK(htim);
04397
04398   return status;
04399 }
04400
04401 /**
04402   * @brief  Initializes the TIM One Pulse Channels according to the specified
04403   *         parameters in the TIM_OnePulse_InitTypeDef.
04404   * @param  htim TIM One Pulse handle
04405   * @param  sConfig TIM One Pulse configuration structure
04406   * @param  OutputChannel TIM output channel to configure
04407   *          This parameter can be one of the following values:
04408   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04409   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04410   * @param  InputChannel TIM input Channel to configure
04411   *          This parameter can be one of the following values:
04412   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04413   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04414   * @note  To output a waveform with a minimum delay user can enable the fast
04415   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
04416   *        output is forced in response to the edge detection on TIx input,
04417   *        without taking in account the comparison.
04418   * @retval HAL status
04419   */
04420 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
04421                                                  uint32_t OutputChannel,  uint32_t InputChannel)
04422 {
04423   HAL_StatusTypeDef status = HAL_OK;
04424   TIM_OC_InitTypeDef temp1;
04425
04426   /* Check the parameters */
04427   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
04428   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
04429
04430   if (OutputChannel != InputChannel)
04431   {
04432     /* Process Locked */
04433     __HAL_LOCK(htim);
04434
04435     htim->State = HAL_TIM_STATE_BUSY;
04436
04437     /* Extract the Output compare configuration from sConfig structure */
04438     temp1.OCMode = sConfig->OCMode;
04439     temp1.Pulse = sConfig->Pulse;
04440     temp1.OCPolarity = sConfig->OCPolarity;
04441     temp1.OCNPolarity = sConfig->OCNPolarity;
04442     temp1.OCIdleState = sConfig->OCIdleState;
04443     temp1.OCNIdleState = sConfig->OCNIdleState;
04444
04445     switch (OutputChannel)
04446     {
04447       case TIM_CHANNEL_1:
04448       {
04449         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04450
04451         TIM_OC1_SetConfig(htim->Instance, &temp1);
04452         break;
04453       }
04454
04455       case TIM_CHANNEL_2:
04456       {
04457         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04458
04459         TIM_OC2_SetConfig(htim->Instance, &temp1);
04460         break;
04461       }
04462
04463       default:
04464         status = HAL_ERROR;
04465         break;
04466     }
04467
04468     if (status == HAL_OK)
04469     {
04470       switch (InputChannel)
04471       {
04472         case TIM_CHANNEL_1:
04473         {
04474           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04475
04476           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
04477                             sConfig->ICSelection, sConfig->ICFilter);
04478
04479           /* Reset the IC1PSC Bits */
04480           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
04481
04482           /* Select the Trigger source */
04483           htim->Instance->SMCR &= ~TIM_SMCR_TS;
04484           htim->Instance->SMCR |= TIM_TS_TI1FP1;
04485
04486           /* Select the Slave Mode */
04487           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
04488           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
04489           break;
04490         }
04491
04492         case TIM_CHANNEL_2:
04493         {
04494           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04495
04496           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
04497                             sConfig->ICSelection, sConfig->ICFilter);
04498
04499           /* Reset the IC2PSC Bits */
04500           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
04501
04502           /* Select the Trigger source */
04503           htim->Instance->SMCR &= ~TIM_SMCR_TS;
04504           htim->Instance->SMCR |= TIM_TS_TI2FP2;
04505
04506           /* Select the Slave Mode */
04507           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
04508           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
04509           break;
04510         }
04511
04512         default:
04513           status = HAL_ERROR;
04514           break;
04515       }
04516     }
04517
04518     htim->State = HAL_TIM_STATE_READY;
04519
04520     __HAL_UNLOCK(htim);
04521
04522     return status;
04523   }
04524   else
04525   {
04526     return HAL_ERROR;
04527   }
04528 }
04529
04530 /**
04531   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
04532   * @param  htim TIM handle
04533   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
04534   *         This parameter can be one of the following values:
04535   *            @arg TIM_DMABASE_CR1
04536   *            @arg TIM_DMABASE_CR2
04537   *            @arg TIM_DMABASE_SMCR
04538   *            @arg TIM_DMABASE_DIER
04539   *            @arg TIM_DMABASE_SR
04540   *            @arg TIM_DMABASE_EGR
04541   *            @arg TIM_DMABASE_CCMR1
04542   *            @arg TIM_DMABASE_CCMR2
04543   *            @arg TIM_DMABASE_CCER
04544   *            @arg TIM_DMABASE_CNT
04545   *            @arg TIM_DMABASE_PSC
04546   *            @arg TIM_DMABASE_ARR
04547   *            @arg TIM_DMABASE_RCR
04548   *            @arg TIM_DMABASE_CCR1
04549   *            @arg TIM_DMABASE_CCR2
04550   *            @arg TIM_DMABASE_CCR3
04551   *            @arg TIM_DMABASE_CCR4
04552   *            @arg TIM_DMABASE_BDTR
04553   *            @arg TIM_DMABASE_OR1
04554   *            @arg TIM_DMABASE_CCMR3
04555   *            @arg TIM_DMABASE_CCR5
04556   *            @arg TIM_DMABASE_CCR6
04557   *            @arg TIM_DMABASE_AF1
04558   *            @arg TIM_DMABASE_AF2
04559   *            @arg TIM_DMABASE_TISEL
04560   * @param  BurstRequestSrc TIM DMA Request sources
04561   *         This parameter can be one of the following values:
04562   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04563   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04564   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04565   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04566   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04567   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04568   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04569   * @param  BurstBuffer The Buffer address.
04570   * @param  BurstLength DMA Burst length. This parameter can be one value
04571   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
04572   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
04573   * @retval HAL status
04574   */
04575 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04576                                               uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t  BurstLength)
04577 {
04578   HAL_StatusTypeDef status;
04579
04580   status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
04581                                             ((BurstLength) >> 8U) + 1U);
04582
04583
04584
04585   return status;
04586 }
04587
04588 /**
04589   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
04590   * @param  htim TIM handle
04591   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
04592   *         This parameter can be one of the following values:
04593   *            @arg TIM_DMABASE_CR1
04594   *            @arg TIM_DMABASE_CR2
04595   *            @arg TIM_DMABASE_SMCR
04596   *            @arg TIM_DMABASE_DIER
04597   *            @arg TIM_DMABASE_SR
04598   *            @arg TIM_DMABASE_EGR
04599   *            @arg TIM_DMABASE_CCMR1
04600   *            @arg TIM_DMABASE_CCMR2
04601   *            @arg TIM_DMABASE_CCER
04602   *            @arg TIM_DMABASE_CNT
04603   *            @arg TIM_DMABASE_PSC
04604   *            @arg TIM_DMABASE_ARR
04605   *            @arg TIM_DMABASE_RCR
04606   *            @arg TIM_DMABASE_CCR1
04607   *            @arg TIM_DMABASE_CCR2
04608   *            @arg TIM_DMABASE_CCR3
04609   *            @arg TIM_DMABASE_CCR4
04610   *            @arg TIM_DMABASE_BDTR
04611   *            @arg TIM_DMABASE_OR1
04612   *            @arg TIM_DMABASE_CCMR3
04613   *            @arg TIM_DMABASE_CCR5
04614   *            @arg TIM_DMABASE_CCR6
04615   *            @arg TIM_DMABASE_AF1
04616   *            @arg TIM_DMABASE_AF2
04617   *            @arg TIM_DMABASE_TISEL
04618   * @param  BurstRequestSrc TIM DMA Request sources
04619   *         This parameter can be one of the following values:
04620   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04621   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04622   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04623   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04624   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04625   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04626   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04627   * @param  BurstBuffer The Buffer address.
04628   * @param  BurstLength DMA Burst length. This parameter can be one value
04629   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
04630   * @param  DataLength Data length. This parameter can be one value
04631   *         between 1 and 0xFFFF.
04632   * @retval HAL status
04633   */
04634 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04635                                                    uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
04636                                                    uint32_t  BurstLength,  uint32_t  DataLength)
04637 {
04638   HAL_StatusTypeDef status = HAL_OK;
04639
04640   /* Check the parameters */
04641   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
04642   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
04643   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04644   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
04645   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
04646
04647   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
04648   {
04649     return HAL_BUSY;
04650   }
04651   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
04652   {
04653     if ((BurstBuffer == NULL) && (BurstLength > 0U))
04654     {
04655       return HAL_ERROR;
04656     }
04657     else
04658     {
04659       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
04660     }
04661   }
04662   else
04663   {
04664     /* nothing to do */
04665   }
04666
04667   switch (BurstRequestSrc)
04668   {
04669     case TIM_DMA_UPDATE:
04670     {
04671       /* Set the DMA Period elapsed callbacks */
04672       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
04673       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
04674
04675       /* Set the DMA error callback */
04676       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
04677
04678       /* Enable the DMA channel */
04679       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
04680                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04681       {
04682         /* Return error status */
04683         return HAL_ERROR;
04684       }
04685       break;
04686     }
04687     case TIM_DMA_CC1:
04688     {
04689       /* Set the DMA compare callbacks */
04690       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
04691       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04692
04693       /* Set the DMA error callback */
04694       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
04695
04696       /* Enable the DMA channel */
04697       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
04698                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04699       {
04700         /* Return error status */
04701         return HAL_ERROR;
04702       }
04703       break;
04704     }
04705     case TIM_DMA_CC2:
04706     {
04707       /* Set the DMA compare callbacks */
04708       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
04709       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04710
04711       /* Set the DMA error callback */
04712       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
04713
04714       /* Enable the DMA channel */
04715       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
04716                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04717       {
04718         /* Return error status */
04719         return HAL_ERROR;
04720       }
04721       break;
04722     }
04723     case TIM_DMA_CC3:
04724     {
04725       /* Set the DMA compare callbacks */
04726       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
04727       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04728
04729       /* Set the DMA error callback */
04730       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
04731
04732       /* Enable the DMA channel */
04733       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
04734                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04735       {
04736         /* Return error status */
04737         return HAL_ERROR;
04738       }
04739       break;
04740     }
04741     case TIM_DMA_CC4:
04742     {
04743       /* Set the DMA compare callbacks */
04744       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
04745       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04746
04747       /* Set the DMA error callback */
04748       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
04749
04750       /* Enable the DMA channel */
04751       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
04752                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04753       {
04754         /* Return error status */
04755         return HAL_ERROR;
04756       }
04757       break;
04758     }
04759     case TIM_DMA_COM:
04760     {
04761       /* Set the DMA commutation callbacks */
04762       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
04763       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
04764
04765       /* Set the DMA error callback */
04766       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
04767
04768       /* Enable the DMA channel */
04769       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
04770                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04771       {
04772         /* Return error status */
04773         return HAL_ERROR;
04774       }
04775       break;
04776     }
04777     case TIM_DMA_TRIGGER:
04778     {
04779       /* Set the DMA trigger callbacks */
04780       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
04781       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
04782
04783       /* Set the DMA error callback */
04784       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
04785
04786       /* Enable the DMA channel */
04787       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
04788                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
04789       {
04790         /* Return error status */
04791         return HAL_ERROR;
04792       }
04793       break;
04794     }
04795     default:
04796       status = HAL_ERROR;
04797       break;
04798   }
04799
04800   if (status == HAL_OK)
04801   {
04802     /* Configure the DMA Burst Mode */
04803     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
04804     /* Enable the TIM DMA Request */
04805     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
04806   }
04807
04808   /* Return function status */
04809   return status;
04810 }
04811
04812 /**
04813   * @brief  Stops the TIM DMA Burst mode
04814   * @param  htim TIM handle
04815   * @param  BurstRequestSrc TIM DMA Request sources to disable
04816   * @retval HAL status
04817   */
04818 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
04819 {
04820   HAL_StatusTypeDef status = HAL_OK;
04821
04822   /* Check the parameters */
04823   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04824
04825   /* Abort the DMA transfer (at least disable the DMA channel) */
04826   switch (BurstRequestSrc)
04827   {
04828     case TIM_DMA_UPDATE:
04829     {
04830       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
04831       break;
04832     }
04833     case TIM_DMA_CC1:
04834     {
04835       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
04836       break;
04837     }
04838     case TIM_DMA_CC2:
04839     {
04840       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
04841       break;
04842     }
04843     case TIM_DMA_CC3:
04844     {
04845       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
04846       break;
04847     }
04848     case TIM_DMA_CC4:
04849     {
04850       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
04851       break;
04852     }
04853     case TIM_DMA_COM:
04854     {
04855       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
04856       break;
04857     }
04858     case TIM_DMA_TRIGGER:
04859     {
04860       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
04861       break;
04862     }
04863     default:
04864       status = HAL_ERROR;
04865       break;
04866   }
04867
04868   if (status == HAL_OK)
04869   {
04870     /* Disable the TIM Update DMA request */
04871     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
04872
04873     /* Change the DMA burst operation state */
04874     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
04875   }
04876
04877   /* Return function status */
04878   return status;
04879 }
04880
04881 /**
04882   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
04883   * @param  htim TIM handle
04884   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
04885   *         This parameter can be one of the following values:
04886   *            @arg TIM_DMABASE_CR1
04887   *            @arg TIM_DMABASE_CR2
04888   *            @arg TIM_DMABASE_SMCR
04889   *            @arg TIM_DMABASE_DIER
04890   *            @arg TIM_DMABASE_SR
04891   *            @arg TIM_DMABASE_EGR
04892   *            @arg TIM_DMABASE_CCMR1
04893   *            @arg TIM_DMABASE_CCMR2
04894   *            @arg TIM_DMABASE_CCER
04895   *            @arg TIM_DMABASE_CNT
04896   *            @arg TIM_DMABASE_PSC
04897   *            @arg TIM_DMABASE_ARR
04898   *            @arg TIM_DMABASE_RCR
04899   *            @arg TIM_DMABASE_CCR1
04900   *            @arg TIM_DMABASE_CCR2
04901   *            @arg TIM_DMABASE_CCR3
04902   *            @arg TIM_DMABASE_CCR4
04903   *            @arg TIM_DMABASE_BDTR
04904   *            @arg TIM_DMABASE_OR1
04905   *            @arg TIM_DMABASE_CCMR3
04906   *            @arg TIM_DMABASE_CCR5
04907   *            @arg TIM_DMABASE_CCR6
04908   *            @arg TIM_DMABASE_AF1
04909   *            @arg TIM_DMABASE_AF2
04910   *            @arg TIM_DMABASE_TISEL
04911   * @param  BurstRequestSrc TIM DMA Request sources
04912   *         This parameter can be one of the following values:
04913   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04914   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04915   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04916   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04917   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04918   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04919   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04920   * @param  BurstBuffer The Buffer address.
04921   * @param  BurstLength DMA Burst length. This parameter can be one value
04922   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
04923   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
04924   * @retval HAL status
04925   */
04926 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04927                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
04928 {
04929   HAL_StatusTypeDef status;
04930
04931   status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
04932                                            ((BurstLength) >> 8U) + 1U);
04933
04934
04935   return status;
04936 }
04937
04938 /**
04939   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
04940   * @param  htim TIM handle
04941   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
04942   *         This parameter can be one of the following values:
04943   *            @arg TIM_DMABASE_CR1
04944   *            @arg TIM_DMABASE_CR2
04945   *            @arg TIM_DMABASE_SMCR
04946   *            @arg TIM_DMABASE_DIER
04947   *            @arg TIM_DMABASE_SR
04948   *            @arg TIM_DMABASE_EGR
04949   *            @arg TIM_DMABASE_CCMR1
04950   *            @arg TIM_DMABASE_CCMR2
04951   *            @arg TIM_DMABASE_CCER
04952   *            @arg TIM_DMABASE_CNT
04953   *            @arg TIM_DMABASE_PSC
04954   *            @arg TIM_DMABASE_ARR
04955   *            @arg TIM_DMABASE_RCR
04956   *            @arg TIM_DMABASE_CCR1
04957   *            @arg TIM_DMABASE_CCR2
04958   *            @arg TIM_DMABASE_CCR3
04959   *            @arg TIM_DMABASE_CCR4
04960   *            @arg TIM_DMABASE_BDTR
04961   *            @arg TIM_DMABASE_OR1
04962   *            @arg TIM_DMABASE_CCMR3
04963   *            @arg TIM_DMABASE_CCR5
04964   *            @arg TIM_DMABASE_CCR6
04965   *            @arg TIM_DMABASE_AF1
04966   *            @arg TIM_DMABASE_AF2
04967   *            @arg TIM_DMABASE_TISEL
04968   * @param  BurstRequestSrc TIM DMA Request sources
04969   *         This parameter can be one of the following values:
04970   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04971   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04972   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04973   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04974   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04975   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04976   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04977   * @param  BurstBuffer The Buffer address.
04978   * @param  BurstLength DMA Burst length. This parameter can be one value
04979   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
04980   * @param  DataLength Data length. This parameter can be one value
04981   *         between 1 and 0xFFFF.
04982   * @retval HAL status
04983   */
04984 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04985                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
04986                                                   uint32_t  BurstLength, uint32_t  DataLength)
04987 {
04988   HAL_StatusTypeDef status = HAL_OK;
04989
04990   /* Check the parameters */
04991   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
04992   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
04993   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04994   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
04995   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
04996
04997   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
04998   {
04999     return HAL_BUSY;
05000   }
05001   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
05002   {
05003     if ((BurstBuffer == NULL) && (BurstLength > 0U))
05004     {
05005       return HAL_ERROR;
05006     }
05007     else
05008     {
05009       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
05010     }
05011   }
05012   else
05013   {
05014     /* nothing to do */
05015   }
05016   switch (BurstRequestSrc)
05017   {
05018     case TIM_DMA_UPDATE:
05019     {
05020       /* Set the DMA Period elapsed callbacks */
05021       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
05022       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
05023
05024       /* Set the DMA error callback */
05025       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
05026
05027       /* Enable the DMA channel */
05028       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05029                            DataLength) != HAL_OK)
05030       {
05031         /* Return error status */
05032         return HAL_ERROR;
05033       }
05034       break;
05035     }
05036     case TIM_DMA_CC1:
05037     {
05038       /* Set the DMA capture callbacks */
05039       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
05040       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
05041
05042       /* Set the DMA error callback */
05043       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
05044
05045       /* Enable the DMA channel */
05046       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05047                            DataLength) != HAL_OK)
05048       {
05049         /* Return error status */
05050         return HAL_ERROR;
05051       }
05052       break;
05053     }
05054     case TIM_DMA_CC2:
05055     {
05056       /* Set the DMA capture callbacks */
05057       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
05058       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
05059
05060       /* Set the DMA error callback */
05061       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
05062
05063       /* Enable the DMA channel */
05064       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05065                            DataLength) != HAL_OK)
05066       {
05067         /* Return error status */
05068         return HAL_ERROR;
05069       }
05070       break;
05071     }
05072     case TIM_DMA_CC3:
05073     {
05074       /* Set the DMA capture callbacks */
05075       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
05076       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
05077
05078       /* Set the DMA error callback */
05079       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
05080
05081       /* Enable the DMA channel */
05082       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05083                            DataLength) != HAL_OK)
05084       {
05085         /* Return error status */
05086         return HAL_ERROR;
05087       }
05088       break;
05089     }
05090     case TIM_DMA_CC4:
05091     {
05092       /* Set the DMA capture callbacks */
05093       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
05094       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
05095
05096       /* Set the DMA error callback */
05097       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
05098
05099       /* Enable the DMA channel */
05100       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05101                            DataLength) != HAL_OK)
05102       {
05103         /* Return error status */
05104         return HAL_ERROR;
05105       }
05106       break;
05107     }
05108     case TIM_DMA_COM:
05109     {
05110       /* Set the DMA commutation callbacks */
05111       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
05112       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
05113
05114       /* Set the DMA error callback */
05115       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
05116
05117       /* Enable the DMA channel */
05118       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05119                            DataLength) != HAL_OK)
05120       {
05121         /* Return error status */
05122         return HAL_ERROR;
05123       }
05124       break;
05125     }
05126     case TIM_DMA_TRIGGER:
05127     {
05128       /* Set the DMA trigger callbacks */
05129       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
05130       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
05131
05132       /* Set the DMA error callback */
05133       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
05134
05135       /* Enable the DMA channel */
05136       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
05137                            DataLength) != HAL_OK)
05138       {
05139         /* Return error status */
05140         return HAL_ERROR;
05141       }
05142       break;
05143     }
05144     default:
05145       status = HAL_ERROR;
05146       break;
05147   }
05148
05149   if (status == HAL_OK)
05150   {
05151     /* Configure the DMA Burst Mode */
05152     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
05153
05154     /* Enable the TIM DMA Request */
05155     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
05156   }
05157
05158   /* Return function status */
05159   return status;
05160 }
05161
05162 /**
05163   * @brief  Stop the DMA burst reading
05164   * @param  htim TIM handle
05165   * @param  BurstRequestSrc TIM DMA Request sources to disable.
05166   * @retval HAL status
05167   */
05168 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
05169 {
05170   HAL_StatusTypeDef status = HAL_OK;
05171
05172   /* Check the parameters */
05173   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
05174
05175   /* Abort the DMA transfer (at least disable the DMA channel) */
05176   switch (BurstRequestSrc)
05177   {
05178     case TIM_DMA_UPDATE:
05179     {
05180       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
05181       break;
05182     }
05183     case TIM_DMA_CC1:
05184     {
05185       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
05186       break;
05187     }
05188     case TIM_DMA_CC2:
05189     {
05190       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
05191       break;
05192     }
05193     case TIM_DMA_CC3:
05194     {
05195       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
05196       break;
05197     }
05198     case TIM_DMA_CC4:
05199     {
05200       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
05201       break;
05202     }
05203     case TIM_DMA_COM:
05204     {
05205       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
05206       break;
05207     }
05208     case TIM_DMA_TRIGGER:
05209     {
05210       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
05211       break;
05212     }
05213     default:
05214       status = HAL_ERROR;
05215       break;
05216   }
05217
05218   if (status == HAL_OK)
05219   {
05220     /* Disable the TIM Update DMA request */
05221     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
05222
05223     /* Change the DMA burst operation state */
05224     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
05225   }
05226
05227   /* Return function status */
05228   return status;
05229 }
05230
05231 /**
05232   * @brief  Generate a software event
05233   * @param  htim TIM handle
05234   * @param  EventSource specifies the event source.
05235   *          This parameter can be one of the following values:
05236   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
05237   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
05238   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
05239   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
05240   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
05241   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
05242   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
05243   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
05244   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
05245   * @note   Basic timers can only generate an update event.
05246   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
05247   * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
05248   *         only for timer instances supporting break input(s).
05249   * @retval HAL status
05250   */
05251
05252 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
05253 {
05254   /* Check the parameters */
05255   assert_param(IS_TIM_INSTANCE(htim->Instance));
05256   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
05257
05258   /* Process Locked */
05259   __HAL_LOCK(htim);
05260
05261   /* Change the TIM state */
05262   htim->State = HAL_TIM_STATE_BUSY;
05263
05264   /* Set the event sources */
05265   htim->Instance->EGR = EventSource;
05266
05267   /* Change the TIM state */
05268   htim->State = HAL_TIM_STATE_READY;
05269
05270   __HAL_UNLOCK(htim);
05271
05272   /* Return function status */
05273   return HAL_OK;
05274 }
05275
05276 /**
05277   * @brief  Configures the OCRef clear feature
05278   * @param  htim TIM handle
05279   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
05280   *         contains the OCREF clear feature and parameters for the TIM peripheral.
05281   * @param  Channel specifies the TIM Channel
05282   *          This parameter can be one of the following values:
05283   *            @arg TIM_CHANNEL_1: TIM Channel 1
05284   *            @arg TIM_CHANNEL_2: TIM Channel 2
05285   *            @arg TIM_CHANNEL_3: TIM Channel 3
05286   *            @arg TIM_CHANNEL_4: TIM Channel 4
05287   *            @arg TIM_CHANNEL_5: TIM Channel 5
05288   *            @arg TIM_CHANNEL_6: TIM Channel 6
05289   * @retval HAL status
05290   */
05291 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
05292                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
05293                                            uint32_t Channel)
05294 {
05295   HAL_StatusTypeDef status = HAL_OK;
05296
05297   /* Check the parameters */
05298   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
05299   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
05300
05301   /* Process Locked */
05302   __HAL_LOCK(htim);
05303
05304   htim->State = HAL_TIM_STATE_BUSY;
05305
05306   switch (sClearInputConfig->ClearInputSource)
05307   {
05308     case TIM_CLEARINPUTSOURCE_NONE:
05309     {
05310       /* Clear the OCREF clear selection bit and the the ETR Bits */
05311       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
05312
05313       /* Clear TIMx_OR1_OCREF_CLR (reset value) */
05314       CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR);
05315       break;
05316     }
05317 #if defined(COMP1) || defined(COMP2) || defined(COMP3)
05318 #if defined(COMP1) && defined(COMP2)
05319     case TIM_CLEARINPUTSOURCE_COMP1:
05320     case TIM_CLEARINPUTSOURCE_COMP2:
05321 #endif /* COMP1 && COMP2 */
05322 #if defined(COMP3)
05323     case TIM_CLEARINPUTSOURCE_COMP3:
05324 #endif /* COMP3 */
05325     {
05326       /* Clear the OCREF clear selection bit */
05327       CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
05328
05329       /* OCREF_CLR_INT is connected to COMPx output */
05330       MODIFY_REG(htim->Instance->OR1, TIMx_OR1_OCREF_CLR, sClearInputConfig->ClearInputSource);
05331       break;
05332     }
05333 #endif /* COMP1 || COMP2 || COMP3 */
05334
05335     case TIM_CLEARINPUTSOURCE_ETR:
05336     {
05337       /* Check the parameters */
05338       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
05339       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
05340       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
05341
05342       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
05343       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
05344       {
05345         htim->State = HAL_TIM_STATE_READY;
05346         __HAL_UNLOCK(htim);
05347         return HAL_ERROR;
05348       }
05349
05350       TIM_ETR_SetConfig(htim->Instance,
05351                         sClearInputConfig->ClearInputPrescaler,
05352                         sClearInputConfig->ClearInputPolarity,
05353                         sClearInputConfig->ClearInputFilter);
05354
05355       /* Set the OCREF clear selection bit */
05356       SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
05357
05358       /* Clear TIMx_OR1_OCREF_CLR (reset value) */
05359       CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR);
05360       break;
05361     }
05362
05363     default:
05364       status = HAL_ERROR;
05365       break;
05366   }
05367
05368   if (status == HAL_OK)
05369   {
05370     switch (Channel)
05371     {
05372       case TIM_CHANNEL_1:
05373       {
05374         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05375         {
05376           /* Enable the OCREF clear feature for Channel 1 */
05377           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
05378         }
05379         else
05380         {
05381           /* Disable the OCREF clear feature for Channel 1 */
05382           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
05383         }
05384         break;
05385       }
05386       case TIM_CHANNEL_2:
05387       {
05388         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05389         {
05390           /* Enable the OCREF clear feature for Channel 2 */
05391           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
05392         }
05393         else
05394         {
05395           /* Disable the OCREF clear feature for Channel 2 */
05396           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
05397         }
05398         break;
05399       }
05400       case TIM_CHANNEL_3:
05401       {
05402         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05403         {
05404           /* Enable the OCREF clear feature for Channel 3 */
05405           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
05406         }
05407         else
05408         {
05409           /* Disable the OCREF clear feature for Channel 3 */
05410           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
05411         }
05412         break;
05413       }
05414       case TIM_CHANNEL_4:
05415       {
05416         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05417         {
05418           /* Enable the OCREF clear feature for Channel 4 */
05419           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
05420         }
05421         else
05422         {
05423           /* Disable the OCREF clear feature for Channel 4 */
05424           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
05425         }
05426         break;
05427       }
05428       case TIM_CHANNEL_5:
05429       {
05430         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05431         {
05432           /* Enable the OCREF clear feature for Channel 5 */
05433           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
05434         }
05435         else
05436         {
05437           /* Disable the OCREF clear feature for Channel 5 */
05438           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
05439         }
05440         break;
05441       }
05442       case TIM_CHANNEL_6:
05443       {
05444         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
05445         {
05446           /* Enable the OCREF clear feature for Channel 6 */
05447           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
05448         }
05449         else
05450         {
05451           /* Disable the OCREF clear feature for Channel 6 */
05452           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
05453         }
05454         break;
05455       }
05456       default:
05457         break;
05458     }
05459   }
05460
05461   htim->State = HAL_TIM_STATE_READY;
05462
05463   __HAL_UNLOCK(htim);
05464
05465   return status;
05466 }
05467
05468 /**
05469   * @brief   Configures the clock source to be used
05470   * @param  htim TIM handle
05471   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
05472   *         contains the clock source information for the TIM peripheral.
05473   * @retval HAL status
05474   */
05475 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
05476 {
05477   HAL_StatusTypeDef status = HAL_OK;
05478   uint32_t tmpsmcr;
05479
05480   /* Process Locked */
05481   __HAL_LOCK(htim);
05482
05483   htim->State = HAL_TIM_STATE_BUSY;
05484
05485   /* Check the parameters */
05486   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
05487
05488   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
05489   tmpsmcr = htim->Instance->SMCR;
05490   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
05491   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05492   htim->Instance->SMCR = tmpsmcr;
05493
05494   switch (sClockSourceConfig->ClockSource)
05495   {
05496     case TIM_CLOCKSOURCE_INTERNAL:
05497     {
05498       assert_param(IS_TIM_INSTANCE(htim->Instance));
05499       break;
05500     }
05501
05502     case TIM_CLOCKSOURCE_ETRMODE1:
05503     {
05504       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
05505       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
05506
05507       /* Check ETR input conditioning related parameters */
05508       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
05509       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05510       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05511
05512       /* Configure the ETR Clock source */
05513       TIM_ETR_SetConfig(htim->Instance,
05514                         sClockSourceConfig->ClockPrescaler,
05515                         sClockSourceConfig->ClockPolarity,
05516                         sClockSourceConfig->ClockFilter);
05517
05518       /* Select the External clock mode1 and the ETRF trigger */
05519       tmpsmcr = htim->Instance->SMCR;
05520       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
05521       /* Write to TIMx SMCR */
05522       htim->Instance->SMCR = tmpsmcr;
05523       break;
05524     }
05525
05526     case TIM_CLOCKSOURCE_ETRMODE2:
05527     {
05528       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
05529       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
05530
05531       /* Check ETR input conditioning related parameters */
05532       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
05533       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05534       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05535
05536       /* Configure the ETR Clock source */
05537       TIM_ETR_SetConfig(htim->Instance,
05538                         sClockSourceConfig->ClockPrescaler,
05539                         sClockSourceConfig->ClockPolarity,
05540                         sClockSourceConfig->ClockFilter);
05541       /* Enable the External clock mode2 */
05542       htim->Instance->SMCR |= TIM_SMCR_ECE;
05543       break;
05544     }
05545
05546     case TIM_CLOCKSOURCE_TI1:
05547     {
05548       /* Check whether or not the timer instance supports external clock mode 1 */
05549       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
05550
05551       /* Check TI1 input conditioning related parameters */
05552       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05553       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05554
05555       TIM_TI1_ConfigInputStage(htim->Instance,
05556                                sClockSourceConfig->ClockPolarity,
05557                                sClockSourceConfig->ClockFilter);
05558       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
05559       break;
05560     }
05561
05562     case TIM_CLOCKSOURCE_TI2:
05563     {
05564       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
05565       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
05566
05567       /* Check TI2 input conditioning related parameters */
05568       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05569       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05570
05571       TIM_TI2_ConfigInputStage(htim->Instance,
05572                                sClockSourceConfig->ClockPolarity,
05573                                sClockSourceConfig->ClockFilter);
05574       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
05575       break;
05576     }
05577
05578     case TIM_CLOCKSOURCE_TI1ED:
05579     {
05580       /* Check whether or not the timer instance supports external clock mode 1 */
05581       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
05582
05583       /* Check TI1 input conditioning related parameters */
05584       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
05585       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
05586
05587       TIM_TI1_ConfigInputStage(htim->Instance,
05588                                sClockSourceConfig->ClockPolarity,
05589                                sClockSourceConfig->ClockFilter);
05590       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
05591       break;
05592     }
05593
05594     case TIM_CLOCKSOURCE_ITR0:
05595     case TIM_CLOCKSOURCE_ITR1:
05596     case TIM_CLOCKSOURCE_ITR2:
05597     case TIM_CLOCKSOURCE_ITR3:
05598     {
05599       /* Check whether or not the timer instance supports internal trigger input */
05600       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
05601
05602       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
05603       break;
05604     }
05605
05606     default:
05607       status = HAL_ERROR;
05608       break;
05609   }
05610   htim->State = HAL_TIM_STATE_READY;
05611
05612   __HAL_UNLOCK(htim);
05613
05614   return status;
05615 }
05616
05617 /**
05618   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
05619   *         or a XOR combination between CH1_input, CH2_input & CH3_input
05620   * @param  htim TIM handle.
05621   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
05622   *         output of a XOR gate.
05623   *          This parameter can be one of the following values:
05624   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
05625   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
05626   *            pins are connected to the TI1 input (XOR combination)
05627   * @retval HAL status
05628   */
05629 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
05630 {
05631   uint32_t tmpcr2;
05632
05633   /* Check the parameters */
05634   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
05635   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
05636
05637   /* Get the TIMx CR2 register value */
05638   tmpcr2 = htim->Instance->CR2;
05639
05640   /* Reset the TI1 selection */
05641   tmpcr2 &= ~TIM_CR2_TI1S;
05642
05643   /* Set the TI1 selection */
05644   tmpcr2 |= TI1_Selection;
05645
05646   /* Write to TIMxCR2 */
05647   htim->Instance->CR2 = tmpcr2;
05648
05649   return HAL_OK;
05650 }
05651
05652 /**
05653   * @brief  Configures the TIM in Slave mode
05654   * @param  htim TIM handle.
05655   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
05656   *         contains the selected trigger (internal trigger input, filtered
05657   *         timer input or external trigger input) and the Slave mode
05658   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
05659   * @retval HAL status
05660   */
05661 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
05662 {
05663   /* Check the parameters */
05664   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
05665   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
05666   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
05667
05668   __HAL_LOCK(htim);
05669
05670   htim->State = HAL_TIM_STATE_BUSY;
05671
05672   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
05673   {
05674     htim->State = HAL_TIM_STATE_READY;
05675     __HAL_UNLOCK(htim);
05676     return HAL_ERROR;
05677   }
05678
05679   /* Disable Trigger Interrupt */
05680   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
05681
05682   /* Disable Trigger DMA request */
05683   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
05684
05685   htim->State = HAL_TIM_STATE_READY;
05686
05687   __HAL_UNLOCK(htim);
05688
05689   return HAL_OK;
05690 }
05691
05692 /**
05693   * @brief  Configures the TIM in Slave mode in interrupt mode
05694   * @param  htim TIM handle.
05695   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
05696   *         contains the selected trigger (internal trigger input, filtered
05697   *         timer input or external trigger input) and the Slave mode
05698   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
05699   * @retval HAL status
05700   */
05701 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
05702                                                 const TIM_SlaveConfigTypeDef *sSlaveConfig)
05703 {
05704   /* Check the parameters */
05705   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
05706   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
05707   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
05708
05709   __HAL_LOCK(htim);
05710
05711   htim->State = HAL_TIM_STATE_BUSY;
05712
05713   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
05714   {
05715     htim->State = HAL_TIM_STATE_READY;
05716     __HAL_UNLOCK(htim);
05717     return HAL_ERROR;
05718   }
05719
05720   /* Enable Trigger Interrupt */
05721   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
05722
05723   /* Disable Trigger DMA request */
05724   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
05725
05726   htim->State = HAL_TIM_STATE_READY;
05727
05728   __HAL_UNLOCK(htim);
05729
05730   return HAL_OK;
05731 }
05732
05733 /**
05734   * @brief  Read the captured value from Capture Compare unit
05735   * @param  htim TIM handle.
05736   * @param  Channel TIM Channels to be enabled
05737   *          This parameter can be one of the following values:
05738   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
05739   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
05740   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
05741   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
05742   * @retval Captured value
05743   */
05744 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
05745 {
05746   uint32_t tmpreg = 0U;
05747
05748   switch (Channel)
05749   {
05750     case TIM_CHANNEL_1:
05751     {
05752       /* Check the parameters */
05753       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05754
05755       /* Return the capture 1 value */
05756       tmpreg =  htim->Instance->CCR1;
05757
05758       break;
05759     }
05760     case TIM_CHANNEL_2:
05761     {
05762       /* Check the parameters */
05763       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05764
05765       /* Return the capture 2 value */
05766       tmpreg =   htim->Instance->CCR2;
05767
05768       break;
05769     }
05770
05771     case TIM_CHANNEL_3:
05772     {
05773       /* Check the parameters */
05774       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
05775
05776       /* Return the capture 3 value */
05777       tmpreg =   htim->Instance->CCR3;
05778
05779       break;
05780     }
05781
05782     case TIM_CHANNEL_4:
05783     {
05784       /* Check the parameters */
05785       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
05786
05787       /* Return the capture 4 value */
05788       tmpreg =   htim->Instance->CCR4;
05789
05790       break;
05791     }
05792
05793     default:
05794       break;
05795   }
05796
05797   return tmpreg;
05798 }
05799
05800 /**
05801   * @}
05802   */
05803
05804 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
05805   *  @brief    TIM Callbacks functions
05806   *
05807 @verbatim
05808   ==============================================================================
05809                         ##### TIM Callbacks functions #####
05810   ==============================================================================
05811  [..]
05812    This section provides TIM callback functions:
05813    (+) TIM Period elapsed callback
05814    (+) TIM Output Compare callback
05815    (+) TIM Input capture callback
05816    (+) TIM Trigger callback
05817    (+) TIM Error callback
05818
05819 @endverbatim
05820   * @{
05821   */
05822
05823 /**
05824   * @brief  Period elapsed callback in non-blocking mode
05825   * @param  htim TIM handle
05826   * @retval None
05827   */
05828 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
05829 {
05830   /* Prevent unused argument(s) compilation warning */
05831   UNUSED(htim);
05832
05833   /* NOTE : This function should not be modified, when the callback is needed,
05834             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
05835    */
05836 }
05837
05838 /**
05839   * @brief  Period elapsed half complete callback in non-blocking mode
05840   * @param  htim TIM handle
05841   * @retval None
05842   */
05843 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
05844 {
05845   /* Prevent unused argument(s) compilation warning */
05846   UNUSED(htim);
05847
05848   /* NOTE : This function should not be modified, when the callback is needed,
05849             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
05850    */
05851 }
05852
05853 /**
05854   * @brief  Output Compare callback in non-blocking mode
05855   * @param  htim TIM OC handle
05856   * @retval None
05857   */
05858 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
05859 {
05860   /* Prevent unused argument(s) compilation warning */
05861   UNUSED(htim);
05862
05863   /* NOTE : This function should not be modified, when the callback is needed,
05864             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
05865    */
05866 }
05867
05868 /**
05869   * @brief  Input Capture callback in non-blocking mode
05870   * @param  htim TIM IC handle
05871   * @retval None
05872   */
05873 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
05874 {
05875   /* Prevent unused argument(s) compilation warning */
05876   UNUSED(htim);
05877
05878   /* NOTE : This function should not be modified, when the callback is needed,
05879             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
05880    */
05881 }
05882
05883 /**
05884   * @brief  Input Capture half complete callback in non-blocking mode
05885   * @param  htim TIM IC handle
05886   * @retval None
05887   */
05888 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
05889 {
05890   /* Prevent unused argument(s) compilation warning */
05891   UNUSED(htim);
05892
05893   /* NOTE : This function should not be modified, when the callback is needed,
05894             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
05895    */
05896 }
05897
05898 /**
05899   * @brief  PWM Pulse finished callback in non-blocking mode
05900   * @param  htim TIM handle
05901   * @retval None
05902   */
05903 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
05904 {
05905   /* Prevent unused argument(s) compilation warning */
05906   UNUSED(htim);
05907
05908   /* NOTE : This function should not be modified, when the callback is needed,
05909             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
05910    */
05911 }
05912
05913 /**
05914   * @brief  PWM Pulse finished half complete callback in non-blocking mode
05915   * @param  htim TIM handle
05916   * @retval None
05917   */
05918 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
05919 {
05920   /* Prevent unused argument(s) compilation warning */
05921   UNUSED(htim);
05922
05923   /* NOTE : This function should not be modified, when the callback is needed,
05924             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
05925    */
05926 }
05927
05928 /**
05929   * @brief  Hall Trigger detection callback in non-blocking mode
05930   * @param  htim TIM handle
05931   * @retval None
05932   */
05933 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
05934 {
05935   /* Prevent unused argument(s) compilation warning */
05936   UNUSED(htim);
05937
05938   /* NOTE : This function should not be modified, when the callback is needed,
05939             the HAL_TIM_TriggerCallback could be implemented in the user file
05940    */
05941 }
05942
05943 /**
05944   * @brief  Hall Trigger detection half complete callback in non-blocking mode
05945   * @param  htim TIM handle
05946   * @retval None
05947   */
05948 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
05949 {
05950   /* Prevent unused argument(s) compilation warning */
05951   UNUSED(htim);
05952
05953   /* NOTE : This function should not be modified, when the callback is needed,
05954             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
05955    */
05956 }
05957
05958 /**
05959   * @brief  Timer error callback in non-blocking mode
05960   * @param  htim TIM handle
05961   * @retval None
05962   */
05963 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
05964 {
05965   /* Prevent unused argument(s) compilation warning */
05966   UNUSED(htim);
05967
05968   /* NOTE : This function should not be modified, when the callback is needed,
05969             the HAL_TIM_ErrorCallback could be implemented in the user file
05970    */
05971 }
05972
05973 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05974 /**
05975   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
05976   * @param htim tim handle
05977   * @param CallbackID ID of the callback to be registered
05978   *        This parameter can be one of the following values:
05979   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
05980   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
05981   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
05982   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
05983   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
05984   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
05985   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
05986   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
05987   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
05988   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
05989   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
05990   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
05991   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
05992   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
05993   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
05994   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
05995   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
05996   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
05997   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
05998   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
05999   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
06000   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
06001   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
06002   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
06003   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
06004   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
06005   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
06006   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
06007   *          @param pCallback pointer to the callback function
06008   *          @retval status
06009   */
06010 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
06011                                            pTIM_CallbackTypeDef pCallback)
06012 {
06013   HAL_StatusTypeDef status = HAL_OK;
06014
06015   if (pCallback == NULL)
06016   {
06017     return HAL_ERROR;
06018   }
06019   /* Process locked */
06020   __HAL_LOCK(htim);
06021
06022   if (htim->State == HAL_TIM_STATE_READY)
06023   {
06024     switch (CallbackID)
06025     {
06026       case HAL_TIM_BASE_MSPINIT_CB_ID :
06027         htim->Base_MspInitCallback                 = pCallback;
06028         break;
06029
06030       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
06031         htim->Base_MspDeInitCallback               = pCallback;
06032         break;
06033
06034       case HAL_TIM_IC_MSPINIT_CB_ID :
06035         htim->IC_MspInitCallback                   = pCallback;
06036         break;
06037
06038       case HAL_TIM_IC_MSPDEINIT_CB_ID :
06039         htim->IC_MspDeInitCallback                 = pCallback;
06040         break;
06041
06042       case HAL_TIM_OC_MSPINIT_CB_ID :
06043         htim->OC_MspInitCallback                   = pCallback;
06044         break;
06045
06046       case HAL_TIM_OC_MSPDEINIT_CB_ID :
06047         htim->OC_MspDeInitCallback                 = pCallback;
06048         break;
06049
06050       case HAL_TIM_PWM_MSPINIT_CB_ID :
06051         htim->PWM_MspInitCallback                  = pCallback;
06052         break;
06053
06054       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
06055         htim->PWM_MspDeInitCallback                = pCallback;
06056         break;
06057
06058       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
06059         htim->OnePulse_MspInitCallback             = pCallback;
06060         break;
06061
06062       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
06063         htim->OnePulse_MspDeInitCallback           = pCallback;
06064         break;
06065
06066       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
06067         htim->Encoder_MspInitCallback              = pCallback;
06068         break;
06069
06070       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
06071         htim->Encoder_MspDeInitCallback            = pCallback;
06072         break;
06073
06074       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
06075         htim->HallSensor_MspInitCallback           = pCallback;
06076         break;
06077
06078       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
06079         htim->HallSensor_MspDeInitCallback         = pCallback;
06080         break;
06081
06082       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
06083         htim->PeriodElapsedCallback                = pCallback;
06084         break;
06085
06086       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
06087         htim->PeriodElapsedHalfCpltCallback        = pCallback;
06088         break;
06089
06090       case HAL_TIM_TRIGGER_CB_ID :
06091         htim->TriggerCallback                      = pCallback;
06092         break;
06093
06094       case HAL_TIM_TRIGGER_HALF_CB_ID :
06095         htim->TriggerHalfCpltCallback              = pCallback;
06096         break;
06097
06098       case HAL_TIM_IC_CAPTURE_CB_ID :
06099         htim->IC_CaptureCallback                   = pCallback;
06100         break;
06101
06102       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
06103         htim->IC_CaptureHalfCpltCallback           = pCallback;
06104         break;
06105
06106       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
06107         htim->OC_DelayElapsedCallback              = pCallback;
06108         break;
06109
06110       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
06111         htim->PWM_PulseFinishedCallback            = pCallback;
06112         break;
06113
06114       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
06115         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
06116         break;
06117
06118       case HAL_TIM_ERROR_CB_ID :
06119         htim->ErrorCallback                        = pCallback;
06120         break;
06121
06122       case HAL_TIM_COMMUTATION_CB_ID :
06123         htim->CommutationCallback                  = pCallback;
06124         break;
06125
06126       case HAL_TIM_COMMUTATION_HALF_CB_ID :
06127         htim->CommutationHalfCpltCallback          = pCallback;
06128         break;
06129
06130       case HAL_TIM_BREAK_CB_ID :
06131         htim->BreakCallback                        = pCallback;
06132         break;
06133
06134       case HAL_TIM_BREAK2_CB_ID :
06135         htim->Break2Callback                       = pCallback;
06136         break;
06137
06138       default :
06139         /* Return error status */
06140         status = HAL_ERROR;
06141         break;
06142     }
06143   }
06144   else if (htim->State == HAL_TIM_STATE_RESET)
06145   {
06146     switch (CallbackID)
06147     {
06148       case HAL_TIM_BASE_MSPINIT_CB_ID :
06149         htim->Base_MspInitCallback         = pCallback;
06150         break;
06151
06152       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
06153         htim->Base_MspDeInitCallback       = pCallback;
06154         break;
06155
06156       case HAL_TIM_IC_MSPINIT_CB_ID :
06157         htim->IC_MspInitCallback           = pCallback;
06158         break;
06159
06160       case HAL_TIM_IC_MSPDEINIT_CB_ID :
06161         htim->IC_MspDeInitCallback         = pCallback;
06162         break;
06163
06164       case HAL_TIM_OC_MSPINIT_CB_ID :
06165         htim->OC_MspInitCallback           = pCallback;
06166         break;
06167
06168       case HAL_TIM_OC_MSPDEINIT_CB_ID :
06169         htim->OC_MspDeInitCallback         = pCallback;
06170         break;
06171
06172       case HAL_TIM_PWM_MSPINIT_CB_ID :
06173         htim->PWM_MspInitCallback          = pCallback;
06174         break;
06175
06176       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
06177         htim->PWM_MspDeInitCallback        = pCallback;
06178         break;
06179
06180       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
06181         htim->OnePulse_MspInitCallback     = pCallback;
06182         break;
06183
06184       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
06185         htim->OnePulse_MspDeInitCallback   = pCallback;
06186         break;
06187
06188       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
06189         htim->Encoder_MspInitCallback      = pCallback;
06190         break;
06191
06192       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
06193         htim->Encoder_MspDeInitCallback    = pCallback;
06194         break;
06195
06196       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
06197         htim->HallSensor_MspInitCallback   = pCallback;
06198         break;
06199
06200       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
06201         htim->HallSensor_MspDeInitCallback = pCallback;
06202         break;
06203
06204       default :
06205         /* Return error status */
06206         status = HAL_ERROR;
06207         break;
06208     }
06209   }
06210   else
06211   {
06212     /* Return error status */
06213     status = HAL_ERROR;
06214   }
06215
06216   /* Release Lock */
06217   __HAL_UNLOCK(htim);
06218
06219   return status;
06220 }
06221
06222 /**
06223   * @brief  Unregister a TIM callback
06224   *         TIM callback is redirected to the weak predefined callback
06225   * @param htim tim handle
06226   * @param CallbackID ID of the callback to be unregistered
06227   *        This parameter can be one of the following values:
06228   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
06229   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
06230   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
06231   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
06232   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
06233   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
06234   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
06235   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
06236   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
06237   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
06238   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
06239   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
06240   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
06241   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
06242   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
06243   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
06244   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
06245   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
06246   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
06247   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
06248   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
06249   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
06250   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
06251   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
06252   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
06253   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
06254   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
06255   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
06256   *          @retval status
06257   */
06258 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
06259 {
06260   HAL_StatusTypeDef status = HAL_OK;
06261
06262   /* Process locked */
06263   __HAL_LOCK(htim);
06264
06265   if (htim->State == HAL_TIM_STATE_READY)
06266   {
06267     switch (CallbackID)
06268     {
06269       case HAL_TIM_BASE_MSPINIT_CB_ID :
06270         /* Legacy weak Base MspInit Callback */
06271         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
06272         break;
06273
06274       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
06275         /* Legacy weak Base Msp DeInit Callback */
06276         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
06277         break;
06278
06279       case HAL_TIM_IC_MSPINIT_CB_ID :
06280         /* Legacy weak IC Msp Init Callback */
06281         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
06282         break;
06283
06284       case HAL_TIM_IC_MSPDEINIT_CB_ID :
06285         /* Legacy weak IC Msp DeInit Callback */
06286         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
06287         break;
06288
06289       case HAL_TIM_OC_MSPINIT_CB_ID :
06290         /* Legacy weak OC Msp Init Callback */
06291         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
06292         break;
06293
06294       case HAL_TIM_OC_MSPDEINIT_CB_ID :
06295         /* Legacy weak OC Msp DeInit Callback */
06296         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
06297         break;
06298
06299       case HAL_TIM_PWM_MSPINIT_CB_ID :
06300         /* Legacy weak PWM Msp Init Callback */
06301         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
06302         break;
06303
06304       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
06305         /* Legacy weak PWM Msp DeInit Callback */
06306         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
06307         break;
06308
06309       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
06310         /* Legacy weak One Pulse Msp Init Callback */
06311         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
06312         break;
06313
06314       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
06315         /* Legacy weak One Pulse Msp DeInit Callback */
06316         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
06317         break;
06318
06319       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
06320         /* Legacy weak Encoder Msp Init Callback */
06321         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
06322         break;
06323
06324       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
06325         /* Legacy weak Encoder Msp DeInit Callback */
06326         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
06327         break;
06328
06329       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
06330         /* Legacy weak Hall Sensor Msp Init Callback */
06331         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
06332         break;
06333
06334       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
06335         /* Legacy weak Hall Sensor Msp DeInit Callback */
06336         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
06337         break;
06338
06339       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
06340         /* Legacy weak Period Elapsed Callback */
06341         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
06342         break;
06343
06344       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
06345         /* Legacy weak Period Elapsed half complete Callback */
06346         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
06347         break;
06348
06349       case HAL_TIM_TRIGGER_CB_ID :
06350         /* Legacy weak Trigger Callback */
06351         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
06352         break;
06353
06354       case HAL_TIM_TRIGGER_HALF_CB_ID :
06355         /* Legacy weak Trigger half complete Callback */
06356         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
06357         break;
06358
06359       case HAL_TIM_IC_CAPTURE_CB_ID :
06360         /* Legacy weak IC Capture Callback */
06361         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
06362         break;
06363
06364       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
06365         /* Legacy weak IC Capture half complete Callback */
06366         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
06367         break;
06368
06369       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
06370         /* Legacy weak OC Delay Elapsed Callback */
06371         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
06372         break;
06373
06374       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
06375         /* Legacy weak PWM Pulse Finished Callback */
06376         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
06377         break;
06378
06379       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
06380         /* Legacy weak PWM Pulse Finished half complete Callback */
06381         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
06382         break;
06383
06384       case HAL_TIM_ERROR_CB_ID :
06385         /* Legacy weak Error Callback */
06386         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
06387         break;
06388
06389       case HAL_TIM_COMMUTATION_CB_ID :
06390         /* Legacy weak Commutation Callback */
06391         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
06392         break;
06393
06394       case HAL_TIM_COMMUTATION_HALF_CB_ID :
06395         /* Legacy weak Commutation half complete Callback */
06396         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
06397         break;
06398
06399       case HAL_TIM_BREAK_CB_ID :
06400         /* Legacy weak Break Callback */
06401         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
06402         break;
06403
06404       case HAL_TIM_BREAK2_CB_ID :
06405         /* Legacy weak Break2 Callback */
06406         htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
06407         break;
06408
06409       default :
06410         /* Return error status */
06411         status = HAL_ERROR;
06412         break;
06413     }
06414   }
06415   else if (htim->State == HAL_TIM_STATE_RESET)
06416   {
06417     switch (CallbackID)
06418     {
06419       case HAL_TIM_BASE_MSPINIT_CB_ID :
06420         /* Legacy weak Base MspInit Callback */
06421         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
06422         break;
06423
06424       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
06425         /* Legacy weak Base Msp DeInit Callback */
06426         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
06427         break;
06428
06429       case HAL_TIM_IC_MSPINIT_CB_ID :
06430         /* Legacy weak IC Msp Init Callback */
06431         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
06432         break;
06433
06434       case HAL_TIM_IC_MSPDEINIT_CB_ID :
06435         /* Legacy weak IC Msp DeInit Callback */
06436         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
06437         break;
06438
06439       case HAL_TIM_OC_MSPINIT_CB_ID :
06440         /* Legacy weak OC Msp Init Callback */
06441         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
06442         break;
06443
06444       case HAL_TIM_OC_MSPDEINIT_CB_ID :
06445         /* Legacy weak OC Msp DeInit Callback */
06446         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
06447         break;
06448
06449       case HAL_TIM_PWM_MSPINIT_CB_ID :
06450         /* Legacy weak PWM Msp Init Callback */
06451         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
06452         break;
06453
06454       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
06455         /* Legacy weak PWM Msp DeInit Callback */
06456         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
06457         break;
06458
06459       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
06460         /* Legacy weak One Pulse Msp Init Callback */
06461         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
06462         break;
06463
06464       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
06465         /* Legacy weak One Pulse Msp DeInit Callback */
06466         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
06467         break;
06468
06469       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
06470         /* Legacy weak Encoder Msp Init Callback */
06471         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
06472         break;
06473
06474       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
06475         /* Legacy weak Encoder Msp DeInit Callback */
06476         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
06477         break;
06478
06479       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
06480         /* Legacy weak Hall Sensor Msp Init Callback */
06481         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
06482         break;
06483
06484       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
06485         /* Legacy weak Hall Sensor Msp DeInit Callback */
06486         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
06487         break;
06488
06489       default :
06490         /* Return error status */
06491         status = HAL_ERROR;
06492         break;
06493     }
06494   }
06495   else
06496   {
06497     /* Return error status */
06498     status = HAL_ERROR;
06499   }
06500
06501   /* Release Lock */
06502   __HAL_UNLOCK(htim);
06503
06504   return status;
06505 }
06506 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06507
06508 /**
06509   * @}
06510   */
06511
06512 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
06513   *  @brief   TIM Peripheral State functions
06514   *
06515 @verbatim
06516   ==============================================================================
06517                         ##### Peripheral State functions #####
06518   ==============================================================================
06519     [..]
06520     This subsection permits to get in run-time the status of the peripheral
06521     and the data flow.
06522
06523 @endverbatim
06524   * @{
06525   */
06526
06527 /**
06528   * @brief  Return the TIM Base handle state.
06529   * @param  htim TIM Base handle
06530   * @retval HAL state
06531   */
06532 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
06533 {
06534   return htim->State;
06535 }
06536
06537 /**
06538   * @brief  Return the TIM OC handle state.
06539   * @param  htim TIM Output Compare handle
06540   * @retval HAL state
06541   */
06542 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
06543 {
06544   return htim->State;
06545 }
06546
06547 /**
06548   * @brief  Return the TIM PWM handle state.
06549   * @param  htim TIM handle
06550   * @retval HAL state
06551   */
06552 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
06553 {
06554   return htim->State;
06555 }
06556
06557 /**
06558   * @brief  Return the TIM Input Capture handle state.
06559   * @param  htim TIM IC handle
06560   * @retval HAL state
06561   */
06562 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
06563 {
06564   return htim->State;
06565 }
06566
06567 /**
06568   * @brief  Return the TIM One Pulse Mode handle state.
06569   * @param  htim TIM OPM handle
06570   * @retval HAL state
06571   */
06572 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
06573 {
06574   return htim->State;
06575 }
06576
06577 /**
06578   * @brief  Return the TIM Encoder Mode handle state.
06579   * @param  htim TIM Encoder Interface handle
06580   * @retval HAL state
06581   */
06582 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
06583 {
06584   return htim->State;
06585 }
06586
06587 /**
06588   * @brief  Return the TIM Encoder Mode handle state.
06589   * @param  htim TIM handle
06590   * @retval Active channel
06591   */
06592 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
06593 {
06594   return htim->Channel;
06595 }
06596
06597 /**
06598   * @brief  Return actual state of the TIM channel.
06599   * @param  htim TIM handle
06600   * @param  Channel TIM Channel
06601   *          This parameter can be one of the following values:
06602   *            @arg TIM_CHANNEL_1: TIM Channel 1
06603   *            @arg TIM_CHANNEL_2: TIM Channel 2
06604   *            @arg TIM_CHANNEL_3: TIM Channel 3
06605   *            @arg TIM_CHANNEL_4: TIM Channel 4
06606   *            @arg TIM_CHANNEL_5: TIM Channel 5
06607   *            @arg TIM_CHANNEL_6: TIM Channel 6
06608   * @retval TIM Channel state
06609   */
06610 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
06611 {
06612   HAL_TIM_ChannelStateTypeDef channel_state;
06613
06614   /* Check the parameters */
06615   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
06616
06617   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
06618
06619   return channel_state;
06620 }
06621
06622 /**
06623   * @brief  Return actual state of a DMA burst operation.
06624   * @param  htim TIM handle
06625   * @retval DMA burst state
06626   */
06627 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
06628 {
06629   /* Check the parameters */
06630   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
06631
06632   return htim->DMABurstState;
06633 }
06634
06635 /**
06636   * @}
06637   */
06638
06639 /**
06640   * @}
06641   */
06642
06643 /** @defgroup TIM_Private_Functions TIM Private Functions
06644   * @{
06645   */
06646
06647 /**
06648   * @brief  TIM DMA error callback
06649   * @param  hdma pointer to DMA handle.
06650   * @retval None
06651   */
06652 void TIM_DMAError(DMA_HandleTypeDef *hdma)
06653 {
06654   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06655
06656   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06657   {
06658     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06659     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
06660   }
06661   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06662   {
06663     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06664     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
06665   }
06666   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06667   {
06668     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06669     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
06670   }
06671   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06672   {
06673     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06674     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
06675   }
06676   else
06677   {
06678     htim->State = HAL_TIM_STATE_READY;
06679   }
06680
06681 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06682   htim->ErrorCallback(htim);
06683 #else
06684   HAL_TIM_ErrorCallback(htim);
06685 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06686
06687   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06688 }
06689
06690 /**
06691   * @brief  TIM DMA Delay Pulse complete callback.
06692   * @param  hdma pointer to DMA handle.
06693   * @retval None
06694   */
06695 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
06696 {
06697   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06698
06699   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06700   {
06701     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06702
06703     if (hdma->Init.Mode == DMA_NORMAL)
06704     {
06705       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
06706     }
06707   }
06708   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06709   {
06710     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06711
06712     if (hdma->Init.Mode == DMA_NORMAL)
06713     {
06714       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
06715     }
06716   }
06717   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06718   {
06719     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06720
06721     if (hdma->Init.Mode == DMA_NORMAL)
06722     {
06723       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
06724     }
06725   }
06726   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06727   {
06728     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06729
06730     if (hdma->Init.Mode == DMA_NORMAL)
06731     {
06732       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
06733     }
06734   }
06735   else
06736   {
06737     /* nothing to do */
06738   }
06739
06740 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06741   htim->PWM_PulseFinishedCallback(htim);
06742 #else
06743   HAL_TIM_PWM_PulseFinishedCallback(htim);
06744 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06745
06746   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06747 }
06748
06749 /**
06750   * @brief  TIM DMA Delay Pulse half complete callback.
06751   * @param  hdma pointer to DMA handle.
06752   * @retval None
06753   */
06754 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
06755 {
06756   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06757
06758   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06759   {
06760     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06761   }
06762   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06763   {
06764     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06765   }
06766   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06767   {
06768     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06769   }
06770   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06771   {
06772     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06773   }
06774   else
06775   {
06776     /* nothing to do */
06777   }
06778
06779 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06780   htim->PWM_PulseFinishedHalfCpltCallback(htim);
06781 #else
06782   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
06783 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06784
06785   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06786 }
06787
06788 /**
06789   * @brief  TIM DMA Capture complete callback.
06790   * @param  hdma pointer to DMA handle.
06791   * @retval None
06792   */
06793 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
06794 {
06795   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06796
06797   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06798   {
06799     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06800
06801     if (hdma->Init.Mode == DMA_NORMAL)
06802     {
06803       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
06804       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
06805     }
06806   }
06807   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06808   {
06809     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06810
06811     if (hdma->Init.Mode == DMA_NORMAL)
06812     {
06813       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
06814       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
06815     }
06816   }
06817   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06818   {
06819     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06820
06821     if (hdma->Init.Mode == DMA_NORMAL)
06822     {
06823       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
06824       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
06825     }
06826   }
06827   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06828   {
06829     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06830
06831     if (hdma->Init.Mode == DMA_NORMAL)
06832     {
06833       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
06834       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
06835     }
06836   }
06837   else
06838   {
06839     /* nothing to do */
06840   }
06841
06842 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06843   htim->IC_CaptureCallback(htim);
06844 #else
06845   HAL_TIM_IC_CaptureCallback(htim);
06846 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06847
06848   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06849 }
06850
06851 /**
06852   * @brief  TIM DMA Capture half complete callback.
06853   * @param  hdma pointer to DMA handle.
06854   * @retval None
06855   */
06856 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
06857 {
06858   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06859
06860   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
06861   {
06862     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
06863   }
06864   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
06865   {
06866     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
06867   }
06868   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
06869   {
06870     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
06871   }
06872   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
06873   {
06874     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
06875   }
06876   else
06877   {
06878     /* nothing to do */
06879   }
06880
06881 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06882   htim->IC_CaptureHalfCpltCallback(htim);
06883 #else
06884   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
06885 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06886
06887   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
06888 }
06889
06890 /**
06891   * @brief  TIM DMA Period Elapse complete callback.
06892   * @param  hdma pointer to DMA handle.
06893   * @retval None
06894   */
06895 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
06896 {
06897   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06898
06899   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
06900   {
06901     htim->State = HAL_TIM_STATE_READY;
06902   }
06903
06904 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06905   htim->PeriodElapsedCallback(htim);
06906 #else
06907   HAL_TIM_PeriodElapsedCallback(htim);
06908 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06909 }
06910
06911 /**
06912   * @brief  TIM DMA Period Elapse half complete callback.
06913   * @param  hdma pointer to DMA handle.
06914   * @retval None
06915   */
06916 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
06917 {
06918   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06919
06920 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06921   htim->PeriodElapsedHalfCpltCallback(htim);
06922 #else
06923   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
06924 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06925 }
06926
06927 /**
06928   * @brief  TIM DMA Trigger callback.
06929   * @param  hdma pointer to DMA handle.
06930   * @retval None
06931   */
06932 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
06933 {
06934   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06935
06936   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
06937   {
06938     htim->State = HAL_TIM_STATE_READY;
06939   }
06940
06941 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06942   htim->TriggerCallback(htim);
06943 #else
06944   HAL_TIM_TriggerCallback(htim);
06945 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06946 }
06947
06948 /**
06949   * @brief  TIM DMA Trigger half complete callback.
06950   * @param  hdma pointer to DMA handle.
06951   * @retval None
06952   */
06953 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
06954 {
06955   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
06956
06957 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06958   htim->TriggerHalfCpltCallback(htim);
06959 #else
06960   HAL_TIM_TriggerHalfCpltCallback(htim);
06961 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06962 }
06963
06964 /**
06965   * @brief  Time Base configuration
06966   * @param  TIMx TIM peripheral
06967   * @param  Structure TIM Base configuration structure
06968   * @retval None
06969   */
06970 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
06971 {
06972   uint32_t tmpcr1;
06973   tmpcr1 = TIMx->CR1;
06974
06975   /* Set TIM Time Base Unit parameters ---------------------------------------*/
06976   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
06977   {
06978     /* Select the Counter Mode */
06979     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
06980     tmpcr1 |= Structure->CounterMode;
06981   }
06982
06983   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
06984   {
06985     /* Set the clock division */
06986     tmpcr1 &= ~TIM_CR1_CKD;
06987     tmpcr1 |= (uint32_t)Structure->ClockDivision;
06988   }
06989
06990   /* Set the auto-reload preload */
06991   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
06992
06993   TIMx->CR1 = tmpcr1;
06994
06995   /* Set the Autoreload value */
06996   TIMx->ARR = (uint32_t)Structure->Period ;
06997
06998   /* Set the Prescaler value */
06999   TIMx->PSC = Structure->Prescaler;
07000
07001   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
07002   {
07003     /* Set the Repetition Counter value */
07004     TIMx->RCR = Structure->RepetitionCounter;
07005   }
07006
07007   /* Generate an update event to reload the Prescaler
07008      and the repetition counter (only for advanced timer) value immediately */
07009   TIMx->EGR = TIM_EGR_UG;
07010 }
07011
07012 /**
07013   * @brief  Timer Output Compare 1 configuration
07014   * @param  TIMx to select the TIM peripheral
07015   * @param  OC_Config The output configuration structure
07016   * @retval None
07017   */
07018 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
07019 {
07020   uint32_t tmpccmrx;
07021   uint32_t tmpccer;
07022   uint32_t tmpcr2;
07023
07024   /* Disable the Channel 1: Reset the CC1E Bit */
07025   TIMx->CCER &= ~TIM_CCER_CC1E;
07026
07027   /* Get the TIMx CCER register value */
07028   tmpccer = TIMx->CCER;
07029   /* Get the TIMx CR2 register value */
07030   tmpcr2 =  TIMx->CR2;
07031
07032   /* Get the TIMx CCMR1 register value */
07033   tmpccmrx = TIMx->CCMR1;
07034
07035   /* Reset the Output Compare Mode Bits */
07036   tmpccmrx &= ~TIM_CCMR1_OC1M;
07037   tmpccmrx &= ~TIM_CCMR1_CC1S;
07038   /* Select the Output Compare Mode */
07039   tmpccmrx |= OC_Config->OCMode;
07040
07041   /* Reset the Output Polarity level */
07042   tmpccer &= ~TIM_CCER_CC1P;
07043   /* Set the Output Compare Polarity */
07044   tmpccer |= OC_Config->OCPolarity;
07045
07046   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
07047   {
07048     /* Check parameters */
07049     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
07050
07051     /* Reset the Output N Polarity level */
07052     tmpccer &= ~TIM_CCER_CC1NP;
07053     /* Set the Output N Polarity */
07054     tmpccer |= OC_Config->OCNPolarity;
07055     /* Reset the Output N State */
07056     tmpccer &= ~TIM_CCER_CC1NE;
07057   }
07058
07059   if (IS_TIM_BREAK_INSTANCE(TIMx))
07060   {
07061     /* Check parameters */
07062     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
07063     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
07064
07065     /* Reset the Output Compare and Output Compare N IDLE State */
07066     tmpcr2 &= ~TIM_CR2_OIS1;
07067     tmpcr2 &= ~TIM_CR2_OIS1N;
07068     /* Set the Output Idle state */
07069     tmpcr2 |= OC_Config->OCIdleState;
07070     /* Set the Output N Idle state */
07071     tmpcr2 |= OC_Config->OCNIdleState;
07072   }
07073
07074   /* Write to TIMx CR2 */
07075   TIMx->CR2 = tmpcr2;
07076
07077   /* Write to TIMx CCMR1 */
07078   TIMx->CCMR1 = tmpccmrx;
07079
07080   /* Set the Capture Compare Register value */
07081   TIMx->CCR1 = OC_Config->Pulse;
07082
07083   /* Write to TIMx CCER */
07084   TIMx->CCER = tmpccer;
07085 }
07086
07087 /**
07088   * @brief  Timer Output Compare 2 configuration
07089   * @param  TIMx to select the TIM peripheral
07090   * @param  OC_Config The output configuration structure
07091   * @retval None
07092   */
07093 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
07094 {
07095   uint32_t tmpccmrx;
07096   uint32_t tmpccer;
07097   uint32_t tmpcr2;
07098
07099   /* Disable the Channel 2: Reset the CC2E Bit */
07100   TIMx->CCER &= ~TIM_CCER_CC2E;
07101
07102   /* Get the TIMx CCER register value */
07103   tmpccer = TIMx->CCER;
07104   /* Get the TIMx CR2 register value */
07105   tmpcr2 =  TIMx->CR2;
07106
07107   /* Get the TIMx CCMR1 register value */
07108   tmpccmrx = TIMx->CCMR1;
07109
07110   /* Reset the Output Compare mode and Capture/Compare selection Bits */
07111   tmpccmrx &= ~TIM_CCMR1_OC2M;
07112   tmpccmrx &= ~TIM_CCMR1_CC2S;
07113
07114   /* Select the Output Compare Mode */
07115   tmpccmrx |= (OC_Config->OCMode << 8U);
07116
07117   /* Reset the Output Polarity level */
07118   tmpccer &= ~TIM_CCER_CC2P;
07119   /* Set the Output Compare Polarity */
07120   tmpccer |= (OC_Config->OCPolarity << 4U);
07121
07122   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
07123   {
07124     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
07125
07126     /* Reset the Output N Polarity level */
07127     tmpccer &= ~TIM_CCER_CC2NP;
07128     /* Set the Output N Polarity */
07129     tmpccer |= (OC_Config->OCNPolarity << 4U);
07130     /* Reset the Output N State */
07131     tmpccer &= ~TIM_CCER_CC2NE;
07132
07133   }
07134
07135   if (IS_TIM_BREAK_INSTANCE(TIMx))
07136   {
07137     /* Check parameters */
07138     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
07139     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
07140
07141     /* Reset the Output Compare and Output Compare N IDLE State */
07142     tmpcr2 &= ~TIM_CR2_OIS2;
07143     tmpcr2 &= ~TIM_CR2_OIS2N;
07144     /* Set the Output Idle state */
07145     tmpcr2 |= (OC_Config->OCIdleState << 2U);
07146     /* Set the Output N Idle state */
07147     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
07148   }
07149
07150   /* Write to TIMx CR2 */
07151   TIMx->CR2 = tmpcr2;
07152
07153   /* Write to TIMx CCMR1 */
07154   TIMx->CCMR1 = tmpccmrx;
07155
07156   /* Set the Capture Compare Register value */
07157   TIMx->CCR2 = OC_Config->Pulse;
07158
07159   /* Write to TIMx CCER */
07160   TIMx->CCER = tmpccer;
07161 }
07162
07163 /**
07164   * @brief  Timer Output Compare 3 configuration
07165   * @param  TIMx to select the TIM peripheral
07166   * @param  OC_Config The output configuration structure
07167   * @retval None
07168   */
07169 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
07170 {
07171   uint32_t tmpccmrx;
07172   uint32_t tmpccer;
07173   uint32_t tmpcr2;
07174
07175   /* Disable the Channel 3: Reset the CC2E Bit */
07176   TIMx->CCER &= ~TIM_CCER_CC3E;
07177
07178   /* Get the TIMx CCER register value */
07179   tmpccer = TIMx->CCER;
07180   /* Get the TIMx CR2 register value */
07181   tmpcr2 =  TIMx->CR2;
07182
07183   /* Get the TIMx CCMR2 register value */
07184   tmpccmrx = TIMx->CCMR2;
07185
07186   /* Reset the Output Compare mode and Capture/Compare selection Bits */
07187   tmpccmrx &= ~TIM_CCMR2_OC3M;
07188   tmpccmrx &= ~TIM_CCMR2_CC3S;
07189   /* Select the Output Compare Mode */
07190   tmpccmrx |= OC_Config->OCMode;
07191
07192   /* Reset the Output Polarity level */
07193   tmpccer &= ~TIM_CCER_CC3P;
07194   /* Set the Output Compare Polarity */
07195   tmpccer |= (OC_Config->OCPolarity << 8U);
07196
07197   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
07198   {
07199     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
07200
07201     /* Reset the Output N Polarity level */
07202     tmpccer &= ~TIM_CCER_CC3NP;
07203     /* Set the Output N Polarity */
07204     tmpccer |= (OC_Config->OCNPolarity << 8U);
07205     /* Reset the Output N State */
07206     tmpccer &= ~TIM_CCER_CC3NE;
07207   }
07208
07209   if (IS_TIM_BREAK_INSTANCE(TIMx))
07210   {
07211     /* Check parameters */
07212     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
07213     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
07214
07215     /* Reset the Output Compare and Output Compare N IDLE State */
07216     tmpcr2 &= ~TIM_CR2_OIS3;
07217     tmpcr2 &= ~TIM_CR2_OIS3N;
07218     /* Set the Output Idle state */
07219     tmpcr2 |= (OC_Config->OCIdleState << 4U);
07220     /* Set the Output N Idle state */
07221     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
07222   }
07223
07224   /* Write to TIMx CR2 */
07225   TIMx->CR2 = tmpcr2;
07226
07227   /* Write to TIMx CCMR2 */
07228   TIMx->CCMR2 = tmpccmrx;
07229
07230   /* Set the Capture Compare Register value */
07231   TIMx->CCR3 = OC_Config->Pulse;
07232
07233   /* Write to TIMx CCER */
07234   TIMx->CCER = tmpccer;
07235 }
07236
07237 /**
07238   * @brief  Timer Output Compare 4 configuration
07239   * @param  TIMx to select the TIM peripheral
07240   * @param  OC_Config The output configuration structure
07241   * @retval None
07242   */
07243 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
07244 {
07245   uint32_t tmpccmrx;
07246   uint32_t tmpccer;
07247   uint32_t tmpcr2;
07248
07249   /* Disable the Channel 4: Reset the CC4E Bit */
07250   TIMx->CCER &= ~TIM_CCER_CC4E;
07251
07252   /* Get the TIMx CCER register value */
07253   tmpccer = TIMx->CCER;
07254   /* Get the TIMx CR2 register value */
07255   tmpcr2 =  TIMx->CR2;
07256
07257   /* Get the TIMx CCMR2 register value */
07258   tmpccmrx = TIMx->CCMR2;
07259
07260   /* Reset the Output Compare mode and Capture/Compare selection Bits */
07261   tmpccmrx &= ~TIM_CCMR2_OC4M;
07262   tmpccmrx &= ~TIM_CCMR2_CC4S;
07263
07264   /* Select the Output Compare Mode */
07265   tmpccmrx |= (OC_Config->OCMode << 8U);
07266
07267   /* Reset the Output Polarity level */
07268   tmpccer &= ~TIM_CCER_CC4P;
07269   /* Set the Output Compare Polarity */
07270   tmpccer |= (OC_Config->OCPolarity << 12U);
07271
07272   if (IS_TIM_BREAK_INSTANCE(TIMx))
07273   {
07274     /* Check parameters */
07275     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
07276
07277     /* Reset the Output Compare IDLE State */
07278     tmpcr2 &= ~TIM_CR2_OIS4;
07279
07280     /* Set the Output Idle state */
07281     tmpcr2 |= (OC_Config->OCIdleState << 6U);
07282   }
07283
07284   /* Write to TIMx CR2 */
07285   TIMx->CR2 = tmpcr2;
07286
07287   /* Write to TIMx CCMR2 */
07288   TIMx->CCMR2 = tmpccmrx;
07289
07290   /* Set the Capture Compare Register value */
07291   TIMx->CCR4 = OC_Config->Pulse;
07292
07293   /* Write to TIMx CCER */
07294   TIMx->CCER = tmpccer;
07295 }
07296
07297 /**
07298   * @brief  Timer Output Compare 5 configuration
07299   * @param  TIMx to select the TIM peripheral
07300   * @param  OC_Config The output configuration structure
07301   * @retval None
07302   */
07303 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
07304                               const TIM_OC_InitTypeDef *OC_Config)
07305 {
07306   uint32_t tmpccmrx;
07307   uint32_t tmpccer;
07308   uint32_t tmpcr2;
07309
07310   /* Disable the output: Reset the CCxE Bit */
07311   TIMx->CCER &= ~TIM_CCER_CC5E;
07312
07313   /* Get the TIMx CCER register value */
07314   tmpccer = TIMx->CCER;
07315   /* Get the TIMx CR2 register value */
07316   tmpcr2 =  TIMx->CR2;
07317   /* Get the TIMx CCMR1 register value */
07318   tmpccmrx = TIMx->CCMR3;
07319
07320   /* Reset the Output Compare Mode Bits */
07321   tmpccmrx &= ~(TIM_CCMR3_OC5M);
07322   /* Select the Output Compare Mode */
07323   tmpccmrx |= OC_Config->OCMode;
07324
07325   /* Reset the Output Polarity level */
07326   tmpccer &= ~TIM_CCER_CC5P;
07327   /* Set the Output Compare Polarity */
07328   tmpccer |= (OC_Config->OCPolarity << 16U);
07329
07330   if (IS_TIM_BREAK_INSTANCE(TIMx))
07331   {
07332     /* Reset the Output Compare IDLE State */
07333     tmpcr2 &= ~TIM_CR2_OIS5;
07334     /* Set the Output Idle state */
07335     tmpcr2 |= (OC_Config->OCIdleState << 8U);
07336   }
07337   /* Write to TIMx CR2 */
07338   TIMx->CR2 = tmpcr2;
07339
07340   /* Write to TIMx CCMR3 */
07341   TIMx->CCMR3 = tmpccmrx;
07342
07343   /* Set the Capture Compare Register value */
07344   TIMx->CCR5 = OC_Config->Pulse;
07345
07346   /* Write to TIMx CCER */
07347   TIMx->CCER = tmpccer;
07348 }
07349
07350 /**
07351   * @brief  Timer Output Compare 6 configuration
07352   * @param  TIMx to select the TIM peripheral
07353   * @param  OC_Config The output configuration structure
07354   * @retval None
07355   */
07356 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
07357                               const TIM_OC_InitTypeDef *OC_Config)
07358 {
07359   uint32_t tmpccmrx;
07360   uint32_t tmpccer;
07361   uint32_t tmpcr2;
07362
07363   /* Disable the output: Reset the CCxE Bit */
07364   TIMx->CCER &= ~TIM_CCER_CC6E;
07365
07366   /* Get the TIMx CCER register value */
07367   tmpccer = TIMx->CCER;
07368   /* Get the TIMx CR2 register value */
07369   tmpcr2 =  TIMx->CR2;
07370   /* Get the TIMx CCMR1 register value */
07371   tmpccmrx = TIMx->CCMR3;
07372
07373   /* Reset the Output Compare Mode Bits */
07374   tmpccmrx &= ~(TIM_CCMR3_OC6M);
07375   /* Select the Output Compare Mode */
07376   tmpccmrx |= (OC_Config->OCMode << 8U);
07377
07378   /* Reset the Output Polarity level */
07379   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
07380   /* Set the Output Compare Polarity */
07381   tmpccer |= (OC_Config->OCPolarity << 20U);
07382
07383   if (IS_TIM_BREAK_INSTANCE(TIMx))
07384   {
07385     /* Reset the Output Compare IDLE State */
07386     tmpcr2 &= ~TIM_CR2_OIS6;
07387     /* Set the Output Idle state */
07388     tmpcr2 |= (OC_Config->OCIdleState << 10U);
07389   }
07390
07391   /* Write to TIMx CR2 */
07392   TIMx->CR2 = tmpcr2;
07393
07394   /* Write to TIMx CCMR3 */
07395   TIMx->CCMR3 = tmpccmrx;
07396
07397   /* Set the Capture Compare Register value */
07398   TIMx->CCR6 = OC_Config->Pulse;
07399
07400   /* Write to TIMx CCER */
07401   TIMx->CCER = tmpccer;
07402 }
07403
07404 /**
07405   * @brief  Slave Timer configuration function
07406   * @param  htim TIM handle
07407   * @param  sSlaveConfig Slave timer configuration
07408   * @retval None
07409   */
07410 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
07411                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig)
07412 {
07413   HAL_StatusTypeDef status = HAL_OK;
07414   uint32_t tmpsmcr;
07415   uint32_t tmpccmr1;
07416   uint32_t tmpccer;
07417
07418   /* Get the TIMx SMCR register value */
07419   tmpsmcr = htim->Instance->SMCR;
07420
07421   /* Reset the Trigger Selection Bits */
07422   tmpsmcr &= ~TIM_SMCR_TS;
07423   /* Set the Input Trigger source */
07424   tmpsmcr |= sSlaveConfig->InputTrigger;
07425
07426   /* Reset the slave mode Bits */
07427   tmpsmcr &= ~TIM_SMCR_SMS;
07428   /* Set the slave mode */
07429   tmpsmcr |= sSlaveConfig->SlaveMode;
07430
07431   /* Write to TIMx SMCR */
07432   htim->Instance->SMCR = tmpsmcr;
07433
07434   /* Configure the trigger prescaler, filter, and polarity */
07435   switch (sSlaveConfig->InputTrigger)
07436   {
07437     case TIM_TS_ETRF:
07438     {
07439       /* Check the parameters */
07440       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
07441       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
07442       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
07443       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
07444       /* Configure the ETR Trigger source */
07445       TIM_ETR_SetConfig(htim->Instance,
07446                         sSlaveConfig->TriggerPrescaler,
07447                         sSlaveConfig->TriggerPolarity,
07448                         sSlaveConfig->TriggerFilter);
07449       break;
07450     }
07451
07452     case TIM_TS_TI1F_ED:
07453     {
07454       /* Check the parameters */
07455       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
07456       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
07457
07458       if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
07459       {
07460         return HAL_ERROR;
07461       }
07462
07463       /* Disable the Channel 1: Reset the CC1E Bit */
07464       tmpccer = htim->Instance->CCER;
07465       htim->Instance->CCER &= ~TIM_CCER_CC1E;
07466       tmpccmr1 = htim->Instance->CCMR1;
07467
07468       /* Set the filter */
07469       tmpccmr1 &= ~TIM_CCMR1_IC1F;
07470       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
07471
07472       /* Write to TIMx CCMR1 and CCER registers */
07473       htim->Instance->CCMR1 = tmpccmr1;
07474       htim->Instance->CCER = tmpccer;
07475       break;
07476     }
07477
07478     case TIM_TS_TI1FP1:
07479     {
07480       /* Check the parameters */
07481       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
07482       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
07483       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
07484
07485       /* Configure TI1 Filter and Polarity */
07486       TIM_TI1_ConfigInputStage(htim->Instance,
07487                                sSlaveConfig->TriggerPolarity,
07488                                sSlaveConfig->TriggerFilter);
07489       break;
07490     }
07491
07492     case TIM_TS_TI2FP2:
07493     {
07494       /* Check the parameters */
07495       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
07496       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
07497       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
07498
07499       /* Configure TI2 Filter and Polarity */
07500       TIM_TI2_ConfigInputStage(htim->Instance,
07501                                sSlaveConfig->TriggerPolarity,
07502                                sSlaveConfig->TriggerFilter);
07503       break;
07504     }
07505
07506     case TIM_TS_ITR0:
07507     case TIM_TS_ITR1:
07508     case TIM_TS_ITR2:
07509     case TIM_TS_ITR3:
07510     {
07511       /* Check the parameter */
07512       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
07513       break;
07514     }
07515
07516     default:
07517       status = HAL_ERROR;
07518       break;
07519   }
07520
07521   return status;
07522 }
07523
07524 /**
07525   * @brief  Configure the TI1 as Input.
07526   * @param  TIMx to select the TIM peripheral.
07527   * @param  TIM_ICPolarity The Input Polarity.
07528   *          This parameter can be one of the following values:
07529   *            @arg TIM_ICPOLARITY_RISING
07530   *            @arg TIM_ICPOLARITY_FALLING
07531   *            @arg TIM_ICPOLARITY_BOTHEDGE
07532   * @param  TIM_ICSelection specifies the input to be used.
07533   *          This parameter can be one of the following values:
07534   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
07535   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
07536   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
07537   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07538   *          This parameter must be a value between 0x00 and 0x0F.
07539   * @retval None
07540   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
07541   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
07542   *        protected against un-initialized filter and polarity values.
07543   */
07544 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
07545                        uint32_t TIM_ICFilter)
07546 {
07547   uint32_t tmpccmr1;
07548   uint32_t tmpccer;
07549
07550   /* Disable the Channel 1: Reset the CC1E Bit */
07551   TIMx->CCER &= ~TIM_CCER_CC1E;
07552   tmpccmr1 = TIMx->CCMR1;
07553   tmpccer = TIMx->CCER;
07554
07555   /* Select the Input */
07556   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
07557   {
07558     tmpccmr1 &= ~TIM_CCMR1_CC1S;
07559     tmpccmr1 |= TIM_ICSelection;
07560   }
07561   else
07562   {
07563     tmpccmr1 |= TIM_CCMR1_CC1S_0;
07564   }
07565
07566   /* Set the filter */
07567   tmpccmr1 &= ~TIM_CCMR1_IC1F;
07568   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
07569
07570   /* Select the Polarity and set the CC1E Bit */
07571   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
07572   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
07573
07574   /* Write to TIMx CCMR1 and CCER registers */
07575   TIMx->CCMR1 = tmpccmr1;
07576   TIMx->CCER = tmpccer;
07577 }
07578
07579 /**
07580   * @brief  Configure the Polarity and Filter for TI1.
07581   * @param  TIMx to select the TIM peripheral.
07582   * @param  TIM_ICPolarity The Input Polarity.
07583   *          This parameter can be one of the following values:
07584   *            @arg TIM_ICPOLARITY_RISING
07585   *            @arg TIM_ICPOLARITY_FALLING
07586   *            @arg TIM_ICPOLARITY_BOTHEDGE
07587   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07588   *          This parameter must be a value between 0x00 and 0x0F.
07589   * @retval None
07590   */
07591 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
07592 {
07593   uint32_t tmpccmr1;
07594   uint32_t tmpccer;
07595
07596   /* Disable the Channel 1: Reset the CC1E Bit */
07597   tmpccer = TIMx->CCER;
07598   TIMx->CCER &= ~TIM_CCER_CC1E;
07599   tmpccmr1 = TIMx->CCMR1;
07600
07601   /* Set the filter */
07602   tmpccmr1 &= ~TIM_CCMR1_IC1F;
07603   tmpccmr1 |= (TIM_ICFilter << 4U);
07604
07605   /* Select the Polarity and set the CC1E Bit */
07606   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
07607   tmpccer |= TIM_ICPolarity;
07608
07609   /* Write to TIMx CCMR1 and CCER registers */
07610   TIMx->CCMR1 = tmpccmr1;
07611   TIMx->CCER = tmpccer;
07612 }
07613
07614 /**
07615   * @brief  Configure the TI2 as Input.
07616   * @param  TIMx to select the TIM peripheral
07617   * @param  TIM_ICPolarity The Input Polarity.
07618   *          This parameter can be one of the following values:
07619   *            @arg TIM_ICPOLARITY_RISING
07620   *            @arg TIM_ICPOLARITY_FALLING
07621   *            @arg TIM_ICPOLARITY_BOTHEDGE
07622   * @param  TIM_ICSelection specifies the input to be used.
07623   *          This parameter can be one of the following values:
07624   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
07625   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
07626   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
07627   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07628   *          This parameter must be a value between 0x00 and 0x0F.
07629   * @retval None
07630   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
07631   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
07632   *        protected against un-initialized filter and polarity values.
07633   */
07634 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
07635                               uint32_t TIM_ICFilter)
07636 {
07637   uint32_t tmpccmr1;
07638   uint32_t tmpccer;
07639
07640   /* Disable the Channel 2: Reset the CC2E Bit */
07641   TIMx->CCER &= ~TIM_CCER_CC2E;
07642   tmpccmr1 = TIMx->CCMR1;
07643   tmpccer = TIMx->CCER;
07644
07645   /* Select the Input */
07646   tmpccmr1 &= ~TIM_CCMR1_CC2S;
07647   tmpccmr1 |= (TIM_ICSelection << 8U);
07648
07649   /* Set the filter */
07650   tmpccmr1 &= ~TIM_CCMR1_IC2F;
07651   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
07652
07653   /* Select the Polarity and set the CC2E Bit */
07654   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
07655   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
07656
07657   /* Write to TIMx CCMR1 and CCER registers */
07658   TIMx->CCMR1 = tmpccmr1 ;
07659   TIMx->CCER = tmpccer;
07660 }
07661
07662 /**
07663   * @brief  Configure the Polarity and Filter for TI2.
07664   * @param  TIMx to select the TIM peripheral.
07665   * @param  TIM_ICPolarity The Input Polarity.
07666   *          This parameter can be one of the following values:
07667   *            @arg TIM_ICPOLARITY_RISING
07668   *            @arg TIM_ICPOLARITY_FALLING
07669   *            @arg TIM_ICPOLARITY_BOTHEDGE
07670   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07671   *          This parameter must be a value between 0x00 and 0x0F.
07672   * @retval None
07673   */
07674 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
07675 {
07676   uint32_t tmpccmr1;
07677   uint32_t tmpccer;
07678
07679   /* Disable the Channel 2: Reset the CC2E Bit */
07680   TIMx->CCER &= ~TIM_CCER_CC2E;
07681   tmpccmr1 = TIMx->CCMR1;
07682   tmpccer = TIMx->CCER;
07683
07684   /* Set the filter */
07685   tmpccmr1 &= ~TIM_CCMR1_IC2F;
07686   tmpccmr1 |= (TIM_ICFilter << 12U);
07687
07688   /* Select the Polarity and set the CC2E Bit */
07689   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
07690   tmpccer |= (TIM_ICPolarity << 4U);
07691
07692   /* Write to TIMx CCMR1 and CCER registers */
07693   TIMx->CCMR1 = tmpccmr1 ;
07694   TIMx->CCER = tmpccer;
07695 }
07696
07697 /**
07698   * @brief  Configure the TI3 as Input.
07699   * @param  TIMx to select the TIM peripheral
07700   * @param  TIM_ICPolarity The Input Polarity.
07701   *          This parameter can be one of the following values:
07702   *            @arg TIM_ICPOLARITY_RISING
07703   *            @arg TIM_ICPOLARITY_FALLING
07704   *            @arg TIM_ICPOLARITY_BOTHEDGE
07705   * @param  TIM_ICSelection specifies the input to be used.
07706   *          This parameter can be one of the following values:
07707   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
07708   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
07709   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
07710   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07711   *          This parameter must be a value between 0x00 and 0x0F.
07712   * @retval None
07713   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
07714   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
07715   *        protected against un-initialized filter and polarity values.
07716   */
07717 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
07718                               uint32_t TIM_ICFilter)
07719 {
07720   uint32_t tmpccmr2;
07721   uint32_t tmpccer;
07722
07723   /* Disable the Channel 3: Reset the CC3E Bit */
07724   TIMx->CCER &= ~TIM_CCER_CC3E;
07725   tmpccmr2 = TIMx->CCMR2;
07726   tmpccer = TIMx->CCER;
07727
07728   /* Select the Input */
07729   tmpccmr2 &= ~TIM_CCMR2_CC3S;
07730   tmpccmr2 |= TIM_ICSelection;
07731
07732   /* Set the filter */
07733   tmpccmr2 &= ~TIM_CCMR2_IC3F;
07734   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
07735
07736   /* Select the Polarity and set the CC3E Bit */
07737   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
07738   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
07739
07740   /* Write to TIMx CCMR2 and CCER registers */
07741   TIMx->CCMR2 = tmpccmr2;
07742   TIMx->CCER = tmpccer;
07743 }
07744
07745 /**
07746   * @brief  Configure the TI4 as Input.
07747   * @param  TIMx to select the TIM peripheral
07748   * @param  TIM_ICPolarity The Input Polarity.
07749   *          This parameter can be one of the following values:
07750   *            @arg TIM_ICPOLARITY_RISING
07751   *            @arg TIM_ICPOLARITY_FALLING
07752   *            @arg TIM_ICPOLARITY_BOTHEDGE
07753   * @param  TIM_ICSelection specifies the input to be used.
07754   *          This parameter can be one of the following values:
07755   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
07756   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
07757   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
07758   * @param  TIM_ICFilter Specifies the Input Capture Filter.
07759   *          This parameter must be a value between 0x00 and 0x0F.
07760   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
07761   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
07762   *        protected against un-initialized filter and polarity values.
07763   * @retval None
07764   */
07765 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
07766                               uint32_t TIM_ICFilter)
07767 {
07768   uint32_t tmpccmr2;
07769   uint32_t tmpccer;
07770
07771   /* Disable the Channel 4: Reset the CC4E Bit */
07772   TIMx->CCER &= ~TIM_CCER_CC4E;
07773   tmpccmr2 = TIMx->CCMR2;
07774   tmpccer = TIMx->CCER;
07775
07776   /* Select the Input */
07777   tmpccmr2 &= ~TIM_CCMR2_CC4S;
07778   tmpccmr2 |= (TIM_ICSelection << 8U);
07779
07780   /* Set the filter */
07781   tmpccmr2 &= ~TIM_CCMR2_IC4F;
07782   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
07783
07784   /* Select the Polarity and set the CC4E Bit */
07785   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
07786   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
07787
07788   /* Write to TIMx CCMR2 and CCER registers */
07789   TIMx->CCMR2 = tmpccmr2;
07790   TIMx->CCER = tmpccer ;
07791 }
07792
07793 /**
07794   * @brief  Selects the Input Trigger source
07795   * @param  TIMx to select the TIM peripheral
07796   * @param  InputTriggerSource The Input Trigger source.
07797   *          This parameter can be one of the following values:
07798   *            @arg TIM_TS_ITR0: Internal Trigger 0
07799   *            @arg TIM_TS_ITR1: Internal Trigger 1
07800   *            @arg TIM_TS_ITR2: Internal Trigger 2
07801   *            @arg TIM_TS_ITR3: Internal Trigger 3
07802   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
07803   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
07804   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
07805   *            @arg TIM_TS_ETRF: External Trigger input
07806   * @retval None
07807   */
07808 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
07809 {
07810   uint32_t tmpsmcr;
07811
07812   /* Get the TIMx SMCR register value */
07813   tmpsmcr = TIMx->SMCR;
07814   /* Reset the TS Bits */
07815   tmpsmcr &= ~TIM_SMCR_TS;
07816   /* Set the Input Trigger source and the slave mode*/
07817   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
07818   /* Write to TIMx SMCR */
07819   TIMx->SMCR = tmpsmcr;
07820 }
07821 /**
07822   * @brief  Configures the TIMx External Trigger (ETR).
07823   * @param  TIMx to select the TIM peripheral
07824   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
07825   *          This parameter can be one of the following values:
07826   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
07827   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
07828   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
07829   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
07830   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
07831   *          This parameter can be one of the following values:
07832   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
07833   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
07834   * @param  ExtTRGFilter External Trigger Filter.
07835   *          This parameter must be a value between 0x00 and 0x0F
07836   * @retval None
07837   */
07838 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
07839                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
07840 {
07841   uint32_t tmpsmcr;
07842
07843   tmpsmcr = TIMx->SMCR;
07844
07845   /* Reset the ETR Bits */
07846   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
07847
07848   /* Set the Prescaler, the Filter value and the Polarity */
07849   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
07850
07851   /* Write to TIMx SMCR */
07852   TIMx->SMCR = tmpsmcr;
07853 }
07854
07855 /**
07856   * @brief  Enables or disables the TIM Capture Compare Channel x.
07857   * @param  TIMx to select the TIM peripheral
07858   * @param  Channel specifies the TIM Channel
07859   *          This parameter can be one of the following values:
07860   *            @arg TIM_CHANNEL_1: TIM Channel 1
07861   *            @arg TIM_CHANNEL_2: TIM Channel 2
07862   *            @arg TIM_CHANNEL_3: TIM Channel 3
07863   *            @arg TIM_CHANNEL_4: TIM Channel 4
07864   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
07865   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
07866   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
07867   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
07868   * @retval None
07869   */
07870 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
07871 {
07872   uint32_t tmp;
07873
07874   /* Check the parameters */
07875   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
07876   assert_param(IS_TIM_CHANNELS(Channel));
07877
07878   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
07879
07880   /* Reset the CCxE Bit */
07881   TIMx->CCER &= ~tmp;
07882
07883   /* Set or reset the CCxE Bit */
07884   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
07885 }
07886
07887 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
07888 /**
07889   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
07890   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
07891   *                the configuration information for TIM module.
07892   * @retval None
07893   */
07894 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
07895 {
07896   /* Reset the TIM callback to the legacy weak callbacks */
07897   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
07898   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
07899   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
07900   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
07901   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
07902   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
07903   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
07904   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
07905   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
07906   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
07907   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
07908   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
07909   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
07910   htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
07911 }
07912 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
07913
07914 /**
07915   * @}
07916   */
07917
07918 #endif /* HAL_TIM_MODULE_ENABLED */
07919 /**
07920   * @}
07921   */
07922
07923 /**
07924   * @}
07925   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_tim.h Source File

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stm32g0xx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_TIM_H
00021 #define STM32G0xx_HAL_TIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup TIM
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup TIM_Exported_Types TIM Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  TIM Time base Configuration Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00049                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00050
00051   uint32_t CounterMode;       /*!< Specifies the counter mode.
00052                                    This parameter can be a value of @ref TIM_Counter_Mode */
00053
00054   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00055                                    Auto-Reload Register at the next update event.
00056                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00057
00058   uint32_t ClockDivision;     /*!< Specifies the clock division.
00059                                    This parameter can be a value of @ref TIM_ClockDivision */
00060
00061   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00062                                     reaches zero, an update event is generated and counting restarts
00063                                     from the RCR value (N).
00064                                     This means in PWM mode that (N+1) corresponds to:
00065                                         - the number of PWM periods in edge-aligned mode
00066                                         - the number of half PWM period in center-aligned mode
00067                                      GP timers: this parameter must be a number between Min_Data = 0x00 and
00068                                      Max_Data = 0xFF.
00069                                      Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
00070                                      Max_Data = 0xFFFF. */
00071
00072   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
00073                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
00074 } TIM_Base_InitTypeDef;
00075
00076 /**
00077   * @brief  TIM Output Compare Configuration Structure definition
00078   */
00079 typedef struct
00080 {
00081   uint32_t OCMode;        /*!< Specifies the TIM mode.
00082                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00083
00084   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00085                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00086
00087   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00088                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00089
00090   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00091                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00092                                @note This parameter is valid only for timer instances supporting break feature. */
00093
00094   uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
00095                                This parameter can be a value of @ref TIM_Output_Fast_State
00096                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00097
00098
00099   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00100                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00101                                @note This parameter is valid only for timer instances supporting break feature. */
00102
00103   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00104                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00105                                @note This parameter is valid only for timer instances supporting break feature. */
00106 } TIM_OC_InitTypeDef;
00107
00108 /**
00109   * @brief  TIM One Pulse Mode Configuration Structure definition
00110   */
00111 typedef struct
00112 {
00113   uint32_t OCMode;        /*!< Specifies the TIM mode.
00114                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00115
00116   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00117                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00118
00119   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00120                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00121
00122   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00123                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00124                                @note This parameter is valid only for timer instances supporting break feature. */
00125
00126   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00127                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00128                                @note This parameter is valid only for timer instances supporting break feature. */
00129
00130   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00131                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00132                                @note This parameter is valid only for timer instances supporting break feature. */
00133
00134   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00135                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00136
00137   uint32_t ICSelection;   /*!< Specifies the input.
00138                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00139
00140   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00141                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00142 } TIM_OnePulse_InitTypeDef;
00143
00144 /**
00145   * @brief  TIM Input Capture Configuration Structure definition
00146   */
00147 typedef struct
00148 {
00149   uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
00150                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00151
00152   uint32_t ICSelection;  /*!< Specifies the input.
00153                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00154
00155   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00156                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00157
00158   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00159                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00160 } TIM_IC_InitTypeDef;
00161
00162 /**
00163   * @brief  TIM Encoder Configuration Structure definition
00164   */
00165 typedef struct
00166 {
00167   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00168                                This parameter can be a value of @ref TIM_Encoder_Mode */
00169
00170   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00171                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
00172
00173   uint32_t IC1Selection;  /*!< Specifies the input.
00174                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00175
00176   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00177                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00178
00179   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00180                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00181
00182   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00183                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
00184
00185   uint32_t IC2Selection;  /*!< Specifies the input.
00186                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00187
00188   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00189                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00190
00191   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00192                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00193 } TIM_Encoder_InitTypeDef;
00194
00195 /**
00196   * @brief  Clock Configuration Handle Structure definition
00197   */
00198 typedef struct
00199 {
00200   uint32_t ClockSource;     /*!< TIM clock sources
00201                                  This parameter can be a value of @ref TIM_Clock_Source */
00202   uint32_t ClockPolarity;   /*!< TIM clock polarity
00203                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00204   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00205                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00206   uint32_t ClockFilter;     /*!< TIM clock filter
00207                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00208 } TIM_ClockConfigTypeDef;
00209
00210 /**
00211   * @brief  TIM Clear Input Configuration Handle Structure definition
00212   */
00213 typedef struct
00214 {
00215   uint32_t ClearInputState;      /*!< TIM clear Input state
00216                                       This parameter can be ENABLE or DISABLE */
00217   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00218                                       This parameter can be a value of @ref TIM_ClearInput_Source */
00219   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00220                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00221   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00222                                       This parameter must be 0: When OCRef clear feature is used with ETR source,
00223                                       ETR prescaler must be off */
00224   uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
00225                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00226 } TIM_ClearInputConfigTypeDef;
00227
00228 /**
00229   * @brief  TIM Master configuration Structure definition
00230   * @note   Advanced timers provide TRGO2 internal line which is redirected
00231   *         to the ADC
00232   */
00233 typedef struct
00234 {
00235   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00236                                         This parameter can be a value of @ref TIM_Master_Mode_Selection */
00237   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00238                                         This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
00239   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00240                                         This parameter can be a value of @ref TIM_Master_Slave_Mode
00241                                         @note When the Master/slave mode is enabled, the effect of
00242                                         an event on the trigger input (TRGI) is delayed to allow a
00243                                         perfect synchronization between the current timer and its
00244                                         slaves (through TRGO). It is not mandatory in case of timer
00245                                         synchronization mode. */
00246 } TIM_MasterConfigTypeDef;
00247
00248 /**
00249   * @brief  TIM Slave configuration Structure definition
00250   */
00251 typedef struct
00252 {
00253   uint32_t  SlaveMode;         /*!< Slave mode selection
00254                                     This parameter can be a value of @ref TIM_Slave_Mode */
00255   uint32_t  InputTrigger;      /*!< Input Trigger source
00256                                     This parameter can be a value of @ref TIM_Trigger_Selection */
00257   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00258                                     This parameter can be a value of @ref TIM_Trigger_Polarity */
00259   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00260                                     This parameter can be a value of @ref TIM_Trigger_Prescaler */
00261   uint32_t  TriggerFilter;     /*!< Input trigger filter
00262                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
00263
00264 } TIM_SlaveConfigTypeDef;
00265
00266 /**
00267   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00268   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00269   *        filter and polarity.
00270   */
00271 typedef struct
00272 {
00273   uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00274
00275   uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00276
00277   uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
00278
00279   uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00280
00281   uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00282
00283   uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
00284
00285   uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00286
00287   uint32_t BreakAFMode;          /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
00288
00289   uint32_t Break2State;          /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
00290
00291   uint32_t Break2Polarity;       /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
00292
00293   uint32_t Break2Filter;         /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00294
00295   uint32_t Break2AFMode;         /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
00296
00297   uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00298
00299 } TIM_BreakDeadTimeConfigTypeDef;
00300
00301 /**
00302   * @brief  HAL State structures definition
00303   */
00304 typedef enum
00305 {
00306   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00307   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00308   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00309   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00310   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
00311 } HAL_TIM_StateTypeDef;
00312
00313 /**
00314   * @brief  TIM Channel States definition
00315   */
00316 typedef enum
00317 {
00318   HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
00319   HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
00320   HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
00321 } HAL_TIM_ChannelStateTypeDef;
00322
00323 /**
00324   * @brief  DMA Burst States definition
00325   */
00326 typedef enum
00327 {
00328   HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
00329   HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
00330   HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
00331 } HAL_TIM_DMABurstStateTypeDef;
00332
00333 /**
00334   * @brief  HAL Active channel structures definition
00335   */
00336 typedef enum
00337 {
00338   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
00339   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
00340   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
00341   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
00342   HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
00343   HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
00344   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
00345 } HAL_TIM_ActiveChannel;
00346
00347 /**
00348   * @brief  TIM Time Base Handle Structure definition
00349   */
00350 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00351 typedef struct __TIM_HandleTypeDef
00352 #else
00353 typedef struct
00354 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00355 {
00356   TIM_TypeDef                        *Instance;         /*!< Register base address                             */
00357   TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
00358   HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
00359   DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
00360                                                              This array is accessed by a @ref DMA_Handle_index */
00361   HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
00362   __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
00363   __IO HAL_TIM_ChannelStateTypeDef   ChannelState[6];   /*!< TIM channel operation state                       */
00364   __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
00365   __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
00366
00367 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00368   void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
00369   void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
00370   void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
00371   void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
00372   void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
00373   void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
00374   void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
00375   void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
00376   void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
00377   void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
00378   void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
00379   void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
00380   void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
00381   void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
00382   void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
00383   void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
00384   void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
00385   void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
00386   void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
00387   void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
00388   void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
00389   void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
00390   void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
00391   void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
00392   void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
00393   void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
00394   void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
00395   void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
00396 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00397 } TIM_HandleTypeDef;
00398
00399 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00400 /**
00401   * @brief  HAL TIM Callback ID enumeration definition
00402   */
00403 typedef enum
00404 {
00405   HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */
00406   , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */
00407   , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */
00408   , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */
00409   , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */
00410   , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */
00411   , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */
00412   , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */
00413   , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */
00414   , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */
00415   , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */
00416   , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */
00417   , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
00418   , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
00419   , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
00420   , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
00421   , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
00422   , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
00423
00424   , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
00425   , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
00426   , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
00427   , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */
00428   , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
00429   , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
00430   , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
00431   , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
00432   , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
00433   , HAL_TIM_BREAK2_CB_ID                  = 0x1BU   /*!< TIM Break2 Callback ID                                     */
00434 } HAL_TIM_CallbackIDTypeDef;
00435
00436 /**
00437   * @brief  HAL TIM Callback pointer definition
00438   */
00439 typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
00440
00441 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00442
00443 /**
00444   * @}
00445   */
00446 /* End of exported types -----------------------------------------------------*/
00447
00448 /* Exported constants --------------------------------------------------------*/
00449 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00450   * @{
00451   */
00452
00453 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
00454   * @{
00455   */
00456 #define TIM_CLEARINPUTSOURCE_NONE           0x10000000U           /*!< OCREF_CLR is disabled */
00457 #define TIM_CLEARINPUTSOURCE_ETR            0x20000000U           /*!< OCREF_CLR is connected to ETRF input */
00458 #if defined(COMP1) && defined(COMP2) && defined(COMP3)
00459 #define TIM_CLEARINPUTSOURCE_COMP1          0x00000000U           /*!< OCREF_CLR_INT is connected to COMP1 output */
00460 #define TIM_CLEARINPUTSOURCE_COMP2          TIM1_OR1_OCREF_CLR_0  /*!< OCREF_CLR_INT is connected to COMP2 output */
00461 #define TIM_CLEARINPUTSOURCE_COMP3          TIM1_OR1_OCREF_CLR_1  /*!< OCREF_CLR_INT is connected to COMP3 output */
00462 #elif defined(COMP1) && defined(COMP2)
00463 #define TIM_CLEARINPUTSOURCE_COMP1          0x00000000U           /*!< OCREF_CLR_INT is connected to COMP1 output */
00464 #define TIM_CLEARINPUTSOURCE_COMP2          TIM1_OR1_OCREF_CLR    /*!< OCREF_CLR_INT is connected to COMP2 output */
00465 #endif /* COMP1 && COMP2 && COMP3 */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
00471   * @{
00472   */
00473 #define TIM_DMABASE_CR1                    0x00000000U
00474 #define TIM_DMABASE_CR2                    0x00000001U
00475 #define TIM_DMABASE_SMCR                   0x00000002U
00476 #define TIM_DMABASE_DIER                   0x00000003U
00477 #define TIM_DMABASE_SR                     0x00000004U
00478 #define TIM_DMABASE_EGR                    0x00000005U
00479 #define TIM_DMABASE_CCMR1                  0x00000006U
00480 #define TIM_DMABASE_CCMR2                  0x00000007U
00481 #define TIM_DMABASE_CCER                   0x00000008U
00482 #define TIM_DMABASE_CNT                    0x00000009U
00483 #define TIM_DMABASE_PSC                    0x0000000AU
00484 #define TIM_DMABASE_ARR                    0x0000000BU
00485 #define TIM_DMABASE_RCR                    0x0000000CU
00486 #define TIM_DMABASE_CCR1                   0x0000000DU
00487 #define TIM_DMABASE_CCR2                   0x0000000EU
00488 #define TIM_DMABASE_CCR3                   0x0000000FU
00489 #define TIM_DMABASE_CCR4                   0x00000010U
00490 #define TIM_DMABASE_BDTR                   0x00000011U
00491 #define TIM_DMABASE_DCR                    0x00000012U
00492 #define TIM_DMABASE_DMAR                   0x00000013U
00493 #define TIM_DMABASE_OR1                    0x00000014U
00494 #define TIM_DMABASE_CCMR3                  0x00000015U
00495 #define TIM_DMABASE_CCR5                   0x00000016U
00496 #define TIM_DMABASE_CCR6                   0x00000017U
00497 #define TIM_DMABASE_AF1                    0x00000018U
00498 #define TIM_DMABASE_AF2                    0x00000019U
00499 #define TIM_DMABASE_TISEL                  0x0000001AU
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup TIM_Event_Source TIM Event Source
00505   * @{
00506   */
00507 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00508 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
00509 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
00510 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
00511 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
00512 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00513 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00514 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00515 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00516 /**
00517   * @}
00518   */
00519
00520 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
00521   * @{
00522   */
00523 #define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
00524 #define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
00525 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00531   * @{
00532   */
00533 #define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
00534 #define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
00535 /**
00536   * @}
00537   */
00538
00539 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00540   * @{
00541   */
00542 #define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
00543 #define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
00544 #define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
00545 #define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
00546 /**
00547   * @}
00548   */
00549
00550 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00551   * @{
00552   */
00553 #define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
00554 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
00555 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
00556 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
00557 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
00558 /**
00559   * @}
00560   */
00561
00562 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
00563   * @{
00564   */
00565 #define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
00566 #define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
00567 /**
00568   * @}
00569   */
00570
00571 /** @defgroup TIM_ClockDivision TIM Clock Division
00572   * @{
00573   */
00574 #define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
00575 #define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
00576 #define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00582   * @{
00583   */
00584 #define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
00585 #define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
00591   * @{
00592   */
00593 #define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
00594 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
00595
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00601   * @{
00602   */
00603 #define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
00604 #define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
00605 /**
00606   * @}
00607   */
00608
00609 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
00610   * @{
00611   */
00612 #define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
00613 #define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
00614 /**
00615   * @}
00616   */
00617
00618 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00619   * @{
00620   */
00621 #define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
00622 #define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
00623 /**
00624   * @}
00625   */
00626
00627 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00628   * @{
00629   */
00630 #define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
00631 #define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
00632 /**
00633   * @}
00634   */
00635
00636 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00637   * @{
00638   */
00639 #define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
00640 #define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
00641 /**
00642   * @}
00643   */
00644
00645 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00646   * @{
00647   */
00648 #define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
00649 #define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
00650 /**
00651   * @}
00652   */
00653
00654 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00655   * @{
00656   */
00657 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
00658 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
00659 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
00660 /**
00661   * @}
00662   */
00663
00664 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
00665   * @{
00666   */
00667 #define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
00668 #define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
00669 /**
00670   * @}
00671   */
00672
00673 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00674   * @{
00675   */
00676 #define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
00677 #define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
00678 #define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00684   * @{
00685   */
00686 #define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
00687 #define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
00688 #define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
00689 #define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
00690 /**
00691   * @}
00692   */
00693
00694 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00695   * @{
00696   */
00697 #define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
00698 #define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
00699 /**
00700   * @}
00701   */
00702
00703 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00704   * @{
00705   */
00706 #define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
00707 #define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
00708 #define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
00709 /**
00710   * @}
00711   */
00712
00713 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
00714   * @{
00715   */
00716 #define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
00717 #define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
00718 #define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
00719 #define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
00720 #define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
00721 #define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
00722 #define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
00723 #define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
00724 /**
00725   * @}
00726   */
00727
00728 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00729   * @{
00730   */
00731 #define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
00732 #define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
00733 /**
00734   * @}
00735   */
00736
00737 /** @defgroup TIM_DMA_sources TIM DMA Sources
00738   * @{
00739   */
00740 #define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
00741 #define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
00742 #define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
00743 #define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
00744 #define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
00745 #define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
00746 #define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
00747 /**
00748   * @}
00749   */
00750
00751 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection
00752   * @{
00753   */
00754 #define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
00755 #define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
00756 /**
00757   * @}
00758   */
00759
00760 /** @defgroup TIM_Flag_definition TIM Flag Definition
00761   * @{
00762   */
00763 #define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
00764 #define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
00765 #define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
00766 #define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
00767 #define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
00768 #define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
00769 #define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
00770 #define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
00771 #define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
00772 #define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
00773 #define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
00774 #define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
00775 #define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
00776 #define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
00777 #define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
00778 #define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
00779 /**
00780   * @}
00781   */
00782
00783 /** @defgroup TIM_Channel TIM Channel
00784   * @{
00785   */
00786 #define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
00787 #define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
00788 #define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
00789 #define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
00790 #define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
00791 #define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
00792 #define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
00793 /**
00794   * @}
00795   */
00796
00797 /** @defgroup TIM_Clock_Source TIM Clock Source
00798   * @{
00799   */
00800 #define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
00801 #define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
00802 #define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
00803 #define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
00804 #define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
00805 #define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
00806 #define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
00807 #define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
00808 #define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
00809 #define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
00810 #if defined(USB_BASE)
00811 #define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
00812 #endif /* USB_BASE */
00813 /**
00814   * @}
00815   */
00816
00817 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00818   * @{
00819   */
00820 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
00821 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
00822 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
00823 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00824 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00825 /**
00826   * @}
00827   */
00828
00829 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00830   * @{
00831   */
00832 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
00833 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00834 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00835 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00836 /**
00837   * @}
00838   */
00839
00840 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00841   * @{
00842   */
00843 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
00844 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
00845 /**
00846   * @}
00847   */
00848
00849 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00850   * @{
00851   */
00852 #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
00853 #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00854 #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00855 #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00856 /**
00857   * @}
00858   */
00859
00860 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
00861   * @{
00862   */
00863 #define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
00864 #define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
00865 /**
00866   * @}
00867   */
00868
00869 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
00870   * @{
00871   */
00872 #define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
00873 #define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
00874 /**
00875   * @}
00876   */
00877 /** @defgroup TIM_Lock_level  TIM Lock level
00878   * @{
00879   */
00880 #define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
00881 #define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
00882 #define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
00883 #define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
00884 /**
00885   * @}
00886   */
00887
00888 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
00889   * @{
00890   */
00891 #define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
00892 #define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
00893 /**
00894   * @}
00895   */
00896
00897 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00898   * @{
00899   */
00900 #define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
00901 #define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
00902 /**
00903   * @}
00904   */
00905
00906 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
00907   * @{
00908   */
00909 #define TIM_BREAK_AFMODE_INPUT             0x00000000U                          /*!< Break input BRK in input mode */
00910 #define TIM_BREAK_AFMODE_BIDIRECTIONAL     TIM_BDTR_BKBID                       /*!< Break input BRK in bidirectional mode */
00911 /**
00912   * @}
00913   */
00914
00915 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
00916   * @{
00917   */
00918 #define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
00919 #define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
00920 /**
00921   * @}
00922   */
00923
00924 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
00925   * @{
00926   */
00927 #define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
00928 #define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
00929 /**
00930   * @}
00931   */
00932
00933 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
00934   * @{
00935   */
00936 #define TIM_BREAK2_AFMODE_INPUT            0x00000000U                          /*!< Break2 input BRK2 in input mode */
00937 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL    TIM_BDTR_BK2BID                      /*!< Break2 input BRK2 in bidirectional mode */
00938 /**
00939   * @}
00940   */
00941
00942 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00943   * @{
00944   */
00945 #define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
00946 #define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
00947 /**
00948   * @}
00949   */
00950
00951 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
00952   * @{
00953   */
00954 #define TIM_GROUPCH5_NONE                  0x00000000U                          /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00955 #define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /*!< OC1REFC is the logical AND of OC1REFC and OC5REF    */
00956 #define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /*!< OC2REFC is the logical AND of OC2REFC and OC5REF    */
00957 #define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF    */
00958 /**
00959   * @}
00960   */
00961
00962 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00963   * @{
00964   */
00965 #define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
00966 #define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
00967 #define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
00968 #define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
00969 #define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
00970 #define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
00971 #define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
00972 #define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
00973 /**
00974   * @}
00975   */
00976
00977 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
00978   * @{
00979   */
00980 #define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
00981 #define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
00982 #define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
00983 #define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
00984 #define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
00985 #define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
00986 #define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
00987 #define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
00988 #define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
00989 #define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
00990 #define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
00991 #define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
00992 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
00993 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
00994 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
00995 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
00996 /**
00997   * @}
00998   */
00999
01000 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
01001   * @{
01002   */
01003 #define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
01004 #define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
01005 /**
01006   * @}
01007   */
01008
01009 /** @defgroup TIM_Slave_Mode TIM Slave mode
01010   * @{
01011   */
01012 #define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
01013 #define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
01014 #define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
01015 #define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
01016 #define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
01017 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
01018 /**
01019   * @}
01020   */
01021
01022 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
01023   * @{
01024   */
01025 #define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
01026 #define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
01027 #define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
01028 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
01029 #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
01030 #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
01031 #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
01032 #define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
01033 #define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
01034 #define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
01035 #define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
01036 #define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
01037 #define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
01038 #define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
01039 /**
01040   * @}
01041   */
01042
01043 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
01044   * @{
01045   */
01046 #define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
01047 #define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
01048 #define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
01049 #define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
01050 #if defined(USB_BASE)
01051 #define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
01052 #endif /* USB_BASE */
01053 #define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
01054 #define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
01055 #define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
01056 #define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
01057 #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
01058 /**
01059   * @}
01060   */
01061
01062 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
01063   * @{
01064   */
01065 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
01066 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
01067 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01068 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01069 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
01070 /**
01071   * @}
01072   */
01073
01074 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
01075   * @{
01076   */
01077 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
01078 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
01079 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
01080 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
01081 /**
01082   * @}
01083   */
01084
01085 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
01086   * @{
01087   */
01088 #define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
01089 #define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
01090 /**
01091   * @}
01092   */
01093
01094 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
01095   * @{
01096   */
01097 #define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
01098 #define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01099 #define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01100 #define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01101 #define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01102 #define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01103 #define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01104 #define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01105 #define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
01106 #define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01107 #define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01108 #define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01109 #define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01110 #define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01111 #define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01112 #define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01113 #define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01114 #define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
01115 /**
01116   * @}
01117   */
01118
01119 /** @defgroup DMA_Handle_index TIM DMA Handle Index
01120   * @{
01121   */
01122 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
01123 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
01124 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
01125 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
01126 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
01127 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
01128 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
01129 /**
01130   * @}
01131   */
01132
01133 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
01134   * @{
01135   */
01136 #define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
01137 #define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
01138 #define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
01139 #define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
01140 /**
01141   * @}
01142   */
01143
01144 /** @defgroup TIM_Break_System TIM Break System
01145   * @{
01146   */
01147 #define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/15/16/17 */
01148 #define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
01149 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
01150 #define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */
01151 /**
01152   * @}
01153   */
01154
01155 /**
01156   * @}
01157   */
01158 /* End of exported constants -------------------------------------------------*/
01159
01160 /* Exported macros -----------------------------------------------------------*/
01161 /** @defgroup TIM_Exported_Macros TIM Exported Macros
01162   * @{
01163   */
01164
01165 /** @brief  Reset TIM handle state.
01166   * @param  __HANDLE__ TIM handle.
01167   * @retval None
01168   */
01169 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01170 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
01171                                                       (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
01172                                                       (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
01173                                                       (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
01174                                                       (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
01175                                                       (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
01176                                                       (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
01177                                                       (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
01178                                                       (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
01179                                                       (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
01180                                                       (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
01181                                                       (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
01182                                                       (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
01183                                                       (__HANDLE__)->Base_MspInitCallback         = NULL;            \
01184                                                       (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
01185                                                       (__HANDLE__)->IC_MspInitCallback           = NULL;            \
01186                                                       (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
01187                                                       (__HANDLE__)->OC_MspInitCallback           = NULL;            \
01188                                                       (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
01189                                                       (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
01190                                                       (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
01191                                                       (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
01192                                                       (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
01193                                                       (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
01194                                                       (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
01195                                                       (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
01196                                                       (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
01197                                                      } while(0)
01198 #else
01199 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
01200                                                       (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
01201                                                       (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
01202                                                       (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
01203                                                       (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
01204                                                       (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
01205                                                       (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
01206                                                       (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
01207                                                       (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
01208                                                       (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
01209                                                       (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
01210                                                       (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
01211                                                       (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
01212                                                      } while(0)
01213 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01214
01215 /**
01216   * @brief  Enable the TIM peripheral.
01217   * @param  __HANDLE__ TIM handle
01218   * @retval None
01219   */
01220 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
01221
01222 /**
01223   * @brief  Enable the TIM main Output.
01224   * @param  __HANDLE__ TIM handle
01225   * @retval None
01226   */
01227 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
01228
01229 /**
01230   * @brief  Disable the TIM peripheral.
01231   * @param  __HANDLE__ TIM handle
01232   * @retval None
01233   */
01234 #define __HAL_TIM_DISABLE(__HANDLE__) \
01235   do { \
01236     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
01237     { \
01238       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
01239       { \
01240         (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
01241       } \
01242     } \
01243   } while(0)
01244
01245 /**
01246   * @brief  Disable the TIM main Output.
01247   * @param  __HANDLE__ TIM handle
01248   * @retval None
01249   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
01250   *       disabled
01251   */
01252 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
01253   do { \
01254     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
01255     { \
01256       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
01257       { \
01258         (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
01259       } \
01260     } \
01261   } while(0)
01262
01263 /**
01264   * @brief  Disable the TIM main Output.
01265   * @param  __HANDLE__ TIM handle
01266   * @retval None
01267   * @note The Main Output Enable of a timer instance is disabled unconditionally
01268   */
01269 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
01270
01271 /** @brief  Enable the specified TIM interrupt.
01272   * @param  __HANDLE__ specifies the TIM Handle.
01273   * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
01274   *          This parameter can be one of the following values:
01275   *            @arg TIM_IT_UPDATE: Update interrupt
01276   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01277   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01278   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01279   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01280   *            @arg TIM_IT_COM:   Commutation interrupt
01281   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01282   *            @arg TIM_IT_BREAK: Break interrupt
01283   * @retval None
01284   */
01285 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
01286
01287 /** @brief  Disable the specified TIM interrupt.
01288   * @param  __HANDLE__ specifies the TIM Handle.
01289   * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
01290   *          This parameter can be one of the following values:
01291   *            @arg TIM_IT_UPDATE: Update interrupt
01292   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01293   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01294   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01295   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01296   *            @arg TIM_IT_COM:   Commutation interrupt
01297   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01298   *            @arg TIM_IT_BREAK: Break interrupt
01299   * @retval None
01300   */
01301 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
01302
01303 /** @brief  Enable the specified DMA request.
01304   * @param  __HANDLE__ specifies the TIM Handle.
01305   * @param  __DMA__ specifies the TIM DMA request to enable.
01306   *          This parameter can be one of the following values:
01307   *            @arg TIM_DMA_UPDATE: Update DMA request
01308   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01309   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01310   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01311   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01312   *            @arg TIM_DMA_COM:   Commutation DMA request
01313   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01314   * @retval None
01315   */
01316 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
01317
01318 /** @brief  Disable the specified DMA request.
01319   * @param  __HANDLE__ specifies the TIM Handle.
01320   * @param  __DMA__ specifies the TIM DMA request to disable.
01321   *          This parameter can be one of the following values:
01322   *            @arg TIM_DMA_UPDATE: Update DMA request
01323   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01324   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01325   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01326   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01327   *            @arg TIM_DMA_COM:   Commutation DMA request
01328   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01329   * @retval None
01330   */
01331 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
01332
01333 /** @brief  Check whether the specified TIM interrupt flag is set or not.
01334   * @param  __HANDLE__ specifies the TIM Handle.
01335   * @param  __FLAG__ specifies the TIM interrupt flag to check.
01336   *        This parameter can be one of the following values:
01337   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01338   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01339   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01340   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01341   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01342   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01343   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01344   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01345   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01346   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01347   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01348   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01349   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01350   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01351   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01352   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01353   * @retval The new state of __FLAG__ (TRUE or FALSE).
01354   */
01355 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
01356
01357 /** @brief  Clear the specified TIM interrupt flag.
01358   * @param  __HANDLE__ specifies the TIM Handle.
01359   * @param  __FLAG__ specifies the TIM interrupt flag to clear.
01360   *        This parameter can be one of the following values:
01361   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01362   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01363   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01364   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01365   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01366   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01367   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01368   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01369   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01370   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01371   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01372   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01373   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01374   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01375   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01376   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01377   * @retval The new state of __FLAG__ (TRUE or FALSE).
01378   */
01379 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
01380
01381 /**
01382   * @brief  Check whether the specified TIM interrupt source is enabled or not.
01383   * @param  __HANDLE__ TIM handle
01384   * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
01385   *          This parameter can be one of the following values:
01386   *            @arg TIM_IT_UPDATE: Update interrupt
01387   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01388   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01389   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01390   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01391   *            @arg TIM_IT_COM:   Commutation interrupt
01392   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01393   *            @arg TIM_IT_BREAK: Break interrupt
01394   * @retval The state of TIM_IT (SET or RESET).
01395   */
01396 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
01397                                                              == (__INTERRUPT__)) ? SET : RESET)
01398
01399 /** @brief Clear the TIM interrupt pending bits.
01400   * @param  __HANDLE__ TIM handle
01401   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01402   *          This parameter can be one of the following values:
01403   *            @arg TIM_IT_UPDATE: Update interrupt
01404   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01405   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01406   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01407   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01408   *            @arg TIM_IT_COM:   Commutation interrupt
01409   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01410   *            @arg TIM_IT_BREAK: Break interrupt
01411   * @retval None
01412   */
01413 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
01414
01415 /**
01416   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
01417   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
01418   *       in an atomic way.
01419   * @param  __HANDLE__ TIM handle.
01420   * @retval None
01421 mode.
01422   */
01423 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
01424
01425 /**
01426   * @brief  Disable update interrupt flag (UIF) remapping.
01427   * @param  __HANDLE__ TIM handle.
01428   * @retval None
01429 mode.
01430   */
01431 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
01432
01433 /**
01434   * @brief  Get update interrupt flag (UIF) copy status.
01435   * @param  __COUNTER__ Counter value.
01436   * @retval The state of UIFCPY (TRUE or FALSE).
01437 mode.
01438   */
01439 #define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
01440
01441 /**
01442   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
01443   * @param  __HANDLE__ TIM handle.
01444   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
01445   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
01446   *       or Encoder mode.
01447   */
01448 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
01449
01450 /**
01451   * @brief  Set the TIM Prescaler on runtime.
01452   * @param  __HANDLE__ TIM handle.
01453   * @param  __PRESC__ specifies the Prescaler new value.
01454   * @retval None
01455   */
01456 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
01457
01458 /**
01459   * @brief  Set the TIM Counter Register value on runtime.
01460   * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
01461   *      case of 32 bits counter TIM instance.
01462   *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
01463   * @param  __HANDLE__ TIM handle.
01464   * @param  __COUNTER__ specifies the Counter register new value.
01465   * @retval None
01466   */
01467 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
01468
01469 /**
01470   * @brief  Get the TIM Counter Register value on runtime.
01471   * @param  __HANDLE__ TIM handle.
01472   * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
01473   */
01474 #define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
01475
01476 /**
01477   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
01478   * @param  __HANDLE__ TIM handle.
01479   * @param  __AUTORELOAD__ specifies the Counter register new value.
01480   * @retval None
01481   */
01482 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01483   do{                                                    \
01484     (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01485     (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01486   } while(0)
01487
01488 /**
01489   * @brief  Get the TIM Autoreload Register value on runtime.
01490   * @param  __HANDLE__ TIM handle.
01491   * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
01492   */
01493 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
01494
01495 /**
01496   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
01497   * @param  __HANDLE__ TIM handle.
01498   * @param  __CKD__ specifies the clock division value.
01499   *          This parameter can be one of the following value:
01500   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01501   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01502   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01503   * @retval None
01504   */
01505 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01506   do{                                                   \
01507     (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
01508     (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
01509     (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
01510   } while(0)
01511
01512 /**
01513   * @brief  Get the TIM Clock Division value on runtime.
01514   * @param  __HANDLE__ TIM handle.
01515   * @retval The clock division can be one of the following values:
01516   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01517   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01518   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01519   */
01520 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01521
01522 /**
01523   * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
01524   *         function.
01525   * @param  __HANDLE__ TIM handle.
01526   * @param  __CHANNEL__ TIM Channels to be configured.
01527   *          This parameter can be one of the following values:
01528   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01529   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01530   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01531   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01532   * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
01533   *          This parameter can be one of the following values:
01534   *            @arg TIM_ICPSC_DIV1: no prescaler
01535   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01536   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01537   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01538   * @retval None
01539   */
01540 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01541   do{                                                    \
01542     TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01543     TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01544   } while(0)
01545
01546 /**
01547   * @brief  Get the TIM Input Capture prescaler on runtime.
01548   * @param  __HANDLE__ TIM handle.
01549   * @param  __CHANNEL__ TIM Channels to be configured.
01550   *          This parameter can be one of the following values:
01551   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01552   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01553   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01554   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01555   * @retval The input capture prescaler can be one of the following values:
01556   *            @arg TIM_ICPSC_DIV1: no prescaler
01557   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01558   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01559   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01560   */
01561 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01562   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01563    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
01564    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01565    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
01566
01567 /**
01568   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
01569   * @param  __HANDLE__ TIM handle.
01570   * @param  __CHANNEL__ TIM Channels to be configured.
01571   *          This parameter can be one of the following values:
01572   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01573   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01574   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01575   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01576   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01577   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01578   * @param  __COMPARE__ specifies the Capture Compare register new value.
01579   * @retval None
01580   */
01581 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
01582   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
01583    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
01584    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
01585    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
01586    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
01587    ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
01588
01589 /**
01590   * @brief  Get the TIM Capture Compare Register value on runtime.
01591   * @param  __HANDLE__ TIM handle.
01592   * @param  __CHANNEL__ TIM Channel associated with the capture compare register
01593   *          This parameter can be one of the following values:
01594   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01595   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01596   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01597   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01598   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
01599   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
01600   * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
01601   */
01602 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01603   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
01604    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
01605    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
01606    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
01607    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
01608    ((__HANDLE__)->Instance->CCR6))
01609
01610 /**
01611   * @brief  Set the TIM Output compare preload.
01612   * @param  __HANDLE__ TIM handle.
01613   * @param  __CHANNEL__ TIM Channels to be configured.
01614   *          This parameter can be one of the following values:
01615   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01616   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01617   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01618   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01619   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01620   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01621   * @retval None
01622   */
01623 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01624   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
01625    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
01626    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
01627    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
01628    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
01629    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
01630
01631 /**
01632   * @brief  Reset the TIM Output compare preload.
01633   * @param  __HANDLE__ TIM handle.
01634   * @param  __CHANNEL__ TIM Channels to be configured.
01635   *          This parameter can be one of the following values:
01636   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01637   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01638   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01639   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01640   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01641   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01642   * @retval None
01643   */
01644 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01645   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
01646    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
01647    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
01648    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
01649    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
01650    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
01651
01652 /**
01653   * @brief  Enable fast mode for a given channel.
01654   * @param  __HANDLE__ TIM handle.
01655   * @param  __CHANNEL__ TIM Channels to be configured.
01656   *          This parameter can be one of the following values:
01657   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01658   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01659   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01660   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01661   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01662   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01663   * @note  When fast mode is enabled an active edge on the trigger input acts
01664   *        like a compare match on CCx output. Delay to sample the trigger
01665   *        input and to activate CCx output is reduced to 3 clock cycles.
01666   * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
01667   * @retval None
01668   */
01669 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
01670   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
01671    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
01672    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
01673    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
01674    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
01675    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
01676
01677 /**
01678   * @brief  Disable fast mode for a given channel.
01679   * @param  __HANDLE__ TIM handle.
01680   * @param  __CHANNEL__ TIM Channels to be configured.
01681   *          This parameter can be one of the following values:
01682   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01683   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01684   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01685   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01686   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01687   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01688   * @note  When fast mode is disabled CCx output behaves normally depending
01689   *        on counter and CCRx values even when the trigger is ON. The minimum
01690   *        delay to activate CCx output when an active edge occurs on the
01691   *        trigger input is 5 clock cycles.
01692   * @retval None
01693   */
01694 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
01695   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
01696    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
01697    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
01698    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
01699    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
01700    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
01701
01702 /**
01703   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
01704   * @param  __HANDLE__ TIM handle.
01705   * @note  When the URS bit of the TIMx_CR1 register is set, only counter
01706   *        overflow/underflow generates an update interrupt or DMA request (if
01707   *        enabled)
01708   * @retval None
01709   */
01710 #define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
01711
01712 /**
01713   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
01714   * @param  __HANDLE__ TIM handle.
01715   * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
01716   *        following events generate an update interrupt or DMA request (if
01717   *        enabled):
01718   *           _ Counter overflow underflow
01719   *           _ Setting the UG bit
01720   *           _ Update generation through the slave mode controller
01721   * @retval None
01722   */
01723 #define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
01724
01725 /**
01726   * @brief  Set the TIM Capture x input polarity on runtime.
01727   * @param  __HANDLE__ TIM handle.
01728   * @param  __CHANNEL__ TIM Channels to be configured.
01729   *          This parameter can be one of the following values:
01730   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01731   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01732   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01733   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01734   * @param  __POLARITY__ Polarity for TIx source
01735   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01736   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01737   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01738   * @retval None
01739   */
01740 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01741   do{                                                                     \
01742     TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01743     TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01744   }while(0)
01745
01746 /** @brief  Select the Capture/compare DMA request source.
01747   * @param  __HANDLE__ specifies the TIM Handle.
01748   * @param  __CCDMA__ specifies Capture/compare DMA request source
01749   *          This parameter can be one of the following values:
01750   *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
01751   *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
01752   * @retval None
01753   */
01754 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
01755   MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
01756
01757 /**
01758   * @}
01759   */
01760 /* End of exported macros ----------------------------------------------------*/
01761
01762 /* Private constants ---------------------------------------------------------*/
01763 /** @defgroup TIM_Private_Constants TIM Private Constants
01764   * @{
01765   */
01766 /* The counter of a timer instance is disabled only if all the CCx and CCxN
01767    channels have been disabled */
01768 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
01769 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
01770 /**
01771   * @}
01772   */
01773 /* End of private constants --------------------------------------------------*/
01774
01775 /* Private macros ------------------------------------------------------------*/
01776 /** @defgroup TIM_Private_Macros TIM Private Macros
01777   * @{
01778   */
01779 #if defined(COMP1) && defined(COMP2) && defined(COMP3)
01780 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01781                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
01782                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
01783                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3)    || \
01784                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01785 #elif defined(COMP1) && defined(COMP2)
01786 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01787                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
01788                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
01789                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01790 #else
01791 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01792                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01793 #endif /* COMP1 && COMP2 && COMP3 */
01794
01795 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
01796                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
01797                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
01798                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
01799                                    ((__BASE__) == TIM_DMABASE_SR)    || \
01800                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
01801                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
01802                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
01803                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
01804                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
01805                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
01806                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
01807                                    ((__BASE__) == TIM_DMABASE_RCR)   || \
01808                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
01809                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
01810                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
01811                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
01812                                    ((__BASE__) == TIM_DMABASE_BDTR)  || \
01813                                    ((__BASE__) == TIM_DMABASE_OR1)    || \
01814                                    ((__BASE__) == TIM_DMABASE_CCMR3) || \
01815                                    ((__BASE__) == TIM_DMABASE_CCR5)  || \
01816                                    ((__BASE__) == TIM_DMABASE_CCR6)  || \
01817                                    ((__BASE__) == TIM_DMABASE_AF1)   || \
01818                                    ((__BASE__) == TIM_DMABASE_AF2)   || \
01819                                    ((__BASE__) == TIM_DMABASE_TISEL))
01820
01821 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01822
01823 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
01824                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
01825                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01826                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01827                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
01828
01829 #define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
01830                                             ((__MODE__) == TIM_UIFREMAP_ENABLE))
01831
01832 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
01833                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
01834                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
01835
01836 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
01837                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
01838
01839 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
01840                                             ((__STATE__) == TIM_OCFAST_ENABLE))
01841
01842 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
01843                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
01844
01845 #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
01846                                             ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
01847
01848 #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
01849                                             ((__STATE__) == TIM_OCIDLESTATE_RESET))
01850
01851 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
01852                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
01853
01854 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
01855                                                       ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
01856
01857 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
01858                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
01859                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
01860
01861 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
01862                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
01863                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
01864
01865 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
01866                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
01867                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
01868                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
01869
01870 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
01871                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
01872
01873 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
01874                                             ((__MODE__) == TIM_ENCODERMODE_TI2) || \
01875                                             ((__MODE__) == TIM_ENCODERMODE_TI12))
01876
01877 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01878
01879 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
01880                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
01881                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
01882                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
01883                                             ((__CHANNEL__) == TIM_CHANNEL_5) || \
01884                                             ((__CHANNEL__) == TIM_CHANNEL_6) || \
01885                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
01886
01887 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
01888                                             ((__CHANNEL__) == TIM_CHANNEL_2))
01889
01890 #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
01891   ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
01892
01893 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
01894                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
01895                                                     ((__CHANNEL__) == TIM_CHANNEL_3))
01896
01897 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
01898                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
01899                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
01900                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
01901                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
01902                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
01903                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
01904                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
01905                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
01906                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
01907
01908 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
01909                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01910                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
01911                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
01912                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
01913
01914 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
01915                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
01916                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
01917                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
01918
01919 #define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
01920
01921 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01922                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01923
01924 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01925                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01926                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01927                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
01928
01929 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
01930
01931 #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
01932                                             ((__STATE__) == TIM_OSSR_DISABLE))
01933
01934 #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
01935                                             ((__STATE__) == TIM_OSSI_DISABLE))
01936
01937 #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
01938                                             ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
01939                                             ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
01940                                             ((__LEVEL__) == TIM_LOCKLEVEL_3))
01941
01942 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
01943
01944
01945 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
01946                                             ((__STATE__) == TIM_BREAK_DISABLE))
01947
01948 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
01949                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
01950
01951 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
01952                                          ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
01953
01954
01955 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
01956                                             ((__STATE__) == TIM_BREAK2_DISABLE))
01957
01958 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
01959                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
01960
01961 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
01962                                           ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
01963
01964
01965 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01966                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
01967
01968 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
01969
01970 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
01971                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
01972                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
01973                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
01974                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
01975                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
01976                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
01977                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
01978
01979 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
01980                                          ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
01981                                          ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
01982                                          ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
01983                                          ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
01984                                          ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
01985                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01986                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01987                                          ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
01988                                          ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
01989                                          ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
01990                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
01991                                          ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
01992                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
01993                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
01994                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
01995                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
01996
01997 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
01998                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
01999
02000 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
02001                                      ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
02002                                      ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
02003                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
02004                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
02005                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
02006
02007 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
02008                                    ((__MODE__) == TIM_OCMODE_PWM2)               || \
02009                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
02010                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
02011                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
02012                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
02013
02014 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
02015                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
02016                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
02017                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
02018                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
02019                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
02020                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
02021                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
02022
02023 #if defined(USB_BASE)
02024 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
02025                                                  ((__SELECTION__) == TIM_TS_ITR1)    || \
02026                                                  ((__SELECTION__) == TIM_TS_ITR2)    || \
02027                                                  ((__SELECTION__) == TIM_TS_ITR3)    || \
02028                                                  ((__SELECTION__) == TIM_TS_ITR7)    || \
02029                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
02030                                                  ((__SELECTION__) == TIM_TS_TI1FP1)  || \
02031                                                  ((__SELECTION__) == TIM_TS_TI2FP2)  || \
02032                                                  ((__SELECTION__) == TIM_TS_ETRF))
02033 #else
02034 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
02035                                                  ((__SELECTION__) == TIM_TS_ITR1)    || \
02036                                                  ((__SELECTION__) == TIM_TS_ITR2)    || \
02037                                                  ((__SELECTION__) == TIM_TS_ITR3)    || \
02038                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
02039                                                  ((__SELECTION__) == TIM_TS_TI1FP1)  || \
02040                                                  ((__SELECTION__) == TIM_TS_TI2FP2)  || \
02041                                                  ((__SELECTION__) == TIM_TS_ETRF))
02042 #endif /* USB_BASE */
02043
02044 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
02045                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
02046                                                                ((__SELECTION__) == TIM_TS_ITR2) || \
02047                                                                ((__SELECTION__) == TIM_TS_ITR3) || \
02048                                                                ((__SELECTION__) == TIM_TS_NONE))
02049
02050 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
02051                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
02052                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
02053                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
02054                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
02055
02056 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
02057                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
02058                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
02059                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
02060
02061 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
02062
02063 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
02064                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
02065
02066 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
02067                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
02068                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
02069                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
02070                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
02071                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
02072                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
02073                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
02074                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
02075                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
02076                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
02077                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
02078                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
02079                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
02080                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
02081                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
02082                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
02083                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
02084
02085 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
02086
02087 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
02088
02089 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
02090
02091 #if defined(PWR_PVD_SUPPORT)
02092 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
02093                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
02094                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
02095                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
02096 #else
02097 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
02098                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
02099                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
02100 #endif /* PWR_PVD_SUPPORT */
02101
02102 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
02103                                                        ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
02104
02105 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
02106   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
02107    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
02108    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
02109    ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
02110
02111 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
02112   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
02113    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
02114    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
02115    ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
02116
02117 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
02118   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
02119    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
02120    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
02121    ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
02122
02123 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
02124   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
02125    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
02126    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
02127    ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
02128
02129 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
02130   (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
02131    ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
02132    ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
02133    ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
02134    ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
02135    (__HANDLE__)->ChannelState[5])
02136
02137 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
02138   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
02139    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
02140    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
02141    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
02142    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
02143    ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
02144
02145 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
02146                                                                        (__HANDLE__)->ChannelState[0]  = \
02147                                                                        (__CHANNEL_STATE__);  \
02148                                                                        (__HANDLE__)->ChannelState[1]  = \
02149                                                                        (__CHANNEL_STATE__);  \
02150                                                                        (__HANDLE__)->ChannelState[2]  = \
02151                                                                        (__CHANNEL_STATE__);  \
02152                                                                        (__HANDLE__)->ChannelState[3]  = \
02153                                                                        (__CHANNEL_STATE__);  \
02154                                                                        (__HANDLE__)->ChannelState[4]  = \
02155                                                                        (__CHANNEL_STATE__);  \
02156                                                                        (__HANDLE__)->ChannelState[5]  = \
02157                                                                        (__CHANNEL_STATE__);  \
02158                                                                      } while(0)
02159
02160 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
02161   (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
02162    ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
02163    ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
02164    (__HANDLE__)->ChannelNState[3])
02165
02166 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
02167   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
02168    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
02169    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
02170    ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
02171
02172 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
02173                                                                          (__HANDLE__)->ChannelNState[0] = \
02174                                                                          (__CHANNEL_STATE__);  \
02175                                                                          (__HANDLE__)->ChannelNState[1] = \
02176                                                                          (__CHANNEL_STATE__);  \
02177                                                                          (__HANDLE__)->ChannelNState[2] = \
02178                                                                          (__CHANNEL_STATE__);  \
02179                                                                          (__HANDLE__)->ChannelNState[3] = \
02180                                                                          (__CHANNEL_STATE__);  \
02181                                                                        } while(0)
02182
02183 /**
02184   * @}
02185   */
02186 /* End of private macros -----------------------------------------------------*/
02187
02188 /* Include TIM HAL Extended module */
02189 #include "stm32g0xx_hal_tim_ex.h"
02190
02191 /* Exported functions --------------------------------------------------------*/
02192 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
02193   * @{
02194   */
02195
02196 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
02197   *  @brief   Time Base functions
02198   * @{
02199   */
02200 /* Time Base functions ********************************************************/
02201 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
02202 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
02203 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
02204 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
02205 /* Blocking mode: Polling */
02206 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
02207 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
02208 /* Non-Blocking mode: Interrupt */
02209 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
02210 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
02211 /* Non-Blocking mode: DMA */
02212 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
02213 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
02214 /**
02215   * @}
02216   */
02217
02218 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
02219   *  @brief   TIM Output Compare functions
02220   * @{
02221   */
02222 /* Timer Output Compare functions *********************************************/
02223 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
02224 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
02225 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
02226 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
02227 /* Blocking mode: Polling */
02228 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02229 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02230 /* Non-Blocking mode: Interrupt */
02231 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02232 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02233 /* Non-Blocking mode: DMA */
02234 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
02235                                        uint16_t Length);
02236 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02237 /**
02238   * @}
02239   */
02240
02241 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
02242   *  @brief   TIM PWM functions
02243   * @{
02244   */
02245 /* Timer PWM functions ********************************************************/
02246 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
02247 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
02248 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
02249 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
02250 /* Blocking mode: Polling */
02251 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02252 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02253 /* Non-Blocking mode: Interrupt */
02254 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02255 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02256 /* Non-Blocking mode: DMA */
02257 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
02258                                         uint16_t Length);
02259 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02260 /**
02261   * @}
02262   */
02263
02264 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
02265   *  @brief   TIM Input Capture functions
02266   * @{
02267   */
02268 /* Timer Input Capture functions **********************************************/
02269 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
02270 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
02271 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
02272 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
02273 /* Blocking mode: Polling */
02274 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02275 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02276 /* Non-Blocking mode: Interrupt */
02277 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02278 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02279 /* Non-Blocking mode: DMA */
02280 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
02281 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02282 /**
02283   * @}
02284   */
02285
02286 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
02287   *  @brief   TIM One Pulse functions
02288   * @{
02289   */
02290 /* Timer One Pulse functions **************************************************/
02291 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
02292 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
02293 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
02294 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
02295 /* Blocking mode: Polling */
02296 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02297 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02298 /* Non-Blocking mode: Interrupt */
02299 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02300 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02301 /**
02302   * @}
02303   */
02304
02305 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
02306   *  @brief   TIM Encoder functions
02307   * @{
02308   */
02309 /* Timer Encoder functions ****************************************************/
02310 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
02311 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
02312 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
02313 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
02314 /* Blocking mode: Polling */
02315 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02316 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02317 /* Non-Blocking mode: Interrupt */
02318 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02319 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02320 /* Non-Blocking mode: DMA */
02321 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
02322                                             uint32_t *pData2, uint16_t Length);
02323 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02324 /**
02325   * @}
02326   */
02327
02328 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02329   *  @brief   IRQ handler management
02330   * @{
02331   */
02332 /* Interrupt Handler functions  ***********************************************/
02333 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
02334 /**
02335   * @}
02336   */
02337
02338 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
02339   *  @brief   Peripheral Control functions
02340   * @{
02341   */
02342 /* Control functions  *********************************************************/
02343 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
02344                                            uint32_t Channel);
02345 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
02346                                             uint32_t Channel);
02347 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
02348                                            uint32_t Channel);
02349 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
02350                                                  uint32_t OutputChannel,  uint32_t InputChannel);
02351 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
02352                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
02353                                            uint32_t Channel);
02354 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
02355 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
02356 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
02357 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
02358 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02359                                               uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer, uint32_t  BurstLength);
02360 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02361                                                    uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
02362                                                    uint32_t BurstLength,  uint32_t DataLength);
02363 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
02364 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02365                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
02366 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02367                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
02368                                                   uint32_t  BurstLength, uint32_t  DataLength);
02369 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
02370 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
02371 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
02372 /**
02373   * @}
02374   */
02375
02376 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
02377   *  @brief   TIM Callbacks functions
02378   * @{
02379   */
02380 /* Callback in non blocking modes (Interrupt and DMA) *************************/
02381 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
02382 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
02383 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
02384 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
02385 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
02386 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
02387 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
02388 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
02389 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
02390 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
02391
02392 /* Callbacks Register/UnRegister functions  ***********************************/
02393 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02394 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
02395                                            pTIM_CallbackTypeDef pCallback);
02396 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
02397 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02398
02399 /**
02400   * @}
02401   */
02402
02403 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
02404   *  @brief  Peripheral State functions
02405   * @{
02406   */
02407 /* Peripheral State functions  ************************************************/
02408 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
02409 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
02410 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
02411 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
02412 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
02413 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
02414
02415 /* Peripheral Channel state functions  ************************************************/
02416 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
02417 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
02418 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
02419 /**
02420   * @}
02421   */
02422
02423 /**
02424   * @}
02425   */
02426 /* End of exported functions -------------------------------------------------*/
02427
02428 /* Private functions----------------------------------------------------------*/
02429 /** @defgroup TIM_Private_Functions TIM Private Functions
02430   * @{
02431   */
02432 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
02433 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
02434 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
02435 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
02436                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
02437
02438 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
02439 void TIM_DMAError(DMA_HandleTypeDef *hdma);
02440 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
02441 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
02442 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
02443
02444 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02445 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
02446 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02447
02448 /**
02449   * @}
02450   */
02451 /* End of private functions --------------------------------------------------*/
02452
02453 /**
02454   * @}
02455   */
02456
02457 /**
02458   * @}
02459   */
02460
02461 #ifdef __cplusplus
02462 }
02463 #endif
02464
02465 #endif /* STM32G0xx_HAL_TIM_H */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_tim_ex.c Source File

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stm32g0xx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer Extended peripheral:
00008   *           + Time Hall Sensor Interface Initialization
00009   *           + Time Hall Sensor Interface Start
00010   *           + Time Complementary signal break and dead time configuration
00011   *           + Time Master and Slave synchronization configuration
00012   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00013   *           + Time OCRef clear configuration
00014   *           + Timer remapping capabilities configuration
00015   ******************************************************************************
00016   * @attention
00017   *
00018   * Copyright (c) 2018 STMicroelectronics.
00019   * All rights reserved.
00020   *
00021   * This software is licensed under terms that can be found in the LICENSE file
00022   * in the root directory of this software component.
00023   * If no LICENSE file comes with this software, it is provided AS-IS.
00024   *
00025   ******************************************************************************
00026   @verbatim
00027   ==============================================================================
00028                       ##### TIMER Extended features #####
00029   ==============================================================================
00030   [..]
00031     The Timer Extended features include:
00032     (#) Complementary outputs with programmable dead-time for :
00033         (++) Output Compare
00034         (++) PWM generation (Edge and Center-aligned Mode)
00035         (++) One-pulse mode output
00036     (#) Synchronization circuit to control the timer with external signals and to
00037         interconnect several timers together.
00038     (#) Break input to put the timer output signals in reset state or in a known state.
00039     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00040         positioning purposes
00041
00042             ##### How to use this driver #####
00043   ==============================================================================
00044     [..]
00045      (#) Initialize the TIM low level resources by implementing the following functions
00046          depending on the selected feature:
00047            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
00048
00049      (#) Initialize the TIM low level resources :
00050         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00051         (##) TIM pins configuration
00052             (+++) Enable the clock for the TIM GPIOs using the following function:
00053               __HAL_RCC_GPIOx_CLK_ENABLE();
00054             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00055
00056      (#) The external Clock can be configured, if needed (the default clock is the
00057          internal clock from the APBx), using the following function:
00058          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00059          any start function.
00060
00061      (#) Configure the TIM in the desired functioning mode using one of the
00062          initialization function of this driver:
00063           (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
00064                Timer Hall Sensor Interface and the commutation event with the corresponding
00065                Interrupt and DMA request if needed (Note that One Timer is used to interface
00066                with the Hall sensor Interface and another Timer should be used to use
00067                the commutation event).
00068
00069      (#) Activate the TIM peripheral using one of the start functions:
00070            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
00071                 HAL_TIMEx_OCN_Start_IT()
00072            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
00073                 HAL_TIMEx_PWMN_Start_IT()
00074            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00075            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
00076                 HAL_TIMEx_HallSensor_Start_IT().
00077
00078   @endverbatim
00079   ******************************************************************************
00080   */
00081
00082 /* Includes ------------------------------------------------------------------*/
00083 #include "stm32g0xx_hal.h"
00084
00085 /** @addtogroup STM32G0xx_HAL_Driver
00086   * @{
00087   */
00088
00089 /** @defgroup TIMEx TIMEx
00090   * @brief TIM Extended HAL module driver
00091   * @{
00092   */
00093
00094 #ifdef HAL_TIM_MODULE_ENABLED
00095
00096 /* Private typedef -----------------------------------------------------------*/
00097 /* Private define ------------------------------------------------------------*/
00098 /* Private constants ---------------------------------------------------------*/
00099 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
00100   * @{
00101   */
00102 /* Timeout for break input rearm */
00103 #define TIM_BREAKINPUT_REARM_TIMEOUT    5UL /* 5 milliseconds */
00104 /**
00105   * @}
00106   */
00107 /* End of private constants --------------------------------------------------*/
00108
00109 /* Private macros ------------------------------------------------------------*/
00110 /* Private variables ---------------------------------------------------------*/
00111 /* Private function prototypes -----------------------------------------------*/
00112 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
00113 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
00114 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
00115
00116 /* Exported functions --------------------------------------------------------*/
00117 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
00118   * @{
00119   */
00120
00121 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00122   * @brief    Timer Hall Sensor functions
00123   *
00124 @verbatim
00125   ==============================================================================
00126                       ##### Timer Hall Sensor functions #####
00127   ==============================================================================
00128   [..]
00129     This section provides functions allowing to:
00130     (+) Initialize and configure TIM HAL Sensor.
00131     (+) De-initialize TIM HAL Sensor.
00132     (+) Start the Hall Sensor Interface.
00133     (+) Stop the Hall Sensor Interface.
00134     (+) Start the Hall Sensor Interface and enable interrupts.
00135     (+) Stop the Hall Sensor Interface and disable interrupts.
00136     (+) Start the Hall Sensor Interface and enable DMA transfers.
00137     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00138
00139 @endverbatim
00140   * @{
00141   */
00142 /**
00143   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
00144   * @note   When the timer instance is initialized in Hall Sensor Interface mode,
00145   *         timer channels 1 and channel 2 are reserved and cannot be used for
00146   *         other purpose.
00147   * @param  htim TIM Hall Sensor Interface handle
00148   * @param  sConfig TIM Hall Sensor configuration structure
00149   * @retval HAL status
00150   */
00151 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
00152 {
00153   TIM_OC_InitTypeDef OC_Config;
00154
00155   /* Check the TIM handle allocation */
00156   if (htim == NULL)
00157   {
00158     return HAL_ERROR;
00159   }
00160
00161   /* Check the parameters */
00162   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00163   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00164   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00165   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00166   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00167   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
00168   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00169   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00170
00171   if (htim->State == HAL_TIM_STATE_RESET)
00172   {
00173     /* Allocate lock resource and initialize it */
00174     htim->Lock = HAL_UNLOCKED;
00175
00176 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00177     /* Reset interrupt callbacks to legacy week callbacks */
00178     TIM_ResetCallback(htim);
00179
00180     if (htim->HallSensor_MspInitCallback == NULL)
00181     {
00182       htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
00183     }
00184     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00185     htim->HallSensor_MspInitCallback(htim);
00186 #else
00187     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00188     HAL_TIMEx_HallSensor_MspInit(htim);
00189 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00190   }
00191
00192   /* Set the TIM state */
00193   htim->State = HAL_TIM_STATE_BUSY;
00194
00195   /* Configure the Time base in the Encoder Mode */
00196   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00197
00198   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00199   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00200
00201   /* Reset the IC1PSC Bits */
00202   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00203   /* Set the IC1PSC value */
00204   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00205
00206   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00207   htim->Instance->CR2 |= TIM_CR2_TI1S;
00208
00209   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00210   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00211   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00212
00213   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00214   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00215   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00216
00217   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00218   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00219   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00220   OC_Config.OCMode = TIM_OCMODE_PWM2;
00221   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00222   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00223   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00224   OC_Config.Pulse = sConfig->Commutation_Delay;
00225
00226   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00227
00228   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00229     register to 101 */
00230   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00231   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00232
00233   /* Initialize the DMA burst operation state */
00234   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
00235
00236   /* Initialize the TIM channels state */
00237   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00238   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00239   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00240   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00241
00242   /* Initialize the TIM state*/
00243   htim->State = HAL_TIM_STATE_READY;
00244
00245   return HAL_OK;
00246 }
00247
00248 /**
00249   * @brief  DeInitializes the TIM Hall Sensor interface
00250   * @param  htim TIM Hall Sensor Interface handle
00251   * @retval HAL status
00252   */
00253 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00254 {
00255   /* Check the parameters */
00256   assert_param(IS_TIM_INSTANCE(htim->Instance));
00257
00258   htim->State = HAL_TIM_STATE_BUSY;
00259
00260   /* Disable the TIM Peripheral Clock */
00261   __HAL_TIM_DISABLE(htim);
00262
00263 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00264   if (htim->HallSensor_MspDeInitCallback == NULL)
00265   {
00266     htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
00267   }
00268   /* DeInit the low level hardware */
00269   htim->HallSensor_MspDeInitCallback(htim);
00270 #else
00271   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00272   HAL_TIMEx_HallSensor_MspDeInit(htim);
00273 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00274
00275   /* Change the DMA burst operation state */
00276   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
00277
00278   /* Change the TIM channels state */
00279   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
00280   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
00281   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
00282   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
00283
00284   /* Change TIM state */
00285   htim->State = HAL_TIM_STATE_RESET;
00286
00287   /* Release Lock */
00288   __HAL_UNLOCK(htim);
00289
00290   return HAL_OK;
00291 }
00292
00293 /**
00294   * @brief  Initializes the TIM Hall Sensor MSP.
00295   * @param  htim TIM Hall Sensor Interface handle
00296   * @retval None
00297   */
00298 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00299 {
00300   /* Prevent unused argument(s) compilation warning */
00301   UNUSED(htim);
00302
00303   /* NOTE : This function should not be modified, when the callback is needed,
00304             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00305    */
00306 }
00307
00308 /**
00309   * @brief  DeInitializes TIM Hall Sensor MSP.
00310   * @param  htim TIM Hall Sensor Interface handle
00311   * @retval None
00312   */
00313 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00314 {
00315   /* Prevent unused argument(s) compilation warning */
00316   UNUSED(htim);
00317
00318   /* NOTE : This function should not be modified, when the callback is needed,
00319             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00320    */
00321 }
00322
00323 /**
00324   * @brief  Starts the TIM Hall Sensor Interface.
00325   * @param  htim TIM Hall Sensor Interface handle
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00329 {
00330   uint32_t tmpsmcr;
00331   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
00332   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
00333   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
00334   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
00335
00336   /* Check the parameters */
00337   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00338
00339   /* Check the TIM channels state */
00340   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
00341       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
00342       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
00343       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
00344   {
00345     return HAL_ERROR;
00346   }
00347
00348   /* Set the TIM channels state */
00349   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00350   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
00351   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00352   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
00353
00354   /* Enable the Input Capture channel 1
00355   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00356   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00357   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00358
00359   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00360   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00361   {
00362     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00363     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00364     {
00365       __HAL_TIM_ENABLE(htim);
00366     }
00367   }
00368   else
00369   {
00370     __HAL_TIM_ENABLE(htim);
00371   }
00372
00373   /* Return function status */
00374   return HAL_OK;
00375 }
00376
00377 /**
00378   * @brief  Stops the TIM Hall sensor Interface.
00379   * @param  htim TIM Hall Sensor Interface handle
00380   * @retval HAL status
00381   */
00382 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00383 {
00384   /* Check the parameters */
00385   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00386
00387   /* Disable the Input Capture channels 1, 2 and 3
00388   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00389   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00390   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00391
00392   /* Disable the Peripheral */
00393   __HAL_TIM_DISABLE(htim);
00394
00395   /* Set the TIM channels state */
00396   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00397   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00398   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00399   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00400
00401   /* Return function status */
00402   return HAL_OK;
00403 }
00404
00405 /**
00406   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00407   * @param  htim TIM Hall Sensor Interface handle
00408   * @retval HAL status
00409   */
00410 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00411 {
00412   uint32_t tmpsmcr;
00413   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
00414   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
00415   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
00416   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
00417
00418   /* Check the parameters */
00419   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00420
00421   /* Check the TIM channels state */
00422   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
00423       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
00424       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
00425       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
00426   {
00427     return HAL_ERROR;
00428   }
00429
00430   /* Set the TIM channels state */
00431   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00432   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
00433   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00434   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
00435
00436   /* Enable the capture compare Interrupts 1 event */
00437   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00438
00439   /* Enable the Input Capture channel 1
00440   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00441   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00442   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00443
00444   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00445   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00446   {
00447     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00448     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00449     {
00450       __HAL_TIM_ENABLE(htim);
00451     }
00452   }
00453   else
00454   {
00455     __HAL_TIM_ENABLE(htim);
00456   }
00457
00458   /* Return function status */
00459   return HAL_OK;
00460 }
00461
00462 /**
00463   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00464   * @param  htim TIM Hall Sensor Interface handle
00465   * @retval HAL status
00466   */
00467 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00468 {
00469   /* Check the parameters */
00470   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00471
00472   /* Disable the Input Capture channel 1
00473   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00474   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00475   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00476
00477   /* Disable the capture compare Interrupts event */
00478   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00479
00480   /* Disable the Peripheral */
00481   __HAL_TIM_DISABLE(htim);
00482
00483   /* Set the TIM channels state */
00484   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00485   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00486   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00487   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
00488
00489   /* Return function status */
00490   return HAL_OK;
00491 }
00492
00493 /**
00494   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00495   * @param  htim TIM Hall Sensor Interface handle
00496   * @param  pData The destination Buffer address.
00497   * @param  Length The length of data to be transferred from TIM peripheral to memory.
00498   * @retval HAL status
00499   */
00500 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00501 {
00502   uint32_t tmpsmcr;
00503   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
00504   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
00505
00506   /* Check the parameters */
00507   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00508
00509   /* Set the TIM channel state */
00510   if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
00511       || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
00512   {
00513     return HAL_BUSY;
00514   }
00515   else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
00516            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
00517   {
00518     if ((pData == NULL) || (Length == 0U))
00519     {
00520       return HAL_ERROR;
00521     }
00522     else
00523     {
00524       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00525       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
00526     }
00527   }
00528   else
00529   {
00530     return HAL_ERROR;
00531   }
00532
00533   /* Enable the Input Capture channel 1
00534   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00535   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00536   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00537
00538   /* Set the DMA Input Capture 1 Callbacks */
00539   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00540   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
00541   /* Set the DMA error callback */
00542   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00543
00544   /* Enable the DMA channel for Capture 1*/
00545   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
00546   {
00547     /* Return error status */
00548     return HAL_ERROR;
00549   }
00550   /* Enable the capture compare 1 Interrupt */
00551   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00552
00553   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00554   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00555   {
00556     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00557     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00558     {
00559       __HAL_TIM_ENABLE(htim);
00560     }
00561   }
00562   else
00563   {
00564     __HAL_TIM_ENABLE(htim);
00565   }
00566
00567   /* Return function status */
00568   return HAL_OK;
00569 }
00570
00571 /**
00572   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00573   * @param  htim TIM Hall Sensor Interface handle
00574   * @retval HAL status
00575   */
00576 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00577 {
00578   /* Check the parameters */
00579   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00580
00581   /* Disable the Input Capture channel 1
00582   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
00583   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00584   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00585
00586
00587   /* Disable the capture compare Interrupts 1 event */
00588   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00589
00590   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
00591
00592   /* Disable the Peripheral */
00593   __HAL_TIM_DISABLE(htim);
00594
00595   /* Set the TIM channel state */
00596   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00597   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
00598
00599   /* Return function status */
00600   return HAL_OK;
00601 }
00602
00603 /**
00604   * @}
00605   */
00606
00607 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00608   *  @brief   Timer Complementary Output Compare functions
00609   *
00610 @verbatim
00611   ==============================================================================
00612               ##### Timer Complementary Output Compare functions #####
00613   ==============================================================================
00614   [..]
00615     This section provides functions allowing to:
00616     (+) Start the Complementary Output Compare/PWM.
00617     (+) Stop the Complementary Output Compare/PWM.
00618     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00619     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00620     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00621     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00622
00623 @endverbatim
00624   * @{
00625   */
00626
00627 /**
00628   * @brief  Starts the TIM Output Compare signal generation on the complementary
00629   *         output.
00630   * @param  htim TIM Output Compare handle
00631   * @param  Channel TIM Channel to be enabled
00632   *          This parameter can be one of the following values:
00633   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00634   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00635   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00636   * @retval HAL status
00637   */
00638 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00639 {
00640   uint32_t tmpsmcr;
00641
00642   /* Check the parameters */
00643   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00644
00645   /* Check the TIM complementary channel state */
00646   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
00647   {
00648     return HAL_ERROR;
00649   }
00650
00651   /* Set the TIM complementary channel state */
00652   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00653
00654   /* Enable the Capture compare channel N */
00655   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00656
00657   /* Enable the Main Output */
00658   __HAL_TIM_MOE_ENABLE(htim);
00659
00660   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00661   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00662   {
00663     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00664     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00665     {
00666       __HAL_TIM_ENABLE(htim);
00667     }
00668   }
00669   else
00670   {
00671     __HAL_TIM_ENABLE(htim);
00672   }
00673
00674   /* Return function status */
00675   return HAL_OK;
00676 }
00677
00678 /**
00679   * @brief  Stops the TIM Output Compare signal generation on the complementary
00680   *         output.
00681   * @param  htim TIM handle
00682   * @param  Channel TIM Channel to be disabled
00683   *          This parameter can be one of the following values:
00684   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00685   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00686   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00687   * @retval HAL status
00688   */
00689 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00690 {
00691   /* Check the parameters */
00692   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00693
00694   /* Disable the Capture compare channel N */
00695   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00696
00697   /* Disable the Main Output */
00698   __HAL_TIM_MOE_DISABLE(htim);
00699
00700   /* Disable the Peripheral */
00701   __HAL_TIM_DISABLE(htim);
00702
00703   /* Set the TIM complementary channel state */
00704   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
00705
00706   /* Return function status */
00707   return HAL_OK;
00708 }
00709
00710 /**
00711   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00712   *         on the complementary output.
00713   * @param  htim TIM OC handle
00714   * @param  Channel TIM Channel to be enabled
00715   *          This parameter can be one of the following values:
00716   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00717   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00718   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00719   * @retval HAL status
00720   */
00721 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00722 {
00723   HAL_StatusTypeDef status = HAL_OK;
00724   uint32_t tmpsmcr;
00725
00726   /* Check the parameters */
00727   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00728
00729   /* Check the TIM complementary channel state */
00730   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
00731   {
00732     return HAL_ERROR;
00733   }
00734
00735   /* Set the TIM complementary channel state */
00736   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00737
00738   switch (Channel)
00739   {
00740     case TIM_CHANNEL_1:
00741     {
00742       /* Enable the TIM Output Compare interrupt */
00743       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00744       break;
00745     }
00746
00747     case TIM_CHANNEL_2:
00748     {
00749       /* Enable the TIM Output Compare interrupt */
00750       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00751       break;
00752     }
00753
00754     case TIM_CHANNEL_3:
00755     {
00756       /* Enable the TIM Output Compare interrupt */
00757       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00758       break;
00759     }
00760
00761
00762     default:
00763       status = HAL_ERROR;
00764       break;
00765   }
00766
00767   if (status == HAL_OK)
00768   {
00769     /* Enable the TIM Break interrupt */
00770     __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00771
00772     /* Enable the Capture compare channel N */
00773     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00774
00775     /* Enable the Main Output */
00776     __HAL_TIM_MOE_ENABLE(htim);
00777
00778     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00779     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00780     {
00781       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00782       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00783       {
00784         __HAL_TIM_ENABLE(htim);
00785       }
00786     }
00787     else
00788     {
00789       __HAL_TIM_ENABLE(htim);
00790     }
00791   }
00792
00793   /* Return function status */
00794   return status;
00795 }
00796
00797 /**
00798   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00799   *         on the complementary output.
00800   * @param  htim TIM Output Compare handle
00801   * @param  Channel TIM Channel to be disabled
00802   *          This parameter can be one of the following values:
00803   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00804   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00805   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00806   * @retval HAL status
00807   */
00808 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00809 {
00810   HAL_StatusTypeDef status = HAL_OK;
00811   uint32_t tmpccer;
00812
00813   /* Check the parameters */
00814   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00815
00816   switch (Channel)
00817   {
00818     case TIM_CHANNEL_1:
00819     {
00820       /* Disable the TIM Output Compare interrupt */
00821       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00822       break;
00823     }
00824
00825     case TIM_CHANNEL_2:
00826     {
00827       /* Disable the TIM Output Compare interrupt */
00828       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00829       break;
00830     }
00831
00832     case TIM_CHANNEL_3:
00833     {
00834       /* Disable the TIM Output Compare interrupt */
00835       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00836       break;
00837     }
00838
00839     default:
00840       status = HAL_ERROR;
00841       break;
00842   }
00843
00844   if (status == HAL_OK)
00845   {
00846     /* Disable the Capture compare channel N */
00847     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00848
00849     /* Disable the TIM Break interrupt (only if no more channel is active) */
00850     tmpccer = htim->Instance->CCER;
00851     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
00852     {
00853       __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00854     }
00855
00856     /* Disable the Main Output */
00857     __HAL_TIM_MOE_DISABLE(htim);
00858
00859     /* Disable the Peripheral */
00860     __HAL_TIM_DISABLE(htim);
00861
00862     /* Set the TIM complementary channel state */
00863     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
00864   }
00865
00866   /* Return function status */
00867   return status;
00868 }
00869
00870 /**
00871   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00872   *         on the complementary output.
00873   * @param  htim TIM Output Compare handle
00874   * @param  Channel TIM Channel to be enabled
00875   *          This parameter can be one of the following values:
00876   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00877   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00878   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00879   * @param  pData The source Buffer address.
00880   * @param  Length The length of data to be transferred from memory to TIM peripheral
00881   * @retval HAL status
00882   */
00883 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
00884                                           uint16_t Length)
00885 {
00886   HAL_StatusTypeDef status = HAL_OK;
00887   uint32_t tmpsmcr;
00888
00889   /* Check the parameters */
00890   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00891
00892   /* Set the TIM complementary channel state */
00893   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
00894   {
00895     return HAL_BUSY;
00896   }
00897   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
00898   {
00899     if ((pData == NULL) || (Length == 0U))
00900     {
00901       return HAL_ERROR;
00902     }
00903     else
00904     {
00905       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
00906     }
00907   }
00908   else
00909   {
00910     return HAL_ERROR;
00911   }
00912
00913   switch (Channel)
00914   {
00915     case TIM_CHANNEL_1:
00916     {
00917       /* Set the DMA compare callbacks */
00918       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
00919       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00920
00921       /* Set the DMA error callback */
00922       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
00923
00924       /* Enable the DMA channel */
00925       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
00926                            Length) != HAL_OK)
00927       {
00928         /* Return error status */
00929         return HAL_ERROR;
00930       }
00931       /* Enable the TIM Output Compare DMA request */
00932       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00933       break;
00934     }
00935
00936     case TIM_CHANNEL_2:
00937     {
00938       /* Set the DMA compare callbacks */
00939       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
00940       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00941
00942       /* Set the DMA error callback */
00943       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
00944
00945       /* Enable the DMA channel */
00946       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
00947                            Length) != HAL_OK)
00948       {
00949         /* Return error status */
00950         return HAL_ERROR;
00951       }
00952       /* Enable the TIM Output Compare DMA request */
00953       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00954       break;
00955     }
00956
00957     case TIM_CHANNEL_3:
00958     {
00959       /* Set the DMA compare callbacks */
00960       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
00961       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00962
00963       /* Set the DMA error callback */
00964       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
00965
00966       /* Enable the DMA channel */
00967       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
00968                            Length) != HAL_OK)
00969       {
00970         /* Return error status */
00971         return HAL_ERROR;
00972       }
00973       /* Enable the TIM Output Compare DMA request */
00974       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00975       break;
00976     }
00977
00978     default:
00979       status = HAL_ERROR;
00980       break;
00981   }
00982
00983   if (status == HAL_OK)
00984   {
00985     /* Enable the Capture compare channel N */
00986     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00987
00988     /* Enable the Main Output */
00989     __HAL_TIM_MOE_ENABLE(htim);
00990
00991     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00992     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
00993     {
00994       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00995       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00996       {
00997         __HAL_TIM_ENABLE(htim);
00998       }
00999     }
01000     else
01001     {
01002       __HAL_TIM_ENABLE(htim);
01003     }
01004   }
01005
01006   /* Return function status */
01007   return status;
01008 }
01009
01010 /**
01011   * @brief  Stops the TIM Output Compare signal generation in DMA mode
01012   *         on the complementary output.
01013   * @param  htim TIM Output Compare handle
01014   * @param  Channel TIM Channel to be disabled
01015   *          This parameter can be one of the following values:
01016   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01017   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01018   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01019   * @retval HAL status
01020   */
01021 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01022 {
01023   HAL_StatusTypeDef status = HAL_OK;
01024
01025   /* Check the parameters */
01026   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01027
01028   switch (Channel)
01029   {
01030     case TIM_CHANNEL_1:
01031     {
01032       /* Disable the TIM Output Compare DMA request */
01033       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01034       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01035       break;
01036     }
01037
01038     case TIM_CHANNEL_2:
01039     {
01040       /* Disable the TIM Output Compare DMA request */
01041       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01042       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01043       break;
01044     }
01045
01046     case TIM_CHANNEL_3:
01047     {
01048       /* Disable the TIM Output Compare DMA request */
01049       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01050       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01051       break;
01052     }
01053
01054     default:
01055       status = HAL_ERROR;
01056       break;
01057   }
01058
01059   if (status == HAL_OK)
01060   {
01061     /* Disable the Capture compare channel N */
01062     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01063
01064     /* Disable the Main Output */
01065     __HAL_TIM_MOE_DISABLE(htim);
01066
01067     /* Disable the Peripheral */
01068     __HAL_TIM_DISABLE(htim);
01069
01070     /* Set the TIM complementary channel state */
01071     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01072   }
01073
01074   /* Return function status */
01075   return status;
01076 }
01077
01078 /**
01079   * @}
01080   */
01081
01082 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
01083   * @brief    Timer Complementary PWM functions
01084   *
01085 @verbatim
01086   ==============================================================================
01087                  ##### Timer Complementary PWM functions #####
01088   ==============================================================================
01089   [..]
01090     This section provides functions allowing to:
01091     (+) Start the Complementary PWM.
01092     (+) Stop the Complementary PWM.
01093     (+) Start the Complementary PWM and enable interrupts.
01094     (+) Stop the Complementary PWM and disable interrupts.
01095     (+) Start the Complementary PWM and enable DMA transfers.
01096     (+) Stop the Complementary PWM and disable DMA transfers.
01097     (+) Start the Complementary Input Capture measurement.
01098     (+) Stop the Complementary Input Capture.
01099     (+) Start the Complementary Input Capture and enable interrupts.
01100     (+) Stop the Complementary Input Capture and disable interrupts.
01101     (+) Start the Complementary Input Capture and enable DMA transfers.
01102     (+) Stop the Complementary Input Capture and disable DMA transfers.
01103     (+) Start the Complementary One Pulse generation.
01104     (+) Stop the Complementary One Pulse.
01105     (+) Start the Complementary One Pulse and enable interrupts.
01106     (+) Stop the Complementary One Pulse and disable interrupts.
01107
01108 @endverbatim
01109   * @{
01110   */
01111
01112 /**
01113   * @brief  Starts the PWM signal generation on the complementary output.
01114   * @param  htim TIM handle
01115   * @param  Channel TIM Channel to be enabled
01116   *          This parameter can be one of the following values:
01117   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01118   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01119   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01120   * @retval HAL status
01121   */
01122 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01123 {
01124   uint32_t tmpsmcr;
01125
01126   /* Check the parameters */
01127   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01128
01129   /* Check the TIM complementary channel state */
01130   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
01131   {
01132     return HAL_ERROR;
01133   }
01134
01135   /* Set the TIM complementary channel state */
01136   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01137
01138   /* Enable the complementary PWM output  */
01139   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01140
01141   /* Enable the Main Output */
01142   __HAL_TIM_MOE_ENABLE(htim);
01143
01144   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01145   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01146   {
01147     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01148     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01149     {
01150       __HAL_TIM_ENABLE(htim);
01151     }
01152   }
01153   else
01154   {
01155     __HAL_TIM_ENABLE(htim);
01156   }
01157
01158   /* Return function status */
01159   return HAL_OK;
01160 }
01161
01162 /**
01163   * @brief  Stops the PWM signal generation on the complementary output.
01164   * @param  htim TIM handle
01165   * @param  Channel TIM Channel to be disabled
01166   *          This parameter can be one of the following values:
01167   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01168   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01169   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01170   * @retval HAL status
01171   */
01172 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01173 {
01174   /* Check the parameters */
01175   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01176
01177   /* Disable the complementary PWM output  */
01178   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01179
01180   /* Disable the Main Output */
01181   __HAL_TIM_MOE_DISABLE(htim);
01182
01183   /* Disable the Peripheral */
01184   __HAL_TIM_DISABLE(htim);
01185
01186   /* Set the TIM complementary channel state */
01187   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01188
01189   /* Return function status */
01190   return HAL_OK;
01191 }
01192
01193 /**
01194   * @brief  Starts the PWM signal generation in interrupt mode on the
01195   *         complementary output.
01196   * @param  htim TIM handle
01197   * @param  Channel TIM Channel to be disabled
01198   *          This parameter can be one of the following values:
01199   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01200   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01201   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01202   * @retval HAL status
01203   */
01204 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01205 {
01206   HAL_StatusTypeDef status = HAL_OK;
01207   uint32_t tmpsmcr;
01208
01209   /* Check the parameters */
01210   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01211
01212   /* Check the TIM complementary channel state */
01213   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
01214   {
01215     return HAL_ERROR;
01216   }
01217
01218   /* Set the TIM complementary channel state */
01219   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01220
01221   switch (Channel)
01222   {
01223     case TIM_CHANNEL_1:
01224     {
01225       /* Enable the TIM Capture/Compare 1 interrupt */
01226       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01227       break;
01228     }
01229
01230     case TIM_CHANNEL_2:
01231     {
01232       /* Enable the TIM Capture/Compare 2 interrupt */
01233       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01234       break;
01235     }
01236
01237     case TIM_CHANNEL_3:
01238     {
01239       /* Enable the TIM Capture/Compare 3 interrupt */
01240       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01241       break;
01242     }
01243
01244     default:
01245       status = HAL_ERROR;
01246       break;
01247   }
01248
01249   if (status == HAL_OK)
01250   {
01251     /* Enable the TIM Break interrupt */
01252     __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01253
01254     /* Enable the complementary PWM output  */
01255     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01256
01257     /* Enable the Main Output */
01258     __HAL_TIM_MOE_ENABLE(htim);
01259
01260     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01261     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01262     {
01263       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01264       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01265       {
01266         __HAL_TIM_ENABLE(htim);
01267       }
01268     }
01269     else
01270     {
01271       __HAL_TIM_ENABLE(htim);
01272     }
01273   }
01274
01275   /* Return function status */
01276   return status;
01277 }
01278
01279 /**
01280   * @brief  Stops the PWM signal generation in interrupt mode on the
01281   *         complementary output.
01282   * @param  htim TIM handle
01283   * @param  Channel TIM Channel to be disabled
01284   *          This parameter can be one of the following values:
01285   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01286   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01287   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01288   * @retval HAL status
01289   */
01290 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01291 {
01292   HAL_StatusTypeDef status = HAL_OK;
01293   uint32_t tmpccer;
01294
01295   /* Check the parameters */
01296   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01297
01298   switch (Channel)
01299   {
01300     case TIM_CHANNEL_1:
01301     {
01302       /* Disable the TIM Capture/Compare 1 interrupt */
01303       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01304       break;
01305     }
01306
01307     case TIM_CHANNEL_2:
01308     {
01309       /* Disable the TIM Capture/Compare 2 interrupt */
01310       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01311       break;
01312     }
01313
01314     case TIM_CHANNEL_3:
01315     {
01316       /* Disable the TIM Capture/Compare 3 interrupt */
01317       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01318       break;
01319     }
01320
01321     default:
01322       status = HAL_ERROR;
01323       break;
01324   }
01325
01326   if (status == HAL_OK)
01327   {
01328     /* Disable the complementary PWM output  */
01329     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01330
01331     /* Disable the TIM Break interrupt (only if no more channel is active) */
01332     tmpccer = htim->Instance->CCER;
01333     if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
01334     {
01335       __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01336     }
01337
01338     /* Disable the Main Output */
01339     __HAL_TIM_MOE_DISABLE(htim);
01340
01341     /* Disable the Peripheral */
01342     __HAL_TIM_DISABLE(htim);
01343
01344     /* Set the TIM complementary channel state */
01345     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01346   }
01347
01348   /* Return function status */
01349   return status;
01350 }
01351
01352 /**
01353   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01354   *         complementary output
01355   * @param  htim TIM handle
01356   * @param  Channel TIM Channel to be enabled
01357   *          This parameter can be one of the following values:
01358   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01359   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01360   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01361   * @param  pData The source Buffer address.
01362   * @param  Length The length of data to be transferred from memory to TIM peripheral
01363   * @retval HAL status
01364   */
01365 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
01366                                            uint16_t Length)
01367 {
01368   HAL_StatusTypeDef status = HAL_OK;
01369   uint32_t tmpsmcr;
01370
01371   /* Check the parameters */
01372   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01373
01374   /* Set the TIM complementary channel state */
01375   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
01376   {
01377     return HAL_BUSY;
01378   }
01379   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
01380   {
01381     if ((pData == NULL) || (Length == 0U))
01382     {
01383       return HAL_ERROR;
01384     }
01385     else
01386     {
01387       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
01388     }
01389   }
01390   else
01391   {
01392     return HAL_ERROR;
01393   }
01394
01395   switch (Channel)
01396   {
01397     case TIM_CHANNEL_1:
01398     {
01399       /* Set the DMA compare callbacks */
01400       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
01401       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01402
01403       /* Set the DMA error callback */
01404       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
01405
01406       /* Enable the DMA channel */
01407       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
01408                            Length) != HAL_OK)
01409       {
01410         /* Return error status */
01411         return HAL_ERROR;
01412       }
01413       /* Enable the TIM Capture/Compare 1 DMA request */
01414       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01415       break;
01416     }
01417
01418     case TIM_CHANNEL_2:
01419     {
01420       /* Set the DMA compare callbacks */
01421       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
01422       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01423
01424       /* Set the DMA error callback */
01425       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
01426
01427       /* Enable the DMA channel */
01428       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
01429                            Length) != HAL_OK)
01430       {
01431         /* Return error status */
01432         return HAL_ERROR;
01433       }
01434       /* Enable the TIM Capture/Compare 2 DMA request */
01435       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01436       break;
01437     }
01438
01439     case TIM_CHANNEL_3:
01440     {
01441       /* Set the DMA compare callbacks */
01442       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
01443       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01444
01445       /* Set the DMA error callback */
01446       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
01447
01448       /* Enable the DMA channel */
01449       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
01450                            Length) != HAL_OK)
01451       {
01452         /* Return error status */
01453         return HAL_ERROR;
01454       }
01455       /* Enable the TIM Capture/Compare 3 DMA request */
01456       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01457       break;
01458     }
01459
01460     default:
01461       status = HAL_ERROR;
01462       break;
01463   }
01464
01465   if (status == HAL_OK)
01466   {
01467     /* Enable the complementary PWM output  */
01468     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01469
01470     /* Enable the Main Output */
01471     __HAL_TIM_MOE_ENABLE(htim);
01472
01473     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01474     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01475     {
01476       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01477       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01478       {
01479         __HAL_TIM_ENABLE(htim);
01480       }
01481     }
01482     else
01483     {
01484       __HAL_TIM_ENABLE(htim);
01485     }
01486   }
01487
01488   /* Return function status */
01489   return status;
01490 }
01491
01492 /**
01493   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01494   *         output
01495   * @param  htim TIM handle
01496   * @param  Channel TIM Channel to be disabled
01497   *          This parameter can be one of the following values:
01498   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01499   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01500   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01501   * @retval HAL status
01502   */
01503 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01504 {
01505   HAL_StatusTypeDef status = HAL_OK;
01506
01507   /* Check the parameters */
01508   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01509
01510   switch (Channel)
01511   {
01512     case TIM_CHANNEL_1:
01513     {
01514       /* Disable the TIM Capture/Compare 1 DMA request */
01515       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01516       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01517       break;
01518     }
01519
01520     case TIM_CHANNEL_2:
01521     {
01522       /* Disable the TIM Capture/Compare 2 DMA request */
01523       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01524       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01525       break;
01526     }
01527
01528     case TIM_CHANNEL_3:
01529     {
01530       /* Disable the TIM Capture/Compare 3 DMA request */
01531       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01532       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01533       break;
01534     }
01535
01536     default:
01537       status = HAL_ERROR;
01538       break;
01539   }
01540
01541   if (status == HAL_OK)
01542   {
01543     /* Disable the complementary PWM output */
01544     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01545
01546     /* Disable the Main Output */
01547     __HAL_TIM_MOE_DISABLE(htim);
01548
01549     /* Disable the Peripheral */
01550     __HAL_TIM_DISABLE(htim);
01551
01552     /* Set the TIM complementary channel state */
01553     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
01554   }
01555
01556   /* Return function status */
01557   return status;
01558 }
01559
01560 /**
01561   * @}
01562   */
01563
01564 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
01565   * @brief    Timer Complementary One Pulse functions
01566   *
01567 @verbatim
01568   ==============================================================================
01569                 ##### Timer Complementary One Pulse functions #####
01570   ==============================================================================
01571   [..]
01572     This section provides functions allowing to:
01573     (+) Start the Complementary One Pulse generation.
01574     (+) Stop the Complementary One Pulse.
01575     (+) Start the Complementary One Pulse and enable interrupts.
01576     (+) Stop the Complementary One Pulse and disable interrupts.
01577
01578 @endverbatim
01579   * @{
01580   */
01581
01582 /**
01583   * @brief  Starts the TIM One Pulse signal generation on the complementary
01584   *         output.
01585   * @note OutputChannel must match the pulse output channel chosen when calling
01586   *       @ref HAL_TIM_OnePulse_ConfigChannel().
01587   * @param  htim TIM One Pulse handle
01588   * @param  OutputChannel pulse output channel to enable
01589   *          This parameter can be one of the following values:
01590   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01591   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01592   * @retval HAL status
01593   */
01594 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01595 {
01596   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
01597   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
01598   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
01599   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
01600   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
01601
01602   /* Check the parameters */
01603   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01604
01605   /* Check the TIM channels state */
01606   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
01607       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
01608       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
01609       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
01610   {
01611     return HAL_ERROR;
01612   }
01613
01614   /* Set the TIM channels state */
01615   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
01616   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
01617   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
01618   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
01619
01620   /* Enable the complementary One Pulse output channel and the Input Capture channel */
01621   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01622   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
01623
01624   /* Enable the Main Output */
01625   __HAL_TIM_MOE_ENABLE(htim);
01626
01627   /* Return function status */
01628   return HAL_OK;
01629 }
01630
01631 /**
01632   * @brief  Stops the TIM One Pulse signal generation on the complementary
01633   *         output.
01634   * @note OutputChannel must match the pulse output channel chosen when calling
01635   *       @ref HAL_TIM_OnePulse_ConfigChannel().
01636   * @param  htim TIM One Pulse handle
01637   * @param  OutputChannel pulse output channel to disable
01638   *          This parameter can be one of the following values:
01639   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01640   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01641   * @retval HAL status
01642   */
01643 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01644 {
01645   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
01646
01647   /* Check the parameters */
01648   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01649
01650   /* Disable the complementary One Pulse output channel and the Input Capture channel */
01651   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01652   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
01653
01654   /* Disable the Main Output */
01655   __HAL_TIM_MOE_DISABLE(htim);
01656
01657   /* Disable the Peripheral */
01658   __HAL_TIM_DISABLE(htim);
01659
01660   /* Set the TIM  channels state */
01661   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
01662   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
01663   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
01664   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
01665
01666   /* Return function status */
01667   return HAL_OK;
01668 }
01669
01670 /**
01671   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01672   *         complementary channel.
01673   * @note OutputChannel must match the pulse output channel chosen when calling
01674   *       @ref HAL_TIM_OnePulse_ConfigChannel().
01675   * @param  htim TIM One Pulse handle
01676   * @param  OutputChannel pulse output channel to enable
01677   *          This parameter can be one of the following values:
01678   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01679   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01680   * @retval HAL status
01681   */
01682 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01683 {
01684   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
01685   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
01686   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
01687   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
01688   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
01689
01690   /* Check the parameters */
01691   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01692
01693   /* Check the TIM channels state */
01694   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
01695       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
01696       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
01697       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
01698   {
01699     return HAL_ERROR;
01700   }
01701
01702   /* Set the TIM channels state */
01703   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
01704   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
01705   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
01706   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
01707
01708   /* Enable the TIM Capture/Compare 1 interrupt */
01709   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01710
01711   /* Enable the TIM Capture/Compare 2 interrupt */
01712   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01713
01714   /* Enable the complementary One Pulse output channel and the Input Capture channel */
01715   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01716   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
01717
01718   /* Enable the Main Output */
01719   __HAL_TIM_MOE_ENABLE(htim);
01720
01721   /* Return function status */
01722   return HAL_OK;
01723 }
01724
01725 /**
01726   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01727   *         complementary channel.
01728   * @note OutputChannel must match the pulse output channel chosen when calling
01729   *       @ref HAL_TIM_OnePulse_ConfigChannel().
01730   * @param  htim TIM One Pulse handle
01731   * @param  OutputChannel pulse output channel to disable
01732   *          This parameter can be one of the following values:
01733   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01734   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01735   * @retval HAL status
01736   */
01737 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01738 {
01739   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
01740
01741   /* Check the parameters */
01742   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01743
01744   /* Disable the TIM Capture/Compare 1 interrupt */
01745   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01746
01747   /* Disable the TIM Capture/Compare 2 interrupt */
01748   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01749
01750   /* Disable the complementary One Pulse output channel and the Input Capture channel */
01751   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01752   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
01753
01754   /* Disable the Main Output */
01755   __HAL_TIM_MOE_DISABLE(htim);
01756
01757   /* Disable the Peripheral */
01758   __HAL_TIM_DISABLE(htim);
01759
01760   /* Set the TIM  channels state */
01761   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
01762   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
01763   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
01764   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
01765
01766   /* Return function status */
01767   return HAL_OK;
01768 }
01769
01770 /**
01771   * @}
01772   */
01773
01774 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
01775   * @brief    Peripheral Control functions
01776   *
01777 @verbatim
01778   ==============================================================================
01779                     ##### Peripheral Control functions #####
01780   ==============================================================================
01781   [..]
01782     This section provides functions allowing to:
01783       (+) Configure the commutation event in case of use of the Hall sensor interface.
01784       (+) Configure Output channels for OC and PWM mode.
01785
01786       (+) Configure Complementary channels, break features and dead time.
01787       (+) Configure Master synchronization.
01788       (+) Configure timer remapping capabilities.
01789       (+) Select timer input source.
01790       (+) Enable or disable channel grouping.
01791
01792 @endverbatim
01793   * @{
01794   */
01795
01796 /**
01797   * @brief  Configure the TIM commutation event sequence.
01798   * @note  This function is mandatory to use the commutation event in order to
01799   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01800   *        the typical use of this feature is with the use of another Timer(interface Timer)
01801   *        configured in Hall sensor interface, this interface Timer will generate the
01802   *        commutation at its TRGO output (connected to Timer used in this function) each time
01803   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01804   * @param  htim TIM handle
01805   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01806   *          This parameter can be one of the following values:
01807   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01808   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01809   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01810   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01811   *            @arg TIM_TS_NONE: No trigger is needed
01812   * @param  CommutationSource the Commutation Event source
01813   *          This parameter can be one of the following values:
01814   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01815   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01816   * @retval HAL status
01817   */
01818 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01819                                               uint32_t  CommutationSource)
01820 {
01821   /* Check the parameters */
01822   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01823   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01824
01825   __HAL_LOCK(htim);
01826
01827   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01828       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01829   {
01830     /* Select the Input trigger */
01831     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01832     htim->Instance->SMCR |= InputTrigger;
01833   }
01834
01835   /* Select the Capture Compare preload feature */
01836   htim->Instance->CR2 |= TIM_CR2_CCPC;
01837   /* Select the Commutation event source */
01838   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01839   htim->Instance->CR2 |= CommutationSource;
01840
01841   /* Disable Commutation Interrupt */
01842   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
01843
01844   /* Disable Commutation DMA request */
01845   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
01846
01847   __HAL_UNLOCK(htim);
01848
01849   return HAL_OK;
01850 }
01851
01852 /**
01853   * @brief  Configure the TIM commutation event sequence with interrupt.
01854   * @note  This function is mandatory to use the commutation event in order to
01855   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01856   *        the typical use of this feature is with the use of another Timer(interface Timer)
01857   *        configured in Hall sensor interface, this interface Timer will generate the
01858   *        commutation at its TRGO output (connected to Timer used in this function) each time
01859   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01860   * @param  htim TIM handle
01861   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01862   *          This parameter can be one of the following values:
01863   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01864   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01865   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01866   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01867   *            @arg TIM_TS_NONE: No trigger is needed
01868   * @param  CommutationSource the Commutation Event source
01869   *          This parameter can be one of the following values:
01870   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01871   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01872   * @retval HAL status
01873   */
01874 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01875                                                  uint32_t  CommutationSource)
01876 {
01877   /* Check the parameters */
01878   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01879   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01880
01881   __HAL_LOCK(htim);
01882
01883   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01884       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01885   {
01886     /* Select the Input trigger */
01887     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01888     htim->Instance->SMCR |= InputTrigger;
01889   }
01890
01891   /* Select the Capture Compare preload feature */
01892   htim->Instance->CR2 |= TIM_CR2_CCPC;
01893   /* Select the Commutation event source */
01894   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01895   htim->Instance->CR2 |= CommutationSource;
01896
01897   /* Disable Commutation DMA request */
01898   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
01899
01900   /* Enable the Commutation Interrupt */
01901   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01902
01903   __HAL_UNLOCK(htim);
01904
01905   return HAL_OK;
01906 }
01907
01908 /**
01909   * @brief  Configure the TIM commutation event sequence with DMA.
01910   * @note  This function is mandatory to use the commutation event in order to
01911   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01912   *        the typical use of this feature is with the use of another Timer(interface Timer)
01913   *        configured in Hall sensor interface, this interface Timer will generate the
01914   *        commutation at its TRGO output (connected to Timer used in this function) each time
01915   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01916   * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
01917   * @param  htim TIM handle
01918   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01919   *          This parameter can be one of the following values:
01920   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01921   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01922   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01923   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01924   *            @arg TIM_TS_NONE: No trigger is needed
01925   * @param  CommutationSource the Commutation Event source
01926   *          This parameter can be one of the following values:
01927   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01928   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01929   * @retval HAL status
01930   */
01931 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01932                                                   uint32_t  CommutationSource)
01933 {
01934   /* Check the parameters */
01935   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01936   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01937
01938   __HAL_LOCK(htim);
01939
01940   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01941       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01942   {
01943     /* Select the Input trigger */
01944     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01945     htim->Instance->SMCR |= InputTrigger;
01946   }
01947
01948   /* Select the Capture Compare preload feature */
01949   htim->Instance->CR2 |= TIM_CR2_CCPC;
01950   /* Select the Commutation event source */
01951   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01952   htim->Instance->CR2 |= CommutationSource;
01953
01954   /* Enable the Commutation DMA Request */
01955   /* Set the DMA Commutation Callback */
01956   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
01957   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
01958   /* Set the DMA error callback */
01959   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
01960
01961   /* Disable Commutation Interrupt */
01962   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
01963
01964   /* Enable the Commutation DMA Request */
01965   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01966
01967   __HAL_UNLOCK(htim);
01968
01969   return HAL_OK;
01970 }
01971
01972 /**
01973   * @brief  Configures the TIM in master mode.
01974   * @param  htim TIM handle.
01975   * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
01976   *         contains the selected trigger output (TRGO) and the Master/Slave
01977   *         mode.
01978   * @retval HAL status
01979   */
01980 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
01981                                                         const TIM_MasterConfigTypeDef *sMasterConfig)
01982 {
01983   uint32_t tmpcr2;
01984   uint32_t tmpsmcr;
01985
01986   /* Check the parameters */
01987   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
01988   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01989   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01990
01991   /* Check input state */
01992   __HAL_LOCK(htim);
01993
01994   /* Change the handler state */
01995   htim->State = HAL_TIM_STATE_BUSY;
01996
01997   /* Get the TIMx CR2 register value */
01998   tmpcr2 = htim->Instance->CR2;
01999
02000   /* Get the TIMx SMCR register value */
02001   tmpsmcr = htim->Instance->SMCR;
02002
02003   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
02004   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
02005   {
02006     /* Check the parameters */
02007     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
02008
02009     /* Clear the MMS2 bits */
02010     tmpcr2 &= ~TIM_CR2_MMS2;
02011     /* Select the TRGO2 source*/
02012     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
02013   }
02014
02015   /* Reset the MMS Bits */
02016   tmpcr2 &= ~TIM_CR2_MMS;
02017   /* Select the TRGO source */
02018   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
02019
02020   /* Update TIMx CR2 */
02021   htim->Instance->CR2 = tmpcr2;
02022
02023   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
02024   {
02025     /* Reset the MSM Bit */
02026     tmpsmcr &= ~TIM_SMCR_MSM;
02027     /* Set master mode */
02028     tmpsmcr |= sMasterConfig->MasterSlaveMode;
02029
02030     /* Update TIMx SMCR */
02031     htim->Instance->SMCR = tmpsmcr;
02032   }
02033
02034   /* Change the htim state */
02035   htim->State = HAL_TIM_STATE_READY;
02036
02037   __HAL_UNLOCK(htim);
02038
02039   return HAL_OK;
02040 }
02041
02042 /**
02043   * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
02044   *         and the AOE(automatic output enable).
02045   * @param  htim TIM handle
02046   * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
02047   *         contains the BDTR Register configuration  information for the TIM peripheral.
02048   * @note   Interrupts can be generated when an active level is detected on the
02049   *         break input, the break 2 input or the system break input. Break
02050   *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
02051   * @retval HAL status
02052   */
02053 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
02054                                                 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
02055 {
02056   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
02057   uint32_t tmpbdtr = 0U;
02058
02059   /* Check the parameters */
02060   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02061   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
02062   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
02063   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
02064   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
02065   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
02066   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
02067   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
02068   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
02069
02070   /* Check input state */
02071   __HAL_LOCK(htim);
02072
02073   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
02074      the OSSI State, the dead time value and the Automatic Output Enable Bit */
02075
02076   /* Set the BDTR bits */
02077   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
02078   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
02079   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
02080   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
02081   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
02082   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
02083   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
02084   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
02085
02086   if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
02087   {
02088     /* Check the parameters */
02089     assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
02090
02091     /* Set BREAK AF mode */
02092     MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
02093   }
02094
02095   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
02096   {
02097     /* Check the parameters */
02098     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
02099     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
02100     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
02101
02102     /* Set the BREAK2 input related BDTR bits */
02103     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
02104     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
02105     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
02106
02107     if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
02108     {
02109       /* Check the parameters */
02110       assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
02111
02112       /* Set BREAK2 AF mode */
02113       MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
02114     }
02115   }
02116
02117   /* Set TIMx_BDTR */
02118   htim->Instance->BDTR = tmpbdtr;
02119
02120   __HAL_UNLOCK(htim);
02121
02122   return HAL_OK;
02123 }
02124
02125 /**
02126   * @brief  Configures the break input source.
02127   * @param  htim TIM handle.
02128   * @param  BreakInput Break input to configure
02129   *          This parameter can be one of the following values:
02130   *            @arg TIM_BREAKINPUT_BRK: Timer break input
02131   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
02132   * @param  sBreakInputConfig Break input source configuration
02133   * @retval HAL status
02134   */
02135 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
02136                                              uint32_t BreakInput,
02137                                              const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
02138
02139 {
02140   HAL_StatusTypeDef status = HAL_OK;
02141   uint32_t tmporx;
02142   uint32_t bkin_enable_mask;
02143   uint32_t bkin_polarity_mask;
02144   uint32_t bkin_enable_bitpos;
02145   uint32_t bkin_polarity_bitpos;
02146
02147   /* Check the parameters */
02148   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
02149   assert_param(IS_TIM_BREAKINPUT(BreakInput));
02150   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
02151   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
02152   assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
02153
02154   /* Check input state */
02155   __HAL_LOCK(htim);
02156
02157   switch (sBreakInputConfig->Source)
02158   {
02159     case TIM_BREAKINPUTSOURCE_BKIN:
02160     {
02161       bkin_enable_mask = TIM1_AF1_BKINE;
02162       bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
02163       bkin_polarity_mask = TIM1_AF1_BKINP;
02164       bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
02165       break;
02166     }
02167 #if defined(COMP1) && defined(COMP2)
02168     case TIM_BREAKINPUTSOURCE_COMP1:
02169     {
02170       bkin_enable_mask = TIM1_AF1_BKCMP1E;
02171       bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
02172       bkin_polarity_mask = TIM1_AF1_BKCMP1P;
02173       bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
02174       break;
02175     }
02176     case TIM_BREAKINPUTSOURCE_COMP2:
02177     {
02178       bkin_enable_mask = TIM1_AF1_BKCMP2E;
02179       bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
02180       bkin_polarity_mask = TIM1_AF1_BKCMP2P;
02181       bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
02182       break;
02183     }
02184 #endif /* COMP1 && COMP2 */
02185 #if defined(COMP3)
02186     case TIM_BREAKINPUTSOURCE_COMP3:
02187     {
02188       bkin_enable_mask = TIM1_AF1_BKCMP3E;
02189       bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
02190       bkin_polarity_mask = TIM1_AF1_BKCMP3P;
02191       bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
02192       break;
02193     }
02194 #endif /* COMP3 */
02195
02196     default:
02197     {
02198       bkin_enable_mask = 0U;
02199       bkin_polarity_mask = 0U;
02200       bkin_enable_bitpos = 0U;
02201       bkin_polarity_bitpos = 0U;
02202       break;
02203     }
02204   }
02205
02206   switch (BreakInput)
02207   {
02208     case TIM_BREAKINPUT_BRK:
02209     {
02210       /* Get the TIMx_AF1 register value */
02211       tmporx = htim->Instance->AF1;
02212
02213       /* Enable the break input */
02214       tmporx &= ~bkin_enable_mask;
02215       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
02216
02217       /* Set the break input polarity */
02218       tmporx &= ~bkin_polarity_mask;
02219       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
02220
02221       /* Set TIMx_AF1 */
02222       htim->Instance->AF1 = tmporx;
02223       break;
02224     }
02225     case TIM_BREAKINPUT_BRK2:
02226     {
02227       /* Get the TIMx_AF2 register value */
02228       tmporx = htim->Instance->AF2;
02229
02230       /* Enable the break input */
02231       tmporx &= ~bkin_enable_mask;
02232       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
02233
02234       /* Set the break input polarity */
02235       tmporx &= ~bkin_polarity_mask;
02236       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
02237
02238       /* Set TIMx_AF2 */
02239       htim->Instance->AF2 = tmporx;
02240       break;
02241     }
02242     default:
02243       status = HAL_ERROR;
02244       break;
02245   }
02246
02247   __HAL_UNLOCK(htim);
02248
02249   return status;
02250 }
02251
02252 /**
02253   * @brief  Configures the TIMx Remapping input capabilities.
02254   * @param  htim TIM handle.
02255   * @param  Remap specifies the TIM remapping source.
02256   *         For TIM1, the parameter can take one of the following values:
02257   *            @arg TIM_TIM1_ETR_GPIO:                TIM1 ETR is is connected to GPIO
02258   *            @arg TIM_TIM1_ETR_COMP1:               TIM1 ETR is connected to COMP1 output
02259   *            @arg TIM_TIM1_ETR_COMP2:               TIM1 ETR is connected to COMP2 output
02260   *            @arg TIM_TIM1_ETR_COMP3:               TIM1 ETR is connected to COMP3 output    (**)
02261   *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1 ETR is connected to ADC1 AWD1
02262   *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1 ETR is connected to ADC1 AWD2
02263   *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1 ETR is connected to ADC1 AWD3
02264   *
02265   *         For TIM2, the parameter can take one of the following values: (*)
02266   *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
02267   *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
02268   *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
02269   *            @arg TIM_TIM2_ETR_COMP3:               TIM2_ETR is connected to COMP3 output    (**)
02270   *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
02271   *            @arg TIM_TIM2_ETR_MCO:                 TIM2_ETR is connected to MCO             (**)
02272   *            @arg TIM_TIM2_ETR_MCO2:                TIM2_ETR is connected to MCO2            (**)
02273   *
02274   *         For TIM3, the parameter can take one of the following values:
02275   *            @arg TIM_TIM3_ETR_GPIO                TIM3_ETR is connected to GPIO
02276   *            @arg TIM_TIM3_ETR_COMP1               TIM3_ETR is connected to COMP1 output
02277   *            @arg TIM_TIM3_ETR_COMP2               TIM3_ETR is connected to COMP2 output
02278   *            @arg TIM_TIM3_ETR_COMP3               TIM3_ETR is connected to COMP3 output    (**)
02279   *
02280   *         For TIM4, the parameter can take one of the following values:(*)
02281   *            @arg TIM_TIM4_ETR_GPIO                TIM4_ETR is connected to GPIO
02282   *            @arg TIM_TIM4_ETR_COMP1               TIM4_ETR is connected to COMP1 output
02283   *            @arg TIM_TIM4_ETR_COMP2               TIM4_ETR is connected to COMP2 output
02284   *            @arg TIM_TIM4_ETR_COMP3               TIM4_ETR is connected to COMP3 output    (**)
02285   *
02286   *  (*) Timer instance not available on all devices \n
02287   *  (**) Value not defined in all devices. \n
02288   *
02289   * @retval HAL status
02290   */
02291 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
02292 {
02293   /* Check parameters */
02294   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
02295   assert_param(IS_TIM_REMAP(Remap));
02296
02297   __HAL_LOCK(htim);
02298
02299   MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
02300
02301   __HAL_UNLOCK(htim);
02302
02303   return HAL_OK;
02304 }
02305
02306 /**
02307   * @brief  Select the timer input source
02308   * @param  htim TIM handle.
02309   * @param  Channel specifies the TIM Channel
02310   *          This parameter can be one of the following values:
02311   *            @arg TIM_CHANNEL_1: TI1 input channel
02312   *            @arg TIM_CHANNEL_2: TI2 input channel
02313   *            @arg TIM_CHANNEL_3: TI3 input channel
02314   * @param  TISelection specifies the timer input source
02315   *
02316   *         For TIM1 this parameter can be one of the following values:
02317   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
02318   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
02319   *            @arg TIM_TIM1_TI2_GPIO:                TIM1 TI2 is connected to GPIO
02320   *            @arg TIM_TIM1_TI2_COMP2:               TIM1 TI2 is connected to COMP2 output
02321   *            @arg TIM_TIM1_TI3_GPIO:                TIM1 TI3 is connected to GPIO
02322   *            @arg TIM_TIM1_TI3_COMP3:               TIM1 TI3 is connected to COMP3 output   (**)
02323   *
02324   *         For TIM2, the parameter is one of the following values: (*)
02325   *            @arg TIM_TIM2_TI1_GPIO:                TIM2 TI1 is connected to GPIO
02326   *            @arg TIM_TIM2_TI1_COMP1:               TIM2 TI1 is connected to COMP1 output
02327   *            @arg TIM_TIM2_TI2_GPIO:                TIM2 TI2 is connected to GPIO
02328   *            @arg TIM_TIM2_TI2_COMP2:               TIM2 TI2 is connected to COMP2 output
02329   *            @arg TIM_TIM2_TI3_GPIO:                TIM2 TI3 is connected to GPIO
02330   *            @arg TIM_TIM2_TI3_COMP3:               TIM2 TI3 is connected to COMP3 output   (**)
02331   *
02332   *         For TIM3, the parameter is one of the following values:
02333   *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
02334   *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
02335   *            @arg TIM_TIM3_TI2_GPIO:                TIM3 TI2 is connected to GPIO
02336   *            @arg TIM_TIM3_TI2_COMP2:               TIM3 TI2 is connected to COMP2 output
02337   *            @arg TIM_TIM3_TI3_GPIO:                TIM3 TI3 is connected to GPIO
02338   *            @arg TIM_TIM3_TI3_COMP3:               TIM3 TI3 is connected to COMP3 output   (**)
02339   *
02340   *         For TIM4, the parameter is one of the following values: (*)
02341   *            @arg TIM_TIM4_TI1_GPIO:                TIM4 TI1 is connected to GPIO
02342   *            @arg TIM_TIM4_TI1_COMP1:               TIM4 TI1 is connected to COMP1 output
02343   *            @arg TIM_TIM4_TI2_GPIO:                TIM4 TI2 is connected to GPIO
02344   *            @arg TIM_TIM4_TI2_COMP2:               TIM4 TI2 is connected to COMP2 output
02345   *            @arg TIM_TIM4_TI3_GPIO:                TIM4 TI3 is connected to GPIO
02346   *            @arg TIM_TIM4_TI3_COMP3:               TIM4 TI3 is connected to COMP3 output
02347   *
02348   *         For TIM14, the parameter is one of the following values:
02349   *            @arg TIM_TIM14_TI1_GPIO:               TIM14 TI1 is connected to GPIO
02350   *            @arg TIM_TIM14_TI1_RTC:                TIM14 TI1 is connected to RTC clock
02351   *            @arg TIM_TIM14_TI1_HSE_32:             TIM14 TI1 is connected to HSE div 32
02352   *            @arg TIM_TIM14_TI1_MCO:                TIM14 TI1 is connected to MCO
02353   *            @arg TIM_TIM14_TI1_MCO2:               TIM14 TI1 is connected to MCO2          (**)
02354   *
02355   *         For TIM15, the parameter is one of the following values:
02356   *            @arg TIM_TIM15_TI1_GPIO:               TIM15 TI1 is connected to GPIO
02357   *            @arg TIM_TIM15_TI1_TIM2_CH1:           TIM15 TI1 is connected to TIM2 CH1
02358   *            @arg TIM_TIM15_TI1_TIM3_CH1:           TIM15 TI1 is connected to TIM3 CH1
02359   *            @arg TIM_TIM15_TI2_GPIO:               TIM15 TI2 is connected to GPIO
02360   *            @arg TIM_TIM15_TI2_TIM2_CH2:           TIM15 TI2 is connected to TIM2 CH2
02361   *            @arg TIM_TIM15_TI2_TIM3_CH2:           TIM15 TI2 is connected to TIM3 CH2
02362   *
02363   *         For TIM16, the parameter can have the following values:
02364   *            @arg TIM_TIM16_TI1_GPIO:               TIM16 TI1 is connected to GPIO
02365   *            @arg TIM_TIM16_TI1_LSI:                TIM16 TI1 is connected to LSI
02366   *            @arg TIM_TIM16_TI1_LSE:                TIM16 TI1 is connected to LSE
02367   *            @arg TIM_TIM16_TI1_RTC_WAKEUP:         TIM16 TI1 is connected to TRC wakeup interrupt
02368   *            @arg TIM_TIM16_TI1_MCO2:               TIM16 TI1 is connected to MCO2          (**)
02369   *
02370   *         For TIM17, the parameter can have the following values:
02371   *            @arg TIM_TIM17_TI1_GPIO:               TIM17 TI1 is connected to GPIO
02372   *            @arg TIM_TIM14_TI1_HSI:                TIM17 TI1 is connected to HSI           (**)
02373   *            @arg TIM_TIM17_TI1_HSE_32:             TIM17 TI1 is connected to HSE div 32
02374   *            @arg TIM_TIM17_TI1_MCO:                TIM17 TI1 is connected to MCO
02375   *            @arg TIM_TIM17_TI1_MCO2:               TIM17 TI1 is connected to MCO2          (**)
02376   *
02377   *  (*) Timer instance not available on all devices \n
02378   *  (**) Value not defined in all devices. \n
02379   *
02380   * @retval HAL status
02381   */
02382 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
02383 {
02384   HAL_StatusTypeDef status = HAL_OK;
02385
02386   /* Check parameters */
02387   assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
02388   assert_param(IS_TIM_TISEL(TISelection));
02389
02390   __HAL_LOCK(htim);
02391
02392   switch (Channel)
02393   {
02394     case TIM_CHANNEL_1:
02395       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
02396       break;
02397     case TIM_CHANNEL_2:
02398       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
02399       break;
02400     case TIM_CHANNEL_3:
02401       MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
02402       break;
02403     default:
02404       status = HAL_ERROR;
02405       break;
02406   }
02407
02408   __HAL_UNLOCK(htim);
02409
02410   return status;
02411 }
02412
02413 /**
02414   * @brief  Group channel 5 and channel 1, 2 or 3
02415   * @param  htim TIM handle.
02416   * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
02417   *         This parameter can be any combination of the following values:
02418   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
02419   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
02420   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
02421   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
02422   * @retval HAL status
02423   */
02424 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
02425 {
02426   /* Check parameters */
02427   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
02428   assert_param(IS_TIM_GROUPCH5(Channels));
02429
02430   /* Process Locked */
02431   __HAL_LOCK(htim);
02432
02433   htim->State = HAL_TIM_STATE_BUSY;
02434
02435   /* Clear GC5Cx bit fields */
02436   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
02437
02438   /* Set GC5Cx bit fields */
02439   htim->Instance->CCR5 |= Channels;
02440
02441   /* Change the htim state */
02442   htim->State = HAL_TIM_STATE_READY;
02443
02444   __HAL_UNLOCK(htim);
02445
02446   return HAL_OK;
02447 }
02448
02449 /**
02450   * @brief  Disarm the designated break input (when it operates in bidirectional mode).
02451   * @param  htim TIM handle.
02452   * @param  BreakInput Break input to disarm
02453   *          This parameter can be one of the following values:
02454   *            @arg TIM_BREAKINPUT_BRK: Timer break input
02455   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
02456   * @note  The break input can be disarmed only when it is configured in
02457   *        bidirectional mode and when when MOE is reset.
02458   * @note  Purpose is to be able to have the input voltage back to high-state,
02459   *        whatever the time constant on the output .
02460   * @retval HAL status
02461   */
02462 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
02463 {
02464   HAL_StatusTypeDef status = HAL_OK;
02465   uint32_t tmpbdtr;
02466
02467   /* Check the parameters */
02468   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
02469   assert_param(IS_TIM_BREAKINPUT(BreakInput));
02470
02471   switch (BreakInput)
02472   {
02473     case TIM_BREAKINPUT_BRK:
02474     {
02475       /* Check initial conditions */
02476       tmpbdtr = READ_REG(htim->Instance->BDTR);
02477       if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
02478           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
02479       {
02480         /* Break input BRK is disarmed */
02481         SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
02482       }
02483       break;
02484     }
02485
02486     case TIM_BREAKINPUT_BRK2:
02487     {
02488       /* Check initial conditions */
02489       tmpbdtr = READ_REG(htim->Instance->BDTR);
02490       if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
02491           (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
02492       {
02493         /* Break input BRK is disarmed */
02494         SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
02495       }
02496       break;
02497     }
02498     default:
02499       status = HAL_ERROR;
02500       break;
02501   }
02502
02503   return status;
02504 }
02505
02506 /**
02507   * @brief  Arm the designated break input (when it operates in bidirectional mode).
02508   * @param  htim TIM handle.
02509   * @param  BreakInput Break input to arm
02510   *          This parameter can be one of the following values:
02511   *            @arg TIM_BREAKINPUT_BRK: Timer break input
02512   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
02513   * @note  Arming is possible at anytime, even if fault is present.
02514   * @note  Break input is automatically armed as soon as MOE bit is set.
02515   * @retval HAL status
02516   */
02517 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
02518 {
02519   HAL_StatusTypeDef status = HAL_OK;
02520   uint32_t tickstart;
02521
02522   /* Check the parameters */
02523   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
02524   assert_param(IS_TIM_BREAKINPUT(BreakInput));
02525
02526   switch (BreakInput)
02527   {
02528     case TIM_BREAKINPUT_BRK:
02529     {
02530       /* Check initial conditions */
02531       if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
02532       {
02533         /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
02534         /* Init tickstart for timeout management */
02535         tickstart = HAL_GetTick();
02536         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
02537         {
02538           if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
02539           {
02540             /* New check to avoid false timeout detection in case of preemption */
02541             if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
02542             {
02543               return HAL_TIMEOUT;
02544             }
02545           }
02546         }
02547       }
02548       break;
02549     }
02550
02551     case TIM_BREAKINPUT_BRK2:
02552     {
02553       /* Check initial conditions */
02554       if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
02555       {
02556         /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
02557         /* Init tickstart for timeout management */
02558         tickstart = HAL_GetTick();
02559         while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
02560         {
02561           if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
02562           {
02563             /* New check to avoid false timeout detection in case of preemption */
02564             if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
02565             {
02566               return HAL_TIMEOUT;
02567             }
02568           }
02569         }
02570       }
02571       break;
02572     }
02573     default:
02574       status = HAL_ERROR;
02575       break;
02576   }
02577
02578   return status;
02579 }
02580
02581 /**
02582   * @}
02583   */
02584
02585 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
02586   * @brief    Extended Callbacks functions
02587   *
02588 @verbatim
02589   ==============================================================================
02590                     ##### Extended Callbacks functions #####
02591   ==============================================================================
02592   [..]
02593     This section provides Extended TIM callback functions:
02594     (+) Timer Commutation callback
02595     (+) Timer Break callback
02596
02597 @endverbatim
02598   * @{
02599   */
02600
02601 /**
02602   * @brief  Hall commutation changed callback in non-blocking mode
02603   * @param  htim TIM handle
02604   * @retval None
02605   */
02606 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
02607 {
02608   /* Prevent unused argument(s) compilation warning */
02609   UNUSED(htim);
02610
02611   /* NOTE : This function should not be modified, when the callback is needed,
02612             the HAL_TIMEx_CommutCallback could be implemented in the user file
02613    */
02614 }
02615 /**
02616   * @brief  Hall commutation changed half complete callback in non-blocking mode
02617   * @param  htim TIM handle
02618   * @retval None
02619   */
02620 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
02621 {
02622   /* Prevent unused argument(s) compilation warning */
02623   UNUSED(htim);
02624
02625   /* NOTE : This function should not be modified, when the callback is needed,
02626             the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
02627    */
02628 }
02629
02630 /**
02631   * @brief  Hall Break detection callback in non-blocking mode
02632   * @param  htim TIM handle
02633   * @retval None
02634   */
02635 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
02636 {
02637   /* Prevent unused argument(s) compilation warning */
02638   UNUSED(htim);
02639
02640   /* NOTE : This function should not be modified, when the callback is needed,
02641             the HAL_TIMEx_BreakCallback could be implemented in the user file
02642    */
02643 }
02644
02645 /**
02646   * @brief  Hall Break2 detection callback in non blocking mode
02647   * @param  htim: TIM handle
02648   * @retval None
02649   */
02650 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
02651 {
02652   /* Prevent unused argument(s) compilation warning */
02653   UNUSED(htim);
02654
02655   /* NOTE : This function Should not be modified, when the callback is needed,
02656             the HAL_TIMEx_Break2Callback could be implemented in the user file
02657    */
02658 }
02659 /**
02660   * @}
02661   */
02662
02663 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02664   * @brief    Extended Peripheral State functions
02665   *
02666 @verbatim
02667   ==============================================================================
02668                 ##### Extended Peripheral State functions #####
02669   ==============================================================================
02670   [..]
02671     This subsection permits to get in run-time the status of the peripheral
02672     and the data flow.
02673
02674 @endverbatim
02675   * @{
02676   */
02677
02678 /**
02679   * @brief  Return the TIM Hall Sensor interface handle state.
02680   * @param  htim TIM Hall Sensor handle
02681   * @retval HAL state
02682   */
02683 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
02684 {
02685   return htim->State;
02686 }
02687
02688 /**
02689   * @brief  Return actual state of the TIM complementary channel.
02690   * @param  htim TIM handle
02691   * @param  ChannelN TIM Complementary channel
02692   *          This parameter can be one of the following values:
02693   *            @arg TIM_CHANNEL_1: TIM Channel 1
02694   *            @arg TIM_CHANNEL_2: TIM Channel 2
02695   *            @arg TIM_CHANNEL_3: TIM Channel 3
02696   * @retval TIM Complementary channel state
02697   */
02698 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN)
02699 {
02700   HAL_TIM_ChannelStateTypeDef channel_state;
02701
02702   /* Check the parameters */
02703   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
02704
02705   channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
02706
02707   return channel_state;
02708 }
02709 /**
02710   * @}
02711   */
02712
02713 /**
02714   * @}
02715   */
02716
02717 /* Private functions ---------------------------------------------------------*/
02718 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
02719   * @{
02720   */
02721
02722 /**
02723   * @brief  TIM DMA Commutation callback.
02724   * @param  hdma pointer to DMA handle.
02725   * @retval None
02726   */
02727 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
02728 {
02729   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02730
02731   /* Change the htim state */
02732   htim->State = HAL_TIM_STATE_READY;
02733
02734 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02735   htim->CommutationCallback(htim);
02736 #else
02737   HAL_TIMEx_CommutCallback(htim);
02738 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02739 }
02740
02741 /**
02742   * @brief  TIM DMA Commutation half complete callback.
02743   * @param  hdma pointer to DMA handle.
02744   * @retval None
02745   */
02746 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
02747 {
02748   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02749
02750   /* Change the htim state */
02751   htim->State = HAL_TIM_STATE_READY;
02752
02753 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02754   htim->CommutationHalfCpltCallback(htim);
02755 #else
02756   HAL_TIMEx_CommutHalfCpltCallback(htim);
02757 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02758 }
02759
02760
02761 /**
02762   * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
02763   * @param  hdma pointer to DMA handle.
02764   * @retval None
02765   */
02766 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
02767 {
02768   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02769
02770   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
02771   {
02772     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02773
02774     if (hdma->Init.Mode == DMA_NORMAL)
02775     {
02776       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02777     }
02778   }
02779   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
02780   {
02781     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02782
02783     if (hdma->Init.Mode == DMA_NORMAL)
02784     {
02785       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02786     }
02787   }
02788   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
02789   {
02790     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02791
02792     if (hdma->Init.Mode == DMA_NORMAL)
02793     {
02794       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
02795     }
02796   }
02797   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
02798   {
02799     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
02800
02801     if (hdma->Init.Mode == DMA_NORMAL)
02802     {
02803       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
02804     }
02805   }
02806   else
02807   {
02808     /* nothing to do */
02809   }
02810
02811 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02812   htim->PWM_PulseFinishedCallback(htim);
02813 #else
02814   HAL_TIM_PWM_PulseFinishedCallback(htim);
02815 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02816
02817   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02818 }
02819
02820 /**
02821   * @brief  TIM DMA error callback (complementary channel)
02822   * @param  hdma pointer to DMA handle.
02823   * @retval None
02824   */
02825 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
02826 {
02827   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02828
02829   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
02830   {
02831     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02832     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
02833   }
02834   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
02835   {
02836     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02837     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
02838   }
02839   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
02840   {
02841     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02842     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
02843   }
02844   else
02845   {
02846     /* nothing to do */
02847   }
02848
02849 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02850   htim->ErrorCallback(htim);
02851 #else
02852   HAL_TIM_ErrorCallback(htim);
02853 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02854
02855   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02856 }
02857
02858 /**
02859   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02860   * @param  TIMx to select the TIM peripheral
02861   * @param  Channel specifies the TIM Channel
02862   *          This parameter can be one of the following values:
02863   *            @arg TIM_CHANNEL_1: TIM Channel 1
02864   *            @arg TIM_CHANNEL_2: TIM Channel 2
02865   *            @arg TIM_CHANNEL_3: TIM Channel 3
02866   * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
02867   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
02868   * @retval None
02869   */
02870 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
02871 {
02872   uint32_t tmp;
02873
02874   tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
02875
02876   /* Reset the CCxNE Bit */
02877   TIMx->CCER &=  ~tmp;
02878
02879   /* Set or reset the CCxNE Bit */
02880   TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
02881 }
02882 /**
02883   * @}
02884   */
02885
02886 #endif /* HAL_TIM_MODULE_ENABLED */
02887 /**
02888   * @}
02889   */
02890
02891 /**
02892   * @}
02893   */
Generated on Mon Jun 6 2022 10:29:02 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_tim_ex.h Source File

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stm32g0xx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_TIM_EX_H
00021 #define STM32G0xx_HAL_TIM_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup TIMEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  TIM Hall sensor Configuration Structure definition
00045   */
00046
00047 typedef struct
00048 {
00049   uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
00050                                      This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00051
00052   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00053                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00054
00055   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00056                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00057
00058   uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00059                                      This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00060 } TIM_HallSensor_InitTypeDef;
00061
00062 /**
00063   * @brief  TIM Break/Break2 input configuration
00064   */
00065 typedef struct
00066 {
00067   uint32_t Source;         /*!< Specifies the source of the timer break input.
00068                                 This parameter can be a value of @ref TIMEx_Break_Input_Source */
00069   uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
00070                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
00071   uint32_t Polarity;       /*!< Specifies the break input source polarity.
00072                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
00073 } TIMEx_BreakInputConfigTypeDef;
00074
00075 /**
00076   * @}
00077   */
00078 /* End of exported types -----------------------------------------------------*/
00079
00080 /* Exported constants --------------------------------------------------------*/
00081 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
00082   * @{
00083   */
00084
00085 /** @defgroup TIMEx_Remap TIM Extended Remapping
00086   * @{
00087   */
00088 #define TIM_TIM1_ETR_GPIO           0x00000000U                                 /* !< TIM1_ETR is connected to GPIO */
00089 #if defined(COMP1) && defined(COMP2)
00090 #define TIM_TIM1_ETR_COMP1          TIM1_AF1_ETRSEL_0                           /* !< TIM1_ETR is connected to COMP1 output */
00091 #define TIM_TIM1_ETR_COMP2          TIM1_AF1_ETRSEL_1                           /* !< TIM1_ETR is connected to COMP2 output */
00092 #endif /* COMP1 && COMP2 */
00093 #define TIM_TIM1_ETR_ADC1_AWD1      (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)     /* !< TIM1_ETR is connected to ADC1 AWD1 */
00094 #define TIM_TIM1_ETR_ADC1_AWD2      TIM1_AF1_ETRSEL_2                           /* !< TIM1_ETR is connected to ADC1 AWD2 */
00095 #define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)     /* !< TIM1_ETR is connected to ADC1 AWD3 */
00096 #if defined(COMP3)
00097 #define TIM_TIM1_ETR_COMP3          (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)     /* !< TIM1_ETR is connected to COMP3 output */
00098 #endif /* COMP3 */
00099 #if defined(TIM2)
00100 #define TIM_TIM2_ETR_GPIO           0x00000000U                                 /* !< TIM2_ETR is connected to GPIO      */
00101 #define TIM_TIM2_ETR_COMP1          TIM2_AF1_ETRSEL_0                           /* !< TIM2_ETR is connected to COMP1 output */
00102 #define TIM_TIM2_ETR_COMP2          TIM2_AF1_ETRSEL_1                           /* !< TIM2_ETR is connected to COMP2 output */
00103 #define TIM_TIM2_ETR_LSE            (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0)     /* !< TIM2_ETR is connected to LSE */
00104 #if defined(COMP3)
00105 #define TIM_TIM2_ETR_MCO            TIM2_AF1_ETRSEL_2                           /* !< TIM2_ETR is connected to MCO */
00106 #define TIM_TIM2_ETR_MCO2           (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)     /* !< TIM2_ETR is connected to MCO2 */
00107 #define TIM_TIM2_ETR_COMP3          (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)     /* !< TIM2_ETR is connected to COMP3 output */
00108 #endif /* COMP3 */
00109 #endif /*  TIM2 */
00110 #if defined(TIM3)
00111 #define TIM_TIM3_ETR_GPIO           0x00000000U                                 /* !< TIM3_ETR is connected to GPIO */
00112 #if defined(COMP1) && defined(COMP2)
00113 #define TIM_TIM3_ETR_COMP1          TIM3_AF1_ETRSEL_0                           /* !< TIM3_ETR is connected to COMP1 output */
00114 #define TIM_TIM3_ETR_COMP2          TIM3_AF1_ETRSEL_1                           /* !< TIM3_ETR is connected to COMP2 output */
00115 #endif /* COMP1 && COMP2 */
00116 #if defined(COMP3)
00117 #define TIM_TIM3_ETR_COMP3          (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0)     /* !< TIM3_ETR is connected to COMP3 output */
00118 #endif /* COMP3 */
00119 #endif /* TIM3 */
00120 #if defined(TIM4)
00121 #define TIM_TIM4_ETR_GPIO           0x00000000U                                 /* !< TIM4_ETR is connected to GPIO */
00122 #if defined(COMP1) && defined(COMP2)
00123 #define TIM_TIM4_ETR_COMP1          TIM4_AF1_ETRSEL_0                           /* !< TIM4_ETR is connected to COMP1 output */
00124 #define TIM_TIM4_ETR_COMP2          TIM4_AF1_ETRSEL_1                           /* !< TIM4_ETR is connected to COMP2 output */
00125 #endif /* COMP1 && COMP2 */
00126 #if defined(COMP3)
00127 #define TIM_TIM4_ETR_COMP3          (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0)     /* !< TIM4_ETR is connected to COMP3 output */
00128 #endif /* COMP3 */
00129 #endif /* TIM4 */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup TIMEx_Break_Input TIM Extended Break input
00135   * @{
00136   */
00137 #define TIM_BREAKINPUT_BRK     0x00000001U                                      /*!< Timer break input  */
00138 #define TIM_BREAKINPUT_BRK2    0x00000002U                                      /*!< Timer break2 input */
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
00144   * @{
00145   */
00146 #define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
00147 #if defined(COMP1) && defined(COMP2)
00148 #define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
00149 #define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
00150 #endif /* COMP1 && COMP2 */
00151 #if defined(COMP3)
00152 #define TIM_BREAKINPUTSOURCE_COMP3    0x00000008U                               /* !< The COMP3 output is connected to the break input */
00153 #endif /* COMP3 */
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
00159   * @{
00160   */
00161 #define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /*!< Break input source is disabled */
00162 #define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /*!< Break input source is enabled */
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
00168   * @{
00169   */
00170 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /*!< Break input source is active low */
00171 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /*!< Break input source is active_high */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
00177   * @{
00178   */
00179 #define TIM_TIM1_TI1_GPIO                     0x00000000U                       /* !< TIM1_TI1 is connected to GPIO */
00180 #if defined(COMP1)
00181 #define TIM_TIM1_TI1_COMP1                    0x00000001U                       /* !< TIM1_TI1 is connected to COMP1 OUT */
00182 #endif /* COMP1 */
00183
00184 #define TIM_TIM1_TI2_GPIO                     0x00000000U                       /* !< TIM1_TI2 is connected to GPIO */
00185 #if defined(COMP2)
00186 #define TIM_TIM1_TI2_COMP2                    0x00000100U                       /* !< TIM1_TI2 is connected to COMP2 OUT */
00187 #endif /* COMP2 */
00188
00189 #define TIM_TIM1_TI3_GPIO                     0x00000000U                       /* !< TIM1_TI3 is connected to GPIO */
00190 #if defined(COMP3)
00191 #define TIM_TIM1_TI3_COMP3                    0x00010000U                       /* !< TIM1_TI3 is connected to COMP3 OUT */
00192 #endif /* COMP3 */
00193
00194 #if defined(TIM2)
00195 #define TIM_TIM2_TI1_GPIO                     0x00000000U                       /* !< TIM2_TI1 is connected to GPIO */
00196 #define TIM_TIM2_TI1_COMP1                    0x00000001U                       /* !< TIM2_TI1 is connected to COMP1 OUT */
00197
00198 #define TIM_TIM2_TI2_GPIO                     0x00000000U                       /* !< TIM2_TI2 is connected to GPIO */
00199 #define TIM_TIM2_TI2_COMP2                    0x00000100U                       /* !< TIM2_TI2 is connected to COMP2 OUT */
00200
00201 #define TIM_TIM2_TI3_GPIO                     0x00000000U                       /* !< TIM2_TI3 is connected to GPIO */
00202 #if defined(COMP3)
00203 #define TIM_TIM2_TI3_COMP3                    0x00010000U                       /* !< TIM2_TI3 is connected to COMP3 OUT */
00204 #endif /* COMP3 */
00205 #endif /* TIM2 */
00206
00207 #define TIM_TIM3_TI1_GPIO                     0x00000000U                       /* !< TIM3_TI1 is connected to GPIO */
00208 #if defined(COMP1)
00209 #define TIM_TIM3_TI1_COMP1                    0x00000001U                       /* !< TIM3_TI1 is connected to COMP1 OUT */
00210 #endif /* COMP1 */
00211
00212 #define TIM_TIM3_TI2_GPIO                     0x00000000U                       /* !< TIM3_TI2 is connected to GPIO */
00213 #if defined(COMP2)
00214 #define TIM_TIM3_TI2_COMP2                    0x00000100U                       /* !< TIM3_TI2 is connected to COMP2 OUT */
00215 #endif /* COMP2 */
00216
00217 #define TIM_TIM3_TI3_GPIO                     0x00000000U                       /* !< TIM3_TI3 is connected to GPIO */
00218 #if defined(COMP3)
00219 #define TIM_TIM3_TI3_COMP3                    0x00010000U                       /* !< TIM3_TI3 is connected to COMP3 OUT */
00220 #endif /* COMP3 */
00221
00222 #if defined(TIM4)
00223 #define TIM_TIM4_TI1_GPIO                     0x00000000U                       /* !< TIM4_TI1 is connected to GPIO */
00224 #if defined(COMP1)
00225 #define TIM_TIM4_TI1_COMP1                    0x00000001U                       /* !< TIM4_TI1 is connected to COMP1 OUT */
00226 #endif /* COMP1 */
00227
00228 #define TIM_TIM4_TI2_GPIO                     0x00000000U                       /* !< TIM4_TI2 is connected to GPIO */
00229 #if defined(COMP2)
00230 #define TIM_TIM4_TI2_COMP2                    0x00000100U                       /* !< TIM4_TI2 is connected to COMP2 OUT */
00231 #endif /* COMP2 */
00232
00233 #define TIM_TIM4_TI3_GPIO                     0x00000000U                       /* !< TIM4_TI3 is connected to GPIO */
00234 #if defined(COMP3)
00235 #define TIM_TIM4_TI3_COMP3                    0x00010000U                       /* !< TIM4_TI3 is connected to COMP3 OUT */
00236 #endif /* COMP3 */
00237 #endif /* TIM4 */
00238
00239 #define TIM_TIM14_TI1_GPIO                    0x00000000U                       /* !< TIM14_TI1 is connected to GPIO */
00240 #define TIM_TIM14_TI1_RTC                     0x00000001U                       /* !< TIM14_TI1 is connected to RTC clock */
00241 #define TIM_TIM14_TI1_HSE_32                  0x00000002U                       /* !< TIM14_TI1 is connected to HSE div 32 */
00242 #define TIM_TIM14_TI1_MCO                     0x00000003U                       /* !< TIM14_TI1 is connected to MCO */
00243 #if defined(RCC_MCO2_SUPPORT)
00244 #define TIM_TIM14_TI1_MCO2                    0x00000004U                       /* !< TIM14_TI1 is connected to MCO2 */
00245 #endif
00246
00247 #if defined(TIM15)
00248 #define TIM_TIM15_TI1_GPIO                    0x00000000U                       /* !< TIM15_TI1 is connected to GPIO */
00249 #define TIM_TIM15_TI1_TIM2_CH1                0x00000001U                       /* !< TIM15_TI1 is connected to TIM2 CH1 */
00250 #define TIM_TIM15_TI1_TIM3_CH1                0x00000002U                       /* !< TIM15_TI1 is connected to TIM3 CH1 */
00251
00252 #define TIM_TIM15_TI2_GPIO                    0x00000000U                       /* !< TIM15_TI2 is connected to GPIO */
00253 #define TIM_TIM15_TI2_TIM2_CH2                0x00000100U                       /* !< TIM15_TI2 is connected to TIM2 CH2 */
00254 #define TIM_TIM15_TI2_TIM3_CH2                0x00000200U                       /* !< TIM15_TI2 is connected to TIM3 CH2 */
00255 #endif /* TIM15 */
00256
00257 #define TIM_TIM16_TI1_GPIO                    0x00000000U                       /* !< TIM16_TI1 is connected to GPIO */
00258 #define TIM_TIM16_TI1_LSI                     0x00000001U                       /* !< TIM16_TI1 is connected to LSI */
00259 #define TIM_TIM16_TI1_LSE                     0x00000002U                       /* !< TIM16_TI1 is connected to LSE */
00260 #define TIM_TIM16_TI1_RTC_WAKEUP              0x00000003U                       /* !< TIM16_TI1 is connected to TRC wakeup interrupt */
00261 #if defined(RCC_MCO2_SUPPORT)
00262 #define TIM_TIM16_TI1_MCO2                    0x00000004U                       /* !< TIM16_TI1 is connected to MCO2 */
00263 #endif /* RCC_MCO2_SUPPORT */
00264
00265 #define TIM_TIM17_TI1_GPIO                    0x00000000U                       /* !< TIM17_TI1 is connected to GPIO */
00266 #if defined(RCC_HSI48_SUPPORT)
00267 #define TIM_TIM17_TI1_HSI48                   0x00000001U                       /* !< TIM17_TI1 is connected to HSI48/256 */
00268 #endif /* RCC_HSI48_SUPPORT */
00269 #define TIM_TIM17_TI1_HSE_32                  0x00000002U                       /* !< TIM17_TI1 is connected to HSE div 32 */
00270 #define TIM_TIM17_TI1_MCO                     0x00000003U                       /* !< TIM17_TI1 is connected to MCO */
00271 #if defined(RCC_MCO2_SUPPORT)
00272 #define TIM_TIM17_TI1_MCO2                    0x00000004U                       /* !< TIM17_TI1 is connected to MCO2 */
00273 #endif /* RCC_MCO2_SUPPORT */
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281 /* End of exported constants -------------------------------------------------*/
00282
00283 /* Exported macro ------------------------------------------------------------*/
00284 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
00285   * @{
00286   */
00287
00288 /**
00289   * @}
00290   */
00291 /* End of exported macro -----------------------------------------------------*/
00292
00293 /* Private macro -------------------------------------------------------------*/
00294 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
00295   * @{
00296   */
00297 #define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
00298
00299 #define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
00300                                             ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
00301
00302 #if defined(COMP1) && defined(COMP2) && defined(COMP3)
00303 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00304                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00305                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
00306                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3))
00307 #elif defined(COMP1) && defined(COMP2)
00308 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00309                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00310                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
00311 #else
00312 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)
00313 #endif /* COMP1 && COMP2 && COMP3 */
00314
00315 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
00316                                                    ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
00317
00318 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
00319                                                          ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
00320
00321 #define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
00322
00323 /**
00324   * @}
00325   */
00326 /* End of private macro ------------------------------------------------------*/
00327
00328 /* Exported functions --------------------------------------------------------*/
00329 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
00330   * @{
00331   */
00332
00333 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00334   *  @brief    Timer Hall Sensor functions
00335   * @{
00336   */
00337 /*  Timer Hall Sensor functions  **********************************************/
00338 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
00339 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
00340
00341 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
00342 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
00343
00344 /* Blocking mode: Polling */
00345 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
00346 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
00347 /* Non-Blocking mode: Interrupt */
00348 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
00349 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
00350 /* Non-Blocking mode: DMA */
00351 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
00352 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
00353 /**
00354   * @}
00355   */
00356
00357 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00358   *  @brief   Timer Complementary Output Compare functions
00359   * @{
00360   */
00361 /*  Timer Complementary Output Compare functions  *****************************/
00362 /* Blocking mode: Polling */
00363 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00364 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00365
00366 /* Non-Blocking mode: Interrupt */
00367 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00368 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00369
00370 /* Non-Blocking mode: DMA */
00371 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
00372                                           uint16_t Length);
00373 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00374 /**
00375   * @}
00376   */
00377
00378 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00379   *  @brief    Timer Complementary PWM functions
00380   * @{
00381   */
00382 /*  Timer Complementary PWM functions  ****************************************/
00383 /* Blocking mode: Polling */
00384 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00385 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00386
00387 /* Non-Blocking mode: Interrupt */
00388 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00389 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00390 /* Non-Blocking mode: DMA */
00391 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
00392                                            uint16_t Length);
00393 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00394 /**
00395   * @}
00396   */
00397
00398 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
00399   *  @brief    Timer Complementary One Pulse functions
00400   * @{
00401   */
00402 /*  Timer Complementary One Pulse functions  **********************************/
00403 /* Blocking mode: Polling */
00404 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00405 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00406
00407 /* Non-Blocking mode: Interrupt */
00408 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00409 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00410 /**
00411   * @}
00412   */
00413
00414 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
00415   *  @brief    Peripheral Control functions
00416   * @{
00417   */
00418 /* Extended Control functions  ************************************************/
00419 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00420                                               uint32_t  CommutationSource);
00421 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00422                                                  uint32_t  CommutationSource);
00423 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00424                                                   uint32_t  CommutationSource);
00425 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
00426                                                         const TIM_MasterConfigTypeDef *sMasterConfig);
00427 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
00428                                                 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
00429 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
00430                                              const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
00431 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
00432 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
00433 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
00434
00435 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
00436 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
00437 /**
00438   * @}
00439   */
00440
00441 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
00442   * @brief    Extended Callbacks functions
00443   * @{
00444   */
00445 /* Extended Callback **********************************************************/
00446 void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
00447 void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
00448 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
00449 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
00450 /**
00451   * @}
00452   */
00453
00454 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
00455   * @brief    Extended Peripheral State functions
00456   * @{
00457   */
00458 /* Extended Peripheral State functions  ***************************************/
00459 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
00460 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN);
00461 /**
00462   * @}
00463   */
00464
00465 /**
00466   * @}
00467   */
00468 /* End of exported functions -------------------------------------------------*/
00469
00470 /* Private functions----------------------------------------------------------*/
00471 /** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
00472   * @{
00473   */
00474 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
00475 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
00476 /**
00477   * @}
00478   */
00479 /* End of private functions --------------------------------------------------*/
00480
00481 /**
00482   * @}
00483   */
00484
00485 /**
00486   * @}
00487   */
00488
00489 #ifdef __cplusplus
00490 }
00491 #endif
00492
00493
00494 #endif /* STM32G0xx_HAL_TIM_EX_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_uart.c Source File

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stm32g0xx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @brief   UART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * Copyright (c) 2018 STMicroelectronics.
00017   * All rights reserved.
00018   *
00019   * This software is licensed under terms that can be found in the LICENSE file
00020   * in the root directory of this software component.
00021   * If no LICENSE file comes with this software, it is provided AS-IS.
00022   *
00023   ******************************************************************************
00024   @verbatim
00025  ===============================================================================
00026                         ##### How to use this driver #####
00027  ===============================================================================
00028   [..]
00029     The UART HAL driver can be used as follows:
00030
00031     (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
00032     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00033         (++) Enable the USARTx interface clock.
00034         (++) UART pins configuration:
00035             (+++) Enable the clock for the UART GPIOs.
00036             (+++) Configure these UART pins as alternate function pull-up.
00037         (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00038              and HAL_UART_Receive_IT() APIs):
00039             (+++) Configure the USARTx interrupt priority.
00040             (+++) Enable the NVIC USART IRQ handle.
00041         (++) UART interrupts handling:
00042               -@@-  The specific UART interrupts (Transmission complete interrupt,
00043                 RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
00044                 are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
00045                 inside the transmit and receive processes.
00046         (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00047              and HAL_UART_Receive_DMA() APIs):
00048             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00049             (+++) Enable the DMAx interface clock.
00050             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00051             (+++) Configure the DMA Tx/Rx channel.
00052             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00053             (+++) Configure the priority and enable the NVIC for the transfer complete
00054                   interrupt on the DMA Tx/Rx channel.
00055
00056     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
00057         flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
00058
00059     (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
00060         in the huart handle AdvancedInit structure.
00061
00062     (#) For the UART asynchronous mode, initialize the UART registers by calling
00063         the HAL_UART_Init() API.
00064
00065     (#) For the UART Half duplex mode, initialize the UART registers by calling
00066         the HAL_HalfDuplex_Init() API.
00067
00068     (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
00069         by calling the HAL_LIN_Init() API.
00070
00071     (#) For the UART Multiprocessor mode, initialize the UART registers
00072         by calling the HAL_MultiProcessor_Init() API.
00073
00074     (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
00075         by calling the HAL_RS485Ex_Init() API.
00076
00077     [..]
00078     (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
00079         also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
00080         calling the customized HAL_UART_MspInit() API.
00081
00082     ##### Callback registration #####
00083     ==================================
00084
00085     [..]
00086     The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
00087     allows the user to configure dynamically the driver callbacks.
00088
00089     [..]
00090     Use Function HAL_UART_RegisterCallback() to register a user callback.
00091     Function HAL_UART_RegisterCallback() allows to register following callbacks:
00092     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00093     (+) TxCpltCallback            : Tx Complete Callback.
00094     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00095     (+) RxCpltCallback            : Rx Complete Callback.
00096     (+) ErrorCallback             : Error Callback.
00097     (+) AbortCpltCallback         : Abort Complete Callback.
00098     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00099     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00100     (+) WakeupCallback            : Wakeup Callback.
00101     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00102     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00103     (+) MspInitCallback           : UART MspInit.
00104     (+) MspDeInitCallback         : UART MspDeInit.
00105     This function takes as parameters the HAL peripheral handle, the Callback ID
00106     and a pointer to the user callback function.
00107
00108     [..]
00109     Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
00110     weak (surcharged) function.
00111     HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00112     and the Callback ID.
00113     This function allows to reset following callbacks:
00114     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00115     (+) TxCpltCallback            : Tx Complete Callback.
00116     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00117     (+) RxCpltCallback            : Rx Complete Callback.
00118     (+) ErrorCallback             : Error Callback.
00119     (+) AbortCpltCallback         : Abort Complete Callback.
00120     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00121     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00122     (+) WakeupCallback            : Wakeup Callback.
00123     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00124     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00125     (+) MspInitCallback           : UART MspInit.
00126     (+) MspDeInitCallback         : UART MspDeInit.
00127
00128     [..]
00129     For specific callback RxEventCallback, use dedicated registration/reset functions:
00130     respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
00131
00132     [..]
00133     By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
00134     all callbacks are set to the corresponding weak (surcharged) functions:
00135     examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
00136     Exception done for MspInit and MspDeInit functions that are respectively
00137     reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
00138     and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
00139     If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
00140     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00141
00142     [..]
00143     Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
00144     Exception done MspInit/MspDeInit that can be registered/unregistered
00145     in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
00146     MspInit/DeInit callbacks can be used during the Init/DeInit.
00147     In that case first register the MspInit/MspDeInit user callbacks
00148     using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
00149     or HAL_UART_Init() function.
00150
00151     [..]
00152     When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
00153     not defined, the callback registration feature is not available
00154     and weak (surcharged) callbacks are used.
00155
00156
00157   @endverbatim
00158   ******************************************************************************
00159   */
00160
00161 /* Includes ------------------------------------------------------------------*/
00162 #include "stm32g0xx_hal.h"
00163
00164 /** @addtogroup STM32G0xx_HAL_Driver
00165   * @{
00166   */
00167
00168 /** @defgroup UART UART
00169   * @brief HAL UART module driver
00170   * @{
00171   */
00172
00173 #ifdef HAL_UART_MODULE_ENABLED
00174
00175 /* Private typedef -----------------------------------------------------------*/
00176 /* Private define ------------------------------------------------------------*/
00177 /** @defgroup UART_Private_Constants UART Private Constants
00178   * @{
00179   */
00180 #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
00181                                       USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
00182
00183 #define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
00184                                       USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
00185
00186 #define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
00187 #define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
00188
00189 #define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
00190 #define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
00191 /**
00192   * @}
00193   */
00194
00195 /* Private macros ------------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /** @addtogroup UART_Private_Functions
00198   * @{
00199   */
00200 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
00201 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
00202 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00203 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00204 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00205 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00206 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00207 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00208 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00209 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00210 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00211 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00212 static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
00213 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
00214 static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
00215 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
00216 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00217 static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
00218 static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
00219 static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
00220 static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
00221 /**
00222   * @}
00223   */
00224
00225 /* Private variables ---------------------------------------------------------*/
00226 /** @addtogroup UART_Private_variables
00227   * @{
00228   */
00229 const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
00230 /**
00231   * @}
00232   */
00233
00234 /* Exported Constants --------------------------------------------------------*/
00235 /* Exported functions --------------------------------------------------------*/
00236
00237 /** @defgroup UART_Exported_Functions UART Exported Functions
00238   * @{
00239   */
00240
00241 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00242   *  @brief    Initialization and Configuration functions
00243   *
00244 @verbatim
00245 ===============================================================================
00246             ##### Initialization and Configuration functions #####
00247  ===============================================================================
00248     [..]
00249     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00250     in asynchronous mode.
00251       (+) For the asynchronous mode the parameters below can be configured:
00252         (++) Baud Rate
00253         (++) Word Length
00254         (++) Stop Bit
00255         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00256              in the data register is transmitted but is changed by the parity bit.
00257         (++) Hardware flow control
00258         (++) Receiver/transmitter modes
00259         (++) Over Sampling Method
00260         (++) One-Bit Sampling Method
00261       (+) For the asynchronous mode, the following advanced features can be configured as well:
00262         (++) TX and/or RX pin level inversion
00263         (++) data logical level inversion
00264         (++) RX and TX pins swap
00265         (++) RX overrun detection disabling
00266         (++) DMA disabling on RX error
00267         (++) MSB first on communication line
00268         (++) auto Baud rate detection
00269     [..]
00270     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
00271     follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
00272     and UART multiprocessor mode configuration procedures (details for the procedures
00273     are available in reference manual).
00274
00275 @endverbatim
00276
00277   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00278   8-bit or 9-bit), the possible UART formats are listed in the
00279   following table.
00280
00281   Table 1. UART frame format.
00282     +-----------------------------------------------------------------------+
00283     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00284     |---------|---------|-----------|---------------------------------------|
00285     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00286     |---------|---------|-----------|---------------------------------------|
00287     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00288     |---------|---------|-----------|---------------------------------------|
00289     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00290     |---------|---------|-----------|---------------------------------------|
00291     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00292     |---------|---------|-----------|---------------------------------------|
00293     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00294     |---------|---------|-----------|---------------------------------------|
00295     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00296     +-----------------------------------------------------------------------+
00297
00298   * @{
00299   */
00300
00301 /**
00302   * @brief Initialize the UART mode according to the specified
00303   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00304   * @param huart UART handle.
00305   * @retval HAL status
00306   */
00307 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00308 {
00309   /* Check the UART handle allocation */
00310   if (huart == NULL)
00311   {
00312     return HAL_ERROR;
00313   }
00314
00315   if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00316   {
00317     /* Check the parameters */
00318     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00319   }
00320   else
00321   {
00322     /* Check the parameters */
00323     assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00324   }
00325
00326   if (huart->gState == HAL_UART_STATE_RESET)
00327   {
00328     /* Allocate lock resource and initialize it */
00329     huart->Lock = HAL_UNLOCKED;
00330
00331 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00332     UART_InitCallbacksToDefault(huart);
00333
00334     if (huart->MspInitCallback == NULL)
00335     {
00336       huart->MspInitCallback = HAL_UART_MspInit;
00337     }
00338
00339     /* Init the low level hardware */
00340     huart->MspInitCallback(huart);
00341 #else
00342     /* Init the low level hardware : GPIO, CLOCK */
00343     HAL_UART_MspInit(huart);
00344 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00345   }
00346
00347   huart->gState = HAL_UART_STATE_BUSY;
00348
00349   __HAL_UART_DISABLE(huart);
00350
00351   /* Set the UART Communication parameters */
00352   if (UART_SetConfig(huart) == HAL_ERROR)
00353   {
00354     return HAL_ERROR;
00355   }
00356
00357   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00358   {
00359     UART_AdvFeatureConfig(huart);
00360   }
00361
00362   /* In asynchronous mode, the following bits must be kept cleared:
00363   - LINEN and CLKEN bits in the USART_CR2 register,
00364   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00365   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00366   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00367
00368   __HAL_UART_ENABLE(huart);
00369
00370   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00371   return (UART_CheckIdleState(huart));
00372 }
00373
00374 /**
00375   * @brief Initialize the half-duplex mode according to the specified
00376   *        parameters in the UART_InitTypeDef and creates the associated handle.
00377   * @param huart UART handle.
00378   * @retval HAL status
00379   */
00380 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00381 {
00382   /* Check the UART handle allocation */
00383   if (huart == NULL)
00384   {
00385     return HAL_ERROR;
00386   }
00387
00388   /* Check UART instance */
00389   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
00390
00391   if (huart->gState == HAL_UART_STATE_RESET)
00392   {
00393     /* Allocate lock resource and initialize it */
00394     huart->Lock = HAL_UNLOCKED;
00395
00396 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00397     UART_InitCallbacksToDefault(huart);
00398
00399     if (huart->MspInitCallback == NULL)
00400     {
00401       huart->MspInitCallback = HAL_UART_MspInit;
00402     }
00403
00404     /* Init the low level hardware */
00405     huart->MspInitCallback(huart);
00406 #else
00407     /* Init the low level hardware : GPIO, CLOCK */
00408     HAL_UART_MspInit(huart);
00409 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00410   }
00411
00412   huart->gState = HAL_UART_STATE_BUSY;
00413
00414   __HAL_UART_DISABLE(huart);
00415
00416   /* Set the UART Communication parameters */
00417   if (UART_SetConfig(huart) == HAL_ERROR)
00418   {
00419     return HAL_ERROR;
00420   }
00421
00422   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00423   {
00424     UART_AdvFeatureConfig(huart);
00425   }
00426
00427   /* In half-duplex mode, the following bits must be kept cleared:
00428   - LINEN and CLKEN bits in the USART_CR2 register,
00429   - SCEN and IREN bits in the USART_CR3 register.*/
00430   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00431   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
00432
00433   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00434   SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
00435
00436   __HAL_UART_ENABLE(huart);
00437
00438   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00439   return (UART_CheckIdleState(huart));
00440 }
00441
00442
00443 /**
00444   * @brief Initialize the LIN mode according to the specified
00445   *        parameters in the UART_InitTypeDef and creates the associated handle.
00446   * @param huart             UART handle.
00447   * @param BreakDetectLength Specifies the LIN break detection length.
00448   *        This parameter can be one of the following values:
00449   *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
00450   *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
00451   * @retval HAL status
00452   */
00453 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00454 {
00455   /* Check the UART handle allocation */
00456   if (huart == NULL)
00457   {
00458     return HAL_ERROR;
00459   }
00460
00461   /* Check the LIN UART instance */
00462   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
00463   /* Check the Break detection length parameter */
00464   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00465
00466   /* LIN mode limited to 16-bit oversampling only */
00467   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
00468   {
00469     return HAL_ERROR;
00470   }
00471   /* LIN mode limited to 8-bit data length */
00472   if (huart->Init.WordLength != UART_WORDLENGTH_8B)
00473   {
00474     return HAL_ERROR;
00475   }
00476
00477   if (huart->gState == HAL_UART_STATE_RESET)
00478   {
00479     /* Allocate lock resource and initialize it */
00480     huart->Lock = HAL_UNLOCKED;
00481
00482 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00483     UART_InitCallbacksToDefault(huart);
00484
00485     if (huart->MspInitCallback == NULL)
00486     {
00487       huart->MspInitCallback = HAL_UART_MspInit;
00488     }
00489
00490     /* Init the low level hardware */
00491     huart->MspInitCallback(huart);
00492 #else
00493     /* Init the low level hardware : GPIO, CLOCK */
00494     HAL_UART_MspInit(huart);
00495 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00496   }
00497
00498   huart->gState = HAL_UART_STATE_BUSY;
00499
00500   __HAL_UART_DISABLE(huart);
00501
00502   /* Set the UART Communication parameters */
00503   if (UART_SetConfig(huart) == HAL_ERROR)
00504   {
00505     return HAL_ERROR;
00506   }
00507
00508   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00509   {
00510     UART_AdvFeatureConfig(huart);
00511   }
00512
00513   /* In LIN mode, the following bits must be kept cleared:
00514   - LINEN and CLKEN bits in the USART_CR2 register,
00515   - SCEN and IREN bits in the USART_CR3 register.*/
00516   CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
00517   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
00518
00519   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00520   SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
00521
00522   /* Set the USART LIN Break detection length. */
00523   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00524
00525   __HAL_UART_ENABLE(huart);
00526
00527   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00528   return (UART_CheckIdleState(huart));
00529 }
00530
00531
00532 /**
00533   * @brief Initialize the multiprocessor mode according to the specified
00534   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00535   * @param huart        UART handle.
00536   * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
00537   * @param WakeUpMethod Specifies the UART wakeup method.
00538   *        This parameter can be one of the following values:
00539   *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
00540   *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
00541   * @note  If the user resorts to idle line detection wake up, the Address parameter
00542   *        is useless and ignored by the initialization function.
00543   * @note  If the user resorts to address mark wake up, the address length detection
00544   *        is configured by default to 4 bits only. For the UART to be able to
00545   *        manage 6-, 7- or 8-bit long addresses detection, the API
00546   *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
00547   *        HAL_MultiProcessor_Init().
00548   * @retval HAL status
00549   */
00550 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00551 {
00552   /* Check the UART handle allocation */
00553   if (huart == NULL)
00554   {
00555     return HAL_ERROR;
00556   }
00557
00558   /* Check the wake up method parameter */
00559   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00560
00561   if (huart->gState == HAL_UART_STATE_RESET)
00562   {
00563     /* Allocate lock resource and initialize it */
00564     huart->Lock = HAL_UNLOCKED;
00565
00566 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00567     UART_InitCallbacksToDefault(huart);
00568
00569     if (huart->MspInitCallback == NULL)
00570     {
00571       huart->MspInitCallback = HAL_UART_MspInit;
00572     }
00573
00574     /* Init the low level hardware */
00575     huart->MspInitCallback(huart);
00576 #else
00577     /* Init the low level hardware : GPIO, CLOCK */
00578     HAL_UART_MspInit(huart);
00579 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00580   }
00581
00582   huart->gState = HAL_UART_STATE_BUSY;
00583
00584   __HAL_UART_DISABLE(huart);
00585
00586   /* Set the UART Communication parameters */
00587   if (UART_SetConfig(huart) == HAL_ERROR)
00588   {
00589     return HAL_ERROR;
00590   }
00591
00592   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00593   {
00594     UART_AdvFeatureConfig(huart);
00595   }
00596
00597   /* In multiprocessor mode, the following bits must be kept cleared:
00598   - LINEN and CLKEN bits in the USART_CR2 register,
00599   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
00600   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00601   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00602
00603   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
00604   {
00605     /* If address mark wake up method is chosen, set the USART address node */
00606     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
00607   }
00608
00609   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00610   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00611
00612   __HAL_UART_ENABLE(huart);
00613
00614   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00615   return (UART_CheckIdleState(huart));
00616 }
00617
00618
00619 /**
00620   * @brief DeInitialize the UART peripheral.
00621   * @param huart UART handle.
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00625 {
00626   /* Check the UART handle allocation */
00627   if (huart == NULL)
00628   {
00629     return HAL_ERROR;
00630   }
00631
00632   /* Check the parameters */
00633   assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00634
00635   huart->gState = HAL_UART_STATE_BUSY;
00636
00637   __HAL_UART_DISABLE(huart);
00638
00639   huart->Instance->CR1 = 0x0U;
00640   huart->Instance->CR2 = 0x0U;
00641   huart->Instance->CR3 = 0x0U;
00642
00643 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00644   if (huart->MspDeInitCallback == NULL)
00645   {
00646     huart->MspDeInitCallback = HAL_UART_MspDeInit;
00647   }
00648   /* DeInit the low level hardware */
00649   huart->MspDeInitCallback(huart);
00650 #else
00651   /* DeInit the low level hardware */
00652   HAL_UART_MspDeInit(huart);
00653 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00654
00655   huart->ErrorCode = HAL_UART_ERROR_NONE;
00656   huart->gState = HAL_UART_STATE_RESET;
00657   huart->RxState = HAL_UART_STATE_RESET;
00658   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
00659   huart->RxEventType = HAL_UART_RXEVENT_TC;
00660
00661   __HAL_UNLOCK(huart);
00662
00663   return HAL_OK;
00664 }
00665
00666 /**
00667   * @brief Initialize the UART MSP.
00668   * @param huart UART handle.
00669   * @retval None
00670   */
00671 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00672 {
00673   /* Prevent unused argument(s) compilation warning */
00674   UNUSED(huart);
00675
00676   /* NOTE : This function should not be modified, when the callback is needed,
00677             the HAL_UART_MspInit can be implemented in the user file
00678    */
00679 }
00680
00681 /**
00682   * @brief DeInitialize the UART MSP.
00683   * @param huart UART handle.
00684   * @retval None
00685   */
00686 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00687 {
00688   /* Prevent unused argument(s) compilation warning */
00689   UNUSED(huart);
00690
00691   /* NOTE : This function should not be modified, when the callback is needed,
00692             the HAL_UART_MspDeInit can be implemented in the user file
00693    */
00694 }
00695
00696 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00697 /**
00698   * @brief  Register a User UART Callback
00699   *         To be used instead of the weak predefined callback
00700   * @param  huart uart handle
00701   * @param  CallbackID ID of the callback to be registered
00702   *         This parameter can be one of the following values:
00703   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00704   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00705   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00706   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00707   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
00708   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00709   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00710   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00711   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
00712   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00713   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00714   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
00715   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
00716   * @param  pCallback pointer to the Callback function
00717   * @retval HAL status
00718   */
00719 HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
00720                                             pUART_CallbackTypeDef pCallback)
00721 {
00722   HAL_StatusTypeDef status = HAL_OK;
00723
00724   if (pCallback == NULL)
00725   {
00726     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00727
00728     return HAL_ERROR;
00729   }
00730
00731   __HAL_LOCK(huart);
00732
00733   if (huart->gState == HAL_UART_STATE_READY)
00734   {
00735     switch (CallbackID)
00736     {
00737       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
00738         huart->TxHalfCpltCallback = pCallback;
00739         break;
00740
00741       case HAL_UART_TX_COMPLETE_CB_ID :
00742         huart->TxCpltCallback = pCallback;
00743         break;
00744
00745       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
00746         huart->RxHalfCpltCallback = pCallback;
00747         break;
00748
00749       case HAL_UART_RX_COMPLETE_CB_ID :
00750         huart->RxCpltCallback = pCallback;
00751         break;
00752
00753       case HAL_UART_ERROR_CB_ID :
00754         huart->ErrorCallback = pCallback;
00755         break;
00756
00757       case HAL_UART_ABORT_COMPLETE_CB_ID :
00758         huart->AbortCpltCallback = pCallback;
00759         break;
00760
00761       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
00762         huart->AbortTransmitCpltCallback = pCallback;
00763         break;
00764
00765       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
00766         huart->AbortReceiveCpltCallback = pCallback;
00767         break;
00768
00769       case HAL_UART_WAKEUP_CB_ID :
00770         huart->WakeupCallback = pCallback;
00771         break;
00772
00773       case HAL_UART_RX_FIFO_FULL_CB_ID :
00774         huart->RxFifoFullCallback = pCallback;
00775         break;
00776
00777       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
00778         huart->TxFifoEmptyCallback = pCallback;
00779         break;
00780
00781       case HAL_UART_MSPINIT_CB_ID :
00782         huart->MspInitCallback = pCallback;
00783         break;
00784
00785       case HAL_UART_MSPDEINIT_CB_ID :
00786         huart->MspDeInitCallback = pCallback;
00787         break;
00788
00789       default :
00790         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00791
00792         status =  HAL_ERROR;
00793         break;
00794     }
00795   }
00796   else if (huart->gState == HAL_UART_STATE_RESET)
00797   {
00798     switch (CallbackID)
00799     {
00800       case HAL_UART_MSPINIT_CB_ID :
00801         huart->MspInitCallback = pCallback;
00802         break;
00803
00804       case HAL_UART_MSPDEINIT_CB_ID :
00805         huart->MspDeInitCallback = pCallback;
00806         break;
00807
00808       default :
00809         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00810
00811         status =  HAL_ERROR;
00812         break;
00813     }
00814   }
00815   else
00816   {
00817     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00818
00819     status =  HAL_ERROR;
00820   }
00821
00822   __HAL_UNLOCK(huart);
00823
00824   return status;
00825 }
00826
00827 /**
00828   * @brief  Unregister an UART Callback
00829   *         UART callaback is redirected to the weak predefined callback
00830   * @param  huart uart handle
00831   * @param  CallbackID ID of the callback to be unregistered
00832   *         This parameter can be one of the following values:
00833   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00834   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00835   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00836   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00837   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
00838   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00839   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00840   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00841   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
00842   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00843   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00844   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
00845   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
00846   * @retval HAL status
00847   */
00848 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
00849 {
00850   HAL_StatusTypeDef status = HAL_OK;
00851
00852   __HAL_LOCK(huart);
00853
00854   if (HAL_UART_STATE_READY == huart->gState)
00855   {
00856     switch (CallbackID)
00857     {
00858       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
00859         huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
00860         break;
00861
00862       case HAL_UART_TX_COMPLETE_CB_ID :
00863         huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
00864         break;
00865
00866       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
00867         huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
00868         break;
00869
00870       case HAL_UART_RX_COMPLETE_CB_ID :
00871         huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
00872         break;
00873
00874       case HAL_UART_ERROR_CB_ID :
00875         huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback          */
00876         break;
00877
00878       case HAL_UART_ABORT_COMPLETE_CB_ID :
00879         huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
00880         break;
00881
00882       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
00883         huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
00884                                                                                   AbortTransmitCpltCallback          */
00885         break;
00886
00887       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
00888         huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak
00889                                                                                   AbortReceiveCpltCallback           */
00890         break;
00891
00892       case HAL_UART_WAKEUP_CB_ID :
00893         huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback         */
00894         break;
00895
00896       case HAL_UART_RX_FIFO_FULL_CB_ID :
00897         huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback     */
00898         break;
00899
00900       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
00901         huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback    */
00902         break;
00903
00904       case HAL_UART_MSPINIT_CB_ID :
00905         huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback        */
00906         break;
00907
00908       case HAL_UART_MSPDEINIT_CB_ID :
00909         huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
00910         break;
00911
00912       default :
00913         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00914
00915         status =  HAL_ERROR;
00916         break;
00917     }
00918   }
00919   else if (HAL_UART_STATE_RESET == huart->gState)
00920   {
00921     switch (CallbackID)
00922     {
00923       case HAL_UART_MSPINIT_CB_ID :
00924         huart->MspInitCallback = HAL_UART_MspInit;
00925         break;
00926
00927       case HAL_UART_MSPDEINIT_CB_ID :
00928         huart->MspDeInitCallback = HAL_UART_MspDeInit;
00929         break;
00930
00931       default :
00932         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00933
00934         status =  HAL_ERROR;
00935         break;
00936     }
00937   }
00938   else
00939   {
00940     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00941
00942     status =  HAL_ERROR;
00943   }
00944
00945   __HAL_UNLOCK(huart);
00946
00947   return status;
00948 }
00949
00950 /**
00951   * @brief  Register a User UART Rx Event Callback
00952   *         To be used instead of the weak predefined callback
00953   * @param  huart     Uart handle
00954   * @param  pCallback Pointer to the Rx Event Callback function
00955   * @retval HAL status
00956   */
00957 HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
00958 {
00959   HAL_StatusTypeDef status = HAL_OK;
00960
00961   if (pCallback == NULL)
00962   {
00963     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00964
00965     return HAL_ERROR;
00966   }
00967
00968   /* Process locked */
00969   __HAL_LOCK(huart);
00970
00971   if (huart->gState == HAL_UART_STATE_READY)
00972   {
00973     huart->RxEventCallback = pCallback;
00974   }
00975   else
00976   {
00977     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00978
00979     status =  HAL_ERROR;
00980   }
00981
00982   /* Release Lock */
00983   __HAL_UNLOCK(huart);
00984
00985   return status;
00986 }
00987
00988 /**
00989   * @brief  UnRegister the UART Rx Event Callback
00990   *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
00991   * @param  huart     Uart handle
00992   * @retval HAL status
00993   */
00994 HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
00995 {
00996   HAL_StatusTypeDef status = HAL_OK;
00997
00998   /* Process locked */
00999   __HAL_LOCK(huart);
01000
01001   if (huart->gState == HAL_UART_STATE_READY)
01002   {
01003     huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
01004   }
01005   else
01006   {
01007     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
01008
01009     status =  HAL_ERROR;
01010   }
01011
01012   /* Release Lock */
01013   __HAL_UNLOCK(huart);
01014   return status;
01015 }
01016
01017 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01018
01019 /**
01020   * @}
01021   */
01022
01023 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
01024   * @brief UART Transmit/Receive functions
01025   *
01026 @verbatim
01027  ===============================================================================
01028                       ##### IO operation functions #####
01029  ===============================================================================
01030     This subsection provides a set of functions allowing to manage the UART asynchronous
01031     and Half duplex data transfers.
01032
01033     (#) There are two mode of transfer:
01034        (+) Blocking mode: The communication is performed in polling mode.
01035            The HAL status of all data processing is returned by the same function
01036            after finishing transfer.
01037        (+) Non-Blocking mode: The communication is performed using Interrupts
01038            or DMA, These API's return the HAL status.
01039            The end of the data processing will be indicated through the
01040            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
01041            using DMA mode.
01042            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
01043            will be executed respectively at the end of the transmit or Receive process
01044            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
01045
01046     (#) Blocking mode API's are :
01047         (+) HAL_UART_Transmit()
01048         (+) HAL_UART_Receive()
01049
01050     (#) Non-Blocking mode API's with Interrupt are :
01051         (+) HAL_UART_Transmit_IT()
01052         (+) HAL_UART_Receive_IT()
01053         (+) HAL_UART_IRQHandler()
01054
01055     (#) Non-Blocking mode API's with DMA are :
01056         (+) HAL_UART_Transmit_DMA()
01057         (+) HAL_UART_Receive_DMA()
01058         (+) HAL_UART_DMAPause()
01059         (+) HAL_UART_DMAResume()
01060         (+) HAL_UART_DMAStop()
01061
01062     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
01063         (+) HAL_UART_TxHalfCpltCallback()
01064         (+) HAL_UART_TxCpltCallback()
01065         (+) HAL_UART_RxHalfCpltCallback()
01066         (+) HAL_UART_RxCpltCallback()
01067         (+) HAL_UART_ErrorCallback()
01068
01069     (#) Non-Blocking mode transfers could be aborted using Abort API's :
01070         (+) HAL_UART_Abort()
01071         (+) HAL_UART_AbortTransmit()
01072         (+) HAL_UART_AbortReceive()
01073         (+) HAL_UART_Abort_IT()
01074         (+) HAL_UART_AbortTransmit_IT()
01075         (+) HAL_UART_AbortReceive_IT()
01076
01077     (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
01078         (+) HAL_UART_AbortCpltCallback()
01079         (+) HAL_UART_AbortTransmitCpltCallback()
01080         (+) HAL_UART_AbortReceiveCpltCallback()
01081
01082     (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
01083         reception services:
01084         (+) HAL_UARTEx_RxEventCallback()
01085
01086     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
01087         Errors are handled as follows :
01088        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
01089            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
01090            in Interrupt mode reception .
01091            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
01092            to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
01093            Transfer is kept ongoing on UART side.
01094            If user wants to abort it, Abort services should be called by user.
01095        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
01096            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
01097            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
01098            user callback is executed.
01099
01100     -@- In the Half duplex communication, it is forbidden to run the transmit
01101         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
01102
01103 @endverbatim
01104   * @{
01105   */
01106
01107 /**
01108   * @brief Send an amount of data in blocking mode.
01109   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01110   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01111   *         of u16 provided through pData.
01112   * @note When FIFO mode is enabled, writing a data in the TDR register adds one
01113   *       data to the TXFIFO. Write operations to the TDR register are performed
01114   *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
01115   *       TXE are mapped on the same bit-field.
01116   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01117   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
01118   *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
01119   *         use of specific alignment compilation directives or pragmas might be required
01120   *         to ensure proper alignment for pData.
01121   * @param huart   UART handle.
01122   * @param pData   Pointer to data buffer (u8 or u16 data elements).
01123   * @param Size    Amount of data elements (u8 or u16) to be sent.
01124   * @param Timeout Timeout duration.
01125   * @retval HAL status
01126   */
01127 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
01128 {
01129   const uint8_t  *pdata8bits;
01130   const uint16_t *pdata16bits;
01131   uint32_t tickstart;
01132
01133   /* Check that a Tx process is not already ongoing */
01134   if (huart->gState == HAL_UART_STATE_READY)
01135   {
01136     if ((pData == NULL) || (Size == 0U))
01137     {
01138       return  HAL_ERROR;
01139     }
01140
01141     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01142        should be aligned on a u16 frontier, as data to be filled into TDR will be
01143        handled through a u16 cast. */
01144     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01145     {
01146       if ((((uint32_t)pData) & 1U) != 0U)
01147       {
01148         return  HAL_ERROR;
01149       }
01150     }
01151
01152     huart->ErrorCode = HAL_UART_ERROR_NONE;
01153     huart->gState = HAL_UART_STATE_BUSY_TX;
01154
01155     /* Init tickstart for timeout management */
01156     tickstart = HAL_GetTick();
01157
01158     huart->TxXferSize  = Size;
01159     huart->TxXferCount = Size;
01160
01161     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
01162     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01163     {
01164       pdata8bits  = NULL;
01165       pdata16bits = (const uint16_t *) pData;
01166     }
01167     else
01168     {
01169       pdata8bits  = pData;
01170       pdata16bits = NULL;
01171     }
01172
01173     while (huart->TxXferCount > 0U)
01174     {
01175       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01176       {
01177         return HAL_TIMEOUT;
01178       }
01179       if (pdata8bits == NULL)
01180       {
01181         huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
01182         pdata16bits++;
01183       }
01184       else
01185       {
01186         huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
01187         pdata8bits++;
01188       }
01189       huart->TxXferCount--;
01190     }
01191
01192     if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
01193     {
01194       return HAL_TIMEOUT;
01195     }
01196
01197     /* At end of Tx process, restore huart->gState to Ready */
01198     huart->gState = HAL_UART_STATE_READY;
01199
01200     return HAL_OK;
01201   }
01202   else
01203   {
01204     return HAL_BUSY;
01205   }
01206 }
01207
01208 /**
01209   * @brief Receive an amount of data in blocking mode.
01210   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01211   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01212   *         of u16 available through pData.
01213   * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
01214   *       is not empty. Read operations from the RDR register are performed when
01215   *       RXFNE flag is set. From hardware perspective, RXFNE flag and
01216   *       RXNE are mapped on the same bit-field.
01217   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01218   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
01219   *         (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
01220   *         use of specific alignment compilation directives or pragmas might be required
01221   *         to ensure proper alignment for pData.
01222   * @param huart   UART handle.
01223   * @param pData   Pointer to data buffer (u8 or u16 data elements).
01224   * @param Size    Amount of data elements (u8 or u16) to be received.
01225   * @param Timeout Timeout duration.
01226   * @retval HAL status
01227   */
01228 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01229 {
01230   uint8_t  *pdata8bits;
01231   uint16_t *pdata16bits;
01232   uint16_t uhMask;
01233   uint32_t tickstart;
01234
01235   /* Check that a Rx process is not already ongoing */
01236   if (huart->RxState == HAL_UART_STATE_READY)
01237   {
01238     if ((pData == NULL) || (Size == 0U))
01239     {
01240       return  HAL_ERROR;
01241     }
01242
01243     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01244        should be aligned on a u16 frontier, as data to be received from RDR will be
01245        handled through a u16 cast. */
01246     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01247     {
01248       if ((((uint32_t)pData) & 1U) != 0U)
01249       {
01250         return  HAL_ERROR;
01251       }
01252     }
01253
01254     huart->ErrorCode = HAL_UART_ERROR_NONE;
01255     huart->RxState = HAL_UART_STATE_BUSY_RX;
01256     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01257
01258     /* Init tickstart for timeout management */
01259     tickstart = HAL_GetTick();
01260
01261     huart->RxXferSize  = Size;
01262     huart->RxXferCount = Size;
01263
01264     /* Computation of UART mask to apply to RDR register */
01265     UART_MASK_COMPUTATION(huart);
01266     uhMask = huart->Mask;
01267
01268     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
01269     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01270     {
01271       pdata8bits  = NULL;
01272       pdata16bits = (uint16_t *) pData;
01273     }
01274     else
01275     {
01276       pdata8bits  = pData;
01277       pdata16bits = NULL;
01278     }
01279
01280     /* as long as data have to be received */
01281     while (huart->RxXferCount > 0U)
01282     {
01283       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
01284       {
01285         return HAL_TIMEOUT;
01286       }
01287       if (pdata8bits == NULL)
01288       {
01289         *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
01290         pdata16bits++;
01291       }
01292       else
01293       {
01294         *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
01295         pdata8bits++;
01296       }
01297       huart->RxXferCount--;
01298     }
01299
01300     /* At end of Rx process, restore huart->RxState to Ready */
01301     huart->RxState = HAL_UART_STATE_READY;
01302
01303     return HAL_OK;
01304   }
01305   else
01306   {
01307     return HAL_BUSY;
01308   }
01309 }
01310
01311 /**
01312   * @brief Send an amount of data in interrupt mode.
01313   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01314   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01315   *         of u16 provided through pData.
01316   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01317   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
01318   *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
01319   *         use of specific alignment compilation directives or pragmas might be required
01320   *         to ensure proper alignment for pData.
01321   * @param huart UART handle.
01322   * @param pData Pointer to data buffer (u8 or u16 data elements).
01323   * @param Size  Amount of data elements (u8 or u16) to be sent.
01324   * @retval HAL status
01325   */
01326 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
01327 {
01328   /* Check that a Tx process is not already ongoing */
01329   if (huart->gState == HAL_UART_STATE_READY)
01330   {
01331     if ((pData == NULL) || (Size == 0U))
01332     {
01333       return HAL_ERROR;
01334     }
01335
01336     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01337        should be aligned on a u16 frontier, as data to be filled into TDR will be
01338        handled through a u16 cast. */
01339     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01340     {
01341       if ((((uint32_t)pData) & 1U) != 0U)
01342       {
01343         return  HAL_ERROR;
01344       }
01345     }
01346
01347     huart->pTxBuffPtr  = pData;
01348     huart->TxXferSize  = Size;
01349     huart->TxXferCount = Size;
01350     huart->TxISR       = NULL;
01351
01352     huart->ErrorCode = HAL_UART_ERROR_NONE;
01353     huart->gState = HAL_UART_STATE_BUSY_TX;
01354
01355     /* Configure Tx interrupt processing */
01356     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01357     {
01358       /* Set the Tx ISR function pointer according to the data word length */
01359       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01360       {
01361         huart->TxISR = UART_TxISR_16BIT_FIFOEN;
01362       }
01363       else
01364       {
01365         huart->TxISR = UART_TxISR_8BIT_FIFOEN;
01366       }
01367
01368       /* Enable the TX FIFO threshold interrupt */
01369       ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01370     }
01371     else
01372     {
01373       /* Set the Tx ISR function pointer according to the data word length */
01374       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01375       {
01376         huart->TxISR = UART_TxISR_16BIT;
01377       }
01378       else
01379       {
01380         huart->TxISR = UART_TxISR_8BIT;
01381       }
01382
01383       /* Enable the Transmit Data Register Empty interrupt */
01384       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01385     }
01386
01387     return HAL_OK;
01388   }
01389   else
01390   {
01391     return HAL_BUSY;
01392   }
01393 }
01394
01395 /**
01396   * @brief Receive an amount of data in interrupt mode.
01397   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01398   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01399   *         of u16 available through pData.
01400   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01401   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
01402   *         (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
01403   *         use of specific alignment compilation directives or pragmas might be required
01404   *         to ensure proper alignment for pData.
01405   * @param huart UART handle.
01406   * @param pData Pointer to data buffer (u8 or u16 data elements).
01407   * @param Size  Amount of data elements (u8 or u16) to be received.
01408   * @retval HAL status
01409   */
01410 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01411 {
01412   /* Check that a Rx process is not already ongoing */
01413   if (huart->RxState == HAL_UART_STATE_READY)
01414   {
01415     if ((pData == NULL) || (Size == 0U))
01416     {
01417       return HAL_ERROR;
01418     }
01419
01420     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01421        should be aligned on a u16 frontier, as data to be received from RDR will be
01422        handled through a u16 cast. */
01423     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01424     {
01425       if ((((uint32_t)pData) & 1U) != 0U)
01426       {
01427         return  HAL_ERROR;
01428       }
01429     }
01430
01431     /* Set Reception type to Standard reception */
01432     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01433
01434     if (!(IS_LPUART_INSTANCE(huart->Instance)))
01435     {
01436       /* Check that USART RTOEN bit is set */
01437       if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
01438       {
01439         /* Enable the UART Receiver Timeout Interrupt */
01440         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
01441       }
01442     }
01443
01444     return (UART_Start_Receive_IT(huart, pData, Size));
01445   }
01446   else
01447   {
01448     return HAL_BUSY;
01449   }
01450 }
01451
01452 /**
01453   * @brief Send an amount of data in DMA mode.
01454   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01455   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01456   *         of u16 provided through pData.
01457   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01458   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
01459   *         (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
01460   *         use of specific alignment compilation directives or pragmas might be required
01461   *         to ensure proper alignment for pData.
01462   * @param huart UART handle.
01463   * @param pData Pointer to data buffer (u8 or u16 data elements).
01464   * @param Size  Amount of data elements (u8 or u16) to be sent.
01465   * @retval HAL status
01466   */
01467 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
01468 {
01469   /* Check that a Tx process is not already ongoing */
01470   if (huart->gState == HAL_UART_STATE_READY)
01471   {
01472     if ((pData == NULL) || (Size == 0U))
01473     {
01474       return HAL_ERROR;
01475     }
01476
01477     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01478        should be aligned on a u16 frontier, as data copy into TDR will be
01479        handled by DMA from a u16 frontier. */
01480     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01481     {
01482       if ((((uint32_t)pData) & 1U) != 0U)
01483       {
01484         return  HAL_ERROR;
01485       }
01486     }
01487
01488     huart->pTxBuffPtr  = pData;
01489     huart->TxXferSize  = Size;
01490     huart->TxXferCount = Size;
01491
01492     huart->ErrorCode = HAL_UART_ERROR_NONE;
01493     huart->gState = HAL_UART_STATE_BUSY_TX;
01494
01495     if (huart->hdmatx != NULL)
01496     {
01497       /* Set the UART DMA transfer complete callback */
01498       huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
01499
01500       /* Set the UART DMA Half transfer complete callback */
01501       huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
01502
01503       /* Set the DMA error callback */
01504       huart->hdmatx->XferErrorCallback = UART_DMAError;
01505
01506       /* Set the DMA abort callback */
01507       huart->hdmatx->XferAbortCallback = NULL;
01508
01509       /* Enable the UART transmit DMA channel */
01510       if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
01511       {
01512         /* Set error code to DMA */
01513         huart->ErrorCode = HAL_UART_ERROR_DMA;
01514
01515         /* Restore huart->gState to ready */
01516         huart->gState = HAL_UART_STATE_READY;
01517
01518         return HAL_ERROR;
01519       }
01520     }
01521     /* Clear the TC flag in the ICR register */
01522     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
01523
01524     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01525     in the UART CR3 register */
01526     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01527
01528     return HAL_OK;
01529   }
01530   else
01531   {
01532     return HAL_BUSY;
01533   }
01534 }
01535
01536 /**
01537   * @brief Receive an amount of data in DMA mode.
01538   * @note   When the UART parity is enabled (PCE = 1), the received data contain
01539   *         the parity bit (MSB position).
01540   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01541   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01542   *         of u16 available through pData.
01543   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01544   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
01545   *         (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
01546   *         use of specific alignment compilation directives or pragmas might be required
01547   *         to ensure proper alignment for pData.
01548   * @param huart UART handle.
01549   * @param pData Pointer to data buffer (u8 or u16 data elements).
01550   * @param Size  Amount of data elements (u8 or u16) to be received.
01551   * @retval HAL status
01552   */
01553 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01554 {
01555   /* Check that a Rx process is not already ongoing */
01556   if (huart->RxState == HAL_UART_STATE_READY)
01557   {
01558     if ((pData == NULL) || (Size == 0U))
01559     {
01560       return HAL_ERROR;
01561     }
01562
01563     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
01564        should be aligned on a u16 frontier, as data copy from RDR will be
01565        handled by DMA from a u16 frontier. */
01566     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01567     {
01568       if ((((uint32_t)pData) & 1U) != 0U)
01569       {
01570         return  HAL_ERROR;
01571       }
01572     }
01573
01574     /* Set Reception type to Standard reception */
01575     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01576
01577     if (!(IS_LPUART_INSTANCE(huart->Instance)))
01578     {
01579       /* Check that USART RTOEN bit is set */
01580       if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
01581       {
01582         /* Enable the UART Receiver Timeout Interrupt */
01583         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
01584       }
01585     }
01586
01587     return (UART_Start_Receive_DMA(huart, pData, Size));
01588   }
01589   else
01590   {
01591     return HAL_BUSY;
01592   }
01593 }
01594
01595 /**
01596   * @brief Pause the DMA Transfer.
01597   * @param huart UART handle.
01598   * @retval HAL status
01599   */
01600 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
01601 {
01602   const HAL_UART_StateTypeDef gstate = huart->gState;
01603   const HAL_UART_StateTypeDef rxstate = huart->RxState;
01604
01605   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
01606       (gstate == HAL_UART_STATE_BUSY_TX))
01607   {
01608     /* Disable the UART DMA Tx request */
01609     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01610   }
01611   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
01612       (rxstate == HAL_UART_STATE_BUSY_RX))
01613   {
01614     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01615     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01616     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01617
01618     /* Disable the UART DMA Rx request */
01619     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01620   }
01621
01622   return HAL_OK;
01623 }
01624
01625 /**
01626   * @brief Resume the DMA Transfer.
01627   * @param huart UART handle.
01628   * @retval HAL status
01629   */
01630 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01631 {
01632   if (huart->gState == HAL_UART_STATE_BUSY_TX)
01633   {
01634     /* Enable the UART DMA Tx request */
01635     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01636   }
01637   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
01638   {
01639     /* Clear the Overrun flag before resuming the Rx transfer */
01640     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
01641
01642     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
01643     if (huart->Init.Parity != UART_PARITY_NONE)
01644     {
01645       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01646     }
01647     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01648
01649     /* Enable the UART DMA Rx request */
01650     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01651   }
01652
01653   return HAL_OK;
01654 }
01655
01656 /**
01657   * @brief Stop the DMA Transfer.
01658   * @param huart UART handle.
01659   * @retval HAL status
01660   */
01661 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01662 {
01663   /* The Lock is not implemented on this API to allow the user application
01664      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
01665      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
01666      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01667      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01668      the stream and the corresponding call back is executed. */
01669
01670   const HAL_UART_StateTypeDef gstate = huart->gState;
01671   const HAL_UART_StateTypeDef rxstate = huart->RxState;
01672
01673   /* Stop UART DMA Tx request if ongoing */
01674   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
01675       (gstate == HAL_UART_STATE_BUSY_TX))
01676   {
01677     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01678
01679     /* Abort the UART DMA Tx channel */
01680     if (huart->hdmatx != NULL)
01681     {
01682       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01683       {
01684         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01685         {
01686           /* Set error code to DMA */
01687           huart->ErrorCode = HAL_UART_ERROR_DMA;
01688
01689           return HAL_TIMEOUT;
01690         }
01691       }
01692     }
01693
01694     UART_EndTxTransfer(huart);
01695   }
01696
01697   /* Stop UART DMA Rx request if ongoing */
01698   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
01699       (rxstate == HAL_UART_STATE_BUSY_RX))
01700   {
01701     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01702
01703     /* Abort the UART DMA Rx channel */
01704     if (huart->hdmarx != NULL)
01705     {
01706       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01707       {
01708         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01709         {
01710           /* Set error code to DMA */
01711           huart->ErrorCode = HAL_UART_ERROR_DMA;
01712
01713           return HAL_TIMEOUT;
01714         }
01715       }
01716     }
01717
01718     UART_EndRxTransfer(huart);
01719   }
01720
01721   return HAL_OK;
01722 }
01723
01724 /**
01725   * @brief  Abort ongoing transfers (blocking mode).
01726   * @param  huart UART handle.
01727   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01728   *         This procedure performs following operations :
01729   *           - Disable UART Interrupts (Tx and Rx)
01730   *           - Disable the DMA transfer in the peripheral register (if enabled)
01731   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01732   *           - Set handle State to READY
01733   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01734   * @retval HAL status
01735   */
01736 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
01737 {
01738   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01739   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
01740                                           USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01741   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01742
01743   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
01744   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
01745   {
01746     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
01747   }
01748
01749   /* Abort the UART DMA Tx channel if enabled */
01750   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01751   {
01752     /* Disable the UART DMA Tx request if enabled */
01753     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01754
01755     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01756     if (huart->hdmatx != NULL)
01757     {
01758       /* Set the UART DMA Abort callback to Null.
01759          No call back execution at end of DMA abort procedure */
01760       huart->hdmatx->XferAbortCallback = NULL;
01761
01762       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01763       {
01764         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01765         {
01766           /* Set error code to DMA */
01767           huart->ErrorCode = HAL_UART_ERROR_DMA;
01768
01769           return HAL_TIMEOUT;
01770         }
01771       }
01772     }
01773   }
01774
01775   /* Abort the UART DMA Rx channel if enabled */
01776   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01777   {
01778     /* Disable the UART DMA Rx request if enabled */
01779     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01780
01781     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01782     if (huart->hdmarx != NULL)
01783     {
01784       /* Set the UART DMA Abort callback to Null.
01785          No call back execution at end of DMA abort procedure */
01786       huart->hdmarx->XferAbortCallback = NULL;
01787
01788       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01789       {
01790         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01791         {
01792           /* Set error code to DMA */
01793           huart->ErrorCode = HAL_UART_ERROR_DMA;
01794
01795           return HAL_TIMEOUT;
01796         }
01797       }
01798     }
01799   }
01800
01801   /* Reset Tx and Rx transfer counters */
01802   huart->TxXferCount = 0U;
01803   huart->RxXferCount = 0U;
01804
01805   /* Clear the Error flags in the ICR register */
01806   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01807
01808   /* Flush the whole TX FIFO (if needed) */
01809   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01810   {
01811     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01812   }
01813
01814   /* Discard the received data */
01815   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01816
01817   /* Restore huart->gState and huart->RxState to Ready */
01818   huart->gState  = HAL_UART_STATE_READY;
01819   huart->RxState = HAL_UART_STATE_READY;
01820   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01821
01822   huart->ErrorCode = HAL_UART_ERROR_NONE;
01823
01824   return HAL_OK;
01825 }
01826
01827 /**
01828   * @brief  Abort ongoing Transmit transfer (blocking mode).
01829   * @param  huart UART handle.
01830   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01831   *         This procedure performs following operations :
01832   *           - Disable UART Interrupts (Tx)
01833   *           - Disable the DMA transfer in the peripheral register (if enabled)
01834   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01835   *           - Set handle State to READY
01836   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01837   * @retval HAL status
01838   */
01839 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
01840 {
01841   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01842   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
01843   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01844
01845   /* Abort the UART DMA Tx channel if enabled */
01846   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01847   {
01848     /* Disable the UART DMA Tx request if enabled */
01849     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01850
01851     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01852     if (huart->hdmatx != NULL)
01853     {
01854       /* Set the UART DMA Abort callback to Null.
01855          No call back execution at end of DMA abort procedure */
01856       huart->hdmatx->XferAbortCallback = NULL;
01857
01858       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01859       {
01860         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01861         {
01862           /* Set error code to DMA */
01863           huart->ErrorCode = HAL_UART_ERROR_DMA;
01864
01865           return HAL_TIMEOUT;
01866         }
01867       }
01868     }
01869   }
01870
01871   /* Reset Tx transfer counter */
01872   huart->TxXferCount = 0U;
01873
01874   /* Flush the whole TX FIFO (if needed) */
01875   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01876   {
01877     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01878   }
01879
01880   /* Restore huart->gState to Ready */
01881   huart->gState = HAL_UART_STATE_READY;
01882
01883   return HAL_OK;
01884 }
01885
01886 /**
01887   * @brief  Abort ongoing Receive transfer (blocking mode).
01888   * @param  huart UART handle.
01889   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01890   *         This procedure performs following operations :
01891   *           - Disable UART Interrupts (Rx)
01892   *           - Disable the DMA transfer in the peripheral register (if enabled)
01893   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01894   *           - Set handle State to READY
01895   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01896   * @retval HAL status
01897   */
01898 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
01899 {
01900   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
01901   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
01902   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
01903
01904   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
01905   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
01906   {
01907     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
01908   }
01909
01910   /* Abort the UART DMA Rx channel if enabled */
01911   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01912   {
01913     /* Disable the UART DMA Rx request if enabled */
01914     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01915
01916     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01917     if (huart->hdmarx != NULL)
01918     {
01919       /* Set the UART DMA Abort callback to Null.
01920          No call back execution at end of DMA abort procedure */
01921       huart->hdmarx->XferAbortCallback = NULL;
01922
01923       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01924       {
01925         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01926         {
01927           /* Set error code to DMA */
01928           huart->ErrorCode = HAL_UART_ERROR_DMA;
01929
01930           return HAL_TIMEOUT;
01931         }
01932       }
01933     }
01934   }
01935
01936   /* Reset Rx transfer counter */
01937   huart->RxXferCount = 0U;
01938
01939   /* Clear the Error flags in the ICR register */
01940   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01941
01942   /* Discard the received data */
01943   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01944
01945   /* Restore huart->RxState to Ready */
01946   huart->RxState = HAL_UART_STATE_READY;
01947   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
01948
01949   return HAL_OK;
01950 }
01951
01952 /**
01953   * @brief  Abort ongoing transfers (Interrupt mode).
01954   * @param  huart UART handle.
01955   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01956   *         This procedure performs following operations :
01957   *           - Disable UART Interrupts (Tx and Rx)
01958   *           - Disable the DMA transfer in the peripheral register (if enabled)
01959   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01960   *           - Set handle State to READY
01961   *           - At abort completion, call user abort complete callback
01962   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01963   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01964   * @retval HAL status
01965   */
01966 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
01967 {
01968   uint32_t abortcplt = 1U;
01969
01970   /* Disable interrupts */
01971   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
01972                                           USART_CR1_TXEIE_TXFNFIE));
01973   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01974
01975   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
01976   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
01977   {
01978     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
01979   }
01980
01981   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
01982      before any call to DMA Abort functions */
01983   /* DMA Tx Handle is valid */
01984   if (huart->hdmatx != NULL)
01985   {
01986     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
01987        Otherwise, set it to NULL */
01988     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01989     {
01990       huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
01991     }
01992     else
01993     {
01994       huart->hdmatx->XferAbortCallback = NULL;
01995     }
01996   }
01997   /* DMA Rx Handle is valid */
01998   if (huart->hdmarx != NULL)
01999   {
02000     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
02001        Otherwise, set it to NULL */
02002     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02003     {
02004       huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
02005     }
02006     else
02007     {
02008       huart->hdmarx->XferAbortCallback = NULL;
02009     }
02010   }
02011
02012   /* Abort the UART DMA Tx channel if enabled */
02013   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
02014   {
02015     /* Disable DMA Tx at UART level */
02016     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
02017
02018     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
02019     if (huart->hdmatx != NULL)
02020     {
02021       /* UART Tx DMA Abort callback has already been initialised :
02022          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02023
02024       /* Abort DMA TX */
02025       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
02026       {
02027         huart->hdmatx->XferAbortCallback = NULL;
02028       }
02029       else
02030       {
02031         abortcplt = 0U;
02032       }
02033     }
02034   }
02035
02036   /* Abort the UART DMA Rx channel if enabled */
02037   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02038   {
02039     /* Disable the UART DMA Rx request if enabled */
02040     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02041
02042     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
02043     if (huart->hdmarx != NULL)
02044     {
02045       /* UART Rx DMA Abort callback has already been initialised :
02046          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02047
02048       /* Abort DMA RX */
02049       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02050       {
02051         huart->hdmarx->XferAbortCallback = NULL;
02052         abortcplt = 1U;
02053       }
02054       else
02055       {
02056         abortcplt = 0U;
02057       }
02058     }
02059   }
02060
02061   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
02062   if (abortcplt == 1U)
02063   {
02064     /* Reset Tx and Rx transfer counters */
02065     huart->TxXferCount = 0U;
02066     huart->RxXferCount = 0U;
02067
02068     /* Clear ISR function pointers */
02069     huart->RxISR = NULL;
02070     huart->TxISR = NULL;
02071
02072     /* Reset errorCode */
02073     huart->ErrorCode = HAL_UART_ERROR_NONE;
02074
02075     /* Clear the Error flags in the ICR register */
02076     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02077
02078     /* Flush the whole TX FIFO (if needed) */
02079     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
02080     {
02081       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
02082     }
02083
02084     /* Discard the received data */
02085     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
02086
02087     /* Restore huart->gState and huart->RxState to Ready */
02088     huart->gState  = HAL_UART_STATE_READY;
02089     huart->RxState = HAL_UART_STATE_READY;
02090     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02091
02092     /* As no DMA to be aborted, call directly user Abort complete callback */
02093 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02094     /* Call registered Abort complete callback */
02095     huart->AbortCpltCallback(huart);
02096 #else
02097     /* Call legacy weak Abort complete callback */
02098     HAL_UART_AbortCpltCallback(huart);
02099 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02100   }
02101
02102   return HAL_OK;
02103 }
02104
02105 /**
02106   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
02107   * @param  huart UART handle.
02108   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
02109   *         This procedure performs following operations :
02110   *           - Disable UART Interrupts (Tx)
02111   *           - Disable the DMA transfer in the peripheral register (if enabled)
02112   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02113   *           - Set handle State to READY
02114   *           - At abort completion, call user abort complete callback
02115   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02116   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02117   * @retval HAL status
02118   */
02119 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
02120 {
02121   /* Disable interrupts */
02122   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
02123   ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
02124
02125   /* Abort the UART DMA Tx channel if enabled */
02126   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
02127   {
02128     /* Disable the UART DMA Tx request if enabled */
02129     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
02130
02131     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
02132     if (huart->hdmatx != NULL)
02133     {
02134       /* Set the UART DMA Abort callback :
02135          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02136       huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
02137
02138       /* Abort DMA TX */
02139       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
02140       {
02141         /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
02142         huart->hdmatx->XferAbortCallback(huart->hdmatx);
02143       }
02144     }
02145     else
02146     {
02147       /* Reset Tx transfer counter */
02148       huart->TxXferCount = 0U;
02149
02150       /* Clear TxISR function pointers */
02151       huart->TxISR = NULL;
02152
02153       /* Restore huart->gState to Ready */
02154       huart->gState = HAL_UART_STATE_READY;
02155
02156       /* As no DMA to be aborted, call directly user Abort complete callback */
02157 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02158       /* Call registered Abort Transmit Complete Callback */
02159       huart->AbortTransmitCpltCallback(huart);
02160 #else
02161       /* Call legacy weak Abort Transmit Complete Callback */
02162       HAL_UART_AbortTransmitCpltCallback(huart);
02163 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02164     }
02165   }
02166   else
02167   {
02168     /* Reset Tx transfer counter */
02169     huart->TxXferCount = 0U;
02170
02171     /* Clear TxISR function pointers */
02172     huart->TxISR = NULL;
02173
02174     /* Flush the whole TX FIFO (if needed) */
02175     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
02176     {
02177       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
02178     }
02179
02180     /* Restore huart->gState to Ready */
02181     huart->gState = HAL_UART_STATE_READY;
02182
02183     /* As no DMA to be aborted, call directly user Abort complete callback */
02184 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02185     /* Call registered Abort Transmit Complete Callback */
02186     huart->AbortTransmitCpltCallback(huart);
02187 #else
02188     /* Call legacy weak Abort Transmit Complete Callback */
02189     HAL_UART_AbortTransmitCpltCallback(huart);
02190 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02191   }
02192
02193   return HAL_OK;
02194 }
02195
02196 /**
02197   * @brief  Abort ongoing Receive transfer (Interrupt mode).
02198   * @param  huart UART handle.
02199   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
02200   *         This procedure performs following operations :
02201   *           - Disable UART Interrupts (Rx)
02202   *           - Disable the DMA transfer in the peripheral register (if enabled)
02203   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02204   *           - Set handle State to READY
02205   *           - At abort completion, call user abort complete callback
02206   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02207   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02208   * @retval HAL status
02209   */
02210 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
02211 {
02212   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02213   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
02214   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
02215
02216   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
02217   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
02218   {
02219     ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
02220   }
02221
02222   /* Abort the UART DMA Rx channel if enabled */
02223   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02224   {
02225     /* Disable the UART DMA Rx request if enabled */
02226     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02227
02228     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
02229     if (huart->hdmarx != NULL)
02230     {
02231       /* Set the UART DMA Abort callback :
02232          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02233       huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
02234
02235       /* Abort DMA RX */
02236       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02237       {
02238         /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
02239         huart->hdmarx->XferAbortCallback(huart->hdmarx);
02240       }
02241     }
02242     else
02243     {
02244       /* Reset Rx transfer counter */
02245       huart->RxXferCount = 0U;
02246
02247       /* Clear RxISR function pointer */
02248       huart->pRxBuffPtr = NULL;
02249
02250       /* Clear the Error flags in the ICR register */
02251       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02252
02253       /* Discard the received data */
02254       __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
02255
02256       /* Restore huart->RxState to Ready */
02257       huart->RxState = HAL_UART_STATE_READY;
02258       huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02259
02260       /* As no DMA to be aborted, call directly user Abort complete callback */
02261 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02262       /* Call registered Abort Receive Complete Callback */
02263       huart->AbortReceiveCpltCallback(huart);
02264 #else
02265       /* Call legacy weak Abort Receive Complete Callback */
02266       HAL_UART_AbortReceiveCpltCallback(huart);
02267 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02268     }
02269   }
02270   else
02271   {
02272     /* Reset Rx transfer counter */
02273     huart->RxXferCount = 0U;
02274
02275     /* Clear RxISR function pointer */
02276     huart->pRxBuffPtr = NULL;
02277
02278     /* Clear the Error flags in the ICR register */
02279     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02280
02281     /* Restore huart->RxState to Ready */
02282     huart->RxState = HAL_UART_STATE_READY;
02283     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02284
02285     /* As no DMA to be aborted, call directly user Abort complete callback */
02286 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02287     /* Call registered Abort Receive Complete Callback */
02288     huart->AbortReceiveCpltCallback(huart);
02289 #else
02290     /* Call legacy weak Abort Receive Complete Callback */
02291     HAL_UART_AbortReceiveCpltCallback(huart);
02292 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02293   }
02294
02295   return HAL_OK;
02296 }
02297
02298 /**
02299   * @brief Handle UART interrupt request.
02300   * @param huart UART handle.
02301   * @retval None
02302   */
02303 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
02304 {
02305   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
02306   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
02307   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
02308
02309   uint32_t errorflags;
02310   uint32_t errorcode;
02311
02312   /* If no error occurs */
02313   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
02314   if (errorflags == 0U)
02315   {
02316     /* UART in mode Receiver ---------------------------------------------------*/
02317     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02318         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02319             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02320     {
02321       if (huart->RxISR != NULL)
02322       {
02323         huart->RxISR(huart);
02324       }
02325       return;
02326     }
02327   }
02328
02329   /* If some errors occur */
02330   if ((errorflags != 0U)
02331       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
02332            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
02333   {
02334     /* UART parity error interrupt occurred -------------------------------------*/
02335     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02336     {
02337       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
02338
02339       huart->ErrorCode |= HAL_UART_ERROR_PE;
02340     }
02341
02342     /* UART frame error interrupt occurred --------------------------------------*/
02343     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02344     {
02345       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
02346
02347       huart->ErrorCode |= HAL_UART_ERROR_FE;
02348     }
02349
02350     /* UART noise error interrupt occurred --------------------------------------*/
02351     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02352     {
02353       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
02354
02355       huart->ErrorCode |= HAL_UART_ERROR_NE;
02356     }
02357
02358     /* UART Over-Run interrupt occurred -----------------------------------------*/
02359     if (((isrflags & USART_ISR_ORE) != 0U)
02360         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
02361             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
02362     {
02363       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
02364
02365       huart->ErrorCode |= HAL_UART_ERROR_ORE;
02366     }
02367
02368     /* UART Receiver Timeout interrupt occurred ---------------------------------*/
02369     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
02370     {
02371       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
02372
02373       huart->ErrorCode |= HAL_UART_ERROR_RTO;
02374     }
02375
02376     /* Call UART Error Call back function if need be ----------------------------*/
02377     if (huart->ErrorCode != HAL_UART_ERROR_NONE)
02378     {
02379       /* UART in mode Receiver --------------------------------------------------*/
02380       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02381           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02382               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02383       {
02384         if (huart->RxISR != NULL)
02385         {
02386           huart->RxISR(huart);
02387         }
02388       }
02389
02390       /* If Error is to be considered as blocking :
02391           - Receiver Timeout error in Reception
02392           - Overrun error in Reception
02393           - any error occurs in DMA mode reception
02394       */
02395       errorcode = huart->ErrorCode;
02396       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
02397           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
02398       {
02399         /* Blocking error : transfer is aborted
02400            Set the UART state ready to be able to start again the process,
02401            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
02402         UART_EndRxTransfer(huart);
02403
02404         /* Abort the UART DMA Rx channel if enabled */
02405         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02406         {
02407           /* Disable the UART DMA Rx request if enabled */
02408           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02409
02410           /* Abort the UART DMA Rx channel */
02411           if (huart->hdmarx != NULL)
02412           {
02413             /* Set the UART DMA Abort callback :
02414                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
02415             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
02416
02417             /* Abort DMA RX */
02418             if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02419             {
02420               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
02421               huart->hdmarx->XferAbortCallback(huart->hdmarx);
02422             }
02423           }
02424           else
02425           {
02426             /* Call user error callback */
02427 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02428             /*Call registered error callback*/
02429             huart->ErrorCallback(huart);
02430 #else
02431             /*Call legacy weak error callback*/
02432             HAL_UART_ErrorCallback(huart);
02433 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02434
02435           }
02436         }
02437         else
02438         {
02439           /* Call user error callback */
02440 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02441           /*Call registered error callback*/
02442           huart->ErrorCallback(huart);
02443 #else
02444           /*Call legacy weak error callback*/
02445           HAL_UART_ErrorCallback(huart);
02446 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02447         }
02448       }
02449       else
02450       {
02451         /* Non Blocking error : transfer could go on.
02452            Error is notified to user through user error callback */
02453 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02454         /*Call registered error callback*/
02455         huart->ErrorCallback(huart);
02456 #else
02457         /*Call legacy weak error callback*/
02458         HAL_UART_ErrorCallback(huart);
02459 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02460         huart->ErrorCode = HAL_UART_ERROR_NONE;
02461       }
02462     }
02463     return;
02464
02465   } /* End if some error occurs */
02466
02467   /* Check current reception Mode :
02468      If Reception till IDLE event has been selected : */
02469   if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
02470       && ((isrflags & USART_ISR_IDLE) != 0U)
02471       && ((cr1its & USART_ISR_IDLE) != 0U))
02472   {
02473     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
02474
02475     /* Check if DMA mode is enabled in UART */
02476     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02477     {
02478       /* DMA mode enabled */
02479       /* Check received length : If all expected data are received, do nothing,
02480          (DMA cplt callback will be called).
02481          Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
02482       uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
02483       if ((nb_remaining_rx_data > 0U)
02484           && (nb_remaining_rx_data < huart->RxXferSize))
02485       {
02486         /* Reception is not complete */
02487         huart->RxXferCount = nb_remaining_rx_data;
02488
02489         /* In Normal mode, end DMA xfer and HAL UART Rx process*/
02490         if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
02491         {
02492           /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02493           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
02494           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02495
02496           /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02497              in the UART CR3 register */
02498           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02499
02500           /* At end of Rx process, restore huart->RxState to Ready */
02501           huart->RxState = HAL_UART_STATE_READY;
02502           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02503
02504           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
02505
02506           /* Last bytes received, so no need as the abort is immediate */
02507           (void)HAL_DMA_Abort(huart->hdmarx);
02508         }
02509
02510         /* Initialize type of RxEvent that correspond to RxEvent callback execution;
02511            In this case, Rx Event type is Idle Event */
02512         huart->RxEventType = HAL_UART_RXEVENT_IDLE;
02513
02514 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02515         /*Call registered Rx Event callback*/
02516         huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
02517 #else
02518         /*Call legacy weak Rx Event callback*/
02519         HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
02520 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
02521       }
02522       return;
02523     }
02524     else
02525     {
02526       /* DMA mode not enabled */
02527       /* Check received length : If all expected data are received, do nothing.
02528          Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
02529       uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
02530       if ((huart->RxXferCount > 0U)
02531           && (nb_rx_data > 0U))
02532       {
02533         /* Disable the UART Parity Error Interrupt and RXNE interrupts */
02534         ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02535
02536         /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
02537         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
02538
02539         /* Rx process is completed, restore huart->RxState to Ready */
02540         huart->RxState = HAL_UART_STATE_READY;
02541         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
02542
02543         /* Clear RxISR function pointer */
02544         huart->RxISR = NULL;
02545
02546         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
02547
02548         /* Initialize type of RxEvent that correspond to RxEvent callback execution;
02549            In this case, Rx Event type is Idle Event */
02550         huart->RxEventType = HAL_UART_RXEVENT_IDLE;
02551
02552 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02553         /*Call registered Rx complete callback*/
02554         huart->RxEventCallback(huart, nb_rx_data);
02555 #else
02556         /*Call legacy weak Rx Event callback*/
02557         HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
02558 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
02559       }
02560       return;
02561     }
02562   }
02563
02564   /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
02565   if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
02566   {
02567     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
02568
02569     /* UART Rx state is not reset as a reception process might be ongoing.
02570        If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
02571
02572 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02573     /* Call registered Wakeup Callback */
02574     huart->WakeupCallback(huart);
02575 #else
02576     /* Call legacy weak Wakeup Callback */
02577     HAL_UARTEx_WakeupCallback(huart);
02578 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02579     return;
02580   }
02581
02582   /* UART in mode Transmitter ------------------------------------------------*/
02583   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02584       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02585           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02586   {
02587     if (huart->TxISR != NULL)
02588     {
02589       huart->TxISR(huart);
02590     }
02591     return;
02592   }
02593
02594   /* UART in mode Transmitter (transmission end) -----------------------------*/
02595   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02596   {
02597     UART_EndTransmit_IT(huart);
02598     return;
02599   }
02600
02601   /* UART TX Fifo Empty occurred ----------------------------------------------*/
02602   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02603   {
02604 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02605     /* Call registered Tx Fifo Empty Callback */
02606     huart->TxFifoEmptyCallback(huart);
02607 #else
02608     /* Call legacy weak Tx Fifo Empty Callback */
02609     HAL_UARTEx_TxFifoEmptyCallback(huart);
02610 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02611     return;
02612   }
02613
02614   /* UART RX Fifo Full occurred ----------------------------------------------*/
02615   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02616   {
02617 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02618     /* Call registered Rx Fifo Full Callback */
02619     huart->RxFifoFullCallback(huart);
02620 #else
02621     /* Call legacy weak Rx Fifo Full Callback */
02622     HAL_UARTEx_RxFifoFullCallback(huart);
02623 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02624     return;
02625   }
02626 }
02627
02628 /**
02629   * @brief Tx Transfer completed callback.
02630   * @param huart UART handle.
02631   * @retval None
02632   */
02633 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
02634 {
02635   /* Prevent unused argument(s) compilation warning */
02636   UNUSED(huart);
02637
02638   /* NOTE : This function should not be modified, when the callback is needed,
02639             the HAL_UART_TxCpltCallback can be implemented in the user file.
02640    */
02641 }
02642
02643 /**
02644   * @brief  Tx Half Transfer completed callback.
02645   * @param  huart UART handle.
02646   * @retval None
02647   */
02648 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
02649 {
02650   /* Prevent unused argument(s) compilation warning */
02651   UNUSED(huart);
02652
02653   /* NOTE: This function should not be modified, when the callback is needed,
02654            the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
02655    */
02656 }
02657
02658 /**
02659   * @brief  Rx Transfer completed callback.
02660   * @param  huart UART handle.
02661   * @retval None
02662   */
02663 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
02664 {
02665   /* Prevent unused argument(s) compilation warning */
02666   UNUSED(huart);
02667
02668   /* NOTE : This function should not be modified, when the callback is needed,
02669             the HAL_UART_RxCpltCallback can be implemented in the user file.
02670    */
02671 }
02672
02673 /**
02674   * @brief  Rx Half Transfer completed callback.
02675   * @param  huart UART handle.
02676   * @retval None
02677   */
02678 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
02679 {
02680   /* Prevent unused argument(s) compilation warning */
02681   UNUSED(huart);
02682
02683   /* NOTE: This function should not be modified, when the callback is needed,
02684            the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
02685    */
02686 }
02687
02688 /**
02689   * @brief  UART error callback.
02690   * @param  huart UART handle.
02691   * @retval None
02692   */
02693 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
02694 {
02695   /* Prevent unused argument(s) compilation warning */
02696   UNUSED(huart);
02697
02698   /* NOTE : This function should not be modified, when the callback is needed,
02699             the HAL_UART_ErrorCallback can be implemented in the user file.
02700    */
02701 }
02702
02703 /**
02704   * @brief  UART Abort Complete callback.
02705   * @param  huart UART handle.
02706   * @retval None
02707   */
02708 __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
02709 {
02710   /* Prevent unused argument(s) compilation warning */
02711   UNUSED(huart);
02712
02713   /* NOTE : This function should not be modified, when the callback is needed,
02714             the HAL_UART_AbortCpltCallback can be implemented in the user file.
02715    */
02716 }
02717
02718 /**
02719   * @brief  UART Abort Complete callback.
02720   * @param  huart UART handle.
02721   * @retval None
02722   */
02723 __weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
02724 {
02725   /* Prevent unused argument(s) compilation warning */
02726   UNUSED(huart);
02727
02728   /* NOTE : This function should not be modified, when the callback is needed,
02729             the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
02730    */
02731 }
02732
02733 /**
02734   * @brief  UART Abort Receive Complete callback.
02735   * @param  huart UART handle.
02736   * @retval None
02737   */
02738 __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
02739 {
02740   /* Prevent unused argument(s) compilation warning */
02741   UNUSED(huart);
02742
02743   /* NOTE : This function should not be modified, when the callback is needed,
02744             the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
02745    */
02746 }
02747
02748 /**
02749   * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
02750   * @param  huart UART handle
02751   * @param  Size  Number of data available in application reception buffer (indicates a position in
02752   *               reception buffer until which, data are available)
02753   * @retval None
02754   */
02755 __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
02756 {
02757   /* Prevent unused argument(s) compilation warning */
02758   UNUSED(huart);
02759   UNUSED(Size);
02760
02761   /* NOTE : This function should not be modified, when the callback is needed,
02762             the HAL_UARTEx_RxEventCallback can be implemented in the user file.
02763    */
02764 }
02765
02766 /**
02767   * @}
02768   */
02769
02770 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
02771   *  @brief   UART control functions
02772   *
02773 @verbatim
02774  ===============================================================================
02775                       ##### Peripheral Control functions #####
02776  ===============================================================================
02777     [..]
02778     This subsection provides a set of functions allowing to control the UART.
02779      (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
02780      (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
02781      (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
02782      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
02783      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
02784      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
02785      (+) UART_SetConfig() API configures the UART peripheral
02786      (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
02787      (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
02788      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
02789      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
02790      (+) HAL_LIN_SendBreak() API transmits the break characters
02791 @endverbatim
02792   * @{
02793   */
02794
02795 /**
02796   * @brief  Update on the fly the receiver timeout value in RTOR register.
02797   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02798   *                    the configuration information for the specified UART module.
02799   * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
02800   *                     value must be less or equal to 0x0FFFFFFFF.
02801   * @retval None
02802   */
02803 void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
02804 {
02805   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02806   {
02807     assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
02808     MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
02809   }
02810 }
02811
02812 /**
02813   * @brief  Enable the UART receiver timeout feature.
02814   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02815   *                    the configuration information for the specified UART module.
02816   * @retval HAL status
02817   */
02818 HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
02819 {
02820   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02821   {
02822     if (huart->gState == HAL_UART_STATE_READY)
02823     {
02824       /* Process Locked */
02825       __HAL_LOCK(huart);
02826
02827       huart->gState = HAL_UART_STATE_BUSY;
02828
02829       /* Set the USART RTOEN bit */
02830       SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
02831
02832       huart->gState = HAL_UART_STATE_READY;
02833
02834       /* Process Unlocked */
02835       __HAL_UNLOCK(huart);
02836
02837       return HAL_OK;
02838     }
02839     else
02840     {
02841       return HAL_BUSY;
02842     }
02843   }
02844   else
02845   {
02846     return HAL_ERROR;
02847   }
02848 }
02849
02850 /**
02851   * @brief  Disable the UART receiver timeout feature.
02852   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02853   *                    the configuration information for the specified UART module.
02854   * @retval HAL status
02855   */
02856 HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
02857 {
02858   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02859   {
02860     if (huart->gState == HAL_UART_STATE_READY)
02861     {
02862       /* Process Locked */
02863       __HAL_LOCK(huart);
02864
02865       huart->gState = HAL_UART_STATE_BUSY;
02866
02867       /* Clear the USART RTOEN bit */
02868       CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
02869
02870       huart->gState = HAL_UART_STATE_READY;
02871
02872       /* Process Unlocked */
02873       __HAL_UNLOCK(huart);
02874
02875       return HAL_OK;
02876     }
02877     else
02878     {
02879       return HAL_BUSY;
02880     }
02881   }
02882   else
02883   {
02884     return HAL_ERROR;
02885   }
02886 }
02887
02888 /**
02889   * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
02890   *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
02891   * @param  huart UART handle.
02892   * @retval HAL status
02893   */
02894 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
02895 {
02896   __HAL_LOCK(huart);
02897
02898   huart->gState = HAL_UART_STATE_BUSY;
02899
02900   /* Enable USART mute mode by setting the MME bit in the CR1 register */
02901   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
02902
02903   huart->gState = HAL_UART_STATE_READY;
02904
02905   return (UART_CheckIdleState(huart));
02906 }
02907
02908 /**
02909   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
02910   *         as it may not have been in mute mode at this very moment).
02911   * @param  huart UART handle.
02912   * @retval HAL status
02913   */
02914 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
02915 {
02916   __HAL_LOCK(huart);
02917
02918   huart->gState = HAL_UART_STATE_BUSY;
02919
02920   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
02921   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
02922
02923   huart->gState = HAL_UART_STATE_READY;
02924
02925   return (UART_CheckIdleState(huart));
02926 }
02927
02928 /**
02929   * @brief Enter UART mute mode (means UART actually enters mute mode).
02930   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
02931   * @param huart UART handle.
02932   * @retval None
02933   */
02934 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
02935 {
02936   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
02937 }
02938
02939 /**
02940   * @brief  Enable the UART transmitter and disable the UART receiver.
02941   * @param  huart UART handle.
02942   * @retval HAL status
02943   */
02944 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
02945 {
02946   __HAL_LOCK(huart);
02947   huart->gState = HAL_UART_STATE_BUSY;
02948
02949   /* Clear TE and RE bits */
02950   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
02951
02952   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
02953   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
02954
02955   huart->gState = HAL_UART_STATE_READY;
02956
02957   __HAL_UNLOCK(huart);
02958
02959   return HAL_OK;
02960 }
02961
02962 /**
02963   * @brief  Enable the UART receiver and disable the UART transmitter.
02964   * @param  huart UART handle.
02965   * @retval HAL status.
02966   */
02967 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
02968 {
02969   __HAL_LOCK(huart);
02970   huart->gState = HAL_UART_STATE_BUSY;
02971
02972   /* Clear TE and RE bits */
02973   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
02974
02975   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
02976   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
02977
02978   huart->gState = HAL_UART_STATE_READY;
02979
02980   __HAL_UNLOCK(huart);
02981
02982   return HAL_OK;
02983 }
02984
02985
02986 /**
02987   * @brief  Transmit break characters.
02988   * @param  huart UART handle.
02989   * @retval HAL status
02990   */
02991 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
02992 {
02993   /* Check the parameters */
02994   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
02995
02996   __HAL_LOCK(huart);
02997
02998   huart->gState = HAL_UART_STATE_BUSY;
02999
03000   /* Send break characters */
03001   __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
03002
03003   huart->gState = HAL_UART_STATE_READY;
03004
03005   __HAL_UNLOCK(huart);
03006
03007   return HAL_OK;
03008 }
03009
03010 /**
03011   * @}
03012   */
03013
03014 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
03015   *  @brief   UART Peripheral State functions
03016   *
03017 @verbatim
03018   ==============================================================================
03019             ##### Peripheral State and Error functions #####
03020   ==============================================================================
03021     [..]
03022     This subsection provides functions allowing to :
03023       (+) Return the UART handle state.
03024       (+) Return the UART handle error code
03025
03026 @endverbatim
03027   * @{
03028   */
03029
03030 /**
03031   * @brief Return the UART handle state.
03032   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
03033   *               the configuration information for the specified UART.
03034   * @retval HAL state
03035   */
03036 HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart)
03037 {
03038   uint32_t temp1;
03039   uint32_t temp2;
03040   temp1 = huart->gState;
03041   temp2 = huart->RxState;
03042
03043   return (HAL_UART_StateTypeDef)(temp1 | temp2);
03044 }
03045
03046 /**
03047   * @brief  Return the UART handle error code.
03048   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
03049   *               the configuration information for the specified UART.
03050   * @retval UART Error Code
03051   */
03052 uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart)
03053 {
03054   return huart->ErrorCode;
03055 }
03056 /**
03057   * @}
03058   */
03059
03060 /**
03061   * @}
03062   */
03063
03064 /** @defgroup UART_Private_Functions UART Private Functions
03065   * @{
03066   */
03067
03068 /**
03069   * @brief  Initialize the callbacks to their default values.
03070   * @param  huart UART handle.
03071   * @retval none
03072   */
03073 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03074 void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
03075 {
03076   /* Init the UART Callback settings */
03077   huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
03078   huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
03079   huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
03080   huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
03081   huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
03082   huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
03083   huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
03084   huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
03085   huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
03086   huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
03087   huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
03088   huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
03089
03090 }
03091 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03092
03093 /**
03094   * @brief Configure the UART peripheral.
03095   * @param huart UART handle.
03096   * @retval HAL status
03097   */
03098 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
03099 {
03100   uint32_t tmpreg;
03101   uint16_t brrtemp;
03102   UART_ClockSourceTypeDef clocksource;
03103   uint32_t usartdiv;
03104   HAL_StatusTypeDef ret               = HAL_OK;
03105   uint32_t lpuart_ker_ck_pres;
03106   uint32_t pclk;
03107
03108   /* Check the parameters */
03109   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
03110   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
03111   if (UART_INSTANCE_LOWPOWER(huart))
03112   {
03113     assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
03114   }
03115   else
03116   {
03117     assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
03118     assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
03119   }
03120
03121   assert_param(IS_UART_PARITY(huart->Init.Parity));
03122   assert_param(IS_UART_MODE(huart->Init.Mode));
03123   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
03124   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
03125   assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
03126
03127   /*-------------------------- USART CR1 Configuration -----------------------*/
03128   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
03129   *  the UART Word Length, Parity, Mode and oversampling:
03130   *  set the M bits according to huart->Init.WordLength value
03131   *  set PCE and PS bits according to huart->Init.Parity value
03132   *  set TE and RE bits according to huart->Init.Mode value
03133   *  set OVER8 bit according to huart->Init.OverSampling value */
03134   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
03135   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
03136
03137   /*-------------------------- USART CR2 Configuration -----------------------*/
03138   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
03139   * to huart->Init.StopBits value */
03140   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
03141
03142   /*-------------------------- USART CR3 Configuration -----------------------*/
03143   /* Configure
03144   * - UART HardWare Flow Control: set CTSE and RTSE bits according
03145   *   to huart->Init.HwFlowCtl value
03146   * - one-bit sampling method versus three samples' majority rule according
03147   *   to huart->Init.OneBitSampling (not applicable to LPUART) */
03148   tmpreg = (uint32_t)huart->Init.HwFlowCtl;
03149
03150   if (!(UART_INSTANCE_LOWPOWER(huart)))
03151   {
03152     tmpreg |= huart->Init.OneBitSampling;
03153   }
03154   MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
03155
03156   /*-------------------------- USART PRESC Configuration -----------------------*/
03157   /* Configure
03158   * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
03159   MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
03160
03161   /*-------------------------- USART BRR Configuration -----------------------*/
03162   UART_GETCLOCKSOURCE(huart, clocksource);
03163
03164   /* Check LPUART instance */
03165   if (UART_INSTANCE_LOWPOWER(huart))
03166   {
03167     /* Retrieve frequency clock */
03168     switch (clocksource)
03169     {
03170       case UART_CLOCKSOURCE_PCLK1:
03171         pclk = HAL_RCC_GetPCLK1Freq();
03172         break;
03173       case UART_CLOCKSOURCE_HSI:
03174         pclk = (uint32_t) HSI_VALUE;
03175         break;
03176       case UART_CLOCKSOURCE_SYSCLK:
03177         pclk = HAL_RCC_GetSysClockFreq();
03178         break;
03179       case UART_CLOCKSOURCE_LSE:
03180         pclk = (uint32_t) LSE_VALUE;
03181         break;
03182       default:
03183         pclk = 0U;
03184         ret = HAL_ERROR;
03185         break;
03186     }
03187
03188     /* If proper clock source reported */
03189     if (pclk != 0U)
03190     {
03191       /* Compute clock after Prescaler */
03192       lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
03193
03194       /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
03195       if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
03196           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
03197       {
03198         ret = HAL_ERROR;
03199       }
03200       else
03201       {
03202         /* Check computed UsartDiv value is in allocated range
03203            (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
03204         usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03205         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
03206         {
03207           huart->Instance->BRR = usartdiv;
03208         }
03209         else
03210         {
03211           ret = HAL_ERROR;
03212         }
03213       } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
03214                 (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
03215     } /* if (pclk != 0) */
03216   }
03217   /* Check UART Over Sampling to set Baud Rate Register */
03218   else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
03219   {
03220     switch (clocksource)
03221     {
03222       case UART_CLOCKSOURCE_PCLK1:
03223         pclk = HAL_RCC_GetPCLK1Freq();
03224         break;
03225       case UART_CLOCKSOURCE_HSI:
03226         pclk = (uint32_t) HSI_VALUE;
03227         break;
03228       case UART_CLOCKSOURCE_SYSCLK:
03229         pclk = HAL_RCC_GetSysClockFreq();
03230         break;
03231       case UART_CLOCKSOURCE_LSE:
03232         pclk = (uint32_t) LSE_VALUE;
03233         break;
03234       default:
03235         pclk = 0U;
03236         ret = HAL_ERROR;
03237         break;
03238     }
03239
03240     /* USARTDIV must be greater than or equal to 0d16 */
03241     if (pclk != 0U)
03242     {
03243       usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03244       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
03245       {
03246         brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
03247         brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
03248         huart->Instance->BRR = brrtemp;
03249       }
03250       else
03251       {
03252         ret = HAL_ERROR;
03253       }
03254     }
03255   }
03256   else
03257   {
03258     switch (clocksource)
03259     {
03260       case UART_CLOCKSOURCE_PCLK1:
03261         pclk = HAL_RCC_GetPCLK1Freq();
03262         break;
03263       case UART_CLOCKSOURCE_HSI:
03264         pclk = (uint32_t) HSI_VALUE;
03265         break;
03266       case UART_CLOCKSOURCE_SYSCLK:
03267         pclk = HAL_RCC_GetSysClockFreq();
03268         break;
03269       case UART_CLOCKSOURCE_LSE:
03270         pclk = (uint32_t) LSE_VALUE;
03271         break;
03272       default:
03273         pclk = 0U;
03274         ret = HAL_ERROR;
03275         break;
03276     }
03277
03278     if (pclk != 0U)
03279     {
03280       /* USARTDIV must be greater than or equal to 0d16 */
03281       usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03282       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
03283       {
03284         huart->Instance->BRR = (uint16_t)usartdiv;
03285       }
03286       else
03287       {
03288         ret = HAL_ERROR;
03289       }
03290     }
03291   }
03292
03293   /* Initialize the number of data to process during RX/TX ISR execution */
03294   huart->NbTxDataToProcess = 1;
03295   huart->NbRxDataToProcess = 1;
03296
03297   /* Clear ISR function pointers */
03298   huart->RxISR = NULL;
03299   huart->TxISR = NULL;
03300
03301   return ret;
03302 }
03303
03304 /**
03305   * @brief Configure the UART peripheral advanced features.
03306   * @param huart UART handle.
03307   * @retval None
03308   */
03309 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
03310 {
03311   /* Check whether the set of advanced features to configure is properly set */
03312   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
03313
03314   /* if required, configure TX pin active level inversion */
03315   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
03316   {
03317     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
03318     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
03319   }
03320
03321   /* if required, configure RX pin active level inversion */
03322   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
03323   {
03324     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
03325     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
03326   }
03327
03328   /* if required, configure data inversion */
03329   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
03330   {
03331     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
03332     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
03333   }
03334
03335   /* if required, configure RX/TX pins swap */
03336   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
03337   {
03338     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
03339     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
03340   }
03341
03342   /* if required, configure RX overrun detection disabling */
03343   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
03344   {
03345     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
03346     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
03347   }
03348
03349   /* if required, configure DMA disabling on reception error */
03350   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
03351   {
03352     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
03353     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
03354   }
03355
03356   /* if required, configure auto Baud rate detection scheme */
03357   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
03358   {
03359     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
03360     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
03361     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
03362     /* set auto Baudrate detection parameters if detection is enabled */
03363     if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
03364     {
03365       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
03366       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
03367     }
03368   }
03369
03370   /* if required, configure MSB first on communication line */
03371   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
03372   {
03373     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
03374     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
03375   }
03376 }
03377
03378 /**
03379   * @brief Check the UART Idle State.
03380   * @param huart UART handle.
03381   * @retval HAL status
03382   */
03383 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
03384 {
03385   uint32_t tickstart;
03386
03387   /* Initialize the UART ErrorCode */
03388   huart->ErrorCode = HAL_UART_ERROR_NONE;
03389
03390   /* Init tickstart for timeout management */
03391   tickstart = HAL_GetTick();
03392
03393   /* Check if the Transmitter is enabled */
03394   if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
03395   {
03396     /* Wait until TEACK flag is set */
03397     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
03398     {
03399       /* Timeout occurred */
03400       return HAL_TIMEOUT;
03401     }
03402   }
03403
03404   /* Check if the Receiver is enabled */
03405   if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
03406   {
03407     /* Wait until REACK flag is set */
03408     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
03409     {
03410       /* Timeout occurred */
03411       return HAL_TIMEOUT;
03412     }
03413   }
03414
03415   /* Initialize the UART State */
03416   huart->gState = HAL_UART_STATE_READY;
03417   huart->RxState = HAL_UART_STATE_READY;
03418   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03419   huart->RxEventType = HAL_UART_RXEVENT_TC;
03420
03421   __HAL_UNLOCK(huart);
03422
03423   return HAL_OK;
03424 }
03425
03426 /**
03427   * @brief  This function handles UART Communication Timeout. It waits
03428   *                  until a flag is no longer in the specified status.
03429   * @param huart     UART handle.
03430   * @param Flag      Specifies the UART flag to check
03431   * @param Status    The actual Flag status (SET or RESET)
03432   * @param Tickstart Tick start value
03433   * @param Timeout   Timeout duration
03434   * @retval HAL status
03435   */
03436 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
03437                                               uint32_t Tickstart, uint32_t Timeout)
03438 {
03439   /* Wait until flag is set */
03440   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
03441   {
03442     /* Check for the Timeout */
03443     if (Timeout != HAL_MAX_DELAY)
03444     {
03445       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
03446       {
03447         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
03448            interrupts for the interrupt process */
03449         ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
03450                                                 USART_CR1_TXEIE_TXFNFIE));
03451         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03452
03453         huart->gState = HAL_UART_STATE_READY;
03454         huart->RxState = HAL_UART_STATE_READY;
03455
03456         __HAL_UNLOCK(huart);
03457
03458         return HAL_TIMEOUT;
03459       }
03460
03461       if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
03462       {
03463         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
03464         {
03465           /* Clear Receiver Timeout flag*/
03466           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
03467
03468           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
03469              interrupts for the interrupt process */
03470           ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
03471                                                   USART_CR1_TXEIE_TXFNFIE));
03472           ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03473
03474           huart->gState = HAL_UART_STATE_READY;
03475           huart->RxState = HAL_UART_STATE_READY;
03476           huart->ErrorCode = HAL_UART_ERROR_RTO;
03477
03478           /* Process Unlocked */
03479           __HAL_UNLOCK(huart);
03480
03481           return HAL_TIMEOUT;
03482         }
03483       }
03484     }
03485   }
03486   return HAL_OK;
03487 }
03488
03489 /**
03490   * @brief  Start Receive operation in interrupt mode.
03491   * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
03492   * @note   When calling this function, parameters validity is considered as already checked,
03493   *         i.e. Rx State, buffer address, ...
03494   *         UART Handle is assumed as Locked.
03495   * @param  huart UART handle.
03496   * @param  pData Pointer to data buffer (u8 or u16 data elements).
03497   * @param  Size  Amount of data elements (u8 or u16) to be received.
03498   * @retval HAL status
03499   */
03500 HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
03501 {
03502   huart->pRxBuffPtr  = pData;
03503   huart->RxXferSize  = Size;
03504   huart->RxXferCount = Size;
03505   huart->RxISR       = NULL;
03506
03507   /* Computation of UART mask to apply to RDR register */
03508   UART_MASK_COMPUTATION(huart);
03509
03510   huart->ErrorCode = HAL_UART_ERROR_NONE;
03511   huart->RxState = HAL_UART_STATE_BUSY_RX;
03512
03513   /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
03514   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
03515
03516   /* Configure Rx interrupt processing */
03517   if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
03518   {
03519     /* Set the Rx ISR function pointer according to the data word length */
03520     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
03521     {
03522       huart->RxISR = UART_RxISR_16BIT_FIFOEN;
03523     }
03524     else
03525     {
03526       huart->RxISR = UART_RxISR_8BIT_FIFOEN;
03527     }
03528
03529     /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
03530     if (huart->Init.Parity != UART_PARITY_NONE)
03531     {
03532       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03533     }
03534     ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
03535   }
03536   else
03537   {
03538     /* Set the Rx ISR function pointer according to the data word length */
03539     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
03540     {
03541       huart->RxISR = UART_RxISR_16BIT;
03542     }
03543     else
03544     {
03545       huart->RxISR = UART_RxISR_8BIT;
03546     }
03547
03548     /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
03549     if (huart->Init.Parity != UART_PARITY_NONE)
03550     {
03551       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
03552     }
03553     else
03554     {
03555       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03556     }
03557   }
03558   return HAL_OK;
03559 }
03560
03561 /**
03562   * @brief  Start Receive operation in DMA mode.
03563   * @note   This function could be called by all HAL UART API providing reception in DMA mode.
03564   * @note   When calling this function, parameters validity is considered as already checked,
03565   *         i.e. Rx State, buffer address, ...
03566   *         UART Handle is assumed as Locked.
03567   * @param  huart UART handle.
03568   * @param  pData Pointer to data buffer (u8 or u16 data elements).
03569   * @param  Size  Amount of data elements (u8 or u16) to be received.
03570   * @retval HAL status
03571   */
03572 HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
03573 {
03574   huart->pRxBuffPtr = pData;
03575   huart->RxXferSize = Size;
03576
03577   huart->ErrorCode = HAL_UART_ERROR_NONE;
03578   huart->RxState = HAL_UART_STATE_BUSY_RX;
03579
03580   if (huart->hdmarx != NULL)
03581   {
03582     /* Set the UART DMA transfer complete callback */
03583     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
03584
03585     /* Set the UART DMA Half transfer complete callback */
03586     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
03587
03588     /* Set the DMA error callback */
03589     huart->hdmarx->XferErrorCallback = UART_DMAError;
03590
03591     /* Set the DMA abort callback */
03592     huart->hdmarx->XferAbortCallback = NULL;
03593
03594     /* Enable the DMA channel */
03595     if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
03596     {
03597       /* Set error code to DMA */
03598       huart->ErrorCode = HAL_UART_ERROR_DMA;
03599
03600       /* Restore huart->RxState to ready */
03601       huart->RxState = HAL_UART_STATE_READY;
03602
03603       return HAL_ERROR;
03604     }
03605   }
03606
03607   /* Enable the UART Parity Error Interrupt */
03608   if (huart->Init.Parity != UART_PARITY_NONE)
03609   {
03610     ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03611   }
03612
03613   /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
03614   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
03615
03616   /* Enable the DMA transfer for the receiver request by setting the DMAR bit
03617   in the UART CR3 register */
03618   ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
03619
03620   return HAL_OK;
03621 }
03622
03623
03624 /**
03625   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
03626   * @param  huart UART handle.
03627   * @retval None
03628   */
03629 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
03630 {
03631   /* Disable TXEIE, TCIE, TXFT interrupts */
03632   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
03633   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
03634
03635   /* At end of Tx process, restore huart->gState to Ready */
03636   huart->gState = HAL_UART_STATE_READY;
03637 }
03638
03639
03640 /**
03641   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
03642   * @param  huart UART handle.
03643   * @retval None
03644   */
03645 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
03646 {
03647   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
03648   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03649   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03650
03651   /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
03652   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
03653   {
03654     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
03655   }
03656
03657   /* At end of Rx process, restore huart->RxState to Ready */
03658   huart->RxState = HAL_UART_STATE_READY;
03659   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03660
03661   /* Reset RxIsr function pointer */
03662   huart->RxISR = NULL;
03663 }
03664
03665
03666 /**
03667   * @brief DMA UART transmit process complete callback.
03668   * @param hdma DMA handle.
03669   * @retval None
03670   */
03671 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
03672 {
03673   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03674
03675   /* DMA Normal mode */
03676   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
03677   {
03678     huart->TxXferCount = 0U;
03679
03680     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
03681        in the UART CR3 register */
03682     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
03683
03684     /* Enable the UART Transmit Complete Interrupt */
03685     ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03686   }
03687   /* DMA Circular mode */
03688   else
03689   {
03690 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03691     /*Call registered Tx complete callback*/
03692     huart->TxCpltCallback(huart);
03693 #else
03694     /*Call legacy weak Tx complete callback*/
03695     HAL_UART_TxCpltCallback(huart);
03696 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03697   }
03698 }
03699
03700 /**
03701   * @brief DMA UART transmit process half complete callback.
03702   * @param hdma DMA handle.
03703   * @retval None
03704   */
03705 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
03706 {
03707   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03708
03709 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03710   /*Call registered Tx Half complete callback*/
03711   huart->TxHalfCpltCallback(huart);
03712 #else
03713   /*Call legacy weak Tx Half complete callback*/
03714   HAL_UART_TxHalfCpltCallback(huart);
03715 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03716 }
03717
03718 /**
03719   * @brief DMA UART receive process complete callback.
03720   * @param hdma DMA handle.
03721   * @retval None
03722   */
03723 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
03724 {
03725   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03726
03727   /* DMA Normal mode */
03728   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
03729   {
03730     huart->RxXferCount = 0U;
03731
03732     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
03733     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03734     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03735
03736     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
03737        in the UART CR3 register */
03738     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
03739
03740     /* At end of Rx process, restore huart->RxState to Ready */
03741     huart->RxState = HAL_UART_STATE_READY;
03742
03743     /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
03744     if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
03745     {
03746       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
03747     }
03748   }
03749
03750   /* Initialize type of RxEvent that correspond to RxEvent callback execution;
03751      In this case, Rx Event type is Transfer Complete */
03752   huart->RxEventType = HAL_UART_RXEVENT_TC;
03753
03754   /* Check current reception Mode :
03755      If Reception till IDLE event has been selected : use Rx Event callback */
03756   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
03757   {
03758 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03759     /*Call registered Rx Event callback*/
03760     huart->RxEventCallback(huart, huart->RxXferSize);
03761 #else
03762     /*Call legacy weak Rx Event callback*/
03763     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
03764 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03765   }
03766   else
03767   {
03768     /* In other cases : use Rx Complete callback */
03769 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03770     /*Call registered Rx complete callback*/
03771     huart->RxCpltCallback(huart);
03772 #else
03773     /*Call legacy weak Rx complete callback*/
03774     HAL_UART_RxCpltCallback(huart);
03775 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03776   }
03777 }
03778
03779 /**
03780   * @brief DMA UART receive process half complete callback.
03781   * @param hdma DMA handle.
03782   * @retval None
03783   */
03784 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
03785 {
03786   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03787
03788   /* Initialize type of RxEvent that correspond to RxEvent callback execution;
03789      In this case, Rx Event type is Half Transfer */
03790   huart->RxEventType = HAL_UART_RXEVENT_HT;
03791
03792   /* Check current reception Mode :
03793      If Reception till IDLE event has been selected : use Rx Event callback */
03794   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
03795   {
03796 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03797     /*Call registered Rx Event callback*/
03798     huart->RxEventCallback(huart, huart->RxXferSize / 2U);
03799 #else
03800     /*Call legacy weak Rx Event callback*/
03801     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
03802 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03803   }
03804   else
03805   {
03806     /* In other cases : use Rx Half Complete callback */
03807 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03808     /*Call registered Rx Half complete callback*/
03809     huart->RxHalfCpltCallback(huart);
03810 #else
03811     /*Call legacy weak Rx Half complete callback*/
03812     HAL_UART_RxHalfCpltCallback(huart);
03813 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03814   }
03815 }
03816
03817 /**
03818   * @brief DMA UART communication error callback.
03819   * @param hdma DMA handle.
03820   * @retval None
03821   */
03822 static void UART_DMAError(DMA_HandleTypeDef *hdma)
03823 {
03824   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03825
03826   const HAL_UART_StateTypeDef gstate = huart->gState;
03827   const HAL_UART_StateTypeDef rxstate = huart->RxState;
03828
03829   /* Stop UART DMA Tx request if ongoing */
03830   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
03831       (gstate == HAL_UART_STATE_BUSY_TX))
03832   {
03833     huart->TxXferCount = 0U;
03834     UART_EndTxTransfer(huart);
03835   }
03836
03837   /* Stop UART DMA Rx request if ongoing */
03838   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
03839       (rxstate == HAL_UART_STATE_BUSY_RX))
03840   {
03841     huart->RxXferCount = 0U;
03842     UART_EndRxTransfer(huart);
03843   }
03844
03845   huart->ErrorCode |= HAL_UART_ERROR_DMA;
03846
03847 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03848   /*Call registered error callback*/
03849   huart->ErrorCallback(huart);
03850 #else
03851   /*Call legacy weak error callback*/
03852   HAL_UART_ErrorCallback(huart);
03853 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03854 }
03855
03856 /**
03857   * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
03858   *         (To be called at end of DMA Abort procedure following error occurrence).
03859   * @param  hdma DMA handle.
03860   * @retval None
03861   */
03862 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
03863 {
03864   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03865   huart->RxXferCount = 0U;
03866   huart->TxXferCount = 0U;
03867
03868 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03869   /*Call registered error callback*/
03870   huart->ErrorCallback(huart);
03871 #else
03872   /*Call legacy weak error callback*/
03873   HAL_UART_ErrorCallback(huart);
03874 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03875 }
03876
03877 /**
03878   * @brief  DMA UART Tx communication abort callback, when initiated by user
03879   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03880   * @note   When this callback is executed, User Abort complete call back is called only if no
03881   *         Abort still ongoing for Rx DMA Handle.
03882   * @param  hdma DMA handle.
03883   * @retval None
03884   */
03885 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03886 {
03887   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03888
03889   huart->hdmatx->XferAbortCallback = NULL;
03890
03891   /* Check if an Abort process is still ongoing */
03892   if (huart->hdmarx != NULL)
03893   {
03894     if (huart->hdmarx->XferAbortCallback != NULL)
03895     {
03896       return;
03897     }
03898   }
03899
03900   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
03901   huart->TxXferCount = 0U;
03902   huart->RxXferCount = 0U;
03903
03904   /* Reset errorCode */
03905   huart->ErrorCode = HAL_UART_ERROR_NONE;
03906
03907   /* Clear the Error flags in the ICR register */
03908   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03909
03910   /* Flush the whole TX FIFO (if needed) */
03911   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
03912   {
03913     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
03914   }
03915
03916   /* Restore huart->gState and huart->RxState to Ready */
03917   huart->gState  = HAL_UART_STATE_READY;
03918   huart->RxState = HAL_UART_STATE_READY;
03919   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03920
03921   /* Call user Abort complete callback */
03922 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03923   /* Call registered Abort complete callback */
03924   huart->AbortCpltCallback(huart);
03925 #else
03926   /* Call legacy weak Abort complete callback */
03927   HAL_UART_AbortCpltCallback(huart);
03928 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03929 }
03930
03931
03932 /**
03933   * @brief  DMA UART Rx communication abort callback, when initiated by user
03934   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03935   * @note   When this callback is executed, User Abort complete call back is called only if no
03936   *         Abort still ongoing for Tx DMA Handle.
03937   * @param  hdma DMA handle.
03938   * @retval None
03939   */
03940 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03941 {
03942   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03943
03944   huart->hdmarx->XferAbortCallback = NULL;
03945
03946   /* Check if an Abort process is still ongoing */
03947   if (huart->hdmatx != NULL)
03948   {
03949     if (huart->hdmatx->XferAbortCallback != NULL)
03950     {
03951       return;
03952     }
03953   }
03954
03955   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
03956   huart->TxXferCount = 0U;
03957   huart->RxXferCount = 0U;
03958
03959   /* Reset errorCode */
03960   huart->ErrorCode = HAL_UART_ERROR_NONE;
03961
03962   /* Clear the Error flags in the ICR register */
03963   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03964
03965   /* Discard the received data */
03966   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03967
03968   /* Restore huart->gState and huart->RxState to Ready */
03969   huart->gState  = HAL_UART_STATE_READY;
03970   huart->RxState = HAL_UART_STATE_READY;
03971   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
03972
03973   /* Call user Abort complete callback */
03974 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03975   /* Call registered Abort complete callback */
03976   huart->AbortCpltCallback(huart);
03977 #else
03978   /* Call legacy weak Abort complete callback */
03979   HAL_UART_AbortCpltCallback(huart);
03980 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03981 }
03982
03983
03984 /**
03985   * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
03986   *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
03987   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
03988   *         and leads to user Tx Abort Complete callback execution).
03989   * @param  hdma DMA handle.
03990   * @retval None
03991   */
03992 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
03993 {
03994   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03995
03996   huart->TxXferCount = 0U;
03997
03998   /* Flush the whole TX FIFO (if needed) */
03999   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
04000   {
04001     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
04002   }
04003
04004   /* Restore huart->gState to Ready */
04005   huart->gState = HAL_UART_STATE_READY;
04006
04007   /* Call user Abort complete callback */
04008 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04009   /* Call registered Abort Transmit Complete Callback */
04010   huart->AbortTransmitCpltCallback(huart);
04011 #else
04012   /* Call legacy weak Abort Transmit Complete Callback */
04013   HAL_UART_AbortTransmitCpltCallback(huart);
04014 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04015 }
04016
04017 /**
04018   * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
04019   *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
04020   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
04021   *         and leads to user Rx Abort Complete callback execution).
04022   * @param  hdma DMA handle.
04023   * @retval None
04024   */
04025 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
04026 {
04027   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
04028
04029   huart->RxXferCount = 0U;
04030
04031   /* Clear the Error flags in the ICR register */
04032   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
04033
04034   /* Discard the received data */
04035   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04036
04037   /* Restore huart->RxState to Ready */
04038   huart->RxState = HAL_UART_STATE_READY;
04039   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04040
04041   /* Call user Abort complete callback */
04042 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04043   /* Call registered Abort Receive Complete Callback */
04044   huart->AbortReceiveCpltCallback(huart);
04045 #else
04046   /* Call legacy weak Abort Receive Complete Callback */
04047   HAL_UART_AbortReceiveCpltCallback(huart);
04048 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04049 }
04050
04051 /**
04052   * @brief TX interrupt handler for 7 or 8 bits data word length .
04053   * @note   Function is called under interruption only, once
04054   *         interruptions have been enabled by HAL_UART_Transmit_IT().
04055   * @param huart UART handle.
04056   * @retval None
04057   */
04058 static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
04059 {
04060   /* Check that a Tx process is ongoing */
04061   if (huart->gState == HAL_UART_STATE_BUSY_TX)
04062   {
04063     if (huart->TxXferCount == 0U)
04064     {
04065       /* Disable the UART Transmit Data Register Empty Interrupt */
04066       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
04067
04068       /* Enable the UART Transmit Complete Interrupt */
04069       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04070     }
04071     else
04072     {
04073       huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
04074       huart->pTxBuffPtr++;
04075       huart->TxXferCount--;
04076     }
04077   }
04078 }
04079
04080 /**
04081   * @brief TX interrupt handler for 9 bits data word length.
04082   * @note   Function is called under interruption only, once
04083   *         interruptions have been enabled by HAL_UART_Transmit_IT().
04084   * @param huart UART handle.
04085   * @retval None
04086   */
04087 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
04088 {
04089   const uint16_t *tmp;
04090
04091   /* Check that a Tx process is ongoing */
04092   if (huart->gState == HAL_UART_STATE_BUSY_TX)
04093   {
04094     if (huart->TxXferCount == 0U)
04095     {
04096       /* Disable the UART Transmit Data Register Empty Interrupt */
04097       ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
04098
04099       /* Enable the UART Transmit Complete Interrupt */
04100       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04101     }
04102     else
04103     {
04104       tmp = (const uint16_t *) huart->pTxBuffPtr;
04105       huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
04106       huart->pTxBuffPtr += 2U;
04107       huart->TxXferCount--;
04108     }
04109   }
04110 }
04111
04112 /**
04113   * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
04114   * @note   Function is called under interruption only, once
04115   *         interruptions have been enabled by HAL_UART_Transmit_IT().
04116   * @param huart UART handle.
04117   * @retval None
04118   */
04119 static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
04120 {
04121   uint16_t  nb_tx_data;
04122
04123   /* Check that a Tx process is ongoing */
04124   if (huart->gState == HAL_UART_STATE_BUSY_TX)
04125   {
04126     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
04127     {
04128       if (huart->TxXferCount == 0U)
04129       {
04130         /* Disable the TX FIFO threshold interrupt */
04131         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
04132
04133         /* Enable the UART Transmit Complete Interrupt */
04134         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04135
04136         break; /* force exit loop */
04137       }
04138       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
04139       {
04140         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
04141         huart->pTxBuffPtr++;
04142         huart->TxXferCount--;
04143       }
04144       else
04145       {
04146         /* Nothing to do */
04147       }
04148     }
04149   }
04150 }
04151
04152 /**
04153   * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
04154   * @note   Function is called under interruption only, once
04155   *         interruptions have been enabled by HAL_UART_Transmit_IT().
04156   * @param huart UART handle.
04157   * @retval None
04158   */
04159 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
04160 {
04161   const uint16_t *tmp;
04162   uint16_t  nb_tx_data;
04163
04164   /* Check that a Tx process is ongoing */
04165   if (huart->gState == HAL_UART_STATE_BUSY_TX)
04166   {
04167     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
04168     {
04169       if (huart->TxXferCount == 0U)
04170       {
04171         /* Disable the TX FIFO threshold interrupt */
04172         ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
04173
04174         /* Enable the UART Transmit Complete Interrupt */
04175         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04176
04177         break; /* force exit loop */
04178       }
04179       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
04180       {
04181         tmp = (const uint16_t *) huart->pTxBuffPtr;
04182         huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
04183         huart->pTxBuffPtr += 2U;
04184         huart->TxXferCount--;
04185       }
04186       else
04187       {
04188         /* Nothing to do */
04189       }
04190     }
04191   }
04192 }
04193
04194 /**
04195   * @brief  Wrap up transmission in non-blocking mode.
04196   * @param  huart pointer to a UART_HandleTypeDef structure that contains
04197   *                the configuration information for the specified UART module.
04198   * @retval None
04199   */
04200 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
04201 {
04202   /* Disable the UART Transmit Complete Interrupt */
04203   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
04204
04205   /* Tx process is ended, restore huart->gState to Ready */
04206   huart->gState = HAL_UART_STATE_READY;
04207
04208   /* Cleat TxISR function pointer */
04209   huart->TxISR = NULL;
04210
04211 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04212   /*Call registered Tx complete callback*/
04213   huart->TxCpltCallback(huart);
04214 #else
04215   /*Call legacy weak Tx complete callback*/
04216   HAL_UART_TxCpltCallback(huart);
04217 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04218 }
04219
04220 /**
04221   * @brief RX interrupt handler for 7 or 8 bits data word length .
04222   * @param huart UART handle.
04223   * @retval None
04224   */
04225 static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
04226 {
04227   uint16_t uhMask = huart->Mask;
04228   uint16_t  uhdata;
04229
04230   /* Check that a Rx process is ongoing */
04231   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04232   {
04233     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04234     *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
04235     huart->pRxBuffPtr++;
04236     huart->RxXferCount--;
04237
04238     if (huart->RxXferCount == 0U)
04239     {
04240       /* Disable the UART Parity Error Interrupt and RXNE interrupts */
04241       ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
04242
04243       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
04244       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
04245
04246       /* Rx process is completed, restore huart->RxState to Ready */
04247       huart->RxState = HAL_UART_STATE_READY;
04248
04249       /* Clear RxISR function pointer */
04250       huart->RxISR = NULL;
04251
04252       /* Initialize type of RxEvent to Transfer Complete */
04253       huart->RxEventType = HAL_UART_RXEVENT_TC;
04254
04255       /* Check current reception Mode :
04256          If Reception till IDLE event has been selected : */
04257       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
04258       {
04259         /* Set reception type to Standard */
04260         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04261
04262         /* Disable IDLE interrupt */
04263         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
04264
04265         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
04266         {
04267           /* Clear IDLE Flag */
04268           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
04269         }
04270
04271 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04272         /*Call registered Rx Event callback*/
04273         huart->RxEventCallback(huart, huart->RxXferSize);
04274 #else
04275         /*Call legacy weak Rx Event callback*/
04276         HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
04277 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
04278       }
04279       else
04280       {
04281         /* Standard reception API called */
04282 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04283         /*Call registered Rx complete callback*/
04284         huart->RxCpltCallback(huart);
04285 #else
04286         /*Call legacy weak Rx complete callback*/
04287         HAL_UART_RxCpltCallback(huart);
04288 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04289       }
04290     }
04291   }
04292   else
04293   {
04294     /* Clear RXNE interrupt flag */
04295     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04296   }
04297 }
04298
04299 /**
04300   * @brief RX interrupt handler for 9 bits data word length .
04301   * @note   Function is called under interruption only, once
04302   *         interruptions have been enabled by HAL_UART_Receive_IT()
04303   * @param huart UART handle.
04304   * @retval None
04305   */
04306 static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
04307 {
04308   uint16_t *tmp;
04309   uint16_t uhMask = huart->Mask;
04310   uint16_t  uhdata;
04311
04312   /* Check that a Rx process is ongoing */
04313   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04314   {
04315     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04316     tmp = (uint16_t *) huart->pRxBuffPtr ;
04317     *tmp = (uint16_t)(uhdata & uhMask);
04318     huart->pRxBuffPtr += 2U;
04319     huart->RxXferCount--;
04320
04321     if (huart->RxXferCount == 0U)
04322     {
04323       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
04324       ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
04325
04326       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
04327       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
04328
04329       /* Rx process is completed, restore huart->RxState to Ready */
04330       huart->RxState = HAL_UART_STATE_READY;
04331
04332       /* Clear RxISR function pointer */
04333       huart->RxISR = NULL;
04334
04335       /* Initialize type of RxEvent to Transfer Complete */
04336       huart->RxEventType = HAL_UART_RXEVENT_TC;
04337
04338       /* Check current reception Mode :
04339          If Reception till IDLE event has been selected : */
04340       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
04341       {
04342         /* Set reception type to Standard */
04343         huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04344
04345         /* Disable IDLE interrupt */
04346         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
04347
04348         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
04349         {
04350           /* Clear IDLE Flag */
04351           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
04352         }
04353
04354 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04355         /*Call registered Rx Event callback*/
04356         huart->RxEventCallback(huart, huart->RxXferSize);
04357 #else
04358         /*Call legacy weak Rx Event callback*/
04359         HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
04360 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
04361       }
04362       else
04363       {
04364         /* Standard reception API called */
04365 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04366         /*Call registered Rx complete callback*/
04367         huart->RxCpltCallback(huart);
04368 #else
04369         /*Call legacy weak Rx complete callback*/
04370         HAL_UART_RxCpltCallback(huart);
04371 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04372       }
04373     }
04374   }
04375   else
04376   {
04377     /* Clear RXNE interrupt flag */
04378     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04379   }
04380 }
04381
04382 /**
04383   * @brief RX interrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
04384   * @note   Function is called under interruption only, once
04385   *         interruptions have been enabled by HAL_UART_Receive_IT()
04386   * @param huart UART handle.
04387   * @retval None
04388   */
04389 static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
04390 {
04391   uint16_t  uhMask = huart->Mask;
04392   uint16_t  uhdata;
04393   uint16_t  nb_rx_data;
04394   uint16_t  rxdatacount;
04395   uint32_t  isrflags = READ_REG(huart->Instance->ISR);
04396   uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
04397   uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
04398
04399   /* Check that a Rx process is ongoing */
04400   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04401   {
04402     nb_rx_data = huart->NbRxDataToProcess;
04403     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
04404     {
04405       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04406       *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
04407       huart->pRxBuffPtr++;
04408       huart->RxXferCount--;
04409       isrflags = READ_REG(huart->Instance->ISR);
04410
04411       /* If some non blocking errors occurred */
04412       if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
04413       {
04414         /* UART parity error interrupt occurred -------------------------------------*/
04415         if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
04416         {
04417           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
04418
04419           huart->ErrorCode |= HAL_UART_ERROR_PE;
04420         }
04421
04422         /* UART frame error interrupt occurred --------------------------------------*/
04423         if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
04424         {
04425           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
04426
04427           huart->ErrorCode |= HAL_UART_ERROR_FE;
04428         }
04429
04430         /* UART noise error interrupt occurred --------------------------------------*/
04431         if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
04432         {
04433           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
04434
04435           huart->ErrorCode |= HAL_UART_ERROR_NE;
04436         }
04437
04438         /* Call UART Error Call back function if need be ----------------------------*/
04439         if (huart->ErrorCode != HAL_UART_ERROR_NONE)
04440         {
04441           /* Non Blocking error : transfer could go on.
04442           Error is notified to user through user error callback */
04443 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04444           /*Call registered error callback*/
04445           huart->ErrorCallback(huart);
04446 #else
04447           /*Call legacy weak error callback*/
04448           HAL_UART_ErrorCallback(huart);
04449 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04450           huart->ErrorCode = HAL_UART_ERROR_NONE;
04451         }
04452       }
04453
04454       if (huart->RxXferCount == 0U)
04455       {
04456         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
04457         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
04458
04459         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
04460            and RX FIFO Threshold interrupt */
04461         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
04462
04463         /* Rx process is completed, restore huart->RxState to Ready */
04464         huart->RxState = HAL_UART_STATE_READY;
04465
04466         /* Clear RxISR function pointer */
04467         huart->RxISR = NULL;
04468
04469         /* Initialize type of RxEvent to Transfer Complete */
04470         huart->RxEventType = HAL_UART_RXEVENT_TC;
04471
04472         /* Check current reception Mode :
04473            If Reception till IDLE event has been selected : */
04474         if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
04475         {
04476           /* Set reception type to Standard */
04477           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04478
04479           /* Disable IDLE interrupt */
04480           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
04481
04482           if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
04483           {
04484             /* Clear IDLE Flag */
04485             __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
04486           }
04487
04488 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04489           /*Call registered Rx Event callback*/
04490           huart->RxEventCallback(huart, huart->RxXferSize);
04491 #else
04492           /*Call legacy weak Rx Event callback*/
04493           HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
04494 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
04495         }
04496         else
04497         {
04498           /* Standard reception API called */
04499 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04500           /*Call registered Rx complete callback*/
04501           huart->RxCpltCallback(huart);
04502 #else
04503           /*Call legacy weak Rx complete callback*/
04504           HAL_UART_RxCpltCallback(huart);
04505 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04506         }
04507       }
04508     }
04509
04510     /* When remaining number of bytes to receive is less than the RX FIFO
04511     threshold, next incoming frames are processed as if FIFO mode was
04512     disabled (i.e. one interrupt per received frame).
04513     */
04514     rxdatacount = huart->RxXferCount;
04515     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
04516     {
04517       /* Disable the UART RXFT interrupt*/
04518       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
04519
04520       /* Update the RxISR function pointer */
04521       huart->RxISR = UART_RxISR_8BIT;
04522
04523       /* Enable the UART Data Register Not Empty interrupt */
04524       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
04525     }
04526   }
04527   else
04528   {
04529     /* Clear RXNE interrupt flag */
04530     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04531   }
04532 }
04533
04534 /**
04535   * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
04536   * @note   Function is called under interruption only, once
04537   *         interruptions have been enabled by HAL_UART_Receive_IT()
04538   * @param huart UART handle.
04539   * @retval None
04540   */
04541 static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
04542 {
04543   uint16_t *tmp;
04544   uint16_t  uhMask = huart->Mask;
04545   uint16_t  uhdata;
04546   uint16_t  nb_rx_data;
04547   uint16_t  rxdatacount;
04548   uint32_t  isrflags = READ_REG(huart->Instance->ISR);
04549   uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
04550   uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
04551
04552   /* Check that a Rx process is ongoing */
04553   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04554   {
04555     nb_rx_data = huart->NbRxDataToProcess;
04556     while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
04557     {
04558       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04559       tmp = (uint16_t *) huart->pRxBuffPtr ;
04560       *tmp = (uint16_t)(uhdata & uhMask);
04561       huart->pRxBuffPtr += 2U;
04562       huart->RxXferCount--;
04563       isrflags = READ_REG(huart->Instance->ISR);
04564
04565       /* If some non blocking errors occurred */
04566       if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
04567       {
04568         /* UART parity error interrupt occurred -------------------------------------*/
04569         if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
04570         {
04571           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
04572
04573           huart->ErrorCode |= HAL_UART_ERROR_PE;
04574         }
04575
04576         /* UART frame error interrupt occurred --------------------------------------*/
04577         if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
04578         {
04579           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
04580
04581           huart->ErrorCode |= HAL_UART_ERROR_FE;
04582         }
04583
04584         /* UART noise error interrupt occurred --------------------------------------*/
04585         if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
04586         {
04587           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
04588
04589           huart->ErrorCode |= HAL_UART_ERROR_NE;
04590         }
04591
04592         /* Call UART Error Call back function if need be ----------------------------*/
04593         if (huart->ErrorCode != HAL_UART_ERROR_NONE)
04594         {
04595           /* Non Blocking error : transfer could go on.
04596           Error is notified to user through user error callback */
04597 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04598           /*Call registered error callback*/
04599           huart->ErrorCallback(huart);
04600 #else
04601           /*Call legacy weak error callback*/
04602           HAL_UART_ErrorCallback(huart);
04603 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04604           huart->ErrorCode = HAL_UART_ERROR_NONE;
04605         }
04606       }
04607
04608       if (huart->RxXferCount == 0U)
04609       {
04610         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
04611         ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
04612
04613         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
04614            and RX FIFO Threshold interrupt */
04615         ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
04616
04617         /* Rx process is completed, restore huart->RxState to Ready */
04618         huart->RxState = HAL_UART_STATE_READY;
04619
04620         /* Clear RxISR function pointer */
04621         huart->RxISR = NULL;
04622
04623         /* Initialize type of RxEvent to Transfer Complete */
04624         huart->RxEventType = HAL_UART_RXEVENT_TC;
04625
04626         /* Check current reception Mode :
04627            If Reception till IDLE event has been selected : */
04628         if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
04629         {
04630           /* Set reception type to Standard */
04631           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
04632
04633           /* Disable IDLE interrupt */
04634           ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
04635
04636           if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
04637           {
04638             /* Clear IDLE Flag */
04639             __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
04640           }
04641
04642 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04643           /*Call registered Rx Event callback*/
04644           huart->RxEventCallback(huart, huart->RxXferSize);
04645 #else
04646           /*Call legacy weak Rx Event callback*/
04647           HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
04648 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
04649         }
04650         else
04651         {
04652           /* Standard reception API called */
04653 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04654           /*Call registered Rx complete callback*/
04655           huart->RxCpltCallback(huart);
04656 #else
04657           /*Call legacy weak Rx complete callback*/
04658           HAL_UART_RxCpltCallback(huart);
04659 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04660         }
04661       }
04662     }
04663
04664     /* When remaining number of bytes to receive is less than the RX FIFO
04665     threshold, next incoming frames are processed as if FIFO mode was
04666     disabled (i.e. one interrupt per received frame).
04667     */
04668     rxdatacount = huart->RxXferCount;
04669     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
04670     {
04671       /* Disable the UART RXFT interrupt*/
04672       ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
04673
04674       /* Update the RxISR function pointer */
04675       huart->RxISR = UART_RxISR_16BIT;
04676
04677       /* Enable the UART Data Register Not Empty interrupt */
04678       ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
04679     }
04680   }
04681   else
04682   {
04683     /* Clear RXNE interrupt flag */
04684     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04685   }
04686 }
04687
04688 /**
04689   * @}
04690   */
04691
04692 #endif /* HAL_UART_MODULE_ENABLED */
04693 /**
04694   * @}
04695   */
04696
04697 /**
04698   * @}
04699   */
04700
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_uart.h Source File

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stm32g0xx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_UART_H
00021 #define STM32G0xx_HAL_UART_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup UART
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup UART_Exported_Types UART Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief UART Init Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t BaudRate;                /*!< This member configures the UART communication baud rate.
00049                                          The baud rate register is computed using the following formula:
00050                                          LPUART:
00051                                          =======
00052                                          Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
00053                                          where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
00054                                          UART:
00055                                          =====
00056                                          - If oversampling is 16 or in LIN mode,
00057                                             Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
00058                                          - If oversampling is 8,
00059                                             Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
00060                                             ((huart->Init.BaudRate)))[15:4]
00061                                             Baud Rate Register[3] =  0
00062                                             Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) /
00063                                             ((huart->Init.BaudRate)))[3:0]) >> 1
00064                                          where uart_ker_ck_pres is the UART input clock divided by a prescaler */
00065
00066   uint32_t WordLength;              /*!< Specifies the number of data bits transmitted or received in a frame.
00067                                          This parameter can be a value of @ref UARTEx_Word_Length. */
00068
00069   uint32_t StopBits;                /*!< Specifies the number of stop bits transmitted.
00070                                          This parameter can be a value of @ref UART_Stop_Bits. */
00071
00072   uint32_t Parity;                  /*!< Specifies the parity mode.
00073                                          This parameter can be a value of @ref UART_Parity
00074                                          @note When parity is enabled, the computed parity is inserted
00075                                                at the MSB position of the transmitted data (9th bit when
00076                                                the word length is set to 9 data bits; 8th bit when the
00077                                                word length is set to 8 data bits). */
00078
00079   uint32_t Mode;                    /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00080                                          This parameter can be a value of @ref UART_Mode. */
00081
00082   uint32_t HwFlowCtl;               /*!< Specifies whether the hardware flow control mode is enabled
00083                                          or disabled.
00084                                          This parameter can be a value of @ref UART_Hardware_Flow_Control. */
00085
00086   uint32_t OverSampling;            /*!< Specifies whether the Over sampling 8 is enabled or disabled,
00087                                          to achieve higher speed (up to f_PCLK/8).
00088                                          This parameter can be a value of @ref UART_Over_Sampling. */
00089
00090   uint32_t OneBitSampling;          /*!< Specifies whether a single sample or three samples' majority vote is selected.
00091                                          Selecting the single sample method increases the receiver tolerance to clock
00092                                          deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
00093
00094   uint32_t ClockPrescaler;          /*!< Specifies the prescaler value used to divide the UART clock source.
00095                                          This parameter can be a value of @ref UART_ClockPrescaler. */
00096
00097 } UART_InitTypeDef;
00098
00099 /**
00100   * @brief  UART Advanced Features initialization structure definition
00101   */
00102 typedef struct
00103 {
00104   uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
00105                                        Advanced Features may be initialized at the same time .
00106                                        This parameter can be a value of
00107                                        @ref UART_Advanced_Features_Initialization_Type. */
00108
00109   uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
00110                                        This parameter can be a value of @ref UART_Tx_Inv. */
00111
00112   uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
00113                                        This parameter can be a value of @ref UART_Rx_Inv. */
00114
00115   uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
00116                                        vs negative/inverted logic).
00117                                        This parameter can be a value of @ref UART_Data_Inv. */
00118
00119   uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
00120                                        This parameter can be a value of @ref UART_Rx_Tx_Swap. */
00121
00122   uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
00123                                        This parameter can be a value of @ref UART_Overrun_Disable. */
00124
00125   uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
00126                                        This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
00127
00128   uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
00129                                        This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
00130
00131   uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
00132                                        detection is carried out.
00133                                        This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
00134
00135   uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
00136                                        This parameter can be a value of @ref UART_MSB_First. */
00137 } UART_AdvFeatureInitTypeDef;
00138
00139 /**
00140   * @brief HAL UART State definition
00141   * @note  HAL UART State value is a combination of 2 different substates:
00142   *        gState and RxState (see @ref UART_State_Definition).
00143   *        - gState contains UART state information related to global Handle management
00144   *          and also information related to Tx operations.
00145   *          gState value coding follow below described bitmap :
00146   *          b7-b6  Error information
00147   *             00 : No Error
00148   *             01 : (Not Used)
00149   *             10 : Timeout
00150   *             11 : Error
00151   *          b5     Peripheral initialization status
00152   *             0  : Reset (Peripheral not initialized)
00153   *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
00154   *          b4-b3  (not used)
00155   *             xx : Should be set to 00
00156   *          b2     Intrinsic process state
00157   *             0  : Ready
00158   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00159   *          b1     (not used)
00160   *             x  : Should be set to 0
00161   *          b0     Tx state
00162   *             0  : Ready (no Tx operation ongoing)
00163   *             1  : Busy (Tx operation ongoing)
00164   *        - RxState contains information related to Rx operations.
00165   *          RxState value coding follow below described bitmap :
00166   *          b7-b6  (not used)
00167   *             xx : Should be set to 00
00168   *          b5     Peripheral initialization status
00169   *             0  : Reset (Peripheral not initialized)
00170   *             1  : Init done (Peripheral initialized)
00171   *          b4-b2  (not used)
00172   *            xxx : Should be set to 000
00173   *          b1     Rx state
00174   *             0  : Ready (no Rx operation ongoing)
00175   *             1  : Busy (Rx operation ongoing)
00176   *          b0     (not used)
00177   *             x  : Should be set to 0.
00178   */
00179 typedef uint32_t HAL_UART_StateTypeDef;
00180
00181 /**
00182   * @brief UART clock sources definition
00183   */
00184 typedef enum
00185 {
00186   UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */
00187   UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */
00188   UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */
00189   UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00190   UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00191 } UART_ClockSourceTypeDef;
00192
00193 /**
00194   * @brief HAL UART Reception type definition
00195   * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
00196   *        This parameter can be a value of @ref UART_Reception_Type_Values :
00197   *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
00198   *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
00199   *           HAL_UART_RECEPTION_TORTO            = 0x02U,
00200   *           HAL_UART_RECEPTION_TOCHARMATCH      = 0x03U,
00201   */
00202 typedef uint32_t HAL_UART_RxTypeTypeDef;
00203
00204 /**
00205   * @brief HAL UART Rx Event type definition
00206   * @note  HAL UART Rx Event type value aims to identify which type of Event has occurred
00207   *        leading to call of the RxEvent callback.
00208   *        This parameter can be a value of @ref UART_RxEvent_Type_Values :
00209   *           HAL_UART_RXEVENT_TC                 = 0x00U,
00210   *           HAL_UART_RXEVENT_HT                 = 0x01U,
00211   *           HAL_UART_RXEVENT_IDLE               = 0x02U,
00212   */
00213 typedef uint32_t HAL_UART_RxEventTypeTypeDef;
00214
00215 /**
00216   * @brief  UART handle Structure definition
00217   */
00218 typedef struct __UART_HandleTypeDef
00219 {
00220   USART_TypeDef            *Instance;                /*!< UART registers base address        */
00221
00222   UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
00223
00224   UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
00225
00226   const uint8_t            *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
00227
00228   uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
00229
00230   __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
00231
00232   uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
00233
00234   uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
00235
00236   __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
00237
00238   uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
00239
00240   uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
00241                                                           This parameter can be a value of @ref UARTEx_FIFO_mode. */
00242
00243   uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
00244
00245   uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
00246
00247   __IO HAL_UART_RxTypeTypeDef ReceptionType;         /*!< Type of ongoing reception          */
00248
00249   __IO HAL_UART_RxEventTypeTypeDef RxEventType;      /*!< Type of Rx Event                   */
00250
00251   void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
00252
00253   void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
00254
00255   DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
00256
00257   DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
00258
00259   HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
00260
00261   __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
00262                                                           and also related to Tx operations. This parameter
00263                                                           can be a value of @ref HAL_UART_StateTypeDef */
00264
00265   __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations. This
00266                                                           parameter can be a value of @ref HAL_UART_StateTypeDef */
00267
00268   __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
00269
00270 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00271   void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
00272   void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
00273   void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
00274   void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
00275   void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
00276   void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
00277   void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
00278   void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
00279   void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
00280   void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
00281   void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
00282   void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
00283
00284   void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
00285   void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
00286 #endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
00287
00288 } UART_HandleTypeDef;
00289
00290 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00291 /**
00292   * @brief  HAL UART Callback ID enumeration definition
00293   */
00294 typedef enum
00295 {
00296   HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
00297   HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
00298   HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
00299   HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
00300   HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
00301   HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
00302   HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
00303   HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
00304   HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
00305   HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
00306   HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
00307
00308   HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
00309   HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
00310
00311 } HAL_UART_CallbackIDTypeDef;
00312
00313 /**
00314   * @brief  HAL UART Callback pointer definition
00315   */
00316 typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
00317 typedef  void (*pUART_RxEventCallbackTypeDef)
00318 (struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
00319
00320 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00321
00322 /**
00323   * @}
00324   */
00325
00326 /* Exported constants --------------------------------------------------------*/
00327 /** @defgroup UART_Exported_Constants UART Exported Constants
00328   * @{
00329   */
00330
00331 /** @defgroup UART_State_Definition UART State Code Definition
00332   * @{
00333   */
00334 #define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
00335                                                           Value is allowed for gState and RxState */
00336 #define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
00337                                                           Value is allowed for gState and RxState */
00338 #define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
00339                                                           Value is allowed for gState only */
00340 #define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
00341                                                           Value is allowed for gState only */
00342 #define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
00343                                                           Value is allowed for RxState only */
00344 #define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
00345                                                           Not to be used for neither gState nor RxState.Value is result
00346                                                           of combination (Or) between gState and RxState values */
00347 #define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
00348                                                           Value is allowed for gState only */
00349 #define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
00350                                                           Value is allowed for gState only */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup UART_Error_Definition   UART Error Definition
00356   * @{
00357   */
00358 #define  HAL_UART_ERROR_NONE             (0x00000000U)    /*!< No error                */
00359 #define  HAL_UART_ERROR_PE               (0x00000001U)    /*!< Parity error            */
00360 #define  HAL_UART_ERROR_NE               (0x00000002U)    /*!< Noise error             */
00361 #define  HAL_UART_ERROR_FE               (0x00000004U)    /*!< Frame error             */
00362 #define  HAL_UART_ERROR_ORE              (0x00000008U)    /*!< Overrun error           */
00363 #define  HAL_UART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error      */
00364 #define  HAL_UART_ERROR_RTO              (0x00000020U)    /*!< Receiver Timeout error  */
00365
00366 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00367 #define  HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error  */
00368 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
00374   * @{
00375   */
00376 #define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
00377 #define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
00378 #define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
00379 #define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup UART_Parity  UART Parity
00385   * @{
00386   */
00387 #define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
00388 #define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
00389 #define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00395   * @{
00396   */
00397 #define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
00398 #define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
00399 #define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
00400 #define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
00401 /**
00402   * @}
00403   */
00404
00405 /** @defgroup UART_Mode UART Transfer Mode
00406   * @{
00407   */
00408 #define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
00409 #define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
00410 #define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup UART_State  UART State
00416   * @{
00417   */
00418 #define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
00419 #define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup UART_Over_Sampling UART Over Sampling
00425   * @{
00426   */
00427 #define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
00428 #define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
00434   * @{
00435   */
00436 #define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
00437 #define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup UART_ClockPrescaler  UART Clock Prescaler
00443   * @{
00444   */
00445 #define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00446 #define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00447 #define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00448 #define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00449 #define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00450 #define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00451 #define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00452 #define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00453 #define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00454 #define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00455 #define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00456 #define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
00462   * @{
00463   */
00464 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection
00465                                                                               on start bit              */
00466 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection
00467                                                                               on falling edge           */
00468 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection
00469                                                                               on 0x7F frame detection   */
00470 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection
00471                                                                               on 0x55 frame detection   */
00472 /**
00473   * @}
00474   */
00475
00476 /** @defgroup UART_Receiver_Timeout UART Receiver Timeout
00477   * @{
00478   */
00479 #define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
00480 #define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
00481 /**
00482   * @}
00483   */
00484
00485 /** @defgroup UART_LIN    UART Local Interconnection Network mode
00486   * @{
00487   */
00488 #define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
00489 #define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
00495   * @{
00496   */
00497 #define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
00498 #define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup UART_DMA_Tx    UART DMA Tx
00504   * @{
00505   */
00506 #define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
00507 #define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
00508 /**
00509   * @}
00510   */
00511
00512 /** @defgroup UART_DMA_Rx   UART DMA Rx
00513   * @{
00514   */
00515 #define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
00516 #define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
00517 /**
00518   * @}
00519   */
00520
00521 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
00522   * @{
00523   */
00524 #define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
00525 #define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
00531   * @{
00532   */
00533 #define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
00534 #define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
00535 /**
00536   * @}
00537   */
00538
00539 /** @defgroup UART_Request_Parameters UART Request Parameters
00540   * @{
00541   */
00542 #define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
00543 #define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
00544 #define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
00545 #define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00546 #define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00547 /**
00548   * @}
00549   */
00550
00551 /** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
00552   * @{
00553   */
00554 #define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
00555 #define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
00556 #define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
00557 #define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
00558 #define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
00559 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
00560 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
00561 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
00562 #define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
00563 /**
00564   * @}
00565   */
00566
00567 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
00568   * @{
00569   */
00570 #define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
00571 #define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
00572 /**
00573   * @}
00574   */
00575
00576 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
00577   * @{
00578   */
00579 #define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
00580 #define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
00581 /**
00582   * @}
00583   */
00584
00585 /** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
00586   * @{
00587   */
00588 #define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
00589 #define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
00590 /**
00591   * @}
00592   */
00593
00594 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
00595   * @{
00596   */
00597 #define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
00598 #define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
00604   * @{
00605   */
00606 #define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
00607 #define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
00613   * @{
00614   */
00615 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
00616 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
00617 /**
00618   * @}
00619   */
00620
00621 /** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
00622   * @{
00623   */
00624 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
00625 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup UART_MSB_First   UART Advanced Feature MSB First
00631   * @{
00632   */
00633 #define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received
00634                                                                          first disable                      */
00635 #define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received
00636                                                                          first enable                       */
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
00642   * @{
00643   */
00644 #define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
00645 #define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
00646 /**
00647   * @}
00648   */
00649
00650 /** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
00651   * @{
00652   */
00653 #define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
00654 #define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
00655 /**
00656   * @}
00657   */
00658
00659 /** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
00660   * @{
00661   */
00662 #define UART_CR2_ADDRESS_LSB_POS             24U             /*!< UART address-matching LSB position in CR2 register */
00663 /**
00664   * @}
00665   */
00666
00667 /** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
00668   * @{
00669   */
00670 #define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                     */
00671 #define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                   */
00672 #define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register
00673                                                                          not empty or RXFIFO is not empty            */
00674 /**
00675   * @}
00676   */
00677
00678 /** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
00679   * @{
00680   */
00681 #define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
00682 #define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
00683 /**
00684   * @}
00685   */
00686
00687 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
00688   * @{
00689   */
00690 #define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB
00691                                                           position in CR1 register */
00692 /**
00693   * @}
00694   */
00695
00696 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
00697   * @{
00698   */
00699 #define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB
00700                                                           position in CR1 register */
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
00706   * @{
00707   */
00708 #define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
00709 /**
00710   * @}
00711   */
00712
00713 /** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
00714   * @{
00715   */
00716 #define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup UART_Flags     UART Status Flags
00722   *        Elements values convention: 0xXXXX
00723   *           - 0xXXXX  : Flag mask in the ISR register
00724   * @{
00725   */
00726 #define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
00727 #define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
00728 #define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
00729 #define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
00730 #define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
00731 #define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
00732 #define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
00733 #define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
00734 #define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
00735 #define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
00736 #define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
00737 #define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
00738 #define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
00739 #define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
00740 #define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
00741 #define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
00742 #define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
00743 #define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
00744 #define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
00745 #define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
00746 #define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
00747 #define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
00748 #define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
00749 #define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
00750 #define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
00751 #define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
00752 #define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
00753 /**
00754   * @}
00755   */
00756
00757 /** @defgroup UART_Interrupt_definition   UART Interrupts Definition
00758   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00759   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00760   *           - XX  : Interrupt source register (2bits)
00761   *                 - 01: CR1 register
00762   *                 - 10: CR2 register
00763   *                 - 11: CR3 register
00764   *           - ZZZZZ  : Flag position in the ISR register(5bits)
00765   *        Elements values convention: 000000000XXYYYYYb
00766   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00767   *           - XX  : Interrupt source register (2bits)
00768   *                 - 01: CR1 register
00769   *                 - 10: CR2 register
00770   *                 - 11: CR3 register
00771   *        Elements values convention: 0000ZZZZ00000000b
00772   *           - ZZZZ  : Flag position in the ISR register(4bits)
00773   * @{
00774   */
00775 #define UART_IT_PE                          0x0028U              /*!< UART parity error interruption                 */
00776 #define UART_IT_TXE                         0x0727U              /*!< UART transmit data register empty interruption */
00777 #define UART_IT_TXFNF                       0x0727U              /*!< UART TX FIFO not full interruption             */
00778 #define UART_IT_TC                          0x0626U              /*!< UART transmission complete interruption        */
00779 #define UART_IT_RXNE                        0x0525U              /*!< UART read data register not empty interruption */
00780 #define UART_IT_RXFNE                       0x0525U              /*!< UART RXFIFO not empty interruption             */
00781 #define UART_IT_IDLE                        0x0424U              /*!< UART idle interruption                         */
00782 #define UART_IT_LBD                         0x0846U              /*!< UART LIN break detection interruption          */
00783 #define UART_IT_CTS                         0x096AU              /*!< UART CTS interruption                          */
00784 #define UART_IT_CM                          0x112EU              /*!< UART character match interruption              */
00785 #define UART_IT_WUF                         0x1476U              /*!< UART wake-up from stop mode interruption       */
00786 #define UART_IT_RXFF                        0x183FU              /*!< UART RXFIFO full interruption                  */
00787 #define UART_IT_TXFE                        0x173EU              /*!< UART TXFIFO empty interruption                 */
00788 #define UART_IT_RXFT                        0x1A7CU              /*!< UART RXFIFO threshold reached interruption     */
00789 #define UART_IT_TXFT                        0x1B77U              /*!< UART TXFIFO threshold reached interruption     */
00790 #define UART_IT_RTO                         0x0B3AU              /*!< UART receiver timeout interruption             */
00791
00792 #define UART_IT_ERR                         0x0060U              /*!< UART error interruption                        */
00793
00794 #define UART_IT_ORE                         0x0300U              /*!< UART overrun error interruption                */
00795 #define UART_IT_NE                          0x0200U              /*!< UART noise error interruption                  */
00796 #define UART_IT_FE                          0x0100U              /*!< UART frame error interruption                  */
00797 /**
00798   * @}
00799   */
00800
00801 /** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
00802   * @{
00803   */
00804 #define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
00805 #define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
00806 #define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
00807 #define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
00808 #define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
00809 #define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
00810 #define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
00811 #define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
00812 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
00813 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
00814 #define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
00815 #define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
00816 /**
00817   * @}
00818   */
00819
00820 /** @defgroup UART_Reception_Type_Values  UART Reception type values
00821   * @{
00822   */
00823 #define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
00824 #define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
00825 #define HAL_UART_RECEPTION_TORTO             (0x00000002U)             /*!< Reception till completion or RTO event   */
00826 #define HAL_UART_RECEPTION_TOCHARMATCH       (0x00000003U)             /*!< Reception till completion or CM event    */
00827 /**
00828   * @}
00829   */
00830
00831 /** @defgroup UART_RxEvent_Type_Values  UART RxEvent type values
00832   * @{
00833   */
00834 #define HAL_UART_RXEVENT_TC                  (0x00000000U)             /*!< RxEvent linked to Transfer Complete event */
00835 #define HAL_UART_RXEVENT_HT                  (0x00000001U)             /*!< RxEvent linked to Half Transfer event     */
00836 #define HAL_UART_RXEVENT_IDLE                (0x00000002U)             /*!< RxEvent linked to IDLE event              */
00837 /**
00838   * @}
00839   */
00840
00841 /**
00842   * @}
00843   */
00844
00845 /* Exported macros -----------------------------------------------------------*/
00846 /** @defgroup UART_Exported_Macros UART Exported Macros
00847   * @{
00848   */
00849
00850 /** @brief  Reset UART handle states.
00851   * @param  __HANDLE__ UART handle.
00852   * @retval None
00853   */
00854 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00855 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00856                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00857                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00858                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00859                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00860                                                      } while(0U)
00861 #else
00862 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00863                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00864                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00865                                                      } while(0U)
00866 #endif /*USE_HAL_UART_REGISTER_CALLBACKS */
00867
00868 /** @brief  Flush the UART Data registers.
00869   * @param  __HANDLE__ specifies the UART Handle.
00870   * @retval None
00871   */
00872 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
00873   do{                \
00874     SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
00875     SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
00876   }  while(0U)
00877
00878 /** @brief  Clear the specified UART pending flag.
00879   * @param  __HANDLE__ specifies the UART Handle.
00880   * @param  __FLAG__ specifies the flag to check.
00881   *          This parameter can be any combination of the following values:
00882   *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
00883   *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
00884   *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
00885   *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
00886   *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
00887   *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
00888   *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
00889   *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
00890   *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
00891   *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
00892   *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
00893   *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
00894   * @retval None
00895   */
00896 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00897
00898 /** @brief  Clear the UART PE pending flag.
00899   * @param  __HANDLE__ specifies the UART Handle.
00900   * @retval None
00901   */
00902 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
00903
00904 /** @brief  Clear the UART FE pending flag.
00905   * @param  __HANDLE__ specifies the UART Handle.
00906   * @retval None
00907   */
00908 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
00909
00910 /** @brief  Clear the UART NE pending flag.
00911   * @param  __HANDLE__ specifies the UART Handle.
00912   * @retval None
00913   */
00914 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
00915
00916 /** @brief  Clear the UART ORE pending flag.
00917   * @param  __HANDLE__ specifies the UART Handle.
00918   * @retval None
00919   */
00920 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
00921
00922 /** @brief  Clear the UART IDLE pending flag.
00923   * @param  __HANDLE__ specifies the UART Handle.
00924   * @retval None
00925   */
00926 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
00927
00928 /** @brief  Clear the UART TX FIFO empty clear flag.
00929   * @param  __HANDLE__ specifies the UART Handle.
00930   * @retval None
00931   */
00932 #define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
00933
00934 /** @brief  Check whether the specified UART flag is set or not.
00935   * @param  __HANDLE__ specifies the UART Handle.
00936   * @param  __FLAG__ specifies the flag to check.
00937   *        This parameter can be one of the following values:
00938   *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
00939   *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
00940   *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
00941   *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
00942   *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
00943   *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
00944   *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
00945   *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
00946   *            @arg @ref UART_FLAG_SBKF  Send Break flag
00947   *            @arg @ref UART_FLAG_CMF   Character match flag
00948   *            @arg @ref UART_FLAG_BUSY  Busy flag
00949   *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
00950   *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
00951   *            @arg @ref UART_FLAG_CTS   CTS Change flag
00952   *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
00953   *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
00954   *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
00955   *            @arg @ref UART_FLAG_TC    Transmission Complete flag
00956   *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
00957   *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
00958   *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
00959   *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
00960   *            @arg @ref UART_FLAG_ORE   Overrun Error flag
00961   *            @arg @ref UART_FLAG_NE    Noise Error flag
00962   *            @arg @ref UART_FLAG_FE    Framing Error flag
00963   *            @arg @ref UART_FLAG_PE    Parity Error flag
00964   * @retval The new state of __FLAG__ (TRUE or FALSE).
00965   */
00966 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00967
00968 /** @brief  Enable the specified UART interrupt.
00969   * @param  __HANDLE__ specifies the UART Handle.
00970   * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
00971   *          This parameter can be one of the following values:
00972   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00973   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00974   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00975   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00976   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00977   *            @arg @ref UART_IT_CM    Character match interrupt
00978   *            @arg @ref UART_IT_CTS   CTS change interrupt
00979   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
00980   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
00981   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
00982   *            @arg @ref UART_IT_TC    Transmission complete interrupt
00983   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
00984   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
00985   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
00986   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
00987   *            @arg @ref UART_IT_PE    Parity Error interrupt
00988   *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
00989   * @retval None
00990   */
00991 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (\
00992                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
00993                                                            ((__HANDLE__)->Instance->CR1 |= (1U <<\
00994                                                                ((__INTERRUPT__) & UART_IT_MASK))): \
00995                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
00996                                                            ((__HANDLE__)->Instance->CR2 |= (1U <<\
00997                                                                ((__INTERRUPT__) & UART_IT_MASK))): \
00998                                                            ((__HANDLE__)->Instance->CR3 |= (1U <<\
00999                                                                ((__INTERRUPT__) & UART_IT_MASK))))
01000
01001 /** @brief  Disable the specified UART interrupt.
01002   * @param  __HANDLE__ specifies the UART Handle.
01003   * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
01004   *          This parameter can be one of the following values:
01005   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
01006   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
01007   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
01008   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
01009   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
01010   *            @arg @ref UART_IT_CM    Character match interrupt
01011   *            @arg @ref UART_IT_CTS   CTS change interrupt
01012   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
01013   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
01014   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
01015   *            @arg @ref UART_IT_TC    Transmission complete interrupt
01016   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
01017   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
01018   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
01019   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
01020   *            @arg @ref UART_IT_PE    Parity Error interrupt
01021   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
01022   * @retval None
01023   */
01024 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (\
01025                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
01026                                                            ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
01027                                                                ((__INTERRUPT__) & UART_IT_MASK))): \
01028                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
01029                                                            ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
01030                                                                ((__INTERRUPT__) & UART_IT_MASK))): \
01031                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
01032                                                                ((__INTERRUPT__) & UART_IT_MASK))))
01033
01034 /** @brief  Check whether the specified UART interrupt has occurred or not.
01035   * @param  __HANDLE__ specifies the UART Handle.
01036   * @param  __INTERRUPT__ specifies the UART interrupt to check.
01037   *          This parameter can be one of the following values:
01038   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
01039   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
01040   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
01041   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
01042   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
01043   *            @arg @ref UART_IT_CM    Character match interrupt
01044   *            @arg @ref UART_IT_CTS   CTS change interrupt
01045   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
01046   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
01047   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
01048   *            @arg @ref UART_IT_TC    Transmission complete interrupt
01049   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
01050   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
01051   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
01052   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
01053   *            @arg @ref UART_IT_PE    Parity Error interrupt
01054   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
01055   * @retval The new state of __INTERRUPT__ (SET or RESET).
01056   */
01057 #define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
01058                                                         & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
01059
01060 /** @brief  Check whether the specified UART interrupt source is enabled or not.
01061   * @param  __HANDLE__ specifies the UART Handle.
01062   * @param  __INTERRUPT__ specifies the UART interrupt source to check.
01063   *          This parameter can be one of the following values:
01064   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
01065   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
01066   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
01067   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
01068   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
01069   *            @arg @ref UART_IT_CM    Character match interrupt
01070   *            @arg @ref UART_IT_CTS   CTS change interrupt
01071   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
01072   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
01073   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
01074   *            @arg @ref UART_IT_TC    Transmission complete interrupt
01075   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
01076   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
01077   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
01078   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
01079   *            @arg @ref UART_IT_PE    Parity Error interrupt
01080   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
01081   * @retval The new state of __INTERRUPT__ (SET or RESET).
01082   */
01083 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
01084                                                                 (__HANDLE__)->Instance->CR1 : \
01085                                                                 (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
01086                                                                  (__HANDLE__)->Instance->CR2 : \
01087                                                                  (__HANDLE__)->Instance->CR3)) & (1U <<\
01088                                                                      (((uint16_t)(__INTERRUPT__)) &\
01089                                                                       UART_IT_MASK)))  != RESET) ? SET : RESET)
01090
01091 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
01092   * @param  __HANDLE__ specifies the UART Handle.
01093   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
01094   *                       to clear the corresponding interrupt
01095   *          This parameter can be one of the following values:
01096   *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
01097   *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
01098   *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
01099   *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
01100   *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
01101   *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
01102   *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
01103   *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
01104   *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
01105   *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
01106   *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
01107   *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
01108   * @retval None
01109   */
01110 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
01111
01112 /** @brief  Set a specific UART request flag.
01113   * @param  __HANDLE__ specifies the UART Handle.
01114   * @param  __REQ__ specifies the request flag to set
01115   *          This parameter can be one of the following values:
01116   *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
01117   *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
01118   *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
01119   *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
01120   *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
01121   * @retval None
01122   */
01123 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
01124
01125 /** @brief  Enable the UART one bit sample method.
01126   * @param  __HANDLE__ specifies the UART Handle.
01127   * @retval None
01128   */
01129 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
01130
01131 /** @brief  Disable the UART one bit sample method.
01132   * @param  __HANDLE__ specifies the UART Handle.
01133   * @retval None
01134   */
01135 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
01136
01137 /** @brief  Enable UART.
01138   * @param  __HANDLE__ specifies the UART Handle.
01139   * @retval None
01140   */
01141 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
01142
01143 /** @brief  Disable UART.
01144   * @param  __HANDLE__ specifies the UART Handle.
01145   * @retval None
01146   */
01147 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
01148
01149 /** @brief  Enable CTS flow control.
01150   * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
01151   *         without need to call HAL_UART_Init() function.
01152   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01153   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01154   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01155   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01156   *           - macro could only be called when corresponding UART instance is disabled
01157   *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
01158   *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01159   * @param  __HANDLE__ specifies the UART Handle.
01160   * @retval None
01161   */
01162 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)               \
01163   do{                                                             \
01164     ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
01165     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
01166   } while(0U)
01167
01168 /** @brief  Disable CTS flow control.
01169   * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
01170   *         without need to call HAL_UART_Init() function.
01171   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01172   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01173   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01174   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01175   *           - macro could only be called when corresponding UART instance is disabled
01176   *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
01177   *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01178   * @param  __HANDLE__ specifies the UART Handle.
01179   * @retval None
01180   */
01181 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)               \
01182   do{                                                              \
01183     ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
01184     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
01185   } while(0U)
01186
01187 /** @brief  Enable RTS flow control.
01188   * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
01189   *         without need to call HAL_UART_Init() function.
01190   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01191   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01192   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01193   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01194   *           - macro could only be called when corresponding UART instance is disabled
01195   *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
01196   *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01197   * @param  __HANDLE__ specifies the UART Handle.
01198   * @retval None
01199   */
01200 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)              \
01201   do{                                                            \
01202     ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
01203     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
01204   } while(0U)
01205
01206 /** @brief  Disable RTS flow control.
01207   * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
01208   *         without need to call HAL_UART_Init() function.
01209   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01210   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01211   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01212   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01213   *           - macro could only be called when corresponding UART instance is disabled
01214   *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
01215   *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01216   * @param  __HANDLE__ specifies the UART Handle.
01217   * @retval None
01218   */
01219 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)              \
01220   do{                                                             \
01221     ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
01222     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
01223   } while(0U)
01224 /**
01225   * @}
01226   */
01227
01228 /* Private macros --------------------------------------------------------*/
01229 /** @defgroup UART_Private_Macros   UART Private Macros
01230   * @{
01231   */
01232 /** @brief  Get UART clok division factor from clock prescaler value.
01233   * @param  __CLOCKPRESCALER__ UART prescaler value.
01234   * @retval UART clock division factor
01235   */
01236 #define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
01237   (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
01238    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
01239    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
01240    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
01241    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
01242    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
01243    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
01244    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
01245    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
01246    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
01247    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
01248    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
01249
01250 /** @brief  BRR division operation to set BRR register with LPUART.
01251   * @param  __PCLK__ LPUART clock.
01252   * @param  __BAUD__ Baud rate set by the user.
01253   * @param  __CLOCKPRESCALER__ UART prescaler value.
01254   * @retval Division result
01255   */
01256 #define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
01257   ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
01258                (uint32_t)((__BAUD__)/2U)) / (__BAUD__))                                \
01259   )
01260
01261 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
01262   * @param  __PCLK__ UART clock.
01263   * @param  __BAUD__ Baud rate set by the user.
01264   * @param  __CLOCKPRESCALER__ UART prescaler value.
01265   * @retval Division result
01266   */
01267 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
01268   (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
01269
01270 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
01271   * @param  __PCLK__ UART clock.
01272   * @param  __BAUD__ Baud rate set by the user.
01273   * @param  __CLOCKPRESCALER__ UART prescaler value.
01274   * @retval Division result
01275   */
01276 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                       \
01277   ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
01278
01279 /** @brief  Check whether or not UART instance is Low Power UART.
01280   * @param  __HANDLE__ specifies the UART Handle.
01281   * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
01282   */
01283 #define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
01284
01285 /** @brief  Check UART Baud rate.
01286   * @param  __BAUDRATE__ Baudrate specified by the user.
01287   *         The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 64 MHz)
01288   *         divided by the smallest oversampling used on the USART (i.e. 8)
01289   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
01290   */
01291 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U)
01292
01293 /** @brief  Check UART assertion time.
01294   * @param  __TIME__ 5-bit value assertion time.
01295   * @retval Test result (TRUE or FALSE).
01296   */
01297 #define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
01298
01299 /** @brief  Check UART deassertion time.
01300   * @param  __TIME__ 5-bit value deassertion time.
01301   * @retval Test result (TRUE or FALSE).
01302   */
01303 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
01304
01305 /**
01306   * @brief Ensure that UART frame number of stop bits is valid.
01307   * @param __STOPBITS__ UART frame number of stop bits.
01308   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01309   */
01310 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
01311                                         ((__STOPBITS__) == UART_STOPBITS_1)   || \
01312                                         ((__STOPBITS__) == UART_STOPBITS_1_5) || \
01313                                         ((__STOPBITS__) == UART_STOPBITS_2))
01314
01315 /**
01316   * @brief Ensure that LPUART frame number of stop bits is valid.
01317   * @param __STOPBITS__ LPUART frame number of stop bits.
01318   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01319   */
01320 #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
01321                                           ((__STOPBITS__) == UART_STOPBITS_2))
01322
01323 /**
01324   * @brief Ensure that UART frame parity is valid.
01325   * @param __PARITY__ UART frame parity.
01326   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
01327   */
01328 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
01329                                     ((__PARITY__) == UART_PARITY_EVEN) || \
01330                                     ((__PARITY__) == UART_PARITY_ODD))
01331
01332 /**
01333   * @brief Ensure that UART hardware flow control is valid.
01334   * @param __CONTROL__ UART hardware flow control.
01335   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
01336   */
01337 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
01338   (((__CONTROL__) == UART_HWCONTROL_NONE) || \
01339    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
01340    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
01341    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
01342
01343 /**
01344   * @brief Ensure that UART communication mode is valid.
01345   * @param __MODE__ UART communication mode.
01346   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01347   */
01348 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
01349
01350 /**
01351   * @brief Ensure that UART state is valid.
01352   * @param __STATE__ UART state.
01353   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
01354   */
01355 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
01356                                   ((__STATE__) == UART_STATE_ENABLE))
01357
01358 /**
01359   * @brief Ensure that UART oversampling is valid.
01360   * @param __SAMPLING__ UART oversampling.
01361   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
01362   */
01363 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
01364                                             ((__SAMPLING__) == UART_OVERSAMPLING_8))
01365
01366 /**
01367   * @brief Ensure that UART frame sampling is valid.
01368   * @param __ONEBIT__ UART frame sampling.
01369   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01370   */
01371 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
01372                                             ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
01373
01374 /**
01375   * @brief Ensure that UART auto Baud rate detection mode is valid.
01376   * @param __MODE__ UART auto Baud rate detection mode.
01377   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01378   */
01379 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
01380                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
01381                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
01382                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
01383
01384 /**
01385   * @brief Ensure that UART receiver timeout setting is valid.
01386   * @param __TIMEOUT__ UART receiver timeout setting.
01387   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01388   */
01389 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
01390                                                 ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
01391
01392 /** @brief  Check the receiver timeout value.
01393   * @note   The maximum UART receiver timeout value is 0xFFFFFF.
01394   * @param  __TIMEOUTVALUE__ receiver timeout value.
01395   * @retval Test result (TRUE or FALSE)
01396   */
01397 #define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
01398
01399 /**
01400   * @brief Ensure that UART LIN state is valid.
01401   * @param __LIN__ UART LIN state.
01402   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
01403   */
01404 #define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
01405                                      ((__LIN__) == UART_LIN_ENABLE))
01406
01407 /**
01408   * @brief Ensure that UART LIN break detection length is valid.
01409   * @param __LENGTH__ UART LIN break detection length.
01410   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
01411   */
01412 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
01413                                                      ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
01414
01415 /**
01416   * @brief Ensure that UART DMA TX state is valid.
01417   * @param __DMATX__ UART DMA TX state.
01418   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
01419   */
01420 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
01421                                        ((__DMATX__) == UART_DMA_TX_ENABLE))
01422
01423 /**
01424   * @brief Ensure that UART DMA RX state is valid.
01425   * @param __DMARX__ UART DMA RX state.
01426   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
01427   */
01428 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
01429                                        ((__DMARX__) == UART_DMA_RX_ENABLE))
01430
01431 /**
01432   * @brief Ensure that UART half-duplex state is valid.
01433   * @param __HDSEL__ UART half-duplex state.
01434   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
01435   */
01436 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
01437                                             ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
01438
01439 /**
01440   * @brief Ensure that UART wake-up method is valid.
01441   * @param __WAKEUP__ UART wake-up method .
01442   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
01443   */
01444 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
01445                                           ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
01446
01447 /**
01448   * @brief Ensure that UART request parameter is valid.
01449   * @param __PARAM__ UART request parameter.
01450   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01451   */
01452 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
01453                                               ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
01454                                               ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
01455                                               ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
01456                                               ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
01457
01458 /**
01459   * @brief Ensure that UART advanced features initialization is valid.
01460   * @param __INIT__ UART advanced features initialization.
01461   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01462   */
01463 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
01464                                                             UART_ADVFEATURE_TXINVERT_INIT          | \
01465                                                             UART_ADVFEATURE_RXINVERT_INIT          | \
01466                                                             UART_ADVFEATURE_DATAINVERT_INIT        | \
01467                                                             UART_ADVFEATURE_SWAP_INIT              | \
01468                                                             UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01469                                                             UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
01470                                                             UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
01471                                                             UART_ADVFEATURE_MSBFIRST_INIT))
01472
01473 /**
01474   * @brief Ensure that UART frame TX inversion setting is valid.
01475   * @param __TXINV__ UART frame TX inversion setting.
01476   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01477   */
01478 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
01479                                              ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
01480
01481 /**
01482   * @brief Ensure that UART frame RX inversion setting is valid.
01483   * @param __RXINV__ UART frame RX inversion setting.
01484   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01485   */
01486 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
01487                                              ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
01488
01489 /**
01490   * @brief Ensure that UART frame data inversion setting is valid.
01491   * @param __DATAINV__ UART frame data inversion setting.
01492   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01493   */
01494 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
01495                                                  ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
01496
01497 /**
01498   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
01499   * @param __SWAP__ UART frame RX/TX pins swap setting.
01500   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01501   */
01502 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
01503                                            ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
01504
01505 /**
01506   * @brief Ensure that UART frame overrun setting is valid.
01507   * @param __OVERRUN__ UART frame overrun setting.
01508   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01509   */
01510 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
01511                                           ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
01512
01513 /**
01514   * @brief Ensure that UART auto Baud rate state is valid.
01515   * @param __AUTOBAUDRATE__ UART auto Baud rate state.
01516   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
01517   */
01518 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
01519                                                             UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
01520                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
01521
01522 /**
01523   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
01524   * @param __DMA__ UART DMA enabling or disabling on error setting.
01525   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01526   */
01527 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01528                                                    ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
01529
01530 /**
01531   * @brief Ensure that UART frame MSB first setting is valid.
01532   * @param __MSBFIRST__ UART frame MSB first setting.
01533   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01534   */
01535 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
01536                                                    ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
01537
01538 /**
01539   * @brief Ensure that UART stop mode state is valid.
01540   * @param __STOPMODE__ UART stop mode state.
01541   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
01542   */
01543 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
01544                                                    ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
01545
01546 /**
01547   * @brief Ensure that UART mute mode state is valid.
01548   * @param __MUTE__ UART mute mode state.
01549   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
01550   */
01551 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
01552                                            ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
01553
01554 /**
01555   * @brief Ensure that UART wake-up selection is valid.
01556   * @param __WAKE__ UART wake-up selection.
01557   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
01558   */
01559 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
01560                                             ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
01561                                             ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
01562
01563 /**
01564   * @brief Ensure that UART driver enable polarity is valid.
01565   * @param __POLARITY__ UART driver enable polarity.
01566   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
01567   */
01568 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
01569                                               ((__POLARITY__) == UART_DE_POLARITY_LOW))
01570
01571 /**
01572   * @brief Ensure that UART Prescaler is valid.
01573   * @param __CLOCKPRESCALER__ UART Prescaler value.
01574   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
01575   */
01576 #define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
01577                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
01578                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
01579                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
01580                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
01581                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
01582                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
01583                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
01584                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
01585                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
01586                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
01587                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
01588
01589 /**
01590   * @}
01591   */
01592
01593 /* Include UART HAL Extended module */
01594 #include "stm32g0xx_hal_uart_ex.h"
01595
01596 /* Exported functions --------------------------------------------------------*/
01597 /** @addtogroup UART_Exported_Functions UART Exported Functions
01598   * @{
01599   */
01600
01601 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
01602   * @{
01603   */
01604
01605 /* Initialization and de-initialization functions  ****************************/
01606 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
01607 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
01608 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
01609 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
01610 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
01611 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
01612 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
01613
01614 /* Callbacks Register/UnRegister functions  ***********************************/
01615 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01616 HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
01617                                             pUART_CallbackTypeDef pCallback);
01618 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
01619
01620 HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
01621 HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
01622 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01623
01624 /**
01625   * @}
01626   */
01627
01628 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
01629   * @{
01630   */
01631
01632 /* IO operation functions *****************************************************/
01633 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
01634 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01635 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
01636 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01637 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
01638 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01639 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
01640 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
01641 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
01642 /* Transfer Abort functions */
01643 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
01644 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
01645 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
01646 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
01647 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
01648 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
01649
01650 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
01651 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
01652 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
01653 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
01654 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
01655 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
01656 void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
01657 void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
01658 void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
01659
01660 void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
01661
01662 /**
01663   * @}
01664   */
01665
01666 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
01667   * @{
01668   */
01669
01670 /* Peripheral Control functions  ************************************************/
01671 void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
01672 HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
01673 HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
01674
01675 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
01676 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
01677 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
01678 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
01679 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
01680 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
01681
01682 /**
01683   * @}
01684   */
01685
01686 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01687   * @{
01688   */
01689
01690 /* Peripheral State and Errors functions  **************************************************/
01691 HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
01692 uint32_t              HAL_UART_GetError(const UART_HandleTypeDef *huart);
01693
01694 /**
01695   * @}
01696   */
01697
01698 /**
01699   * @}
01700   */
01701
01702 /* Private functions -----------------------------------------------------------*/
01703 /** @addtogroup UART_Private_Functions UART Private Functions
01704   * @{
01705   */
01706 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01707 void              UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
01708 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01709 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
01710 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
01711 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
01712                                               uint32_t Tickstart, uint32_t Timeout);
01713 void              UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
01714 HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01715 HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01716
01717 /**
01718   * @}
01719   */
01720
01721 /* Private variables -----------------------------------------------------------*/
01722 /** @defgroup UART_Private_variables UART Private variables
01723   * @{
01724   */
01725 /* Prescaler Table used in BRR computation macros.
01726    Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
01727 extern const uint16_t UARTPrescTable[12];
01728 /**
01729   * @}
01730   */
01731
01732 /**
01733   * @}
01734   */
01735
01736 /**
01737   * @}
01738   */
01739
01740 #ifdef __cplusplus
01741 }
01742 #endif
01743
01744 #endif /* STM32G0xx_HAL_UART_H */
01745
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_uart_ex.c Source File

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stm32g0xx_hal_uart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_uart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended UART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * Copyright (c) 2018 STMicroelectronics.
00016   * All rights reserved.
00017   *
00018   * This software is licensed under terms that can be found in the LICENSE file
00019   * in the root directory of this software component.
00020   * If no LICENSE file comes with this software, it is provided AS-IS.
00021   *
00022   ******************************************************************************
00023   @verbatim
00024   ==============================================================================
00025                ##### UART peripheral extended features  #####
00026   ==============================================================================
00027
00028     (#) Declare a UART_HandleTypeDef handle structure.
00029
00030     (#) For the UART RS485 Driver Enable mode, initialize the UART registers
00031         by calling the HAL_RS485Ex_Init() API.
00032
00033     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00034
00035         -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
00036             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00037             configured prior starting RX/TX transfers.
00038
00039   @endverbatim
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32g0xx_hal.h"
00045
00046 /** @addtogroup STM32G0xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup UARTEx UARTEx
00051   * @brief UART Extended HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_UART_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /** @defgroup UARTEX_Private_Constants UARTEx Private Constants
00060   * @{
00061   */
00062 /* UART RX FIFO depth */
00063 #define RX_FIFO_DEPTH 8U
00064
00065 /* UART TX FIFO depth */
00066 #define TX_FIFO_DEPTH 8U
00067 /**
00068   * @}
00069   */
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073 /* Private function prototypes -----------------------------------------------*/
00074 /** @defgroup UARTEx_Private_Functions UARTEx Private Functions
00075   * @{
00076   */
00077 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00078 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
00079 /**
00080   * @}
00081   */
00082
00083 /* Exported functions --------------------------------------------------------*/
00084
00085 /** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
00090   * @brief    Extended Initialization and Configuration Functions
00091   *
00092 @verbatim
00093 ===============================================================================
00094             ##### Initialization and Configuration functions #####
00095  ===============================================================================
00096     [..]
00097     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00098     in asynchronous mode.
00099       (+) For the asynchronous mode the parameters below can be configured:
00100         (++) Baud Rate
00101         (++) Word Length
00102         (++) Stop Bit
00103         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00104              in the data register is transmitted but is changed by the parity bit.
00105         (++) Hardware flow control
00106         (++) Receiver/transmitter modes
00107         (++) Over Sampling Method
00108         (++) One-Bit Sampling Method
00109       (+) For the asynchronous mode, the following advanced features can be configured as well:
00110         (++) TX and/or RX pin level inversion
00111         (++) data logical level inversion
00112         (++) RX and TX pins swap
00113         (++) RX overrun detection disabling
00114         (++) DMA disabling on RX error
00115         (++) MSB first on communication line
00116         (++) auto Baud rate detection
00117     [..]
00118     The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
00119      procedures (details for the procedures are available in reference manual).
00120
00121 @endverbatim
00122
00123   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00124   8-bit or 9-bit), the possible UART formats are listed in the
00125   following table.
00126
00127     Table 1. UART frame format.
00128     +-----------------------------------------------------------------------+
00129     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00130     |---------|---------|-----------|---------------------------------------|
00131     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00132     |---------|---------|-----------|---------------------------------------|
00133     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00134     |---------|---------|-----------|---------------------------------------|
00135     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00136     |---------|---------|-----------|---------------------------------------|
00137     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00138     |---------|---------|-----------|---------------------------------------|
00139     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00140     |---------|---------|-----------|---------------------------------------|
00141     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00142     +-----------------------------------------------------------------------+
00143
00144   * @{
00145   */
00146
00147 /**
00148   * @brief Initialize the RS485 Driver enable feature according to the specified
00149   *         parameters in the UART_InitTypeDef and creates the associated handle.
00150   * @param huart            UART handle.
00151   * @param Polarity         Select the driver enable polarity.
00152   *          This parameter can be one of the following values:
00153   *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
00154   *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
00155   * @param AssertionTime    Driver Enable assertion time:
00156   *       5-bit value defining the time between the activation of the DE (Driver Enable)
00157   *       signal and the beginning of the start bit. It is expressed in sample time
00158   *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
00159   * @param DeassertionTime  Driver Enable deassertion time:
00160   *       5-bit value defining the time between the end of the last stop bit, in a
00161   *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
00162   *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
00163   *       oversampling rate).
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
00167                                    uint32_t DeassertionTime)
00168 {
00169   uint32_t temp;
00170
00171   /* Check the UART handle allocation */
00172   if (huart == NULL)
00173   {
00174     return HAL_ERROR;
00175   }
00176   /* Check the Driver Enable UART instance */
00177   assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
00178
00179   /* Check the Driver Enable polarity */
00180   assert_param(IS_UART_DE_POLARITY(Polarity));
00181
00182   /* Check the Driver Enable assertion time */
00183   assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
00184
00185   /* Check the Driver Enable deassertion time */
00186   assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
00187
00188   if (huart->gState == HAL_UART_STATE_RESET)
00189   {
00190     /* Allocate lock resource and initialize it */
00191     huart->Lock = HAL_UNLOCKED;
00192
00193 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00194     UART_InitCallbacksToDefault(huart);
00195
00196     if (huart->MspInitCallback == NULL)
00197     {
00198       huart->MspInitCallback = HAL_UART_MspInit;
00199     }
00200
00201     /* Init the low level hardware */
00202     huart->MspInitCallback(huart);
00203 #else
00204     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00205     HAL_UART_MspInit(huart);
00206 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00207   }
00208
00209   huart->gState = HAL_UART_STATE_BUSY;
00210
00211   /* Disable the Peripheral */
00212   __HAL_UART_DISABLE(huart);
00213
00214   /* Set the UART Communication parameters */
00215   if (UART_SetConfig(huart) == HAL_ERROR)
00216   {
00217     return HAL_ERROR;
00218   }
00219
00220   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00221   {
00222     UART_AdvFeatureConfig(huart);
00223   }
00224
00225   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
00226   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
00227
00228   /* Set the Driver Enable polarity */
00229   MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
00230
00231   /* Set the Driver Enable assertion and deassertion times */
00232   temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
00233   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
00234   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
00235
00236   /* Enable the Peripheral */
00237   __HAL_UART_ENABLE(huart);
00238
00239   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00240   return (UART_CheckIdleState(huart));
00241 }
00242
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
00248   *  @brief Extended functions
00249   *
00250 @verbatim
00251  ===============================================================================
00252                       ##### IO operation functions #####
00253  ===============================================================================
00254     This subsection provides a set of Wakeup and FIFO mode related callback functions.
00255
00256     (#) Wakeup from Stop mode Callback:
00257         (+) HAL_UARTEx_WakeupCallback()
00258
00259     (#) TX/RX Fifos Callbacks:
00260         (+) HAL_UARTEx_RxFifoFullCallback()
00261         (+) HAL_UARTEx_TxFifoEmptyCallback()
00262
00263 @endverbatim
00264   * @{
00265   */
00266
00267 /**
00268   * @brief UART wakeup from Stop mode callback.
00269   * @param huart UART handle.
00270   * @retval None
00271   */
00272 __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
00273 {
00274   /* Prevent unused argument(s) compilation warning */
00275   UNUSED(huart);
00276
00277   /* NOTE : This function should not be modified, when the callback is needed,
00278             the HAL_UARTEx_WakeupCallback can be implemented in the user file.
00279    */
00280 }
00281
00282 /**
00283   * @brief  UART RX Fifo full callback.
00284   * @param  huart UART handle.
00285   * @retval None
00286   */
00287 __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
00288 {
00289   /* Prevent unused argument(s) compilation warning */
00290   UNUSED(huart);
00291
00292   /* NOTE : This function should not be modified, when the callback is needed,
00293             the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
00294    */
00295 }
00296
00297 /**
00298   * @brief  UART TX Fifo empty callback.
00299   * @param  huart UART handle.
00300   * @retval None
00301   */
00302 __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
00303 {
00304   /* Prevent unused argument(s) compilation warning */
00305   UNUSED(huart);
00306
00307   /* NOTE : This function should not be modified, when the callback is needed,
00308             the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
00309    */
00310 }
00311
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
00317   * @brief    Extended Peripheral Control functions
00318   *
00319 @verbatim
00320  ===============================================================================
00321                       ##### Peripheral Control functions #####
00322  ===============================================================================
00323     [..] This section provides the following functions:
00324      (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
00325          detection length to more than 4 bits for multiprocessor address mark wake up.
00326      (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
00327          trigger: address match, Start Bit detection or RXNE bit status.
00328      (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
00329      (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
00330      (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
00331      (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
00332      (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00333      (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00334
00335     [..] This subsection also provides a set of additional functions providing enhanced reception
00336     services to user. (For example, these functions allow application to handle use cases
00337     where number of data to be received is unknown).
00338
00339     (#) Compared to standard reception services which only consider number of received
00340         data elements as reception completion criteria, these functions also consider additional events
00341         as triggers for updating reception status to caller :
00342        (+) Detection of inactivity period (RX line has not been active for a given period).
00343           (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
00344                for 1 frame time, after last received byte.
00345           (++) RX inactivity detected by RTO, i.e. line has been in idle state
00346                for a programmable time, after last received byte.
00347        (+) Detection that a specific character has been received.
00348
00349     (#) There are two mode of transfer:
00350        (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
00351            or till IDLE event occurs. Reception is handled only during function execution.
00352            When function exits, no data reception could occur. HAL status and number of actually received data elements,
00353            are returned by function after finishing transfer.
00354        (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
00355            These API's return the HAL status.
00356            The end of the data processing will be indicated through the
00357            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
00358            The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
00359            The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
00360
00361     (#) Blocking mode API:
00362         (+) HAL_UARTEx_ReceiveToIdle()
00363
00364     (#) Non-Blocking mode API with Interrupt:
00365         (+) HAL_UARTEx_ReceiveToIdle_IT()
00366
00367     (#) Non-Blocking mode API with DMA:
00368         (+) HAL_UARTEx_ReceiveToIdle_DMA()
00369
00370 @endverbatim
00371   * @{
00372   */
00373
00374 /**
00375   * @brief By default in multiprocessor mode, when the wake up method is set
00376   *        to address mark, the UART handles only 4-bit long addresses detection;
00377   *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
00378   *        long).
00379   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
00380   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
00381   * @param huart         UART handle.
00382   * @param AddressLength This parameter can be one of the following values:
00383   *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
00384   *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
00385   * @retval HAL status
00386   */
00387 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
00388 {
00389   /* Check the UART handle allocation */
00390   if (huart == NULL)
00391   {
00392     return HAL_ERROR;
00393   }
00394
00395   /* Check the address length parameter */
00396   assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
00397
00398   huart->gState = HAL_UART_STATE_BUSY;
00399
00400   /* Disable the Peripheral */
00401   __HAL_UART_DISABLE(huart);
00402
00403   /* Set the address length */
00404   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
00405
00406   /* Enable the Peripheral */
00407   __HAL_UART_ENABLE(huart);
00408
00409   /* TEACK and/or REACK to check before moving huart->gState to Ready */
00410   return (UART_CheckIdleState(huart));
00411 }
00412
00413 /**
00414   * @brief Set Wakeup from Stop mode interrupt flag selection.
00415   * @note It is the application responsibility to enable the interrupt used as
00416   *       usart_wkup interrupt source before entering low-power mode.
00417   * @param huart           UART handle.
00418   * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
00419   *          This parameter can be one of the following values:
00420   *          @arg @ref UART_WAKEUP_ON_ADDRESS
00421   *          @arg @ref UART_WAKEUP_ON_STARTBIT
00422   *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
00423   * @retval HAL status
00424   */
00425 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00426 {
00427   HAL_StatusTypeDef status = HAL_OK;
00428   uint32_t tickstart;
00429
00430   /* check the wake-up from stop mode UART instance */
00431   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00432   /* check the wake-up selection parameter */
00433   assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
00434
00435   /* Process Locked */
00436   __HAL_LOCK(huart);
00437
00438   huart->gState = HAL_UART_STATE_BUSY;
00439
00440   /* Disable the Peripheral */
00441   __HAL_UART_DISABLE(huart);
00442
00443   /* Set the wake-up selection scheme */
00444   MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
00445
00446   if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
00447   {
00448     UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
00449   }
00450
00451   /* Enable the Peripheral */
00452   __HAL_UART_ENABLE(huart);
00453
00454   /* Init tickstart for timeout management */
00455   tickstart = HAL_GetTick();
00456
00457   /* Wait until REACK flag is set */
00458   if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
00459   {
00460     status = HAL_TIMEOUT;
00461   }
00462   else
00463   {
00464     /* Initialize the UART State */
00465     huart->gState = HAL_UART_STATE_READY;
00466   }
00467
00468   /* Process Unlocked */
00469   __HAL_UNLOCK(huart);
00470
00471   return status;
00472 }
00473
00474 /**
00475   * @brief Enable UART Stop Mode.
00476   * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
00477   * @param huart UART handle.
00478   * @retval HAL status
00479   */
00480 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
00481 {
00482   /* Process Locked */
00483   __HAL_LOCK(huart);
00484
00485   /* Set UESM bit */
00486   ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
00487
00488   /* Process Unlocked */
00489   __HAL_UNLOCK(huart);
00490
00491   return HAL_OK;
00492 }
00493
00494 /**
00495   * @brief Disable UART Stop Mode.
00496   * @param huart UART handle.
00497   * @retval HAL status
00498   */
00499 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
00500 {
00501   /* Process Locked */
00502   __HAL_LOCK(huart);
00503
00504   /* Clear UESM bit */
00505   ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
00506
00507   /* Process Unlocked */
00508   __HAL_UNLOCK(huart);
00509
00510   return HAL_OK;
00511 }
00512
00513 /**
00514   * @brief  Enable the FIFO mode.
00515   * @param huart      UART handle.
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
00519 {
00520   uint32_t tmpcr1;
00521
00522   /* Check parameters */
00523   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00524
00525   /* Process Locked */
00526   __HAL_LOCK(huart);
00527
00528   huart->gState = HAL_UART_STATE_BUSY;
00529
00530   /* Save actual UART configuration */
00531   tmpcr1 = READ_REG(huart->Instance->CR1);
00532
00533   /* Disable UART */
00534   __HAL_UART_DISABLE(huart);
00535
00536   /* Enable FIFO mode */
00537   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00538   huart->FifoMode = UART_FIFOMODE_ENABLE;
00539
00540   /* Restore UART configuration */
00541   WRITE_REG(huart->Instance->CR1, tmpcr1);
00542
00543   /* Determine the number of data to process during RX/TX ISR execution */
00544   UARTEx_SetNbDataToProcess(huart);
00545
00546   huart->gState = HAL_UART_STATE_READY;
00547
00548   /* Process Unlocked */
00549   __HAL_UNLOCK(huart);
00550
00551   return HAL_OK;
00552 }
00553
00554 /**
00555   * @brief  Disable the FIFO mode.
00556   * @param huart      UART handle.
00557   * @retval HAL status
00558   */
00559 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
00560 {
00561   uint32_t tmpcr1;
00562
00563   /* Check parameters */
00564   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00565
00566   /* Process Locked */
00567   __HAL_LOCK(huart);
00568
00569   huart->gState = HAL_UART_STATE_BUSY;
00570
00571   /* Save actual UART configuration */
00572   tmpcr1 = READ_REG(huart->Instance->CR1);
00573
00574   /* Disable UART */
00575   __HAL_UART_DISABLE(huart);
00576
00577   /* Enable FIFO mode */
00578   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00579   huart->FifoMode = UART_FIFOMODE_DISABLE;
00580
00581   /* Restore UART configuration */
00582   WRITE_REG(huart->Instance->CR1, tmpcr1);
00583
00584   huart->gState = HAL_UART_STATE_READY;
00585
00586   /* Process Unlocked */
00587   __HAL_UNLOCK(huart);
00588
00589   return HAL_OK;
00590 }
00591
00592 /**
00593   * @brief  Set the TXFIFO threshold.
00594   * @param huart      UART handle.
00595   * @param Threshold  TX FIFO threshold value
00596   *          This parameter can be one of the following values:
00597   *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
00598   *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
00599   *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
00600   *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
00601   *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
00602   *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
00603   * @retval HAL status
00604   */
00605 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
00606 {
00607   uint32_t tmpcr1;
00608
00609   /* Check parameters */
00610   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00611   assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
00612
00613   /* Process Locked */
00614   __HAL_LOCK(huart);
00615
00616   huart->gState = HAL_UART_STATE_BUSY;
00617
00618   /* Save actual UART configuration */
00619   tmpcr1 = READ_REG(huart->Instance->CR1);
00620
00621   /* Disable UART */
00622   __HAL_UART_DISABLE(huart);
00623
00624   /* Update TX threshold configuration */
00625   MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00626
00627   /* Determine the number of data to process during RX/TX ISR execution */
00628   UARTEx_SetNbDataToProcess(huart);
00629
00630   /* Restore UART configuration */
00631   WRITE_REG(huart->Instance->CR1, tmpcr1);
00632
00633   huart->gState = HAL_UART_STATE_READY;
00634
00635   /* Process Unlocked */
00636   __HAL_UNLOCK(huart);
00637
00638   return HAL_OK;
00639 }
00640
00641 /**
00642   * @brief  Set the RXFIFO threshold.
00643   * @param huart      UART handle.
00644   * @param Threshold  RX FIFO threshold value
00645   *          This parameter can be one of the following values:
00646   *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
00647   *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
00648   *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
00649   *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
00650   *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
00651   *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
00652   * @retval HAL status
00653   */
00654 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
00655 {
00656   uint32_t tmpcr1;
00657
00658   /* Check the parameters */
00659   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00660   assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
00661
00662   /* Process Locked */
00663   __HAL_LOCK(huart);
00664
00665   huart->gState = HAL_UART_STATE_BUSY;
00666
00667   /* Save actual UART configuration */
00668   tmpcr1 = READ_REG(huart->Instance->CR1);
00669
00670   /* Disable UART */
00671   __HAL_UART_DISABLE(huart);
00672
00673   /* Update RX threshold configuration */
00674   MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00675
00676   /* Determine the number of data to process during RX/TX ISR execution */
00677   UARTEx_SetNbDataToProcess(huart);
00678
00679   /* Restore UART configuration */
00680   WRITE_REG(huart->Instance->CR1, tmpcr1);
00681
00682   huart->gState = HAL_UART_STATE_READY;
00683
00684   /* Process Unlocked */
00685   __HAL_UNLOCK(huart);
00686
00687   return HAL_OK;
00688 }
00689
00690 /**
00691   * @brief Receive an amount of data in blocking mode till either the expected number of data
00692   *        is received or an IDLE event occurs.
00693   * @note  HAL_OK is returned if reception is completed (expected number of data has been received)
00694   *        or if reception is stopped after IDLE event (less than the expected number of data has been received)
00695   *        In this case, RxLen output parameter indicates number of data available in reception buffer.
00696   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00697   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
00698   *        of uint16_t available through pData.
00699   * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
00700   *       is not empty. Read operations from the RDR register are performed when
00701   *       RXFNE flag is set. From hardware perspective, RXFNE flag and
00702   *       RXNE are mapped on the same bit-field.
00703   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00704   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
00705   *         (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
00706   *         use of specific alignment compilation directives or pragmas might be required to ensure proper
00707   *         alignment for pData.
00708   * @param huart   UART handle.
00709   * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
00710   * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
00711   * @param RxLen   Number of data elements finally received
00712   *                (could be lower than Size, in case reception ends on IDLE event)
00713   * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
00714   * @retval HAL status
00715   */
00716 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
00717                                            uint32_t Timeout)
00718 {
00719   uint8_t  *pdata8bits;
00720   uint16_t *pdata16bits;
00721   uint16_t uhMask;
00722   uint32_t tickstart;
00723
00724   /* Check that a Rx process is not already ongoing */
00725   if (huart->RxState == HAL_UART_STATE_READY)
00726   {
00727     if ((pData == NULL) || (Size == 0U))
00728     {
00729       return  HAL_ERROR;
00730     }
00731
00732     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
00733        should be aligned on a uint16_t frontier, as data to be received from RDR will be
00734        handled through a uint16_t cast. */
00735     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00736     {
00737       if ((((uint32_t)pData) & 1U) != 0U)
00738       {
00739         return  HAL_ERROR;
00740       }
00741     }
00742
00743     huart->ErrorCode = HAL_UART_ERROR_NONE;
00744     huart->RxState = HAL_UART_STATE_BUSY_RX;
00745     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
00746     huart->RxEventType = HAL_UART_RXEVENT_TC;
00747
00748     /* Init tickstart for timeout management */
00749     tickstart = HAL_GetTick();
00750
00751     huart->RxXferSize  = Size;
00752     huart->RxXferCount = Size;
00753
00754     /* Computation of UART mask to apply to RDR register */
00755     UART_MASK_COMPUTATION(huart);
00756     uhMask = huart->Mask;
00757
00758     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00759     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00760     {
00761       pdata8bits  = NULL;
00762       pdata16bits = (uint16_t *) pData;
00763     }
00764     else
00765     {
00766       pdata8bits  = pData;
00767       pdata16bits = NULL;
00768     }
00769
00770     /* Initialize output number of received elements */
00771     *RxLen = 0U;
00772
00773     /* as long as data have to be received */
00774     while (huart->RxXferCount > 0U)
00775     {
00776       /* Check if IDLE flag is set */
00777       if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
00778       {
00779         /* Clear IDLE flag in ISR */
00780         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
00781
00782         /* If Set, but no data ever received, clear flag without exiting loop */
00783         /* If Set, and data has already been received, this means Idle Event is valid : End reception */
00784         if (*RxLen > 0U)
00785         {
00786           huart->RxEventType = HAL_UART_RXEVENT_IDLE;
00787           huart->RxState = HAL_UART_STATE_READY;
00788
00789           return HAL_OK;
00790         }
00791       }
00792
00793       /* Check if RXNE flag is set */
00794       if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
00795       {
00796         if (pdata8bits == NULL)
00797         {
00798           *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
00799           pdata16bits++;
00800         }
00801         else
00802         {
00803           *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
00804           pdata8bits++;
00805         }
00806         /* Increment number of received elements */
00807         *RxLen += 1U;
00808         huart->RxXferCount--;
00809       }
00810
00811       /* Check for the Timeout */
00812       if (Timeout != HAL_MAX_DELAY)
00813       {
00814         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
00815         {
00816           huart->RxState = HAL_UART_STATE_READY;
00817
00818           return HAL_TIMEOUT;
00819         }
00820       }
00821     }
00822
00823     /* Set number of received elements in output parameter : RxLen */
00824     *RxLen = huart->RxXferSize - huart->RxXferCount;
00825     /* At end of Rx process, restore huart->RxState to Ready */
00826     huart->RxState = HAL_UART_STATE_READY;
00827
00828     return HAL_OK;
00829   }
00830   else
00831   {
00832     return HAL_BUSY;
00833   }
00834 }
00835
00836 /**
00837   * @brief Receive an amount of data in interrupt mode till either the expected number of data
00838   *        is received or an IDLE event occurs.
00839   * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
00840   *        to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
00841   *        number of received data elements.
00842   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00843   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
00844   *        of uint16_t available through pData.
00845   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00846   *        address of user data buffer for storing data to be received, should be aligned on a half word frontier
00847   *        (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
00848   *        use of specific alignment compilation directives or pragmas might be required
00849   *        to ensure proper alignment for pData.
00850   * @param huart UART handle.
00851   * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
00852   * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
00853   * @retval HAL status
00854   */
00855 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00856 {
00857   HAL_StatusTypeDef status;
00858
00859   /* Check that a Rx process is not already ongoing */
00860   if (huart->RxState == HAL_UART_STATE_READY)
00861   {
00862     if ((pData == NULL) || (Size == 0U))
00863     {
00864       return HAL_ERROR;
00865     }
00866
00867     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
00868        should be aligned on a uint16_t frontier, as data to be received from RDR will be
00869        handled through a uint16_t cast. */
00870     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00871     {
00872       if ((((uint32_t)pData) & 1U) != 0U)
00873       {
00874         return  HAL_ERROR;
00875       }
00876     }
00877
00878     /* Set Reception type to reception till IDLE Event*/
00879     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
00880     huart->RxEventType = HAL_UART_RXEVENT_TC;
00881
00882     status =  UART_Start_Receive_IT(huart, pData, Size);
00883
00884     /* Check Rx process has been successfully started */
00885     if (status == HAL_OK)
00886     {
00887       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
00888       {
00889         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
00890         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
00891       }
00892       else
00893       {
00894         /* In case of errors already pending when reception is started,
00895            Interrupts may have already been raised and lead to reception abortion.
00896            (Overrun error for instance).
00897            In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
00898         status = HAL_ERROR;
00899       }
00900     }
00901
00902     return status;
00903   }
00904   else
00905   {
00906     return HAL_BUSY;
00907   }
00908 }
00909
00910 /**
00911   * @brief Receive an amount of data in DMA mode till either the expected number
00912   *        of data is received or an IDLE event occurs.
00913   * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
00914   *        to DMA services, transferring automatically received data elements in user reception buffer and
00915   *        calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
00916   *        reception phase as ended. In all cases, callback execution will indicate number of received data elements.
00917   * @note  When the UART parity is enabled (PCE = 1), the received data contain
00918   *        the parity bit (MSB position).
00919   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00920   *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
00921   *        of uint16_t available through pData.
00922   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00923   *        address of user data buffer for storing data to be received, should be aligned on a half word frontier
00924   *        (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
00925   *        use of specific alignment compilation directives or pragmas might be required
00926   *        to ensure proper alignment for pData.
00927   * @param huart UART handle.
00928   * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
00929   * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
00930   * @retval HAL status
00931   */
00932 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00933 {
00934   HAL_StatusTypeDef status;
00935
00936   /* Check that a Rx process is not already ongoing */
00937   if (huart->RxState == HAL_UART_STATE_READY)
00938   {
00939     if ((pData == NULL) || (Size == 0U))
00940     {
00941       return HAL_ERROR;
00942     }
00943
00944     /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
00945        should be aligned on a uint16_t frontier, as data copy from RDR will be
00946        handled by DMA from a uint16_t frontier. */
00947     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00948     {
00949       if ((((uint32_t)pData) & 1U) != 0U)
00950       {
00951         return  HAL_ERROR;
00952       }
00953     }
00954
00955     /* Set Reception type to reception till IDLE Event*/
00956     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
00957     huart->RxEventType = HAL_UART_RXEVENT_TC;
00958
00959     status =  UART_Start_Receive_DMA(huart, pData, Size);
00960
00961     /* Check Rx process has been successfully started */
00962     if (status == HAL_OK)
00963     {
00964       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
00965       {
00966         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
00967         ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
00968       }
00969       else
00970       {
00971         /* In case of errors already pending when reception is started,
00972            Interrupts may have already been raised and lead to reception abortion.
00973            (Overrun error for instance).
00974            In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
00975         status = HAL_ERROR;
00976       }
00977     }
00978
00979     return status;
00980   }
00981   else
00982   {
00983     return HAL_BUSY;
00984   }
00985 }
00986
00987 /**
00988   * @brief Provide Rx Event type that has lead to RxEvent callback execution.
00989   * @note  When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
00990   *        of reception process is provided to application through calls of Rx Event callback (either default one
00991   *        HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
00992   *        Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
00993   *        to Rx Event callback execution.
00994   * @note  This function is expected to be called within the user implementation of Rx Event Callback,
00995   *        in order to provide the accurate value :
00996   *        In Interrupt Mode :
00997   *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
00998   *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
00999   *             received data is lower than expected one)
01000   *        In DMA Mode :
01001   *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
01002   *           - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
01003   *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
01004   *             received data is lower than expected one).
01005   *        In DMA mode, RxEvent callback could be called several times;
01006   *        When DMA is configured in Normal Mode, HT event does not stop Reception process;
01007   *        When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
01008   * @param  huart UART handle.
01009   * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
01010   */
01011 HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
01012 {
01013   /* Return Rx Event type value, as stored in UART handle */
01014   return(huart->RxEventType);
01015 }
01016
01017 /**
01018   * @}
01019   */
01020
01021 /**
01022   * @}
01023   */
01024
01025 /** @addtogroup UARTEx_Private_Functions
01026   * @{
01027   */
01028
01029 /**
01030   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
01031   * @param huart           UART handle.
01032   * @param WakeUpSelection UART wake up from stop mode parameters.
01033   * @retval None
01034   */
01035 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
01036 {
01037   assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
01038
01039   /* Set the USART address length */
01040   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
01041
01042   /* Set the USART address node */
01043   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
01044 }
01045
01046 /**
01047   * @brief Calculate the number of data to process in RX/TX ISR.
01048   * @note The RX FIFO depth and the TX FIFO depth is extracted from
01049   *       the UART configuration registers.
01050   * @param huart UART handle.
01051   * @retval None
01052   */
01053 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
01054 {
01055   uint8_t rx_fifo_depth;
01056   uint8_t tx_fifo_depth;
01057   uint8_t rx_fifo_threshold;
01058   uint8_t tx_fifo_threshold;
01059   static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
01060   static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
01061
01062   if (huart->FifoMode == UART_FIFOMODE_DISABLE)
01063   {
01064     huart->NbTxDataToProcess = 1U;
01065     huart->NbRxDataToProcess = 1U;
01066   }
01067   else
01068   {
01069     rx_fifo_depth = RX_FIFO_DEPTH;
01070     tx_fifo_depth = TX_FIFO_DEPTH;
01071     rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
01072     tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
01073     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
01074                                (uint16_t)denominator[tx_fifo_threshold];
01075     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
01076                                (uint16_t)denominator[rx_fifo_threshold];
01077   }
01078 }
01079 /**
01080   * @}
01081   */
01082
01083 #endif /* HAL_UART_MODULE_ENABLED */
01084
01085 /**
01086   * @}
01087   */
01088
01089 /**
01090   * @}
01091   */
01092
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_uart_ex.h Source File

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stm32g0xx_hal_uart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_uart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_UART_EX_H
00021 #define STM32G0xx_HAL_UART_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup UARTEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup UARTEx_Exported_Types UARTEx Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief  UART wake up from stop mode parameters
00045   */
00046 typedef struct
00047 {
00048   uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
00049                                     This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
00050                                     If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
00051                                     be filled up. */
00052
00053   uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
00054                                     This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
00055
00056   uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
00057 } UART_WakeUpTypeDef;
00058
00059 /**
00060   * @}
00061   */
00062
00063 /* Exported constants --------------------------------------------------------*/
00064 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
00065   * @{
00066   */
00067
00068 /** @defgroup UARTEx_Word_Length UARTEx Word Length
00069   * @{
00070   */
00071 #define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
00072 #define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
00073 #define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
00074 /**
00075   * @}
00076   */
00077
00078 /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
00079   * @{
00080   */
00081 #define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
00082 #define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
00088   * @brief    UART FIFO mode
00089   * @{
00090   */
00091 #define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
00092 #define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
00098   * @brief    UART TXFIFO threshold level
00099   * @{
00100   */
00101 #define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TX FIFO reaches 1/8 of its depth */
00102 #define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TX FIFO reaches 1/4 of its depth */
00103 #define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TX FIFO reaches 1/2 of its depth */
00104 #define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
00105 #define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TX FIFO reaches 7/8 of its depth */
00106 #define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty            */
00107 /**
00108   * @}
00109   */
00110
00111 /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
00112   * @brief    UART RXFIFO threshold level
00113   * @{
00114   */
00115 #define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RX FIFO reaches 1/8 of its depth */
00116 #define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RX FIFO reaches 1/4 of its depth */
00117 #define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RX FIFO reaches 1/2 of its depth */
00118 #define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
00119 #define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RX FIFO reaches 7/8 of its depth */
00120 #define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full             */
00121 /**
00122   * @}
00123   */
00124
00125 /**
00126   * @}
00127   */
00128
00129 /* Exported macros -----------------------------------------------------------*/
00130 /* Exported functions --------------------------------------------------------*/
00131 /** @addtogroup UARTEx_Exported_Functions
00132   * @{
00133   */
00134
00135 /** @addtogroup UARTEx_Exported_Functions_Group1
00136   * @{
00137   */
00138
00139 /* Initialization and de-initialization functions  ****************************/
00140 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
00141                                    uint32_t DeassertionTime);
00142
00143 /**
00144   * @}
00145   */
00146
00147 /** @addtogroup UARTEx_Exported_Functions_Group2
00148   * @{
00149   */
00150
00151 void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
00152
00153 void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
00154 void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
00155
00156 /**
00157   * @}
00158   */
00159
00160 /** @addtogroup UARTEx_Exported_Functions_Group3
00161   * @{
00162   */
00163
00164 /* Peripheral Control functions  **********************************************/
00165 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00166 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
00167 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
00168
00169 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
00170
00171 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
00172 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
00173 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
00174 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
00175
00176 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
00177                                            uint32_t Timeout);
00178 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00179 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00180
00181 HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
00182
00183
00184 /**
00185   * @}
00186   */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /* Private macros ------------------------------------------------------------*/
00193 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
00194   * @{
00195   */
00196
00197 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00198 /** @brief  Report the UART clock source.
00199   * @param  __HANDLE__ specifies the UART Handle.
00200   * @param  __CLOCKSOURCE__ output variable.
00201   * @retval UART clocking source, written in __CLOCKSOURCE__.
00202   */
00203 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00204   do {                                                        \
00205     if((__HANDLE__)->Instance == USART1)                      \
00206     {                                                         \
00207       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00208       {                                                       \
00209         case RCC_USART1CLKSOURCE_PCLK1:                       \
00210           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00211           break;                                              \
00212         case RCC_USART1CLKSOURCE_HSI:                         \
00213           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00214           break;                                              \
00215         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00216           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00217           break;                                              \
00218         case RCC_USART1CLKSOURCE_LSE:                         \
00219           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00220           break;                                              \
00221         default:                                              \
00222           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00223           break;                                              \
00224       }                                                       \
00225     }                                                         \
00226     else if((__HANDLE__)->Instance == USART2)                 \
00227     {                                                         \
00228       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00229       {                                                       \
00230         case RCC_USART2CLKSOURCE_PCLK1:                       \
00231           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00232           break;                                              \
00233         case RCC_USART2CLKSOURCE_HSI:                         \
00234           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00235           break;                                              \
00236         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00237           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00238           break;                                              \
00239         case RCC_USART2CLKSOURCE_LSE:                         \
00240           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00241           break;                                              \
00242         default:                                              \
00243           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00244           break;                                              \
00245       }                                                       \
00246     }                                                         \
00247     else if((__HANDLE__)->Instance == USART3)                 \
00248     {                                                         \
00249       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00250       {                                                       \
00251         case RCC_USART3CLKSOURCE_PCLK1:                       \
00252           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00253           break;                                              \
00254         case RCC_USART3CLKSOURCE_HSI:                         \
00255           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00256           break;                                              \
00257         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00258           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00259           break;                                              \
00260         case RCC_USART3CLKSOURCE_LSE:                         \
00261           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00262           break;                                              \
00263         default:                                              \
00264           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00265           break;                                              \
00266       }                                                       \
00267     }                                                         \
00268     else if((__HANDLE__)->Instance == USART4)                 \
00269     {                                                         \
00270       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00271     }                                                         \
00272     else if((__HANDLE__)->Instance == USART5)                 \
00273     {                                                         \
00274       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00275     }                                                         \
00276     else if((__HANDLE__)->Instance == USART6)                 \
00277     {                                                         \
00278       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00279     }                                                         \
00280     else if((__HANDLE__)->Instance == LPUART1)                \
00281     {                                                         \
00282       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00283       {                                                       \
00284         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00285           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00286           break;                                              \
00287         case RCC_LPUART1CLKSOURCE_HSI:                        \
00288           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00289           break;                                              \
00290         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00291           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00292           break;                                              \
00293         case RCC_LPUART1CLKSOURCE_LSE:                        \
00294           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00295           break;                                              \
00296         default:                                              \
00297           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00298           break;                                              \
00299       }                                                       \
00300     }                                                         \
00301     else if((__HANDLE__)->Instance == LPUART2)                \
00302     {                                                         \
00303       switch(__HAL_RCC_GET_LPUART2_SOURCE())                  \
00304       {                                                       \
00305         case RCC_LPUART2CLKSOURCE_PCLK1:                      \
00306           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00307           break;                                              \
00308         case RCC_LPUART2CLKSOURCE_HSI:                        \
00309           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00310           break;                                              \
00311         case RCC_LPUART2CLKSOURCE_SYSCLK:                     \
00312           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00313           break;                                              \
00314         case RCC_LPUART2CLKSOURCE_LSE:                        \
00315           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00316           break;                                              \
00317         default:                                              \
00318           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00319           break;                                              \
00320       }                                                       \
00321     }                                                         \
00322     else                                                      \
00323     {                                                         \
00324       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00325     }                                                         \
00326   } while(0U)
00327 #elif defined(STM32G0B0xx)
00328 /** @brief  Report the UART clock source.
00329   * @param  __HANDLE__ specifies the UART Handle.
00330   * @param  __CLOCKSOURCE__ output variable.
00331   * @retval UART clocking source, written in __CLOCKSOURCE__.
00332   */
00333 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00334   do {                                                        \
00335     if((__HANDLE__)->Instance == USART1)                      \
00336     {                                                         \
00337       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00338       {                                                       \
00339         case RCC_USART1CLKSOURCE_PCLK1:                       \
00340           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00341           break;                                              \
00342         case RCC_USART1CLKSOURCE_HSI:                         \
00343           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00344           break;                                              \
00345         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00346           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00347           break;                                              \
00348         case RCC_USART1CLKSOURCE_LSE:                         \
00349           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00350           break;                                              \
00351         default:                                              \
00352           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00353           break;                                              \
00354       }                                                       \
00355     }                                                         \
00356     else if((__HANDLE__)->Instance == USART2)                 \
00357     {                                                         \
00358       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00359       {                                                       \
00360         case RCC_USART2CLKSOURCE_PCLK1:                       \
00361           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00362           break;                                              \
00363         case RCC_USART2CLKSOURCE_HSI:                         \
00364           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00365           break;                                              \
00366         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00367           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00368           break;                                              \
00369         case RCC_USART2CLKSOURCE_LSE:                         \
00370           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00371           break;                                              \
00372         default:                                              \
00373           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00374           break;                                              \
00375       }                                                       \
00376     }                                                         \
00377     else if((__HANDLE__)->Instance == USART3)                 \
00378     {                                                         \
00379       switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00380       {                                                       \
00381         case RCC_USART3CLKSOURCE_PCLK1:                       \
00382           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00383           break;                                              \
00384         case RCC_USART3CLKSOURCE_HSI:                         \
00385           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00386           break;                                              \
00387         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00388           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00389           break;                                              \
00390         case RCC_USART3CLKSOURCE_LSE:                         \
00391           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00392           break;                                              \
00393         default:                                              \
00394           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00395           break;                                              \
00396       }                                                       \
00397     }                                                         \
00398     else if((__HANDLE__)->Instance == USART4)                 \
00399     {                                                         \
00400       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00401     }                                                         \
00402     else if((__HANDLE__)->Instance == USART5)                 \
00403     {                                                         \
00404       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00405     }                                                         \
00406     else if((__HANDLE__)->Instance == USART6)                 \
00407     {                                                         \
00408       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00409     }                                                         \
00410     else                                                      \
00411     {                                                         \
00412       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00413     }                                                         \
00414   } while(0U)
00415 #elif defined(STM32G081xx) || defined(STM32G071xx)
00416 /** @brief  Report the UART clock source.
00417   * @param  __HANDLE__ specifies the UART Handle.
00418   * @param  __CLOCKSOURCE__ output variable.
00419   * @retval UART clocking source, written in __CLOCKSOURCE__.
00420   */
00421 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00422   do {                                                        \
00423     if((__HANDLE__)->Instance == USART1)                      \
00424     {                                                         \
00425       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00426       {                                                       \
00427         case RCC_USART1CLKSOURCE_PCLK1:                       \
00428           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00429           break;                                              \
00430         case RCC_USART1CLKSOURCE_HSI:                         \
00431           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00432           break;                                              \
00433         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00434           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00435           break;                                              \
00436         case RCC_USART1CLKSOURCE_LSE:                         \
00437           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00438           break;                                              \
00439         default:                                              \
00440           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00441           break;                                              \
00442       }                                                       \
00443     }                                                         \
00444     else if((__HANDLE__)->Instance == USART2)                 \
00445     {                                                         \
00446       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00447       {                                                       \
00448         case RCC_USART2CLKSOURCE_PCLK1:                       \
00449           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00450           break;                                              \
00451         case RCC_USART2CLKSOURCE_HSI:                         \
00452           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00453           break;                                              \
00454         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00455           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00456           break;                                              \
00457         case RCC_USART2CLKSOURCE_LSE:                         \
00458           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00459           break;                                              \
00460         default:                                              \
00461           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00462           break;                                              \
00463       }                                                       \
00464     }                                                         \
00465     else if((__HANDLE__)->Instance == USART3)                 \
00466     {                                                         \
00467       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00468     }                                                         \
00469     else if((__HANDLE__)->Instance == USART4)                 \
00470     {                                                         \
00471       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00472     }                                                         \
00473     else if((__HANDLE__)->Instance == LPUART1)                \
00474     {                                                         \
00475       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00476       {                                                       \
00477         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00478           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00479           break;                                              \
00480         case RCC_LPUART1CLKSOURCE_HSI:                        \
00481           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00482           break;                                              \
00483         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00484           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00485           break;                                              \
00486         case RCC_LPUART1CLKSOURCE_LSE:                        \
00487           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00488           break;                                              \
00489         default:                                              \
00490           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00491           break;                                              \
00492       }                                                       \
00493     }                                                         \
00494     else                                                      \
00495     {                                                         \
00496       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00497     }                                                         \
00498   } while(0U)
00499 #elif defined(STM32G070xx)
00500 /** @brief  Report the UART clock source.
00501   * @param  __HANDLE__ specifies the UART Handle.
00502   * @param  __CLOCKSOURCE__ output variable.
00503   * @retval UART clocking source, written in __CLOCKSOURCE__.
00504   */
00505 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00506   do {                                                        \
00507     if((__HANDLE__)->Instance == USART1)                      \
00508     {                                                         \
00509       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00510       {                                                       \
00511         case RCC_USART1CLKSOURCE_PCLK1:                       \
00512           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00513           break;                                              \
00514         case RCC_USART1CLKSOURCE_HSI:                         \
00515           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00516           break;                                              \
00517         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00518           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00519           break;                                              \
00520         case RCC_USART1CLKSOURCE_LSE:                         \
00521           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00522           break;                                              \
00523         default:                                              \
00524           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00525           break;                                              \
00526       }                                                       \
00527     }                                                         \
00528     else if((__HANDLE__)->Instance == USART2)                 \
00529     {                                                         \
00530       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00531       {                                                       \
00532         case RCC_USART2CLKSOURCE_PCLK1:                       \
00533           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00534           break;                                              \
00535         case RCC_USART2CLKSOURCE_HSI:                         \
00536           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00537           break;                                              \
00538         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00539           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00540           break;                                              \
00541         case RCC_USART2CLKSOURCE_LSE:                         \
00542           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00543           break;                                              \
00544         default:                                              \
00545           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00546           break;                                              \
00547       }                                                       \
00548     }                                                         \
00549     else if((__HANDLE__)->Instance == USART3)                 \
00550     {                                                         \
00551       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00552     }                                                         \
00553     else if((__HANDLE__)->Instance == USART4)                 \
00554     {                                                         \
00555       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00556     }                                                         \
00557     else                                                      \
00558     {                                                         \
00559       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00560     }                                                         \
00561   } while(0U)
00562 #elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G051xx) || defined(STM32G061xx)
00563 /** @brief  Report the UART clock source.
00564   * @param  __HANDLE__ specifies the UART Handle.
00565   * @param  __CLOCKSOURCE__ output variable.
00566   * @retval UART clocking source, written in __CLOCKSOURCE__.
00567   */
00568 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00569   do {                                                        \
00570     if((__HANDLE__)->Instance == USART1)                      \
00571     {                                                         \
00572       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00573       {                                                       \
00574         case RCC_USART1CLKSOURCE_PCLK1:                       \
00575           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00576           break;                                              \
00577         case RCC_USART1CLKSOURCE_HSI:                         \
00578           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00579           break;                                              \
00580         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00581           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00582           break;                                              \
00583         case RCC_USART1CLKSOURCE_LSE:                         \
00584           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00585           break;                                              \
00586         default:                                              \
00587           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00588           break;                                              \
00589       }                                                       \
00590     }                                                         \
00591     else if((__HANDLE__)->Instance == USART2)                 \
00592     {                                                         \
00593       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00594     }                                                         \
00595     else if((__HANDLE__)->Instance == LPUART1)                \
00596     {                                                         \
00597       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00598       {                                                       \
00599         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00600           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00601           break;                                              \
00602         case RCC_LPUART1CLKSOURCE_HSI:                        \
00603           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00604           break;                                              \
00605         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00606           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00607           break;                                              \
00608         case RCC_LPUART1CLKSOURCE_LSE:                        \
00609           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00610           break;                                              \
00611         default:                                              \
00612           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00613           break;                                              \
00614       }                                                       \
00615     }                                                         \
00616     else                                                      \
00617     {                                                         \
00618       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00619     }                                                         \
00620   } while(0U)
00621 #elif defined(STM32G030xx) || defined(STM32G050xx)
00622 /** @brief  Report the UART clock source.
00623   * @param  __HANDLE__ specifies the UART Handle.
00624   * @param  __CLOCKSOURCE__ output variable.
00625   * @retval UART clocking source, written in __CLOCKSOURCE__.
00626   */
00627 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00628   do {                                                        \
00629     if((__HANDLE__)->Instance == USART1)                      \
00630     {                                                         \
00631       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00632       {                                                       \
00633         case RCC_USART1CLKSOURCE_PCLK1:                       \
00634           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00635           break;                                              \
00636         case RCC_USART1CLKSOURCE_HSI:                         \
00637           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00638           break;                                              \
00639         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00640           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00641           break;                                              \
00642         case RCC_USART1CLKSOURCE_LSE:                         \
00643           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00644           break;                                              \
00645         default:                                              \
00646           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00647           break;                                              \
00648       }                                                       \
00649     }                                                         \
00650     else if((__HANDLE__)->Instance == USART2)                 \
00651     {                                                         \
00652       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
00653     }                                                         \
00654     else                                                      \
00655     {                                                         \
00656       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00657     }                                                         \
00658   } while(0U)
00659 #endif /* STM32G0C1xx || STM32G0B1xx */
00660
00661 /** @brief  Report the UART mask to apply to retrieve the received data
00662   *         according to the word length and to the parity bits activation.
00663   * @note   If PCE = 1, the parity bit is not included in the data extracted
00664   *         by the reception API().
00665   *         This masking operation is not carried out in the case of
00666   *         DMA transfers.
00667   * @param  __HANDLE__ specifies the UART Handle.
00668   * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
00669   */
00670 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
00671   do {                                                                \
00672     if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
00673     {                                                                 \
00674       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00675       {                                                               \
00676         (__HANDLE__)->Mask = 0x01FFU ;                                \
00677       }                                                               \
00678       else                                                            \
00679       {                                                               \
00680         (__HANDLE__)->Mask = 0x00FFU ;                                \
00681       }                                                               \
00682     }                                                                 \
00683     else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
00684     {                                                                 \
00685       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00686       {                                                               \
00687         (__HANDLE__)->Mask = 0x00FFU ;                                \
00688       }                                                               \
00689       else                                                            \
00690       {                                                               \
00691         (__HANDLE__)->Mask = 0x007FU ;                                \
00692       }                                                               \
00693     }                                                                 \
00694     else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
00695     {                                                                 \
00696       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00697       {                                                               \
00698         (__HANDLE__)->Mask = 0x007FU ;                                \
00699       }                                                               \
00700       else                                                            \
00701       {                                                               \
00702         (__HANDLE__)->Mask = 0x003FU ;                                \
00703       }                                                               \
00704     }                                                                 \
00705     else                                                              \
00706     {                                                                 \
00707       (__HANDLE__)->Mask = 0x0000U;                                   \
00708     }                                                                 \
00709   } while(0U)
00710
00711 /**
00712   * @brief Ensure that UART frame length is valid.
00713   * @param __LENGTH__ UART frame length.
00714   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00715   */
00716 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
00717                                          ((__LENGTH__) == UART_WORDLENGTH_8B) || \
00718                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00719
00720 /**
00721   * @brief Ensure that UART wake-up address length is valid.
00722   * @param __ADDRESS__ UART wake-up address length.
00723   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
00724   */
00725 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
00726                                                    ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
00727
00728 /**
00729   * @brief Ensure that UART TXFIFO threshold level is valid.
00730   * @param __THRESHOLD__ UART TXFIFO threshold level.
00731   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00732   */
00733 #define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
00734                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
00735                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
00736                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
00737                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
00738                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
00739
00740 /**
00741   * @brief Ensure that UART RXFIFO threshold level is valid.
00742   * @param __THRESHOLD__ UART RXFIFO threshold level.
00743   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00744   */
00745 #define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
00746                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
00747                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
00748                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
00749                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
00750                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
00751
00752 /**
00753   * @}
00754   */
00755
00756 /* Private functions ---------------------------------------------------------*/
00757
00758 /**
00759   * @}
00760   */
00761
00762 /**
00763   * @}
00764   */
00765
00766 #ifdef __cplusplus
00767 }
00768 #endif
00769
00770 #endif /* STM32G0xx_HAL_UART_EX_H */
00771
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_usart.c Source File

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stm32g0xx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
00008   *          Peripheral (USART).
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State and Error functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * Copyright (c) 2018 STMicroelectronics.
00018   * All rights reserved.
00019   *
00020   * This software is licensed under terms that can be found in the LICENSE file
00021   * in the root directory of this software component.
00022   * If no LICENSE file comes with this software, it is provided AS-IS.
00023   *
00024   ******************************************************************************
00025   @verbatim
00026  ===============================================================================
00027                         ##### How to use this driver #####
00028  ===============================================================================
00029     [..]
00030       The USART HAL driver can be used as follows:
00031
00032       (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
00033       (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
00034           (++) Enable the USARTx interface clock.
00035           (++) USART pins configuration:
00036             (+++) Enable the clock for the USART GPIOs.
00037             (+++) Configure these USART pins as alternate function pull-up.
00038           (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00039                 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00040             (+++) Configure the USARTx interrupt priority.
00041             (+++) Enable the NVIC USART IRQ handle.
00042             (++) USART interrupts handling:
00043               -@@-   The specific USART interrupts (Transmission complete interrupt,
00044                   RXNE interrupt and Error Interrupts) will be managed using the macros
00045                   __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00046           (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00047                HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
00048             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00049             (+++) Enable the DMAx interface clock.
00050             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00051             (+++) Configure the DMA Tx/Rx channel.
00052             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00053             (+++) Configure the priority and enable the NVIC for the transfer
00054                   complete interrupt on the DMA Tx/Rx channel.
00055
00056       (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
00057           (Receiver/Transmitter) in the husart handle Init structure.
00058
00059       (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00060           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00061                by calling the customized HAL_USART_MspInit(&husart) API.
00062
00063     [..]
00064      (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
00065         HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
00066         HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
00067
00068     ##### Callback registration #####
00069     ==================================
00070
00071     [..]
00072     The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
00073     allows the user to configure dynamically the driver callbacks.
00074
00075     [..]
00076     Use Function HAL_USART_RegisterCallback() to register a user callback.
00077     Function HAL_USART_RegisterCallback() allows to register following callbacks:
00078     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00079     (+) TxCpltCallback            : Tx Complete Callback.
00080     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00081     (+) RxCpltCallback            : Rx Complete Callback.
00082     (+) TxRxCpltCallback          : Tx Rx Complete Callback.
00083     (+) ErrorCallback             : Error Callback.
00084     (+) AbortCpltCallback         : Abort Complete Callback.
00085     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00086     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00087     (+) MspInitCallback           : USART MspInit.
00088     (+) MspDeInitCallback         : USART MspDeInit.
00089     This function takes as parameters the HAL peripheral handle, the Callback ID
00090     and a pointer to the user callback function.
00091
00092     [..]
00093     Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
00094     weak (surcharged) function.
00095     HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00096     and the Callback ID.
00097     This function allows to reset following callbacks:
00098     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00099     (+) TxCpltCallback            : Tx Complete Callback.
00100     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00101     (+) RxCpltCallback            : Rx Complete Callback.
00102     (+) TxRxCpltCallback          : Tx Rx Complete Callback.
00103     (+) ErrorCallback             : Error Callback.
00104     (+) AbortCpltCallback         : Abort Complete Callback.
00105     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00106     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00107     (+) MspInitCallback           : USART MspInit.
00108     (+) MspDeInitCallback         : USART MspDeInit.
00109
00110     [..]
00111     By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
00112     all callbacks are set to the corresponding weak (surcharged) functions:
00113     examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
00114     Exception done for MspInit and MspDeInit functions that are respectively
00115     reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
00116     and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
00117     If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
00118     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00119
00120     [..]
00121     Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
00122     Exception done MspInit/MspDeInit that can be registered/unregistered
00123     in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
00124     MspInit/DeInit callbacks can be used during the Init/DeInit.
00125     In that case first register the MspInit/MspDeInit user callbacks
00126     using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
00127     or HAL_USART_Init() function.
00128
00129     [..]
00130     When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
00131     not defined, the callback registration feature is not available
00132     and weak (surcharged) callbacks are used.
00133
00134
00135   @endverbatim
00136   ******************************************************************************
00137   */
00138
00139 /* Includes ------------------------------------------------------------------*/
00140 #include "stm32g0xx_hal.h"
00141
00142 /** @addtogroup STM32G0xx_HAL_Driver
00143   * @{
00144   */
00145
00146 /** @defgroup USART USART
00147   * @brief HAL USART Synchronous module driver
00148   * @{
00149   */
00150
00151 #ifdef HAL_USART_MODULE_ENABLED
00152
00153 /* Private typedef -----------------------------------------------------------*/
00154 /* Private define ------------------------------------------------------------*/
00155 /** @defgroup USART_Private_Constants USART Private Constants
00156   * @{
00157   */
00158 #define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
00159 #define USART_TEACK_REACK_TIMEOUT             1000U             /*!< USART TX or RX enable acknowledge time-out value */
00160 #define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
00161                                               USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
00162                                               USART_CR1_FIFOEN ))                                  /*!< USART CR1 fields of parameters set by USART_SetConfig API */
00163
00164 #define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
00165                                               USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
00166                                               USART_CR2_DIS_NSS))                                  /*!< USART CR2 fields of parameters set by USART_SetConfig API */
00167
00168 #define USART_CR3_FIELDS          ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))             /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */
00169
00170 #define USART_BRR_MIN    0x10U        /* USART BRR minimum authorized value */
00171 #define USART_BRR_MAX    0xFFFFU      /* USART BRR maximum authorized value */
00172 /**
00173   * @}
00174   */
00175
00176 /* Private macros ------------------------------------------------------------*/
00177 /* Private variables ---------------------------------------------------------*/
00178 /* Private function prototypes -----------------------------------------------*/
00179 /** @addtogroup USART_Private_Functions
00180   * @{
00181   */
00182 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00183 void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
00184 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00185 static void USART_EndTransfer(USART_HandleTypeDef *husart);
00186 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00187 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00188 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00189 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00190 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00191 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00192 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00193 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00194 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
00195                                                       uint32_t Tickstart, uint32_t Timeout);
00196 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
00197 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
00198 static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
00199 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
00200 static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
00201 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
00202 static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00203 static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
00204 static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
00205 static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
00206 static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
00207
00208
00209 /**
00210   * @}
00211   */
00212
00213 /* Exported functions --------------------------------------------------------*/
00214
00215 /** @defgroup USART_Exported_Functions USART Exported Functions
00216   * @{
00217   */
00218
00219 /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00220   * @brief    Initialization and Configuration functions
00221   *
00222 @verbatim
00223  ===============================================================================
00224             ##### Initialization and Configuration functions #####
00225  ===============================================================================
00226     [..]
00227     This subsection provides a set of functions allowing to initialize the USART
00228     in asynchronous and in synchronous modes.
00229       (+) For the asynchronous mode only these parameters can be configured:
00230         (++) Baud Rate
00231         (++) Word Length
00232         (++) Stop Bit
00233         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00234              in the data register is transmitted but is changed by the parity bit.
00235         (++) USART polarity
00236         (++) USART phase
00237         (++) USART LastBit
00238         (++) Receiver/transmitter modes
00239
00240     [..]
00241     The HAL_USART_Init() function follows the USART  synchronous configuration
00242     procedure (details for the procedure are available in reference manual).
00243
00244 @endverbatim
00245
00246   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00247   8-bit or 9-bit), the possible USART formats are listed in the
00248   following table.
00249
00250     Table 1. USART frame format.
00251     +-----------------------------------------------------------------------+
00252     |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
00253     |---------|---------|-----------|---------------------------------------|
00254     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00255     |---------|---------|-----------|---------------------------------------|
00256     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00257     |---------|---------|-----------|---------------------------------------|
00258     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00259     |---------|---------|-----------|---------------------------------------|
00260     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00261     |---------|---------|-----------|---------------------------------------|
00262     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00263     |---------|---------|-----------|---------------------------------------|
00264     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00265     +-----------------------------------------------------------------------+
00266
00267   * @{
00268   */
00269
00270 /**
00271   * @brief  Initialize the USART mode according to the specified
00272   *         parameters in the USART_InitTypeDef and initialize the associated handle.
00273   * @param  husart USART handle.
00274   * @retval HAL status
00275   */
00276 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00277 {
00278   /* Check the USART handle allocation */
00279   if (husart == NULL)
00280   {
00281     return HAL_ERROR;
00282   }
00283
00284   /* Check the parameters */
00285   assert_param(IS_USART_INSTANCE(husart->Instance));
00286
00287   if (husart->State == HAL_USART_STATE_RESET)
00288   {
00289     /* Allocate lock resource and initialize it */
00290     husart->Lock = HAL_UNLOCKED;
00291
00292 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00293     USART_InitCallbacksToDefault(husart);
00294
00295     if (husart->MspInitCallback == NULL)
00296     {
00297       husart->MspInitCallback = HAL_USART_MspInit;
00298     }
00299
00300     /* Init the low level hardware */
00301     husart->MspInitCallback(husart);
00302 #else
00303     /* Init the low level hardware : GPIO, CLOCK */
00304     HAL_USART_MspInit(husart);
00305 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00306   }
00307
00308   husart->State = HAL_USART_STATE_BUSY;
00309
00310   /* Disable the Peripheral */
00311   __HAL_USART_DISABLE(husart);
00312
00313   /* Set the Usart Communication parameters */
00314   if (USART_SetConfig(husart) == HAL_ERROR)
00315   {
00316     return HAL_ERROR;
00317   }
00318
00319   /* In Synchronous mode, the following bits must be kept cleared:
00320   - LINEN bit in the USART_CR2 register
00321   - HDSEL, SCEN and IREN bits in the USART_CR3 register.
00322   */
00323   husart->Instance->CR2 &= ~USART_CR2_LINEN;
00324   husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00325
00326   /* Enable the Peripheral */
00327   __HAL_USART_ENABLE(husart);
00328
00329   /* TEACK and/or REACK to check before moving husart->State to Ready */
00330   return (USART_CheckIdleState(husart));
00331 }
00332
00333 /**
00334   * @brief DeInitialize the USART peripheral.
00335   * @param  husart USART handle.
00336   * @retval HAL status
00337   */
00338 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00339 {
00340   /* Check the USART handle allocation */
00341   if (husart == NULL)
00342   {
00343     return HAL_ERROR;
00344   }
00345
00346   /* Check the parameters */
00347   assert_param(IS_USART_INSTANCE(husart->Instance));
00348
00349   husart->State = HAL_USART_STATE_BUSY;
00350
00351   husart->Instance->CR1 = 0x0U;
00352   husart->Instance->CR2 = 0x0U;
00353   husart->Instance->CR3 = 0x0U;
00354
00355 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00356   if (husart->MspDeInitCallback == NULL)
00357   {
00358     husart->MspDeInitCallback = HAL_USART_MspDeInit;
00359   }
00360   /* DeInit the low level hardware */
00361   husart->MspDeInitCallback(husart);
00362 #else
00363   /* DeInit the low level hardware */
00364   HAL_USART_MspDeInit(husart);
00365 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00366
00367   husart->ErrorCode = HAL_USART_ERROR_NONE;
00368   husart->State = HAL_USART_STATE_RESET;
00369
00370   /* Process Unlock */
00371   __HAL_UNLOCK(husart);
00372
00373   return HAL_OK;
00374 }
00375
00376 /**
00377   * @brief Initialize the USART MSP.
00378   * @param husart USART handle.
00379   * @retval None
00380   */
00381 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00382 {
00383   /* Prevent unused argument(s) compilation warning */
00384   UNUSED(husart);
00385
00386   /* NOTE : This function should not be modified, when the callback is needed,
00387             the HAL_USART_MspInit can be implemented in the user file
00388    */
00389 }
00390
00391 /**
00392   * @brief DeInitialize the USART MSP.
00393   * @param husart USART handle.
00394   * @retval None
00395   */
00396 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00397 {
00398   /* Prevent unused argument(s) compilation warning */
00399   UNUSED(husart);
00400
00401   /* NOTE : This function should not be modified, when the callback is needed,
00402             the HAL_USART_MspDeInit can be implemented in the user file
00403    */
00404 }
00405
00406 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00407 /**
00408   * @brief  Register a User USART Callback
00409   *         To be used instead of the weak predefined callback
00410   * @param  husart usart handle
00411   * @param  CallbackID ID of the callback to be registered
00412   *         This parameter can be one of the following values:
00413   *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00414   *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00415   *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00416   *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00417   *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
00418   *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
00419   *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00420   *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00421   *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00422   *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
00423   *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
00424   * @param  pCallback pointer to the Callback function
00425   * @retval HAL status
00426 +  */
00427 HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
00428                                              pUSART_CallbackTypeDef pCallback)
00429 {
00430   HAL_StatusTypeDef status = HAL_OK;
00431
00432   if (pCallback == NULL)
00433   {
00434     /* Update the error code */
00435     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00436
00437     return HAL_ERROR;
00438   }
00439   /* Process locked */
00440   __HAL_LOCK(husart);
00441
00442   if (husart->State == HAL_USART_STATE_READY)
00443   {
00444     switch (CallbackID)
00445     {
00446       case HAL_USART_TX_HALFCOMPLETE_CB_ID :
00447         husart->TxHalfCpltCallback = pCallback;
00448         break;
00449
00450       case HAL_USART_TX_COMPLETE_CB_ID :
00451         husart->TxCpltCallback = pCallback;
00452         break;
00453
00454       case HAL_USART_RX_HALFCOMPLETE_CB_ID :
00455         husart->RxHalfCpltCallback = pCallback;
00456         break;
00457
00458       case HAL_USART_RX_COMPLETE_CB_ID :
00459         husart->RxCpltCallback = pCallback;
00460         break;
00461
00462       case HAL_USART_TX_RX_COMPLETE_CB_ID :
00463         husart->TxRxCpltCallback = pCallback;
00464         break;
00465
00466       case HAL_USART_ERROR_CB_ID :
00467         husart->ErrorCallback = pCallback;
00468         break;
00469
00470       case HAL_USART_ABORT_COMPLETE_CB_ID :
00471         husart->AbortCpltCallback = pCallback;
00472         break;
00473
00474       case HAL_USART_RX_FIFO_FULL_CB_ID :
00475         husart->RxFifoFullCallback = pCallback;
00476         break;
00477
00478       case HAL_USART_TX_FIFO_EMPTY_CB_ID :
00479         husart->TxFifoEmptyCallback = pCallback;
00480         break;
00481
00482       case HAL_USART_MSPINIT_CB_ID :
00483         husart->MspInitCallback = pCallback;
00484         break;
00485
00486       case HAL_USART_MSPDEINIT_CB_ID :
00487         husart->MspDeInitCallback = pCallback;
00488         break;
00489
00490       default :
00491         /* Update the error code */
00492         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00493
00494         /* Return error status */
00495         status =  HAL_ERROR;
00496         break;
00497     }
00498   }
00499   else if (husart->State == HAL_USART_STATE_RESET)
00500   {
00501     switch (CallbackID)
00502     {
00503       case HAL_USART_MSPINIT_CB_ID :
00504         husart->MspInitCallback = pCallback;
00505         break;
00506
00507       case HAL_USART_MSPDEINIT_CB_ID :
00508         husart->MspDeInitCallback = pCallback;
00509         break;
00510
00511       default :
00512         /* Update the error code */
00513         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00514
00515         /* Return error status */
00516         status =  HAL_ERROR;
00517         break;
00518     }
00519   }
00520   else
00521   {
00522     /* Update the error code */
00523     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00524
00525     /* Return error status */
00526     status =  HAL_ERROR;
00527   }
00528
00529   /* Release Lock */
00530   __HAL_UNLOCK(husart);
00531
00532   return status;
00533 }
00534
00535 /**
00536   * @brief  Unregister an USART Callback
00537   *         USART callaback is redirected to the weak predefined callback
00538   * @param  husart usart handle
00539   * @param  CallbackID ID of the callback to be unregistered
00540   *         This parameter can be one of the following values:
00541   *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00542   *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00543   *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00544   *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00545   *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
00546   *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
00547   *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00548   *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00549   *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00550   *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
00551   *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
00552   * @retval HAL status
00553   */
00554 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
00555 {
00556   HAL_StatusTypeDef status = HAL_OK;
00557
00558   /* Process locked */
00559   __HAL_LOCK(husart);
00560
00561   if (HAL_USART_STATE_READY == husart->State)
00562   {
00563     switch (CallbackID)
00564     {
00565       case HAL_USART_TX_HALFCOMPLETE_CB_ID :
00566         husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback  */
00567         break;
00568
00569       case HAL_USART_TX_COMPLETE_CB_ID :
00570         husart->TxCpltCallback = HAL_USART_TxCpltCallback;                       /* Legacy weak TxCpltCallback       */
00571         break;
00572
00573       case HAL_USART_RX_HALFCOMPLETE_CB_ID :
00574         husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback   */
00575         break;
00576
00577       case HAL_USART_RX_COMPLETE_CB_ID :
00578         husart->RxCpltCallback = HAL_USART_RxCpltCallback;                       /* Legacy weak RxCpltCallback       */
00579         break;
00580
00581       case HAL_USART_TX_RX_COMPLETE_CB_ID :
00582         husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback;                   /* Legacy weak TxRxCpltCallback     */
00583         break;
00584
00585       case HAL_USART_ERROR_CB_ID :
00586         husart->ErrorCallback = HAL_USART_ErrorCallback;                         /* Legacy weak ErrorCallback        */
00587         break;
00588
00589       case HAL_USART_ABORT_COMPLETE_CB_ID :
00590         husart->AbortCpltCallback = HAL_USART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback    */
00591         break;
00592
00593       case HAL_USART_RX_FIFO_FULL_CB_ID :
00594         husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback   */
00595         break;
00596
00597       case HAL_USART_TX_FIFO_EMPTY_CB_ID :
00598         husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback  */
00599         break;
00600
00601       case HAL_USART_MSPINIT_CB_ID :
00602         husart->MspInitCallback = HAL_USART_MspInit;                             /* Legacy weak MspInitCallback      */
00603         break;
00604
00605       case HAL_USART_MSPDEINIT_CB_ID :
00606         husart->MspDeInitCallback = HAL_USART_MspDeInit;                         /* Legacy weak MspDeInitCallback    */
00607         break;
00608
00609       default :
00610         /* Update the error code */
00611         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00612
00613         /* Return error status */
00614         status =  HAL_ERROR;
00615         break;
00616     }
00617   }
00618   else if (HAL_USART_STATE_RESET == husart->State)
00619   {
00620     switch (CallbackID)
00621     {
00622       case HAL_USART_MSPINIT_CB_ID :
00623         husart->MspInitCallback = HAL_USART_MspInit;
00624         break;
00625
00626       case HAL_USART_MSPDEINIT_CB_ID :
00627         husart->MspDeInitCallback = HAL_USART_MspDeInit;
00628         break;
00629
00630       default :
00631         /* Update the error code */
00632         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00633
00634         /* Return error status */
00635         status =  HAL_ERROR;
00636         break;
00637     }
00638   }
00639   else
00640   {
00641     /* Update the error code */
00642     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00643
00644     /* Return error status */
00645     status =  HAL_ERROR;
00646   }
00647
00648   /* Release Lock */
00649   __HAL_UNLOCK(husart);
00650
00651   return status;
00652 }
00653 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00654
00655
00656 /**
00657   * @}
00658   */
00659
00660 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00661   * @brief   USART Transmit and Receive functions
00662   *
00663 @verbatim
00664  ===============================================================================
00665                       ##### IO operation functions #####
00666  ===============================================================================
00667     [..] This subsection provides a set of functions allowing to manage the USART synchronous
00668     data transfers.
00669
00670     [..] The USART supports master mode only: it cannot receive or send data related to an input
00671          clock (SCLK is always an output).
00672
00673     [..]
00674
00675     (#) There are two modes of transfer:
00676         (++) Blocking mode: The communication is performed in polling mode.
00677              The HAL status of all data processing is returned by the same function
00678              after finishing transfer.
00679         (++) No-Blocking mode: The communication is performed using Interrupts
00680              or DMA, These API's return the HAL status.
00681              The end of the data processing will be indicated through the
00682              dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00683              using DMA mode.
00684              The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
00685              will be executed respectively at the end of the transmit or Receive process
00686              The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
00687
00688     (#) Blocking mode API's are :
00689         (++) HAL_USART_Transmit() in simplex mode
00690         (++) HAL_USART_Receive() in full duplex receive only
00691         (++) HAL_USART_TransmitReceive() in full duplex mode
00692
00693     (#) Non-Blocking mode API's with Interrupt are :
00694         (++) HAL_USART_Transmit_IT() in simplex mode
00695         (++) HAL_USART_Receive_IT() in full duplex receive only
00696         (++) HAL_USART_TransmitReceive_IT() in full duplex mode
00697         (++) HAL_USART_IRQHandler()
00698
00699     (#) No-Blocking mode API's  with DMA are :
00700         (++) HAL_USART_Transmit_DMA() in simplex mode
00701         (++) HAL_USART_Receive_DMA() in full duplex receive only
00702         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00703         (++) HAL_USART_DMAPause()
00704         (++) HAL_USART_DMAResume()
00705         (++) HAL_USART_DMAStop()
00706
00707     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00708         (++) HAL_USART_TxCpltCallback()
00709         (++) HAL_USART_RxCpltCallback()
00710         (++) HAL_USART_TxHalfCpltCallback()
00711         (++) HAL_USART_RxHalfCpltCallback()
00712         (++) HAL_USART_ErrorCallback()
00713         (++) HAL_USART_TxRxCpltCallback()
00714
00715     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00716         (++) HAL_USART_Abort()
00717         (++) HAL_USART_Abort_IT()
00718
00719     (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
00720         (++) HAL_USART_AbortCpltCallback()
00721
00722     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00723         Errors are handled as follows :
00724         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00725              to be evaluated by user : this concerns Frame Error,
00726              Parity Error or Noise Error in Interrupt mode reception .
00727              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
00728              error type, and HAL_USART_ErrorCallback() user callback is executed.
00729              Transfer is kept ongoing on USART side.
00730              If user wants to abort it, Abort services should be called by user.
00731         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00732              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00733              Error code is set to allow user to identify error type,
00734              and HAL_USART_ErrorCallback() user callback is executed.
00735
00736 @endverbatim
00737   * @{
00738   */
00739
00740 /**
00741   * @brief  Simplex send an amount of data in blocking mode.
00742   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00743   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
00744   *         of u16 provided through pTxData.
00745   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00746   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
00747   *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
00748   *         use of specific alignment compilation directives or pragmas might be required
00749   *         to ensure proper alignment for pTxData.
00750   * @param  husart USART handle.
00751   * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
00752   * @param  Size Amount of data elements (u8 or u16) to be sent.
00753   * @param  Timeout Timeout duration.
00754   * @retval HAL status
00755   */
00756 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
00757                                      uint32_t Timeout)
00758 {
00759   const uint8_t  *ptxdata8bits;
00760   const uint16_t *ptxdata16bits;
00761   uint32_t tickstart;
00762
00763   if (husart->State == HAL_USART_STATE_READY)
00764   {
00765     if ((pTxData == NULL) || (Size == 0U))
00766     {
00767       return  HAL_ERROR;
00768     }
00769
00770     /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
00771        should be aligned on a u16 frontier, as data to be filled into TDR will be
00772        handled through a u16 cast. */
00773     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00774     {
00775       if ((((uint32_t)pTxData) & 1U) != 0U)
00776       {
00777         return  HAL_ERROR;
00778       }
00779     }
00780
00781     /* Process Locked */
00782     __HAL_LOCK(husart);
00783
00784     husart->ErrorCode = HAL_USART_ERROR_NONE;
00785     husart->State = HAL_USART_STATE_BUSY_TX;
00786
00787     /* Init tickstart for timeout management */
00788     tickstart = HAL_GetTick();
00789
00790     husart->TxXferSize = Size;
00791     husart->TxXferCount = Size;
00792
00793     /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
00794     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00795     {
00796       ptxdata8bits  = NULL;
00797       ptxdata16bits = (const uint16_t *) pTxData;
00798     }
00799     else
00800     {
00801       ptxdata8bits  = pTxData;
00802       ptxdata16bits = NULL;
00803     }
00804
00805     /* Check the remaining data to be sent */
00806     while (husart->TxXferCount > 0U)
00807     {
00808       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00809       {
00810         return HAL_TIMEOUT;
00811       }
00812       if (ptxdata8bits == NULL)
00813       {
00814         husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
00815         ptxdata16bits++;
00816       }
00817       else
00818       {
00819         husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
00820         ptxdata8bits++;
00821       }
00822
00823       husart->TxXferCount--;
00824     }
00825
00826     if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00827     {
00828       return HAL_TIMEOUT;
00829     }
00830
00831     /* Clear Transmission Complete Flag */
00832     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
00833
00834     /* Clear overrun flag and discard the received data */
00835     __HAL_USART_CLEAR_OREFLAG(husart);
00836     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
00837     __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
00838
00839     /* At end of Tx process, restore husart->State to Ready */
00840     husart->State = HAL_USART_STATE_READY;
00841
00842     /* Process Unlocked */
00843     __HAL_UNLOCK(husart);
00844
00845     return HAL_OK;
00846   }
00847   else
00848   {
00849     return HAL_BUSY;
00850   }
00851 }
00852
00853 /**
00854   * @brief Receive an amount of data in blocking mode.
00855   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
00856   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00857   *         the received data is handled as a set of u16. In this case, Size must indicate the number
00858   *         of u16 available through pRxData.
00859   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00860   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
00861   *         (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
00862   *         use of specific alignment compilation directives or pragmas might be required to ensure
00863   *         proper alignment for pRxData.
00864   * @param husart USART handle.
00865   * @param pRxData Pointer to data buffer (u8 or u16 data elements).
00866   * @param Size Amount of data elements (u8 or u16) to be received.
00867   * @param Timeout Timeout duration.
00868   * @retval HAL status
00869   */
00870 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00871 {
00872   uint8_t  *prxdata8bits;
00873   uint16_t *prxdata16bits;
00874   uint16_t uhMask;
00875   uint32_t tickstart;
00876
00877   if (husart->State == HAL_USART_STATE_READY)
00878   {
00879     if ((pRxData == NULL) || (Size == 0U))
00880     {
00881       return  HAL_ERROR;
00882     }
00883
00884     /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
00885        should be aligned on a u16 frontier, as data to be received from RDR will be
00886        handled through a u16 cast. */
00887     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00888     {
00889       if ((((uint32_t)pRxData) & 1U) != 0U)
00890       {
00891         return  HAL_ERROR;
00892       }
00893     }
00894
00895     /* Process Locked */
00896     __HAL_LOCK(husart);
00897
00898     husart->ErrorCode = HAL_USART_ERROR_NONE;
00899     husart->State = HAL_USART_STATE_BUSY_RX;
00900
00901     /* Init tickstart for timeout management */
00902     tickstart = HAL_GetTick();
00903
00904     husart->RxXferSize = Size;
00905     husart->RxXferCount = Size;
00906
00907     /* Computation of USART mask to apply to RDR register */
00908     USART_MASK_COMPUTATION(husart);
00909     uhMask = husart->Mask;
00910
00911     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00912     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00913     {
00914       prxdata8bits  = NULL;
00915       prxdata16bits = (uint16_t *) pRxData;
00916     }
00917     else
00918     {
00919       prxdata8bits  = pRxData;
00920       prxdata16bits = NULL;
00921     }
00922
00923     /* as long as data have to be received */
00924     while (husart->RxXferCount > 0U)
00925     {
00926       if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
00927       {
00928         /* Wait until TXE flag is set to send dummy byte in order to generate the
00929         * clock for the slave to send data.
00930         * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
00931         * can be written for all the cases. */
00932         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00933         {
00934           return HAL_TIMEOUT;
00935         }
00936         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
00937       }
00938
00939       /* Wait for RXNE Flag */
00940       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00941       {
00942         return HAL_TIMEOUT;
00943       }
00944
00945       if (prxdata8bits == NULL)
00946       {
00947         *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
00948         prxdata16bits++;
00949       }
00950       else
00951       {
00952         *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
00953         prxdata8bits++;
00954       }
00955
00956       husart->RxXferCount--;
00957
00958     }
00959
00960     /* Clear SPI slave underrun flag and discard transmit data */
00961     if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
00962     {
00963       __HAL_USART_CLEAR_UDRFLAG(husart);
00964       __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
00965     }
00966
00967     /* At end of Rx process, restore husart->State to Ready */
00968     husart->State = HAL_USART_STATE_READY;
00969
00970     /* Process Unlocked */
00971     __HAL_UNLOCK(husart);
00972
00973     return HAL_OK;
00974   }
00975   else
00976   {
00977     return HAL_BUSY;
00978   }
00979 }
00980
00981 /**
00982   * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
00983   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00984   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
00985   *         of u16 available through pTxData and through pRxData.
00986   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00987   *         address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
00988   *         (16 bits) (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
00989   *         use of specific alignment compilation directives or pragmas might be required to ensure
00990   *         proper alignment for pTxData and pRxData.
00991   * @param  husart USART handle.
00992   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
00993   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
00994   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
00995   * @param  Timeout Timeout duration.
00996   * @retval HAL status
00997   */
00998 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
00999                                             uint16_t Size, uint32_t Timeout)
01000 {
01001   uint8_t  *prxdata8bits;
01002   uint16_t *prxdata16bits;
01003   const uint8_t  *ptxdata8bits;
01004   const uint16_t *ptxdata16bits;
01005   uint16_t uhMask;
01006   uint16_t rxdatacount;
01007   uint32_t tickstart;
01008
01009   if (husart->State == HAL_USART_STATE_READY)
01010   {
01011     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01012     {
01013       return  HAL_ERROR;
01014     }
01015
01016     /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
01017        should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
01018        handled through a u16 cast. */
01019     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01020     {
01021       if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
01022       {
01023         return  HAL_ERROR;
01024       }
01025     }
01026
01027     /* Process Locked */
01028     __HAL_LOCK(husart);
01029
01030     husart->ErrorCode = HAL_USART_ERROR_NONE;
01031     husart->State = HAL_USART_STATE_BUSY_RX;
01032
01033     /* Init tickstart for timeout management */
01034     tickstart = HAL_GetTick();
01035
01036     husart->RxXferSize = Size;
01037     husart->TxXferSize = Size;
01038     husart->TxXferCount = Size;
01039     husart->RxXferCount = Size;
01040
01041     /* Computation of USART mask to apply to RDR register */
01042     USART_MASK_COMPUTATION(husart);
01043     uhMask = husart->Mask;
01044
01045     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
01046     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01047     {
01048       prxdata8bits  = NULL;
01049       ptxdata8bits  = NULL;
01050       ptxdata16bits = (const uint16_t *) pTxData;
01051       prxdata16bits = (uint16_t *) pRxData;
01052     }
01053     else
01054     {
01055       prxdata8bits  = pRxData;
01056       ptxdata8bits  = pTxData;
01057       ptxdata16bits = NULL;
01058       prxdata16bits = NULL;
01059     }
01060
01061     if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE))
01062     {
01063       /* Wait until TXE flag is set to send data */
01064       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01065       {
01066         return HAL_TIMEOUT;
01067       }
01068       if (ptxdata8bits == NULL)
01069       {
01070         husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
01071         ptxdata16bits++;
01072       }
01073       else
01074       {
01075         husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
01076         ptxdata8bits++;
01077       }
01078
01079       husart->TxXferCount--;
01080     }
01081
01082     /* Check the remain data to be sent */
01083     /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
01084     rxdatacount = husart->RxXferCount;
01085     while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
01086     {
01087       if (husart->TxXferCount > 0U)
01088       {
01089         /* Wait until TXE flag is set to send data */
01090         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01091         {
01092           return HAL_TIMEOUT;
01093         }
01094         if (ptxdata8bits == NULL)
01095         {
01096           husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
01097           ptxdata16bits++;
01098         }
01099         else
01100         {
01101           husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
01102           ptxdata8bits++;
01103         }
01104
01105         husart->TxXferCount--;
01106       }
01107
01108       if (husart->RxXferCount > 0U)
01109       {
01110         /* Wait for RXNE Flag */
01111         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
01112         {
01113           return HAL_TIMEOUT;
01114         }
01115
01116         if (prxdata8bits == NULL)
01117         {
01118           *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
01119           prxdata16bits++;
01120         }
01121         else
01122         {
01123           *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
01124           prxdata8bits++;
01125         }
01126
01127         husart->RxXferCount--;
01128       }
01129       rxdatacount = husart->RxXferCount;
01130     }
01131
01132     /* At end of TxRx process, restore husart->State to Ready */
01133     husart->State = HAL_USART_STATE_READY;
01134
01135     /* Process Unlocked */
01136     __HAL_UNLOCK(husart);
01137
01138     return HAL_OK;
01139   }
01140   else
01141   {
01142     return HAL_BUSY;
01143   }
01144 }
01145
01146 /**
01147   * @brief  Send an amount of data in interrupt mode.
01148   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01149   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01150   *         of u16 provided through pTxData.
01151   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01152   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier
01153   *         (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
01154   *         use of specific alignment compilation directives or pragmas might be required to ensure
01155   *         proper alignment for pTxData.
01156   * @param  husart USART handle.
01157   * @param  pTxData pointer to data buffer (u8 or u16 data elements).
01158   * @param  Size amount of data elements (u8 or u16) to be sent.
01159   * @retval HAL status
01160   */
01161 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
01162 {
01163   if (husart->State == HAL_USART_STATE_READY)
01164   {
01165     if ((pTxData == NULL) || (Size == 0U))
01166     {
01167       return HAL_ERROR;
01168     }
01169
01170     /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
01171        should be aligned on a u16 frontier, as data to be filled into TDR will be
01172        handled through a u16 cast. */
01173     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01174     {
01175       if ((((uint32_t)pTxData) & 1U) != 0U)
01176       {
01177         return  HAL_ERROR;
01178       }
01179     }
01180
01181     /* Process Locked */
01182     __HAL_LOCK(husart);
01183
01184     husart->pTxBuffPtr  = pTxData;
01185     husart->TxXferSize  = Size;
01186     husart->TxXferCount = Size;
01187     husart->TxISR       = NULL;
01188
01189     husart->ErrorCode = HAL_USART_ERROR_NONE;
01190     husart->State     = HAL_USART_STATE_BUSY_TX;
01191
01192     /* The USART Error Interrupts: (Frame error, noise error, overrun error)
01193     are not managed by the USART Transmit Process to avoid the overrun interrupt
01194     when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
01195     to benefit for the frame error and noise interrupts the usart mode should be
01196     configured only for transmit "USART_MODE_TX" */
01197
01198     /* Configure Tx interrupt processing */
01199     if (husart->FifoMode == USART_FIFOMODE_ENABLE)
01200     {
01201       /* Set the Tx ISR function pointer according to the data word length */
01202       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01203       {
01204         husart->TxISR = USART_TxISR_16BIT_FIFOEN;
01205       }
01206       else
01207       {
01208         husart->TxISR = USART_TxISR_8BIT_FIFOEN;
01209       }
01210
01211       /* Process Unlocked */
01212       __HAL_UNLOCK(husart);
01213
01214       /* Enable the TX FIFO threshold interrupt */
01215       __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT);
01216     }
01217     else
01218     {
01219       /* Set the Tx ISR function pointer according to the data word length */
01220       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01221       {
01222         husart->TxISR = USART_TxISR_16BIT;
01223       }
01224       else
01225       {
01226         husart->TxISR = USART_TxISR_8BIT;
01227       }
01228
01229       /* Process Unlocked */
01230       __HAL_UNLOCK(husart);
01231
01232       /* Enable the USART Transmit Data Register Empty Interrupt */
01233       __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
01234     }
01235
01236     return HAL_OK;
01237   }
01238   else
01239   {
01240     return HAL_BUSY;
01241   }
01242 }
01243
01244 /**
01245   * @brief Receive an amount of data in interrupt mode.
01246   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
01247   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01248   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01249   *         of u16 available through pRxData.
01250   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01251   *         address of user data buffer for storing data to be received, should be aligned on a half word frontier
01252   *         (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
01253   *         use of specific alignment compilation directives or pragmas might be required to ensure
01254   *         proper alignment for pRxData.
01255   * @param  husart USART handle.
01256   * @param  pRxData pointer to data buffer (u8 or u16 data elements).
01257   * @param  Size amount of data elements (u8 or u16) to be received.
01258   * @retval HAL status
01259   */
01260 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
01261 {
01262   uint16_t nb_dummy_data;
01263
01264   if (husart->State == HAL_USART_STATE_READY)
01265   {
01266     if ((pRxData == NULL) || (Size == 0U))
01267     {
01268       return HAL_ERROR;
01269     }
01270
01271     /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
01272        should be aligned on a u16 frontier, as data to be received from RDR will be
01273        handled through a u16 cast. */
01274     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01275     {
01276       if ((((uint32_t)pRxData) & 1U) != 0U)
01277       {
01278         return  HAL_ERROR;
01279       }
01280     }
01281
01282     /* Process Locked */
01283     __HAL_LOCK(husart);
01284
01285     husart->pRxBuffPtr  = pRxData;
01286     husart->RxXferSize  = Size;
01287     husart->RxXferCount = Size;
01288     husart->RxISR       = NULL;
01289
01290     USART_MASK_COMPUTATION(husart);
01291
01292     husart->ErrorCode = HAL_USART_ERROR_NONE;
01293     husart->State = HAL_USART_STATE_BUSY_RX;
01294
01295     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01296     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01297
01298     /* Configure Rx interrupt processing */
01299     if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01300     {
01301       /* Set the Rx ISR function pointer according to the data word length */
01302       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01303       {
01304         husart->RxISR = USART_RxISR_16BIT_FIFOEN;
01305       }
01306       else
01307       {
01308         husart->RxISR = USART_RxISR_8BIT_FIFOEN;
01309       }
01310
01311       /* Process Unlocked */
01312       __HAL_UNLOCK(husart);
01313
01314       /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
01315       if (husart->Init.Parity != USART_PARITY_NONE)
01316       {
01317         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01318       }
01319       SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
01320     }
01321     else
01322     {
01323       /* Set the Rx ISR function pointer according to the data word length */
01324       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01325       {
01326         husart->RxISR = USART_RxISR_16BIT;
01327       }
01328       else
01329       {
01330         husart->RxISR = USART_RxISR_8BIT;
01331       }
01332
01333       /* Process Unlocked */
01334       __HAL_UNLOCK(husart);
01335
01336       /* Enable the USART Parity Error and Data Register not empty Interrupts */
01337       if (husart->Init.Parity != USART_PARITY_NONE)
01338       {
01339         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01340       }
01341       else
01342       {
01343         SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
01344       }
01345     }
01346
01347     if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
01348     {
01349       /* Send dummy data in order to generate the clock for the Slave to send the next data.
01350          When FIFO mode is disabled only one data must be transferred.
01351          When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold.
01352       */
01353       if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01354       {
01355         for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--)
01356         {
01357           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01358         }
01359       }
01360       else
01361       {
01362         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01363       }
01364     }
01365
01366     return HAL_OK;
01367   }
01368   else
01369   {
01370     return HAL_BUSY;
01371   }
01372 }
01373
01374 /**
01375   * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
01376   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01377   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
01378   *         of u16 available through pTxData and through pRxData.
01379   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01380   *         address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
01381   *         (16 bits) (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
01382   *         use of specific alignment compilation directives or pragmas might be required to ensure
01383   *         proper alignment for pTxData and pRxData.
01384   * @param  husart USART handle.
01385   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
01386   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
01387   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
01388   * @retval HAL status
01389   */
01390 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
01391                                                uint16_t Size)
01392 {
01393
01394   if (husart->State == HAL_USART_STATE_READY)
01395   {
01396     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01397     {
01398       return HAL_ERROR;
01399     }
01400
01401     /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
01402        should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
01403        handled through a u16 cast. */
01404     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01405     {
01406       if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
01407       {
01408         return  HAL_ERROR;
01409       }
01410     }
01411
01412     /* Process Locked */
01413     __HAL_LOCK(husart);
01414
01415     husart->pRxBuffPtr = pRxData;
01416     husart->RxXferSize = Size;
01417     husart->RxXferCount = Size;
01418     husart->pTxBuffPtr = pTxData;
01419     husart->TxXferSize = Size;
01420     husart->TxXferCount = Size;
01421
01422     /* Computation of USART mask to apply to RDR register */
01423     USART_MASK_COMPUTATION(husart);
01424
01425     husart->ErrorCode = HAL_USART_ERROR_NONE;
01426     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01427
01428     /* Configure TxRx interrupt processing */
01429     if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01430     {
01431       /* Set the Rx ISR function pointer according to the data word length */
01432       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01433       {
01434         husart->TxISR = USART_TxISR_16BIT_FIFOEN;
01435         husart->RxISR = USART_RxISR_16BIT_FIFOEN;
01436       }
01437       else
01438       {
01439         husart->TxISR = USART_TxISR_8BIT_FIFOEN;
01440         husart->RxISR = USART_RxISR_8BIT_FIFOEN;
01441       }
01442
01443       /* Process Locked */
01444       __HAL_UNLOCK(husart);
01445
01446       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01447       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01448
01449       if (husart->Init.Parity != USART_PARITY_NONE)
01450       {
01451         /* Enable the USART Parity Error interrupt  */
01452         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01453       }
01454
01455       /* Enable the TX and  RX FIFO Threshold interrupts */
01456       SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
01457     }
01458     else
01459     {
01460       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01461       {
01462         husart->TxISR = USART_TxISR_16BIT;
01463         husart->RxISR = USART_RxISR_16BIT;
01464       }
01465       else
01466       {
01467         husart->TxISR = USART_TxISR_8BIT;
01468         husart->RxISR = USART_RxISR_8BIT;
01469       }
01470
01471       /* Process Locked */
01472       __HAL_UNLOCK(husart);
01473
01474       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01475       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01476
01477       /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
01478       if (husart->Init.Parity != USART_PARITY_NONE)
01479       {
01480         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01481       }
01482       else
01483       {
01484         SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
01485       }
01486
01487       /* Enable the USART Transmit Data Register Empty Interrupt */
01488       SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01489     }
01490
01491     return HAL_OK;
01492   }
01493   else
01494   {
01495     return HAL_BUSY;
01496   }
01497 }
01498
01499 /**
01500   * @brief Send an amount of data in DMA mode.
01501   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01502   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01503   *         of u16 provided through pTxData.
01504   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01505   *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
01506   *         (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
01507   *         use of specific alignment compilation directives or pragmas might be required
01508   *         to ensure proper alignment for pTxData.
01509   * @param  husart USART handle.
01510   * @param  pTxData pointer to data buffer (u8 or u16 data elements).
01511   * @param  Size amount of data elements (u8 or u16) to be sent.
01512   * @retval HAL status
01513   */
01514 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
01515 {
01516   HAL_StatusTypeDef status = HAL_OK;
01517   const uint32_t *tmp;
01518
01519   if (husart->State == HAL_USART_STATE_READY)
01520   {
01521     if ((pTxData == NULL) || (Size == 0U))
01522     {
01523       return HAL_ERROR;
01524     }
01525
01526     /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
01527        should be aligned on a u16 frontier, as data copy into TDR will be
01528        handled by DMA from a u16 frontier. */
01529     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01530     {
01531       if ((((uint32_t)pTxData) & 1U) != 0U)
01532       {
01533         return  HAL_ERROR;
01534       }
01535     }
01536
01537     /* Process Locked */
01538     __HAL_LOCK(husart);
01539
01540     husart->pTxBuffPtr = pTxData;
01541     husart->TxXferSize = Size;
01542     husart->TxXferCount = Size;
01543
01544     husart->ErrorCode = HAL_USART_ERROR_NONE;
01545     husart->State = HAL_USART_STATE_BUSY_TX;
01546
01547     if (husart->hdmatx != NULL)
01548     {
01549       /* Set the USART DMA transfer complete callback */
01550       husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01551
01552       /* Set the USART DMA Half transfer complete callback */
01553       husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01554
01555       /* Set the DMA error callback */
01556       husart->hdmatx->XferErrorCallback = USART_DMAError;
01557
01558       /* Enable the USART transmit DMA channel */
01559       tmp = (const uint32_t *)&pTxData;
01560       status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01561     }
01562
01563     if (status == HAL_OK)
01564     {
01565       /* Clear the TC flag in the ICR register */
01566       __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01567
01568       /* Process Unlocked */
01569       __HAL_UNLOCK(husart);
01570
01571       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01572          in the USART CR3 register */
01573       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01574
01575       return HAL_OK;
01576     }
01577     else
01578     {
01579       /* Set error code to DMA */
01580       husart->ErrorCode = HAL_USART_ERROR_DMA;
01581
01582       /* Process Unlocked */
01583       __HAL_UNLOCK(husart);
01584
01585       /* Restore husart->State to ready */
01586       husart->State = HAL_USART_STATE_READY;
01587
01588       return HAL_ERROR;
01589     }
01590   }
01591   else
01592   {
01593     return HAL_BUSY;
01594   }
01595 }
01596
01597 /**
01598   * @brief Receive an amount of data in DMA mode.
01599   * @note   When the USART parity is enabled (PCE = 1), the received data contain
01600   *         the parity bit (MSB position).
01601   * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
01602   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01603   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01604   *         of u16 available through pRxData.
01605   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01606   *         address of user data buffer for storing data to be received, should be aligned on
01607   *         a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier).
01608   *         Depending on compilation chain, use of specific alignment compilation directives or pragmas
01609   *         might be required to ensure proper alignment for pRxData.
01610   * @param  husart USART handle.
01611   * @param  pRxData pointer to data buffer (u8 or u16 data elements).
01612   * @param  Size amount of data elements (u8 or u16) to be received.
01613   * @retval HAL status
01614   */
01615 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
01616 {
01617   HAL_StatusTypeDef status = HAL_OK;
01618   uint32_t *tmp = (uint32_t *)&pRxData;
01619
01620   /* Check that a Rx process is not already ongoing */
01621   if (husart->State == HAL_USART_STATE_READY)
01622   {
01623     if ((pRxData == NULL) || (Size == 0U))
01624     {
01625       return HAL_ERROR;
01626     }
01627
01628     /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
01629        should be aligned on a u16 frontier, as data copy from RDR will be
01630        handled by DMA from a u16 frontier. */
01631     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01632     {
01633       if ((((uint32_t)pRxData) & 1U) != 0U)
01634       {
01635         return  HAL_ERROR;
01636       }
01637     }
01638
01639     /* Process Locked */
01640     __HAL_LOCK(husart);
01641
01642     husart->pRxBuffPtr = pRxData;
01643     husart->RxXferSize = Size;
01644     husart->pTxBuffPtr = pRxData;
01645     husart->TxXferSize = Size;
01646
01647     husart->ErrorCode = HAL_USART_ERROR_NONE;
01648     husart->State = HAL_USART_STATE_BUSY_RX;
01649
01650     if (husart->hdmarx != NULL)
01651     {
01652       /* Set the USART DMA Rx transfer complete callback */
01653       husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01654
01655       /* Set the USART DMA Half transfer complete callback */
01656       husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01657
01658       /* Set the USART DMA Rx transfer error callback */
01659       husart->hdmarx->XferErrorCallback = USART_DMAError;
01660
01661       /* Enable the USART receive DMA channel */
01662       status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
01663     }
01664
01665     if ((status == HAL_OK) &&
01666         (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
01667     {
01668       /* Enable the USART transmit DMA channel: the transmit channel is used in order
01669          to generate in the non-blocking mode the clock to the slave device,
01670          this mode isn't a simplex receive mode but a full-duplex receive mode */
01671
01672       /* Set the USART DMA Tx Complete and Error callback to Null */
01673       if (husart->hdmatx != NULL)
01674       {
01675         husart->hdmatx->XferErrorCallback = NULL;
01676         husart->hdmatx->XferHalfCpltCallback = NULL;
01677         husart->hdmatx->XferCpltCallback = NULL;
01678         status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01679       }
01680     }
01681
01682     if (status == HAL_OK)
01683     {
01684       /* Process Unlocked */
01685       __HAL_UNLOCK(husart);
01686
01687       if (husart->Init.Parity != USART_PARITY_NONE)
01688       {
01689         /* Enable the USART Parity Error Interrupt */
01690         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01691       }
01692
01693       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01694       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01695
01696       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01697          in the USART CR3 register */
01698       SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01699
01700       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01701          in the USART CR3 register */
01702       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01703
01704       return HAL_OK;
01705     }
01706     else
01707     {
01708       if (husart->hdmarx != NULL)
01709       {
01710         status = HAL_DMA_Abort(husart->hdmarx);
01711       }
01712
01713       /* No need to check on error code */
01714       UNUSED(status);
01715
01716       /* Set error code to DMA */
01717       husart->ErrorCode = HAL_USART_ERROR_DMA;
01718
01719       /* Process Unlocked */
01720       __HAL_UNLOCK(husart);
01721
01722       /* Restore husart->State to ready */
01723       husart->State = HAL_USART_STATE_READY;
01724
01725       return HAL_ERROR;
01726     }
01727   }
01728   else
01729   {
01730     return HAL_BUSY;
01731   }
01732 }
01733
01734 /**
01735   * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
01736   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
01737   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01738   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
01739   *         of u16 available through pTxData and through pRxData.
01740   * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01741   *         address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
01742   *         (16 bits) (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation
01743   *         chain, use of specific alignment compilation directives or pragmas might be required
01744   *         to ensure proper alignment for pTxData and pRxData.
01745   * @param  husart USART handle.
01746   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
01747   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
01748   * @param  Size amount of data elements (u8 or u16) to be received/sent.
01749   * @retval HAL status
01750   */
01751 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
01752                                                 uint16_t Size)
01753 {
01754   HAL_StatusTypeDef status;
01755   const uint32_t *tmp;
01756
01757   if (husart->State == HAL_USART_STATE_READY)
01758   {
01759     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01760     {
01761       return HAL_ERROR;
01762     }
01763
01764     /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
01765        should be aligned on a u16 frontier, as data copy to/from TDR/RDR will be
01766        handled by DMA from a u16 frontier. */
01767     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01768     {
01769       if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
01770       {
01771         return  HAL_ERROR;
01772       }
01773     }
01774
01775     /* Process Locked */
01776     __HAL_LOCK(husart);
01777
01778     husart->pRxBuffPtr = pRxData;
01779     husart->RxXferSize = Size;
01780     husart->pTxBuffPtr = pTxData;
01781     husart->TxXferSize = Size;
01782
01783     husart->ErrorCode = HAL_USART_ERROR_NONE;
01784     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01785
01786     if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
01787     {
01788       /* Set the USART DMA Rx transfer complete callback */
01789       husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01790
01791       /* Set the USART DMA Half transfer complete callback */
01792       husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01793
01794       /* Set the USART DMA Tx transfer complete callback */
01795       husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01796
01797       /* Set the USART DMA Half transfer complete callback */
01798       husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01799
01800       /* Set the USART DMA Tx transfer error callback */
01801       husart->hdmatx->XferErrorCallback = USART_DMAError;
01802
01803       /* Set the USART DMA Rx transfer error callback */
01804       husart->hdmarx->XferErrorCallback = USART_DMAError;
01805
01806       /* Enable the USART receive DMA channel */
01807       tmp = (uint32_t *)&pRxData;
01808       status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size);
01809
01810       /* Enable the USART transmit DMA channel */
01811       if (status == HAL_OK)
01812       {
01813         tmp = (const uint32_t *)&pTxData;
01814         status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01815       }
01816     }
01817     else
01818     {
01819       status = HAL_ERROR;
01820     }
01821
01822     if (status == HAL_OK)
01823     {
01824       /* Process Unlocked */
01825       __HAL_UNLOCK(husart);
01826
01827       if (husart->Init.Parity != USART_PARITY_NONE)
01828       {
01829         /* Enable the USART Parity Error Interrupt */
01830         SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01831       }
01832
01833       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01834       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01835
01836       /* Clear the TC flag in the ICR register */
01837       __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01838
01839       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01840          in the USART CR3 register */
01841       SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01842
01843       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01844          in the USART CR3 register */
01845       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01846
01847       return HAL_OK;
01848     }
01849     else
01850     {
01851       if (husart->hdmarx != NULL)
01852       {
01853         status = HAL_DMA_Abort(husart->hdmarx);
01854       }
01855
01856       /* No need to check on error code */
01857       UNUSED(status);
01858
01859       /* Set error code to DMA */
01860       husart->ErrorCode = HAL_USART_ERROR_DMA;
01861
01862       /* Process Unlocked */
01863       __HAL_UNLOCK(husart);
01864
01865       /* Restore husart->State to ready */
01866       husart->State = HAL_USART_STATE_READY;
01867
01868       return HAL_ERROR;
01869     }
01870   }
01871   else
01872   {
01873     return HAL_BUSY;
01874   }
01875 }
01876
01877 /**
01878   * @brief Pause the DMA Transfer.
01879   * @param  husart USART handle.
01880   * @retval HAL status
01881   */
01882 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01883 {
01884   const HAL_USART_StateTypeDef state = husart->State;
01885
01886   /* Process Locked */
01887   __HAL_LOCK(husart);
01888
01889   if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
01890       (state == HAL_USART_STATE_BUSY_TX))
01891   {
01892     /* Disable the USART DMA Tx request */
01893     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01894   }
01895   else if ((state == HAL_USART_STATE_BUSY_RX) ||
01896            (state == HAL_USART_STATE_BUSY_TX_RX))
01897   {
01898     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01899     {
01900       /* Disable the USART DMA Tx request */
01901       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01902     }
01903     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01904     {
01905       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01906       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01907       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01908
01909       /* Disable the USART DMA Rx request */
01910       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01911     }
01912   }
01913   else
01914   {
01915     /* Nothing to do */
01916   }
01917
01918   /* Process Unlocked */
01919   __HAL_UNLOCK(husart);
01920
01921   return HAL_OK;
01922 }
01923
01924 /**
01925   * @brief Resume the DMA Transfer.
01926   * @param  husart USART handle.
01927   * @retval HAL status
01928   */
01929 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01930 {
01931   const HAL_USART_StateTypeDef state = husart->State;
01932
01933   /* Process Locked */
01934   __HAL_LOCK(husart);
01935
01936   if (state == HAL_USART_STATE_BUSY_TX)
01937   {
01938     /* Enable the USART DMA Tx request */
01939     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01940   }
01941   else if ((state == HAL_USART_STATE_BUSY_RX) ||
01942            (state == HAL_USART_STATE_BUSY_TX_RX))
01943   {
01944     /* Clear the Overrun flag before resuming the Rx transfer*/
01945     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
01946
01947     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
01948     if (husart->Init.Parity != USART_PARITY_NONE)
01949     {
01950       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01951     }
01952     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01953
01954     /* Enable the USART DMA Rx request  before the DMA Tx request */
01955     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01956
01957     /* Enable the USART DMA Tx request */
01958     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01959   }
01960   else
01961   {
01962     /* Nothing to do */
01963   }
01964
01965   /* Process Unlocked */
01966   __HAL_UNLOCK(husart);
01967
01968   return HAL_OK;
01969 }
01970
01971 /**
01972   * @brief Stop the DMA Transfer.
01973   * @param  husart USART handle.
01974   * @retval HAL status
01975   */
01976 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01977 {
01978   /* The Lock is not implemented on this API to allow the user application
01979      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
01980      HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
01981      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01982      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01983      the stream and the corresponding call back is executed. */
01984
01985   /* Disable the USART Tx/Rx DMA requests */
01986   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01987   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01988
01989   /* Abort the USART DMA tx channel */
01990   if (husart->hdmatx != NULL)
01991   {
01992     if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
01993     {
01994       if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01995       {
01996         /* Set error code to DMA */
01997         husart->ErrorCode = HAL_USART_ERROR_DMA;
01998
01999         return HAL_TIMEOUT;
02000       }
02001     }
02002   }
02003   /* Abort the USART DMA rx channel */
02004   if (husart->hdmarx != NULL)
02005   {
02006     if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
02007     {
02008       if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
02009       {
02010         /* Set error code to DMA */
02011         husart->ErrorCode = HAL_USART_ERROR_DMA;
02012
02013         return HAL_TIMEOUT;
02014       }
02015     }
02016   }
02017
02018   USART_EndTransfer(husart);
02019   husart->State = HAL_USART_STATE_READY;
02020
02021   return HAL_OK;
02022 }
02023
02024 /**
02025   * @brief  Abort ongoing transfers (blocking mode).
02026   * @param  husart USART handle.
02027   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
02028   *         This procedure performs following operations :
02029   *           - Disable USART Interrupts (Tx and Rx)
02030   *           - Disable the DMA transfer in the peripheral register (if enabled)
02031   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
02032   *           - Set handle State to READY
02033   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
02034   * @retval HAL status
02035   */
02036 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
02037 {
02038   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
02039   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
02040                                     USART_CR1_TCIE));
02041   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
02042
02043   /* Abort the USART DMA Tx channel if enabled */
02044   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
02045   {
02046     /* Disable the USART DMA Tx request if enabled */
02047     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02048
02049     /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
02050     if (husart->hdmatx != NULL)
02051     {
02052       /* Set the USART DMA Abort callback to Null.
02053          No call back execution at end of DMA abort procedure */
02054       husart->hdmatx->XferAbortCallback = NULL;
02055
02056       if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
02057       {
02058         if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
02059         {
02060           /* Set error code to DMA */
02061           husart->ErrorCode = HAL_USART_ERROR_DMA;
02062
02063           return HAL_TIMEOUT;
02064         }
02065       }
02066     }
02067   }
02068
02069   /* Abort the USART DMA Rx channel if enabled */
02070   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02071   {
02072     /* Disable the USART DMA Rx request if enabled */
02073     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02074
02075     /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
02076     if (husart->hdmarx != NULL)
02077     {
02078       /* Set the USART DMA Abort callback to Null.
02079          No call back execution at end of DMA abort procedure */
02080       husart->hdmarx->XferAbortCallback = NULL;
02081
02082       if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
02083       {
02084         if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
02085         {
02086           /* Set error code to DMA */
02087           husart->ErrorCode = HAL_USART_ERROR_DMA;
02088
02089           return HAL_TIMEOUT;
02090         }
02091       }
02092     }
02093   }
02094
02095   /* Reset Tx and Rx transfer counters */
02096   husart->TxXferCount = 0U;
02097   husart->RxXferCount = 0U;
02098
02099   /* Clear the Error flags in the ICR register */
02100   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02101
02102   /* Flush the whole TX FIFO (if needed) */
02103   if (husart->FifoMode == USART_FIFOMODE_ENABLE)
02104   {
02105     __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
02106   }
02107
02108   /* Discard the received data */
02109   __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
02110
02111   /* Restore husart->State to Ready */
02112   husart->State  = HAL_USART_STATE_READY;
02113
02114   /* Reset Handle ErrorCode to No Error */
02115   husart->ErrorCode = HAL_USART_ERROR_NONE;
02116
02117   return HAL_OK;
02118 }
02119
02120 /**
02121   * @brief  Abort ongoing transfers (Interrupt mode).
02122   * @param  husart USART handle.
02123   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
02124   *         This procedure performs following operations :
02125   *           - Disable USART Interrupts (Tx and Rx)
02126   *           - Disable the DMA transfer in the peripheral register (if enabled)
02127   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02128   *           - Set handle State to READY
02129   *           - At abort completion, call user abort complete callback
02130   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02131   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02132   * @retval HAL status
02133   */
02134 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
02135 {
02136   uint32_t abortcplt = 1U;
02137
02138   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
02139   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
02140                                     USART_CR1_TCIE));
02141   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
02142
02143   /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
02144      before any call to DMA Abort functions */
02145   /* DMA Tx Handle is valid */
02146   if (husart->hdmatx != NULL)
02147   {
02148     /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
02149        Otherwise, set it to NULL */
02150     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
02151     {
02152       husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
02153     }
02154     else
02155     {
02156       husart->hdmatx->XferAbortCallback = NULL;
02157     }
02158   }
02159   /* DMA Rx Handle is valid */
02160   if (husart->hdmarx != NULL)
02161   {
02162     /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
02163        Otherwise, set it to NULL */
02164     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02165     {
02166       husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
02167     }
02168     else
02169     {
02170       husart->hdmarx->XferAbortCallback = NULL;
02171     }
02172   }
02173
02174   /* Abort the USART DMA Tx channel if enabled */
02175   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
02176   {
02177     /* Disable DMA Tx at USART level */
02178     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02179
02180     /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
02181     if (husart->hdmatx != NULL)
02182     {
02183       /* USART Tx DMA Abort callback has already been initialised :
02184          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
02185
02186       /* Abort DMA TX */
02187       if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
02188       {
02189         husart->hdmatx->XferAbortCallback = NULL;
02190       }
02191       else
02192       {
02193         abortcplt = 0U;
02194       }
02195     }
02196   }
02197
02198   /* Abort the USART DMA Rx channel if enabled */
02199   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02200   {
02201     /* Disable the USART DMA Rx request if enabled */
02202     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02203
02204     /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
02205     if (husart->hdmarx != NULL)
02206     {
02207       /* USART Rx DMA Abort callback has already been initialised :
02208          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
02209
02210       /* Abort DMA RX */
02211       if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
02212       {
02213         husart->hdmarx->XferAbortCallback = NULL;
02214         abortcplt = 1U;
02215       }
02216       else
02217       {
02218         abortcplt = 0U;
02219       }
02220     }
02221   }
02222
02223   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
02224   if (abortcplt == 1U)
02225   {
02226     /* Reset Tx and Rx transfer counters */
02227     husart->TxXferCount = 0U;
02228     husart->RxXferCount = 0U;
02229
02230     /* Reset errorCode */
02231     husart->ErrorCode = HAL_USART_ERROR_NONE;
02232
02233     /* Clear the Error flags in the ICR register */
02234     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02235
02236     /* Flush the whole TX FIFO (if needed) */
02237     if (husart->FifoMode == USART_FIFOMODE_ENABLE)
02238     {
02239       __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
02240     }
02241
02242     /* Discard the received data */
02243     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
02244
02245     /* Restore husart->State to Ready */
02246     husart->State  = HAL_USART_STATE_READY;
02247
02248     /* As no DMA to be aborted, call directly user Abort complete callback */
02249 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02250     /* Call registered Abort Complete Callback */
02251     husart->AbortCpltCallback(husart);
02252 #else
02253     /* Call legacy weak Abort Complete Callback */
02254     HAL_USART_AbortCpltCallback(husart);
02255 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02256   }
02257
02258   return HAL_OK;
02259 }
02260
02261 /**
02262   * @brief  Handle USART interrupt request.
02263   * @param  husart USART handle.
02264   * @retval None
02265   */
02266 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
02267 {
02268   uint32_t isrflags   = READ_REG(husart->Instance->ISR);
02269   uint32_t cr1its     = READ_REG(husart->Instance->CR1);
02270   uint32_t cr3its     = READ_REG(husart->Instance->CR3);
02271
02272   uint32_t errorflags;
02273   uint32_t errorcode;
02274
02275   /* If no error occurs */
02276   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
02277                                       USART_ISR_UDR));
02278   if (errorflags == 0U)
02279   {
02280     /* USART in mode Receiver ---------------------------------------------------*/
02281     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02282         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02283             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02284     {
02285       if (husart->RxISR != NULL)
02286       {
02287         husart->RxISR(husart);
02288       }
02289       return;
02290     }
02291   }
02292
02293   /* If some errors occur */
02294   if ((errorflags != 0U)
02295       && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
02296           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
02297   {
02298     /* USART parity error interrupt occurred -------------------------------------*/
02299     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02300     {
02301       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
02302
02303       husart->ErrorCode |= HAL_USART_ERROR_PE;
02304     }
02305
02306     /* USART frame error interrupt occurred --------------------------------------*/
02307     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02308     {
02309       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
02310
02311       husart->ErrorCode |= HAL_USART_ERROR_FE;
02312     }
02313
02314     /* USART noise error interrupt occurred --------------------------------------*/
02315     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02316     {
02317       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
02318
02319       husart->ErrorCode |= HAL_USART_ERROR_NE;
02320     }
02321
02322     /* USART Over-Run interrupt occurred -----------------------------------------*/
02323     if (((isrflags & USART_ISR_ORE) != 0U)
02324         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
02325             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
02326     {
02327       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
02328
02329       husart->ErrorCode |= HAL_USART_ERROR_ORE;
02330     }
02331
02332     /* USART Receiver Timeout interrupt occurred ---------------------------------*/
02333     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
02334     {
02335       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
02336
02337       husart->ErrorCode |= HAL_USART_ERROR_RTO;
02338     }
02339
02340     /* USART SPI slave underrun error interrupt occurred -------------------------*/
02341     if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02342     {
02343       /* Ignore SPI slave underrun errors when reception is going on */
02344       if (husart->State == HAL_USART_STATE_BUSY_RX)
02345       {
02346         __HAL_USART_CLEAR_UDRFLAG(husart);
02347         return;
02348       }
02349       else
02350       {
02351         __HAL_USART_CLEAR_UDRFLAG(husart);
02352         husart->ErrorCode |= HAL_USART_ERROR_UDR;
02353       }
02354     }
02355
02356     /* Call USART Error Call back function if need be --------------------------*/
02357     if (husart->ErrorCode != HAL_USART_ERROR_NONE)
02358     {
02359       /* USART in mode Receiver ---------------------------------------------------*/
02360       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02361           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02362               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02363       {
02364         if (husart->RxISR != NULL)
02365         {
02366           husart->RxISR(husart);
02367         }
02368       }
02369
02370       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
02371          consider error as blocking */
02372       errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
02373       if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
02374           (errorcode != 0U))
02375       {
02376         /* Blocking error : transfer is aborted
02377            Set the USART state ready to be able to start again the process,
02378            Disable Interrupts, and disable DMA requests, if ongoing */
02379         USART_EndTransfer(husart);
02380
02381         /* Abort the USART DMA Rx channel if enabled */
02382         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02383         {
02384           /* Disable the USART DMA Rx request if enabled */
02385           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
02386
02387           /* Abort the USART DMA Tx channel */
02388           if (husart->hdmatx != NULL)
02389           {
02390             /* Set the USART Tx DMA Abort callback to NULL : no callback
02391                executed at end of DMA abort procedure */
02392             husart->hdmatx->XferAbortCallback = NULL;
02393
02394             /* Abort DMA TX */
02395             (void)HAL_DMA_Abort_IT(husart->hdmatx);
02396           }
02397
02398           /* Abort the USART DMA Rx channel */
02399           if (husart->hdmarx != NULL)
02400           {
02401             /* Set the USART Rx DMA Abort callback :
02402                will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
02403             husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
02404
02405             /* Abort DMA RX */
02406             if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
02407             {
02408               /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
02409               husart->hdmarx->XferAbortCallback(husart->hdmarx);
02410             }
02411           }
02412           else
02413           {
02414             /* Call user error callback */
02415 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02416             /* Call registered Error Callback */
02417             husart->ErrorCallback(husart);
02418 #else
02419             /* Call legacy weak Error Callback */
02420             HAL_USART_ErrorCallback(husart);
02421 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02422           }
02423         }
02424         else
02425         {
02426           /* Call user error callback */
02427 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02428           /* Call registered Error Callback */
02429           husart->ErrorCallback(husart);
02430 #else
02431           /* Call legacy weak Error Callback */
02432           HAL_USART_ErrorCallback(husart);
02433 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02434         }
02435       }
02436       else
02437       {
02438         /* Non Blocking error : transfer could go on.
02439            Error is notified to user through user error callback */
02440 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02441         /* Call registered Error Callback */
02442         husart->ErrorCallback(husart);
02443 #else
02444         /* Call legacy weak Error Callback */
02445         HAL_USART_ErrorCallback(husart);
02446 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02447         husart->ErrorCode = HAL_USART_ERROR_NONE;
02448       }
02449     }
02450     return;
02451
02452   } /* End if some error occurs */
02453
02454
02455   /* USART in mode Transmitter ------------------------------------------------*/
02456   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02457       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02458           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02459   {
02460     if (husart->TxISR != NULL)
02461     {
02462       husart->TxISR(husart);
02463     }
02464     return;
02465   }
02466
02467   /* USART in mode Transmitter (transmission end) -----------------------------*/
02468   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02469   {
02470     USART_EndTransmit_IT(husart);
02471     return;
02472   }
02473
02474   /* USART TX Fifo Empty occurred ----------------------------------------------*/
02475   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02476   {
02477 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02478     /* Call registered Tx Fifo Empty Callback */
02479     husart->TxFifoEmptyCallback(husart);
02480 #else
02481     /* Call legacy weak Tx Fifo Empty Callback */
02482     HAL_USARTEx_TxFifoEmptyCallback(husart);
02483 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02484     return;
02485   }
02486
02487   /* USART RX Fifo Full occurred ----------------------------------------------*/
02488   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02489   {
02490 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02491     /* Call registered Rx Fifo Full Callback */
02492     husart->RxFifoFullCallback(husart);
02493 #else
02494     /* Call legacy weak Rx Fifo Full Callback */
02495     HAL_USARTEx_RxFifoFullCallback(husart);
02496 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02497     return;
02498   }
02499 }
02500
02501 /**
02502   * @brief Tx Transfer completed callback.
02503   * @param husart USART handle.
02504   * @retval None
02505   */
02506 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
02507 {
02508   /* Prevent unused argument(s) compilation warning */
02509   UNUSED(husart);
02510
02511   /* NOTE : This function should not be modified, when the callback is needed,
02512             the HAL_USART_TxCpltCallback can be implemented in the user file.
02513    */
02514 }
02515
02516 /**
02517   * @brief  Tx Half Transfer completed callback.
02518   * @param husart USART handle.
02519   * @retval None
02520   */
02521 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
02522 {
02523   /* Prevent unused argument(s) compilation warning */
02524   UNUSED(husart);
02525
02526   /* NOTE: This function should not be modified, when the callback is needed,
02527            the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
02528    */
02529 }
02530
02531 /**
02532   * @brief  Rx Transfer completed callback.
02533   * @param husart USART handle.
02534   * @retval None
02535   */
02536 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
02537 {
02538   /* Prevent unused argument(s) compilation warning */
02539   UNUSED(husart);
02540
02541   /* NOTE: This function should not be modified, when the callback is needed,
02542            the HAL_USART_RxCpltCallback can be implemented in the user file.
02543    */
02544 }
02545
02546 /**
02547   * @brief Rx Half Transfer completed callback.
02548   * @param husart USART handle.
02549   * @retval None
02550   */
02551 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
02552 {
02553   /* Prevent unused argument(s) compilation warning */
02554   UNUSED(husart);
02555
02556   /* NOTE : This function should not be modified, when the callback is needed,
02557             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
02558    */
02559 }
02560
02561 /**
02562   * @brief Tx/Rx Transfers completed callback for the non-blocking process.
02563   * @param husart USART handle.
02564   * @retval None
02565   */
02566 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
02567 {
02568   /* Prevent unused argument(s) compilation warning */
02569   UNUSED(husart);
02570
02571   /* NOTE : This function should not be modified, when the callback is needed,
02572             the HAL_USART_TxRxCpltCallback can be implemented in the user file
02573    */
02574 }
02575
02576 /**
02577   * @brief USART error callback.
02578   * @param husart USART handle.
02579   * @retval None
02580   */
02581 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
02582 {
02583   /* Prevent unused argument(s) compilation warning */
02584   UNUSED(husart);
02585
02586   /* NOTE : This function should not be modified, when the callback is needed,
02587             the HAL_USART_ErrorCallback can be implemented in the user file.
02588    */
02589 }
02590
02591 /**
02592   * @brief  USART Abort Complete callback.
02593   * @param  husart USART handle.
02594   * @retval None
02595   */
02596 __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
02597 {
02598   /* Prevent unused argument(s) compilation warning */
02599   UNUSED(husart);
02600
02601   /* NOTE : This function should not be modified, when the callback is needed,
02602             the HAL_USART_AbortCpltCallback can be implemented in the user file.
02603    */
02604 }
02605
02606 /**
02607   * @}
02608   */
02609
02610 /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
02611   *  @brief   USART Peripheral State and Error functions
02612   *
02613 @verbatim
02614   ==============================================================================
02615             ##### Peripheral State and Error functions #####
02616   ==============================================================================
02617     [..]
02618     This subsection provides functions allowing to :
02619       (+) Return the USART handle state
02620       (+) Return the USART handle error code
02621
02622 @endverbatim
02623   * @{
02624   */
02625
02626
02627 /**
02628   * @brief Return the USART handle state.
02629   * @param husart pointer to a USART_HandleTypeDef structure that contains
02630   *              the configuration information for the specified USART.
02631   * @retval USART handle state
02632   */
02633 HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart)
02634 {
02635   return husart->State;
02636 }
02637
02638 /**
02639   * @brief Return the USART error code.
02640   * @param husart pointer to a USART_HandleTypeDef structure that contains
02641   *              the configuration information for the specified USART.
02642   * @retval USART handle Error Code
02643   */
02644 uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
02645 {
02646   return husart->ErrorCode;
02647 }
02648
02649 /**
02650   * @}
02651   */
02652
02653 /**
02654   * @}
02655   */
02656
02657 /** @defgroup USART_Private_Functions USART Private Functions
02658   * @{
02659   */
02660
02661 /**
02662   * @brief  Initialize the callbacks to their default values.
02663   * @param  husart USART handle.
02664   * @retval none
02665   */
02666 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02667 void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
02668 {
02669   /* Init the USART Callback settings */
02670   husart->TxHalfCpltCallback        = HAL_USART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02671   husart->TxCpltCallback            = HAL_USART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02672   husart->RxHalfCpltCallback        = HAL_USART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02673   husart->RxCpltCallback            = HAL_USART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02674   husart->TxRxCpltCallback          = HAL_USART_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback          */
02675   husart->ErrorCallback             = HAL_USART_ErrorCallback;             /* Legacy weak ErrorCallback             */
02676   husart->AbortCpltCallback         = HAL_USART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02677   husart->RxFifoFullCallback        = HAL_USARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02678   husart->TxFifoEmptyCallback       = HAL_USARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02679 }
02680 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02681
02682 /**
02683   * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
02684   * @param  husart USART handle.
02685   * @retval None
02686   */
02687 static void USART_EndTransfer(USART_HandleTypeDef *husart)
02688 {
02689   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
02690   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
02691                                     USART_CR1_TCIE));
02692   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
02693
02694   /* At end of process, restore husart->State to Ready */
02695   husart->State = HAL_USART_STATE_READY;
02696 }
02697
02698 /**
02699   * @brief DMA USART transmit process complete callback.
02700   * @param  hdma DMA handle.
02701   * @retval None
02702   */
02703 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02704 {
02705   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02706
02707   /* DMA Normal mode */
02708   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02709   {
02710     husart->TxXferCount = 0U;
02711
02712     if (husart->State == HAL_USART_STATE_BUSY_TX)
02713     {
02714       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02715          in the USART CR3 register */
02716       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02717
02718       /* Enable the USART Transmit Complete Interrupt */
02719       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
02720     }
02721   }
02722   /* DMA Circular mode */
02723   else
02724   {
02725     if (husart->State == HAL_USART_STATE_BUSY_TX)
02726     {
02727 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02728       /* Call registered Tx Complete Callback */
02729       husart->TxCpltCallback(husart);
02730 #else
02731       /* Call legacy weak Tx Complete Callback */
02732       HAL_USART_TxCpltCallback(husart);
02733 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02734     }
02735   }
02736 }
02737
02738 /**
02739   * @brief DMA USART transmit process half complete callback.
02740   * @param  hdma DMA handle.
02741   * @retval None
02742   */
02743 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02744 {
02745   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02746
02747 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02748   /* Call registered Tx Half Complete Callback */
02749   husart->TxHalfCpltCallback(husart);
02750 #else
02751   /* Call legacy weak Tx Half Complete Callback */
02752   HAL_USART_TxHalfCpltCallback(husart);
02753 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02754 }
02755
02756 /**
02757   * @brief DMA USART receive process complete callback.
02758   * @param  hdma DMA handle.
02759   * @retval None
02760   */
02761 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02762 {
02763   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02764
02765   /* DMA Normal mode */
02766   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02767   {
02768     husart->RxXferCount = 0U;
02769
02770     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02771     CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
02772     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02773
02774     /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
02775        in USART CR3 register */
02776     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02777     /* similarly, disable the DMA TX transfer that was started to provide the
02778        clock to the slave device */
02779     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02780
02781     if (husart->State == HAL_USART_STATE_BUSY_RX)
02782     {
02783 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02784       /* Call registered Rx Complete Callback */
02785       husart->RxCpltCallback(husart);
02786 #else
02787       /* Call legacy weak Rx Complete Callback */
02788       HAL_USART_RxCpltCallback(husart);
02789 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02790     }
02791     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
02792     else
02793     {
02794 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02795       /* Call registered Tx Rx Complete Callback */
02796       husart->TxRxCpltCallback(husart);
02797 #else
02798       /* Call legacy weak Tx Rx Complete Callback */
02799       HAL_USART_TxRxCpltCallback(husart);
02800 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02801     }
02802     husart->State = HAL_USART_STATE_READY;
02803   }
02804   /* DMA circular mode */
02805   else
02806   {
02807     if (husart->State == HAL_USART_STATE_BUSY_RX)
02808     {
02809 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02810       /* Call registered Rx Complete Callback */
02811       husart->RxCpltCallback(husart);
02812 #else
02813       /* Call legacy weak Rx Complete Callback */
02814       HAL_USART_RxCpltCallback(husart);
02815 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02816     }
02817     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
02818     else
02819     {
02820 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02821       /* Call registered Tx Rx Complete Callback */
02822       husart->TxRxCpltCallback(husart);
02823 #else
02824       /* Call legacy weak Tx Rx Complete Callback */
02825       HAL_USART_TxRxCpltCallback(husart);
02826 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02827     }
02828   }
02829 }
02830
02831 /**
02832   * @brief DMA USART receive process half complete callback.
02833   * @param  hdma DMA handle.
02834   * @retval None
02835   */
02836 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02837 {
02838   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02839
02840 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02841   /* Call registered Rx Half Complete Callback */
02842   husart->RxHalfCpltCallback(husart);
02843 #else
02844   /* Call legacy weak Rx Half Complete Callback */
02845   HAL_USART_RxHalfCpltCallback(husart);
02846 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02847 }
02848
02849 /**
02850   * @brief DMA USART communication error callback.
02851   * @param  hdma DMA handle.
02852   * @retval None
02853   */
02854 static void USART_DMAError(DMA_HandleTypeDef *hdma)
02855 {
02856   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02857
02858   husart->RxXferCount = 0U;
02859   husart->TxXferCount = 0U;
02860   USART_EndTransfer(husart);
02861
02862   husart->ErrorCode |= HAL_USART_ERROR_DMA;
02863   husart->State = HAL_USART_STATE_READY;
02864
02865 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02866   /* Call registered Error Callback */
02867   husart->ErrorCallback(husart);
02868 #else
02869   /* Call legacy weak Error Callback */
02870   HAL_USART_ErrorCallback(husart);
02871 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02872 }
02873
02874 /**
02875   * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
02876   *         (To be called at end of DMA Abort procedure following error occurrence).
02877   * @param  hdma DMA handle.
02878   * @retval None
02879   */
02880 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02881 {
02882   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02883   husart->RxXferCount = 0U;
02884   husart->TxXferCount = 0U;
02885
02886 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02887   /* Call registered Error Callback */
02888   husart->ErrorCallback(husart);
02889 #else
02890   /* Call legacy weak Error Callback */
02891   HAL_USART_ErrorCallback(husart);
02892 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02893 }
02894
02895 /**
02896   * @brief  DMA USART Tx communication abort callback, when initiated by user
02897   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02898   * @note   When this callback is executed, User Abort complete call back is called only if no
02899   *         Abort still ongoing for Rx DMA Handle.
02900   * @param  hdma DMA handle.
02901   * @retval None
02902   */
02903 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02904 {
02905   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02906
02907   husart->hdmatx->XferAbortCallback = NULL;
02908
02909   /* Check if an Abort process is still ongoing */
02910   if (husart->hdmarx != NULL)
02911   {
02912     if (husart->hdmarx->XferAbortCallback != NULL)
02913     {
02914       return;
02915     }
02916   }
02917
02918   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02919   husart->TxXferCount = 0U;
02920   husart->RxXferCount = 0U;
02921
02922   /* Reset errorCode */
02923   husart->ErrorCode = HAL_USART_ERROR_NONE;
02924
02925   /* Clear the Error flags in the ICR register */
02926   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02927
02928   /* Restore husart->State to Ready */
02929   husart->State = HAL_USART_STATE_READY;
02930
02931   /* Call user Abort complete callback */
02932 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02933   /* Call registered Abort Complete Callback */
02934   husart->AbortCpltCallback(husart);
02935 #else
02936   /* Call legacy weak Abort Complete Callback */
02937   HAL_USART_AbortCpltCallback(husart);
02938 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02939
02940 }
02941
02942
02943 /**
02944   * @brief  DMA USART Rx communication abort callback, when initiated by user
02945   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02946   * @note   When this callback is executed, User Abort complete call back is called only if no
02947   *         Abort still ongoing for Tx DMA Handle.
02948   * @param  hdma DMA handle.
02949   * @retval None
02950   */
02951 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02952 {
02953   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02954
02955   husart->hdmarx->XferAbortCallback = NULL;
02956
02957   /* Check if an Abort process is still ongoing */
02958   if (husart->hdmatx != NULL)
02959   {
02960     if (husart->hdmatx->XferAbortCallback != NULL)
02961     {
02962       return;
02963     }
02964   }
02965
02966   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02967   husart->TxXferCount = 0U;
02968   husart->RxXferCount = 0U;
02969
02970   /* Reset errorCode */
02971   husart->ErrorCode = HAL_USART_ERROR_NONE;
02972
02973   /* Clear the Error flags in the ICR register */
02974   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02975
02976   /* Restore husart->State to Ready */
02977   husart->State  = HAL_USART_STATE_READY;
02978
02979   /* Call user Abort complete callback */
02980 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02981   /* Call registered Abort Complete Callback */
02982   husart->AbortCpltCallback(husart);
02983 #else
02984   /* Call legacy weak Abort Complete Callback */
02985   HAL_USART_AbortCpltCallback(husart);
02986 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02987 }
02988
02989
02990 /**
02991   * @brief  Handle USART Communication Timeout. It waits
02992   *         until a flag is no longer in the specified status.
02993   * @param  husart USART handle.
02994   * @param  Flag Specifies the USART flag to check.
02995   * @param  Status the actual Flag status (SET or RESET).
02996   * @param  Tickstart Tick start value
02997   * @param  Timeout timeout duration.
02998   * @retval HAL status
02999   */
03000 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
03001                                                       uint32_t Tickstart, uint32_t Timeout)
03002 {
03003   /* Wait until flag is set */
03004   while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
03005   {
03006     /* Check for the Timeout */
03007     if (Timeout != HAL_MAX_DELAY)
03008     {
03009       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
03010       {
03011         husart->State = HAL_USART_STATE_READY;
03012
03013         /* Process Unlocked */
03014         __HAL_UNLOCK(husart);
03015
03016         return HAL_TIMEOUT;
03017       }
03018     }
03019   }
03020   return HAL_OK;
03021 }
03022
03023 /**
03024   * @brief Configure the USART peripheral.
03025   * @param husart USART handle.
03026   * @retval HAL status
03027   */
03028 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
03029 {
03030   uint32_t tmpreg;
03031   USART_ClockSourceTypeDef clocksource;
03032   HAL_StatusTypeDef ret                = HAL_OK;
03033   uint16_t brrtemp;
03034   uint32_t usartdiv                    = 0x00000000;
03035   uint32_t pclk;
03036
03037   /* Check the parameters */
03038   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
03039   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
03040   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
03041   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
03042   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
03043   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
03044   assert_param(IS_USART_PARITY(husart->Init.Parity));
03045   assert_param(IS_USART_MODE(husart->Init.Mode));
03046   assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler));
03047
03048   /*-------------------------- USART CR1 Configuration -----------------------*/
03049   /* Clear M, PCE, PS, TE and RE bits and configure
03050   *  the USART Word Length, Parity and Mode:
03051   *  set the M bits according to husart->Init.WordLength value
03052   *  set PCE and PS bits according to husart->Init.Parity value
03053   *  set TE and RE bits according to husart->Init.Mode value
03054   *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
03055   tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
03056   MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
03057
03058   /*---------------------------- USART CR2 Configuration ---------------------*/
03059   /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
03060    * set CPOL bit according to husart->Init.CLKPolarity value
03061    * set CPHA bit according to husart->Init.CLKPhase value
03062    * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
03063    * set STOP[13:12] bits according to husart->Init.StopBits value */
03064   tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
03065   tmpreg |= (uint32_t)husart->Init.CLKLastBit;
03066   tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
03067   tmpreg |= (uint32_t)husart->Init.StopBits;
03068   MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
03069
03070   /*-------------------------- USART PRESC Configuration -----------------------*/
03071   /* Configure
03072    * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */
03073   MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler);
03074
03075   /*-------------------------- USART BRR Configuration -----------------------*/
03076   /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
03077   USART_GETCLOCKSOURCE(husart, clocksource);
03078
03079   switch (clocksource)
03080   {
03081     case USART_CLOCKSOURCE_PCLK1:
03082       pclk = HAL_RCC_GetPCLK1Freq();
03083       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
03084       break;
03085     case USART_CLOCKSOURCE_HSI:
03086       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
03087       break;
03088     case USART_CLOCKSOURCE_SYSCLK:
03089       pclk = HAL_RCC_GetSysClockFreq();
03090       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
03091       break;
03092     case USART_CLOCKSOURCE_LSE:
03093       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
03094       break;
03095     default:
03096       ret = HAL_ERROR;
03097       break;
03098   }
03099
03100   /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
03101   if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
03102   {
03103     brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
03104     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
03105     husart->Instance->BRR = brrtemp;
03106   }
03107   else
03108   {
03109     ret = HAL_ERROR;
03110   }
03111
03112   /* Initialize the number of data to process during RX/TX ISR execution */
03113   husart->NbTxDataToProcess = 1U;
03114   husart->NbRxDataToProcess = 1U;
03115
03116   /* Clear ISR function pointers */
03117   husart->RxISR   = NULL;
03118   husart->TxISR   = NULL;
03119
03120   return ret;
03121 }
03122
03123 /**
03124   * @brief Check the USART Idle State.
03125   * @param husart USART handle.
03126   * @retval HAL status
03127   */
03128 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
03129 {
03130   uint32_t tickstart;
03131
03132   /* Initialize the USART ErrorCode */
03133   husart->ErrorCode = HAL_USART_ERROR_NONE;
03134
03135   /* Init tickstart for timeout management */
03136   tickstart = HAL_GetTick();
03137
03138   /* Check if the Transmitter is enabled */
03139   if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
03140   {
03141     /* Wait until TEACK flag is set */
03142     if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
03143     {
03144       /* Timeout occurred */
03145       return HAL_TIMEOUT;
03146     }
03147   }
03148   /* Check if the Receiver is enabled */
03149   if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
03150   {
03151     /* Wait until REACK flag is set */
03152     if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
03153     {
03154       /* Timeout occurred */
03155       return HAL_TIMEOUT;
03156     }
03157   }
03158
03159   /* Initialize the USART state*/
03160   husart->State = HAL_USART_STATE_READY;
03161
03162   /* Process Unlocked */
03163   __HAL_UNLOCK(husart);
03164
03165   return HAL_OK;
03166 }
03167
03168 /**
03169   * @brief  Simplex send an amount of data in non-blocking mode.
03170   * @note   Function called under interruption only, once
03171   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03172   * @note   The USART errors are not managed to avoid the overrun error.
03173   * @note   ISR function executed when FIFO mode is disabled and when the
03174   *         data word length is less than 9 bits long.
03175   * @param  husart USART handle.
03176   * @retval None
03177   */
03178 static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
03179 {
03180   const HAL_USART_StateTypeDef state = husart->State;
03181
03182   /* Check that a Tx process is ongoing */
03183   if ((state == HAL_USART_STATE_BUSY_TX) ||
03184       (state == HAL_USART_STATE_BUSY_TX_RX))
03185   {
03186     if (husart->TxXferCount == 0U)
03187     {
03188       /* Disable the USART Transmit data register empty interrupt */
03189       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
03190
03191       /* Enable the USART Transmit Complete Interrupt */
03192       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03193     }
03194     else
03195     {
03196       husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
03197       husart->pTxBuffPtr++;
03198       husart->TxXferCount--;
03199     }
03200   }
03201 }
03202
03203 /**
03204   * @brief  Simplex send an amount of data in non-blocking mode.
03205   * @note   Function called under interruption only, once
03206   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03207   * @note   The USART errors are not managed to avoid the overrun error.
03208   * @note   ISR function executed when FIFO mode is disabled and when the
03209   *         data word length is 9 bits long.
03210   * @param  husart USART handle.
03211   * @retval None
03212   */
03213 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
03214 {
03215   const HAL_USART_StateTypeDef state = husart->State;
03216   const uint16_t *tmp;
03217
03218   if ((state == HAL_USART_STATE_BUSY_TX) ||
03219       (state == HAL_USART_STATE_BUSY_TX_RX))
03220   {
03221     if (husart->TxXferCount == 0U)
03222     {
03223       /* Disable the USART Transmit data register empty interrupt */
03224       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
03225
03226       /* Enable the USART Transmit Complete Interrupt */
03227       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03228     }
03229     else
03230     {
03231       tmp = (const uint16_t *) husart->pTxBuffPtr;
03232       husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
03233       husart->pTxBuffPtr += 2U;
03234       husart->TxXferCount--;
03235     }
03236   }
03237 }
03238
03239 /**
03240   * @brief  Simplex send an amount of data in non-blocking mode.
03241   * @note   Function called under interruption only, once
03242   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03243   * @note   The USART errors are not managed to avoid the overrun error.
03244   * @note   ISR function executed when FIFO mode is enabled and when the
03245   *         data word length is less than 9 bits long.
03246   * @param  husart USART handle.
03247   * @retval None
03248   */
03249 static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
03250 {
03251   const HAL_USART_StateTypeDef state = husart->State;
03252   uint16_t  nb_tx_data;
03253
03254   /* Check that a Tx process is ongoing */
03255   if ((state == HAL_USART_STATE_BUSY_TX) ||
03256       (state == HAL_USART_STATE_BUSY_TX_RX))
03257   {
03258     for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03259     {
03260       if (husart->TxXferCount == 0U)
03261       {
03262         /* Disable the TX FIFO threshold interrupt */
03263         __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
03264
03265         /* Enable the USART Transmit Complete Interrupt */
03266         __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03267
03268         break; /* force exit loop */
03269       }
03270       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
03271       {
03272         husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
03273         husart->pTxBuffPtr++;
03274         husart->TxXferCount--;
03275       }
03276       else
03277       {
03278         /* Nothing to do */
03279       }
03280     }
03281   }
03282 }
03283
03284 /**
03285   * @brief  Simplex send an amount of data in non-blocking mode.
03286   * @note   Function called under interruption only, once
03287   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03288   * @note   The USART errors are not managed to avoid the overrun error.
03289   * @note   ISR function executed when FIFO mode is enabled and when the
03290   *         data word length is 9 bits long.
03291   * @param  husart USART handle.
03292   * @retval None
03293   */
03294 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
03295 {
03296   const HAL_USART_StateTypeDef state = husart->State;
03297   const uint16_t *tmp;
03298   uint16_t  nb_tx_data;
03299
03300   /* Check that a Tx process is ongoing */
03301   if ((state == HAL_USART_STATE_BUSY_TX) ||
03302       (state == HAL_USART_STATE_BUSY_TX_RX))
03303   {
03304     for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03305     {
03306       if (husart->TxXferCount == 0U)
03307       {
03308         /* Disable the TX FIFO threshold interrupt */
03309         __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
03310
03311         /* Enable the USART Transmit Complete Interrupt */
03312         __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03313
03314         break; /* force exit loop */
03315       }
03316       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
03317       {
03318         tmp = (const uint16_t *) husart->pTxBuffPtr;
03319         husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
03320         husart->pTxBuffPtr += 2U;
03321         husart->TxXferCount--;
03322       }
03323       else
03324       {
03325         /* Nothing to do */
03326       }
03327     }
03328   }
03329 }
03330
03331 /**
03332   * @brief  Wraps up transmission in non-blocking mode.
03333   * @param  husart Pointer to a USART_HandleTypeDef structure that contains
03334   *                the configuration information for the specified USART module.
03335   * @retval None
03336   */
03337 static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
03338 {
03339   /* Disable the USART Transmit Complete Interrupt */
03340   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
03341
03342   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03343   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
03344
03345   /* Clear TxISR function pointer */
03346   husart->TxISR = NULL;
03347
03348   if (husart->State == HAL_USART_STATE_BUSY_TX)
03349   {
03350     /* Clear overrun flag and discard the received data */
03351     __HAL_USART_CLEAR_OREFLAG(husart);
03352     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03353
03354     /* Tx process is completed, restore husart->State to Ready */
03355     husart->State = HAL_USART_STATE_READY;
03356
03357 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03358     /* Call registered Tx Complete Callback */
03359     husart->TxCpltCallback(husart);
03360 #else
03361     /* Call legacy weak Tx Complete Callback */
03362     HAL_USART_TxCpltCallback(husart);
03363 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03364   }
03365   else if (husart->RxXferCount == 0U)
03366   {
03367     /* TxRx process is completed, restore husart->State to Ready */
03368     husart->State = HAL_USART_STATE_READY;
03369
03370 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03371     /* Call registered Tx Rx Complete Callback */
03372     husart->TxRxCpltCallback(husart);
03373 #else
03374     /* Call legacy weak Tx Rx Complete Callback */
03375     HAL_USART_TxRxCpltCallback(husart);
03376 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03377   }
03378   else
03379   {
03380     /* Nothing to do */
03381   }
03382 }
03383
03384
03385 /**
03386   * @brief  Simplex receive an amount of data in non-blocking mode.
03387   * @note   Function called under interruption only, once
03388   *         interruptions have been enabled by HAL_USART_Receive_IT().
03389   * @note   ISR function executed when FIFO mode is disabled and when the
03390   *         data word length is less than 9 bits long.
03391   * @param  husart USART handle
03392   * @retval None
03393   */
03394 static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
03395 {
03396   const HAL_USART_StateTypeDef state = husart->State;
03397   uint16_t txdatacount;
03398   uint16_t uhMask = husart->Mask;
03399   uint32_t txftie;
03400
03401   if ((state == HAL_USART_STATE_BUSY_RX) ||
03402       (state == HAL_USART_STATE_BUSY_TX_RX))
03403   {
03404     *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
03405     husart->pRxBuffPtr++;
03406     husart->RxXferCount--;
03407
03408     if (husart->RxXferCount == 0U)
03409     {
03410       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
03411       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03412
03413       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03414       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
03415
03416       /* Clear RxISR function pointer */
03417       husart->RxISR = NULL;
03418
03419       /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03420       txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03421       txdatacount = husart->TxXferCount;
03422
03423       if (state == HAL_USART_STATE_BUSY_RX)
03424       {
03425         /* Clear SPI slave underrun flag and discard transmit data */
03426         if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03427         {
03428           __HAL_USART_CLEAR_UDRFLAG(husart);
03429           __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03430         }
03431
03432         /* Rx process is completed, restore husart->State to Ready */
03433         husart->State = HAL_USART_STATE_READY;
03434
03435 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03436         /* Call registered Rx Complete Callback */
03437         husart->RxCpltCallback(husart);
03438 #else
03439         /* Call legacy weak Rx Complete Callback */
03440         HAL_USART_RxCpltCallback(husart);
03441 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03442       }
03443       else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03444                (txftie != USART_CR3_TXFTIE) &&
03445                (txdatacount == 0U))
03446       {
03447         /* TxRx process is completed, restore husart->State to Ready */
03448         husart->State = HAL_USART_STATE_READY;
03449
03450 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03451         /* Call registered Tx Rx Complete Callback */
03452         husart->TxRxCpltCallback(husart);
03453 #else
03454         /* Call legacy weak Tx Rx Complete Callback */
03455         HAL_USART_TxRxCpltCallback(husart);
03456 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03457       }
03458       else
03459       {
03460         /* Nothing to do */
03461       }
03462     }
03463     else if ((state == HAL_USART_STATE_BUSY_RX) &&
03464              (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03465     {
03466       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03467       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03468     }
03469     else
03470     {
03471       /* Nothing to do */
03472     }
03473   }
03474 }
03475
03476 /**
03477   * @brief  Simplex receive an amount of data in non-blocking mode.
03478   * @note   Function called under interruption only, once
03479   *         interruptions have been enabled by HAL_USART_Receive_IT().
03480   * @note   ISR function executed when FIFO mode is disabled and when the
03481   *         data word length is 9 bits long.
03482   * @param  husart USART handle
03483   * @retval None
03484   */
03485 static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
03486 {
03487   const HAL_USART_StateTypeDef state = husart->State;
03488   uint16_t txdatacount;
03489   uint16_t *tmp;
03490   uint16_t uhMask = husart->Mask;
03491   uint32_t txftie;
03492
03493   if ((state == HAL_USART_STATE_BUSY_RX) ||
03494       (state == HAL_USART_STATE_BUSY_TX_RX))
03495   {
03496     tmp = (uint16_t *) husart->pRxBuffPtr;
03497     *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
03498     husart->pRxBuffPtr += 2U;
03499     husart->RxXferCount--;
03500
03501     if (husart->RxXferCount == 0U)
03502     {
03503       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
03504       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03505
03506       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03507       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
03508
03509       /* Clear RxISR function pointer */
03510       husart->RxISR = NULL;
03511
03512       /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03513       txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03514       txdatacount = husart->TxXferCount;
03515
03516       if (state == HAL_USART_STATE_BUSY_RX)
03517       {
03518         /* Clear SPI slave underrun flag and discard transmit data */
03519         if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03520         {
03521           __HAL_USART_CLEAR_UDRFLAG(husart);
03522           __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03523         }
03524
03525         /* Rx process is completed, restore husart->State to Ready */
03526         husart->State = HAL_USART_STATE_READY;
03527
03528 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03529         /* Call registered Rx Complete Callback */
03530         husart->RxCpltCallback(husart);
03531 #else
03532         /* Call legacy weak Rx Complete Callback */
03533         HAL_USART_RxCpltCallback(husart);
03534 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03535       }
03536       else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03537                (txftie != USART_CR3_TXFTIE) &&
03538                (txdatacount == 0U))
03539       {
03540         /* TxRx process is completed, restore husart->State to Ready */
03541         husart->State = HAL_USART_STATE_READY;
03542
03543 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03544         /* Call registered Tx Rx Complete Callback */
03545         husart->TxRxCpltCallback(husart);
03546 #else
03547         /* Call legacy weak Tx Rx Complete Callback */
03548         HAL_USART_TxRxCpltCallback(husart);
03549 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03550       }
03551       else
03552       {
03553         /* Nothing to do */
03554       }
03555     }
03556     else if ((state == HAL_USART_STATE_BUSY_RX) &&
03557              (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03558     {
03559       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03560       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03561     }
03562     else
03563     {
03564       /* Nothing to do */
03565     }
03566   }
03567 }
03568
03569 /**
03570   * @brief  Simplex receive an amount of data in non-blocking mode.
03571   * @note   Function called under interruption only, once
03572   *         interruptions have been enabled by HAL_USART_Receive_IT().
03573   * @note   ISR function executed when FIFO mode is enabled and when the
03574   *         data word length is less than 9 bits long.
03575   * @param  husart USART handle
03576   * @retval None
03577   */
03578 static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
03579 {
03580   HAL_USART_StateTypeDef state = husart->State;
03581   uint16_t txdatacount;
03582   uint16_t rxdatacount;
03583   uint16_t uhMask = husart->Mask;
03584   uint16_t nb_rx_data;
03585   uint32_t txftie;
03586
03587   /* Check that a Rx process is ongoing */
03588   if ((state == HAL_USART_STATE_BUSY_RX) ||
03589       (state == HAL_USART_STATE_BUSY_TX_RX))
03590   {
03591     for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03592     {
03593       if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
03594       {
03595         *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
03596         husart->pRxBuffPtr++;
03597         husart->RxXferCount--;
03598
03599         if (husart->RxXferCount == 0U)
03600         {
03601           /* Disable the USART Parity Error Interrupt */
03602           CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
03603
03604           /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
03605              and RX FIFO Threshold interrupt */
03606           CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03607
03608           /* Clear RxISR function pointer */
03609           husart->RxISR = NULL;
03610
03611           /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03612           txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03613           txdatacount = husart->TxXferCount;
03614
03615           if (state == HAL_USART_STATE_BUSY_RX)
03616           {
03617             /* Clear SPI slave underrun flag and discard transmit data */
03618             if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03619             {
03620               __HAL_USART_CLEAR_UDRFLAG(husart);
03621               __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03622             }
03623
03624             /* Rx process is completed, restore husart->State to Ready */
03625             husart->State = HAL_USART_STATE_READY;
03626             state = HAL_USART_STATE_READY;
03627
03628 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03629             /* Call registered Rx Complete Callback */
03630             husart->RxCpltCallback(husart);
03631 #else
03632             /* Call legacy weak Rx Complete Callback */
03633             HAL_USART_RxCpltCallback(husart);
03634 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03635           }
03636           else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03637                    (txftie != USART_CR3_TXFTIE) &&
03638                    (txdatacount == 0U))
03639           {
03640             /* TxRx process is completed, restore husart->State to Ready */
03641             husart->State = HAL_USART_STATE_READY;
03642             state = HAL_USART_STATE_READY;
03643
03644 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03645             /* Call registered Tx Rx Complete Callback */
03646             husart->TxRxCpltCallback(husart);
03647 #else
03648             /* Call legacy weak Tx Rx Complete Callback */
03649             HAL_USART_TxRxCpltCallback(husart);
03650 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03651           }
03652           else
03653           {
03654             /* Nothing to do */
03655           }
03656         }
03657         else if ((state == HAL_USART_STATE_BUSY_RX) &&
03658                  (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03659         {
03660           /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03661           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03662         }
03663         else
03664         {
03665           /* Nothing to do */
03666         }
03667       }
03668     }
03669
03670     /* When remaining number of bytes to receive is less than the RX FIFO
03671     threshold, next incoming frames are processed as if FIFO mode was
03672     disabled (i.e. one interrupt per received frame).
03673     */
03674     rxdatacount = husart->RxXferCount;
03675     if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
03676     {
03677       /* Disable the USART RXFT interrupt*/
03678       CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
03679
03680       /* Update the RxISR function pointer */
03681       husart->RxISR = USART_RxISR_8BIT;
03682
03683       /* Enable the USART Data Register Not Empty interrupt */
03684       SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03685
03686       if ((husart->TxXferCount == 0U) &&
03687           (state == HAL_USART_STATE_BUSY_TX_RX) &&
03688           (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03689       {
03690         /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03691         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03692       }
03693     }
03694   }
03695   else
03696   {
03697     /* Clear RXNE interrupt flag */
03698     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03699   }
03700 }
03701
03702 /**
03703   * @brief  Simplex receive an amount of data in non-blocking mode.
03704   * @note   Function called under interruption only, once
03705   *         interruptions have been enabled by HAL_USART_Receive_IT().
03706   * @note   ISR function executed when FIFO mode is enabled and when the
03707   *         data word length is 9 bits long.
03708   * @param  husart USART handle
03709   * @retval None
03710   */
03711 static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
03712 {
03713   HAL_USART_StateTypeDef state = husart->State;
03714   uint16_t txdatacount;
03715   uint16_t rxdatacount;
03716   uint16_t *tmp;
03717   uint16_t uhMask = husart->Mask;
03718   uint16_t nb_rx_data;
03719   uint32_t txftie;
03720
03721   /* Check that a Tx process is ongoing */
03722   if ((state == HAL_USART_STATE_BUSY_RX) ||
03723       (state == HAL_USART_STATE_BUSY_TX_RX))
03724   {
03725     for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03726     {
03727       if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
03728       {
03729         tmp = (uint16_t *) husart->pRxBuffPtr;
03730         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
03731         husart->pRxBuffPtr += 2U;
03732         husart->RxXferCount--;
03733
03734         if (husart->RxXferCount == 0U)
03735         {
03736           /* Disable the USART Parity Error Interrupt */
03737           CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
03738
03739           /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
03740              and RX FIFO Threshold interrupt */
03741           CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03742
03743           /* Clear RxISR function pointer */
03744           husart->RxISR = NULL;
03745
03746           /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
03747           txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
03748           txdatacount = husart->TxXferCount;
03749
03750           if (state == HAL_USART_STATE_BUSY_RX)
03751           {
03752             /* Clear SPI slave underrun flag and discard transmit data */
03753             if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03754             {
03755               __HAL_USART_CLEAR_UDRFLAG(husart);
03756               __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03757             }
03758
03759             /* Rx process is completed, restore husart->State to Ready */
03760             husart->State = HAL_USART_STATE_READY;
03761             state = HAL_USART_STATE_READY;
03762
03763 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03764             /* Call registered Rx Complete Callback */
03765             husart->RxCpltCallback(husart);
03766 #else
03767             /* Call legacy weak Rx Complete Callback */
03768             HAL_USART_RxCpltCallback(husart);
03769 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03770           }
03771           else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03772                    (txftie != USART_CR3_TXFTIE) &&
03773                    (txdatacount == 0U))
03774           {
03775             /* TxRx process is completed, restore husart->State to Ready */
03776             husart->State = HAL_USART_STATE_READY;
03777             state = HAL_USART_STATE_READY;
03778
03779 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03780             /* Call registered Tx Rx Complete Callback */
03781             husart->TxRxCpltCallback(husart);
03782 #else
03783             /* Call legacy weak Tx Rx Complete Callback */
03784             HAL_USART_TxRxCpltCallback(husart);
03785 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03786           }
03787           else
03788           {
03789             /* Nothing to do */
03790           }
03791         }
03792         else if ((state == HAL_USART_STATE_BUSY_RX) &&
03793                  (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03794         {
03795           /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03796           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03797         }
03798         else
03799         {
03800           /* Nothing to do */
03801         }
03802       }
03803     }
03804
03805     /* When remaining number of bytes to receive is less than the RX FIFO
03806     threshold, next incoming frames are processed as if FIFO mode was
03807     disabled (i.e. one interrupt per received frame).
03808     */
03809     rxdatacount = husart->RxXferCount;
03810     if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
03811     {
03812       /* Disable the USART RXFT interrupt*/
03813       CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
03814
03815       /* Update the RxISR function pointer */
03816       husart->RxISR = USART_RxISR_16BIT;
03817
03818       /* Enable the USART Data Register Not Empty interrupt */
03819       SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03820
03821       if ((husart->TxXferCount == 0U) &&
03822           (state == HAL_USART_STATE_BUSY_TX_RX) &&
03823           (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03824       {
03825         /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03826         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03827       }
03828     }
03829   }
03830   else
03831   {
03832     /* Clear RXNE interrupt flag */
03833     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03834   }
03835 }
03836
03837 /**
03838   * @}
03839   */
03840
03841 #endif /* HAL_USART_MODULE_ENABLED */
03842 /**
03843   * @}
03844   */
03845
03846 /**
03847   * @}
03848   */
03849
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_usart.h Source File

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stm32g0xx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_USART_H
00021 #define STM32G0xx_HAL_USART_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup USART
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /** @defgroup USART_Exported_Types USART Exported Types
00040   * @{
00041   */
00042
00043 /**
00044   * @brief USART Init Structure definition
00045   */
00046 typedef struct
00047 {
00048   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00049                                            The baud rate is computed using the following formula:
00050                                               Baud Rate Register[15:4] = ((2 * fclk_pres) /
00051                                               ((huart->Init.BaudRate)))[15:4]
00052                                               Baud Rate Register[3]    = 0
00053                                               Baud Rate Register[2:0]  =  (((2 * fclk_pres) /
00054                                               ((huart->Init.BaudRate)))[3:0]) >> 1
00055                                               where fclk_pres is the USART input clock frequency (fclk)
00056                                               divided by a prescaler.
00057                                            @note  Oversampling by 8 is systematically applied to
00058                                                   achieve high baud rates. */
00059
00060   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00061                                            This parameter can be a value of @ref USARTEx_Word_Length. */
00062
00063   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00064                                            This parameter can be a value of @ref USART_Stop_Bits. */
00065
00066   uint32_t Parity;                   /*!< Specifies the parity mode.
00067                                            This parameter can be a value of @ref USART_Parity
00068                                            @note When parity is enabled, the computed parity is inserted
00069                                                  at the MSB position of the transmitted data (9th bit when
00070                                                  the word length is set to 9 data bits; 8th bit when the
00071                                                  word length is set to 8 data bits). */
00072
00073   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00074                                            This parameter can be a value of @ref USART_Mode. */
00075
00076   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00077                                            This parameter can be a value of @ref USART_Clock_Polarity. */
00078
00079   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00080                                            This parameter can be a value of @ref USART_Clock_Phase. */
00081
00082   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00083                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00084                                            This parameter can be a value of @ref USART_Last_Bit. */
00085
00086   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
00087                                            This parameter can be a value of @ref USART_ClockPrescaler. */
00088 } USART_InitTypeDef;
00089
00090 /**
00091   * @brief HAL USART State structures definition
00092   */
00093 typedef enum
00094 {
00095   HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
00096   HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
00097   HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
00098   HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
00099   HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
00100   HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
00101   HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
00102   HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
00103 } HAL_USART_StateTypeDef;
00104
00105 /**
00106   * @brief  USART clock sources definitions
00107   */
00108 typedef enum
00109 {
00110   USART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source     */
00111   USART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
00112   USART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
00113   USART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00114   USART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00115 } USART_ClockSourceTypeDef;
00116
00117 /**
00118   * @brief  USART handle Structure definition
00119   */
00120 typedef struct __USART_HandleTypeDef
00121 {
00122   USART_TypeDef                 *Instance;               /*!< USART registers base address        */
00123
00124   USART_InitTypeDef             Init;                    /*!< USART communication parameters      */
00125
00126   const uint8_t                 *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */
00127
00128   uint16_t                      TxXferSize;              /*!< USART Tx Transfer size              */
00129
00130   __IO uint16_t                 TxXferCount;             /*!< USART Tx Transfer Counter           */
00131
00132   uint8_t                       *pRxBuffPtr;             /*!< Pointer to USART Rx transfer Buffer */
00133
00134   uint16_t                      RxXferSize;              /*!< USART Rx Transfer size              */
00135
00136   __IO uint16_t                 RxXferCount;             /*!< USART Rx Transfer Counter           */
00137
00138   uint16_t                      Mask;                    /*!< USART Rx RDR register mask          */
00139
00140   uint16_t                      NbRxDataToProcess;       /*!< Number of data to process during RX ISR execution */
00141
00142   uint16_t                      NbTxDataToProcess;       /*!< Number of data to process during TX ISR execution */
00143
00144   uint32_t                      SlaveMode;               /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
00145                                                               of @ref USARTEx_Slave_Mode */
00146
00147   uint32_t                      FifoMode;                /*!< Specifies if the FIFO mode will be used. This parameter can be a value
00148                                                               of @ref USARTEx_FIFO_mode. */
00149
00150   void (*RxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Rx IRQ handler  */
00151
00152   void (*TxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Tx IRQ handler  */
00153
00154   DMA_HandleTypeDef             *hdmatx;                 /*!< USART Tx DMA Handle parameters      */
00155
00156   DMA_HandleTypeDef             *hdmarx;                 /*!< USART Rx DMA Handle parameters      */
00157
00158   HAL_LockTypeDef               Lock;                    /*!< Locking object                      */
00159
00160   __IO HAL_USART_StateTypeDef   State;                   /*!< USART communication state           */
00161
00162   __IO uint32_t                 ErrorCode;               /*!< USART Error code                    */
00163
00164 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00165   void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
00166   void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
00167   void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
00168   void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
00169   void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
00170   void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
00171   void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
00172   void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Fifo Full Callback            */
00173   void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart);       /*!< USART Tx Fifo Empty Callback           */
00174
00175   void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
00176   void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
00177 #endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
00178
00179 } USART_HandleTypeDef;
00180
00181 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00182 /**
00183   * @brief  HAL USART Callback ID enumeration definition
00184   */
00185 typedef enum
00186 {
00187   HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
00188   HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
00189   HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
00190   HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
00191   HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
00192   HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
00193   HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
00194   HAL_USART_RX_FIFO_FULL_CB_ID            = 0x07U,    /*!< USART Rx Fifo Full Callback ID            */
00195   HAL_USART_TX_FIFO_EMPTY_CB_ID           = 0x08U,    /*!< USART Tx Fifo Empty Callback ID           */
00196
00197   HAL_USART_MSPINIT_CB_ID                 = 0x09U,    /*!< USART MspInit callback ID                 */
00198   HAL_USART_MSPDEINIT_CB_ID               = 0x0AU     /*!< USART MspDeInit callback ID               */
00199
00200 } HAL_USART_CallbackIDTypeDef;
00201
00202 /**
00203   * @brief  HAL USART Callback pointer definition
00204   */
00205 typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
00206
00207 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00208
00209 /**
00210   * @}
00211   */
00212
00213 /* Exported constants --------------------------------------------------------*/
00214 /** @defgroup USART_Exported_Constants USART Exported Constants
00215   * @{
00216   */
00217
00218 /** @defgroup USART_Error_Definition   USART Error Definition
00219   * @{
00220   */
00221 #define HAL_USART_ERROR_NONE             (0x00000000U)    /*!< No error                  */
00222 #define HAL_USART_ERROR_PE               (0x00000001U)    /*!< Parity error              */
00223 #define HAL_USART_ERROR_NE               (0x00000002U)    /*!< Noise error               */
00224 #define HAL_USART_ERROR_FE               (0x00000004U)    /*!< Frame error               */
00225 #define HAL_USART_ERROR_ORE              (0x00000008U)    /*!< Overrun error             */
00226 #define HAL_USART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error        */
00227 #define HAL_USART_ERROR_UDR              (0x00000020U)    /*!< SPI slave underrun error  */
00228 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00229 #define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error    */
00230 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00231 #define  HAL_USART_ERROR_RTO              (0x00000080U)    /*!< Receiver Timeout error  */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup USART_Stop_Bits  USART Number of Stop Bits
00237   * @{
00238   */
00239 #define USART_STOPBITS_0_5                   USART_CR2_STOP_0                     /*!< USART frame with 0.5 stop bit  */
00240 #define USART_STOPBITS_1                     0x00000000U                          /*!< USART frame with 1 stop bit    */
00241 #define USART_STOPBITS_1_5                  (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
00242 #define USART_STOPBITS_2                     USART_CR2_STOP_1                     /*!< USART frame with 2 stop bits   */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup USART_Parity    USART Parity
00248   * @{
00249   */
00250 #define USART_PARITY_NONE                   0x00000000U                      /*!< No parity   */
00251 #define USART_PARITY_EVEN                   USART_CR1_PCE                    /*!< Even parity */
00252 #define USART_PARITY_ODD                    (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup USART_Mode   USART Mode
00258   * @{
00259   */
00260 #define USART_MODE_RX                       USART_CR1_RE                    /*!< RX mode        */
00261 #define USART_MODE_TX                       USART_CR1_TE                    /*!< TX mode        */
00262 #define USART_MODE_TX_RX                    (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup USART_Clock  USART Clock
00268   * @{
00269   */
00270 #define USART_CLOCK_DISABLE                 0x00000000U       /*!< USART clock disable */
00271 #define USART_CLOCK_ENABLE                  USART_CR2_CLKEN   /*!< USART clock enable  */
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup USART_Clock_Polarity  USART Clock Polarity
00277   * @{
00278   */
00279 #define USART_POLARITY_LOW                  0x00000000U      /*!< Driver enable signal is active high */
00280 #define USART_POLARITY_HIGH                 USART_CR2_CPOL   /*!< Driver enable signal is active low  */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup USART_Clock_Phase   USART Clock Phase
00286   * @{
00287   */
00288 #define USART_PHASE_1EDGE                   0x00000000U      /*!< USART frame phase on first clock transition  */
00289 #define USART_PHASE_2EDGE                   USART_CR2_CPHA   /*!< USART frame phase on second clock transition */
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup USART_Last_Bit  USART Last Bit
00295   * @{
00296   */
00297 #define USART_LASTBIT_DISABLE               0x00000000U      /*!< USART frame last data bit clock pulse not output to SCLK pin */
00298 #define USART_LASTBIT_ENABLE                USART_CR2_LBCL   /*!< USART frame last data bit clock pulse output to SCLK pin     */
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup USART_ClockPrescaler  USART Clock Prescaler
00304   * @{
00305   */
00306 #define USART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00307 #define USART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00308 #define USART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00309 #define USART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00310 #define USART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00311 #define USART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00312 #define USART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00313 #define USART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00314 #define USART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00315 #define USART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00316 #define USART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00317 #define USART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00318
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup USART_Request_Parameters  USART Request Parameters
00324   * @{
00325   */
00326 #define USART_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00327 #define USART_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup USART_Flags      USART Flags
00333   *        Elements values convention: 0xXXXX
00334   *           - 0xXXXX  : Flag mask in the ISR register
00335   * @{
00336   */
00337 #define USART_FLAG_TXFT                     USART_ISR_TXFT          /*!< USART TXFIFO threshold flag                */
00338 #define USART_FLAG_RXFT                     USART_ISR_RXFT          /*!< USART RXFIFO threshold flag                */
00339 #define USART_FLAG_RXFF                     USART_ISR_RXFF          /*!< USART RXFIFO Full flag                     */
00340 #define USART_FLAG_TXFE                     USART_ISR_TXFE          /*!< USART TXFIFO Empty flag                    */
00341 #define USART_FLAG_REACK                    USART_ISR_REACK         /*!< USART receive enable acknowledge flag      */
00342 #define USART_FLAG_TEACK                    USART_ISR_TEACK         /*!< USART transmit enable acknowledge flag     */
00343 #define USART_FLAG_BUSY                     USART_ISR_BUSY          /*!< USART busy flag                            */
00344 #define USART_FLAG_UDR                      USART_ISR_UDR           /*!< SPI slave underrun error flag              */
00345 #define USART_FLAG_TXE                      USART_ISR_TXE_TXFNF     /*!< USART transmit data register empty         */
00346 #define USART_FLAG_TXFNF                    USART_ISR_TXE_TXFNF     /*!< USART TXFIFO not full                      */
00347 #define USART_FLAG_RTOF                     USART_ISR_RTOF          /*!< USART receiver timeout flag                */
00348 #define USART_FLAG_TC                       USART_ISR_TC            /*!< USART transmission complete                */
00349 #define USART_FLAG_RXNE                     USART_ISR_RXNE_RXFNE    /*!< USART read data register not empty         */
00350 #define USART_FLAG_RXFNE                    USART_ISR_RXNE_RXFNE    /*!< USART RXFIFO not empty                     */
00351 #define USART_FLAG_IDLE                     USART_ISR_IDLE          /*!< USART idle flag                            */
00352 #define USART_FLAG_ORE                      USART_ISR_ORE           /*!< USART overrun error                        */
00353 #define USART_FLAG_NE                       USART_ISR_NE            /*!< USART noise error                          */
00354 #define USART_FLAG_FE                       USART_ISR_FE            /*!< USART frame error                          */
00355 #define USART_FLAG_PE                       USART_ISR_PE            /*!< USART parity error                         */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00361   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00362   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00363   *           - XX  : Interrupt source register (2bits)
00364   *                 - 01: CR1 register
00365   *                 - 10: CR2 register
00366   *                 - 11: CR3 register
00367   *           - ZZZZ  : Flag position in the ISR register(4bits)
00368   * @{
00369   */
00370
00371 #define USART_IT_PE                          0x0028U     /*!< USART parity error interruption                 */
00372 #define USART_IT_TXE                         0x0727U     /*!< USART transmit data register empty interruption */
00373 #define USART_IT_TXFNF                       0x0727U     /*!< USART TX FIFO not full interruption             */
00374 #define USART_IT_TC                          0x0626U     /*!< USART transmission complete interruption        */
00375 #define USART_IT_RXNE                        0x0525U     /*!< USART read data register not empty interruption */
00376 #define USART_IT_RXFNE                       0x0525U     /*!< USART RXFIFO not empty interruption             */
00377 #define USART_IT_IDLE                        0x0424U     /*!< USART idle interruption                         */
00378 #define USART_IT_ERR                         0x0060U     /*!< USART error interruption                        */
00379 #define USART_IT_ORE                         0x0300U     /*!< USART overrun error interruption                */
00380 #define USART_IT_NE                          0x0200U     /*!< USART noise error interruption                  */
00381 #define USART_IT_FE                          0x0100U     /*!< USART frame error interruption                  */
00382 #define USART_IT_RXFF                        0x183FU     /*!< USART RXFIFO full interruption                  */
00383 #define USART_IT_TXFE                        0x173EU     /*!< USART TXFIFO empty interruption                 */
00384 #define USART_IT_RXFT                        0x1A7CU     /*!< USART RXFIFO threshold reached interruption     */
00385 #define USART_IT_TXFT                        0x1B77U     /*!< USART TXFIFO threshold reached interruption     */
00386
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
00392   * @{
00393   */
00394 #define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag             */
00395 #define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag            */
00396 #define USART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag     */
00397 #define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag            */
00398 #define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag       */
00399 #define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag    */
00400 #define USART_CLEAR_UDRF                      USART_ICR_UDRCF           /*!< SPI slave underrun error Clear Flag */
00401 #define USART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO Empty Clear Flag             */
00402 #define USART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< USART receiver timeout clear flag  */
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
00408   * @{
00409   */
00410 #define USART_IT_MASK                             0x001FU     /*!< USART interruptions flags mask */
00411 #define USART_CR_MASK                             0x00E0U     /*!< USART control register mask */
00412 #define USART_CR_POS                              5U          /*!< USART control register position */
00413 #define USART_ISR_MASK                            0x1F00U     /*!< USART ISR register mask         */
00414 #define USART_ISR_POS                             8U          /*!< USART ISR register position     */
00415 /**
00416   * @}
00417   */
00418
00419 /**
00420   * @}
00421   */
00422
00423 /* Exported macros -----------------------------------------------------------*/
00424 /** @defgroup USART_Exported_Macros USART Exported Macros
00425   * @{
00426   */
00427
00428 /** @brief Reset USART handle state.
00429   * @param  __HANDLE__ USART handle.
00430   * @retval None
00431   */
00432 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00433 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
00434                                                         (__HANDLE__)->State = HAL_USART_STATE_RESET; \
00435                                                         (__HANDLE__)->MspInitCallback = NULL;        \
00436                                                         (__HANDLE__)->MspDeInitCallback = NULL;      \
00437                                                       } while(0U)
00438 #else
00439 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00440 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00441
00442 /** @brief  Check whether the specified USART flag is set or not.
00443   * @param  __HANDLE__ specifies the USART Handle
00444   * @param  __FLAG__ specifies the flag to check.
00445   *        This parameter can be one of the following values:
00446   *            @arg @ref USART_FLAG_TXFT  TXFIFO threshold flag
00447   *            @arg @ref USART_FLAG_RXFT  RXFIFO threshold flag
00448   *            @arg @ref USART_FLAG_RXFF  RXFIFO Full flag
00449   *            @arg @ref USART_FLAG_TXFE  TXFIFO Empty flag
00450   *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
00451   *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
00452   *            @arg @ref USART_FLAG_BUSY  Busy flag
00453   *            @arg @ref USART_FLAG_UDR   SPI slave underrun error flag
00454   *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
00455   *            @arg @ref USART_FLAG_TXFNF TXFIFO not full flag
00456   *            @arg @ref USART_FLAG_TC    Transmission Complete flag
00457   *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
00458   *            @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
00459   *            @arg @ref USART_FLAG_RTOF  Receiver Timeout flag
00460   *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
00461   *            @arg @ref USART_FLAG_ORE   OverRun Error flag
00462   *            @arg @ref USART_FLAG_NE    Noise Error flag
00463   *            @arg @ref USART_FLAG_FE    Framing Error flag
00464   *            @arg @ref USART_FLAG_PE    Parity Error flag
00465   * @retval The new state of __FLAG__ (TRUE or FALSE).
00466   */
00467 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00468
00469 /** @brief  Clear the specified USART pending flag.
00470   * @param  __HANDLE__ specifies the USART Handle.
00471   * @param  __FLAG__ specifies the flag to check.
00472   *          This parameter can be any combination of the following values:
00473   *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
00474   *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
00475   *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
00476   *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
00477   *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
00478   *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
00479   *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
00480   *            @arg @ref USART_CLEAR_RTOF     Receiver Timeout clear flag
00481   *            @arg @ref USART_CLEAR_UDRF     SPI slave underrun error Clear Flag
00482   * @retval None
00483   */
00484 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00485
00486 /** @brief  Clear the USART PE pending flag.
00487   * @param  __HANDLE__ specifies the USART Handle.
00488   * @retval None
00489   */
00490 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
00491
00492 /** @brief  Clear the USART FE pending flag.
00493   * @param  __HANDLE__ specifies the USART Handle.
00494   * @retval None
00495   */
00496 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
00497
00498 /** @brief  Clear the USART NE pending flag.
00499   * @param  __HANDLE__ specifies the USART Handle.
00500   * @retval None
00501   */
00502 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
00503
00504 /** @brief  Clear the USART ORE pending flag.
00505   * @param  __HANDLE__ specifies the USART Handle.
00506   * @retval None
00507   */
00508 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
00509
00510 /** @brief  Clear the USART IDLE pending flag.
00511   * @param  __HANDLE__ specifies the USART Handle.
00512   * @retval None
00513   */
00514 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
00515
00516 /** @brief  Clear the USART TX FIFO empty clear flag.
00517   * @param  __HANDLE__ specifies the USART Handle.
00518   * @retval None
00519   */
00520 #define __HAL_USART_CLEAR_TXFECF(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
00521
00522 /** @brief  Clear SPI slave underrun error flag.
00523   * @param  __HANDLE__ specifies the USART Handle.
00524   * @retval None
00525   */
00526 #define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
00527
00528 /** @brief  Enable the specified USART interrupt.
00529   * @param  __HANDLE__ specifies the USART Handle.
00530   * @param  __INTERRUPT__ specifies the USART interrupt source to enable.
00531   *          This parameter can be one of the following values:
00532   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00533   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00534   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00535   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00536   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00537   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00538   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00539   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00540   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00541   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00542   *            @arg @ref USART_IT_PE    Parity Error interrupt
00543   *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
00544   * @retval None
00545   */
00546 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
00547   (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
00548    ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00549    ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
00550    ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00551    ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00552
00553 /** @brief  Disable the specified USART interrupt.
00554   * @param  __HANDLE__ specifies the USART Handle.
00555   * @param  __INTERRUPT__ specifies the USART interrupt source to disable.
00556   *          This parameter can be one of the following values:
00557   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00558   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00559   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00560   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00561   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00562   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00563   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00564   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00565   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00566   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00567   *            @arg @ref USART_IT_PE    Parity Error interrupt
00568   *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
00569   * @retval None
00570   */
00571 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
00572   (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
00573    ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00574    ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
00575    ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00576    ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00577
00578 /** @brief  Check whether the specified USART interrupt has occurred or not.
00579   * @param  __HANDLE__ specifies the USART Handle.
00580   * @param  __INTERRUPT__ specifies the USART interrupt source to check.
00581   *          This parameter can be one of the following values:
00582   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00583   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00584   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00585   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00586   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00587   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00588   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00589   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00590   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00591   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00592   *            @arg @ref USART_IT_ORE   OverRun Error interrupt
00593   *            @arg @ref USART_IT_NE    Noise Error interrupt
00594   *            @arg @ref USART_IT_FE    Framing Error interrupt
00595   *            @arg @ref USART_IT_PE    Parity Error interrupt
00596   * @retval The new state of __INTERRUPT__ (SET or RESET).
00597   */
00598 #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
00599                                                          & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
00600                                                                       USART_ISR_POS))) != 0U) ? SET : RESET)
00601
00602 /** @brief  Check whether the specified USART interrupt source is enabled or not.
00603   * @param  __HANDLE__ specifies the USART Handle.
00604   * @param  __INTERRUPT__ specifies the USART interrupt source to check.
00605   *          This parameter can be one of the following values:
00606   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00607   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00608   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00609   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00610   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00611   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00612   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00613   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00614   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00615   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00616   *            @arg @ref USART_IT_ORE   OverRun Error interrupt
00617   *            @arg @ref USART_IT_NE    Noise Error interrupt
00618   *            @arg @ref USART_IT_FE    Framing Error interrupt
00619   *            @arg @ref USART_IT_PE    Parity Error interrupt
00620   * @retval The new state of __INTERRUPT__ (SET or RESET).
00621   */
00622 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
00623                                                                  (__HANDLE__)->Instance->CR1 : \
00624                                                                  (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
00625                                                                   (__HANDLE__)->Instance->CR2 : \
00626                                                                   (__HANDLE__)->Instance->CR3)) & (0x01U <<\
00627                                                                       (((uint16_t)(__INTERRUPT__)) &\
00628                                                                        USART_IT_MASK)))  != 0U) ? SET : RESET)
00629
00630 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
00631   * @param  __HANDLE__ specifies the USART Handle.
00632   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00633   *                       to clear the corresponding interrupt.
00634   *          This parameter can be one of the following values:
00635   *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
00636   *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
00637   *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
00638   *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
00639   *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
00640   *            @arg @ref USART_CLEAR_RTOF     Receiver timeout clear flag
00641   *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
00642   *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
00643   * @retval None
00644   */
00645 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00646
00647 /** @brief  Set a specific USART request flag.
00648   * @param  __HANDLE__ specifies the USART Handle.
00649   * @param  __REQ__ specifies the request flag to set.
00650   *          This parameter can be one of the following values:
00651   *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
00652   *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
00653   *
00654   * @retval None
00655   */
00656 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00657
00658 /** @brief  Enable the USART one bit sample method.
00659   * @param  __HANDLE__ specifies the USART Handle.
00660   * @retval None
00661   */
00662 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00663
00664 /** @brief  Disable the USART one bit sample method.
00665   * @param  __HANDLE__ specifies the USART Handle.
00666   * @retval None
00667   */
00668 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
00669
00670 /** @brief  Enable USART.
00671   * @param  __HANDLE__ specifies the USART Handle.
00672   * @retval None
00673   */
00674 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
00675
00676 /** @brief  Disable USART.
00677   * @param  __HANDLE__ specifies the USART Handle.
00678   * @retval None
00679   */
00680 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
00681
00682 /**
00683   * @}
00684   */
00685
00686 /* Private macros --------------------------------------------------------*/
00687 /** @defgroup USART_Private_Macros   USART Private Macros
00688   * @{
00689   */
00690
00691 /** @brief  Get USART clock division factor from clock prescaler value.
00692   * @param  __CLOCKPRESCALER__ USART prescaler value.
00693   * @retval USART clock division factor
00694   */
00695 #define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
00696   (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
00697    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
00698    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
00699    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
00700    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
00701    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
00702    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
00703    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
00704    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
00705    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
00706    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
00707    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
00708
00709 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
00710   * @param  __PCLK__ USART clock.
00711   * @param  __BAUD__ Baud rate set by the user.
00712   * @param  __CLOCKPRESCALER__ USART prescaler value.
00713   * @retval Division result
00714   */
00715 #define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
00716   (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
00717     + ((__BAUD__)/2U)) / (__BAUD__))
00718
00719 /** @brief  Check USART Baud rate.
00720   * @param  __BAUDRATE__ Baudrate specified by the user.
00721   *         The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 64 MHz)
00722   *         divided by the smallest oversampling used on the USART (i.e. 8)
00723   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)  */
00724 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
00725
00726 /**
00727   * @brief Ensure that USART frame number of stop bits is valid.
00728   * @param __STOPBITS__ USART frame number of stop bits.
00729   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00730   */
00731 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
00732                                          ((__STOPBITS__) == USART_STOPBITS_1)   || \
00733                                          ((__STOPBITS__) == USART_STOPBITS_1_5) || \
00734                                          ((__STOPBITS__) == USART_STOPBITS_2))
00735
00736 /**
00737   * @brief Ensure that USART frame parity is valid.
00738   * @param __PARITY__ USART frame parity.
00739   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00740   */
00741 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
00742                                      ((__PARITY__) == USART_PARITY_EVEN) || \
00743                                      ((__PARITY__) == USART_PARITY_ODD))
00744
00745 /**
00746   * @brief Ensure that USART communication mode is valid.
00747   * @param __MODE__ USART communication mode.
00748   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00749   */
00750 #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
00751
00752 /**
00753   * @brief Ensure that USART clock state is valid.
00754   * @param __CLOCK__ USART clock state.
00755   * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
00756   */
00757 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
00758                                    ((__CLOCK__) == USART_CLOCK_ENABLE))
00759
00760 /**
00761   * @brief Ensure that USART frame polarity is valid.
00762   * @param __CPOL__ USART frame polarity.
00763   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00764   */
00765 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
00766
00767 /**
00768   * @brief Ensure that USART frame phase is valid.
00769   * @param __CPHA__ USART frame phase.
00770   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00771   */
00772 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
00773
00774 /**
00775   * @brief Ensure that USART frame last bit clock pulse setting is valid.
00776   * @param __LASTBIT__ USART frame last bit clock pulse setting.
00777   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00778   */
00779 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
00780                                        ((__LASTBIT__) == USART_LASTBIT_ENABLE))
00781
00782 /**
00783   * @brief Ensure that USART request parameter is valid.
00784   * @param __PARAM__ USART request parameter.
00785   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00786   */
00787 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
00788                                                ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
00789
00790 /**
00791   * @brief Ensure that USART Prescaler is valid.
00792   * @param __CLOCKPRESCALER__ USART Prescaler value.
00793   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00794   */
00795 #define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
00796                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
00797                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
00798                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
00799                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
00800                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
00801                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
00802                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
00803                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
00804                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
00805                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
00806                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))
00807
00808 /**
00809   * @}
00810   */
00811
00812 /* Include USART HAL Extended module */
00813 #include "stm32g0xx_hal_usart_ex.h"
00814
00815 /* Exported functions --------------------------------------------------------*/
00816 /** @addtogroup USART_Exported_Functions USART Exported Functions
00817   * @{
00818   */
00819
00820 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00821   * @{
00822   */
00823
00824 /* Initialization and de-initialization functions  ****************************/
00825 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00826 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00827 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00828 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
00829
00830 /* Callbacks Register/UnRegister functions  ***********************************/
00831 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00832 HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
00833                                              pUSART_CallbackTypeDef pCallback);
00834 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
00835 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00836
00837 /**
00838   * @}
00839   */
00840
00841 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
00842   * @{
00843   */
00844
00845 /* IO operation functions *****************************************************/
00846 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
00847                                      uint32_t Timeout);
00848 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00849 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
00850                                             uint16_t Size, uint32_t Timeout);
00851 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
00852 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00853 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
00854                                                uint16_t Size);
00855 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
00856 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00857 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
00858                                                 uint16_t Size);
00859 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
00860 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
00861 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
00862 /* Transfer Abort functions */
00863 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
00864 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
00865
00866 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
00867 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
00868 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
00869 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
00870 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
00871 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
00872 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
00873 void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
00874
00875 /**
00876   * @}
00877   */
00878
00879 /** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
00880   * @{
00881   */
00882
00883 /* Peripheral State and Error functions ***************************************/
00884 HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
00885 uint32_t               HAL_USART_GetError(const USART_HandleTypeDef *husart);
00886
00887 /**
00888   * @}
00889   */
00890
00891 /**
00892   * @}
00893   */
00894
00895 /**
00896   * @}
00897   */
00898
00899 /**
00900   * @}
00901   */
00902
00903 #ifdef __cplusplus
00904 }
00905 #endif
00906
00907 #endif /* STM32G0xx_HAL_USART_H */
00908
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_usart_ex.c Source File

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stm32g0xx_hal_usart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_usart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended USART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
00008   *           + Peripheral Control functions
00009   *
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * Copyright (c) 2018 STMicroelectronics.
00015   * All rights reserved.
00016   *
00017   * This software is licensed under terms that can be found in the LICENSE file
00018   * in the root directory of this software component.
00019   * If no LICENSE file comes with this software, it is provided AS-IS.
00020   *
00021   ******************************************************************************
00022   @verbatim
00023   ==============================================================================
00024                ##### USART peripheral extended features  #####
00025   ==============================================================================
00026
00027     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00028
00029         -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
00030             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00031             configured prior starting RX/TX transfers.
00032
00033     (#) Slave mode enabling/disabling and NSS pin configuration.
00034
00035         -@- When USART operates in Slave mode, Slave mode must be enabled prior
00036             starting RX/TX transfers.
00037
00038   @endverbatim
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32g0xx_hal.h"
00044
00045 /** @addtogroup STM32G0xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup USARTEx USARTEx
00050   * @brief USART Extended HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_USART_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /** @defgroup USARTEx_Private_Constants USARTEx Private Constants
00058   * @{
00059   */
00060 /* USART RX FIFO depth */
00061 #define RX_FIFO_DEPTH 8U
00062
00063 /* USART TX FIFO depth */
00064 #define TX_FIFO_DEPTH 8U
00065 /**
00066   * @}
00067   */
00068
00069 /* Private define ------------------------------------------------------------*/
00070 /* Private macros ------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 /** @defgroup USARTEx_Private_Functions USARTEx Private Functions
00074   * @{
00075   */
00076 static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
00077 /**
00078   * @}
00079   */
00080
00081 /* Exported functions --------------------------------------------------------*/
00082
00083 /** @defgroup USARTEx_Exported_Functions  USARTEx Exported Functions
00084   * @{
00085   */
00086
00087 /** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
00088   * @brief Extended USART Transmit/Receive functions
00089   *
00090 @verbatim
00091  ===============================================================================
00092                       ##### IO operation functions #####
00093  ===============================================================================
00094     This subsection provides a set of FIFO mode related callback functions.
00095
00096     (#) TX/RX Fifos Callbacks:
00097         (+) HAL_USARTEx_RxFifoFullCallback()
00098         (+) HAL_USARTEx_TxFifoEmptyCallback()
00099
00100 @endverbatim
00101   * @{
00102   */
00103
00104 /**
00105   * @brief  USART RX Fifo full callback.
00106   * @param  husart USART handle.
00107   * @retval None
00108   */
00109 __weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
00110 {
00111   /* Prevent unused argument(s) compilation warning */
00112   UNUSED(husart);
00113
00114   /* NOTE : This function should not be modified, when the callback is needed,
00115             the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
00116    */
00117 }
00118
00119 /**
00120   * @brief  USART TX Fifo empty callback.
00121   * @param  husart USART handle.
00122   * @retval None
00123   */
00124 __weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
00125 {
00126   /* Prevent unused argument(s) compilation warning */
00127   UNUSED(husart);
00128
00129   /* NOTE : This function should not be modified, when the callback is needed,
00130             the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
00131    */
00132 }
00133
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
00139   * @brief    Extended Peripheral Control functions
00140   *
00141 @verbatim
00142  ===============================================================================
00143                       ##### Peripheral Control functions #####
00144  ===============================================================================
00145     [..] This section provides the following functions:
00146      (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
00147      (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
00148      (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
00149      (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
00150      (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
00151      (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00152      (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00153
00154
00155 @endverbatim
00156   * @{
00157   */
00158
00159 /**
00160   * @brief  Enable the SPI slave mode.
00161   * @note When the USART operates in SPI slave mode, it handles data flow using
00162   *       the serial interface clock derived from the external SCLK signal
00163   *       provided by the external master SPI device.
00164   * @note In SPI slave mode, the USART must be enabled before starting the master
00165   *       communications (or between frames while the clock is stable). Otherwise,
00166   *       if the USART slave is enabled while the master is in the middle of a
00167   *       frame, it will become desynchronized with the master.
00168   * @note The data register of the slave needs to be ready before the first edge
00169   *       of the communication clock or before the end of the ongoing communication,
00170   *       otherwise the SPI slave will transmit zeros.
00171   * @param husart      USART handle.
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
00175 {
00176   uint32_t tmpcr1;
00177
00178   /* Check parameters */
00179   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00180
00181   /* Process Locked */
00182   __HAL_LOCK(husart);
00183
00184   husart->State = HAL_USART_STATE_BUSY;
00185
00186   /* Save actual USART configuration */
00187   tmpcr1 = READ_REG(husart->Instance->CR1);
00188
00189   /* Disable USART */
00190   __HAL_USART_DISABLE(husart);
00191
00192   /* In SPI slave mode mode, the following bits must be kept cleared:
00193   - LINEN and CLKEN bit in the USART_CR2 register
00194   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00195   CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00196   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00197
00198   /* Enable SPI slave mode */
00199   SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
00200
00201   /* Restore USART configuration */
00202   WRITE_REG(husart->Instance->CR1, tmpcr1);
00203
00204   husart->SlaveMode = USART_SLAVEMODE_ENABLE;
00205
00206   husart->State = HAL_USART_STATE_READY;
00207
00208   /* Enable USART */
00209   __HAL_USART_ENABLE(husart);
00210
00211   /* Process Unlocked */
00212   __HAL_UNLOCK(husart);
00213
00214   return HAL_OK;
00215 }
00216
00217 /**
00218   * @brief  Disable the SPI slave mode.
00219   * @param husart      USART handle.
00220   * @retval HAL status
00221   */
00222 HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
00223 {
00224   uint32_t tmpcr1;
00225
00226   /* Check parameters */
00227   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00228
00229   /* Process Locked */
00230   __HAL_LOCK(husart);
00231
00232   husart->State = HAL_USART_STATE_BUSY;
00233
00234   /* Save actual USART configuration */
00235   tmpcr1 = READ_REG(husart->Instance->CR1);
00236
00237   /* Disable USART */
00238   __HAL_USART_DISABLE(husart);
00239
00240   /* Disable SPI slave mode */
00241   CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
00242
00243   /* Restore USART configuration */
00244   WRITE_REG(husart->Instance->CR1, tmpcr1);
00245
00246   husart->SlaveMode = USART_SLAVEMODE_DISABLE;
00247
00248   husart->State = HAL_USART_STATE_READY;
00249
00250   /* Process Unlocked */
00251   __HAL_UNLOCK(husart);
00252
00253   return HAL_OK;
00254 }
00255
00256 /**
00257   * @brief  Configure the Slave Select input pin (NSS).
00258   * @note Software NSS management: SPI slave will always be selected and NSS
00259   *       input pin will be ignored.
00260   * @note Hardware NSS management: the SPI slave selection depends on NSS
00261   *       input pin. The slave is selected when NSS is low and deselected when
00262   *       NSS is high.
00263   * @param husart      USART handle.
00264   * @param NSSConfig   NSS configuration.
00265   *          This parameter can be one of the following values:
00266   *            @arg @ref USART_NSS_HARD
00267   *            @arg @ref USART_NSS_SOFT
00268   * @retval HAL status
00269   */
00270 HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
00271 {
00272   uint32_t tmpcr1;
00273
00274   /* Check parameters */
00275   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00276   assert_param(IS_USART_NSS(NSSConfig));
00277
00278   /* Process Locked */
00279   __HAL_LOCK(husart);
00280
00281   husart->State = HAL_USART_STATE_BUSY;
00282
00283   /* Save actual USART configuration */
00284   tmpcr1 = READ_REG(husart->Instance->CR1);
00285
00286   /* Disable USART */
00287   __HAL_USART_DISABLE(husart);
00288
00289   /* Program DIS_NSS bit in the USART_CR2 register */
00290   MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
00291
00292   /* Restore USART configuration */
00293   WRITE_REG(husart->Instance->CR1, tmpcr1);
00294
00295   husart->State = HAL_USART_STATE_READY;
00296
00297   /* Process Unlocked */
00298   __HAL_UNLOCK(husart);
00299
00300   return HAL_OK;
00301 }
00302
00303 /**
00304   * @brief  Enable the FIFO mode.
00305   * @param husart      USART handle.
00306   * @retval HAL status
00307   */
00308 HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
00309 {
00310   uint32_t tmpcr1;
00311
00312   /* Check parameters */
00313   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00314
00315   /* Process Locked */
00316   __HAL_LOCK(husart);
00317
00318   husart->State = HAL_USART_STATE_BUSY;
00319
00320   /* Save actual USART configuration */
00321   tmpcr1 = READ_REG(husart->Instance->CR1);
00322
00323   /* Disable USART */
00324   __HAL_USART_DISABLE(husart);
00325
00326   /* Enable FIFO mode */
00327   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00328   husart->FifoMode = USART_FIFOMODE_ENABLE;
00329
00330   /* Restore USART configuration */
00331   WRITE_REG(husart->Instance->CR1, tmpcr1);
00332
00333   /* Determine the number of data to process during RX/TX ISR execution */
00334   USARTEx_SetNbDataToProcess(husart);
00335
00336   husart->State = HAL_USART_STATE_READY;
00337
00338   /* Process Unlocked */
00339   __HAL_UNLOCK(husart);
00340
00341   return HAL_OK;
00342 }
00343
00344 /**
00345   * @brief  Disable the FIFO mode.
00346   * @param husart      USART handle.
00347   * @retval HAL status
00348   */
00349 HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
00350 {
00351   uint32_t tmpcr1;
00352
00353   /* Check parameters */
00354   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00355
00356   /* Process Locked */
00357   __HAL_LOCK(husart);
00358
00359   husart->State = HAL_USART_STATE_BUSY;
00360
00361   /* Save actual USART configuration */
00362   tmpcr1 = READ_REG(husart->Instance->CR1);
00363
00364   /* Disable USART */
00365   __HAL_USART_DISABLE(husart);
00366
00367   /* Enable FIFO mode */
00368   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00369   husart->FifoMode = USART_FIFOMODE_DISABLE;
00370
00371   /* Restore USART configuration */
00372   WRITE_REG(husart->Instance->CR1, tmpcr1);
00373
00374   husart->State = HAL_USART_STATE_READY;
00375
00376   /* Process Unlocked */
00377   __HAL_UNLOCK(husart);
00378
00379   return HAL_OK;
00380 }
00381
00382 /**
00383   * @brief  Set the TXFIFO threshold.
00384   * @param husart      USART handle.
00385   * @param Threshold  TX FIFO threshold value
00386   *          This parameter can be one of the following values:
00387   *            @arg @ref USART_TXFIFO_THRESHOLD_1_8
00388   *            @arg @ref USART_TXFIFO_THRESHOLD_1_4
00389   *            @arg @ref USART_TXFIFO_THRESHOLD_1_2
00390   *            @arg @ref USART_TXFIFO_THRESHOLD_3_4
00391   *            @arg @ref USART_TXFIFO_THRESHOLD_7_8
00392   *            @arg @ref USART_TXFIFO_THRESHOLD_8_8
00393   * @retval HAL status
00394   */
00395 HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
00396 {
00397   uint32_t tmpcr1;
00398
00399   /* Check parameters */
00400   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00401   assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
00402
00403   /* Process Locked */
00404   __HAL_LOCK(husart);
00405
00406   husart->State = HAL_USART_STATE_BUSY;
00407
00408   /* Save actual USART configuration */
00409   tmpcr1 = READ_REG(husart->Instance->CR1);
00410
00411   /* Disable USART */
00412   __HAL_USART_DISABLE(husart);
00413
00414   /* Update TX threshold configuration */
00415   MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00416
00417   /* Determine the number of data to process during RX/TX ISR execution */
00418   USARTEx_SetNbDataToProcess(husart);
00419
00420   /* Restore USART configuration */
00421   WRITE_REG(husart->Instance->CR1, tmpcr1);
00422
00423   husart->State = HAL_USART_STATE_READY;
00424
00425   /* Process Unlocked */
00426   __HAL_UNLOCK(husart);
00427
00428   return HAL_OK;
00429 }
00430
00431 /**
00432   * @brief  Set the RXFIFO threshold.
00433   * @param husart      USART handle.
00434   * @param Threshold  RX FIFO threshold value
00435   *          This parameter can be one of the following values:
00436   *            @arg @ref USART_RXFIFO_THRESHOLD_1_8
00437   *            @arg @ref USART_RXFIFO_THRESHOLD_1_4
00438   *            @arg @ref USART_RXFIFO_THRESHOLD_1_2
00439   *            @arg @ref USART_RXFIFO_THRESHOLD_3_4
00440   *            @arg @ref USART_RXFIFO_THRESHOLD_7_8
00441   *            @arg @ref USART_RXFIFO_THRESHOLD_8_8
00442   * @retval HAL status
00443   */
00444 HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
00445 {
00446   uint32_t tmpcr1;
00447
00448   /* Check the parameters */
00449   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00450   assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
00451
00452   /* Process Locked */
00453   __HAL_LOCK(husart);
00454
00455   husart->State = HAL_USART_STATE_BUSY;
00456
00457   /* Save actual USART configuration */
00458   tmpcr1 = READ_REG(husart->Instance->CR1);
00459
00460   /* Disable USART */
00461   __HAL_USART_DISABLE(husart);
00462
00463   /* Update RX threshold configuration */
00464   MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00465
00466   /* Determine the number of data to process during RX/TX ISR execution */
00467   USARTEx_SetNbDataToProcess(husart);
00468
00469   /* Restore USART configuration */
00470   WRITE_REG(husart->Instance->CR1, tmpcr1);
00471
00472   husart->State = HAL_USART_STATE_READY;
00473
00474   /* Process Unlocked */
00475   __HAL_UNLOCK(husart);
00476
00477   return HAL_OK;
00478 }
00479
00480 /**
00481   * @}
00482   */
00483
00484 /**
00485   * @}
00486   */
00487
00488 /** @addtogroup USARTEx_Private_Functions
00489   * @{
00490   */
00491
00492 /**
00493   * @brief Calculate the number of data to process in RX/TX ISR.
00494   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00495   *       the USART configuration registers.
00496   * @param husart USART handle.
00497   * @retval None
00498   */
00499 static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
00500 {
00501   uint8_t rx_fifo_depth;
00502   uint8_t tx_fifo_depth;
00503   uint8_t rx_fifo_threshold;
00504   uint8_t tx_fifo_threshold;
00505   /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
00506   static const uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00507   static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00508
00509   if (husart->FifoMode == USART_FIFOMODE_DISABLE)
00510   {
00511     husart->NbTxDataToProcess = 1U;
00512     husart->NbRxDataToProcess = 1U;
00513   }
00514   else
00515   {
00516     rx_fifo_depth = RX_FIFO_DEPTH;
00517     tx_fifo_depth = TX_FIFO_DEPTH;
00518     rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
00519                                             USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
00520     tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
00521                                             USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
00522     husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
00523                                 (uint16_t)denominator[tx_fifo_threshold];
00524     husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
00525                                 (uint16_t)denominator[rx_fifo_threshold];
00526   }
00527 }
00528 /**
00529   * @}
00530   */
00531
00532 #endif /* HAL_USART_MODULE_ENABLED */
00533
00534 /**
00535   * @}
00536   */
00537
00538 /**
00539   * @}
00540   */
00541
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_usart_ex.h Source File

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stm32g0xx_hal_usart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_usart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_USART_EX_H
00021 #define STM32G0xx_HAL_USART_EX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup USARTEx
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039 /* Exported constants --------------------------------------------------------*/
00040 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
00041   * @{
00042   */
00043
00044 /** @defgroup USARTEx_Word_Length USARTEx Word Length
00045   * @{
00046   */
00047 #define USART_WORDLENGTH_7B                  (USART_CR1_M1)   /*!< 7-bit long USART frame */
00048 #define USART_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long USART frame */
00049 #define USART_WORDLENGTH_9B                  (USART_CR1_M0)   /*!< 9-bit long USART frame */
00050 /**
00051   * @}
00052   */
00053
00054 /** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
00055   * @{
00056   */
00057 #define USART_NSS_HARD                        0x00000000U          /*!< SPI slave selection depends on NSS input pin              */
00058 #define USART_NSS_SOFT                        USART_CR2_DIS_NSS    /*!< SPI slave is always selected and NSS input pin is ignored */
00059 /**
00060   * @}
00061   */
00062
00063
00064 /** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
00065   * @brief    USART SLAVE mode
00066   * @{
00067   */
00068 #define USART_SLAVEMODE_DISABLE   0x00000000U     /*!< USART SPI Slave Mode Enable  */
00069 #define USART_SLAVEMODE_ENABLE    USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup USARTEx_FIFO_mode USARTEx FIFO  mode
00075   * @brief    USART FIFO  mode
00076   * @{
00077   */
00078 #define USART_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
00079 #define USART_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
00085   * @brief    USART TXFIFO level
00086   * @{
00087   */
00088 #define USART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00089 #define USART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
00090 #define USART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
00091 #define USART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
00092 #define USART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
00093 #define USART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
00094 /**
00095   * @}
00096   */
00097
00098 /** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
00099   * @brief    USART RXFIFO level
00100   * @{
00101   */
00102 #define USART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
00103 #define USART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
00104 #define USART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
00105 #define USART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
00106 #define USART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
00107 #define USART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 /* Private macros ------------------------------------------------------------*/
00117 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
00118   * @{
00119   */
00120
00121 /** @brief  Report the USART clock source.
00122   * @param  __HANDLE__ specifies the USART Handle.
00123   * @param  __CLOCKSOURCE__ output variable.
00124   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00125   */
00126 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00127 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00128   do {                                                         \
00129     if((__HANDLE__)->Instance == USART1)                       \
00130     {                                                          \
00131       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00132       {                                                        \
00133         case RCC_USART1CLKSOURCE_PCLK1:                        \
00134           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00135           break;                                               \
00136         case RCC_USART1CLKSOURCE_HSI:                          \
00137           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00138           break;                                               \
00139         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00140           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00141           break;                                               \
00142         case RCC_USART1CLKSOURCE_LSE:                          \
00143           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00144           break;                                               \
00145         default:                                               \
00146           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00147           break;                                               \
00148       }                                                        \
00149     }                                                          \
00150     else if((__HANDLE__)->Instance == USART2)                  \
00151     {                                                          \
00152       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00153       {                                                        \
00154         case RCC_USART2CLKSOURCE_PCLK1:                        \
00155           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00156           break;                                               \
00157         case RCC_USART2CLKSOURCE_HSI:                          \
00158           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00159           break;                                               \
00160         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00161           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00162           break;                                               \
00163         case RCC_USART2CLKSOURCE_LSE:                          \
00164           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00165           break;                                               \
00166         default:                                               \
00167           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00168           break;                                               \
00169       }                                                        \
00170     }                                                          \
00171     else if((__HANDLE__)->Instance == USART3)                  \
00172     {                                                          \
00173       switch(__HAL_RCC_GET_USART3_SOURCE())                    \
00174       {                                                        \
00175         case RCC_USART3CLKSOURCE_PCLK1:                        \
00176           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00177           break;                                               \
00178         case RCC_USART3CLKSOURCE_HSI:                          \
00179           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00180           break;                                               \
00181         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00182           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00183           break;                                               \
00184         case RCC_USART3CLKSOURCE_LSE:                          \
00185           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00186           break;                                               \
00187         default:                                               \
00188           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00189           break;                                               \
00190       }                                                        \
00191     }                                                          \
00192     else if((__HANDLE__)->Instance == USART4)                  \
00193     {                                                          \
00194       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
00195     }                                                          \
00196     else if((__HANDLE__)->Instance == USART5)                  \
00197     {                                                          \
00198       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
00199     }                                                          \
00200     else if((__HANDLE__)->Instance == USART6)                  \
00201     {                                                          \
00202       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
00203     }                                                          \
00204     else                                                       \
00205     {                                                          \
00206       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00207     }                                                          \
00208   } while(0U)
00209 #elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
00210 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00211   do {                                                         \
00212     if((__HANDLE__)->Instance == USART1)                       \
00213     {                                                          \
00214       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00215       {                                                        \
00216         case RCC_USART1CLKSOURCE_PCLK1:                        \
00217           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00218           break;                                               \
00219         case RCC_USART1CLKSOURCE_HSI:                          \
00220           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00221           break;                                               \
00222         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00223           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00224           break;                                               \
00225         case RCC_USART1CLKSOURCE_LSE:                          \
00226           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00227           break;                                               \
00228         default:                                               \
00229           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00230           break;                                               \
00231       }                                                        \
00232     }                                                          \
00233     else if((__HANDLE__)->Instance == USART2)                  \
00234     {                                                          \
00235       switch(__HAL_RCC_GET_USART2_SOURCE())                    \
00236       {                                                        \
00237         case RCC_USART2CLKSOURCE_PCLK1:                        \
00238           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00239           break;                                               \
00240         case RCC_USART2CLKSOURCE_HSI:                          \
00241           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00242           break;                                               \
00243         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00244           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00245           break;                                               \
00246         case RCC_USART2CLKSOURCE_LSE:                          \
00247           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00248           break;                                               \
00249         default:                                               \
00250           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00251           break;                                               \
00252       }                                                        \
00253     }                                                          \
00254     else if((__HANDLE__)->Instance == USART3)                  \
00255     {                                                          \
00256       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
00257     }                                                          \
00258     else if((__HANDLE__)->Instance == USART4)                  \
00259     {                                                          \
00260       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
00261     }                                                          \
00262     else                                                       \
00263     {                                                          \
00264       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00265     }                                                          \
00266   } while(0U)
00267 #else
00268 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00269   do {                                                         \
00270     if((__HANDLE__)->Instance == USART1)                       \
00271     {                                                          \
00272       switch(__HAL_RCC_GET_USART1_SOURCE())                    \
00273       {                                                        \
00274         case RCC_USART1CLKSOURCE_PCLK1:                        \
00275           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00276           break;                                               \
00277         case RCC_USART1CLKSOURCE_HSI:                          \
00278           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00279           break;                                               \
00280         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00281           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00282           break;                                               \
00283         case RCC_USART1CLKSOURCE_LSE:                          \
00284           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00285           break;                                               \
00286         default:                                               \
00287           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00288           break;                                               \
00289       }                                                        \
00290     }                                                          \
00291     else if((__HANDLE__)->Instance == USART2)                  \
00292     {                                                          \
00293       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
00294     }                                                          \
00295     else                                                       \
00296     {                                                          \
00297       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00298     }                                                          \
00299   } while(0U)
00300 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00301 /** @brief  Compute the USART mask to apply to retrieve the received data
00302   *         according to the word length and to the parity bits activation.
00303   * @note   If PCE = 1, the parity bit is not included in the data extracted
00304   *         by the reception API().
00305   *         This masking operation is not carried out in the case of
00306   *         DMA transfers.
00307   * @param  __HANDLE__ specifies the USART Handle.
00308   * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
00309   */
00310 #define USART_MASK_COMPUTATION(__HANDLE__)                            \
00311   do {                                                                \
00312     if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)         \
00313     {                                                                 \
00314       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00315       {                                                               \
00316         (__HANDLE__)->Mask = 0x01FFU;                                 \
00317       }                                                               \
00318       else                                                            \
00319       {                                                               \
00320         (__HANDLE__)->Mask = 0x00FFU;                                 \
00321       }                                                               \
00322     }                                                                 \
00323     else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)    \
00324     {                                                                 \
00325       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00326       {                                                               \
00327         (__HANDLE__)->Mask = 0x00FFU;                                 \
00328       }                                                               \
00329       else                                                            \
00330       {                                                               \
00331         (__HANDLE__)->Mask = 0x007FU;                                 \
00332       }                                                               \
00333     }                                                                 \
00334     else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)    \
00335     {                                                                 \
00336       if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
00337       {                                                               \
00338         (__HANDLE__)->Mask = 0x007FU;                                 \
00339       }                                                               \
00340       else                                                            \
00341       {                                                               \
00342         (__HANDLE__)->Mask = 0x003FU;                                 \
00343       }                                                               \
00344     }                                                                 \
00345     else                                                              \
00346     {                                                                 \
00347       (__HANDLE__)->Mask = 0x0000U;                                   \
00348     }                                                                 \
00349   } while(0U)
00350
00351 /**
00352   * @brief Ensure that USART frame length is valid.
00353   * @param __LENGTH__ USART frame length.
00354   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00355   */
00356 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
00357                                           ((__LENGTH__) == USART_WORDLENGTH_8B) || \
00358                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00359
00360 /**
00361   * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
00362   * @param __NSS__ USART Negative Slave Select pin management.
00363   * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
00364   */
00365 #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
00366                                ((__NSS__) == USART_NSS_SOFT))
00367
00368 /**
00369   * @brief Ensure that USART Slave Mode is valid.
00370   * @param __STATE__ USART Slave Mode.
00371   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00372   */
00373 #define IS_USART_SLAVEMODE(__STATE__)   (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
00374                                          ((__STATE__) == USART_SLAVEMODE_ENABLE))
00375
00376 /**
00377   * @brief Ensure that USART FIFO mode is valid.
00378   * @param __STATE__ USART FIFO mode.
00379   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00380   */
00381 #define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
00382                                              ((__STATE__) == USART_FIFOMODE_ENABLE))
00383
00384 /**
00385   * @brief Ensure that USART TXFIFO threshold level is valid.
00386   * @param __THRESHOLD__ USART TXFIFO threshold level.
00387   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00388   */
00389 #define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
00390                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
00391                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
00392                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
00393                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
00394                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
00395
00396 /**
00397   * @brief Ensure that USART RXFIFO threshold level is valid.
00398   * @param __THRESHOLD__ USART RXFIFO threshold level.
00399   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00400   */
00401 #define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
00402                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
00403                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
00404                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
00405                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
00406                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
00407 /**
00408   * @}
00409   */
00410
00411 /* Exported functions --------------------------------------------------------*/
00412 /** @addtogroup USARTEx_Exported_Functions
00413   * @{
00414   */
00415
00416 /** @addtogroup USARTEx_Exported_Functions_Group1
00417   * @{
00418   */
00419
00420 /* IO operation functions *****************************************************/
00421 void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
00422 void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
00423
00424 /**
00425   * @}
00426   */
00427
00428 /** @addtogroup USARTEx_Exported_Functions_Group2
00429   * @{
00430   */
00431
00432 /* Peripheral Control functions ***********************************************/
00433 HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
00434 HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
00435 HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
00436 HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
00437 HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
00438 HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
00439 HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
00440
00441 /**
00442   * @}
00443   */
00444
00445 /**
00446   * @}
00447   */
00448
00449 /**
00450   * @}
00451   */
00452
00453 /**
00454   * @}
00455   */
00456
00457 #ifdef __cplusplus
00458 }
00459 #endif
00460
00461 #endif /* STM32G0xx_HAL_USART_EX_H */
00462
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_wwdg.c Source File

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stm32g0xx_hal_wwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @brief   WWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Window Watchdog (WWDG) peripheral:
00008   *           + Initialization and Configuration functions
00009   *           + IO operation functions
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * Copyright (c) 2018 STMicroelectronics.
00014   * All rights reserved.
00015   *
00016   * This software is licensed under terms that can be found in the LICENSE file
00017   * in the root directory of this software component.
00018   * If no LICENSE file comes with this software, it is provided AS-IS.
00019   *
00020   ******************************************************************************
00021   @verbatim
00022   ==============================================================================
00023                       ##### WWDG Specific features #####
00024   ==============================================================================
00025   [..]
00026     Once enabled the WWDG generates a system reset on expiry of a programmed
00027     time period, unless the program refreshes the counter (T[6;0] downcounter)
00028     before reaching 0x3F value (i.e. a reset is generated when the counter
00029     value rolls down from 0x40 to 0x3F).
00030
00031     (+) An MCU reset is also generated if the counter value is refreshed
00032         before the counter has reached the refresh window value. This
00033         implies that the counter must be refreshed in a limited window.
00034     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00035     (+) If required by application, an Early Wakeup Interrupt can be triggered
00036         in order to be warned before WWDG expiration. The Early Wakeup Interrupt
00037         (EWI) can be used if specific safety operations or data logging must
00038         be performed before the actual reset is generated. When the downcounter
00039         reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
00040         line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
00041         disabled except by a system reset.
00042     (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
00043         reset occurs.
00044     (+) The WWDG counter input clock is derived from the APB clock divided
00045         by a programmable prescaler.
00046     (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
00047     (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
00048         where T[5;0] are the lowest 6 bits of Counter.
00049     (+) WWDG Counter refresh is allowed between the following limits :
00050         (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
00051         (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
00052     (+) Typical values:
00053         (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler:
00054              max timeout before reset: approximately 64us
00055         (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler
00056              dividing by 128:
00057              max timeout before reset: approximately 524.28ms
00058
00059                      ##### How to use this driver #####
00060   ==============================================================================
00061
00062     *** Common driver usage ***
00063     ===========================
00064
00065   [..]
00066     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00067     (+) Configure the WWDG prescaler, refresh window value, counter value and early
00068         interrupt status using HAL_WWDG_Init() function. This will automatically
00069         enable WWDG and start its downcounter. Time reference can be taken from
00070         function exit. Care must be taken to provide a counter value
00071         greater than 0x40 to prevent generation of immediate reset.
00072     (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
00073         generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
00074         triggered by the interrupt service routine, flag will be automatically
00075         cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
00076         can add his own code by customization of callback HAL_WWDG_WakeupCallback.
00077     (+) Then the application program must refresh the WWDG counter at regular
00078         intervals during normal operation to prevent an MCU reset, using
00079         HAL_WWDG_Refresh() function. This operation must occur only when
00080         the counter is lower than the refresh window value already programmed.
00081
00082     *** Callback registration ***
00083     =============================
00084
00085   [..]
00086     The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
00087     the user to configure dynamically the driver callbacks. Use Functions
00088     HAL_WWDG_RegisterCallback() to register a user callback.
00089
00090     (+) Function HAL_WWDG_RegisterCallback() allows to register following
00091         callbacks:
00092         (++) EwiCallback : callback for Early WakeUp Interrupt.
00093         (++) MspInitCallback : WWDG MspInit.
00094     This function takes as parameters the HAL peripheral handle, the Callback ID
00095     and a pointer to the user callback function.
00096
00097     (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
00098     the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
00099     takes as parameters the HAL peripheral handle and the Callback ID.
00100     This function allows to reset following callbacks:
00101         (++) EwiCallback : callback for  Early WakeUp Interrupt.
00102         (++) MspInitCallback : WWDG MspInit.
00103
00104     [..]
00105     When calling HAL_WWDG_Init function, callbacks are reset to the
00106     corresponding legacy weak (surcharged) functions:
00107     HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
00108     not been registered before.
00109
00110     [..]
00111     When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
00112     not defined, the callback registering feature is not available
00113     and weak (surcharged) callbacks are used.
00114
00115     *** WWDG HAL driver macros list ***
00116     ===================================
00117     [..]
00118       Below the list of available macros in WWDG HAL driver.
00119       (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
00120       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
00121       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
00122       (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
00123
00124   @endverbatim
00125   ******************************************************************************
00126   */
00127
00128 /* Includes ------------------------------------------------------------------*/
00129 #include "stm32g0xx_hal.h"
00130
00131 /** @addtogroup STM32G0xx_HAL_Driver
00132   * @{
00133   */
00134
00135 #ifdef HAL_WWDG_MODULE_ENABLED
00136 /** @defgroup WWDG WWDG
00137   * @brief WWDG HAL module driver.
00138   * @{
00139   */
00140
00141 /* Private typedef -----------------------------------------------------------*/
00142 /* Private define ------------------------------------------------------------*/
00143 /* Private macro -------------------------------------------------------------*/
00144 /* Private variables ---------------------------------------------------------*/
00145 /* Private function prototypes -----------------------------------------------*/
00146 /* Exported functions --------------------------------------------------------*/
00147
00148 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00149   * @{
00150   */
00151
00152 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
00153   *  @brief    Initialization and Configuration functions.
00154   *
00155 @verbatim
00156   ==============================================================================
00157           ##### Initialization and Configuration functions #####
00158   ==============================================================================
00159   [..]
00160     This section provides functions allowing to:
00161       (+) Initialize and start the WWDG according to the specified parameters
00162           in the WWDG_InitTypeDef of associated handle.
00163       (+) Initialize the WWDG MSP.
00164
00165 @endverbatim
00166   * @{
00167   */
00168
00169 /**
00170   * @brief  Initialize the WWDG according to the specified.
00171   *         parameters in the WWDG_InitTypeDef of  associated handle.
00172   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00173   *                the configuration information for the specified WWDG module.
00174   * @retval HAL status
00175   */
00176 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00177 {
00178   /* Check the WWDG handle allocation */
00179   if (hwwdg == NULL)
00180   {
00181     return HAL_ERROR;
00182   }
00183
00184   /* Check the parameters */
00185   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00186   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00187   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00188   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00189   assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
00190
00191 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00192   /* Reset Callback pointers */
00193   if (hwwdg->EwiCallback == NULL)
00194   {
00195     hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
00196   }
00197
00198   if (hwwdg->MspInitCallback == NULL)
00199   {
00200     hwwdg->MspInitCallback = HAL_WWDG_MspInit;
00201   }
00202
00203   /* Init the low level hardware */
00204   hwwdg->MspInitCallback(hwwdg);
00205 #else
00206   /* Init the low level hardware */
00207   HAL_WWDG_MspInit(hwwdg);
00208 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00209
00210   /* Set WWDG Counter */
00211   WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
00212
00213   /* Set WWDG Prescaler and Window */
00214   WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
00215
00216   /* Return function status */
00217   return HAL_OK;
00218 }
00219
00220
00221 /**
00222   * @brief  Initialize the WWDG MSP.
00223   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00224   *                the configuration information for the specified WWDG module.
00225   * @note   When rewriting this function in user file, mechanism may be added
00226   *         to avoid multiple initialize when HAL_WWDG_Init function is called
00227   *         again to change parameters.
00228   * @retval None
00229   */
00230 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00231 {
00232   /* Prevent unused argument(s) compilation warning */
00233   UNUSED(hwwdg);
00234
00235   /* NOTE: This function should not be modified, when the callback is needed,
00236            the HAL_WWDG_MspInit could be implemented in the user file
00237    */
00238 }
00239
00240
00241 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00242 /**
00243   * @brief  Register a User WWDG Callback
00244   *         To be used instead of the weak (surcharged) predefined callback
00245   * @param  hwwdg WWDG handle
00246   * @param  CallbackID ID of the callback to be registered
00247   *         This parameter can be one of the following values:
00248   *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
00249   *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
00250   * @param  pCallback pointer to the Callback function
00251   * @retval status
00252   */
00253 HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
00254                                             pWWDG_CallbackTypeDef pCallback)
00255 {
00256   HAL_StatusTypeDef status = HAL_OK;
00257
00258   if (pCallback == NULL)
00259   {
00260     status = HAL_ERROR;
00261   }
00262   else
00263   {
00264     switch (CallbackID)
00265     {
00266       case HAL_WWDG_EWI_CB_ID:
00267         hwwdg->EwiCallback = pCallback;
00268         break;
00269
00270       case HAL_WWDG_MSPINIT_CB_ID:
00271         hwwdg->MspInitCallback = pCallback;
00272         break;
00273
00274       default:
00275         status = HAL_ERROR;
00276         break;
00277     }
00278   }
00279
00280   return status;
00281 }
00282
00283
00284 /**
00285   * @brief  Unregister a WWDG Callback
00286   *         WWDG Callback is redirected to the weak (surcharged) predefined callback
00287   * @param  hwwdg WWDG handle
00288   * @param  CallbackID ID of the callback to be registered
00289   *         This parameter can be one of the following values:
00290   *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
00291   *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
00292   * @retval status
00293   */
00294 HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
00295 {
00296   HAL_StatusTypeDef status = HAL_OK;
00297
00298   switch (CallbackID)
00299   {
00300     case HAL_WWDG_EWI_CB_ID:
00301       hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
00302       break;
00303
00304     case HAL_WWDG_MSPINIT_CB_ID:
00305       hwwdg->MspInitCallback = HAL_WWDG_MspInit;
00306       break;
00307
00308     default:
00309       status = HAL_ERROR;
00310       break;
00311   }
00312
00313   return status;
00314 }
00315 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00316
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00322   *  @brief    IO operation functions
00323   *
00324 @verbatim
00325   ==============================================================================
00326                       ##### IO operation functions #####
00327   ==============================================================================
00328   [..]
00329     This section provides functions allowing to:
00330     (+) Refresh the WWDG.
00331     (+) Handle WWDG interrupt request and associated function callback.
00332
00333 @endverbatim
00334   * @{
00335   */
00336
00337 /**
00338   * @brief  Refresh the WWDG.
00339   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00340   *                the configuration information for the specified WWDG module.
00341   * @retval HAL status
00342   */
00343 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
00344 {
00345   /* Write to WWDG CR the WWDG Counter value to refresh with */
00346   WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
00347
00348   /* Return function status */
00349   return HAL_OK;
00350 }
00351
00352 /**
00353   * @brief  Handle WWDG interrupt request.
00354   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00355   *         or data logging must be performed before the actual reset is generated.
00356   *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
00357   *         EWIMode set to WWDG_EWI_ENABLE.
00358   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00359   *         generated and the corresponding Interrupt Service Routine (ISR) can
00360   *         be used to trigger specific actions (such as communications or data
00361   *         logging), before resetting the device.
00362   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00363   *                the configuration information for the specified WWDG module.
00364   * @retval None
00365   */
00366 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00367 {
00368   /* Check if Early Wakeup Interrupt is enable */
00369   if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00370   {
00371     /* Check if WWDG Early Wakeup Interrupt occurred */
00372     if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00373     {
00374       /* Clear the WWDG Early Wakeup flag */
00375       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00376
00377 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00378       /* Early Wakeup registered callback */
00379       hwwdg->EwiCallback(hwwdg);
00380 #else
00381       /* Early Wakeup callback */
00382       HAL_WWDG_EarlyWakeupCallback(hwwdg);
00383 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00384     }
00385   }
00386 }
00387
00388
00389 /**
00390   * @brief  WWDG Early Wakeup callback.
00391   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00392   *                the configuration information for the specified WWDG module.
00393   * @retval None
00394   */
00395 __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
00396 {
00397   /* Prevent unused argument(s) compilation warning */
00398   UNUSED(hwwdg);
00399
00400   /* NOTE: This function should not be modified, when the callback is needed,
00401            the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
00402    */
00403 }
00404
00405 /**
00406   * @}
00407   */
00408
00409 /**
00410   * @}
00411   */
00412
00413 #endif /* HAL_WWDG_MODULE_ENABLED */
00414 /**
00415   * @}
00416   */
00417
00418 /**
00419   * @}
00420   */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_hal_wwdg.h Source File

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stm32g0xx_hal_wwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_HAL_WWDG_H
00021 #define STM32G0xx_HAL_WWDG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx_hal_def.h"
00029
00030 /** @addtogroup STM32G0xx_HAL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup WWDG
00035   * @{
00036   */
00037
00038 /* Exported types ------------------------------------------------------------*/
00039
00040 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  WWDG Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
00050                                This parameter can be a value of @ref WWDG_Prescaler */
00051
00052   uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
00053                                This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
00054
00055   uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
00056                                This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00057
00058   uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
00059                                This parameter can be a value of @ref WWDG_EWI_Mode */
00060
00061 } WWDG_InitTypeDef;
00062
00063 /**
00064   * @brief  WWDG handle Structure definition
00065   */
00066 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00067 typedef struct __WWDG_HandleTypeDef
00068 #else
00069 typedef struct
00070 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00071 {
00072   WWDG_TypeDef      *Instance;  /*!< Register base address */
00073
00074   WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
00075
00076 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00077   void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);                  /*!< WWDG Early WakeUp Interrupt callback */
00078
00079   void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg);              /*!< WWDG Msp Init callback */
00080 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00081 } WWDG_HandleTypeDef;
00082
00083 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00084 /**
00085   * @brief  HAL WWDG common Callback ID enumeration definition
00086   */
00087 typedef enum
00088 {
00089   HAL_WWDG_EWI_CB_ID          = 0x00U,    /*!< WWDG EWI callback ID */
00090   HAL_WWDG_MSPINIT_CB_ID      = 0x01U,    /*!< WWDG MspInit callback ID */
00091 } HAL_WWDG_CallbackIDTypeDef;
00092
00093 /**
00094   * @brief  HAL WWDG Callback pointer definition
00095   */
00096 typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
00097
00098 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00099 /**
00100   * @}
00101   */
00102
00103 /* Exported constants --------------------------------------------------------*/
00104
00105 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00106   * @{
00107   */
00108
00109 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00110   * @{
00111   */
00112 #define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00113 /**
00114   * @}
00115   */
00116
00117 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00118   * @brief WWDG Flag definition
00119   * @{
00120   */
00121 #define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup WWDG_Prescaler WWDG Prescaler
00127   * @{
00128   */
00129 #define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
00130 #define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
00131 #define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
00132 #define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
00133 #define WWDG_PRESCALER_16                   WWDG_CFR_WDGTB_2                         /*!< WWDG counter clock = (PCLK1/4096)/16 */
00134 #define WWDG_PRESCALER_32                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/32 */
00135 #define WWDG_PRESCALER_64                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)    /*!< WWDG counter clock = (PCLK1/4096)/64 */
00136 #define WWDG_PRESCALER_128                  WWDG_CFR_WDGTB                           /*!< WWDG counter clock = (PCLK1/4096)/128 */
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
00142   * @{
00143   */
00144 #define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
00145 #define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
00146 /**
00147   * @}
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Private macros ------------------------------------------------------------*/
00155
00156 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00157   * @{
00158   */
00159 #define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
00160                                              ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
00161                                              ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
00162                                              ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
00163                                              ((__PRESCALER__) == WWDG_PRESCALER_16) || \
00164                                              ((__PRESCALER__) == WWDG_PRESCALER_32) || \
00165                                              ((__PRESCALER__) == WWDG_PRESCALER_64) || \
00166                                              ((__PRESCALER__) == WWDG_PRESCALER_128))
00167
00168 #define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
00169
00170 #define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
00171
00172 #define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
00173                                              ((__MODE__) == WWDG_EWI_DISABLE))
00174 /**
00175   * @}
00176   */
00177
00178
00179 /* Exported macros ------------------------------------------------------------*/
00180
00181 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00182   * @{
00183   */
00184
00185 /**
00186   * @brief  Enable the WWDG peripheral.
00187   * @param  __HANDLE__  WWDG handle
00188   * @retval None
00189   */
00190 #define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00191
00192 /**
00193   * @brief  Enable the WWDG early wakeup interrupt.
00194   * @param  __HANDLE__     WWDG handle
00195   * @param  __INTERRUPT__  specifies the interrupt to enable.
00196   *         This parameter can be one of the following values:
00197   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00198   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00199   * @retval None
00200   */
00201 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00202
00203 /**
00204   * @brief  Check whether the selected WWDG interrupt has occurred or not.
00205   * @param  __HANDLE__  WWDG handle
00206   * @param  __INTERRUPT__  specifies the it to check.
00207   *        This parameter can be one of the following values:
00208   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00209   * @retval The new state of WWDG_FLAG (SET or RESET).
00210   */
00211 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00212
00213 /** @brief  Clear the WWDG interrupt pending bits.
00214   *         bits to clear the selected interrupt pending bits.
00215   * @param  __HANDLE__  WWDG handle
00216   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
00217   *         This parameter can be one of the following values:
00218   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00219   */
00220 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00221
00222 /**
00223   * @brief  Check whether the specified WWDG flag is set or not.
00224   * @param  __HANDLE__  WWDG handle
00225   * @param  __FLAG__  specifies the flag to check.
00226   *         This parameter can be one of the following values:
00227   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00228   * @retval The new state of WWDG_FLAG (SET or RESET).
00229   */
00230 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00231
00232 /**
00233   * @brief  Clear the WWDG's pending flags.
00234   * @param  __HANDLE__  WWDG handle
00235   * @param  __FLAG__  specifies the flag to clear.
00236   *         This parameter can be one of the following values:
00237   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00238   * @retval None
00239   */
00240 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00241
00242 /** @brief  Check whether the specified WWDG interrupt source is enabled or not.
00243   * @param  __HANDLE__  WWDG Handle.
00244   * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
00245   *         This parameter can be one of the following values:
00246   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00247   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00248   */
00249 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
00250                                                               & (__INTERRUPT__)) == (__INTERRUPT__))
00251
00252 /**
00253   * @}
00254   */
00255
00256 /* Exported functions --------------------------------------------------------*/
00257
00258 /** @addtogroup WWDG_Exported_Functions
00259   * @{
00260   */
00261
00262 /** @addtogroup WWDG_Exported_Functions_Group1
00263   * @{
00264   */
00265 /* Initialization/de-initialization functions  **********************************/
00266 HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00267 void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00268 /* Callbacks Register/UnRegister functions  ***********************************/
00269 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00270 HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
00271                                                 pWWDG_CallbackTypeDef pCallback);
00272 HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
00273 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @addtogroup WWDG_Exported_Functions_Group2
00280   * @{
00281   */
00282 /* I/O operation functions ******************************************************/
00283 HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
00284 void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00285 void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 #ifdef __cplusplus
00303 }
00304 #endif
00305
00306 #endif /* STM32G0xx_HAL_WWDG_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_adc.c Source File

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stm32g0xx_ll_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_adc.c
00004   * @author  MCD Application Team
00005   * @brief   ADC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_adc.h"
00022 #include "stm32g0xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (ADC1)
00035
00036 /** @addtogroup ADC_LL ADC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup ADC_LL_Private_Constants
00044   * @{
00045   */
00046
00047 /* Definitions of ADC hardware constraints delays */
00048 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
00049 /*       not timeout values:                                                  */
00050 /*       Timeout values for ADC operations are dependent to device clock      */
00051 /*       configuration (system clock versus ADC clock),                       */
00052 /*       and therefore must be defined in user application.                   */
00053 /*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
00054 /*       values definition.                                                   */
00055 /* Note: ADC timeout values are defined here in CPU cycles to be independent  */
00056 /*       of device clock setting.                                             */
00057 /*       In user application, ADC timeout values should be defined with       */
00058 /*       temporal values, in function of device clock settings.               */
00059 /*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
00060 /*        - ADC clock from synchronous clock with AHB prescaler 512,          */
00061 /*          APB prescaler 16, ADC prescaler 4.                                */
00062 /*        - ADC clock from asynchronous clock (HSI) with prescaler 1,         */
00063 /*          with highest ratio CPU clock frequency vs HSI clock frequency:    */
00064 /*          CPU clock frequency max 56MHz, HSI frequency 16MHz: ratio 4.      */
00065 /* Unit: CPU cycles.                                                          */
00066 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          (512UL * 16UL * 4UL)
00067 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
00068 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
00069 /* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles                 */
00070 /*       after the channel configuration has been changed.                    */
00071 /*       Driver timeout is approximated to 6 CPU cycles.                      */
00072 #define ADC_TIMEOUT_CCRDY_CPU_CYCLES            (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Private macros ------------------------------------------------------------*/
00079
00080 /** @addtogroup ADC_LL_Private_Macros
00081   * @{
00082   */
00083
00084 /* Check of parameters for configuration of ADC hierarchical scope:           */
00085 /* common to several ADC instances.                                           */
00086 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
00087   (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                    \
00088    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
00089    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
00090    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
00091    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
00092    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
00093    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
00094    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
00095    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
00096    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
00097    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
00098    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
00099   )
00100
00101 #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__)                         \
00102   (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH)                      \
00103    || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW)                    \
00104   )
00105
00106 /* Check of parameters for configuration of ADC hierarchical scope:           */
00107 /* ADC instance.                                                              */
00108 #define IS_LL_ADC_CLOCK(__CLOCK__)                                             \
00109   (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                                \
00110    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
00111    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
00112    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC)                                      \
00113   )
00114
00115 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
00116   (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                                 \
00117    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
00118    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
00119    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
00120   )
00121
00122 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
00123   (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                               \
00124    || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
00125   )
00126
00127 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
00128   (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                    \
00129    || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
00130    || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF)                              \
00131    || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF)                     \
00132   )
00133
00134 /* Check of parameters for configuration of ADC hierarchical scope:           */
00135 /* ADC group regular                                                          */
00136 #if defined(TIM15) && defined(TIM6) && defined(TIM2)
00137 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00138   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00139    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00140    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
00141    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00142    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00143    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00144    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00145    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00146   )
00147 #elif defined(TIM15) && defined(TIM6)
00148 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00149   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00150    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00151    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
00152    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00153    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00154    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00155    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00156   )
00157 #elif defined(TIM2)
00158 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00159   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00160    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00161    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
00162    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00163    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00164    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00165   )
00166 #else
00167 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00168   (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
00169    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00170    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
00171    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00172    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00173   )
00174 #endif /* TIM15 && TIM6 && TIM2 */
00175
00176 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
00177   (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
00178    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
00179   )
00180
00181 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
00182   (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                    \
00183    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
00184    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
00185   )
00186
00187 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
00188   (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
00189    || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
00190   )
00191
00192 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__)                               \
00193   (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED)                                \
00194    || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE)                      \
00195   )
00196
00197 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
00198   (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
00199    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
00200    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
00201    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
00202    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
00203    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
00204    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
00205    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
00206   )
00207
00208 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
00209   (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)              \
00210    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
00211   )
00212
00213 /**
00214   * @}
00215   */
00216
00217
00218 /* Private function prototypes -----------------------------------------------*/
00219
00220 /* Exported functions --------------------------------------------------------*/
00221 /** @addtogroup ADC_LL_Exported_Functions
00222   * @{
00223   */
00224
00225 /** @addtogroup ADC_LL_EF_Init
00226   * @{
00227   */
00228
00229 /**
00230   * @brief  De-initialize registers of all ADC instances belonging to
00231   *         the same ADC common instance to their default reset values.
00232   * @note   This function is performing a hard reset, using high level
00233   *         clock source RCC ADC reset.
00234   * @param  ADCxy_COMMON ADC common instance
00235   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00236   * @retval An ErrorStatus enumeration value:
00237   *          - SUCCESS: ADC common registers are de-initialized
00238   *          - ERROR: not applicable
00239   */
00240 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
00241 {
00242   /* Check the parameters */
00243   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00244
00245   /* Prevent unused argument(s) compilation warning if no assert_param check */
00246   (void)(ADCxy_COMMON);
00247
00248   /* Force reset of ADC clock (core clock) */
00249   LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
00250
00251   /* Release reset of ADC clock (core clock) */
00252   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
00253
00254   return SUCCESS;
00255 }
00256
00257 /**
00258   * @brief  Initialize some features of ADC common parameters
00259   *         (all ADC instances belonging to the same ADC common instance)
00260   *         and multimode (for devices with several ADC instances available).
00261   * @note   The setting of ADC common parameters is conditioned to
00262   *         ADC instances state:
00263   *         All ADC instances belonging to the same ADC common instance
00264   *         must be disabled.
00265   * @param  ADCxy_COMMON ADC common instance
00266   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00267   * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00268   * @retval An ErrorStatus enumeration value:
00269   *          - SUCCESS: ADC common registers are initialized
00270   *          - ERROR: ADC common registers are not initialized
00271   */
00272 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
00273 {
00274   ErrorStatus status = SUCCESS;
00275
00276   /* Check the parameters */
00277   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00278   assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
00279
00280   /* Note: Hardware constraint (refer to description of functions             */
00281   /*       "LL_ADC_SetCommonXXX()":                                           */
00282   /*       On this STM32 series, setting of these features is conditioned to  */
00283   /*       ADC state:                                                         */
00284   /*       All ADC instances of the ADC common group must be disabled.        */
00285   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
00286   {
00287     /* Configuration of ADC hierarchical scope:                               */
00288     /*  - common to several ADC                                               */
00289     /*    (all ADC instances belonging to the same ADC common instance)       */
00290     /*    - Set ADC clock (conversion clock)                                  */
00291     LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
00292   }
00293   else
00294   {
00295     /* Initialization error: One or several ADC instances belonging to        */
00296     /* the same ADC common instance are not disabled.                         */
00297     status = ERROR;
00298   }
00299
00300   return status;
00301 }
00302
00303 /**
00304   * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
00305   * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00306   *                              whose fields will be set to default values.
00307   * @retval None
00308   */
00309 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
00310 {
00311   /* Set pADC_CommonInitStruct fields to default values */
00312   /* Set fields of ADC common */
00313   /* (all ADC instances belonging to the same ADC common instance) */
00314   pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
00315
00316 }
00317
00318 /**
00319   * @brief  De-initialize registers of the selected ADC instance
00320   *         to their default reset values.
00321   * @note   To reset all ADC instances quickly (perform a hard reset),
00322   *         use function @ref LL_ADC_CommonDeInit().
00323   * @note   If this functions returns error status, it means that ADC instance
00324   *         is in an unknown state.
00325   *         In this case, perform a hard reset using high level
00326   *         clock source RCC ADC reset.
00327   *         Refer to function @ref LL_ADC_CommonDeInit().
00328   * @param  ADCx ADC instance
00329   * @retval An ErrorStatus enumeration value:
00330   *          - SUCCESS: ADC registers are de-initialized
00331   *          - ERROR: ADC registers are not de-initialized
00332   */
00333 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
00334 {
00335   ErrorStatus status = SUCCESS;
00336
00337   __IO uint32_t timeout_cpu_cycles = 0UL;
00338
00339   /* Check the parameters */
00340   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00341
00342   /* Disable ADC instance if not already disabled.                            */
00343   if (LL_ADC_IsEnabled(ADCx) == 1UL)
00344   {
00345     /* Set ADC group regular trigger source to SW start to ensure to not      */
00346     /* have an external trigger event occurring during the conversion stop    */
00347     /* ADC disable process.                                                   */
00348     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
00349
00350     /* Stop potential ADC conversion on going on ADC group regular.           */
00351     if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
00352     {
00353       if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
00354       {
00355         LL_ADC_REG_StopConversion(ADCx);
00356       }
00357     }
00358
00359     /* Wait for ADC conversions are effectively stopped                       */
00360     timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
00361     while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
00362     {
00363       timeout_cpu_cycles--;
00364       if (timeout_cpu_cycles == 0UL)
00365       {
00366         /* Time-out error */
00367         status = ERROR;
00368         break;
00369       }
00370     }
00371
00372     /* Disable the ADC instance */
00373     LL_ADC_Disable(ADCx);
00374
00375     /* Wait for ADC instance is effectively disabled */
00376     timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
00377     while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
00378     {
00379       timeout_cpu_cycles--;
00380       if (timeout_cpu_cycles == 0UL)
00381       {
00382         /* Time-out error */
00383         status = ERROR;
00384         break;
00385       }
00386     }
00387   }
00388
00389   /* Check whether ADC state is compliant with expected state */
00390   if (READ_BIT(ADCx->CR,
00391                (ADC_CR_ADSTP | ADC_CR_ADSTART
00392                 | ADC_CR_ADDIS | ADC_CR_ADEN)
00393               )
00394       == 0UL)
00395   {
00396     /* ========== Reset ADC registers ========== */
00397     /* Reset register IER */
00398     CLEAR_BIT(ADCx->IER,
00399               (LL_ADC_IT_ADRDY
00400                | LL_ADC_IT_EOC
00401                | LL_ADC_IT_EOS
00402                | LL_ADC_IT_OVR
00403                | LL_ADC_IT_EOSMP
00404                | LL_ADC_IT_AWD1
00405                | LL_ADC_IT_AWD2
00406                | LL_ADC_IT_AWD3
00407                | LL_ADC_IT_EOCAL
00408                | LL_ADC_IT_CCRDY
00409               )
00410              );
00411
00412     /* Reset register ISR */
00413     SET_BIT(ADCx->ISR,
00414             (LL_ADC_FLAG_ADRDY
00415              | LL_ADC_FLAG_EOC
00416              | LL_ADC_FLAG_EOS
00417              | LL_ADC_FLAG_OVR
00418              | LL_ADC_FLAG_EOSMP
00419              | LL_ADC_FLAG_AWD1
00420              | LL_ADC_FLAG_AWD2
00421              | LL_ADC_FLAG_AWD3
00422              | LL_ADC_FLAG_EOCAL
00423              | LL_ADC_FLAG_CCRDY
00424             )
00425            );
00426
00427     /* Reset register CR */
00428     /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode     */
00429     /* "read-set": no direct reset applicable.                                */
00430     CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
00431
00432     /* Reset register CFGR1 */
00433     CLEAR_BIT(ADCx->CFGR1,
00434               (ADC_CFGR1_AWD1CH  | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
00435                | ADC_CFGR1_AUTOFF  | ADC_CFGR1_WAIT   | ADC_CFGR1_CONT    | ADC_CFGR1_OVRMOD
00436                | ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN   | ADC_CFGR1_RES
00437                | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
00438              );
00439
00440     /* Reset register CFGR2 */
00441     /* Note: Update of ADC clock mode is conditioned to ADC state disabled:   */
00442     /*       already done above.                                              */
00443     CLEAR_BIT(ADCx->CFGR2,
00444               (ADC_CFGR2_CKMODE
00445                | ADC_CFGR2_TOVS   | ADC_CFGR2_OVSS  | ADC_CFGR2_OVSR
00446                | ADC_CFGR2_OVSE)
00447              );
00448
00449     /* Reset register SMPR */
00450     CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
00451
00452     /* Reset register AWD1TR */
00453     MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
00454
00455     /* Reset register AWD2TR */
00456     MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
00457
00458     /* Reset register AWD3TR */
00459     MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
00460
00461     /* Reset register CHSELR */
00462     CLEAR_BIT(ADCx->CHSELR,
00463               (ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
00464                | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
00465                | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9  | ADC_CHSELR_CHSEL8
00466                | ADC_CHSELR_CHSEL7  | ADC_CHSELR_CHSEL6  | ADC_CHSELR_CHSEL5  | ADC_CHSELR_CHSEL4
00467                | ADC_CHSELR_CHSEL3  | ADC_CHSELR_CHSEL2  | ADC_CHSELR_CHSEL1  | ADC_CHSELR_CHSEL0)
00468              );
00469
00470     /* Wait for ADC channel configuration ready */
00471     timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
00472     while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
00473     {
00474       timeout_cpu_cycles--;
00475       if (timeout_cpu_cycles == 0UL)
00476       {
00477         /* Time-out error */
00478         status = ERROR;
00479         break;
00480       }
00481     }
00482
00483     /* Clear flag ADC channel configuration ready */
00484     LL_ADC_ClearFlag_CCRDY(ADCx);
00485
00486     /* Reset register DR */
00487     /* bits in access mode read only, no direct reset applicable */
00488
00489     /* Reset register CALFACT */
00490     CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
00491
00492   }
00493   else
00494   {
00495     /* ADC instance is in an unknown state */
00496     /* Need to performing a hard reset of ADC instance, using high level      */
00497     /* clock source RCC ADC reset.                                            */
00498     /* Caution: On this STM32 series, if several ADC instances are available  */
00499     /*          on the selected device, RCC ADC reset will reset              */
00500     /*          all ADC instances belonging to the common ADC instance.       */
00501     status = ERROR;
00502   }
00503
00504   return status;
00505 }
00506
00507 /**
00508   * @brief  Initialize some features of ADC instance.
00509   * @note   These parameters have an impact on ADC scope: ADC instance.
00510   *         Refer to corresponding unitary functions into
00511   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00512   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00513   *         is conditioned to ADC state:
00514   *         ADC instance must be disabled.
00515   *         This condition is applied to all ADC features, for efficiency
00516   *         and compatibility over all STM32 families. However, the different
00517   *         features can be set under different ADC state conditions
00518   *         (setting possible with ADC enabled without conversion on going,
00519   *         ADC enabled with conversion on going, ...)
00520   *         Each feature can be updated afterwards with a unitary function
00521   *         and potentially with ADC in a different state than disabled,
00522   *         refer to description of each function for setting
00523   *         conditioned to ADC state.
00524   * @note   After using this function, some other features must be configured
00525   *         using LL unitary functions.
00526   *         The minimum configuration remaining to be done is:
00527   *          - Set ADC group regular sequencer:
00528   *            Depending on the sequencer mode (refer to
00529   *            function @ref LL_ADC_REG_SetSequencerConfigurable() ):
00530   *            - map channel on the selected sequencer rank.
00531   *              Refer to function @ref LL_ADC_REG_SetSequencerRanks();
00532   *            - map channel on rank corresponding to channel number.
00533   *              Refer to function @ref LL_ADC_REG_SetSequencerChannels();
00534   *          - Set ADC channel sampling time
00535   *            Refer to function LL_ADC_SetSamplingTimeCommonChannels();
00536   *            Refer to function LL_ADC_SetChannelSamplingTime();
00537   * @param  ADCx ADC instance
00538   * @param  pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00539   * @retval An ErrorStatus enumeration value:
00540   *          - SUCCESS: ADC registers are initialized
00541   *          - ERROR: ADC registers are not initialized
00542   */
00543 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
00544 {
00545   ErrorStatus status = SUCCESS;
00546
00547   /* Check the parameters */
00548   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00549
00550   assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock));
00551   assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
00552   assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
00553   assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
00554
00555   /* Note: Hardware constraint (refer to description of this function):       */
00556   /*       ADC instance must be disabled.                                     */
00557   if (LL_ADC_IsEnabled(ADCx) == 0UL)
00558   {
00559     /* Configuration of ADC hierarchical scope:                               */
00560     /*  - ADC instance                                                        */
00561     /*    - Set ADC data resolution                                           */
00562     /*    - Set ADC conversion data alignment                                 */
00563     /*    - Set ADC low power mode                                            */
00564     MODIFY_REG(ADCx->CFGR1,
00565                ADC_CFGR1_RES
00566                | ADC_CFGR1_ALIGN
00567                | ADC_CFGR1_WAIT
00568                | ADC_CFGR1_AUTOFF
00569                ,
00570                pADC_InitStruct->Resolution
00571                | pADC_InitStruct->DataAlignment
00572                | pADC_InitStruct->LowPowerMode
00573               );
00574
00575     MODIFY_REG(ADCx->CFGR2,
00576                ADC_CFGR2_CKMODE
00577                ,
00578                pADC_InitStruct->Clock
00579               );
00580   }
00581   else
00582   {
00583     /* Initialization error: ADC instance is not disabled. */
00584     status = ERROR;
00585   }
00586
00587   return status;
00588 }
00589
00590 /**
00591   * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
00592   * @param  pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
00593   *                        whose fields will be set to default values.
00594   * @retval None
00595   */
00596 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
00597 {
00598   /* Set pADC_InitStruct fields to default values */
00599   /* Set fields of ADC instance */
00600   pADC_InitStruct->Clock         = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
00601   pADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
00602   pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
00603   pADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
00604
00605 }
00606
00607 /**
00608   * @brief  Initialize some features of ADC group regular.
00609   * @note   These parameters have an impact on ADC scope: ADC group regular.
00610   *         Refer to corresponding unitary functions into
00611   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00612   *         (functions with prefix "REG").
00613   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00614   *         is conditioned to ADC state:
00615   *         ADC instance must be disabled.
00616   *         This condition is applied to all ADC features, for efficiency
00617   *         and compatibility over all STM32 families. However, the different
00618   *         features can be set under different ADC state conditions
00619   *         (setting possible with ADC enabled without conversion on going,
00620   *         ADC enabled with conversion on going, ...)
00621   *         Each feature can be updated afterwards with a unitary function
00622   *         and potentially with ADC in a different state than disabled,
00623   *         refer to description of each function for setting
00624   *         conditioned to ADC state.
00625   * @note   Before using this function, ADC group regular sequencer
00626   *         must be configured: refer to function
00627   *         @ref LL_ADC_REG_SetSequencerConfigurable().
00628   * @note   After using this function, other features must be configured
00629   *         using LL unitary functions.
00630   *         The minimum configuration remaining to be done is:
00631   *          - Set ADC group regular sequencer:
00632   *            Depending on the sequencer mode (refer to
00633   *            function @ref LL_ADC_REG_SetSequencerConfigurable() ):
00634   *            - map channel on the selected sequencer rank.
00635   *              Refer to function @ref LL_ADC_REG_SetSequencerRanks();
00636   *            - map channel on rank corresponding to channel number.
00637   *              Refer to function @ref LL_ADC_REG_SetSequencerChannels();
00638   *          - Set ADC channel sampling time
00639   *            Refer to function LL_ADC_SetSamplingTimeCommonChannels();
00640   *            Refer to function LL_ADC_SetChannelSamplingTime();
00641   * @param  ADCx ADC instance
00642   * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00643   * @retval An ErrorStatus enumeration value:
00644   *          - SUCCESS: ADC registers are initialized
00645   *          - ERROR: ADC registers are not initialized
00646   */
00647 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
00648 {
00649   ErrorStatus status = SUCCESS;
00650
00651   /* Check the parameters */
00652   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00653   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
00654   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
00655   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
00656   assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
00657
00658   if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
00659   {
00660     assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
00661   }
00662
00663   if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
00664       || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00665      )
00666   {
00667     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
00668
00669     /* ADC group regular continuous mode and discontinuous mode                 */
00670     /* can not be enabled simultenaeously                                       */
00671     assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
00672                  || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
00673   }
00674
00675   /* Note: Hardware constraint (refer to description of this function):       */
00676   /*       ADC instance must be disabled.                                     */
00677   if (LL_ADC_IsEnabled(ADCx) == 0UL)
00678   {
00679     /* Configuration of ADC hierarchical scope:                               */
00680     /*  - ADC group regular                                                   */
00681     /*    - Set ADC group regular trigger source                              */
00682     /*    - Set ADC group regular sequencer length                            */
00683     /*    - Set ADC group regular sequencer discontinuous mode                */
00684     /*    - Set ADC group regular continuous mode                             */
00685     /*    - Set ADC group regular conversion data transfer: no transfer or    */
00686     /*      transfer by DMA, and DMA requests mode                            */
00687     /*    - Set ADC group regular overrun behavior                            */
00688     /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
00689     /*       setting of trigger source to SW start.                           */
00690     if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
00691         || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00692        )
00693     {
00694       /* Case of sequencer mode fixed
00695          or sequencer length >= 2 ranks with sequencer mode fully configurable:
00696          discontinuous mode configured */
00697       MODIFY_REG(ADCx->CFGR1,
00698                  ADC_CFGR1_EXTSEL
00699                  | ADC_CFGR1_EXTEN
00700                  | ADC_CFGR1_DISCEN
00701                  | ADC_CFGR1_CONT
00702                  | ADC_CFGR1_DMAEN
00703                  | ADC_CFGR1_DMACFG
00704                  | ADC_CFGR1_OVRMOD
00705                  ,
00706                  pADC_RegInitStruct->TriggerSource
00707                  | pADC_RegInitStruct->SequencerDiscont
00708                  | pADC_RegInitStruct->ContinuousMode
00709                  | pADC_RegInitStruct->DMATransfer
00710                  | pADC_RegInitStruct->Overrun
00711                 );
00712     }
00713     else
00714     {
00715       /* Case of sequencer mode fully configurable
00716          and sequencer length 1 rank (sequencer disabled):
00717          discontinuous mode discarded (fixed to disable) */
00718       MODIFY_REG(ADCx->CFGR1,
00719                  ADC_CFGR1_EXTSEL
00720                  | ADC_CFGR1_EXTEN
00721                  | ADC_CFGR1_DISCEN
00722                  | ADC_CFGR1_CONT
00723                  | ADC_CFGR1_DMAEN
00724                  | ADC_CFGR1_DMACFG
00725                  | ADC_CFGR1_OVRMOD
00726                  ,
00727                  pADC_RegInitStruct->TriggerSource
00728                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
00729                  | pADC_RegInitStruct->ContinuousMode
00730                  | pADC_RegInitStruct->DMATransfer
00731                  | pADC_RegInitStruct->Overrun
00732                 );
00733     }
00734
00735     /* Set ADC group regular sequencer length */
00736     if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
00737     {
00738       LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
00739     }
00740   }
00741   else
00742   {
00743     /* Initialization error: ADC instance is not disabled. */
00744     status = ERROR;
00745   }
00746   return status;
00747 }
00748
00749 /**
00750   * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
00751   * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00752   *                            whose fields will be set to default values.
00753   * @retval None
00754   */
00755 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
00756 {
00757   /* Set pADC_RegInitStruct fields to default values */
00758   /* Set fields of ADC group regular */
00759   /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by      */
00760   /*       setting of trigger source to SW start.                             */
00761   pADC_RegInitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
00762   pADC_RegInitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
00763   pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
00764   pADC_RegInitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
00765   pADC_RegInitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
00766   pADC_RegInitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
00767 }
00768
00769 /**
00770   * @}
00771   */
00772
00773 /**
00774   * @}
00775   */
00776
00777 /**
00778   * @}
00779   */
00780
00781 #endif /* ADC1 */
00782
00783 /**
00784   * @}
00785   */
00786
00787 #endif /* USE_FULL_LL_DRIVER */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_adc.h Source File

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stm32g0xx_ll_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_ADC_H
00021 #define STM32G0xx_LL_ADC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (ADC1)
00035
00036 /** @defgroup ADC_LL ADC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
00045   * @{
00046   */
00047
00048 /* Internal mask for ADC group regular sequencer:                             */
00049 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
00050 /* - sequencer rank bits position into the selected register                  */
00051
00052 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00053
00054 /* Definition of ADC group regular sequencer bits information to be inserted  */
00055 /* into ADC group regular sequencer ranks literals definition.                */
00056 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
00057 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
00058 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
00059 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
00060 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
00061 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
00062 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
00063 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
00064
00065
00066
00067 /* Internal mask for ADC group regular trigger:                               */
00068 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
00069 /* - regular trigger source                                                   */
00070 /* - regular trigger edge                                                     */
00071 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00072
00073 /* Mask containing trigger source masks for each of possible                  */
00074 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00075 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00076 #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
00077                                              ((ADC_CFGR1_EXTSEL)                            << (4U * 1UL)) | \
00078                                              ((ADC_CFGR1_EXTSEL)                            << (4U * 2UL)) | \
00079                                              ((ADC_CFGR1_EXTSEL)                            << (4U * 3UL))  )
00080
00081 /* Mask containing trigger edge masks for each of possible                    */
00082 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00083 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00084 #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
00085                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
00086                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
00087                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
00088
00089 /* Definition of ADC group regular trigger bits information.                  */
00090 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
00091 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
00092
00093
00094
00095 /* Internal mask for ADC channel:                                             */
00096 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
00097 /* - channel identifier defined by number                                     */
00098 /* - channel identifier defined by bitfield                                   */
00099 /* - channel differentiation between external channels (connected to          */
00100 /*   GPIO pins) and internal channels (connected to internal paths)           */
00101 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR1_AWD1CH)
00102 #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_CHSELR_CHSEL)
00103 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ     (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
00104 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
00105 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
00106                                             ADC_CHANNEL_ID_INTERNAL_CH_MASK)
00107 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
00108 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
00109
00110 /* Channel differentiation between external and internal channels */
00111 #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
00112 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)
00113
00114 /* Definition of channels ID number information to be inserted into           */
00115 /* channels literals definition.                                              */
00116 #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
00117 #define ADC_CHANNEL_1_NUMBER               (ADC_CFGR1_AWD1CH_0)
00118 #define ADC_CHANNEL_2_NUMBER               (ADC_CFGR1_AWD1CH_1)
00119 #define ADC_CHANNEL_3_NUMBER               (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
00120 #define ADC_CHANNEL_4_NUMBER               (ADC_CFGR1_AWD1CH_2)
00121 #define ADC_CHANNEL_5_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
00122 #define ADC_CHANNEL_6_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
00123 #define ADC_CHANNEL_7_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
00124 #define ADC_CHANNEL_8_NUMBER               (ADC_CFGR1_AWD1CH_3)
00125 #define ADC_CHANNEL_9_NUMBER               (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
00126 #define ADC_CHANNEL_10_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
00127 #define ADC_CHANNEL_11_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
00128 #define ADC_CHANNEL_12_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
00129 #define ADC_CHANNEL_13_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
00130 #define ADC_CHANNEL_14_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
00131 #define ADC_CHANNEL_15_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
00132                                             ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
00133 #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR1_AWD1CH_4)
00134 #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
00135 #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
00136
00137 /* Definition of channels ID bitfield information to be inserted into         */
00138 /* channels literals definition.                                              */
00139 #define ADC_CHANNEL_0_BITFIELD             (ADC_CHSELR_CHSEL0)
00140 #define ADC_CHANNEL_1_BITFIELD             (ADC_CHSELR_CHSEL1)
00141 #define ADC_CHANNEL_2_BITFIELD             (ADC_CHSELR_CHSEL2)
00142 #define ADC_CHANNEL_3_BITFIELD             (ADC_CHSELR_CHSEL3)
00143 #define ADC_CHANNEL_4_BITFIELD             (ADC_CHSELR_CHSEL4)
00144 #define ADC_CHANNEL_5_BITFIELD             (ADC_CHSELR_CHSEL5)
00145 #define ADC_CHANNEL_6_BITFIELD             (ADC_CHSELR_CHSEL6)
00146 #define ADC_CHANNEL_7_BITFIELD             (ADC_CHSELR_CHSEL7)
00147 #define ADC_CHANNEL_8_BITFIELD             (ADC_CHSELR_CHSEL8)
00148 #define ADC_CHANNEL_9_BITFIELD             (ADC_CHSELR_CHSEL9)
00149 #define ADC_CHANNEL_10_BITFIELD            (ADC_CHSELR_CHSEL10)
00150 #define ADC_CHANNEL_11_BITFIELD            (ADC_CHSELR_CHSEL11)
00151 #define ADC_CHANNEL_12_BITFIELD            (ADC_CHSELR_CHSEL12)
00152 #define ADC_CHANNEL_13_BITFIELD            (ADC_CHSELR_CHSEL13)
00153 #define ADC_CHANNEL_14_BITFIELD            (ADC_CHSELR_CHSEL14)
00154 #define ADC_CHANNEL_15_BITFIELD            (ADC_CHSELR_CHSEL15)
00155 #define ADC_CHANNEL_16_BITFIELD            (ADC_CHSELR_CHSEL16)
00156 #define ADC_CHANNEL_17_BITFIELD            (ADC_CHSELR_CHSEL17)
00157 #define ADC_CHANNEL_18_BITFIELD            (ADC_CHSELR_CHSEL18)
00158
00159 /* Internal mask for ADC channel sampling time:                               */
00160 /* To select into literals LL_ADC_SAMPLINGTIME_x                              */
00161 /* the relevant bits for:                                                     */
00162 /* (concatenation of multiple bits used in register SMPR)                     */
00163 /* - ADC channels sampling time: setting channel wise, to map each channel    */
00164 /*   on one of the common sampling time available.                            */
00165 /* - ADC channels common sampling time: set a sampling time into one of the   */
00166 /*   common sampling time available.                                          */
00167 #define ADC_SAMPLING_TIME_CH_MASK          (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
00168 #define ADC_SAMPLING_TIME_SMP_MASK         (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
00169 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK   (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
00170
00171 /* Internal mask for ADC analog watchdog:                                     */
00172 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
00173 /* (concatenation of multiple bits used in different analog watchdogs,        */
00174 /* (feature of several watchdogs not available on all STM32 families)).       */
00175 /* - analog watchdog 1: monitored channel defined by number,                  */
00176 /*   selection of ADC group (ADC group regular).                              */
00177 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
00178 /*   selection on groups.                                                     */
00179
00180 /* Internal register offset for ADC analog watchdog channel configuration */
00181 #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
00182 #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
00183 #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
00184
00185 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
00186 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
00187 #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
00188 #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
00189
00190 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
00191 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
00192
00193 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
00194 #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
00195 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
00196
00197 #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
00198
00199 /* Internal register offset for ADC analog watchdog threshold configuration */
00200 #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
00201 #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
00202 #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
00203 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
00204 #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
00205 #define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit to discriminate threshold high: mask of bit */
00206 #define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit to discriminate threshold high: position of bit */
00207 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
00208 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
00209
00210
00211
00212 /* ADC registers bits positions */
00213 #define ADC_CFGR1_RES_BITOFFSET_POS        ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */
00214 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS     (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
00215 #define ADC_TR1_HT1_BITOFFSET_POS          (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
00216 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS    ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
00217 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS    ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
00218 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS    ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
00219 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS    ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
00220 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS    ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
00221 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS    ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
00222 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS    ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
00223 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS    ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
00224 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS    ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
00225 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS    ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
00226 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS   (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
00227 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS   (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
00228 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS   (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
00229 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS   (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
00230 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS   (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
00231 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS   (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
00232 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS   (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
00233 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS   (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
00234 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS   (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
00235 #define ADC_SMPR_SMP1_BITOFFSET_POS        ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
00236 #define ADC_SMPR_SMP2_BITOFFSET_POS        ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
00237 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS     ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
00238
00239
00240 /* ADC registers bits groups */
00241 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
00242
00243
00244 /* ADC internal channels related definitions */
00245 /* Internal voltage reference VrefInt */
00246 #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00247 #define VREFINT_CAL_VREF                   ( 3000UL)                    /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
00248 /* Temperature sensor */
00249 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G0, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00250 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00251 #define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)            /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00252 #define TEMPSENSOR_CAL2_TEMP               (( int32_t)  130)            /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00253 #define TEMPSENSOR_CAL_VREFANALOG          ( 3000UL)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
00254
00255 /**
00256   * @}
00257   */
00258
00259
00260 /* Private macros ------------------------------------------------------------*/
00261 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
00262   * @{
00263   */
00264
00265 /**
00266   * @brief  Driver macro reserved for internal use: set a pointer to
00267   *         a register from a register basis from which an offset
00268   *         is applied.
00269   * @param  __REG__ Register basis from which the offset is applied.
00270   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00271   * @retval Pointer to register address
00272   */
00273 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00274   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
00275
00276 /**
00277   * @}
00278   */
00279
00280
00281 /* Exported types ------------------------------------------------------------*/
00282 #if defined(USE_FULL_LL_DRIVER)
00283 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
00284   * @{
00285   */
00286
00287 /**
00288   * @brief  Structure definition of some features of ADC common parameters
00289   *         and multimode
00290   *         (all ADC instances belonging to the same ADC common instance).
00291   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
00292   *         is conditioned to ADC instances state (all ADC instances
00293   *         sharing the same ADC common instance):
00294   *         All ADC instances sharing the same ADC common instance must be
00295   *         disabled.
00296   */
00297 typedef struct
00298 {
00299   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
00300                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
00301
00302                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
00303
00304 } LL_ADC_CommonInitTypeDef;
00305
00306 /**
00307   * @brief  Structure definition of some features of ADC instance.
00308   * @note   These parameters have an impact on ADC scope: ADC instance.
00309   *         Refer to corresponding unitary functions into
00310   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00311   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00312   *         is conditioned to ADC state:
00313   *         ADC instance must be disabled.
00314   *         This condition is applied to all ADC features, for efficiency
00315   *         and compatibility over all STM32 families. However, the different
00316   *         features can be set under different ADC state conditions
00317   *         (setting possible with ADC enabled without conversion on going,
00318   *         ADC enabled with conversion on going, ...)
00319   *         Each feature can be updated afterwards with a unitary function
00320   *         and potentially with ADC in a different state than disabled,
00321   *         refer to description of each function for setting
00322   *         conditioned to ADC state.
00323   */
00324 typedef struct
00325 {
00326   uint32_t Clock;                       /*!< Set ADC instance clock source and prescaler.
00327                                              This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
00328                                              @note On this STM32 series, this parameter has some clock ratio constraints:
00329                                                    ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
00330                                                    (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
00331
00332                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
00333                                              For more details, refer to description of this function. */
00334
00335   uint32_t Resolution;                  /*!< Set ADC resolution.
00336                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
00337
00338                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
00339
00340   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
00341                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
00342
00343                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
00344
00345   uint32_t LowPowerMode;                /*!< Set ADC low power mode.
00346                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE
00347
00348                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
00349
00350 } LL_ADC_InitTypeDef;
00351
00352 /**
00353   * @brief  Structure definition of some features of ADC group regular.
00354   * @note   These parameters have an impact on ADC scope: ADC group regular.
00355   *         Refer to corresponding unitary functions into
00356   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00357   *         (functions with prefix "REG").
00358   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
00359   *         is conditioned to ADC state:
00360   *         ADC instance must be disabled.
00361   *         This condition is applied to all ADC features, for efficiency
00362   *         and compatibility over all STM32 families. However, the different
00363   *         features can be set under different ADC state conditions
00364   *         (setting possible with ADC enabled without conversion on going,
00365   *         ADC enabled with conversion on going, ...)
00366   *         Each feature can be updated afterwards with a unitary function
00367   *         and potentially with ADC in a different state than disabled,
00368   *         refer to description of each function for setting
00369   *         conditioned to ADC state.
00370   */
00371 typedef struct
00372 {
00373   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
00374                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
00375                                              @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
00376                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00377                                                    In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
00378
00379                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
00380
00381   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
00382                                              @note This parameter has an effect only if group regular sequencer is set to mode "fully configurable". Refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
00383                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
00384
00385                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
00386
00387   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00388                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
00389                                              @note This parameter has an effect only if group regular sequencer is enabled
00390                                                    (depending on the sequencer mode: scan length of 2 ranks or more, or several ADC channels enabled in group regular sequencer. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
00391
00392                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
00393
00394   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
00395                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
00396                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
00397
00398                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
00399
00400   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
00401                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
00402
00403                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
00404
00405   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
00406                                              data preserved or overwritten.
00407                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
00408
00409                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
00410
00411 } LL_ADC_REG_InitTypeDef;
00412
00413 /**
00414   * @}
00415   */
00416 #endif /* USE_FULL_LL_DRIVER */
00417
00418 /* Exported constants --------------------------------------------------------*/
00419 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
00420   * @{
00421   */
00422
00423 /** @defgroup ADC_LL_EC_FLAG ADC flags
00424   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
00425   * @{
00426   */
00427 #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
00428 #define LL_ADC_FLAG_CCRDY                  ADC_ISR_CCRDY      /*!< ADC flag ADC channel configuration ready */
00429 #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
00430 #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
00431 #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
00432 #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
00433 #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
00434 #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
00435 #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
00436 #define LL_ADC_FLAG_EOCAL                  ADC_ISR_EOCAL      /*!< ADC flag end of calibration */
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
00442   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
00443   * @{
00444   */
00445 #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
00446 #define LL_ADC_IT_CCRDY                    ADC_IER_CCRDYIE    /*!< ADC interruption channel configuration ready */
00447 #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
00448 #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
00449 #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
00450 #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
00451 #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
00452 #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
00453 #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
00454 #define LL_ADC_IT_EOCAL                    ADC_IER_EOCALIE    /*!< ADC interruption ADC end of calibration */
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
00460   * @{
00461   */
00462 /* List of ADC registers intended to be used (most commonly) with             */
00463 /* DMA transfer.                                                              */
00464 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
00465 #define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00471   * @{
00472   */
00473 #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */
00474 #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00475 #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00476 #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00477 #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00478 #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00479 #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00480 #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00481 #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00482 #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00483 #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00484 #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE  ADC common - Clock frequency mode
00490   * @{
00491   */
00492 #define LL_ADC_CLOCK_FREQ_MODE_HIGH        (0x00000000UL)         /*!< ADC clock mode to high frequency. On STM32G0, ADC clock frequency above 3.5MHz.  */
00493 #define LL_ADC_CLOCK_FREQ_MODE_LOW         (ADC_CCR_LFMEN)        /*!< ADC clock mode to low frequency. On STM32G0, ADC clock frequency below 3.5MHz.  */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
00499   * @{
00500   */
00501 /* Note: Other measurement paths to internal channels may be available        */
00502 /*       (connections to other peripherals).                                  */
00503 /*       If they are not listed below, they do not require any specific       */
00504 /*       path enable. In this case, Access to measurement path is done        */
00505 /*       only by selecting the corresponding ADC internal channel.            */
00506 #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement paths all disabled */
00507 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
00508 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
00509 #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */
00510 /**
00511   * @}
00512   */
00513
00514 /** @defgroup ADC_LL_EC_CLOCK_SOURCE  ADC instance - Clock source
00515   * @{
00516   */
00517 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CFGR2_CKMODE_1)                                  /*!< ADC synchronous clock derived from AHB clock divided by 4 */
00518 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CFGR2_CKMODE_0)                                  /*!< ADC synchronous clock derived from AHB clock divided by 2 */
00519 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0)             /*!< ADC synchronous clock derived from AHB clock not divided  */
00520 #define LL_ADC_CLOCK_ASYNC                 (0x00000000UL)                                        /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
00526   * @{
00527   */
00528 #define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */
00529 #define LL_ADC_RESOLUTION_10B              (                  ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
00530 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR1_RES_1                  ) /*!< ADC resolution  8 bits */
00531 #define LL_ADC_RESOLUTION_6B               (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution  6 bits */
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
00537   * @{
00538   */
00539 #define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)         /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
00540 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR1_ALIGN)      /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
00541 /**
00542   * @}
00543   */
00544
00545 /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
00546   * @{
00547   */
00548 #define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low power mode activated */
00549 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR1_WAIT)                    /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
00550 #define LL_ADC_LP_AUTOPOWEROFF             (ADC_CFGR1_AUTOFF)                  /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
00551 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF    (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
00552 /**
00553   * @}
00554   */
00555
00556 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ  ADC group regular - Trigger frequency mode
00557   * @{
00558   */
00559 #define LL_ADC_TRIGGER_FREQ_HIGH           (0x00000000UL)            /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
00560 #define LL_ADC_TRIGGER_FREQ_LOW            (ADC_CFGR2_LFTRIG)        /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON  ADC instance - Sampling time common to a group of channels
00566   * @{
00567   */
00568 #define LL_ADC_SAMPLINGTIME_COMMON_1       (ADC_SMPR_SMP1_BITOFFSET_POS)                             /*!< Set sampling time common to a group of channels: sampling time nb 1 */
00569 #define LL_ADC_SAMPLINGTIME_COMMON_2       (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
00570 /**
00571   * @}
00572   */
00573
00574 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
00575   * @{
00576   */
00577 #define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
00583   * @{
00584   */
00585 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00586 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00587 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00588 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00589 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00590 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00591 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00592 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00593 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00594 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00595 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00596 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00597 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00598 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00599 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00600 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00601 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00602 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00603 #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00604 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
00605 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Temperature sensor. */
00606 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
00607 /**
00608   * @}
00609   */
00610
00611 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
00612   * @{
00613   */
00614 #define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                                                                 /*!< ADC group regular conversion trigger internal: SW start. */
00615 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (                                                               ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00616 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4       (                                          ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00617 #if defined(TIM2)
00618 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (                     ADC_CFGR1_EXTSEL_1                      | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00619 #endif /* TIM2 */
00620 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (                     ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00621 #if defined(TIM4)
00622 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1                      | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00623 #endif /* TIM4 */
00624 #if defined(TIM6)
00625 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR1_EXTSEL_2                      | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00626 #endif /* TIM6 */
00627 #if defined(TIM15)
00628 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR1_EXTSEL_2                                           | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00629 #endif /* TIM15 */
00630 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
00636   * @{
00637   */
00638 #define LL_ADC_REG_TRIG_EXT_RISING         (                    ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
00639 #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR1_EXTEN_1                    ) /*!< ADC group regular conversion trigger polarity set to falling edge */
00640 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00641 /**
00642   * @}
00643   */
00644
00645 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
00646   * @{
00647   */
00648 #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are performed in single mode: one conversion per trigger */
00649 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR1_CONT)        /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
00650 /**
00651   * @}
00652   */
00653
00654 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
00655   * @{
00656   */
00657 #define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)                        /*!< ADC conversions are not transferred by DMA */
00658 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                   ADC_CFGR1_DMAEN)  /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
00659 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)  /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
00660 /**
00661   * @}
00662   */
00663
00664 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00665   * @{
00666   */
00667 #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior in case of overrun: data preserved */
00668 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR1_OVRMOD)     /*!< ADC group regular behavior in case of overrun: data overwritten */
00669 /**
00670   * @}
00671   */
00672
00673 /** @defgroup ADC_LL_EC_REG_SEQ_MODE  ADC group regular - Sequencer configuration flexibility
00674   * @{
00675   */
00676 #define LL_ADC_REG_SEQ_FIXED               (0x00000000UL)         /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
00677 #define LL_ADC_REG_SEQ_CONFIGURABLE        (ADC_CFGR1_CHSELRMOD)  /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
00678 /**
00679   * @}
00680   */
00681
00682 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
00683   * @{
00684   */
00685 #define LL_ADC_REG_SEQ_SCAN_DISABLE        (ADC_CHSELR_SQ2)       /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00686 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (ADC_CHSELR_SQ3)       /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
00687 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (ADC_CHSELR_SQ4)       /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
00688 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (ADC_CHSELR_SQ5)       /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
00689 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (ADC_CHSELR_SQ6)       /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
00690 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (ADC_CHSELR_SQ7)       /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
00691 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (ADC_CHSELR_SQ8)       /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
00692 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (0x00000000UL)         /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
00693 /**
00694   * @}
00695   */
00696
00697 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION  ADC group regular - Sequencer scan direction
00698   * @{
00699   */
00700 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD    (0x00000000UL)         /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
00701 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD   (ADC_CFGR1_SCANDIR)    /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
00702 /**
00703   * @}
00704   */
00705
00706 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
00707   * @{
00708   */
00709 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                                               /*!< ADC group regular sequencer discontinuous mode disable */
00710 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR1_DISCEN)                                                           /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00716   * @{
00717   */
00718 #define LL_ADC_REG_RANK_1                  (ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
00719 #define LL_ADC_REG_RANK_2                  (ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
00720 #define LL_ADC_REG_RANK_3                  (ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
00721 #define LL_ADC_REG_RANK_4                  (ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
00722 #define LL_ADC_REG_RANK_5                  (ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
00723 #define LL_ADC_REG_RANK_6                  (ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
00724 #define LL_ADC_REG_RANK_7                  (ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
00725 #define LL_ADC_REG_RANK_8                  (ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
00731   * @{
00732   */
00733 #define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000UL)                                        /*!< Sampling time 1.5 ADC clock cycle */
00734 #define LL_ADC_SAMPLINGTIME_3CYCLES_5      (ADC_SMPR_SMP1_0)                                     /*!< Sampling time 3.5 ADC clock cycles */
00735 #define LL_ADC_SAMPLINGTIME_7CYCLES_5      (ADC_SMPR_SMP1_1)                                     /*!< Sampling time 7.5 ADC clock cycles */
00736 #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0)                   /*!< Sampling time 12.5 ADC clock cycles */
00737 #define LL_ADC_SAMPLINGTIME_19CYCLES_5     (ADC_SMPR_SMP1_2)                                     /*!< Sampling time 19.5 ADC clock cycles */
00738 #define LL_ADC_SAMPLINGTIME_39CYCLES_5     (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0)                   /*!< Sampling time 39.5 ADC clock cycles */
00739 #define LL_ADC_SAMPLINGTIME_79CYCLES_5     (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1)                   /*!< Sampling time 79.5 ADC clock cycles */
00740 #define LL_ADC_SAMPLINGTIME_160CYCLES_5    (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
00741 /**
00742   * @}
00743   */
00744
00745 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
00746   * @{
00747   */
00748 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
00749 #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
00750 #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
00751 /**
00752   * @}
00753   */
00754
00755 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
00756   * @{
00757   */
00758 #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                             /*!< ADC analog watchdog monitoring disabled */
00759 #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                         | ADC_CFGR1_AWD1EN                    ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
00760 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
00761 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
00762 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
00763 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
00764 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
00765 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
00766 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
00767 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
00768 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
00769 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
00770 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
00771 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
00772 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
00773 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
00774 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
00775 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
00776 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
00777 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
00778 #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
00779 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
00780 #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
00781 #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
00782 /**
00783   * @}
00784   */
00785
00786 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
00787   * @{
00788   */
00789 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD1TR_HT1                 ) /*!< ADC analog watchdog threshold high */
00790 #define LL_ADC_AWD_THRESHOLD_LOW           (                 ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
00791 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
00792 /**
00793   * @}
00794   */
00795
00796 /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
00797   * @{
00798   */
00799 #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */
00800 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_OVSE)  /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
00801 /**
00802   * @}
00803   */
00804
00805 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
00806   * @{
00807   */
00808 #define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
00809 #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TOVS)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
00810 /**
00811   * @}
00812   */
00813
00814 /** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
00815   * @{
00816   */
00817 #define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                                           /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00818 #define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00819 #define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00820 #define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00821 #define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00822 #define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00823 #define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00824 #define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00825 /**
00826   * @}
00827   */
00828
00829 /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
00830   * @{
00831   */
00832 #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                                              /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
00833 #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
00834 #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
00835 #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
00836 #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
00837 #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
00838 #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
00839 #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
00840 #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
00841 /**
00842   * @}
00843   */
00844
00845 /** @defgroup ADC_LL_EC_HELPER_MACRO  Definitions of constants used by helper macro
00846   * @{
00847   */
00848 #define LL_ADC_TEMPERATURE_CALC_ERROR     ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */
00849 /**
00850   * @}
00851   */
00852
00853 /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
00854   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
00855   *         not timeout values.
00856   *         For details on delays values, refer to descriptions in source code
00857   *         above each literal definition.
00858   * @{
00859   */
00860
00861 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
00862 /*       not timeout values.                                                  */
00863 /*       Timeout values for ADC operations are dependent to device clock      */
00864 /*       configuration (system clock versus ADC clock),                       */
00865 /*       and therefore must be defined in user application.                   */
00866 /*       Indications for estimation of ADC timeout delays, for this           */
00867 /*       STM32 series:                                                        */
00868 /*       - ADC calibration time: maximum delay is 82/fADC.                    */
00869 /*         (refer to device datasheet, parameter "tCAL")                      */
00870 /*       - ADC enable time: maximum delay is 1 conversion cycle.              */
00871 /*         (refer to device datasheet, parameter "tSTAB")                     */
00872 /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
00873 /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
00874 /*         cycles                                                             */
00875 /*       - ADC conversion time: duration depending on ADC clock and ADC       */
00876 /*         configuration.                                                     */
00877 /*         (refer to device reference manual, section "Timing")               */
00878
00879 /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
00880 /* Delay set to maximum value (refer to device datasheet,                     */
00881 /* parameter "tADCVREG_STUP").                                                */
00882 /* Unit: us                                                                   */
00883 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
00884
00885 /* Delay for internal voltage reference stabilization time.                   */
00886 /* Delay set to maximum value (refer to device datasheet,                     */
00887 /* parameter "tstart_vrefint").                                               */
00888 /* Unit: us                                                                   */
00889 #define LL_ADC_DELAY_VREFINT_STAB_US           ( 12UL)  /*!< Delay for internal voltage reference stabilization time */
00890
00891 /* Delay for temperature sensor stabilization time.                           */
00892 /* Literal set to maximum value (refer to device datasheet,                   */
00893 /* parameter "tSTART").                                                       */
00894 /* Unit: us                                                                   */
00895 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US        (120UL)  /*!< Delay for temperature sensor stabilization time (starting from temperature sensor enable, refer to @ref LL_ADC_SetCommonPathInternalCh()) */
00896 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)  /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */
00897
00898 /* Delay required between ADC end of calibration and ADC enable.              */
00899 /* Note: On this STM32 series, a minimum number of ADC clock cycles           */
00900 /*       are required between ADC end of calibration and ADC enable.          */
00901 /*       Wait time can be computed in user application by waiting for the     */
00902 /*       equivalent number of CPU cycles, by taking into account              */
00903 /*       ratio of CPU clock versus ADC clock prescalers.                      */
00904 /* Unit: ADC clock cycles.                                                    */
00905 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES   (  2UL)  /*!< Delay required between ADC end of calibration and ADC enable */
00906
00907 /**
00908   * @}
00909   */
00910
00911 /**
00912   * @}
00913   */
00914
00915
00916 /* Exported macro ------------------------------------------------------------*/
00917 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
00918   * @{
00919   */
00920
00921 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
00922   * @{
00923   */
00924
00925 /**
00926   * @brief  Write a value in ADC register
00927   * @param  __INSTANCE__ ADC Instance
00928   * @param  __REG__ Register to be written
00929   * @param  __VALUE__ Value to be written in the register
00930   * @retval None
00931   */
00932 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00933
00934 /**
00935   * @brief  Read a value in ADC register
00936   * @param  __INSTANCE__ ADC Instance
00937   * @param  __REG__ Register to be read
00938   * @retval Register value
00939   */
00940 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00941 /**
00942   * @}
00943   */
00944
00945 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
00946   * @{
00947   */
00948
00949 /**
00950   * @brief  Helper macro to get ADC channel number in decimal format
00951   *         from literals LL_ADC_CHANNEL_x.
00952   * @note   Example:
00953   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
00954   *           will return decimal number "4".
00955   * @note   The input can be a value from functions where a channel
00956   *         number is returned, either defined with number
00957   *         or with bitfield (only one bit must be set).
00958   * @param  __CHANNEL__ This parameter can be one of the following values:
00959   *         @arg @ref LL_ADC_CHANNEL_0
00960   *         @arg @ref LL_ADC_CHANNEL_1
00961   *         @arg @ref LL_ADC_CHANNEL_2
00962   *         @arg @ref LL_ADC_CHANNEL_3
00963   *         @arg @ref LL_ADC_CHANNEL_4
00964   *         @arg @ref LL_ADC_CHANNEL_5
00965   *         @arg @ref LL_ADC_CHANNEL_6
00966   *         @arg @ref LL_ADC_CHANNEL_7
00967   *         @arg @ref LL_ADC_CHANNEL_8
00968   *         @arg @ref LL_ADC_CHANNEL_9
00969   *         @arg @ref LL_ADC_CHANNEL_10
00970   *         @arg @ref LL_ADC_CHANNEL_11
00971   *         @arg @ref LL_ADC_CHANNEL_12
00972   *         @arg @ref LL_ADC_CHANNEL_13
00973   *         @arg @ref LL_ADC_CHANNEL_14
00974   *         @arg @ref LL_ADC_CHANNEL_15         (1)
00975   *         @arg @ref LL_ADC_CHANNEL_16         (1)
00976   *         @arg @ref LL_ADC_CHANNEL_17         (1)
00977   *         @arg @ref LL_ADC_CHANNEL_18
00978   *         @arg @ref LL_ADC_CHANNEL_VREFINT
00979   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
00980   *         @arg @ref LL_ADC_CHANNEL_VBAT
00981   *
00982   *         (1) On STM32G0, parameter can be set in ADC group sequencer
00983   *             only if sequencer is set in mode "not fully configurable",
00984   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
00985   * @retval Value between Min_Data=0 and Max_Data=18
00986   */
00987 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                                     \
00988   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                                            \
00989    (                                                                                                    \
00990        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS              \
00991    )                                                                                                    \
00992    :                                                                                                    \
00993    ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) :                      \
00994     ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) :                     \
00995      ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) :                    \
00996       ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) :                   \
00997        ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) :                  \
00998         ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) :                 \
00999          ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) :                \
01000           ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) :               \
01001            ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) :              \
01002             ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) :             \
01003              ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) :         \
01004               ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) :        \
01005                ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) :       \
01006                 ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) :      \
01007                  ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) :     \
01008                   ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) :    \
01009                    ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) :   \
01010                     ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) :  \
01011                      ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) : \
01012                       (0UL)))))))))))))))))))))
01013
01014 /**
01015   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
01016   *         from number in decimal format.
01017   * @note   Example:
01018   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01019   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
01020   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
01021   * @retval Returned value can be one of the following values:
01022   *         @arg @ref LL_ADC_CHANNEL_0
01023   *         @arg @ref LL_ADC_CHANNEL_1
01024   *         @arg @ref LL_ADC_CHANNEL_2
01025   *         @arg @ref LL_ADC_CHANNEL_3
01026   *         @arg @ref LL_ADC_CHANNEL_4
01027   *         @arg @ref LL_ADC_CHANNEL_5
01028   *         @arg @ref LL_ADC_CHANNEL_6
01029   *         @arg @ref LL_ADC_CHANNEL_7
01030   *         @arg @ref LL_ADC_CHANNEL_8
01031   *         @arg @ref LL_ADC_CHANNEL_9
01032   *         @arg @ref LL_ADC_CHANNEL_10
01033   *         @arg @ref LL_ADC_CHANNEL_11
01034   *         @arg @ref LL_ADC_CHANNEL_12
01035   *         @arg @ref LL_ADC_CHANNEL_13
01036   *         @arg @ref LL_ADC_CHANNEL_14
01037   *         @arg @ref LL_ADC_CHANNEL_15         (1)
01038   *         @arg @ref LL_ADC_CHANNEL_16         (1)
01039   *         @arg @ref LL_ADC_CHANNEL_17         (1)
01040   *         @arg @ref LL_ADC_CHANNEL_18
01041   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (2)
01042   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
01043   *         @arg @ref LL_ADC_CHANNEL_VBAT       (2)
01044   *
01045   *         (1) On STM32G0, parameter can be set in ADC group sequencer
01046   *             only if sequencer is set in mode "not fully configurable",
01047   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
01048   *         (2) For ADC channel read back from ADC register,
01049   *             comparison with internal channel parameter to be done
01050   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01051   */
01052 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
01053   (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) |                 \
01054    (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
01055
01056 /**
01057   * @brief  Helper macro to determine whether the selected channel
01058   *         corresponds to literal definitions of driver.
01059   * @note   The different literal definitions of ADC channels are:
01060   *         - ADC internal channel:
01061   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
01062   *         - ADC external channel (channel connected to a GPIO pin):
01063   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
01064   * @note   The channel parameter must be a value defined from literal
01065   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01066   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01067   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
01068   *         must not be a value from functions where a channel number is
01069   *         returned from ADC registers,
01070   *         because internal and external channels share the same channel
01071   *         number in ADC registers. The differentiation is made only with
01072   *         parameters definitions of driver.
01073   * @param  __CHANNEL__ This parameter can be one of the following values:
01074   *         @arg @ref LL_ADC_CHANNEL_0
01075   *         @arg @ref LL_ADC_CHANNEL_1
01076   *         @arg @ref LL_ADC_CHANNEL_2
01077   *         @arg @ref LL_ADC_CHANNEL_3
01078   *         @arg @ref LL_ADC_CHANNEL_4
01079   *         @arg @ref LL_ADC_CHANNEL_5
01080   *         @arg @ref LL_ADC_CHANNEL_6
01081   *         @arg @ref LL_ADC_CHANNEL_7
01082   *         @arg @ref LL_ADC_CHANNEL_8
01083   *         @arg @ref LL_ADC_CHANNEL_9
01084   *         @arg @ref LL_ADC_CHANNEL_10
01085   *         @arg @ref LL_ADC_CHANNEL_11
01086   *         @arg @ref LL_ADC_CHANNEL_12
01087   *         @arg @ref LL_ADC_CHANNEL_13
01088   *         @arg @ref LL_ADC_CHANNEL_14
01089   *         @arg @ref LL_ADC_CHANNEL_15         (1)
01090   *         @arg @ref LL_ADC_CHANNEL_16         (1)
01091   *         @arg @ref LL_ADC_CHANNEL_17         (1)
01092   *         @arg @ref LL_ADC_CHANNEL_18
01093   *         @arg @ref LL_ADC_CHANNEL_VREFINT
01094   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
01095   *         @arg @ref LL_ADC_CHANNEL_VBAT
01096   *
01097   *         (1) On STM32G0, parameter can be set in ADC group sequencer
01098   *             only if sequencer is set in mode "not fully configurable",
01099   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
01100   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01101   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01102   */
01103 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
01104   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
01105
01106 /**
01107   * @brief  Helper macro to convert a channel defined from parameter
01108   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01109   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01110   *         to its equivalent parameter definition of a ADC external channel
01111   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
01112   * @note   The channel parameter can be, additionally to a value
01113   *         defined from parameter definition of a ADC internal channel
01114   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
01115   *         a value defined from parameter definition of
01116   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01117   *         or a value from functions where a channel number is returned
01118   *         from ADC registers.
01119   * @param  __CHANNEL__ This parameter can be one of the following values:
01120   *         @arg @ref LL_ADC_CHANNEL_0
01121   *         @arg @ref LL_ADC_CHANNEL_1
01122   *         @arg @ref LL_ADC_CHANNEL_2
01123   *         @arg @ref LL_ADC_CHANNEL_3
01124   *         @arg @ref LL_ADC_CHANNEL_4
01125   *         @arg @ref LL_ADC_CHANNEL_5
01126   *         @arg @ref LL_ADC_CHANNEL_6
01127   *         @arg @ref LL_ADC_CHANNEL_7
01128   *         @arg @ref LL_ADC_CHANNEL_8
01129   *         @arg @ref LL_ADC_CHANNEL_9
01130   *         @arg @ref LL_ADC_CHANNEL_10
01131   *         @arg @ref LL_ADC_CHANNEL_11
01132   *         @arg @ref LL_ADC_CHANNEL_12
01133   *         @arg @ref LL_ADC_CHANNEL_13
01134   *         @arg @ref LL_ADC_CHANNEL_14
01135   *         @arg @ref LL_ADC_CHANNEL_15         (1)
01136   *         @arg @ref LL_ADC_CHANNEL_16         (1)
01137   *         @arg @ref LL_ADC_CHANNEL_17         (1)
01138   *         @arg @ref LL_ADC_CHANNEL_18
01139   *         @arg @ref LL_ADC_CHANNEL_VREFINT
01140   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
01141   *         @arg @ref LL_ADC_CHANNEL_VBAT
01142   *
01143   *         (1) On STM32G0, parameter can be set in ADC group sequencer
01144   *             only if sequencer is set in mode "not fully configurable",
01145   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
01146   * @retval Returned value can be one of the following values:
01147   *         @arg @ref LL_ADC_CHANNEL_0
01148   *         @arg @ref LL_ADC_CHANNEL_1
01149   *         @arg @ref LL_ADC_CHANNEL_2
01150   *         @arg @ref LL_ADC_CHANNEL_3
01151   *         @arg @ref LL_ADC_CHANNEL_4
01152   *         @arg @ref LL_ADC_CHANNEL_5
01153   *         @arg @ref LL_ADC_CHANNEL_6
01154   *         @arg @ref LL_ADC_CHANNEL_7
01155   *         @arg @ref LL_ADC_CHANNEL_8
01156   *         @arg @ref LL_ADC_CHANNEL_9
01157   *         @arg @ref LL_ADC_CHANNEL_10
01158   *         @arg @ref LL_ADC_CHANNEL_11
01159   *         @arg @ref LL_ADC_CHANNEL_12
01160   *         @arg @ref LL_ADC_CHANNEL_13
01161   *         @arg @ref LL_ADC_CHANNEL_14
01162   *         @arg @ref LL_ADC_CHANNEL_15
01163   *         @arg @ref LL_ADC_CHANNEL_16
01164   *         @arg @ref LL_ADC_CHANNEL_17
01165   *         @arg @ref LL_ADC_CHANNEL_18
01166   */
01167 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
01168   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
01169
01170 /**
01171   * @brief  Helper macro to determine whether the internal channel
01172   *         selected is available on the ADC instance selected.
01173   * @note   The channel parameter must be a value defined from parameter
01174   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01175   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01176   *         must not be a value defined from parameter definition of
01177   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01178   *         or a value from functions where a channel number is
01179   *         returned from ADC registers,
01180   *         because internal and external channels share the same channel
01181   *         number in ADC registers. The differentiation is made only with
01182   *         parameters definitions of driver.
01183   * @param  __ADC_INSTANCE__ ADC instance
01184   * @param  __CHANNEL__ This parameter can be one of the following values:
01185   *         @arg @ref LL_ADC_CHANNEL_VREFINT
01186   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
01187   *         @arg @ref LL_ADC_CHANNEL_VBAT
01188   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01189   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01190   */
01191 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01192   (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                             \
01193    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                             \
01194    ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT))
01195
01196 /**
01197   * @brief  Helper macro to define ADC analog watchdog parameter:
01198   *         define a single channel to monitor with analog watchdog
01199   *         from sequencer channel and groups definition.
01200   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
01201   *         Example:
01202   *           LL_ADC_SetAnalogWDMonitChannels(
01203   *             ADC1, LL_ADC_AWD1,
01204   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
01205   * @param  __CHANNEL__ This parameter can be one of the following values:
01206   *         @arg @ref LL_ADC_CHANNEL_0
01207   *         @arg @ref LL_ADC_CHANNEL_1
01208   *         @arg @ref LL_ADC_CHANNEL_2
01209   *         @arg @ref LL_ADC_CHANNEL_3
01210   *         @arg @ref LL_ADC_CHANNEL_4
01211   *         @arg @ref LL_ADC_CHANNEL_5
01212   *         @arg @ref LL_ADC_CHANNEL_6
01213   *         @arg @ref LL_ADC_CHANNEL_7
01214   *         @arg @ref LL_ADC_CHANNEL_8
01215   *         @arg @ref LL_ADC_CHANNEL_9
01216   *         @arg @ref LL_ADC_CHANNEL_10
01217   *         @arg @ref LL_ADC_CHANNEL_11
01218   *         @arg @ref LL_ADC_CHANNEL_12
01219   *         @arg @ref LL_ADC_CHANNEL_13
01220   *         @arg @ref LL_ADC_CHANNEL_14
01221   *         @arg @ref LL_ADC_CHANNEL_15         (1)
01222   *         @arg @ref LL_ADC_CHANNEL_16         (1)
01223   *         @arg @ref LL_ADC_CHANNEL_17         (1)
01224   *         @arg @ref LL_ADC_CHANNEL_18
01225   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (2)
01226   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
01227   *         @arg @ref LL_ADC_CHANNEL_VBAT       (2)
01228   *
01229   *         (1) On STM32G0, parameter can be set in ADC group sequencer
01230   *             only if sequencer is set in mode "not fully configurable",
01231   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
01232   *         (2) For ADC channel read back from ADC register,
01233   *             comparison with internal channel parameter to be done
01234   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01235   * @param  __GROUP__ This parameter can be one of the following values:
01236   *         @arg @ref LL_ADC_GROUP_REGULAR
01237   * @retval Returned value can be one of the following values:
01238   *         @arg @ref LL_ADC_AWD_DISABLE
01239   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
01240   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
01241   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
01242   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
01243   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
01244   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
01245   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
01246   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
01247   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
01248   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
01249   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
01250   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
01251   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
01252   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
01253   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
01254   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
01255   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
01256   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
01257   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
01258   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
01259   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
01260   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
01261   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG
01262   */
01263 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
01264   (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
01265
01266 /**
01267   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
01268   *         or low in function of ADC resolution, when ADC resolution is
01269   *         different of 12 bits.
01270   * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
01271   *         or @ref LL_ADC_SetAnalogWDThresholds().
01272   *         Example, with a ADC resolution of 8 bits, to set the value of
01273   *         analog watchdog threshold high (on 8 bits):
01274   *           LL_ADC_SetAnalogWDThresholds
01275   *            (< ADCx param >,
01276   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
01277   *            );
01278   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01279   *         @arg @ref LL_ADC_RESOLUTION_12B
01280   *         @arg @ref LL_ADC_RESOLUTION_10B
01281   *         @arg @ref LL_ADC_RESOLUTION_8B
01282   *         @arg @ref LL_ADC_RESOLUTION_6B
01283   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
01284   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01285   */
01286 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
01287   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
01288
01289 /**
01290   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
01291   *         or low in function of ADC resolution, when ADC resolution is
01292   *         different of 12 bits.
01293   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01294   *         Example, with a ADC resolution of 8 bits, to get the value of
01295   *         analog watchdog threshold high (on 8 bits):
01296   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
01297   *            (LL_ADC_RESOLUTION_8B,
01298   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
01299   *            );
01300   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01301   *         @arg @ref LL_ADC_RESOLUTION_12B
01302   *         @arg @ref LL_ADC_RESOLUTION_10B
01303   *         @arg @ref LL_ADC_RESOLUTION_8B
01304   *         @arg @ref LL_ADC_RESOLUTION_6B
01305   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
01306   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01307   */
01308 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
01309   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
01310
01311 /**
01312   * @brief  Helper macro to get the ADC analog watchdog threshold high
01313   *         or low from raw value containing both thresholds concatenated.
01314   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01315   *         Example, to get analog watchdog threshold high from the register raw value:
01316   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
01317   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
01318   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
01319   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
01320   * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01321   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01322   */
01323 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
01324   (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
01325
01326 /**
01327   * @brief  Helper macro to select the ADC common instance
01328   *         to which is belonging the selected ADC instance.
01329   * @note   ADC common register instance can be used for:
01330   *         - Set parameters common to several ADC instances
01331   *         - Multimode (for devices with several ADC instances)
01332   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01333   * @param  __ADCx__ ADC instance
01334   * @retval ADC common register instance
01335   */
01336 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01337   (ADC1_COMMON)
01338
01339 /**
01340   * @brief  Helper macro to check if all ADC instances sharing the same
01341   *         ADC common instance are disabled.
01342   * @note   This check is required by functions with setting conditioned to
01343   *         ADC state:
01344   *         All ADC instances of the ADC common group must be disabled.
01345   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01346   * @note   On devices with only 1 ADC common instance, parameter of this macro
01347   *         is useless and can be ignored (parameter kept for compatibility
01348   *         with devices featuring several ADC common instances).
01349   * @param  __ADCXY_COMMON__ ADC common instance
01350   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01351   * @retval Value "0" if all ADC instances sharing the same ADC common instance
01352   *         are disabled.
01353   *         Value "1" if at least one ADC instance sharing the same ADC common instance
01354   *         is enabled.
01355   */
01356 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01357   LL_ADC_IsEnabled(ADC1)
01358
01359 /**
01360   * @brief  Helper macro to define the ADC conversion data full-scale digital
01361   *         value corresponding to the selected ADC resolution.
01362   * @note   ADC conversion data full-scale corresponds to voltage range
01363   *         determined by analog voltage references Vref+ and Vref-
01364   *         (refer to reference manual).
01365   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01366   *         @arg @ref LL_ADC_RESOLUTION_12B
01367   *         @arg @ref LL_ADC_RESOLUTION_10B
01368   *         @arg @ref LL_ADC_RESOLUTION_8B
01369   *         @arg @ref LL_ADC_RESOLUTION_6B
01370   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
01371   */
01372 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
01373   (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
01374
01375 /**
01376   * @brief  Helper macro to convert the ADC conversion data from
01377   *         a resolution to another resolution.
01378   * @param  __DATA__ ADC conversion data to be converted
01379   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
01380   *         This parameter can be one of the following values:
01381   *         @arg @ref LL_ADC_RESOLUTION_12B
01382   *         @arg @ref LL_ADC_RESOLUTION_10B
01383   *         @arg @ref LL_ADC_RESOLUTION_8B
01384   *         @arg @ref LL_ADC_RESOLUTION_6B
01385   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
01386   *         This parameter can be one of the following values:
01387   *         @arg @ref LL_ADC_RESOLUTION_12B
01388   *         @arg @ref LL_ADC_RESOLUTION_10B
01389   *         @arg @ref LL_ADC_RESOLUTION_8B
01390   *         @arg @ref LL_ADC_RESOLUTION_6B
01391   * @retval ADC conversion data to the requested resolution
01392   */
01393 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
01394                                          __ADC_RESOLUTION_CURRENT__,\
01395                                          __ADC_RESOLUTION_TARGET__)          \
01396 (((__DATA__)                                                                 \
01397   << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))  \
01398  >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))     \
01399 )
01400
01401 /**
01402   * @brief  Helper macro to calculate the voltage (unit: mVolt)
01403   *         corresponding to a ADC conversion data (unit: digital value).
01404   * @note   Analog reference voltage (Vref+) must be either known from
01405   *         user board environment or can be calculated using ADC measurement
01406   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01407   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
01408   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
01409   *                       (unit: digital value).
01410   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01411   *         @arg @ref LL_ADC_RESOLUTION_12B
01412   *         @arg @ref LL_ADC_RESOLUTION_10B
01413   *         @arg @ref LL_ADC_RESOLUTION_8B
01414   *         @arg @ref LL_ADC_RESOLUTION_6B
01415   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01416   */
01417 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
01418                                       __ADC_DATA__,\
01419                                       __ADC_RESOLUTION__)                    \
01420 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
01421  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
01422 )
01423
01424 /**
01425   * @brief  Helper macro to calculate analog reference voltage (Vref+)
01426   *         (unit: mVolt) from ADC conversion data of internal voltage
01427   *         reference VrefInt.
01428   * @note   Computation is using VrefInt calibration value
01429   *         stored in system memory for each device during production.
01430   * @note   This voltage depends on user board environment: voltage level
01431   *         connected to pin Vref+.
01432   *         On devices with small package, the pin Vref+ is not present
01433   *         and internally bonded to pin Vdda.
01434   * @note   On this STM32 series, calibration data of internal voltage reference
01435   *         VrefInt corresponds to a resolution of 12 bits,
01436   *         this is the recommended ADC resolution to convert voltage of
01437   *         internal voltage reference VrefInt.
01438   *         Otherwise, this macro performs the processing to scale
01439   *         ADC conversion data to 12 bits.
01440   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
01441   *         of internal voltage reference VrefInt (unit: digital value).
01442   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01443   *         @arg @ref LL_ADC_RESOLUTION_12B
01444   *         @arg @ref LL_ADC_RESOLUTION_10B
01445   *         @arg @ref LL_ADC_RESOLUTION_8B
01446   *         @arg @ref LL_ADC_RESOLUTION_6B
01447   * @retval Analog reference voltage (unit: mV)
01448   */
01449 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
01450                                          __ADC_RESOLUTION__)                 \
01451 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
01452  / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
01453                                     (__ADC_RESOLUTION__),                    \
01454                                     LL_ADC_RESOLUTION_12B)                   \
01455 )
01456
01457 /**
01458   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01459   *         from ADC conversion data of internal temperature sensor.
01460   * @note   Computation is using temperature sensor calibration values
01461   *         stored in system memory for each device during production.
01462   * @note   Calculation formula:
01463   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
01464   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
01465   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
01466   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
01467   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
01468   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
01469   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
01470   *                            TEMP_DEGC_CAL1 (calibrated in factory)
01471   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
01472   *                            TEMP_DEGC_CAL2 (calibrated in factory)
01473   *         Caution: Calculation relevancy under reserve that calibration
01474   *                  parameters are correct (address and data).
01475   *                  To calculate temperature using temperature sensor
01476   *                  datasheet typical values (generic values less, therefore
01477   *                  less accurate than calibrated values),
01478   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
01479   * @note   As calculation input, the analog reference voltage (Vref+) must be
01480   *         defined as it impacts the ADC LSB equivalent voltage.
01481   * @note   Analog reference voltage (Vref+) must be either known from
01482   *         user board environment or can be calculated using ADC measurement
01483   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01484   * @note   On this STM32 series, calibration data of temperature sensor
01485   *         corresponds to a resolution of 12 bits,
01486   *         this is the recommended ADC resolution to convert voltage of
01487   *         temperature sensor.
01488   *         Otherwise, this macro performs the processing to scale
01489   *         ADC conversion data to 12 bits.
01490   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
01491   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
01492   *                                 temperature sensor (unit: digital value).
01493   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
01494   *                                 sensor voltage has been measured.
01495   *         This parameter can be one of the following values:
01496   *         @arg @ref LL_ADC_RESOLUTION_12B
01497   *         @arg @ref LL_ADC_RESOLUTION_10B
01498   *         @arg @ref LL_ADC_RESOLUTION_8B
01499   *         @arg @ref LL_ADC_RESOLUTION_6B
01500   * @retval Temperature (unit: degree Celsius)
01501   *         In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
01502   */
01503 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
01504                                   __TEMPSENSOR_ADC_DATA__,\
01505                                   __ADC_RESOLUTION__)\
01506 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ?        \
01507   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
01508                                                     (__ADC_RESOLUTION__),          \
01509                                                     LL_ADC_RESOLUTION_12B)         \
01510                    * (__VREFANALOG_VOLTAGE__))                                     \
01511                   / TEMPSENSOR_CAL_VREFANALOG)                                     \
01512         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
01513      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
01514     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
01515    ) + TEMPSENSOR_CAL1_TEMP                                                        \
01516   )                                                                                \
01517   :                                                                                \
01518   ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR)                                         \
01519 )
01520
01521 /**
01522   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01523   *         from ADC conversion data of internal temperature sensor.
01524   * @note   Computation is using temperature sensor typical values
01525   *         (refer to device datasheet).
01526   * @note   Calculation formula:
01527   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
01528   *                         / Avg_Slope + CALx_TEMP
01529   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
01530   *                                   (unit: digital value)
01531   *                Avg_Slope        = temperature sensor slope
01532   *                                   (unit: uV/Degree Celsius)
01533   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
01534   *                                   temperature CALx_TEMP (unit: mV)
01535   *         Caution: Calculation relevancy under reserve the temperature sensor
01536   *                  of the current device has characteristics in line with
01537   *                  datasheet typical values.
01538   *                  If temperature sensor calibration values are available on
01539   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
01540   *                  temperature calculation will be more accurate using
01541   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
01542   * @note   As calculation input, the analog reference voltage (Vref+) must be
01543   *         defined as it impacts the ADC LSB equivalent voltage.
01544   * @note   Analog reference voltage (Vref+) must be either known from
01545   *         user board environment or can be calculated using ADC measurement
01546   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01547   * @note   ADC measurement data must correspond to a resolution of 12 bits
01548   *         (full scale digital value 4095). If not the case, the data must be
01549   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01550   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
01551   *                                       On STM32G0, refer to device datasheet parameter "Avg_Slope".
01552   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
01553   *                                       On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
01554   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
01555   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
01556   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
01557   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
01558   *         This parameter can be one of the following values:
01559   *         @arg @ref LL_ADC_RESOLUTION_12B
01560   *         @arg @ref LL_ADC_RESOLUTION_10B
01561   *         @arg @ref LL_ADC_RESOLUTION_8B
01562   *         @arg @ref LL_ADC_RESOLUTION_6B
01563   * @retval Temperature (unit: degree Celsius)
01564   */
01565 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
01566                                              __TEMPSENSOR_TYP_CALX_V__,\
01567                                              __TEMPSENSOR_CALX_TEMP__,\
01568                                              __VREFANALOG_VOLTAGE__,\
01569                                              __TEMPSENSOR_ADC_DATA__,\
01570                                              __ADC_RESOLUTION__)            \
01571 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
01572                / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
01573               * 1000UL)                                                     \
01574     -                                                                       \
01575     (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
01576               * 1000UL)                                                     \
01577    )                                                                        \
01578   ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
01579  ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
01580 )
01581
01582 /**
01583   * @}
01584   */
01585
01586 /**
01587   * @}
01588   */
01589
01590
01591 /* Exported functions --------------------------------------------------------*/
01592 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
01593   * @{
01594   */
01595
01596 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
01597   * @{
01598   */
01599 /* Note: LL ADC functions to set DMA transfer are located into sections of    */
01600 /*       configuration of ADC instance, groups and multimode (if available):  */
01601 /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
01602
01603 /**
01604   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
01605   *         ADC register address from ADC instance and a list of ADC registers
01606   *         intended to be used (most commonly) with DMA transfer.
01607   * @note   These ADC registers are data registers:
01608   *         when ADC conversion data is available in ADC data registers,
01609   *         ADC generates a DMA transfer request.
01610   * @note   This macro is intended to be used with LL DMA driver, refer to
01611   *         function "LL_DMA_ConfigAddresses()".
01612   *         Example:
01613   *           LL_DMA_ConfigAddresses(DMA1,
01614   *                                  LL_DMA_CHANNEL_1,
01615   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
01616   *                                  (uint32_t)&< array or variable >,
01617   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
01618   * @note   For devices with several ADC: in multimode, some devices
01619   *         use a different data register outside of ADC instance scope
01620   *         (common data register). This macro manages this register difference,
01621   *         only ADC instance has to be set as parameter.
01622   * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr
01623   * @param  ADCx ADC instance
01624   * @param  Register This parameter can be one of the following values:
01625   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
01626   * @retval ADC register address
01627   */
01628 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
01629 {
01630   /* Prevent unused argument(s) compilation warning */
01631   (void)(Register);
01632
01633   /* Retrieve address of register DR */
01634   return (uint32_t) &(ADCx->DR);
01635 }
01636
01637 /**
01638   * @}
01639   */
01640
01641 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
01642   * @{
01643   */
01644
01645 /**
01646   * @brief  Set parameter common to several ADC: Clock source and prescaler.
01647   * @note   On this STM32 series, setting of this feature is conditioned to
01648   *         ADC state:
01649   *         All ADC instances of the ADC common group must be disabled.
01650   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
01651   *         ADC instance or by using helper macro helper macro
01652   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
01653   * @rmtoll CCR      PRESC          LL_ADC_SetCommonClock
01654   * @param  ADCxy_COMMON ADC common instance
01655   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01656   * @param  CommonClock This parameter can be one of the following values:
01657   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1   (1)
01658   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2   (1)
01659   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4   (1)
01660   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6   (1)
01661   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8   (1)
01662   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10  (1)
01663   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12  (1)
01664   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16  (1)
01665   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32  (1)
01666   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64  (1)
01667   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
01668   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
01669   *
01670   *         (1) ADC common clock asynchronous prescaler is applied to
01671   *             each ADC instance if the corresponding ADC instance clock
01672   *             is set to clock source asynchronous.
01673   *             (refer to function @ref LL_ADC_SetClock() ).
01674   * @retval None
01675   */
01676 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
01677 {
01678   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
01679 }
01680
01681 /**
01682   * @brief  Get parameter common to several ADC: Clock source and prescaler.
01683   * @rmtoll CCR      PRESC          LL_ADC_GetCommonClock
01684   * @param  ADCxy_COMMON ADC common instance
01685   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01686   * @retval Returned value can be one of the following values:
01687   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1   (1)
01688   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2   (1)
01689   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4   (1)
01690   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6   (1)
01691   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8   (1)
01692   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10  (1)
01693   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12  (1)
01694   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16  (1)
01695   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32  (1)
01696   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64  (1)
01697   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
01698   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
01699   *
01700   *         (1) ADC common clock asynchronous prescaler is applied to
01701   *             each ADC instance if the corresponding ADC instance clock
01702   *             is set to clock source asynchronous.
01703   *             (refer to function @ref LL_ADC_SetClock() ).
01704   */
01705 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
01706 {
01707   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
01708 }
01709
01710 /**
01711   * @brief  Legacy feature, useless on STM32G0 (ADC common clock low frequency
01712             mode is automatically managed by ADC peripheral on STM32G0).
01713             Function kept for legacy purpose.
01714   * @note   On this STM32 series, setting of this feature is conditioned to
01715   *         ADC state:
01716   *         ADC must be disabled or enabled without conversion on going
01717   *         on group regular.
01718   * @rmtoll CCR      LFMEN          LL_ADC_SetCommonFrequencyMode
01719   * @param  ADCxy_COMMON ADC common instance
01720   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01721   * @param  CommonFrequencyMode This parameter can be one of the following values:
01722   *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
01723   *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
01724   * @retval None
01725   */
01726 __STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonFrequencyMode)
01727 {
01728   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, CommonFrequencyMode);
01729 }
01730
01731 /**
01732   * @brief  Legacy feature, useless on STM32G0 (ADC common clock low frequency
01733             mode is automatically managed by ADC peripheral on STM32G0).
01734             Function kept for legacy purpose.
01735   * @rmtoll CCR      LFMEN          LL_ADC_GetCommonFrequencyMode
01736   * @param  ADCxy_COMMON ADC common instance
01737   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01738   * @retval Returned value can be one of the following values:
01739   *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
01740   *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
01741   */
01742 __STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON)
01743 {
01744   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN));
01745 }
01746
01747 /**
01748   * @brief  Set parameter common to several ADC: measurement path to
01749   *         internal channels (VrefInt, temperature sensor, ...).
01750   *         Configure all paths (overwrite current configuration).
01751   * @note   One or several values can be selected.
01752   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
01753   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
01754   *         The values not selected are removed from configuration.
01755   * @note   Stabilization time of measurement path to internal channel:
01756   *         After enabling internal paths, before starting ADC conversion,
01757   *         a delay is required for internal voltage reference and
01758   *         temperature sensor stabilization time.
01759   *         Refer to device datasheet.
01760   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
01761   *         Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
01762   *         @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
01763   * @note   ADC internal channel sampling time constraint:
01764   *         For ADC conversion of internal channels,
01765   *         a sampling time minimum value is required.
01766   *         Refer to device datasheet.
01767   * @note   On this STM32 series, setting of this feature is conditioned to
01768   *         ADC state:
01769   *         All ADC instances of the ADC common group must be disabled.
01770   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
01771   *         ADC instance or by using helper macro helper macro
01772   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
01773   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
01774   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
01775   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
01776   * @param  ADCxy_COMMON ADC common instance
01777   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01778   * @param  PathInternal This parameter can be a combination of the following values:
01779   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
01780   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
01781   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
01782   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
01783   * @retval None
01784   */
01785 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
01786 {
01787   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
01788 }
01789
01790 /**
01791   * @brief  Set parameter common to several ADC: measurement path to
01792   *         internal channels (VrefInt, temperature sensor, ...).
01793   *         Add paths to the current configuration.
01794   * @note   One or several values can be selected.
01795   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
01796   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
01797   * @note   Stabilization time of measurement path to internal channel:
01798   *         After enabling internal paths, before starting ADC conversion,
01799   *         a delay is required for internal voltage reference and
01800   *         temperature sensor stabilization time.
01801   *         Refer to device datasheet.
01802   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
01803   *         Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
01804   *         @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
01805   * @note   ADC internal channel sampling time constraint:
01806   *         For ADC conversion of internal channels,
01807   *         a sampling time minimum value is required.
01808   *         Refer to device datasheet.
01809   * @note   On this STM32 series, setting of this feature is conditioned to
01810   *         ADC state:
01811   *         All ADC instances of the ADC common group must be disabled.
01812   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
01813   *         ADC instance or by using helper macro helper macro
01814   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
01815   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
01816   *         CCR      TSEN           LL_ADC_SetCommonPathInternalChAdd\n
01817   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalChAdd
01818   * @param  ADCxy_COMMON ADC common instance
01819   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01820   * @param  PathInternal This parameter can be a combination of the following values:
01821   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
01822   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
01823   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
01824   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
01825   * @retval None
01826   */
01827 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
01828 {
01829   SET_BIT(ADCxy_COMMON->CCR, PathInternal);
01830 }
01831
01832 /**
01833   * @brief  Set parameter common to several ADC: measurement path to
01834   *         internal channels (VrefInt, temperature sensor, ...).
01835   *         Remove paths to the current configuration.
01836   * @note   One or several values can be selected.
01837   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
01838   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
01839   * @note   On this STM32 series, setting of this feature is conditioned to
01840   *         ADC state:
01841   *         All ADC instances of the ADC common group must be disabled.
01842   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
01843   *         ADC instance or by using helper macro helper macro
01844   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
01845   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
01846   *         CCR      TSEN           LL_ADC_SetCommonPathInternalChRem\n
01847   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalChRem
01848   * @param  ADCxy_COMMON ADC common instance
01849   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01850   * @param  PathInternal This parameter can be a combination of the following values:
01851   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
01852   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
01853   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
01854   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
01855   * @retval None
01856   */
01857 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
01858 {
01859   CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
01860 }
01861
01862 /**
01863   * @brief  Get parameter common to several ADC: measurement path to internal
01864   *         channels (VrefInt, temperature sensor, ...).
01865   * @note   One or several values can be selected.
01866   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
01867   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
01868   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
01869   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
01870   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
01871   * @param  ADCxy_COMMON ADC common instance
01872   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01873   * @retval Returned value can be a combination of the following values:
01874   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
01875   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
01876   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
01877   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
01878   */
01879 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
01880 {
01881   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
01882 }
01883
01884 /**
01885   * @}
01886   */
01887
01888 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
01889   * @{
01890   */
01891
01892 /**
01893   * @brief  Set ADC instance clock source and prescaler.
01894   * @note   On this STM32 series, setting of this feature is conditioned to
01895   *         ADC state:
01896   *         ADC must be disabled.
01897   * @rmtoll CFGR2    CKMODE         LL_ADC_SetClock
01898   * @param  ADCx ADC instance
01899   * @param  ClockSource This parameter can be one of the following values:
01900   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
01901   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
01902   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
01903   *         @arg @ref LL_ADC_CLOCK_ASYNC (1)
01904   *
01905   *         (1) Asynchronous clock prescaler can be configured using
01906   *             function @ref LL_ADC_SetCommonClock().\n
01907   *         (2) Caution: This parameter has some clock ratio constraints:
01908   *             This configuration must be enabled only if PCLK has a 50%
01909   *             duty clock cycle (APB prescaler configured inside the RCC
01910   *             must be bypassed and the system clock must by 50% duty
01911   *             cycle).
01912   *             Refer to reference manual.
01913   * @retval None
01914   */
01915 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
01916 {
01917   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
01918 }
01919
01920 /**
01921   * @brief  Get ADC instance clock source and prescaler.
01922   * @rmtoll CFGR2    CKMODE         LL_ADC_GetClock
01923   * @param  ADCx ADC instance
01924   * @retval Returned value can be one of the following values:
01925   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
01926   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
01927   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
01928   *         @arg @ref LL_ADC_CLOCK_ASYNC (1)
01929   *
01930   *         (1) Asynchronous clock prescaler can be retrieved using
01931   *             function @ref LL_ADC_GetCommonClock().\n
01932   *         (2) Caution: This parameter has some clock ratio constraints:
01933   *             This configuration must be enabled only if PCLK has a 50%
01934   *             duty clock cycle (APB prescaler configured inside the RCC
01935   *             must be bypassed and the system clock must by 50% duty
01936   *             cycle).
01937   *             Refer to reference manual.
01938   */
01939 __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
01940 {
01941   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
01942 }
01943
01944 /**
01945   * @brief  Set ADC calibration factor in the mode single-ended
01946   *         or differential (for devices with differential mode available).
01947   * @note   This function is intended to set calibration parameters
01948   *         without having to perform a new calibration using
01949   *         @ref LL_ADC_StartCalibration().
01950   * @note   On this STM32 series, setting of this feature is conditioned to
01951   *         ADC state:
01952   *         ADC must be enabled, without calibration on going, without conversion
01953   *         on going on group regular.
01954   * @rmtoll CALFACT  CALFACT        LL_ADC_SetCalibrationFactor
01955   * @param  ADCx ADC instance
01956   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
01957   * @retval None
01958   */
01959 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
01960 {
01961   MODIFY_REG(ADCx->CALFACT,
01962              ADC_CALFACT_CALFACT,
01963              CalibrationFactor);
01964 }
01965
01966 /**
01967   * @brief  Get ADC calibration factor in the mode single-ended
01968   *         or differential (for devices with differential mode available).
01969   * @note   Calibration factors are set by hardware after performing
01970   *         a calibration run using function @ref LL_ADC_StartCalibration().
01971   * @rmtoll CALFACT  CALFACT        LL_ADC_GetCalibrationFactor
01972   * @param  ADCx ADC instance
01973   * @retval Value between Min_Data=0x00 and Max_Data=0x7F
01974   */
01975 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
01976 {
01977   return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
01978 }
01979
01980 /**
01981   * @brief  Set ADC resolution.
01982   *         Refer to reference manual for alignments formats
01983   *         dependencies to ADC resolutions.
01984   * @note   On this STM32 series, setting of this feature is conditioned to
01985   *         ADC state:
01986   *         ADC must be disabled.
01987   * @rmtoll CFGR1    RES            LL_ADC_SetResolution
01988   * @param  ADCx ADC instance
01989   * @param  Resolution This parameter can be one of the following values:
01990   *         @arg @ref LL_ADC_RESOLUTION_12B
01991   *         @arg @ref LL_ADC_RESOLUTION_10B
01992   *         @arg @ref LL_ADC_RESOLUTION_8B
01993   *         @arg @ref LL_ADC_RESOLUTION_6B
01994   * @retval None
01995   */
01996 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
01997 {
01998   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
01999 }
02000
02001 /**
02002   * @brief  Get ADC resolution.
02003   *         Refer to reference manual for alignments formats
02004   *         dependencies to ADC resolutions.
02005   * @rmtoll CFGR1    RES            LL_ADC_GetResolution
02006   * @param  ADCx ADC instance
02007   * @retval Returned value can be one of the following values:
02008   *         @arg @ref LL_ADC_RESOLUTION_12B
02009   *         @arg @ref LL_ADC_RESOLUTION_10B
02010   *         @arg @ref LL_ADC_RESOLUTION_8B
02011   *         @arg @ref LL_ADC_RESOLUTION_6B
02012   */
02013 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
02014 {
02015   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
02016 }
02017
02018 /**
02019   * @brief  Set ADC conversion data alignment.
02020   * @note   Refer to reference manual for alignments formats
02021   *         dependencies to ADC resolutions.
02022   * @note   On this STM32 series, setting of this feature is conditioned to
02023   *         ADC state:
02024   *         ADC must be disabled.
02025   * @rmtoll CFGR1    ALIGN          LL_ADC_SetDataAlignment
02026   * @param  ADCx ADC instance
02027   * @param  DataAlignment This parameter can be one of the following values:
02028   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02029   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02030   * @retval None
02031   */
02032 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
02033 {
02034   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
02035 }
02036
02037 /**
02038   * @brief  Get ADC conversion data alignment.
02039   * @note   Refer to reference manual for alignments formats
02040   *         dependencies to ADC resolutions.
02041   * @rmtoll CFGR1    ALIGN          LL_ADC_GetDataAlignment
02042   * @param  ADCx ADC instance
02043   * @retval Returned value can be one of the following values:
02044   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02045   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02046   */
02047 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
02048 {
02049   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
02050 }
02051
02052 /**
02053   * @brief  Set ADC low power mode.
02054   * @note   Description of ADC low power modes:
02055   *         - ADC low power mode "auto wait": Dynamic low power mode,
02056   *           ADC conversions occurrences are limited to the minimum necessary
02057   *           in order to reduce power consumption.
02058   *           New ADC conversion starts only when the previous
02059   *           unitary conversion data (for ADC group regular)
02060   *           has been retrieved by user software.
02061   *           In the meantime, ADC remains idle: does not performs any
02062   *           other conversion.
02063   *           This mode allows to automatically adapt the ADC conversions
02064   *           triggers to the speed of the software that reads the data.
02065   *           Moreover, this avoids risk of overrun for low frequency
02066   *           applications.
02067   *           How to use this low power mode:
02068   *           - It is not recommended to use with interruption or DMA
02069   *             since these modes have to clear immediately the EOC flag
02070   *             (by CPU to free the IRQ pending event or by DMA).
02071   *             Auto wait will work but fort a very short time, discarding
02072   *             its intended benefit (except specific case of high load of CPU
02073   *             or DMA transfers which can justify usage of auto wait).
02074   *           - Do use with polling: 1. Start conversion,
02075   *             2. Later on, when conversion data is needed: poll for end of
02076   *             conversion  to ensure that conversion is completed and
02077   *             retrieve ADC conversion data. This will trig another
02078   *             ADC conversion start.
02079   *         - ADC low power mode "auto power-off" (feature available on
02080   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
02081   *           the ADC automatically powers-off after a conversion and
02082   *           automatically wakes up when a new conversion is triggered
02083   *           (with startup time between trigger and start of sampling).
02084   *           This feature can be combined with low power mode "auto wait".
02085   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02086   *         is corresponding to previous ADC conversion start, independently
02087   *         of delay during which ADC was idle.
02088   *         Therefore, the ADC conversion data may be outdated: does not
02089   *         correspond to the current voltage level on the selected
02090   *         ADC channel.
02091   * @note   On this STM32 series, setting of this feature is conditioned to
02092   *         ADC state:
02093   *         ADC must be disabled.
02094   * @rmtoll CFGR1    WAIT           LL_ADC_SetLowPowerMode\n
02095   *         CFGR1    AUTOFF         LL_ADC_SetLowPowerMode
02096   * @param  ADCx ADC instance
02097   * @param  LowPowerMode This parameter can be one of the following values:
02098   *         @arg @ref LL_ADC_LP_MODE_NONE
02099   *         @arg @ref LL_ADC_LP_AUTOWAIT
02100   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF
02101   *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
02102   * @retval None
02103   */
02104 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
02105 {
02106   MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
02107 }
02108
02109 /**
02110   * @brief  Get ADC low power mode:
02111   * @note   Description of ADC low power modes:
02112   *         - ADC low power mode "auto wait": Dynamic low power mode,
02113   *           ADC conversions occurrences are limited to the minimum necessary
02114   *           in order to reduce power consumption.
02115   *           New ADC conversion starts only when the previous
02116   *           unitary conversion data (for ADC group regular)
02117   *           has been retrieved by user software.
02118   *           In the meantime, ADC remains idle: does not performs any
02119   *           other conversion.
02120   *           This mode allows to automatically adapt the ADC conversions
02121   *           triggers to the speed of the software that reads the data.
02122   *           Moreover, this avoids risk of overrun for low frequency
02123   *           applications.
02124   *           How to use this low power mode:
02125   *           - It is not recommended to use with interruption or DMA
02126   *             since these modes have to clear immediately the EOC flag
02127   *             (by CPU to free the IRQ pending event or by DMA).
02128   *             Auto wait will work but fort a very short time, discarding
02129   *             its intended benefit (except specific case of high load of CPU
02130   *             or DMA transfers which can justify usage of auto wait).
02131   *           - Do use with polling: 1. Start conversion,
02132   *             2. Later on, when conversion data is needed: poll for end of
02133   *             conversion  to ensure that conversion is completed and
02134   *             retrieve ADC conversion data. This will trig another
02135   *             ADC conversion start.
02136   *         - ADC low power mode "auto power-off" (feature available on
02137   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
02138   *           the ADC automatically powers-off after a conversion and
02139   *           automatically wakes up when a new conversion is triggered
02140   *           (with startup time between trigger and start of sampling).
02141   *           This feature can be combined with low power mode "auto wait".
02142   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02143   *         is corresponding to previous ADC conversion start, independently
02144   *         of delay during which ADC was idle.
02145   *         Therefore, the ADC conversion data may be outdated: does not
02146   *         correspond to the current voltage level on the selected
02147   *         ADC channel.
02148   * @rmtoll CFGR1    WAIT           LL_ADC_GetLowPowerMode\n
02149   *         CFGR1    AUTOFF         LL_ADC_GetLowPowerMode
02150   * @param  ADCx ADC instance
02151   * @retval Returned value can be one of the following values:
02152   *         @arg @ref LL_ADC_LP_MODE_NONE
02153   *         @arg @ref LL_ADC_LP_AUTOWAIT
02154   *         @arg @ref LL_ADC_LP_AUTOPOWEROFF
02155   *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
02156   */
02157 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
02158 {
02159   return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
02160 }
02161
02162 /**
02163   * @brief  Set ADC trigger frequency mode.
02164   * @note   ADC trigger frequency mode must be set to low frequency when
02165   *         a duration is exceeded before ADC conversion start trigger event
02166   *         (between ADC enable and ADC conversion start trigger event
02167   *         or between two ADC conversion start trigger event).
02168   *         Duration value: Refer to device datasheet, parameter "tIdle".
02169   * @note   When ADC trigger frequency mode is set to low frequency,
02170   *         some rearm cycles are inserted before performing ADC conversion
02171   *         start, inducing a delay of 2 ADC clock cycles.
02172   * @note   Usage of ADC trigger frequency mode with ADC low power mode:
02173   *         - Low power mode auto wait: Only the first ADC conversion
02174   *           start trigger inserts the rearm delay.
02175   *         - Low power mode auto power-off: ADC trigger frequency mode
02176   *           is discarded.
02177   * @note   On this STM32 series, setting of this feature is conditioned to
02178   *         ADC state:
02179   *         ADC must be disabled.
02180   * @rmtoll CFGR2    LFTRIG         LL_ADC_SetTriggerFrequencyMode
02181   * @param  ADCx ADC instance
02182   * @param  TriggerFrequencyMode This parameter can be one of the following values:
02183   *         @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
02184   *         @arg @ref LL_ADC_TRIGGER_FREQ_LOW
02185   * @retval None
02186   */
02187 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
02188 {
02189   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
02190 }
02191
02192 /**
02193   * @brief  Get ADC trigger frequency mode.
02194   * @rmtoll CFGR2    LFTRIG         LL_ADC_GetTriggerFrequencyMode
02195   * @param  ADCx ADC instance
02196   * @retval Returned value can be one of the following values:
02197   *         @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
02198   *         @arg @ref LL_ADC_TRIGGER_FREQ_LOW
02199   */
02200 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx)
02201 {
02202   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
02203 }
02204
02205 /**
02206   * @brief  Set sampling time common to a group of channels.
02207   * @note   Unit: ADC clock cycles.
02208   * @note   On this STM32 series, sampling time scope is on ADC instance:
02209   *         Sampling time common to all channels.
02210   *         (on some other STM32 families, sampling time is channel wise)
02211   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
02212   *         converted:
02213   *         sampling time constraints must be respected (sampling time can be
02214   *         adjusted in function of ADC clock frequency and sampling time
02215   *         setting).
02216   *         Refer to device datasheet for timings values (parameters TS_vrefint,
02217   *         TS_temp, ...).
02218   * @note   Conversion time is the addition of sampling time and processing time.
02219   *         On this STM32 series, ADC processing time is:
02220   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
02221   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
02222   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
02223   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
02224   * @note   In case of ADC conversion of internal channel (VrefInt,
02225   *         temperature sensor, ...), a sampling time minimum value
02226   *         is required.
02227   *         Refer to device datasheet.
02228   * @note   On this STM32 series, setting of this feature is conditioned to
02229   *         ADC state:
02230   *         ADC must be disabled or enabled without conversion on going
02231   *         on group regular.
02232   * @rmtoll SMPR     SMP1           LL_ADC_SetSamplingTimeCommonChannels\n
02233   * @rmtoll SMPR     SMP2           LL_ADC_SetSamplingTimeCommonChannels
02234   * @param  ADCx ADC instance
02235   * @param  SamplingTimeY This parameter can be one of the following values:
02236   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
02237   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
02238   * @param  SamplingTime This parameter can be one of the following values:
02239   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
02240   *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
02241   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
02242   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
02243   *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
02244   *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
02245   *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
02246   *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
02247   * @retval None
02248   */
02249 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
02250                                                           uint32_t SamplingTime)
02251 {
02252   MODIFY_REG(ADCx->SMPR,
02253              ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
02254              SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
02255 }
02256
02257 /**
02258   * @brief  Get sampling time common to a group of channels.
02259   * @note   Unit: ADC clock cycles.
02260   * @note   On this STM32 series, sampling time scope is on ADC instance:
02261   *         Sampling time common to all channels.
02262   *         (on some other STM32 families, sampling time is channel wise)
02263   * @note   Conversion time is the addition of sampling time and processing time.
02264   *         Refer to reference manual for ADC processing time of
02265   *         this STM32 series.
02266   * @rmtoll SMPR     SMP1           LL_ADC_GetSamplingTimeCommonChannels\n
02267   * @rmtoll SMPR     SMP2           LL_ADC_GetSamplingTimeCommonChannels
02268   * @param  ADCx ADC instance
02269   * @param  SamplingTimeY This parameter can be one of the following values:
02270   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
02271   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
02272   * @retval Returned value can be one of the following values:
02273   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
02274   *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
02275   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
02276   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
02277   *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
02278   *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
02279   *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
02280   *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
02281   */
02282 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
02283 {
02284   return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
02285                     >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
02286 }
02287
02288 /**
02289   * @}
02290   */
02291
02292 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
02293   * @{
02294   */
02295
02296 /**
02297   * @brief  Set ADC group regular conversion trigger source:
02298   *         internal (SW start) or from external peripheral (timer event,
02299   *         external interrupt line).
02300   * @note   On this STM32 series, setting trigger source to external trigger
02301   *         also set trigger polarity to rising edge
02302   *         (default setting for compatibility with some ADC on other
02303   *         STM32 families having this setting set by HW default value).
02304   *         In case of need to modify trigger edge, use
02305   *         function @ref LL_ADC_REG_SetTriggerEdge().
02306   * @note   On this STM32 series, ADC trigger frequency mode must be set
02307   *         in function of frequency of ADC group regular conversion trigger.
02308   *         Refer to description of function
02309   *         @ref LL_ADC_SetTriggerFrequencyMode().
02310   * @note   Availability of parameters of trigger sources from timer
02311   *         depends on timers availability on the selected device.
02312   * @note   On this STM32 series, setting of this feature is conditioned to
02313   *         ADC state:
02314   *         ADC must be disabled.
02315   * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_SetTriggerSource\n
02316   *         CFGR1    EXTEN          LL_ADC_REG_SetTriggerSource
02317   * @param  ADCx ADC instance
02318   * @param  TriggerSource This parameter can be one of the following values:
02319   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
02320   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
02321   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
02322   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO   (1)
02323   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
02324   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO   (1)
02325   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO  (1)
02326   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
02327   *
02328   *         (1) On STM32G0, parameter not available on all devices
02329   * @retval None
02330   */
02331 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
02332 {
02333   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
02334 }
02335
02336 /**
02337   * @brief  Get ADC group regular conversion trigger source:
02338   *         internal (SW start) or from external peripheral (timer event,
02339   *         external interrupt line).
02340   * @note   To determine whether group regular trigger source is
02341   *         internal (SW start) or external, without detail
02342   *         of which peripheral is selected as external trigger,
02343   *         (equivalent to
02344   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
02345   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
02346   * @note   Availability of parameters of trigger sources from timer
02347   *         depends on timers availability on the selected device.
02348   * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_GetTriggerSource\n
02349   *         CFGR1    EXTEN          LL_ADC_REG_GetTriggerSource
02350   * @param  ADCx ADC instance
02351   * @retval Returned value can be one of the following values:
02352   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
02353   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
02354   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
02355   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO   (1)
02356   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
02357   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO   (1)
02358   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO  (1)
02359   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
02360   *
02361   *         (1) On STM32G0, parameter not available on all devices
02362   */
02363 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
02364 {
02365   __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
02366
02367   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
02368   /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}.                           */
02369   uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
02370
02371   /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL       */
02372   /* to match with triggers literals definition.                              */
02373   return ((trigger_source
02374            & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
02375           | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
02376          );
02377 }
02378
02379 /**
02380   * @brief  Get ADC group regular conversion trigger source internal (SW start)
02381   *         or external.
02382   * @note   In case of group regular trigger source set to external trigger,
02383   *         to determine which peripheral is selected as external trigger,
02384   *         use function @ref LL_ADC_REG_GetTriggerSource().
02385   * @rmtoll CFGR1    EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
02386   * @param  ADCx ADC instance
02387   * @retval Value "0" if trigger source external trigger
02388   *         Value "1" if trigger source SW start.
02389   */
02390 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
02391 {
02392   return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
02393 }
02394
02395 /**
02396   * @brief  Set ADC group regular conversion trigger polarity.
02397   * @note   Applicable only for trigger source set to external trigger.
02398   * @note   On this STM32 series, setting of this feature is conditioned to
02399   *         ADC state:
02400   *         ADC must be disabled.
02401   * @rmtoll CFGR1    EXTEN          LL_ADC_REG_SetTriggerEdge
02402   * @param  ADCx ADC instance
02403   * @param  ExternalTriggerEdge This parameter can be one of the following values:
02404   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
02405   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
02406   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
02407   * @retval None
02408   */
02409 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
02410 {
02411   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
02412 }
02413
02414 /**
02415   * @brief  Get ADC group regular conversion trigger polarity.
02416   * @note   Applicable only for trigger source set to external trigger.
02417   * @rmtoll CFGR1    EXTEN          LL_ADC_REG_GetTriggerEdge
02418   * @param  ADCx ADC instance
02419   * @retval Returned value can be one of the following values:
02420   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
02421   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
02422   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
02423   */
02424 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
02425 {
02426   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
02427 }
02428
02429 /**
02430   * @brief  Set ADC group regular sequencer configuration flexibility.
02431   * @note   On this STM32 series, ADC group regular sequencer both modes
02432   *         "fully configurable" or "not fully configurable" are
02433   *         available:
02434   *         - sequencer configured to fully configurable:
02435   *           sequencer length and each rank
02436   *           affectation to a channel are configurable.
02437   *           Refer to description of function
02438   *           @ref LL_ADC_REG_SetSequencerLength().
02439   *         - sequencer configured to not fully configurable:
02440   *           sequencer length and each rank affectation to a channel
02441   *           are fixed by channel HW number.
02442   *           Refer to description of function
02443   *           @ref LL_ADC_REG_SetSequencerChannels().
02444   * @note   On this STM32 series, after modifying sequencer (functions
02445   *         @ref LL_ADC_REG_SetSequencerLength()
02446   *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
02447   *         it is mandatory to wait for the assertion of CCRDY flag
02448   *         Otherwise, some actions may be ignored.
02449   *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
02450   *         for more details.
02451   * @note   On this STM32 series, setting of this feature is conditioned to
02452   *         ADC state:
02453   *         ADC must be disabled.
02454   * @rmtoll CFGR     CHSELRMOD      LL_ADC_REG_SetSequencerConfigurable
02455   * @param  ADCx ADC instance
02456   * @param  Configurability This parameter can be one of the following values:
02457   *         @arg @ref LL_ADC_REG_SEQ_FIXED
02458   *         @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
02459   * @retval None
02460   */
02461 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
02462 {
02463   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
02464 }
02465
02466 /**
02467   * @brief  Get ADC group regular sequencer configuration flexibility.
02468   * @note   On this STM32 series, ADC group regular sequencer both modes
02469   *         "fully configurable" or "not fully configurable" are
02470   *         available:
02471   *         - sequencer configured to fully configurable:
02472   *           sequencer length and each rank
02473   *           affectation to a channel are configurable.
02474   *           Refer to description of function
02475   *           @ref LL_ADC_REG_SetSequencerLength().
02476   *         - sequencer configured to not fully configurable:
02477   *           sequencer length and each rank affectation to a channel
02478   *           are fixed by channel HW number.
02479   *           Refer to description of function
02480   *           @ref LL_ADC_REG_SetSequencerChannels().
02481   * @rmtoll CFGR     CHSELRMOD      LL_ADC_REG_SetSequencerConfigurable
02482   * @param  ADCx ADC instance
02483   * @retval Returned value can be one of the following values:
02484   *         @arg @ref LL_ADC_REG_SEQ_FIXED
02485   *         @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
02486   */
02487 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)
02488 {
02489   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
02490 }
02491
02492 /**
02493   * @brief  Set ADC group regular sequencer length and scan direction.
02494   * @note   Description of ADC group regular sequencer features:
02495   *         - For devices with sequencer fully configurable
02496   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
02497   *           sequencer length and each rank affectation to a channel
02498   *           are configurable.
02499   *           This function performs configuration of:
02500   *           - Sequence length: Number of ranks in the scan sequence.
02501   *           - Sequence direction: Unless specified in parameters, sequencer
02502   *             scan direction is forward (from rank 1 to rank n).
02503   *           Sequencer ranks are selected using
02504   *           function "LL_ADC_REG_SetSequencerRanks()".
02505   *         - For devices with sequencer not fully configurable
02506   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
02507   *           sequencer length and each rank affectation to a channel
02508   *           are defined by channel number.
02509   *           This function performs configuration of:
02510   *           - Sequence length: Number of ranks in the scan sequence is
02511   *             defined by number of channels set in the sequence,
02512   *             rank of each channel is fixed by channel HW number.
02513   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
02514   *           - Sequence direction: Unless specified in parameters, sequencer
02515   *             scan direction is forward (from lowest channel number to
02516   *             highest channel number).
02517   *           Sequencer ranks are selected using
02518   *           function "LL_ADC_REG_SetSequencerChannels()".
02519   *           To set scan direction differently, refer to function
02520   *           @ref LL_ADC_REG_SetSequencerScanDirection().
02521   * @note   On this STM32 series, ADC group regular sequencer both modes
02522   *         "fully configurable" or "not fully configurable"
02523   *         are available, they can be chosen using
02524   *         function @ref LL_ADC_REG_SetSequencerConfigurable().
02525   * @note   On this STM32 series, after modifying sequencer (functions
02526   *         @ref LL_ADC_REG_SetSequencerLength()
02527   *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
02528   *         it is mandatory to wait for the assertion of CCRDY flag
02529   *         using @ref LL_ADC_IsActiveFlag_CCRDY().
02530   *         Otherwise, some actions may be ignored.
02531   *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
02532   *         for more details.
02533   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
02534   *         ADC conversion on only 1 channel.
02535   * @note   On this STM32 series, setting of this feature is conditioned to
02536   *         ADC state:
02537   *         ADC must be disabled or enabled without conversion on going
02538   *         on group regular.
02539   * @rmtoll CHSELR   SQ1            LL_ADC_REG_SetSequencerLength\n
02540   *         CHSELR   SQ2            LL_ADC_REG_SetSequencerLength\n
02541   *         CHSELR   SQ3            LL_ADC_REG_SetSequencerLength\n
02542   *         CHSELR   SQ4            LL_ADC_REG_SetSequencerLength\n
02543   *         CHSELR   SQ5            LL_ADC_REG_SetSequencerLength\n
02544   *         CHSELR   SQ6            LL_ADC_REG_SetSequencerLength\n
02545   *         CHSELR   SQ7            LL_ADC_REG_SetSequencerLength\n
02546   *         CHSELR   SQ8            LL_ADC_REG_SetSequencerLength
02547   * @param  ADCx ADC instance
02548   * @param  SequencerNbRanks This parameter can be one of the following values:
02549   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
02550   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
02551   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
02552   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
02553   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
02554   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
02555   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
02556   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
02557   * @retval None
02558   */
02559 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
02560 {
02561   SET_BIT(ADCx->CHSELR, SequencerNbRanks);
02562 }
02563
02564 /**
02565   * @brief  Get ADC group regular sequencer length and scan direction.
02566   * @note   Description of ADC group regular sequencer features:
02567   *         - For devices with sequencer fully configurable
02568   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
02569   *           sequencer length and each rank affectation to a channel
02570   *           are configurable.
02571   *           This function retrieves:
02572   *           - Sequence length: Number of ranks in the scan sequence.
02573   *           - Sequence direction: Unless specified in parameters, sequencer
02574   *             scan direction is forward (from rank 1 to rank n).
02575   *           Sequencer ranks are selected using
02576   *           function "LL_ADC_REG_SetSequencerRanks()".
02577   *         - For devices with sequencer not fully configurable
02578   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
02579   *           sequencer length and each rank affectation to a channel
02580   *           are defined by channel number.
02581   *           This function retrieves:
02582   *           - Sequence length: Number of ranks in the scan sequence is
02583   *             defined by number of channels set in the sequence,
02584   *             rank of each channel is fixed by channel HW number.
02585   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
02586   *           - Sequence direction: Unless specified in parameters, sequencer
02587   *             scan direction is forward (from lowest channel number to
02588   *             highest channel number).
02589   *           Sequencer ranks are selected using
02590   *           function "LL_ADC_REG_SetSequencerChannels()".
02591   *          To set scan direction differently, refer to function
02592   *          @ref LL_ADC_REG_SetSequencerScanDirection().
02593   * @note   On this STM32 series, ADC group regular sequencer both modes
02594   *         "fully configurable" or "not fully configurable"
02595   *         are available, they can be chosen using
02596   *         function @ref LL_ADC_REG_SetSequencerConfigurable().
02597   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
02598   *         ADC conversion on only 1 channel.
02599   * @rmtoll CHSELR   SQ1            LL_ADC_REG_GetSequencerLength\n
02600   *         CHSELR   SQ2            LL_ADC_REG_GetSequencerLength\n
02601   *         CHSELR   SQ3            LL_ADC_REG_GetSequencerLength\n
02602   *         CHSELR   SQ4            LL_ADC_REG_GetSequencerLength\n
02603   *         CHSELR   SQ5            LL_ADC_REG_GetSequencerLength\n
02604   *         CHSELR   SQ6            LL_ADC_REG_GetSequencerLength\n
02605   *         CHSELR   SQ7            LL_ADC_REG_GetSequencerLength\n
02606   *         CHSELR   SQ8            LL_ADC_REG_GetSequencerLength
02607   * @param  ADCx ADC instance
02608   * @retval Returned value can be one of the following values:
02609   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
02610   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
02611   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
02612   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
02613   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
02614   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
02615   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
02616   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
02617   */
02618 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
02619 {
02620   __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
02621   uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
02622   uint32_t rank_index;
02623   uint32_t rank_shifted;
02624
02625   /* Parse register for end of sequence identifier */
02626   /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
02627            (ADC_CHSELR_SQ2), value "4" to length of end of sequence
02628            identifier (0xF) */
02629   for (rank_index = 0U; rank_index <= (28U - 4U); rank_index += 4U)
02630   {
02631     rank_shifted = (uint32_t)(0xF0UL << rank_index);
02632     if ((channels_ranks & rank_shifted) == rank_shifted)
02633     {
02634       sequencer_length = rank_shifted;
02635       break;
02636     }
02637   }
02638
02639   return sequencer_length;
02640 }
02641
02642 /**
02643   * @brief  Set ADC group regular sequencer scan direction.
02644   * @note   On this STM32 series, parameter relevant only is sequencer is set
02645   *         to mode not fully configurable,
02646   *         refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
02647   * @note   On some other STM32 series, this setting is not available and
02648   *         the default scan direction is forward.
02649   * @note   On this STM32 series, after modifying sequencer (functions
02650   *         @ref LL_ADC_REG_SetSequencerLength()
02651   *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
02652   *         it is mandatory to wait for the assertion of CCRDY flag
02653   *         using @ref LL_ADC_IsActiveFlag_CCRDY().
02654   *         Otherwise, some actions may be ignored.
02655   *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
02656   *         for more details.
02657   * @note   On this STM32 series, setting of this feature is conditioned to
02658   *         ADC state:
02659   *         ADC must be disabled.
02660   * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_SetSequencerScanDirection
02661   * @param  ADCx ADC instance
02662   * @param  ScanDirection This parameter can be one of the following values:
02663   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
02664   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
02665   * @retval None
02666   */
02667 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
02668 {
02669   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
02670 }
02671
02672 /**
02673   * @brief  Get ADC group regular sequencer scan direction.
02674   * @note   On this STM32 series, parameter relevant only is sequencer is set
02675   *         to mode not fully configurable,
02676   *         refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
02677   * @note   On some other STM32 families, this setting is not available and
02678   *         the default scan direction is forward.
02679   * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_GetSequencerScanDirection
02680   * @param  ADCx ADC instance
02681   * @retval Returned value can be one of the following values:
02682   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
02683   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
02684   */
02685 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
02686 {
02687   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
02688 }
02689
02690 /**
02691   * @brief  Set ADC group regular sequencer discontinuous mode:
02692   *         sequence subdivided and scan conversions interrupted every selected
02693   *         number of ranks.
02694   * @note   It is not possible to enable both ADC group regular
02695   *         continuous mode and sequencer discontinuous mode.
02696   * @note   On this STM32 series, setting of this feature is conditioned to
02697   *         ADC state:
02698   *         ADC must be disabled.
02699   * @rmtoll CFGR1    DISCEN         LL_ADC_REG_SetSequencerDiscont\n
02700   * @param  ADCx ADC instance
02701   * @param  SeqDiscont This parameter can be one of the following values:
02702   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
02703   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
02704   * @retval None
02705   */
02706 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
02707 {
02708   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
02709 }
02710
02711 /**
02712   * @brief  Get ADC group regular sequencer discontinuous mode:
02713   *         sequence subdivided and scan conversions interrupted every selected
02714   *         number of ranks.
02715   * @rmtoll CFGR1    DISCEN         LL_ADC_REG_GetSequencerDiscont\n
02716   * @param  ADCx ADC instance
02717   * @retval Returned value can be one of the following values:
02718   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
02719   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
02720   */
02721 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
02722 {
02723   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
02724 }
02725
02726 /**
02727   * @brief  Set ADC group regular sequence: channel on the selected
02728   *         scan sequence rank.
02729   * @note   This function performs configuration of:
02730   *         - Channels ordering into each rank of scan sequence:
02731   *           whatever channel can be placed into whatever rank.
02732   * @note   On this STM32 series, ADC group regular sequencer is
02733   *         fully configurable: sequencer length and each rank
02734   *         affectation to a channel are configurable.
02735   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
02736   * @note   Depending on devices and packages, some channels may not be available.
02737   *         Refer to device datasheet for channels availability.
02738   * @note   On this STM32 series, to measure internal channels (VrefInt,
02739   *         TempSensor, ...), measurement paths to internal channels must be
02740   *         enabled separately.
02741   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
02742   * @note   On this STM32 series, after modifying sequencer (functions
02743   *         @ref LL_ADC_REG_SetSequencerLength()
02744   *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
02745   *         it is mandatory to wait for the assertion of CCRDY flag
02746   *         using @ref LL_ADC_IsActiveFlag_CCRDY().
02747   *         Otherwise, some actions may be ignored.
02748   *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
02749   *         for more details.
02750   * @note   On this STM32 series, setting of this feature is conditioned to
02751   *         ADC state:
02752   *         ADC must be disabled or enabled without conversion on going
02753   *         on group regular.
02754   * @rmtoll CHSELR   SQ1            LL_ADC_REG_SetSequencerRanks\n
02755   *         CHSELR   SQ2            LL_ADC_REG_SetSequencerRanks\n
02756   *         CHSELR   SQ3            LL_ADC_REG_SetSequencerRanks\n
02757   *         CHSELR   SQ4            LL_ADC_REG_SetSequencerRanks\n
02758   *         CHSELR   SQ5            LL_ADC_REG_SetSequencerRanks\n
02759   *         CHSELR   SQ6            LL_ADC_REG_SetSequencerRanks\n
02760   *         CHSELR   SQ7            LL_ADC_REG_SetSequencerRanks\n
02761   *         CHSELR   SQ8            LL_ADC_REG_SetSequencerRanks
02762   * @param  ADCx ADC instance
02763   * @param  Rank This parameter can be one of the following values:
02764   *         @arg @ref LL_ADC_REG_RANK_1
02765   *         @arg @ref LL_ADC_REG_RANK_2
02766   *         @arg @ref LL_ADC_REG_RANK_3
02767   *         @arg @ref LL_ADC_REG_RANK_4
02768   *         @arg @ref LL_ADC_REG_RANK_5
02769   *         @arg @ref LL_ADC_REG_RANK_6
02770   *         @arg @ref LL_ADC_REG_RANK_7
02771   *         @arg @ref LL_ADC_REG_RANK_8
02772   * @param  Channel This parameter can be one of the following values:
02773   *         @arg @ref LL_ADC_CHANNEL_0
02774   *         @arg @ref LL_ADC_CHANNEL_1
02775   *         @arg @ref LL_ADC_CHANNEL_2
02776   *         @arg @ref LL_ADC_CHANNEL_3
02777   *         @arg @ref LL_ADC_CHANNEL_4
02778   *         @arg @ref LL_ADC_CHANNEL_5
02779   *         @arg @ref LL_ADC_CHANNEL_6
02780   *         @arg @ref LL_ADC_CHANNEL_7
02781   *         @arg @ref LL_ADC_CHANNEL_8
02782   *         @arg @ref LL_ADC_CHANNEL_9
02783   *         @arg @ref LL_ADC_CHANNEL_10
02784   *         @arg @ref LL_ADC_CHANNEL_11
02785   *         @arg @ref LL_ADC_CHANNEL_12
02786   *         @arg @ref LL_ADC_CHANNEL_13
02787   *         @arg @ref LL_ADC_CHANNEL_14
02788   *         @arg @ref LL_ADC_CHANNEL_15         (1)
02789   *         @arg @ref LL_ADC_CHANNEL_16         (1)
02790   *         @arg @ref LL_ADC_CHANNEL_17         (1)
02791   *         @arg @ref LL_ADC_CHANNEL_18
02792   *         @arg @ref LL_ADC_CHANNEL_VREFINT
02793   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
02794   *         @arg @ref LL_ADC_CHANNEL_VBAT
02795   *
02796   *         (1) On STM32G0, parameter can be set in ADC group sequencer
02797   *             only if sequencer is set in mode "not fully configurable",
02798   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
02799   * @retval None
02800   */
02801 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
02802 {
02803   /* Set bits with content of parameter "Channel" with bits position          */
02804   /* in register depending on parameter "Rank".                               */
02805   /* Parameters "Rank" and "Channel" are used with masks because containing   */
02806   /* other bits reserved for other purpose.                                   */
02807   MODIFY_REG(ADCx->CHSELR,
02808              ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
02809              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
02810 }
02811
02812 /**
02813   * @brief  Get ADC group regular sequence: channel on the selected
02814   *         scan sequence rank.
02815   * @note   On this STM32 series, ADC group regular sequencer is
02816   *         fully configurable: sequencer length and each rank
02817   *         affectation to a channel are configurable.
02818   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
02819   * @note   Depending on devices and packages, some channels may not be available.
02820   *         Refer to device datasheet for channels availability.
02821   * @note   Usage of the returned channel number:
02822   *         - To reinject this channel into another function LL_ADC_xxx:
02823   *           the returned channel number is only partly formatted on definition
02824   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02825   *           with parts of literals LL_ADC_CHANNEL_x or using
02826   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02827   *           Then the selected literal LL_ADC_CHANNEL_x can be used
02828   *           as parameter for another function.
02829   *         - To get the channel number in decimal format:
02830   *           process the returned value with the helper macro
02831   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02832   * @rmtoll CHSELR   SQ1            LL_ADC_REG_GetSequencerRanks\n
02833   *         CHSELR   SQ2            LL_ADC_REG_GetSequencerRanks\n
02834   *         CHSELR   SQ3            LL_ADC_REG_GetSequencerRanks\n
02835   *         CHSELR   SQ4            LL_ADC_REG_GetSequencerRanks\n
02836   *         CHSELR   SQ5            LL_ADC_REG_GetSequencerRanks\n
02837   *         CHSELR   SQ6            LL_ADC_REG_GetSequencerRanks\n
02838   *         CHSELR   SQ7            LL_ADC_REG_GetSequencerRanks\n
02839   *         CHSELR   SQ8            LL_ADC_REG_GetSequencerRanks
02840   * @param  ADCx ADC instance
02841   * @param  Rank This parameter can be one of the following values:
02842   *         @arg @ref LL_ADC_REG_RANK_1
02843   *         @arg @ref LL_ADC_REG_RANK_2
02844   *         @arg @ref LL_ADC_REG_RANK_3
02845   *         @arg @ref LL_ADC_REG_RANK_4
02846   *         @arg @ref LL_ADC_REG_RANK_5
02847   *         @arg @ref LL_ADC_REG_RANK_6
02848   *         @arg @ref LL_ADC_REG_RANK_7
02849   *         @arg @ref LL_ADC_REG_RANK_8
02850   * @retval Returned value can be one of the following values:
02851   *         @arg @ref LL_ADC_CHANNEL_0
02852   *         @arg @ref LL_ADC_CHANNEL_1
02853   *         @arg @ref LL_ADC_CHANNEL_2
02854   *         @arg @ref LL_ADC_CHANNEL_3
02855   *         @arg @ref LL_ADC_CHANNEL_4
02856   *         @arg @ref LL_ADC_CHANNEL_5
02857   *         @arg @ref LL_ADC_CHANNEL_6
02858   *         @arg @ref LL_ADC_CHANNEL_7
02859   *         @arg @ref LL_ADC_CHANNEL_8
02860   *         @arg @ref LL_ADC_CHANNEL_9
02861   *         @arg @ref LL_ADC_CHANNEL_10
02862   *         @arg @ref LL_ADC_CHANNEL_11
02863   *         @arg @ref LL_ADC_CHANNEL_12
02864   *         @arg @ref LL_ADC_CHANNEL_13
02865   *         @arg @ref LL_ADC_CHANNEL_14
02866   *         @arg @ref LL_ADC_CHANNEL_15         (1)
02867   *         @arg @ref LL_ADC_CHANNEL_16         (1)
02868   *         @arg @ref LL_ADC_CHANNEL_17         (1)
02869   *         @arg @ref LL_ADC_CHANNEL_18
02870   *         @arg @ref LL_ADC_CHANNEL_VREFINT    (2)
02871   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
02872   *         @arg @ref LL_ADC_CHANNEL_VBAT       (2)
02873   *
02874   *         (1) On STM32G0, parameter can be set in ADC group sequencer
02875   *             only if sequencer is set in mode "not fully configurable",
02876   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
02877   *         (2) For ADC channel read back from ADC register,
02878   *             comparison with internal channel parameter to be done
02879   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02880   */
02881 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
02882 {
02883   return (uint32_t)((READ_BIT(ADCx->CHSELR,
02884                               ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
02885                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
02886                     ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
02887                    );
02888 }
02889
02890 /**
02891   * @brief  Set ADC group regular sequence: channel on rank corresponding to
02892   *         channel number.
02893   * @note   This function performs:
02894   *         - Channels ordering into each rank of scan sequence:
02895   *           rank of each channel is fixed by channel HW number
02896   *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
02897   *         - Set channels selected by overwriting the current sequencer
02898   *           configuration.
02899   * @note   On this STM32 series, ADC group regular sequencer both modes
02900   *         "fully configurable" or "not fully configurable"
02901   *         are available, they can be chosen using
02902   *         function @ref LL_ADC_REG_SetSequencerConfigurable().
02903   *         This function can be used with setting "not fully configurable".
02904   *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
02905   *         and @ref LL_ADC_REG_SetSequencerLength().
02906   * @note   On this STM32 series, after modifying sequencer (functions
02907   *         @ref LL_ADC_REG_SetSequencerLength()
02908   *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
02909   *         it is mandatory to wait for the assertion of CCRDY flag
02910   *         using @ref LL_ADC_IsActiveFlag_CCRDY().
02911   *         Otherwise, some actions may be ignored.
02912   *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
02913   *         for more details.
02914   * @note   Depending on devices and packages, some channels may not be available.
02915   *         Refer to device datasheet for channels availability.
02916   * @note   On this STM32 series, to measure internal channels (VrefInt,
02917   *         TempSensor, ...), measurement paths to internal channels must be
02918   *         enabled separately.
02919   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
02920   * @note   On this STM32 series, setting of this feature is conditioned to
02921   *         ADC state:
02922   *         ADC must be disabled or enabled without conversion on going
02923   *         on group regular.
02924   * @note   One or several values can be selected.
02925   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
02926   * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChannels\n
02927   *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChannels\n
02928   *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChannels\n
02929   *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChannels\n
02930   *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChannels\n
02931   *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChannels\n
02932   *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChannels\n
02933   *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChannels\n
02934   *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChannels\n
02935   *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChannels\n
02936   *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChannels\n
02937   *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChannels\n
02938   *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChannels\n
02939   *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChannels\n
02940   *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChannels\n
02941   *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChannels\n
02942   *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChannels\n
02943   *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChannels\n
02944   *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChannels
02945   * @param  ADCx ADC instance
02946   * @param  Channel This parameter can be a combination of the following values:
02947   *         @arg @ref LL_ADC_CHANNEL_0
02948   *         @arg @ref LL_ADC_CHANNEL_1
02949   *         @arg @ref LL_ADC_CHANNEL_2
02950   *         @arg @ref LL_ADC_CHANNEL_3
02951   *         @arg @ref LL_ADC_CHANNEL_4
02952   *         @arg @ref LL_ADC_CHANNEL_5
02953   *         @arg @ref LL_ADC_CHANNEL_6
02954   *         @arg @ref LL_ADC_CHANNEL_7
02955   *         @arg @ref LL_ADC_CHANNEL_8
02956   *         @arg @ref LL_ADC_CHANNEL_9
02957   *         @arg @ref LL_ADC_CHANNEL_10
02958   *         @arg @ref LL_ADC_CHANNEL_11
02959   *         @arg @ref LL_ADC_CHANNEL_12
02960   *         @arg @ref LL_ADC_CHANNEL_13
02961   *         @arg @ref LL_ADC_CHANNEL_14
02962   *         @arg @ref LL_ADC_CHANNEL_15         (1)
02963   *         @arg @ref LL_ADC_CHANNEL_16         (1)
02964   *         @arg @ref LL_ADC_CHANNEL_17         (1)
02965   *         @arg @ref LL_ADC_CHANNEL_18
02966   *         @arg @ref LL_ADC_CHANNEL_VREFINT
02967   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
02968   *         @arg @ref LL_ADC_CHANNEL_VBAT
02969   *
02970   *         (1) On STM32G0, parameter can be set in ADC group sequencer
02971   *             only if sequencer is set in mode "not fully configurable",
02972   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
02973   * @retval None
02974   */
02975 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
02976 {
02977   /* Parameter "Channel" is used with masks because containing                */
02978   /* other bits reserved for other purpose.                                   */
02979   WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
02980 }
02981
02982 /**
02983   * @brief  Add channel to ADC group regular sequence: channel on rank corresponding to
02984   *         channel number.
02985   * @note   This function performs:
02986   *         - Channels ordering into each rank of scan sequence:
02987   *           rank of each channel is fixed by channel HW number
02988   *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
02989   *         - Set channels selected by adding them to the current sequencer
02990   *           configuration.
02991   * @note   On this STM32 series, ADC group regular sequencer both modes
02992   *         "fully configurable" or "not fully configurable"
02993   *         are available, they can be chosen using
02994   *         function @ref LL_ADC_REG_SetSequencerConfigurable().
02995   *         This function can be used with setting "not fully configurable".
02996   *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
02997   *         and @ref LL_ADC_REG_SetSequencerLength().
02998   * @note   On this STM32 series, after modifying sequencer (functions
02999   *         @ref LL_ADC_REG_SetSequencerLength()
03000   *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
03001   *         it is mandatory to wait for the assertion of CCRDY flag
03002   *         using @ref LL_ADC_IsActiveFlag_CCRDY().
03003   *         Otherwise, some actions may be ignored.
03004   *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
03005   *         for more details.
03006   * @note   Depending on devices and packages, some channels may not be available.
03007   *         Refer to device datasheet for channels availability.
03008   * @note   On this STM32 series, to measure internal channels (VrefInt,
03009   *         TempSensor, ...), measurement paths to internal channels must be
03010   *         enabled separately.
03011   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03012   * @note   On this STM32 series, setting of this feature is conditioned to
03013   *         ADC state:
03014   *         ADC must be disabled or enabled without conversion on going
03015   *         on group regular.
03016   * @note   One or several values can be selected.
03017   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
03018   * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChAdd\n
03019   *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChAdd\n
03020   *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChAdd\n
03021   *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChAdd\n
03022   *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChAdd\n
03023   *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChAdd\n
03024   *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChAdd\n
03025   *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChAdd\n
03026   *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChAdd\n
03027   *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChAdd\n
03028   *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChAdd\n
03029   *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChAdd\n
03030   *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChAdd\n
03031   *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChAdd\n
03032   *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChAdd\n
03033   *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChAdd\n
03034   *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChAdd\n
03035   *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChAdd\n
03036   *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChAdd
03037   * @param  ADCx ADC instance
03038   * @param  Channel This parameter can be a combination of the following values:
03039   *         @arg @ref LL_ADC_CHANNEL_0
03040   *         @arg @ref LL_ADC_CHANNEL_1
03041   *         @arg @ref LL_ADC_CHANNEL_2
03042   *         @arg @ref LL_ADC_CHANNEL_3
03043   *         @arg @ref LL_ADC_CHANNEL_4
03044   *         @arg @ref LL_ADC_CHANNEL_5
03045   *         @arg @ref LL_ADC_CHANNEL_6
03046   *         @arg @ref LL_ADC_CHANNEL_7
03047   *         @arg @ref LL_ADC_CHANNEL_8
03048   *         @arg @ref LL_ADC_CHANNEL_9
03049   *         @arg @ref LL_ADC_CHANNEL_10
03050   *         @arg @ref LL_ADC_CHANNEL_11
03051   *         @arg @ref LL_ADC_CHANNEL_12
03052   *         @arg @ref LL_ADC_CHANNEL_13
03053   *         @arg @ref LL_ADC_CHANNEL_14
03054   *         @arg @ref LL_ADC_CHANNEL_15         (1)
03055   *         @arg @ref LL_ADC_CHANNEL_16         (1)
03056   *         @arg @ref LL_ADC_CHANNEL_17         (1)
03057   *         @arg @ref LL_ADC_CHANNEL_18
03058   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03059   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03060   *         @arg @ref LL_ADC_CHANNEL_VBAT
03061   *
03062   *         (1) On STM32G0, parameter can be set in ADC group sequencer
03063   *             only if sequencer is set in mode "not fully configurable",
03064   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
03065   * @retval None
03066   */
03067 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
03068 {
03069   /* Parameter "Channel" is used with masks because containing                */
03070   /* other bits reserved for other purpose.                                   */
03071   SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
03072 }
03073
03074 /**
03075   * @brief  Remove channel to ADC group regular sequence: channel on rank corresponding to
03076   *         channel number.
03077   * @note   This function performs:
03078   *         - Channels ordering into each rank of scan sequence:
03079   *           rank of each channel is fixed by channel HW number
03080   *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
03081   *         - Set channels selected by removing them to the current sequencer
03082   *           configuration.
03083   * @note   On this STM32 series, ADC group regular sequencer both modes
03084   *         "fully configurable" or "not fully configurable"
03085   *         are available, they can be chosen using
03086   *         function @ref LL_ADC_REG_SetSequencerConfigurable().
03087   *         This function can be used with setting "not fully configurable".
03088   *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
03089   *         and @ref LL_ADC_REG_SetSequencerLength().
03090   * @note   On this STM32 series, after modifying sequencer (functions
03091   *         @ref LL_ADC_REG_SetSequencerLength()
03092   *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
03093   *         it is mandatory to wait for the assertion of CCRDY flag
03094   *         using @ref LL_ADC_IsActiveFlag_CCRDY().
03095   *         Otherwise, some actions may be ignored.
03096   *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
03097   *         for more details.
03098   * @note   Depending on devices and packages, some channels may not be available.
03099   *         Refer to device datasheet for channels availability.
03100   * @note   On this STM32 series, to measure internal channels (VrefInt,
03101   *         TempSensor, ...), measurement paths to internal channels must be
03102   *         enabled separately.
03103   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03104   * @note   On this STM32 series, setting of this feature is conditioned to
03105   *         ADC state:
03106   *         ADC must be disabled or enabled without conversion on going
03107   *         on group regular.
03108   * @note   One or several values can be selected.
03109   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
03110   * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChRem\n
03111   *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChRem\n
03112   *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChRem\n
03113   *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChRem\n
03114   *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChRem\n
03115   *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChRem\n
03116   *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChRem\n
03117   *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChRem\n
03118   *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChRem\n
03119   *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChRem\n
03120   *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChRem\n
03121   *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChRem\n
03122   *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChRem\n
03123   *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChRem\n
03124   *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChRem\n
03125   *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChRem\n
03126   *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChRem\n
03127   *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChRem\n
03128   *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChRem
03129   * @param  ADCx ADC instance
03130   * @param  Channel This parameter can be a combination of the following values:
03131   *         @arg @ref LL_ADC_CHANNEL_0
03132   *         @arg @ref LL_ADC_CHANNEL_1
03133   *         @arg @ref LL_ADC_CHANNEL_2
03134   *         @arg @ref LL_ADC_CHANNEL_3
03135   *         @arg @ref LL_ADC_CHANNEL_4
03136   *         @arg @ref LL_ADC_CHANNEL_5
03137   *         @arg @ref LL_ADC_CHANNEL_6
03138   *         @arg @ref LL_ADC_CHANNEL_7
03139   *         @arg @ref LL_ADC_CHANNEL_8
03140   *         @arg @ref LL_ADC_CHANNEL_9
03141   *         @arg @ref LL_ADC_CHANNEL_10
03142   *         @arg @ref LL_ADC_CHANNEL_11
03143   *         @arg @ref LL_ADC_CHANNEL_12
03144   *         @arg @ref LL_ADC_CHANNEL_13
03145   *         @arg @ref LL_ADC_CHANNEL_14
03146   *         @arg @ref LL_ADC_CHANNEL_15         (1)
03147   *         @arg @ref LL_ADC_CHANNEL_16         (1)
03148   *         @arg @ref LL_ADC_CHANNEL_17         (1)
03149   *         @arg @ref LL_ADC_CHANNEL_18
03150   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03151   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03152   *         @arg @ref LL_ADC_CHANNEL_VBAT
03153   *
03154   *         (1) On STM32G0, parameter can be set in ADC group sequencer
03155   *             only if sequencer is set in mode "not fully configurable",
03156   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
03157   * @retval None
03158   */
03159 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
03160 {
03161   /* Parameter "Channel" is used with masks because containing                */
03162   /* other bits reserved for other purpose.                                   */
03163   CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
03164 }
03165
03166 /**
03167   * @brief  Get ADC group regular sequence: channel on rank corresponding to
03168   *         channel number.
03169   * @note   This function performs:
03170   *         - Channels order reading into each rank of scan sequence:
03171   *           rank of each channel is fixed by channel HW number
03172   *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
03173   * @note   On this STM32 series, ADC group regular sequencer both modes
03174   *         "fully configurable" or "not fully configurable"
03175   *         are available, they can be chosen using
03176   *         function @ref LL_ADC_REG_SetSequencerConfigurable().
03177   *         This function can be used with setting "not fully configurable".
03178   *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
03179   *         and @ref LL_ADC_REG_SetSequencerLength().
03180   * @note   Depending on devices and packages, some channels may not be available.
03181   *         Refer to device datasheet for channels availability.
03182   * @note   On this STM32 series, to measure internal channels (VrefInt,
03183   *         TempSensor, ...), measurement paths to internal channels must be
03184   *         enabled separately.
03185   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03186   * @note   On this STM32 series, setting of this feature is conditioned to
03187   *         ADC state:
03188   *         ADC must be disabled or enabled without conversion on going
03189   *         on group regular.
03190   * @note   One or several values can be retrieved.
03191   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
03192   * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_GetSequencerChannels\n
03193   *         CHSELR   CHSEL1         LL_ADC_REG_GetSequencerChannels\n
03194   *         CHSELR   CHSEL2         LL_ADC_REG_GetSequencerChannels\n
03195   *         CHSELR   CHSEL3         LL_ADC_REG_GetSequencerChannels\n
03196   *         CHSELR   CHSEL4         LL_ADC_REG_GetSequencerChannels\n
03197   *         CHSELR   CHSEL5         LL_ADC_REG_GetSequencerChannels\n
03198   *         CHSELR   CHSEL6         LL_ADC_REG_GetSequencerChannels\n
03199   *         CHSELR   CHSEL7         LL_ADC_REG_GetSequencerChannels\n
03200   *         CHSELR   CHSEL8         LL_ADC_REG_GetSequencerChannels\n
03201   *         CHSELR   CHSEL9         LL_ADC_REG_GetSequencerChannels\n
03202   *         CHSELR   CHSEL10        LL_ADC_REG_GetSequencerChannels\n
03203   *         CHSELR   CHSEL11        LL_ADC_REG_GetSequencerChannels\n
03204   *         CHSELR   CHSEL12        LL_ADC_REG_GetSequencerChannels\n
03205   *         CHSELR   CHSEL13        LL_ADC_REG_GetSequencerChannels\n
03206   *         CHSELR   CHSEL14        LL_ADC_REG_GetSequencerChannels\n
03207   *         CHSELR   CHSEL15        LL_ADC_REG_GetSequencerChannels\n
03208   *         CHSELR   CHSEL16        LL_ADC_REG_GetSequencerChannels\n
03209   *         CHSELR   CHSEL17        LL_ADC_REG_GetSequencerChannels\n
03210   *         CHSELR   CHSEL18        LL_ADC_REG_GetSequencerChannels
03211   * @param  ADCx ADC instance
03212   * @retval Returned value can be a combination of the following values:
03213   *         @arg @ref LL_ADC_CHANNEL_0
03214   *         @arg @ref LL_ADC_CHANNEL_1
03215   *         @arg @ref LL_ADC_CHANNEL_2
03216   *         @arg @ref LL_ADC_CHANNEL_3
03217   *         @arg @ref LL_ADC_CHANNEL_4
03218   *         @arg @ref LL_ADC_CHANNEL_5
03219   *         @arg @ref LL_ADC_CHANNEL_6
03220   *         @arg @ref LL_ADC_CHANNEL_7
03221   *         @arg @ref LL_ADC_CHANNEL_8
03222   *         @arg @ref LL_ADC_CHANNEL_9
03223   *         @arg @ref LL_ADC_CHANNEL_10
03224   *         @arg @ref LL_ADC_CHANNEL_11
03225   *         @arg @ref LL_ADC_CHANNEL_12
03226   *         @arg @ref LL_ADC_CHANNEL_13
03227   *         @arg @ref LL_ADC_CHANNEL_14
03228   *         @arg @ref LL_ADC_CHANNEL_15         (1)
03229   *         @arg @ref LL_ADC_CHANNEL_16         (1)
03230   *         @arg @ref LL_ADC_CHANNEL_17         (1)
03231   *         @arg @ref LL_ADC_CHANNEL_18
03232   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03233   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03234   *         @arg @ref LL_ADC_CHANNEL_VBAT
03235   *
03236   *         (1) On STM32G0, parameter can be set in ADC group sequencer
03237   *             only if sequencer is set in mode "not fully configurable",
03238   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
03239   */
03240 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
03241 {
03242   uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
03243
03244   return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
03245           | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
03246           | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
03247           | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
03248           | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
03249           | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
03250           | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
03251           | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
03252           | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
03253           | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
03254           | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
03255           | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
03256           | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
03257           | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
03258           | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
03259           | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
03260           | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
03261           | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
03262 #if defined(ADC_CCR_VBATEN)
03263           | (((channels_bitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
03264 #endif /* ADC_CCR_VBATEN */
03265          );
03266 }
03267
03268 /**
03269   * @brief  Set ADC continuous conversion mode on ADC group regular.
03270   * @note   Description of ADC continuous conversion mode:
03271   *         - single mode: one conversion per trigger
03272   *         - continuous mode: after the first trigger, following
03273   *           conversions launched successively automatically.
03274   * @note   It is not possible to enable both ADC group regular
03275   *         continuous mode and sequencer discontinuous mode.
03276   * @note   On this STM32 series, setting of this feature is conditioned to
03277   *         ADC state:
03278   *         ADC must be disabled.
03279   * @rmtoll CFGR1    CONT           LL_ADC_REG_SetContinuousMode
03280   * @param  ADCx ADC instance
03281   * @param  Continuous This parameter can be one of the following values:
03282   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03283   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03284   * @retval None
03285   */
03286 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
03287 {
03288   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
03289 }
03290
03291 /**
03292   * @brief  Get ADC continuous conversion mode on ADC group regular.
03293   * @note   Description of ADC continuous conversion mode:
03294   *         - single mode: one conversion per trigger
03295   *         - continuous mode: after the first trigger, following
03296   *           conversions launched successively automatically.
03297   * @rmtoll CFGR1    CONT           LL_ADC_REG_GetContinuousMode
03298   * @param  ADCx ADC instance
03299   * @retval Returned value can be one of the following values:
03300   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03301   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03302   */
03303 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
03304 {
03305   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
03306 }
03307
03308 /**
03309   * @brief  Set ADC group regular conversion data transfer: no transfer or
03310   *         transfer by DMA, and DMA requests mode.
03311   * @note   If transfer by DMA selected, specifies the DMA requests
03312   *         mode:
03313   *         - Limited mode (One shot mode): DMA transfer requests are stopped
03314   *           when number of DMA data transfers (number of
03315   *           ADC conversions) is reached.
03316   *           This ADC mode is intended to be used with DMA mode non-circular.
03317   *         - Unlimited mode: DMA transfer requests are unlimited,
03318   *           whatever number of DMA data transfers (number of
03319   *           ADC conversions).
03320   *           This ADC mode is intended to be used with DMA mode circular.
03321   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
03322   *         mode non-circular:
03323   *         when DMA transfers size will be reached, DMA will stop transfers of
03324   *         ADC conversions data ADC will raise an overrun error
03325   *        (overrun flag and interruption if enabled).
03326   * @note   To configure DMA source address (peripheral address),
03327   *         use function @ref LL_ADC_DMA_GetRegAddr().
03328   * @note   On this STM32 series, setting of this feature is conditioned to
03329   *         ADC state:
03330   *         ADC must be disabled.
03331   * @rmtoll CFGR1    DMAEN          LL_ADC_REG_SetDMATransfer\n
03332   *         CFGR1    DMACFG         LL_ADC_REG_SetDMATransfer
03333   * @param  ADCx ADC instance
03334   * @param  DMATransfer This parameter can be one of the following values:
03335   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
03336   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03337   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03338   * @retval None
03339   */
03340 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
03341 {
03342   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
03343 }
03344
03345 /**
03346   * @brief  Get ADC group regular conversion data transfer: no transfer or
03347   *         transfer by DMA, and DMA requests mode.
03348   * @note   If transfer by DMA selected, specifies the DMA requests
03349   *         mode:
03350   *         - Limited mode (One shot mode): DMA transfer requests are stopped
03351   *           when number of DMA data transfers (number of
03352   *           ADC conversions) is reached.
03353   *           This ADC mode is intended to be used with DMA mode non-circular.
03354   *         - Unlimited mode: DMA transfer requests are unlimited,
03355   *           whatever number of DMA data transfers (number of
03356   *           ADC conversions).
03357   *           This ADC mode is intended to be used with DMA mode circular.
03358   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
03359   *         mode non-circular:
03360   *         when DMA transfers size will be reached, DMA will stop transfers of
03361   *         ADC conversions data ADC will raise an overrun error
03362   *         (overrun flag and interruption if enabled).
03363   * @note   To configure DMA source address (peripheral address),
03364   *         use function @ref LL_ADC_DMA_GetRegAddr().
03365   * @rmtoll CFGR1    DMAEN          LL_ADC_REG_GetDMATransfer\n
03366   *         CFGR1    DMACFG         LL_ADC_REG_GetDMATransfer
03367   * @param  ADCx ADC instance
03368   * @retval Returned value can be one of the following values:
03369   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
03370   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03371   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03372   */
03373 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
03374 {
03375   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
03376 }
03377
03378 /**
03379   * @brief  Set ADC group regular behavior in case of overrun:
03380   *         data preserved or overwritten.
03381   * @note   Compatibility with devices without feature overrun:
03382   *         other devices without this feature have a behavior
03383   *         equivalent to data overwritten.
03384   *         The default setting of overrun is data preserved.
03385   *         Therefore, for compatibility with all devices, parameter
03386   *         overrun should be set to data overwritten.
03387   * @note   On this STM32 series, setting of this feature is conditioned to
03388   *         ADC state:
03389   *         ADC must be disabled.
03390   * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_SetOverrun
03391   * @param  ADCx ADC instance
03392   * @param  Overrun This parameter can be one of the following values:
03393   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03394   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03395   * @retval None
03396   */
03397 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
03398 {
03399   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
03400 }
03401
03402 /**
03403   * @brief  Get ADC group regular behavior in case of overrun:
03404   *         data preserved or overwritten.
03405   * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_GetOverrun
03406   * @param  ADCx ADC instance
03407   * @retval Returned value can be one of the following values:
03408   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03409   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03410   */
03411 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
03412 {
03413   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
03414 }
03415
03416 /**
03417   * @}
03418   */
03419
03420 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
03421   * @{
03422   */
03423
03424 /**
03425   * @brief  Set sampling time of the selected ADC channel
03426   *         Unit: ADC clock cycles.
03427   * @note   On this device, sampling time is on channel scope: independently
03428   *         of channel mapped on ADC group regular or injected.
03429   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
03430   *         converted:
03431   *         sampling time constraints must be respected (sampling time can be
03432   *         adjusted in function of ADC clock frequency and sampling time
03433   *         setting).
03434   *         Refer to device datasheet for timings values (parameters TS_vrefint,
03435   *         TS_temp, ...).
03436   * @note   Conversion time is the addition of sampling time and processing time.
03437   *         Refer to reference manual for ADC processing time of
03438   *         this STM32 series.
03439   * @note   In case of ADC conversion of internal channel (VrefInt,
03440   *         temperature sensor, ...), a sampling time minimum value
03441   *         is required.
03442   *         Refer to device datasheet.
03443   * @note   On this STM32 series, setting of this feature is conditioned to
03444   *         ADC state:
03445   *         ADC must be disabled or enabled without conversion on going
03446   *         on group regular.
03447   * @rmtoll SMPR     SMPSEL0        LL_ADC_SetChannelSamplingTime\n
03448   *         SMPR     SMPSEL1        LL_ADC_SetChannelSamplingTime\n
03449   *         SMPR     SMPSEL2        LL_ADC_SetChannelSamplingTime\n
03450   *         SMPR     SMPSEL3        LL_ADC_SetChannelSamplingTime\n
03451   *         SMPR     SMPSEL4        LL_ADC_SetChannelSamplingTime\n
03452   *         SMPR     SMPSEL5        LL_ADC_SetChannelSamplingTime\n
03453   *         SMPR     SMPSEL6        LL_ADC_SetChannelSamplingTime\n
03454   *         SMPR     SMPSEL7        LL_ADC_SetChannelSamplingTime\n
03455   *         SMPR     SMPSEL8        LL_ADC_SetChannelSamplingTime\n
03456   *         SMPR     SMPSEL9        LL_ADC_SetChannelSamplingTime\n
03457   *         SMPR     SMPSEL10       LL_ADC_SetChannelSamplingTime\n
03458   *         SMPR     SMPSEL11       LL_ADC_SetChannelSamplingTime\n
03459   *         SMPR     SMPSEL12       LL_ADC_SetChannelSamplingTime\n
03460   *         SMPR     SMPSEL13       LL_ADC_SetChannelSamplingTime\n
03461   *         SMPR     SMPSEL14       LL_ADC_SetChannelSamplingTime\n
03462   *         SMPR     SMPSEL15       LL_ADC_SetChannelSamplingTime\n
03463   *         SMPR     SMPSEL16       LL_ADC_SetChannelSamplingTime\n
03464   *         SMPR     SMPSEL17       LL_ADC_SetChannelSamplingTime\n
03465   *         SMPR     SMPSEL18       LL_ADC_SetChannelSamplingTime
03466   * @param  ADCx ADC instance
03467   * @param  Channel This parameter can be a combination of the following values:
03468   *         @arg @ref LL_ADC_CHANNEL_0
03469   *         @arg @ref LL_ADC_CHANNEL_1
03470   *         @arg @ref LL_ADC_CHANNEL_2
03471   *         @arg @ref LL_ADC_CHANNEL_3
03472   *         @arg @ref LL_ADC_CHANNEL_4
03473   *         @arg @ref LL_ADC_CHANNEL_5
03474   *         @arg @ref LL_ADC_CHANNEL_6
03475   *         @arg @ref LL_ADC_CHANNEL_7
03476   *         @arg @ref LL_ADC_CHANNEL_8
03477   *         @arg @ref LL_ADC_CHANNEL_9
03478   *         @arg @ref LL_ADC_CHANNEL_10
03479   *         @arg @ref LL_ADC_CHANNEL_11
03480   *         @arg @ref LL_ADC_CHANNEL_12
03481   *         @arg @ref LL_ADC_CHANNEL_13
03482   *         @arg @ref LL_ADC_CHANNEL_14
03483   *         @arg @ref LL_ADC_CHANNEL_15         (1)
03484   *         @arg @ref LL_ADC_CHANNEL_16         (1)
03485   *         @arg @ref LL_ADC_CHANNEL_17         (1)
03486   *         @arg @ref LL_ADC_CHANNEL_18
03487   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03488   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03489   *         @arg @ref LL_ADC_CHANNEL_VBAT
03490   *
03491   *         (1) On STM32G0, parameter can be set in ADC group sequencer
03492   *             only if sequencer is set in mode "not fully configurable",
03493   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
03494   * @param  SamplingTimeY This parameter can be one of the following values:
03495   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
03496   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
03497   * @retval None
03498   */
03499 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
03500 {
03501   /* Parameter "Channel" is used with masks because containing                */
03502   /* other bits reserved for other purpose.                                   */
03503   MODIFY_REG(ADCx->SMPR,
03504              (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
03505              (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
03506             );
03507 }
03508
03509 /**
03510   * @brief  Get sampling time of the selected ADC channel
03511   *         Unit: ADC clock cycles.
03512   * @note   On this device, sampling time is on channel scope: independently
03513   *         of channel mapped on ADC group regular or injected.
03514   * @note   Conversion time is the addition of sampling time and processing time.
03515   *         Refer to reference manual for ADC processing time of
03516   *         this STM32 series.
03517   * @rmtoll SMPR     SMPSEL0        LL_ADC_GetChannelSamplingTime\n
03518   *         SMPR     SMPSEL1        LL_ADC_GetChannelSamplingTime\n
03519   *         SMPR     SMPSEL2        LL_ADC_GetChannelSamplingTime\n
03520   *         SMPR     SMPSEL3        LL_ADC_GetChannelSamplingTime\n
03521   *         SMPR     SMPSEL4        LL_ADC_GetChannelSamplingTime\n
03522   *         SMPR     SMPSEL5        LL_ADC_GetChannelSamplingTime\n
03523   *         SMPR     SMPSEL6        LL_ADC_GetChannelSamplingTime\n
03524   *         SMPR     SMPSEL7        LL_ADC_GetChannelSamplingTime\n
03525   *         SMPR     SMPSEL8        LL_ADC_GetChannelSamplingTime\n
03526   *         SMPR     SMPSEL9        LL_ADC_GetChannelSamplingTime\n
03527   *         SMPR     SMPSEL10       LL_ADC_GetChannelSamplingTime\n
03528   *         SMPR     SMPSEL11       LL_ADC_GetChannelSamplingTime\n
03529   *         SMPR     SMPSEL12       LL_ADC_GetChannelSamplingTime\n
03530   *         SMPR     SMPSEL13       LL_ADC_GetChannelSamplingTime\n
03531   *         SMPR     SMPSEL14       LL_ADC_GetChannelSamplingTime\n
03532   *         SMPR     SMPSEL15       LL_ADC_GetChannelSamplingTime\n
03533   *         SMPR     SMPSEL16       LL_ADC_GetChannelSamplingTime\n
03534   *         SMPR     SMPSEL17       LL_ADC_GetChannelSamplingTime\n
03535   *         SMPR     SMPSEL18       LL_ADC_GetChannelSamplingTime
03536   * @param  ADCx ADC instance
03537   * @param  Channel This parameter can be one of the following values:
03538   *         @arg @ref LL_ADC_CHANNEL_0
03539   *         @arg @ref LL_ADC_CHANNEL_1
03540   *         @arg @ref LL_ADC_CHANNEL_2
03541   *         @arg @ref LL_ADC_CHANNEL_3
03542   *         @arg @ref LL_ADC_CHANNEL_4
03543   *         @arg @ref LL_ADC_CHANNEL_5
03544   *         @arg @ref LL_ADC_CHANNEL_6
03545   *         @arg @ref LL_ADC_CHANNEL_7
03546   *         @arg @ref LL_ADC_CHANNEL_8
03547   *         @arg @ref LL_ADC_CHANNEL_9
03548   *         @arg @ref LL_ADC_CHANNEL_10
03549   *         @arg @ref LL_ADC_CHANNEL_11
03550   *         @arg @ref LL_ADC_CHANNEL_12
03551   *         @arg @ref LL_ADC_CHANNEL_13
03552   *         @arg @ref LL_ADC_CHANNEL_14
03553   *         @arg @ref LL_ADC_CHANNEL_15         (1)
03554   *         @arg @ref LL_ADC_CHANNEL_16         (1)
03555   *         @arg @ref LL_ADC_CHANNEL_17         (1)
03556   *         @arg @ref LL_ADC_CHANNEL_18
03557   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03558   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03559   *         @arg @ref LL_ADC_CHANNEL_VBAT
03560   *
03561   *         (1) On STM32G0, parameter can be set in ADC group sequencer
03562   *             only if sequencer is set in mode "not fully configurable",
03563   *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
03564   * @retval Returned value can be one of the following values:
03565   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
03566   *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
03567   */
03568 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
03569 {
03570   __IO uint32_t smpr = READ_REG(ADCx->SMPR);
03571
03572   /* Retrieve sampling time bit corresponding to the selected channel            */
03573   /* and shift it to position 0.                                                 */
03574   uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
03575                                   >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) &
03576                                       0x1FUL));
03577
03578   /* Select sampling time bitfield depending on sampling time bit value 0 or 1.  */
03579   return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
03580           | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
03581 }
03582
03583 /**
03584   * @}
03585   */
03586
03587 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
03588   * @{
03589   */
03590
03591 /**
03592   * @brief  Set ADC analog watchdog monitored channels:
03593   *         a single channel, multiple channels or all channels,
03594   *         on ADC group regular.
03595   * @note   Once monitored channels are selected, analog watchdog
03596   *         is enabled.
03597   * @note   In case of need to define a single channel to monitor
03598   *         with analog watchdog from sequencer channel definition,
03599   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
03600   * @note   On this STM32 series, there are 2 kinds of analog watchdog
03601   *         instance:
03602   *         - AWD standard (instance AWD1):
03603   *           - channels monitored: can monitor 1 channel or all channels.
03604   *           - groups monitored: ADC group regular.
03605   *           - resolution: resolution is not limited (corresponds to
03606   *             ADC resolution configured).
03607   *         - AWD flexible (instances AWD2, AWD3):
03608   *           - channels monitored: flexible on channels monitored, selection is
03609   *             channel wise, from from 1 to all channels.
03610   *             Specificity of this analog watchdog: Multiple channels can
03611   *             be selected. For example:
03612   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
03613   *           - groups monitored: not selection possible (monitoring on both
03614   *             groups regular and injected).
03615   *             Channels selected are monitored on groups regular and injected:
03616   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
03617   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
03618   *           - resolution: resolution is not limited (corresponds to
03619   *             ADC resolution configured).
03620   * @note   On this STM32 series, setting of this feature is conditioned to
03621   *         ADC state:
03622   *         ADC must be disabled.
03623   * @rmtoll CFGR1    AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
03624   *         CFGR1    AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
03625   *         CFGR1    AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
03626   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
03627   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
03628   * @param  ADCx ADC instance
03629   * @param  AWDy This parameter can be one of the following values:
03630   *         @arg @ref LL_ADC_AWD1
03631   *         @arg @ref LL_ADC_AWD2
03632   *         @arg @ref LL_ADC_AWD3
03633   * @param  AWDChannelGroup This parameter can be one of the following values:
03634   *         @arg @ref LL_ADC_AWD_DISABLE
03635   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
03636   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
03637   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
03638   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
03639   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
03640   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
03641   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
03642   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
03643   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
03644   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
03645   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
03646   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
03647   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
03648   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
03649   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
03650   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
03651   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
03652   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
03653   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
03654   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
03655   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
03656   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
03657   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG
03658   * @retval None
03659   */
03660 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
03661 {
03662   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
03663   /* in register and register position depending on parameter "AWDy".         */
03664   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
03665   /* containing other bits reserved for other purpose.                        */
03666   __IO uint32_t *preg;
03667
03668   if (AWDy == LL_ADC_AWD1)
03669   {
03670     preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
03671   }
03672   else
03673   {
03674     preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
03675   }
03676
03677   MODIFY_REG(*preg,
03678              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
03679              AWDChannelGroup & AWDy);
03680 }
03681
03682 /**
03683   * @brief  Get ADC analog watchdog monitored channel.
03684   * @note   Usage of the returned channel number:
03685   *         - To reinject this channel into another function LL_ADC_xxx:
03686   *           the returned channel number is only partly formatted on definition
03687   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
03688   *           with parts of literals LL_ADC_CHANNEL_x or using
03689   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03690   *           Then the selected literal LL_ADC_CHANNEL_x can be used
03691   *           as parameter for another function.
03692   *         - To get the channel number in decimal format:
03693   *           process the returned value with the helper macro
03694   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03695   *           Applicable only when the analog watchdog is set to monitor
03696   *           one channel.
03697   * @note   On this STM32 series, there are 2 kinds of analog watchdog
03698   *         instance:
03699   *         - AWD standard (instance AWD1):
03700   *           - channels monitored: can monitor 1 channel or all channels.
03701   *           - groups monitored: ADC group regular.
03702   *           - resolution: resolution is not limited (corresponds to
03703   *             ADC resolution configured).
03704   *         - AWD flexible (instances AWD2, AWD3):
03705   *           - channels monitored: flexible on channels monitored, selection is
03706   *             channel wise, from from 1 to all channels.
03707   *             Specificity of this analog watchdog: Multiple channels can
03708   *             be selected. For example:
03709   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
03710   *           - groups monitored: not selection possible (monitoring on both
03711   *             groups regular and injected).
03712   *             Channels selected are monitored on groups regular and injected:
03713   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
03714   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
03715   *           - resolution: resolution is not limited (corresponds to
03716   *             ADC resolution configured).
03717   * @note   On this STM32 series, setting of this feature is conditioned to
03718   *         ADC state:
03719   *         ADC must be disabled or enabled without conversion on going
03720   *         on group regular.
03721   * @rmtoll CFGR1    AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
03722   *         CFGR1    AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
03723   *         CFGR1    AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
03724   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
03725   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
03726   * @param  ADCx ADC instance
03727   * @param  AWDy This parameter can be one of the following values:
03728   *         @arg @ref LL_ADC_AWD1
03729   *         @arg @ref LL_ADC_AWD2 (1)
03730   *         @arg @ref LL_ADC_AWD3 (1)
03731   *
03732   *         (1) On this AWD number, monitored channel can be retrieved
03733   *             if only 1 channel is programmed (or none or all channels).
03734   *             This function cannot retrieve monitored channel if
03735   *             multiple channels are programmed simultaneously
03736   *             by bitfield.
03737   * @retval Returned value can be one of the following values:
03738   *         @arg @ref LL_ADC_AWD_DISABLE
03739   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
03740   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
03741   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
03742   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
03743   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
03744   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
03745   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
03746   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
03747   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
03748   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
03749   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
03750   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
03751   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
03752   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
03753   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
03754   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
03755   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
03756   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
03757   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
03758   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
03759   */
03760 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
03761 {
03762   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
03763                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
03764
03765   uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
03766
03767   /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled       */
03768   /* (parameter value LL_ADC_AWD_DISABLE).                                    */
03769   /* Else, the selected AWD is enabled and is monitoring a group of channels  */
03770   /* or a single channel.                                                     */
03771   if (analog_wd_monit_channels != 0UL)
03772   {
03773     if (AWDy == LL_ADC_AWD1)
03774     {
03775       if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
03776       {
03777         /* AWD monitoring a group of channels */
03778         analog_wd_monit_channels = ((analog_wd_monit_channels
03779                                      | (ADC_AWD_CR23_CHANNEL_MASK)
03780                                     )
03781                                     & (~(ADC_CFGR1_AWD1CH))
03782                                    );
03783       }
03784       else
03785       {
03786         /* AWD monitoring a single channel */
03787         analog_wd_monit_channels = (analog_wd_monit_channels
03788                                     | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos))
03789                                    );
03790       }
03791     }
03792     else
03793     {
03794       if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
03795       {
03796         /* AWD monitoring a group of channels */
03797         analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
03798                                     | (ADC_CFGR1_AWD1EN)
03799                                    );
03800       }
03801       else
03802       {
03803         /* AWD monitoring a single channel */
03804         /* AWD monitoring a group of channels */
03805         analog_wd_monit_channels = (analog_wd_monit_channels
03806                                     | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
03807                                     | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos)
03808                                    );
03809       }
03810     }
03811   }
03812
03813   return analog_wd_monit_channels;
03814 }
03815
03816 /**
03817   * @brief  Set ADC analog watchdog thresholds value of both thresholds
03818   *         high and low.
03819   * @note   If value of only one threshold high or low must be set,
03820   *         use function @ref LL_ADC_SetAnalogWDThresholds().
03821   * @note   In case of ADC resolution different of 12 bits,
03822   *         analog watchdog thresholds data require a specific shift.
03823   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
03824   * @note   On this STM32 series, there are 2 kinds of analog watchdog
03825   *         instance:
03826   *         - AWD standard (instance AWD1):
03827   *           - channels monitored: can monitor 1 channel or all channels.
03828   *           - groups monitored: ADC group regular.
03829   *           - resolution: resolution is not limited (corresponds to
03830   *             ADC resolution configured).
03831   *         - AWD flexible (instances AWD2, AWD3):
03832   *           - channels monitored: flexible on channels monitored, selection is
03833   *             channel wise, from from 1 to all channels.
03834   *             Specificity of this analog watchdog: Multiple channels can
03835   *             be selected. For example:
03836   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
03837   *           - groups monitored: not selection possible (monitoring on both
03838   *             groups regular and injected).
03839   *             Channels selected are monitored on groups regular and injected:
03840   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
03841   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
03842   *           - resolution: resolution is not limited (corresponds to
03843   *             ADC resolution configured).
03844   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
03845   *         impacted: the comparison of analog watchdog thresholds is done on
03846   *         oversampling final computation (after ratio and shift application):
03847   *         ADC data register bitfield [15:4] (12 most significant bits).
03848   *         Examples:
03849   *         - Oversampling ratio and shift selected to have ADC conversion data
03850   *           on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
03851   *           ADC analog watchdog thresholds must be divided by 16.
03852   *         - Oversampling ratio and shift selected to have ADC conversion data
03853   *           on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
03854   *           ADC analog watchdog thresholds must be divided by 4.
03855   *         - Oversampling ratio and shift selected to have ADC conversion data
03856   *           on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
03857   *           ADC analog watchdog thresholds match directly to ADC data register.
03858   * @note   On this STM32 series, setting of this feature is conditioned to
03859   *         ADC state:
03860   *         ADC must be disabled or enabled without conversion on going
03861   *         on group regular.
03862   * @rmtoll AWD1TR   HT1            LL_ADC_ConfigAnalogWDThresholds\n
03863   *         AWD2TR   HT2            LL_ADC_ConfigAnalogWDThresholds\n
03864   *         AWD3TR   HT3            LL_ADC_ConfigAnalogWDThresholds\n
03865   *         AWD1TR   LT1            LL_ADC_ConfigAnalogWDThresholds\n
03866   *         AWD2TR   LT2            LL_ADC_ConfigAnalogWDThresholds\n
03867   *         AWD3TR   LT3            LL_ADC_ConfigAnalogWDThresholds
03868   * @param  ADCx ADC instance
03869   * @param  AWDy This parameter can be one of the following values:
03870   *         @arg @ref LL_ADC_AWD1
03871   *         @arg @ref LL_ADC_AWD2
03872   *         @arg @ref LL_ADC_AWD3
03873   * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
03874   * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
03875   * @retval None
03876   */
03877 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
03878                                                      uint32_t AWDThresholdLowValue)
03879 {
03880   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
03881   /* position in register and register position depending on parameter        */
03882   /* "AWDy".                                                                  */
03883   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
03884   /* containing other bits reserved for other purpose.                        */
03885   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
03886
03887   MODIFY_REG(*preg,
03888              ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
03889              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
03890 }
03891
03892 /**
03893   * @brief  Set ADC analog watchdog threshold value of threshold
03894   *         high or low.
03895   * @note   If values of both thresholds high or low must be set,
03896   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
03897   * @note   In case of ADC resolution different of 12 bits,
03898   *         analog watchdog thresholds data require a specific shift.
03899   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
03900   * @note   On this STM32 series, there are 2 kinds of analog watchdog
03901   *         instance:
03902   *         - AWD standard (instance AWD1):
03903   *           - channels monitored: can monitor 1 channel or all channels.
03904   *           - groups monitored: ADC group regular.
03905   *           - resolution: resolution is not limited (corresponds to
03906   *             ADC resolution configured).
03907   *         - AWD flexible (instances AWD2, AWD3):
03908   *           - channels monitored: flexible on channels monitored, selection is
03909   *             channel wise, from from 1 to all channels.
03910   *             Specificity of this analog watchdog: Multiple channels can
03911   *             be selected. For example:
03912   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
03913   *           - groups monitored: not selection possible (monitoring on both
03914   *             groups regular and injected).
03915   *             Channels selected are monitored on groups regular and injected:
03916   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
03917   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
03918   *           - resolution: resolution is not limited (corresponds to
03919   *             ADC resolution configured).
03920   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
03921   *         impacted: the comparison of analog watchdog thresholds is done on
03922   *         oversampling final computation (after ratio and shift application):
03923   *         ADC data register bitfield [15:4] (12 most significant bits).
03924   *         Examples:
03925   *         - Oversampling ratio and shift selected to have ADC conversion data
03926   *           on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
03927   *           ADC analog watchdog thresholds must be divided by 16.
03928   *         - Oversampling ratio and shift selected to have ADC conversion data
03929   *           on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
03930   *           ADC analog watchdog thresholds must be divided by 4.
03931   *         - Oversampling ratio and shift selected to have ADC conversion data
03932   *           on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
03933   *           ADC analog watchdog thresholds match directly to ADC data register.
03934   * @note   On this STM32 series, setting of this feature is not conditioned to
03935   *         ADC state:
03936   *         ADC can be disabled, enabled with or without conversion on going
03937   *         on ADC group regular.
03938   * @rmtoll AWD1TR   HT1            LL_ADC_SetAnalogWDThresholds\n
03939   *         AWD2TR   HT2            LL_ADC_SetAnalogWDThresholds\n
03940   *         AWD3TR   HT3            LL_ADC_SetAnalogWDThresholds\n
03941   *         AWD1TR   LT1            LL_ADC_SetAnalogWDThresholds\n
03942   *         AWD2TR   LT2            LL_ADC_SetAnalogWDThresholds\n
03943   *         AWD3TR   LT3            LL_ADC_SetAnalogWDThresholds
03944   * @param  ADCx ADC instance
03945   * @param  AWDy This parameter can be one of the following values:
03946   *         @arg @ref LL_ADC_AWD1
03947   *         @arg @ref LL_ADC_AWD2
03948   *         @arg @ref LL_ADC_AWD3
03949   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
03950   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
03951   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
03952   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
03953   * @retval None
03954   */
03955 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
03956                                                   uint32_t AWDThresholdValue)
03957 {
03958   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
03959   /* position in register and register position depending on parameters       */
03960   /* "AWDThresholdsHighLow" and "AWDy".                                       */
03961   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
03962   /* containing other bits reserved for other purpose.                        */
03963   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
03964                                              (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
03965                                              + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
03966
03967   MODIFY_REG(*preg,
03968              AWDThresholdsHighLow,
03969              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
03970 }
03971
03972 /**
03973   * @brief  Get ADC analog watchdog threshold value of threshold high,
03974   *         threshold low or raw data with ADC thresholds high and low
03975   *         concatenated.
03976   * @note   If raw data with ADC thresholds high and low is retrieved,
03977   *         the data of each threshold high or low can be isolated
03978   *         using helper macro:
03979   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
03980   * @note   In case of ADC resolution different of 12 bits,
03981   *         analog watchdog thresholds data require a specific shift.
03982   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
03983   * @rmtoll AWD1TR   HT1            LL_ADC_GetAnalogWDThresholds\n
03984   *         AWD2TR   HT2            LL_ADC_GetAnalogWDThresholds\n
03985   *         AWD3TR   HT3            LL_ADC_GetAnalogWDThresholds\n
03986   *         AWD1TR   LT1            LL_ADC_GetAnalogWDThresholds\n
03987   *         AWD2TR   LT2            LL_ADC_GetAnalogWDThresholds\n
03988   *         AWD3TR   LT3            LL_ADC_GetAnalogWDThresholds
03989   * @param  ADCx ADC instance
03990   * @param  AWDy This parameter can be one of the following values:
03991   *         @arg @ref LL_ADC_AWD1
03992   *         @arg @ref LL_ADC_AWD2
03993   *         @arg @ref LL_ADC_AWD3
03994   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
03995   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
03996   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
03997   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
03998   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03999   */
04000 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
04001 {
04002   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
04003   /* position in register and register position depending on parameters       */
04004   /* "AWDThresholdsHighLow" and "AWDy".                                       */
04005   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
04006   /* containing other bits reserved for other purpose.                        */
04007   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
04008                                                    (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
04009                                                    + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
04010
04011   return (uint32_t)(READ_BIT(*preg,
04012                              (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
04013                     >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
04014                         & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1)));
04015 }
04016
04017 /**
04018   * @}
04019   */
04020
04021 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
04022   * @{
04023   */
04024
04025 /**
04026   * @brief  Set ADC oversampling scope.
04027   * @note   On this STM32 series, setting of this feature is conditioned to
04028   *         ADC state:
04029   *         ADC must be disabled.
04030   * @rmtoll CFGR2    OVSE           LL_ADC_SetOverSamplingScope
04031   * @param  ADCx ADC instance
04032   * @param  OvsScope This parameter can be one of the following values:
04033   *         @arg @ref LL_ADC_OVS_DISABLE
04034   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
04035   * @retval None
04036   */
04037 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
04038 {
04039   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
04040 }
04041
04042 /**
04043   * @brief  Get ADC oversampling scope.
04044   * @rmtoll CFGR2    OVSE           LL_ADC_GetOverSamplingScope
04045   * @param  ADCx ADC instance
04046   * @retval Returned value can be one of the following values:
04047   *         @arg @ref LL_ADC_OVS_DISABLE
04048   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
04049   */
04050 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
04051 {
04052   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
04053 }
04054
04055 /**
04056   * @brief  Set ADC oversampling discontinuous mode (triggered mode)
04057   *         on the selected ADC group.
04058   * @note   Number of oversampled conversions are done either in:
04059   *         - continuous mode (all conversions of oversampling ratio
04060   *           are done from 1 trigger)
04061   *         - discontinuous mode (each conversion of oversampling ratio
04062   *           needs a trigger)
04063   * @note   On this STM32 series, setting of this feature is conditioned to
04064   *         ADC state:
04065   *         ADC must be disabled.
04066   * @rmtoll CFGR2    TOVS           LL_ADC_SetOverSamplingDiscont
04067   * @param  ADCx ADC instance
04068   * @param  OverSamplingDiscont This parameter can be one of the following values:
04069   *         @arg @ref LL_ADC_OVS_REG_CONT
04070   *         @arg @ref LL_ADC_OVS_REG_DISCONT
04071   * @retval None
04072   */
04073 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
04074 {
04075   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
04076 }
04077
04078 /**
04079   * @brief  Get ADC oversampling discontinuous mode (triggered mode)
04080   *         on the selected ADC group.
04081   * @note   Number of oversampled conversions are done either in:
04082   *         - continuous mode (all conversions of oversampling ratio
04083   *           are done from 1 trigger)
04084   *         - discontinuous mode (each conversion of oversampling ratio
04085   *           needs a trigger)
04086   * @rmtoll CFGR2    TOVS           LL_ADC_GetOverSamplingDiscont
04087   * @param  ADCx ADC instance
04088   * @retval Returned value can be one of the following values:
04089   *         @arg @ref LL_ADC_OVS_REG_CONT
04090   *         @arg @ref LL_ADC_OVS_REG_DISCONT
04091   */
04092 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
04093 {
04094   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
04095 }
04096
04097 /**
04098   * @brief  Set ADC oversampling
04099   * @note   This function set the 2 items of oversampling configuration:
04100   *         - ratio
04101   *         - shift
04102   * @note   On this STM32 series, setting of this feature is conditioned to
04103   *         ADC state:
04104   *         ADC must be disabled.
04105   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
04106   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
04107   * @param  ADCx ADC instance
04108   * @param  Ratio This parameter can be one of the following values:
04109   *         @arg @ref LL_ADC_OVS_RATIO_2
04110   *         @arg @ref LL_ADC_OVS_RATIO_4
04111   *         @arg @ref LL_ADC_OVS_RATIO_8
04112   *         @arg @ref LL_ADC_OVS_RATIO_16
04113   *         @arg @ref LL_ADC_OVS_RATIO_32
04114   *         @arg @ref LL_ADC_OVS_RATIO_64
04115   *         @arg @ref LL_ADC_OVS_RATIO_128
04116   *         @arg @ref LL_ADC_OVS_RATIO_256
04117   * @param  Shift This parameter can be one of the following values:
04118   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
04119   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
04120   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
04121   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
04122   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
04123   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
04124   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
04125   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
04126   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
04127   * @retval None
04128   */
04129 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
04130 {
04131   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
04132 }
04133
04134 /**
04135   * @brief  Get ADC oversampling ratio
04136   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
04137   * @param  ADCx ADC instance
04138   * @retval Ratio This parameter can be one of the following values:
04139   *         @arg @ref LL_ADC_OVS_RATIO_2
04140   *         @arg @ref LL_ADC_OVS_RATIO_4
04141   *         @arg @ref LL_ADC_OVS_RATIO_8
04142   *         @arg @ref LL_ADC_OVS_RATIO_16
04143   *         @arg @ref LL_ADC_OVS_RATIO_32
04144   *         @arg @ref LL_ADC_OVS_RATIO_64
04145   *         @arg @ref LL_ADC_OVS_RATIO_128
04146   *         @arg @ref LL_ADC_OVS_RATIO_256
04147   */
04148 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
04149 {
04150   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
04151 }
04152
04153 /**
04154   * @brief  Get ADC oversampling shift
04155   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
04156   * @param  ADCx ADC instance
04157   * @retval Shift This parameter can be one of the following values:
04158   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
04159   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
04160   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
04161   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
04162   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
04163   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
04164   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
04165   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
04166   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
04167   */
04168 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
04169 {
04170   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
04171 }
04172
04173 /**
04174   * @}
04175   */
04176
04177 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
04178   * @{
04179   */
04180
04181 /**
04182   * @brief  Enable ADC instance internal voltage regulator.
04183   * @note   On this STM32 series, there are three possibilities to enable
04184   *         the voltage regulator:
04185   *         - by enabling it manually
04186   *           using function @ref LL_ADC_EnableInternalRegulator().
04187   *         - by launching a calibration
04188   *           using function @ref LL_ADC_StartCalibration().
04189   *         - by enabling the ADC
04190   *           using function @ref LL_ADC_Enable().
04191   * @note   On this STM32 series, after ADC internal voltage regulator enable,
04192   *         a delay for ADC internal voltage regulator stabilization
04193   *         is required before performing a ADC calibration or ADC enable.
04194   *         Refer to device datasheet, parameter "tADCVREG_STUP".
04195   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
04196   * @note   On this STM32 series, setting of this feature is conditioned to
04197   *         ADC state:
04198   *         ADC must be ADC disabled.
04199   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
04200   * @param  ADCx ADC instance
04201   * @retval None
04202   */
04203 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
04204 {
04205   /* Note: Write register with some additional bits forced to state reset     */
04206   /*       instead of modifying only the selected bit for this function,      */
04207   /*       to not interfere with bits with HW property "rs".                  */
04208   MODIFY_REG(ADCx->CR,
04209              ADC_CR_BITS_PROPERTY_RS,
04210              ADC_CR_ADVREGEN);
04211 }
04212
04213 /**
04214   * @brief  Disable ADC internal voltage regulator.
04215   * @note   On this STM32 series, setting of this feature is conditioned to
04216   *         ADC state:
04217   *         ADC must be ADC disabled.
04218   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
04219   * @param  ADCx ADC instance
04220   * @retval None
04221   */
04222 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
04223 {
04224   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
04225 }
04226
04227 /**
04228   * @brief  Get the selected ADC instance internal voltage regulator state.
04229   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
04230   * @param  ADCx ADC instance
04231   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
04232   */
04233 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
04234 {
04235   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
04236 }
04237
04238 /**
04239   * @brief  Enable the selected ADC instance.
04240   * @note   On this STM32 series, after ADC enable, a delay for
04241   *         ADC internal analog stabilization is required before performing a
04242   *         ADC conversion start.
04243   *         Refer to device datasheet, parameter tSTAB.
04244   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
04245   *         is enabled and when conversion clock is active.
04246   *         (not only core clock: this ADC has a dual clock domain)
04247   * @note   On this STM32 series, setting of this feature is conditioned to
04248   *         ADC state:
04249   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
04250   * @rmtoll CR       ADEN           LL_ADC_Enable
04251   * @param  ADCx ADC instance
04252   * @retval None
04253   */
04254 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
04255 {
04256   /* Note: Write register with some additional bits forced to state reset     */
04257   /*       instead of modifying only the selected bit for this function,      */
04258   /*       to not interfere with bits with HW property "rs".                  */
04259   MODIFY_REG(ADCx->CR,
04260              ADC_CR_BITS_PROPERTY_RS,
04261              ADC_CR_ADEN);
04262 }
04263
04264 /**
04265   * @brief  Disable the selected ADC instance.
04266   * @note   On this STM32 series, setting of this feature is conditioned to
04267   *         ADC state:
04268   *         ADC must be not disabled. Must be enabled without conversion on going
04269   *         on group regular.
04270   * @rmtoll CR       ADDIS          LL_ADC_Disable
04271   * @param  ADCx ADC instance
04272   * @retval None
04273   */
04274 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
04275 {
04276   /* Note: Write register with some additional bits forced to state reset     */
04277   /*       instead of modifying only the selected bit for this function,      */
04278   /*       to not interfere with bits with HW property "rs".                  */
04279   MODIFY_REG(ADCx->CR,
04280              ADC_CR_BITS_PROPERTY_RS,
04281              ADC_CR_ADDIS);
04282 }
04283
04284 /**
04285   * @brief  Get the selected ADC instance enable state.
04286   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
04287   *         is enabled and when conversion clock is active.
04288   *         (not only core clock: this ADC has a dual clock domain)
04289   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
04290   * @param  ADCx ADC instance
04291   * @retval 0: ADC is disabled, 1: ADC is enabled.
04292   */
04293 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
04294 {
04295   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
04296 }
04297
04298 /**
04299   * @brief  Get the selected ADC instance disable state.
04300   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
04301   * @param  ADCx ADC instance
04302   * @retval 0: no ADC disable command on going.
04303   */
04304 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
04305 {
04306   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
04307 }
04308
04309 /**
04310   * @brief  Start ADC calibration in the mode single-ended
04311   *         or differential (for devices with differential mode available).
04312   * @note   On this STM32 series, a minimum number of ADC clock cycles
04313   *         are required between ADC end of calibration and ADC enable.
04314   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
04315   * @note   In case of usage of ADC with DMA transfer:
04316   *         On this STM32 series, ADC DMA transfer request should be disabled
04317   *         during calibration:
04318   *         Calibration factor is available in data register
04319   *         and also transferred by DMA.
04320   *         To not insert ADC calibration factor among ADC conversion data
04321   *         in array variable, DMA transfer must be disabled during
04322   *         calibration.
04323   *         (DMA transfer setting backup and disable before calibration,
04324   *         DMA transfer setting restore after calibration.
04325   *         Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
04326   *         @ref LL_ADC_REG_SetDMATransfer() ).
04327   * @note   In case of usage of feature auto power-off:
04328   *         This mode must be disabled during calibration
04329   *         Refer to function @ref LL_ADC_SetLowPowerMode().
04330   * @note   On this STM32 series, setting of this feature is conditioned to
04331   *         ADC state:
04332   *         ADC must be ADC disabled.
04333   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration
04334   * @param  ADCx ADC instance
04335   * @retval None
04336   */
04337 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
04338 {
04339   /* Note: Write register with some additional bits forced to state reset     */
04340   /*       instead of modifying only the selected bit for this function,      */
04341   /*       to not interfere with bits with HW property "rs".                  */
04342   MODIFY_REG(ADCx->CR,
04343              ADC_CR_BITS_PROPERTY_RS,
04344              ADC_CR_ADCAL);
04345 }
04346
04347 /**
04348   * @brief  Get ADC calibration state.
04349   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
04350   * @param  ADCx ADC instance
04351   * @retval 0: calibration complete, 1: calibration in progress.
04352   */
04353 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
04354 {
04355   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
04356 }
04357
04358 /**
04359   * @}
04360   */
04361
04362 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
04363   * @{
04364   */
04365
04366 /**
04367   * @brief  Start ADC group regular conversion.
04368   * @note   On this STM32 series, this function is relevant for both
04369   *         internal trigger (SW start) and external trigger:
04370   *         - If ADC trigger has been set to software start, ADC conversion
04371   *           starts immediately.
04372   *         - If ADC trigger has been set to external trigger, ADC conversion
04373   *           will start at next trigger event (on the selected trigger edge)
04374   *           following the ADC start conversion command.
04375   * @note   On this STM32 series, setting of this feature is conditioned to
04376   *         ADC state:
04377   *         ADC must be enabled without conversion on going on group regular,
04378   *         without conversion stop command on going on group regular,
04379   *         without ADC disable command on going.
04380   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
04381   * @param  ADCx ADC instance
04382   * @retval None
04383   */
04384 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
04385 {
04386   /* Note: Write register with some additional bits forced to state reset     */
04387   /*       instead of modifying only the selected bit for this function,      */
04388   /*       to not interfere with bits with HW property "rs".                  */
04389   MODIFY_REG(ADCx->CR,
04390              ADC_CR_BITS_PROPERTY_RS,
04391              ADC_CR_ADSTART);
04392 }
04393
04394 /**
04395   * @brief  Stop ADC group regular conversion.
04396   * @note   On this STM32 series, setting of this feature is conditioned to
04397   *         ADC state:
04398   *         ADC must be enabled with conversion on going on group regular,
04399   *         without ADC disable command on going.
04400   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
04401   * @param  ADCx ADC instance
04402   * @retval None
04403   */
04404 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
04405 {
04406   /* Note: Write register with some additional bits forced to state reset     */
04407   /*       instead of modifying only the selected bit for this function,      */
04408   /*       to not interfere with bits with HW property "rs".                  */
04409   MODIFY_REG(ADCx->CR,
04410              ADC_CR_BITS_PROPERTY_RS,
04411              ADC_CR_ADSTP);
04412 }
04413
04414 /**
04415   * @brief  Get ADC group regular conversion state.
04416   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
04417   * @param  ADCx ADC instance
04418   * @retval 0: no conversion is on going on ADC group regular.
04419   */
04420 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
04421 {
04422   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
04423 }
04424
04425 /**
04426   * @brief  Get ADC group regular command of conversion stop state
04427   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
04428   * @param  ADCx ADC instance
04429   * @retval 0: no command of conversion stop is on going on ADC group regular.
04430   */
04431 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
04432 {
04433   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
04434 }
04435
04436 /**
04437   * @brief  Get ADC group regular conversion data, range fit for
04438   *         all ADC configurations: all ADC resolutions and
04439   *         all oversampling increased data width (for devices
04440   *         with feature oversampling).
04441   * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData32
04442   * @param  ADCx ADC instance
04443   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
04444   */
04445 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
04446 {
04447   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
04448 }
04449
04450 /**
04451   * @brief  Get ADC group regular conversion data, range fit for
04452   *         ADC resolution 12 bits.
04453   * @note   For devices with feature oversampling: Oversampling
04454   *         can increase data width, function for extended range
04455   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
04456   * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData12
04457   * @param  ADCx ADC instance
04458   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
04459   */
04460 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
04461 {
04462   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
04463 }
04464
04465 /**
04466   * @brief  Get ADC group regular conversion data, range fit for
04467   *         ADC resolution 10 bits.
04468   * @note   For devices with feature oversampling: Oversampling
04469   *         can increase data width, function for extended range
04470   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
04471   * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData10
04472   * @param  ADCx ADC instance
04473   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
04474   */
04475 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
04476 {
04477   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
04478 }
04479
04480 /**
04481   * @brief  Get ADC group regular conversion data, range fit for
04482   *         ADC resolution 8 bits.
04483   * @note   For devices with feature oversampling: Oversampling
04484   *         can increase data width, function for extended range
04485   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
04486   * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData8
04487   * @param  ADCx ADC instance
04488   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
04489   */
04490 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
04491 {
04492   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
04493 }
04494
04495 /**
04496   * @brief  Get ADC group regular conversion data, range fit for
04497   *         ADC resolution 6 bits.
04498   * @note   For devices with feature oversampling: Oversampling
04499   *         can increase data width, function for extended range
04500   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
04501   * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData6
04502   * @param  ADCx ADC instance
04503   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
04504   */
04505 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
04506 {
04507   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
04508 }
04509
04510 /**
04511   * @}
04512   */
04513
04514 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
04515   * @{
04516   */
04517
04518 /**
04519   * @brief  Get flag ADC ready.
04520   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
04521   *         is enabled and when conversion clock is active.
04522   *         (not only core clock: this ADC has a dual clock domain)
04523   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
04524   * @param  ADCx ADC instance
04525   * @retval State of bit (1 or 0).
04526   */
04527 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
04528 {
04529   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
04530 }
04531
04532 /**
04533   * @brief  Get flag ADC channel configuration ready.
04534   * @note   On this STM32 series, after modifying sequencer
04535   *         it is mandatory to wait for the assertion of CCRDY flag
04536   *         using @ref LL_ADC_IsActiveFlag_CCRDY().
04537   *         Otherwise, performing some actions (configuration update,
04538   *         ADC conversion start, ... ) will be ignored.
04539   *         Functions requiring wait for CCRDY flag are:
04540   *         @ref LL_ADC_REG_SetSequencerLength()
04541   *         @ref LL_ADC_REG_SetSequencerRanks()
04542   *         @ref LL_ADC_REG_SetSequencerChannels()
04543   *         @ref LL_ADC_REG_SetSequencerChAdd()
04544   *         @ref LL_ADC_REG_SetSequencerChRem()
04545   *         @ref LL_ADC_REG_SetSequencerScanDirection()
04546   *         @ref LL_ADC_REG_SetSequencerConfigurable()
04547   * @note   Duration of ADC channel configuration ready: CCRDY handshake
04548   *         requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
04549   *         has been changed.
04550   * @rmtoll ISR      CCRDY          LL_ADC_IsActiveFlag_CCRDY
04551   * @param  ADCx ADC instance
04552   * @retval State of bit (1 or 0).
04553   */
04554 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx)
04555 {
04556   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
04557 }
04558
04559 /**
04560   * @brief  Get flag ADC group regular end of unitary conversion.
04561   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
04562   * @param  ADCx ADC instance
04563   * @retval State of bit (1 or 0).
04564   */
04565 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
04566 {
04567   return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
04568 }
04569
04570 /**
04571   * @brief  Get flag ADC group regular end of sequence conversions.
04572   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
04573   * @param  ADCx ADC instance
04574   * @retval State of bit (1 or 0).
04575   */
04576 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
04577 {
04578   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
04579 }
04580
04581 /**
04582   * @brief  Get flag ADC group regular overrun.
04583   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
04584   * @param  ADCx ADC instance
04585   * @retval State of bit (1 or 0).
04586   */
04587 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
04588 {
04589   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
04590 }
04591
04592 /**
04593   * @brief  Get flag ADC group regular end of sampling phase.
04594   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
04595   * @param  ADCx ADC instance
04596   * @retval State of bit (1 or 0).
04597   */
04598 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
04599 {
04600   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
04601 }
04602
04603 /**
04604   * @brief  Get flag ADC analog watchdog 1 flag
04605   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
04606   * @param  ADCx ADC instance
04607   * @retval State of bit (1 or 0).
04608   */
04609 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
04610 {
04611   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
04612 }
04613
04614 /**
04615   * @brief  Get flag ADC analog watchdog 2.
04616   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
04617   * @param  ADCx ADC instance
04618   * @retval State of bit (1 or 0).
04619   */
04620 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
04621 {
04622   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
04623 }
04624
04625 /**
04626   * @brief  Get flag ADC analog watchdog 3.
04627   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
04628   * @param  ADCx ADC instance
04629   * @retval State of bit (1 or 0).
04630   */
04631 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
04632 {
04633   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
04634 }
04635
04636 /**
04637   * @brief  Get flag ADC end of calibration.
04638   * @rmtoll ISR      EOCAL          LL_ADC_IsActiveFlag_EOCAL
04639   * @param  ADCx ADC instance
04640   * @retval State of bit (1 or 0).
04641   */
04642 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
04643 {
04644   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
04645 }
04646
04647 /**
04648   * @brief  Clear flag ADC ready.
04649   * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
04650   *         is enabled and when conversion clock is active.
04651   *         (not only core clock: this ADC has a dual clock domain)
04652   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
04653   * @param  ADCx ADC instance
04654   * @retval None
04655   */
04656 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
04657 {
04658   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
04659 }
04660
04661 /**
04662   * @brief  Clear flag ADC channel configuration ready.
04663   * @rmtoll ISR      CCRDY          LL_ADC_ClearFlag_CCRDY
04664   * @param  ADCx ADC instance
04665   * @retval State of bit (1 or 0).
04666   */
04667 __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
04668 {
04669   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
04670 }
04671
04672 /**
04673   * @brief  Clear flag ADC group regular end of unitary conversion.
04674   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
04675   * @param  ADCx ADC instance
04676   * @retval None
04677   */
04678 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
04679 {
04680   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
04681 }
04682
04683 /**
04684   * @brief  Clear flag ADC group regular end of sequence conversions.
04685   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
04686   * @param  ADCx ADC instance
04687   * @retval None
04688   */
04689 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
04690 {
04691   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
04692 }
04693
04694 /**
04695   * @brief  Clear flag ADC group regular overrun.
04696   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
04697   * @param  ADCx ADC instance
04698   * @retval None
04699   */
04700 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
04701 {
04702   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
04703 }
04704
04705 /**
04706   * @brief  Clear flag ADC group regular end of sampling phase.
04707   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
04708   * @param  ADCx ADC instance
04709   * @retval None
04710   */
04711 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
04712 {
04713   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
04714 }
04715
04716 /**
04717   * @brief  Clear flag ADC analog watchdog 1.
04718   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
04719   * @param  ADCx ADC instance
04720   * @retval None
04721   */
04722 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
04723 {
04724   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
04725 }
04726
04727 /**
04728   * @brief  Clear flag ADC analog watchdog 2.
04729   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
04730   * @param  ADCx ADC instance
04731   * @retval None
04732   */
04733 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
04734 {
04735   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
04736 }
04737
04738 /**
04739   * @brief  Clear flag ADC analog watchdog 3.
04740   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
04741   * @param  ADCx ADC instance
04742   * @retval None
04743   */
04744 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
04745 {
04746   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
04747 }
04748
04749 /**
04750   * @brief  Clear flag ADC end of calibration.
04751   * @rmtoll ISR      EOCAL          LL_ADC_ClearFlag_EOCAL
04752   * @param  ADCx ADC instance
04753   * @retval None
04754   */
04755 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
04756 {
04757   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
04758 }
04759
04760 /**
04761   * @}
04762   */
04763
04764 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
04765   * @{
04766   */
04767
04768 /**
04769   * @brief  Enable ADC ready.
04770   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
04771   * @param  ADCx ADC instance
04772   * @retval None
04773   */
04774 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
04775 {
04776   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
04777 }
04778
04779 /**
04780   * @brief  Enable interruption ADC channel configuration ready.
04781   * @rmtoll IER      CCRDYIE        LL_ADC_EnableIT_CCRDY
04782   * @param  ADCx ADC instance
04783   * @retval State of bit (1 or 0).
04784   */
04785 __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
04786 {
04787   SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
04788 }
04789
04790 /**
04791   * @brief  Enable interruption ADC group regular end of unitary conversion.
04792   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
04793   * @param  ADCx ADC instance
04794   * @retval None
04795   */
04796 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
04797 {
04798   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
04799 }
04800
04801 /**
04802   * @brief  Enable interruption ADC group regular end of sequence conversions.
04803   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
04804   * @param  ADCx ADC instance
04805   * @retval None
04806   */
04807 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
04808 {
04809   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
04810 }
04811
04812 /**
04813   * @brief  Enable ADC group regular interruption overrun.
04814   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
04815   * @param  ADCx ADC instance
04816   * @retval None
04817   */
04818 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
04819 {
04820   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
04821 }
04822
04823 /**
04824   * @brief  Enable interruption ADC group regular end of sampling.
04825   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
04826   * @param  ADCx ADC instance
04827   * @retval None
04828   */
04829 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
04830 {
04831   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
04832 }
04833
04834 /**
04835   * @brief  Enable interruption ADC analog watchdog 1.
04836   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
04837   * @param  ADCx ADC instance
04838   * @retval None
04839   */
04840 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
04841 {
04842   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
04843 }
04844
04845 /**
04846   * @brief  Enable interruption ADC analog watchdog 2.
04847   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
04848   * @param  ADCx ADC instance
04849   * @retval None
04850   */
04851 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
04852 {
04853   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
04854 }
04855
04856 /**
04857   * @brief  Enable interruption ADC analog watchdog 3.
04858   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
04859   * @param  ADCx ADC instance
04860   * @retval None
04861   */
04862 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
04863 {
04864   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
04865 }
04866
04867 /**
04868   * @brief  Enable interruption ADC end of calibration.
04869   * @rmtoll IER      EOCALIE        LL_ADC_EnableIT_EOCAL
04870   * @param  ADCx ADC instance
04871   * @retval None
04872   */
04873 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
04874 {
04875   SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
04876 }
04877
04878 /**
04879   * @brief  Disable interruption ADC ready.
04880   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
04881   * @param  ADCx ADC instance
04882   * @retval None
04883   */
04884 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
04885 {
04886   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
04887 }
04888
04889 /**
04890   * @brief  Disable interruption ADC channel configuration ready.
04891   * @rmtoll IER      CCRDYIE        LL_ADC_DisableIT_CCRDY
04892   * @param  ADCx ADC instance
04893   * @retval State of bit (1 or 0).
04894   */
04895 __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
04896 {
04897   CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
04898 }
04899
04900 /**
04901   * @brief  Disable interruption ADC group regular end of unitary conversion.
04902   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
04903   * @param  ADCx ADC instance
04904   * @retval None
04905   */
04906 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
04907 {
04908   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
04909 }
04910
04911 /**
04912   * @brief  Disable interruption ADC group regular end of sequence conversions.
04913   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
04914   * @param  ADCx ADC instance
04915   * @retval None
04916   */
04917 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
04918 {
04919   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
04920 }
04921
04922 /**
04923   * @brief  Disable interruption ADC group regular overrun.
04924   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
04925   * @param  ADCx ADC instance
04926   * @retval None
04927   */
04928 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
04929 {
04930   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
04931 }
04932
04933 /**
04934   * @brief  Disable interruption ADC group regular end of sampling.
04935   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
04936   * @param  ADCx ADC instance
04937   * @retval None
04938   */
04939 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
04940 {
04941   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
04942 }
04943
04944 /**
04945   * @brief  Disable interruption ADC analog watchdog 1.
04946   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
04947   * @param  ADCx ADC instance
04948   * @retval None
04949   */
04950 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
04951 {
04952   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
04953 }
04954
04955 /**
04956   * @brief  Disable interruption ADC analog watchdog 2.
04957   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
04958   * @param  ADCx ADC instance
04959   * @retval None
04960   */
04961 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
04962 {
04963   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
04964 }
04965
04966 /**
04967   * @brief  Disable interruption ADC analog watchdog 3.
04968   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
04969   * @param  ADCx ADC instance
04970   * @retval None
04971   */
04972 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
04973 {
04974   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
04975 }
04976
04977 /**
04978   * @brief  Disable interruption ADC end of calibration.
04979   * @rmtoll IER      EOCALIE        LL_ADC_DisableIT_EOCAL
04980   * @param  ADCx ADC instance
04981   * @retval None
04982   */
04983 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
04984 {
04985   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
04986 }
04987
04988 /**
04989   * @brief  Get state of interruption ADC ready
04990   *         (0: interrupt disabled, 1: interrupt enabled).
04991   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
04992   * @param  ADCx ADC instance
04993   * @retval State of bit (1 or 0).
04994   */
04995 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
04996 {
04997   return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
04998 }
04999
05000 /**
05001   * @brief  Get state of interruption ADC channel configuration ready.
05002   * @rmtoll IER      CCRDYIE        LL_ADC_IsEnabledIT_CCRDY
05003   * @param  ADCx ADC instance
05004   * @retval State of bit (1 or 0).
05005   */
05006 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx)
05007 {
05008   return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
05009 }
05010
05011 /**
05012   * @brief  Get state of interruption ADC group regular end of unitary conversion
05013   *         (0: interrupt disabled, 1: interrupt enabled).
05014   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
05015   * @param  ADCx ADC instance
05016   * @retval State of bit (1 or 0).
05017   */
05018 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
05019 {
05020   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
05021 }
05022
05023 /**
05024   * @brief  Get state of interruption ADC group regular end of sequence conversions
05025   *         (0: interrupt disabled, 1: interrupt enabled).
05026   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
05027   * @param  ADCx ADC instance
05028   * @retval State of bit (1 or 0).
05029   */
05030 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
05031 {
05032   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
05033 }
05034
05035 /**
05036   * @brief  Get state of interruption ADC group regular overrun
05037   *         (0: interrupt disabled, 1: interrupt enabled).
05038   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
05039   * @param  ADCx ADC instance
05040   * @retval State of bit (1 or 0).
05041   */
05042 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
05043 {
05044   return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
05045 }
05046
05047 /**
05048   * @brief  Get state of interruption ADC group regular end of sampling
05049   *         (0: interrupt disabled, 1: interrupt enabled).
05050   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
05051   * @param  ADCx ADC instance
05052   * @retval State of bit (1 or 0).
05053   */
05054 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
05055 {
05056   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
05057 }
05058
05059 /**
05060   * @brief  Get state of interruption ADC analog watchdog 1
05061   *         (0: interrupt disabled, 1: interrupt enabled).
05062   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
05063   * @param  ADCx ADC instance
05064   * @retval State of bit (1 or 0).
05065   */
05066 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
05067 {
05068   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
05069 }
05070
05071 /**
05072   * @brief  Get state of interruption Get ADC analog watchdog 2
05073   *         (0: interrupt disabled, 1: interrupt enabled).
05074   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
05075   * @param  ADCx ADC instance
05076   * @retval State of bit (1 or 0).
05077   */
05078 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
05079 {
05080   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
05081 }
05082
05083 /**
05084   * @brief  Get state of interruption Get ADC analog watchdog 3
05085   *         (0: interrupt disabled, 1: interrupt enabled).
05086   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
05087   * @param  ADCx ADC instance
05088   * @retval State of bit (1 or 0).
05089   */
05090 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
05091 {
05092   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
05093 }
05094
05095 /**
05096   * @brief  Get state of interruption ADC end of calibration
05097   *         (0: interrupt disabled, 1: interrupt enabled).
05098   * @rmtoll IER      EOCALIE        LL_ADC_IsEnabledIT_EOCAL
05099   * @param  ADCx ADC instance
05100   * @retval State of bit (1 or 0).
05101   */
05102 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
05103 {
05104   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
05105 }
05106
05107 /**
05108   * @}
05109   */
05110
05111 #if defined(USE_FULL_LL_DRIVER)
05112 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
05113   * @{
05114   */
05115
05116 /* Initialization of some features of ADC common parameters and multimode */
05117 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
05118 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
05119 void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
05120
05121 /* De-initialization of ADC instance */
05122 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
05123
05124 /* Initialization of some features of ADC instance */
05125 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
05126 void        LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
05127
05128 /* Initialization of some features of ADC instance and ADC group regular */
05129 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
05130 void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
05131
05132 /**
05133   * @}
05134   */
05135 #endif /* USE_FULL_LL_DRIVER */
05136
05137 /**
05138   * @}
05139   */
05140
05141 /**
05142   * @}
05143   */
05144
05145 #endif /* ADC1 */
05146
05147 /**
05148   * @}
05149   */
05150
05151 #ifdef __cplusplus
05152 }
05153 #endif
05154
05155 #endif /* STM32G0xx_LL_ADC_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_bus.h Source File

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stm32g0xx_ll_bus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_bus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of BUS LL module.
00006
00007   @verbatim
00008                       ##### RCC Limitations #####
00009   ==============================================================================
00010     [..]
00011       A delay between an RCC peripheral clock enable and the effective peripheral
00012       enabling should be taken into account in order to manage the peripheral read/write
00013       from/to registers.
00014       (+) This delay depends on the peripheral mapping.
00015         (++) AHB & APB peripherals, 1 dummy read is necessary
00016
00017     [..]
00018       Workarounds:
00019       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00020           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * Copyright (c) 2018 STMicroelectronics.
00027   * All rights reserved.
00028   *
00029   * This software is licensed under terms that can be found in the LICENSE file in
00030   * the root directory of this software component.
00031   * If no LICENSE file comes with this software, it is provided AS-IS.
00032   ******************************************************************************
00033   */
00034
00035 /* Define to prevent recursive inclusion -------------------------------------*/
00036 #ifndef STM32G0xx_LL_BUS_H
00037 #define STM32G0xx_LL_BUS_H
00038
00039 #ifdef __cplusplus
00040 extern "C" {
00041 #endif
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32g0xx.h"
00045
00046 /** @addtogroup STM32G0xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined(RCC)
00051
00052 /** @defgroup BUS_LL BUS
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058
00059 /* Private constants ---------------------------------------------------------*/
00060
00061 /* Private macros ------------------------------------------------------------*/
00062
00063 /* Exported types ------------------------------------------------------------*/
00064 /* Exported constants --------------------------------------------------------*/
00065 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
00066   * @{
00067   */
00068
00069 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
00070   * @{
00071   */
00072 #define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
00073 #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHBENR_DMA1EN
00074 #if defined(DMA2)
00075 #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHBENR_DMA2EN
00076 #endif /* DMA2 */
00077 #define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHBENR_FLASHEN
00078 #define LL_AHB1_GRP1_PERIPH_SRAM           RCC_AHBSMENR_SRAMSMEN
00079 #if defined(CRC)
00080 #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHBENR_CRCEN
00081 #endif /* CRC */
00082 #if defined(AES)
00083 #define LL_AHB1_GRP1_PERIPH_CRYP           RCC_AHBENR_AESEN
00084 #endif /* AES */
00085 #if defined(RNG)
00086 #define LL_AHB1_GRP1_PERIPH_RNG            RCC_AHBENR_RNGEN
00087 #endif /* RNG */
00088 /**
00089   * @}
00090   */
00091
00092
00093 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
00094   * @{
00095   */
00096 #define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
00097 #if defined(TIM2)
00098 #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APBENR1_TIM2EN
00099 #endif /* TIM2 */
00100 #if defined(TIM3)
00101 #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APBENR1_TIM3EN
00102 #endif /* TIM3 */
00103 #if defined(TIM4)
00104 #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APBENR1_TIM4EN
00105 #endif /* TIM4 */
00106 #if defined(TIM6)
00107 #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APBENR1_TIM6EN
00108 #endif /* TIM6 */
00109 #if defined(TIM7)
00110 #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APBENR1_TIM7EN
00111 #endif /* TIM7 */
00112 #if defined(LPUART2)
00113 #define LL_APB1_GRP1_PERIPH_LPUART2        RCC_APBENR1_LPUART2EN
00114 #endif /* LPUART2 */
00115 #if defined(USART5)
00116 #define LL_APB1_GRP1_PERIPH_USART5         RCC_APBENR1_USART5EN
00117 #endif /* USART5 */
00118 #if defined(USART6)
00119 #define LL_APB1_GRP1_PERIPH_USART6         RCC_APBENR1_USART6EN
00120 #endif /* USART6 */
00121 #define LL_APB1_GRP1_PERIPH_RTC            RCC_APBENR1_RTCAPBEN
00122 #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APBENR1_WWDGEN
00123 #if defined(FDCAN1) || defined(FDCAN2)
00124 #define LL_APB1_GRP1_PERIPH_FDCAN          RCC_APBENR1_FDCANEN
00125 #endif /* FDCAN1 */
00126 #if defined(USB_DRD_FS)
00127 #define LL_APB1_GRP1_PERIPH_USB            RCC_APBENR1_USBEN
00128 #endif /* USB_DRD_FS */
00129 #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APBENR1_SPI2EN
00130 #if defined(SPI3)
00131 #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APBENR1_SPI3EN
00132 #endif /* SPI3 */
00133 #if defined(CRS)
00134 #define LL_APB1_GRP1_PERIPH_CRS            RCC_APBENR1_CRSEN
00135 #endif /* CRS */
00136 #define LL_APB1_GRP1_PERIPH_USART2         RCC_APBENR1_USART2EN
00137 #if defined(USART3)
00138 #define LL_APB1_GRP1_PERIPH_USART3         RCC_APBENR1_USART3EN
00139 #endif /* USART3 */
00140 #if defined(USART4)
00141 #define LL_APB1_GRP1_PERIPH_USART4         RCC_APBENR1_USART4EN
00142 #endif /* USART4 */
00143 #if defined(LPUART1)
00144 #define LL_APB1_GRP1_PERIPH_LPUART1        RCC_APBENR1_LPUART1EN
00145 #endif /* LPUART1 */
00146 #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APBENR1_I2C1EN
00147 #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APBENR1_I2C2EN
00148 #if defined(I2C3)
00149 #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APBENR1_I2C3EN
00150 #endif /* I2C3 */
00151 #if defined(CEC)
00152 #define LL_APB1_GRP1_PERIPH_CEC            RCC_APBENR1_CECEN
00153 #endif /* CEC */
00154 #if defined(UCPD1)
00155 #define LL_APB1_GRP1_PERIPH_UCPD1          RCC_APBENR1_UCPD1EN
00156 #endif /* UCPD1 */
00157 #if defined(UCPD2)
00158 #define LL_APB1_GRP1_PERIPH_UCPD2          RCC_APBENR1_UCPD2EN
00159 #endif /* UCPD2 */
00160 #define LL_APB1_GRP1_PERIPH_DBGMCU         RCC_APBENR1_DBGEN
00161 #define LL_APB1_GRP1_PERIPH_PWR            RCC_APBENR1_PWREN
00162 #if defined(DAC1)
00163 #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APBENR1_DAC1EN
00164 #endif /* DAC1 */
00165 #if defined(LPTIM2)
00166 #define LL_APB1_GRP1_PERIPH_LPTIM2         RCC_APBENR1_LPTIM2EN
00167 #endif /* LPTIM2 */
00168 #if defined(LPTIM1)
00169 #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APBENR1_LPTIM1EN
00170 #endif /* LPTIM1 */
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
00176   * @{
00177   */
00178 #define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
00179 #define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APBENR2_SYSCFGEN
00180 #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APBENR2_TIM1EN
00181 #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APBENR2_SPI1EN
00182 #define LL_APB2_GRP1_PERIPH_USART1         RCC_APBENR2_USART1EN
00183 #if defined(TIM14)
00184 #define LL_APB2_GRP1_PERIPH_TIM14          RCC_APBENR2_TIM14EN
00185 #endif /* TIM14 */
00186 #if defined(TIM15)
00187 #define LL_APB2_GRP1_PERIPH_TIM15          RCC_APBENR2_TIM15EN
00188 #endif /* TIM15 */
00189 #if defined(TIM16)
00190 #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APBENR2_TIM16EN
00191 #endif /* TIM16 */
00192 #if defined(TIM17)
00193 #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APBENR2_TIM17EN
00194 #endif /* TIM17 */
00195 #if defined(ADC)
00196 #define LL_APB2_GRP1_PERIPH_ADC            RCC_APBENR2_ADCEN
00197 #endif /* ADC */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH  IOP GRP1 PERIPH
00203   * @{
00204   */
00205 #define LL_IOP_GRP1_PERIPH_ALL             0xFFFFFFFFU
00206 #define LL_IOP_GRP1_PERIPH_GPIOA           RCC_IOPENR_GPIOAEN
00207 #define LL_IOP_GRP1_PERIPH_GPIOB           RCC_IOPENR_GPIOBEN
00208 #define LL_IOP_GRP1_PERIPH_GPIOC           RCC_IOPENR_GPIOCEN
00209 #define LL_IOP_GRP1_PERIPH_GPIOD           RCC_IOPENR_GPIODEN
00210 #if defined(GPIOE)
00211 #define LL_IOP_GRP1_PERIPH_GPIOE           RCC_IOPENR_GPIOEEN
00212 #endif /* GPIOE */
00213 #if defined(GPIOF)
00214 #define LL_IOP_GRP1_PERIPH_GPIOF           RCC_IOPENR_GPIOFEN
00215 #endif /* GPIOF */
00216 /**
00217   * @}
00218   */
00219
00220 /**
00221   * @}
00222   */
00223
00224 /* Exported macro ------------------------------------------------------------*/
00225 /* Exported functions --------------------------------------------------------*/
00226 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
00227   * @{
00228   */
00229
00230 /** @defgroup BUS_LL_EF_AHB1 AHB1
00231   * @{
00232   */
00233
00234 /**
00235   * @brief  Enable AHB1 peripherals clock.
00236   * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_EnableClock\n
00237   *         AHBENR       FLASHEN       LL_AHB1_GRP1_EnableClock\n
00238   *         AHBENR       CRCEN         LL_AHB1_GRP1_EnableClock\n
00239   *         AHBENR       AESEN         LL_AHB1_GRP1_EnableClock\n
00240   *         AHBENR       RNGEN         LL_AHB1_GRP1_EnableClock
00241   * @param  Periphs This parameter can be a combination of the following values:
00242   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00243   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00244   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00245   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
00246   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
00247   * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
00248   * @retval None
00249   */
00250 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
00251 {
00252   __IO uint32_t tmpreg;
00253   SET_BIT(RCC->AHBENR, Periphs);
00254   /* Delay after an RCC peripheral clock enabling */
00255   tmpreg = READ_BIT(RCC->AHBENR, Periphs);
00256   (void)tmpreg;
00257 }
00258
00259 /**
00260   * @brief  Check if AHB1 peripheral clock is enabled or not
00261   * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
00262   *         AHBENR       FLASHEN       LL_AHB1_GRP1_IsEnabledClock\n
00263   *         AHBENR       CRCEN         LL_AHB1_GRP1_IsEnabledClock\n
00264   *         AHBENR       AESEN         LL_AHB1_GRP1_IsEnabledClock\n
00265   *         AHBENR       RNGEN         LL_AHB1_GRP1_IsEnabledClock
00266   * @param  Periphs This parameter can be a combination of the following values:
00267   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00268   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00269   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00270   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
00271   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
00272   * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
00273   * @retval State of Periphs (1 or 0).
00274   */
00275 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
00276 {
00277   return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL);
00278 }
00279
00280 /**
00281   * @brief  Disable AHB1 peripherals clock.
00282   * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_DisableClock\n
00283   *         AHBENR       FLASHEN       LL_AHB1_GRP1_DisableClock\n
00284   *         AHBENR       CRCEN         LL_AHB1_GRP1_DisableClock\n
00285   *         AHBENR       AESEN         LL_AHB1_GRP1_DisableClock\n
00286   *         AHBENR       RNGEN         LL_AHB1_GRP1_DisableClock
00287   * @param  Periphs This parameter can be a combination of the following values:
00288   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00289   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00290   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00291   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
00292   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
00293   * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
00294   * @retval None
00295   */
00296 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
00297 {
00298   CLEAR_BIT(RCC->AHBENR, Periphs);
00299 }
00300
00301 /**
00302   * @brief  Force AHB1 peripherals reset.
00303   * @rmtoll AHBRSTR      DMA1RST       LL_AHB1_GRP1_ForceReset\n
00304   *         AHBRSTR      FLASHRST      LL_AHB1_GRP1_ForceReset\n
00305   *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ForceReset\n
00306   *         AHBRSTR      AESRST        LL_AHB1_GRP1_ForceReset\n
00307   *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ForceReset
00308   * @param  Periphs This parameter can be a combination of the following values:
00309   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00310   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00311   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00312   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00313   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
00314   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
00315   * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
00316   * @retval None
00317   */
00318 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
00319 {
00320   SET_BIT(RCC->AHBRSTR, Periphs);
00321 }
00322
00323 /**
00324   * @brief  Release AHB1 peripherals reset.
00325   * @rmtoll AHBRSTR      DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
00326   *         AHBRSTR      FLASHRST      LL_AHB1_GRP1_ReleaseReset\n
00327   *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ReleaseReset\n
00328   *         AHBRSTR      AESRST        LL_AHB1_GRP1_ReleaseReset\n
00329   *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ReleaseReset
00330   * @param  Periphs This parameter can be a combination of the following values:
00331   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00332   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00333   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00334   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00335   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
00336   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
00337   * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
00338   * @retval None
00339   */
00340 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
00341 {
00342   CLEAR_BIT(RCC->AHBRSTR, Periphs);
00343 }
00344
00345 /**
00346   * @brief  Enable AHB1 peripheral clocks in Sleep and Stop modes
00347   * @rmtoll AHBSMENR     DMA1SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
00348   *         AHBSMENR     FLASHSMEN     LL_AHB1_GRP1_EnableClockStopSleep\n
00349   *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
00350   *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_EnableClockStopSleep\n
00351   *         AHBSMENR     AESSMEN       LL_AHB1_GRP1_EnableClockStopSleep\n
00352   *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_EnableClockStopSleep
00353   * @param  Periphs This parameter can be a combination of the following values:
00354   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00355   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00356   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
00357   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00358   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
00359   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
00360   * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
00361   * @retval None
00362   */
00363 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
00364 {
00365   __IO uint32_t tmpreg;
00366   SET_BIT(RCC->AHBSMENR, Periphs);
00367   /* Delay after an RCC peripheral clock enabling */
00368   tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
00369   (void)tmpreg;
00370 }
00371
00372 /**
00373   * @brief  Disable AHB1 peripheral clocks in Sleep and Stop modes
00374   * @rmtoll AHBSMENR     DMA1SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
00375   *         AHBSMENR     FLASHSMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
00376   *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
00377   *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_DisableClockStopSleep\n
00378   *         AHBSMENR     AESSMEN       LL_AHB1_GRP1_DisableClockStopSleep\n
00379   *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_DisableClockStopSleep
00380   * @param  Periphs This parameter can be a combination of the following values:
00381   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00382   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00383   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
00384   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00385   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
00386   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
00387   * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
00388   * @retval None
00389   */
00390 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
00391 {
00392   CLEAR_BIT(RCC->AHBSMENR, Periphs);
00393 }
00394
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup BUS_LL_EF_APB1 APB1
00400   * @{
00401   */
00402
00403 /**
00404   * @brief  Enable APB1 peripherals clock.
00405   * @rmtoll APBENR1      TIM2EN        LL_APB1_GRP1_EnableClock\n
00406   *         APBENR1      TIM3EN        LL_APB1_GRP1_EnableClock\n
00407   *         APBENR1      TIM4EN        LL_APB1_GRP1_EnableClock\n
00408   *         APBENR1      TIM6EN        LL_APB1_GRP1_EnableClock\n
00409   *         APBENR1      TIM7EN        LL_APB1_GRP1_EnableClock\n
00410   *         APBENR1      RTCAPBEN      LL_APB1_GRP1_EnableClock\n
00411   *         APBENR1      WWDGEN        LL_APB1_GRP1_EnableClock\n
00412   *         APBENR1      SPI2EN        LL_APB1_GRP1_EnableClock\n
00413   *         APBENR1      SPI3EN        LL_APB1_GRP1_EnableClock\n
00414   *         APBENR1      USART2EN      LL_APB1_GRP1_EnableClock\n
00415   *         APBENR1      USART3EN      LL_APB1_GRP1_EnableClock\n
00416   *         APBENR1      USART4EN      LL_APB1_GRP1_EnableClock\n
00417   *         APBENR1      USART5EN      LL_APB1_GRP1_EnableClock\n
00418   *         APBENR1      USART6EN      LL_APB1_GRP1_EnableClock\n
00419   *         APBENR1      LPUART1EN     LL_APB1_GRP1_EnableClock\n
00420   *         APBENR1      LPUART2EN     LL_APB1_GRP1_EnableClock\n
00421   *         APBENR1      I2C1EN        LL_APB1_GRP1_EnableClock\n
00422   *         APBENR1      I2C2EN        LL_APB1_GRP1_EnableClock\n
00423   *         APBENR1      I2C3EN        LL_APB1_GRP1_EnableClock\n
00424   *         APBENR1      CECEN         LL_APB1_GRP1_EnableClock\n
00425   *         APBENR1      UCPD1EN       LL_APB1_GRP1_EnableClock\n
00426   *         APBENR1      UCPD2EN       LL_APB1_GRP1_EnableClock\n
00427   *         APBENR1      USBEN         LL_APB1_GRP1_EnableClock\n
00428   *         APBENR1      FDCANEN       LL_APB1_GRP1_EnableClock\n
00429   *         APBENR1      DBGEN         LL_APB1_GRP1_EnableClock\n
00430   *         APBENR1      PWREN         LL_APB1_GRP1_EnableClock\n
00431   *         APBENR1      DAC1EN        LL_APB1_GRP1_EnableClock\n
00432   *         APBENR1      LPTIM2EN      LL_APB1_GRP1_EnableClock\n
00433   *         APBENR1      LPTIM1EN      LL_APB1_GRP1_EnableClock
00434   * @param  Periphs This parameter can be a combination of the following values:
00435   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
00436   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00437   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
00438   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
00439   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
00440   *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
00441   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00442   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00443   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
00444   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00445   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
00446   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
00447   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
00448   *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
00449   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
00450   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
00451   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00452   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00453   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
00454   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
00455   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
00456   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
00457   *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
00458   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
00459   *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
00460   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00461   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
00462   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
00463   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
00464   * @note Peripheral marked with (1) are not available all devices
00465   * @retval None
00466   */
00467 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
00468 {
00469   __IO uint32_t tmpreg;
00470   SET_BIT(RCC->APBENR1, Periphs);
00471   /* Delay after an RCC peripheral clock enabling */
00472   tmpreg = READ_BIT(RCC->APBENR1, Periphs);
00473   (void)tmpreg;
00474 }
00475
00476 /**
00477   * @brief  Check if APB1 peripheral clock is enabled or not
00478   * @rmtoll APBENR1      TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
00479   *         APBENR1      TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
00480   *         APBENR1      TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
00481   *         APBENR1      TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
00482   *         APBENR1      TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
00483   *         APBENR1      RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n
00484   *         APBENR1      WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
00485   *         APBENR1      SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
00486   *         APBENR1      SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
00487   *         APBENR1      USART2EN      LL_APB1_GRP1_IsEnabledClock\n
00488   *         APBENR1      USART3EN      LL_APB1_GRP1_IsEnabledClock\n
00489   *         APBENR1      USART4EN      LL_APB1_GRP1_IsEnabledClock\n
00490   *         APBENR1      USART5EN      LL_APB1_GRP1_IsEnabledClock\n
00491   *         APBENR1      USART6EN      LL_APB1_GRP1_IsEnabledClock\n
00492   *         APBENR1      LPUART1EN     LL_APB1_GRP1_IsEnabledClock\n
00493   *         APBENR1      LPUART2EN     LL_APB1_GRP1_IsEnabledClock\n
00494   *         APBENR1      I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
00495   *         APBENR1      I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
00496   *         APBENR1      I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
00497   *         APBENR1      CECEN         LL_APB1_GRP1_IsEnabledClock\n
00498   *         APBENR1      UCPD1EN       LL_APB1_GRP1_IsEnabledClock\n
00499   *         APBENR1      UCPD2EN       LL_APB1_GRP1_IsEnabledClock\n
00500   *         APBENR1      USBEN         LL_APB1_GRP1_IsEnabledClock\n
00501   *         APBENR1      FDCANEN       LL_APB1_GRP1_IsEnabledClock\n
00502   *         APBENR1      DBGEN         LL_APB1_GRP1_IsEnabledClock\n
00503   *         APBENR1      PWREN         LL_APB1_GRP1_IsEnabledClock\n
00504   *         APBENR1      DAC1EN        LL_APB1_GRP1_IsEnabledClock\n
00505   *         APBENR1      LPTIM2EN      LL_APB1_GRP1_IsEnabledClock\n
00506   *         APBENR1      LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
00507   * @param  Periphs This parameter can be a combination of the following values:
00508   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
00509   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00510   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
00511   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
00512   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
00513   *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
00514   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00515   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00516   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
00517   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00518   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
00519   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
00520   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
00521   *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
00522   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
00523   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
00524   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00525   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00526   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
00527   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
00528   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
00529   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
00530   *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
00531   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
00532   *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
00533   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00534   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
00535   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
00536   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
00537   * @note Peripheral marked with (1) are not available all devices
00538   * @retval State of Periphs (1 or 0).
00539   */
00540 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
00541 {
00542   return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
00543 }
00544
00545 /**
00546   * @brief  Disable APB1 peripherals clock.
00547   * @rmtoll APBENR1      TIM2EN        LL_APB1_GRP1_DisableClock\n
00548   *         APBENR1      TIM3EN        LL_APB1_GRP1_DisableClock\n
00549   *         APBENR1      TIM4EN        LL_APB1_GRP1_DisableClock\n
00550   *         APBENR1      TIM6EN        LL_APB1_GRP1_DisableClock\n
00551   *         APBENR1      TIM7EN        LL_APB1_GRP1_DisableClock\n
00552   *         APBENR1      RTCAPBEN      LL_APB1_GRP1_DisableClock\n
00553   *         APBENR1      WWDGEN        LL_APB1_GRP1_DisableClock\n
00554   *         APBENR1      SPI2EN        LL_APB1_GRP1_DisableClock\n
00555   *         APBENR1      SPI3EN        LL_APB1_GRP1_DisableClock\n
00556   *         APBENR1      USART2EN      LL_APB1_GRP1_DisableClock\n
00557   *         APBENR1      USART3EN      LL_APB1_GRP1_DisableClock\n
00558   *         APBENR1      USART4EN      LL_APB1_GRP1_DisableClock\n
00559   *         APBENR1      USART5EN      LL_APB1_GRP1_DisableClock\n
00560   *         APBENR1      USART6EN      LL_APB1_GRP1_DisableClock\n
00561   *         APBENR1      LPUART1EN     LL_APB1_GRP1_DisableClock\n
00562   *         APBENR1      LPUART2EN     LL_APB1_GRP1_DisableClock\n
00563   *         APBENR1      I2C1EN        LL_APB1_GRP1_DisableClock\n
00564   *         APBENR1      I2C2EN        LL_APB1_GRP1_DisableClock\n
00565   *         APBENR1      I2C3EN        LL_APB1_GRP1_DisableClock\n
00566   *         APBENR1      CECEN         LL_APB1_GRP1_DisableClock\n
00567   *         APBENR1      UCPD1EN       LL_APB1_GRP1_DisableClock\n
00568   *         APBENR1      UCPD2EN       LL_APB1_GRP1_DisableClock\n
00569   *         APBENR1      USBEN         LL_APB1_GRP1_DisableClock\n
00570   *         APBENR1      FDCANEN       LL_APB1_GRP1_DisableClock\n
00571   *         APBENR1      DBGEN         LL_APB1_GRP1_DisableClock\n
00572   *         APBENR1      PWREN         LL_APB1_GRP1_DisableClock\n
00573   *         APBENR1      DAC1EN        LL_APB1_GRP1_DisableClock\n
00574   *         APBENR1      LPTIM2EN      LL_APB1_GRP1_DisableClock\n
00575   *         APBENR1      LPTIM1EN      LL_APB1_GRP1_DisableClock
00576   * @param  Periphs This parameter can be a combination of the following values:
00577   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
00578   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00579   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
00580   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
00581   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
00582   *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
00583   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00584   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00585   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
00586   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00587   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
00588   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
00589   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
00590   *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
00591   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
00592   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
00593   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00594   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00595   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
00596   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
00597   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
00598   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
00599   *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
00600   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
00601   *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
00602   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00603   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
00604   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
00605   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
00606   * @note Peripheral marked with (1) are not available all devices
00607   * @retval None
00608   */
00609 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
00610 {
00611   CLEAR_BIT(RCC->APBENR1, Periphs);
00612 }
00613
00614 /**
00615   * @brief  Force APB1 peripherals reset.
00616   * @rmtoll APBRSTR1     TIM2RST       LL_APB1_GRP1_ForceReset\n
00617   *         APBRSTR1     TIM3RST       LL_APB1_GRP1_ForceReset\n
00618   *         APBRSTR1     TIM4RST       LL_APB1_GRP1_ForceReset\n
00619   *         APBRSTR1     TIM6RST       LL_APB1_GRP1_ForceReset\n
00620   *         APBRSTR1     TIM7RST       LL_APB1_GRP1_ForceReset\n
00621   *         APBRSTR1     RTCRST        LL_APB1_GRP1_ForceReset\n
00622   *         APBRSTR1     SPI2RST       LL_APB1_GRP1_ForceReset\n
00623   *         APBRSTR1     SPI3RST       LL_APB1_GRP1_ForceReset\n
00624   *         APBRSTR1     USART2RST     LL_APB1_GRP1_ForceReset\n
00625   *         APBRSTR1     USART3RST     LL_APB1_GRP1_ForceReset\n
00626   *         APBRSTR1     USART4RST     LL_APB1_GRP1_ForceReset\n
00627   *         APBRSTR1     USART5RST     LL_APB1_GRP1_ForceReset\n
00628   *         APBRSTR1     USART6RST     LL_APB1_GRP1_ForceReset\n
00629   *         APBRSTR1     LPUART1RST    LL_APB1_GRP1_ForceReset\n
00630   *         APBRSTR1     LPUART2RST    LL_APB1_GRP1_ForceReset\n
00631   *         APBRSTR1     I2C1RST       LL_APB1_GRP1_ForceReset\n
00632   *         APBRSTR1     I2C2RST       LL_APB1_GRP1_ForceReset\n
00633   *         APBRSTR1     I2C3RST       LL_APB1_GRP1_ForceReset\n
00634   *         APBRSTR1     CECRST        LL_APB1_GRP1_ForceReset\n
00635   *         APBRSTR1     UCPD1RST      LL_APB1_GRP1_ForceReset\n
00636   *         APBRSTR1     UCPD2RST      LL_APB1_GRP1_ForceReset\n
00637   *         APBRSTR1     USBRST        LL_APB1_GRP1_ForceReset\n
00638   *         APBRSTR1     FDCANRST      LL_APB1_GRP1_ForceReset\n
00639   *         APBRSTR1     DBGRST        LL_APB1_GRP1_ForceReset\n
00640   *         APBRSTR1     PWRRST        LL_APB1_GRP1_ForceReset\n
00641   *         APBRSTR1     DAC1RST       LL_APB1_GRP1_ForceReset\n
00642   *         APBRSTR1     LPTIM2RST     LL_APB1_GRP1_ForceReset\n
00643   *         APBRSTR1     LPTIM1RST     LL_APB1_GRP1_ForceReset
00644   * @param  Periphs This parameter can be a combination of the following values:
00645   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
00646   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00647   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
00648   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
00649   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
00650   *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
00651   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00652   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
00653   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00654   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
00655   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
00656   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
00657   *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
00658   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
00659   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
00660   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00661   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00662   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
00663   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
00664   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
00665   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
00666   *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
00667   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
00668   *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
00669   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00670   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
00671   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
00672   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
00673   * @note Peripheral marked with (1) are not available all devices
00674   * @retval None
00675   */
00676 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
00677 {
00678   SET_BIT(RCC->APBRSTR1, Periphs);
00679 }
00680
00681 /**
00682   * @brief  Release APB1 peripherals reset.
00683   * @rmtoll APBRSTR1     TIM2RST       LL_APB1_GRP1_ReleaseReset\n
00684   *         APBRSTR1     TIM4RST       LL_APB1_GRP1_ReleaseReset\n
00685   *         APBRSTR1     TIM6RST       LL_APB1_GRP1_ReleaseReset\n
00686   *         APBRSTR1     TIM7RST       LL_APB1_GRP1_ReleaseReset\n
00687   *         APBRSTR1     RTCRST        LL_APB1_GRP1_ReleaseReset\n
00688   *         APBRSTR1     SPI2RST       LL_APB1_GRP1_ReleaseReset\n
00689   *         APBRSTR1     SPI3RST       LL_APB1_GRP1_ReleaseReset\n
00690   *         APBRSTR1     USART2RST     LL_APB1_GRP1_ReleaseReset\n
00691   *         APBRSTR1     USART3RST     LL_APB1_GRP1_ReleaseReset\n
00692   *         APBRSTR1     USART4RST     LL_APB1_GRP1_ReleaseReset\n
00693   *         APBRSTR1     USART5RST     LL_APB1_GRP1_ReleaseReset\n
00694   *         APBRSTR1     USART6RST     LL_APB1_GRP1_ReleaseReset\n
00695   *         APBRSTR1     LPUART1RST    LL_APB1_GRP1_ReleaseReset\n
00696   *         APBRSTR1     LPUART2RST    LL_APB1_GRP1_ReleaseReset\n
00697   *         APBRSTR1     I2C1RST       LL_APB1_GRP1_ReleaseReset\n
00698   *         APBRSTR1     I2C2RST       LL_APB1_GRP1_ReleaseReset\n
00699   *         APBRSTR1     I2C3RST       LL_APB1_GRP1_ReleaseReset\n
00700   *         APBRSTR1     CECRST        LL_APB1_GRP1_ReleaseReset\n
00701   *         APBRSTR1     UCPD1RST      LL_APB1_GRP1_ReleaseReset\n
00702   *         APBRSTR1     UCPD2RST      LL_APB1_GRP1_ReleaseReset\n
00703   *         APBRSTR1     USBRST        LL_APB1_GRP1_ReleaseReset\n
00704   *         APBRSTR1     FDCANRST      LL_APB1_GRP1_ReleaseReset\n
00705   *         APBRSTR1     DBGRST        LL_APB1_GRP1_ReleaseReset\n
00706   *         APBRSTR1     PWRRST        LL_APB1_GRP1_ReleaseReset\n
00707   *         APBRSTR1     DAC1RST       LL_APB1_GRP1_ReleaseReset\n
00708   *         APBRSTR1     LPTIM2RST     LL_APB1_GRP1_ReleaseReset\n
00709   *         APBRSTR1     LPTIM1RST     LL_APB1_GRP1_ReleaseReset
00710   * @param  Periphs This parameter can be a combination of the following values:
00711   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
00712   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00713   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
00714   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
00715   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
00716   *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
00717   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00718   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
00719   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00720   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
00721   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
00722   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
00723   *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
00724   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
00725   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
00726   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00727   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00728   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
00729   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
00730   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
00731   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
00732   *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
00733   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
00734   *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
00735   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00736   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
00737   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
00738   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
00739   * @note Peripheral marked with (1) are not available all devices
00740   * @retval None
00741   */
00742 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
00743 {
00744   CLEAR_BIT(RCC->APBRSTR1, Periphs);
00745 }
00746
00747 /**
00748   * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
00749   * @rmtoll APBSMENR1    TIM2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00750   *         APBSMENR1    TIM3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00751   *         APBSMENR1    TIM4SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00752   *         APBSMENR1    TIM6SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00753   *         APBSMENR1    TIM7SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00754   *         APBSMENR1    RTCAPBSMEN    LL_APB1_GRP1_EnableClockStopSleep\n
00755   *         APBSMENR1    WWDGSMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00756   *         APBSMENR1    SPI2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00757   *         APBSMENR1    SPI3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00758   *         APBSMENR1    USART2SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
00759   *         APBSMENR1    USART3SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
00760   *         APBSMENR1    USART4SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
00761   *         APBSMENR1    USART5SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
00762   *         APBSMENR1    USART6SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
00763   *         APBSMENR1    LPUART1SMEN   LL_APB1_GRP1_EnableClockStopSleep\n
00764   *         APBSMENR1    LPUART2SMEN   LL_APB1_GRP1_EnableClockStopSleep\n
00765   *         APBSMENR1    I2C1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00766   *         APBSMENR1    I2C2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00767   *         APBSMENR1    I2C3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00768   *         APBSMENR1    CECSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
00769   *         APBSMENR1    UCPD1SMEN     LL_APB1_GRP1_EnableClockStopSleep\n
00770   *         APBSMENR1    UCPD2SMEN     LL_APB1_GRP1_EnableClockStopSleep\n
00771   *         APBSMENR1    USBSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
00772   *         APBSMENR1    FDCANSMEN     LL_APB1_GRP1_EnableClockStopSleep\n
00773   *         APBSMENR1    DBGSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
00774   *         APBSMENR1    PWRSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
00775   *         APBSMENR1    DAC1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
00776   *         APBSMENR1    LPTIM2SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
00777   *         APBSMENR1    LPTIM1SMEN    LL_APB1_GRP1_EnableClockStopSleep
00778   * @param  Periphs This parameter can be a combination of the following values:
00779   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
00780   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00781   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
00782   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
00783   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
00784   *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
00785   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00786   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00787   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
00788   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00789   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
00790   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
00791   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
00792   *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
00793   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
00794   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
00795   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00796   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00797   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
00798   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
00799   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
00800   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
00801   *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
00802   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
00803   *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
00804   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00805   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
00806   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
00807   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
00808   * @note Peripheral marked with (1) are not available all devices
00809   * @retval None
00810   */
00811 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
00812 {
00813   __IO uint32_t tmpreg;
00814   SET_BIT(RCC->APBSMENR1, Periphs);
00815   /* Delay after an RCC peripheral clock enabling */
00816   tmpreg = READ_BIT(RCC->APBSMENR1, Periphs);
00817   (void)tmpreg;
00818 }
00819
00820 /**
00821   * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
00822   * @rmtoll APBSMENR1    TIM2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00823   *         APBSMENR1    TIM3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00824   *         APBSMENR1    TIM'SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00825   *         APBSMENR1    TIM6SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00826   *         APBSMENR1    TIM7SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00827   *         APBSMENR1    RTCAPBSMEN    LL_APB1_GRP1_DisableClockStopSleep\n
00828   *         APBSMENR1    WWDGSMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00829   *         APBSMENR1    SPI2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00830   *         APBSMENR1    SPI3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00831   *         APBSMENR1    USART2SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
00832   *         APBSMENR1    USART3SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
00833   *         APBSMENR1    USART4SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
00834   *         APBSMENR1    USART5SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
00835   *         APBSMENR1    USART6SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
00836   *         APBSMENR1    LPUART1SMEN   LL_APB1_GRP1_DisableClockStopSleep\n
00837   *         APBSMENR1    LPUART2SMEN   LL_APB1_GRP1_DisableClockStopSleep\n
00838   *         APBSMENR1    I2C1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00839   *         APBSMENR1    I2C2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00840   *         APBSMENR1    I2C3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00841   *         APBSMENR1    CECSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
00842   *         APBSMENR1    UCPD1SMEN     LL_APB1_GRP1_DisableClockStopSleep\n
00843   *         APBSMENR1    UCPD2SMEN     LL_APB1_GRP1_DisableClockStopSleep\n
00844   *         APBSMENR1    USBSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
00845   *         APBSMENR1    FSCANSMEN     LL_APB1_GRP1_DisableClockStopSleep\n
00846   *         APBSMENR1    DBGSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
00847   *         APBSMENR1    PWRSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
00848   *         APBSMENR1    DAC1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
00849   *         APBSMENR1    LPTIM2SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
00850   *         APBSMENR1    LPTIM1SMEN    LL_APB1_GRP1_DisableClockStopSleep
00851   * @param  Periphs This parameter can be a combination of the following values:
00852   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
00853   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00854   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
00855   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
00856   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
00857   *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
00858   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00859   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00860   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
00861   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00862   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
00863   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
00864   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
00865   *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
00866   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
00867   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
00868   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00869   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
00870   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
00871   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
00872   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
00873   *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
00874   *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
00875   *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
00876   *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
00877   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00878   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
00879   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
00880   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
00881   * @note Peripheral marked with (1) are not available all devices
00882   * @retval None
00883   */
00884 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
00885 {
00886   CLEAR_BIT(RCC->APBSMENR1, Periphs);
00887 }
00888
00889 /**
00890   * @}
00891   */
00892
00893 /** @defgroup BUS_LL_EF_APB2 APB2
00894   * @{
00895   */
00896
00897 /**
00898   * @brief  Enable APB2 peripherals clock.
00899   * @rmtoll APBENR2      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
00900   *         APBENR2      TIM1EN        LL_APB2_GRP1_EnableClock\n
00901   *         APBENR2      SPI1EN        LL_APB2_GRP1_EnableClock\n
00902   *         APBENR2      USART1EN      LL_APB2_GRP1_EnableClock\n
00903   *         APBENR2      TIM14EN       LL_APB2_GRP1_EnableClock\n
00904   *         APBENR2      TIM15EN       LL_APB2_GRP1_EnableClock\n
00905   *         APBENR2      TIM16EN       LL_APB2_GRP1_EnableClock\n
00906   *         APBENR2      TIM17EN       LL_APB2_GRP1_EnableClock\n
00907   *         APBENR2      ADCEN         LL_APB2_GRP1_EnableClock
00908   * @param  Periphs This parameter can be a combination of the following values:
00909   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
00910   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
00911   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
00912   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00913   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
00914   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
00915   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
00916   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
00917   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
00918   * @note (*) peripheral not available on all devices
00919   * @retval None
00920   */
00921 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
00922 {
00923   __IO uint32_t tmpreg;
00924   SET_BIT(RCC->APBENR2, Periphs);
00925   /* Delay after an RCC peripheral clock enabling */
00926   tmpreg = READ_BIT(RCC->APBENR2, Periphs);
00927   (void)tmpreg;
00928 }
00929
00930 /**
00931   * @brief  Check if APB2 peripheral clock is enabled or not
00932   * @rmtoll APBENR2      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
00933   *         APBENR2      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
00934   *         APBENR2      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
00935   *         APBENR2      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
00936   *         APBENR2      TIM14EN       LL_APB2_GRP1_IsEnabledClock\n
00937   *         APBENR2      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
00938   *         APBENR2      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
00939   *         APBENR2      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
00940   *         APBENR2      ADCEN         LL_APB2_GRP1_IsEnabledClock
00941   * @param  Periphs This parameter can be a combination of the following values:
00942   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
00943   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
00944   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
00945   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00946   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
00947   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
00948   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
00949   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
00950   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
00951   * @note (*) peripheral not available on all devices
00952   * @retval State of Periphs (1 or 0).
00953   */
00954 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
00955 {
00956   return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
00957 }
00958
00959 /**
00960   * @brief  Disable APB2 peripherals clock.
00961   * @rmtoll APBENR2      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
00962   *         APBENR2      TIM1EN        LL_APB2_GRP1_DisableClock\n
00963   *         APBENR2      SPI1EN        LL_APB2_GRP1_DisableClock\n
00964   *         APBENR2      USART1EN      LL_APB2_GRP1_DisableClock\n
00965   *         APBENR2      TIM14EN       LL_APB2_GRP1_DisableClock\n
00966   *         APBENR2      TIM15EN       LL_APB2_GRP1_DisableClock\n
00967   *         APBENR2      TIM16EN       LL_APB2_GRP1_DisableClock\n
00968   *         APBENR2      TIM17EN       LL_APB2_GRP1_DisableClock\n
00969   *         APBENR2      ADCEN         LL_APB2_GRP1_DisableClock
00970   * @param  Periphs This parameter can be a combination of the following values:
00971   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
00972   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
00973   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
00974   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00975   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
00976   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
00977   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
00978   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
00979   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
00980   * @note (*) peripheral not available on all devices
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
00984 {
00985   CLEAR_BIT(RCC->APBENR2, Periphs);
00986 }
00987
00988 /**
00989   * @brief  Force APB2 peripherals reset.
00990   * @rmtoll APBRSTR2     SYSCFGRST     LL_APB2_GRP1_ForceReset\n
00991   *         APBRSTR2     TIM1RST       LL_APB2_GRP1_ForceReset\n
00992   *         APBRSTR2     SPI1RST       LL_APB2_GRP1_ForceReset\n
00993   *         APBRSTR2     USART1RST     LL_APB2_GRP1_ForceReset\n
00994   *         APBRSTR2     TIM14RST      LL_APB2_GRP1_ForceReset\n
00995   *         APBRSTR2     TIM15RST      LL_APB2_GRP1_ForceReset\n
00996   *         APBRSTR2     TIM16RST      LL_APB2_GRP1_ForceReset\n
00997   *         APBRSTR2     TIM17RST      LL_APB2_GRP1_ForceReset\n
00998   *         APBRSTR2     ADCRST        LL_APB2_GRP1_ForceReset
00999   * @param  Periphs This parameter can be a combination of the following values:
01000   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
01001   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01002   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01003   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01004   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01005   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
01006   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
01007   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01008   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01009   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
01010   * @note (*) peripheral not available on all devices
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
01014 {
01015   SET_BIT(RCC->APBRSTR2, Periphs);
01016 }
01017
01018 /**
01019   * @brief  Release APB2 peripherals reset.
01020   * @rmtoll APBRSTR2     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n
01021   *         APBRSTR2     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
01022   *         APBRSTR2     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
01023   *         APBRSTR2     USART1RST     LL_APB2_GRP1_ReleaseReset\n
01024   *         APBRSTR2     TIM14RST      LL_APB2_GRP1_ReleaseReset\n
01025   *         APBRSTR2     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
01026   *         APBRSTR2     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
01027   *         APBRSTR2     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
01028   *         APBRSTR2     ADCRST        LL_APB2_GRP1_ReleaseReset
01029   * @param  Periphs This parameter can be a combination of the following values:
01030   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
01031   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01032   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01033   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01034   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01035   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
01036   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
01037   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01038   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01039   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
01040   * @note (*) peripheral not available on all devices
01041   * @retval None
01042   */
01043 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
01044 {
01045   CLEAR_BIT(RCC->APBRSTR2, Periphs);
01046 }
01047
01048 /**
01049   * @brief  Enable APB2 peripheral clocks in Sleep and Stop modes
01050   * @rmtoll APBSMENR2    SYSCFGSMEN    LL_APB2_GRP1_EnableClockStopSleep\n
01051   *         APBSMENR2    TIM1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01052   *         APBSMENR2    SPI1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01053   *         APBSMENR2    USART1SMEN    LL_APB2_GRP1_EnableClockStopSleep\n
01054   *         APBSMENR2    TIM14SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
01055   *         APBSMENR2    TIM15SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
01056   *         APBSMENR2    TIM16SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
01057   *         APBSMENR2    TIM17SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
01058   *         APBSMENR2    ADCSMEN       LL_APB2_GRP1_EnableClockStopSleep
01059   * @param  Periphs This parameter can be a combination of the following values:
01060   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01061   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01062   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01063   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01064   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
01065   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
01066   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01067   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01068   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
01069   * @note (*) peripheral not available on all devices
01070   * @retval None
01071   */
01072 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
01073 {
01074   __IO uint32_t tmpreg;
01075   SET_BIT(RCC->APBSMENR2, Periphs);
01076   /* Delay after an RCC peripheral clock enabling */
01077   tmpreg = READ_BIT(RCC->APBSMENR2, Periphs);
01078   (void)tmpreg;
01079 }
01080
01081 /**
01082   * @brief  Disable APB2 peripheral clocks in Sleep and Stop modes
01083   * @rmtoll APBSMENR2    SYSCFGSMEN    LL_APB2_GRP1_DisableClockStopSleep\n
01084   *         APBSMENR2    TIM1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01085   *         APBSMENR2    SPI1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01086   *         APBSMENR2    USART1SMEN    LL_APB2_GRP1_DisableClockStopSleep\n
01087   *         APBSMENR2    TIM14SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
01088   *         APBSMENR2    TIM15SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
01089   *         APBSMENR2    TIM16SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
01090   *         APBSMENR2    TIM17SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
01091   *         APBSMENR2    ADCSMEN       LL_APB2_GRP1_DisableClockStopSleep
01092   * @param  Periphs This parameter can be a combination of the following values:
01093   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01094   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01095   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01096   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01097   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
01098   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
01099   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01100   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01101   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
01102   * @note (*) peripheral not available on all devices
01103   * @retval None
01104   */
01105 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
01106 {
01107   CLEAR_BIT(RCC->APBSMENR2, Periphs);
01108 }
01109
01110 /**
01111   * @}
01112   */
01113
01114 /** @defgroup BUS_LL_EF_IOP IOP
01115   * @{
01116   */
01117
01118 /**
01119   * @brief  Enable IOP peripherals clock.
01120   * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_EnableClock\n
01121   *         IOPENR       GPIOBEN       LL_IOP_GRP1_EnableClock\n
01122   *         IOPENR       GPIOCEN       LL_IOP_GRP1_EnableClock\n
01123   *         IOPENR       GPIODEN       LL_IOP_GRP1_EnableClock\n
01124   *         IOPENR       GPIOEEN       LL_IOP_GRP1_EnableClock\n
01125   *         IOPENR       GPIOFEN       LL_IOP_GRP1_EnableClock
01126   * @param  Periphs This parameter can be a combination of the following values:
01127   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
01128   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
01129   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
01130   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
01131   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
01132   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
01133   * @retval None
01134   */
01135 __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
01136 {
01137   __IO uint32_t tmpreg;
01138   SET_BIT(RCC->IOPENR, Periphs);
01139   /* Delay after an RCC peripheral clock enabling */
01140   tmpreg = READ_BIT(RCC->IOPENR, Periphs);
01141   (void)tmpreg;
01142 }
01143
01144 /**
01145   * @brief  Check if IOP peripheral clock is enabled or not
01146   * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_IsEnabledClock\n
01147   *         IOPENR       GPIOBEN       LL_IOP_GRP1_IsEnabledClock\n
01148   *         IOPENR       GPIOCEN       LL_IOP_GRP1_IsEnabledClock\n
01149   *         IOPENR       GPIODEN       LL_IOP_GRP1_IsEnabledClock\n
01150   *         IOPENR       GPIOEEN       LL_IOP_GRP1_IsEnabledClock\n
01151   *         IOPENR       GPIOFEN       LL_IOP_GRP1_IsEnabledClock
01152   * @param  Periphs This parameter can be a combination of the following values:
01153   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
01154   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
01155   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
01156   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
01157   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
01158   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
01159   * @retval State of Periphs (1 or 0).
01160   */
01161 __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
01162 {
01163   return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
01164 }
01165
01166 /**
01167   * @brief  Disable IOP peripherals clock.
01168   * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_DisableClock\n
01169   *         IOPENR       GPIOBEN       LL_IOP_GRP1_DisableClock\n
01170   *         IOPENR       GPIOCEN       LL_IOP_GRP1_DisableClock\n
01171   *         IOPENR       GPIODEN       LL_IOP_GRP1_DisableClock\n
01172   *         IOPENR       GPIOEEN       LL_IOP_GRP1_DisableClock\n
01173   *         IOPENR       GPIOFEN       LL_IOP_GRP1_DisableClock
01174   * @param  Periphs This parameter can be a combination of the following values:
01175   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
01176   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
01177   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
01178   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
01179   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
01180   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
01181   * @retval None
01182   */
01183 __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
01184 {
01185   CLEAR_BIT(RCC->IOPENR, Periphs);
01186 }
01187
01188 /**
01189   * @brief  Disable IOP peripherals clock.
01190   * @rmtoll IOPRSTR      GPIOARST      LL_IOP_GRP1_ForceReset\n
01191   *         IOPRSTR      GPIOBRST      LL_IOP_GRP1_ForceReset\n
01192   *         IOPRSTR      GPIOCRST      LL_IOP_GRP1_ForceReset\n
01193   *         IOPRSTR      GPIODRST      LL_IOP_GRP1_ForceReset\n
01194   *         IOPRSTR      GPIOERST      LL_IOP_GRP1_ForceReset\n
01195   *         IOPRSTR      GPIOFRST      LL_IOP_GRP1_ForceReset
01196   * @param  Periphs This parameter can be a combination of the following values:
01197   *         @arg @ref LL_IOP_GRP1_PERIPH_ALL
01198   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
01199   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
01200   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
01201   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
01202   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
01203   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
01204   * @retval None
01205   */
01206 __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
01207 {
01208   SET_BIT(RCC->IOPRSTR, Periphs);
01209 }
01210
01211 /**
01212   * @brief  Release IOP peripherals reset.
01213   * @rmtoll IOPRSTR      GPIOARST      LL_IOP_GRP1_ReleaseReset\n
01214   *         IOPRSTR      GPIOBRST      LL_IOP_GRP1_ReleaseReset\n
01215   *         IOPRSTR      GPIOCRST      LL_IOP_GRP1_ReleaseReset\n
01216   *         IOPRSTR      GPIODRST      LL_IOP_GRP1_ReleaseReset\n
01217   *         IOPRSTR      GPIOERST      LL_IOP_GRP1_ReleaseReset\n
01218   *         IOPRSTR      GPIOFRST      LL_IOP_GRP1_ReleaseReset
01219   * @param  Periphs This parameter can be a combination of the following values:
01220   *         @arg @ref LL_IOP_GRP1_PERIPH_ALL
01221   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
01222   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
01223   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
01224   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
01225   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
01226   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
01227   * @retval None
01228   */
01229 __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
01230 {
01231   CLEAR_BIT(RCC->IOPRSTR, Periphs);
01232 }
01233
01234 /**
01235   * @brief  Enable IOP peripheral clocks in Sleep and Stop modes
01236   * @rmtoll IOPSMENR     GPIOASMEN     LL_IOP_GRP1_EnableClockStopSleep\n
01237   *         IOPSMENR     GPIOBSMEN     LL_IOP_GRP1_EnableClockStopSleep\n
01238   *         IOPSMENR     GPIOCSMEN     LL_IOP_GRP1_EnableClockStopSleep\n
01239   *         IOPSMENR     GPIODSMEN     LL_IOP_GRP1_EnableClockStopSleep\n
01240   *         IOPSMENR     GPIOESMEN     LL_IOP_GRP1_EnableClockStopSleep\n
01241   *         IOPSMENR     GPIOFSMEN     LL_IOP_GRP1_EnableClockStopSleep
01242   * @param  Periphs This parameter can be a combination of the following values:
01243   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
01244   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
01245   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
01246   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
01247   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
01248   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
01249   * @retval None
01250   */
01251 __STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)
01252 {
01253   __IO uint32_t tmpreg;
01254   SET_BIT(RCC->IOPSMENR, Periphs);
01255   /* Delay after an RCC peripheral clock enabling */
01256   tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
01257   (void)tmpreg;
01258 }
01259
01260 /**
01261   * @brief  Disable IOP peripheral clocks in Sleep and Stop modes
01262   * @rmtoll IOPSMENR     GPIOASMEN     LL_IOP_GRP1_DisableClockStopSleep\n
01263   *         IOPSMENR     GPIOBSMEN     LL_IOP_GRP1_DisableClockStopSleep\n
01264   *         IOPSMENR     GPIOCSMEN     LL_IOP_GRP1_DisableClockStopSleep\n
01265   *         IOPSMENR     GPIODSMEN     LL_IOP_GRP1_DisableClockStopSleep\n
01266   *         IOPSMENR     GPIOESMEN     LL_IOP_GRP1_DisableClockStopSleep\n
01267   *         IOPSMENR     GPIOFSMEN     LL_IOP_GRP1_DisableClockStopSleep
01268   * @param  Periphs This parameter can be a combination of the following values:
01269   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
01270   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
01271   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
01272   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
01273   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
01274   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
01275   * @retval None
01276   */
01277 __STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)
01278 {
01279   CLEAR_BIT(RCC->IOPSMENR, Periphs);
01280 }
01281
01282 /**
01283   * @}
01284   */
01285
01286
01287 /**
01288   * @}
01289   */
01290
01291 /**
01292   * @}
01293   */
01294
01295 #endif /* RCC */
01296
01297 /**
01298   * @}
01299   */
01300
01301 #ifdef __cplusplus
01302 }
01303 #endif
01304
01305 #endif /* STM32G0xx_LL_BUS_H */
01306
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_comp.c Source File

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stm32g0xx_ll_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_comp.h"
00022
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G0xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (COMP1) || defined (COMP2)
00034
00035 /** @addtogroup COMP_LL COMP
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043
00044 /** @addtogroup COMP_LL_Private_Macros
00045   * @{
00046   */
00047
00048 /* Check of parameters for configuration of COMP hierarchical scope:          */
00049 /* COMP instance.                                                             */
00050
00051 #define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
00052   (   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
00053    || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
00054   )
00055
00056 /* Note: On this STM32 series, comparator input plus parameters are           */
00057 /*       the same on all COMP instances.                                      */
00058 /*       However, comparator instance kept as macro parameter for             */
00059 /*       compatibility with other STM32 families.                             */
00060 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00061   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00062    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00063    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                             \
00064   )
00065
00066 /* Note: On this STM32 series, comparator input minus parameters are          */
00067 /*       the same on all COMP instances.                                      */
00068 /*       However, comparator instance kept as macro parameter for             */
00069 /*       compatibility with other STM32 families.                             */
00070 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00071   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00072    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00073    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00074    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00075    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00076    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
00077    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00078    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00079    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
00080   )
00081
00082 #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
00083   (   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
00084    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
00085    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
00086    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
00087   )
00088
00089 #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
00090   (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
00091    || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
00092   )
00093
00094 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)          \
00095   (   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
00096    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC4)           \
00097    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5)           \
00098    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3)           \
00099    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3)           \
00100    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2)          \
00101   )
00102
00103 /**
00104   * @}
00105   */
00106
00107
00108 /* Private function prototypes -----------------------------------------------*/
00109
00110 /* Exported functions --------------------------------------------------------*/
00111 /** @addtogroup COMP_LL_Exported_Functions
00112   * @{
00113   */
00114
00115 /** @addtogroup COMP_LL_EF_Init
00116   * @{
00117   */
00118
00119 /**
00120   * @brief  De-initialize registers of the selected COMP instance
00121   *         to their default reset values.
00122   * @note   If comparator is locked, de-initialization by software is
00123   *         not possible.
00124   *         The only way to unlock the comparator is a device hardware reset.
00125   * @param  COMPx COMP instance
00126   * @retval An ErrorStatus enumeration value:
00127   *          - SUCCESS: COMP registers are de-initialized
00128   *          - ERROR: COMP registers are not de-initialized
00129   */
00130 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
00131 {
00132   ErrorStatus status = SUCCESS;
00133
00134   /* Check the parameters */
00135   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00136
00137   /* Note: Hardware constraint (refer to description of this function):       */
00138   /*       COMP instance must not be locked.                                  */
00139   if (LL_COMP_IsLocked(COMPx) == 0UL)
00140   {
00141     LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL);
00142
00143   }
00144   else
00145   {
00146     /* Comparator instance is locked: de-initialization by software is         */
00147     /* not possible.                                                           */
00148     /* The only way to unlock the comparator is a device hardware reset.       */
00149     status = ERROR;
00150   }
00151
00152   return status;
00153 }
00154
00155 /**
00156   * @brief  Initialize some features of COMP instance.
00157   * @note   This function configures features of the selected COMP instance.
00158   *         Some features are also available at scope COMP common instance
00159   *         (common to several COMP instances).
00160   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00161   * @param  COMPx COMP instance
00162   * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00163   * @retval An ErrorStatus enumeration value:
00164   *          - SUCCESS: COMP registers are initialized
00165   *          - ERROR: COMP registers are not initialized
00166   */
00167 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
00168 {
00169   ErrorStatus status = SUCCESS;
00170
00171   /* Check the parameters */
00172   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00173   assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
00174   assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
00175   assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
00176   assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
00177   assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
00178   assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource));
00179
00180   /* Note: Hardware constraint (refer to description of this function)        */
00181   /*       COMP instance must not be locked.                                  */
00182   if (LL_COMP_IsLocked(COMPx) == 0UL)
00183   {
00184     /* Configuration of comparator instance :                                 */
00185     /*  - PowerMode                                                           */
00186     /*  - InputPlus                                                           */
00187     /*  - InputMinus                                                          */
00188     /*  - InputHysteresis                                                     */
00189     /*  - OutputPolarity                                                      */
00190     /*  - OutputBlankingSource                                                */
00191     MODIFY_REG(COMPx->CSR,
00192                COMP_CSR_PWRMODE
00193                | COMP_CSR_INPSEL
00194                | COMP_CSR_INMSEL
00195                | COMP_CSR_HYST
00196                | COMP_CSR_POLARITY
00197                | COMP_CSR_BLANKING
00198                ,
00199                COMP_InitStruct->PowerMode
00200                | COMP_InitStruct->InputPlus
00201                | COMP_InitStruct->InputMinus
00202                | COMP_InitStruct->InputHysteresis
00203                | COMP_InitStruct->OutputPolarity
00204                | COMP_InitStruct->OutputBlankingSource
00205               );
00206
00207   }
00208   else
00209   {
00210     /* Initialization error: COMP instance is locked.                         */
00211     status = ERROR;
00212   }
00213
00214   return status;
00215 }
00216
00217 /**
00218   * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
00219   * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00220   *                        whose fields will be set to default values.
00221   * @retval None
00222   */
00223 void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
00224 {
00225   /* Set COMP_InitStruct fields to default values */
00226   COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_MEDIUMSPEED;
00227   COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
00228   COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
00229   COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
00230   COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
00231   COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
00232 }
00233
00234 /**
00235   * @}
00236   */
00237
00238 /**
00239   * @}
00240   */
00241
00242 /**
00243   * @}
00244   */
00245
00246 #endif /* COMP1 || COMP2 */
00247
00248 /**
00249   * @}
00250   */
00251
00252 #endif /* USE_FULL_LL_DRIVER */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_comp.h Source File

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stm32g0xx_ll_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_COMP_H
00021 #define STM32G0xx_LL_COMP_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (COMP1) || defined (COMP2)
00035
00036 /** @defgroup COMP_LL COMP
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @defgroup COMP_LL_Private_Constants COMP Private Constants
00044   * @{
00045   */
00046
00047 /* Internal mask for pair of comparators instances window mode:               */
00048 /* To select into literals LL_COMP_WINDOWMODE_COMPx_INPUT_PLUS_COMMON         */
00049 /* the relevant bits for:                                                     */
00050 /* (concatenation of multiple bits used in different registers)               */
00051 /* - Comparator instance selected as master for window mode : register offset */
00052 /* - Window mode enable or disable: bit value */
00053 #define LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK  (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...) defined as reference register */
00054 #define LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) offset vs register of COMP instance odd */
00055 #define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK     (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
00056 #define LL_COMP_WINDOWMODE_COMPX_SETTING_MASK       (COMP_CSR_WINMODE)
00057 #define LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK     (COMP_CSR_WINOUT)
00058 #define LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK      (COMP_CSR_WINOUT << 1UL)
00059 #define LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW     (1UL)
00060
00061 /* COMP registers bits positions */
00062 #define LL_COMP_WINDOWMODE_BITOFFSET_POS   (11UL) /* Value equivalent to POSITION_VAL(COMP_CSR_WINMODE) */
00063 #define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
00064
00065 /**
00066   * @}
00067   */
00068
00069 /* Private macros ------------------------------------------------------------*/
00070 /** @defgroup COMP_LL_Private_Macros COMP Private Macros
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  Driver macro reserved for internal use: set a pointer to
00076   *         a register from a register basis from which an offset
00077   *         is applied.
00078   * @param  __REG__ Register basis from which the offset is applied.
00079   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00080   * @retval Pointer to register address
00081   */
00082 #define __COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                        \
00083   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
00084
00085 /**
00086   * @}
00087   */
00088
00089 /* Exported types ------------------------------------------------------------*/
00090 #if defined(USE_FULL_LL_DRIVER)
00091 /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
00092   * @{
00093   */
00094
00095 /**
00096   * @brief  Structure definition of some features of COMP instance.
00097   */
00098 typedef struct
00099 {
00100   uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
00101                                              This parameter can be a value of @ref COMP_LL_EC_POWERMODE
00102
00103                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
00104
00105   uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
00106                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
00107
00108                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
00109
00110   uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
00111                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
00112
00113                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
00114
00115   uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
00116                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
00117
00118                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
00119
00120   uint32_t OutputPolarity;              /*!< Set comparator output polarity.
00121                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
00122
00123                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
00124
00125   uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
00126                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
00127
00128                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
00129
00130 } LL_COMP_InitTypeDef;
00131
00132 /**
00133   * @}
00134   */
00135 #endif /* USE_FULL_LL_DRIVER */
00136
00137 /* Exported constants --------------------------------------------------------*/
00138 /** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
00139   * @{
00140   */
00141
00142 /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
00143   * @{
00144   */
00145 #define LL_COMP_WINDOWMODE_DISABLE                 (0x00000000UL)                                                   /*!< Window mode disable: Comparators 1 and 2 are independent */
00146 #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00147 #define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)  /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). If used from COMP3 instance (when available), comparators instances pair COMP2 and COMP3 have their input plus connected together, the common input is COMP2 input plus (COMP3 input plus is no more accessible). */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup COMP_LL_EC_COMMON_WINDOWOUTPUT Comparator common modes - Window output
00153   * @{
00154   */
00155 #define LL_COMP_WINDOWOUTPUT_EACH_COMP               (0x00000000UL)                                                  /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. The same way, if both comparators output are high, then monitored signal is below window. */
00156 #define LL_COMP_WINDOWOUTPUT_COMP1                   (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)  /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/
00157 #define LL_COMP_WINDOWOUTPUT_COMP2                   (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/
00158 #if defined(COMP3)
00159 #define LL_COMP_WINDOWOUTPUT_COMP3                   (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK)  /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Available only on devices featuring COMP3 instance. */
00160 #endif /* COMP3 */
00161 #define LL_COMP_WINDOWOUTPUT_BOTH                    (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK)      /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
00167   * @{
00168   */
00169 #define LL_COMP_POWERMODE_HIGHSPEED     (0x00000000UL)                            /*!< COMP power mode to high speed */
00170 #define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CSR_PWRMODE_0)                      /*!< COMP power mode to medium speed */
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
00176   * @{
00177   */
00178 #define LL_COMP_INPUT_PLUS_IO1          (0x00000000UL)                          /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2, pin PB0 for COMP3 (for devices featuring COMP3 instance)) */
00179 #define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_INPSEL_0)                     /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2, pin PC1 for COMP3 (for devices featuring COMP3 instance)) */
00180 #define LL_COMP_INPUT_PLUS_IO3          (COMP_CSR_INPSEL_1)                     /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2, pin PE7 for COMP3 (for devices featuring COMP3 instance)) */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
00186   * @{
00187   */
00188 #define LL_COMP_INPUT_MINUS_1_4VREFINT  (0x00000000UL)                                                                  /*!< Comparator input minus connected to 1/4 VrefInt  */
00189 #define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                                            COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt  */
00190 #define LL_COMP_INPUT_MINUS_3_4VREFINT  (                                        COMP_CSR_INMSEL_1                    ) /*!< Comparator input minus connected to 3/4 VrefInt  */
00191 #define LL_COMP_INPUT_MINUS_VREFINT     (                                        COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */
00192 #define LL_COMP_INPUT_MINUS_DAC1_CH1    (                    COMP_CSR_INMSEL_2                                        ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
00193 #define LL_COMP_INPUT_MINUS_DAC1_CH2    (                    COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
00194 #define LL_COMP_INPUT_MINUS_IO1         (                    COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2, pin PB2 for COMP3 (for devices featuring COMP3 instance)) */
00195 #define LL_COMP_INPUT_MINUS_IO2         (                    COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2, pin PC0 for COMP3 (for devices featuring COMP3 instance)) */
00196 #define LL_COMP_INPUT_MINUS_IO3         (COMP_CSR_INMSEL_3                                                            ) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2, pin PE8 for COMP3 (for devices featuring COMP3 instance)) */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
00202   * @{
00203   */
00204 #define LL_COMP_HYSTERESIS_NONE         (0x00000000UL)                      /*!< No hysteresis */
00205 #define LL_COMP_HYSTERESIS_LOW          (                  COMP_CSR_HYST_0) /*!< Hysteresis level low */
00206 #define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CSR_HYST_1                  ) /*!< Hysteresis level medium */
00207 #define LL_COMP_HYSTERESIS_HIGH         (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
00213   * @{
00214   */
00215 #define LL_COMP_OUTPUTPOL_NONINVERTED   (0x00000000UL)          /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
00216 #define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_POLARITY)     /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
00222   * @{
00223   */
00224 #define LL_COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
00225 /* Note: Output blanking source common to all COMP instances */
00226 #define LL_COMP_BLANKINGSRC_TIM1_OC4        (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC4 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00227 #define LL_COMP_BLANKINGSRC_TIM1_OC5        (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00228 #define LL_COMP_BLANKINGSRC_TIM2_OC3        (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00229 #define LL_COMP_BLANKINGSRC_TIM3_OC3        (COMP_CSR_BLANKING_3)   /*!< Comparator output blanking source TIM3 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00230 #define LL_COMP_BLANKINGSRC_TIM15_OC2       (COMP_CSR_BLANKING_4)   /*!< Comparator output blanking source TIM15 OC2 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
00236   * @{
00237   */
00238 #define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000UL)          /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
00239 #define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001UL)          /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
00245   * @note   Only COMP peripheral HW delays are defined in COMP LL driver driver,
00246   *         not timeout values.
00247   *         For details on delays values, refer to descriptions in source code
00248   *         above each literal definition.
00249   * @{
00250   */
00251
00252 /* Delay for comparator startup time.                                         */
00253 /* Note: Delay required to reach propagation delay specification.             */
00254 /* Literal set to maximum value (refer to device datasheet,                   */
00255 /* parameter "tSTART").                                                       */
00256 /* Unit: us                                                                   */
00257 #define LL_COMP_DELAY_STARTUP_US          ( 80UL) /*!< Delay for COMP startup time */
00258
00259 /* Delay for comparator voltage scaler stabilization time.                    */
00260 /* Note: Voltage scaler is used when selecting comparator input               */
00261 /*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
00262 /* Literal set to maximum value (refer to device datasheet,                   */
00263 /* parameter "tSTART_SCALER").                                                */
00264 /* Unit: us                                                                   */
00265 #define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL) /*!< Delay for COMP voltage scaler stabilization time */
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /* Exported macro ------------------------------------------------------------*/
00276 /** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
00277   * @{
00278   */
00279 /** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
00280   * @{
00281   */
00282
00283 /**
00284   * @brief  Write a value in COMP register
00285   * @param  __INSTANCE__ comparator instance
00286   * @param  __REG__ Register to be written
00287   * @param  __VALUE__ Value to be written in the register
00288   * @retval None
00289   */
00290 #define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00291
00292 /**
00293   * @brief  Read a value in COMP register
00294   * @param  __INSTANCE__ comparator instance
00295   * @param  __REG__ Register to be read
00296   * @retval Register value
00297   */
00298 #define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
00304   * @{
00305   */
00306
00307 /**
00308   * @brief  Helper macro to select the COMP common instance
00309   *         to which is belonging the selected COMP instance.
00310   * @note   COMP common register instance can be used to
00311   *         set parameters common to several COMP instances.
00312   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00313   * @param  __COMPx__ COMP instance
00314   * @retval COMP common instance or value "0" if there is no COMP common instance.
00315   */
00316 #if defined(COMP3)
00317 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
00318   ((((__COMPx__) == COMP3))                                                    \
00319     ? (                                                                        \
00320        (COMP23_COMMON)                                                         \
00321       )                                                                        \
00322       :                                                                        \
00323       (                                                                        \
00324        (COMP12_COMMON)                                                         \
00325       )                                                                        \
00326   )
00327 #else
00328 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
00329   (COMP12_COMMON)
00330 #endif /* COMP3 */
00331
00332 /**
00333   * @}
00334   */
00335
00336 /**
00337   * @}
00338   */
00339
00340 /* Exported functions --------------------------------------------------------*/
00341 /** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
00342   * @{
00343   */
00344
00345 /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
00346   * @{
00347   */
00348
00349 /**
00350   * @brief  Set window mode of a pair of comparators instances
00351   *         (2 consecutive COMP instances COMP<x> and COMP<x+1>).
00352   * @rmtoll CSR      WINMODE        LL_COMP_SetCommonWindowMode
00353   * @param  COMPxy_COMMON Comparator common instance
00354   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00355   * @param  WindowMode This parameter can be one of the following values:
00356   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00357   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
00358   *         @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1)(2)
00359   *
00360   *         (1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON
00361   *         (2) Parameter specificity on devices STM32G0B1xx and STM32G0C1xx: only parameter that can be used only with comparator common instance COMP23_COMMON
00362   * @retval None
00363   */
00364 __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
00365 {
00366   uint32_t window_mode_tmp = WindowMode;
00367
00368   /* Note: On this STM32 series, window mode can be set from any instance     */
00369   /*       of the pair of comparator instances.                               */
00370 #if defined(COMP3)
00371   /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common   */
00372   /*       group of COMP2 and COMP3, instances odd and even are inverted.     */
00373   /*       Perform switch of parameter selected.                              */
00374   if(COMPxy_COMMON == COMP23_COMMON)
00375   {
00376     if(WindowMode == LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)
00377     {
00378       window_mode_tmp = LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON;
00379     }
00380   }
00381 #endif /* COMP3 */
00382
00383   __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (window_mode_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
00384
00385   /* Clear the potential previous setting of window mode */
00386   __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(window_mode_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL));
00387   CLEAR_BIT(*preg_clear,
00388             COMP_CSR_WINMODE
00389            );
00390
00391   /* Set window mode */
00392   MODIFY_REG(*preg,
00393              COMP_CSR_WINMODE,
00394              (window_mode_tmp & LL_COMP_WINDOWMODE_COMPX_SETTING_MASK)
00395             );
00396 }
00397
00398 /**
00399   * @brief  Get window mode of a pair of comparators instances
00400   *         (2 consecutive COMP instances COMP<x> and COMP<x+1>).
00401   * @rmtoll CSR      WINMODE        LL_COMP_GetCommonWindowMode
00402   * @param  COMPxy_COMMON Comparator common instance
00403   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00404   * @retval Returned value can be one of the following values:
00405   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00406   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
00407   *         @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1)(2)
00408   *
00409   *         (1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON
00410   *         (2) Parameter specificity on devices STM32G0B1xx and STM32G0C1xx: only parameter that can be used only with comparator common instance COMP23_COMMON
00411   */
00412 __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
00413 {
00414   /* Note: On this STM32 series, window mode can be set from any instance     */
00415   /*       of the pair of comparator instances.                               */
00416 #if defined(COMP3)
00417   uint32_t window_mode_comp_odd;
00418   uint32_t window_mode_comp_even;
00419
00420   /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common   */
00421   /*       group of COMP2 and COMP3, instances odd and even are inverted.     */
00422   /*       Perform switch of parameter selected.                              */
00423   if(COMPxy_COMMON == COMP23_COMMON)
00424   {
00425     window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00426     window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE);
00427   }
00428   else
00429   {
00430     window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE);
00431     window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00432   }
00433 #else
00434    const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE);
00435    const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
00436 #endif /* COMP3 */
00437
00438   return (uint32_t)(window_mode_comp_odd
00439                     | window_mode_comp_even
00440                     | ((window_mode_comp_even >> LL_COMP_WINDOWMODE_BITOFFSET_POS) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK));
00441 }
00442
00443 /**
00444   * @brief  Set window output of a pair of comparators instances
00445   *         (2 consecutive COMP instances COMP<x> and COMP<x+1>).
00446   * @rmtoll CSR      WINOUT         LL_COMP_SetCommonWindowOutput
00447   * @param  COMPxy_COMMON Comparator common instance
00448   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00449   * @param  WindowOutput This parameter can be one of the following values:
00450   *         @arg @ref LL_COMP_WINDOWOUTPUT_EACH_COMP
00451   *         @arg @ref LL_COMP_WINDOWOUTPUT_COMP1 (1)
00452   *         @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 (1)
00453   *         @arg @ref LL_COMP_WINDOWOUTPUT_COMP3 (2)
00454   *         @arg @ref LL_COMP_WINDOWOUTPUT_BOTH
00455   *
00456   *         (1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON
00457   *         (2) Parameter available only on devices STM32G0B1xx and STM32G0C1xx, must be used with comparator common instance COMP23_COMMON
00458   * @retval None
00459   */
00460 __STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput)
00461 {
00462   uint32_t window_output_tmp = WindowOutput;
00463
00464 #if defined(COMP3)
00465   /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common   */
00466   /*       group of COMP2 and COMP3, instances odd and even are inverted.     */
00467   /*       Perform switch of parameter selected.                              */
00468   if(COMPxy_COMMON == COMP23_COMMON)
00469   {
00470     if(WindowOutput == LL_COMP_WINDOWOUTPUT_COMP2)
00471     {
00472       window_output_tmp = LL_COMP_WINDOWOUTPUT_COMP3;
00473     }
00474     else if(WindowOutput == LL_COMP_WINDOWOUTPUT_COMP3)
00475     {
00476       window_output_tmp = LL_COMP_WINDOWOUTPUT_COMP2;
00477     }
00478     else
00479     {
00480       /* No modification of other parameters */
00481     }
00482   }
00483 #endif /* COMP3 */
00484
00485   __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (window_output_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
00486
00487   /* Clear the potential previous setting of window output on the relevant comparator instance */
00488   /* (clear bit of window output unless specific case of setting of comparator both output selected) */
00489   __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (~(window_output_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL));
00490   MODIFY_REG(*preg_clear,
00491              COMP_CSR_WINOUT,
00492              ((window_output_tmp & LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) >> LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW)
00493             );
00494
00495   /* Set window output */
00496   MODIFY_REG(*preg,
00497              COMP_CSR_WINOUT,
00498              (window_output_tmp & LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK)
00499             );
00500 }
00501
00502 /**
00503   * @brief  Get window output of a pair of comparators instances
00504   *         (2 consecutive COMP instances COMP<x> and COMP<x+1>).
00505   * @rmtoll CSR      WINMODE        LL_COMP_GetCommonWindowOutput
00506   * @param  COMPxy_COMMON Comparator common instance
00507   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00508   * @retval Returned value can be one of the following values:
00509   *         @arg @ref LL_COMP_WINDOWOUTPUT_EACH_COMP
00510   *         @arg @ref LL_COMP_WINDOWOUTPUT_COMP1 (1)
00511   *         @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 (1)
00512   *         @arg @ref LL_COMP_WINDOWOUTPUT_COMP3 (2)
00513   *         @arg @ref LL_COMP_WINDOWOUTPUT_BOTH
00514   *
00515   *         (1) Parameter available on all STM32G0 devices, must be used with comparator common instance COMP12_COMMON
00516   *         (2) Parameter available only on devices STM32G0B1xx and STM32G0C1xx, must be used with comparator common instance COMP23_COMMON
00517   */
00518 __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON)
00519 {
00520 #if defined(COMP3)
00521   uint32_t window_output_comp_odd;
00522   uint32_t window_output_comp_even;
00523
00524   /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common   */
00525   /*       group of COMP2 and COMP3, instances odd and even are inverted.     */
00526   /*       Perform switch of parameter selected.                              */
00527   if(COMPxy_COMMON == COMP23_COMMON)
00528   {
00529     window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
00530     window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT);
00531   }
00532   else
00533   {
00534     window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT);
00535     window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
00536   }
00537 #else
00538   const uint32_t window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT);
00539   const uint32_t window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
00540 #endif /* COMP3 */
00541
00542   /* Construct value corresponding to LL_COMP_WINDOWOUTPUT_xxx */
00543   return (uint32_t)(window_output_comp_odd
00544                     | window_output_comp_even
00545                     | ((window_output_comp_even >> COMP_CSR_WINOUT_Pos) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
00546                     | (window_output_comp_odd + window_output_comp_even));
00547 }
00548
00549 /**
00550   * @}
00551   */
00552
00553 /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
00554   * @{
00555   */
00556
00557 /**
00558   * @brief  Set comparator instance operating mode to adjust power and speed.
00559   * @rmtoll CSR      PWRMODE        LL_COMP_SetPowerMode
00560   * @param  COMPx Comparator instance
00561   * @param  PowerMode This parameter can be one of the following values:
00562   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00563   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
00564   * @retval None
00565   */
00566 __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
00567 {
00568   MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode);
00569 }
00570
00571 /**
00572   * @brief  Get comparator instance operating mode to adjust power and speed.
00573   * @rmtoll CSR      PWRMODE        LL_COMP_GetPowerMode
00574   * @param  COMPx Comparator instance
00575   * @retval Returned value can be one of the following values:
00576   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00577   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
00578   */
00579 __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
00580 {
00581   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
00582 }
00583
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
00589   * @{
00590   */
00591
00592 /**
00593   * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
00594   * @note   In case of comparator input selected to be connected to IO:
00595   *         GPIO pins are specific to each comparator instance.
00596   *         Refer to description of parameters or to reference manual.
00597   * @note   On this STM32 series, a voltage scaler is used
00598   *         when COMP input is based on VrefInt (VrefInt or subdivision
00599   *         of VrefInt):
00600   *         Voltage scaler requires a delay for voltage stabilization.
00601   *         Refer to device datasheet, parameter "tSTART_SCALER".
00602   * @rmtoll CSR      INMSEL         LL_COMP_ConfigInputs\n
00603   *         CSR      INPSEL         LL_COMP_ConfigInputs\n
00604   * @param  COMPx Comparator instance
00605   * @param  InputMinus This parameter can be one of the following values:
00606   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00607   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00608   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00609   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00610   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00611   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00612   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00613   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00614   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
00615   * @param  InputPlus This parameter can be one of the following values:
00616   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00617   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00618   *         @arg @ref LL_COMP_INPUT_PLUS_IO3
00619   * @retval None
00620   */
00621 __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
00622 {
00623   MODIFY_REG(COMPx->CSR,
00624              COMP_CSR_INMSEL | COMP_CSR_INPSEL,
00625              InputMinus | InputPlus);
00626 }
00627
00628 /**
00629   * @brief  Set comparator input plus (non-inverting).
00630   * @note   In case of comparator input selected to be connected to IO:
00631   *         GPIO pins are specific to each comparator instance.
00632   *         Refer to description of parameters or to reference manual.
00633   * @rmtoll CSR      INPSEL         LL_COMP_SetInputPlus
00634   * @param  COMPx Comparator instance
00635   * @param  InputPlus This parameter can be one of the following values:
00636   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00637   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00638   *         @arg @ref LL_COMP_INPUT_PLUS_IO3
00639   * @retval None
00640   */
00641 __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
00642 {
00643   MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
00644 }
00645
00646 /**
00647   * @brief  Get comparator input plus (non-inverting).
00648   * @note   In case of comparator input selected to be connected to IO:
00649   *         GPIO pins are specific to each comparator instance.
00650   *         Refer to description of parameters or to reference manual.
00651   * @rmtoll CSR      INPSEL         LL_COMP_GetInputPlus
00652   * @param  COMPx Comparator instance
00653   * @retval Returned value can be one of the following values:
00654   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00655   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00656   *         @arg @ref LL_COMP_INPUT_PLUS_IO3
00657   */
00658 __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
00659 {
00660   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
00661 }
00662
00663 /**
00664   * @brief  Set comparator input minus (inverting).
00665   * @note   In case of comparator input selected to be connected to IO:
00666   *         GPIO pins are specific to each comparator instance.
00667   *         Refer to description of parameters or to reference manual.
00668   * @note   On this STM32 series, a voltage scaler is used
00669   *         when COMP input is based on VrefInt (VrefInt or subdivision
00670   *         of VrefInt):
00671   *         Voltage scaler requires a delay for voltage stabilization.
00672   *         Refer to device datasheet, parameter "tSTART_SCALER".
00673   * @rmtoll CSR      INMSEL         LL_COMP_SetInputMinus
00674   * @param  COMPx Comparator instance
00675   * @param  InputMinus This parameter can be one of the following values:
00676   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00677   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00678   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00679   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00680   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00681   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00682   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00683   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00684   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
00685   * @retval None
00686   */
00687 __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
00688 {
00689   MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL, InputMinus);
00690 }
00691
00692 /**
00693   * @brief  Get comparator input minus (inverting).
00694   * @note   In case of comparator input selected to be connected to IO:
00695   *         GPIO pins are specific to each comparator instance.
00696   *         Refer to description of parameters or to reference manual.
00697   * @rmtoll CSR      INMSEL         LL_COMP_GetInputMinus
00698   * @param  COMPx Comparator instance
00699   * @retval Returned value can be one of the following values:
00700   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00701   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00702   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00703   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00704   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00705   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00706   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00707   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00708   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
00709   */
00710 __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
00711 {
00712   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL));
00713 }
00714
00715 /**
00716   * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
00717   * @rmtoll CSR      HYST           LL_COMP_SetInputHysteresis
00718   * @param  COMPx Comparator instance
00719   * @param  InputHysteresis This parameter can be one of the following values:
00720   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00721   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00722   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00723   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00724   * @retval None
00725   */
00726 __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
00727 {
00728   MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
00729 }
00730
00731 /**
00732   * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
00733   * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis
00734   * @param  COMPx Comparator instance
00735   * @retval Returned value can be one of the following values:
00736   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00737   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00738   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00739   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00740   */
00741 __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
00742 {
00743   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
00744 }
00745
00746 /**
00747   * @}
00748   */
00749
00750 /** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
00751   * @{
00752   */
00753
00754 /**
00755   * @brief  Set comparator instance output polarity.
00756   * @rmtoll CSR      POLARITY       LL_COMP_SetOutputPolarity
00757   * @param  COMPx Comparator instance
00758   * @param  OutputPolarity This parameter can be one of the following values:
00759   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00760   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00761   * @retval None
00762   */
00763 __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
00764 {
00765   MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
00766 }
00767
00768 /**
00769   * @brief  Get comparator instance output polarity.
00770   * @rmtoll CSR      POLARITY       LL_COMP_GetOutputPolarity
00771   * @param  COMPx Comparator instance
00772   * @retval Returned value can be one of the following values:
00773   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00774   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00775   */
00776 __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
00777 {
00778   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
00779 }
00780
00781 /**
00782   * @brief  Set comparator instance blanking source.
00783   * @note   Blanking source may be specific to each comparator instance.
00784   *         Refer to description of parameters or to reference manual.
00785   * @note   Availability of parameters of blanking source from timer
00786   *         depends on timers availability on the selected device.
00787   * @rmtoll CSR      BLANKING       LL_COMP_SetOutputBlankingSource
00788   * @param  COMPx Comparator instance
00789   * @param  BlankingSource This parameter can be one of the following values:
00790   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00791   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC4  (1)
00792   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5  (1)
00793   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3  (1)
00794   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3  (1)
00795   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2 (1)
00796   *
00797   *         (1) Parameter availability depending on timer availability
00798   *             on the selected device.
00799   * @retval None
00800   */
00801 __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
00802 {
00803   MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
00804 }
00805
00806 /**
00807   * @brief  Get comparator instance blanking source.
00808   * @note   Availability of parameters of blanking source from timer
00809   *         depends on timers availability on the selected device.
00810   * @note   Blanking source may be specific to each comparator instance.
00811   *         Refer to description of parameters or to reference manual.
00812   * @rmtoll CSR      BLANKING       LL_COMP_GetOutputBlankingSource
00813   * @param  COMPx Comparator instance
00814   * @retval Returned value can be one of the following values:
00815   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00816   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC4  (1)
00817   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5  (1)
00818   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3  (1)
00819   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3  (1)
00820   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2 (1)
00821   *
00822   *         (1) Parameter availability depending on timer availability
00823   *             on the selected device.
00824   */
00825 __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
00826 {
00827   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
00828 }
00829
00830 /**
00831   * @}
00832   */
00833
00834 /** @defgroup COMP_LL_EF_Operation Operation on comparator instance
00835   * @{
00836   */
00837
00838 /**
00839   * @brief  Enable comparator instance.
00840   * @note   After enable from off state, comparator requires a delay
00841   *         to reach reach propagation delay specification.
00842   *         Refer to device datasheet, parameter "tSTART".
00843   * @rmtoll CSR      EN             LL_COMP_Enable
00844   * @param  COMPx Comparator instance
00845   * @retval None
00846   */
00847 __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
00848 {
00849   SET_BIT(COMPx->CSR, COMP_CSR_EN);
00850 }
00851
00852 /**
00853   * @brief  Disable comparator instance.
00854   * @rmtoll CSR      EN             LL_COMP_Disable
00855   * @param  COMPx Comparator instance
00856   * @retval None
00857   */
00858 __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
00859 {
00860   CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
00861 }
00862
00863 /**
00864   * @brief  Get comparator enable state
00865   *         (0: COMP is disabled, 1: COMP is enabled)
00866   * @rmtoll CSR      EN             LL_COMP_IsEnabled
00867   * @param  COMPx Comparator instance
00868   * @retval State of bit (1 or 0).
00869   */
00870 __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
00871 {
00872   return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
00873 }
00874
00875 /**
00876   * @brief  Lock comparator instance.
00877   * @note   Once locked, comparator configuration can be accessed in read-only.
00878   * @note   The only way to unlock the comparator is a device hardware reset.
00879   * @rmtoll CSR      LOCK           LL_COMP_Lock
00880   * @param  COMPx Comparator instance
00881   * @retval None
00882   */
00883 __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
00884 {
00885   SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
00886 }
00887
00888 /**
00889   * @brief  Get comparator lock state
00890   *         (0: COMP is unlocked, 1: COMP is locked).
00891   * @note   Once locked, comparator configuration can be accessed in read-only.
00892   * @note   The only way to unlock the comparator is a device hardware reset.
00893   * @rmtoll CSR      LOCK           LL_COMP_IsLocked
00894   * @param  COMPx Comparator instance
00895   * @retval State of bit (1 or 0).
00896   */
00897 __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
00898 {
00899   return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
00900 }
00901
00902 /**
00903   * @brief  Read comparator instance output level.
00904   * @note   The comparator output level depends on the selected polarity
00905   *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
00906   *         If the comparator polarity is not inverted:
00907   *          - Comparator output is low when the input plus
00908   *            is at a lower voltage than the input minus
00909   *          - Comparator output is high when the input plus
00910   *            is at a higher voltage than the input minus
00911   *         If the comparator polarity is inverted:
00912   *          - Comparator output is high when the input plus
00913   *            is at a lower voltage than the input minus
00914   *          - Comparator output is low when the input plus
00915   *            is at a higher voltage than the input minus
00916   * @rmtoll CSR      VALUE          LL_COMP_ReadOutputLevel
00917   * @param  COMPx Comparator instance
00918   * @retval Returned value can be one of the following values:
00919   *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
00920   *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
00921   */
00922 __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
00923 {
00924   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
00925                     >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
00926 }
00927
00928 /**
00929   * @}
00930   */
00931
00932 #if defined(USE_FULL_LL_DRIVER)
00933 /** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
00934   * @{
00935   */
00936
00937 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
00938 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
00939 void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
00940
00941 /**
00942   * @}
00943   */
00944 #endif /* USE_FULL_LL_DRIVER */
00945
00946 /**
00947   * @}
00948   */
00949
00950 /**
00951   * @}
00952   */
00953
00954 /**
00955   * @}
00956   */
00957
00958 #endif /* COMP1 || COMP2 */
00959
00960 /**
00961   * @}
00962   */
00963
00964 #ifdef __cplusplus
00965 }
00966 #endif
00967
00968 #endif /* STM32G0xx_LL_COMP_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_cortex.h Source File

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stm32g0xx_ll_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL CORTEX driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
00014           functions
00015       (+) Low power mode configuration (SCB register of Cortex-MCU)
00016       (+) MPU API to configure and enable regions
00017       (+) API to access to MCU info (CPUID register)
00018
00019   @endverbatim
00020   ******************************************************************************
00021   * @attention
00022   *
00023   * Copyright (c) 2018 STMicroelectronics.
00024   * All rights reserved.
00025   *
00026   * This software is licensed under terms that can be found in the LICENSE file in
00027   * the root directory of this software component.
00028   * If no LICENSE file comes with this software, it is provided AS-IS.
00029   *
00030   ******************************************************************************
00031   */
00032
00033 /* Define to prevent recursive inclusion -------------------------------------*/
00034 #ifndef STM32G0xx_LL_CORTEX_H
00035 #define STM32G0xx_LL_CORTEX_H
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041 /* Includes ------------------------------------------------------------------*/
00042 #include "stm32g0xx.h"
00043
00044 /** @addtogroup STM32G0xx_LL_Driver
00045   * @{
00046   */
00047
00048 /** @defgroup CORTEX_LL CORTEX
00049   * @{
00050   */
00051
00052 /* Private types -------------------------------------------------------------*/
00053 /* Private variables ---------------------------------------------------------*/
00054
00055 /* Private constants ---------------------------------------------------------*/
00056
00057 /* Private macros ------------------------------------------------------------*/
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /* Exported constants --------------------------------------------------------*/
00061 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
00062   * @{
00063   */
00064
00065 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
00066   * @{
00067   */
00068 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
00069 #define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
00070 /**
00071   * @}
00072   */
00073
00074 #if __MPU_PRESENT
00075
00076 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
00077   * @{
00078   */
00079 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
00080 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
00081 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
00082 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
00088   * @{
00089   */
00090 #define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
00091 #define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
00092 #define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
00093 #define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
00094 #define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
00095 #define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
00096 #define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
00097 #define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
00098 /**
00099   * @}
00100   */
00101
00102 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
00103   * @{
00104   */
00105 #define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
00106 #define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
00107 #define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
00108 #define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
00109 #define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
00110 #define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
00111 #define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
00112 #define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
00113 #define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
00114 #define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
00115 #define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
00116 #define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
00117 #define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
00118 #define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
00119 #define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
00120 #define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
00121 #define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
00122 #define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
00123 #define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
00124 #define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
00125 #define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
00126 #define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
00127 #define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
00128 #define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
00129 #define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
00135   * @{
00136   */
00137 #define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
00138 #define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
00139 #define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
00140 #define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
00141 #define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
00142 #define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
00148   * @{
00149   */
00150 #define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
00151 #define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
00152 #define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
00153 #define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
00159   * @{
00160   */
00161 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
00162 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
00168   * @{
00169   */
00170 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
00171 #define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
00177   * @{
00178   */
00179 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
00180 #define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
00186   * @{
00187   */
00188 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
00189 #define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
00190 /**
00191   * @}
00192   */
00193 #endif /* __MPU_PRESENT */
00194 /**
00195   * @}
00196   */
00197
00198 /* Exported macro ------------------------------------------------------------*/
00199
00200 /* Exported functions --------------------------------------------------------*/
00201 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
00202   * @{
00203   */
00204
00205 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
00206   * @{
00207   */
00208
00209 /**
00210   * @brief  This function checks if the Systick counter flag is active or not.
00211   * @note   It can be used in timeout function on application side.
00212   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
00213   * @retval State of bit (1 or 0).
00214   */
00215 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
00216 {
00217   return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
00218 }
00219
00220 /**
00221   * @brief  Configures the SysTick clock source
00222   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
00223   * @param  Source This parameter can be one of the following values:
00224   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00225   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00226   * @retval None
00227   */
00228 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
00229 {
00230   if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
00231   {
00232     SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00233   }
00234   else
00235   {
00236     CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00237   }
00238 }
00239
00240 /**
00241   * @brief  Get the SysTick clock source
00242   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
00243   * @retval Returned value can be one of the following values:
00244   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00245   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00246   */
00247 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
00248 {
00249   return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00250 }
00251
00252 /**
00253   * @brief  Enable SysTick exception request
00254   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
00255   * @retval None
00256   */
00257 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
00258 {
00259   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00260 }
00261
00262 /**
00263   * @brief  Disable SysTick exception request
00264   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
00265   * @retval None
00266   */
00267 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
00268 {
00269   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00270 }
00271
00272 /**
00273   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
00274   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
00275   * @retval State of bit (1 or 0).
00276   */
00277 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
00278 {
00279   return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
00280 }
00281
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
00287   * @{
00288   */
00289
00290 /**
00291   * @brief  Processor uses sleep as its low power mode
00292   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
00293   * @retval None
00294   */
00295 __STATIC_INLINE void LL_LPM_EnableSleep(void)
00296 {
00297   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00298   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00299 }
00300
00301 /**
00302   * @brief  Processor uses deep sleep as its low power mode
00303   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
00304   * @retval None
00305   */
00306 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
00307 {
00308   /* Set SLEEPDEEP bit of Cortex System Control Register */
00309   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00310 }
00311
00312 /**
00313   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
00314   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
00315   *         empty main application.
00316   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
00317   * @retval None
00318   */
00319 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
00320 {
00321   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00322   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00323 }
00324
00325 /**
00326   * @brief  Do not sleep when returning to Thread mode.
00327   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
00328   * @retval None
00329   */
00330 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
00331 {
00332   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00333   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00334 }
00335
00336 /**
00337   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
00338   *         processor.
00339   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
00340   * @retval None
00341   */
00342 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
00343 {
00344   /* Set SEVEONPEND bit of Cortex System Control Register */
00345   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00346 }
00347
00348 /**
00349   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
00350   *         excluded
00351   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
00352   * @retval None
00353   */
00354 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
00355 {
00356   /* Clear SEVEONPEND bit of Cortex System Control Register */
00357   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00358 }
00359
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
00365   * @{
00366   */
00367
00368 /**
00369   * @brief  Get Implementer code
00370   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
00371   * @retval Value should be equal to 0x41 for ARM
00372   */
00373 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
00374 {
00375   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
00376 }
00377
00378 /**
00379   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
00380   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
00381   * @retval Value between 0 and 255 (0x0: revision 0)
00382   */
00383 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
00384 {
00385   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
00386 }
00387
00388 /**
00389   * @brief  Get Architecture number
00390   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetArchitecture
00391   * @retval Value should be equal to 0xC for Cortex-M0+ devices
00392   */
00393 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
00394 {
00395   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
00396 }
00397
00398 /**
00399   * @brief  Get Part number
00400   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
00401   * @retval Value should be equal to 0xC60 for Cortex-M0+
00402   */
00403 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
00404 {
00405   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
00406 }
00407
00408 /**
00409   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
00410   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
00411   * @retval Value between 0 and 255 (0x1: patch 1)
00412   */
00413 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
00414 {
00415   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
00416 }
00417
00418 /**
00419   * @}
00420   */
00421
00422 #if __MPU_PRESENT
00423 /** @defgroup CORTEX_LL_EF_MPU MPU
00424   * @{
00425   */
00426
00427 /**
00428   * @brief  Enable MPU with input options
00429   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
00430   * @param  Options This parameter can be one of the following values:
00431   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
00432   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
00433   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
00434   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
00435   * @retval None
00436   */
00437 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
00438 {
00439   /* Enable the MPU*/
00440   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
00441   /* Ensure MPU settings take effects */
00442   __DSB();
00443   /* Sequence instruction fetches using update settings */
00444   __ISB();
00445 }
00446
00447 /**
00448   * @brief  Disable MPU
00449   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
00450   * @retval None
00451   */
00452 __STATIC_INLINE void LL_MPU_Disable(void)
00453 {
00454   /* Make sure outstanding transfers are done */
00455   __DMB();
00456   /* Disable MPU*/
00457   WRITE_REG(MPU->CTRL, 0U);
00458 }
00459
00460 /**
00461   * @brief  Check if MPU is enabled or not
00462   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
00463   * @retval State of bit (1 or 0).
00464   */
00465 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
00466 {
00467   return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
00468 }
00469
00470 /**
00471   * @brief  Enable a MPU region
00472   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
00473   * @param  Region This parameter can be one of the following values:
00474   *         @arg @ref LL_MPU_REGION_NUMBER0
00475   *         @arg @ref LL_MPU_REGION_NUMBER1
00476   *         @arg @ref LL_MPU_REGION_NUMBER2
00477   *         @arg @ref LL_MPU_REGION_NUMBER3
00478   *         @arg @ref LL_MPU_REGION_NUMBER4
00479   *         @arg @ref LL_MPU_REGION_NUMBER5
00480   *         @arg @ref LL_MPU_REGION_NUMBER6
00481   *         @arg @ref LL_MPU_REGION_NUMBER7
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
00485 {
00486   /* Set Region number */
00487   WRITE_REG(MPU->RNR, Region);
00488   /* Enable the MPU region */
00489   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00490 }
00491
00492 /**
00493   * @brief  Configure and enable a region
00494   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
00495   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
00496   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
00497   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
00498   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
00499   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
00500   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
00501   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
00502   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
00503   * @param  Region This parameter can be one of the following values:
00504   *         @arg @ref LL_MPU_REGION_NUMBER0
00505   *         @arg @ref LL_MPU_REGION_NUMBER1
00506   *         @arg @ref LL_MPU_REGION_NUMBER2
00507   *         @arg @ref LL_MPU_REGION_NUMBER3
00508   *         @arg @ref LL_MPU_REGION_NUMBER4
00509   *         @arg @ref LL_MPU_REGION_NUMBER5
00510   *         @arg @ref LL_MPU_REGION_NUMBER6
00511   *         @arg @ref LL_MPU_REGION_NUMBER7
00512   * @param  Address Value of region base address
00513   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
00514   * @param  Attributes This parameter can be a combination of the following values:
00515   *         @arg @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
00516   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
00517   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
00518   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
00519   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
00520   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
00521   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
00522   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
00523   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
00524   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
00525   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
00526   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
00527   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
00528   * @retval None
00529   */
00530 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
00531 {
00532   /* Set Region number */
00533   WRITE_REG(MPU->RNR, Region);
00534   /* Set base address */
00535   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
00536   /* Configure MPU */
00537   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
00538 }
00539
00540 /**
00541   * @brief  Disable a region
00542   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
00543   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
00544   * @param  Region This parameter can be one of the following values:
00545   *         @arg @ref LL_MPU_REGION_NUMBER0
00546   *         @arg @ref LL_MPU_REGION_NUMBER1
00547   *         @arg @ref LL_MPU_REGION_NUMBER2
00548   *         @arg @ref LL_MPU_REGION_NUMBER3
00549   *         @arg @ref LL_MPU_REGION_NUMBER4
00550   *         @arg @ref LL_MPU_REGION_NUMBER5
00551   *         @arg @ref LL_MPU_REGION_NUMBER6
00552   *         @arg @ref LL_MPU_REGION_NUMBER7
00553   * @retval None
00554   */
00555 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
00556 {
00557   /* Set Region number */
00558   WRITE_REG(MPU->RNR, Region);
00559   /* Disable the MPU region */
00560   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00561 }
00562
00563 /**
00564   * @}
00565   */
00566
00567 #endif /* __MPU_PRESENT */
00568 /**
00569   * @}
00570   */
00571
00572 /**
00573   * @}
00574   */
00575
00576 /**
00577   * @}
00578   */
00579
00580 #ifdef __cplusplus
00581 }
00582 #endif
00583
00584 #endif /* STM32G0xx_LL_CORTEX_H */
00585
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_crc.c Source File

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stm32g0xx_ll_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_crc.h"
00022 #include "stm32g0xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (CRC)
00035
00036 /** @addtogroup CRC_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /* Private function prototypes -----------------------------------------------*/
00045
00046 /* Exported functions --------------------------------------------------------*/
00047 /** @addtogroup CRC_LL_Exported_Functions
00048   * @{
00049   */
00050
00051 /** @addtogroup CRC_LL_EF_Init
00052   * @{
00053   */
00054
00055 /**
00056   * @brief  De-initialize CRC registers (Registers restored to their default values).
00057   * @param  CRCx CRC Instance
00058   * @retval An ErrorStatus enumeration value:
00059   *          - SUCCESS: CRC registers are de-initialized
00060   *          - ERROR: CRC registers are not de-initialized
00061   */
00062 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
00063 {
00064   ErrorStatus status = SUCCESS;
00065
00066   /* Check the parameters */
00067   assert_param(IS_CRC_ALL_INSTANCE(CRCx));
00068
00069   if (CRCx == CRC)
00070   {
00071     /* Force CRC reset */
00072     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
00073
00074     /* Release CRC reset */
00075     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
00076   }
00077   else
00078   {
00079     status = ERROR;
00080   }
00081
00082   return (status);
00083 }
00084
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /**
00094   * @}
00095   */
00096
00097 #endif /* defined (CRC) */
00098
00099 /**
00100   * @}
00101   */
00102
00103 #endif /* USE_FULL_LL_DRIVER */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_crc.h Source File

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stm32g0xx_ll_crc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_CRC_H
00021 #define STM32G0xx_LL_CRC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(CRC)
00035
00036 /** @defgroup CRC_LL CRC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047 /** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
00048   * @{
00049   */
00050
00051 /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
00052   * @{
00053   */
00054 #define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
00055 #define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
00056 #define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
00057 #define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
00058 /**
00059   * @}
00060   */
00061
00062 /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
00063   * @{
00064   */
00065 #define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
00066 #define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
00067 #define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
00068 #define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
00074   * @{
00075   */
00076 #define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
00077 #define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
00083   * @brief    Normal representation of this polynomial value is
00084   *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
00085   * @{
00086   */
00087 #define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
00093   * @{
00094   */
00095 #define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported macro ------------------------------------------------------------*/
00105 /** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
00106   * @{
00107   */
00108
00109 /** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
00110   * @{
00111   */
00112
00113 /**
00114   * @brief  Write a value in CRC register
00115   * @param  __INSTANCE__ CRC Instance
00116   * @param  __REG__ Register to be written
00117   * @param  __VALUE__ Value to be written in the register
00118   * @retval None
00119   */
00120 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
00121
00122 /**
00123   * @brief  Read a value in CRC register
00124   * @param  __INSTANCE__ CRC Instance
00125   * @param  __REG__ Register to be read
00126   * @retval Register value
00127   */
00128 #define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00129 /**
00130   * @}
00131   */
00132
00133 /**
00134   * @}
00135   */
00136
00137
00138 /* Exported functions --------------------------------------------------------*/
00139 /** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
00140   * @{
00141   */
00142
00143 /** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
00144   * @{
00145   */
00146
00147 /**
00148   * @brief  Reset the CRC calculation unit.
00149   * @note   If Programmable Initial CRC value feature
00150   *         is available, also set the Data Register to the value stored in the
00151   *         CRC_INIT register, otherwise, reset Data Register to its default value.
00152   * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
00153   * @param  CRCx CRC Instance
00154   * @retval None
00155   */
00156 __STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
00157 {
00158   SET_BIT(CRCx->CR, CRC_CR_RESET);
00159 }
00160
00161 /**
00162   * @brief  Configure size of the polynomial.
00163   * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
00164   * @param  CRCx CRC Instance
00165   * @param  PolySize This parameter can be one of the following values:
00166   *         @arg @ref LL_CRC_POLYLENGTH_32B
00167   *         @arg @ref LL_CRC_POLYLENGTH_16B
00168   *         @arg @ref LL_CRC_POLYLENGTH_8B
00169   *         @arg @ref LL_CRC_POLYLENGTH_7B
00170   * @retval None
00171   */
00172 __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
00173 {
00174   MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
00175 }
00176
00177 /**
00178   * @brief  Return size of the polynomial.
00179   * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
00180   * @param  CRCx CRC Instance
00181   * @retval Returned value can be one of the following values:
00182   *         @arg @ref LL_CRC_POLYLENGTH_32B
00183   *         @arg @ref LL_CRC_POLYLENGTH_16B
00184   *         @arg @ref LL_CRC_POLYLENGTH_8B
00185   *         @arg @ref LL_CRC_POLYLENGTH_7B
00186   */
00187 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
00188 {
00189   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
00190 }
00191
00192 /**
00193   * @brief  Configure the reversal of the bit order of the input data
00194   * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
00195   * @param  CRCx CRC Instance
00196   * @param  ReverseMode This parameter can be one of the following values:
00197   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00198   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00199   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00200   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00201   * @retval None
00202   */
00203 __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00204 {
00205   MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
00206 }
00207
00208 /**
00209   * @brief  Return type of reversal for input data bit order
00210   * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
00211   * @param  CRCx CRC Instance
00212   * @retval Returned value can be one of the following values:
00213   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00214   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00215   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00216   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00217   */
00218 __STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
00219 {
00220   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
00221 }
00222
00223 /**
00224   * @brief  Configure the reversal of the bit order of the Output data
00225   * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
00226   * @param  CRCx CRC Instance
00227   * @param  ReverseMode This parameter can be one of the following values:
00228   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00229   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00230   * @retval None
00231   */
00232 __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00233 {
00234   MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
00235 }
00236
00237 /**
00238   * @brief  Return type of reversal of the bit order of the Output data
00239   * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
00240   * @param  CRCx CRC Instance
00241   * @retval Returned value can be one of the following values:
00242   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00243   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00244   */
00245 __STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
00246 {
00247   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
00248 }
00249
00250 /**
00251   * @brief  Initialize the Programmable initial CRC value.
00252   * @note   If the CRC size is less than 32 bits, the least significant bits
00253   *         are used to write the correct value
00254   * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
00255   * @rmtoll INIT         INIT          LL_CRC_SetInitialData
00256   * @param  CRCx CRC Instance
00257   * @param  InitCrc Value to be programmed in Programmable initial CRC value register
00258   * @retval None
00259   */
00260 __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
00261 {
00262   WRITE_REG(CRCx->INIT, InitCrc);
00263 }
00264
00265 /**
00266   * @brief  Return current Initial CRC value.
00267   * @note   If the CRC size is less than 32 bits, the least significant bits
00268   *         are used to read the correct value
00269   * @rmtoll INIT         INIT          LL_CRC_GetInitialData
00270   * @param  CRCx CRC Instance
00271   * @retval Value programmed in Programmable initial CRC value register
00272   */
00273 __STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
00274 {
00275   return (uint32_t)(READ_REG(CRCx->INIT));
00276 }
00277
00278 /**
00279   * @brief  Initialize the Programmable polynomial value
00280   *         (coefficients of the polynomial to be used for CRC calculation).
00281   * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
00282   * @note   Please check Reference Manual and existing Errata Sheets,
00283   *         regarding possible limitations for Polynomial values usage.
00284   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00285   * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
00286   * @param  CRCx CRC Instance
00287   * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
00288   * @retval None
00289   */
00290 __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
00291 {
00292   WRITE_REG(CRCx->POL, PolynomCoef);
00293 }
00294
00295 /**
00296   * @brief  Return current Programmable polynomial value
00297   * @note   Please check Reference Manual and existing Errata Sheets,
00298   *         regarding possible limitations for Polynomial values usage.
00299   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00300   * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
00301   * @param  CRCx CRC Instance
00302   * @retval Value programmed in Programmable Polynomial value register
00303   */
00304 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
00305 {
00306   return (uint32_t)(READ_REG(CRCx->POL));
00307 }
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup CRC_LL_EF_Data_Management Data_Management
00314   * @{
00315   */
00316
00317 /**
00318   * @brief  Write given 32-bit data to the CRC calculator
00319   * @rmtoll DR           DR            LL_CRC_FeedData32
00320   * @param  CRCx CRC Instance
00321   * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
00322   * @retval None
00323   */
00324 __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
00325 {
00326   WRITE_REG(CRCx->DR, InData);
00327 }
00328
00329 /**
00330   * @brief  Write given 16-bit data to the CRC calculator
00331   * @rmtoll DR           DR            LL_CRC_FeedData16
00332   * @param  CRCx CRC Instance
00333   * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
00334   * @retval None
00335   */
00336 __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
00337 {
00338   __IO uint16_t *pReg;
00339
00340   pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);                             /* Derogation MisraC2012 R.11.5 */
00341   *pReg = InData;
00342 }
00343
00344 /**
00345   * @brief  Write given 8-bit data to the CRC calculator
00346   * @rmtoll DR           DR            LL_CRC_FeedData8
00347   * @param  CRCx CRC Instance
00348   * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
00349   * @retval None
00350   */
00351 __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
00352 {
00353   *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
00354 }
00355
00356 /**
00357   * @brief  Return current CRC calculation result. 32 bits value is returned.
00358   * @rmtoll DR           DR            LL_CRC_ReadData32
00359   * @param  CRCx CRC Instance
00360   * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
00361   */
00362 __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
00363 {
00364   return (uint32_t)(READ_REG(CRCx->DR));
00365 }
00366
00367 /**
00368   * @brief  Return current CRC calculation result. 16 bits value is returned.
00369   * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
00370   * @rmtoll DR           DR            LL_CRC_ReadData16
00371   * @param  CRCx CRC Instance
00372   * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
00373   */
00374 __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
00375 {
00376   return (uint16_t)READ_REG(CRCx->DR);
00377 }
00378
00379 /**
00380   * @brief  Return current CRC calculation result. 8 bits value is returned.
00381   * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
00382   * @rmtoll DR           DR            LL_CRC_ReadData8
00383   * @param  CRCx CRC Instance
00384   * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
00385   */
00386 __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
00387 {
00388   return (uint8_t)READ_REG(CRCx->DR);
00389 }
00390
00391 /**
00392   * @brief  Return current CRC calculation result. 7 bits value is returned.
00393   * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
00394   * @rmtoll DR           DR            LL_CRC_ReadData7
00395   * @param  CRCx CRC Instance
00396   * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
00397   */
00398 __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
00399 {
00400   return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
00401 }
00402
00403 /**
00404   * @brief  Return data stored in the Independent Data(IDR) register.
00405   * @note   This register can be used as a temporary storage location for one 32-bit long data.
00406   * @rmtoll IDR          IDR           LL_CRC_Read_IDR
00407   * @param  CRCx CRC Instance
00408   * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
00409   */
00410 __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
00411 {
00412   return (uint32_t)(READ_REG(CRCx->IDR));
00413 }
00414
00415 /**
00416   * @brief  Store data in the Independent Data(IDR) register.
00417   * @note   This register can be used as a temporary storage location for one 32-bit long data.
00418   * @rmtoll IDR          IDR           LL_CRC_Write_IDR
00419   * @param  CRCx CRC Instance
00420   * @param  InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
00421   * @retval None
00422   */
00423 __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
00424 {
00425   *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
00426 }
00427 /**
00428   * @}
00429   */
00430
00431 #if defined(USE_FULL_LL_DRIVER)
00432 /** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
00433   * @{
00434   */
00435
00436 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
00437
00438 /**
00439   * @}
00440   */
00441 #endif /* USE_FULL_LL_DRIVER */
00442
00443 /**
00444   * @}
00445   */
00446
00447 /**
00448   * @}
00449   */
00450
00451 #endif /* defined(CRC) */
00452
00453 /**
00454   * @}
00455   */
00456
00457 #ifdef __cplusplus
00458 }
00459 #endif
00460
00461 #endif /* STM32G0xx_LL_CRC_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_crs.c Source File

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stm32g0xx_ll_crs.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @brief   CRS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_crs.h"
00022 #include "stm32g0xx_ll_bus.h"
00023
00024 /** @addtogroup STM32G0xx_LL_Driver
00025   * @{
00026   */
00027
00028 #if defined(CRS)
00029
00030 /** @defgroup CRS_LL CRS
00031   * @{
00032   */
00033
00034 /* Private types -------------------------------------------------------------*/
00035 /* Private variables ---------------------------------------------------------*/
00036 /* Private constants ---------------------------------------------------------*/
00037 /* Private macros ------------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039
00040 /* Exported functions --------------------------------------------------------*/
00041 /** @addtogroup CRS_LL_Exported_Functions
00042   * @{
00043   */
00044
00045 /** @addtogroup CRS_LL_EF_Init
00046   * @{
00047   */
00048
00049 /**
00050   * @brief  De-Initializes CRS peripheral registers to their default reset values.
00051   * @retval An ErrorStatus enumeration value:
00052   *          - SUCCESS: CRS registers are de-initialized
00053   *          - ERROR: not applicable
00054   */
00055 ErrorStatus LL_CRS_DeInit(void)
00056 {
00057   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
00058   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
00059
00060   return  SUCCESS;
00061 }
00062
00063
00064
00065 /**
00066   * @}
00067   */
00068
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 #endif /* defined(CRS) */
00078
00079 /**
00080   * @}
00081   */
00082
00083 #endif /* USE_FULL_LL_DRIVER */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_crs.h Source File

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stm32g0xx_ll_crs.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRS LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_CRS_H
00021 #define STM32G0xx_LL_CRS_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(CRS)
00035
00036 /** @defgroup CRS_LL CRS
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
00048   * @{
00049   */
00050
00051 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
00052   * @brief    Flags defines which can be used with LL_CRS_ReadReg function
00053   * @{
00054   */
00055 #define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
00056 #define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
00057 #define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
00058 #define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
00059 #define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
00060 #define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
00061 #define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup CRS_LL_EC_IT IT Defines
00067   * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
00068   * @{
00069   */
00070 #define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
00071 #define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
00072 #define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
00073 #define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
00074 /**
00075   * @}
00076   */
00077
00078 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
00079   * @{
00080   */
00081 #define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */
00082 #define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00083 #define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00084 #define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00085 #define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00086 #define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00087 #define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00088 #define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
00094   * @{
00095   */
00096 #define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal source GPIO */
00097 #define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00098 #define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
00104   * @{
00105   */
00106 #define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */
00107 #define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
00113   * @{
00114   */
00115 #define LL_CRS_FREQ_ERROR_DIR_UP           0x00000000U         /*!< Upcounting direction, the actual frequency is above the target */
00116 #define LL_CRS_FREQ_ERROR_DIR_DOWN         CRS_ISR_FEDIR       /*!< Downcounting direction, the actual frequency is below the target */
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
00122   * @{
00123   */
00124 /**
00125   * @brief Reset value of the RELOAD field
00126   * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
00127   *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
00128   */
00129 #define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU
00130
00131 /**
00132   * @brief Reset value of Frequency error limit.
00133   */
00134 #define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U
00135
00136 /**
00137   * @brief Reset value of the HSI48 Calibration field
00138   * @note The default value is 64, which corresponds to the middle of the trimming interval.
00139   *       The trimming step is specified in the product datasheet.
00140   *       A higher TRIM value corresponds to a higher output frequency.
00141   */
00142 #define LL_CRS_HSI48CALIBRATION_DEFAULT    0x00000040U
00143 /**
00144   * @}
00145   */
00146
00147 /**
00148   * @}
00149   */
00150
00151 /* Exported macro ------------------------------------------------------------*/
00152 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
00153   * @{
00154   */
00155
00156 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
00157   * @{
00158   */
00159
00160 /**
00161   * @brief  Write a value in CRS register
00162   * @param  __INSTANCE__ CRS Instance
00163   * @param  __REG__ Register to be written
00164   * @param  __VALUE__ Value to be written in the register
00165   * @retval None
00166   */
00167 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00168
00169 /**
00170   * @brief  Read a value in CRS register
00171   * @param  __INSTANCE__ CRS Instance
00172   * @param  __REG__ Register to be read
00173   * @retval Register value
00174   */
00175 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
00181   * @{
00182   */
00183
00184 /**
00185   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
00186   * @note   The RELOAD value should be selected according to the ratio between
00187   *         the target frequency and the frequency of the synchronization source after
00188   *         prescaling. It is then decreased by one in order to reach the expected
00189   *         synchronization on the zero value. The formula is the following:
00190   *              RELOAD = (fTARGET / fSYNC) -1
00191   * @param  __FTARGET__ Target frequency (value in Hz)
00192   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
00193   * @retval Reload value (in Hz)
00194   */
00195 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
00196
00197 /**
00198   * @}
00199   */
00200
00201 /**
00202   * @}
00203   */
00204
00205 /* Exported functions --------------------------------------------------------*/
00206 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
00207   * @{
00208   */
00209
00210 /** @defgroup CRS_LL_EF_Configuration Configuration
00211   * @{
00212   */
00213
00214 /**
00215   * @brief  Enable Frequency error counter
00216   * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
00217   * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
00218   * @retval None
00219   */
00220 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
00221 {
00222   SET_BIT(CRS->CR, CRS_CR_CEN);
00223 }
00224
00225 /**
00226   * @brief  Disable Frequency error counter
00227   * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
00228   * @retval None
00229   */
00230 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
00231 {
00232   CLEAR_BIT(CRS->CR, CRS_CR_CEN);
00233 }
00234
00235 /**
00236   * @brief  Check if Frequency error counter is enabled or not
00237   * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
00238   * @retval State of bit (1 or 0).
00239   */
00240 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
00241 {
00242   return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
00243 }
00244
00245 /**
00246   * @brief  Enable Automatic trimming counter
00247   * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
00248   * @retval None
00249   */
00250 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
00251 {
00252   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00253 }
00254
00255 /**
00256   * @brief  Disable Automatic trimming counter
00257   * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
00258   * @retval None
00259   */
00260 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
00261 {
00262   CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00263 }
00264
00265 /**
00266   * @brief  Check if Automatic trimming is enabled or not
00267   * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
00268   * @retval State of bit (1 or 0).
00269   */
00270 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
00271 {
00272   return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
00273 }
00274
00275 /**
00276   * @brief  Set HSI48 oscillator smooth trimming
00277   * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
00278   * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
00279   * @param  Value a number between Min_Data = 0 and Max_Data = 127
00280   * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
00281   * @retval None
00282   */
00283 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
00284 {
00285   MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
00286 }
00287
00288 /**
00289   * @brief  Get HSI48 oscillator smooth trimming
00290   * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
00291   * @retval a number between Min_Data = 0 and Max_Data = 127
00292   */
00293 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
00294 {
00295   return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
00296 }
00297
00298 /**
00299   * @brief  Set counter reload value
00300   * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
00301   * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
00302   * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
00303   *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
00304   * @retval None
00305   */
00306 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
00307 {
00308   MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
00309 }
00310
00311 /**
00312   * @brief  Get counter reload value
00313   * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
00314   * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
00315   */
00316 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
00317 {
00318   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
00319 }
00320
00321 /**
00322   * @brief  Set frequency error limit
00323   * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
00324   * @param  Value a number between Min_Data = 0 and Max_Data = 255
00325   * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
00326   * @retval None
00327   */
00328 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
00329 {
00330   MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
00331 }
00332
00333 /**
00334   * @brief  Get frequency error limit
00335   * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
00336   * @retval A number between Min_Data = 0 and Max_Data = 255
00337   */
00338 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
00339 {
00340   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
00341 }
00342
00343 /**
00344   * @brief  Set division factor for SYNC signal
00345   * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
00346   * @param  Divider This parameter can be one of the following values:
00347   *         @arg @ref LL_CRS_SYNC_DIV_1
00348   *         @arg @ref LL_CRS_SYNC_DIV_2
00349   *         @arg @ref LL_CRS_SYNC_DIV_4
00350   *         @arg @ref LL_CRS_SYNC_DIV_8
00351   *         @arg @ref LL_CRS_SYNC_DIV_16
00352   *         @arg @ref LL_CRS_SYNC_DIV_32
00353   *         @arg @ref LL_CRS_SYNC_DIV_64
00354   *         @arg @ref LL_CRS_SYNC_DIV_128
00355   * @retval None
00356   */
00357 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
00358 {
00359   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
00360 }
00361
00362 /**
00363   * @brief  Get division factor for SYNC signal
00364   * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
00365   * @retval Returned value can be one of the following values:
00366   *         @arg @ref LL_CRS_SYNC_DIV_1
00367   *         @arg @ref LL_CRS_SYNC_DIV_2
00368   *         @arg @ref LL_CRS_SYNC_DIV_4
00369   *         @arg @ref LL_CRS_SYNC_DIV_8
00370   *         @arg @ref LL_CRS_SYNC_DIV_16
00371   *         @arg @ref LL_CRS_SYNC_DIV_32
00372   *         @arg @ref LL_CRS_SYNC_DIV_64
00373   *         @arg @ref LL_CRS_SYNC_DIV_128
00374   */
00375 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
00376 {
00377   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
00378 }
00379
00380 /**
00381   * @brief  Set SYNC signal source
00382   * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
00383   * @param  Source This parameter can be one of the following values:
00384   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00385   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00386   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00387   * @retval None
00388   */
00389 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
00390 {
00391   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
00392 }
00393
00394 /**
00395   * @brief  Get SYNC signal source
00396   * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
00397   * @retval Returned value can be one of the following values:
00398   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00399   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00400   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00401   */
00402 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
00403 {
00404   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
00405 }
00406
00407 /**
00408   * @brief  Set input polarity for the SYNC signal source
00409   * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
00410   * @param  Polarity This parameter can be one of the following values:
00411   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00412   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00413   * @retval None
00414   */
00415 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
00416 {
00417   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
00418 }
00419
00420 /**
00421   * @brief  Get input polarity for the SYNC signal source
00422   * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
00423   * @retval Returned value can be one of the following values:
00424   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00425   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00426   */
00427 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
00428 {
00429   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
00430 }
00431
00432 /**
00433   * @brief  Configure CRS for the synchronization
00434   * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
00435   *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
00436   *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
00437   *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
00438   *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
00439   *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
00440   * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127
00441   * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
00442   * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
00443   * @param  Settings This parameter can be a combination of the following values:
00444   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
00445   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
00446   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
00447   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
00448   * @retval None
00449   */
00450 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
00451 {
00452   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
00453   MODIFY_REG(CRS->CFGR,
00454              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
00455              ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
00456 }
00457
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
00463   * @{
00464   */
00465
00466 /**
00467   * @brief  Generate software SYNC event
00468   * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
00469   * @retval None
00470   */
00471 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
00472 {
00473   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
00474 }
00475
00476 /**
00477   * @brief  Get the frequency error direction latched in the time of the last
00478   * SYNC event
00479   * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
00480   * @retval Returned value can be one of the following values:
00481   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
00482   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
00483   */
00484 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
00485 {
00486   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
00487 }
00488
00489 /**
00490   * @brief  Get the frequency error counter value latched in the time of the last SYNC event
00491   * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
00492   * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00493   */
00494 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
00495 {
00496   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
00497 }
00498
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
00504   * @{
00505   */
00506
00507 /**
00508   * @brief  Check if SYNC event OK signal occurred or not
00509   * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
00510   * @retval State of bit (1 or 0).
00511   */
00512 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
00513 {
00514   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
00515 }
00516
00517 /**
00518   * @brief  Check if SYNC warning signal occurred or not
00519   * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
00520   * @retval State of bit (1 or 0).
00521   */
00522 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
00523 {
00524   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
00525 }
00526
00527 /**
00528   * @brief  Check if Synchronization or trimming error signal occurred or not
00529   * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
00530   * @retval State of bit (1 or 0).
00531   */
00532 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
00533 {
00534   return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
00535 }
00536
00537 /**
00538   * @brief  Check if Expected SYNC signal occurred or not
00539   * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
00540   * @retval State of bit (1 or 0).
00541   */
00542 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
00543 {
00544   return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
00545 }
00546
00547 /**
00548   * @brief  Check if SYNC error signal occurred or not
00549   * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
00550   * @retval State of bit (1 or 0).
00551   */
00552 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
00553 {
00554   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
00555 }
00556
00557 /**
00558   * @brief  Check if SYNC missed error signal occurred or not
00559   * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
00560   * @retval State of bit (1 or 0).
00561   */
00562 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
00563 {
00564   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
00565 }
00566
00567 /**
00568   * @brief  Check if Trimming overflow or underflow occurred or not
00569   * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
00570   * @retval State of bit (1 or 0).
00571   */
00572 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
00573 {
00574   return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
00575 }
00576
00577 /**
00578   * @brief  Clear the SYNC event OK flag
00579   * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
00580   * @retval None
00581   */
00582 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
00583 {
00584   WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
00585 }
00586
00587 /**
00588   * @brief  Clear the  SYNC warning flag
00589   * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
00590   * @retval None
00591   */
00592 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
00593 {
00594   WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
00595 }
00596
00597 /**
00598   * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
00599   * the ERR flag
00600   * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
00601   * @retval None
00602   */
00603 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
00604 {
00605   WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
00606 }
00607
00608 /**
00609   * @brief  Clear Expected SYNC flag
00610   * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
00611   * @retval None
00612   */
00613 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
00614 {
00615   WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
00616 }
00617
00618 /**
00619   * @}
00620   */
00621
00622 /** @defgroup CRS_LL_EF_IT_Management IT_Management
00623   * @{
00624   */
00625
00626 /**
00627   * @brief  Enable SYNC event OK interrupt
00628   * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
00629   * @retval None
00630   */
00631 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
00632 {
00633   SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00634 }
00635
00636 /**
00637   * @brief  Disable SYNC event OK interrupt
00638   * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
00639   * @retval None
00640   */
00641 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
00642 {
00643   CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00644 }
00645
00646 /**
00647   * @brief  Check if SYNC event OK interrupt is enabled or not
00648   * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
00649   * @retval State of bit (1 or 0).
00650   */
00651 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
00652 {
00653   return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
00654 }
00655
00656 /**
00657   * @brief  Enable SYNC warning interrupt
00658   * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
00659   * @retval None
00660   */
00661 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
00662 {
00663   SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00664 }
00665
00666 /**
00667   * @brief  Disable SYNC warning interrupt
00668   * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
00669   * @retval None
00670   */
00671 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
00672 {
00673   CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00674 }
00675
00676 /**
00677   * @brief  Check if SYNC warning interrupt is enabled or not
00678   * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
00679   * @retval State of bit (1 or 0).
00680   */
00681 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
00682 {
00683   return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
00684 }
00685
00686 /**
00687   * @brief  Enable Synchronization or trimming error interrupt
00688   * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
00689   * @retval None
00690   */
00691 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
00692 {
00693   SET_BIT(CRS->CR, CRS_CR_ERRIE);
00694 }
00695
00696 /**
00697   * @brief  Disable Synchronization or trimming error interrupt
00698   * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
00699   * @retval None
00700   */
00701 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
00702 {
00703   CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
00704 }
00705
00706 /**
00707   * @brief  Check if Synchronization or trimming error interrupt is enabled or not
00708   * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
00709   * @retval State of bit (1 or 0).
00710   */
00711 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
00712 {
00713   return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
00714 }
00715
00716 /**
00717   * @brief  Enable Expected SYNC interrupt
00718   * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
00719   * @retval None
00720   */
00721 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
00722 {
00723   SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
00724 }
00725
00726 /**
00727   * @brief  Disable Expected SYNC interrupt
00728   * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
00729   * @retval None
00730   */
00731 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
00732 {
00733   CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
00734 }
00735
00736 /**
00737   * @brief  Check if Expected SYNC interrupt is enabled or not
00738   * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
00739   * @retval State of bit (1 or 0).
00740   */
00741 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
00742 {
00743   return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
00744 }
00745
00746 /**
00747   * @}
00748   */
00749
00750 #if defined(USE_FULL_LL_DRIVER)
00751 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
00752   * @{
00753   */
00754
00755 ErrorStatus LL_CRS_DeInit(void);
00756
00757 /**
00758   * @}
00759   */
00760 #endif /* USE_FULL_LL_DRIVER */
00761
00762 /**
00763   * @}
00764   */
00765
00766 /**
00767   * @}
00768   */
00769
00770 #endif /* defined(CRS) */
00771
00772 /**
00773   * @}
00774   */
00775
00776 #ifdef __cplusplus
00777 }
00778 #endif
00779
00780 #endif /* STM32G0xx_LL_CRS_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dac.c Source File

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stm32g0xx_ll_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_dac.c
00004   * @author  MCD Application Team
00005   * @brief   DAC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_dac.h"
00022 #include "stm32g0xx_ll_bus.h"
00023
00024 #ifdef USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(DAC1)
00035
00036 /** @addtogroup DAC_LL DAC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /** @addtogroup DAC_LL_Private_Macros
00046   * @{
00047   */
00048 #define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)        \
00049   (  ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)      \
00050      || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)   \
00051   )
00052
00053 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00054   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00055    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
00056    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00057    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
00058    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00059    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00060    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00061    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT)                     \
00062    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT)                     \
00063    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00064   )
00065
00066 #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)              \
00067   (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)        \
00068       || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
00069       || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
00070   )
00071
00072 #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)  \
00073   ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)                               \
00074      && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                           \
00075            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                     \
00076            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                     \
00077            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                     \
00078            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                     \
00079            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                     \
00080            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                     \
00081            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                     \
00082            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                     \
00083            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                     \
00084            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                    \
00085            || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                   \
00086     )                                                                                                     \
00087     ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)                          \
00088        && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                           \
00089              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                        \
00090              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                        \
00091              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                       \
00092              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                       \
00093              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                       \
00094              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                      \
00095              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                      \
00096              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                      \
00097              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                     \
00098              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                     \
00099              || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                    \
00100       )                                                                                                   \
00101   )
00102
00103 #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
00104   (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
00105       || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                 \
00106   )
00107
00108 #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)                     \
00109   (   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
00110       || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)           \
00111   )
00112
00113 #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)                                 \
00114   (   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
00115       || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)             \
00116   )
00117
00118 /**
00119   * @}
00120   */
00121
00122
00123 /* Private function prototypes -----------------------------------------------*/
00124
00125 /* Exported functions --------------------------------------------------------*/
00126 /** @addtogroup DAC_LL_Exported_Functions
00127   * @{
00128   */
00129
00130 /** @addtogroup DAC_LL_EF_Init
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  De-initialize registers of the selected DAC instance
00136   *         to their default reset values.
00137   * @param  DACx DAC instance
00138   * @retval An ErrorStatus enumeration value:
00139   *          - SUCCESS: DAC registers are de-initialized
00140   *          - ERROR: not applicable
00141   */
00142 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
00143 {
00144   /* Check the parameters */
00145   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00146
00147   /* Force reset of DAC clock */
00148   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
00149
00150   /* Release reset of DAC clock */
00151   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
00152
00153   return SUCCESS;
00154 }
00155
00156 /**
00157   * @brief  Initialize some features of DAC channel.
00158   * @note   @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel.
00159   *         Leaving it ready to be enabled and output:
00160   *         a level by calling one of
00161   *           @ref LL_DAC_ConvertData12RightAligned
00162   *           @ref LL_DAC_ConvertData12LeftAligned
00163   *           @ref LL_DAC_ConvertData8RightAligned
00164   *         or one of the supported autogenerated wave.
00165   * @note   This function allows configuration of:
00166   *          - Output mode
00167   *          - Trigger
00168   *          - Wave generation
00169   * @note   The setting of these parameters by function @ref LL_DAC_Init()
00170   *         is conditioned to DAC state:
00171   *         DAC channel must be disabled.
00172   * @param  DACx DAC instance
00173   * @param  DAC_Channel This parameter can be one of the following values:
00174   *         @arg @ref LL_DAC_CHANNEL_1
00175   *         @arg @ref LL_DAC_CHANNEL_2
00176   * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
00177   * @retval An ErrorStatus enumeration value:
00178   *          - SUCCESS: DAC registers are initialized
00179   *          - ERROR: DAC registers are not initialized
00180   */
00181 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
00182 {
00183   ErrorStatus status = SUCCESS;
00184
00185   /* Check the parameters */
00186   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00187   assert_param(IS_LL_DAC_CHANNEL(DAC_Channel));
00188   assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
00189   assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
00190   assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection));
00191   assert_param(IS_LL_DAC_OUTPUT_MODE(DAC_InitStruct->OutputMode));
00192   assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
00193   if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00194   {
00195     assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration,
00196                                                   DAC_InitStruct->WaveAutoGenerationConfig));
00197   }
00198
00199   /* Note: Hardware constraint (refer to description of this function)        */
00200   /*       DAC instance must be disabled.                                     */
00201   if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL)
00202   {
00203     /* Configuration of DAC channel:                                          */
00204     /*  - TriggerSource                                                       */
00205     /*  - WaveAutoGeneration                                                  */
00206     /*  - OutputBuffer                                                        */
00207     /*  - OutputConnection                                                    */
00208     /*  - OutputMode                                                          */
00209     if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00210     {
00211       MODIFY_REG(DACx->CR,
00212                  (DAC_CR_TSEL1
00213                   | DAC_CR_WAVE1
00214                   | DAC_CR_MAMP1
00215                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00216                  ,
00217                  (DAC_InitStruct->TriggerSource
00218                   | DAC_InitStruct->WaveAutoGeneration
00219                   | DAC_InitStruct->WaveAutoGenerationConfig
00220                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00221                 );
00222     }
00223     else
00224     {
00225       MODIFY_REG(DACx->CR,
00226                  (DAC_CR_TSEL1
00227                   | DAC_CR_WAVE1
00228                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00229                  ,
00230                  (DAC_InitStruct->TriggerSource
00231                   | LL_DAC_WAVE_AUTO_GENERATION_NONE
00232                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00233                 );
00234     }
00235     MODIFY_REG(DACx->MCR,
00236                (DAC_MCR_MODE1_1
00237                 | DAC_MCR_MODE1_0
00238                 | DAC_MCR_MODE1_2
00239                ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00240                ,
00241                (DAC_InitStruct->OutputBuffer
00242                 | DAC_InitStruct->OutputConnection
00243                 | DAC_InitStruct->OutputMode
00244                ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00245               );
00246   }
00247   else
00248   {
00249     /* Initialization error: DAC instance is not disabled.                    */
00250     status = ERROR;
00251   }
00252   return status;
00253 }
00254
00255 /**
00256   * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
00257   * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
00258   *                       whose fields will be set to default values.
00259   * @retval None
00260   */
00261 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
00262 {
00263   /* Set DAC_InitStruct fields to default values */
00264   DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
00265   DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
00266   /* Note: Parameter discarded if wave auto generation is disabled,           */
00267   /*       set anyway to its default value.                                   */
00268   DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
00269   DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
00270   DAC_InitStruct->OutputConnection         = LL_DAC_OUTPUT_CONNECT_GPIO;
00271   DAC_InitStruct->OutputMode               = LL_DAC_OUTPUT_MODE_NORMAL;
00272 }
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 /**
00283   * @}
00284   */
00285
00286 #endif /* DAC1 */
00287
00288 /**
00289   * @}
00290   */
00291
00292 #endif /* USE_FULL_LL_DRIVER */
00293
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dac.h Source File

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stm32g0xx_ll_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_dac.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DAC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_DAC_H
00021 #define STM32G0xx_LL_DAC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(DAC1)
00035
00036 /** @defgroup DAC_LL DAC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
00045   * @{
00046   */
00047
00048 /* Internal masks for DAC channels definition */
00049 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
00050 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR            */
00051 /* - channel bits position into register SWTRIG                               */
00052 /* - channel register offset of data holding register DHRx                    */
00053 /* - channel register offset of data output register DORx                     */
00054 /* - channel register offset of sample-and-hold sample time register SHSRx    */
00055 #define DAC_CR_CH1_BITOFFSET           0UL   /* Position of channel bits into registers
00056                                                 CR, MCR, CCR, SHHR, SHRR of channel 1 */
00057 #define DAC_CR_CH2_BITOFFSET           16UL  /* Position of channel bits into registers
00058                                                 CR, MCR, CCR, SHHR, SHRR of channel 2 */
00059 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
00060
00061 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
00062 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
00063 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
00064
00065 #define DAC_REG_DHR12R1_REGOFFSET      0x00000000UL            /* Register DHR12Rx channel 1 taken as reference */
00066 #define DAC_REG_DHR12L1_REGOFFSET      0x00100000UL            /* Register offset of DHR12Lx channel 1 versus
00067                                                                   DHR12Rx channel 1 (shifted left of 20 bits)   */
00068 #define DAC_REG_DHR8R1_REGOFFSET       0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus
00069                                                                   DHR12Rx channel 1 (shifted left of 24 bits)   */
00070
00071 #define DAC_REG_DHR12R2_REGOFFSET      0x30000000UL            /* Register offset of DHR12Rx channel 2 versus
00072                                                                   DHR12Rx channel 1 (shifted left of 28 bits)   */
00073 #define DAC_REG_DHR12L2_REGOFFSET      0x00400000UL            /* Register offset of DHR12Lx channel 2 versus
00074                                                                   DHR12Rx channel 1 (shifted left of 20 bits)   */
00075 #define DAC_REG_DHR8R2_REGOFFSET       0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus
00076                                                                   DHR12Rx channel 1 (shifted left of 24 bits)   */
00077
00078 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
00079 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
00080 #define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000UL
00081 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK\
00082                                         | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
00083
00084 #define DAC_REG_DOR1_REGOFFSET         0x00000000UL            /* Register DORx channel 1 taken as reference */
00085
00086 #define DAC_REG_DOR2_REGOFFSET         0x00000020UL            /* Register offset of DORx channel 1 versus
00087                                                                   DORx channel 2 (shifted left of 5 bits)    */
00088 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
00089
00090 #define DAC_REG_SHSR1_REGOFFSET        0x00000000UL            /* Register SHSRx channel 1 taken as reference */
00091 #define DAC_REG_SHSR2_REGOFFSET        0x00000040UL            /* Register offset of SHSRx channel 1 versus
00092                                                                   SHSRx channel 2 (shifted left of 6 bits)    */
00093 #define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
00094
00095
00096 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0         0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
00097                                                                    DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
00098 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of DORx registers offset when shifted
00099                                                                    to position 0                                    */
00100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0       0x00000001UL /* Mask of SHSRx registers offset when shifted
00101                                                                    to position 0                                    */
00102
00103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           28UL  /* Position of bits register offset of DHR12Rx
00104                                                                    channel 1 or 2 versus DHR12Rx channel 1
00105                                                                    (shifted left of 28 bits)                   */
00106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20UL  /* Position of bits register offset of DHR12Lx
00107                                                                    channel 1 or 2 versus DHR12Rx channel 1
00108                                                                    (shifted left of 20 bits)                   */
00109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24UL  /* Position of bits register offset of DHR8Rx
00110                                                                    channel 1 or 2 versus DHR12Rx channel 1
00111                                                                    (shifted left of 24 bits)                   */
00112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS               5UL  /* Position of bits register offset of DORx
00113                                                                    channel 1 or 2 versus DORx channel 1
00114                                                                    (shifted left of 5 bits)                    */
00115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS              6UL  /* Position of bits register offset of SHSRx
00116                                                                    channel 1 or 2 versus SHSRx channel 1
00117                                                                    (shifted left of 6 bits)                    */
00118
00119 /* DAC registers bits positions */
00120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                DAC_DHR12RD_DACC2DHR_Pos
00121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                DAC_DHR12LD_DACC2DHR_Pos
00122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                 DAC_DHR8RD_DACC2DHR_Pos
00123
00124 /* Miscellaneous data */
00125 #define DAC_DIGITAL_SCALE_12BITS                  4095UL   /* Full-scale digital value with a resolution of 12
00126                                                               bits (voltage range determined by analog voltage
00127                                                               references Vref+ and Vref-, refer to reference manual) */
00128
00129 /**
00130   * @}
00131   */
00132
00133
00134 /* Private macros ------------------------------------------------------------*/
00135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
00136   * @{
00137   */
00138
00139 /**
00140   * @brief  Driver macro reserved for internal use: set a pointer to
00141   *         a register from a register basis from which an offset
00142   *         is applied.
00143   * @param  __REG__ Register basis from which the offset is applied.
00144   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00145   * @retval Pointer to register address
00146   */
00147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00148   ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
00149
00150 /**
00151   * @}
00152   */
00153
00154
00155 /* Exported types ------------------------------------------------------------*/
00156 #if defined(USE_FULL_LL_DRIVER)
00157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  Structure definition of some features of DAC instance.
00163   */
00164 typedef struct
00165 {
00166   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel:
00167                                              internal (SW start) or from external peripheral
00168                                              (timer event, external interrupt line).
00169                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
00170
00171                                              This feature can be modified afterwards using unitary
00172                                              function @ref LL_DAC_SetTriggerSource(). */
00173
00174   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
00175                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
00176
00177                                              This feature can be modified afterwards using unitary
00178                                              function @ref LL_DAC_SetWaveAutoGeneration(). */
00179
00180   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
00181                                              If waveform automatic generation mode is set to noise, this parameter
00182                                              can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
00183                                              If waveform automatic generation mode is set to triangle,
00184                                              this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
00185                                              @note If waveform automatic generation mode is disabled,
00186                                               this parameter is discarded.
00187
00188                                              This feature can be modified afterwards using unitary
00189                                              function @ref LL_DAC_SetWaveNoiseLFSR(),
00190                                              @ref LL_DAC_SetWaveTriangleAmplitude()
00191                                              depending on the wave automatic generation selected. */
00192
00193   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
00194                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
00195
00196                                              This feature can be modified afterwards using unitary
00197                                              function @ref LL_DAC_SetOutputBuffer(). */
00198
00199   uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.
00200                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
00201
00202                                              This feature can be modified afterwards using unitary
00203                                              function @ref LL_DAC_SetOutputConnection(). */
00204
00205   uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC
00206                                              channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
00207
00208                                              This feature can be modified afterwards using unitary
00209                                              function @ref LL_DAC_SetOutputMode(). */
00210 } LL_DAC_InitTypeDef;
00211
00212 /**
00213   * @}
00214   */
00215 #endif /* USE_FULL_LL_DRIVER */
00216
00217 /* Exported constants --------------------------------------------------------*/
00218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
00219   * @{
00220   */
00221
00222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
00223   * @brief    Flags defines which can be used with LL_DAC_ReadReg function
00224   * @{
00225   */
00226 /* DAC channel 1 flags */
00227 #define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
00228 #define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
00229 #define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */
00230
00231 /* DAC channel 2 flags */
00232 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
00233 #define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
00234 #define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup DAC_LL_EC_IT DAC interruptions
00241   * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
00242   * @{
00243   */
00244 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
00245
00246 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
00253   * @{
00254   */
00255 #define LL_DAC_CHANNEL_1                   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
00256 #define LL_DAC_CHANNEL_2                   (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
00262   * @{
00263   */
00264 #define LL_DAC_MODE_NORMAL_OPERATION       0x00000000UL            /*!< DAC channel in mode normal operation */
00265 #define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
00271   * @{
00272   */
00273 #define LL_DAC_TRIG_SOFTWARE               0x00000000UL                                                        /*!< DAC channel conversion trigger internal (SW start) */
00274 #define LL_DAC_TRIG_EXT_TIM1_TRGO          (                                                   DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
00275 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (                                  DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
00276 #define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */
00277 #define LL_DAC_TRIG_EXT_TIM6_TRGO          (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
00278 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
00279 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (DAC_CR_TSEL1_3                                                   ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
00280 #define LL_DAC_TRIG_EXT_LPTIM1_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
00281 #define LL_DAC_TRIG_EXT_LPTIM2_OUT         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
00282 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
00288   * @{
00289   */
00290 #define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000UL                    /*!< DAC channel wave auto generation mode disabled. */
00291 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (               DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
00292 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1               ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
00298   * @{
00299   */
00300 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000UL                                                        /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
00301 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
00302 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
00303 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
00304 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
00305 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
00306 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
00307 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
00308 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
00309 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
00310 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
00311 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
00317   * @{
00318   */
00319 #define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000UL                                                        /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
00320 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
00321 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
00322 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
00323 #define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
00324 #define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
00325 #define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
00326 #define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
00327 #define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
00328 #define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
00329 #define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
00330 #define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
00336   * @{
00337   */
00338 #define LL_DAC_OUTPUT_MODE_NORMAL          0x00000000UL            /*!< The selected DAC channel output is on mode normal. */
00339 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
00345   * @{
00346   */
00347 #define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000UL            /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
00348 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
00354   * @{
00355   */
00356 #define LL_DAC_OUTPUT_CONNECT_GPIO         0x00000000UL            /*!< The selected DAC channel output is connected to external pin */
00357 #define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
00363   * @{
00364   */
00365 #define LL_DAC_RESOLUTION_12B              0x00000000UL            /*!< DAC channel resolution 12 bits */
00366 #define LL_DAC_RESOLUTION_8B               0x00000002UL            /*!< DAC channel resolution 8 bits */
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
00372   * @{
00373   */
00374 /* List of DAC registers intended to be used (most commonly) with             */
00375 /* DMA transfer.                                                              */
00376 /* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
00377 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
00378 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
00379 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
00385   * @note   Only DAC peripheral HW delays are defined in DAC LL driver driver,
00386   *         not timeout values.
00387   *         For details on delays values, refer to descriptions in source code
00388   *         above each literal definition.
00389   * @{
00390   */
00391
00392 /* Delay for DAC channel voltage settling time from DAC channel startup       */
00393 /* (transition from disable to enable).                                       */
00394 /* Note: DAC channel startup time depends on board application environment:   */
00395 /*       impedance connected to DAC channel output.                           */
00396 /*       The delay below is specified under conditions:                       */
00397 /*        - voltage maximum transition (lowest to highest value)              */
00398 /*        - until voltage reaches final value +-1LSB                          */
00399 /*        - DAC channel output buffer enabled                                 */
00400 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
00401 /* Literal set to maximum value (refer to device datasheet,                   */
00402 /* parameter "tWAKEUP").                                                      */
00403 /* Unit: us                                                                   */
00404 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             8UL  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
00405
00406 /* Delay for DAC channel voltage settling time.                               */
00407 /* Note: DAC channel startup time depends on board application environment:   */
00408 /*       impedance connected to DAC channel output.                           */
00409 /*       The delay below is specified under conditions:                       */
00410 /*        - voltage maximum transition (lowest to highest value)              */
00411 /*        - until voltage reaches final value +-1LSB                          */
00412 /*        - DAC channel output buffer enabled                                 */
00413 /*        - load impedance of 5kOhm min, 50pF max                             */
00414 /* Literal set to maximum value (refer to device datasheet,                   */
00415 /* parameter "tSETTLING").                                                    */
00416 /* Unit: us                                                                   */
00417 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US                     3UL /*!< Delay for DAC channel voltage settling time */
00418
00419 /**
00420   * @}
00421   */
00422
00423 /**
00424   * @}
00425   */
00426
00427 /* Exported macro ------------------------------------------------------------*/
00428 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
00429   * @{
00430   */
00431
00432 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
00433   * @{
00434   */
00435
00436 /**
00437   * @brief  Write a value in DAC register
00438   * @param  __INSTANCE__ DAC Instance
00439   * @param  __REG__ Register to be written
00440   * @param  __VALUE__ Value to be written in the register
00441   * @retval None
00442   */
00443 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00444
00445 /**
00446   * @brief  Read a value in DAC register
00447   * @param  __INSTANCE__ DAC Instance
00448   * @param  __REG__ Register to be read
00449   * @retval Register value
00450   */
00451 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00452
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
00458   * @{
00459   */
00460
00461 /**
00462   * @brief  Helper macro to get DAC channel number in decimal format
00463   *         from literals LL_DAC_CHANNEL_x.
00464   *         Example:
00465   *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
00466   *            will return decimal number "1".
00467   * @note   The input can be a value from functions where a channel
00468   *         number is returned.
00469   * @param  __CHANNEL__ This parameter can be one of the following values:
00470   *         @arg @ref LL_DAC_CHANNEL_1
00471   *         @arg @ref LL_DAC_CHANNEL_2
00472   * @retval 1...2
00473   */
00474 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
00475   ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
00476
00477 /**
00478   * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
00479   *         from number in decimal format.
00480   *         Example:
00481   *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
00482   *           will return a data equivalent to "LL_DAC_CHANNEL_1".
00483   * @note  If the input parameter does not correspond to a DAC channel,
00484   *        this macro returns value '0'.
00485   * @param  __DECIMAL_NB__ 1...2
00486   * @retval Returned value can be one of the following values:
00487   *         @arg @ref LL_DAC_CHANNEL_1
00488   *         @arg @ref LL_DAC_CHANNEL_2
00489   */
00490 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
00491   (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1  ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
00492
00493 /**
00494   * @brief  Helper macro to define the DAC conversion data full-scale digital
00495   *         value corresponding to the selected DAC resolution.
00496   * @note   DAC conversion data full-scale corresponds to voltage range
00497   *         determined by analog voltage references Vref+ and Vref-
00498   *         (refer to reference manual).
00499   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00500   *         @arg @ref LL_DAC_RESOLUTION_12B
00501   *         @arg @ref LL_DAC_RESOLUTION_8B
00502   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
00503   */
00504 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
00505   ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
00506
00507 /**
00508   * @brief  Helper macro to calculate the DAC conversion data (unit: digital
00509   *         value) corresponding to a voltage (unit: mVolt).
00510   * @note   This helper macro is intended to provide input data in voltage
00511   *         rather than digital value,
00512   *         to be used with LL DAC functions such as
00513   *         @ref LL_DAC_ConvertData12RightAligned().
00514   * @note   Analog reference voltage (Vref+) must be either known from
00515   *         user board environment or can be calculated using ADC measurement
00516   *         and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
00517   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
00518   * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
00519   *                         (unit: mVolt).
00520   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00521   *         @arg @ref LL_DAC_RESOLUTION_12B
00522   *         @arg @ref LL_DAC_RESOLUTION_8B
00523   * @retval DAC conversion data (unit: digital value)
00524   */
00525 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
00526                                       __DAC_VOLTAGE__,\
00527                                       __DAC_RESOLUTION__)                      \
00528 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
00529  / (__VREFANALOG_VOLTAGE__)                                                  \
00530 )
00531
00532 /**
00533   * @}
00534   */
00535
00536 /**
00537   * @}
00538   */
00539
00540
00541 /* Exported functions --------------------------------------------------------*/
00542 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
00543   * @{
00544   */
00545 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
00546   * @{
00547   */
00548
00549 /**
00550   * @brief  Set the operating mode for the selected DAC channel:
00551   *         calibration or normal operating mode.
00552   * @rmtoll CR       CEN1           LL_DAC_SetMode\n
00553   *         CR       CEN2           LL_DAC_SetMode
00554   * @param  DACx DAC instance
00555   * @param  DAC_Channel This parameter can be one of the following values:
00556   *         @arg @ref LL_DAC_CHANNEL_1
00557   *         @arg @ref LL_DAC_CHANNEL_2
00558   * @param  ChannelMode This parameter can be one of the following values:
00559   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00560   *         @arg @ref LL_DAC_MODE_CALIBRATION
00561   * @retval None
00562   */
00563 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
00564 {
00565   MODIFY_REG(DACx->CR,
00566              DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00567              ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00568 }
00569
00570 /**
00571   * @brief  Get the operating mode for the selected DAC channel:
00572   *         calibration or normal operating mode.
00573   * @rmtoll CR       CEN1           LL_DAC_GetMode\n
00574   *         CR       CEN2           LL_DAC_GetMode
00575   * @param  DACx DAC instance
00576   * @param  DAC_Channel This parameter can be one of the following values:
00577   *         @arg @ref LL_DAC_CHANNEL_1
00578   *         @arg @ref LL_DAC_CHANNEL_2
00579   * @retval Returned value can be one of the following values:
00580   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00581   *         @arg @ref LL_DAC_MODE_CALIBRATION
00582   */
00583 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00584 {
00585   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00586                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00587                    );
00588 }
00589
00590 /**
00591   * @brief  Set the offset trimming value for the selected DAC channel.
00592   *         Trimming has an impact when output buffer is enabled
00593   *         and is intended to replace factory calibration default values.
00594   * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n
00595   *         CCR      OTRIM2         LL_DAC_SetTrimmingValue
00596   * @param  DACx DAC instance
00597   * @param  DAC_Channel This parameter can be one of the following values:
00598   *         @arg @ref LL_DAC_CHANNEL_1
00599   *         @arg @ref LL_DAC_CHANNEL_2
00600   * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00601   * @retval None
00602   */
00603 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
00604 {
00605   MODIFY_REG(DACx->CCR,
00606              DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00607              TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00608 }
00609
00610 /**
00611   * @brief  Get the offset trimming value for the selected DAC channel.
00612   *         Trimming has an impact when output buffer is enabled
00613   *         and is intended to replace factory calibration default values.
00614   * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n
00615   *         CCR      OTRIM2         LL_DAC_GetTrimmingValue
00616   * @param  DACx DAC instance
00617   * @param  DAC_Channel This parameter can be one of the following values:
00618   *         @arg @ref LL_DAC_CHANNEL_1
00619   *         @arg @ref LL_DAC_CHANNEL_2
00620   * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00621   */
00622 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00623 {
00624   return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00625                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00626                    );
00627 }
00628
00629 /**
00630   * @brief  Set the conversion trigger source for the selected DAC channel.
00631   * @note   For conversion trigger source to be effective, DAC trigger
00632   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00633   * @note   To set conversion trigger source, DAC channel must be disabled.
00634   *         Otherwise, the setting is discarded.
00635   * @note   Availability of parameters of trigger sources from timer
00636   *         depends on timers availability on the selected device.
00637   * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
00638   *         CR       TSEL2          LL_DAC_SetTriggerSource
00639   * @param  DACx DAC instance
00640   * @param  DAC_Channel This parameter can be one of the following values:
00641   *         @arg @ref LL_DAC_CHANNEL_1
00642   *         @arg @ref LL_DAC_CHANNEL_2
00643   * @param  TriggerSource This parameter can be one of the following values:
00644   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00645   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
00646   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00647   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
00648   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00649   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00650   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
00651   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
00652   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
00653   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00654   * @retval None
00655   */
00656 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
00657 {
00658   MODIFY_REG(DACx->CR,
00659              DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00660              TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00661 }
00662
00663 /**
00664   * @brief  Get the conversion trigger source for the selected DAC channel.
00665   * @note   For conversion trigger source to be effective, DAC trigger
00666   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00667   * @note   Availability of parameters of trigger sources from timer
00668   *         depends on timers availability on the selected device.
00669   * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
00670   *         CR       TSEL2          LL_DAC_GetTriggerSource
00671   * @param  DACx DAC instance
00672   * @param  DAC_Channel This parameter can be one of the following values:
00673   *         @arg @ref LL_DAC_CHANNEL_1
00674   *         @arg @ref LL_DAC_CHANNEL_2
00675   * @retval Returned value can be one of the following values:
00676   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00677   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
00678   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00679   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
00680   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00681   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00682   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
00683   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
00684   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
00685   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00686   */
00687 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00688 {
00689   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00690                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00691                    );
00692 }
00693
00694 /**
00695   * @brief  Set the waveform automatic generation mode
00696   *         for the selected DAC channel.
00697   * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
00698   *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
00699   * @param  DACx DAC instance
00700   * @param  DAC_Channel This parameter can be one of the following values:
00701   *         @arg @ref LL_DAC_CHANNEL_1
00702   *         @arg @ref LL_DAC_CHANNEL_2
00703   * @param  WaveAutoGeneration This parameter can be one of the following values:
00704   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00705   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00706   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00707   * @retval None
00708   */
00709 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
00710 {
00711   MODIFY_REG(DACx->CR,
00712              DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00713              WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00714 }
00715
00716 /**
00717   * @brief  Get the waveform automatic generation mode
00718   *         for the selected DAC channel.
00719   * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
00720   *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
00721   * @param  DACx DAC instance
00722   * @param  DAC_Channel This parameter can be one of the following values:
00723   *         @arg @ref LL_DAC_CHANNEL_1
00724   *         @arg @ref LL_DAC_CHANNEL_2
00725   * @retval Returned value can be one of the following values:
00726   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00727   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00728   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00729   */
00730 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00731 {
00732   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00733                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00734                    );
00735 }
00736
00737 /**
00738   * @brief  Set the noise waveform generation for the selected DAC channel:
00739   *         Noise mode and parameters LFSR (linear feedback shift register).
00740   * @note   For wave generation to be effective, DAC channel
00741   *         wave generation mode must be enabled using
00742   *         function @ref LL_DAC_SetWaveAutoGeneration().
00743   * @note   This setting can be set when the selected DAC channel is disabled
00744   *         (otherwise, the setting operation is ignored).
00745   * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
00746   *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
00747   * @param  DACx DAC instance
00748   * @param  DAC_Channel This parameter can be one of the following values:
00749   *         @arg @ref LL_DAC_CHANNEL_1
00750   *         @arg @ref LL_DAC_CHANNEL_2
00751   * @param  NoiseLFSRMask This parameter can be one of the following values:
00752   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00753   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00754   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00755   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00756   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00757   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00758   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00759   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00760   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00761   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00762   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00763   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00764   * @retval None
00765   */
00766 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
00767 {
00768   MODIFY_REG(DACx->CR,
00769              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00770              NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00771 }
00772
00773 /**
00774   * @brief  Get the noise waveform generation for the selected DAC channel:
00775   *         Noise mode and parameters LFSR (linear feedback shift register).
00776   * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
00777   *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
00778   * @param  DACx DAC instance
00779   * @param  DAC_Channel This parameter can be one of the following values:
00780   *         @arg @ref LL_DAC_CHANNEL_1
00781   *         @arg @ref LL_DAC_CHANNEL_2
00782   * @retval Returned value can be one of the following values:
00783   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00784   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00785   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00786   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00787   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00788   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00789   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00790   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00791   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00792   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00793   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00794   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00795   */
00796 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00797 {
00798   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00799                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00800                    );
00801 }
00802
00803 /**
00804   * @brief  Set the triangle waveform generation for the selected DAC channel:
00805   *         triangle mode and amplitude.
00806   * @note   For wave generation to be effective, DAC channel
00807   *         wave generation mode must be enabled using
00808   *         function @ref LL_DAC_SetWaveAutoGeneration().
00809   * @note   This setting can be set when the selected DAC channel is disabled
00810   *         (otherwise, the setting operation is ignored).
00811   * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
00812   *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
00813   * @param  DACx DAC instance
00814   * @param  DAC_Channel This parameter can be one of the following values:
00815   *         @arg @ref LL_DAC_CHANNEL_1
00816   *         @arg @ref LL_DAC_CHANNEL_2
00817   * @param  TriangleAmplitude This parameter can be one of the following values:
00818   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00819   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00820   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00821   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00822   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00823   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00824   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00825   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00826   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00827   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00828   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00829   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00830   * @retval None
00831   */
00832 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
00833                                                      uint32_t TriangleAmplitude)
00834 {
00835   MODIFY_REG(DACx->CR,
00836              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00837              TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00838 }
00839
00840 /**
00841   * @brief  Get the triangle waveform generation for the selected DAC channel:
00842   *         triangle mode and amplitude.
00843   * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
00844   *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
00845   * @param  DACx DAC instance
00846   * @param  DAC_Channel This parameter can be one of the following values:
00847   *         @arg @ref LL_DAC_CHANNEL_1
00848   *         @arg @ref LL_DAC_CHANNEL_2
00849   * @retval Returned value can be one of the following values:
00850   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00851   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00852   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00853   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00854   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00855   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00856   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00857   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00858   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00859   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00860   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00861   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00862   */
00863 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00864 {
00865   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00866                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00867                    );
00868 }
00869
00870 /**
00871   * @brief  Set the output for the selected DAC channel.
00872   * @note   This function set several features:
00873   *         - mode normal or sample-and-hold
00874   *         - buffer
00875   *         - connection to GPIO or internal path.
00876   *         These features can also be set individually using
00877   *         dedicated functions:
00878   *         - @ref LL_DAC_SetOutputBuffer()
00879   *         - @ref LL_DAC_SetOutputMode()
00880   *         - @ref LL_DAC_SetOutputConnection()
00881   * @note   On this STM32 series, output connection depends on output mode
00882   *         (normal or sample and hold) and output buffer state.
00883   *         - if output connection is set to internal path and output buffer
00884   *           is enabled (whatever output mode):
00885   *           output connection is also connected to GPIO pin
00886   *           (both connections to GPIO pin and internal path).
00887   *         - if output connection is set to GPIO pin, output buffer
00888   *           is disabled, output mode set to sample and hold:
00889   *           output connection is also connected to internal path
00890   *           (both connections to GPIO pin and internal path).
00891   * @note   Mode sample-and-hold requires an external capacitor
00892   *         to be connected between DAC channel output and ground.
00893   *         Capacitor value depends on load on DAC channel output and
00894   *         sample-and-hold timings configured.
00895   *         As indication, capacitor typical value is 100nF
00896   *         (refer to device datasheet, parameter "CSH").
00897   * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n
00898   *         CR       MODE2          LL_DAC_ConfigOutput
00899   * @param  DACx DAC instance
00900   * @param  DAC_Channel This parameter can be one of the following values:
00901   *         @arg @ref LL_DAC_CHANNEL_1
00902   *         @arg @ref LL_DAC_CHANNEL_2
00903   * @param  OutputMode This parameter can be one of the following values:
00904   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00905   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00906   * @param  OutputBuffer This parameter can be one of the following values:
00907   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00908   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00909   * @param  OutputConnection This parameter can be one of the following values:
00910   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
00911   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
00912   * @retval None
00913   */
00914 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
00915                                          uint32_t OutputBuffer, uint32_t OutputConnection)
00916 {
00917   MODIFY_REG(DACx->MCR,
00918              (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00919              (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00920 }
00921
00922 /**
00923   * @brief  Set the output mode normal or sample-and-hold
00924   *         for the selected DAC channel.
00925   * @note   Mode sample-and-hold requires an external capacitor
00926   *         to be connected between DAC channel output and ground.
00927   *         Capacitor value depends on load on DAC channel output and
00928   *         sample-and-hold timings configured.
00929   *         As indication, capacitor typical value is 100nF
00930   *         (refer to device datasheet, parameter "CSH").
00931   * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n
00932   *         CR       MODE2          LL_DAC_SetOutputMode
00933   * @param  DACx DAC instance
00934   * @param  DAC_Channel This parameter can be one of the following values:
00935   *         @arg @ref LL_DAC_CHANNEL_1
00936   *         @arg @ref LL_DAC_CHANNEL_2
00937   * @param  OutputMode This parameter can be one of the following values:
00938   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00939   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00940   * @retval None
00941   */
00942 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
00943 {
00944   MODIFY_REG(DACx->MCR,
00945              (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00946              OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00947 }
00948
00949 /**
00950   * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.
00951   * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n
00952   *         CR       MODE2          LL_DAC_GetOutputMode
00953   * @param  DACx DAC instance
00954   * @param  DAC_Channel This parameter can be one of the following values:
00955   *         @arg @ref LL_DAC_CHANNEL_1
00956   *         @arg @ref LL_DAC_CHANNEL_2
00957   * @retval Returned value can be one of the following values:
00958   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00959   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00960   */
00961 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00962 {
00963   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00964                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00965                    );
00966 }
00967
00968 /**
00969   * @brief  Set the output buffer for the selected DAC channel.
00970   * @note   On this STM32 series, when buffer is enabled, its offset can be
00971   *         trimmed: factory calibration default values can be
00972   *         replaced by user trimming values, using function
00973   *         @ref LL_DAC_SetTrimmingValue().
00974   * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n
00975   *         CR       MODE2          LL_DAC_SetOutputBuffer
00976   * @param  DACx DAC instance
00977   * @param  DAC_Channel This parameter can be one of the following values:
00978   *         @arg @ref LL_DAC_CHANNEL_1
00979   *         @arg @ref LL_DAC_CHANNEL_2
00980   * @param  OutputBuffer This parameter can be one of the following values:
00981   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00982   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00983   * @retval None
00984   */
00985 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
00986 {
00987   MODIFY_REG(DACx->MCR,
00988              (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00989              OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00990 }
00991
00992 /**
00993   * @brief  Get the output buffer state for the selected DAC channel.
00994   * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n
00995   *         CR       MODE2          LL_DAC_GetOutputBuffer
00996   * @param  DACx DAC instance
00997   * @param  DAC_Channel This parameter can be one of the following values:
00998   *         @arg @ref LL_DAC_CHANNEL_1
00999   *         @arg @ref LL_DAC_CHANNEL_2
01000   * @retval Returned value can be one of the following values:
01001   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
01002   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
01003   */
01004 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01005 {
01006   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01007                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01008                    );
01009 }
01010
01011 /**
01012   * @brief  Set the output connection for the selected DAC channel.
01013   * @note   On this STM32 series, output connection depends on output mode (normal or
01014   *         sample and hold) and output buffer state.
01015   *         - if output connection is set to internal path and output buffer
01016   *           is enabled (whatever output mode):
01017   *           output connection is also connected to GPIO pin
01018   *           (both connections to GPIO pin and internal path).
01019   *         - if output connection is set to GPIO pin, output buffer
01020   *           is disabled, output mode set to sample and hold:
01021   *           output connection is also connected to internal path
01022   *           (both connections to GPIO pin and internal path).
01023   * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n
01024   *         CR       MODE2          LL_DAC_SetOutputConnection
01025   * @param  DACx DAC instance
01026   * @param  DAC_Channel This parameter can be one of the following values:
01027   *         @arg @ref LL_DAC_CHANNEL_1
01028   *         @arg @ref LL_DAC_CHANNEL_2
01029   * @param  OutputConnection This parameter can be one of the following values:
01030   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01031   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01032   * @retval None
01033   */
01034 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
01035 {
01036   MODIFY_REG(DACx->MCR,
01037              (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01038              OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01039 }
01040
01041 /**
01042   * @brief  Get the output connection for the selected DAC channel.
01043   * @note   On this STM32 series, output connection depends on output mode (normal or
01044   *         sample and hold) and output buffer state.
01045   *         - if output connection is set to internal path and output buffer
01046   *           is enabled (whatever output mode):
01047   *           output connection is also connected to GPIO pin
01048   *           (both connections to GPIO pin and internal path).
01049   *         - if output connection is set to GPIO pin, output buffer
01050   *           is disabled, output mode set to sample and hold:
01051   *           output connection is also connected to internal path
01052   *           (both connections to GPIO pin and internal path).
01053   * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n
01054   *         CR       MODE2          LL_DAC_GetOutputConnection
01055   * @param  DACx DAC instance
01056   * @param  DAC_Channel This parameter can be one of the following values:
01057   *         @arg @ref LL_DAC_CHANNEL_1
01058   *         @arg @ref LL_DAC_CHANNEL_2
01059   * @retval Returned value can be one of the following values:
01060   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01061   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01062   */
01063 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01064 {
01065   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01066                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01067                    );
01068 }
01069
01070 /**
01071   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01072   *         sample time
01073   * @note   Sample time must be set when DAC channel is disabled
01074   *         or during DAC operation when DAC channel flag BWSTx is reset,
01075   *         otherwise the setting is ignored.
01076   *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
01077   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n
01078   *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime
01079   * @param  DACx DAC instance
01080   * @param  DAC_Channel This parameter can be one of the following values:
01081   *         @arg @ref LL_DAC_CHANNEL_1
01082   *         @arg @ref LL_DAC_CHANNEL_2
01083   * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
01084   * @retval None
01085   */
01086 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
01087 {
01088   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
01089                                              & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
01090
01091   MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
01092 }
01093
01094 /**
01095   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01096   *         sample time
01097   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n
01098   *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime
01099   * @param  DACx DAC instance
01100   * @param  DAC_Channel This parameter can be one of the following values:
01101   *         @arg @ref LL_DAC_CHANNEL_1
01102   *         @arg @ref LL_DAC_CHANNEL_2
01103   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01104   */
01105 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01106 {
01107   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
01108                                                    & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
01109
01110   return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
01111 }
01112
01113 /**
01114   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01115   *         hold time
01116   * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n
01117   *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime
01118   * @param  DACx DAC instance
01119   * @param  DAC_Channel This parameter can be one of the following values:
01120   *         @arg @ref LL_DAC_CHANNEL_1
01121   *         @arg @ref LL_DAC_CHANNEL_2
01122   * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
01123   * @retval None
01124   */
01125 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
01126 {
01127   MODIFY_REG(DACx->SHHR,
01128              DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01129              HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01130 }
01131
01132 /**
01133   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01134   *         hold time
01135   * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n
01136   *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime
01137   * @param  DACx DAC instance
01138   * @param  DAC_Channel This parameter can be one of the following values:
01139   *         @arg @ref LL_DAC_CHANNEL_1
01140   *         @arg @ref LL_DAC_CHANNEL_2
01141   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01142   */
01143 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01144 {
01145   return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01146                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01147                    );
01148 }
01149
01150 /**
01151   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01152   *         refresh time
01153   * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n
01154   *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime
01155   * @param  DACx DAC instance
01156   * @param  DAC_Channel This parameter can be one of the following values:
01157   *         @arg @ref LL_DAC_CHANNEL_1
01158   *         @arg @ref LL_DAC_CHANNEL_2
01159   * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
01160   * @retval None
01161   */
01162 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
01163 {
01164   MODIFY_REG(DACx->SHRR,
01165              DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01166              RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01167 }
01168
01169 /**
01170   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01171   *         refresh time
01172   * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n
01173   *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime
01174   * @param  DACx DAC instance
01175   * @param  DAC_Channel This parameter can be one of the following values:
01176   *         @arg @ref LL_DAC_CHANNEL_1
01177   *         @arg @ref LL_DAC_CHANNEL_2
01178   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01179   */
01180 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01181 {
01182   return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01183                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01184                    );
01185 }
01186
01187 /**
01188   * @}
01189   */
01190
01191 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
01192   * @{
01193   */
01194
01195 /**
01196   * @brief  Enable DAC DMA transfer request of the selected channel.
01197   * @note   To configure DMA source address (peripheral address),
01198   *         use function @ref LL_DAC_DMA_GetRegAddr().
01199   * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
01200   *         CR       DMAEN2         LL_DAC_EnableDMAReq
01201   * @param  DACx DAC instance
01202   * @param  DAC_Channel This parameter can be one of the following values:
01203   *         @arg @ref LL_DAC_CHANNEL_1
01204   *         @arg @ref LL_DAC_CHANNEL_2
01205   * @retval None
01206   */
01207 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01208 {
01209   SET_BIT(DACx->CR,
01210           DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01211 }
01212
01213 /**
01214   * @brief  Disable DAC DMA transfer request of the selected channel.
01215   * @note   To configure DMA source address (peripheral address),
01216   *         use function @ref LL_DAC_DMA_GetRegAddr().
01217   * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
01218   *         CR       DMAEN2         LL_DAC_DisableDMAReq
01219   * @param  DACx DAC instance
01220   * @param  DAC_Channel This parameter can be one of the following values:
01221   *         @arg @ref LL_DAC_CHANNEL_1
01222   *         @arg @ref LL_DAC_CHANNEL_2
01223   * @retval None
01224   */
01225 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01226 {
01227   CLEAR_BIT(DACx->CR,
01228             DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01229 }
01230
01231 /**
01232   * @brief  Get DAC DMA transfer request state of the selected channel.
01233   *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
01234   * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
01235   *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
01236   * @param  DACx DAC instance
01237   * @param  DAC_Channel This parameter can be one of the following values:
01238   *         @arg @ref LL_DAC_CHANNEL_1
01239   *         @arg @ref LL_DAC_CHANNEL_2
01240   * @retval State of bit (1 or 0).
01241   */
01242 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01243 {
01244   return ((READ_BIT(DACx->CR,
01245                     DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01246            == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
01247 }
01248
01249 /**
01250   * @brief  Function to help to configure DMA transfer to DAC: retrieve the
01251   *         DAC register address from DAC instance and a list of DAC registers
01252   *         intended to be used (most commonly) with DMA transfer.
01253   * @note   These DAC registers are data holding registers:
01254   *         when DAC conversion is requested, DAC generates a DMA transfer
01255   *         request to have data available in DAC data holding registers.
01256   * @note   This macro is intended to be used with LL DMA driver, refer to
01257   *         function "LL_DMA_ConfigAddresses()".
01258   *         Example:
01259   *           LL_DMA_ConfigAddresses(DMA1,
01260   *                                  LL_DMA_CHANNEL_1,
01261   *                                  (uint32_t)&< array or variable >,
01262   *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
01263   *                                  LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
01264   *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
01265   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01266   *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01267   *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01268   *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01269   *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01270   *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
01271   * @param  DACx DAC instance
01272   * @param  DAC_Channel This parameter can be one of the following values:
01273   *         @arg @ref LL_DAC_CHANNEL_1
01274   *         @arg @ref LL_DAC_CHANNEL_2
01275   * @param  Register This parameter can be one of the following values:
01276   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
01277   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
01278   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
01279   * @retval DAC register address
01280   */
01281 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
01282 {
01283   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
01284   /* DAC channel selected.                                                    */
01285   return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
01286                                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
01287 }
01288 /**
01289   * @}
01290   */
01291
01292 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
01293   * @{
01294   */
01295
01296 /**
01297   * @brief  Enable DAC selected channel.
01298   * @rmtoll CR       EN1            LL_DAC_Enable\n
01299   *         CR       EN2            LL_DAC_Enable
01300   * @note   After enable from off state, DAC channel requires a delay
01301   *         for output voltage to reach accuracy +/- 1 LSB.
01302   *         Refer to device datasheet, parameter "tWAKEUP".
01303   * @param  DACx DAC instance
01304   * @param  DAC_Channel This parameter can be one of the following values:
01305   *         @arg @ref LL_DAC_CHANNEL_1
01306   *         @arg @ref LL_DAC_CHANNEL_2
01307   * @retval None
01308   */
01309 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01310 {
01311   SET_BIT(DACx->CR,
01312           DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01313 }
01314
01315 /**
01316   * @brief  Disable DAC selected channel.
01317   * @rmtoll CR       EN1            LL_DAC_Disable\n
01318   *         CR       EN2            LL_DAC_Disable
01319   * @param  DACx DAC instance
01320   * @param  DAC_Channel This parameter can be one of the following values:
01321   *         @arg @ref LL_DAC_CHANNEL_1
01322   *         @arg @ref LL_DAC_CHANNEL_2
01323   * @retval None
01324   */
01325 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01326 {
01327   CLEAR_BIT(DACx->CR,
01328             DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01329 }
01330
01331 /**
01332   * @brief  Get DAC enable state of the selected channel.
01333   *         (0: DAC channel is disabled, 1: DAC channel is enabled)
01334   * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
01335   *         CR       EN2            LL_DAC_IsEnabled
01336   * @param  DACx DAC instance
01337   * @param  DAC_Channel This parameter can be one of the following values:
01338   *         @arg @ref LL_DAC_CHANNEL_1
01339   *         @arg @ref LL_DAC_CHANNEL_2
01340   * @retval State of bit (1 or 0).
01341   */
01342 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01343 {
01344   return ((READ_BIT(DACx->CR,
01345                     DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01346            == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
01347 }
01348
01349 /**
01350   * @brief  Enable DAC trigger of the selected channel.
01351   * @note   - If DAC trigger is disabled, DAC conversion is performed
01352   *           automatically once the data holding register is updated,
01353   *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01354   *           @ref LL_DAC_ConvertData12RightAligned(), ...
01355   *         - If DAC trigger is enabled, DAC conversion is performed
01356   *           only when a hardware of software trigger event is occurring.
01357   *           Select trigger source using
01358   *           function @ref LL_DAC_SetTriggerSource().
01359   * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
01360   *         CR       TEN2           LL_DAC_EnableTrigger
01361   * @param  DACx DAC instance
01362   * @param  DAC_Channel This parameter can be one of the following values:
01363   *         @arg @ref LL_DAC_CHANNEL_1
01364   *         @arg @ref LL_DAC_CHANNEL_2
01365   * @retval None
01366   */
01367 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01368 {
01369   SET_BIT(DACx->CR,
01370           DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01371 }
01372
01373 /**
01374   * @brief  Disable DAC trigger of the selected channel.
01375   * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
01376   *         CR       TEN2           LL_DAC_DisableTrigger
01377   * @param  DACx DAC instance
01378   * @param  DAC_Channel This parameter can be one of the following values:
01379   *         @arg @ref LL_DAC_CHANNEL_1
01380   *         @arg @ref LL_DAC_CHANNEL_2
01381   * @retval None
01382   */
01383 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01384 {
01385   CLEAR_BIT(DACx->CR,
01386             DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01387 }
01388
01389 /**
01390   * @brief  Get DAC trigger state of the selected channel.
01391   *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
01392   * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
01393   *         CR       TEN2           LL_DAC_IsTriggerEnabled
01394   * @param  DACx DAC instance
01395   * @param  DAC_Channel This parameter can be one of the following values:
01396   *         @arg @ref LL_DAC_CHANNEL_1
01397   *         @arg @ref LL_DAC_CHANNEL_2
01398   * @retval State of bit (1 or 0).
01399   */
01400 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01401 {
01402   return ((READ_BIT(DACx->CR,
01403                     DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01404            == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
01405 }
01406
01407 /**
01408   * @brief  Trig DAC conversion by software for the selected DAC channel.
01409   * @note   Preliminarily, DAC trigger must be set to software trigger
01410   *         using function
01411   *           @ref LL_DAC_Init()
01412   *           @ref LL_DAC_SetTriggerSource()
01413   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
01414   *         and DAC trigger must be enabled using
01415   *         function @ref LL_DAC_EnableTrigger().
01416   * @note   For devices featuring DAC with 2 channels: this function
01417   *         can perform a SW start of both DAC channels simultaneously.
01418   *         Two channels can be selected as parameter.
01419   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
01420   * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
01421   *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
01422   * @param  DACx DAC instance
01423   * @param  DAC_Channel  This parameter can a combination of the following values:
01424   *         @arg @ref LL_DAC_CHANNEL_1
01425   *         @arg @ref LL_DAC_CHANNEL_2
01426   * @retval None
01427   */
01428 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01429 {
01430   SET_BIT(DACx->SWTRIGR,
01431           (DAC_Channel & DAC_SWTR_CHX_MASK));
01432 }
01433
01434 /**
01435   * @brief  Set the data to be loaded in the data holding register
01436   *         in format 12 bits left alignment (LSB aligned on bit 0),
01437   *         for the selected DAC channel.
01438   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
01439   *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
01440   * @param  DACx DAC instance
01441   * @param  DAC_Channel This parameter can be one of the following values:
01442   *         @arg @ref LL_DAC_CHANNEL_1
01443   *         @arg @ref LL_DAC_CHANNEL_2
01444   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01445   * @retval None
01446   */
01447 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01448 {
01449   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
01450                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
01451
01452   MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
01453 }
01454
01455 /**
01456   * @brief  Set the data to be loaded in the data holding register
01457   *         in format 12 bits left alignment (MSB aligned on bit 15),
01458   *         for the selected DAC channel.
01459   * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
01460   *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
01461   * @param  DACx DAC instance
01462   * @param  DAC_Channel This parameter can be one of the following values:
01463   *         @arg @ref LL_DAC_CHANNEL_1
01464   *         @arg @ref LL_DAC_CHANNEL_2
01465   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01466   * @retval None
01467   */
01468 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01469 {
01470   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
01471                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
01472
01473   MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
01474 }
01475
01476 /**
01477   * @brief  Set the data to be loaded in the data holding register
01478   *         in format 8 bits left alignment (LSB aligned on bit 0),
01479   *         for the selected DAC channel.
01480   * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
01481   *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
01482   * @param  DACx DAC instance
01483   * @param  DAC_Channel This parameter can be one of the following values:
01484   *         @arg @ref LL_DAC_CHANNEL_1
01485   *         @arg @ref LL_DAC_CHANNEL_2
01486   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
01487   * @retval None
01488   */
01489 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01490 {
01491   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
01492                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
01493
01494   MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
01495 }
01496
01497
01498 /**
01499   * @brief  Set the data to be loaded in the data holding register
01500   *         in format 12 bits left alignment (LSB aligned on bit 0),
01501   *         for both DAC channels.
01502   * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
01503   *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
01504   * @param  DACx DAC instance
01505   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01506   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01507   * @retval None
01508   */
01509 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
01510                                                           uint32_t DataChannel2)
01511 {
01512   MODIFY_REG(DACx->DHR12RD,
01513              (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
01514              ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01515 }
01516
01517 /**
01518   * @brief  Set the data to be loaded in the data holding register
01519   *         in format 12 bits left alignment (MSB aligned on bit 15),
01520   *         for both DAC channels.
01521   * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
01522   *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
01523   * @param  DACx DAC instance
01524   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01525   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01526   * @retval None
01527   */
01528 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
01529                                                          uint32_t DataChannel2)
01530 {
01531   /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
01532   /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
01533   /*       the 4 LSB must be taken into account for the shift value.          */
01534   MODIFY_REG(DACx->DHR12LD,
01535              (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
01536              ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
01537 }
01538
01539 /**
01540   * @brief  Set the data to be loaded in the data holding register
01541   *         in format 8 bits left alignment (LSB aligned on bit 0),
01542   *         for both DAC channels.
01543   * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
01544   *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
01545   * @param  DACx DAC instance
01546   * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
01547   * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
01548   * @retval None
01549   */
01550 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
01551                                                          uint32_t DataChannel2)
01552 {
01553   MODIFY_REG(DACx->DHR8RD,
01554              (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
01555              ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01556 }
01557
01558
01559 /**
01560   * @brief  Retrieve output data currently generated for the selected DAC channel.
01561   * @note   Whatever alignment and resolution settings
01562   *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01563   *         @ref LL_DAC_ConvertData12RightAligned(), ...),
01564   *         output data format is 12 bits right aligned (LSB aligned on bit 0).
01565   * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
01566   *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
01567   * @param  DACx DAC instance
01568   * @param  DAC_Channel This parameter can be one of the following values:
01569   *         @arg @ref LL_DAC_CHANNEL_1
01570   *         @arg @ref LL_DAC_CHANNEL_2
01571   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01572   */
01573 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01574 {
01575   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
01576                                                    & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
01577
01578   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
01579 }
01580
01581 /**
01582   * @}
01583   */
01584
01585 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
01586   * @{
01587   */
01588
01589 /**
01590   * @brief  Get DAC calibration offset flag for DAC channel 1
01591   * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
01592   * @param  DACx DAC instance
01593   * @retval State of bit (1 or 0).
01594   */
01595 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
01596 {
01597   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
01598 }
01599
01600
01601 /**
01602   * @brief  Get DAC calibration offset flag for DAC channel 2
01603   * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2
01604   * @param  DACx DAC instance
01605   * @retval State of bit (1 or 0).
01606   */
01607 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
01608 {
01609   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
01610 }
01611
01612
01613 /**
01614   * @brief  Get DAC busy writing sample time flag for DAC channel 1
01615   * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1
01616   * @param  DACx DAC instance
01617   * @retval State of bit (1 or 0).
01618   */
01619 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
01620 {
01621   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
01622 }
01623
01624 /**
01625   * @brief  Get DAC busy writing sample time flag for DAC channel 2
01626   * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
01627   * @param  DACx DAC instance
01628   * @retval State of bit (1 or 0).
01629   */
01630 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
01631 {
01632   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
01633 }
01634
01635
01636 /**
01637   * @brief  Get DAC underrun flag for DAC channel 1
01638   * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
01639   * @param  DACx DAC instance
01640   * @retval State of bit (1 or 0).
01641   */
01642 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
01643 {
01644   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
01645 }
01646
01647
01648 /**
01649   * @brief  Get DAC underrun flag for DAC channel 2
01650   * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
01651   * @param  DACx DAC instance
01652   * @retval State of bit (1 or 0).
01653   */
01654 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
01655 {
01656   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
01657 }
01658
01659
01660 /**
01661   * @brief  Clear DAC underrun flag for DAC channel 1
01662   * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
01663   * @param  DACx DAC instance
01664   * @retval None
01665   */
01666 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
01667 {
01668   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
01669 }
01670
01671
01672 /**
01673   * @brief  Clear DAC underrun flag for DAC channel 2
01674   * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
01675   * @param  DACx DAC instance
01676   * @retval None
01677   */
01678 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
01679 {
01680   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
01681 }
01682
01683
01684 /**
01685   * @}
01686   */
01687
01688 /** @defgroup DAC_LL_EF_IT_Management IT management
01689   * @{
01690   */
01691
01692 /**
01693   * @brief  Enable DMA underrun interrupt for DAC channel 1
01694   * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
01695   * @param  DACx DAC instance
01696   * @retval None
01697   */
01698 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
01699 {
01700   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01701 }
01702
01703
01704 /**
01705   * @brief  Enable DMA underrun interrupt for DAC channel 2
01706   * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
01707   * @param  DACx DAC instance
01708   * @retval None
01709   */
01710 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
01711 {
01712   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01713 }
01714
01715
01716 /**
01717   * @brief  Disable DMA underrun interrupt for DAC channel 1
01718   * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
01719   * @param  DACx DAC instance
01720   * @retval None
01721   */
01722 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
01723 {
01724   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01725 }
01726
01727
01728 /**
01729   * @brief  Disable DMA underrun interrupt for DAC channel 2
01730   * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
01731   * @param  DACx DAC instance
01732   * @retval None
01733   */
01734 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
01735 {
01736   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01737 }
01738
01739
01740 /**
01741   * @brief  Get DMA underrun interrupt for DAC channel 1
01742   * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
01743   * @param  DACx DAC instance
01744   * @retval State of bit (1 or 0).
01745   */
01746 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
01747 {
01748   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
01749 }
01750
01751
01752 /**
01753   * @brief  Get DMA underrun interrupt for DAC channel 2
01754   * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
01755   * @param  DACx DAC instance
01756   * @retval State of bit (1 or 0).
01757   */
01758 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
01759 {
01760   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
01761 }
01762
01763
01764 /**
01765   * @}
01766   */
01767
01768 #if defined(USE_FULL_LL_DRIVER)
01769 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
01770   * @{
01771   */
01772
01773 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
01774 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
01775 void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
01776
01777 /**
01778   * @}
01779   */
01780 #endif /* USE_FULL_LL_DRIVER */
01781
01782 /**
01783   * @}
01784   */
01785
01786 /**
01787   * @}
01788   */
01789
01790 #endif /* DAC1 */
01791
01792 /**
01793   * @}
01794   */
01795
01796 #ifdef __cplusplus
01797 }
01798 #endif
01799
01800 #endif /* STM32G0xx_LL_DAC_H */
01801
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dma.c Source File

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stm32g0xx_ll_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_dma.h"
00022 #include "stm32g0xx_ll_bus.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G0xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (DMA1) || defined (DMA2)
00034
00035 /** @defgroup DMA_LL DMA
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /** @addtogroup DMA_LL_Private_Macros
00044   * @{
00045   */
00046 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
00047                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
00048                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
00049
00050 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
00051                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
00052
00053 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
00054                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
00055
00056 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
00057                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
00058
00059 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
00060                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
00061                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
00062
00063 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
00064                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
00065                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
00066
00067 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
00068
00069 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= LL_DMAMUX_MAX_REQ)
00070
00071 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
00072                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
00073                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
00074                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
00075
00076 #if defined(DMA2)
00077 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00078                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00079                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00080                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00081                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00082                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00083                                                               ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00084                                                               ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
00085                                                             (((INSTANCE) == DMA2) && \
00086                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00087                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00088                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00089                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00090                                                               ((CHANNEL) == LL_DMA_CHANNEL_5))))
00091 #else /* DMA1 */
00092 #if   defined(DMA1_Channel7)
00093 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00094                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00095                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00096                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00097                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00098                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00099                                                               ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00100                                                               ((CHANNEL) == LL_DMA_CHANNEL_7))))
00101 #else
00102 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00103                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00104                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00105                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00106                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00107                                                               ((CHANNEL) == LL_DMA_CHANNEL_5))))
00108 #endif /* DMA1_Channel8 */
00109 #endif /* DMA2 */
00110 /**
00111   * @}
00112   */
00113
00114 /* Private function prototypes -----------------------------------------------*/
00115
00116 /* Exported functions --------------------------------------------------------*/
00117 /** @addtogroup DMA_LL_Exported_Functions
00118   * @{
00119   */
00120
00121 /** @addtogroup DMA_LL_EF_Init
00122   * @{
00123   */
00124
00125 /**
00126   * @brief  De-initialize the DMA registers to their default reset values.
00127   * @param  DMAx DMAx Instance
00128   * @param  Channel This parameter can be one of the following values:
00129   *         @arg @ref LL_DMA_CHANNEL_1
00130   *         @arg @ref LL_DMA_CHANNEL_2
00131   *         @arg @ref LL_DMA_CHANNEL_3
00132   *         @arg @ref LL_DMA_CHANNEL_4
00133   *         @arg @ref LL_DMA_CHANNEL_5
00134   *         @arg @ref LL_DMA_CHANNEL_6
00135   *         @arg @ref LL_DMA_CHANNEL_7
00136   *         @arg @ref LL_DMA_CHANNEL_ALL
00137   * @retval An ErrorStatus enumeration value:
00138   *          - SUCCESS: DMA registers are de-initialized
00139   *          - ERROR: DMA registers are not de-initialized
00140   */
00141 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
00142 {
00143   ErrorStatus status = SUCCESS;
00144
00145   /* Check the DMA Instance DMAx and Channel parameters*/
00146   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
00147
00148   if (Channel == LL_DMA_CHANNEL_ALL)
00149   {
00150     if (DMAx == DMA1)
00151     {
00152       /* Force reset of DMA clock */
00153       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
00154
00155       /* Release reset of DMA clock */
00156       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
00157     }
00158 #if defined(DMA2)
00159     else if (DMAx == DMA2)
00160     {
00161       /* Force reset of DMA clock */
00162       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
00163
00164       /* Release reset of DMA clock */
00165       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
00166     }
00167 #endif /* DMA2 */
00168     else
00169     {
00170       status = ERROR;
00171     }
00172   }
00173   else
00174   {
00175     DMA_Channel_TypeDef *tmp;
00176
00177     tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
00178
00179     /* Disable the selected DMAx_Channely */
00180     CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
00181
00182     /* Reset DMAx_Channely control register */
00183     WRITE_REG(tmp->CCR, 0U);
00184
00185     /* Reset DMAx_Channely remaining bytes register */
00186     WRITE_REG(tmp->CNDTR, 0U);
00187
00188     /* Reset DMAx_Channely peripheral address register */
00189     WRITE_REG(tmp->CPAR, 0U);
00190
00191     /* Reset DMAx_Channely memory address register */
00192     WRITE_REG(tmp->CMAR, 0U);
00193
00194     /* Reset Request register field for DMAx Channel */
00195     LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
00196
00197     if (Channel == LL_DMA_CHANNEL_1)
00198     {
00199       /* Reset interrupt pending bits for DMAx Channel1 */
00200       LL_DMA_ClearFlag_GI1(DMAx);
00201     }
00202     else if (Channel == LL_DMA_CHANNEL_2)
00203     {
00204       /* Reset interrupt pending bits for DMAx Channel2 */
00205       LL_DMA_ClearFlag_GI2(DMAx);
00206     }
00207     else if (Channel == LL_DMA_CHANNEL_3)
00208     {
00209       /* Reset interrupt pending bits for DMAx Channel3 */
00210       LL_DMA_ClearFlag_GI3(DMAx);
00211     }
00212     else if (Channel == LL_DMA_CHANNEL_4)
00213     {
00214       /* Reset interrupt pending bits for DMAx Channel4 */
00215       LL_DMA_ClearFlag_GI4(DMAx);
00216     }
00217     else if (Channel == LL_DMA_CHANNEL_5)
00218     {
00219       /* Reset interrupt pending bits for DMAx Channel5 */
00220       LL_DMA_ClearFlag_GI5(DMAx);
00221     }
00222 #if defined(DMA1_Channel6)
00223     else if (Channel == LL_DMA_CHANNEL_6)
00224     {
00225       /* Reset interrupt pending bits for DMAx Channel6 */
00226       LL_DMA_ClearFlag_GI6(DMAx);
00227     }
00228 #endif /* DMA1_Channel6 */
00229 #if defined(DMA1_Channel7)
00230     else if (Channel == LL_DMA_CHANNEL_7)
00231     {
00232       /* Reset interrupt pending bits for DMAx Channel7 */
00233       LL_DMA_ClearFlag_GI7(DMAx);
00234     }
00235 #endif /* DMA1_Channel7 */
00236     else
00237     {
00238       status = ERROR;
00239     }
00240   }
00241
00242   return status;
00243 }
00244
00245 /**
00246   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
00247   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
00248   *         @arg @ref __LL_DMA_GET_INSTANCE
00249   *         @arg @ref __LL_DMA_GET_CHANNEL
00250   * @param  DMAx DMAx Instance
00251   * @param  Channel This parameter can be one of the following values:
00252   *         @arg @ref LL_DMA_CHANNEL_1
00253   *         @arg @ref LL_DMA_CHANNEL_2
00254   *         @arg @ref LL_DMA_CHANNEL_3
00255   *         @arg @ref LL_DMA_CHANNEL_4
00256   *         @arg @ref LL_DMA_CHANNEL_5
00257   *         @arg @ref LL_DMA_CHANNEL_6
00258   *         @arg @ref LL_DMA_CHANNEL_7
00259   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
00260   * @retval An ErrorStatus enumeration value:
00261   *          - SUCCESS: DMA registers are initialized
00262   *          - ERROR: Not applicable
00263   */
00264 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
00265 {
00266   /* Check the DMA Instance DMAx and Channel parameters*/
00267   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
00268
00269   /* Check the DMA parameters from DMA_InitStruct */
00270   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
00271   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
00272   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
00273   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
00274   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
00275   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
00276   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
00277   assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
00278   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
00279
00280   /*---------------------------- DMAx CCR Configuration ------------------------
00281    * Configure DMAx_Channely: data transfer direction, data transfer mode,
00282    *                          peripheral and memory increment mode,
00283    *                          data size alignment and  priority level with parameters :
00284    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
00285    * - Mode:           DMA_CCR_CIRC bit
00286    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
00287    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
00288    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
00289    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
00290    * - Priority:               DMA_CCR_PL[1:0] bits
00291    */
00292   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
00293                         DMA_InitStruct->Mode                   | \
00294                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
00295                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
00296                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
00297                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
00298                         DMA_InitStruct->Priority);
00299
00300   /*-------------------------- DMAx CMAR Configuration -------------------------
00301    * Configure the memory or destination base address with parameter :
00302    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
00303    */
00304   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
00305
00306   /*-------------------------- DMAx CPAR Configuration -------------------------
00307    * Configure the peripheral or source base address with parameter :
00308    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
00309    */
00310   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
00311
00312   /*--------------------------- DMAx CNDTR Configuration -----------------------
00313    * Configure the peripheral base address with parameter :
00314    * - NbData: DMA_CNDTR_NDT[15:0] bits
00315    */
00316   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
00317
00318   /*--------------------------- DMAMUXx CCR Configuration ----------------------
00319    * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
00320    * - PeriphRequest: DMA_CxCR[7:0] bits
00321    */
00322   LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
00323
00324   return SUCCESS;
00325 }
00326
00327 /**
00328   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
00329   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
00330   * @retval None
00331   */
00332 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
00333 {
00334   /* Set DMA_InitStruct fields to default values */
00335   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
00336   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
00337   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
00338   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
00339   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
00340   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
00341   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
00342   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
00343   DMA_InitStruct->NbData                 = 0x00000000U;
00344   DMA_InitStruct->PeriphRequest          = LL_DMAMUX_REQ_MEM2MEM;
00345   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
00346 }
00347
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360 #endif /* DMA1 || DMA2 */
00361
00362 /**
00363   * @}
00364   */
00365
00366 #endif /* USE_FULL_LL_DRIVER */
00367
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dma.h Source File

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stm32g0xx_ll_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_DMA_H
00021 #define STM32G0xx_LL_DMA_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029 #include "stm32g0xx_ll_dmamux.h"
00030
00031 /** @addtogroup STM32G0xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (DMA1) || defined (DMA2)
00036
00037 /** @defgroup DMA_LL DMA
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
00044   * @{
00045   */
00046 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
00047 static const uint8_t CHANNEL_OFFSET_TAB[] =
00048 {
00049   (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
00050   (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
00051   (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
00052   (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
00053   (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
00054 #if defined(DMA1_Channel6_BASE)
00055   (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
00056 #endif /* DMA1_Channel6_BASE */
00057 #if defined(DMA1_Channel7_BASE)
00058   (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
00059 #endif /* DMA1_Channel7_BASE */
00060 };
00061 /**
00062   * @}
00063   */
00064
00065 /* Private constants ---------------------------------------------------------*/
00066 /* Private macros ------------------------------------------------------------*/
00067
00068 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
00069   * @{
00070   */
00071 /**
00072   * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel
00073   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00074   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00075   * @param  __DMA_INSTANCE__ DMAx
00076   * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
00077   */
00078 #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \
00079   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
00080 /**
00081   * @}
00082   */
00083 /* Exported types ------------------------------------------------------------*/
00084 #if defined(USE_FULL_LL_DRIVER)
00085 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
00086   * @{
00087   */
00088 typedef struct
00089 {
00090   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
00091                                         or as Source base address in case of memory to memory transfer direction.
00092
00093                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00094
00095   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
00096                                         or as Destination base address in case of memory to memory transfer direction.
00097
00098                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00099
00100   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
00101                                         from memory to memory or from peripheral to memory.
00102                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
00103
00104                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
00105
00106   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
00107                                         This parameter can be a value of @ref DMA_LL_EC_MODE
00108                                         @note: The circular buffer mode cannot be used if the memory to memory
00109                                                data transfer direction is configured on the selected Channel
00110
00111                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
00112
00113   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
00114                                         is incremented or not.
00115                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
00116
00117                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
00118
00119   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
00120                                         is incremented or not.
00121                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
00122
00123                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
00124
00125   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
00126                                         in case of memory to memory transfer direction.
00127                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
00128
00129                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
00130
00131   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
00132                                         in case of memory to memory transfer direction.
00133                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
00134
00135                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
00136
00137   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
00138                                         The data unit is equal to the source buffer configuration set in PeripheralSize
00139                                         or MemorySize parameters depending in the transfer direction.
00140                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
00141
00142                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
00143
00144   uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
00145                                         This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
00146
00147                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
00148
00149   uint32_t Priority;               /*!< Specifies the channel priority level.
00150                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
00151
00152                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
00153
00154 } LL_DMA_InitTypeDef;
00155 /**
00156   * @}
00157   */
00158 #endif /*USE_FULL_LL_DRIVER*/
00159
00160 /* Exported constants --------------------------------------------------------*/
00161 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
00162   * @{
00163   */
00164 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
00165   * @brief    Flags defines which can be used with LL_DMA_WriteReg function
00166   * @{
00167   */
00168 #define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
00169 #define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
00170 #define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
00171 #define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
00172 #define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
00173 #define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
00174 #define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
00175 #define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
00176 #define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
00177 #define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
00178 #define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
00179 #define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
00180 #define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
00181 #define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
00182 #define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
00183 #define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
00184 #define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
00185 #define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
00186 #define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
00187 #define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
00188 #if defined(DMA1_Channel6)
00189 #define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
00190 #define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
00191 #define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
00192 #define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
00193 #endif /* DMA1_Channel6 */
00194 #if defined(DMA1_Channel7)
00195 #define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
00196 #define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
00197 #define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
00198 #define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
00199 #endif /* DMA1_Channel7 */
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
00205   * @brief    Flags defines which can be used with LL_DMA_ReadReg function
00206   * @{
00207   */
00208 #define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
00209 #define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
00210 #define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
00211 #define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
00212 #define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
00213 #define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
00214 #define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
00215 #define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
00216 #define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
00217 #define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
00218 #define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
00219 #define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
00220 #define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
00221 #define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
00222 #define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
00223 #define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
00224 #define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
00225 #define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
00226 #define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
00227 #define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
00228 #if defined(DMA1_Channel6)
00229 #define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
00230 #define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
00231 #define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
00232 #define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
00233 #endif /* DMA1_Channel6 */
00234 #if defined(DMA1_Channel7)
00235 #define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
00236 #define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
00237 #define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
00238 #define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
00239 #endif /* DMA1_Channel7 */
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup DMA_LL_EC_IT IT Defines
00245   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
00246   * @{
00247   */
00248 #define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
00249 #define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
00250 #define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
00256   * @{
00257   */
00258 #define LL_DMA_CHANNEL_1                  0x00000000U /*!< DMA Channel 1 */
00259 #define LL_DMA_CHANNEL_2                  0x00000001U /*!< DMA Channel 2 */
00260 #define LL_DMA_CHANNEL_3                  0x00000002U /*!< DMA Channel 3 */
00261 #define LL_DMA_CHANNEL_4                  0x00000003U /*!< DMA Channel 4 */
00262 #define LL_DMA_CHANNEL_5                  0x00000004U /*!< DMA Channel 5 */
00263 #if defined(DMA1_Channel6)
00264 #define LL_DMA_CHANNEL_6                  0x00000005U /*!< DMA Channel 6 */
00265 #endif /* DMA1_Channel6 */
00266 #if defined(DMA1_Channel7)
00267 #define LL_DMA_CHANNEL_7                  0x00000006U /*!< DMA Channel 7 */
00268 #endif /* DMA1_Channel7 */
00269 #if defined(USE_FULL_LL_DRIVER)
00270 #define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
00271 #endif /*USE_FULL_LL_DRIVER*/
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
00277   * @{
00278   */
00279 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
00280 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
00281 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup DMA_LL_EC_MODE Transfer mode
00287   * @{
00288   */
00289 #define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
00290 #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
00296   * @{
00297   */
00298 #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
00299 #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
00305   * @{
00306   */
00307 #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
00308 #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
00314   * @{
00315   */
00316 #define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
00317 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
00318 #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
00324   * @{
00325   */
00326 #define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
00327 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
00328 #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
00334   * @{
00335   */
00336 #define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
00337 #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
00338 #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
00339 #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
00340 /**
00341   * @}
00342   */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /* Exported macro ------------------------------------------------------------*/
00349 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
00350   * @{
00351   */
00352
00353 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
00354   * @{
00355   */
00356 /**
00357   * @brief  Write a value in DMA register
00358   * @param  __INSTANCE__ DMA Instance
00359   * @param  __REG__ Register to be written
00360   * @param  __VALUE__ Value to be written in the register
00361   * @retval None
00362   */
00363 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00364
00365 /**
00366   * @brief  Read a value in DMA register
00367   * @param  __INSTANCE__ DMA Instance
00368   * @param  __REG__ Register to be read
00369   * @retval Register value
00370   */
00371 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
00377   * @{
00378   */
00379 /**
00380   * @brief  Convert DMAx_Channely into DMAx
00381   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00382   * @retval DMAx
00383   */
00384 #if defined(DMA2)
00385 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
00386   (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
00387 #else /* DMA1 */
00388 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
00389 #endif /* DMA2 */
00390
00391 /**
00392   * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
00393   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00394   * @retval LL_DMA_CHANNEL_y
00395   */
00396 #if defined(DMA2)
00397 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00398   (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00399    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00400    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00401    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00402    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00403    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00404    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00405    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00406    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00407    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00408    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00409    LL_DMA_CHANNEL_7)
00410 #else /* DMA1 */
00411 #if   defined(DMA1_Channel7)
00412 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00413   (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00414    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00415    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00416    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00417    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00418    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00419    LL_DMA_CHANNEL_7)
00420 #else
00421 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00422   (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00423    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00424    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00425    ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00426    LL_DMA_CHANNEL_5)
00427 #endif /* DMA1_Channel8 */
00428 #endif /* DMA2 */
00429
00430 /**
00431   * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
00432   * @param  __DMA_INSTANCE__ DMAx
00433   * @param  __CHANNEL__ LL_DMA_CHANNEL_y
00434   * @retval DMAx_Channely
00435   */
00436 #if defined(DMA2)
00437 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00438   ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00439    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00440    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00441    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00442    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00443    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00444    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00445    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00446    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00447    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00448    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00449    DMA1_Channel7)
00450 #else /* DMA1 */
00451 #if   defined(DMA1_Channel7)
00452 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00453   ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00454    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00455    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00456    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00457    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00458    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00459    DMA1_Channel7)
00460 #else
00461 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00462   ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00463    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00464    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00465    (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00466    DMA1_Channel5)
00467 #endif /* DMA1_Channel8 */
00468 #endif /* DMA2 */
00469
00470 /**
00471   * @}
00472   */
00473
00474 /**
00475   * @}
00476   */
00477
00478 /* Exported functions --------------------------------------------------------*/
00479 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
00480   * @{
00481   */
00482
00483 /** @defgroup DMA_LL_EF_Configuration Configuration
00484   * @{
00485   */
00486 /**
00487   * @brief  Enable DMA channel.
00488   * @rmtoll CCR          EN            LL_DMA_EnableChannel
00489   * @param  DMAx DMAx Instance
00490   * @param  Channel This parameter can be one of the following values:
00491   *         @arg @ref LL_DMA_CHANNEL_1
00492   *         @arg @ref LL_DMA_CHANNEL_2
00493   *         @arg @ref LL_DMA_CHANNEL_3
00494   *         @arg @ref LL_DMA_CHANNEL_4
00495   *         @arg @ref LL_DMA_CHANNEL_5
00496   *         @arg @ref LL_DMA_CHANNEL_6
00497   *         @arg @ref LL_DMA_CHANNEL_7
00498   * @retval None
00499   */
00500 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00501 {
00502   uint32_t dma_base_addr = (uint32_t)DMAx;
00503   SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
00504 }
00505
00506 /**
00507   * @brief  Disable DMA channel.
00508   * @rmtoll CCR          EN            LL_DMA_DisableChannel
00509   * @param  DMAx DMAx Instance
00510   * @param  Channel This parameter can be one of the following values:
00511   *         @arg @ref LL_DMA_CHANNEL_1
00512   *         @arg @ref LL_DMA_CHANNEL_2
00513   *         @arg @ref LL_DMA_CHANNEL_3
00514   *         @arg @ref LL_DMA_CHANNEL_4
00515   *         @arg @ref LL_DMA_CHANNEL_5
00516   *         @arg @ref LL_DMA_CHANNEL_6
00517   *         @arg @ref LL_DMA_CHANNEL_7
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00521 {
00522   uint32_t dma_base_addr = (uint32_t)DMAx;
00523   CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
00524 }
00525
00526 /**
00527   * @brief  Check if DMA channel is enabled or disabled.
00528   * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
00529   * @param  DMAx DMAx Instance
00530   * @param  Channel This parameter can be one of the following values:
00531   *         @arg @ref LL_DMA_CHANNEL_1
00532   *         @arg @ref LL_DMA_CHANNEL_2
00533   *         @arg @ref LL_DMA_CHANNEL_3
00534   *         @arg @ref LL_DMA_CHANNEL_4
00535   *         @arg @ref LL_DMA_CHANNEL_5
00536   *         @arg @ref LL_DMA_CHANNEL_6
00537   *         @arg @ref LL_DMA_CHANNEL_7
00538   * @retval State of bit (1 or 0).
00539   */
00540 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00541 {
00542   uint32_t dma_base_addr = (uint32_t)DMAx;
00543   return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00544                     DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
00545 }
00546
00547 /**
00548   * @brief  Configure all parameters link to DMA transfer.
00549   * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
00550   *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
00551   *         CCR          CIRC          LL_DMA_ConfigTransfer\n
00552   *         CCR          PINC          LL_DMA_ConfigTransfer\n
00553   *         CCR          MINC          LL_DMA_ConfigTransfer\n
00554   *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
00555   *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
00556   *         CCR          PL            LL_DMA_ConfigTransfer
00557   * @param  DMAx DMAx Instance
00558   * @param  Channel This parameter can be one of the following values:
00559   *         @arg @ref LL_DMA_CHANNEL_1
00560   *         @arg @ref LL_DMA_CHANNEL_2
00561   *         @arg @ref LL_DMA_CHANNEL_3
00562   *         @arg @ref LL_DMA_CHANNEL_4
00563   *         @arg @ref LL_DMA_CHANNEL_5
00564   *         @arg @ref LL_DMA_CHANNEL_6
00565   *         @arg @ref LL_DMA_CHANNEL_7
00566   * @param  Configuration This parameter must be a combination of all the following values:
00567   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00568   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
00569   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
00570   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
00571   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
00572   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
00573   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
00574   * @retval None
00575   */
00576 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
00577 {
00578   uint32_t dma_base_addr = (uint32_t)DMAx;
00579   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00580              DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
00581              Configuration);
00582 }
00583
00584 /**
00585   * @brief  Set Data transfer direction (read from peripheral or from memory).
00586   * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
00587   *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
00588   * @param  DMAx DMAx Instance
00589   * @param  Channel This parameter can be one of the following values:
00590   *         @arg @ref LL_DMA_CHANNEL_1
00591   *         @arg @ref LL_DMA_CHANNEL_2
00592   *         @arg @ref LL_DMA_CHANNEL_3
00593   *         @arg @ref LL_DMA_CHANNEL_4
00594   *         @arg @ref LL_DMA_CHANNEL_5
00595   *         @arg @ref LL_DMA_CHANNEL_6
00596   *         @arg @ref LL_DMA_CHANNEL_7
00597   * @param  Direction This parameter can be one of the following values:
00598   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00599   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00600   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00601   * @retval None
00602   */
00603 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
00604 {
00605   uint32_t dma_base_addr = (uint32_t)DMAx;
00606   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00607              DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
00608 }
00609
00610 /**
00611   * @brief  Get Data transfer direction (read from peripheral or from memory).
00612   * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
00613   *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
00614   * @param  DMAx DMAx Instance
00615   * @param  Channel This parameter can be one of the following values:
00616   *         @arg @ref LL_DMA_CHANNEL_1
00617   *         @arg @ref LL_DMA_CHANNEL_2
00618   *         @arg @ref LL_DMA_CHANNEL_3
00619   *         @arg @ref LL_DMA_CHANNEL_4
00620   *         @arg @ref LL_DMA_CHANNEL_5
00621   *         @arg @ref LL_DMA_CHANNEL_6
00622   *         @arg @ref LL_DMA_CHANNEL_7
00623   * @retval Returned value can be one of the following values:
00624   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00625   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00626   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00627   */
00628 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
00629 {
00630   uint32_t dma_base_addr = (uint32_t)DMAx;
00631   return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00632                    DMA_CCR_DIR | DMA_CCR_MEM2MEM));
00633 }
00634
00635 /**
00636   * @brief  Set DMA mode circular or normal.
00637   * @note The circular buffer mode cannot be used if the memory-to-memory
00638   * data transfer is configured on the selected Channel.
00639   * @rmtoll CCR          CIRC          LL_DMA_SetMode
00640   * @param  DMAx DMAx Instance
00641   * @param  Channel This parameter can be one of the following values:
00642   *         @arg @ref LL_DMA_CHANNEL_1
00643   *         @arg @ref LL_DMA_CHANNEL_2
00644   *         @arg @ref LL_DMA_CHANNEL_3
00645   *         @arg @ref LL_DMA_CHANNEL_4
00646   *         @arg @ref LL_DMA_CHANNEL_5
00647   *         @arg @ref LL_DMA_CHANNEL_6
00648   *         @arg @ref LL_DMA_CHANNEL_7
00649   * @param  Mode This parameter can be one of the following values:
00650   *         @arg @ref LL_DMA_MODE_NORMAL
00651   *         @arg @ref LL_DMA_MODE_CIRCULAR
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
00655 {
00656   uint32_t dma_base_addr = (uint32_t)DMAx;
00657   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
00658              Mode);
00659 }
00660
00661 /**
00662   * @brief  Get DMA mode circular or normal.
00663   * @rmtoll CCR          CIRC          LL_DMA_GetMode
00664   * @param  DMAx DMAx Instance
00665   * @param  Channel This parameter can be one of the following values:
00666   *         @arg @ref LL_DMA_CHANNEL_1
00667   *         @arg @ref LL_DMA_CHANNEL_2
00668   *         @arg @ref LL_DMA_CHANNEL_3
00669   *         @arg @ref LL_DMA_CHANNEL_4
00670   *         @arg @ref LL_DMA_CHANNEL_5
00671   *         @arg @ref LL_DMA_CHANNEL_6
00672   *         @arg @ref LL_DMA_CHANNEL_7
00673   * @retval Returned value can be one of the following values:
00674   *         @arg @ref LL_DMA_MODE_NORMAL
00675   *         @arg @ref LL_DMA_MODE_CIRCULAR
00676   */
00677 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
00678 {
00679   uint32_t dma_base_addr = (uint32_t)DMAx;
00680   return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00681                    DMA_CCR_CIRC));
00682 }
00683
00684 /**
00685   * @brief  Set Peripheral increment mode.
00686   * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
00687   * @param  DMAx DMAx Instance
00688   * @param  Channel This parameter can be one of the following values:
00689   *         @arg @ref LL_DMA_CHANNEL_1
00690   *         @arg @ref LL_DMA_CHANNEL_2
00691   *         @arg @ref LL_DMA_CHANNEL_3
00692   *         @arg @ref LL_DMA_CHANNEL_4
00693   *         @arg @ref LL_DMA_CHANNEL_5
00694   *         @arg @ref LL_DMA_CHANNEL_6
00695   *         @arg @ref LL_DMA_CHANNEL_7
00696   * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
00697   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00698   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00699   * @retval None
00700   */
00701 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
00702 {
00703   uint32_t dma_base_addr = (uint32_t)DMAx;
00704   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
00705              PeriphOrM2MSrcIncMode);
00706 }
00707
00708 /**
00709   * @brief  Get Peripheral increment mode.
00710   * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
00711   * @param  DMAx DMAx Instance
00712   * @param  Channel This parameter can be one of the following values:
00713   *         @arg @ref LL_DMA_CHANNEL_1
00714   *         @arg @ref LL_DMA_CHANNEL_2
00715   *         @arg @ref LL_DMA_CHANNEL_3
00716   *         @arg @ref LL_DMA_CHANNEL_4
00717   *         @arg @ref LL_DMA_CHANNEL_5
00718   *         @arg @ref LL_DMA_CHANNEL_6
00719   *         @arg @ref LL_DMA_CHANNEL_7
00720   * @retval Returned value can be one of the following values:
00721   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00722   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00723   */
00724 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00725 {
00726   uint32_t dma_base_addr = (uint32_t)DMAx;
00727   return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00728                    DMA_CCR_PINC));
00729 }
00730
00731 /**
00732   * @brief  Set Memory increment mode.
00733   * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
00734   * @param  DMAx DMAx Instance
00735   * @param  Channel This parameter can be one of the following values:
00736   *         @arg @ref LL_DMA_CHANNEL_1
00737   *         @arg @ref LL_DMA_CHANNEL_2
00738   *         @arg @ref LL_DMA_CHANNEL_3
00739   *         @arg @ref LL_DMA_CHANNEL_4
00740   *         @arg @ref LL_DMA_CHANNEL_5
00741   *         @arg @ref LL_DMA_CHANNEL_6
00742   *         @arg @ref LL_DMA_CHANNEL_7
00743   * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
00744   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00745   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00746   * @retval None
00747   */
00748 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
00749 {
00750   uint32_t dma_base_addr = (uint32_t)DMAx;
00751   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
00752              MemoryOrM2MDstIncMode);
00753 }
00754
00755 /**
00756   * @brief  Get Memory increment mode.
00757   * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
00758   * @param  DMAx DMAx Instance
00759   * @param  Channel This parameter can be one of the following values:
00760   *         @arg @ref LL_DMA_CHANNEL_1
00761   *         @arg @ref LL_DMA_CHANNEL_2
00762   *         @arg @ref LL_DMA_CHANNEL_3
00763   *         @arg @ref LL_DMA_CHANNEL_4
00764   *         @arg @ref LL_DMA_CHANNEL_5
00765   *         @arg @ref LL_DMA_CHANNEL_6
00766   *         @arg @ref LL_DMA_CHANNEL_7
00767   * @retval Returned value can be one of the following values:
00768   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00769   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00770   */
00771 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00772 {
00773   uint32_t dma_base_addr = (uint32_t)DMAx;
00774   return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00775                    DMA_CCR_MINC));
00776 }
00777
00778 /**
00779   * @brief  Set Peripheral size.
00780   * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
00781   * @param  DMAx DMAx Instance
00782   * @param  Channel This parameter can be one of the following values:
00783   *         @arg @ref LL_DMA_CHANNEL_1
00784   *         @arg @ref LL_DMA_CHANNEL_2
00785   *         @arg @ref LL_DMA_CHANNEL_3
00786   *         @arg @ref LL_DMA_CHANNEL_4
00787   *         @arg @ref LL_DMA_CHANNEL_5
00788   *         @arg @ref LL_DMA_CHANNEL_6
00789   *         @arg @ref LL_DMA_CHANNEL_7
00790   * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
00791   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00792   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00793   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00794   * @retval None
00795   */
00796 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
00797 {
00798   uint32_t dma_base_addr = (uint32_t)DMAx;
00799   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
00800              PeriphOrM2MSrcDataSize);
00801 }
00802
00803 /**
00804   * @brief  Get Peripheral size.
00805   * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
00806   * @param  DMAx DMAx Instance
00807   * @param  Channel This parameter can be one of the following values:
00808   *         @arg @ref LL_DMA_CHANNEL_1
00809   *         @arg @ref LL_DMA_CHANNEL_2
00810   *         @arg @ref LL_DMA_CHANNEL_3
00811   *         @arg @ref LL_DMA_CHANNEL_4
00812   *         @arg @ref LL_DMA_CHANNEL_5
00813   *         @arg @ref LL_DMA_CHANNEL_6
00814   *         @arg @ref LL_DMA_CHANNEL_7
00815   * @retval Returned value can be one of the following values:
00816   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00817   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00818   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00819   */
00820 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
00821 {
00822   uint32_t dma_base_addr = (uint32_t)DMAx;
00823   return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00824                    DMA_CCR_PSIZE));
00825 }
00826
00827 /**
00828   * @brief  Set Memory size.
00829   * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
00830   * @param  DMAx DMAx Instance
00831   * @param  Channel This parameter can be one of the following values:
00832   *         @arg @ref LL_DMA_CHANNEL_1
00833   *         @arg @ref LL_DMA_CHANNEL_2
00834   *         @arg @ref LL_DMA_CHANNEL_3
00835   *         @arg @ref LL_DMA_CHANNEL_4
00836   *         @arg @ref LL_DMA_CHANNEL_5
00837   *         @arg @ref LL_DMA_CHANNEL_6
00838   *         @arg @ref LL_DMA_CHANNEL_7
00839   * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
00840   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00841   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00842   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00843   * @retval None
00844   */
00845 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
00846 {
00847   uint32_t dma_base_addr = (uint32_t)DMAx;
00848   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
00849              MemoryOrM2MDstDataSize);
00850 }
00851
00852 /**
00853   * @brief  Get Memory size.
00854   * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
00855   * @param  DMAx DMAx Instance
00856   * @param  Channel This parameter can be one of the following values:
00857   *         @arg @ref LL_DMA_CHANNEL_1
00858   *         @arg @ref LL_DMA_CHANNEL_2
00859   *         @arg @ref LL_DMA_CHANNEL_3
00860   *         @arg @ref LL_DMA_CHANNEL_4
00861   *         @arg @ref LL_DMA_CHANNEL_5
00862   *         @arg @ref LL_DMA_CHANNEL_6
00863   *         @arg @ref LL_DMA_CHANNEL_7
00864   * @retval Returned value can be one of the following values:
00865   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00866   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00867   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00868   */
00869 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
00870 {
00871   uint32_t dma_base_addr = (uint32_t)DMAx;
00872   return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00873                    DMA_CCR_MSIZE));
00874 }
00875
00876 /**
00877   * @brief  Set Channel priority level.
00878   * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
00879   * @param  DMAx DMAx Instance
00880   * @param  Channel This parameter can be one of the following values:
00881   *         @arg @ref LL_DMA_CHANNEL_1
00882   *         @arg @ref LL_DMA_CHANNEL_2
00883   *         @arg @ref LL_DMA_CHANNEL_3
00884   *         @arg @ref LL_DMA_CHANNEL_4
00885   *         @arg @ref LL_DMA_CHANNEL_5
00886   *         @arg @ref LL_DMA_CHANNEL_6
00887   *         @arg @ref LL_DMA_CHANNEL_7
00888   * @param  Priority This parameter can be one of the following values:
00889   *         @arg @ref LL_DMA_PRIORITY_LOW
00890   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00891   *         @arg @ref LL_DMA_PRIORITY_HIGH
00892   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00893   * @retval None
00894   */
00895 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
00896 {
00897   uint32_t dma_base_addr = (uint32_t)DMAx;
00898   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
00899              Priority);
00900 }
00901
00902 /**
00903   * @brief  Get Channel priority level.
00904   * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
00905   * @param  DMAx DMAx Instance
00906   * @param  Channel This parameter can be one of the following values:
00907   *         @arg @ref LL_DMA_CHANNEL_1
00908   *         @arg @ref LL_DMA_CHANNEL_2
00909   *         @arg @ref LL_DMA_CHANNEL_3
00910   *         @arg @ref LL_DMA_CHANNEL_4
00911   *         @arg @ref LL_DMA_CHANNEL_5
00912   *         @arg @ref LL_DMA_CHANNEL_6
00913   *         @arg @ref LL_DMA_CHANNEL_7
00914   * @retval Returned value can be one of the following values:
00915   *         @arg @ref LL_DMA_PRIORITY_LOW
00916   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00917   *         @arg @ref LL_DMA_PRIORITY_HIGH
00918   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00919   */
00920 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
00921 {
00922   uint32_t dma_base_addr = (uint32_t)DMAx;
00923   return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
00924                    DMA_CCR_PL));
00925 }
00926
00927 /**
00928   * @brief  Set Number of data to transfer.
00929   * @note   This action has no effect if
00930   *         channel is enabled.
00931   * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
00932   * @param  DMAx DMAx Instance
00933   * @param  Channel This parameter can be one of the following values:
00934   *         @arg @ref LL_DMA_CHANNEL_1
00935   *         @arg @ref LL_DMA_CHANNEL_2
00936   *         @arg @ref LL_DMA_CHANNEL_3
00937   *         @arg @ref LL_DMA_CHANNEL_4
00938   *         @arg @ref LL_DMA_CHANNEL_5
00939   *         @arg @ref LL_DMA_CHANNEL_6
00940   *         @arg @ref LL_DMA_CHANNEL_7
00941   * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
00942   * @retval None
00943   */
00944 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
00945 {
00946   uint32_t dma_base_addr = (uint32_t)DMAx;
00947   MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
00948              DMA_CNDTR_NDT, NbData);
00949 }
00950
00951 /**
00952   * @brief  Get Number of data to transfer.
00953   * @note   Once the channel is enabled, the return value indicate the
00954   *         remaining bytes to be transmitted.
00955   * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
00956   * @param  DMAx DMAx Instance
00957   * @param  Channel This parameter can be one of the following values:
00958   *         @arg @ref LL_DMA_CHANNEL_1
00959   *         @arg @ref LL_DMA_CHANNEL_2
00960   *         @arg @ref LL_DMA_CHANNEL_3
00961   *         @arg @ref LL_DMA_CHANNEL_4
00962   *         @arg @ref LL_DMA_CHANNEL_5
00963   *         @arg @ref LL_DMA_CHANNEL_6
00964   *         @arg @ref LL_DMA_CHANNEL_7
00965   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00966   */
00967 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
00968 {
00969   uint32_t dma_base_addr = (uint32_t)DMAx;
00970   return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
00971                    DMA_CNDTR_NDT));
00972 }
00973
00974 /**
00975   * @brief  Configure the Source and Destination addresses.
00976   * @note   This API must not be called when the DMA channel is enabled.
00977   * @note   Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
00978   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
00979   *         CMAR         MA            LL_DMA_ConfigAddresses
00980   * @param  DMAx DMAx Instance
00981   * @param  Channel This parameter can be one of the following values:
00982   *         @arg @ref LL_DMA_CHANNEL_1
00983   *         @arg @ref LL_DMA_CHANNEL_2
00984   *         @arg @ref LL_DMA_CHANNEL_3
00985   *         @arg @ref LL_DMA_CHANNEL_4
00986   *         @arg @ref LL_DMA_CHANNEL_5
00987   *         @arg @ref LL_DMA_CHANNEL_6
00988   *         @arg @ref LL_DMA_CHANNEL_7
00989   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00990   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00991   * @param  Direction This parameter can be one of the following values:
00992   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00993   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00994   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00995   * @retval None
00996   */
00997 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
00998                                             uint32_t DstAddress, uint32_t Direction)
00999 {
01000   uint32_t dma_base_addr = (uint32_t)DMAx;
01001   /* Direction Memory to Periph */
01002   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
01003   {
01004     WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress);
01005     WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
01006   }
01007   /* Direction Periph to Memory and Memory to Memory */
01008   else
01009   {
01010     WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
01011     WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress);
01012   }
01013 }
01014
01015 /**
01016   * @brief  Set the Memory address.
01017   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01018   * @note   This API must not be called when the DMA channel is enabled.
01019   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
01020   * @param  DMAx DMAx Instance
01021   * @param  Channel This parameter can be one of the following values:
01022   *         @arg @ref LL_DMA_CHANNEL_1
01023   *         @arg @ref LL_DMA_CHANNEL_2
01024   *         @arg @ref LL_DMA_CHANNEL_3
01025   *         @arg @ref LL_DMA_CHANNEL_4
01026   *         @arg @ref LL_DMA_CHANNEL_5
01027   *         @arg @ref LL_DMA_CHANNEL_6
01028   *         @arg @ref LL_DMA_CHANNEL_7
01029   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01030   * @retval None
01031   */
01032 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01033 {
01034   uint32_t dma_base_addr = (uint32_t)DMAx;
01035   WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
01036 }
01037
01038 /**
01039   * @brief  Set the Peripheral address.
01040   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01041   * @note   This API must not be called when the DMA channel is enabled.
01042   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
01043   * @param  DMAx DMAx Instance
01044   * @param  Channel This parameter can be one of the following values:
01045   *         @arg @ref LL_DMA_CHANNEL_1
01046   *         @arg @ref LL_DMA_CHANNEL_2
01047   *         @arg @ref LL_DMA_CHANNEL_3
01048   *         @arg @ref LL_DMA_CHANNEL_4
01049   *         @arg @ref LL_DMA_CHANNEL_5
01050   *         @arg @ref LL_DMA_CHANNEL_6
01051   *         @arg @ref LL_DMA_CHANNEL_7
01052   * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01053   * @retval None
01054   */
01055 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
01056 {
01057   uint32_t dma_base_addr = (uint32_t)DMAx;
01058   WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
01059 }
01060
01061 /**
01062   * @brief  Get Memory address.
01063   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01064   * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
01065   * @param  DMAx DMAx Instance
01066   * @param  Channel This parameter can be one of the following values:
01067   *         @arg @ref LL_DMA_CHANNEL_1
01068   *         @arg @ref LL_DMA_CHANNEL_2
01069   *         @arg @ref LL_DMA_CHANNEL_3
01070   *         @arg @ref LL_DMA_CHANNEL_4
01071   *         @arg @ref LL_DMA_CHANNEL_5
01072   *         @arg @ref LL_DMA_CHANNEL_6
01073   *         @arg @ref LL_DMA_CHANNEL_7
01074   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01075   */
01076 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01077 {
01078   uint32_t dma_base_addr = (uint32_t)DMAx;
01079   return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
01080 }
01081
01082 /**
01083   * @brief  Get Peripheral address.
01084   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01085   * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
01086   * @param  DMAx DMAx Instance
01087   * @param  Channel This parameter can be one of the following values:
01088   *         @arg @ref LL_DMA_CHANNEL_1
01089   *         @arg @ref LL_DMA_CHANNEL_2
01090   *         @arg @ref LL_DMA_CHANNEL_3
01091   *         @arg @ref LL_DMA_CHANNEL_4
01092   *         @arg @ref LL_DMA_CHANNEL_5
01093   *         @arg @ref LL_DMA_CHANNEL_6
01094   *         @arg @ref LL_DMA_CHANNEL_7
01095   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01096   */
01097 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01098 {
01099   uint32_t dma_base_addr = (uint32_t)DMAx;
01100   return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
01101 }
01102
01103 /**
01104   * @brief  Set the Memory to Memory Source address.
01105   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01106   * @note   This API must not be called when the DMA channel is enabled.
01107   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
01108   * @param  DMAx DMAx Instance
01109   * @param  Channel This parameter can be one of the following values:
01110   *         @arg @ref LL_DMA_CHANNEL_1
01111   *         @arg @ref LL_DMA_CHANNEL_2
01112   *         @arg @ref LL_DMA_CHANNEL_3
01113   *         @arg @ref LL_DMA_CHANNEL_4
01114   *         @arg @ref LL_DMA_CHANNEL_5
01115   *         @arg @ref LL_DMA_CHANNEL_6
01116   *         @arg @ref LL_DMA_CHANNEL_7
01117   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01118   * @retval None
01119   */
01120 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01121 {
01122   uint32_t dma_base_addr = (uint32_t)DMAx;
01123   WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
01124 }
01125
01126 /**
01127   * @brief  Set the Memory to Memory Destination address.
01128   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01129   * @note   This API must not be called when the DMA channel is enabled.
01130   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
01131   * @param  DMAx DMAx Instance
01132   * @param  Channel This parameter can be one of the following values:
01133   *         @arg @ref LL_DMA_CHANNEL_1
01134   *         @arg @ref LL_DMA_CHANNEL_2
01135   *         @arg @ref LL_DMA_CHANNEL_3
01136   *         @arg @ref LL_DMA_CHANNEL_4
01137   *         @arg @ref LL_DMA_CHANNEL_5
01138   *         @arg @ref LL_DMA_CHANNEL_6
01139   *         @arg @ref LL_DMA_CHANNEL_7
01140   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01141   * @retval None
01142   */
01143 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01144 {
01145   uint32_t dma_base_addr = (uint32_t)DMAx;
01146   WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
01147 }
01148
01149 /**
01150   * @brief  Get the Memory to Memory Source address.
01151   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01152   * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
01153   * @param  DMAx DMAx Instance
01154   * @param  Channel This parameter can be one of the following values:
01155   *         @arg @ref LL_DMA_CHANNEL_1
01156   *         @arg @ref LL_DMA_CHANNEL_2
01157   *         @arg @ref LL_DMA_CHANNEL_3
01158   *         @arg @ref LL_DMA_CHANNEL_4
01159   *         @arg @ref LL_DMA_CHANNEL_5
01160   *         @arg @ref LL_DMA_CHANNEL_6
01161   *         @arg @ref LL_DMA_CHANNEL_7
01162   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01163   */
01164 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01165 {
01166   uint32_t dma_base_addr = (uint32_t)DMAx;
01167   return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
01168 }
01169
01170 /**
01171   * @brief  Get the Memory to Memory Destination address.
01172   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01173   * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
01174   * @param  DMAx DMAx Instance
01175   * @param  Channel This parameter can be one of the following values:
01176   *         @arg @ref LL_DMA_CHANNEL_1
01177   *         @arg @ref LL_DMA_CHANNEL_2
01178   *         @arg @ref LL_DMA_CHANNEL_3
01179   *         @arg @ref LL_DMA_CHANNEL_4
01180   *         @arg @ref LL_DMA_CHANNEL_5
01181   *         @arg @ref LL_DMA_CHANNEL_6
01182   *         @arg @ref LL_DMA_CHANNEL_7
01183   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01184   */
01185 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01186 {
01187   uint32_t dma_base_addr = (uint32_t)DMAx;
01188   return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
01189 }
01190
01191 /**
01192   * @brief  Set DMA request for DMA Channels on DMAMUX Channel x.
01193   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
01194   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
01195   * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest
01196   * @param  DMAx DMAx Instance
01197   * @param  Channel This parameter can be one of the following values:
01198   *         @arg @ref LL_DMA_CHANNEL_1
01199   *         @arg @ref LL_DMA_CHANNEL_2
01200   *         @arg @ref LL_DMA_CHANNEL_3
01201   *         @arg @ref LL_DMA_CHANNEL_4
01202   *         @arg @ref LL_DMA_CHANNEL_5
01203   *         @arg @ref LL_DMA_CHANNEL_6
01204   *         @arg @ref LL_DMA_CHANNEL_7
01205   * @param  Request This parameter can be one of the following values:
01206   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
01207   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
01208   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
01209   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
01210   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
01211   *         @arg @ref LL_DMAMUX_REQ_ADC1
01212   *         @arg @ref LL_DMAMUX_REQ_AES_IN
01213   *         @arg @ref LL_DMAMUX_REQ_AES_OUT
01214   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
01215   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
01216   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
01217   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
01218   *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
01219   *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
01220   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
01221   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
01222   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
01223   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
01224   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
01225   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
01226   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
01227   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
01228   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
01229   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
01230   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
01231   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
01232   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
01233   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
01234   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
01235   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
01236   *         @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
01237   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
01238   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
01239   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
01240   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
01241   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
01242   *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
01243   *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
01244   *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
01245   *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
01246   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
01247   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH2
01248   *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
01249   *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
01250   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
01251   *         @arg @ref LL_DMAMUX_REQ_TIM16_COM
01252   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
01253   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
01254   *         @arg @ref LL_DMAMUX_REQ_TIM17_COM
01255   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
01256   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
01257   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
01258   *         @arg @ref LL_DMAMUX_REQ_USART2_RX
01259   *         @arg @ref LL_DMAMUX_REQ_USART2_TX
01260   *         @arg @ref LL_DMAMUX_REQ_USART3_RX
01261   *         @arg @ref LL_DMAMUX_REQ_USART3_TX
01262   *         @arg @ref LL_DMAMUX_REQ_USART4_RX
01263   *         @arg @ref LL_DMAMUX_REQ_USART4_TX
01264   *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
01265   *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
01266   *         @arg @ref LL_DMAMUX_REQ_UCPD2_RX
01267   *         @arg @ref LL_DMAMUX_REQ_UCPD2_TX
01268   * @retval None
01269   */
01270 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
01271 {
01272   uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
01273   MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
01274 }
01275
01276 /**
01277   * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.
01278   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
01279   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
01280   * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest
01281   * @param  DMAx DMAx Instance
01282   * @param  Channel This parameter can be one of the following values:
01283   *         @arg @ref LL_DMA_CHANNEL_1
01284   *         @arg @ref LL_DMA_CHANNEL_2
01285   *         @arg @ref LL_DMA_CHANNEL_3
01286   *         @arg @ref LL_DMA_CHANNEL_4
01287   *         @arg @ref LL_DMA_CHANNEL_5
01288   *         @arg @ref LL_DMA_CHANNEL_6
01289   *         @arg @ref LL_DMA_CHANNEL_7
01290   * @retval Returned value can be one of the following values:
01291   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
01292   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
01293   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
01294   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
01295   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
01296   *         @arg @ref LL_DMAMUX_REQ_ADC1
01297   *         @arg @ref LL_DMAMUX_REQ_AES_IN
01298   *         @arg @ref LL_DMAMUX_REQ_AES_OUT
01299   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
01300   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
01301   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
01302   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
01303   *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
01304   *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
01305   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
01306   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
01307   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
01308   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
01309   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
01310   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
01311   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
01312   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
01313   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
01314   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
01315   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
01316   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
01317   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
01318   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
01319   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
01320   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
01321   *         @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
01322   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
01323   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
01324   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
01325   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
01326   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
01327   *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
01328   *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
01329   *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
01330   *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
01331   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
01332   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH2
01333   *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
01334   *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
01335   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
01336   *         @arg @ref LL_DMAMUX_REQ_TIM16_COM
01337   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
01338   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
01339   *         @arg @ref LL_DMAMUX_REQ_TIM17_COM
01340   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
01341   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
01342   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
01343   *         @arg @ref LL_DMAMUX_REQ_USART2_RX
01344   *         @arg @ref LL_DMAMUX_REQ_USART2_TX
01345   *         @arg @ref LL_DMAMUX_REQ_USART3_RX
01346   *         @arg @ref LL_DMAMUX_REQ_USART3_TX
01347   *         @arg @ref LL_DMAMUX_REQ_USART4_RX
01348   *         @arg @ref LL_DMAMUX_REQ_USART4_TX
01349   *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
01350   *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
01351   *         @arg @ref LL_DMAMUX_REQ_UCPD2_RX
01352   *         @arg @ref LL_DMAMUX_REQ_UCPD2_TX
01353   */
01354 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
01355 {
01356   uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
01357   return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
01358 }
01359
01360 /**
01361   * @}
01362   */
01363
01364 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
01365   * @{
01366   */
01367
01368 /**
01369   * @brief  Get Channel 1 global interrupt flag.
01370   * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
01371   * @param  DMAx DMAx Instance
01372   * @retval State of bit (1 or 0).
01373   */
01374 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
01375 {
01376   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
01377 }
01378
01379 /**
01380   * @brief  Get Channel 2 global interrupt flag.
01381   * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
01382   * @param  DMAx DMAx Instance
01383   * @retval State of bit (1 or 0).
01384   */
01385 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
01386 {
01387   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
01388 }
01389
01390 /**
01391   * @brief  Get Channel 3 global interrupt flag.
01392   * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
01393   * @param  DMAx DMAx Instance
01394   * @retval State of bit (1 or 0).
01395   */
01396 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
01397 {
01398   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
01399 }
01400
01401 /**
01402   * @brief  Get Channel 4 global interrupt flag.
01403   * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
01404   * @param  DMAx DMAx Instance
01405   * @retval State of bit (1 or 0).
01406   */
01407 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
01408 {
01409   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
01410 }
01411
01412 /**
01413   * @brief  Get Channel 5 global interrupt flag.
01414   * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
01415   * @param  DMAx DMAx Instance
01416   * @retval State of bit (1 or 0).
01417   */
01418 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
01419 {
01420   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
01421 }
01422
01423 #if defined(DMA1_Channel6)
01424 /**
01425   * @brief  Get Channel 6 global interrupt flag.
01426   * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
01427   * @param  DMAx DMAx Instance
01428   * @retval State of bit (1 or 0).
01429   */
01430 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
01431 {
01432   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
01433 }
01434
01435 #endif /* DMA1_Channel6 */
01436 #if defined(DMA1_Channel7)
01437 /**
01438   * @brief  Get Channel 7 global interrupt flag.
01439   * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
01440   * @param  DMAx DMAx Instance
01441   * @retval State of bit (1 or 0).
01442   */
01443 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
01444 {
01445   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
01446 }
01447
01448 #endif /* DMA1_Channel7 */
01449 /**
01450   * @brief  Get Channel 1 transfer complete flag.
01451   * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
01452   * @param  DMAx DMAx Instance
01453   * @retval State of bit (1 or 0).
01454   */
01455 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
01456 {
01457   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
01458 }
01459
01460 /**
01461   * @brief  Get Channel 2 transfer complete flag.
01462   * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
01463   * @param  DMAx DMAx Instance
01464   * @retval State of bit (1 or 0).
01465   */
01466 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
01467 {
01468   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
01469 }
01470
01471 /**
01472   * @brief  Get Channel 3 transfer complete flag.
01473   * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
01474   * @param  DMAx DMAx Instance
01475   * @retval State of bit (1 or 0).
01476   */
01477 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
01478 {
01479   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
01480 }
01481
01482 /**
01483   * @brief  Get Channel 4 transfer complete flag.
01484   * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
01485   * @param  DMAx DMAx Instance
01486   * @retval State of bit (1 or 0).
01487   */
01488 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
01489 {
01490   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
01491 }
01492
01493 /**
01494   * @brief  Get Channel 5 transfer complete flag.
01495   * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
01496   * @param  DMAx DMAx Instance
01497   * @retval State of bit (1 or 0).
01498   */
01499 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
01500 {
01501   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
01502 }
01503
01504 #if defined(DMA1_Channel6)
01505 /**
01506   * @brief  Get Channel 6 transfer complete flag.
01507   * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
01508   * @param  DMAx DMAx Instance
01509   * @retval State of bit (1 or 0).
01510   */
01511 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
01512 {
01513   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
01514 }
01515
01516 #endif /* DMA1_Channel6 */
01517 #if defined(DMA1_Channel7)
01518 /**
01519   * @brief  Get Channel 7 transfer complete flag.
01520   * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
01521   * @param  DMAx DMAx Instance
01522   * @retval State of bit (1 or 0).
01523   */
01524 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
01525 {
01526   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
01527 }
01528
01529 #endif /* DMA1_Channel7 */
01530 /**
01531   * @brief  Get Channel 1 half transfer flag.
01532   * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
01533   * @param  DMAx DMAx Instance
01534   * @retval State of bit (1 or 0).
01535   */
01536 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
01537 {
01538   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
01539 }
01540
01541 /**
01542   * @brief  Get Channel 2 half transfer flag.
01543   * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
01544   * @param  DMAx DMAx Instance
01545   * @retval State of bit (1 or 0).
01546   */
01547 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
01548 {
01549   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
01550 }
01551
01552 /**
01553   * @brief  Get Channel 3 half transfer flag.
01554   * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
01555   * @param  DMAx DMAx Instance
01556   * @retval State of bit (1 or 0).
01557   */
01558 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
01559 {
01560   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
01561 }
01562
01563 /**
01564   * @brief  Get Channel 4 half transfer flag.
01565   * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
01566   * @param  DMAx DMAx Instance
01567   * @retval State of bit (1 or 0).
01568   */
01569 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
01570 {
01571   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
01572 }
01573
01574 /**
01575   * @brief  Get Channel 5 half transfer flag.
01576   * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
01577   * @param  DMAx DMAx Instance
01578   * @retval State of bit (1 or 0).
01579   */
01580 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
01581 {
01582   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
01583 }
01584
01585 #if defined(DMA1_Channel6)
01586 /**
01587   * @brief  Get Channel 6 half transfer flag.
01588   * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
01589   * @param  DMAx DMAx Instance
01590   * @retval State of bit (1 or 0).
01591   */
01592 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
01593 {
01594   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
01595 }
01596
01597 #endif /* DMA1_Channel6 */
01598 #if defined(DMA1_Channel7)
01599 /**
01600   * @brief  Get Channel 7 half transfer flag.
01601   * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
01602   * @param  DMAx DMAx Instance
01603   * @retval State of bit (1 or 0).
01604   */
01605 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
01606 {
01607   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
01608 }
01609
01610 #endif /* DMA1_Channel7 */
01611 /**
01612   * @brief  Get Channel 1 transfer error flag.
01613   * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
01614   * @param  DMAx DMAx Instance
01615   * @retval State of bit (1 or 0).
01616   */
01617 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
01618 {
01619   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
01620 }
01621
01622 /**
01623   * @brief  Get Channel 2 transfer error flag.
01624   * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
01625   * @param  DMAx DMAx Instance
01626   * @retval State of bit (1 or 0).
01627   */
01628 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
01629 {
01630   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
01631 }
01632
01633 /**
01634   * @brief  Get Channel 3 transfer error flag.
01635   * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
01636   * @param  DMAx DMAx Instance
01637   * @retval State of bit (1 or 0).
01638   */
01639 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
01640 {
01641   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
01642 }
01643
01644 /**
01645   * @brief  Get Channel 4 transfer error flag.
01646   * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
01647   * @param  DMAx DMAx Instance
01648   * @retval State of bit (1 or 0).
01649   */
01650 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
01651 {
01652   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
01653 }
01654
01655 /**
01656   * @brief  Get Channel 5 transfer error flag.
01657   * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
01658   * @param  DMAx DMAx Instance
01659   * @retval State of bit (1 or 0).
01660   */
01661 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
01662 {
01663   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
01664 }
01665
01666 #if defined(DMA1_Channel6)
01667 /**
01668   * @brief  Get Channel 6 transfer error flag.
01669   * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
01670   * @param  DMAx DMAx Instance
01671   * @retval State of bit (1 or 0).
01672   */
01673 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
01674 {
01675   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
01676 }
01677
01678 #endif /* DMA1_Channel6 */
01679 #if defined(DMA1_Channel7)
01680 /**
01681   * @brief  Get Channel 7 transfer error flag.
01682   * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
01683   * @param  DMAx DMAx Instance
01684   * @retval State of bit (1 or 0).
01685   */
01686 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
01687 {
01688   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
01689 }
01690
01691 #endif /* DMA1_Channel7 */
01692 /**
01693   * @brief  Clear Channel 1 global interrupt flag.
01694   * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
01695     Instead clear specific flags transfer complete, half transfer & transfer
01696     error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
01697     LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
01698   * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
01699   * @param  DMAx DMAx Instance
01700   * @retval None
01701   */
01702 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
01703 {
01704   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
01705 }
01706
01707 /**
01708   * @brief  Clear Channel 2 global interrupt flag.
01709   * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
01710     Instead clear specific flags transfer complete, half transfer & transfer
01711     error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
01712     LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
01713   * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
01714   * @param  DMAx DMAx Instance
01715   * @retval None
01716   */
01717 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
01718 {
01719   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
01720 }
01721
01722 /**
01723   * @brief  Clear Channel 3 global interrupt flag.
01724   * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
01725     Instead clear specific flags transfer complete, half transfer & transfer
01726     error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
01727     LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
01728   * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
01729   * @param  DMAx DMAx Instance
01730   * @retval None
01731   */
01732 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
01733 {
01734   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
01735 }
01736
01737 /**
01738   * @brief  Clear Channel 4 global interrupt flag.
01739   * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
01740     Instead clear specific flags transfer complete, half transfer & transfer
01741     error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
01742     LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
01743   * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
01744   * @param  DMAx DMAx Instance
01745   * @retval None
01746   */
01747 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
01748 {
01749   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
01750 }
01751
01752 /**
01753   * @brief  Clear Channel 5 global interrupt flag.
01754   * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
01755     Instead clear specific flags transfer complete, half transfer & transfer
01756     error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
01757     LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
01758   * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
01759   * @param  DMAx DMAx Instance
01760   * @retval None
01761   */
01762 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
01763 {
01764   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
01765 }
01766
01767 #if defined(DMA1_Channel6)
01768 /**
01769   * @brief  Clear Channel 6 global interrupt flag.
01770   * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
01771     Instead clear specific flags transfer complete, half transfer & transfer
01772     error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
01773     LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet.
01774   * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
01775   * @param  DMAx DMAx Instance
01776   * @retval None
01777   */
01778 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
01779 {
01780   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
01781 }
01782
01783 #endif /* DMA1_Channel6 */
01784 #if defined(DMA1_Channel7)
01785 /**
01786   * @brief  Clear Channel 7 global interrupt flag.
01787   * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
01788     Instead clear specific flags transfer complete, half transfer & transfer
01789     error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
01790     LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet.
01791   * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
01792   * @param  DMAx DMAx Instance
01793   * @retval None
01794   */
01795 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
01796 {
01797   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
01798 }
01799
01800 #endif /* DMA1_Channel7 */
01801 /**
01802   * @brief  Clear Channel 1  transfer complete flag.
01803   * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
01804   * @param  DMAx DMAx Instance
01805   * @retval None
01806   */
01807 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
01808 {
01809   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
01810 }
01811
01812 /**
01813   * @brief  Clear Channel 2  transfer complete flag.
01814   * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
01815   * @param  DMAx DMAx Instance
01816   * @retval None
01817   */
01818 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
01819 {
01820   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
01821 }
01822
01823 /**
01824   * @brief  Clear Channel 3  transfer complete flag.
01825   * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
01826   * @param  DMAx DMAx Instance
01827   * @retval None
01828   */
01829 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
01830 {
01831   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
01832 }
01833
01834 /**
01835   * @brief  Clear Channel 4  transfer complete flag.
01836   * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
01837   * @param  DMAx DMAx Instance
01838   * @retval None
01839   */
01840 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
01841 {
01842   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
01843 }
01844
01845 /**
01846   * @brief  Clear Channel 5  transfer complete flag.
01847   * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
01848   * @param  DMAx DMAx Instance
01849   * @retval None
01850   */
01851 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
01852 {
01853   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
01854 }
01855
01856 #if defined(DMA1_Channel6)
01857 /**
01858   * @brief  Clear Channel 6  transfer complete flag.
01859   * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
01860   * @param  DMAx DMAx Instance
01861   * @retval None
01862   */
01863 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
01864 {
01865   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
01866 }
01867
01868 #endif /* DMA1_Channel6 */
01869 #if defined(DMA1_Channel7)
01870 /**
01871   * @brief  Clear Channel 7  transfer complete flag.
01872   * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
01873   * @param  DMAx DMAx Instance
01874   * @retval None
01875   */
01876 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
01877 {
01878   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
01879 }
01880
01881 #endif /* DMA1_Channel7 */
01882 /**
01883   * @brief  Clear Channel 1  half transfer flag.
01884   * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
01885   * @param  DMAx DMAx Instance
01886   * @retval None
01887   */
01888 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
01889 {
01890   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
01891 }
01892
01893 /**
01894   * @brief  Clear Channel 2  half transfer flag.
01895   * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
01896   * @param  DMAx DMAx Instance
01897   * @retval None
01898   */
01899 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
01900 {
01901   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
01902 }
01903
01904 /**
01905   * @brief  Clear Channel 3  half transfer flag.
01906   * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
01907   * @param  DMAx DMAx Instance
01908   * @retval None
01909   */
01910 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
01911 {
01912   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
01913 }
01914
01915 /**
01916   * @brief  Clear Channel 4  half transfer flag.
01917   * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
01918   * @param  DMAx DMAx Instance
01919   * @retval None
01920   */
01921 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
01922 {
01923   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
01924 }
01925
01926 /**
01927   * @brief  Clear Channel 5  half transfer flag.
01928   * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
01929   * @param  DMAx DMAx Instance
01930   * @retval None
01931   */
01932 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
01933 {
01934   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
01935 }
01936
01937 #if defined(DMA1_Channel6)
01938 /**
01939   * @brief  Clear Channel 6  half transfer flag.
01940   * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
01941   * @param  DMAx DMAx Instance
01942   * @retval None
01943   */
01944 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
01945 {
01946   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
01947 }
01948
01949 #endif /* DMA1_Channel6 */
01950 #if defined(DMA1_Channel7)
01951 /**
01952   * @brief  Clear Channel 7  half transfer flag.
01953   * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
01954   * @param  DMAx DMAx Instance
01955   * @retval None
01956   */
01957 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
01958 {
01959   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
01960 }
01961
01962 #endif /* DMA1_Channel7 */
01963 /**
01964   * @brief  Clear Channel 1 transfer error flag.
01965   * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
01966   * @param  DMAx DMAx Instance
01967   * @retval None
01968   */
01969 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
01970 {
01971   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
01972 }
01973
01974 /**
01975   * @brief  Clear Channel 2 transfer error flag.
01976   * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
01977   * @param  DMAx DMAx Instance
01978   * @retval None
01979   */
01980 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
01981 {
01982   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
01983 }
01984
01985 /**
01986   * @brief  Clear Channel 3 transfer error flag.
01987   * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
01988   * @param  DMAx DMAx Instance
01989   * @retval None
01990   */
01991 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
01992 {
01993   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
01994 }
01995
01996 /**
01997   * @brief  Clear Channel 4 transfer error flag.
01998   * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
01999   * @param  DMAx DMAx Instance
02000   * @retval None
02001   */
02002 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
02003 {
02004   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
02005 }
02006
02007 /**
02008   * @brief  Clear Channel 5 transfer error flag.
02009   * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
02010   * @param  DMAx DMAx Instance
02011   * @retval None
02012   */
02013 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
02014 {
02015   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
02016 }
02017
02018 #if defined(DMA1_Channel6)
02019 /**
02020   * @brief  Clear Channel 6 transfer error flag.
02021   * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
02022   * @param  DMAx DMAx Instance
02023   * @retval None
02024   */
02025 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
02026 {
02027   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
02028 }
02029
02030 #endif /* DMA1_Channel6 */
02031 #if defined(DMA1_Channel7)
02032 /**
02033   * @brief  Clear Channel 7 transfer error flag.
02034   * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
02035   * @param  DMAx DMAx Instance
02036   * @retval None
02037   */
02038 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
02039 {
02040   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
02041 }
02042
02043 #endif /* DMA1_Channel7 */
02044 /**
02045   * @}
02046   */
02047
02048 /** @defgroup DMA_LL_EF_IT_Management IT_Management
02049   * @{
02050   */
02051 /**
02052   * @brief  Enable Transfer complete interrupt.
02053   * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
02054   * @param  DMAx DMAx Instance
02055   * @param  Channel This parameter can be one of the following values:
02056   *         @arg @ref LL_DMA_CHANNEL_1
02057   *         @arg @ref LL_DMA_CHANNEL_2
02058   *         @arg @ref LL_DMA_CHANNEL_3
02059   *         @arg @ref LL_DMA_CHANNEL_4
02060   *         @arg @ref LL_DMA_CHANNEL_5
02061   *         @arg @ref LL_DMA_CHANNEL_6
02062   *         @arg @ref LL_DMA_CHANNEL_7
02063   * @retval None
02064   */
02065 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02066 {
02067   uint32_t dma_base_addr = (uint32_t)DMAx;
02068   SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
02069 }
02070
02071 /**
02072   * @brief  Enable Half transfer interrupt.
02073   * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
02074   * @param  DMAx DMAx Instance
02075   * @param  Channel This parameter can be one of the following values:
02076   *         @arg @ref LL_DMA_CHANNEL_1
02077   *         @arg @ref LL_DMA_CHANNEL_2
02078   *         @arg @ref LL_DMA_CHANNEL_3
02079   *         @arg @ref LL_DMA_CHANNEL_4
02080   *         @arg @ref LL_DMA_CHANNEL_5
02081   *         @arg @ref LL_DMA_CHANNEL_6
02082   *         @arg @ref LL_DMA_CHANNEL_7
02083   * @retval None
02084   */
02085 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02086 {
02087   uint32_t dma_base_addr = (uint32_t)DMAx;
02088   SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
02089 }
02090
02091 /**
02092   * @brief  Enable Transfer error interrupt.
02093   * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
02094   * @param  DMAx DMAx Instance
02095   * @param  Channel This parameter can be one of the following values:
02096   *         @arg @ref LL_DMA_CHANNEL_1
02097   *         @arg @ref LL_DMA_CHANNEL_2
02098   *         @arg @ref LL_DMA_CHANNEL_3
02099   *         @arg @ref LL_DMA_CHANNEL_4
02100   *         @arg @ref LL_DMA_CHANNEL_5
02101   *         @arg @ref LL_DMA_CHANNEL_6
02102   *         @arg @ref LL_DMA_CHANNEL_7
02103   * @retval None
02104   */
02105 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02106 {
02107   uint32_t dma_base_addr = (uint32_t)DMAx;
02108   SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
02109 }
02110
02111 /**
02112   * @brief  Disable Transfer complete interrupt.
02113   * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
02114   * @param  DMAx DMAx Instance
02115   * @param  Channel This parameter can be one of the following values:
02116   *         @arg @ref LL_DMA_CHANNEL_1
02117   *         @arg @ref LL_DMA_CHANNEL_2
02118   *         @arg @ref LL_DMA_CHANNEL_3
02119   *         @arg @ref LL_DMA_CHANNEL_4
02120   *         @arg @ref LL_DMA_CHANNEL_5
02121   *         @arg @ref LL_DMA_CHANNEL_6
02122   *         @arg @ref LL_DMA_CHANNEL_7
02123   * @retval None
02124   */
02125 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02126 {
02127   uint32_t dma_base_addr = (uint32_t)DMAx;
02128   CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
02129 }
02130
02131 /**
02132   * @brief  Disable Half transfer interrupt.
02133   * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
02134   * @param  DMAx DMAx Instance
02135   * @param  Channel This parameter can be one of the following values:
02136   *         @arg @ref LL_DMA_CHANNEL_1
02137   *         @arg @ref LL_DMA_CHANNEL_2
02138   *         @arg @ref LL_DMA_CHANNEL_3
02139   *         @arg @ref LL_DMA_CHANNEL_4
02140   *         @arg @ref LL_DMA_CHANNEL_5
02141   *         @arg @ref LL_DMA_CHANNEL_6
02142   *         @arg @ref LL_DMA_CHANNEL_7
02143   * @retval None
02144   */
02145 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02146 {
02147   uint32_t dma_base_addr = (uint32_t)DMAx;
02148   CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
02149 }
02150
02151 /**
02152   * @brief  Disable Transfer error interrupt.
02153   * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
02154   * @param  DMAx DMAx Instance
02155   * @param  Channel This parameter can be one of the following values:
02156   *         @arg @ref LL_DMA_CHANNEL_1
02157   *         @arg @ref LL_DMA_CHANNEL_2
02158   *         @arg @ref LL_DMA_CHANNEL_3
02159   *         @arg @ref LL_DMA_CHANNEL_4
02160   *         @arg @ref LL_DMA_CHANNEL_5
02161   *         @arg @ref LL_DMA_CHANNEL_6
02162   *         @arg @ref LL_DMA_CHANNEL_7
02163   * @retval None
02164   */
02165 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02166 {
02167   uint32_t dma_base_addr = (uint32_t)DMAx;
02168   CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
02169 }
02170
02171 /**
02172   * @brief  Check if Transfer complete Interrupt is enabled.
02173   * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
02174   * @param  DMAx DMAx Instance
02175   * @param  Channel This parameter can be one of the following values:
02176   *         @arg @ref LL_DMA_CHANNEL_1
02177   *         @arg @ref LL_DMA_CHANNEL_2
02178   *         @arg @ref LL_DMA_CHANNEL_3
02179   *         @arg @ref LL_DMA_CHANNEL_4
02180   *         @arg @ref LL_DMA_CHANNEL_5
02181   *         @arg @ref LL_DMA_CHANNEL_6
02182   *         @arg @ref LL_DMA_CHANNEL_7
02183   * @retval State of bit (1 or 0).
02184   */
02185 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02186 {
02187   uint32_t dma_base_addr = (uint32_t)DMAx;
02188   return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
02189                     DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
02190 }
02191
02192 /**
02193   * @brief  Check if Half transfer Interrupt is enabled.
02194   * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
02195   * @param  DMAx DMAx Instance
02196   * @param  Channel This parameter can be one of the following values:
02197   *         @arg @ref LL_DMA_CHANNEL_1
02198   *         @arg @ref LL_DMA_CHANNEL_2
02199   *         @arg @ref LL_DMA_CHANNEL_3
02200   *         @arg @ref LL_DMA_CHANNEL_4
02201   *         @arg @ref LL_DMA_CHANNEL_5
02202   *         @arg @ref LL_DMA_CHANNEL_6
02203   *         @arg @ref LL_DMA_CHANNEL_7
02204   * @retval State of bit (1 or 0).
02205   */
02206 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02207 {
02208   uint32_t dma_base_addr = (uint32_t)DMAx;
02209   return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
02210                     DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
02211 }
02212
02213 /**
02214   * @brief  Check if Transfer error Interrupt is enabled.
02215   * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
02216   * @param  DMAx DMAx Instance
02217   * @param  Channel This parameter can be one of the following values:
02218   *         @arg @ref LL_DMA_CHANNEL_1
02219   *         @arg @ref LL_DMA_CHANNEL_2
02220   *         @arg @ref LL_DMA_CHANNEL_3
02221   *         @arg @ref LL_DMA_CHANNEL_4
02222   *         @arg @ref LL_DMA_CHANNEL_5
02223   *         @arg @ref LL_DMA_CHANNEL_6
02224   *         @arg @ref LL_DMA_CHANNEL_7
02225   * @retval State of bit (1 or 0).
02226   */
02227 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02228 {
02229   uint32_t dma_base_addr = (uint32_t)DMAx;
02230   return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
02231                     DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
02232 }
02233
02234 /**
02235   * @}
02236   */
02237
02238 #if defined(USE_FULL_LL_DRIVER)
02239 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
02240   * @{
02241   */
02242 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
02243 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
02244 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
02245
02246 /**
02247   * @}
02248   */
02249 #endif /* USE_FULL_LL_DRIVER */
02250
02251 /**
02252   * @}
02253   */
02254
02255 /**
02256   * @}
02257   */
02258
02259 #endif /* DMA1 || DMA2 */
02260
02261 /**
02262   * @}
02263   */
02264
02265 #ifdef __cplusplus
02266 }
02267 #endif
02268
02269 #endif /* STM32G0xx_LL_DMA_H */
02270
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_dmamux.h Source File

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stm32g0xx_ll_dmamux.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_dmamux.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMAMUX LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_DMAMUX_H
00021 #define STM32G0xx_LL_DMAMUX_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (DMAMUX1)
00035
00036 /** @defgroup DMAMUX_LL DMAMUX
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
00044   * @{
00045   */
00046 /* Define used to get DMAMUX CCR register size */
00047 #define DMAMUX_CCR_SIZE                   0x00000004UL
00048
00049 /* Define used to get DMAMUX RGCR register size */
00050 #define DMAMUX_RGCR_SIZE                  0x00000004UL
00051 /**
00052   * @}
00053   */
00054
00055 /* Private macros ------------------------------------------------------------*/
00056 /* Exported types ------------------------------------------------------------*/
00057 /* Exported constants --------------------------------------------------------*/
00058 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
00059   * @{
00060   */
00061 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
00062   * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
00063   * @{
00064   */
00065 #define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
00066 #define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
00067 #define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
00068 #define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
00069 #define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
00070 #if defined(DMAMUX1_Channel5)
00071 #define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
00072 #endif /* DMAMUX1_Channel5 */
00073 #if defined(DMAMUX1_Channel6)
00074 #define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
00075 #endif /* DMAMUX1_Channel6 */
00076 #if defined(DMA2)
00077 #define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
00078 #define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
00079 #define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
00080 #define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
00081 #define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
00082 #endif /* DMA2 */
00083 #define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
00084 #define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
00085 #define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
00086 #define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
00087 /**
00088   * @}
00089   */
00090
00091 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
00092   * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
00093   * @{
00094   */
00095 #define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
00096 #define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
00097 #define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
00098 #define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
00099 #define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
00100 #if defined(DMAMUX1_Channel5)
00101 #define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
00102 #endif /* DMAMUX1_Channel5 */
00103 #if defined(DMAMUX1_Channel6)
00104 #define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
00105 #endif /* DMAMUX1_Channel6 */
00106 #if defined(DMA2)
00107 #define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
00108 #define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
00109 #define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
00110 #define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
00111 #define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
00112 #endif /* DMA2 */
00113 #define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
00114 #define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
00115 #define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
00116 #define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup DMAMUX_LL_EC_IT IT Defines
00122   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
00123   * @{
00124   */
00125 #define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt */
00126 #define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
00132   * @{
00133   */
00134 #define LL_DMAMUX_REQ_MEM2MEM             0x00000000U  /*!< memory to memory transfer  */
00135 #define LL_DMAMUX_REQ_GENERATOR0          0x00000001U  /*!< DMAMUX request generator 0 */
00136 #define LL_DMAMUX_REQ_GENERATOR1          0x00000002U  /*!< DMAMUX request generator 1 */
00137 #define LL_DMAMUX_REQ_GENERATOR2          0x00000003U  /*!< DMAMUX request generator 2 */
00138 #define LL_DMAMUX_REQ_GENERATOR3          0x00000004U  /*!< DMAMUX request generator 3 */
00139 #define LL_DMAMUX_REQ_ADC1                0x00000005U  /*!< DMAMUX ADC1 request        */
00140 #if defined(AES)
00141 #define LL_DMAMUX_REQ_AES_IN              0x00000006U  /*!< DMAMUX AES_IN request      */
00142 #define LL_DMAMUX_REQ_AES_OUT             0x00000007U  /*!< DMAMUX AES_OUT request     */
00143 #endif /* AES */
00144 #if defined(DAC1)
00145 #define LL_DMAMUX_REQ_DAC1_CH1            0x00000008U  /*!< DMAMUX DAC_CH1 request     */
00146 #define LL_DMAMUX_REQ_DAC1_CH2            0x00000009U  /*!< DMAMUX DAC_CH2 request     */
00147 #endif /* DAC1 */
00148 #define LL_DMAMUX_REQ_I2C1_RX             0x0000000AU  /*!< DMAMUX I2C1 RX request     */
00149 #define LL_DMAMUX_REQ_I2C1_TX             0x0000000BU  /*!< DMAMUX I2C1 TX request     */
00150 #define LL_DMAMUX_REQ_I2C2_RX             0x0000000CU  /*!< DMAMUX I2C2 RX request     */
00151 #define LL_DMAMUX_REQ_I2C2_TX             0x0000000DU  /*!< DMAMUX I2C2 TX request     */
00152 #if defined(LPUART1)
00153 #define LL_DMAMUX_REQ_LPUART1_RX          0x0000000EU  /*!< DMAMUX LPUART1 RX request  */
00154 #define LL_DMAMUX_REQ_LPUART1_TX          0x0000000FU  /*!< DMAMUX LPUART1 TX request  */
00155 #endif /* LPUART1 */
00156 #define LL_DMAMUX_REQ_SPI1_RX             0x00000010U  /*!< DMAMUX SPI1 RX request     */
00157 #define LL_DMAMUX_REQ_SPI1_TX             0x00000011U  /*!< DMAMUX SPI1 TX request     */
00158 #define LL_DMAMUX_REQ_SPI2_RX             0x00000012U  /*!< DMAMUX SPI2 RX request     */
00159 #define LL_DMAMUX_REQ_SPI2_TX             0x00000013U  /*!< DMAMUX SPI2 TX request     */
00160 #define LL_DMAMUX_REQ_TIM1_CH1            0x00000014U  /*!< DMAMUX TIM1 CH1 request    */
00161 #define LL_DMAMUX_REQ_TIM1_CH2            0x00000015U  /*!< DMAMUX TIM1 CH2 request    */
00162 #define LL_DMAMUX_REQ_TIM1_CH3            0x00000016U  /*!< DMAMUX TIM1 CH3 request    */
00163 #define LL_DMAMUX_REQ_TIM1_CH4            0x00000017U  /*!< DMAMUX TIM1 CH4 request    */
00164 #define LL_DMAMUX_REQ_TIM1_TRIG_COM       0x00000018U  /*!< DMAMUX TIM1 TRIG COM request */
00165 #define LL_DMAMUX_REQ_TIM1_UP             0x00000019U  /*!< DMAMUX TIM1 UP request     */
00166 #if defined(TIM2)
00167 #define LL_DMAMUX_REQ_TIM2_CH1            0x0000001AU  /*!< DMAMUX TIM2 CH1 request    */
00168 #define LL_DMAMUX_REQ_TIM2_CH2            0x0000001BU  /*!< DMAMUX TIM2 CH2 request    */
00169 #define LL_DMAMUX_REQ_TIM2_CH3            0x0000001CU  /*!< DMAMUX TIM2 CH3 request    */
00170 #define LL_DMAMUX_REQ_TIM2_CH4            0x0000001DU  /*!< DMAMUX TIM2 CH4 request    */
00171 #define LL_DMAMUX_REQ_TIM2_TRIG           0x0000001EU  /*!< DMAMUX TIM2 TRIG request   */
00172 #define LL_DMAMUX_REQ_TIM2_UP             0x0000001FU  /*!< DMAMUX TIM2 UP request     */
00173 #endif /* TIM2 */
00174 #define LL_DMAMUX_REQ_TIM3_CH1            0x00000020U  /*!< DMAMUX TIM3 CH1 request    */
00175 #define LL_DMAMUX_REQ_TIM3_CH2            0x00000021U  /*!< DMAMUX TIM3 CH2 request    */
00176 #define LL_DMAMUX_REQ_TIM3_CH3            0x00000022U  /*!< DMAMUX TIM3 CH3 request    */
00177 #define LL_DMAMUX_REQ_TIM3_CH4            0x00000023U  /*!< DMAMUX TIM3 CH4 request    */
00178 #define LL_DMAMUX_REQ_TIM3_TRIG           0x00000024U  /*!< DMAMUX TIM3 TRIG request   */
00179 #define LL_DMAMUX_REQ_TIM3_UP             0x00000025U  /*!< DMAMUX TIM3 UP request     */
00180 #if defined(TIM6)
00181 #define LL_DMAMUX_REQ_TIM6_UP             0x00000026U  /*!< DMAMUX TIM6 UP request     */
00182 #endif /* TIM6 */
00183 #if defined(TIM7)
00184 #define LL_DMAMUX_REQ_TIM7_UP             0x00000027U  /*!< DMAMUX TIM7 UP request     */
00185 #endif /* TIM7 */
00186 #if defined(TIM15)
00187 #define LL_DMAMUX_REQ_TIM15_CH1           0x00000028U  /*!< DMAMUX TIM15 CH1 request   */
00188 #define LL_DMAMUX_REQ_TIM15_CH2           0x00000029U  /*!< DMAMUX TIM15 CH2 request   */
00189 #define LL_DMAMUX_REQ_TIM15_TRIG_COM      0x0000002AU  /*!< DMAMUX TIM15 TRIG COM request */
00190 #define LL_DMAMUX_REQ_TIM15_UP            0x0000002BU  /*!< DMAMUX TIM15 UP request    */
00191 #endif /* TIM15 */
00192 #define LL_DMAMUX_REQ_TIM16_CH1           0x0000002CU  /*!< DMAMUX TIM16 CH1 request   */
00193 #define LL_DMAMUX_REQ_TIM16_COM           0x0000002DU  /*!< DMAMUX TIM16 COM request   */
00194 #define LL_DMAMUX_REQ_TIM16_UP            0x0000002EU  /*!< DMAMUX TIM16 UP request    */
00195 #define LL_DMAMUX_REQ_TIM17_CH1           0x0000002FU  /*!< DMAMUX TIM17 CH1 request   */
00196 #define LL_DMAMUX_REQ_TIM17_COM           0x00000030U  /*!< DMAMUX TIM17 COM request   */
00197 #define LL_DMAMUX_REQ_TIM17_UP            0x00000031U  /*!< DMAMUX TIM17 UP request    */
00198 #define LL_DMAMUX_REQ_USART1_RX           0x00000032U  /*!< DMAMUX USART1 RX request  */
00199 #define LL_DMAMUX_REQ_USART1_TX           0x00000033U  /*!< DMAMUX USART1 TX request  */
00200 #define LL_DMAMUX_REQ_USART2_RX           0x00000034U  /*!< DMAMUX USART2 RX request  */
00201 #define LL_DMAMUX_REQ_USART2_TX           0x00000035U  /*!< DMAMUX USART2 TX request  */
00202 #if defined(USART3)
00203 #define LL_DMAMUX_REQ_USART3_RX           0x00000036U  /*!< DMAMUX USART3 RX request  */
00204 #define LL_DMAMUX_REQ_USART3_TX           0x00000037U  /*!< DMAMUX USART3 TX request  */
00205 #endif /* USART3 */
00206 #if defined(USART4)
00207 #define LL_DMAMUX_REQ_USART4_RX           0x00000038U  /*!< DMAMUX USART4 RX request  */
00208 #define LL_DMAMUX_REQ_USART4_TX           0x00000039U  /*!< DMAMUX USART4 TX request  */
00209 #endif /* USART4 */
00210 #if defined(UCPD1)
00211 #define LL_DMAMUX_REQ_UCPD1_RX            0x0000003AU  /*!< DMAMUX UCPD1 RX request  */
00212 #define LL_DMAMUX_REQ_UCPD1_TX            0x0000003BU  /*!< DMAMUX UCPD1 TX request  */
00213 #endif /* UCPD1 */
00214 #if defined(UCPD2)
00215 #define LL_DMAMUX_REQ_UCPD2_RX            0x0000003CU  /*!< DMAMUX UCPD2 RX request  */
00216 #define LL_DMAMUX_REQ_UCPD2_TX            0x0000003DU  /*!< DMAMUX UCPD2 TX request  */
00217 #endif /* UCPD2 */
00218
00219 #if defined(I2C3)
00220 #define LL_DMAMUX_REQ_I2C3_RX             0x0000003EU  /*!< DMAMUX I2C3 RX request  */
00221 #define LL_DMAMUX_REQ_I2C3_TX             0x0000003FU  /*!< DMAMUX I2C3 TX request  */
00222 #endif /* I2C3 */
00223
00224 #if defined(LPUART2)
00225 #define LL_DMAMUX_REQ_LPUART2_RX          0x00000040U  /*!< DMAMUX LPUART2 RX request  */
00226 #define LL_DMAMUX_REQ_LPUART2_TX          0x00000041U  /*!< DMAMUX LPUART2 TX request  */
00227 #endif /* LPUART2 */
00228
00229 #if defined(SPI3)
00230 #define LL_DMAMUX_REQ_SPI3_RX             0x00000042U  /*!< DMAMUX SPI3 RX request     */
00231 #define LL_DMAMUX_REQ_SPI3_TX             0x00000043U  /*!< DMAMUX SPI3 TX request     */
00232 #endif /* SPI3 */
00233
00234 #if defined(TIM4)
00235 #define LL_DMAMUX_REQ_TIM4_CH1            0x00000044U  /*!< DMAMUX TIM4 CH1 request    */
00236 #define LL_DMAMUX_REQ_TIM4_CH2            0x00000045U  /*!< DMAMUX TIM4 CH2 request    */
00237 #define LL_DMAMUX_REQ_TIM4_CH3            0x00000046U  /*!< DMAMUX TIM4 CH3 request    */
00238 #define LL_DMAMUX_REQ_TIM4_CH4            0x00000047U  /*!< DMAMUX TIM4 CH4 request    */
00239 #define LL_DMAMUX_REQ_TIM4_TRIG           0x00000048U  /*!< DMAMUX TIM4 TRIG request   */
00240 #define LL_DMAMUX_REQ_TIM4_UP             0x00000049U  /*!< DMAMUX TIM4 UP request     */
00241 #endif /* TIM4 */
00242
00243 #if defined(USART5)
00244 #define LL_DMAMUX_REQ_USART5_RX           0x0000004AU  /*!< DMAMUX USART5 RX request  */
00245 #define LL_DMAMUX_REQ_USART5_TX           0x0000004BU  /*!< DMAMUX USART5 TX request  */
00246 #endif /* USART5 */
00247
00248 #if defined(USART6)
00249 #define LL_DMAMUX_REQ_USART6_RX           0x0000004CU  /*!< DMAMUX USART6 RX request  */
00250 #define LL_DMAMUX_REQ_USART6_TX           0x0000004DU  /*!< DMAMUX USART6 TX request  */
00251 #endif /* USART6 */
00252
00253 #if defined(STM32G0C1xx)||defined(STM32G0B1xx)
00254 #define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_USART6_TX
00255 #elif defined(STM32G0B0xx)
00256 #define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_USART4_TX
00257 #elif defined(STM32G081xx)||defined(STM32G071xx)
00258 #define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_UCPD2_TX
00259 #elif defined(STM32G070xx)
00260 #define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_USART4_TX
00261 #else
00262 #define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_USART2_TX
00263 #endif /* STM32G0C1xx || STM32G0B1xx */
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
00269   * @{
00270   */
00271 #define LL_DMAMUX_CHANNEL_0               0x00000000U               /*!< DMAMUX Channel 0 connected to DMA1 Channel 1  */
00272 #define LL_DMAMUX_CHANNEL_1               0x00000001U               /*!< DMAMUX Channel 1 connected to DMA1 Channel 2  */
00273 #define LL_DMAMUX_CHANNEL_2               0x00000002U               /*!< DMAMUX Channel 2 connected to DMA1 Channel 3  */
00274 #define LL_DMAMUX_CHANNEL_3               0x00000003U               /*!< DMAMUX Channel 3 connected to DMA1 Channel 4  */
00275 #define LL_DMAMUX_CHANNEL_4               0x00000004U               /*!< DMAMUX Channel 4 connected to DMA1 Channel 5  */
00276 #if defined(DMAMUX1_Channel5)
00277 #define LL_DMAMUX_CHANNEL_5               0x00000005U               /*!< DMAMUX Channel 5 connected to DMA1 Channel 6  */
00278 #endif /* DMAMUX1_Channel5 */
00279 #if defined(DMAMUX1_Channel6)
00280 #define LL_DMAMUX_CHANNEL_6               0x00000006U               /*!< DMAMUX Channel 6 connected to DMA1 Channel 7  */
00281 #endif /* DMAMUX1_Channel6 */
00282 #if defined(DMA2)
00283 #define LL_DMAMUX_CHANNEL_7               0x00000007U               /*!< DMAMUX Channel 7 connected to DMA2 Channel 1  */
00284 #define LL_DMAMUX_CHANNEL_8               0x00000008U               /*!< DMAMUX Channel 8 connected to DMA2 Channel 2  */
00285 #define LL_DMAMUX_CHANNEL_9               0x00000009U               /*!< DMAMUX Channel 9 connected to DMA2 Channel 3  */
00286 #define LL_DMAMUX_CHANNEL_10              0x0000000AU               /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */
00287 #define LL_DMAMUX_CHANNEL_11              0x0000000BU               /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */
00288 #endif /* DMA2 */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
00294   * @{
00295   */
00296 #define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked   */
00297 #define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge */
00298 #define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge */
00299 #define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
00305   * @{
00306   */
00307 #define LL_DMAMUX_SYNC_EXTI_LINE0         0x00000000U                                                                                     /*!< Synchronization signal from EXTI Line0  */
00308 #define LL_DMAMUX_SYNC_EXTI_LINE1         DMAMUX_CxCR_SYNC_ID_0                                                                           /*!< Synchronization signal from EXTI Line1  */
00309 #define LL_DMAMUX_SYNC_EXTI_LINE2         DMAMUX_CxCR_SYNC_ID_1                                                                           /*!< Synchronization signal from EXTI Line2  */
00310 #define LL_DMAMUX_SYNC_EXTI_LINE3         (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line3  */
00311 #define LL_DMAMUX_SYNC_EXTI_LINE4         DMAMUX_CxCR_SYNC_ID_2                                                                           /*!< Synchronization signal from EXTI Line4  */
00312 #define LL_DMAMUX_SYNC_EXTI_LINE5         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line5  */
00313 #define LL_DMAMUX_SYNC_EXTI_LINE6         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line6  */
00314 #define LL_DMAMUX_SYNC_EXTI_LINE7         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line7  */
00315 #define LL_DMAMUX_SYNC_EXTI_LINE8         DMAMUX_CxCR_SYNC_ID_3                                                                           /*!< Synchronization signal from EXTI Line8  */
00316 #define LL_DMAMUX_SYNC_EXTI_LINE9         (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line9  */
00317 #define LL_DMAMUX_SYNC_EXTI_LINE10        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line10  */
00318 #define LL_DMAMUX_SYNC_EXTI_LINE11        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line11  */
00319 #define LL_DMAMUX_SYNC_EXTI_LINE12        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from EXTI Line12  */
00320 #define LL_DMAMUX_SYNC_EXTI_LINE13        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line1 3 */
00321 #define LL_DMAMUX_SYNC_EXTI_LINE14        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                         /*!< Synchronization signal from EXTI Line1 4 */
00322 #define LL_DMAMUX_SYNC_EXTI_LINE15        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 5 */
00323 #define LL_DMAMUX_SYNC_DMAMUX_CH0         DMAMUX_CxCR_SYNC_ID_4                                                                           /*!< Synchronization signal from DMAMUX channel0 Event */
00324 #define LL_DMAMUX_SYNC_DMAMUX_CH1         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from DMAMUX channel1 Event */
00325 #define LL_DMAMUX_SYNC_DMAMUX_CH2         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from DMAMUX channel2 Event */
00326 #define LL_DMAMUX_SYNC_DMAMUX_CH3         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from DMAMUX channel3 Event */
00327 #if defined(LPTIM1)
00328 #define LL_DMAMUX_SYNC_LPTIM1_OUT         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from LPTIM1 Output */
00329 #endif /* LPTIM1 */
00330 #if defined(LPTIM2)
00331 #define LL_DMAMUX_SYNC_LPTIM2_OUT         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from LPTIM2 Output */
00332 #endif /* LPTIM2 */
00333 #define LL_DMAMUX_SYNC_TIM14_OC           (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                         /*!< Synchronization signal from TIM14 OC */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
00339   * @{
00340   */
00341 #define LL_DMAMUX_REQ_GEN_0               0x00000000U
00342 #define LL_DMAMUX_REQ_GEN_1               0x00000001U
00343 #define LL_DMAMUX_REQ_GEN_2               0x00000002U
00344 #define LL_DMAMUX_REQ_GEN_3               0x00000003U
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
00350   * @{
00351   */
00352 #define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation */
00353 #define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge */
00354 #define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge */
00355 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
00361   * @{
00362   */
00363 #define LL_DMAMUX_REQ_GEN_EXTI_LINE0      0x00000000U                                                                                     /*!< Request signal generation from EXTI Line0  */
00364 #define LL_DMAMUX_REQ_GEN_EXTI_LINE1      DMAMUX_RGxCR_SIG_ID_0                                                                           /*!< Request signal generation from EXTI Line1  */
00365 #define LL_DMAMUX_REQ_GEN_EXTI_LINE2      DMAMUX_RGxCR_SIG_ID_1                                                                           /*!< Request signal generation from EXTI Line2  */
00366 #define LL_DMAMUX_REQ_GEN_EXTI_LINE3      (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)                                                  /*!< Request signal generation from EXTI Line3  */
00367 #define LL_DMAMUX_REQ_GEN_EXTI_LINE4      DMAMUX_RGxCR_SIG_ID_2                                                                           /*!< Request signal generation from EXTI Line4  */
00368 #define LL_DMAMUX_REQ_GEN_EXTI_LINE5      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line5  */
00369 #define LL_DMAMUX_REQ_GEN_EXTI_LINE6      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line6  */
00370 #define LL_DMAMUX_REQ_GEN_EXTI_LINE7      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line7  */
00371 #define LL_DMAMUX_REQ_GEN_EXTI_LINE8      DMAMUX_RGxCR_SIG_ID_3                                                                           /*!< Request signal generation from EXTI Line8  */
00372 #define LL_DMAMUX_REQ_GEN_EXTI_LINE9      (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line9  */
00373 #define LL_DMAMUX_REQ_GEN_EXTI_LINE10     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line10 */
00374 #define LL_DMAMUX_REQ_GEN_EXTI_LINE11     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line11 */
00375 #define LL_DMAMUX_REQ_GEN_EXTI_LINE12     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from EXTI Line12 */
00376 #define LL_DMAMUX_REQ_GEN_EXTI_LINE13     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line13 */
00377 #define LL_DMAMUX_REQ_GEN_EXTI_LINE14     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                         /*!< Request signal generation from EXTI Line14 */
00378 #define LL_DMAMUX_REQ_GEN_EXTI_LINE15     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
00379 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH0      DMAMUX_RGxCR_SIG_ID_4                                                                           /*!< Request signal generation from DMAMUX channel0 Event */
00380 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH1      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from DMAMUX channel1 Event */
00381 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH2      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from DMAMUX channel2 Event */
00382 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH3      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from DMAMUX channel3 Event */
00383 #if defined(LPTIM1)
00384 #define LL_DMAMUX_REQ_GEN_LPTIM1_OUT      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from LPTIM1 Output */
00385 #endif /* LPTIM1 */
00386 #if defined(LPTIM2)
00387 #define LL_DMAMUX_REQ_GEN_LPTIM2_OUT      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from LPTIM2 Output */
00388 #endif /* LPTIM2 */
00389 #define LL_DMAMUX_REQ_GEN_TIM14_OC        (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                         /*!< Request signal generation from TIM14 OC */
00390 /**
00391   * @}
00392   */
00393
00394 /**
00395   * @}
00396   */
00397
00398 /* Exported macro ------------------------------------------------------------*/
00399 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
00400   * @{
00401   */
00402
00403 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
00404   * @{
00405   */
00406 /**
00407   * @brief  Write a value in DMAMUX register
00408   * @param  __INSTANCE__ DMAMUX Instance
00409   * @param  __REG__ Register to be written
00410   * @param  __VALUE__ Value to be written in the register
00411   * @retval None
00412   */
00413 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00414
00415 /**
00416   * @brief  Read a value in DMAMUX register
00417   * @param  __INSTANCE__ DMAMUX Instance
00418   * @param  __REG__ Register to be read
00419   * @retval Register value
00420   */
00421 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00422 /**
00423   * @}
00424   */
00425
00426 /**
00427   * @}
00428   */
00429
00430 /* Exported functions --------------------------------------------------------*/
00431 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
00432   * @{
00433   */
00434
00435 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
00436   * @{
00437   */
00438 /**
00439   * @brief  Set DMAMUX request ID for DMAMUX Channel x.
00440   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00441   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00442   * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
00443   * @param  DMAMUXx DMAMUXx Instance
00444   * @param  Channel This parameter can be one of the following values:
00445   *         @arg @ref LL_DMAMUX_CHANNEL_0
00446   *         @arg @ref LL_DMAMUX_CHANNEL_1
00447   *         @arg @ref LL_DMAMUX_CHANNEL_2
00448   *         @arg @ref LL_DMAMUX_CHANNEL_3
00449   *         @arg @ref LL_DMAMUX_CHANNEL_4
00450   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00451   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00452   *
00453   *         @arg All the next values are only available on chip which support DMA2:
00454   *         @arg @ref LL_DMAMUX_CHANNEL_7
00455   *         @arg @ref LL_DMAMUX_CHANNEL_8
00456   *         @arg @ref LL_DMAMUX_CHANNEL_9
00457   *         @arg @ref LL_DMAMUX_CHANNEL_10
00458   *         @arg @ref LL_DMAMUX_CHANNEL_11
00459   * @param  Request This parameter can be one of the following values:
00460   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
00461   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
00462   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
00463   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
00464   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
00465   *         @arg @ref LL_DMAMUX_REQ_ADC1
00466   *         @arg @ref LL_DMAMUX_REQ_AES_IN
00467   *         @arg @ref LL_DMAMUX_REQ_AES_OUT
00468   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
00469   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
00470   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
00471   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
00472   *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
00473   *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
00474   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
00475   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
00476   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
00477   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
00478   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
00479   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
00480   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
00481   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
00482   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
00483   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
00484   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
00485   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
00486   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
00487   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
00488   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
00489   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
00490   *         @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
00491   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
00492   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
00493   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
00494   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
00495   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
00496   *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
00497   *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
00498   *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
00499   *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
00500   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
00501   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH2
00502   *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
00503   *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
00504   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
00505   *         @arg @ref LL_DMAMUX_REQ_TIM16_COM
00506   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
00507   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
00508   *         @arg @ref LL_DMAMUX_REQ_TIM17_COM
00509   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
00510   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
00511   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
00512   *         @arg @ref LL_DMAMUX_REQ_USART2_RX
00513   *         @arg @ref LL_DMAMUX_REQ_USART2_TX
00514   *         @arg @ref LL_DMAMUX_REQ_USART3_RX
00515   *         @arg @ref LL_DMAMUX_REQ_USART3_TX
00516   *         @arg @ref LL_DMAMUX_REQ_USART4_RX
00517   *         @arg @ref LL_DMAMUX_REQ_USART4_TX
00518   *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
00519   *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
00520   *         @arg @ref LL_DMAMUX_REQ_UCPD2_RX
00521   *         @arg @ref LL_DMAMUX_REQ_UCPD2_TX
00522   * @retval None
00523   */
00524 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
00525 {
00526   (void)(DMAMUXx);
00527   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
00528 }
00529
00530 /**
00531   * @brief  Get DMAMUX request ID for DMAMUX Channel x.
00532   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00533   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00534   * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
00535   * @param  DMAMUXx DMAMUXx Instance
00536   * @param  Channel This parameter can be one of the following values:
00537   *         @arg @ref LL_DMAMUX_CHANNEL_0
00538   *         @arg @ref LL_DMAMUX_CHANNEL_1
00539   *         @arg @ref LL_DMAMUX_CHANNEL_2
00540   *         @arg @ref LL_DMAMUX_CHANNEL_3
00541   *         @arg @ref LL_DMAMUX_CHANNEL_4
00542   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00543   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00544   *
00545   *         @arg All the next values are only available on chip which support DMA2:
00546   *         @arg @ref LL_DMAMUX_CHANNEL_7
00547   *         @arg @ref LL_DMAMUX_CHANNEL_8
00548   *         @arg @ref LL_DMAMUX_CHANNEL_9
00549   *         @arg @ref LL_DMAMUX_CHANNEL_10
00550   *         @arg @ref LL_DMAMUX_CHANNEL_11
00551   * @retval Returned value can be one of the following values:
00552   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
00553   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
00554   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
00555   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
00556   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
00557   *         @arg @ref LL_DMAMUX_REQ_ADC1
00558   *         @arg @ref LL_DMAMUX_REQ_AES_IN
00559   *         @arg @ref LL_DMAMUX_REQ_AES_OUT
00560   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
00561   *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
00562   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
00563   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
00564   *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
00565   *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
00566   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
00567   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
00568   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
00569   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
00570   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
00571   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
00572   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
00573   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
00574   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
00575   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
00576   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
00577   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
00578   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
00579   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
00580   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
00581   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
00582   *         @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
00583   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
00584   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
00585   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
00586   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
00587   *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
00588   *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
00589   *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
00590   *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
00591   *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
00592   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
00593   *         @arg @ref LL_DMAMUX_REQ_TIM15_CH2
00594   *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
00595   *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
00596   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
00597   *         @arg @ref LL_DMAMUX_REQ_TIM16_COM
00598   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
00599   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
00600   *         @arg @ref LL_DMAMUX_REQ_TIM17_COM
00601   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
00602   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
00603   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
00604   *         @arg @ref LL_DMAMUX_REQ_USART2_RX
00605   *         @arg @ref LL_DMAMUX_REQ_USART2_TX
00606   *         @arg @ref LL_DMAMUX_REQ_USART3_RX
00607   *         @arg @ref LL_DMAMUX_REQ_USART3_TX
00608   *         @arg @ref LL_DMAMUX_REQ_USART4_RX
00609   *         @arg @ref LL_DMAMUX_REQ_USART4_TX
00610   *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
00611   *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
00612   *         @arg @ref LL_DMAMUX_REQ_UCPD2_RX
00613   *         @arg @ref LL_DMAMUX_REQ_UCPD2_TX
00614   */
00615 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00616 {
00617   (void)(DMAMUXx);
00618   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
00619 }
00620
00621 /**
00622   * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
00623   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00624   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00625   * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
00626   * @param  DMAMUXx DMAMUXx Instance
00627   * @param  Channel This parameter can be one of the following values:
00628   *         @arg @ref LL_DMAMUX_CHANNEL_0
00629   *         @arg @ref LL_DMAMUX_CHANNEL_1
00630   *         @arg @ref LL_DMAMUX_CHANNEL_2
00631   *         @arg @ref LL_DMAMUX_CHANNEL_3
00632   *         @arg @ref LL_DMAMUX_CHANNEL_4
00633   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00634   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00635   *
00636   *         @arg All the next values are only available on chip which support DMA2:
00637   *         @arg @ref LL_DMAMUX_CHANNEL_7
00638   *         @arg @ref LL_DMAMUX_CHANNEL_8
00639   *         @arg @ref LL_DMAMUX_CHANNEL_9
00640   *         @arg @ref LL_DMAMUX_CHANNEL_10
00641   *         @arg @ref LL_DMAMUX_CHANNEL_11
00642   * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
00643   * @retval None
00644   */
00645 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
00646 {
00647   (void)(DMAMUXx);
00648   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
00649 }
00650
00651 /**
00652   * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
00653   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00654   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00655   * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
00656   * @param  DMAMUXx DMAMUXx Instance
00657   * @param  Channel This parameter can be one of the following values:
00658   *         @arg @ref LL_DMAMUX_CHANNEL_0
00659   *         @arg @ref LL_DMAMUX_CHANNEL_1
00660   *         @arg @ref LL_DMAMUX_CHANNEL_2
00661   *         @arg @ref LL_DMAMUX_CHANNEL_3
00662   *         @arg @ref LL_DMAMUX_CHANNEL_4
00663   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00664   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00665   *
00666   *         @arg All the next values are only available on chip which support DMA2:
00667   *         @arg @ref LL_DMAMUX_CHANNEL_7
00668   *         @arg @ref LL_DMAMUX_CHANNEL_8
00669   *         @arg @ref LL_DMAMUX_CHANNEL_9
00670   *         @arg @ref LL_DMAMUX_CHANNEL_10
00671   *         @arg @ref LL_DMAMUX_CHANNEL_11
00672   * @retval Between Min_Data = 1 and Max_Data = 32
00673   */
00674 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00675 {
00676   (void)(DMAMUXx);
00677   return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
00678 }
00679
00680 /**
00681   * @brief  Set the polarity of the signal on which the DMA request is synchronized.
00682   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00683   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00684   * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
00685   * @param  DMAMUXx DMAMUXx Instance
00686   * @param  Channel This parameter can be one of the following values:
00687   *         @arg @ref LL_DMAMUX_CHANNEL_0
00688   *         @arg @ref LL_DMAMUX_CHANNEL_1
00689   *         @arg @ref LL_DMAMUX_CHANNEL_2
00690   *         @arg @ref LL_DMAMUX_CHANNEL_3
00691   *         @arg @ref LL_DMAMUX_CHANNEL_4
00692   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00693   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00694   *
00695   *         @arg All the next values are only available on chip which support DMA2:
00696   *         @arg @ref LL_DMAMUX_CHANNEL_7
00697   *         @arg @ref LL_DMAMUX_CHANNEL_8
00698   *         @arg @ref LL_DMAMUX_CHANNEL_9
00699   *         @arg @ref LL_DMAMUX_CHANNEL_10
00700   *         @arg @ref LL_DMAMUX_CHANNEL_11
00701   * @param  Polarity This parameter can be one of the following values:
00702   *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
00703   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
00704   *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
00705   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
00706   * @retval None
00707   */
00708 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
00709 {
00710   (void)(DMAMUXx);
00711   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
00712 }
00713
00714 /**
00715   * @brief  Get the polarity of the signal on which the DMA request is synchronized.
00716   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00717   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00718   * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
00719   * @param  DMAMUXx DMAMUXx Instance
00720   * @param  Channel This parameter can be one of the following values:
00721   *         @arg @ref LL_DMAMUX_CHANNEL_0
00722   *         @arg @ref LL_DMAMUX_CHANNEL_1
00723   *         @arg @ref LL_DMAMUX_CHANNEL_2
00724   *         @arg @ref LL_DMAMUX_CHANNEL_3
00725   *         @arg @ref LL_DMAMUX_CHANNEL_4
00726   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00727   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00728   *
00729   *         @arg All the next values are only available on chip which support DMA2:
00730   *         @arg @ref LL_DMAMUX_CHANNEL_7
00731   *         @arg @ref LL_DMAMUX_CHANNEL_8
00732   *         @arg @ref LL_DMAMUX_CHANNEL_9
00733   *         @arg @ref LL_DMAMUX_CHANNEL_10
00734   *         @arg @ref LL_DMAMUX_CHANNEL_11
00735   * @retval Returned value can be one of the following values:
00736   *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
00737   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
00738   *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
00739   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
00740   */
00741 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00742 {
00743   (void)(DMAMUXx);
00744   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
00745 }
00746
00747 /**
00748   * @brief  Enable the Event Generation on DMAMUX channel x.
00749   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00750   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00751   * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
00752   * @param  DMAMUXx DMAMUXx Instance
00753   * @param  Channel This parameter can be one of the following values:
00754   *         @arg @ref LL_DMAMUX_CHANNEL_0
00755   *         @arg @ref LL_DMAMUX_CHANNEL_1
00756   *         @arg @ref LL_DMAMUX_CHANNEL_2
00757   *         @arg @ref LL_DMAMUX_CHANNEL_3
00758   *         @arg @ref LL_DMAMUX_CHANNEL_4
00759   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00760   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00761   *
00762   *         @arg All the next values are only available on chip which support DMA2:
00763   *         @arg @ref LL_DMAMUX_CHANNEL_7
00764   *         @arg @ref LL_DMAMUX_CHANNEL_8
00765   *         @arg @ref LL_DMAMUX_CHANNEL_9
00766   *         @arg @ref LL_DMAMUX_CHANNEL_10
00767   *         @arg @ref LL_DMAMUX_CHANNEL_11
00768   * @retval None
00769   */
00770 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00771 {
00772   (void)(DMAMUXx);
00773   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
00774 }
00775
00776 /**
00777   * @brief  Disable the Event Generation on DMAMUX channel x.
00778   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00779   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00780   * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
00781   * @param  DMAMUXx DMAMUXx Instance
00782   * @param  Channel This parameter can be one of the following values:
00783   *         @arg @ref LL_DMAMUX_CHANNEL_0
00784   *         @arg @ref LL_DMAMUX_CHANNEL_1
00785   *         @arg @ref LL_DMAMUX_CHANNEL_2
00786   *         @arg @ref LL_DMAMUX_CHANNEL_3
00787   *         @arg @ref LL_DMAMUX_CHANNEL_4
00788   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00789   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00790   *
00791   *         @arg All the next values are only available on chip which support DMA2:
00792   *         @arg @ref LL_DMAMUX_CHANNEL_7
00793   *         @arg @ref LL_DMAMUX_CHANNEL_8
00794   *         @arg @ref LL_DMAMUX_CHANNEL_9
00795   *         @arg @ref LL_DMAMUX_CHANNEL_10
00796   *         @arg @ref LL_DMAMUX_CHANNEL_11
00797   * @retval None
00798   */
00799 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00800 {
00801   (void)(DMAMUXx);
00802   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
00803 }
00804
00805 /**
00806   * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
00807   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00808   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00809   * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
00810   * @param  DMAMUXx DMAMUXx Instance
00811   * @param  Channel This parameter can be one of the following values:
00812   *         @arg @ref LL_DMAMUX_CHANNEL_0
00813   *         @arg @ref LL_DMAMUX_CHANNEL_1
00814   *         @arg @ref LL_DMAMUX_CHANNEL_2
00815   *         @arg @ref LL_DMAMUX_CHANNEL_3
00816   *         @arg @ref LL_DMAMUX_CHANNEL_4
00817   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00818   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00819   *
00820   *         @arg All the next values are only available on chip which support DMA2:
00821   *         @arg @ref LL_DMAMUX_CHANNEL_7
00822   *         @arg @ref LL_DMAMUX_CHANNEL_8
00823   *         @arg @ref LL_DMAMUX_CHANNEL_9
00824   *         @arg @ref LL_DMAMUX_CHANNEL_10
00825   *         @arg @ref LL_DMAMUX_CHANNEL_11
00826   * @retval State of bit (1 or 0).
00827   */
00828 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00829 {
00830   (void)(DMAMUXx);
00831   return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
00832 }
00833
00834 /**
00835   * @brief  Enable the synchronization mode.
00836   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00837   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00838   * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
00839   * @param  DMAMUXx DMAMUXx Instance
00840   * @param  Channel This parameter can be one of the following values:
00841   *         @arg @ref LL_DMAMUX_CHANNEL_0
00842   *         @arg @ref LL_DMAMUX_CHANNEL_1
00843   *         @arg @ref LL_DMAMUX_CHANNEL_2
00844   *         @arg @ref LL_DMAMUX_CHANNEL_3
00845   *         @arg @ref LL_DMAMUX_CHANNEL_4
00846   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00847   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00848   *
00849   *         @arg All the next values are only available on chip which support DMA2:
00850   *         @arg @ref LL_DMAMUX_CHANNEL_7
00851   *         @arg @ref LL_DMAMUX_CHANNEL_8
00852   *         @arg @ref LL_DMAMUX_CHANNEL_9
00853   *         @arg @ref LL_DMAMUX_CHANNEL_10
00854   *         @arg @ref LL_DMAMUX_CHANNEL_11
00855   * @retval None
00856   */
00857 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00858 {
00859   (void)(DMAMUXx);
00860   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
00861 }
00862
00863 /**
00864   * @brief  Disable the synchronization mode.
00865   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00866   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00867   * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
00868   * @param  DMAMUXx DMAMUXx Instance
00869   * @param  Channel This parameter can be one of the following values:
00870   *         @arg @ref LL_DMAMUX_CHANNEL_0
00871   *         @arg @ref LL_DMAMUX_CHANNEL_1
00872   *         @arg @ref LL_DMAMUX_CHANNEL_2
00873   *         @arg @ref LL_DMAMUX_CHANNEL_3
00874   *         @arg @ref LL_DMAMUX_CHANNEL_4
00875   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00876   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00877   *
00878   *         @arg All the next values are only available on chip which support DMA2:
00879   *         @arg @ref LL_DMAMUX_CHANNEL_7
00880   *         @arg @ref LL_DMAMUX_CHANNEL_8
00881   *         @arg @ref LL_DMAMUX_CHANNEL_9
00882   *         @arg @ref LL_DMAMUX_CHANNEL_10
00883   *         @arg @ref LL_DMAMUX_CHANNEL_11
00884   * @retval None
00885   */
00886 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00887 {
00888   (void)(DMAMUXx);
00889   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
00890 }
00891
00892 /**
00893   * @brief  Check if the synchronization mode is enabled or disabled.
00894   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00895   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00896   * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
00897   * @param  DMAMUXx DMAMUXx Instance
00898   * @param  Channel This parameter can be one of the following values:
00899   *         @arg @ref LL_DMAMUX_CHANNEL_0
00900   *         @arg @ref LL_DMAMUX_CHANNEL_1
00901   *         @arg @ref LL_DMAMUX_CHANNEL_2
00902   *         @arg @ref LL_DMAMUX_CHANNEL_3
00903   *         @arg @ref LL_DMAMUX_CHANNEL_4
00904   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00905   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00906   *
00907   *         @arg All the next values are only available on chip which support DMA2:
00908   *         @arg @ref LL_DMAMUX_CHANNEL_7
00909   *         @arg @ref LL_DMAMUX_CHANNEL_8
00910   *         @arg @ref LL_DMAMUX_CHANNEL_9
00911   *         @arg @ref LL_DMAMUX_CHANNEL_10
00912   *         @arg @ref LL_DMAMUX_CHANNEL_11
00913   * @retval State of bit (1 or 0).
00914   */
00915 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00916 {
00917   (void)(DMAMUXx);
00918   return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
00919 }
00920
00921 /**
00922   * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
00923   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00924   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00925   * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
00926   * @param  DMAMUXx DMAMUXx Instance
00927   * @param  Channel This parameter can be one of the following values:
00928   *         @arg @ref LL_DMAMUX_CHANNEL_0
00929   *         @arg @ref LL_DMAMUX_CHANNEL_1
00930   *         @arg @ref LL_DMAMUX_CHANNEL_2
00931   *         @arg @ref LL_DMAMUX_CHANNEL_3
00932   *         @arg @ref LL_DMAMUX_CHANNEL_4
00933   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00934   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00935   *
00936   *         @arg All the next values are only available on chip which support DMA2:
00937   *         @arg @ref LL_DMAMUX_CHANNEL_7
00938   *         @arg @ref LL_DMAMUX_CHANNEL_8
00939   *         @arg @ref LL_DMAMUX_CHANNEL_9
00940   *         @arg @ref LL_DMAMUX_CHANNEL_10
00941   *         @arg @ref LL_DMAMUX_CHANNEL_11
00942   * @param  SyncID This parameter can be one of the following values:
00943   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
00944   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
00945   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
00946   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
00947   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
00948   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
00949   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
00950   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
00951   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
00952   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
00953   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
00954   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
00955   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
00956   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
00957   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
00958   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
00959   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
00960   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
00961   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
00962   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
00963   *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
00964   *         @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
00965   *         @arg @ref LL_DMAMUX_SYNC_TIM14_OC
00966   * @retval None
00967   */
00968 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
00969 {
00970   (void)(DMAMUXx);
00971   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
00972 }
00973
00974 /**
00975   * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
00976   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00977   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
00978   * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
00979   * @param  DMAMUXx DMAMUXx Instance
00980   * @param  Channel This parameter can be one of the following values:
00981   *         @arg @ref LL_DMAMUX_CHANNEL_0
00982   *         @arg @ref LL_DMAMUX_CHANNEL_1
00983   *         @arg @ref LL_DMAMUX_CHANNEL_2
00984   *         @arg @ref LL_DMAMUX_CHANNEL_3
00985   *         @arg @ref LL_DMAMUX_CHANNEL_4
00986   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
00987   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
00988   *
00989   *         @arg All the next values are only available on chip which support DMA2:
00990   *         @arg @ref LL_DMAMUX_CHANNEL_7
00991   *         @arg @ref LL_DMAMUX_CHANNEL_8
00992   *         @arg @ref LL_DMAMUX_CHANNEL_9
00993   *         @arg @ref LL_DMAMUX_CHANNEL_10
00994   *         @arg @ref LL_DMAMUX_CHANNEL_11
00995   * @retval Returned value can be one of the following values:
00996   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
00997   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
00998   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
00999   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
01000   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
01001   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
01002   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
01003   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
01004   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
01005   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
01006   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
01007   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
01008   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
01009   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
01010   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
01011   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
01012   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
01013   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
01014   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
01015   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
01016   *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
01017   *         @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
01018   *         @arg @ref LL_DMAMUX_SYNC_TIM14_OC
01019   */
01020 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01021 {
01022   (void)(DMAMUXx);
01023   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
01024 }
01025
01026 /**
01027   * @brief  Enable the Request Generator.
01028   * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
01029   * @param  DMAMUXx DMAMUXx Instance
01030   * @param  RequestGenChannel This parameter can be one of the following values:
01031   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01032   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01033   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01034   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01035   * @retval None
01036   */
01037 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01038 {
01039   (void)(DMAMUXx);
01040   SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01041                                                     (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
01042 }
01043
01044 /**
01045   * @brief  Disable the Request Generator.
01046   * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
01047   * @param  DMAMUXx DMAMUXx Instance
01048   * @param  RequestGenChannel This parameter can be one of the following values:
01049   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01050   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01051   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01052   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01053   * @retval None
01054   */
01055 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01056 {
01057   (void)(DMAMUXx);
01058   CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01059                                                       (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
01060 }
01061
01062 /**
01063   * @brief  Check if the Request Generator is enabled or disabled.
01064   * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
01065   * @param  DMAMUXx DMAMUXx Instance
01066   * @param  RequestGenChannel This parameter can be one of the following values:
01067   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01068   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01069   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01070   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01071   * @retval State of bit (1 or 0).
01072   */
01073 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01074 {
01075   (void)(DMAMUXx);
01076   return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01077                                                               (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
01078 }
01079
01080 /**
01081   * @brief  Set the polarity of the signal on which the DMA request is generated.
01082   * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
01083   * @param  DMAMUXx DMAMUXx Instance
01084   * @param  RequestGenChannel This parameter can be one of the following values:
01085   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01086   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01087   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01088   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01089   * @param  Polarity This parameter can be one of the following values:
01090   *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
01091   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
01092   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
01093   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
01094   * @retval None
01095   */
01096 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
01097                                                      uint32_t Polarity)
01098 {
01099   (void)(DMAMUXx);
01100   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01101                                                        (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
01102 }
01103
01104 /**
01105   * @brief  Get the polarity of the signal on which the DMA request is generated.
01106   * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
01107   * @param  DMAMUXx DMAMUXx Instance
01108   * @param  RequestGenChannel This parameter can be one of the following values:
01109   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01110   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01111   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01112   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01113   * @retval Returned value can be one of the following values:
01114   *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
01115   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
01116   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
01117   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
01118   */
01119 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01120 {
01121   (void)(DMAMUXx);
01122   return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
01123                                                             (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
01124 }
01125
01126 /**
01127   * @brief  Set the number of DMA request that will be autorized after a generation event.
01128   * @note   This field can only be written when Generator is disabled.
01129   * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
01130   * @param  DMAMUXx DMAMUXx Instance
01131   * @param  RequestGenChannel This parameter can be one of the following values:
01132   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01133   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01134   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01135   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01136   * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
01137   * @retval None
01138   */
01139 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
01140                                                uint32_t RequestNb)
01141 {
01142   (void)(DMAMUXx);
01143   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01144                                                        (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
01145 }
01146
01147 /**
01148   * @brief  Get the number of DMA request that will be autorized after a generation event.
01149   * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
01150   * @param  DMAMUXx DMAMUXx Instance
01151   * @param  RequestGenChannel This parameter can be one of the following values:
01152   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01153   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01154   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01155   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01156   * @retval Between Min_Data = 1 and Max_Data = 32
01157   */
01158 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01159 {
01160   (void)(DMAMUXx);
01161   return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
01162                                                              (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
01163 }
01164
01165 /**
01166   * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
01167   * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
01168   * @param  DMAMUXx DMAMUXx Instance
01169   * @param  RequestGenChannel This parameter can be one of the following values:
01170   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01171   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01172   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01173   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01174   * @param  RequestSignalID This parameter can be one of the following values:
01175   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
01176   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
01177   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
01178   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
01179   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
01180   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
01181   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
01182   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
01183   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
01184   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
01185   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
01186   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
01187   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
01188   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
01189   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
01190   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
01191   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
01192   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
01193   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
01194   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
01195   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
01196   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
01197   *         @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC
01198   * @retval None
01199   */
01200 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
01201                                                   uint32_t RequestSignalID)
01202 {
01203   (void)(DMAMUXx);
01204   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
01205                                                        (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
01206 }
01207
01208 /**
01209   * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
01210   * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
01211   * @param  DMAMUXx DMAMUXx Instance
01212   * @param  RequestGenChannel This parameter can be one of the following values:
01213   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01214   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01215   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01216   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01217   * @retval Returned value can be one of the following values:
01218   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
01219   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
01220   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
01221   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
01222   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
01223   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
01224   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
01225   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
01226   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
01227   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
01228   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
01229   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
01230   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
01231   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
01232   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
01233   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
01234   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
01235   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
01236   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
01237   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
01238   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
01239   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
01240   *         @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC
01241   */
01242 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01243 {
01244   (void)(DMAMUXx);
01245   return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
01246                                                             (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
01247 }
01248
01249 /**
01250   * @}
01251   */
01252
01253 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
01254   * @{
01255   */
01256
01257 /**
01258   * @brief  Get Synchronization Event Overrun Flag Channel 0.
01259   * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
01260   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01261   * @retval State of bit (1 or 0).
01262   */
01263 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01264 {
01265   (void)(DMAMUXx);
01266   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
01267 }
01268
01269 /**
01270   * @brief  Get Synchronization Event Overrun Flag Channel 1.
01271   * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
01272   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01273   * @retval State of bit (1 or 0).
01274   */
01275 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01276 {
01277   (void)(DMAMUXx);
01278   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
01279 }
01280
01281 /**
01282   * @brief  Get Synchronization Event Overrun Flag Channel 2.
01283   * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
01284   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01285   * @retval State of bit (1 or 0).
01286   */
01287 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01288 {
01289   (void)(DMAMUXx);
01290   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
01291 }
01292
01293 /**
01294   * @brief  Get Synchronization Event Overrun Flag Channel 3.
01295   * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
01296   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01297   * @retval State of bit (1 or 0).
01298   */
01299 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01300 {
01301   (void)(DMAMUXx);
01302   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
01303 }
01304
01305 /**
01306   * @brief  Get Synchronization Event Overrun Flag Channel 4.
01307   * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
01308   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01309   * @retval State of bit (1 or 0).
01310   */
01311 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01312 {
01313   (void)(DMAMUXx);
01314   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
01315 }
01316
01317 #if defined(DMAMUX1_Channel5)
01318 /**
01319   * @brief  Get Synchronization Event Overrun Flag Channel 5.
01320   * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
01321   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01322   * @retval State of bit (1 or 0).
01323   */
01324 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01325 {
01326   (void)(DMAMUXx);
01327   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
01328 }
01329
01330 #endif /* DMAMUX1_Channel5 */
01331 #if defined(DMAMUX1_Channel6)
01332 /**
01333   * @brief  Get Synchronization Event Overrun Flag Channel 6.
01334   * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
01335   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01336   * @retval State of bit (1 or 0).
01337   */
01338 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01339 {
01340   (void)(DMAMUXx);
01341   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
01342 }
01343
01344 #endif /* DMAMUX1_Channel6 */
01345 #if defined(DMAMUX1_Channel7)
01346 /**
01347   * @brief  Get Synchronization Event Overrun Flag Channel 7.
01348   * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
01349   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01350   * @retval State of bit (1 or 0).
01351   */
01352 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01353 {
01354   (void)(DMAMUXx);
01355   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
01356 }
01357
01358 #endif /* DMAMUX1_Channel7 */
01359 #if defined(DMAMUX1_Channel8)
01360 /**
01361   * @brief  Get Synchronization Event Overrun Flag Channel 8.
01362   * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
01363   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01364   * @retval State of bit (1 or 0).
01365   */
01366 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
01367 {
01368   (void)(DMAMUXx);
01369   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
01370 }
01371
01372 #endif /* DMAMUX1_Channel8 */
01373 #if defined(DMAMUX1_Channel9)
01374 /**
01375   * @brief  Get Synchronization Event Overrun Flag Channel 9.
01376   * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
01377   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01378   * @retval State of bit (1 or 0).
01379   */
01380 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
01381 {
01382   (void)(DMAMUXx);
01383   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
01384 }
01385
01386 #endif /* DMAMUX1_Channel9 */
01387 #if defined(DMAMUX1_Channel10)
01388 /**
01389   * @brief  Get Synchronization Event Overrun Flag Channel 10.
01390   * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
01391   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01392   * @retval State of bit (1 or 0).
01393   */
01394 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
01395 {
01396   (void)(DMAMUXx);
01397   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
01398 }
01399
01400 #endif /* DMAMUX1_Channel10 */
01401 #if defined(DMAMUX1_Channel11)
01402 /**
01403   * @brief  Get Synchronization Event Overrun Flag Channel 11.
01404   * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
01405   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01406   * @retval State of bit (1 or 0).
01407   */
01408 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
01409 {
01410   (void)(DMAMUXx);
01411   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
01412 }
01413
01414 #endif /* DMAMUX1_Channel11 */
01415 /**
01416   * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
01417   * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
01418   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01419   * @retval State of bit (1 or 0).
01420   */
01421 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01422 {
01423   (void)(DMAMUXx);
01424   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
01425 }
01426
01427 /**
01428   * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
01429   * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
01430   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01431   * @retval State of bit (1 or 0).
01432   */
01433 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01434 {
01435   (void)(DMAMUXx);
01436   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
01437 }
01438
01439 /**
01440   * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
01441   * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
01442   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01443   * @retval State of bit (1 or 0).
01444   */
01445 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01446 {
01447   (void)(DMAMUXx);
01448   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
01449 }
01450
01451 /**
01452   * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
01453   * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
01454   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01455   * @retval State of bit (1 or 0).
01456   */
01457 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01458 {
01459   (void)(DMAMUXx);
01460   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
01461 }
01462
01463 /**
01464   * @brief  Clear Synchronization Event Overrun Flag Channel 0.
01465   * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
01466   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01467   * @retval None
01468   */
01469 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01470 {
01471   (void)(DMAMUXx);
01472   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
01473 }
01474
01475 /**
01476   * @brief  Clear Synchronization Event Overrun Flag Channel 1.
01477   * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
01478   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01479   * @retval None
01480   */
01481 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01482 {
01483   (void)(DMAMUXx);
01484   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
01485 }
01486
01487 /**
01488   * @brief  Clear Synchronization Event Overrun Flag Channel 2.
01489   * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
01490   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01491   * @retval None
01492   */
01493 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01494 {
01495   (void)(DMAMUXx);
01496   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
01497 }
01498
01499 /**
01500   * @brief  Clear Synchronization Event Overrun Flag Channel 3.
01501   * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
01502   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01503   * @retval None
01504   */
01505 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01506 {
01507   (void)(DMAMUXx);
01508   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
01509 }
01510
01511 /**
01512   * @brief  Clear Synchronization Event Overrun Flag Channel 4.
01513   * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
01514   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01515   * @retval None
01516   */
01517 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01518 {
01519   (void)(DMAMUXx);
01520   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
01521 }
01522
01523 #if defined(DMAMUX1_Channel5)
01524 /**
01525   * @brief  Clear Synchronization Event Overrun Flag Channel 5.
01526   * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
01527   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01528   * @retval None
01529   */
01530 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01531 {
01532   (void)(DMAMUXx);
01533   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
01534 }
01535
01536 #endif /* DMAMUX1_Channel5 */
01537 #if defined(DMAMUX1_Channel6)
01538 /**
01539   * @brief  Clear Synchronization Event Overrun Flag Channel 6.
01540   * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
01541   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01542   * @retval None
01543   */
01544 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01545 {
01546   (void)(DMAMUXx);
01547   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
01548 }
01549
01550 #endif /* DMAMUX1_Channel6 */
01551 #if defined(DMAMUX1_Channel7)
01552 /**
01553   * @brief  Clear Synchronization Event Overrun Flag Channel 7.
01554   * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
01555   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01556   * @retval None
01557   */
01558 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01559 {
01560   (void)(DMAMUXx);
01561   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
01562 }
01563
01564 #endif /* DMAMUX1_Channel7 */
01565 #if defined(DMAMUX1_Channel8)
01566 /**
01567   * @brief  Clear Synchronization Event Overrun Flag Channel 8.
01568   * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
01569   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01570   * @retval None
01571   */
01572 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
01573 {
01574   (void)(DMAMUXx);
01575   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
01576 }
01577
01578 #endif /* DMAMUX1_Channel8 */
01579 #if defined(DMAMUX1_Channel9)
01580 /**
01581   * @brief  Clear Synchronization Event Overrun Flag Channel 9.
01582   * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
01583   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01584   * @retval None
01585   */
01586 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
01587 {
01588   (void)(DMAMUXx);
01589   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
01590 }
01591
01592 #endif /* DMAMUX1_Channel9 */
01593 #if defined(DMAMUX1_Channel10)
01594 /**
01595   * @brief  Clear Synchronization Event Overrun Flag Channel 10.
01596   * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
01597   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01598   * @retval None
01599   */
01600 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
01601 {
01602   (void)(DMAMUXx);
01603   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
01604 }
01605
01606 #endif /* DMAMUX1_Channel10 */
01607 #if defined(DMAMUX1_Channel11)
01608 /**
01609   * @brief  Clear Synchronization Event Overrun Flag Channel 11.
01610   * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
01611   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01612   * @retval None
01613   */
01614 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
01615 {
01616   (void)(DMAMUXx);
01617   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
01618 }
01619
01620 #endif /* DMAMUX1_Channel11 */
01621 /**
01622   * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
01623   * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
01624   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01625   * @retval None
01626   */
01627 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01628 {
01629   (void)(DMAMUXx);
01630   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
01631 }
01632
01633 /**
01634   * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
01635   * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
01636   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01637   * @retval None
01638   */
01639 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01640 {
01641   (void)(DMAMUXx);
01642   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
01643 }
01644
01645 /**
01646   * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
01647   * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
01648   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01649   * @retval None
01650   */
01651 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01652 {
01653   (void)(DMAMUXx);
01654   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
01655 }
01656
01657 /**
01658   * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
01659   * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
01660   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01661   * @retval None
01662   */
01663 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01664 {
01665   (void)(DMAMUXx);
01666   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
01667 }
01668
01669 /**
01670   * @}
01671   */
01672
01673 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
01674   * @{
01675   */
01676
01677 /**
01678   * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
01679   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
01680   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
01681   * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
01682   * @param  DMAMUXx DMAMUXx Instance
01683   * @param  Channel This parameter can be one of the following values:
01684   *         @arg @ref LL_DMAMUX_CHANNEL_0
01685   *         @arg @ref LL_DMAMUX_CHANNEL_1
01686   *         @arg @ref LL_DMAMUX_CHANNEL_2
01687   *         @arg @ref LL_DMAMUX_CHANNEL_3
01688   *         @arg @ref LL_DMAMUX_CHANNEL_4
01689   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
01690   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
01691   *
01692   *         @arg All the next values are only available on chip which support DMA2:
01693   *         @arg @ref LL_DMAMUX_CHANNEL_7
01694   *         @arg @ref LL_DMAMUX_CHANNEL_8
01695   *         @arg @ref LL_DMAMUX_CHANNEL_9
01696   *         @arg @ref LL_DMAMUX_CHANNEL_10
01697   *         @arg @ref LL_DMAMUX_CHANNEL_11
01698   * @retval None
01699   */
01700 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01701 {
01702   (void)(DMAMUXx);
01703   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
01704 }
01705
01706 /**
01707   * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
01708   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
01709   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
01710   * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
01711   * @param  DMAMUXx DMAMUXx Instance
01712   * @param  Channel This parameter can be one of the following values:
01713   *         @arg @ref LL_DMAMUX_CHANNEL_0
01714   *         @arg @ref LL_DMAMUX_CHANNEL_1
01715   *         @arg @ref LL_DMAMUX_CHANNEL_2
01716   *         @arg @ref LL_DMAMUX_CHANNEL_3
01717   *         @arg @ref LL_DMAMUX_CHANNEL_4
01718   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
01719   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
01720   *
01721   *         @arg All the next values are only available on chip which support DMA2:
01722   *         @arg @ref LL_DMAMUX_CHANNEL_7
01723   *         @arg @ref LL_DMAMUX_CHANNEL_8
01724   *         @arg @ref LL_DMAMUX_CHANNEL_9
01725   *         @arg @ref LL_DMAMUX_CHANNEL_10
01726   *         @arg @ref LL_DMAMUX_CHANNEL_11
01727   * @retval None
01728   */
01729 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01730 {
01731   (void)(DMAMUXx);
01732   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
01733 }
01734
01735 /**
01736   * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
01737   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
01738   *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
01739   * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
01740   * @param  DMAMUXx DMAMUXx Instance
01741   * @param  Channel This parameter can be one of the following values:
01742   *         @arg @ref LL_DMAMUX_CHANNEL_0
01743   *         @arg @ref LL_DMAMUX_CHANNEL_1
01744   *         @arg @ref LL_DMAMUX_CHANNEL_2
01745   *         @arg @ref LL_DMAMUX_CHANNEL_3
01746   *         @arg @ref LL_DMAMUX_CHANNEL_4
01747   *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
01748   *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
01749   *
01750   *         @arg All the next values are only available on chip which support DMA2:
01751   *         @arg @ref LL_DMAMUX_CHANNEL_7
01752   *         @arg @ref LL_DMAMUX_CHANNEL_8
01753   *         @arg @ref LL_DMAMUX_CHANNEL_9
01754   *         @arg @ref LL_DMAMUX_CHANNEL_10
01755   *         @arg @ref LL_DMAMUX_CHANNEL_11
01756   * @retval State of bit (1 or 0).
01757   */
01758 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01759 {
01760   (void)(DMAMUXx);
01761   return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL);
01762 }
01763
01764 /**
01765   * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
01766   * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
01767   * @param  DMAMUXx DMAMUXx Instance
01768   * @param  RequestGenChannel This parameter can be one of the following values:
01769   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01770   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01771   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01772   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01773   * @retval None
01774   */
01775 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01776 {
01777   (void)(DMAMUXx);
01778   SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
01779 }
01780
01781 /**
01782   * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
01783   * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
01784   * @param  DMAMUXx DMAMUXx Instance
01785   * @param  RequestGenChannel This parameter can be one of the following values:
01786   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01787   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01788   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01789   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01790   * @retval None
01791   */
01792 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01793 {
01794   (void)(DMAMUXx);
01795   CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
01796 }
01797
01798 /**
01799   * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
01800   * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
01801   * @param  DMAMUXx DMAMUXx Instance
01802   * @param  RequestGenChannel This parameter can be one of the following values:
01803   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01804   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01805   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01806   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01807   * @retval State of bit (1 or 0).
01808   */
01809 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01810 {
01811   (void)(DMAMUXx);
01812   return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
01813 }
01814
01815 /**
01816   * @}
01817   */
01818
01819 /**
01820   * @}
01821   */
01822
01823 /**
01824   * @}
01825   */
01826
01827 #endif /* DMAMUX1 */
01828
01829 /**
01830   * @}
01831   */
01832
01833 #ifdef __cplusplus
01834 }
01835 #endif
01836
01837 #endif /* STM32G0xx_LL_DMAMUX_H */
01838
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_exti.c Source File

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stm32g0xx_ll_exti.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_exti.h"
00022 #ifdef  USE_FULL_ASSERT
00023 #include "stm32_assert.h"
00024 #else
00025 #define assert_param(expr) ((void)0U)
00026 #endif /* USE_FULL_ASSERT */
00027
00028 /** @addtogroup STM32G0xx_LL_Driver
00029   * @{
00030   */
00031
00032 #if defined (EXTI)
00033
00034 /** @defgroup EXTI_LL EXTI
00035   * @{
00036   */
00037
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /* Private macros ------------------------------------------------------------*/
00042 /** @addtogroup EXTI_LL_Private_Macros
00043   * @{
00044   */
00045
00046 #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
00047 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00048 #define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
00049 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00050 #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
00051                                                    || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
00052                                                    || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
00053
00054
00055 #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
00056                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
00057                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
00058                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Private function prototypes -----------------------------------------------*/
00065
00066 /* Exported functions --------------------------------------------------------*/
00067 /** @addtogroup EXTI_LL_Exported_Functions
00068   * @{
00069   */
00070
00071 /** @addtogroup EXTI_LL_EF_Init
00072   * @{
00073   */
00074
00075 /**
00076   * @brief  De-initialize the EXTI registers to their default reset values.
00077   * @retval An ErrorStatus enumeration value:
00078   *          - 0x00: EXTI registers are de-initialized
00079   */
00080 uint32_t LL_EXTI_DeInit(void)
00081 {
00082   /* Interrupt mask register set to default reset values */
00083   LL_EXTI_WriteReg(IMR1,   0xFFF80000U);
00084   /* Event mask register set to default reset values */
00085   LL_EXTI_WriteReg(EMR1,   0x00000000U);
00086   /* Rising Trigger selection register set to default reset values */
00087   LL_EXTI_WriteReg(RTSR1,  0x00000000U);
00088   /* Falling Trigger selection register set to default reset values */
00089   LL_EXTI_WriteReg(FTSR1,  0x00000000U);
00090   /* Software interrupt event register set to default reset values */
00091   LL_EXTI_WriteReg(SWIER1, 0x00000000U);
00092   /* Pending register set to default reset values */
00093 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00094   LL_EXTI_WriteReg(RPR1,    0x0017FFFFU);
00095   LL_EXTI_WriteReg(FPR1,    0x0017FFFFU);
00096 #elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G061xx) || defined(STM32G051xx)
00097   LL_EXTI_WriteReg(RPR1,    0x0007FFFFU);
00098   LL_EXTI_WriteReg(FPR1,    0x0007FFFFU);
00099 #elif defined(STM32G041xx) || defined(STM32G031xx)
00100   LL_EXTI_WriteReg(RPR1,    0x0001FFFFU);
00101   LL_EXTI_WriteReg(FPR1,    0x0001FFFFU);
00102 #elif defined(STM32G0B0xx) || defined(STM32G070xx) || defined(STM32G050xx) || defined(STM32G030xx)
00103   LL_EXTI_WriteReg(RPR1,    0x0000FFFFU);
00104   LL_EXTI_WriteReg(FPR1,    0x0000FFFFU);
00105 #endif /* STM32G0C1xx || STM32G0B1xx */
00106
00107 #if defined(STM32G081xx) || defined(STM32G071xx)
00108   /* Interrupt mask register 2 set to default reset values */
00109   LL_EXTI_WriteReg(IMR2, 0x00000003U);
00110   /* Event mask register 2 set to default reset values */
00111   LL_EXTI_WriteReg(EMR2, 0x00000000U);
00112 #elif defined(STM32G0C1xx) || defined(STM32G0B1xx)
00113   /* Interrupt mask register 2 set to default reset values */
00114   LL_EXTI_WriteReg(IMR2, 0x0000001FU);
00115   /* Event mask register 2 set to default reset values */
00116   LL_EXTI_WriteReg(EMR2, 0x00000000U);
00117   /* Rising Trigger selection register set to default reset values */
00118   LL_EXTI_WriteReg(RTSR2, 0x00000000U);
00119   /* Falling Trigger selection register set to default reset values */
00120   LL_EXTI_WriteReg(FTSR2, 0x00000000U);
00121   /* Software interrupt event register set to default reset values */
00122   LL_EXTI_WriteReg(SWIER2, 0x00000000U);
00123   /* Pending register set to default reset values */
00124   LL_EXTI_WriteReg(RPR2, 0x00000004U);
00125   LL_EXTI_WriteReg(FPR2, 0x00000004U);
00126 #elif defined(STM32G0B0xx)
00127   /* Interrupt mask register 2 set to default reset values */
00128   LL_EXTI_WriteReg(IMR2, 0x00000010U);
00129   /* Event mask register 2 set to default reset values */
00130   LL_EXTI_WriteReg(EMR2, 0x00000000U);
00131 #endif /* STM32G081xx || STM32G071xx */
00132
00133   return 0x00u;
00134 }
00135
00136 /**
00137   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
00138   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
00139   * @retval An ErrorStatus enumeration value:
00140   *          - 0x00: EXTI registers are initialized
00141   *          - any other value : wrong configuration
00142   */
00143 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00144 {
00145   uint32_t status = 0x00u;
00146
00147   /* Check the parameters */
00148   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
00149 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00150   assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
00151 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00152   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
00153   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
00154
00155   /* ENABLE LineCommand */
00156   if (EXTI_InitStruct->LineCommand != DISABLE)
00157   {
00158     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
00159
00160     /* Configure EXTI Lines in range from 0 to 31 */
00161     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
00162     {
00163       switch (EXTI_InitStruct->Mode)
00164       {
00165         case LL_EXTI_MODE_IT:
00166           /* First Disable Event on provided Lines */
00167           LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00168           /* Then Enable IT on provided Lines */
00169           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00170           break;
00171         case LL_EXTI_MODE_EVENT:
00172           /* First Disable IT on provided Lines */
00173           LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00174           /* Then Enable Event on provided Lines */
00175           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00176           break;
00177         case LL_EXTI_MODE_IT_EVENT:
00178           /* Directly Enable IT & Event on provided Lines */
00179           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00180           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00181           break;
00182         default:
00183           status = 0x01u;
00184           break;
00185       }
00186       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00187       {
00188         switch (EXTI_InitStruct->Trigger)
00189         {
00190           case LL_EXTI_TRIGGER_RISING:
00191             /* First Disable Falling Trigger on provided Lines */
00192             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00193             /* Then Enable Rising Trigger on provided Lines */
00194             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00195             break;
00196           case LL_EXTI_TRIGGER_FALLING:
00197             /* First Disable Rising Trigger on provided Lines */
00198             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00199             /* Then Enable Falling Trigger on provided Lines */
00200             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00201             break;
00202           case LL_EXTI_TRIGGER_RISING_FALLING:
00203             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00204             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00205             break;
00206           default:
00207             status |= 0x02u;
00208             break;
00209         }
00210       }
00211     }
00212 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00213     /* Configure EXTI Lines in range from 32 to 63 */
00214     if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
00215     {
00216       switch (EXTI_InitStruct->Mode)
00217       {
00218         case LL_EXTI_MODE_IT:
00219           /* First Disable Event on provided Lines */
00220           LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00221           /* Then Enable IT on provided Lines */
00222           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00223           break;
00224         case LL_EXTI_MODE_EVENT:
00225           /* First Disable IT on provided Lines */
00226           LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00227           /* Then Enable Event on provided Lines */
00228           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00229           break;
00230         case LL_EXTI_MODE_IT_EVENT:
00231           /* Directly Enable IT & Event on provided Lines */
00232           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00233           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00234           break;
00235         default:
00236           status |= 0x04u;
00237           break;
00238       }
00239     }
00240 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00241   }
00242   /* DISABLE LineCommand */
00243   else
00244   {
00245     /* De-configure EXTI Lines in range from 0 to 31 */
00246     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00247     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00248 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00249     /* De-configure EXTI Lines in range from 32 to 63 */
00250     LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00251     LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00252 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00253   }
00254
00255   return status;
00256 }
00257
00258 /**
00259   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
00260   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
00261   * @retval None
00262   */
00263 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00264 {
00265   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
00266 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00267   EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
00268 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00269   EXTI_InitStruct->LineCommand    = DISABLE;
00270   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
00271   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
00272 }
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 /**
00283   * @}
00284   */
00285
00286 #endif /* defined (EXTI) */
00287
00288 /**
00289   * @}
00290   */
00291
00292 #endif /* USE_FULL_LL_DRIVER */
00293
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_exti.h Source File

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stm32g0xx_ll_exti.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_EXTI_H
00021 #define STM32G0xx_LL_EXTI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (EXTI)
00035
00036 /** @defgroup EXTI_LL EXTI
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 #define LL_EXTI_REGISTER_PINPOS_SHFT        16u   /*!< Define used to shift pin position in EXTICR register */
00044
00045 /* Private Macros ------------------------------------------------------------*/
00046 #if defined(USE_FULL_LL_DRIVER)
00047 /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
00048   * @{
00049   */
00050 /**
00051   * @}
00052   */
00053 #endif /*USE_FULL_LL_DRIVER*/
00054 /* Exported types ------------------------------------------------------------*/
00055 #if defined(USE_FULL_LL_DRIVER)
00056 /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
00057   * @{
00058   */
00059 typedef struct
00060 {
00061
00062   uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
00063                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00064 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00065   uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
00066                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00067 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00068   FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
00069                                      This parameter can be set either to ENABLE or DISABLE */
00070
00071   uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
00072                                      This parameter can be a value of @ref EXTI_LL_EC_MODE. */
00073
00074   uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
00075                                      This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
00076 } LL_EXTI_InitTypeDef;
00077
00078 /**
00079   * @}
00080   */
00081 #endif /*USE_FULL_LL_DRIVER*/
00082
00083 /* Exported constants --------------------------------------------------------*/
00084 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
00085   * @{
00086   */
00087
00088 /** @defgroup EXTI_LL_EC_LINE LINE
00089   * @{
00090   */
00091 #define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
00092 #define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
00093 #define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
00094 #define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
00095 #define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
00096 #define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
00097 #define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
00098 #define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
00099 #define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
00100 #define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
00101 #define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
00102 #define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
00103 #define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
00104 #define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
00105 #define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
00106 #define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
00107 #if defined(EXTI_IMR1_IM16)
00108 #define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
00109 #endif /* EXTI_IMR1_IM16 */
00110 #if defined(EXTI_IMR1_IM17)
00111 #define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
00112 #endif /* EXTI_IMR1_IM17 */
00113 #if defined(EXTI_IMR1_IM18)
00114 #define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
00115 #endif /* EXTI_IMR1_IM18 */
00116 #define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
00117 #if defined(EXTI_IMR1_IM20)
00118 #define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
00119 #endif /* EXTI_IMR1_IM20 */
00120 #if defined(EXTI_IMR1_IM21)
00121 #define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
00122 #endif /* EXTI_IMR1_IM21 */
00123 #if defined(EXTI_IMR1_IM22)
00124 #define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
00125 #endif /* EXTI_IMR1_IM22 */
00126 #define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
00127 #if defined(EXTI_IMR1_IM24)
00128 #define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
00129 #endif /* EXTI_IMR1_IM24 */
00130 #if defined(EXTI_IMR1_IM25)
00131 #define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
00132 #endif /* EXTI_IMR1_IM25 */
00133 #if defined(EXTI_IMR1_IM26)
00134 #define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
00135 #endif /* EXTI_IMR1_IM26 */
00136 #if defined(EXTI_IMR1_IM27)
00137 #define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
00138 #endif /* EXTI_IMR1_IM27 */
00139 #if defined(EXTI_IMR1_IM28)
00140 #define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
00141 #endif /* EXTI_IMR1_IM28 */
00142 #if defined(EXTI_IMR1_IM29)
00143 #define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
00144 #endif /* EXTI_IMR1_IM29 */
00145 #if defined(EXTI_IMR1_IM30)
00146 #define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
00147 #endif /* EXTI_IMR1_IM30 */
00148 #if defined(EXTI_IMR1_IM31)
00149 #define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
00150 #endif /* EXTI_IMR1_IM31 */
00151 #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
00152
00153 #if defined(EXTI_IMR2_IM32)
00154 #define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
00155 #endif /* EXTI_IMR2_IM32 */
00156 #if defined(EXTI_IMR2_IM33)
00157 #define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
00158 #endif /* EXTI_IMR2_IM33 */
00159 #if defined(EXTI_IMR2_IM34)
00160 #define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
00161 #endif /* EXTI_IMR2_IM34 */
00162 #if defined(EXTI_IMR2_IM35)
00163 #define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
00164 #endif /* EXTI_IMR2_IM35 */
00165 #if defined(EXTI_IMR2_IM36)
00166 #define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
00167 #endif /* EXTI_IMR2_IM36 */
00168 #if defined(EXTI_IMR2_IM32) || defined(EXTI_IMR2_IM33) || defined(EXTI_IMR2_IM34) || defined(EXTI_IMR2_IM35) || defined(EXTI_IMR2_IM36)
00169 #define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
00170 #endif /* EXTI_IMR2_IM32 || EXTI_IMR2_IM33 || EXTI_IMR2_IM34 || EXTI_IMR2_IM35 || EXTI_IMR2_IM36 */
00171
00172 #define LL_EXTI_LINE_ALL               0xFFFFFFFFU             /*!< All Extended line */
00173
00174 #if defined(USE_FULL_LL_DRIVER)
00175 #define LL_EXTI_LINE_NONE              0x00000000U             /*!< None Extended line */
00176 #endif /*USE_FULL_LL_DRIVER*/
00177
00178 /** @defgroup EXTI_LL_EC_CONFIG_PORT EXTI CONFIG PORT
00179   * @{
00180   */
00181 #define LL_EXTI_CONFIG_PORTA               0U                                          /*!< EXTI PORT A */
00182 #define LL_EXTI_CONFIG_PORTB               EXTI_EXTICR1_EXTI0_0                        /*!< EXTI PORT B */
00183 #define LL_EXTI_CONFIG_PORTC               EXTI_EXTICR1_EXTI0_1                        /*!< EXTI PORT C */
00184 #if defined(GPIOD_BASE)
00185 #define LL_EXTI_CONFIG_PORTD               (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */
00186 #endif /*GPIOD_BASE*/
00187 #if defined(GPIOE_BASE)
00188 #define LL_EXTI_CONFIG_PORTE               EXTI_EXTICR1_EXTI0_2                        /*!< EXTI PORT E */
00189 #endif /*GPIOE_BASE*/
00190 #define LL_EXTI_CONFIG_PORTF               (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup EXTI_LL_EC_CONFIG_LINE EXTI CONFIG LINE
00196   * @{
00197   */
00198 #define LL_EXTI_CONFIG_LINE0               ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
00199 #define LL_EXTI_CONFIG_LINE1               ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
00200 #define LL_EXTI_CONFIG_LINE2               ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)  /*!< EXTI_POSITION_16 | EXTICR[0] */
00201 #define LL_EXTI_CONFIG_LINE3               ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)  /*!< EXTI_POSITION_24 | EXTICR[0] */
00202 #define LL_EXTI_CONFIG_LINE4               ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
00203 #define LL_EXTI_CONFIG_LINE5               ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
00204 #define LL_EXTI_CONFIG_LINE6               ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)  /*!< EXTI_POSITION_16 | EXTICR[1] */
00205 #define LL_EXTI_CONFIG_LINE7               ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)  /*!< EXTI_POSITION_24 | EXTICR[1] */
00206 #define LL_EXTI_CONFIG_LINE8               ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
00207 #define LL_EXTI_CONFIG_LINE9               ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
00208 #define LL_EXTI_CONFIG_LINE10              ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)  /*!< EXTI_POSITION_16 | EXTICR[2] */
00209 #define LL_EXTI_CONFIG_LINE11              ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)  /*!< EXTI_POSITION_24 | EXTICR[2] */
00210 #define LL_EXTI_CONFIG_LINE12              ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
00211 #define LL_EXTI_CONFIG_LINE13              ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
00212 #define LL_EXTI_CONFIG_LINE14              ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)  /*!< EXTI_POSITION_16 | EXTICR[3] */
00213 #define LL_EXTI_CONFIG_LINE15              ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)  /*!< EXTI_POSITION_24 | EXTICR[3] */
00214 /**
00215   * @}
00216   */
00217 /**
00218   * @}
00219   */
00220 #if defined(USE_FULL_LL_DRIVER)
00221
00222 /** @defgroup EXTI_LL_EC_MODE Mode
00223   * @{
00224   */
00225 #define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
00226 #define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
00227 #define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
00233   * @{
00234   */
00235 #define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
00236 #define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
00237 #define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
00238 #define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
00239
00240 /**
00241   * @}
00242   */
00243
00244
00245 #endif /*USE_FULL_LL_DRIVER*/
00246
00247
00248 /**
00249   * @}
00250   */
00251
00252 /* Exported macro ------------------------------------------------------------*/
00253 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
00254   * @{
00255   */
00256
00257 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
00258   * @{
00259   */
00260
00261 /**
00262   * @brief  Write a value in EXTI register
00263   * @param  __REG__ Register to be written
00264   * @param  __VALUE__ Value to be written in the register
00265   * @retval None
00266   */
00267 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
00268
00269 /**
00270   * @brief  Read a value in EXTI register
00271   * @param  __REG__ Register to be read
00272   * @retval Register value
00273   */
00274 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
00275 /**
00276   * @}
00277   */
00278
00279
00280 /**
00281   * @}
00282   */
00283
00284
00285
00286 /* Exported functions --------------------------------------------------------*/
00287 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
00288  * @{
00289  */
00290 /** @defgroup EXTI_LL_EF_IT_Management IT_Management
00291   * @{
00292   */
00293
00294 /**
00295   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
00296   * @note The reset value for the direct or internal lines (see RM)
00297   *       is set to 1 in order to enable the interrupt by default.
00298   *       Bits are set automatically at Power on.
00299   * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
00300   * @param  ExtiLine This parameter can be one of the following values:
00301   *         @arg @ref LL_EXTI_LINE_0
00302   *         @arg @ref LL_EXTI_LINE_1
00303   *         @arg @ref LL_EXTI_LINE_2
00304   *         @arg @ref LL_EXTI_LINE_3
00305   *         @arg @ref LL_EXTI_LINE_4
00306   *         @arg @ref LL_EXTI_LINE_5
00307   *         @arg @ref LL_EXTI_LINE_6
00308   *         @arg @ref LL_EXTI_LINE_7
00309   *         @arg @ref LL_EXTI_LINE_8
00310   *         @arg @ref LL_EXTI_LINE_9
00311   *         @arg @ref LL_EXTI_LINE_10
00312   *         @arg @ref LL_EXTI_LINE_11
00313   *         @arg @ref LL_EXTI_LINE_12
00314   *         @arg @ref LL_EXTI_LINE_13
00315   *         @arg @ref LL_EXTI_LINE_14
00316   *         @arg @ref LL_EXTI_LINE_15
00317   *         @arg @ref LL_EXTI_LINE_16
00318   *         @arg @ref LL_EXTI_LINE_17
00319   *         @arg @ref LL_EXTI_LINE_18
00320   *         @arg @ref LL_EXTI_LINE_19
00321   *         @arg @ref LL_EXTI_LINE_21
00322   *         @arg @ref LL_EXTI_LINE_23
00323   *         @arg @ref LL_EXTI_LINE_25
00324   *         @arg @ref LL_EXTI_LINE_26
00325   *         @arg @ref LL_EXTI_LINE_27
00326   *         @arg @ref LL_EXTI_LINE_28
00327   *         @arg @ref LL_EXTI_LINE_29
00328   *         @arg @ref LL_EXTI_LINE_30
00329   *         @arg @ref LL_EXTI_LINE_31
00330   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00331   * @note   Please check each device line mapping for EXTI Line availability
00332   * @retval None
00333   */
00334 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00335 {
00336   SET_BIT(EXTI->IMR1, ExtiLine);
00337 }
00338
00339 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00340 /**
00341   * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
00342   * @note The reset value for the direct lines (lines 32 & 33)
00343   *       is set to 1 in order to enable the interrupt by default.
00344   *       Bits are set automatically at Power on.
00345   * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
00346   * @param  ExtiLine This parameter can be one of the following values:
00347   *         @arg @ref LL_EXTI_LINE_32
00348   *         @arg @ref LL_EXTI_LINE_33
00349   *         @arg @ref LL_EXTI_LINE_34
00350   *         @arg @ref LL_EXTI_LINE_35
00351   *         @arg @ref LL_EXTI_LINE_36
00352   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00353   * @note   Please check each device line mapping for EXTI Line availability
00354   * @retval None
00355   */
00356 __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
00357 {
00358   SET_BIT(EXTI->IMR2, ExtiLine);
00359 }
00360 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00361
00362 /**
00363   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
00364   * @note The reset value for the direct or internal lines (see RM)
00365   *       is set to 1 in order to enable the interrupt by default.
00366   *       Bits are set automatically at Power on.
00367   * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
00368   * @param  ExtiLine This parameter can be one of the following values:
00369   *         @arg @ref LL_EXTI_LINE_0
00370   *         @arg @ref LL_EXTI_LINE_1
00371   *         @arg @ref LL_EXTI_LINE_2
00372   *         @arg @ref LL_EXTI_LINE_3
00373   *         @arg @ref LL_EXTI_LINE_4
00374   *         @arg @ref LL_EXTI_LINE_5
00375   *         @arg @ref LL_EXTI_LINE_6
00376   *         @arg @ref LL_EXTI_LINE_7
00377   *         @arg @ref LL_EXTI_LINE_8
00378   *         @arg @ref LL_EXTI_LINE_9
00379   *         @arg @ref LL_EXTI_LINE_10
00380   *         @arg @ref LL_EXTI_LINE_11
00381   *         @arg @ref LL_EXTI_LINE_12
00382   *         @arg @ref LL_EXTI_LINE_13
00383   *         @arg @ref LL_EXTI_LINE_14
00384   *         @arg @ref LL_EXTI_LINE_15
00385   *         @arg @ref LL_EXTI_LINE_16
00386   *         @arg @ref LL_EXTI_LINE_17
00387   *         @arg @ref LL_EXTI_LINE_18
00388   *         @arg @ref LL_EXTI_LINE_19
00389   *         @arg @ref LL_EXTI_LINE_21
00390   *         @arg @ref LL_EXTI_LINE_23
00391   *         @arg @ref LL_EXTI_LINE_25
00392   *         @arg @ref LL_EXTI_LINE_26
00393   *         @arg @ref LL_EXTI_LINE_27
00394   *         @arg @ref LL_EXTI_LINE_28
00395   *         @arg @ref LL_EXTI_LINE_29
00396   *         @arg @ref LL_EXTI_LINE_30
00397   *         @arg @ref LL_EXTI_LINE_31
00398   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00399   * @note   Please check each device line mapping for EXTI Line availability
00400   * @retval None
00401   */
00402 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00403 {
00404   CLEAR_BIT(EXTI->IMR1, ExtiLine);
00405 }
00406
00407 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00408 /**
00409   * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
00410   * @note The reset value for the direct lines (lines 32 & 33)
00411   *       is set to 1 in order to enable the interrupt by default.
00412   *       Bits are set automatically at Power on.
00413   * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
00414   * @param  ExtiLine This parameter can be one of the following values:
00415   *         @arg @ref LL_EXTI_LINE_32
00416   *         @arg @ref LL_EXTI_LINE_33
00417   *         @arg @ref LL_EXTI_LINE_34
00418   *         @arg @ref LL_EXTI_LINE_35
00419   *         @arg @ref LL_EXTI_LINE_36
00420   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00421   * @note   Please check each device line mapping for EXTI Line availability
00422   * @retval None
00423   */
00424 __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
00425 {
00426   CLEAR_BIT(EXTI->IMR2, ExtiLine);
00427 }
00428 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00429
00430 /**
00431   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
00432   * @note The reset value for the direct or internal lines (see RM)
00433   *       is set to 1 in order to enable the interrupt by default.
00434   *       Bits are set automatically at Power on.
00435   * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
00436   * @param  ExtiLine This parameter can be one of the following values:
00437   *         @arg @ref LL_EXTI_LINE_0
00438   *         @arg @ref LL_EXTI_LINE_1
00439   *         @arg @ref LL_EXTI_LINE_2
00440   *         @arg @ref LL_EXTI_LINE_3
00441   *         @arg @ref LL_EXTI_LINE_4
00442   *         @arg @ref LL_EXTI_LINE_5
00443   *         @arg @ref LL_EXTI_LINE_6
00444   *         @arg @ref LL_EXTI_LINE_7
00445   *         @arg @ref LL_EXTI_LINE_8
00446   *         @arg @ref LL_EXTI_LINE_9
00447   *         @arg @ref LL_EXTI_LINE_10
00448   *         @arg @ref LL_EXTI_LINE_11
00449   *         @arg @ref LL_EXTI_LINE_12
00450   *         @arg @ref LL_EXTI_LINE_13
00451   *         @arg @ref LL_EXTI_LINE_14
00452   *         @arg @ref LL_EXTI_LINE_15
00453   *         @arg @ref LL_EXTI_LINE_16
00454   *         @arg @ref LL_EXTI_LINE_17
00455   *         @arg @ref LL_EXTI_LINE_18
00456   *         @arg @ref LL_EXTI_LINE_19
00457   *         @arg @ref LL_EXTI_LINE_21
00458   *         @arg @ref LL_EXTI_LINE_23
00459   *         @arg @ref LL_EXTI_LINE_25
00460   *         @arg @ref LL_EXTI_LINE_26
00461   *         @arg @ref LL_EXTI_LINE_27
00462   *         @arg @ref LL_EXTI_LINE_28
00463   *         @arg @ref LL_EXTI_LINE_29
00464   *         @arg @ref LL_EXTI_LINE_30
00465   *         @arg @ref LL_EXTI_LINE_31
00466   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00467   * @note   Please check each device line mapping for EXTI Line availability
00468   * @retval State of bit (1 or 0).
00469   */
00470 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00471 {
00472   return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00473 }
00474
00475 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00476 /**
00477   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
00478   * @note The reset value for the direct lines (lines 32 & 33)
00479   *       is set to 1 in order to enable the interrupt by default.
00480   * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
00481   * @param  ExtiLine This parameter can be one of the following values:
00482   *         @arg @ref LL_EXTI_LINE_32
00483   *         @arg @ref LL_EXTI_LINE_33
00484   *         @arg @ref LL_EXTI_LINE_34
00485   *         @arg @ref LL_EXTI_LINE_35
00486   *         @arg @ref LL_EXTI_LINE_36
00487   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00488   * @note   Please check each device line mapping for EXTI Line availability
00489   * @retval State of bit (1 or 0).
00490   */
00491 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
00492 {
00493   return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00494 }
00495 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00496
00497 /**
00498   * @}
00499   */
00500
00501 /** @defgroup EXTI_LL_EF_Event_Management Event_Management
00502   * @{
00503   */
00504
00505 /**
00506   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
00507   * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
00508   * @param  ExtiLine This parameter can be one of the following values:
00509   *         @arg @ref LL_EXTI_LINE_0
00510   *         @arg @ref LL_EXTI_LINE_1
00511   *         @arg @ref LL_EXTI_LINE_2
00512   *         @arg @ref LL_EXTI_LINE_3
00513   *         @arg @ref LL_EXTI_LINE_4
00514   *         @arg @ref LL_EXTI_LINE_5
00515   *         @arg @ref LL_EXTI_LINE_6
00516   *         @arg @ref LL_EXTI_LINE_7
00517   *         @arg @ref LL_EXTI_LINE_8
00518   *         @arg @ref LL_EXTI_LINE_9
00519   *         @arg @ref LL_EXTI_LINE_10
00520   *         @arg @ref LL_EXTI_LINE_11
00521   *         @arg @ref LL_EXTI_LINE_12
00522   *         @arg @ref LL_EXTI_LINE_13
00523   *         @arg @ref LL_EXTI_LINE_14
00524   *         @arg @ref LL_EXTI_LINE_15
00525   *         @arg @ref LL_EXTI_LINE_16
00526   *         @arg @ref LL_EXTI_LINE_17
00527   *         @arg @ref LL_EXTI_LINE_18
00528   *         @arg @ref LL_EXTI_LINE_19
00529   *         @arg @ref LL_EXTI_LINE_21
00530   *         @arg @ref LL_EXTI_LINE_23
00531   *         @arg @ref LL_EXTI_LINE_25
00532   *         @arg @ref LL_EXTI_LINE_26
00533   *         @arg @ref LL_EXTI_LINE_27
00534   *         @arg @ref LL_EXTI_LINE_28
00535   *         @arg @ref LL_EXTI_LINE_29
00536   *         @arg @ref LL_EXTI_LINE_30
00537   *         @arg @ref LL_EXTI_LINE_31
00538   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00539   * @note   Please check each device line mapping for EXTI Line availability
00540   * @retval None
00541   */
00542 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
00543 {
00544   SET_BIT(EXTI->EMR1, ExtiLine);
00545
00546 }
00547
00548 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00549 /**
00550   * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
00551   * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
00552   * @param  ExtiLine This parameter can be a combination of the following values:
00553   *         @arg @ref LL_EXTI_LINE_32
00554   *         @arg @ref LL_EXTI_LINE_33
00555   *         @arg @ref LL_EXTI_LINE_34
00556   *         @arg @ref LL_EXTI_LINE_35
00557   *         @arg @ref LL_EXTI_LINE_36
00558   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00559   * @note   Please check each device line mapping for EXTI Line availability
00560   * @retval None
00561   */
00562 __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
00563 {
00564   SET_BIT(EXTI->EMR2, ExtiLine);
00565 }
00566 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00567 /**
00568   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
00569   * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
00570   * @param  ExtiLine This parameter can be one of the following values:
00571   *         @arg @ref LL_EXTI_LINE_0
00572   *         @arg @ref LL_EXTI_LINE_1
00573   *         @arg @ref LL_EXTI_LINE_2
00574   *         @arg @ref LL_EXTI_LINE_3
00575   *         @arg @ref LL_EXTI_LINE_4
00576   *         @arg @ref LL_EXTI_LINE_5
00577   *         @arg @ref LL_EXTI_LINE_6
00578   *         @arg @ref LL_EXTI_LINE_7
00579   *         @arg @ref LL_EXTI_LINE_8
00580   *         @arg @ref LL_EXTI_LINE_9
00581   *         @arg @ref LL_EXTI_LINE_10
00582   *         @arg @ref LL_EXTI_LINE_11
00583   *         @arg @ref LL_EXTI_LINE_12
00584   *         @arg @ref LL_EXTI_LINE_13
00585   *         @arg @ref LL_EXTI_LINE_14
00586   *         @arg @ref LL_EXTI_LINE_15
00587   *         @arg @ref LL_EXTI_LINE_16
00588   *         @arg @ref LL_EXTI_LINE_17
00589   *         @arg @ref LL_EXTI_LINE_18
00590   *         @arg @ref LL_EXTI_LINE_19
00591   *         @arg @ref LL_EXTI_LINE_21
00592   *         @arg @ref LL_EXTI_LINE_23
00593   *         @arg @ref LL_EXTI_LINE_25
00594   *         @arg @ref LL_EXTI_LINE_26
00595   *         @arg @ref LL_EXTI_LINE_27
00596   *         @arg @ref LL_EXTI_LINE_28
00597   *         @arg @ref LL_EXTI_LINE_29
00598   *         @arg @ref LL_EXTI_LINE_30
00599   *         @arg @ref LL_EXTI_LINE_31
00600   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00601   * @note   Please check each device line mapping for EXTI Line availability
00602   * @retval None
00603   */
00604 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
00605 {
00606   CLEAR_BIT(EXTI->EMR1, ExtiLine);
00607 }
00608
00609 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00610 /**
00611   * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
00612   * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
00613   * @param  ExtiLine This parameter can be a combination of the following values:
00614   *         @arg @ref LL_EXTI_LINE_32
00615   *         @arg @ref LL_EXTI_LINE_33
00616   *         @arg @ref LL_EXTI_LINE_34
00617   *         @arg @ref LL_EXTI_LINE_35
00618   *         @arg @ref LL_EXTI_LINE_36
00619   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00620   * @note   Please check each device line mapping for EXTI Line availability
00621   * @retval None
00622   */
00623 __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
00624 {
00625   CLEAR_BIT(EXTI->EMR2, ExtiLine);
00626 }
00627 #endif
00628 /**
00629   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
00630   * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
00631   * @param  ExtiLine This parameter can be one of the following values:
00632   *         @arg @ref LL_EXTI_LINE_0
00633   *         @arg @ref LL_EXTI_LINE_1
00634   *         @arg @ref LL_EXTI_LINE_2
00635   *         @arg @ref LL_EXTI_LINE_3
00636   *         @arg @ref LL_EXTI_LINE_4
00637   *         @arg @ref LL_EXTI_LINE_5
00638   *         @arg @ref LL_EXTI_LINE_6
00639   *         @arg @ref LL_EXTI_LINE_7
00640   *         @arg @ref LL_EXTI_LINE_8
00641   *         @arg @ref LL_EXTI_LINE_9
00642   *         @arg @ref LL_EXTI_LINE_10
00643   *         @arg @ref LL_EXTI_LINE_11
00644   *         @arg @ref LL_EXTI_LINE_12
00645   *         @arg @ref LL_EXTI_LINE_13
00646   *         @arg @ref LL_EXTI_LINE_14
00647   *         @arg @ref LL_EXTI_LINE_15
00648   *         @arg @ref LL_EXTI_LINE_16
00649   *         @arg @ref LL_EXTI_LINE_17
00650   *         @arg @ref LL_EXTI_LINE_18
00651   *         @arg @ref LL_EXTI_LINE_19
00652   *         @arg @ref LL_EXTI_LINE_21
00653   *         @arg @ref LL_EXTI_LINE_23
00654   *         @arg @ref LL_EXTI_LINE_25
00655   *         @arg @ref LL_EXTI_LINE_26
00656   *         @arg @ref LL_EXTI_LINE_27
00657   *         @arg @ref LL_EXTI_LINE_28
00658   *         @arg @ref LL_EXTI_LINE_29
00659   *         @arg @ref LL_EXTI_LINE_30
00660   *         @arg @ref LL_EXTI_LINE_31
00661   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00662   * @note   Please check each device line mapping for EXTI Line availability
00663   * @retval State of bit (1 or 0).
00664   */
00665 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
00666 {
00667   return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00668 }
00669
00670 #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00671 /**
00672   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
00673   * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
00674   * @param  ExtiLine This parameter can be a combination of the following values:
00675   *         @arg @ref LL_EXTI_LINE_32
00676   *         @arg @ref LL_EXTI_LINE_33
00677   *         @arg @ref LL_EXTI_LINE_34
00678   *         @arg @ref LL_EXTI_LINE_35
00679   *         @arg @ref LL_EXTI_LINE_36
00680   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00681   * @note   Please check each device line mapping for EXTI Line availability
00682   * @retval State of bit (1 or 0).
00683   */
00684 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
00685 {
00686   return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00687 }
00688 #endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00689
00690 /**
00691   * @}
00692   */
00693
00694 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
00695   * @{
00696   */
00697
00698 /**
00699   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00700   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00701   *       generated on these lines. If a rising edge on a configurable interrupt
00702   *       line occurs during a write operation in the EXTI_RTSR register, the
00703   *       pending bit is not set.
00704   *       Rising and falling edge triggers can be set for
00705   *       the same interrupt line. In this case, both generate a trigger
00706   *       condition.
00707   * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
00708   * @param  ExtiLine This parameter can be a combination of the following values:
00709   *         @arg @ref LL_EXTI_LINE_0
00710   *         @arg @ref LL_EXTI_LINE_1
00711   *         @arg @ref LL_EXTI_LINE_2
00712   *         @arg @ref LL_EXTI_LINE_3
00713   *         @arg @ref LL_EXTI_LINE_4
00714   *         @arg @ref LL_EXTI_LINE_5
00715   *         @arg @ref LL_EXTI_LINE_6
00716   *         @arg @ref LL_EXTI_LINE_7
00717   *         @arg @ref LL_EXTI_LINE_8
00718   *         @arg @ref LL_EXTI_LINE_9
00719   *         @arg @ref LL_EXTI_LINE_10
00720   *         @arg @ref LL_EXTI_LINE_11
00721   *         @arg @ref LL_EXTI_LINE_12
00722   *         @arg @ref LL_EXTI_LINE_13
00723   *         @arg @ref LL_EXTI_LINE_14
00724   *         @arg @ref LL_EXTI_LINE_15
00725   *         @arg @ref LL_EXTI_LINE_16
00726   *         @arg @ref LL_EXTI_LINE_17
00727   *         @arg @ref LL_EXTI_LINE_18
00728   *         @arg @ref LL_EXTI_LINE_20
00729   * @note   Please check each device line mapping for EXTI Line availability
00730   * @retval None
00731   */
00732 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
00733 {
00734   SET_BIT(EXTI->RTSR1, ExtiLine);
00735
00736 }
00737 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00738 /**
00739   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00740   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00741   *       generated on these lines. If a rising edge on a configurable interrupt
00742   *       line occurs during a write operation in the EXTI_RTSR register, the
00743   *       pending bit is not set.
00744   *       Rising and falling edge triggers can be set for
00745   *       the same interrupt line. In this case, both generate a trigger
00746   *       condition.
00747   * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
00748   * @param  ExtiLine This parameter can be a combination of the following values:
00749   *         @arg @ref LL_EXTI_LINE_34
00750   * @note   Please check each device line mapping for EXTI Line availability
00751   * @retval None
00752   */
00753 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
00754 {
00755   SET_BIT(EXTI->RTSR2, ExtiLine);
00756
00757 }
00758 #endif /* STM32G0C1xx || STM32G0B1xx */
00759
00760 /**
00761   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00762   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00763   *       generated on these lines. If a rising edge on a configurable interrupt
00764   *       line occurs during a write operation in the EXTI_RTSR register, the
00765   *       pending bit is not set.
00766   *       Rising and falling edge triggers can be set for
00767   *       the same interrupt line. In this case, both generate a trigger
00768   *       condition.
00769   * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
00770   * @param  ExtiLine This parameter can be a combination of the following values:
00771   *         @arg @ref LL_EXTI_LINE_0
00772   *         @arg @ref LL_EXTI_LINE_1
00773   *         @arg @ref LL_EXTI_LINE_2
00774   *         @arg @ref LL_EXTI_LINE_3
00775   *         @arg @ref LL_EXTI_LINE_4
00776   *         @arg @ref LL_EXTI_LINE_5
00777   *         @arg @ref LL_EXTI_LINE_6
00778   *         @arg @ref LL_EXTI_LINE_7
00779   *         @arg @ref LL_EXTI_LINE_8
00780   *         @arg @ref LL_EXTI_LINE_9
00781   *         @arg @ref LL_EXTI_LINE_10
00782   *         @arg @ref LL_EXTI_LINE_11
00783   *         @arg @ref LL_EXTI_LINE_12
00784   *         @arg @ref LL_EXTI_LINE_13
00785   *         @arg @ref LL_EXTI_LINE_14
00786   *         @arg @ref LL_EXTI_LINE_15
00787   *         @arg @ref LL_EXTI_LINE_16
00788   *         @arg @ref LL_EXTI_LINE_17
00789   *         @arg @ref LL_EXTI_LINE_18
00790   *         @arg @ref LL_EXTI_LINE_20
00791   * @note   Please check each device line mapping for EXTI Line availability
00792   * @retval None
00793   */
00794 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
00795 {
00796   CLEAR_BIT(EXTI->RTSR1, ExtiLine);
00797
00798 }
00799
00800 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00801 /**
00802   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00803   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00804   *       generated on these lines. If a rising edge on a configurable interrupt
00805   *       line occurs during a write operation in the EXTI_RTSR register, the
00806   *       pending bit is not set.
00807   *       Rising and falling edge triggers can be set for
00808   *       the same interrupt line. In this case, both generate a trigger
00809   *       condition.
00810   * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
00811   * @param  ExtiLine This parameter can be a combination of the following values:
00812   *         @arg @ref LL_EXTI_LINE_34
00813   * @note   Please check each device line mapping for EXTI Line availability
00814   * @retval None
00815   */
00816 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
00817 {
00818   CLEAR_BIT(EXTI->RTSR2, ExtiLine);
00819
00820 }
00821 #endif /* STM32G0C1xx || STM32G0B1xx */
00822
00823 /**
00824   * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
00825   * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
00826   * @param  ExtiLine This parameter can be a combination of the following values:
00827   *         @arg @ref LL_EXTI_LINE_0
00828   *         @arg @ref LL_EXTI_LINE_1
00829   *         @arg @ref LL_EXTI_LINE_2
00830   *         @arg @ref LL_EXTI_LINE_3
00831   *         @arg @ref LL_EXTI_LINE_4
00832   *         @arg @ref LL_EXTI_LINE_5
00833   *         @arg @ref LL_EXTI_LINE_6
00834   *         @arg @ref LL_EXTI_LINE_7
00835   *         @arg @ref LL_EXTI_LINE_8
00836   *         @arg @ref LL_EXTI_LINE_9
00837   *         @arg @ref LL_EXTI_LINE_10
00838   *         @arg @ref LL_EXTI_LINE_11
00839   *         @arg @ref LL_EXTI_LINE_12
00840   *         @arg @ref LL_EXTI_LINE_13
00841   *         @arg @ref LL_EXTI_LINE_14
00842   *         @arg @ref LL_EXTI_LINE_15
00843   *         @arg @ref LL_EXTI_LINE_16
00844   *         @arg @ref LL_EXTI_LINE_17
00845   *         @arg @ref LL_EXTI_LINE_20
00846   * @note   Please check each device line mapping for EXTI Line availability
00847   * @retval State of bit (1 or 0).
00848   */
00849 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
00850 {
00851   return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00852 }
00853
00854 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00855 /**
00856   * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
00857   * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
00858   * @param  ExtiLine This parameter can be a combination of the following values:
00859   *         @arg @ref LL_EXTI_LINE_34
00860   * @note   Please check each device line mapping for EXTI Line availability
00861   * @retval State of bit (1 or 0).
00862   */
00863 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
00864 {
00865   return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00866 }
00867 #endif /* STM32G0C1xx || STM32G0B1xx */
00868
00869 /**
00870   * @}
00871   */
00872
00873 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
00874   * @{
00875   */
00876
00877 /**
00878   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00879   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00880   *       generated on these lines. If a falling edge on a configurable interrupt
00881   *       line occurs during a write operation in the EXTI_FTSR register, the
00882   *       pending bit is not set.
00883   *       Rising and falling edge triggers can be set for
00884   *       the same interrupt line. In this case, both generate a trigger
00885   *       condition.
00886   * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
00887   * @param  ExtiLine This parameter can be a combination of the following values:
00888   *         @arg @ref LL_EXTI_LINE_0
00889   *         @arg @ref LL_EXTI_LINE_1
00890   *         @arg @ref LL_EXTI_LINE_2
00891   *         @arg @ref LL_EXTI_LINE_3
00892   *         @arg @ref LL_EXTI_LINE_4
00893   *         @arg @ref LL_EXTI_LINE_5
00894   *         @arg @ref LL_EXTI_LINE_6
00895   *         @arg @ref LL_EXTI_LINE_7
00896   *         @arg @ref LL_EXTI_LINE_8
00897   *         @arg @ref LL_EXTI_LINE_9
00898   *         @arg @ref LL_EXTI_LINE_10
00899   *         @arg @ref LL_EXTI_LINE_11
00900   *         @arg @ref LL_EXTI_LINE_12
00901   *         @arg @ref LL_EXTI_LINE_13
00902   *         @arg @ref LL_EXTI_LINE_14
00903   *         @arg @ref LL_EXTI_LINE_15
00904   *         @arg @ref LL_EXTI_LINE_16
00905   *         @arg @ref LL_EXTI_LINE_17
00906   *         @arg @ref LL_EXTI_LINE_18
00907   *         @arg @ref LL_EXTI_LINE_20
00908   * @note   Please check each device line mapping for EXTI Line availability
00909   * @retval None
00910   */
00911 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
00912 {
00913   SET_BIT(EXTI->FTSR1, ExtiLine);
00914 }
00915
00916 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00917 /**
00918   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
00919   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00920   *       generated on these lines. If a falling edge on a configurable interrupt
00921   *       line occurs during a write operation in the EXTI_FTSR register, the
00922   *       pending bit is not set.
00923   *       Rising and falling edge triggers can be set for
00924   *       the same interrupt line. In this case, both generate a trigger
00925   *       condition.
00926   * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
00927   * @param  ExtiLine This parameter can be a combination of the following values:
00928   *         @arg @ref LL_EXTI_LINE_34
00929   * @note   Please check each device line mapping for EXTI Line availability
00930   * @retval None
00931   */
00932 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
00933 {
00934   SET_BIT(EXTI->FTSR2, ExtiLine);
00935 }
00936 #endif /* STM32G0C1xx || STM32G0B1xx */
00937
00938 /**
00939   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00940   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00941   *       generated on these lines. If a Falling edge on a configurable interrupt
00942   *       line occurs during a write operation in the EXTI_FTSR register, the
00943   *       pending bit is not set.
00944   *       Rising and falling edge triggers can be set for the same interrupt line.
00945   *       In this case, both generate a trigger condition.
00946   * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
00947   * @param  ExtiLine This parameter can be a combination of the following values:
00948   *         @arg @ref LL_EXTI_LINE_0
00949   *         @arg @ref LL_EXTI_LINE_1
00950   *         @arg @ref LL_EXTI_LINE_2
00951   *         @arg @ref LL_EXTI_LINE_3
00952   *         @arg @ref LL_EXTI_LINE_4
00953   *         @arg @ref LL_EXTI_LINE_5
00954   *         @arg @ref LL_EXTI_LINE_6
00955   *         @arg @ref LL_EXTI_LINE_7
00956   *         @arg @ref LL_EXTI_LINE_8
00957   *         @arg @ref LL_EXTI_LINE_9
00958   *         @arg @ref LL_EXTI_LINE_10
00959   *         @arg @ref LL_EXTI_LINE_11
00960   *         @arg @ref LL_EXTI_LINE_12
00961   *         @arg @ref LL_EXTI_LINE_13
00962   *         @arg @ref LL_EXTI_LINE_14
00963   *         @arg @ref LL_EXTI_LINE_15
00964   *         @arg @ref LL_EXTI_LINE_16
00965   *         @arg @ref LL_EXTI_LINE_17
00966   *         @arg @ref LL_EXTI_LINE_18
00967   *         @arg @ref LL_EXTI_LINE_20
00968   * @note   Please check each device line mapping for EXTI Line availability
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
00972 {
00973   CLEAR_BIT(EXTI->FTSR1, ExtiLine);
00974 }
00975
00976 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00977 /**
00978   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
00979   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00980   *       generated on these lines. If a Falling edge on a configurable interrupt
00981   *       line occurs during a write operation in the EXTI_FTSR register, the
00982   *       pending bit is not set.
00983   *       Rising and falling edge triggers can be set for the same interrupt line.
00984   *       In this case, both generate a trigger condition.
00985   * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
00986   * @param  ExtiLine This parameter can be a combination of the following values:
00987   *         @arg @ref LL_EXTI_LINE_34
00988   * @note   Please check each device line mapping for EXTI Line availability
00989   * @retval None
00990   */
00991 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
00992 {
00993   CLEAR_BIT(EXTI->FTSR2, ExtiLine);
00994 }
00995 #endif /* STM32G0C1xx || STM32G0B1xx */
00996
00997 /**
00998   * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
00999   * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
01000   * @param  ExtiLine This parameter can be a combination of the following values:
01001   *         @arg @ref LL_EXTI_LINE_0
01002   *         @arg @ref LL_EXTI_LINE_1
01003   *         @arg @ref LL_EXTI_LINE_2
01004   *         @arg @ref LL_EXTI_LINE_3
01005   *         @arg @ref LL_EXTI_LINE_4
01006   *         @arg @ref LL_EXTI_LINE_5
01007   *         @arg @ref LL_EXTI_LINE_6
01008   *         @arg @ref LL_EXTI_LINE_7
01009   *         @arg @ref LL_EXTI_LINE_8
01010   *         @arg @ref LL_EXTI_LINE_9
01011   *         @arg @ref LL_EXTI_LINE_10
01012   *         @arg @ref LL_EXTI_LINE_11
01013   *         @arg @ref LL_EXTI_LINE_12
01014   *         @arg @ref LL_EXTI_LINE_13
01015   *         @arg @ref LL_EXTI_LINE_14
01016   *         @arg @ref LL_EXTI_LINE_15
01017   *         @arg @ref LL_EXTI_LINE_16
01018   *         @arg @ref LL_EXTI_LINE_17
01019   *         @arg @ref LL_EXTI_LINE_18
01020   *         @arg @ref LL_EXTI_LINE_20
01021   * @note   Please check each device line mapping for EXTI Line availability
01022   * @retval State of bit (1 or 0).
01023   */
01024 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
01025 {
01026   return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01027 }
01028
01029 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
01030 /**
01031   * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
01032   * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
01033   * @param  ExtiLine This parameter can be a combination of the following values:
01034   *         @arg @ref LL_EXTI_LINE_34
01035   * @note   Please check each device line mapping for EXTI Line availability
01036   * @retval State of bit (1 or 0).
01037   */
01038 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
01039 {
01040   return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01041 }
01042 #endif /* STM32G0C1xx || STM32G0B1xx */
01043 /**
01044   * @}
01045   */
01046
01047 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
01048   * @{
01049   */
01050
01051 /**
01052   * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
01053   * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
01054   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
01055   *       resulting in an interrupt request generation.
01056   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
01057   *       register (by writing a 1 into the bit)
01058   * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
01059   * @param  ExtiLine This parameter can be a combination of the following values:
01060   *         @arg @ref LL_EXTI_LINE_0
01061   *         @arg @ref LL_EXTI_LINE_1
01062   *         @arg @ref LL_EXTI_LINE_2
01063   *         @arg @ref LL_EXTI_LINE_3
01064   *         @arg @ref LL_EXTI_LINE_4
01065   *         @arg @ref LL_EXTI_LINE_5
01066   *         @arg @ref LL_EXTI_LINE_6
01067   *         @arg @ref LL_EXTI_LINE_7
01068   *         @arg @ref LL_EXTI_LINE_8
01069   *         @arg @ref LL_EXTI_LINE_9
01070   *         @arg @ref LL_EXTI_LINE_10
01071   *         @arg @ref LL_EXTI_LINE_11
01072   *         @arg @ref LL_EXTI_LINE_12
01073   *         @arg @ref LL_EXTI_LINE_13
01074   *         @arg @ref LL_EXTI_LINE_14
01075   *         @arg @ref LL_EXTI_LINE_15
01076   *         @arg @ref LL_EXTI_LINE_16
01077   *         @arg @ref LL_EXTI_LINE_17
01078   *         @arg @ref LL_EXTI_LINE_18
01079   *         @arg @ref LL_EXTI_LINE_20
01080   * @note   Please check each device line mapping for EXTI Line availability
01081   * @retval None
01082   */
01083 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
01084 {
01085   SET_BIT(EXTI->SWIER1, ExtiLine);
01086 }
01087
01088 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
01089 /**
01090   * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
01091   * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
01092   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
01093   *       resulting in an interrupt request generation.
01094   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
01095   *       register (by writing a 1 into the bit)
01096   * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
01097   * @param  ExtiLine This parameter can be a combination of the following values:
01098   *         @arg @ref LL_EXTI_LINE_34
01099   * @note   Please check each device line mapping for EXTI Line availability
01100   * @retval None
01101   */
01102 __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
01103 {
01104   SET_BIT(EXTI->SWIER2, ExtiLine);
01105 }
01106 #endif /* STM32G0C1xx || STM32G0B1xx */
01107
01108 /**
01109   * @}
01110   */
01111
01112 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
01113   * @{
01114   */
01115
01116 /**
01117   * @brief  Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31
01118   * @note This bit is set when the falling edge event arrives on the interrupt
01119   *       line. This bit is cleared by writing a 1 to the bit.
01120   * @rmtoll FPR1          FPIFx           LL_EXTI_IsActiveFallingFlag_0_31
01121   * @param  ExtiLine This parameter can be a combination of the following values:
01122   *         @arg @ref LL_EXTI_LINE_0
01123   *         @arg @ref LL_EXTI_LINE_1
01124   *         @arg @ref LL_EXTI_LINE_2
01125   *         @arg @ref LL_EXTI_LINE_3
01126   *         @arg @ref LL_EXTI_LINE_4
01127   *         @arg @ref LL_EXTI_LINE_5
01128   *         @arg @ref LL_EXTI_LINE_6
01129   *         @arg @ref LL_EXTI_LINE_7
01130   *         @arg @ref LL_EXTI_LINE_8
01131   *         @arg @ref LL_EXTI_LINE_9
01132   *         @arg @ref LL_EXTI_LINE_10
01133   *         @arg @ref LL_EXTI_LINE_11
01134   *         @arg @ref LL_EXTI_LINE_12
01135   *         @arg @ref LL_EXTI_LINE_13
01136   *         @arg @ref LL_EXTI_LINE_14
01137   *         @arg @ref LL_EXTI_LINE_15
01138   *         @arg @ref LL_EXTI_LINE_16
01139   *         @arg @ref LL_EXTI_LINE_17
01140   *         @arg @ref LL_EXTI_LINE_18
01141   *         @arg @ref LL_EXTI_LINE_20
01142   * @note   Please check each device line mapping for EXTI Line availability
01143   * @retval State of bit (1 or 0).
01144   */
01145 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine)
01146 {
01147   return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01148 }
01149
01150 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
01151 /**
01152   * @brief  Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63
01153   * @note This bit is set when the falling edge event arrives on the interrupt
01154   *       line. This bit is cleared by writing a 1 to the bit.
01155   * @rmtoll FPR2          FPIFx           LL_EXTI_IsActiveFallingFlag_32_63
01156   * @param  ExtiLine This parameter can be a combination of the following values:
01157   *         @arg @ref LL_EXTI_LINE_34
01158   * @note   Please check each device line mapping for EXTI Line availability
01159   * @retval State of bit (1 or 0).
01160   */
01161 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine)
01162 {
01163   return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01164 }
01165 #endif /* STM32G0C1xx || STM32G0B1xx */
01166
01167 /**
01168   * @brief  Read ExtLine Combination Falling Flag for Lines in range 0 to 31
01169   * @note This bit is set when the falling edge event arrives on the interrupt
01170   *       line. This bit is cleared by writing a 1 to the bit.
01171   * @rmtoll FPR1          FPIFx           LL_EXTI_ReadFallingFlag_0_31
01172   * @param  ExtiLine This parameter can be a combination of the following values:
01173   *         @arg @ref LL_EXTI_LINE_0
01174   *         @arg @ref LL_EXTI_LINE_1
01175   *         @arg @ref LL_EXTI_LINE_2
01176   *         @arg @ref LL_EXTI_LINE_3
01177   *         @arg @ref LL_EXTI_LINE_4
01178   *         @arg @ref LL_EXTI_LINE_5
01179   *         @arg @ref LL_EXTI_LINE_6
01180   *         @arg @ref LL_EXTI_LINE_7
01181   *         @arg @ref LL_EXTI_LINE_8
01182   *         @arg @ref LL_EXTI_LINE_9
01183   *         @arg @ref LL_EXTI_LINE_10
01184   *         @arg @ref LL_EXTI_LINE_11
01185   *         @arg @ref LL_EXTI_LINE_12
01186   *         @arg @ref LL_EXTI_LINE_13
01187   *         @arg @ref LL_EXTI_LINE_14
01188   *         @arg @ref LL_EXTI_LINE_15
01189   *         @arg @ref LL_EXTI_LINE_16
01190   *         @arg @ref LL_EXTI_LINE_17
01191   *         @arg @ref LL_EXTI_LINE_18
01192   *         @arg @ref LL_EXTI_LINE_20
01193   * @note   Please check each device line mapping for EXTI Line availability
01194   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01195   */
01196 __STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine)
01197 {
01198   return (READ_BIT(EXTI->FPR1, ExtiLine));
01199 }
01200
01201 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
01202 /**
01203   * @brief  Read ExtLine Combination Falling Flag for Lines in range 32 to 63
01204   * @note This bit is set when the falling edge event arrives on the interrupt
01205   *       line. This bit is cleared by writing a 1 to the bit.
01206   * @rmtoll FPR2          FPIFx           LL_EXTI_ReadFallingFlag_32_63
01207   * @param  ExtiLine This parameter can be a combination of the following values:
01208   *         @arg @ref LL_EXTI_LINE_34
01209   * @note   Please check each device line mapping for EXTI Line availability
01210   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01211   */
01212 __STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine)
01213 {
01214   return (READ_BIT(EXTI->FPR2, ExtiLine));
01215 }
01216 #endif /* STM32G0C1xx || STM32G0B1xx */
01217
01218 /**
01219   * @brief  Clear ExtLine Falling Flags  for Lines in range 0 to 31
01220   * @note This bit is set when the falling edge event arrives on the interrupt
01221   *       line. This bit is cleared by writing a 1 to the bit.
01222   * @rmtoll FPR1          FPIFx           LL_EXTI_ClearFallingFlag_0_31
01223   * @param  ExtiLine This parameter can be a combination of the following values:
01224   *         @arg @ref LL_EXTI_LINE_0
01225   *         @arg @ref LL_EXTI_LINE_1
01226   *         @arg @ref LL_EXTI_LINE_2
01227   *         @arg @ref LL_EXTI_LINE_3
01228   *         @arg @ref LL_EXTI_LINE_4
01229   *         @arg @ref LL_EXTI_LINE_5
01230   *         @arg @ref LL_EXTI_LINE_6
01231   *         @arg @ref LL_EXTI_LINE_7
01232   *         @arg @ref LL_EXTI_LINE_8
01233   *         @arg @ref LL_EXTI_LINE_9
01234   *         @arg @ref LL_EXTI_LINE_10
01235   *         @arg @ref LL_EXTI_LINE_11
01236   *         @arg @ref LL_EXTI_LINE_12
01237   *         @arg @ref LL_EXTI_LINE_13
01238   *         @arg @ref LL_EXTI_LINE_14
01239   *         @arg @ref LL_EXTI_LINE_15
01240   *         @arg @ref LL_EXTI_LINE_16
01241   *         @arg @ref LL_EXTI_LINE_17
01242   *         @arg @ref LL_EXTI_LINE_18
01243   *         @arg @ref LL_EXTI_LINE_20
01244   * @note   Please check each device line mapping for EXTI Line availability
01245   * @retval None
01246   */
01247 __STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine)
01248 {
01249   WRITE_REG(EXTI->FPR1, ExtiLine);
01250 }
01251
01252 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
01253 /**
01254   * @brief  Clear ExtLine Falling Flags  for Lines in range 32 to 63
01255   * @note This bit is set when the falling edge event arrives on the interrupt
01256   *       line. This bit is cleared by writing a 1 to the bit.
01257   * @rmtoll FPR2          FPIFx           LL_EXTI_ClearFallingFlag_32_63
01258   * @param  ExtiLine This parameter can be a combination of the following values:
01259   *         @arg @ref LL_EXTI_LINE_34
01260   * @note   Please check each device line mapping for EXTI Line availability
01261   * @retval None
01262   */
01263 __STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine)
01264 {
01265   WRITE_REG(EXTI->FPR2, ExtiLine);
01266 }
01267 #endif /* STM32G0C1xx || STM32G0B1xx */
01268
01269 /**
01270   * @brief  Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31
01271   * @note This bit is set when the Rising edge event arrives on the interrupt
01272   *       line. This bit is cleared by writing a 1 to the bit.
01273   * @rmtoll RPR1          RPIFx           LL_EXTI_IsActiveRisingFlag_0_31
01274   * @param  ExtiLine This parameter can be a combination of the following values:
01275   *         @arg @ref LL_EXTI_LINE_0
01276   *         @arg @ref LL_EXTI_LINE_1
01277   *         @arg @ref LL_EXTI_LINE_2
01278   *         @arg @ref LL_EXTI_LINE_3
01279   *         @arg @ref LL_EXTI_LINE_4
01280   *         @arg @ref LL_EXTI_LINE_5
01281   *         @arg @ref LL_EXTI_LINE_6
01282   *         @arg @ref LL_EXTI_LINE_7
01283   *         @arg @ref LL_EXTI_LINE_8
01284   *         @arg @ref LL_EXTI_LINE_9
01285   *         @arg @ref LL_EXTI_LINE_10
01286   *         @arg @ref LL_EXTI_LINE_11
01287   *         @arg @ref LL_EXTI_LINE_12
01288   *         @arg @ref LL_EXTI_LINE_13
01289   *         @arg @ref LL_EXTI_LINE_14
01290   *         @arg @ref LL_EXTI_LINE_15
01291   *         @arg @ref LL_EXTI_LINE_16
01292   *         @arg @ref LL_EXTI_LINE_17
01293   *         @arg @ref LL_EXTI_LINE_18
01294   *         @arg @ref LL_EXTI_LINE_20
01295   * @note   Please check each device line mapping for EXTI Line availability
01296   * @retval State of bit (1 or 0).
01297   */
01298 __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine)
01299 {
01300   return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01301 }
01302
01303 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
01304 /**
01305   * @brief  Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63
01306   * @note This bit is set when the Rising edge event arrives on the interrupt
01307   *       line. This bit is cleared by writing a 1 to the bit.
01308   * @rmtoll RPR2          RPIFx           LL_EXTI_IsActiveRisingFlag_32_63
01309   * @param  ExtiLine This parameter can be a combination of the following values:
01310   *         @arg @ref LL_EXTI_LINE_34
01311   * @note   Please check each device line mapping for EXTI Line availability
01312   * @retval State of bit (1 or 0).
01313   */
01314 __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine)
01315 {
01316   return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01317 }
01318 #endif /* STM32G0C1xx || STM32G0B1xx */
01319
01320 /**
01321   * @brief  Read ExtLine Combination Rising Flag for Lines in range 0 to 31
01322   * @note This bit is set when the Rising edge event arrives on the interrupt
01323   *       line. This bit is cleared by writing a 1 to the bit.
01324   * @rmtoll RPR1          RPIFx           LL_EXTI_ReadRisingFlag_0_31
01325   * @param  ExtiLine This parameter can be a combination of the following values:
01326   *         @arg @ref LL_EXTI_LINE_0
01327   *         @arg @ref LL_EXTI_LINE_1
01328   *         @arg @ref LL_EXTI_LINE_2
01329   *         @arg @ref LL_EXTI_LINE_3
01330   *         @arg @ref LL_EXTI_LINE_4
01331   *         @arg @ref LL_EXTI_LINE_5
01332   *         @arg @ref LL_EXTI_LINE_6
01333   *         @arg @ref LL_EXTI_LINE_7
01334   *         @arg @ref LL_EXTI_LINE_8
01335   *         @arg @ref LL_EXTI_LINE_9
01336   *         @arg @ref LL_EXTI_LINE_10
01337   *         @arg @ref LL_EXTI_LINE_11
01338   *         @arg @ref LL_EXTI_LINE_12
01339   *         @arg @ref LL_EXTI_LINE_13
01340   *         @arg @ref LL_EXTI_LINE_14
01341   *         @arg @ref LL_EXTI_LINE_15
01342   *         @arg @ref LL_EXTI_LINE_16
01343   *         @arg @ref LL_EXTI_LINE_17
01344   *         @arg @ref LL_EXTI_LINE_18
01345   *         @arg @ref LL_EXTI_LINE_20
01346   * @note   Please check each device line mapping for EXTI Line availability
01347   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01348   */
01349 __STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine)
01350 {
01351   return (READ_BIT(EXTI->RPR1, ExtiLine));
01352 }
01353
01354 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
01355 /**
01356   * @brief  Read ExtLine Combination Rising Flag for Lines in range 32 to 63
01357   * @note This bit is set when the Rising edge event arrives on the interrupt
01358   *       line. This bit is cleared by writing a 1 to the bit.
01359   * @rmtoll RPR2          RPIFx           LL_EXTI_ReadRisingFlag_32_63
01360   * @param  ExtiLine This parameter can be a combination of the following values:
01361   *         @arg @ref LL_EXTI_LINE_34
01362   * @note   Please check each device line mapping for EXTI Line availability
01363   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01364   */
01365 __STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine)
01366 {
01367   return (READ_BIT(EXTI->RPR2, ExtiLine));
01368 }
01369 #endif /* STM32G0C1xx || STM32G0B1xx */
01370
01371 /**
01372   * @brief  Clear ExtLine Rising Flags  for Lines in range 0 to 31
01373   * @note This bit is set when the Rising edge event arrives on the interrupt
01374   *       line. This bit is cleared by writing a 1 to the bit.
01375   * @rmtoll RPR1          RPIFx           LL_EXTI_ClearRisingFlag_0_31
01376   * @param  ExtiLine This parameter can be a combination of the following values:
01377   *         @arg @ref LL_EXTI_LINE_0
01378   *         @arg @ref LL_EXTI_LINE_1
01379   *         @arg @ref LL_EXTI_LINE_2
01380   *         @arg @ref LL_EXTI_LINE_3
01381   *         @arg @ref LL_EXTI_LINE_4
01382   *         @arg @ref LL_EXTI_LINE_5
01383   *         @arg @ref LL_EXTI_LINE_6
01384   *         @arg @ref LL_EXTI_LINE_7
01385   *         @arg @ref LL_EXTI_LINE_8
01386   *         @arg @ref LL_EXTI_LINE_9
01387   *         @arg @ref LL_EXTI_LINE_10
01388   *         @arg @ref LL_EXTI_LINE_11
01389   *         @arg @ref LL_EXTI_LINE_12
01390   *         @arg @ref LL_EXTI_LINE_13
01391   *         @arg @ref LL_EXTI_LINE_14
01392   *         @arg @ref LL_EXTI_LINE_15
01393   *         @arg @ref LL_EXTI_LINE_16
01394   *         @arg @ref LL_EXTI_LINE_17
01395   *         @arg @ref LL_EXTI_LINE_18
01396   *         @arg @ref LL_EXTI_LINE_20
01397   * @note   Please check each device line mapping for EXTI Line availability
01398   * @retval None
01399   */
01400 __STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine)
01401 {
01402   WRITE_REG(EXTI->RPR1, ExtiLine);
01403 }
01404
01405 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
01406 /**
01407   * @brief  Clear ExtLine Rising Flags  for Lines in range 32 to 63
01408   * @note This bit is set when the Rising edge event arrives on the interrupt
01409   *       line. This bit is cleared by writing a 1 to the bit.
01410   * @rmtoll RPR2          RPIFx           LL_EXTI_ClearRisingFlag_32_63
01411   * @param  ExtiLine This parameter can be a combination of the following values:
01412   *         @arg @ref LL_EXTI_LINE_34
01413   * @note   Please check each device line mapping for EXTI Line availability
01414   * @retval None
01415   */
01416 __STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine)
01417 {
01418   WRITE_REG(EXTI->RPR2, ExtiLine);
01419 }
01420 #endif /* STM32G0C1xx || STM32G0B1xx */
01421
01422 /**
01423   * @}
01424   */
01425 /** @defgroup EXTI_LL_EF_Config EF configuration functions
01426   * @{
01427   */
01428
01429 /**
01430   * @brief  Configure source input for the EXTI external interrupt.
01431   * @rmtoll EXTI_EXTICR1 EXTI0         LL_EXTI_SetEXTISource\n
01432   *         EXTI_EXTICR1 EXTI1         LL_EXTI_SetEXTISource\n
01433   *         EXTI_EXTICR1 EXTI2         LL_EXTI_SetEXTISource\n
01434   *         EXTI_EXTICR1 EXTI3         LL_EXTI_SetEXTISource\n
01435   *         EXTI_EXTICR2 EXTI4         LL_EXTI_SetEXTISource\n
01436   *         EXTI_EXTICR2 EXTI5         LL_EXTI_SetEXTISource\n
01437   *         EXTI_EXTICR2 EXTI6         LL_EXTI_SetEXTISource\n
01438   *         EXTI_EXTICR2 EXTI7         LL_EXTI_SetEXTISource\n
01439   *         EXTI_EXTICR3 EXTI8         LL_EXTI_SetEXTISource\n
01440   *         EXTI_EXTICR3 EXTI9         LL_EXTI_SetEXTISource\n
01441   *         EXTI_EXTICR3 EXTI10        LL_EXTI_SetEXTISource\n
01442   *         EXTI_EXTICR3 EXTI11        LL_EXTI_SetEXTISource\n
01443   *         EXTI_EXTICR4 EXTI12        LL_EXTI_SetEXTISource\n
01444   *         EXTI_EXTICR4 EXTI13        LL_EXTI_SetEXTISource\n
01445   *         EXTI_EXTICR4 EXTI14        LL_EXTI_SetEXTISource\n
01446   *         EXTI_EXTICR4 EXTI15        LL_EXTI_SetEXTISource
01447   * @param  Port This parameter can be one of the following values:
01448   *         @arg @ref EXTI_LL_EC_CONFIG_PORT
01449   *
01450   *         (*) value not defined in all devices
01451   * @param  Line This parameter can be one of the following values:
01452   *         @arg @ref LL_EXTI_CONFIG_LINE0
01453   *         @arg @ref LL_EXTI_CONFIG_LINE1
01454   *         @arg @ref LL_EXTI_CONFIG_LINE2
01455   *         @arg @ref LL_EXTI_CONFIG_LINE3
01456   *         @arg @ref LL_EXTI_CONFIG_LINE4
01457   *         @arg @ref LL_EXTI_CONFIG_LINE5
01458   *         @arg @ref LL_EXTI_CONFIG_LINE6
01459   *         @arg @ref LL_EXTI_CONFIG_LINE7
01460   *         @arg @ref LL_EXTI_CONFIG_LINE8
01461   *         @arg @ref LL_EXTI_CONFIG_LINE9
01462   *         @arg @ref LL_EXTI_CONFIG_LINE10
01463   *         @arg @ref LL_EXTI_CONFIG_LINE11
01464   *         @arg @ref LL_EXTI_CONFIG_LINE12
01465   *         @arg @ref LL_EXTI_CONFIG_LINE13
01466   *         @arg @ref LL_EXTI_CONFIG_LINE14
01467   *         @arg @ref LL_EXTI_CONFIG_LINE15
01468   * @retval None
01469   */
01470 __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line)
01471 {
01472   MODIFY_REG(EXTI->EXTICR[Line & 0x03u], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
01473 }
01474
01475 /**
01476   * @brief  Get the configured defined for specific EXTI Line
01477   * @rmtoll EXTI_EXTICR1 EXTI0         LL_EXTI_SetEXTISource\n
01478   *         EXTI_EXTICR1 EXTI1         LL_EXTI_SetEXTISource\n
01479   *         EXTI_EXTICR1 EXTI2         LL_EXTI_SetEXTISource\n
01480   *         EXTI_EXTICR1 EXTI3         LL_EXTI_SetEXTISource\n
01481   *         EXTI_EXTICR2 EXTI4         LL_EXTI_SetEXTISource\n
01482   *         EXTI_EXTICR2 EXTI5         LL_EXTI_SetEXTISource\n
01483   *         EXTI_EXTICR2 EXTI6         LL_EXTI_SetEXTISource\n
01484   *         EXTI_EXTICR2 EXTI7         LL_EXTI_SetEXTISource\n
01485   *         EXTI_EXTICR3 EXTI8         LL_EXTI_SetEXTISource\n
01486   *         EXTI_EXTICR3 EXTI9         LL_EXTI_SetEXTISource\n
01487   *         EXTI_EXTICR3 EXTI10        LL_EXTI_SetEXTISource\n
01488   *         EXTI_EXTICR3 EXTI11        LL_EXTI_SetEXTISource\n
01489   *         EXTI_EXTICR4 EXTI12        LL_EXTI_SetEXTISource\n
01490   *         EXTI_EXTICR4 EXTI13        LL_EXTI_SetEXTISource\n
01491   *         EXTI_EXTICR4 EXTI14        LL_EXTI_SetEXTISource\n
01492   *         EXTI_EXTICR4 EXTI15        LL_EXTI_SetEXTISource
01493   * @param  Line This parameter can be one of the following values:
01494   *         @arg @ref LL_EXTI_CONFIG_LINE0
01495   *         @arg @ref LL_EXTI_CONFIG_LINE1
01496   *         @arg @ref LL_EXTI_CONFIG_LINE2
01497   *         @arg @ref LL_EXTI_CONFIG_LINE3
01498   *         @arg @ref LL_EXTI_CONFIG_LINE4
01499   *         @arg @ref LL_EXTI_CONFIG_LINE5
01500   *         @arg @ref LL_EXTI_CONFIG_LINE6
01501   *         @arg @ref LL_EXTI_CONFIG_LINE7
01502   *         @arg @ref LL_EXTI_CONFIG_LINE8
01503   *         @arg @ref LL_EXTI_CONFIG_LINE9
01504   *         @arg @ref LL_EXTI_CONFIG_LINE10
01505   *         @arg @ref LL_EXTI_CONFIG_LINE11
01506   *         @arg @ref LL_EXTI_CONFIG_LINE12
01507   *         @arg @ref LL_EXTI_CONFIG_LINE13
01508   *         @arg @ref LL_EXTI_CONFIG_LINE14
01509   *         @arg @ref LL_EXTI_CONFIG_LINE15
01510   * @retval Returned value can be one of the following values:
01511   *         @arg @ref EXTI_LL_EC_CONFIG_PORT
01512   *
01513   *         (*) value not defined in all devices
01514   */
01515 __STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line)
01516 {
01517   return (READ_BIT(EXTI->EXTICR[Line & 0x03u], (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
01518 }
01519 /**
01520   * @}
01521   */
01522
01523 #if defined(USE_FULL_LL_DRIVER)
01524 /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
01525   * @{
01526   */
01527
01528 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01529 uint32_t LL_EXTI_DeInit(void);
01530 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01531
01532
01533 /**
01534   * @}
01535   */
01536 #endif /* USE_FULL_LL_DRIVER */
01537
01538 /**
01539   * @}
01540   */
01541
01542 /**
01543   * @}
01544   */
01545
01546 #endif /* EXTI */
01547
01548 /**
01549   * @}
01550   */
01551
01552 #ifdef __cplusplus
01553 }
01554 #endif
01555
01556 #endif /* STM32G0xx_LL_EXTI_H */
01557
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_gpio.c Source File

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stm32g0xx_ll_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_gpio.h"
00022 #include "stm32g0xx_ll_bus.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G0xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
00034
00035 /** @addtogroup GPIO_LL
00036   * @{
00037   */
00038 /** MISRA C:2012 deviation rule has been granted for following rules:
00039   * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
00040   * range of the shift operator in following API :
00041   * LL_GPIO_Init
00042   */
00043
00044 /* Private types -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 /* Private constants ---------------------------------------------------------*/
00047 /* Private macros ------------------------------------------------------------*/
00048 /** @addtogroup GPIO_LL_Private_Macros
00049   * @{
00050   */
00051 #define IS_LL_GPIO_PIN(__VALUE__)          (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
00052
00053 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
00054                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
00055                                             ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
00056                                             ((__VALUE__) == LL_GPIO_MODE_ANALOG))
00057
00058 #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
00059                                             ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
00060
00061 #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
00062                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
00063                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
00064                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
00065
00066 #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
00067                                             ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
00068                                             ((__VALUE__) == LL_GPIO_PULL_DOWN))
00069
00070 #if defined(GPIOE)
00071 #define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
00072                                             ((__VALUE__) == LL_GPIO_AF_1  )   ||\
00073                                             ((__VALUE__) == LL_GPIO_AF_2  )   ||\
00074                                             ((__VALUE__) == LL_GPIO_AF_3  )   ||\
00075                                             ((__VALUE__) == LL_GPIO_AF_4  )   ||\
00076                                             ((__VALUE__) == LL_GPIO_AF_5  )   ||\
00077                                             ((__VALUE__) == LL_GPIO_AF_6  )   ||\
00078                                             ((__VALUE__) == LL_GPIO_AF_7  )   ||\
00079                                             ((__VALUE__) == LL_GPIO_AF_8  )   ||\
00080                                             ((__VALUE__) == LL_GPIO_AF_9  )   ||\
00081                                             ((__VALUE__) == LL_GPIO_AF_10 ))
00082 #else
00083 #define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
00084                                             ((__VALUE__) == LL_GPIO_AF_1  )   ||\
00085                                             ((__VALUE__) == LL_GPIO_AF_2  )   ||\
00086                                             ((__VALUE__) == LL_GPIO_AF_3  )   ||\
00087                                             ((__VALUE__) == LL_GPIO_AF_4  )   ||\
00088                                             ((__VALUE__) == LL_GPIO_AF_5  )   ||\
00089                                             ((__VALUE__) == LL_GPIO_AF_6  )   ||\
00090                                             ((__VALUE__) == LL_GPIO_AF_7 ))
00091 #endif /* GPIOE */
00092 /**
00093   * @}
00094   */
00095
00096 /* Private function prototypes -----------------------------------------------*/
00097
00098 /* Exported functions --------------------------------------------------------*/
00099 /** @addtogroup GPIO_LL_Exported_Functions
00100   * @{
00101   */
00102
00103 /** @addtogroup GPIO_LL_EF_Init
00104   * @{
00105   */
00106
00107 /**
00108   * @brief  De-initialize GPIO registers (Registers restored to their default values).
00109   * @param  GPIOx GPIO Port
00110   * @retval An ErrorStatus enumeration value:
00111   *          - SUCCESS: GPIO registers are de-initialized
00112   *          - ERROR:   Wrong GPIO Port
00113   */
00114 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
00115 {
00116   ErrorStatus status = SUCCESS;
00117
00118   /* Check the parameters */
00119   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00120
00121   /* Force and Release reset on clock of GPIOx Port */
00122   if (GPIOx == GPIOA)
00123   {
00124     LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA);
00125     LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA);
00126   }
00127   else if (GPIOx == GPIOB)
00128   {
00129     LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB);
00130     LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB);
00131   }
00132   else if (GPIOx == GPIOC)
00133   {
00134     LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOC);
00135     LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOC);
00136   }
00137 #if defined(GPIOD)
00138   else if (GPIOx == GPIOD)
00139   {
00140     LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOD);
00141     LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD);
00142   }
00143 #endif /* GPIOD */
00144 #if defined(GPIOE)
00145   else if (GPIOx == GPIOE)
00146   {
00147     LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOE);
00148     LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOE);
00149   }
00150 #endif /* GPIOE */
00151 #if defined(GPIOF)
00152   else if (GPIOx == GPIOF)
00153   {
00154     LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOF);
00155     LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOF);
00156   }
00157 #endif /* GPIOF */
00158   else
00159   {
00160     status = ERROR;
00161   }
00162
00163   return (status);
00164 }
00165
00166 /**
00167   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
00168   * @param  GPIOx GPIO Port
00169   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00170   *         that contains the configuration information for the specified GPIO peripheral.
00171   * @retval An ErrorStatus enumeration value:
00172   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
00173   *          - ERROR:   Not applicable
00174   */
00175 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
00176 {
00177   uint32_t pinpos;
00178   uint32_t currentpin;
00179
00180   /* Check the parameters */
00181   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00182   assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
00183   assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
00184   assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
00185
00186   /* ------------------------- Configure the port pins ---------------- */
00187   /* Initialize  pinpos on first pin set */
00188   pinpos = 0;
00189
00190   /* Configure the port pins */
00191   while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
00192   {
00193     /* Get current io position */
00194     currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
00195
00196     if (currentpin != 0x00u)
00197     {
00198       if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00199       {
00200         /* Check Speed mode parameters */
00201         assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
00202
00203         /* Speed mode configuration */
00204         LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
00205
00206         /* Check Output mode parameters */
00207         assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
00208
00209         /* Output mode configuration*/
00210         LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
00211       }
00212
00213       /* Pull-up Pull down resistor configuration*/
00214       LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
00215
00216       if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
00217       {
00218         /* Check Alternate parameter */
00219         assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
00220
00221         /* Speed mode configuration */
00222         if (currentpin < LL_GPIO_PIN_8)
00223         {
00224           LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00225         }
00226         else
00227         {
00228           LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00229         }
00230       }
00231
00232       /* Pin Mode configuration */
00233       LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
00234     }
00235     pinpos++;
00236   }
00237
00238   return (SUCCESS);
00239 }
00240
00241 /**
00242   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
00243   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00244   *                          whose fields will be set to default values.
00245   * @retval None
00246   */
00247
00248 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
00249 {
00250   /* Reset GPIO init structure parameters values */
00251   GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
00252   GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
00253   GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
00254   GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
00255   GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
00256   GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
00257 }
00258
00259 /**
00260   * @}
00261   */
00262
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
00272
00273 /**
00274   * @}
00275   */
00276
00277 #endif /* USE_FULL_LL_DRIVER */
00278
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_gpio.h Source File

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stm32g0xx_ll_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_GPIO_H
00021 #define STM32G0xx_LL_GPIO_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
00035
00036 /** @defgroup GPIO_LL GPIO
00037   * @{
00038   */
00039 /** MISRA C:2012 deviation rule has been granted for following rules:
00040   * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
00041   * which may be out of array bounds [..,UNKNOWN] in following APIs:
00042   * LL_GPIO_GetAFPin_0_7
00043   * LL_GPIO_SetAFPin_0_7
00044   * LL_GPIO_SetAFPin_8_15
00045   * LL_GPIO_GetAFPin_8_15
00046   */
00047
00048 /* Private types -------------------------------------------------------------*/
00049 /* Private variables ---------------------------------------------------------*/
00050 /* Private constants ---------------------------------------------------------*/
00051 /* Private macros ------------------------------------------------------------*/
00052 #if defined(USE_FULL_LL_DRIVER)
00053 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
00054   * @{
00055   */
00056
00057 /**
00058   * @}
00059   */
00060 #endif /*USE_FULL_LL_DRIVER*/
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
00065   * @{
00066   */
00067
00068 /**
00069   * @brief LL GPIO Init Structure definition
00070   */
00071 typedef struct
00072 {
00073   uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
00074                               This parameter can be any value of @ref GPIO_LL_EC_PIN */
00075
00076   uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
00077                               This parameter can be a value of @ref GPIO_LL_EC_MODE.
00078
00079                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
00080
00081   uint32_t Speed;        /*!< Specifies the speed for the selected pins.
00082                               This parameter can be a value of @ref GPIO_LL_EC_SPEED.
00083
00084                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
00085
00086   uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
00087                               This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
00088
00089                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
00090
00091   uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
00092                               This parameter can be a value of @ref GPIO_LL_EC_PULL.
00093
00094                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
00095
00096   uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
00097                               This parameter can be a value of @ref GPIO_LL_EC_AF.
00098
00099                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
00100 } LL_GPIO_InitTypeDef;
00101
00102 /**
00103   * @}
00104   */
00105 #endif /* USE_FULL_LL_DRIVER */
00106
00107 /* Exported constants --------------------------------------------------------*/
00108 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
00109   * @{
00110   */
00111
00112 /** @defgroup GPIO_LL_EC_PIN PIN
00113   * @{
00114   */
00115 #define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
00116 #define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
00117 #define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
00118 #define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
00119 #define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
00120 #define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
00121 #define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
00122 #define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
00123 #define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
00124 #define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
00125 #define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
00126 #define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
00127 #define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
00128 #define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
00129 #define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
00130 #define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
00131 #define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
00132                                            GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
00133                                            GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
00134                                            GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
00135                                            GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
00136                                            GPIO_BSRR_BS15) /*!< Select all pins */
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup GPIO_LL_EC_MODE Mode
00142   * @{
00143   */
00144 #define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
00145 #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
00146 #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
00147 #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
00153   * @{
00154   */
00155 #define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
00156 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup GPIO_LL_EC_SPEED Output Speed
00162   * @{
00163   */
00164 #define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
00165 #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
00166 #define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
00167 #define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
00168 /**
00169   * @}
00170   */
00171 #define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
00172 #define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
00173 #define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
00174 #define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
00175
00176
00177 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
00178   * @{
00179   */
00180 #define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
00181 #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
00182 #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup GPIO_LL_EC_AF Alternate Function
00188   * @{
00189   */
00190 #define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
00191 #define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
00192 #define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
00193 #define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
00194 #define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
00195 #define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
00196 #define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
00197 #define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
00198 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
00199 #define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
00200 #define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
00201 #define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
00202 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
00203 /**
00204   * @}
00205   */
00206
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported macro ------------------------------------------------------------*/
00212 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
00213   * @{
00214   */
00215
00216 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
00217   * @{
00218   */
00219
00220 /**
00221   * @brief  Write a value in GPIO register
00222   * @param  __INSTANCE__ GPIO Instance
00223   * @param  __REG__ Register to be written
00224   * @param  __VALUE__ Value to be written in the register
00225   * @retval None
00226   */
00227 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00228
00229 /**
00230   * @brief  Read a value in GPIO register
00231   * @param  __INSTANCE__ GPIO Instance
00232   * @param  __REG__ Register to be read
00233   * @retval Register value
00234   */
00235 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /* Exported functions --------------------------------------------------------*/
00245 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
00246   * @{
00247   */
00248
00249 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
00250   * @{
00251   */
00252
00253 /**
00254   * @brief  Configure gpio mode for a dedicated pin on dedicated port.
00255   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00256   * @note   Warning: only one pin can be passed as parameter.
00257   * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
00258   * @param  GPIOx GPIO Port
00259   * @param  Pin This parameter can be one of the following values:
00260   *         @arg @ref LL_GPIO_PIN_0
00261   *         @arg @ref LL_GPIO_PIN_1
00262   *         @arg @ref LL_GPIO_PIN_2
00263   *         @arg @ref LL_GPIO_PIN_3
00264   *         @arg @ref LL_GPIO_PIN_4
00265   *         @arg @ref LL_GPIO_PIN_5
00266   *         @arg @ref LL_GPIO_PIN_6
00267   *         @arg @ref LL_GPIO_PIN_7
00268   *         @arg @ref LL_GPIO_PIN_8
00269   *         @arg @ref LL_GPIO_PIN_9
00270   *         @arg @ref LL_GPIO_PIN_10
00271   *         @arg @ref LL_GPIO_PIN_11
00272   *         @arg @ref LL_GPIO_PIN_12
00273   *         @arg @ref LL_GPIO_PIN_13
00274   *         @arg @ref LL_GPIO_PIN_14
00275   *         @arg @ref LL_GPIO_PIN_15
00276   * @param  Mode This parameter can be one of the following values:
00277   *         @arg @ref LL_GPIO_MODE_INPUT
00278   *         @arg @ref LL_GPIO_MODE_OUTPUT
00279   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00280   *         @arg @ref LL_GPIO_MODE_ANALOG
00281   * @retval None
00282   */
00283 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
00284 {
00285   MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
00286 }
00287
00288 /**
00289   * @brief  Return gpio mode for a dedicated pin on dedicated port.
00290   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00291   * @note   Warning: only one pin can be passed as parameter.
00292   * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
00293   * @param  GPIOx GPIO Port
00294   * @param  Pin This parameter can be one of the following values:
00295   *         @arg @ref LL_GPIO_PIN_0
00296   *         @arg @ref LL_GPIO_PIN_1
00297   *         @arg @ref LL_GPIO_PIN_2
00298   *         @arg @ref LL_GPIO_PIN_3
00299   *         @arg @ref LL_GPIO_PIN_4
00300   *         @arg @ref LL_GPIO_PIN_5
00301   *         @arg @ref LL_GPIO_PIN_6
00302   *         @arg @ref LL_GPIO_PIN_7
00303   *         @arg @ref LL_GPIO_PIN_8
00304   *         @arg @ref LL_GPIO_PIN_9
00305   *         @arg @ref LL_GPIO_PIN_10
00306   *         @arg @ref LL_GPIO_PIN_11
00307   *         @arg @ref LL_GPIO_PIN_12
00308   *         @arg @ref LL_GPIO_PIN_13
00309   *         @arg @ref LL_GPIO_PIN_14
00310   *         @arg @ref LL_GPIO_PIN_15
00311   * @retval Returned value can be one of the following values:
00312   *         @arg @ref LL_GPIO_MODE_INPUT
00313   *         @arg @ref LL_GPIO_MODE_OUTPUT
00314   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00315   *         @arg @ref LL_GPIO_MODE_ANALOG
00316   */
00317 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
00318 {
00319   return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
00320 }
00321
00322 /**
00323   * @brief  Configure gpio output type for several pins on dedicated port.
00324   * @note   Output type as to be set when gpio pin is in output or
00325   *         alternate modes. Possible type are Push-pull or Open-drain.
00326   * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
00327   * @param  GPIOx GPIO Port
00328   * @param  PinMask This parameter can be a combination of the following values:
00329   *         @arg @ref LL_GPIO_PIN_0
00330   *         @arg @ref LL_GPIO_PIN_1
00331   *         @arg @ref LL_GPIO_PIN_2
00332   *         @arg @ref LL_GPIO_PIN_3
00333   *         @arg @ref LL_GPIO_PIN_4
00334   *         @arg @ref LL_GPIO_PIN_5
00335   *         @arg @ref LL_GPIO_PIN_6
00336   *         @arg @ref LL_GPIO_PIN_7
00337   *         @arg @ref LL_GPIO_PIN_8
00338   *         @arg @ref LL_GPIO_PIN_9
00339   *         @arg @ref LL_GPIO_PIN_10
00340   *         @arg @ref LL_GPIO_PIN_11
00341   *         @arg @ref LL_GPIO_PIN_12
00342   *         @arg @ref LL_GPIO_PIN_13
00343   *         @arg @ref LL_GPIO_PIN_14
00344   *         @arg @ref LL_GPIO_PIN_15
00345   *         @arg @ref LL_GPIO_PIN_ALL
00346   * @param  OutputType This parameter can be one of the following values:
00347   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00348   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00349   * @retval None
00350   */
00351 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
00352 {
00353   MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
00354 }
00355
00356 /**
00357   * @brief  Return gpio output type for several pins on dedicated port.
00358   * @note   Output type as to be set when gpio pin is in output or
00359   *         alternate modes. Possible type are Push-pull or Open-drain.
00360   * @note   Warning: only one pin can be passed as parameter.
00361   * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
00362   * @param  GPIOx GPIO Port
00363   * @param  Pin This parameter can be one of the following values:
00364   *         @arg @ref LL_GPIO_PIN_0
00365   *         @arg @ref LL_GPIO_PIN_1
00366   *         @arg @ref LL_GPIO_PIN_2
00367   *         @arg @ref LL_GPIO_PIN_3
00368   *         @arg @ref LL_GPIO_PIN_4
00369   *         @arg @ref LL_GPIO_PIN_5
00370   *         @arg @ref LL_GPIO_PIN_6
00371   *         @arg @ref LL_GPIO_PIN_7
00372   *         @arg @ref LL_GPIO_PIN_8
00373   *         @arg @ref LL_GPIO_PIN_9
00374   *         @arg @ref LL_GPIO_PIN_10
00375   *         @arg @ref LL_GPIO_PIN_11
00376   *         @arg @ref LL_GPIO_PIN_12
00377   *         @arg @ref LL_GPIO_PIN_13
00378   *         @arg @ref LL_GPIO_PIN_14
00379   *         @arg @ref LL_GPIO_PIN_15
00380   *         @arg @ref LL_GPIO_PIN_ALL
00381   * @retval Returned value can be one of the following values:
00382   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00383   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00384   */
00385 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
00386 {
00387   return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
00388 }
00389
00390 /**
00391   * @brief  Configure gpio speed for a dedicated pin on dedicated port.
00392   * @note   I/O speed can be Low, Medium, Fast or High speed.
00393   * @note   Warning: only one pin can be passed as parameter.
00394   * @note   Refer to datasheet for frequency specifications and the power
00395   *         supply and load conditions for each speed.
00396   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
00397   * @param  GPIOx GPIO Port
00398   * @param  Pin This parameter can be one of the following values:
00399   *         @arg @ref LL_GPIO_PIN_0
00400   *         @arg @ref LL_GPIO_PIN_1
00401   *         @arg @ref LL_GPIO_PIN_2
00402   *         @arg @ref LL_GPIO_PIN_3
00403   *         @arg @ref LL_GPIO_PIN_4
00404   *         @arg @ref LL_GPIO_PIN_5
00405   *         @arg @ref LL_GPIO_PIN_6
00406   *         @arg @ref LL_GPIO_PIN_7
00407   *         @arg @ref LL_GPIO_PIN_8
00408   *         @arg @ref LL_GPIO_PIN_9
00409   *         @arg @ref LL_GPIO_PIN_10
00410   *         @arg @ref LL_GPIO_PIN_11
00411   *         @arg @ref LL_GPIO_PIN_12
00412   *         @arg @ref LL_GPIO_PIN_13
00413   *         @arg @ref LL_GPIO_PIN_14
00414   *         @arg @ref LL_GPIO_PIN_15
00415   * @param  Speed This parameter can be one of the following values:
00416   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00417   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00418   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00419   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00420   * @retval None
00421   */
00422 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
00423 {
00424   MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
00425 }
00426
00427 /**
00428   * @brief  Return gpio speed for a dedicated pin on dedicated port.
00429   * @note   I/O speed can be Low, Medium, Fast or High speed.
00430   * @note   Warning: only one pin can be passed as parameter.
00431   * @note   Refer to datasheet for frequency specifications and the power
00432   *         supply and load conditions for each speed.
00433   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
00434   * @param  GPIOx GPIO Port
00435   * @param  Pin This parameter can be one of the following values:
00436   *         @arg @ref LL_GPIO_PIN_0
00437   *         @arg @ref LL_GPIO_PIN_1
00438   *         @arg @ref LL_GPIO_PIN_2
00439   *         @arg @ref LL_GPIO_PIN_3
00440   *         @arg @ref LL_GPIO_PIN_4
00441   *         @arg @ref LL_GPIO_PIN_5
00442   *         @arg @ref LL_GPIO_PIN_6
00443   *         @arg @ref LL_GPIO_PIN_7
00444   *         @arg @ref LL_GPIO_PIN_8
00445   *         @arg @ref LL_GPIO_PIN_9
00446   *         @arg @ref LL_GPIO_PIN_10
00447   *         @arg @ref LL_GPIO_PIN_11
00448   *         @arg @ref LL_GPIO_PIN_12
00449   *         @arg @ref LL_GPIO_PIN_13
00450   *         @arg @ref LL_GPIO_PIN_14
00451   *         @arg @ref LL_GPIO_PIN_15
00452   * @retval Returned value can be one of the following values:
00453   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00454   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00455   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00456   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00457   */
00458 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
00459 {
00460   return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
00461 }
00462
00463 /**
00464   * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
00465   * @note   Warning: only one pin can be passed as parameter.
00466   * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
00467   * @param  GPIOx GPIO Port
00468   * @param  Pin This parameter can be one of the following values:
00469   *         @arg @ref LL_GPIO_PIN_0
00470   *         @arg @ref LL_GPIO_PIN_1
00471   *         @arg @ref LL_GPIO_PIN_2
00472   *         @arg @ref LL_GPIO_PIN_3
00473   *         @arg @ref LL_GPIO_PIN_4
00474   *         @arg @ref LL_GPIO_PIN_5
00475   *         @arg @ref LL_GPIO_PIN_6
00476   *         @arg @ref LL_GPIO_PIN_7
00477   *         @arg @ref LL_GPIO_PIN_8
00478   *         @arg @ref LL_GPIO_PIN_9
00479   *         @arg @ref LL_GPIO_PIN_10
00480   *         @arg @ref LL_GPIO_PIN_11
00481   *         @arg @ref LL_GPIO_PIN_12
00482   *         @arg @ref LL_GPIO_PIN_13
00483   *         @arg @ref LL_GPIO_PIN_14
00484   *         @arg @ref LL_GPIO_PIN_15
00485   * @param  Pull This parameter can be one of the following values:
00486   *         @arg @ref LL_GPIO_PULL_NO
00487   *         @arg @ref LL_GPIO_PULL_UP
00488   *         @arg @ref LL_GPIO_PULL_DOWN
00489   * @retval None
00490   */
00491 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
00492 {
00493   MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
00494 }
00495
00496 /**
00497   * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
00498   * @note   Warning: only one pin can be passed as parameter.
00499   * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
00500   * @param  GPIOx GPIO Port
00501   * @param  Pin This parameter can be one of the following values:
00502   *         @arg @ref LL_GPIO_PIN_0
00503   *         @arg @ref LL_GPIO_PIN_1
00504   *         @arg @ref LL_GPIO_PIN_2
00505   *         @arg @ref LL_GPIO_PIN_3
00506   *         @arg @ref LL_GPIO_PIN_4
00507   *         @arg @ref LL_GPIO_PIN_5
00508   *         @arg @ref LL_GPIO_PIN_6
00509   *         @arg @ref LL_GPIO_PIN_7
00510   *         @arg @ref LL_GPIO_PIN_8
00511   *         @arg @ref LL_GPIO_PIN_9
00512   *         @arg @ref LL_GPIO_PIN_10
00513   *         @arg @ref LL_GPIO_PIN_11
00514   *         @arg @ref LL_GPIO_PIN_12
00515   *         @arg @ref LL_GPIO_PIN_13
00516   *         @arg @ref LL_GPIO_PIN_14
00517   *         @arg @ref LL_GPIO_PIN_15
00518   * @retval Returned value can be one of the following values:
00519   *         @arg @ref LL_GPIO_PULL_NO
00520   *         @arg @ref LL_GPIO_PULL_UP
00521   *         @arg @ref LL_GPIO_PULL_DOWN
00522   */
00523 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
00524 {
00525   return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
00526 }
00527
00528 /**
00529   * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00530   * @note   Possible values are from AF0 to AF7 depending on target.
00531   * @note   Warning: only one pin can be passed as parameter.
00532   * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
00533   * @param  GPIOx GPIO Port
00534   * @param  Pin This parameter can be one of the following values:
00535   *         @arg @ref LL_GPIO_PIN_0
00536   *         @arg @ref LL_GPIO_PIN_1
00537   *         @arg @ref LL_GPIO_PIN_2
00538   *         @arg @ref LL_GPIO_PIN_3
00539   *         @arg @ref LL_GPIO_PIN_4
00540   *         @arg @ref LL_GPIO_PIN_5
00541   *         @arg @ref LL_GPIO_PIN_6
00542   *         @arg @ref LL_GPIO_PIN_7
00543   * @param  Alternate This parameter can be one of the following values:
00544   *         @arg @ref LL_GPIO_AF_0
00545   *         @arg @ref LL_GPIO_AF_1
00546   *         @arg @ref LL_GPIO_AF_2
00547   *         @arg @ref LL_GPIO_AF_3
00548   *         @arg @ref LL_GPIO_AF_4
00549   *         @arg @ref LL_GPIO_AF_5
00550   *         @arg @ref LL_GPIO_AF_6
00551   *         @arg @ref LL_GPIO_AF_7
00552   * @retval None
00553   */
00554 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00555 {
00556   MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
00557              ((((Pin * Pin) * Pin) * Pin) * Alternate));
00558 }
00559
00560 /**
00561   * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00562   * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
00563   * @param  GPIOx GPIO Port
00564   * @param  Pin This parameter can be one of the following values:
00565   *         @arg @ref LL_GPIO_PIN_0
00566   *         @arg @ref LL_GPIO_PIN_1
00567   *         @arg @ref LL_GPIO_PIN_2
00568   *         @arg @ref LL_GPIO_PIN_3
00569   *         @arg @ref LL_GPIO_PIN_4
00570   *         @arg @ref LL_GPIO_PIN_5
00571   *         @arg @ref LL_GPIO_PIN_6
00572   *         @arg @ref LL_GPIO_PIN_7
00573   * @retval Returned value can be one of the following values:
00574   *         @arg @ref LL_GPIO_AF_0
00575   *         @arg @ref LL_GPIO_AF_1
00576   *         @arg @ref LL_GPIO_AF_2
00577   *         @arg @ref LL_GPIO_AF_3
00578   *         @arg @ref LL_GPIO_AF_4
00579   *         @arg @ref LL_GPIO_AF_5
00580   *         @arg @ref LL_GPIO_AF_6
00581   *         @arg @ref LL_GPIO_AF_7
00582   */
00583 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
00584 {
00585   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
00586                              ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
00587 }
00588
00589 /**
00590   * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00591   * @note   Possible values are from AF0 to AF7 depending on target.
00592   * @note   Warning: only one pin can be passed as parameter.
00593   * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
00594   * @param  GPIOx GPIO Port
00595   * @param  Pin This parameter can be one of the following values:
00596   *         @arg @ref LL_GPIO_PIN_8
00597   *         @arg @ref LL_GPIO_PIN_9
00598   *         @arg @ref LL_GPIO_PIN_10
00599   *         @arg @ref LL_GPIO_PIN_11
00600   *         @arg @ref LL_GPIO_PIN_12
00601   *         @arg @ref LL_GPIO_PIN_13
00602   *         @arg @ref LL_GPIO_PIN_14
00603   *         @arg @ref LL_GPIO_PIN_15
00604   * @param  Alternate This parameter can be one of the following values:
00605   *         @arg @ref LL_GPIO_AF_0
00606   *         @arg @ref LL_GPIO_AF_1
00607   *         @arg @ref LL_GPIO_AF_2
00608   *         @arg @ref LL_GPIO_AF_3
00609   *         @arg @ref LL_GPIO_AF_4
00610   *         @arg @ref LL_GPIO_AF_5
00611   *         @arg @ref LL_GPIO_AF_6
00612   *         @arg @ref LL_GPIO_AF_7
00613   * @retval None
00614   */
00615 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00616 {
00617   MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
00618              (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
00619 }
00620
00621 /**
00622   * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00623   * @note   Possible values are from AF0 to AF7 depending on target.
00624   * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
00625   * @param  GPIOx GPIO Port
00626   * @param  Pin This parameter can be one of the following values:
00627   *         @arg @ref LL_GPIO_PIN_8
00628   *         @arg @ref LL_GPIO_PIN_9
00629   *         @arg @ref LL_GPIO_PIN_10
00630   *         @arg @ref LL_GPIO_PIN_11
00631   *         @arg @ref LL_GPIO_PIN_12
00632   *         @arg @ref LL_GPIO_PIN_13
00633   *         @arg @ref LL_GPIO_PIN_14
00634   *         @arg @ref LL_GPIO_PIN_15
00635   * @retval Returned value can be one of the following values:
00636   *         @arg @ref LL_GPIO_AF_0
00637   *         @arg @ref LL_GPIO_AF_1
00638   *         @arg @ref LL_GPIO_AF_2
00639   *         @arg @ref LL_GPIO_AF_3
00640   *         @arg @ref LL_GPIO_AF_4
00641   *         @arg @ref LL_GPIO_AF_5
00642   *         @arg @ref LL_GPIO_AF_6
00643   *         @arg @ref LL_GPIO_AF_7
00644   */
00645 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
00646 {
00647   return (uint32_t)(READ_BIT(GPIOx->AFR[1],
00648                              (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
00649                                  (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
00650 }
00651
00652
00653 /**
00654   * @brief  Lock configuration of several pins for a dedicated port.
00655   * @note   When the lock sequence has been applied on a port bit, the
00656   *         value of this port bit can no longer be modified until the
00657   *         next reset.
00658   * @note   Each lock bit freezes a specific configuration register
00659   *         (control and alternate function registers).
00660   * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
00661   * @param  GPIOx GPIO Port
00662   * @param  PinMask This parameter can be a combination of the following values:
00663   *         @arg @ref LL_GPIO_PIN_0
00664   *         @arg @ref LL_GPIO_PIN_1
00665   *         @arg @ref LL_GPIO_PIN_2
00666   *         @arg @ref LL_GPIO_PIN_3
00667   *         @arg @ref LL_GPIO_PIN_4
00668   *         @arg @ref LL_GPIO_PIN_5
00669   *         @arg @ref LL_GPIO_PIN_6
00670   *         @arg @ref LL_GPIO_PIN_7
00671   *         @arg @ref LL_GPIO_PIN_8
00672   *         @arg @ref LL_GPIO_PIN_9
00673   *         @arg @ref LL_GPIO_PIN_10
00674   *         @arg @ref LL_GPIO_PIN_11
00675   *         @arg @ref LL_GPIO_PIN_12
00676   *         @arg @ref LL_GPIO_PIN_13
00677   *         @arg @ref LL_GPIO_PIN_14
00678   *         @arg @ref LL_GPIO_PIN_15
00679   *         @arg @ref LL_GPIO_PIN_ALL
00680   * @retval None
00681   */
00682 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00683 {
00684   __IO uint32_t temp;
00685   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00686   WRITE_REG(GPIOx->LCKR, PinMask);
00687   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00688   /* Read LCKK register. This read is mandatory to complete key lock sequence */
00689   temp = READ_REG(GPIOx->LCKR);
00690   (void) temp;
00691 }
00692
00693 /**
00694   * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
00695   * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
00696   * @param  GPIOx GPIO Port
00697   * @param  PinMask This parameter can be a combination of the following values:
00698   *         @arg @ref LL_GPIO_PIN_0
00699   *         @arg @ref LL_GPIO_PIN_1
00700   *         @arg @ref LL_GPIO_PIN_2
00701   *         @arg @ref LL_GPIO_PIN_3
00702   *         @arg @ref LL_GPIO_PIN_4
00703   *         @arg @ref LL_GPIO_PIN_5
00704   *         @arg @ref LL_GPIO_PIN_6
00705   *         @arg @ref LL_GPIO_PIN_7
00706   *         @arg @ref LL_GPIO_PIN_8
00707   *         @arg @ref LL_GPIO_PIN_9
00708   *         @arg @ref LL_GPIO_PIN_10
00709   *         @arg @ref LL_GPIO_PIN_11
00710   *         @arg @ref LL_GPIO_PIN_12
00711   *         @arg @ref LL_GPIO_PIN_13
00712   *         @arg @ref LL_GPIO_PIN_14
00713   *         @arg @ref LL_GPIO_PIN_15
00714   *         @arg @ref LL_GPIO_PIN_ALL
00715   * @retval State of bit (1 or 0).
00716   */
00717 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00718 {
00719   return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
00720 }
00721
00722 /**
00723   * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
00724   * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
00725   * @param  GPIOx GPIO Port
00726   * @retval State of bit (1 or 0).
00727   */
00728 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
00729 {
00730   return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
00731 }
00732
00733 /**
00734   * @}
00735   */
00736
00737 /** @defgroup GPIO_LL_EF_Data_Access Data Access
00738   * @{
00739   */
00740
00741 /**
00742   * @brief  Return full input data register value for a dedicated port.
00743   * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
00744   * @param  GPIOx GPIO Port
00745   * @retval Input data register value of port
00746   */
00747 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
00748 {
00749   return (uint32_t)(READ_REG(GPIOx->IDR));
00750 }
00751
00752 /**
00753   * @brief  Return if input data level for several pins of dedicated port is high or low.
00754   * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
00755   * @param  GPIOx GPIO Port
00756   * @param  PinMask This parameter can be a combination of the following values:
00757   *         @arg @ref LL_GPIO_PIN_0
00758   *         @arg @ref LL_GPIO_PIN_1
00759   *         @arg @ref LL_GPIO_PIN_2
00760   *         @arg @ref LL_GPIO_PIN_3
00761   *         @arg @ref LL_GPIO_PIN_4
00762   *         @arg @ref LL_GPIO_PIN_5
00763   *         @arg @ref LL_GPIO_PIN_6
00764   *         @arg @ref LL_GPIO_PIN_7
00765   *         @arg @ref LL_GPIO_PIN_8
00766   *         @arg @ref LL_GPIO_PIN_9
00767   *         @arg @ref LL_GPIO_PIN_10
00768   *         @arg @ref LL_GPIO_PIN_11
00769   *         @arg @ref LL_GPIO_PIN_12
00770   *         @arg @ref LL_GPIO_PIN_13
00771   *         @arg @ref LL_GPIO_PIN_14
00772   *         @arg @ref LL_GPIO_PIN_15
00773   *         @arg @ref LL_GPIO_PIN_ALL
00774   * @retval State of bit (1 or 0).
00775   */
00776 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00777 {
00778   return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
00779 }
00780
00781 /**
00782   * @brief  Write output data register for the port.
00783   * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
00784   * @param  GPIOx GPIO Port
00785   * @param  PortValue Level value for each pin of the port
00786   * @retval None
00787   */
00788 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
00789 {
00790   WRITE_REG(GPIOx->ODR, PortValue);
00791 }
00792
00793 /**
00794   * @brief  Return full output data register value for a dedicated port.
00795   * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
00796   * @param  GPIOx GPIO Port
00797   * @retval Output data register value of port
00798   */
00799 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
00800 {
00801   return (uint32_t)(READ_REG(GPIOx->ODR));
00802 }
00803
00804 /**
00805   * @brief  Return if input data level for several pins of dedicated port is high or low.
00806   * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
00807   * @param  GPIOx GPIO Port
00808   * @param  PinMask This parameter can be a combination of the following values:
00809   *         @arg @ref LL_GPIO_PIN_0
00810   *         @arg @ref LL_GPIO_PIN_1
00811   *         @arg @ref LL_GPIO_PIN_2
00812   *         @arg @ref LL_GPIO_PIN_3
00813   *         @arg @ref LL_GPIO_PIN_4
00814   *         @arg @ref LL_GPIO_PIN_5
00815   *         @arg @ref LL_GPIO_PIN_6
00816   *         @arg @ref LL_GPIO_PIN_7
00817   *         @arg @ref LL_GPIO_PIN_8
00818   *         @arg @ref LL_GPIO_PIN_9
00819   *         @arg @ref LL_GPIO_PIN_10
00820   *         @arg @ref LL_GPIO_PIN_11
00821   *         @arg @ref LL_GPIO_PIN_12
00822   *         @arg @ref LL_GPIO_PIN_13
00823   *         @arg @ref LL_GPIO_PIN_14
00824   *         @arg @ref LL_GPIO_PIN_15
00825   *         @arg @ref LL_GPIO_PIN_ALL
00826   * @retval State of bit (1 or 0).
00827   */
00828 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00829 {
00830   return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
00831 }
00832
00833 /**
00834   * @brief  Set several pins to high level on dedicated gpio port.
00835   * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
00836   * @param  GPIOx GPIO Port
00837   * @param  PinMask This parameter can be a combination of the following values:
00838   *         @arg @ref LL_GPIO_PIN_0
00839   *         @arg @ref LL_GPIO_PIN_1
00840   *         @arg @ref LL_GPIO_PIN_2
00841   *         @arg @ref LL_GPIO_PIN_3
00842   *         @arg @ref LL_GPIO_PIN_4
00843   *         @arg @ref LL_GPIO_PIN_5
00844   *         @arg @ref LL_GPIO_PIN_6
00845   *         @arg @ref LL_GPIO_PIN_7
00846   *         @arg @ref LL_GPIO_PIN_8
00847   *         @arg @ref LL_GPIO_PIN_9
00848   *         @arg @ref LL_GPIO_PIN_10
00849   *         @arg @ref LL_GPIO_PIN_11
00850   *         @arg @ref LL_GPIO_PIN_12
00851   *         @arg @ref LL_GPIO_PIN_13
00852   *         @arg @ref LL_GPIO_PIN_14
00853   *         @arg @ref LL_GPIO_PIN_15
00854   *         @arg @ref LL_GPIO_PIN_ALL
00855   * @retval None
00856   */
00857 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00858 {
00859   WRITE_REG(GPIOx->BSRR, PinMask);
00860 }
00861
00862 /**
00863   * @brief  Set several pins to low level on dedicated gpio port.
00864   * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
00865   * @param  GPIOx GPIO Port
00866   * @param  PinMask This parameter can be a combination of the following values:
00867   *         @arg @ref LL_GPIO_PIN_0
00868   *         @arg @ref LL_GPIO_PIN_1
00869   *         @arg @ref LL_GPIO_PIN_2
00870   *         @arg @ref LL_GPIO_PIN_3
00871   *         @arg @ref LL_GPIO_PIN_4
00872   *         @arg @ref LL_GPIO_PIN_5
00873   *         @arg @ref LL_GPIO_PIN_6
00874   *         @arg @ref LL_GPIO_PIN_7
00875   *         @arg @ref LL_GPIO_PIN_8
00876   *         @arg @ref LL_GPIO_PIN_9
00877   *         @arg @ref LL_GPIO_PIN_10
00878   *         @arg @ref LL_GPIO_PIN_11
00879   *         @arg @ref LL_GPIO_PIN_12
00880   *         @arg @ref LL_GPIO_PIN_13
00881   *         @arg @ref LL_GPIO_PIN_14
00882   *         @arg @ref LL_GPIO_PIN_15
00883   *         @arg @ref LL_GPIO_PIN_ALL
00884   * @retval None
00885   */
00886 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00887 {
00888   WRITE_REG(GPIOx->BRR, PinMask);
00889 }
00890
00891 /**
00892   * @brief  Toggle data value for several pin of dedicated port.
00893   * @rmtoll ODR          ODy           LL_GPIO_TogglePin
00894   * @param  GPIOx GPIO Port
00895   * @param  PinMask This parameter can be a combination of the following values:
00896   *         @arg @ref LL_GPIO_PIN_0
00897   *         @arg @ref LL_GPIO_PIN_1
00898   *         @arg @ref LL_GPIO_PIN_2
00899   *         @arg @ref LL_GPIO_PIN_3
00900   *         @arg @ref LL_GPIO_PIN_4
00901   *         @arg @ref LL_GPIO_PIN_5
00902   *         @arg @ref LL_GPIO_PIN_6
00903   *         @arg @ref LL_GPIO_PIN_7
00904   *         @arg @ref LL_GPIO_PIN_8
00905   *         @arg @ref LL_GPIO_PIN_9
00906   *         @arg @ref LL_GPIO_PIN_10
00907   *         @arg @ref LL_GPIO_PIN_11
00908   *         @arg @ref LL_GPIO_PIN_12
00909   *         @arg @ref LL_GPIO_PIN_13
00910   *         @arg @ref LL_GPIO_PIN_14
00911   *         @arg @ref LL_GPIO_PIN_15
00912   *         @arg @ref LL_GPIO_PIN_ALL
00913   * @retval None
00914   */
00915 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00916 {
00917   uint32_t odr = READ_REG(GPIOx->ODR);
00918   WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
00919 }
00920
00921
00922 /**
00923   * @}
00924   */
00925
00926 #if defined(USE_FULL_LL_DRIVER)
00927 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
00928   * @{
00929   */
00930
00931 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
00932 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
00933 void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
00934
00935 /**
00936   * @}
00937   */
00938 #endif /* USE_FULL_LL_DRIVER */
00939
00940 /**
00941   * @}
00942   */
00943
00944 /**
00945   * @}
00946   */
00947
00948 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
00949 /**
00950   * @}
00951   */
00952
00953 #ifdef __cplusplus
00954 }
00955 #endif
00956
00957 #endif /* STM32G0xx_LL_GPIO_H */
00958
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_i2c.c Source File

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stm32g0xx_ll_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_i2c.h"
00022 #include "stm32g0xx_ll_bus.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G0xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
00034
00035 /** @defgroup I2C_LL I2C
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /** @addtogroup I2C_LL_Private_Macros
00044   * @{
00045   */
00046
00047 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
00048                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
00049                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
00050                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
00051
00052 #define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
00053                                                  ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
00054
00055 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
00056
00057 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
00058
00059 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
00060                                                  ((__VALUE__) == LL_I2C_NACK))
00061
00062 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
00063                                                  ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
00064 /**
00065   * @}
00066   */
00067
00068 /* Private function prototypes -----------------------------------------------*/
00069
00070 /* Exported functions --------------------------------------------------------*/
00071 /** @addtogroup I2C_LL_Exported_Functions
00072   * @{
00073   */
00074
00075 /** @addtogroup I2C_LL_EF_Init
00076   * @{
00077   */
00078
00079 /**
00080   * @brief  De-initialize the I2C registers to their default reset values.
00081   * @param  I2Cx I2C Instance.
00082   * @retval An ErrorStatus enumeration value:
00083   *          - SUCCESS: I2C registers are de-initialized
00084   *          - ERROR: I2C registers are not de-initialized
00085   */
00086 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
00087 {
00088   ErrorStatus status = SUCCESS;
00089
00090   /* Check the I2C Instance I2Cx */
00091   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00092
00093   if (I2Cx == I2C1)
00094   {
00095     /* Force reset of I2C clock */
00096     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
00097
00098     /* Release reset of I2C clock */
00099     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
00100   }
00101   else if (I2Cx == I2C2)
00102   {
00103     /* Force reset of I2C clock */
00104     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
00105
00106     /* Release reset of I2C clock */
00107     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
00108
00109   }
00110 #if defined(I2C3)
00111   else if (I2Cx == I2C3)
00112   {
00113     /* Force reset of I2C clock */
00114     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
00115
00116     /* Release reset of I2C clock */
00117     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
00118   }
00119 #endif /* I2C3 */
00120   else
00121   {
00122     status = ERROR;
00123   }
00124
00125   return status;
00126 }
00127
00128 /**
00129   * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
00130   * @param  I2Cx I2C Instance.
00131   * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
00132   * @retval An ErrorStatus enumeration value:
00133   *          - SUCCESS: I2C registers are initialized
00134   *          - ERROR: Not applicable
00135   */
00136 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
00137 {
00138   /* Check the I2C Instance I2Cx */
00139   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00140
00141   /* Check the I2C parameters from I2C_InitStruct */
00142   assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
00143   assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
00144   assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
00145   assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
00146   assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
00147   assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
00148
00149   /* Disable the selected I2Cx Peripheral */
00150   LL_I2C_Disable(I2Cx);
00151
00152   /*---------------------------- I2Cx CR1 Configuration ------------------------
00153    * Configure the analog and digital noise filters with parameters :
00154    * - AnalogFilter: I2C_CR1_ANFOFF bit
00155    * - DigitalFilter: I2C_CR1_DNF[3:0] bits
00156    */
00157   LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
00158
00159   /*---------------------------- I2Cx TIMINGR Configuration --------------------
00160    * Configure the SDA setup, hold time and the SCL high, low period with parameter :
00161    * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
00162    *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
00163    */
00164   LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
00165
00166   /* Enable the selected I2Cx Peripheral */
00167   LL_I2C_Enable(I2Cx);
00168
00169   /*---------------------------- I2Cx OAR1 Configuration -----------------------
00170    * Disable, Configure and Enable I2Cx device own address 1 with parameters :
00171    * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
00172    * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
00173    */
00174   LL_I2C_DisableOwnAddress1(I2Cx);
00175   LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
00176
00177   /* OwnAdress1 == 0 is reserved for General Call address */
00178   if (I2C_InitStruct->OwnAddress1 != 0U)
00179   {
00180     LL_I2C_EnableOwnAddress1(I2Cx);
00181   }
00182
00183   /*---------------------------- I2Cx MODE Configuration -----------------------
00184   * Configure I2Cx peripheral mode with parameter :
00185    * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
00186    */
00187   LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
00188
00189   /*---------------------------- I2Cx CR2 Configuration ------------------------
00190    * Configure the ACKnowledge or Non ACKnowledge condition
00191    * after the address receive match code or next received byte with parameter :
00192    * - TypeAcknowledge: I2C_CR2_NACK bit
00193    */
00194   LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
00195
00196   return SUCCESS;
00197 }
00198
00199 /**
00200   * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
00201   * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
00202   * @retval None
00203   */
00204 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
00205 {
00206   /* Set I2C_InitStruct fields to default values */
00207   I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
00208   I2C_InitStruct->Timing          = 0U;
00209   I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
00210   I2C_InitStruct->DigitalFilter   = 0U;
00211   I2C_InitStruct->OwnAddress1     = 0U;
00212   I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
00213   I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
00214 }
00215
00216 /**
00217   * @}
00218   */
00219
00220 /**
00221   * @}
00222   */
00223
00224 /**
00225   * @}
00226   */
00227
00228 #endif /* I2C1 || I2C2 || I2C3 */
00229
00230 /**
00231   * @}
00232   */
00233
00234 #endif /* USE_FULL_LL_DRIVER */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_i2c.h Source File

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stm32g0xx_ll_i2c.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_I2C_H
00021 #define STM32G0xx_LL_I2C_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
00035
00036 /** @defgroup I2C_LL I2C
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
00045   * @{
00046   */
00047 /**
00048   * @}
00049   */
00050
00051 /* Private macros ------------------------------------------------------------*/
00052 #if defined(USE_FULL_LL_DRIVER)
00053 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
00054   * @{
00055   */
00056 /**
00057   * @}
00058   */
00059 #endif /*USE_FULL_LL_DRIVER*/
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 #if defined(USE_FULL_LL_DRIVER)
00063 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
00069                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
00070
00071                                      This feature can be modified afterwards using unitary function
00072                                      @ref LL_I2C_SetMode(). */
00073
00074   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
00075                                      This parameter must be set by referring to the STM32CubeMX Tool and
00076                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
00077
00078                                      This feature can be modified afterwards using unitary function
00079                                      @ref LL_I2C_SetTiming(). */
00080
00081   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
00082                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
00083
00084                                      This feature can be modified afterwards using unitary functions
00085                                      @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
00086
00087   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
00088                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
00089
00090                                      This feature can be modified afterwards using unitary function
00091                                      @ref LL_I2C_SetDigitalFilter(). */
00092
00093   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
00094                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
00095
00096                                      This feature can be modified afterwards using unitary function
00097                                      @ref LL_I2C_SetOwnAddress1(). */
00098
00099   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
00100                                      match code or next received byte.
00101                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
00102
00103                                      This feature can be modified afterwards using unitary function
00104                                      @ref LL_I2C_AcknowledgeNextData(). */
00105
00106   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
00107                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
00108
00109                                      This feature can be modified afterwards using unitary function
00110                                      @ref LL_I2C_SetOwnAddress1(). */
00111 } LL_I2C_InitTypeDef;
00112 /**
00113   * @}
00114   */
00115 #endif /*USE_FULL_LL_DRIVER*/
00116
00117 /* Exported constants --------------------------------------------------------*/
00118 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
00119   * @{
00120   */
00121
00122 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
00123   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
00124   * @{
00125   */
00126 #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
00127 #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
00128 #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
00129 #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
00130 #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
00131 #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
00132 #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
00133 #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
00134 #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
00140   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
00141   * @{
00142   */
00143 #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
00144 #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
00145 #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
00146 #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
00147 #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
00148 #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
00149 #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
00150 #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
00151 #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
00152 #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
00153 #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
00154 #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
00155 #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
00156 #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
00157 #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup I2C_LL_EC_IT IT Defines
00163   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
00164   * @{
00165   */
00166 #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
00167 #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
00168 #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
00169 #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
00170 #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
00171 #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
00172 #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
00178   * @{
00179   */
00180 #define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
00181 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
00182 #define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
00183                                                                          (Default address not acknowledge)        */
00184 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
00190   * @{
00191   */
00192 #define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
00193 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
00199   * @{
00200   */
00201 #define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
00202 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
00208   * @{
00209   */
00210 #define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
00211 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
00217   * @{
00218   */
00219 #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
00220 #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
00221 #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
00222 #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
00223 #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
00224 #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
00225 #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
00226 #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
00227                                                                          All Address2 are acknowledged.        */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
00233   * @{
00234   */
00235 #define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
00236 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
00242   * @{
00243   */
00244 #define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
00245 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
00251   * @{
00252   */
00253 #define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
00254 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
00260   * @{
00261   */
00262 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
00263 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
00264                                                                           with no HW PEC comparison.  */
00265 #define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
00266                                                                           with no HW PEC comparison.  */
00267 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
00268                                                                           with HW PEC comparison.     */
00269 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
00270                                                                           with HW PEC comparison.     */
00271 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
00272                                                                           with HW PEC comparison.     */
00273 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
00274 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00275 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
00276 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
00282   * @{
00283   */
00284 #define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
00285 /*!< Don't Generate Stop and Start condition. */
00286 #define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
00287 /*!< Generate Stop condition (Size should be set to 0).      */
00288 #define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00289 /*!< Generate Start for read request. */
00290 #define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
00291 /*!< Generate Start for write request. */
00292 #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00293 /*!< Generate Restart for read request, slave 7Bit address.  */
00294 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
00295 /*!< Generate Restart for write request, slave 7Bit address. */
00296 #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
00297                                                        I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
00298 /*!< Generate Restart for read request, slave 10Bit address. */
00299 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
00300 /*!< Generate Restart for write request, slave 10Bit address.*/
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
00306   * @{
00307   */
00308 #define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
00309                                                                           slave enters receiver mode.  */
00310 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
00311                                                                           slave enters transmitter mode.*/
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
00317   * @{
00318   */
00319 #define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
00320                                                                           transmission */
00321 #define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
00322                                                                           reception */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
00328   * @{
00329   */
00330 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
00331                                                                           SCL low level timeout.              */
00332 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
00333                                                                           both SCL and SDA high level timeout.*/
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
00339   * @{
00340   */
00341 #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
00342 #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
00343                                                                                        enable bit                   */
00344 #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
00345                                                        I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
00346 (extended clock) enable bits */
00347 /**
00348   * @}
00349   */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /* Exported macro ------------------------------------------------------------*/
00356 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
00357   * @{
00358   */
00359
00360 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
00361   * @{
00362   */
00363
00364 /**
00365   * @brief  Write a value in I2C register
00366   * @param  __INSTANCE__ I2C Instance
00367   * @param  __REG__ Register to be written
00368   * @param  __VALUE__ Value to be written in the register
00369   * @retval None
00370   */
00371 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00372
00373 /**
00374   * @brief  Read a value in I2C register
00375   * @param  __INSTANCE__ I2C Instance
00376   * @param  __REG__ Register to be read
00377   * @retval Register value
00378   */
00379 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
00385   * @{
00386   */
00387 /**
00388   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00389   * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
00390   * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
00391                            (tscldel = (SCLDEL+1)xtpresc)
00392   * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
00393                            (tsdadel = SDADELxtpresc)
00394   * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
00395                             (tsclh = (SCLH+1)xtpresc)
00396   * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
00397                             (tscll = (SCLL+1)xtpresc)
00398   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
00399   */
00400 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
00401   ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
00402    (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
00403    (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
00404    (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
00405    (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
00406 /**
00407   * @}
00408   */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /* Exported functions --------------------------------------------------------*/
00415 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
00416   * @{
00417   */
00418
00419 /** @defgroup I2C_LL_EF_Configuration Configuration
00420   * @{
00421   */
00422
00423 /**
00424   * @brief  Enable I2C peripheral (PE = 1).
00425   * @rmtoll CR1          PE            LL_I2C_Enable
00426   * @param  I2Cx I2C Instance.
00427   * @retval None
00428   */
00429 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
00430 {
00431   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
00432 }
00433
00434 /**
00435   * @brief  Disable I2C peripheral (PE = 0).
00436   * @note   When PE = 0, the I2C SCL and SDA lines are released.
00437   *         Internal state machines and status bits are put back to their reset value.
00438   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
00439   * @rmtoll CR1          PE            LL_I2C_Disable
00440   * @param  I2Cx I2C Instance.
00441   * @retval None
00442   */
00443 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
00444 {
00445   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
00446 }
00447
00448 /**
00449   * @brief  Check if the I2C peripheral is enabled or disabled.
00450   * @rmtoll CR1          PE            LL_I2C_IsEnabled
00451   * @param  I2Cx I2C Instance.
00452   * @retval State of bit (1 or 0).
00453   */
00454 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
00455 {
00456   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
00457 }
00458
00459 /**
00460   * @brief  Configure Noise Filters (Analog and Digital).
00461   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00462   *         The filters can only be programmed when the I2C is disabled (PE = 0).
00463   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
00464   *         CR1          DNF           LL_I2C_ConfigFilters
00465   * @param  I2Cx I2C Instance.
00466   * @param  AnalogFilter This parameter can be one of the following values:
00467   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
00468   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
00469   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
00470                           and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00471   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00472   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00473   * @retval None
00474   */
00475 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
00476 {
00477   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
00478 }
00479
00480 /**
00481   * @brief  Configure Digital Noise Filter.
00482   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00483   *         This filter can only be programmed when the I2C is disabled (PE = 0).
00484   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
00485   * @param  I2Cx I2C Instance.
00486   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
00487                           and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00488   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00489   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00490   * @retval None
00491   */
00492 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
00493 {
00494   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
00495 }
00496
00497 /**
00498   * @brief  Get the current Digital Noise Filter configuration.
00499   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
00500   * @param  I2Cx I2C Instance.
00501   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00502   */
00503 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
00504 {
00505   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
00506 }
00507
00508 /**
00509   * @brief  Enable Analog Noise Filter.
00510   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00511   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
00512   * @param  I2Cx I2C Instance.
00513   * @retval None
00514   */
00515 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
00516 {
00517   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00518 }
00519
00520 /**
00521   * @brief  Disable Analog Noise Filter.
00522   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00523   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
00524   * @param  I2Cx I2C Instance.
00525   * @retval None
00526   */
00527 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
00528 {
00529   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00530 }
00531
00532 /**
00533   * @brief  Check if Analog Noise Filter is enabled or disabled.
00534   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
00535   * @param  I2Cx I2C Instance.
00536   * @retval State of bit (1 or 0).
00537   */
00538 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
00539 {
00540   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
00541 }
00542
00543 /**
00544   * @brief  Enable DMA transmission requests.
00545   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
00546   * @param  I2Cx I2C Instance.
00547   * @retval None
00548   */
00549 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
00550 {
00551   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00552 }
00553
00554 /**
00555   * @brief  Disable DMA transmission requests.
00556   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
00557   * @param  I2Cx I2C Instance.
00558   * @retval None
00559   */
00560 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
00561 {
00562   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00563 }
00564
00565 /**
00566   * @brief  Check if DMA transmission requests are enabled or disabled.
00567   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
00568   * @param  I2Cx I2C Instance.
00569   * @retval State of bit (1 or 0).
00570   */
00571 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
00572 {
00573   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
00574 }
00575
00576 /**
00577   * @brief  Enable DMA reception requests.
00578   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
00579   * @param  I2Cx I2C Instance.
00580   * @retval None
00581   */
00582 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
00583 {
00584   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00585 }
00586
00587 /**
00588   * @brief  Disable DMA reception requests.
00589   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
00590   * @param  I2Cx I2C Instance.
00591   * @retval None
00592   */
00593 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
00594 {
00595   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00596 }
00597
00598 /**
00599   * @brief  Check if DMA reception requests are enabled or disabled.
00600   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
00601   * @param  I2Cx I2C Instance.
00602   * @retval State of bit (1 or 0).
00603   */
00604 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
00605 {
00606   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
00607 }
00608
00609 /**
00610   * @brief  Get the data register address used for DMA transfer
00611   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
00612   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
00613   * @param  I2Cx I2C Instance
00614   * @param  Direction This parameter can be one of the following values:
00615   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
00616   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
00617   * @retval Address of data register
00618   */
00619 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
00620 {
00621   uint32_t data_reg_addr;
00622
00623   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
00624   {
00625     /* return address of TXDR register */
00626     data_reg_addr = (uint32_t) &(I2Cx->TXDR);
00627   }
00628   else
00629   {
00630     /* return address of RXDR register */
00631     data_reg_addr = (uint32_t) &(I2Cx->RXDR);
00632   }
00633
00634   return data_reg_addr;
00635 }
00636
00637 /**
00638   * @brief  Enable Clock stretching.
00639   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00640   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
00641   * @param  I2Cx I2C Instance.
00642   * @retval None
00643   */
00644 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
00645 {
00646   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00647 }
00648
00649 /**
00650   * @brief  Disable Clock stretching.
00651   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00652   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
00653   * @param  I2Cx I2C Instance.
00654   * @retval None
00655   */
00656 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
00657 {
00658   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00659 }
00660
00661 /**
00662   * @brief  Check if Clock stretching is enabled or disabled.
00663   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
00664   * @param  I2Cx I2C Instance.
00665   * @retval State of bit (1 or 0).
00666   */
00667 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
00668 {
00669   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
00670 }
00671
00672 /**
00673   * @brief  Enable hardware byte control in slave mode.
00674   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
00675   * @param  I2Cx I2C Instance.
00676   * @retval None
00677   */
00678 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
00679 {
00680   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
00681 }
00682
00683 /**
00684   * @brief  Disable hardware byte control in slave mode.
00685   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
00686   * @param  I2Cx I2C Instance.
00687   * @retval None
00688   */
00689 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
00690 {
00691   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
00692 }
00693
00694 /**
00695   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
00696   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
00697   * @param  I2Cx I2C Instance.
00698   * @retval State of bit (1 or 0).
00699   */
00700 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
00701 {
00702   return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
00703 }
00704
00705 /**
00706   * @brief  Enable Wakeup from STOP.
00707   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00708   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00709   * @note   This bit can only be programmed when Digital Filter is disabled.
00710   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
00711   * @param  I2Cx I2C Instance.
00712   * @retval None
00713   */
00714 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
00715 {
00716   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00717 }
00718
00719 /**
00720   * @brief  Disable Wakeup from STOP.
00721   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00722   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00723   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
00724   * @param  I2Cx I2C Instance.
00725   * @retval None
00726   */
00727 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
00728 {
00729   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00730 }
00731
00732 /**
00733   * @brief  Check if Wakeup from STOP is enabled or disabled.
00734   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00735   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00736   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
00737   * @param  I2Cx I2C Instance.
00738   * @retval State of bit (1 or 0).
00739   */
00740 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
00741 {
00742   return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
00743 }
00744
00745 /**
00746   * @brief  Enable General Call.
00747   * @note   When enabled the Address 0x00 is ACKed.
00748   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
00749   * @param  I2Cx I2C Instance.
00750   * @retval None
00751   */
00752 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
00753 {
00754   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00755 }
00756
00757 /**
00758   * @brief  Disable General Call.
00759   * @note   When disabled the Address 0x00 is NACKed.
00760   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
00761   * @param  I2Cx I2C Instance.
00762   * @retval None
00763   */
00764 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
00765 {
00766   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00767 }
00768
00769 /**
00770   * @brief  Check if General Call is enabled or disabled.
00771   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
00772   * @param  I2Cx I2C Instance.
00773   * @retval State of bit (1 or 0).
00774   */
00775 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
00776 {
00777   return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
00778 }
00779
00780 /**
00781   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
00782   * @note   Changing this bit is not allowed, when the START bit is set.
00783   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
00784   * @param  I2Cx I2C Instance.
00785   * @param  AddressingMode This parameter can be one of the following values:
00786   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00787   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00788   * @retval None
00789   */
00790 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
00791 {
00792   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
00793 }
00794
00795 /**
00796   * @brief  Get the Master addressing mode.
00797   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
00798   * @param  I2Cx I2C Instance.
00799   * @retval Returned value can be one of the following values:
00800   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00801   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00802   */
00803 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
00804 {
00805   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
00806 }
00807
00808 /**
00809   * @brief  Set the Own Address1.
00810   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
00811   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
00812   * @param  I2Cx I2C Instance.
00813   * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
00814   * @param  OwnAddrSize This parameter can be one of the following values:
00815   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
00816   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
00817   * @retval None
00818   */
00819 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
00820 {
00821   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
00822 }
00823
00824 /**
00825   * @brief  Enable acknowledge on Own Address1 match address.
00826   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
00827   * @param  I2Cx I2C Instance.
00828   * @retval None
00829   */
00830 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
00831 {
00832   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00833 }
00834
00835 /**
00836   * @brief  Disable acknowledge on Own Address1 match address.
00837   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
00838   * @param  I2Cx I2C Instance.
00839   * @retval None
00840   */
00841 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
00842 {
00843   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00844 }
00845
00846 /**
00847   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00848   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
00849   * @param  I2Cx I2C Instance.
00850   * @retval State of bit (1 or 0).
00851   */
00852 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
00853 {
00854   return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
00855 }
00856
00857 /**
00858   * @brief  Set the 7bits Own Address2.
00859   * @note   This action has no effect if own address2 is enabled.
00860   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
00861   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
00862   * @param  I2Cx I2C Instance.
00863   * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
00864   * @param  OwnAddrMask This parameter can be one of the following values:
00865   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
00866   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
00867   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
00868   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
00869   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
00870   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
00871   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
00872   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
00873   * @retval None
00874   */
00875 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
00876 {
00877   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
00878 }
00879
00880 /**
00881   * @brief  Enable acknowledge on Own Address2 match address.
00882   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
00883   * @param  I2Cx I2C Instance.
00884   * @retval None
00885   */
00886 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
00887 {
00888   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00889 }
00890
00891 /**
00892   * @brief  Disable  acknowledge on Own Address2 match address.
00893   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
00894   * @param  I2Cx I2C Instance.
00895   * @retval None
00896   */
00897 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
00898 {
00899   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00900 }
00901
00902 /**
00903   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00904   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
00905   * @param  I2Cx I2C Instance.
00906   * @retval State of bit (1 or 0).
00907   */
00908 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
00909 {
00910   return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
00911 }
00912
00913 /**
00914   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00915   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00916   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
00917   * @param  I2Cx I2C Instance.
00918   * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
00919   * @note   This parameter is computed with the STM32CubeMX Tool.
00920   * @retval None
00921   */
00922 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
00923 {
00924   WRITE_REG(I2Cx->TIMINGR, Timing);
00925 }
00926
00927 /**
00928   * @brief  Get the Timing Prescaler setting.
00929   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
00930   * @param  I2Cx I2C Instance.
00931   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00932   */
00933 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
00934 {
00935   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
00936 }
00937
00938 /**
00939   * @brief  Get the SCL low period setting.
00940   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
00941   * @param  I2Cx I2C Instance.
00942   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00943   */
00944 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
00945 {
00946   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
00947 }
00948
00949 /**
00950   * @brief  Get the SCL high period setting.
00951   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
00952   * @param  I2Cx I2C Instance.
00953   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00954   */
00955 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
00956 {
00957   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
00958 }
00959
00960 /**
00961   * @brief  Get the SDA hold time.
00962   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
00963   * @param  I2Cx I2C Instance.
00964   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00965   */
00966 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
00967 {
00968   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
00969 }
00970
00971 /**
00972   * @brief  Get the SDA setup time.
00973   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
00974   * @param  I2Cx I2C Instance.
00975   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00976   */
00977 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
00978 {
00979   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
00980 }
00981
00982 /**
00983   * @brief  Configure peripheral mode.
00984   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00985   *         SMBus feature is supported by the I2Cx Instance.
00986   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
00987   *         CR1          SMBDEN        LL_I2C_SetMode
00988   * @param  I2Cx I2C Instance.
00989   * @param  PeripheralMode This parameter can be one of the following values:
00990   *         @arg @ref LL_I2C_MODE_I2C
00991   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00992   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00993   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
00997 {
00998   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
00999 }
01000
01001 /**
01002   * @brief  Get peripheral mode.
01003   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01004   *         SMBus feature is supported by the I2Cx Instance.
01005   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
01006   *         CR1          SMBDEN        LL_I2C_GetMode
01007   * @param  I2Cx I2C Instance.
01008   * @retval Returned value can be one of the following values:
01009   *         @arg @ref LL_I2C_MODE_I2C
01010   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
01011   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
01012   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
01013   */
01014 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
01015 {
01016   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
01017 }
01018
01019 /**
01020   * @brief  Enable SMBus alert (Host or Device mode)
01021   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01022   *         SMBus feature is supported by the I2Cx Instance.
01023   * @note   SMBus Device mode:
01024   *         - SMBus Alert pin is drived low and
01025   *           Alert Response Address Header acknowledge is enabled.
01026   *         SMBus Host mode:
01027   *         - SMBus Alert pin management is supported.
01028   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
01029   * @param  I2Cx I2C Instance.
01030   * @retval None
01031   */
01032 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
01033 {
01034   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01035 }
01036
01037 /**
01038   * @brief  Disable SMBus alert (Host or Device mode)
01039   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01040   *         SMBus feature is supported by the I2Cx Instance.
01041   * @note   SMBus Device mode:
01042   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
01043   *           Alert Response Address Header acknowledge is disabled.
01044   *         SMBus Host mode:
01045   *         - SMBus Alert pin management is not supported.
01046   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
01047   * @param  I2Cx I2C Instance.
01048   * @retval None
01049   */
01050 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
01051 {
01052   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01053 }
01054
01055 /**
01056   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
01057   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01058   *         SMBus feature is supported by the I2Cx Instance.
01059   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
01060   * @param  I2Cx I2C Instance.
01061   * @retval State of bit (1 or 0).
01062   */
01063 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
01064 {
01065   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
01066 }
01067
01068 /**
01069   * @brief  Enable SMBus Packet Error Calculation (PEC).
01070   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01071   *         SMBus feature is supported by the I2Cx Instance.
01072   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
01073   * @param  I2Cx I2C Instance.
01074   * @retval None
01075   */
01076 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
01077 {
01078   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01079 }
01080
01081 /**
01082   * @brief  Disable SMBus Packet Error Calculation (PEC).
01083   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01084   *         SMBus feature is supported by the I2Cx Instance.
01085   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
01086   * @param  I2Cx I2C Instance.
01087   * @retval None
01088   */
01089 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
01090 {
01091   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01092 }
01093
01094 /**
01095   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
01096   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01097   *         SMBus feature is supported by the I2Cx Instance.
01098   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
01099   * @param  I2Cx I2C Instance.
01100   * @retval State of bit (1 or 0).
01101   */
01102 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
01103 {
01104   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
01105 }
01106
01107 /**
01108   * @brief  Configure the SMBus Clock Timeout.
01109   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01110   *         SMBus feature is supported by the I2Cx Instance.
01111   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01112   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
01113   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
01114   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
01115   * @param  I2Cx I2C Instance.
01116   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01117   * @param  TimeoutAMode This parameter can be one of the following values:
01118   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01119   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01120   * @param  TimeoutB
01121   * @retval None
01122   */
01123 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
01124                                                uint32_t TimeoutB)
01125 {
01126   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
01127              TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
01128 }
01129
01130 /**
01131   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
01132   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01133   *         SMBus feature is supported by the I2Cx Instance.
01134   * @note   These bits can only be programmed when TimeoutA is disabled.
01135   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
01136   * @param  I2Cx I2C Instance.
01137   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01138   * @retval None
01139   */
01140 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
01141 {
01142   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
01143 }
01144
01145 /**
01146   * @brief  Get the SMBus Clock TimeoutA setting.
01147   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01148   *         SMBus feature is supported by the I2Cx Instance.
01149   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
01150   * @param  I2Cx I2C Instance.
01151   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01152   */
01153 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
01154 {
01155   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
01156 }
01157
01158 /**
01159   * @brief  Set the SMBus Clock TimeoutA mode.
01160   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01161   *         SMBus feature is supported by the I2Cx Instance.
01162   * @note   This bit can only be programmed when TimeoutA is disabled.
01163   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
01164   * @param  I2Cx I2C Instance.
01165   * @param  TimeoutAMode This parameter can be one of the following values:
01166   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01167   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01168   * @retval None
01169   */
01170 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
01171 {
01172   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
01173 }
01174
01175 /**
01176   * @brief  Get the SMBus Clock TimeoutA mode.
01177   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01178   *         SMBus feature is supported by the I2Cx Instance.
01179   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
01180   * @param  I2Cx I2C Instance.
01181   * @retval Returned value can be one of the following values:
01182   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01183   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01184   */
01185 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
01186 {
01187   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
01188 }
01189
01190 /**
01191   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
01192   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01193   *         SMBus feature is supported by the I2Cx Instance.
01194   * @note   These bits can only be programmed when TimeoutB is disabled.
01195   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
01196   * @param  I2Cx I2C Instance.
01197   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01198   * @retval None
01199   */
01200 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
01201 {
01202   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
01203 }
01204
01205 /**
01206   * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
01207   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01208   *         SMBus feature is supported by the I2Cx Instance.
01209   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
01210   * @param  I2Cx I2C Instance.
01211   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01212   */
01213 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
01214 {
01215   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
01216 }
01217
01218 /**
01219   * @brief  Enable the SMBus Clock Timeout.
01220   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01221   *         SMBus feature is supported by the I2Cx Instance.
01222   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
01223   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
01224   * @param  I2Cx I2C Instance.
01225   * @param  ClockTimeout This parameter can be one of the following values:
01226   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01227   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01228   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01229   * @retval None
01230   */
01231 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01232 {
01233   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01234 }
01235
01236 /**
01237   * @brief  Disable the SMBus Clock Timeout.
01238   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01239   *         SMBus feature is supported by the I2Cx Instance.
01240   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
01241   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
01242   * @param  I2Cx I2C Instance.
01243   * @param  ClockTimeout This parameter can be one of the following values:
01244   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01245   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01246   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01247   * @retval None
01248   */
01249 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01250 {
01251   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01252 }
01253
01254 /**
01255   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
01256   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01257   *         SMBus feature is supported by the I2Cx Instance.
01258   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
01259   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
01260   * @param  I2Cx I2C Instance.
01261   * @param  ClockTimeout This parameter can be one of the following values:
01262   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01263   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01264   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01265   * @retval State of bit (1 or 0).
01266   */
01267 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01268 {
01269   return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
01270            (ClockTimeout)) ? 1UL : 0UL);
01271 }
01272
01273 /**
01274   * @}
01275   */
01276
01277 /** @defgroup I2C_LL_EF_IT_Management IT_Management
01278   * @{
01279   */
01280
01281 /**
01282   * @brief  Enable TXIS interrupt.
01283   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
01284   * @param  I2Cx I2C Instance.
01285   * @retval None
01286   */
01287 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
01288 {
01289   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01290 }
01291
01292 /**
01293   * @brief  Disable TXIS interrupt.
01294   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
01295   * @param  I2Cx I2C Instance.
01296   * @retval None
01297   */
01298 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
01299 {
01300   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01301 }
01302
01303 /**
01304   * @brief  Check if the TXIS Interrupt is enabled or disabled.
01305   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
01306   * @param  I2Cx I2C Instance.
01307   * @retval State of bit (1 or 0).
01308   */
01309 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
01310 {
01311   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
01312 }
01313
01314 /**
01315   * @brief  Enable RXNE interrupt.
01316   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
01317   * @param  I2Cx I2C Instance.
01318   * @retval None
01319   */
01320 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
01321 {
01322   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01323 }
01324
01325 /**
01326   * @brief  Disable RXNE interrupt.
01327   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
01328   * @param  I2Cx I2C Instance.
01329   * @retval None
01330   */
01331 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
01332 {
01333   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01334 }
01335
01336 /**
01337   * @brief  Check if the RXNE Interrupt is enabled or disabled.
01338   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
01339   * @param  I2Cx I2C Instance.
01340   * @retval State of bit (1 or 0).
01341   */
01342 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
01343 {
01344   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
01345 }
01346
01347 /**
01348   * @brief  Enable Address match interrupt (slave mode only).
01349   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
01350   * @param  I2Cx I2C Instance.
01351   * @retval None
01352   */
01353 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
01354 {
01355   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01356 }
01357
01358 /**
01359   * @brief  Disable Address match interrupt (slave mode only).
01360   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
01361   * @param  I2Cx I2C Instance.
01362   * @retval None
01363   */
01364 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
01365 {
01366   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01367 }
01368
01369 /**
01370   * @brief  Check if Address match interrupt is enabled or disabled.
01371   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
01372   * @param  I2Cx I2C Instance.
01373   * @retval State of bit (1 or 0).
01374   */
01375 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
01376 {
01377   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
01378 }
01379
01380 /**
01381   * @brief  Enable Not acknowledge received interrupt.
01382   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
01383   * @param  I2Cx I2C Instance.
01384   * @retval None
01385   */
01386 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
01387 {
01388   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01389 }
01390
01391 /**
01392   * @brief  Disable Not acknowledge received interrupt.
01393   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
01394   * @param  I2Cx I2C Instance.
01395   * @retval None
01396   */
01397 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
01398 {
01399   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01400 }
01401
01402 /**
01403   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
01404   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
01405   * @param  I2Cx I2C Instance.
01406   * @retval State of bit (1 or 0).
01407   */
01408 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
01409 {
01410   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
01411 }
01412
01413 /**
01414   * @brief  Enable STOP detection interrupt.
01415   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
01416   * @param  I2Cx I2C Instance.
01417   * @retval None
01418   */
01419 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
01420 {
01421   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01422 }
01423
01424 /**
01425   * @brief  Disable STOP detection interrupt.
01426   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
01427   * @param  I2Cx I2C Instance.
01428   * @retval None
01429   */
01430 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
01431 {
01432   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01433 }
01434
01435 /**
01436   * @brief  Check if STOP detection interrupt is enabled or disabled.
01437   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
01438   * @param  I2Cx I2C Instance.
01439   * @retval State of bit (1 or 0).
01440   */
01441 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
01442 {
01443   return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
01444 }
01445
01446 /**
01447   * @brief  Enable Transfer Complete interrupt.
01448   * @note   Any of these events will generate interrupt :
01449   *         Transfer Complete (TC)
01450   *         Transfer Complete Reload (TCR)
01451   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
01452   * @param  I2Cx I2C Instance.
01453   * @retval None
01454   */
01455 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
01456 {
01457   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01458 }
01459
01460 /**
01461   * @brief  Disable Transfer Complete interrupt.
01462   * @note   Any of these events will generate interrupt :
01463   *         Transfer Complete (TC)
01464   *         Transfer Complete Reload (TCR)
01465   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
01466   * @param  I2Cx I2C Instance.
01467   * @retval None
01468   */
01469 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
01470 {
01471   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01472 }
01473
01474 /**
01475   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
01476   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
01477   * @param  I2Cx I2C Instance.
01478   * @retval State of bit (1 or 0).
01479   */
01480 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
01481 {
01482   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
01483 }
01484
01485 /**
01486   * @brief  Enable Error interrupts.
01487   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01488   *         SMBus feature is supported by the I2Cx Instance.
01489   * @note   Any of these errors will generate interrupt :
01490   *         Arbitration Loss (ARLO)
01491   *         Bus Error detection (BERR)
01492   *         Overrun/Underrun (OVR)
01493   *         SMBus Timeout detection (TIMEOUT)
01494   *         SMBus PEC error detection (PECERR)
01495   *         SMBus Alert pin event detection (ALERT)
01496   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
01497   * @param  I2Cx I2C Instance.
01498   * @retval None
01499   */
01500 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
01501 {
01502   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01503 }
01504
01505 /**
01506   * @brief  Disable Error interrupts.
01507   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01508   *         SMBus feature is supported by the I2Cx Instance.
01509   * @note   Any of these errors will generate interrupt :
01510   *         Arbitration Loss (ARLO)
01511   *         Bus Error detection (BERR)
01512   *         Overrun/Underrun (OVR)
01513   *         SMBus Timeout detection (TIMEOUT)
01514   *         SMBus PEC error detection (PECERR)
01515   *         SMBus Alert pin event detection (ALERT)
01516   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
01517   * @param  I2Cx I2C Instance.
01518   * @retval None
01519   */
01520 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
01521 {
01522   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01523 }
01524
01525 /**
01526   * @brief  Check if Error interrupts are enabled or disabled.
01527   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
01528   * @param  I2Cx I2C Instance.
01529   * @retval State of bit (1 or 0).
01530   */
01531 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
01532 {
01533   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
01534 }
01535
01536 /**
01537   * @}
01538   */
01539
01540 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
01541   * @{
01542   */
01543
01544 /**
01545   * @brief  Indicate the status of Transmit data register empty flag.
01546   * @note   RESET: When next data is written in Transmit data register.
01547   *         SET: When Transmit data register is empty.
01548   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
01549   * @param  I2Cx I2C Instance.
01550   * @retval State of bit (1 or 0).
01551   */
01552 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
01553 {
01554   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
01555 }
01556
01557 /**
01558   * @brief  Indicate the status of Transmit interrupt flag.
01559   * @note   RESET: When next data is written in Transmit data register.
01560   *         SET: When Transmit data register is empty.
01561   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
01562   * @param  I2Cx I2C Instance.
01563   * @retval State of bit (1 or 0).
01564   */
01565 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
01566 {
01567   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
01568 }
01569
01570 /**
01571   * @brief  Indicate the status of Receive data register not empty flag.
01572   * @note   RESET: When Receive data register is read.
01573   *         SET: When the received data is copied in Receive data register.
01574   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
01575   * @param  I2Cx I2C Instance.
01576   * @retval State of bit (1 or 0).
01577   */
01578 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
01579 {
01580   return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
01581 }
01582
01583 /**
01584   * @brief  Indicate the status of Address matched flag (slave mode).
01585   * @note   RESET: Clear default value.
01586   *         SET: When the received slave address matched with one of the enabled slave address.
01587   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
01588   * @param  I2Cx I2C Instance.
01589   * @retval State of bit (1 or 0).
01590   */
01591 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
01592 {
01593   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
01594 }
01595
01596 /**
01597   * @brief  Indicate the status of Not Acknowledge received flag.
01598   * @note   RESET: Clear default value.
01599   *         SET: When a NACK is received after a byte transmission.
01600   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
01601   * @param  I2Cx I2C Instance.
01602   * @retval State of bit (1 or 0).
01603   */
01604 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
01605 {
01606   return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
01607 }
01608
01609 /**
01610   * @brief  Indicate the status of Stop detection flag.
01611   * @note   RESET: Clear default value.
01612   *         SET: When a Stop condition is detected.
01613   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
01614   * @param  I2Cx I2C Instance.
01615   * @retval State of bit (1 or 0).
01616   */
01617 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
01618 {
01619   return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
01620 }
01621
01622 /**
01623   * @brief  Indicate the status of Transfer complete flag (master mode).
01624   * @note   RESET: Clear default value.
01625   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
01626   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
01627   * @param  I2Cx I2C Instance.
01628   * @retval State of bit (1 or 0).
01629   */
01630 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
01631 {
01632   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
01633 }
01634
01635 /**
01636   * @brief  Indicate the status of Transfer complete flag (master mode).
01637   * @note   RESET: Clear default value.
01638   *         SET: When RELOAD=1 and NBYTES date have been transferred.
01639   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
01640   * @param  I2Cx I2C Instance.
01641   * @retval State of bit (1 or 0).
01642   */
01643 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
01644 {
01645   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
01646 }
01647
01648 /**
01649   * @brief  Indicate the status of Bus error flag.
01650   * @note   RESET: Clear default value.
01651   *         SET: When a misplaced Start or Stop condition is detected.
01652   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
01653   * @param  I2Cx I2C Instance.
01654   * @retval State of bit (1 or 0).
01655   */
01656 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
01657 {
01658   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
01659 }
01660
01661 /**
01662   * @brief  Indicate the status of Arbitration lost flag.
01663   * @note   RESET: Clear default value.
01664   *         SET: When arbitration lost.
01665   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
01666   * @param  I2Cx I2C Instance.
01667   * @retval State of bit (1 or 0).
01668   */
01669 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
01670 {
01671   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
01672 }
01673
01674 /**
01675   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
01676   * @note   RESET: Clear default value.
01677   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
01678   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
01679   * @param  I2Cx I2C Instance.
01680   * @retval State of bit (1 or 0).
01681   */
01682 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
01683 {
01684   return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
01685 }
01686
01687 /**
01688   * @brief  Indicate the status of SMBus PEC error flag in reception.
01689   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01690   *         SMBus feature is supported by the I2Cx Instance.
01691   * @note   RESET: Clear default value.
01692   *         SET: When the received PEC does not match with the PEC register content.
01693   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
01694   * @param  I2Cx I2C Instance.
01695   * @retval State of bit (1 or 0).
01696   */
01697 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01698 {
01699   return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
01700 }
01701
01702 /**
01703   * @brief  Indicate the status of SMBus Timeout detection flag.
01704   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01705   *         SMBus feature is supported by the I2Cx Instance.
01706   * @note   RESET: Clear default value.
01707   *         SET: When a timeout or extended clock timeout occurs.
01708   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
01709   * @param  I2Cx I2C Instance.
01710   * @retval State of bit (1 or 0).
01711   */
01712 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01713 {
01714   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
01715 }
01716
01717 /**
01718   * @brief  Indicate the status of SMBus alert flag.
01719   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01720   *         SMBus feature is supported by the I2Cx Instance.
01721   * @note   RESET: Clear default value.
01722   *         SET: When SMBus host configuration, SMBus alert enabled and
01723   *              a falling edge event occurs on SMBA pin.
01724   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
01725   * @param  I2Cx I2C Instance.
01726   * @retval State of bit (1 or 0).
01727   */
01728 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01729 {
01730   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
01731 }
01732
01733 /**
01734   * @brief  Indicate the status of Bus Busy flag.
01735   * @note   RESET: Clear default value.
01736   *         SET: When a Start condition is detected.
01737   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
01738   * @param  I2Cx I2C Instance.
01739   * @retval State of bit (1 or 0).
01740   */
01741 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
01742 {
01743   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
01744 }
01745
01746 /**
01747   * @brief  Clear Address Matched flag.
01748   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
01749   * @param  I2Cx I2C Instance.
01750   * @retval None
01751   */
01752 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
01753 {
01754   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
01755 }
01756
01757 /**
01758   * @brief  Clear Not Acknowledge flag.
01759   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
01760   * @param  I2Cx I2C Instance.
01761   * @retval None
01762   */
01763 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
01764 {
01765   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
01766 }
01767
01768 /**
01769   * @brief  Clear Stop detection flag.
01770   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
01771   * @param  I2Cx I2C Instance.
01772   * @retval None
01773   */
01774 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
01775 {
01776   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
01777 }
01778
01779 /**
01780   * @brief  Clear Transmit data register empty flag (TXE).
01781   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
01782   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
01783   * @param  I2Cx I2C Instance.
01784   * @retval None
01785   */
01786 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
01787 {
01788   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
01789 }
01790
01791 /**
01792   * @brief  Clear Bus error flag.
01793   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
01794   * @param  I2Cx I2C Instance.
01795   * @retval None
01796   */
01797 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
01798 {
01799   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
01800 }
01801
01802 /**
01803   * @brief  Clear Arbitration lost flag.
01804   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
01805   * @param  I2Cx I2C Instance.
01806   * @retval None
01807   */
01808 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
01809 {
01810   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
01811 }
01812
01813 /**
01814   * @brief  Clear Overrun/Underrun flag.
01815   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
01816   * @param  I2Cx I2C Instance.
01817   * @retval None
01818   */
01819 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
01820 {
01821   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
01822 }
01823
01824 /**
01825   * @brief  Clear SMBus PEC error flag.
01826   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01827   *         SMBus feature is supported by the I2Cx Instance.
01828   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
01829   * @param  I2Cx I2C Instance.
01830   * @retval None
01831   */
01832 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01833 {
01834   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
01835 }
01836
01837 /**
01838   * @brief  Clear SMBus Timeout detection flag.
01839   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01840   *         SMBus feature is supported by the I2Cx Instance.
01841   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
01842   * @param  I2Cx I2C Instance.
01843   * @retval None
01844   */
01845 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01846 {
01847   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
01848 }
01849
01850 /**
01851   * @brief  Clear SMBus Alert flag.
01852   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01853   *         SMBus feature is supported by the I2Cx Instance.
01854   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
01855   * @param  I2Cx I2C Instance.
01856   * @retval None
01857   */
01858 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01859 {
01860   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
01861 }
01862
01863 /**
01864   * @}
01865   */
01866
01867 /** @defgroup I2C_LL_EF_Data_Management Data_Management
01868   * @{
01869   */
01870
01871 /**
01872   * @brief  Enable automatic STOP condition generation (master mode).
01873   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
01874   *         This bit has no effect in slave mode or when RELOAD bit is set.
01875   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
01876   * @param  I2Cx I2C Instance.
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
01880 {
01881   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01882 }
01883
01884 /**
01885   * @brief  Disable automatic STOP condition generation (master mode).
01886   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
01887   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
01888   * @param  I2Cx I2C Instance.
01889   * @retval None
01890   */
01891 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
01892 {
01893   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01894 }
01895
01896 /**
01897   * @brief  Check if automatic STOP condition is enabled or disabled.
01898   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
01899   * @param  I2Cx I2C Instance.
01900   * @retval State of bit (1 or 0).
01901   */
01902 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
01903 {
01904   return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
01905 }
01906
01907 /**
01908   * @brief  Enable reload mode (master mode).
01909   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
01910   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
01911   * @param  I2Cx I2C Instance.
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
01915 {
01916   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01917 }
01918
01919 /**
01920   * @brief  Disable reload mode (master mode).
01921   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
01922   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
01923   * @param  I2Cx I2C Instance.
01924   * @retval None
01925   */
01926 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
01927 {
01928   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01929 }
01930
01931 /**
01932   * @brief  Check if reload mode is enabled or disabled.
01933   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
01934   * @param  I2Cx I2C Instance.
01935   * @retval State of bit (1 or 0).
01936   */
01937 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
01938 {
01939   return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
01940 }
01941
01942 /**
01943   * @brief  Configure the number of bytes for transfer.
01944   * @note   Changing these bits when START bit is set is not allowed.
01945   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
01946   * @param  I2Cx I2C Instance.
01947   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01948   * @retval None
01949   */
01950 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
01951 {
01952   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
01953 }
01954
01955 /**
01956   * @brief  Get the number of bytes configured for transfer.
01957   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
01958   * @param  I2Cx I2C Instance.
01959   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
01960   */
01961 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
01962 {
01963   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
01964 }
01965
01966 /**
01967   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
01968             or next received byte.
01969   * @note   Usage in Slave mode only.
01970   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
01971   * @param  I2Cx I2C Instance.
01972   * @param  TypeAcknowledge This parameter can be one of the following values:
01973   *         @arg @ref LL_I2C_ACK
01974   *         @arg @ref LL_I2C_NACK
01975   * @retval None
01976   */
01977 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
01978 {
01979   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
01980 }
01981
01982 /**
01983   * @brief  Generate a START or RESTART condition
01984   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
01985   *         This action has no effect when RELOAD is set.
01986   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
01987   * @param  I2Cx I2C Instance.
01988   * @retval None
01989   */
01990 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
01991 {
01992   SET_BIT(I2Cx->CR2, I2C_CR2_START);
01993 }
01994
01995 /**
01996   * @brief  Generate a STOP condition after the current byte transfer (master mode).
01997   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
01998   * @param  I2Cx I2C Instance.
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
02002 {
02003   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
02004 }
02005
02006 /**
02007   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
02008   * @note   The master sends the complete 10bit slave address read sequence :
02009   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
02010             in Read direction.
02011   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
02012   * @param  I2Cx I2C Instance.
02013   * @retval None
02014   */
02015 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
02016 {
02017   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02018 }
02019
02020 /**
02021   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
02022   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
02023   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
02024   * @param  I2Cx I2C Instance.
02025   * @retval None
02026   */
02027 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
02028 {
02029   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02030 }
02031
02032 /**
02033   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
02034   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
02035   * @param  I2Cx I2C Instance.
02036   * @retval State of bit (1 or 0).
02037   */
02038 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
02039 {
02040   return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
02041 }
02042
02043 /**
02044   * @brief  Configure the transfer direction (master mode).
02045   * @note   Changing these bits when START bit is set is not allowed.
02046   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
02047   * @param  I2Cx I2C Instance.
02048   * @param  TransferRequest This parameter can be one of the following values:
02049   *         @arg @ref LL_I2C_REQUEST_WRITE
02050   *         @arg @ref LL_I2C_REQUEST_READ
02051   * @retval None
02052   */
02053 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
02054 {
02055   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
02056 }
02057
02058 /**
02059   * @brief  Get the transfer direction requested (master mode).
02060   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
02061   * @param  I2Cx I2C Instance.
02062   * @retval Returned value can be one of the following values:
02063   *         @arg @ref LL_I2C_REQUEST_WRITE
02064   *         @arg @ref LL_I2C_REQUEST_READ
02065   */
02066 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
02067 {
02068   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
02069 }
02070
02071 /**
02072   * @brief  Configure the slave address for transfer (master mode).
02073   * @note   Changing these bits when START bit is set is not allowed.
02074   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
02075   * @param  I2Cx I2C Instance.
02076   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
02077   * @retval None
02078   */
02079 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
02080 {
02081   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
02082 }
02083
02084 /**
02085   * @brief  Get the slave address programmed for transfer.
02086   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
02087   * @param  I2Cx I2C Instance.
02088   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
02089   */
02090 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
02091 {
02092   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
02093 }
02094
02095 /**
02096   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
02097   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
02098   *         CR2          ADD10         LL_I2C_HandleTransfer\n
02099   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
02100   *         CR2          START         LL_I2C_HandleTransfer\n
02101   *         CR2          STOP          LL_I2C_HandleTransfer\n
02102   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
02103   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
02104   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
02105   *         CR2          HEAD10R       LL_I2C_HandleTransfer
02106   * @param  I2Cx I2C Instance.
02107   * @param  SlaveAddr Specifies the slave address to be programmed.
02108   * @param  SlaveAddrSize This parameter can be one of the following values:
02109   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
02110   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
02111   * @param  TransferSize Specifies the number of bytes to be programmed.
02112   *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
02113   * @param  EndMode This parameter can be one of the following values:
02114   *         @arg @ref LL_I2C_MODE_RELOAD
02115   *         @arg @ref LL_I2C_MODE_AUTOEND
02116   *         @arg @ref LL_I2C_MODE_SOFTEND
02117   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
02118   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
02119   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
02120   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
02121   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
02122   * @param  Request This parameter can be one of the following values:
02123   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
02124   *         @arg @ref LL_I2C_GENERATE_STOP
02125   *         @arg @ref LL_I2C_GENERATE_START_READ
02126   *         @arg @ref LL_I2C_GENERATE_START_WRITE
02127   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
02128   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
02129   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
02130   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
02131   * @retval None
02132   */
02133 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
02134                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
02135 {
02136   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
02137              (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
02138              I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
02139              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
02140              SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
02141 }
02142
02143 /**
02144   * @brief  Indicate the value of transfer direction (slave mode).
02145   * @note   RESET: Write transfer, Slave enters in receiver mode.
02146   *         SET: Read transfer, Slave enters in transmitter mode.
02147   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
02148   * @param  I2Cx I2C Instance.
02149   * @retval Returned value can be one of the following values:
02150   *         @arg @ref LL_I2C_DIRECTION_WRITE
02151   *         @arg @ref LL_I2C_DIRECTION_READ
02152   */
02153 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
02154 {
02155   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
02156 }
02157
02158 /**
02159   * @brief  Return the slave matched address.
02160   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
02161   * @param  I2Cx I2C Instance.
02162   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
02163   */
02164 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
02165 {
02166   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
02167 }
02168
02169 /**
02170   * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
02171   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02172   *         SMBus feature is supported by the I2Cx Instance.
02173   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
02174             or an Address Matched is received.
02175   *         This bit has no effect when RELOAD bit is set.
02176   *         This bit has no effect in device mode when SBC bit is not set.
02177   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
02178   * @param  I2Cx I2C Instance.
02179   * @retval None
02180   */
02181 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
02182 {
02183   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
02184 }
02185
02186 /**
02187   * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
02188   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02189   *         SMBus feature is supported by the I2Cx Instance.
02190   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
02191   * @param  I2Cx I2C Instance.
02192   * @retval State of bit (1 or 0).
02193   */
02194 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
02195 {
02196   return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
02197 }
02198
02199 /**
02200   * @brief  Get the SMBus Packet Error byte calculated.
02201   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02202   *         SMBus feature is supported by the I2Cx Instance.
02203   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
02204   * @param  I2Cx I2C Instance.
02205   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02206   */
02207 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
02208 {
02209   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
02210 }
02211
02212 /**
02213   * @brief  Read Receive Data register.
02214   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
02215   * @param  I2Cx I2C Instance.
02216   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02217   */
02218 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
02219 {
02220   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
02221 }
02222
02223 /**
02224   * @brief  Write in Transmit Data Register .
02225   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
02226   * @param  I2Cx I2C Instance.
02227   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
02228   * @retval None
02229   */
02230 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
02231 {
02232   WRITE_REG(I2Cx->TXDR, Data);
02233 }
02234
02235 /**
02236   * @}
02237   */
02238
02239 #if defined(USE_FULL_LL_DRIVER)
02240 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
02241   * @{
02242   */
02243
02244 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
02245 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
02246 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
02247
02248
02249 /**
02250   * @}
02251   */
02252 #endif /* USE_FULL_LL_DRIVER */
02253
02254 /**
02255   * @}
02256   */
02257
02258 /**
02259   * @}
02260   */
02261
02262 #endif /* I2C1 || I2C2 || I2C3 */
02263
02264 /**
02265   * @}
02266   */
02267
02268 #ifdef __cplusplus
02269 }
02270 #endif
02271
02272 #endif /* STM32G0xx_LL_I2C_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_iwdg.h Source File

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stm32g0xx_ll_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_IWDG_H
00021 #define STM32G0xx_LL_IWDG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(IWDG)
00035
00036 /** @defgroup IWDG_LL IWDG
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
00045   * @{
00046   */
00047 #define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
00048 #define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
00049 #define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
00050 #define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
00051 /**
00052   * @}
00053   */
00054
00055 /* Private macros ------------------------------------------------------------*/
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
00064   * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
00065   * @{
00066   */
00067 #define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
00068 #define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
00069 #define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
00075   * @{
00076   */
00077 #define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
00078 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
00079 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
00080 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
00081 #define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
00082 #define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
00083 #define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 /* Exported macro ------------------------------------------------------------*/
00093 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
00094   * @{
00095   */
00096
00097 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
00098   * @{
00099   */
00100
00101 /**
00102   * @brief  Write a value in IWDG register
00103   * @param  __INSTANCE__ IWDG Instance
00104   * @param  __REG__ Register to be written
00105   * @param  __VALUE__ Value to be written in the register
00106   * @retval None
00107   */
00108 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00109
00110 /**
00111   * @brief  Read a value in IWDG register
00112   * @param  __INSTANCE__ IWDG Instance
00113   * @param  __REG__ Register to be read
00114   * @retval Register value
00115   */
00116 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00117 /**
00118   * @}
00119   */
00120
00121 /**
00122   * @}
00123   */
00124
00125
00126 /* Exported functions --------------------------------------------------------*/
00127 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
00128   * @{
00129   */
00130 /** @defgroup IWDG_LL_EF_Configuration Configuration
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  Start the Independent Watchdog
00136   * @note   Except if the hardware watchdog option is selected
00137   * @rmtoll KR           KEY           LL_IWDG_Enable
00138   * @param  IWDGx IWDG Instance
00139   * @retval None
00140   */
00141 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
00142 {
00143   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
00144 }
00145
00146 /**
00147   * @brief  Reloads IWDG counter with value defined in the reload register
00148   * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
00149   * @param  IWDGx IWDG Instance
00150   * @retval None
00151   */
00152 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
00153 {
00154   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
00155 }
00156
00157 /**
00158   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00159   * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
00160   * @param  IWDGx IWDG Instance
00161   * @retval None
00162   */
00163 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
00164 {
00165   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
00166 }
00167
00168 /**
00169   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00170   * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
00171   * @param  IWDGx IWDG Instance
00172   * @retval None
00173   */
00174 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
00175 {
00176   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
00177 }
00178
00179 /**
00180   * @brief  Select the prescaler of the IWDG
00181   * @rmtoll PR           PR            LL_IWDG_SetPrescaler
00182   * @param  IWDGx IWDG Instance
00183   * @param  Prescaler This parameter can be one of the following values:
00184   *         @arg @ref LL_IWDG_PRESCALER_4
00185   *         @arg @ref LL_IWDG_PRESCALER_8
00186   *         @arg @ref LL_IWDG_PRESCALER_16
00187   *         @arg @ref LL_IWDG_PRESCALER_32
00188   *         @arg @ref LL_IWDG_PRESCALER_64
00189   *         @arg @ref LL_IWDG_PRESCALER_128
00190   *         @arg @ref LL_IWDG_PRESCALER_256
00191   * @retval None
00192   */
00193 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
00194 {
00195   WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
00196 }
00197
00198 /**
00199   * @brief  Get the selected prescaler of the IWDG
00200   * @rmtoll PR           PR            LL_IWDG_GetPrescaler
00201   * @param  IWDGx IWDG Instance
00202   * @retval Returned value can be one of the following values:
00203   *         @arg @ref LL_IWDG_PRESCALER_4
00204   *         @arg @ref LL_IWDG_PRESCALER_8
00205   *         @arg @ref LL_IWDG_PRESCALER_16
00206   *         @arg @ref LL_IWDG_PRESCALER_32
00207   *         @arg @ref LL_IWDG_PRESCALER_64
00208   *         @arg @ref LL_IWDG_PRESCALER_128
00209   *         @arg @ref LL_IWDG_PRESCALER_256
00210   */
00211 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
00212 {
00213   return (READ_REG(IWDGx->PR));
00214 }
00215
00216 /**
00217   * @brief  Specify the IWDG down-counter reload value
00218   * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
00219   * @param  IWDGx IWDG Instance
00220   * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
00221   * @retval None
00222   */
00223 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
00224 {
00225   WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
00226 }
00227
00228 /**
00229   * @brief  Get the specified IWDG down-counter reload value
00230   * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
00231   * @param  IWDGx IWDG Instance
00232   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00233   */
00234 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
00235 {
00236   return (READ_REG(IWDGx->RLR));
00237 }
00238
00239 /**
00240   * @brief  Specify high limit of the window value to be compared to the down-counter.
00241   * @rmtoll WINR         WIN           LL_IWDG_SetWindow
00242   * @param  IWDGx IWDG Instance
00243   * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
00244   * @retval None
00245   */
00246 __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
00247 {
00248   WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
00249 }
00250
00251 /**
00252   * @brief  Get the high limit of the window value specified.
00253   * @rmtoll WINR         WIN           LL_IWDG_GetWindow
00254   * @param  IWDGx IWDG Instance
00255   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00256   */
00257 __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
00258 {
00259   return (READ_REG(IWDGx->WINR));
00260 }
00261
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
00267   * @{
00268   */
00269
00270 /**
00271   * @brief  Check if flag Prescaler Value Update is set or not
00272   * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
00273   * @param  IWDGx IWDG Instance
00274   * @retval State of bit (1 or 0).
00275   */
00276 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
00277 {
00278   return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
00279 }
00280
00281 /**
00282   * @brief  Check if flag Reload Value Update is set or not
00283   * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
00284   * @param  IWDGx IWDG Instance
00285   * @retval State of bit (1 or 0).
00286   */
00287 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
00288 {
00289   return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
00290 }
00291
00292 /**
00293   * @brief  Check if flag Window Value Update is set or not
00294   * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
00295   * @param  IWDGx IWDG Instance
00296   * @retval State of bit (1 or 0).
00297   */
00298 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
00299 {
00300   return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
00301 }
00302
00303 /**
00304   * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
00305   * @rmtoll SR           PVU           LL_IWDG_IsReady\n
00306   *         SR           RVU           LL_IWDG_IsReady\n
00307   *         SR           WVU           LL_IWDG_IsReady
00308   * @param  IWDGx IWDG Instance
00309   * @retval State of bits (1 or 0).
00310   */
00311 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
00312 {
00313   return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
00314 }
00315
00316 /**
00317   * @}
00318   */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 #endif /* IWDG */
00329
00330 /**
00331   * @}
00332   */
00333
00334 #ifdef __cplusplus
00335 }
00336 #endif
00337
00338 #endif /* STM32G0xx_LL_IWDG_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_lptim.c Source File

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stm32g0xx_ll_lptim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_lptim.c
00004   * @author  MCD Application Team
00005   * @brief   LPTIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_lptim.h"
00022 #include "stm32g0xx_ll_bus.h"
00023 #include "stm32g0xx_ll_rcc.h"
00024
00025
00026 #ifdef  USE_FULL_ASSERT
00027 #include "stm32_assert.h"
00028 #else
00029 #define assert_param(expr) ((void)0U)
00030 #endif /* USE_FULL_ASSERT */
00031
00032 /** @addtogroup STM32G0xx_LL_Driver
00033   * @{
00034   */
00035
00036 #if defined (LPTIM1) || defined (LPTIM2)
00037
00038 /** @addtogroup LPTIM_LL
00039   * @{
00040   */
00041
00042 /* Private types -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 /* Private constants ---------------------------------------------------------*/
00045 /* Private macros ------------------------------------------------------------*/
00046 /** @addtogroup LPTIM_LL_Private_Macros
00047   * @{
00048   */
00049 #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
00050                                              || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
00051
00052 #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
00053                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
00054                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
00055                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
00056                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
00057                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
00058                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
00059                                                 || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
00060
00061 #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
00062                                          || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
00063
00064 #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
00065                                                 || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
00066 /**
00067   * @}
00068   */
00069
00070
00071 /* Private function prototypes -----------------------------------------------*/
00072 /* Private functions ---------------------------------------------------------*/
00073 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00074   * @{
00075   */
00076 /**
00077   * @}
00078   */
00079 /* Exported functions --------------------------------------------------------*/
00080 /** @addtogroup LPTIM_LL_Exported_Functions
00081   * @{
00082   */
00083
00084 /** @addtogroup LPTIM_LL_EF_Init
00085   * @{
00086   */
00087
00088 /**
00089   * @brief  Set LPTIMx registers to their reset values.
00090   * @param  LPTIMx LP Timer instance
00091   * @retval An ErrorStatus enumeration value:
00092   *          - SUCCESS: LPTIMx registers are de-initialized
00093   *          - ERROR: invalid LPTIMx instance
00094   */
00095 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
00096 {
00097   ErrorStatus result = SUCCESS;
00098
00099   /* Check the parameters */
00100   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00101
00102   if (LPTIMx == LPTIM1)
00103   {
00104     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00105     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00106   }
00107 #if defined(LPTIM2)
00108   else if (LPTIMx == LPTIM2)
00109   {
00110     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM2);
00111     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM2);
00112   }
00113 #endif /* LPTIM2 */
00114   else
00115   {
00116     result = ERROR;
00117   }
00118
00119   return result;
00120 }
00121
00122 /**
00123   * @brief  Set each fields of the LPTIM_InitStruct structure to its default
00124   *         value.
00125   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00126   * @retval None
00127   */
00128 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
00129 {
00130   /* Set the default configuration */
00131   LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
00132   LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
00133   LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
00134   LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
00135 }
00136
00137 /**
00138   * @brief  Configure the LPTIMx peripheral according to the specified parameters.
00139   * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
00140   * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
00141   * @param  LPTIMx LP Timer Instance
00142   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00143   * @retval An ErrorStatus enumeration value:
00144   *          - SUCCESS: LPTIMx instance has been initialized
00145   *          - ERROR: LPTIMx instance hasn't been initialized
00146   */
00147 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
00148 {
00149   ErrorStatus result = SUCCESS;
00150   /* Check the parameters */
00151   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00152   assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
00153   assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
00154   assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
00155   assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
00156
00157   /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
00158      (ENABLE bit is reset to 0).
00159   */
00160   if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
00161   {
00162     result = ERROR;
00163   }
00164   else
00165   {
00166     /* Set CKSEL bitfield according to ClockSource value */
00167     /* Set PRESC bitfield according to Prescaler value */
00168     /* Set WAVE bitfield according to Waveform value */
00169     /* Set WAVEPOL bitfield according to Polarity value */
00170     MODIFY_REG(LPTIMx->CFGR,
00171                (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
00172                LPTIM_InitStruct->ClockSource | \
00173                LPTIM_InitStruct->Prescaler | \
00174                LPTIM_InitStruct->Waveform | \
00175                LPTIM_InitStruct->Polarity);
00176   }
00177
00178   return result;
00179 }
00180
00181 /**
00182   * @brief  Disable the LPTIM instance
00183   * @rmtoll CR           ENABLE        LL_LPTIM_Disable
00184   * @param  LPTIMx Low-Power Timer instance
00185   * @note   The following sequence is required to solve LPTIM disable HW limitation.
00186   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
00187   *         stuck in LPTIM interrupt when entering Stop mode" section.
00188   * @retval None
00189   */
00190 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
00191 {
00192   LL_RCC_ClocksTypeDef rcc_clock;
00193   uint32_t tmpclksource = 0;
00194   uint32_t tmpIER;
00195   uint32_t tmpCFGR;
00196   uint32_t tmpCMP;
00197   uint32_t tmpARR;
00198   uint32_t primask_bit;
00199   uint32_t tmpCFGR2;
00200
00201   /* Check the parameters */
00202   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00203
00204   /* Enter critical section */
00205   primask_bit = __get_PRIMASK();
00206   __set_PRIMASK(1) ;
00207
00208   /********** Save LPTIM Config *********/
00209   /* Save LPTIM source clock */
00210   switch ((uint32_t)LPTIMx)
00211   {
00212     case LPTIM1_BASE:
00213       tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
00214       break;
00215 #if defined(LPTIM2)
00216     case LPTIM2_BASE:
00217       tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
00218       break;
00219 #endif /* LPTIM2 */
00220     default:
00221       break;
00222   }
00223
00224   /* Save LPTIM configuration registers */
00225   tmpIER = LPTIMx->IER;
00226   tmpCFGR = LPTIMx->CFGR;
00227   tmpCMP = LPTIMx->CMP;
00228   tmpARR = LPTIMx->ARR;
00229   tmpCFGR2 = LPTIMx->CFGR2;
00230
00231   /************* Reset LPTIM ************/
00232   (void)LL_LPTIM_DeInit(LPTIMx);
00233
00234   /********* Restore LPTIM Config *******/
00235   LL_RCC_GetSystemClocksFreq(&rcc_clock);
00236
00237   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
00238   {
00239     /* Force LPTIM source kernel clock from APB */
00240     switch ((uint32_t)LPTIMx)
00241     {
00242       case LPTIM1_BASE:
00243         LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
00244         break;
00245 #if defined(LPTIM2)
00246       case LPTIM2_BASE:
00247         LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1);
00248         break;
00249 #endif /* LPTIM2 */
00250       default:
00251         break;
00252     }
00253
00254     if (tmpCMP != 0UL)
00255     {
00256       /* Restore CMP and ARR registers (LPTIM should be enabled first) */
00257       LPTIMx->CR |= LPTIM_CR_ENABLE;
00258       LPTIMx->CMP = tmpCMP;
00259
00260       /* Polling on CMP write ok status after above restore operation */
00261       do
00262       {
00263         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
00264       } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
00265
00266       LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
00267     }
00268
00269     if (tmpARR != 0UL)
00270     {
00271       LPTIMx->CR |= LPTIM_CR_ENABLE;
00272       LPTIMx->ARR = tmpARR;
00273
00274       LL_RCC_GetSystemClocksFreq(&rcc_clock);
00275       /* Polling on ARR write ok status after above restore operation */
00276       do
00277       {
00278         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
00279       }
00280       while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
00281
00282       LL_LPTIM_ClearFlag_ARROK(LPTIMx);
00283     }
00284
00285
00286     /* Restore LPTIM source kernel clock */
00287     LL_RCC_SetLPTIMClockSource(tmpclksource);
00288   }
00289
00290   /* Restore configuration registers (LPTIM should be disabled first) */
00291   LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
00292   LPTIMx->IER = tmpIER;
00293   LPTIMx->CFGR = tmpCFGR;
00294   LPTIMx->CFGR2 = tmpCFGR2;
00295
00296   /* Exit critical section: restore previous priority mask */
00297   __set_PRIMASK(primask_bit);
00298 }
00299
00300 /**
00301   * @}
00302   */
00303
00304 /**
00305   * @}
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 #endif /* LPTIM1 || LPTIM2 */
00313
00314 /**
00315   * @}
00316   */
00317
00318 #endif /* USE_FULL_LL_DRIVER */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_lptim.h Source File

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stm32g0xx_ll_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_lptim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPTIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_LPTIM_H
00021 #define STM32G0xx_LL_LPTIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (LPTIM1) || defined (LPTIM2)
00035
00036 /** @defgroup LPTIM_LL LPTIM
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044
00045 /* Private macros ------------------------------------------------------------*/
00046 #if defined(USE_FULL_LL_DRIVER)
00047 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
00048   * @{
00049   */
00050 /**
00051   * @}
00052   */
00053 #endif /*USE_FULL_LL_DRIVER*/
00054
00055 /* Exported types ------------------------------------------------------------*/
00056 #if defined(USE_FULL_LL_DRIVER)
00057 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  LPTIM Init structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
00067                                 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
00068
00069                                 This feature can be modified afterwards using unitary
00070                                 function @ref LL_LPTIM_SetClockSource().*/
00071
00072   uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
00073                                 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
00074
00075                                 This feature can be modified afterwards using using unitary
00076                                 function @ref LL_LPTIM_SetPrescaler().*/
00077
00078   uint32_t Waveform;       /*!< Specifies the waveform shape.
00079                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
00080
00081                                 This feature can be modified afterwards using unitary
00082                                 function @ref LL_LPTIM_ConfigOutput().*/
00083
00084   uint32_t Polarity;       /*!< Specifies waveform polarity.
00085                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
00086
00087                                 This feature can be modified afterwards using unitary
00088                                 function @ref LL_LPTIM_ConfigOutput().*/
00089 } LL_LPTIM_InitTypeDef;
00090
00091 /**
00092   * @}
00093   */
00094 #endif /* USE_FULL_LL_DRIVER */
00095
00096 /* Exported constants --------------------------------------------------------*/
00097 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
00098   * @{
00099   */
00100
00101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
00102   * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
00103   * @{
00104   */
00105 #define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */
00106 #define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */
00107 #define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
00108 #define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
00109 #define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
00110 #define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
00111 #define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup LPTIM_LL_EC_IT IT Defines
00117   * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
00118   * @{
00119   */
00120 #define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE     /*!< Compare match */
00121 #define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE    /*!< Compare register update OK */
00122 #define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE     /*!< Autoreload match */
00123 #define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE  /*!< External trigger edge event */
00124 #define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE    /*!< Autoreload register update OK */
00125 #define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE       /*!< Counter direction change down to up */
00126 #define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE     /*!< Counter direction change up to down */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
00132   * @{
00133   */
00134 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
00135 #define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
00141   * @{
00142   */
00143 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U        /*!<Preload is disabled: registers are updated after each APB bus write access*/
00144 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
00150   * @{
00151   */
00152 #define LL_LPTIM_COUNTER_MODE_INTERNAL        0x00000000U          /*!<The counter is incremented following each internal clock pulse*/
00153 #define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
00159   * @{
00160   */
00161 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U     /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
00162 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE /*!<LPTIM  generates a Set Once waveform*/
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
00168   * @{
00169   */
00170 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U             /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00171 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL       /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
00177   * @{
00178   */
00179 #define LL_LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/
00180 #define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
00181 #define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
00182 #define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
00183 #define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
00184 #define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
00185 #define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
00186 #define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
00192   * @{
00193   */
00194 #define LL_LPTIM_TRIG_SOURCE_GPIO             0x00000000U                                                          /*!<External input trigger is connected to TIMx_ETR input*/
00195 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to RTC Alarm A*/
00196 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to RTC Alarm B*/
00197 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 1*/
00198 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to RTC Tamper 2*/
00199 #if defined(RTC_TAMPER3_SUPPORT)
00200 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 3*/
00201 #endif /* RTC_TAMPER3_SUPPORT */
00202 #define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to COMP1 output*/
00203 #define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                                                   /*!<External input trigger is connected to COMP2 output*/
00204 #if defined(COMP3)
00205 #define LL_LPTIM_TRIG_SOURCE_COMP3            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to COMP3 output*/
00206 #endif /* COMP3 */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
00212   * @{
00213   */
00214 #define LL_LPTIM_TRIG_FILTER_NONE             0x00000000U         /*!<Any trigger active level change is considered as a valid trigger*/
00215 #define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
00216 #define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
00217 #define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT   /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
00223   * @{
00224   */
00225 #define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
00226 #define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
00227 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN   /*!<LPTIM counter starts when a rising or a falling edge is detected*/
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
00233   * @{
00234   */
00235 #define LL_LPTIM_CLK_SOURCE_INTERNAL          0x00000000U      /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
00236 #define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
00242   * @{
00243   */
00244 #define LL_LPTIM_CLK_FILTER_NONE              0x00000000U        /*!<Any external clock signal level change is considered as a valid transition*/
00245 #define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
00246 #define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
00247 #define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT   /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
00253   * @{
00254   */
00255 #define LL_LPTIM_CLK_POLARITY_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
00256 #define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
00257 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
00263   * @{
00264   */
00265 #define LL_LPTIM_ENCODER_MODE_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
00266 #define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
00267 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
00273   * @{
00274   */
00275 #define LL_LPTIM_INPUT1_SRC_GPIO         0x00000000U                                            /*!< For LPTIM1 and LPTIM2 */
00276 #define LL_LPTIM_INPUT1_SRC_COMP1        LPTIM_CFGR2_IN1SEL_0                                   /*!< For LPTIM1 and LPTIM2 */
00277 #define LL_LPTIM_INPUT1_SRC_COMP2        LPTIM_CFGR2_IN1SEL_1                                   /*!< For LPTIM2 */
00278 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2  (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)          /*!< For LPTIM2 */
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
00284   * @{
00285   */
00286 #define LL_LPTIM_INPUT2_SRC_GPIO         0x00000000U                   /*!< For LPTIM1 */
00287 #define LL_LPTIM_INPUT2_SRC_COMP2        LPTIM_CFGR2_IN2SEL_0          /*!< For LPTIM1 */
00288 /**
00289   * @}
00290   */
00291
00292 /**
00293   * @}
00294   */
00295
00296 /* Exported macro ------------------------------------------------------------*/
00297 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
00298   * @{
00299   */
00300
00301 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
00302   * @{
00303   */
00304
00305 /**
00306   * @brief  Write a value in LPTIM register
00307   * @param  __INSTANCE__ LPTIM Instance
00308   * @param  __REG__ Register to be written
00309   * @param  __VALUE__ Value to be written in the register
00310   * @retval None
00311   */
00312 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00313
00314 /**
00315   * @brief  Read a value in LPTIM register
00316   * @param  __INSTANCE__ LPTIM Instance
00317   * @param  __REG__ Register to be read
00318   * @retval Register value
00319   */
00320 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /* Exported functions --------------------------------------------------------*/
00330 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
00331   * @{
00332   */
00333
00334 #if defined(USE_FULL_LL_DRIVER)
00335 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
00336   * @{
00337   */
00338
00339 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
00340 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
00341 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
00342 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
00343 /**
00344   * @}
00345   */
00346 #endif /* USE_FULL_LL_DRIVER */
00347
00348 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
00349   * @{
00350   */
00351
00352 /**
00353   * @brief  Enable the LPTIM instance
00354   * @note After setting the ENABLE bit, a delay of two counter clock is needed
00355   *       before the LPTIM instance is actually enabled.
00356   * @rmtoll CR           ENABLE        LL_LPTIM_Enable
00357   * @param  LPTIMx Low-Power Timer instance
00358   * @retval None
00359   */
00360 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
00361 {
00362   SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
00363 }
00364
00365 /**
00366   * @brief  Indicates whether the LPTIM instance is enabled.
00367   * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
00368   * @param  LPTIMx Low-Power Timer instance
00369   * @retval State of bit (1 or 0).
00370   */
00371 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
00372 {
00373   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
00374 }
00375
00376 /**
00377   * @brief  Starts the LPTIM counter in the desired mode.
00378   * @note LPTIM instance must be enabled before starting the counter.
00379   * @note It is possible to change on the fly from One Shot mode to
00380   *       Continuous mode.
00381   * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
00382   *         CR           SNGSTRT       LL_LPTIM_StartCounter
00383   * @param  LPTIMx Low-Power Timer instance
00384   * @param  OperatingMode This parameter can be one of the following values:
00385   *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
00386   *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
00387   * @retval None
00388   */
00389 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
00390 {
00391   MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
00392 }
00393
00394 /**
00395   * @brief  Enable reset after read.
00396   * @note After calling this function any read access to LPTIM_CNT
00397   *        register will asynchronously reset the LPTIM_CNT register content.
00398   * @rmtoll CR           RSTARE        LL_LPTIM_EnableResetAfterRead
00399   * @param  LPTIMx Low-Power Timer instance
00400   * @retval None
00401   */
00402 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
00403 {
00404   SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
00405 }
00406
00407 /**
00408   * @brief  Disable reset after read.
00409   * @rmtoll CR           RSTARE        LL_LPTIM_DisableResetAfterRead
00410   * @param  LPTIMx Low-Power Timer instance
00411   * @retval None
00412   */
00413 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
00414 {
00415   CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
00416 }
00417
00418 /**
00419   * @brief  Indicate whether the reset after read feature is enabled.
00420   * @rmtoll CR           RSTARE        LL_LPTIM_IsEnabledResetAfterRead
00421   * @param  LPTIMx Low-Power Timer instance
00422   * @retval State of bit (1 or 0).
00423   */
00424 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
00425 {
00426   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
00427 }
00428
00429 /**
00430   * @brief  Reset of the LPTIM_CNT counter register (synchronous).
00431   * @note Due to the synchronous nature of this reset, it only takes
00432   *       place after a synchronization delay of 3 LPTIM core clock cycles
00433   *      (LPTIM core clock may be different from APB clock).
00434   * @note COUNTRST is automatically cleared by hardware
00435   * @rmtoll CR           COUNTRST       LL_LPTIM_ResetCounter\n
00436   * @param  LPTIMx Low-Power Timer instance
00437   * @retval None
00438   */
00439 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
00440 {
00441   SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
00442 }
00443
00444 /**
00445   * @brief  Set the LPTIM registers update mode (enable/disable register preload)
00446   * @note This function must be called when the LPTIM instance is disabled.
00447   * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
00448   * @param  LPTIMx Low-Power Timer instance
00449   * @param  UpdateMode This parameter can be one of the following values:
00450   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00451   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00452   * @retval None
00453   */
00454 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
00455 {
00456   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
00457 }
00458
00459 /**
00460   * @brief  Get the LPTIM registers update mode
00461   * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
00462   * @param  LPTIMx Low-Power Timer instance
00463   * @retval Returned value can be one of the following values:
00464   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00465   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00466   */
00467 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
00468 {
00469   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
00470 }
00471
00472 /**
00473   * @brief  Set the auto reload value
00474   * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
00475   * @note After a write to the LPTIMx_ARR register a new write operation to the
00476   *       same register can only be performed when the previous write operation
00477   *       is completed. Any successive write before  the ARROK flag is set, will
00478   *       lead to unpredictable results.
00479   * @note autoreload value be strictly greater than the compare value.
00480   * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
00481   * @param  LPTIMx Low-Power Timer instance
00482   * @param  AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
00483   * @retval None
00484   */
00485 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
00486 {
00487   MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
00488 }
00489
00490 /**
00491   * @brief  Get actual auto reload value
00492   * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
00493   * @param  LPTIMx Low-Power Timer instance
00494   * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
00495   */
00496 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
00497 {
00498   return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
00499 }
00500
00501 /**
00502   * @brief  Set the compare value
00503   * @note After a write to the LPTIMx_CMP register a new write operation to the
00504   *       same register can only be performed when the previous write operation
00505   *       is completed. Any successive write before the CMPOK flag is set, will
00506   *       lead to unpredictable results.
00507   * @rmtoll CMP          CMP           LL_LPTIM_SetCompare
00508   * @param  LPTIMx Low-Power Timer instance
00509   * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00510   * @retval None
00511   */
00512 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
00513 {
00514   MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
00515 }
00516
00517 /**
00518   * @brief  Get actual compare value
00519   * @rmtoll CMP          CMP           LL_LPTIM_GetCompare
00520   * @param  LPTIMx Low-Power Timer instance
00521   * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00522   */
00523 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
00524 {
00525   return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
00526 }
00527
00528 /**
00529   * @brief  Get actual counter value
00530   * @note When the LPTIM instance is running with an asynchronous clock, reading
00531   *       the LPTIMx_CNT register may return unreliable values. So in this case
00532   *       it is necessary to perform two consecutive read accesses and verify
00533   *       that the two returned values are identical.
00534   * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
00535   * @param  LPTIMx Low-Power Timer instance
00536   * @retval Counter value
00537   */
00538 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
00539 {
00540   return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
00541 }
00542
00543 /**
00544   * @brief  Set the counter mode (selection of the LPTIM counter clock source).
00545   * @note The counter mode can be set only when the LPTIM instance is disabled.
00546   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
00547   * @param  LPTIMx Low-Power Timer instance
00548   * @param  CounterMode This parameter can be one of the following values:
00549   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00550   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00551   * @retval None
00552   */
00553 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
00554 {
00555   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
00556 }
00557
00558 /**
00559   * @brief  Get the counter mode
00560   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
00561   * @param  LPTIMx Low-Power Timer instance
00562   * @retval Returned value can be one of the following values:
00563   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00564   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00565   */
00566 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
00567 {
00568   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
00569 }
00570
00571 /**
00572   * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
00573   * @note This function must be called when the LPTIM instance is disabled.
00574   * @note Regarding the LPTIM output polarity the change takes effect
00575   *       immediately, so the output default value will change immediately after
00576   *       the polarity is re-configured, even before the timer is enabled.
00577   * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n
00578   *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput
00579   * @param  LPTIMx Low-Power Timer instance
00580   * @param  Waveform This parameter can be one of the following values:
00581   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00582   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00583   * @param  Polarity This parameter can be one of the following values:
00584   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00585   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00586   * @retval None
00587   */
00588 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
00589 {
00590   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
00591 }
00592
00593 /**
00594   * @brief  Set  waveform shape
00595   * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
00596   * @param  LPTIMx Low-Power Timer instance
00597   * @param  Waveform This parameter can be one of the following values:
00598   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00599   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00600   * @retval None
00601   */
00602 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
00603 {
00604   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
00605 }
00606
00607 /**
00608   * @brief  Get actual waveform shape
00609   * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
00610   * @param  LPTIMx Low-Power Timer instance
00611   * @retval Returned value can be one of the following values:
00612   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00613   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00614   */
00615 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
00616 {
00617   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
00618 }
00619
00620 /**
00621   * @brief  Set  output polarity
00622   * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity
00623   * @param  LPTIMx Low-Power Timer instance
00624   * @param  Polarity This parameter can be one of the following values:
00625   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00626   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00627   * @retval None
00628   */
00629 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
00630 {
00631   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
00632 }
00633
00634 /**
00635   * @brief  Get actual output polarity
00636   * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity
00637   * @param  LPTIMx Low-Power Timer instance
00638   * @retval Returned value can be one of the following values:
00639   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00640   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00641   */
00642 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
00643 {
00644   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
00645 }
00646
00647 /**
00648   * @brief  Set actual prescaler division ratio.
00649   * @note This function must be called when the LPTIM instance is disabled.
00650   * @note When the LPTIM is configured to be clocked by an internal clock source
00651   *       and the LPTIM counter is configured to be updated by active edges
00652   *       detected on the LPTIM external Input1, the internal clock provided to
00653   *       the LPTIM must be not be prescaled.
00654   * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
00655   * @param  LPTIMx Low-Power Timer instance
00656   * @param  Prescaler This parameter can be one of the following values:
00657   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00658   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00659   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00660   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00661   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00662   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00663   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00664   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
00668 {
00669   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
00670 }
00671
00672 /**
00673   * @brief  Get actual prescaler division ratio.
00674   * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
00675   * @param  LPTIMx Low-Power Timer instance
00676   * @retval Returned value can be one of the following values:
00677   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00678   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00679   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00680   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00681   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00682   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00683   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00684   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00685   */
00686 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
00687 {
00688   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
00689 }
00690
00691 /**
00692   * @brief  Set LPTIM input 1 source (default GPIO).
00693   * @rmtoll CFGR2      IN1SEL       LL_LPTIM_SetInput1Src
00694   * @param  LPTIMx Low-Power Timer instance
00695   * @param  Src This parameter can be one of the following values:
00696   *         @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
00697   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
00698   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
00699   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
00700   * @retval None
00701   */
00702 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00703 {
00704   MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
00705 }
00706
00707 /**
00708   * @brief  Set LPTIM input 2 source (default GPIO).
00709   * @rmtoll CFGR2      IN2SEL       LL_LPTIM_SetInput2Src
00710   * @param  LPTIMx Low-Power Timer instance
00711   * @param  Src This parameter can be one of the following values:
00712   *         @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
00713   *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
00714   * @retval None
00715   */
00716 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00717 {
00718   MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
00719 }
00720
00721 /**
00722   * @}
00723   */
00724
00725 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
00726   * @{
00727   */
00728
00729 /**
00730   * @brief  Enable the timeout function
00731   * @note This function must be called when the LPTIM instance is disabled.
00732   * @note The first trigger event will start the timer, any successive trigger
00733   *       event will reset the counter and the timer will restart.
00734   * @note The timeout value corresponds to the compare value; if no trigger
00735   *       occurs within the expected time frame, the MCU is waked-up by the
00736   *       compare match event.
00737   * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
00738   * @param  LPTIMx Low-Power Timer instance
00739   * @retval None
00740   */
00741 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
00742 {
00743   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00744 }
00745
00746 /**
00747   * @brief  Disable the timeout function
00748   * @note This function must be called when the LPTIM instance is disabled.
00749   * @note A trigger event arriving when the timer is already started will be
00750   *       ignored.
00751   * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
00752   * @param  LPTIMx Low-Power Timer instance
00753   * @retval None
00754   */
00755 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
00756 {
00757   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00758 }
00759
00760 /**
00761   * @brief  Indicate whether the timeout function is enabled.
00762   * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
00763   * @param  LPTIMx Low-Power Timer instance
00764   * @retval State of bit (1 or 0).
00765   */
00766 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
00767 {
00768   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
00769 }
00770
00771 /**
00772   * @brief  Start the LPTIM counter
00773   * @note This function must be called when the LPTIM instance is disabled.
00774   * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
00775   * @param  LPTIMx Low-Power Timer instance
00776   * @retval None
00777   */
00778 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
00779 {
00780   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
00781 }
00782
00783 /**
00784   * @brief  Configure the external trigger used as a trigger event for the LPTIM.
00785   * @note This function must be called when the LPTIM instance is disabled.
00786   * @note An internal clock source must be present when a digital filter is
00787   *       required for the trigger.
00788   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
00789   *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
00790   *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
00791   * @param  LPTIMx Low-Power Timer instance
00792   * @param  Source This parameter can be one of the following values:
00793   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00794   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00795   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00796   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
00797   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00798   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
00799   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
00800   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
00801   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3 (*)
00802   *
00803   *         (*)  Value not defined in all devices. \n
00804   *
00805   * @param  Filter This parameter can be one of the following values:
00806   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00807   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00808   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00809   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00810   * @param  Polarity This parameter can be one of the following values:
00811   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00812   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00813   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00814   * @retval None
00815   */
00816 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
00817 {
00818   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
00819 }
00820
00821 /**
00822   * @brief  Get actual external trigger source.
00823   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
00824   * @param  LPTIMx Low-Power Timer instance
00825   * @retval Returned value can be one of the following values:
00826   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00827   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00828   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00829   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
00830   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00831   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
00832   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
00833   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
00834   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3 (*)
00835   *
00836   *         (*)  Value not defined in all devices. \n
00837   *
00838   */
00839 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
00840 {
00841   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
00842 }
00843
00844 /**
00845   * @brief  Get actual external trigger filter.
00846   * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
00847   * @param  LPTIMx Low-Power Timer instance
00848   * @retval Returned value can be one of the following values:
00849   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00850   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00851   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00852   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00853   */
00854 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
00855 {
00856   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
00857 }
00858
00859 /**
00860   * @brief  Get actual external trigger polarity.
00861   * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
00862   * @param  LPTIMx Low-Power Timer instance
00863   * @retval Returned value can be one of the following values:
00864   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00865   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00866   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00867   */
00868 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
00869 {
00870   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
00871 }
00872
00873 /**
00874   * @}
00875   */
00876
00877 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
00878   * @{
00879   */
00880
00881 /**
00882   * @brief  Set the source of the clock used by the LPTIM instance.
00883   * @note This function must be called when the LPTIM instance is disabled.
00884   * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
00885   * @param  LPTIMx Low-Power Timer instance
00886   * @param  ClockSource This parameter can be one of the following values:
00887   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00888   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00889   * @retval None
00890   */
00891 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
00892 {
00893   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
00894 }
00895
00896 /**
00897   * @brief  Get actual LPTIM instance clock source.
00898   * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
00899   * @param  LPTIMx Low-Power Timer instance
00900   * @retval Returned value can be one of the following values:
00901   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00902   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00903   */
00904 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
00905 {
00906   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
00907 }
00908
00909 /**
00910   * @brief  Configure the active edge or edges used by the counter when
00911             the LPTIM is clocked by an external clock source.
00912   * @note This function must be called when the LPTIM instance is disabled.
00913   * @note When both external clock signal edges are considered active ones,
00914   *       the LPTIM must also be clocked by an internal clock source with a
00915   *       frequency equal to at least four times the external clock frequency.
00916   * @note An internal clock source must be present when a digital filter is
00917   *       required for external clock.
00918   * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
00919   *         CFGR         CKPOL         LL_LPTIM_ConfigClock
00920   * @param  LPTIMx Low-Power Timer instance
00921   * @param  ClockFilter This parameter can be one of the following values:
00922   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00923   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00924   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00925   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00926   * @param  ClockPolarity This parameter can be one of the following values:
00927   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00928   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00929   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00930   * @retval None
00931   */
00932 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
00933 {
00934   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
00935 }
00936
00937 /**
00938   * @brief  Get actual clock polarity
00939   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
00940   * @param  LPTIMx Low-Power Timer instance
00941   * @retval Returned value can be one of the following values:
00942   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00943   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00944   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00945   */
00946 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
00947 {
00948   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
00949 }
00950
00951 /**
00952   * @brief  Get actual clock digital filter
00953   * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
00954   * @param  LPTIMx Low-Power Timer instance
00955   * @retval Returned value can be one of the following values:
00956   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00957   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00958   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00959   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00960   */
00961 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
00962 {
00963   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
00964 }
00965
00966 /**
00967   * @}
00968   */
00969
00970 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
00971   * @{
00972   */
00973
00974 /**
00975   * @brief  Configure the encoder mode.
00976   * @note This function must be called when the LPTIM instance is disabled.
00977   * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
00978   * @param  LPTIMx Low-Power Timer instance
00979   * @param  EncoderMode This parameter can be one of the following values:
00980   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
00981   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
00982   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
00983   * @retval None
00984   */
00985 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
00986 {
00987   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
00988 }
00989
00990 /**
00991   * @brief  Get actual encoder mode.
00992   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
00993   * @param  LPTIMx Low-Power Timer instance
00994   * @retval Returned value can be one of the following values:
00995   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
00996   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
00997   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
00998   */
00999 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
01000 {
01001   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
01002 }
01003
01004 /**
01005   * @brief  Enable the encoder mode
01006   * @note This function must be called when the LPTIM instance is disabled.
01007   * @note In this mode the LPTIM instance must be clocked by an internal clock
01008   *       source. Also, the prescaler division ratio must be equal to 1.
01009   * @note LPTIM instance must be configured in continuous mode prior enabling
01010   *       the encoder mode.
01011   * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
01012   * @param  LPTIMx Low-Power Timer instance
01013   * @retval None
01014   */
01015 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
01016 {
01017   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
01018 }
01019
01020 /**
01021   * @brief  Disable the encoder mode
01022   * @note This function must be called when the LPTIM instance is disabled.
01023   * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
01024   * @param  LPTIMx Low-Power Timer instance
01025   * @retval None
01026   */
01027 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
01028 {
01029   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
01030 }
01031
01032 /**
01033   * @brief  Indicates whether the LPTIM operates in encoder mode.
01034   * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
01035   * @param  LPTIMx Low-Power Timer instance
01036   * @retval State of bit (1 or 0).
01037   */
01038 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
01039 {
01040   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
01041 }
01042
01043 /**
01044   * @}
01045   */
01046
01047 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
01048   * @{
01049   */
01050
01051 /**
01052   * @brief  Clear the compare match flag (CMPMCF)
01053   * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM
01054   * @param  LPTIMx Low-Power Timer instance
01055   * @retval None
01056   */
01057 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
01058 {
01059   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
01060 }
01061
01062 /**
01063   * @brief  Inform application whether a compare match interrupt has occurred.
01064   * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM
01065   * @param  LPTIMx Low-Power Timer instance
01066   * @retval State of bit (1 or 0).
01067   */
01068 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
01069 {
01070   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
01071 }
01072
01073 /**
01074   * @brief  Clear the autoreload match flag (ARRMCF)
01075   * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM
01076   * @param  LPTIMx Low-Power Timer instance
01077   * @retval None
01078   */
01079 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
01080 {
01081   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
01082 }
01083
01084 /**
01085   * @brief  Inform application whether a autoreload match interrupt has occurred.
01086   * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
01087   * @param  LPTIMx Low-Power Timer instance
01088   * @retval State of bit (1 or 0).
01089   */
01090 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
01091 {
01092   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
01093 }
01094
01095 /**
01096   * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
01097   * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
01098   * @param  LPTIMx Low-Power Timer instance
01099   * @retval None
01100   */
01101 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01102 {
01103   SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
01104 }
01105
01106 /**
01107   * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
01108   * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
01109   * @param  LPTIMx Low-Power Timer instance
01110   * @retval State of bit (1 or 0).
01111   */
01112 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
01113 {
01114   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
01115 }
01116
01117 /**
01118   * @brief  Clear the compare register update interrupt flag (CMPOKCF).
01119   * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK
01120   * @param  LPTIMx Low-Power Timer instance
01121   * @retval None
01122   */
01123 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
01124 {
01125   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
01126 }
01127
01128 /**
01129   * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
01130             completed. If so, a new one can be initiated.
01131   * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
01132   * @param  LPTIMx Low-Power Timer instance
01133   * @retval State of bit (1 or 0).
01134   */
01135 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
01136 {
01137   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
01138 }
01139
01140 /**
01141   * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
01142   * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
01143   * @param  LPTIMx Low-Power Timer instance
01144   * @retval None
01145   */
01146 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
01147 {
01148   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
01149 }
01150
01151 /**
01152   * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
01153             completed. If so, a new one can be initiated.
01154   * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
01155   * @param  LPTIMx Low-Power Timer instance
01156   * @retval State of bit (1 or 0).
01157   */
01158 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
01159 {
01160   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
01161 }
01162
01163 /**
01164   * @brief  Clear the counter direction change to up interrupt flag (UPCF).
01165   * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
01166   * @param  LPTIMx Low-Power Timer instance
01167   * @retval None
01168   */
01169 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
01170 {
01171   SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
01172 }
01173
01174 /**
01175   * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
01176             operates in encoder mode).
01177   * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
01178   * @param  LPTIMx Low-Power Timer instance
01179   * @retval State of bit (1 or 0).
01180   */
01181 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
01182 {
01183   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
01184 }
01185
01186 /**
01187   * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
01188   * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
01189   * @param  LPTIMx Low-Power Timer instance
01190   * @retval None
01191   */
01192 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
01193 {
01194   SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
01195 }
01196
01197 /**
01198   * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
01199             operates in encoder mode).
01200   * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
01201   * @param  LPTIMx Low-Power Timer instance
01202   * @retval State of bit (1 or 0).
01203   */
01204 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
01205 {
01206   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
01207 }
01208
01209 /**
01210   * @}
01211   */
01212
01213 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
01214   * @{
01215   */
01216
01217 /**
01218   * @brief  Enable compare match interrupt (CMPMIE).
01219   * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM
01220   * @param  LPTIMx Low-Power Timer instance
01221   * @retval None
01222   */
01223 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01224 {
01225   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01226 }
01227
01228 /**
01229   * @brief  Disable compare match interrupt (CMPMIE).
01230   * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM
01231   * @param  LPTIMx Low-Power Timer instance
01232   * @retval None
01233   */
01234 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01235 {
01236   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01237 }
01238
01239 /**
01240   * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
01241   * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM
01242   * @param  LPTIMx Low-Power Timer instance
01243   * @retval State of bit (1 or 0).
01244   */
01245 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
01246 {
01247   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
01248 }
01249
01250 /**
01251   * @brief  Enable autoreload match interrupt (ARRMIE).
01252   * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM
01253   * @param  LPTIMx Low-Power Timer instance
01254   * @retval None
01255   */
01256 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01257 {
01258   SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01259 }
01260
01261 /**
01262   * @brief  Disable autoreload match interrupt (ARRMIE).
01263   * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM
01264   * @param  LPTIMx Low-Power Timer instance
01265   * @retval None
01266   */
01267 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01268 {
01269   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01270 }
01271
01272 /**
01273   * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
01274   * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
01275   * @param  LPTIMx Low-Power Timer instance
01276   * @retval State of bit (1 or 0).
01277   */
01278 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
01279 {
01280   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
01281 }
01282
01283 /**
01284   * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
01285   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
01286   * @param  LPTIMx Low-Power Timer instance
01287   * @retval None
01288   */
01289 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01290 {
01291   SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01292 }
01293
01294 /**
01295   * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
01296   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
01297   * @param  LPTIMx Low-Power Timer instance
01298   * @retval None
01299   */
01300 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01301 {
01302   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01303 }
01304
01305 /**
01306   * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
01307   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
01308   * @param  LPTIMx Low-Power Timer instance
01309   * @retval State of bit (1 or 0).
01310   */
01311 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
01312 {
01313   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
01314 }
01315
01316 /**
01317   * @brief  Enable compare register write completed interrupt (CMPOKIE).
01318   * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK
01319   * @param  LPTIMx Low-Power Timer instance
01320   * @retval None
01321   */
01322 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01323 {
01324   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01325 }
01326
01327 /**
01328   * @brief  Disable compare register write completed interrupt (CMPOKIE).
01329   * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK
01330   * @param  LPTIMx Low-Power Timer instance
01331   * @retval None
01332   */
01333 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01334 {
01335   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01336 }
01337
01338 /**
01339   * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
01340   * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK
01341   * @param  LPTIMx Low-Power Timer instance
01342   * @retval State of bit (1 or 0).
01343   */
01344 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
01345 {
01346   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
01347 }
01348
01349 /**
01350   * @brief  Enable autoreload register write completed interrupt (ARROKIE).
01351   * @rmtoll IER         ARROKIE       LL_LPTIM_EnableIT_ARROK
01352   * @param  LPTIMx Low-Power Timer instance
01353   * @retval None
01354   */
01355 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01356 {
01357   SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01358 }
01359
01360 /**
01361   * @brief  Disable autoreload register write completed interrupt (ARROKIE).
01362   * @rmtoll IER         ARROKIE       LL_LPTIM_DisableIT_ARROK
01363   * @param  LPTIMx Low-Power Timer instance
01364   * @retval None
01365   */
01366 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01367 {
01368   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01369 }
01370
01371 /**
01372   * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
01373   * @rmtoll IER         ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
01374   * @param  LPTIMx Low-Power Timer instance
01375   * @retval State of bit(1 or 0).
01376   */
01377 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
01378 {
01379   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
01380 }
01381
01382 /**
01383   * @brief  Enable direction change to up interrupt (UPIE).
01384   * @rmtoll IER         UPIE          LL_LPTIM_EnableIT_UP
01385   * @param  LPTIMx Low-Power Timer instance
01386   * @retval None
01387   */
01388 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
01389 {
01390   SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01391 }
01392
01393 /**
01394   * @brief  Disable direction change to up interrupt (UPIE).
01395   * @rmtoll IER         UPIE          LL_LPTIM_DisableIT_UP
01396   * @param  LPTIMx Low-Power Timer instance
01397   * @retval None
01398   */
01399 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
01400 {
01401   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01402 }
01403
01404 /**
01405   * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
01406   * @rmtoll IER         UPIE          LL_LPTIM_IsEnabledIT_UP
01407   * @param  LPTIMx Low-Power Timer instance
01408   * @retval State of bit(1 or 0).
01409   */
01410 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
01411 {
01412   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
01413 }
01414
01415 /**
01416   * @brief  Enable direction change to down interrupt (DOWNIE).
01417   * @rmtoll IER         DOWNIE        LL_LPTIM_EnableIT_DOWN
01418   * @param  LPTIMx Low-Power Timer instance
01419   * @retval None
01420   */
01421 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01422 {
01423   SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01424 }
01425
01426 /**
01427   * @brief  Disable direction change to down interrupt (DOWNIE).
01428   * @rmtoll IER         DOWNIE        LL_LPTIM_DisableIT_DOWN
01429   * @param  LPTIMx Low-Power Timer instance
01430   * @retval None
01431   */
01432 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01433 {
01434   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01435 }
01436
01437 /**
01438   * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
01439   * @rmtoll IER         DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
01440   * @param  LPTIMx Low-Power Timer instance
01441   * @retval State of bit(1 or 0).
01442   */
01443 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
01444 {
01445   return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
01446 }
01447
01448 /**
01449   * @}
01450   */
01451
01452 /**
01453   * @}
01454   */
01455
01456 /**
01457   * @}
01458   */
01459
01460 #endif /* LPTIM1 || LPTIM2 */
01461
01462 /**
01463   * @}
01464   */
01465
01466 #ifdef __cplusplus
01467 }
01468 #endif
01469
01470 #endif /* STM32G0xx_LL_LPTIM_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_lpuart.c Source File

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stm32g0xx_ll_lpuart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_lpuart.c
00004   * @author  MCD Application Team
00005   * @brief   LPUART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_lpuart.h"
00022 #include "stm32g0xx_ll_rcc.h"
00023 #include "stm32g0xx_ll_bus.h"
00024 #ifdef USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (LPUART1) || defined (LPUART2)
00035
00036 /** @addtogroup LPUART_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup LPUART_LL_Private_Constants
00044   * @{
00045   */
00046
00047 /**
00048   * @}
00049   */
00050
00051
00052 /* Private macros ------------------------------------------------------------*/
00053 /** @addtogroup LPUART_LL_Private_Macros
00054   * @{
00055   */
00056
00057 /* Check of parameters for configuration of LPUART registers                  */
00058
00059 #define IS_LL_LPUART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
00060                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
00061                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
00062                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
00063                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
00064                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
00065                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
00066                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
00067                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
00068                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
00069                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
00070                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))
00071
00072 /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
00073 /*              value :                                                       */
00074 /*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
00075 /*                - LPUART_BRR register value should be >= 0x300              */
00076 /*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
00077 /*              Baudrate specified by the user should belong to [8, 21300000].*/
00078 #define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))
00079
00080 /* __VALUE__ BRR content must be greater than or equal to 0x300. */
00081 #define IS_LL_LPUART_BRR_MIN(__VALUE__)   ((__VALUE__) >= 0x300U)
00082
00083 /* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
00084 #define IS_LL_LPUART_BRR_MAX(__VALUE__)   ((__VALUE__) <= 0x000FFFFFU)
00085
00086 #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
00087                                            || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
00088                                            || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
00089                                            || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
00090
00091 #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
00092                                         || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
00093                                         || ((__VALUE__) == LL_LPUART_PARITY_ODD))
00094
00095 #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
00096                                            || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
00097                                            || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
00098
00099 #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
00100                                           || ((__VALUE__) == LL_LPUART_STOPBITS_2))
00101
00102 #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
00103                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
00104                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
00105                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
00106
00107 /**
00108   * @}
00109   */
00110
00111 /* Private function prototypes -----------------------------------------------*/
00112
00113 /* Exported functions --------------------------------------------------------*/
00114 /** @addtogroup LPUART_LL_Exported_Functions
00115   * @{
00116   */
00117
00118 /** @addtogroup LPUART_LL_EF_Init
00119   * @{
00120   */
00121
00122 /**
00123   * @brief  De-initialize LPUART registers (Registers restored to their default values).
00124   * @param  LPUARTx LPUART Instance
00125   * @retval An ErrorStatus enumeration value:
00126   *          - SUCCESS: LPUART registers are de-initialized
00127   *          - ERROR: not applicable
00128   */
00129 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx)
00130 {
00131   ErrorStatus status = SUCCESS;
00132
00133   /* Check the parameters */
00134   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00135
00136   if (LPUARTx == LPUART1)
00137   {
00138     /* Force reset of LPUART peripheral */
00139     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1);
00140
00141     /* Release reset of LPUART peripheral */
00142     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1);
00143   }
00144 #if defined(LPUART2)
00145   else if (LPUARTx == LPUART2)
00146   {
00147     /* Force reset of LPUART peripheral */
00148     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART2);
00149
00150     /* Release reset of LPUART peripheral */
00151     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART2);
00152   }
00153 #endif /* LPUART2 */
00154   else
00155   {
00156     status = ERROR;
00157   }
00158
00159   return (status);
00160 }
00161
00162 /**
00163   * @brief  Initialize LPUART registers according to the specified
00164   *         parameters in LPUART_InitStruct.
00165   * @note   As some bits in LPUART configuration registers can only be written when
00166   *         the LPUART is disabled (USART_CR1_UE bit =0),
00167   *         LPUART Peripheral should be in disabled state prior calling this function.
00168   *         Otherwise, ERROR result will be returned.
00169   * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
00170   * @param  LPUARTx LPUART Instance
00171   * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00172   *         that contains the configuration information for the specified LPUART peripheral.
00173   * @retval An ErrorStatus enumeration value:
00174   *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
00175   *          - ERROR: Problem occurred during LPUART Registers initialization
00176   */
00177 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
00178 {
00179   ErrorStatus status = ERROR;
00180 #if defined(LPUART2)
00181   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00182 #else
00183   uint32_t periphclk;
00184 #endif /* LPUART2 */
00185
00186   /* Check the parameters */
00187   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00188   assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue));
00189   assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
00190   assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
00191   assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
00192   assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
00193   assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
00194   assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
00195
00196   /* LPUART needs to be in disabled state, in order to be able to configure some bits in
00197      CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
00198   if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
00199   {
00200     /*---------------------------- LPUART CR1 Configuration -----------------------
00201      * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
00202      * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
00203      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
00204      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
00205      */
00206     MODIFY_REG(LPUARTx->CR1,
00207                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
00208                (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
00209
00210     /*---------------------------- LPUART CR2 Configuration -----------------------
00211      * Configure LPUARTx CR2 (Stop bits) with parameters:
00212      * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
00213      */
00214     LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
00215
00216     /*---------------------------- LPUART CR3 Configuration -----------------------
00217      * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
00218      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
00219      *   to LPUART_InitStruct->HardwareFlowControl value.
00220      */
00221     LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
00222
00223     /*---------------------------- LPUART BRR Configuration -----------------------
00224      * Retrieve Clock frequency used for LPUART Peripheral
00225      */
00226 #if defined(LPUART2)
00227     if (LPUARTx == LPUART1)
00228     {
00229       periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
00230     }
00231     else if (LPUARTx == LPUART2)
00232     {
00233       periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART2_CLKSOURCE);
00234     }
00235     else
00236     {
00237       /* Nothing to do, as error code is already assigned to ERROR value */
00238     }
00239 #else
00240     periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
00241 #endif /* LPUART2 */
00242
00243     /* Configure the LPUART Baud Rate :
00244        - prescaler value is required
00245        - valid baud rate value (different from 0) is required
00246        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00247     */
00248     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00249         && (LPUART_InitStruct->BaudRate != 0U))
00250     {
00251       status = SUCCESS;
00252       LL_LPUART_SetBaudRate(LPUARTx,
00253                             periphclk,
00254                             LPUART_InitStruct->PrescalerValue,
00255                             LPUART_InitStruct->BaudRate);
00256
00257       /* Check BRR is greater than or equal to 0x300 */
00258       assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
00259
00260       /* Check BRR is lower than or equal to 0xFFFFF */
00261       assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
00262     }
00263
00264     /*---------------------------- LPUART PRESC Configuration -----------------------
00265      * Configure LPUARTx PRESC (Prescaler) with parameters:
00266      * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value.
00267      */
00268     LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue);
00269   }
00270
00271   return (status);
00272 }
00273
00274 /**
00275   * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
00276   * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00277   *                          whose fields will be set to default values.
00278   * @retval None
00279   */
00280
00281 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
00282 {
00283   /* Set LPUART_InitStruct fields to default values */
00284   LPUART_InitStruct->PrescalerValue      = LL_LPUART_PRESCALER_DIV1;
00285   LPUART_InitStruct->BaudRate            = 9600U;
00286   LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
00287   LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
00288   LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
00289   LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
00290   LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
00291 }
00292
00293 /**
00294   * @}
00295   */
00296
00297 /**
00298   * @}
00299   */
00300
00301 /**
00302   * @}
00303   */
00304
00305 #endif /* LPUART1 || LPUART2 */
00306
00307 /**
00308   * @}
00309   */
00310
00311 #endif /* USE_FULL_LL_DRIVER */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_lpuart.h Source File

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stm32g0xx_ll_lpuart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_lpuart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPUART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_LPUART_H
00021 #define STM32G0xx_LL_LPUART_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (LPUART1) || defined (LPUART2)
00035
00036 /** @defgroup LPUART_LL LPUART
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
00043   * @{
00044   */
00045 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
00046 static const uint16_t LPUART_PRESCALER_TAB[] =
00047 {
00048   (uint16_t)1,
00049   (uint16_t)2,
00050   (uint16_t)4,
00051   (uint16_t)6,
00052   (uint16_t)8,
00053   (uint16_t)10,
00054   (uint16_t)12,
00055   (uint16_t)16,
00056   (uint16_t)32,
00057   (uint16_t)64,
00058   (uint16_t)128,
00059   (uint16_t)256
00060 };
00061 /**
00062   * @}
00063   */
00064
00065 /* Private constants ---------------------------------------------------------*/
00066 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
00067   * @{
00068   */
00069 /* Defines used in Baud Rate related macros and corresponding register setting computation */
00070 #define LPUART_LPUARTDIV_FREQ_MUL     256U
00071 #define LPUART_BRR_MASK               0x000FFFFFU
00072 #define LPUART_BRR_MIN_VALUE          0x00000300U
00073 /**
00074   * @}
00075   */
00076
00077
00078 /* Private macros ------------------------------------------------------------*/
00079 #if defined(USE_FULL_LL_DRIVER)
00080 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
00081   * @{
00082   */
00083 /**
00084   * @}
00085   */
00086 #endif /*USE_FULL_LL_DRIVER*/
00087
00088 /* Exported types ------------------------------------------------------------*/
00089 #if defined(USE_FULL_LL_DRIVER)
00090 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
00091   * @{
00092   */
00093
00094 /**
00095   * @brief LL LPUART Init Structure definition
00096   */
00097 typedef struct
00098 {
00099   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00100                                            This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
00101
00102                                            This feature can be modified afterwards using unitary
00103                                            function @ref LL_LPUART_SetPrescaler().*/
00104
00105   uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
00106
00107                                            This feature can be modified afterwards using unitary
00108                                            function @ref LL_LPUART_SetBaudRate().*/
00109
00110   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00111                                            This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
00112
00113                                            This feature can be modified afterwards using unitary
00114                                            function @ref LL_LPUART_SetDataWidth().*/
00115
00116   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00117                                            This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
00118
00119                                            This feature can be modified afterwards using unitary
00120                                            function @ref LL_LPUART_SetStopBitsLength().*/
00121
00122   uint32_t Parity;                    /*!< Specifies the parity mode.
00123                                            This parameter can be a value of @ref LPUART_LL_EC_PARITY.
00124
00125                                            This feature can be modified afterwards using unitary
00126                                            function @ref LL_LPUART_SetParity().*/
00127
00128   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00129                                            This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
00130
00131                                            This feature can be modified afterwards using unitary
00132                                            function @ref LL_LPUART_SetTransferDirection().*/
00133
00134   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00135                                            This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
00136
00137                                            This feature can be modified afterwards using unitary
00138                                            function @ref LL_LPUART_SetHWFlowCtrl().*/
00139
00140 } LL_LPUART_InitTypeDef;
00141
00142 /**
00143   * @}
00144   */
00145 #endif /* USE_FULL_LL_DRIVER */
00146
00147 /* Exported constants --------------------------------------------------------*/
00148 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
00149   * @{
00150   */
00151
00152 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
00153   * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
00154   * @{
00155   */
00156 #define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
00157 #define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
00158 #define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
00159 #define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
00160 #define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
00161 #define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
00162 #define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
00163 #define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
00164 #define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
00170   * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
00171   * @{
00172   */
00173 #define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
00174 #define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
00175 #define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
00176 #define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
00177 #define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
00178 #define LL_LPUART_ISR_RXNE_RXFNE       USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
00179 #define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
00180 #define LL_LPUART_ISR_TXE_TXFNF        USART_ISR_TXE_TXFNF  /*!< Transmit data register empty or TX FIFO Not Full flag*/
00181 #define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
00182 #define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
00183 #define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
00184 #define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
00185 #define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
00186 #define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
00187 #define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
00188 #define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
00189 #define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
00190 #define LL_LPUART_ISR_TXFE             USART_ISR_TXFE       /*!< TX FIFO empty flag */
00191 #define LL_LPUART_ISR_RXFF             USART_ISR_RXFF       /*!< RX FIFO full flag */
00192 #define LL_LPUART_ISR_RXFT             USART_ISR_RXFT       /*!< RX FIFO threshold flag */
00193 #define LL_LPUART_ISR_TXFT             USART_ISR_TXFT       /*!< TX FIFO threshold flag */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup LPUART_LL_EC_IT IT Defines
00199   * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
00200   * @{
00201   */
00202 #define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
00203 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
00204                                                                    interrupt enable */
00205 #define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
00206 #define LL_LPUART_CR1_TXEIE_TXFNFIE  USART_CR1_TXEIE_TXFNFIE  /*!< Transmit data register empty and TX FIFO
00207                                                                    not full interrupt enable */
00208 #define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
00209 #define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
00210 #define LL_LPUART_CR1_TXFEIE         USART_CR1_TXFEIE         /*!< TX FIFO empty interrupt enable */
00211 #define LL_LPUART_CR1_RXFFIE         USART_CR1_RXFFIE         /*!< RX FIFO full interrupt enable */
00212 #define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
00213 #define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
00214 #define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
00215 #define LL_LPUART_CR3_TXFTIE         USART_CR3_TXFTIE         /*!< TX FIFO threshold interrupt enable */
00216 #define LL_LPUART_CR3_RXFTIE         USART_CR3_RXFTIE         /*!< RX FIFO threshold interrupt enable */
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00222   * @{
00223   */
00224 #define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
00225 #define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
00226 #define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
00227 #define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
00228 #define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
00229 #define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup LPUART_LL_EC_DIRECTION Direction
00235   * @{
00236   */
00237 #define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
00238 #define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
00239 #define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
00240 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup LPUART_LL_EC_PARITY Parity Control
00246   * @{
00247   */
00248 #define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
00249 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
00250 #define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
00256   * @{
00257   */
00258 #define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
00259 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
00265   * @{
00266   */
00267 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00268 #define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00269 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
00275   * @{
00276   */
00277 #define LL_LPUART_PRESCALER_DIV1   0x00000000U                    /*!< Input clock not divided   */
00278 #define LL_LPUART_PRESCALER_DIV2   (USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 2  */
00279 #define LL_LPUART_PRESCALER_DIV4   (USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 4  */
00280 #define LL_LPUART_PRESCALER_DIV6   (USART_PRESC_PRESCALER_1 |\
00281                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 6  */
00282 #define LL_LPUART_PRESCALER_DIV8   (USART_PRESC_PRESCALER_2)      /*!< Input clock divided by 8  */
00283 #define LL_LPUART_PRESCALER_DIV10  (USART_PRESC_PRESCALER_2 |\
00284                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 10 */
00285 #define LL_LPUART_PRESCALER_DIV12  (USART_PRESC_PRESCALER_2 |\
00286                                     USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 12 */
00287 #define LL_LPUART_PRESCALER_DIV16  (USART_PRESC_PRESCALER_2 |\
00288                                     USART_PRESC_PRESCALER_1 |\
00289                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 16 */
00290 #define LL_LPUART_PRESCALER_DIV32  (USART_PRESC_PRESCALER_3)      /*!< Input clock divided by 32 */
00291 #define LL_LPUART_PRESCALER_DIV64  (USART_PRESC_PRESCALER_3 |\
00292                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 64 */
00293 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
00294                                     USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 128 */
00295 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
00296                                     USART_PRESC_PRESCALER_1 |\
00297                                     USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 256 */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
00303   * @{
00304   */
00305 #define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
00306 #define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
00312   * @{
00313   */
00314 #define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
00315 #define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00321   * @{
00322   */
00323 #define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
00324 #define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00330   * @{
00331   */
00332 #define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
00333 #define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
00339   * @{
00340   */
00341 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
00342                                                                in positive/direct logic. (1=H, 0=L)                  */
00343 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
00344                                                                in negative/inverse logic. (1=L, 0=H).
00345                                                                The parity bit is also inverted.                      */
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
00351   * @{
00352   */
00353 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
00354                                                             following the start bit */
00355 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
00356                                                             following the start bit */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
00362   * @{
00363   */
00364 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
00365 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
00371   * @{
00372   */
00373 #define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
00374 #define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
00375                                                                            when there is space in the receive buffer  */
00376 #define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
00377                                                                            when the nCTS input is asserted (tied to 0)*/
00378 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
00384   * @{
00385   */
00386 #define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
00387 #define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
00388 #define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
00394   * @{
00395   */
00396 #define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
00397 #define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
00403   * @{
00404   */
00405 #define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
00406 #define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
00407 /**
00408   * @}
00409   */
00410
00411 /**
00412   * @}
00413   */
00414
00415 /* Exported macro ------------------------------------------------------------*/
00416 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
00417   * @{
00418   */
00419
00420 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
00421   * @{
00422   */
00423
00424 /**
00425   * @brief  Write a value in LPUART register
00426   * @param  __INSTANCE__ LPUART Instance
00427   * @param  __REG__ Register to be written
00428   * @param  __VALUE__ Value to be written in the register
00429   * @retval None
00430   */
00431 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00432
00433 /**
00434   * @brief  Read a value in LPUART register
00435   * @param  __INSTANCE__ LPUART Instance
00436   * @param  __REG__ Register to be read
00437   * @retval Register value
00438   */
00439 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
00445   * @{
00446   */
00447
00448 /**
00449   * @brief  Compute LPUARTDIV value according to Peripheral Clock and
00450   *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
00451   * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
00452   * @param  __PRESCALER__ This parameter can be one of the following values:
00453   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00454   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00455   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00456   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00457   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00458   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00459   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00460   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00461   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00462   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00463   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00464   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00465   * @param  __BAUDRATE__ Baud Rate value to achieve
00466   * @retval LPUARTDIV value to be used for BRR register filling
00467   */
00468 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
00469   ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
00470       * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
00471
00472 /**
00473   * @}
00474   */
00475
00476 /**
00477   * @}
00478   */
00479
00480 /* Exported functions --------------------------------------------------------*/
00481 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
00482   * @{
00483   */
00484
00485 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
00486   * @{
00487   */
00488
00489 /**
00490   * @brief  LPUART Enable
00491   * @rmtoll CR1          UE            LL_LPUART_Enable
00492   * @param  LPUARTx LPUART Instance
00493   * @retval None
00494   */
00495 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
00496 {
00497   SET_BIT(LPUARTx->CR1, USART_CR1_UE);
00498 }
00499
00500 /**
00501   * @brief  LPUART Disable
00502   * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
00503   *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
00504   *         flags, in the LPUARTx_ISR are set to their default values.
00505   * @note   In order to go into low-power mode without generating errors on the line,
00506   *         the TE bit must be reset before and the software must wait
00507   *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
00508   *         The DMA requests are also reset when UE = 0 so the DMA channel must
00509   *         be disabled before resetting the UE bit.
00510   * @rmtoll CR1          UE            LL_LPUART_Disable
00511   * @param  LPUARTx LPUART Instance
00512   * @retval None
00513   */
00514 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
00515 {
00516   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
00517 }
00518
00519 /**
00520   * @brief  Indicate if LPUART is enabled
00521   * @rmtoll CR1          UE            LL_LPUART_IsEnabled
00522   * @param  LPUARTx LPUART Instance
00523   * @retval State of bit (1 or 0).
00524   */
00525 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
00526 {
00527   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
00528 }
00529
00530 /**
00531   * @brief  FIFO Mode Enable
00532   * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
00533   * @param  LPUARTx LPUART Instance
00534   * @retval None
00535   */
00536 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
00537 {
00538   SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
00539 }
00540
00541 /**
00542   * @brief  FIFO Mode Disable
00543   * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
00544   * @param  LPUARTx LPUART Instance
00545   * @retval None
00546   */
00547 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
00548 {
00549   CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
00550 }
00551
00552 /**
00553   * @brief  Indicate if FIFO Mode is enabled
00554   * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
00555   * @param  LPUARTx LPUART Instance
00556   * @retval State of bit (1 or 0).
00557   */
00558 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
00559 {
00560   return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
00561 }
00562
00563 /**
00564   * @brief  Configure TX FIFO Threshold
00565   * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
00566   * @param  LPUARTx LPUART Instance
00567   * @param  Threshold This parameter can be one of the following values:
00568   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00569   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00570   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00571   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00572   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00573   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00574   * @retval None
00575   */
00576 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
00577 {
00578   ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00579 }
00580
00581 /**
00582   * @brief  Return TX FIFO Threshold Configuration
00583   * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
00584   * @param  LPUARTx LPUART Instance
00585   * @retval Returned value can be one of the following values:
00586   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00587   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00588   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00589   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00590   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00591   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00592   */
00593 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
00594 {
00595   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00596 }
00597
00598 /**
00599   * @brief  Configure RX FIFO Threshold
00600   * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
00601   * @param  LPUARTx LPUART Instance
00602   * @param  Threshold This parameter can be one of the following values:
00603   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00604   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00605   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00606   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00607   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00608   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00609   * @retval None
00610   */
00611 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
00612 {
00613   ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00614 }
00615
00616 /**
00617   * @brief  Return RX FIFO Threshold Configuration
00618   * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
00619   * @param  LPUARTx LPUART Instance
00620   * @retval Returned value can be one of the following values:
00621   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00622   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00623   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00624   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00625   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00626   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00627   */
00628 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
00629 {
00630   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00631 }
00632
00633 /**
00634   * @brief  Configure TX and RX FIFOs Threshold
00635   * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
00636   *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
00637   * @param  LPUARTx LPUART Instance
00638   * @param  TXThreshold This parameter can be one of the following values:
00639   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00640   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00641   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00642   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00643   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00644   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00645   * @param  RXThreshold This parameter can be one of the following values:
00646   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00647   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00648   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00649   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00650   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00651   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00655 {
00656   ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
00657                     (RXThreshold << USART_CR3_RXFTCFG_Pos));
00658 }
00659
00660 /**
00661   * @brief  LPUART enabled in STOP Mode
00662   * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
00663   *         LPUART clock selection is HSI or LSE in RCC.
00664   * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
00665   * @param  LPUARTx LPUART Instance
00666   * @retval None
00667   */
00668 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
00669 {
00670   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
00671 }
00672
00673 /**
00674   * @brief  LPUART disabled in STOP Mode
00675   * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
00676   * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
00677   * @param  LPUARTx LPUART Instance
00678   * @retval None
00679   */
00680 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
00681 {
00682   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
00683 }
00684
00685 /**
00686   * @brief  Indicate if LPUART is enabled in STOP Mode
00687   *         (able to wake up MCU from Stop mode or not)
00688   * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
00689   * @param  LPUARTx LPUART Instance
00690   * @retval State of bit (1 or 0).
00691   */
00692 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
00693 {
00694   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
00695 }
00696
00697 /**
00698   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00699   * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
00700   * @param  LPUARTx LPUART Instance
00701   * @retval None
00702   */
00703 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
00704 {
00705   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
00706 }
00707
00708 /**
00709   * @brief  Receiver Disable
00710   * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
00711   * @param  LPUARTx LPUART Instance
00712   * @retval None
00713   */
00714 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
00715 {
00716   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
00717 }
00718
00719 /**
00720   * @brief  Transmitter Enable
00721   * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
00722   * @param  LPUARTx LPUART Instance
00723   * @retval None
00724   */
00725 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
00726 {
00727   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
00728 }
00729
00730 /**
00731   * @brief  Transmitter Disable
00732   * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
00733   * @param  LPUARTx LPUART Instance
00734   * @retval None
00735   */
00736 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
00737 {
00738   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
00739 }
00740
00741 /**
00742   * @brief  Configure simultaneously enabled/disabled states
00743   *         of Transmitter and Receiver
00744   * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
00745   *         CR1          TE            LL_LPUART_SetTransferDirection
00746   * @param  LPUARTx LPUART Instance
00747   * @param  TransferDirection This parameter can be one of the following values:
00748   *         @arg @ref LL_LPUART_DIRECTION_NONE
00749   *         @arg @ref LL_LPUART_DIRECTION_RX
00750   *         @arg @ref LL_LPUART_DIRECTION_TX
00751   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00752   * @retval None
00753   */
00754 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
00755 {
00756   ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00757 }
00758
00759 /**
00760   * @brief  Return enabled/disabled states of Transmitter and Receiver
00761   * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
00762   *         CR1          TE            LL_LPUART_GetTransferDirection
00763   * @param  LPUARTx LPUART Instance
00764   * @retval Returned value can be one of the following values:
00765   *         @arg @ref LL_LPUART_DIRECTION_NONE
00766   *         @arg @ref LL_LPUART_DIRECTION_RX
00767   *         @arg @ref LL_LPUART_DIRECTION_TX
00768   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00769   */
00770 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
00771 {
00772   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00773 }
00774
00775 /**
00776   * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
00777   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00778   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00779   *         (depending on data width) and parity is checked on the received data.
00780   * @rmtoll CR1          PS            LL_LPUART_SetParity\n
00781   *         CR1          PCE           LL_LPUART_SetParity
00782   * @param  LPUARTx LPUART Instance
00783   * @param  Parity This parameter can be one of the following values:
00784   *         @arg @ref LL_LPUART_PARITY_NONE
00785   *         @arg @ref LL_LPUART_PARITY_EVEN
00786   *         @arg @ref LL_LPUART_PARITY_ODD
00787   * @retval None
00788   */
00789 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
00790 {
00791   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00792 }
00793
00794 /**
00795   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00796   * @rmtoll CR1          PS            LL_LPUART_GetParity\n
00797   *         CR1          PCE           LL_LPUART_GetParity
00798   * @param  LPUARTx LPUART Instance
00799   * @retval Returned value can be one of the following values:
00800   *         @arg @ref LL_LPUART_PARITY_NONE
00801   *         @arg @ref LL_LPUART_PARITY_EVEN
00802   *         @arg @ref LL_LPUART_PARITY_ODD
00803   */
00804 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
00805 {
00806   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00807 }
00808
00809 /**
00810   * @brief  Set Receiver Wake Up method from Mute mode.
00811   * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
00812   * @param  LPUARTx LPUART Instance
00813   * @param  Method This parameter can be one of the following values:
00814   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00815   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00816   * @retval None
00817   */
00818 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
00819 {
00820   MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
00821 }
00822
00823 /**
00824   * @brief  Return Receiver Wake Up method from Mute mode
00825   * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
00826   * @param  LPUARTx LPUART Instance
00827   * @retval Returned value can be one of the following values:
00828   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00829   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00830   */
00831 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
00832 {
00833   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
00834 }
00835
00836 /**
00837   * @brief  Set Word length (nb of data bits, excluding start and stop bits)
00838   * @rmtoll CR1          M             LL_LPUART_SetDataWidth
00839   * @param  LPUARTx LPUART Instance
00840   * @param  DataWidth This parameter can be one of the following values:
00841   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00842   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00843   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00844   * @retval None
00845   */
00846 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
00847 {
00848   MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
00849 }
00850
00851 /**
00852   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00853   * @rmtoll CR1          M             LL_LPUART_GetDataWidth
00854   * @param  LPUARTx LPUART Instance
00855   * @retval Returned value can be one of the following values:
00856   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00857   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00858   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00859   */
00860 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
00861 {
00862   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
00863 }
00864
00865 /**
00866   * @brief  Allow switch between Mute Mode and Active mode
00867   * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
00868   * @param  LPUARTx LPUART Instance
00869   * @retval None
00870   */
00871 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
00872 {
00873   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
00874 }
00875
00876 /**
00877   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
00878   * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
00879   * @param  LPUARTx LPUART Instance
00880   * @retval None
00881   */
00882 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
00883 {
00884   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
00885 }
00886
00887 /**
00888   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
00889   * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
00890   * @param  LPUARTx LPUART Instance
00891   * @retval State of bit (1 or 0).
00892   */
00893 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
00894 {
00895   return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
00896 }
00897
00898 /**
00899   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
00900   * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
00901   * @param  LPUARTx LPUART Instance
00902   * @param  PrescalerValue This parameter can be one of the following values:
00903   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00904   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00905   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00906   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00907   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00908   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00909   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00910   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00911   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00912   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00913   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00914   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00915   * @retval None
00916   */
00917 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
00918 {
00919   MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
00920 }
00921
00922 /**
00923   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
00924   * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
00925   * @param  LPUARTx LPUART Instance
00926   * @retval Returned value can be one of the following values:
00927   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00928   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00929   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00930   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00931   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00932   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00933   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00934   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00935   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00936   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00937   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00938   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00939   */
00940 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
00941 {
00942   return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
00943 }
00944
00945 /**
00946   * @brief  Set the length of the stop bits
00947   * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
00948   * @param  LPUARTx LPUART Instance
00949   * @param  StopBits This parameter can be one of the following values:
00950   *         @arg @ref LL_LPUART_STOPBITS_1
00951   *         @arg @ref LL_LPUART_STOPBITS_2
00952   * @retval None
00953   */
00954 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
00955 {
00956   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00957 }
00958
00959 /**
00960   * @brief  Retrieve the length of the stop bits
00961   * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
00962   * @param  LPUARTx LPUART Instance
00963   * @retval Returned value can be one of the following values:
00964   *         @arg @ref LL_LPUART_STOPBITS_1
00965   *         @arg @ref LL_LPUART_STOPBITS_2
00966   */
00967 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
00968 {
00969   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
00970 }
00971
00972 /**
00973   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
00974   * @note   Call of this function is equivalent to following function call sequence :
00975   *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
00976   *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
00977   *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
00978   * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
00979   *         CR1          PCE           LL_LPUART_ConfigCharacter\n
00980   *         CR1          M             LL_LPUART_ConfigCharacter\n
00981   *         CR2          STOP          LL_LPUART_ConfigCharacter
00982   * @param  LPUARTx LPUART Instance
00983   * @param  DataWidth This parameter can be one of the following values:
00984   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00985   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00986   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00987   * @param  Parity This parameter can be one of the following values:
00988   *         @arg @ref LL_LPUART_PARITY_NONE
00989   *         @arg @ref LL_LPUART_PARITY_EVEN
00990   *         @arg @ref LL_LPUART_PARITY_ODD
00991   * @param  StopBits This parameter can be one of the following values:
00992   *         @arg @ref LL_LPUART_STOPBITS_1
00993   *         @arg @ref LL_LPUART_STOPBITS_2
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
00997                                                uint32_t StopBits)
00998 {
00999   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01000   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
01001 }
01002
01003 /**
01004   * @brief  Configure TX/RX pins swapping setting.
01005   * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
01006   * @param  LPUARTx LPUART Instance
01007   * @param  SwapConfig This parameter can be one of the following values:
01008   *         @arg @ref LL_LPUART_TXRX_STANDARD
01009   *         @arg @ref LL_LPUART_TXRX_SWAPPED
01010   * @retval None
01011   */
01012 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
01013 {
01014   MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
01015 }
01016
01017 /**
01018   * @brief  Retrieve TX/RX pins swapping configuration.
01019   * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
01020   * @param  LPUARTx LPUART Instance
01021   * @retval Returned value can be one of the following values:
01022   *         @arg @ref LL_LPUART_TXRX_STANDARD
01023   *         @arg @ref LL_LPUART_TXRX_SWAPPED
01024   */
01025 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
01026 {
01027   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
01028 }
01029
01030 /**
01031   * @brief  Configure RX pin active level logic
01032   * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
01033   * @param  LPUARTx LPUART Instance
01034   * @param  PinInvMethod This parameter can be one of the following values:
01035   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
01036   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
01037   * @retval None
01038   */
01039 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
01040 {
01041   MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01042 }
01043
01044 /**
01045   * @brief  Retrieve RX pin active level logic configuration
01046   * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
01047   * @param  LPUARTx LPUART Instance
01048   * @retval Returned value can be one of the following values:
01049   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
01050   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
01051   */
01052 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
01053 {
01054   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
01055 }
01056
01057 /**
01058   * @brief  Configure TX pin active level logic
01059   * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
01060   * @param  LPUARTx LPUART Instance
01061   * @param  PinInvMethod This parameter can be one of the following values:
01062   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
01063   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
01064   * @retval None
01065   */
01066 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
01067 {
01068   MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01069 }
01070
01071 /**
01072   * @brief  Retrieve TX pin active level logic configuration
01073   * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
01074   * @param  LPUARTx LPUART Instance
01075   * @retval Returned value can be one of the following values:
01076   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
01077   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
01078   */
01079 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
01080 {
01081   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
01082 }
01083
01084 /**
01085   * @brief  Configure Binary data logic.
01086   *
01087   * @note   Allow to define how Logical data from the data register are send/received :
01088   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01089   * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
01090   * @param  LPUARTx LPUART Instance
01091   * @param  DataLogic This parameter can be one of the following values:
01092   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
01093   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
01094   * @retval None
01095   */
01096 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
01097 {
01098   MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
01099 }
01100
01101 /**
01102   * @brief  Retrieve Binary data configuration
01103   * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
01104   * @param  LPUARTx LPUART Instance
01105   * @retval Returned value can be one of the following values:
01106   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
01107   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
01108   */
01109 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
01110 {
01111   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
01112 }
01113
01114 /**
01115   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01116   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01117   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01118   * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
01119   * @param  LPUARTx LPUART Instance
01120   * @param  BitOrder This parameter can be one of the following values:
01121   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
01122   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
01123   * @retval None
01124   */
01125 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
01126 {
01127   MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01128 }
01129
01130 /**
01131   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01132   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01133   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01134   * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
01135   * @param  LPUARTx LPUART Instance
01136   * @retval Returned value can be one of the following values:
01137   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
01138   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
01139   */
01140 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
01141 {
01142   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
01143 }
01144
01145 /**
01146   * @brief  Set Address of the LPUART node.
01147   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01148   *         for wake up with address mark detection.
01149   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01150   *         (b7-b4 should be set to 0)
01151   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01152   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01153   *         for wake up with 7-bit address mark detection.
01154   *         The MSB of the character sent by the transmitter should be equal to 1.
01155   *         It may also be used for character detection during normal reception,
01156   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01157   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01158   *         value and CMF flag is set on match)
01159   * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
01160   *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
01161   * @param  LPUARTx LPUART Instance
01162   * @param  AddressLen This parameter can be one of the following values:
01163   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
01164   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
01165   * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
01166   * @retval None
01167   */
01168 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
01169 {
01170   MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01171              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01172 }
01173
01174 /**
01175   * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
01176   * @note   If 4-bit Address Detection is selected in ADDM7,
01177   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01178   *         If 7-bit Address Detection is selected in ADDM7,
01179   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01180   * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
01181   * @param  LPUARTx LPUART Instance
01182   * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
01183   */
01184 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
01185 {
01186   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01187 }
01188
01189 /**
01190   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01191   * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
01192   * @param  LPUARTx LPUART Instance
01193   * @retval Returned value can be one of the following values:
01194   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
01195   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
01196   */
01197 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
01198 {
01199   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
01200 }
01201
01202 /**
01203   * @brief  Enable RTS HW Flow Control
01204   * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
01205   * @param  LPUARTx LPUART Instance
01206   * @retval None
01207   */
01208 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01209 {
01210   SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
01211 }
01212
01213 /**
01214   * @brief  Disable RTS HW Flow Control
01215   * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
01216   * @param  LPUARTx LPUART Instance
01217   * @retval None
01218   */
01219 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01220 {
01221   CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
01222 }
01223
01224 /**
01225   * @brief  Enable CTS HW Flow Control
01226   * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
01227   * @param  LPUARTx LPUART Instance
01228   * @retval None
01229   */
01230 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01231 {
01232   SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
01233 }
01234
01235 /**
01236   * @brief  Disable CTS HW Flow Control
01237   * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
01238   * @param  LPUARTx LPUART Instance
01239   * @retval None
01240   */
01241 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01242 {
01243   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
01244 }
01245
01246 /**
01247   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01248   * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
01249   *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
01250   * @param  LPUARTx LPUART Instance
01251   * @param  HardwareFlowControl This parameter can be one of the following values:
01252   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01253   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01254   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01255   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01256   * @retval None
01257   */
01258 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
01259 {
01260   MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01261 }
01262
01263 /**
01264   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01265   * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
01266   *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
01267   * @param  LPUARTx LPUART Instance
01268   * @retval Returned value can be one of the following values:
01269   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01270   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01271   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01272   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01273   */
01274 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
01275 {
01276   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01277 }
01278
01279 /**
01280   * @brief  Enable Overrun detection
01281   * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
01282   * @param  LPUARTx LPUART Instance
01283   * @retval None
01284   */
01285 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
01286 {
01287   CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01288 }
01289
01290 /**
01291   * @brief  Disable Overrun detection
01292   * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
01293   * @param  LPUARTx LPUART Instance
01294   * @retval None
01295   */
01296 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
01297 {
01298   SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01299 }
01300
01301 /**
01302   * @brief  Indicate if Overrun detection is enabled
01303   * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
01304   * @param  LPUARTx LPUART Instance
01305   * @retval State of bit (1 or 0).
01306   */
01307 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
01308 {
01309   return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
01310 }
01311
01312 /**
01313   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01314   * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
01315   * @param  LPUARTx LPUART Instance
01316   * @param  Type This parameter can be one of the following values:
01317   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01318   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01319   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01320   * @retval None
01321   */
01322 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
01323 {
01324   MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
01325 }
01326
01327 /**
01328   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01329   * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
01330   * @param  LPUARTx LPUART Instance
01331   * @retval Returned value can be one of the following values:
01332   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01333   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01334   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01335   */
01336 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
01337 {
01338   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
01339 }
01340
01341 /**
01342   * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
01343   *
01344   * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
01345   *         according to used Peripheral Clock and expected Baud Rate values
01346   * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
01347   *         (Baud rate value != 0).
01348   * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
01349   *         a care should be taken when generating high baud rates using high PeriphClk
01350   *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
01351   * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
01352   * @param  LPUARTx LPUART Instance
01353   * @param  PeriphClk Peripheral Clock
01354   * @param  PrescalerValue This parameter can be one of the following values:
01355   *         @arg @ref LL_LPUART_PRESCALER_DIV1
01356   *         @arg @ref LL_LPUART_PRESCALER_DIV2
01357   *         @arg @ref LL_LPUART_PRESCALER_DIV4
01358   *         @arg @ref LL_LPUART_PRESCALER_DIV6
01359   *         @arg @ref LL_LPUART_PRESCALER_DIV8
01360   *         @arg @ref LL_LPUART_PRESCALER_DIV10
01361   *         @arg @ref LL_LPUART_PRESCALER_DIV12
01362   *         @arg @ref LL_LPUART_PRESCALER_DIV16
01363   *         @arg @ref LL_LPUART_PRESCALER_DIV32
01364   *         @arg @ref LL_LPUART_PRESCALER_DIV64
01365   *         @arg @ref LL_LPUART_PRESCALER_DIV128
01366   *         @arg @ref LL_LPUART_PRESCALER_DIV256
01367   * @param  BaudRate Baud Rate
01368   * @retval None
01369   */
01370 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01371                                            uint32_t BaudRate)
01372 {
01373   if (BaudRate != 0U)
01374   {
01375     LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
01376   }
01377 }
01378
01379 /**
01380   * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
01381   *         (full BRR content), and to used Peripheral Clock values
01382   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01383   * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
01384   * @param  LPUARTx LPUART Instance
01385   * @param  PeriphClk Peripheral Clock
01386   * @param  PrescalerValue This parameter can be one of the following values:
01387   *         @arg @ref LL_LPUART_PRESCALER_DIV1
01388   *         @arg @ref LL_LPUART_PRESCALER_DIV2
01389   *         @arg @ref LL_LPUART_PRESCALER_DIV4
01390   *         @arg @ref LL_LPUART_PRESCALER_DIV6
01391   *         @arg @ref LL_LPUART_PRESCALER_DIV8
01392   *         @arg @ref LL_LPUART_PRESCALER_DIV10
01393   *         @arg @ref LL_LPUART_PRESCALER_DIV12
01394   *         @arg @ref LL_LPUART_PRESCALER_DIV16
01395   *         @arg @ref LL_LPUART_PRESCALER_DIV32
01396   *         @arg @ref LL_LPUART_PRESCALER_DIV64
01397   *         @arg @ref LL_LPUART_PRESCALER_DIV128
01398   *         @arg @ref LL_LPUART_PRESCALER_DIV256
01399   * @retval Baud Rate
01400   */
01401 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
01402                                                uint32_t PrescalerValue)
01403 {
01404   uint32_t lpuartdiv;
01405   uint32_t brrresult;
01406   uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
01407
01408   lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
01409
01410   if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
01411   {
01412     brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
01413   }
01414   else
01415   {
01416     brrresult = 0x0UL;
01417   }
01418
01419   return (brrresult);
01420 }
01421
01422 /**
01423   * @}
01424   */
01425
01426 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01427   * @{
01428   */
01429
01430 /**
01431   * @brief  Enable Single Wire Half-Duplex mode
01432   * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
01433   * @param  LPUARTx LPUART Instance
01434   * @retval None
01435   */
01436 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
01437 {
01438   SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01439 }
01440
01441 /**
01442   * @brief  Disable Single Wire Half-Duplex mode
01443   * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
01444   * @param  LPUARTx LPUART Instance
01445   * @retval None
01446   */
01447 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
01448 {
01449   CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01450 }
01451
01452 /**
01453   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
01454   * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
01455   * @param  LPUARTx LPUART Instance
01456   * @retval State of bit (1 or 0).
01457   */
01458 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
01459 {
01460   return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
01461 }
01462
01463 /**
01464   * @}
01465   */
01466
01467 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
01468   * @{
01469   */
01470
01471 /**
01472   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01473   * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
01474   * @param  LPUARTx LPUART Instance
01475   * @param  Time Value between Min_Data=0 and Max_Data=31
01476   * @retval None
01477   */
01478 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01479 {
01480   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
01481 }
01482
01483 /**
01484   * @brief  Return DEDT (Driver Enable De-Assertion Time)
01485   * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
01486   * @param  LPUARTx LPUART Instance
01487   * @retval Time value expressed on 5 bits ([4:0] bits) : c
01488   */
01489 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
01490 {
01491   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
01492 }
01493
01494 /**
01495   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01496   * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
01497   * @param  LPUARTx LPUART Instance
01498   * @param  Time Value between Min_Data=0 and Max_Data=31
01499   * @retval None
01500   */
01501 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01502 {
01503   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
01504 }
01505
01506 /**
01507   * @brief  Return DEAT (Driver Enable Assertion Time)
01508   * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
01509   * @param  LPUARTx LPUART Instance
01510   * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
01511   */
01512 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
01513 {
01514   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
01515 }
01516
01517 /**
01518   * @brief  Enable Driver Enable (DE) Mode
01519   * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
01520   * @param  LPUARTx LPUART Instance
01521   * @retval None
01522   */
01523 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
01524 {
01525   SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
01526 }
01527
01528 /**
01529   * @brief  Disable Driver Enable (DE) Mode
01530   * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
01531   * @param  LPUARTx LPUART Instance
01532   * @retval None
01533   */
01534 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
01535 {
01536   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
01537 }
01538
01539 /**
01540   * @brief  Indicate if Driver Enable (DE) Mode is enabled
01541   * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
01542   * @param  LPUARTx LPUART Instance
01543   * @retval State of bit (1 or 0).
01544   */
01545 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
01546 {
01547   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
01548 }
01549
01550 /**
01551   * @brief  Select Driver Enable Polarity
01552   * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
01553   * @param  LPUARTx LPUART Instance
01554   * @param  Polarity This parameter can be one of the following values:
01555   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01556   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01557   * @retval None
01558   */
01559 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
01560 {
01561   MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
01562 }
01563
01564 /**
01565   * @brief  Return Driver Enable Polarity
01566   * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
01567   * @param  LPUARTx LPUART Instance
01568   * @retval Returned value can be one of the following values:
01569   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01570   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01571   */
01572 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
01573 {
01574   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
01575 }
01576
01577 /**
01578   * @}
01579   */
01580
01581 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
01582   * @{
01583   */
01584
01585 /**
01586   * @brief  Check if the LPUART Parity Error Flag is set or not
01587   * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
01588   * @param  LPUARTx LPUART Instance
01589   * @retval State of bit (1 or 0).
01590   */
01591 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
01592 {
01593   return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
01594 }
01595
01596 /**
01597   * @brief  Check if the LPUART Framing Error Flag is set or not
01598   * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
01599   * @param  LPUARTx LPUART Instance
01600   * @retval State of bit (1 or 0).
01601   */
01602 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
01603 {
01604   return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
01605 }
01606
01607 /**
01608   * @brief  Check if the LPUART Noise error detected Flag is set or not
01609   * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
01610   * @param  LPUARTx LPUART Instance
01611   * @retval State of bit (1 or 0).
01612   */
01613 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
01614 {
01615   return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
01616 }
01617
01618 /**
01619   * @brief  Check if the LPUART OverRun Error Flag is set or not
01620   * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
01621   * @param  LPUARTx LPUART Instance
01622   * @retval State of bit (1 or 0).
01623   */
01624 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
01625 {
01626   return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
01627 }
01628
01629 /**
01630   * @brief  Check if the LPUART IDLE line detected Flag is set or not
01631   * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
01632   * @param  LPUARTx LPUART Instance
01633   * @retval State of bit (1 or 0).
01634   */
01635 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
01636 {
01637   return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
01638 }
01639
01640 /* Legacy define */
01641 #define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE
01642
01643 /**
01644   * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
01645   * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
01646   * @param  LPUARTx LPUART Instance
01647   * @retval State of bit (1 or 0).
01648   */
01649 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
01650 {
01651   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
01652 }
01653
01654 /**
01655   * @brief  Check if the LPUART Transmission Complete Flag is set or not
01656   * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
01657   * @param  LPUARTx LPUART Instance
01658   * @retval State of bit (1 or 0).
01659   */
01660 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
01661 {
01662   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
01663 }
01664
01665 /* Legacy define */
01666 #define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF
01667
01668 /**
01669   * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
01670   * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
01671   * @param  LPUARTx LPUART Instance
01672   * @retval State of bit (1 or 0).
01673   */
01674 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
01675 {
01676   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
01677 }
01678
01679 /**
01680   * @brief  Check if the LPUART CTS interrupt Flag is set or not
01681   * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
01682   * @param  LPUARTx LPUART Instance
01683   * @retval State of bit (1 or 0).
01684   */
01685 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
01686 {
01687   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
01688 }
01689
01690 /**
01691   * @brief  Check if the LPUART CTS Flag is set or not
01692   * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
01693   * @param  LPUARTx LPUART Instance
01694   * @retval State of bit (1 or 0).
01695   */
01696 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
01697 {
01698   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
01699 }
01700
01701 /**
01702   * @brief  Check if the LPUART Busy Flag is set or not
01703   * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
01704   * @param  LPUARTx LPUART Instance
01705   * @retval State of bit (1 or 0).
01706   */
01707 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
01708 {
01709   return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
01710 }
01711
01712 /**
01713   * @brief  Check if the LPUART Character Match Flag is set or not
01714   * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
01715   * @param  LPUARTx LPUART Instance
01716   * @retval State of bit (1 or 0).
01717   */
01718 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
01719 {
01720   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
01721 }
01722
01723 /**
01724   * @brief  Check if the LPUART Send Break Flag is set or not
01725   * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
01726   * @param  LPUARTx LPUART Instance
01727   * @retval State of bit (1 or 0).
01728   */
01729 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
01730 {
01731   return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
01732 }
01733
01734 /**
01735   * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
01736   * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
01737   * @param  LPUARTx LPUART Instance
01738   * @retval State of bit (1 or 0).
01739   */
01740 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
01741 {
01742   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
01743 }
01744
01745 /**
01746   * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
01747   * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
01748   * @param  LPUARTx LPUART Instance
01749   * @retval State of bit (1 or 0).
01750   */
01751 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
01752 {
01753   return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
01754 }
01755
01756 /**
01757   * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
01758   * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
01759   * @param  LPUARTx LPUART Instance
01760   * @retval State of bit (1 or 0).
01761   */
01762 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
01763 {
01764   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
01765 }
01766
01767 /**
01768   * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
01769   * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
01770   * @param  LPUARTx LPUART Instance
01771   * @retval State of bit (1 or 0).
01772   */
01773 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
01774 {
01775   return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
01776 }
01777
01778 /**
01779   * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
01780   * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
01781   * @param  LPUARTx LPUART Instance
01782   * @retval State of bit (1 or 0).
01783   */
01784 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
01785 {
01786   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
01787 }
01788
01789 /**
01790   * @brief  Check if the LPUART RX FIFO Full Flag is set or not
01791   * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
01792   * @param  LPUARTx LPUART Instance
01793   * @retval State of bit (1 or 0).
01794   */
01795 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
01796 {
01797   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
01798 }
01799
01800 /**
01801   * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
01802   * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
01803   * @param  LPUARTx LPUART Instance
01804   * @retval State of bit (1 or 0).
01805   */
01806 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
01807 {
01808   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
01809 }
01810
01811 /**
01812   * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
01813   * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
01814   * @param  LPUARTx LPUART Instance
01815   * @retval State of bit (1 or 0).
01816   */
01817 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
01818 {
01819   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
01820 }
01821
01822 /**
01823   * @brief  Clear Parity Error Flag
01824   * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
01825   * @param  LPUARTx LPUART Instance
01826   * @retval None
01827   */
01828 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
01829 {
01830   WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
01831 }
01832
01833 /**
01834   * @brief  Clear Framing Error Flag
01835   * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
01836   * @param  LPUARTx LPUART Instance
01837   * @retval None
01838   */
01839 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
01840 {
01841   WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
01842 }
01843
01844 /**
01845   * @brief  Clear Noise detected Flag
01846   * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
01847   * @param  LPUARTx LPUART Instance
01848   * @retval None
01849   */
01850 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
01851 {
01852   WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
01853 }
01854
01855 /**
01856   * @brief  Clear OverRun Error Flag
01857   * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
01858   * @param  LPUARTx LPUART Instance
01859   * @retval None
01860   */
01861 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
01862 {
01863   WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
01864 }
01865
01866 /**
01867   * @brief  Clear IDLE line detected Flag
01868   * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
01869   * @param  LPUARTx LPUART Instance
01870   * @retval None
01871   */
01872 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
01873 {
01874   WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
01875 }
01876
01877 /**
01878   * @brief  Clear Transmission Complete Flag
01879   * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
01880   * @param  LPUARTx LPUART Instance
01881   * @retval None
01882   */
01883 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
01884 {
01885   WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
01886 }
01887
01888 /**
01889   * @brief  Clear CTS Interrupt Flag
01890   * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
01891   * @param  LPUARTx LPUART Instance
01892   * @retval None
01893   */
01894 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
01895 {
01896   WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
01897 }
01898
01899 /**
01900   * @brief  Clear Character Match Flag
01901   * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
01902   * @param  LPUARTx LPUART Instance
01903   * @retval None
01904   */
01905 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
01906 {
01907   WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
01908 }
01909
01910 /**
01911   * @brief  Clear Wake Up from stop mode Flag
01912   * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
01913   * @param  LPUARTx LPUART Instance
01914   * @retval None
01915   */
01916 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
01917 {
01918   WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
01919 }
01920
01921 /**
01922   * @}
01923   */
01924
01925 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
01926   * @{
01927   */
01928
01929 /**
01930   * @brief  Enable IDLE Interrupt
01931   * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
01932   * @param  LPUARTx LPUART Instance
01933   * @retval None
01934   */
01935 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
01936 {
01937   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
01938 }
01939
01940 /* Legacy define */
01941 #define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE
01942
01943 /**
01944   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
01945   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
01946   * @param  LPUARTx LPUART Instance
01947   * @retval None
01948   */
01949 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
01950 {
01951   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
01952 }
01953
01954 /**
01955   * @brief  Enable Transmission Complete Interrupt
01956   * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
01957   * @param  LPUARTx LPUART Instance
01958   * @retval None
01959   */
01960 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
01961 {
01962   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
01963 }
01964
01965 /* Legacy define */
01966 #define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF
01967
01968 /**
01969   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
01970   * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
01971   * @param  LPUARTx LPUART Instance
01972   * @retval None
01973   */
01974 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
01975 {
01976   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
01977 }
01978
01979 /**
01980   * @brief  Enable Parity Error Interrupt
01981   * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
01982   * @param  LPUARTx LPUART Instance
01983   * @retval None
01984   */
01985 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
01986 {
01987   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
01988 }
01989
01990 /**
01991   * @brief  Enable Character Match Interrupt
01992   * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
01993   * @param  LPUARTx LPUART Instance
01994   * @retval None
01995   */
01996 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
01997 {
01998   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
01999 }
02000
02001 /**
02002   * @brief  Enable TX FIFO Empty Interrupt
02003   * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
02004   * @param  LPUARTx LPUART Instance
02005   * @retval None
02006   */
02007 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
02008 {
02009   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
02010 }
02011
02012 /**
02013   * @brief  Enable RX FIFO Full Interrupt
02014   * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
02015   * @param  LPUARTx LPUART Instance
02016   * @retval None
02017   */
02018 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
02019 {
02020   ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
02021 }
02022
02023 /**
02024   * @brief  Enable Error Interrupt
02025   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02026   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
02027   *         - 0: Interrupt is inhibited
02028   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
02029   * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
02030   * @param  LPUARTx LPUART Instance
02031   * @retval None
02032   */
02033 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
02034 {
02035   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
02036 }
02037
02038 /**
02039   * @brief  Enable CTS Interrupt
02040   * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
02041   * @param  LPUARTx LPUART Instance
02042   * @retval None
02043   */
02044 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
02045 {
02046   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
02047 }
02048
02049 /**
02050   * @brief  Enable Wake Up from Stop Mode Interrupt
02051   * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
02052   * @param  LPUARTx LPUART Instance
02053   * @retval None
02054   */
02055 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
02056 {
02057   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
02058 }
02059
02060 /**
02061   * @brief  Enable TX FIFO Threshold Interrupt
02062   * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
02063   * @param  LPUARTx LPUART Instance
02064   * @retval None
02065   */
02066 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
02067 {
02068   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
02069 }
02070
02071 /**
02072   * @brief  Enable RX FIFO Threshold Interrupt
02073   * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
02074   * @param  LPUARTx LPUART Instance
02075   * @retval None
02076   */
02077 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
02078 {
02079   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
02080 }
02081
02082 /**
02083   * @brief  Disable IDLE Interrupt
02084   * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
02085   * @param  LPUARTx LPUART Instance
02086   * @retval None
02087   */
02088 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
02089 {
02090   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
02091 }
02092
02093 /* Legacy define */
02094 #define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE
02095
02096 /**
02097   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
02098   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
02099   * @param  LPUARTx LPUART Instance
02100   * @retval None
02101   */
02102 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
02103 {
02104   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
02105 }
02106
02107 /**
02108   * @brief  Disable Transmission Complete Interrupt
02109   * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
02110   * @param  LPUARTx LPUART Instance
02111   * @retval None
02112   */
02113 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
02114 {
02115   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
02116 }
02117
02118 /* Legacy define */
02119 #define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF
02120
02121 /**
02122   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
02123   * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
02124   * @param  LPUARTx LPUART Instance
02125   * @retval None
02126   */
02127 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
02128 {
02129   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
02130 }
02131
02132 /**
02133   * @brief  Disable Parity Error Interrupt
02134   * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
02135   * @param  LPUARTx LPUART Instance
02136   * @retval None
02137   */
02138 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
02139 {
02140   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
02141 }
02142
02143 /**
02144   * @brief  Disable Character Match Interrupt
02145   * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
02146   * @param  LPUARTx LPUART Instance
02147   * @retval None
02148   */
02149 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
02150 {
02151   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
02152 }
02153
02154 /**
02155   * @brief  Disable TX FIFO Empty Interrupt
02156   * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
02157   * @param  LPUARTx LPUART Instance
02158   * @retval None
02159   */
02160 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
02161 {
02162   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
02163 }
02164
02165 /**
02166   * @brief  Disable RX FIFO Full Interrupt
02167   * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
02168   * @param  LPUARTx LPUART Instance
02169   * @retval None
02170   */
02171 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
02172 {
02173   ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
02174 }
02175
02176 /**
02177   * @brief  Disable Error Interrupt
02178   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02179   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
02180   *         - 0: Interrupt is inhibited
02181   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
02182   * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
02183   * @param  LPUARTx LPUART Instance
02184   * @retval None
02185   */
02186 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
02187 {
02188   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
02189 }
02190
02191 /**
02192   * @brief  Disable CTS Interrupt
02193   * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
02194   * @param  LPUARTx LPUART Instance
02195   * @retval None
02196   */
02197 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
02198 {
02199   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
02200 }
02201
02202 /**
02203   * @brief  Disable Wake Up from Stop Mode Interrupt
02204   * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
02205   * @param  LPUARTx LPUART Instance
02206   * @retval None
02207   */
02208 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
02209 {
02210   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
02211 }
02212
02213 /**
02214   * @brief  Disable TX FIFO Threshold Interrupt
02215   * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
02216   * @param  LPUARTx LPUART Instance
02217   * @retval None
02218   */
02219 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
02220 {
02221   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
02222 }
02223
02224 /**
02225   * @brief  Disable RX FIFO Threshold Interrupt
02226   * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
02227   * @param  LPUARTx LPUART Instance
02228   * @retval None
02229   */
02230 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
02231 {
02232   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
02233 }
02234
02235 /**
02236   * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
02237   * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
02238   * @param  LPUARTx LPUART Instance
02239   * @retval State of bit (1 or 0).
02240   */
02241 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
02242 {
02243   return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
02244 }
02245
02246 /* Legacy define */
02247 #define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
02248
02249 /**
02250   * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
02251   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
02252   * @param  LPUARTx LPUART Instance
02253   * @retval State of bit (1 or 0).
02254   */
02255 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
02256 {
02257   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
02258 }
02259
02260 /**
02261   * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
02262   * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
02263   * @param  LPUARTx LPUART Instance
02264   * @retval State of bit (1 or 0).
02265   */
02266 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
02267 {
02268   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
02269 }
02270
02271 /* Legacy define */
02272 #define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF
02273
02274 /**
02275   * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
02276   * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
02277   * @param  LPUARTx LPUART Instance
02278   * @retval State of bit (1 or 0).
02279   */
02280 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
02281 {
02282   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
02283 }
02284
02285 /**
02286   * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
02287   * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
02288   * @param  LPUARTx LPUART Instance
02289   * @retval State of bit (1 or 0).
02290   */
02291 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
02292 {
02293   return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
02294 }
02295
02296 /**
02297   * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
02298   * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
02299   * @param  LPUARTx LPUART Instance
02300   * @retval State of bit (1 or 0).
02301   */
02302 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
02303 {
02304   return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
02305 }
02306
02307 /**
02308   * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
02309   * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
02310   * @param  LPUARTx LPUART Instance
02311   * @retval State of bit (1 or 0).
02312   */
02313 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
02314 {
02315   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
02316 }
02317
02318 /**
02319   * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
02320   * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
02321   * @param  LPUARTx LPUART Instance
02322   * @retval State of bit (1 or 0).
02323   */
02324 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
02325 {
02326   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
02327 }
02328
02329 /**
02330   * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
02331   * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
02332   * @param  LPUARTx LPUART Instance
02333   * @retval State of bit (1 or 0).
02334   */
02335 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
02336 {
02337   return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
02338 }
02339
02340 /**
02341   * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
02342   * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
02343   * @param  LPUARTx LPUART Instance
02344   * @retval State of bit (1 or 0).
02345   */
02346 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
02347 {
02348   return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
02349 }
02350
02351 /**
02352   * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
02353   * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
02354   * @param  LPUARTx LPUART Instance
02355   * @retval State of bit (1 or 0).
02356   */
02357 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
02358 {
02359   return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
02360 }
02361
02362 /**
02363   * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
02364   * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
02365   * @param  LPUARTx LPUART Instance
02366   * @retval State of bit (1 or 0).
02367   */
02368 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
02369 {
02370   return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
02371 }
02372
02373 /**
02374   * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
02375   * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
02376   * @param  LPUARTx LPUART Instance
02377   * @retval State of bit (1 or 0).
02378   */
02379 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
02380 {
02381   return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
02382 }
02383
02384 /**
02385   * @}
02386   */
02387
02388 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
02389   * @{
02390   */
02391
02392 /**
02393   * @brief  Enable DMA Mode for reception
02394   * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
02395   * @param  LPUARTx LPUART Instance
02396   * @retval None
02397   */
02398 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
02399 {
02400   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
02401 }
02402
02403 /**
02404   * @brief  Disable DMA Mode for reception
02405   * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
02406   * @param  LPUARTx LPUART Instance
02407   * @retval None
02408   */
02409 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
02410 {
02411   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
02412 }
02413
02414 /**
02415   * @brief  Check if DMA Mode is enabled for reception
02416   * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
02417   * @param  LPUARTx LPUART Instance
02418   * @retval State of bit (1 or 0).
02419   */
02420 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
02421 {
02422   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
02423 }
02424
02425 /**
02426   * @brief  Enable DMA Mode for transmission
02427   * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
02428   * @param  LPUARTx LPUART Instance
02429   * @retval None
02430   */
02431 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
02432 {
02433   ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
02434 }
02435
02436 /**
02437   * @brief  Disable DMA Mode for transmission
02438   * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
02439   * @param  LPUARTx LPUART Instance
02440   * @retval None
02441   */
02442 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
02443 {
02444   ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
02445 }
02446
02447 /**
02448   * @brief  Check if DMA Mode is enabled for transmission
02449   * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
02450   * @param  LPUARTx LPUART Instance
02451   * @retval State of bit (1 or 0).
02452   */
02453 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
02454 {
02455   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
02456 }
02457
02458 /**
02459   * @brief  Enable DMA Disabling on Reception Error
02460   * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
02461   * @param  LPUARTx LPUART Instance
02462   * @retval None
02463   */
02464 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02465 {
02466   SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
02467 }
02468
02469 /**
02470   * @brief  Disable DMA Disabling on Reception Error
02471   * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
02472   * @param  LPUARTx LPUART Instance
02473   * @retval None
02474   */
02475 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02476 {
02477   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
02478 }
02479
02480 /**
02481   * @brief  Indicate if DMA Disabling on Reception Error is disabled
02482   * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
02483   * @param  LPUARTx LPUART Instance
02484   * @retval State of bit (1 or 0).
02485   */
02486 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
02487 {
02488   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
02489 }
02490
02491 /**
02492   * @brief  Get the LPUART data register address used for DMA transfer
02493   * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
02494   * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
02495   * @param  LPUARTx LPUART Instance
02496   * @param  Direction This parameter can be one of the following values:
02497   *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
02498   *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
02499   * @retval Address of data register
02500   */
02501 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
02502 {
02503   uint32_t data_reg_addr;
02504
02505   if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
02506   {
02507     /* return address of TDR register */
02508     data_reg_addr = (uint32_t) &(LPUARTx->TDR);
02509   }
02510   else
02511   {
02512     /* return address of RDR register */
02513     data_reg_addr = (uint32_t) &(LPUARTx->RDR);
02514   }
02515
02516   return data_reg_addr;
02517 }
02518
02519 /**
02520   * @}
02521   */
02522
02523 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
02524   * @{
02525   */
02526
02527 /**
02528   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
02529   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
02530   * @param  LPUARTx LPUART Instance
02531   * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
02532   */
02533 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
02534 {
02535   return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
02536 }
02537
02538 /**
02539   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
02540   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
02541   * @param  LPUARTx LPUART Instance
02542   * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
02543   */
02544 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
02545 {
02546   return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
02547 }
02548
02549 /**
02550   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
02551   * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
02552   * @param  LPUARTx LPUART Instance
02553   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
02554   * @retval None
02555   */
02556 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
02557 {
02558   LPUARTx->TDR = Value;
02559 }
02560
02561 /**
02562   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
02563   * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
02564   * @param  LPUARTx LPUART Instance
02565   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
02566   * @retval None
02567   */
02568 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
02569 {
02570   LPUARTx->TDR = Value & 0x1FFUL;
02571 }
02572
02573 /**
02574   * @}
02575   */
02576
02577 /** @defgroup LPUART_LL_EF_Execution Execution
02578   * @{
02579   */
02580
02581 /**
02582   * @brief  Request Break sending
02583   * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
02584   * @param  LPUARTx LPUART Instance
02585   * @retval None
02586   */
02587 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
02588 {
02589   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
02590 }
02591
02592 /**
02593   * @brief  Put LPUART in mute mode and set the RWU flag
02594   * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
02595   * @param  LPUARTx LPUART Instance
02596   * @retval None
02597   */
02598 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
02599 {
02600   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
02601 }
02602
02603 /**
02604   * @brief  Request a Receive Data and FIFO flush
02605   * @note   Allows to discard the received data without reading them, and avoid an overrun
02606   *         condition.
02607   * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
02608   * @param  LPUARTx LPUART Instance
02609   * @retval None
02610   */
02611 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
02612 {
02613   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
02614 }
02615
02616 /**
02617   * @}
02618   */
02619
02620 #if defined(USE_FULL_LL_DRIVER)
02621 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
02622   * @{
02623   */
02624 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
02625 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
02626 void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
02627 /**
02628   * @}
02629   */
02630 #endif /* USE_FULL_LL_DRIVER */
02631
02632 /**
02633   * @}
02634   */
02635
02636 /**
02637   * @}
02638   */
02639
02640 #endif /* LPUART1 || LPUART2 */
02641
02642 /**
02643   * @}
02644   */
02645
02646 #ifdef __cplusplus
02647 }
02648 #endif
02649
02650 #endif /* STM32G0xx_LL_LPUART_H */
02651
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_pwr.c Source File

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stm32g0xx_ll_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_pwr.h"
00022 #include "stm32g0xx_ll_bus.h"
00023
00024 /** @addtogroup STM32G0xx_LL_Driver
00025   * @{
00026   */
00027
00028 #if defined(PWR)
00029
00030 /** @defgroup PWR_LL PWR
00031   * @{
00032   */
00033
00034 /* Private types -------------------------------------------------------------*/
00035 /* Private variables ---------------------------------------------------------*/
00036 /* Private constants ---------------------------------------------------------*/
00037 /* Private macros ------------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039
00040 /* Exported functions --------------------------------------------------------*/
00041 /** @addtogroup PWR_LL_Exported_Functions
00042   * @{
00043   */
00044
00045 /** @addtogroup PWR_LL_EF_Init
00046   * @{
00047   */
00048
00049 /**
00050   * @brief  De-initialize the PWR registers to their default reset values.
00051   * @retval An ErrorStatus enumeration value:
00052   *          - SUCCESS: PWR registers are de-initialized
00053   *          - ERROR: not applicable
00054   */
00055 ErrorStatus LL_PWR_DeInit(void)
00056 {
00057   /* Force reset of PWR clock */
00058   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
00059
00060   /* Release reset of PWR clock */
00061   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
00062
00063   return SUCCESS;
00064 }
00065
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077 #endif /* defined(PWR) */
00078 /**
00079   * @}
00080   */
00081
00082 #endif /* USE_FULL_LL_DRIVER */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_pwr.h Source File

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stm32g0xx_ll_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_PWR_H
00021 #define STM32G0xx_LL_PWR_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(PWR)
00035
00036 /** @defgroup PWR_LL PWR
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Private constants ---------------------------------------------------------*/
00044
00045 /* Private macros ------------------------------------------------------------*/
00046
00047 /* Exported types ------------------------------------------------------------*/
00048 /* Exported constants --------------------------------------------------------*/
00049 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
00050   * @{
00051   */
00052
00053 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
00054   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
00055   * @{
00056   */
00057 #define LL_PWR_SCR_CSBF                    PWR_SCR_CSBF
00058 #define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF
00059 #define LL_PWR_SCR_CWUF6                   PWR_SCR_CWUF6
00060 #define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5
00061 #define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4
00062 #if defined(PWR_CR3_EWUP3)
00063 #define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3
00064 #endif /* PWR_CR3_EWUP3 */
00065 #define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2
00066 #define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
00072   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
00073   * @{
00074   */
00075 #define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI
00076 #define LL_PWR_SR1_SBF                     PWR_SR1_SBF
00077 #define LL_PWR_SR1_WUF6                    PWR_SR1_WUF6
00078 #define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5
00079 #define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4
00080 #if defined(PWR_CR3_EWUP3)
00081 #define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3
00082 #endif /* PWR_CR3_EWUP3 */
00083 #define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2
00084 #define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1
00085 #if defined(PWR_SR2_PVDO)
00086 #define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO
00087 #endif /* PWR_SR2_PVDO */
00088 #define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF
00089 #define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF
00090 #define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
00096   * @{
00097   */
00098 #define LL_PWR_REGU_VOLTAGE_SCALE1         PWR_CR1_VOS_0
00099 #define LL_PWR_REGU_VOLTAGE_SCALE2         PWR_CR1_VOS_1
00100 /**
00101   * @}
00102   */
00103
00104 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
00105   * @{
00106   */
00107 #define LL_PWR_MODE_STOP0                  (0x00000000UL)
00108 #define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_0)
00109 #define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)
00110 #if defined (PWR_CR1_LPMS_2)
00111 #define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_2)
00112 #endif /* PWR_CR1_LPMS_2 */
00113 /**
00114   * @}
00115   */
00116
00117 #if defined(PWR_CR2_PVDE)
00118 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
00119   * @{
00120   */
00121 #define LL_PWR_PVDLLEVEL_0                  0x000000000u                                /* VPVD0 > 2.05 V */
00122 #define LL_PWR_PVDLLEVEL_1                  (PWR_CR2_PVDFT_0)                           /* VPVD0 > 2.2 V */
00123 #define LL_PWR_PVDLLEVEL_2                  (PWR_CR2_PVDFT_1)                           /* VPVD1 > 2.36 V */
00124 #define LL_PWR_PVDLLEVEL_3                  (PWR_CR2_PVDFT_1 | PWR_CR2_PVDFT_0)         /* VPVD2 > 2.52 V */
00125 #define LL_PWR_PVDLLEVEL_4                  (PWR_CR2_PVDFT_2)                           /* VPVD3 > 2.64 V */
00126 #define LL_PWR_PVDLLEVEL_5                  (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0)         /* VPVD4 > 2.81 V */
00127 #define LL_PWR_PVDLLEVEL_6                  (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1)         /* VPVD5 > 2.91 V */
00128
00129 #define LL_PWR_PVDHLEVEL_0                  0x00000000u                                 /* VPDD0 > 2.15 V */
00130 #define LL_PWR_PVDHLEVEL_1                  (PWR_CR2_PVDRT_0)                           /* VPVD1 > 2.3 V */
00131 #define LL_PWR_PVDHLEVEL_2                  (PWR_CR2_PVDRT_1)                           /* VPVD1 > 2.46 V */
00132 #define LL_PWR_PVDHLEVEL_3                  (PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)         /* VPVD2 > 2.62 V */
00133 #define LL_PWR_PVDHLEVEL_4                  (PWR_CR2_PVDRT_2)                           /* VPVD3 > 2.74 V */
00134 #define LL_PWR_PVDHLEVEL_5                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0)         /* VPVD4 > 2.91 V */
00135 #define LL_PWR_PVDHLEVEL_6                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1)         /* VPVD5 > 3.01 V */
00136 #define LL_PWR_PVDHLEVEL_7                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)  /* External input analog voltage   (Compare internally to VREFINT) */
00137 /**
00138   * @}
00139   */
00140 #endif /* PWR_CR2_PVDE */
00141
00142 #if defined(PWR_PVM_SUPPORT)
00143 /** @defgroup PWR_LL_EC_PVM_IP PVM_IP
00144   * @{
00145   */
00146 #define LL_PWR_PVM_USB                  PWR_CR2_PVMEN_USB                           /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */
00147 /**
00148   * @}
00149   */
00150 #endif /* PWR_PVM_SUPPORT */
00151
00152 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
00153   * @{
00154   */
00155 #define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)
00156 #define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)
00157 #if defined(PWR_CR3_EWUP3)
00158 #define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)
00159 #endif /* PWR_CR3_EWUP3 */
00160 #define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)
00161 #if defined(PWR_CR3_EWUP5)
00162 #define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)
00163 #endif /* PWR_CR3_EWUP5 */
00164 #define LL_PWR_WAKEUP_PIN6                 (PWR_CR3_EWUP6)
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
00170   * @{
00171   */
00172 #define LL_PWR_BATTCHARG_RESISTOR_5K       0x000000000u
00173 #define LL_PWR_BATTCHARG_RESISTOR_1_5K     (PWR_CR4_VBRS)
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup PWR_LL_EC_GPIO GPIO
00179   * @{
00180   */
00181 #define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))
00182 #define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))
00183 #define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))
00184 #define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))
00185 #if defined(GPIOE)
00186 #define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))
00187 #endif /* GPIOE */
00188 #define LL_PWR_GPIO_F                      ((uint32_t)(&(PWR->PUCRF)))
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
00194   * @{
00195   */
00196 #define LL_PWR_GPIO_BIT_0                  0x00000001u
00197 #define LL_PWR_GPIO_BIT_1                  0x00000002u
00198 #define LL_PWR_GPIO_BIT_2                  0x00000004u
00199 #define LL_PWR_GPIO_BIT_3                  0x00000008u
00200 #define LL_PWR_GPIO_BIT_4                  0x00000010u
00201 #define LL_PWR_GPIO_BIT_5                  0x00000020u
00202 #define LL_PWR_GPIO_BIT_6                  0x00000040u
00203 #define LL_PWR_GPIO_BIT_7                  0x00000080u
00204 #define LL_PWR_GPIO_BIT_8                  0x00000100u
00205 #define LL_PWR_GPIO_BIT_9                  0x00000200u
00206 #define LL_PWR_GPIO_BIT_10                 0x00000400u
00207 #define LL_PWR_GPIO_BIT_11                 0x00000800u
00208 #define LL_PWR_GPIO_BIT_12                 0x00001000u
00209 #define LL_PWR_GPIO_BIT_13                 0x00002000u
00210 #define LL_PWR_GPIO_BIT_14                 0x00004000u
00211 #define LL_PWR_GPIO_BIT_15                 0x00008000u
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 /* Exported macro ------------------------------------------------------------*/
00221 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
00222   * @{
00223   */
00224
00225 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
00226   * @{
00227   */
00228
00229 /**
00230   * @brief  Write a value in PWR register
00231   * @param  __REG__ Register to be written
00232   * @param  __VALUE__ Value to be written in the register
00233   * @retval None
00234   */
00235 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
00236
00237 /**
00238   * @brief  Read a value in PWR register
00239   * @param  __REG__ Register to be read
00240   * @retval Register value
00241   */
00242 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
00243 /**
00244   * @}
00245   */
00246
00247 /**
00248   * @}
00249   */
00250
00251
00252 /* Exported functions --------------------------------------------------------*/
00253 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
00254   * @{
00255   */
00256
00257 /** @defgroup PWR_LL_EF_Configuration Configuration
00258   * @{
00259   */
00260 /**
00261   * @brief  Set the main internal regulator output voltage
00262   * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling
00263   * @param  VoltageScaling This parameter can be one of the following values:
00264   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
00265   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
00266   * @retval None
00267   */
00268 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
00269 {
00270   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
00271 }
00272
00273 /**
00274   * @brief  Get the main internal regulator output voltage
00275   * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling
00276   * @retval Returned value can be one of the following values:
00277   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
00278   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
00279   */
00280 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
00281 {
00282   return (READ_BIT(PWR->CR1, PWR_CR1_VOS));
00283 }
00284
00285 /**
00286   * @brief  Switch the regulator from main mode to low-power mode
00287   * @rmtoll CR1          LPR           LL_PWR_EnableLowPowerRunMode
00288   * @retval None
00289   */
00290 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
00291 {
00292   SET_BIT(PWR->CR1, PWR_CR1_LPR);
00293 }
00294
00295 /**
00296   * @brief  Switch the regulator from low-power mode to main mode
00297   * @rmtoll CR1          LPR           LL_PWR_DisableLowPowerRunMode
00298   * @retval None
00299   */
00300 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
00301 {
00302   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
00303 }
00304
00305 /**
00306   * @brief  Check if the regulator is in low-power mode
00307   * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode
00308   * @retval State of bit (1 or 0).
00309   */
00310 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
00311 {
00312   return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
00313 }
00314
00315 /**
00316   * @brief  Switch from run main mode to run low-power mode.
00317   * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode
00318   * @retval None
00319   */
00320 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
00321 {
00322   LL_PWR_EnableLowPowerRunMode();
00323 }
00324
00325 /**
00326   * @brief  Switch from run main mode to low-power mode.
00327   * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode
00328   * @retval None
00329   */
00330 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
00331 {
00332   LL_PWR_DisableLowPowerRunMode();
00333 }
00334
00335 /**
00336   * @brief  Enable access to the backup domain
00337   * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
00338   * @retval None
00339   */
00340 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
00341 {
00342   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00343 }
00344
00345 /**
00346   * @brief  Disable access to the backup domain
00347   * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
00348   * @retval None
00349   */
00350 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
00351 {
00352   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00353 }
00354
00355 /**
00356   * @brief  Check if the backup domain is enabled
00357   * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess
00358   * @retval State of bit (1 or 0).
00359   */
00360 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
00361 {
00362   return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
00363 }
00364
00365 /**
00366   * @brief  Enable Flash Power-down mode during low power sleep mode
00367   * @rmtoll CR1          CFIPD_SLP     LL_PWR_EnableFlashPowerDownInLPSleep
00368   * @retval None
00369   */
00370 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPSleep(void)
00371 {
00372   SET_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
00373 }
00374
00375 /**
00376   * @brief  Disable Flash Power-down mode during Low power sleep mode
00377   * @rmtoll CR1          CFIPD_SLP     LL_PWR_DisableFlashPowerDownInLPSleep
00378   * @retval None
00379   */
00380 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPSleep(void)
00381 {
00382   CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
00383 }
00384
00385 /**
00386   * @brief  Check if flash power-down mode during low power sleep mode domain is enabled
00387   * @rmtoll CR1          CFIPD_SLP     LL_PWR_IsEnableFlashPowerDownInLPSleep
00388   * @retval State of bit (1 or 0).
00389   */
00390 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPSleep(void)
00391 {
00392   return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP) == (PWR_CR1_FPD_LPSLP)) ? 1UL : 0UL);
00393 }
00394
00395 /**
00396   * @brief  Enable Flash Power-down mode during low power run mode
00397   * @rmtoll CR1          CFIPD_RUN     LL_PWR_EnableFlashPowerDownInLPRun
00398   * @retval None
00399   */
00400 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPRun(void)
00401 {
00402   SET_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
00403 }
00404
00405 /**
00406   * @brief  Disable Flash Power-down mode during Low power run mode
00407   * @rmtoll CR1          CFIPD_RUN     LL_PWR_DisableFlashPowerDownInLPRun
00408   * @retval None
00409   */
00410 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPRun(void)
00411 {
00412   CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
00413 }
00414
00415 /**
00416   * @brief  Check if flash power-down mode during low power run mode domain is enabled
00417   * @rmtoll CR1          CFIPD_RUN     LL_PWR_IsEnableFlashPowerDownInLPRun
00418   * @retval State of bit (1 or 0).
00419   */
00420 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPRun(void)
00421 {
00422   return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN) == (PWR_CR1_FPD_LPRUN)) ? 1UL : 0UL);
00423 }
00424
00425 /**
00426   * @brief  Enable Flash Power-down mode during stop mode
00427   * @rmtoll CR1          CFIPD_STOP    LL_PWR_EnableFlashPowerDownInStop
00428   * @retval None
00429   */
00430 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop(void)
00431 {
00432   SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
00433 }
00434
00435 /**
00436   * @brief  Disable Flash Power-down mode during stop mode
00437   * @rmtoll CR1          CFIPD_STOP    LL_PWR_DisableFlashPowerDownInStop
00438   * @retval None
00439   */
00440 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop(void)
00441 {
00442   CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
00443 }
00444
00445 /**
00446   * @brief  Check if flash power-down mode during stop mode domain is enabled
00447   * @rmtoll CR1          CFIPD_STOP    LL_PWR_IsEnableFlashPowerDownInStop
00448   * @retval State of bit (1 or 0).
00449   */
00450 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void)
00451 {
00452   return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL);
00453 }
00454
00455 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
00456 /**
00457   * @brief  Enable VDDIO2 supply
00458   * @rmtoll CR2          IOSV          LL_PWR_EnableVddIO2
00459   * @retval None
00460   */
00461 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
00462 {
00463   SET_BIT(PWR->CR2, PWR_CR2_IOSV);
00464 }
00465
00466 /**
00467   * @brief  Disable VDDIO2 supply
00468   * @rmtoll CR2          IOSV          LL_PWR_DisableVddIO2
00469   * @retval None
00470   */
00471 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
00472 {
00473   CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
00474 }
00475
00476 /**
00477   * @brief  Check if VDDIO2 supply is enabled
00478   * @rmtoll CR2          IOSV          LL_PWR_IsEnabledVddIO2
00479   * @retval State of bit (1 or 0).
00480   */
00481 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
00482 {
00483   return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
00484 }
00485
00486 /**
00487   * @brief  Enable VDDUSB supply
00488   * @rmtoll CR2          USV           LL_PWR_EnableVddUSB
00489   * @retval None
00490   */
00491 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
00492 {
00493   SET_BIT(PWR->CR2, PWR_CR2_USV);
00494 }
00495
00496 /**
00497   * @brief  Disable VDDUSB supply
00498   * @rmtoll CR2          USV           LL_PWR_DisableVddUSB
00499   * @retval None
00500   */
00501 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
00502 {
00503   CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
00504 }
00505
00506 /**
00507   * @brief  Check if VDDUSB supply is enabled
00508   * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB
00509   * @retval State of bit (1 or 0).
00510   */
00511 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
00512 {
00513   return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
00514 }
00515 #endif /* STM32G0C1xx || STM32G0B1xx */
00516
00517 #if defined (PWR_PVM_SUPPORT)
00518 /**
00519   * @brief  Enable the Power Voltage Monitoring on a peripheral
00520   * @rmtoll CR2          PVMUSB         LL_PWR_EnablePVM
00521   * @param  PeriphVoltage This parameter can be one of the following values:
00522   *         @arg @ref LL_PWR_PVM_USB (*)
00523   *
00524   *         (*) value not defined in all devices
00525   * @retval None
00526   */
00527 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
00528 {
00529   SET_BIT(PWR->CR2, PeriphVoltage);
00530 }
00531
00532 /**
00533   * @brief  Disable the Power Voltage Monitoring on a peripheral
00534   * @rmtoll CR2          PVMUSB         LL_PWR_DisablePVM
00535   * @param  PeriphVoltage This parameter can be one of the following values:
00536   *         @arg @ref LL_PWR_PVM_USB (*)
00537   *
00538   *         (*) value not defined in all devices
00539   * @retval None
00540   */
00541 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
00542 {
00543   CLEAR_BIT(PWR->CR2, PeriphVoltage);
00544 }
00545
00546 /**
00547   * @brief  Check if Power Voltage Monitoring is enabled on a peripheral
00548   * @rmtoll CR2          PVMUSB         LL_PWR_IsEnabledPVM
00549   * @param  PeriphVoltage This parameter can be one of the following values:
00550   *         @arg @ref LL_PWR_PVM_USB (*)
00551   *
00552   *         (*) value not defined in all devices
00553   * @retval State of bit (1 or 0).
00554   */
00555 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
00556 {
00557   return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
00558 }
00559 #endif /* PWR_PVM_SUPPORT */
00560
00561 /**
00562   * @brief  Set Low-Power mode
00563   * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode
00564   * @param  LowPowerMode This parameter can be one of the following values:
00565   *         @arg @ref LL_PWR_MODE_STOP0
00566   *         @arg @ref LL_PWR_MODE_STOP1
00567   *         @arg @ref LL_PWR_MODE_STANDBY
00568   *         @arg @ref LL_PWR_MODE_SHUTDOWN
00569   * @retval None
00570   */
00571 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
00572 {
00573   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
00574 }
00575
00576 /**
00577   * @brief  Get Low-Power mode
00578   * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode
00579   * @retval Returned value can be one of the following values:
00580   *         @arg @ref LL_PWR_MODE_STOP0
00581   *         @arg @ref LL_PWR_MODE_STOP1
00582   *         @arg @ref LL_PWR_MODE_STANDBY
00583   *         @arg @ref LL_PWR_MODE_SHUTDOWN
00584   */
00585 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
00586 {
00587   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
00588 }
00589
00590 #if defined (PWR_CR2_PVDE)
00591 /**
00592   * @brief  Configure the high voltage threshold detected by the Power Voltage Detector
00593   * @rmtoll CR2          PLS           LL_PWR_SetPVDHighLevel
00594   * @param  PVDHighLevel This parameter can be one of the following values:
00595   *         @arg @ref LL_PWR_PVDHLEVEL_0
00596   *         @arg @ref LL_PWR_PVDHLEVEL_1
00597   *         @arg @ref LL_PWR_PVDHLEVEL_2
00598   *         @arg @ref LL_PWR_PVDHLEVEL_3
00599   *         @arg @ref LL_PWR_PVDHLEVEL_4
00600   *         @arg @ref LL_PWR_PVDHLEVEL_5
00601   *         @arg @ref LL_PWR_PVDHLEVEL_6
00602   *         @arg @ref LL_PWR_PVDHLEVEL_7
00603   * @retval None
00604   */
00605 __STATIC_INLINE void LL_PWR_SetPVDHighLevel(uint32_t PVDHighLevel)
00606 {
00607   MODIFY_REG(PWR->CR2, PWR_CR2_PVDRT, PVDHighLevel);
00608 }
00609
00610 /**
00611   * @brief  Get the voltage threshold detection
00612   * @rmtoll CR2          PLS           LL_PWR_GetPVDHighLevel
00613   * @retval Returned value can be one of the following values:
00614   *         @arg @ref LL_PWR_PVDHLEVEL_0
00615   *         @arg @ref LL_PWR_PVDHLEVEL_1
00616   *         @arg @ref LL_PWR_PVDHLEVEL_2
00617   *         @arg @ref LL_PWR_PVDHLEVEL_3
00618   *         @arg @ref LL_PWR_PVDHLEVEL_4
00619   *         @arg @ref LL_PWR_PVDHLEVEL_5
00620   *         @arg @ref LL_PWR_PVDHLEVEL_6
00621   *         @arg @ref LL_PWR_PVDHLEVEL_7
00622   */
00623 __STATIC_INLINE uint32_t LL_PWR_GetPVDHighLevel(void)
00624 {
00625   return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDRT));
00626 }
00627 /**
00628   * @brief  Configure the low voltage threshold detected by the Power Voltage Detector
00629   * @rmtoll CR2          PLS           LL_PWR_SetPVDLowLevel
00630   * @param  PVDLowLevel This parameter can be one of the following values:
00631   *         @arg @ref LL_PWR_PVDLLEVEL_0
00632   *         @arg @ref LL_PWR_PVDLLEVEL_1
00633   *         @arg @ref LL_PWR_PVDLLEVEL_2
00634   *         @arg @ref LL_PWR_PVDLLEVEL_3
00635   *         @arg @ref LL_PWR_PVDLLEVEL_4
00636   *         @arg @ref LL_PWR_PVDLLEVEL_5
00637   *         @arg @ref LL_PWR_PVDLLEVEL_6
00638   * @retval None
00639   */
00640 __STATIC_INLINE void LL_PWR_SetPVDLowLevel(uint32_t PVDLowLevel)
00641 {
00642   MODIFY_REG(PWR->CR2, PWR_CR2_PVDFT, PVDLowLevel);
00643 }
00644
00645 /**
00646   * @brief  Get the low voltage threshold detection
00647   * @rmtoll CR2          PLS           LL_PWR_GetPVDLowLevel
00648   * @retval Returned value can be one of the following values:
00649   *         @arg @ref LL_PWR_PVDLLEVEL_0
00650   *         @arg @ref LL_PWR_PVDLLEVEL_1
00651   *         @arg @ref LL_PWR_PVDLLEVEL_2
00652   *         @arg @ref LL_PWR_PVDLLEVEL_3
00653   *         @arg @ref LL_PWR_PVDLLEVEL_4
00654   *         @arg @ref LL_PWR_PVDLLEVEL_5
00655   *         @arg @ref LL_PWR_PVDLLEVEL_6
00656   */
00657 __STATIC_INLINE uint32_t LL_PWR_GetPVDLowLevel(void)
00658 {
00659   return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDFT));
00660 }
00661
00662 /**
00663   * @brief  Enable Power Voltage Detector
00664   * @rmtoll CR2          PVDE          LL_PWR_EnablePVD
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_PWR_EnablePVD(void)
00668 {
00669   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00670 }
00671
00672 /**
00673   * @brief  Disable Power Voltage Detector
00674   * @rmtoll CR2          PVDE          LL_PWR_DisablePVD
00675   * @retval None
00676   */
00677 __STATIC_INLINE void LL_PWR_DisablePVD(void)
00678 {
00679   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00680 }
00681
00682 /**
00683   * @brief  Check if Power Voltage Detector is enabled
00684   * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD
00685   * @retval State of bit (1 or 0).
00686   */
00687 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
00688 {
00689   return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
00690 }
00691 #endif /* PWR_CR2_PVDE */
00692
00693 /**
00694   * @brief  Enable Internal Wake-up line
00695   * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
00696   * @retval None
00697   */
00698 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
00699 {
00700   SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
00701 }
00702
00703 /**
00704   * @brief  Disable Internal Wake-up line
00705   * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU
00706   * @retval None
00707   */
00708 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
00709 {
00710   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
00711 }
00712
00713 /**
00714   * @brief  Check if Internal Wake-up line is enabled
00715   * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU
00716   * @retval State of bit (1 or 0).
00717   */
00718 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
00719 {
00720   return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
00721 }
00722
00723 /**
00724   * @brief  Enable pull-up and pull-down configuration
00725   * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg
00726   * @retval None
00727   */
00728 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
00729 {
00730   SET_BIT(PWR->CR3, PWR_CR3_APC);
00731 }
00732
00733 /**
00734   * @brief  Disable pull-up and pull-down configuration
00735   * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg
00736   * @retval None
00737   */
00738 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
00739 {
00740   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
00741 }
00742
00743 /**
00744   * @brief  Check if pull-up and pull-down configuration  is enabled
00745   * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg
00746   * @retval State of bit (1 or 0).
00747   */
00748 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
00749 {
00750   return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
00751 }
00752
00753 #if defined(PWR_CR3_RRS)
00754 /**
00755   * @brief  Enable SRAM content retention in Standby mode
00756   * @rmtoll CR3          RRS           LL_PWR_EnableSRAMRetention
00757   * @retval None
00758   */
00759 __STATIC_INLINE void LL_PWR_EnableSRAMRetention(void)
00760 {
00761   SET_BIT(PWR->CR3, PWR_CR3_RRS);
00762 }
00763
00764 /**
00765   * @brief  Disable SRAM content retention in Standby mode
00766   * @rmtoll CR3          RRS           LL_PWR_DisableSRAMRetention
00767   * @retval None
00768   */
00769 __STATIC_INLINE void LL_PWR_DisableSRAMRetention(void)
00770 {
00771   CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
00772 }
00773
00774 /**
00775   * @brief  Check if SRAM content retention in Standby mode is enabled
00776   * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAMRetention
00777   * @retval State of bit (1 or 0).
00778   */
00779 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAMRetention(void)
00780 {
00781   return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL);
00782 }
00783 #endif /* PWR_CR3_RRS */
00784
00785 #if defined(PWR_CR3_ENB_ULP)
00786 /**
00787   * @brief  Enable sampling mode of LPMMU reset block
00788   * @rmtoll CR3          ENB_ULP       LL_PWR_EnableLPMUResetSamplingMode
00789   * @retval None
00790   */
00791 __STATIC_INLINE void LL_PWR_EnableLPMUResetSamplingMode(void)
00792 {
00793   SET_BIT(PWR->CR3, PWR_CR3_ENB_ULP);
00794 }
00795
00796 /**
00797   * @brief  Disable sampling mode of LPMMU reset block
00798   * @rmtoll CR3          ENB_ULP       LL_PWR_DisableLPMUResetSamplingMode
00799   * @retval None
00800   */
00801 __STATIC_INLINE void LL_PWR_DisableLPMUResetSamplingMode(void)
00802 {
00803   CLEAR_BIT(PWR->CR3, PWR_CR3_ENB_ULP);
00804 }
00805
00806 /**
00807   * @brief  Check if sampling mode of LPMMU reset block
00808   * @rmtoll CR3          ENB_ULP       LL_PWR_IsEnableLPMUResetSamplingMode
00809   * @retval State of bit (1 or 0).
00810   */
00811 __STATIC_INLINE uint32_t LL_PWR_IsEnableLPMUResetSamplingMode(void)
00812 {
00813   return ((READ_BIT(PWR->CR3, PWR_CR3_ENB_ULP) == (PWR_CR3_ENB_ULP)) ? 1UL : 0UL);
00814 }
00815 #endif /* PWR_CR3_ENB_ULP */
00816
00817 /**
00818   * @brief  Enable the WakeUp PINx functionality
00819   * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\n
00820   *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\n
00821   *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\n
00822   *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\n
00823   *         CR3          EWUP5         LL_PWR_EnableWakeUpPin\n
00824   *         CR3          EWUP6         LL_PWR_EnableWakeUpPin
00825   * @param  WakeUpPin This parameter can be one of the following values:
00826   *         @arg @ref LL_PWR_WAKEUP_PIN1
00827   *         @arg @ref LL_PWR_WAKEUP_PIN2
00828   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00829   *         @arg @ref LL_PWR_WAKEUP_PIN4
00830   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00831   *         @arg @ref LL_PWR_WAKEUP_PIN6
00832   * @retval None
00833   * @note (*) availability depends on devices
00834   */
00835 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
00836 {
00837   SET_BIT(PWR->CR3, WakeUpPin);
00838 }
00839
00840 /**
00841   * @brief  Disable the WakeUp PINx functionality
00842   * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\n
00843   *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\n
00844   *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\n
00845   *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\n
00846   *         CR3          EWUP5         LL_PWR_DisableWakeUpPin\n
00847   *         CR3          EWUP6         LL_PWR_DisableWakeUpPin
00848   * @param  WakeUpPin This parameter can be one of the following values:
00849   *         @arg @ref LL_PWR_WAKEUP_PIN1
00850   *         @arg @ref LL_PWR_WAKEUP_PIN2
00851   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00852   *         @arg @ref LL_PWR_WAKEUP_PIN4
00853   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00854   *         @arg @ref LL_PWR_WAKEUP_PIN6
00855   * @retval None
00856   * @note (*) availability depends on devices
00857   */
00858 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
00859 {
00860   CLEAR_BIT(PWR->CR3, WakeUpPin);
00861 }
00862
00863 /**
00864   * @brief  Check if the WakeUp PINx functionality is enabled
00865   * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\n
00866   *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\n
00867   *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\n
00868   *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\n
00869   *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin\n
00870   *         CR3          EWUP6         LL_PWR_IsEnabledWakeUpPin
00871   * @param  WakeUpPin This parameter can be one of the following values:
00872   *         @arg @ref LL_PWR_WAKEUP_PIN1
00873   *         @arg @ref LL_PWR_WAKEUP_PIN2
00874   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00875   *         @arg @ref LL_PWR_WAKEUP_PIN4
00876   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00877   *         @arg @ref LL_PWR_WAKEUP_PIN6
00878   * @retval State of bit (1 or 0).
00879   * @note (*) availability depends on devices
00880   */
00881 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
00882 {
00883   return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
00884 }
00885
00886 /**
00887   * @brief  Set the resistor impedance
00888   * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor
00889   * @param  Resistor This parameter can be one of the following values:
00890   *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_5K
00891   *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_1_5K
00892   * @retval None
00893   */
00894 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
00895 {
00896   MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
00897 }
00898
00899 /**
00900   * @brief  Get the resistor impedance
00901   * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor
00902   * @retval Returned value can be one of the following values:
00903   *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_5K
00904   *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_1_5K
00905   */
00906 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
00907 {
00908   return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
00909 }
00910
00911 /**
00912   * @brief  Enable battery charging
00913   * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging
00914   * @retval None
00915   */
00916 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
00917 {
00918   SET_BIT(PWR->CR4, PWR_CR4_VBE);
00919 }
00920
00921 /**
00922   * @brief  Disable battery charging
00923   * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging
00924   * @retval None
00925   */
00926 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
00927 {
00928   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
00929 }
00930
00931 /**
00932   * @brief  Check if battery charging is enabled
00933   * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging
00934   * @retval State of bit (1 or 0).
00935   */
00936 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
00937 {
00938   return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
00939 }
00940
00941 /**
00942   * @brief  Set the Wake-Up pin polarity low for the event detection
00943   * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\n
00944   *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\n
00945   *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\n
00946   *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\n
00947   *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow\n
00948   *         CR4          WP6           LL_PWR_SetWakeUpPinPolarityLow
00949   * @param  WakeUpPin This parameter can be one of the following values:
00950   *         @arg @ref LL_PWR_WAKEUP_PIN1
00951   *         @arg @ref LL_PWR_WAKEUP_PIN2
00952   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00953   *         @arg @ref LL_PWR_WAKEUP_PIN4
00954   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00955   *         @arg @ref LL_PWR_WAKEUP_PIN6
00956   * @retval None
00957   * @note (*) availability depends on devices
00958   */
00959 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
00960 {
00961   SET_BIT(PWR->CR4, WakeUpPin);
00962 }
00963
00964 /**
00965   * @brief  Set the Wake-Up pin polarity high for the event detection
00966   * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\n
00967   *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\n
00968   *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\n
00969   *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\n
00970   *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh\n
00971   *         CR4          WP6           LL_PWR_SetWakeUpPinPolarityHigh
00972   * @param  WakeUpPin This parameter can be one of the following values:
00973   *         @arg @ref LL_PWR_WAKEUP_PIN1
00974   *         @arg @ref LL_PWR_WAKEUP_PIN2
00975   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00976   *         @arg @ref LL_PWR_WAKEUP_PIN4
00977   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00978   *         @arg @ref LL_PWR_WAKEUP_PIN6
00979   * @note (*) availability depends on devices
00980   * @retval None
00981   */
00982 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
00983 {
00984   CLEAR_BIT(PWR->CR4, WakeUpPin);
00985 }
00986
00987 /**
00988   * @brief  Get the Wake-Up pin polarity for the event detection
00989   * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\n
00990   *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\n
00991   *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\n
00992   *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\n
00993   *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow\n
00994   *         CR4          WP6           LL_PWR_IsWakeUpPinPolarityLow
00995   * @param  WakeUpPin This parameter can be one of the following values:
00996   *         @arg @ref LL_PWR_WAKEUP_PIN1
00997   *         @arg @ref LL_PWR_WAKEUP_PIN2
00998   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00999   *         @arg @ref LL_PWR_WAKEUP_PIN4
01000   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
01001   *         @arg @ref LL_PWR_WAKEUP_PIN6
01002   * @note (*) availability depends on devices
01003   * @retval State of bit (1 or 0).
01004   */
01005 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
01006 {
01007   return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
01008 }
01009
01010 /**
01011   * @brief  Enable GPIO pull-up state in Standby and Shutdown modes
01012   * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\n
01013   *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\n
01014   *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\n
01015   *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\n
01016   *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\n
01017   *         PUCRF        PU0-13        LL_PWR_EnableGPIOPullUp
01018   * @param  GPIO This parameter can be one of the following values:
01019   *         @arg @ref LL_PWR_GPIO_A
01020   *         @arg @ref LL_PWR_GPIO_B
01021   *         @arg @ref LL_PWR_GPIO_C
01022   *         @arg @ref LL_PWR_GPIO_D
01023   *         @arg @ref LL_PWR_GPIO_E (*)
01024   *         @arg @ref LL_PWR_GPIO_F
01025   * @param  GPIONumber This parameter can be one of the following values:
01026   *         @arg @ref LL_PWR_GPIO_BIT_0
01027   *         @arg @ref LL_PWR_GPIO_BIT_1
01028   *         @arg @ref LL_PWR_GPIO_BIT_2
01029   *         @arg @ref LL_PWR_GPIO_BIT_3
01030   *         @arg @ref LL_PWR_GPIO_BIT_4
01031   *         @arg @ref LL_PWR_GPIO_BIT_5
01032   *         @arg @ref LL_PWR_GPIO_BIT_6
01033   *         @arg @ref LL_PWR_GPIO_BIT_7
01034   *         @arg @ref LL_PWR_GPIO_BIT_8
01035   *         @arg @ref LL_PWR_GPIO_BIT_9
01036   *         @arg @ref LL_PWR_GPIO_BIT_10
01037   *         @arg @ref LL_PWR_GPIO_BIT_11
01038   *         @arg @ref LL_PWR_GPIO_BIT_12
01039   *         @arg @ref LL_PWR_GPIO_BIT_13
01040   *         @arg @ref LL_PWR_GPIO_BIT_14
01041   *         @arg @ref LL_PWR_GPIO_BIT_15
01042   * @retval None
01043   */
01044 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01045 {
01046   SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
01047 }
01048
01049 /**
01050   * @brief  Disable GPIO pull-up state in Standby and Shutdown modes
01051   * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\n
01052   *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\n
01053   *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\n
01054   *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\n
01055   *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\n
01056   *         PUCRF        PU0-13        LL_PWR_DisableGPIOPullUp
01057   * @param  GPIO This parameter can be one of the following values:
01058   *         @arg @ref LL_PWR_GPIO_A
01059   *         @arg @ref LL_PWR_GPIO_B
01060   *         @arg @ref LL_PWR_GPIO_C
01061   *         @arg @ref LL_PWR_GPIO_D
01062   *         @arg @ref LL_PWR_GPIO_E (*)
01063   *         @arg @ref LL_PWR_GPIO_F
01064   * @param  GPIONumber This parameter can be one of the following values:
01065   *         @arg @ref LL_PWR_GPIO_BIT_0
01066   *         @arg @ref LL_PWR_GPIO_BIT_1
01067   *         @arg @ref LL_PWR_GPIO_BIT_2
01068   *         @arg @ref LL_PWR_GPIO_BIT_3
01069   *         @arg @ref LL_PWR_GPIO_BIT_4
01070   *         @arg @ref LL_PWR_GPIO_BIT_5
01071   *         @arg @ref LL_PWR_GPIO_BIT_6
01072   *         @arg @ref LL_PWR_GPIO_BIT_7
01073   *         @arg @ref LL_PWR_GPIO_BIT_8
01074   *         @arg @ref LL_PWR_GPIO_BIT_9
01075   *         @arg @ref LL_PWR_GPIO_BIT_10
01076   *         @arg @ref LL_PWR_GPIO_BIT_11
01077   *         @arg @ref LL_PWR_GPIO_BIT_12
01078   *         @arg @ref LL_PWR_GPIO_BIT_13
01079   *         @arg @ref LL_PWR_GPIO_BIT_14
01080   *         @arg @ref LL_PWR_GPIO_BIT_15
01081   * @retval None
01082   */
01083 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01084 {
01085   CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
01086 }
01087
01088 /**
01089   * @brief  Check if GPIO pull-up state is enabled
01090   * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01091   *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01092   *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01093   *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01094   *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01095   *         PUCRF        PU0-13        LL_PWR_IsEnabledGPIOPullUp
01096   * @param  GPIO This parameter can be one of the following values:
01097   *         @arg @ref LL_PWR_GPIO_A
01098   *         @arg @ref LL_PWR_GPIO_B
01099   *         @arg @ref LL_PWR_GPIO_C
01100   *         @arg @ref LL_PWR_GPIO_D
01101   *         @arg @ref LL_PWR_GPIO_E (*)
01102   *         @arg @ref LL_PWR_GPIO_F
01103   * @param  GPIONumber This parameter can be one of the following values:
01104   *         @arg @ref LL_PWR_GPIO_BIT_0
01105   *         @arg @ref LL_PWR_GPIO_BIT_1
01106   *         @arg @ref LL_PWR_GPIO_BIT_2
01107   *         @arg @ref LL_PWR_GPIO_BIT_3
01108   *         @arg @ref LL_PWR_GPIO_BIT_4
01109   *         @arg @ref LL_PWR_GPIO_BIT_5
01110   *         @arg @ref LL_PWR_GPIO_BIT_6
01111   *         @arg @ref LL_PWR_GPIO_BIT_7
01112   *         @arg @ref LL_PWR_GPIO_BIT_8
01113   *         @arg @ref LL_PWR_GPIO_BIT_9
01114   *         @arg @ref LL_PWR_GPIO_BIT_10
01115   *         @arg @ref LL_PWR_GPIO_BIT_11
01116   *         @arg @ref LL_PWR_GPIO_BIT_12
01117   *         @arg @ref LL_PWR_GPIO_BIT_13
01118   *         @arg @ref LL_PWR_GPIO_BIT_14
01119   *         @arg @ref LL_PWR_GPIO_BIT_15
01120   * @retval State of bit (1 or 0).
01121   */
01122 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01123 {
01124   return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
01125 }
01126
01127 /**
01128   * @brief  Enable GPIO pull-down state in Standby and Shutdown modes
01129   * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\n
01130   *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\n
01131   *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\n
01132   *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\n
01133   *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\n
01134   *         PDCRF        PD0-13        LL_PWR_EnableGPIOPullDown
01135   * @param  GPIO This parameter can be one of the following values:
01136   *         @arg @ref LL_PWR_GPIO_A
01137   *         @arg @ref LL_PWR_GPIO_B
01138   *         @arg @ref LL_PWR_GPIO_C
01139   *         @arg @ref LL_PWR_GPIO_D
01140   *         @arg @ref LL_PWR_GPIO_E (*)
01141   *         @arg @ref LL_PWR_GPIO_F
01142   * @param  GPIONumber This parameter can be one of the following values:
01143   *         @arg @ref LL_PWR_GPIO_BIT_0
01144   *         @arg @ref LL_PWR_GPIO_BIT_1
01145   *         @arg @ref LL_PWR_GPIO_BIT_2
01146   *         @arg @ref LL_PWR_GPIO_BIT_3
01147   *         @arg @ref LL_PWR_GPIO_BIT_4
01148   *         @arg @ref LL_PWR_GPIO_BIT_5
01149   *         @arg @ref LL_PWR_GPIO_BIT_6
01150   *         @arg @ref LL_PWR_GPIO_BIT_7
01151   *         @arg @ref LL_PWR_GPIO_BIT_8
01152   *         @arg @ref LL_PWR_GPIO_BIT_9
01153   *         @arg @ref LL_PWR_GPIO_BIT_10
01154   *         @arg @ref LL_PWR_GPIO_BIT_11
01155   *         @arg @ref LL_PWR_GPIO_BIT_12
01156   *         @arg @ref LL_PWR_GPIO_BIT_13
01157   *         @arg @ref LL_PWR_GPIO_BIT_14
01158   *         @arg @ref LL_PWR_GPIO_BIT_15
01159   * @retval None
01160   */
01161 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01162 {
01163   SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
01164 }
01165
01166 /**
01167   * @brief  Disable GPIO pull-down state in Standby and Shutdown modes
01168   * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\n
01169   *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\n
01170   *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\n
01171   *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\n
01172   *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\n
01173   *         PDCRF        PD0-13        LL_PWR_DisableGPIOPullDown
01174   * @param  GPIO This parameter can be one of the following values:
01175   *         @arg @ref LL_PWR_GPIO_A
01176   *         @arg @ref LL_PWR_GPIO_B
01177   *         @arg @ref LL_PWR_GPIO_C
01178   *         @arg @ref LL_PWR_GPIO_D
01179   *         @arg @ref LL_PWR_GPIO_E (*)
01180   *         @arg @ref LL_PWR_GPIO_F
01181   * @param  GPIONumber This parameter can be one of the following values:
01182   *         @arg @ref LL_PWR_GPIO_BIT_0
01183   *         @arg @ref LL_PWR_GPIO_BIT_1
01184   *         @arg @ref LL_PWR_GPIO_BIT_2
01185   *         @arg @ref LL_PWR_GPIO_BIT_3
01186   *         @arg @ref LL_PWR_GPIO_BIT_4
01187   *         @arg @ref LL_PWR_GPIO_BIT_5
01188   *         @arg @ref LL_PWR_GPIO_BIT_6
01189   *         @arg @ref LL_PWR_GPIO_BIT_7
01190   *         @arg @ref LL_PWR_GPIO_BIT_8
01191   *         @arg @ref LL_PWR_GPIO_BIT_9
01192   *         @arg @ref LL_PWR_GPIO_BIT_10
01193   *         @arg @ref LL_PWR_GPIO_BIT_11
01194   *         @arg @ref LL_PWR_GPIO_BIT_12
01195   *         @arg @ref LL_PWR_GPIO_BIT_13
01196   *         @arg @ref LL_PWR_GPIO_BIT_14
01197   *         @arg @ref LL_PWR_GPIO_BIT_15
01198   * @retval None
01199   */
01200 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01201 {
01202   CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
01203 }
01204
01205 /**
01206   * @brief  Check if GPIO pull-down state is enabled
01207   * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01208   *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01209   *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01210   *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01211   *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01212   *         PDCRF        PD0-13        LL_PWR_IsEnabledGPIOPullDown
01213   * @param  GPIO This parameter can be one of the following values:
01214   *         @arg @ref LL_PWR_GPIO_A
01215   *         @arg @ref LL_PWR_GPIO_B
01216   *         @arg @ref LL_PWR_GPIO_C
01217   *         @arg @ref LL_PWR_GPIO_D
01218   *         @arg @ref LL_PWR_GPIO_E (*)
01219   *         @arg @ref LL_PWR_GPIO_F
01220   * @param  GPIONumber This parameter can be one of the following values:
01221   *         @arg @ref LL_PWR_GPIO_BIT_0
01222   *         @arg @ref LL_PWR_GPIO_BIT_1
01223   *         @arg @ref LL_PWR_GPIO_BIT_2
01224   *         @arg @ref LL_PWR_GPIO_BIT_3
01225   *         @arg @ref LL_PWR_GPIO_BIT_4
01226   *         @arg @ref LL_PWR_GPIO_BIT_5
01227   *         @arg @ref LL_PWR_GPIO_BIT_6
01228   *         @arg @ref LL_PWR_GPIO_BIT_7
01229   *         @arg @ref LL_PWR_GPIO_BIT_8
01230   *         @arg @ref LL_PWR_GPIO_BIT_9
01231   *         @arg @ref LL_PWR_GPIO_BIT_10
01232   *         @arg @ref LL_PWR_GPIO_BIT_11
01233   *         @arg @ref LL_PWR_GPIO_BIT_12
01234   *         @arg @ref LL_PWR_GPIO_BIT_13
01235   *         @arg @ref LL_PWR_GPIO_BIT_14
01236   *         @arg @ref LL_PWR_GPIO_BIT_15
01237   * @retval State of bit (1 or 0).
01238   */
01239 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01240 {
01241   return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
01242 }
01243
01244 /**
01245   * @}
01246   */
01247
01248 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
01249   * @{
01250   */
01251
01252 /**
01253   * @brief  Get Internal Wake-up line Flag
01254   * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU
01255   * @retval State of bit (1 or 0).
01256   */
01257 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
01258 {
01259   return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
01260 }
01261
01262 /**
01263   * @brief  Get Stand-By Flag
01264   * @rmtoll SR1          SBF           LL_PWR_IsActiveFlag_SB
01265   * @retval State of bit (1 or 0).
01266   */
01267 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
01268 {
01269   return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
01270 }
01271
01272 /**
01273   * @brief  Get Wake-up Flag 6
01274   * @rmtoll SR1          WUF6          LL_PWR_IsActiveFlag_WU6
01275   * @retval State of bit (1 or 0).
01276   */
01277 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
01278 {
01279   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL);
01280 }
01281
01282 #if defined(PWR_CR3_EWUP5)
01283 /**
01284   * @brief  Get Wake-up Flag 5
01285   * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5
01286   * @retval State of bit (1 or 0).
01287   */
01288 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
01289 {
01290   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
01291 }
01292 #endif /* PWR_CR3_EWUP5 */
01293
01294 /**
01295   * @brief  Get Wake-up Flag 4
01296   * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4
01297   * @retval State of bit (1 or 0).
01298   */
01299 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
01300 {
01301   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
01302 }
01303
01304 #if defined(PWR_CR3_EWUP3)
01305 /**
01306   * @brief  Get Wake-up Flag 3
01307   * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3
01308   * @retval State of bit (1 or 0).
01309   */
01310 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
01311 {
01312   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
01313 }
01314 #endif /* PWR_CR3_EWUP3 */
01315
01316 /**
01317   * @brief  Get Wake-up Flag 2
01318   * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2
01319   * @retval State of bit (1 or 0).
01320   */
01321 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
01322 {
01323   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
01324 }
01325
01326 /**
01327   * @brief  Get Wake-up Flag 1
01328   * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1
01329   * @retval State of bit (1 or 0).
01330   */
01331 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
01332 {
01333   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
01334 }
01335
01336 /**
01337   * @brief  Clear Stand-By Flag
01338   * @rmtoll SCR          CSBF          LL_PWR_ClearFlag_SB
01339   * @retval None
01340   */
01341 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
01342 {
01343   WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
01344 }
01345
01346 /**
01347   * @brief  Clear Wake-up Flags
01348   * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU
01349   * @retval None
01350   */
01351 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
01352 {
01353   WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
01354 }
01355
01356 /**
01357   * @brief  Clear Wake-up Flag 6
01358   * @rmtoll SCR          CWUF6         LL_PWR_ClearFlag_WU6
01359   * @retval None
01360   */
01361 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
01362 {
01363   WRITE_REG(PWR->SCR, PWR_SCR_CWUF6);
01364 }
01365
01366 #if defined(PWR_CR3_EWUP5)
01367 /**
01368   * @brief  Clear Wake-up Flag 5
01369   * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5
01370   * @retval None
01371   */
01372 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
01373 {
01374   WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
01375 }
01376 #endif /* PWR_CR3_EWUP5 */
01377
01378 /**
01379   * @brief  Clear Wake-up Flag 4
01380   * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4
01381   * @retval None
01382   */
01383 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
01384 {
01385   WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
01386 }
01387
01388 #if defined(PWR_CR3_EWUP3)
01389 /**
01390   * @brief  Clear Wake-up Flag 3
01391   * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3
01392   * @retval None
01393   */
01394 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
01395 {
01396   WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
01397 }
01398 #endif /* PWR_CR3_EWUP3 */
01399
01400 /**
01401   * @brief  Clear Wake-up Flag 2
01402   * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2
01403   * @retval None
01404   */
01405 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
01406 {
01407   WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
01408 }
01409
01410 /**
01411   * @brief  Clear Wake-up Flag 1
01412   * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1
01413   * @retval None
01414   */
01415 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
01416 {
01417   WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
01418 }
01419
01420 #if defined (PWR_PVM_SUPPORT)
01421 /**
01422   * @brief  Indicate whether VDD voltage is below or above the selected PVD
01423   *         threshold
01424   * @rmtoll SR2          PVDMO_USB          LL_PWR_IsActiveFlag_PVMOUSB
01425   * @retval State of bit (1 or 0).
01426   */
01427 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void)
01428 {
01429   return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_USB) == (PWR_SR2_PVMO_USB)) ? 1UL : 0UL);
01430 }
01431 #endif /* PWR_PVM_SUPPORT */
01432
01433 #if defined(PWR_SR2_PVDO)
01434 /**
01435   * @brief  Indicate whether VDD voltage is below or above the selected PVD
01436   *         threshold
01437   * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO
01438   * @retval State of bit (1 or 0).
01439   */
01440 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
01441 {
01442   return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
01443 }
01444 #endif /* PWR_SR2_PVDO */
01445
01446 /**
01447   * @brief  Indicate whether the regulator is ready in the selected voltage
01448   *         range or if its output voltage is still changing to the required
01449   *         voltage level
01450   * @note:  Take care, return value "0" means the regulator is ready.
01451   *         Return value "1" means the output voltage range is still changing.
01452   * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOS
01453   * @retval State of bit (1 or 0).
01454   */
01455 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
01456 {
01457   return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
01458 }
01459
01460 /**
01461   * @brief  Indicate whether the regulator is ready in main mode or is in
01462   *         low-power mode
01463   * @note:  Take care, return value "0" means regulator is ready in main mode
01464   *         Return value "1" means regulator is in low-power mode (LPR)
01465   * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF
01466   * @retval State of bit (1 or 0).
01467   */
01468 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
01469 {
01470   return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
01471 }
01472
01473 /**
01474   * @brief  Indicate whether or not the low-power regulator is ready
01475   * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS
01476   * @retval State of bit (1 or 0).
01477   */
01478 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
01479 {
01480   return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
01481 }
01482
01483 /**
01484   * @brief  Indicate whether or not the flash is ready to be accessed
01485   * @rmtoll SR2          FLASH_RDY     LL_PWR_IsActiveFlag_FLASH_RDY
01486   * @retval State of bit (1 or 0).
01487   */
01488 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void)
01489 {
01490   return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL);
01491 }
01492
01493
01494 /**
01495   * @}
01496   */
01497
01498 #if defined(USE_FULL_LL_DRIVER)
01499 /** @defgroup PWR_LL_EF_Init De-initialization function
01500   * @{
01501   */
01502 ErrorStatus LL_PWR_DeInit(void);
01503 /**
01504   * @}
01505   */
01506 #endif /* USE_FULL_LL_DRIVER */
01507
01508 /**
01509   * @}
01510   */
01511
01512 /**
01513   * @}
01514   */
01515
01516 #endif /* defined(PWR) */
01517
01518 /**
01519   * @}
01520   */
01521
01522 #ifdef __cplusplus
01523 }
01524 #endif
01525
01526 #endif /* STM32G0xx_LL_PWR_H */
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rcc.c Source File

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stm32g0xx_ll_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017 #if defined(USE_FULL_LL_DRIVER)
00018
00019 /* Includes ------------------------------------------------------------------*/
00020 #include "stm32g0xx_ll_rcc.h"
00021 #ifdef  USE_FULL_ASSERT
00022 #include "stm32_assert.h"
00023 #else
00024 #define assert_param(expr) ((void)0U)
00025 #endif /* USE_FULL_ASSERT */
00026 /** @addtogroup STM32G0xx_LL_Driver
00027   * @{
00028   */
00029
00030 #if defined(RCC)
00031
00032 /** @addtogroup RCC_LL
00033   * @{
00034   */
00035
00036 /* Private types -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private constants ---------------------------------------------------------*/
00039 /* Private macros ------------------------------------------------------------*/
00040 /** @addtogroup RCC_LL_Private_Macros
00041   * @{
00042   */
00043 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00044 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
00045                                                || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
00046                                                || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
00047 #elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
00048 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
00049                                                || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
00050 #else
00051 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)
00052 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00053
00054 #if defined(LPUART1) && defined(LPUART2)
00055 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) \
00056                                                 || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE))
00057 #elif defined(LPUART1)
00058 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__)   ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)
00059 #endif /* LPUART1 && LPUART2 */
00060
00061 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00062 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00063                                              || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
00064 #else
00065 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)   ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
00066 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00067
00068 #if defined(LPTIM1) || defined(LPTIM2)
00069 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
00070                                                || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
00071 #endif /* LPTIM1 || LPTIM2 */
00072
00073 #if defined(RNG)
00074 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
00075 #endif /* RNG */
00076
00077 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
00078
00079 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00080 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
00081                                              || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
00082 #else
00083 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
00084 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00085
00086 #if defined(CEC)
00087 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
00088 #endif /* CEC */
00089
00090 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00091 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
00092 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00093
00094 #if defined(FDCAN1) || defined(FDCAN2)
00095 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
00096 #endif /* FDCAN1 || FDCAN2 */
00097
00098 #if defined(RCC_CCIPR_TIM1SEL) && defined(RCC_CCIPR_TIM15SEL)
00099 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
00100                                                || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE))
00101 #elif defined(RCC_CCIPR_TIM1SEL)
00102 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
00103 #endif /* RCC_CCIPR_TIM1SEL */
00104
00105
00106
00107 /**
00108   * @}
00109   */
00110
00111 /* Private function prototypes -----------------------------------------------*/
00112 /** @defgroup RCC_LL_Private_Functions RCC Private functions
00113   * @{
00114   */
00115 static uint32_t RCC_GetSystemClockFreq(void);
00116 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
00117 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
00118 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
00119 static uint32_t RCC_PLL_GetFreqDomain_ADC(void);
00120 static uint32_t RCC_PLL_GetFreqDomain_I2S1(void);
00121 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00122 static uint32_t RCC_PLL_GetFreqDomain_I2S2(void);
00123 static uint32_t RCC_PLL_GetFreqDomain_USB(void);
00124 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00125 #if defined(FDCAN1) || defined(FDCAN2)
00126 static uint32_t RCC_PLL_GetFreqDomain_FDCAN(void);
00127 #endif /* FDCAN1 || FDCAN2 */
00128 #if defined(RNG)
00129 static uint32_t RCC_PLL_GetFreqDomain_RNG(void);
00130 #endif /* RNG */
00131 #if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL)
00132 static uint32_t RCC_PLL_GetFreqDomain_TIM1(void);
00133 #endif /* RCC_PLLQ_SUPPORT && RCC_CCIPR_TIM1SEL */
00134 #if defined(RCC_CCIPR_TIM15SEL)
00135 static uint32_t RCC_PLL_GetFreqDomain_TIM15(void);
00136 #endif /* RCC_CCIPR_TIM15SEL */
00137 /**
00138   * @}
00139   */
00140
00141
00142 /* Exported functions --------------------------------------------------------*/
00143 /** @addtogroup RCC_LL_Exported_Functions
00144   * @{
00145   */
00146
00147 /** @addtogroup RCC_LL_EF_Init
00148   * @{
00149   */
00150
00151 /**
00152   * @brief  Reset the RCC clock configuration to the default reset state.
00153   * @note   The default reset state of the clock configuration is given below:
00154   *         - HSI ON and used as system clock source
00155   *         - HSE and PLL OFF
00156   *         - AHB and APB1 prescaler set to 1.
00157   *         - CSS, MCO OFF
00158   *         - All interrupts disabled
00159   * @note   This function does not modify the configuration of the
00160   *         - Peripheral clocks
00161   *         - LSI, LSE and RTC clocks
00162   * @retval An ErrorStatus enumeration value:
00163   *          - SUCCESS: RCC registers are de-initialized
00164   *          - ERROR: not applicable
00165   */
00166 ErrorStatus LL_RCC_DeInit(void)
00167 {
00168   /* Set HSION bit and wait for HSI READY bit */
00169   LL_RCC_HSI_Enable();
00170   while (LL_RCC_HSI_IsReady() != 1U)
00171   {}
00172
00173   /* Set HSITRIM bits to reset value*/
00174   LL_RCC_HSI_SetCalibTrimming(0x40U);
00175
00176   /* Reset CFGR register */
00177   LL_RCC_WriteReg(CFGR, 0x00000000U);
00178
00179   /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */
00180   LL_RCC_WriteReg(CR, RCC_CR_HSION);
00181   while (LL_RCC_HSE_IsReady() != 0U)
00182   {}
00183   LL_RCC_WriteReg(CR, RCC_CR_HSION);
00184
00185   /* Wait for PLL READY bit to be reset */
00186   while (LL_RCC_PLL_IsReady() != 0U)
00187   {}
00188
00189   /* Reset PLLCFGR register */
00190   LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
00191
00192   /* Disable all interrupts */
00193   LL_RCC_WriteReg(CIER, 0x00000000U);
00194
00195   /* Clear all interrupts flags */
00196   LL_RCC_WriteReg(CICR, 0xFFFFFFFFU);
00197
00198   return SUCCESS;
00199 }
00200
00201 /**
00202   * @}
00203   */
00204
00205 /** @addtogroup RCC_LL_EF_Get_Freq
00206   * @brief  Return the frequencies of different on chip clocks;  System, AHB and APB1 buses clocks
00207   *         and different peripheral clocks available on the device.
00208   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE divided by HSI division factor(**)
00209   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
00210   * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
00211   *         or HSI_VALUE(**) multiplied/divided by the PLL factors.
00212   * @note   (**) HSI_VALUE is a constant defined in this file (default value
00213   *              16 MHz) but the real value may vary depending on the variations
00214   *              in voltage and temperature.
00215   * @note   (***) HSE_VALUE is a constant defined in this file (default value
00216   *               8 MHz), user has to ensure that HSE_VALUE is same as the real
00217   *               frequency of the crystal used. Otherwise, this function may
00218   *               have wrong result.
00219   * @note   The result of this function could be incorrect when using fractional
00220   *         value for HSE crystal.
00221   * @note   This function can be used by the user application to compute the
00222   *         baud-rate for the communication peripherals or configure other parameters.
00223   * @{
00224   */
00225
00226 /**
00227   * @brief  Return the frequencies of different on chip clocks;  System, AHB and APB1 buses clocks
00228   * @note   Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function
00229   *         must be called to update structure fields. Otherwise, any
00230   *         configuration based on this function will be incorrect.
00231   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
00232   * @retval None
00233   */
00234 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
00235 {
00236   /* Get SYSCLK frequency */
00237   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
00238
00239   /* HCLK clock frequency */
00240   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
00241
00242   /* PCLK1 clock frequency */
00243   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
00244 }
00245
00246 /**
00247   * @brief  Return USARTx clock frequency
00248   * @param  USARTxSource This parameter can be one of the following values:
00249   *         @arg @ref LL_RCC_USART1_CLKSOURCE
00250   *         @arg @ref LL_RCC_USART2_CLKSOURCE
00251   *         @arg @ref LL_RCC_USART3_CLKSOURCE
00252   * @retval USART clock frequency (in Hz)
00253   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00254   */
00255 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
00256 {
00257   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00258
00259   /* Check parameter */
00260   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
00261
00262   if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
00263   {
00264     /* USART1CLK clock frequency */
00265     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00266     {
00267       case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
00268         usart_frequency = RCC_GetSystemClockFreq();
00269         break;
00270
00271       case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
00272         if (LL_RCC_HSI_IsReady() == 1U)
00273         {
00274           usart_frequency = HSI_VALUE;
00275         }
00276         break;
00277
00278       case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
00279         if (LL_RCC_LSE_IsReady() == 1U)
00280         {
00281           usart_frequency = LSE_VALUE;
00282         }
00283         break;
00284
00285       case LL_RCC_USART1_CLKSOURCE_PCLK1:  /* USART1 Clock is PCLK1 */
00286       default:
00287         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00288         break;
00289     }
00290   }
00291 #if defined(RCC_CCIPR_USART2SEL)
00292   else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
00293   {
00294     /* USART2CLK clock frequency */
00295     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00296     {
00297       case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
00298         usart_frequency = RCC_GetSystemClockFreq();
00299         break;
00300
00301       case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
00302         if (LL_RCC_HSI_IsReady() == 1U)
00303         {
00304           usart_frequency = HSI_VALUE;
00305         }
00306         break;
00307
00308       case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
00309         if (LL_RCC_LSE_IsReady() == 1U)
00310         {
00311           usart_frequency = LSE_VALUE;
00312         }
00313         break;
00314
00315       case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
00316       default:
00317         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00318         break;
00319     }
00320   }
00321 #endif /* RCC_CCIPR_USART2SEL */
00322 #if defined(RCC_CCIPR_USART3SEL)
00323   else if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
00324   {
00325     /* USART3CLK clock frequency */
00326     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00327     {
00328       case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
00329         usart_frequency = RCC_GetSystemClockFreq();
00330         break;
00331
00332       case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
00333         if (LL_RCC_HSI_IsReady() == 1U)
00334         {
00335           usart_frequency = HSI_VALUE;
00336         }
00337         break;
00338
00339       case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
00340         if (LL_RCC_LSE_IsReady() == 1U)
00341         {
00342           usart_frequency = LSE_VALUE;
00343         }
00344         break;
00345
00346       case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
00347       default:
00348         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00349         break;
00350     }
00351   }
00352 #endif /* RCC_CCIPR_USART3SEL */
00353   else
00354   {
00355     /* nothing to do */
00356   }
00357   return usart_frequency;
00358 }
00359
00360 /**
00361   * @brief  Return I2Cx clock frequency
00362   * @param  I2CxSource This parameter can be one of the following values:
00363   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
00364   * @retval I2C clock frequency (in Hz)
00365   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
00366   */
00367 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
00368 {
00369   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00370
00371   /* Check parameter */
00372   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
00373
00374   if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
00375   {
00376     /* I2C1 CLK clock frequency */
00377     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00378     {
00379       case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
00380         i2c_frequency = RCC_GetSystemClockFreq();
00381         break;
00382
00383       case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
00384         if (LL_RCC_HSI_IsReady() == 1U)
00385         {
00386           i2c_frequency = HSI_VALUE;
00387         }
00388         break;
00389
00390       case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
00391       default:
00392         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00393         break;
00394     }
00395   }
00396 #if defined(RCC_CCIPR_I2C2SEL)
00397   else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
00398   {
00399     /* I2C2 CLK clock frequency */
00400     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00401     {
00402       case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
00403         i2c_frequency = RCC_GetSystemClockFreq();
00404         break;
00405
00406       case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
00407         if (LL_RCC_HSI_IsReady() == 1U)
00408         {
00409           i2c_frequency = HSI_VALUE;
00410         }
00411         break;
00412
00413       case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */
00414       default:
00415         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00416         break;
00417     }
00418   }
00419 #endif /* RCC_CCIPR_I2C2SEL */
00420   else
00421   {
00422     /* nothing to do */
00423   }
00424
00425   return i2c_frequency;
00426 }
00427
00428 /**
00429   * @brief  Return I2Sx clock frequency
00430   * @param  I2SxSource This parameter can be one of the following values:
00431   *         @arg @ref LL_RCC_I2S1_CLKSOURCE
00432   * @retval I2S clock frequency (in Hz)
00433   *         @arg @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
00434   */
00435 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
00436 {
00437   uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00438
00439   /* Check parameter */
00440   assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
00441
00442   if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
00443   {
00444     /* I2S1 CLK clock frequency */
00445     switch (LL_RCC_GetI2SClockSource(I2SxSource))
00446     {
00447       case LL_RCC_I2S1_CLKSOURCE_HSI:    /* I2S1 Clock is HSI */
00448         i2s_frequency = HSI_VALUE;
00449         break;
00450
00451       case LL_RCC_I2S1_CLKSOURCE_PLL:    /* I2S1 Clock is PLL"P" */
00452         if (LL_RCC_PLL_IsReady() == 1U)
00453         {
00454          if (LL_RCC_PLL_IsEnabledDomain_I2S1() == 1U)
00455          {
00456            i2s_frequency = RCC_PLL_GetFreqDomain_I2S1();
00457          }
00458         }
00459         break;
00460
00461
00462       case LL_RCC_I2S1_CLKSOURCE_PIN:          /* I2S1 Clock is External clock */
00463         i2s_frequency = EXTERNAL_CLOCK_VALUE;
00464         break;
00465
00466       case LL_RCC_I2S1_CLKSOURCE_SYSCLK: /* I2S1 Clock is System Clock */
00467       default:
00468         i2s_frequency = RCC_GetSystemClockFreq();
00469         break;
00470     }
00471   }
00472 #if defined(RCC_CCIPR2_I2S2SEL)
00473   else if (I2SxSource == LL_RCC_I2S2_CLKSOURCE)
00474   {
00475     /* I2S2 CLK clock frequency */
00476     switch (LL_RCC_GetI2SClockSource(I2SxSource))
00477     {
00478       case LL_RCC_I2S2_CLKSOURCE_HSI:    /* I2S2 Clock is HSI */
00479         i2s_frequency = HSI_VALUE;
00480         break;
00481
00482       case LL_RCC_I2S2_CLKSOURCE_PLL:    /* I2S2 Clock is PLL"P" */
00483         if (LL_RCC_PLL_IsReady() == 1U)
00484         {
00485          if (LL_RCC_PLL_IsEnabledDomain_I2S2() == 1U)
00486          {
00487            i2s_frequency = RCC_PLL_GetFreqDomain_I2S2();
00488          }
00489         }
00490         break;
00491
00492       case LL_RCC_I2S2_CLKSOURCE_PIN:          /* I2S2 Clock is External clock */
00493         i2s_frequency = EXTERNAL_CLOCK_VALUE;
00494         break;
00495
00496       case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /* I2S2 Clock is System Clock */
00497       default:
00498         i2s_frequency = RCC_GetSystemClockFreq();
00499         break;
00500     }
00501   }
00502 #endif /* RCC_CCIPR2_I2S2SEL */
00503   else
00504   {
00505   }
00506   return i2s_frequency;
00507 }
00508
00509 #if defined(LPUART1) || defined(LPUART2)
00510 /**
00511   * @brief  Return LPUARTx clock frequency
00512   * @param  LPUARTxSource This parameter can be one of the following values:
00513   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
00514   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE (*)
00515   * @retval LPUART clock frequency (in Hz)
00516   *         @arg @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00517   * (*) feature not available on all devices
00518   */
00519 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
00520 {
00521   uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00522
00523   /* Check parameter */
00524   assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
00525
00526   if (LPUARTxSource == LL_RCC_LPUART1_CLKSOURCE)
00527   {
00528     /* LPUART1CLK clock frequency */
00529     switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
00530     {
00531       case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
00532         lpuart_frequency = RCC_GetSystemClockFreq();
00533         break;
00534
00535       case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
00536         if (LL_RCC_HSI_IsReady() == 1U)
00537         {
00538           lpuart_frequency = HSI_VALUE;
00539         }
00540         break;
00541
00542       case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
00543         if (LL_RCC_LSE_IsReady() == 1U)
00544         {
00545           lpuart_frequency = LSE_VALUE;
00546         }
00547         break;
00548
00549       case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
00550       default:
00551         lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00552         break;
00553     }
00554   }
00555 #if defined(LPUART2)
00556   else if (LPUARTxSource == LL_RCC_LPUART2_CLKSOURCE)
00557   {
00558     /* LPUART2CLK clock frequency */
00559     switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
00560     {
00561       case LL_RCC_LPUART2_CLKSOURCE_SYSCLK: /* LPUART2 Clock is System Clock */
00562         lpuart_frequency = RCC_GetSystemClockFreq();
00563         break;
00564
00565       case LL_RCC_LPUART2_CLKSOURCE_HSI:    /* LPUART2 Clock is HSI Osc. */
00566         if (LL_RCC_HSI_IsReady() == 1U)
00567         {
00568           lpuart_frequency = HSI_VALUE;
00569         }
00570         break;
00571
00572       case LL_RCC_LPUART2_CLKSOURCE_LSE:    /* LPUART2 Clock is LSE Osc. */
00573         if (LL_RCC_LSE_IsReady() == 1U)
00574         {
00575           lpuart_frequency = LSE_VALUE;
00576         }
00577         break;
00578
00579       case LL_RCC_LPUART2_CLKSOURCE_PCLK1:  /* LPUART2 Clock is PCLK1 */
00580       default:
00581         lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00582         break;
00583     }
00584   }
00585 #endif /* LPUART2 */
00586   else
00587   {
00588   }
00589
00590   return lpuart_frequency;
00591 }
00592 #endif /* LPUART1 */
00593
00594 #if defined(LPTIM1) && defined(LPTIM2)
00595 /**
00596   * @brief  Return LPTIMx clock frequency
00597   * @param  LPTIMxSource This parameter can be one of the following values:
00598   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
00599   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
00600   * @retval LPTIM clock frequency (in Hz)
00601   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
00602   */
00603 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
00604 {
00605   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00606
00607   /* Check parameter */
00608   assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
00609
00610   if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
00611   {
00612     /* LPTIM1CLK clock frequency */
00613     switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
00614     {
00615       case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
00616         if (LL_RCC_LSI_IsReady() == 1U)
00617         {
00618           lptim_frequency = LSI_VALUE;
00619         }
00620         break;
00621
00622       case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
00623         if (LL_RCC_HSI_IsReady() == 1U)
00624         {
00625           lptim_frequency = HSI_VALUE;
00626         }
00627         break;
00628
00629       case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
00630         if (LL_RCC_LSE_IsReady() == 1U)
00631         {
00632           lptim_frequency = LSE_VALUE;
00633         }
00634         break;
00635
00636       case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
00637       default:
00638         lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00639         break;
00640     }
00641   }
00642   else
00643   {
00644     /* LPTIM2CLK clock frequency */
00645     switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
00646     {
00647       case LL_RCC_LPTIM2_CLKSOURCE_LSI:    /* LPTIM2 Clock is LSI Osc. */
00648         if (LL_RCC_LSI_IsReady() == 1U)
00649         {
00650           lptim_frequency = LSI_VALUE;
00651         }
00652         break;
00653
00654       case LL_RCC_LPTIM2_CLKSOURCE_HSI:    /* LPTIM2 Clock is HSI Osc. */
00655         if (LL_RCC_HSI_IsReady() == 1U)
00656         {
00657           lptim_frequency = HSI_VALUE;
00658         }
00659         break;
00660
00661       case LL_RCC_LPTIM2_CLKSOURCE_LSE:    /* LPTIM2 Clock is LSE Osc. */
00662         if (LL_RCC_LSE_IsReady() == 1U)
00663         {
00664           lptim_frequency = LSE_VALUE;
00665         }
00666         break;
00667
00668       case LL_RCC_LPTIM2_CLKSOURCE_PCLK1:  /* LPTIM2 Clock is PCLK1 */
00669       default:
00670         lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00671         break;
00672     }
00673   }
00674
00675   return lptim_frequency;
00676 }
00677 #endif /* LPTIM1 && LPTIM2 */
00678
00679 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
00680 /**
00681   * @brief  Return TIMx clock frequency
00682   * @param  TIMxSource This parameter can be one of the following values:
00683   *         @arg @ref LL_RCC_TIM1_CLKSOURCE
00684   * @if defined(STM32G081xx)
00685   *         @arg @ref LL_RCC_TIM15_CLKSOURCE
00686   * @endif
00687   * @retval TIMx clock frequency (in Hz)
00688   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00689   */
00690 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
00691 {
00692   uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00693
00694   /* Check parameter */
00695   assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
00696
00697   if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
00698   {
00699     /* TIM1CLK clock frequency */
00700     switch (LL_RCC_GetTIMClockSource(TIMxSource))
00701     {
00702       case LL_RCC_TIM1_CLKSOURCE_PLL:    /* TIM1 Clock is PLLQ */
00703         if (LL_RCC_PLL_IsReady() == 1U)
00704         {
00705          if (LL_RCC_PLL_IsEnabledDomain_TIM1() == 1U)
00706          {
00707            tim_frequency = RCC_PLL_GetFreqDomain_TIM1();
00708          }
00709         }
00710         break;
00711
00712       case LL_RCC_TIM1_CLKSOURCE_PCLK1:  /* TIM1 Clock is PCLK1 */
00713       default:
00714         tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00715         break;
00716     }
00717   }
00718 #if defined(TIM15)
00719   else
00720   {
00721     if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
00722     {
00723       /* TIM15CLK clock frequency */
00724       switch (LL_RCC_GetTIMClockSource(TIMxSource))
00725       {
00726         case LL_RCC_TIM15_CLKSOURCE_PLL:    /* TIM1 Clock is PLLQ */
00727           if (LL_RCC_PLL_IsReady() == 1U)
00728           {
00729            if (LL_RCC_PLL_IsEnabledDomain_TIM15() == 1U)
00730            {
00731              tim_frequency = RCC_PLL_GetFreqDomain_TIM15();
00732            }
00733           }
00734           break;
00735
00736         case LL_RCC_TIM15_CLKSOURCE_PCLK1:  /* TIM15 Clock is PCLK1 */
00737         default:
00738           tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00739           break;
00740       }
00741     }
00742   }
00743 #endif /* TIM15 */
00744   return tim_frequency;
00745 }
00746 #endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */
00747
00748
00749 #if defined(RNG)
00750 /**
00751   * @brief  Return RNGx clock frequency
00752   * @param  RNGxSource This parameter can be one of the following values:
00753   *         @arg @ref LL_RCC_RNG_CLKSOURCE
00754   * @retval RNG clock frequency (in Hz)
00755   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready
00756   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00757   */
00758 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
00759 {
00760   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00761   uint32_t rngdiv;
00762
00763   /* Check parameter */
00764   assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
00765
00766   /* RNGCLK clock frequency */
00767   switch (LL_RCC_GetRNGClockSource(RNGxSource))
00768   {
00769     case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */
00770       if (LL_RCC_PLL_IsReady() == 1U)
00771       {
00772         if (LL_RCC_PLL_IsEnabledDomain_RNG() == 1U)
00773         {
00774           rng_frequency = RCC_PLL_GetFreqDomain_RNG();
00775           rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos));
00776           rng_frequency = (rng_frequency / rngdiv);
00777         }
00778       }
00779       break;
00780
00781     case LL_RCC_RNG_CLKSOURCE_HSI_DIV8:      /* HSI clock divided by 8 used as RNG clock source */
00782       rng_frequency = HSI_VALUE / 8U;
00783       rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos));
00784       rng_frequency = (rng_frequency / rngdiv);
00785       break;
00786     case LL_RCC_RNG_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as RNG clock source */
00787       rng_frequency = RCC_GetSystemClockFreq();
00788       rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos));
00789       rng_frequency = (rng_frequency / rngdiv);
00790       break;
00791
00792     case LL_RCC_RNG_CLKSOURCE_NONE:          /* No clock used as RNG clock source */
00793     default:
00794       rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00795       break;
00796
00797   }
00798
00799   return rng_frequency;
00800 }
00801 #endif /* RNG */
00802
00803 #if defined(CEC)
00804 /**
00805   * @brief  Return CEC clock frequency
00806   * @param  CECxSource This parameter can be one of the following values:
00807   *         @arg @ref LL_RCC_CEC_CLKSOURCE
00808   * @retval CEC clock frequency (in Hz)
00809   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00810   */
00811 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
00812 {
00813   uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00814
00815   /* Check parameter */
00816   assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
00817
00818   /* CECCLK clock frequency */
00819   switch (LL_RCC_GetCECClockSource(CECxSource))
00820   {
00821     case LL_RCC_CEC_CLKSOURCE_LSE:           /* CEC Clock is LSE Osc. */
00822       if (LL_RCC_LSE_IsReady() == 1U)
00823       {
00824         cec_frequency = LSE_VALUE;
00825       }
00826       break;
00827
00828     case LL_RCC_CEC_CLKSOURCE_HSI_DIV488:    /* CEC Clock is HSI Osc. */
00829     default:
00830       if (LL_RCC_HSI_IsReady() == 1U)
00831       {
00832         cec_frequency = (HSI_VALUE / 488U);
00833       }
00834       break;
00835   }
00836
00837   return cec_frequency;
00838 }
00839 #endif /* CEC */
00840
00841 #if defined(FDCAN1) || defined(FDCAN2)
00842 /**
00843   * @brief  Return FDCANx clock frequency
00844   * @param  FDCANxSource This parameter can be one of the following values:
00845   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
00846   * @retval FDCANx clock frequency (in Hz)
00847   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
00848   */
00849 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
00850 {
00851   uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00852
00853   /* Check parameter */
00854   assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
00855
00856   /* FDCANCLK clock frequency */
00857   switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
00858   {
00859     case LL_RCC_FDCAN_CLKSOURCE_PLL:    /* FDCAN Clock is PLL "Q"  Osc. */
00860       if (LL_RCC_PLL_IsReady() == 1U)
00861       {
00862         if (LL_RCC_PLL_IsEnabledDomain_FDCAN() == 1U)
00863         {
00864           fdcan_frequency = RCC_PLL_GetFreqDomain_FDCAN();
00865         }
00866       }
00867       break;
00868
00869     case LL_RCC_FDCAN_CLKSOURCE_HSE:    /* FDCAN Clock is HSE Osc. */
00870       if (LL_RCC_HSE_IsReady() == 1U)
00871       {
00872         fdcan_frequency = HSE_VALUE;
00873       }
00874       break;
00875
00876     case LL_RCC_FDCAN_CLKSOURCE_PCLK1:  /* FDCAN Clock is PCLK1 */
00877     default:
00878       fdcan_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00879       break;
00880   }
00881
00882   return fdcan_frequency;
00883 }
00884 #endif /* FDCAN1 || FDCAN2 */
00885
00886 /**
00887   * @brief  Return ADCx clock frequency
00888   * @param  ADCxSource This parameter can be one of the following values:
00889   *         @arg @ref LL_RCC_ADC_CLKSOURCE
00890   * @retval ADC clock frequency (in Hz)
00891   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready
00892   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00893   */
00894 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
00895 {
00896   uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00897
00898   /* Check parameter */
00899   assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
00900
00901   /* ADCCLK clock frequency */
00902   switch (LL_RCC_GetADCClockSource(ADCxSource))
00903   {
00904     case LL_RCC_ADC_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as ADC clock source */
00905       adc_frequency = RCC_GetSystemClockFreq();
00906       break;
00907     case LL_RCC_ADC_CLKSOURCE_HSI  :        /* HSI clock used as ADC clock source */
00908       adc_frequency = HSI_VALUE;
00909       break;
00910
00911     case LL_RCC_ADC_CLKSOURCE_PLL:         /* PLLP clock used as ADC clock source */
00912       if (LL_RCC_PLL_IsReady() == 1U)
00913       {
00914         if (LL_RCC_PLL_IsEnabledDomain_ADC() == 1U)
00915         {
00916           adc_frequency = RCC_PLL_GetFreqDomain_ADC();
00917         }
00918       }
00919       break;
00920     default:
00921       adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00922       break;
00923   }
00924
00925   return adc_frequency;
00926 }
00927
00928 /**
00929   * @brief  Return RTC clock frequency
00930   * @retval RTC clock frequency (in Hz)
00931   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
00932   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00933   */
00934 uint32_t LL_RCC_GetRTCClockFreq(void)
00935 {
00936   uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00937
00938   /* RTCCLK clock frequency */
00939   switch (LL_RCC_GetRTCClockSource())
00940   {
00941     case LL_RCC_RTC_CLKSOURCE_LSE:       /* LSE clock used as RTC clock source */
00942       if (LL_RCC_LSE_IsReady() == 1U)
00943       {
00944         rtc_frequency = LSE_VALUE;
00945       }
00946       break;
00947
00948     case LL_RCC_RTC_CLKSOURCE_LSI:       /* LSI clock used as RTC clock source */
00949       if (LL_RCC_LSI_IsReady() == 1U)
00950       {
00951         rtc_frequency = LSI_VALUE;
00952       }
00953       break;
00954
00955     case LL_RCC_RTC_CLKSOURCE_HSE_DIV32:        /* HSE clock used as ADC clock source */
00956       rtc_frequency = HSE_VALUE / 32U;
00957       break;
00958
00959     case LL_RCC_RTC_CLKSOURCE_NONE:          /* No clock used as RTC clock source */
00960     default:
00961       rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00962       break;
00963   }
00964
00965   return rtc_frequency;
00966 }
00967
00968 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00969 /**
00970   * @brief  Return USBx clock frequency
00971   * @param  USBxSource This parameter can be one of the following values:
00972   *         @arg @ref LL_RCC_USB_CLKSOURCE
00973   * @retval USB clock frequency (in Hz)
00974   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
00975   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00976   */
00977 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
00978 {
00979   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00980
00981   /* Check parameter */
00982   assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
00983
00984   /* USBCLK clock frequency */
00985   switch (LL_RCC_GetUSBClockSource(USBxSource))
00986   {
00987 #if defined(RCC_HSI48_SUPPORT)
00988     case LL_RCC_USB_CLKSOURCE_HSI48:         /* HSI48 used as USB clock source */
00989       if (LL_RCC_HSI48_IsReady() != 0U)
00990       {
00991         usb_frequency = HSI48_VALUE;
00992       }
00993       break;
00994 #endif /* RCC_HSI48_SUPPORT */
00995
00996     case LL_RCC_USB_CLKSOURCE_HSE:         /* HSE used as USB clock source */
00997       if (LL_RCC_HSE_IsReady() != 0U)
00998       {
00999         usb_frequency = HSE_VALUE;
01000       }
01001       break;
01002
01003     case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
01004       if (LL_RCC_PLL_IsReady() != 0U)
01005       {
01006         if (LL_RCC_PLL_IsEnabledDomain_USB() != 0U)
01007         {
01008           usb_frequency = RCC_PLL_GetFreqDomain_USB();
01009         }
01010       }
01011       break;
01012
01013     default:
01014       usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
01015       break;
01016   }
01017
01018   return usb_frequency;
01019 }
01020 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx) */
01021
01022 /**
01023   * @}
01024   */
01025
01026 /**
01027   * @}
01028   */
01029
01030 /** @addtogroup RCC_LL_Private_Functions
01031   * @{
01032   */
01033
01034 /**
01035   * @brief  Return SYSTEM clock frequency
01036   * @retval SYSTEM clock frequency (in Hz)
01037   */
01038 static uint32_t RCC_GetSystemClockFreq(void)
01039 {
01040   uint32_t frequency;
01041   uint32_t hsidiv;
01042
01043   /* Get SYSCLK source -------------------------------------------------------*/
01044   switch (LL_RCC_GetSysClkSource())
01045   {
01046     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
01047       frequency = HSE_VALUE;
01048       break;
01049
01050     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
01051       frequency = RCC_PLL_GetFreqDomain_SYS();
01052       break;
01053
01054     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
01055     default:
01056       hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
01057       frequency = (HSI_VALUE / hsidiv);
01058       break;
01059   }
01060
01061   return frequency;
01062 }
01063
01064 /**
01065   * @brief  Return HCLK clock frequency
01066   * @param  SYSCLK_Frequency SYSCLK clock frequency
01067   * @retval HCLK clock frequency (in Hz)
01068   */
01069 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
01070 {
01071   /* HCLK clock frequency */
01072   return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
01073 }
01074
01075 /**
01076   * @brief  Return PCLK1 clock frequency
01077   * @param  HCLK_Frequency HCLK clock frequency
01078   * @retval PCLK1 clock frequency (in Hz)
01079   */
01080 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
01081 {
01082   /* PCLK1 clock frequency */
01083   return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
01084 }
01085 /**
01086   * @brief  Return PLL clock frequency used for system domain
01087   * @retval PLL clock frequency (in Hz)
01088   */
01089 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
01090 {
01091   uint32_t pllinputfreq;
01092   uint32_t pllsource;
01093
01094   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01095      SYSCLK = PLL_VCO / PLLR
01096   */
01097   pllsource = LL_RCC_PLL_GetMainSource();
01098
01099   switch (pllsource)
01100   {
01101     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01102       pllinputfreq = HSI_VALUE;
01103       break;
01104
01105     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01106       pllinputfreq = HSE_VALUE;
01107       break;
01108
01109     default:
01110       pllinputfreq = HSI_VALUE;
01111       break;
01112   }
01113   return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01114                                    LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
01115 }
01116 /**
01117   * @brief  Return PLL clock frequency used for ADC domain
01118   * @retval PLL clock frequency (in Hz)
01119   */
01120 static uint32_t RCC_PLL_GetFreqDomain_ADC(void)
01121 {
01122   uint32_t pllinputfreq;
01123   uint32_t pllsource;
01124
01125   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01126      ADC Domain clock = PLL_VCO / PLLP
01127   */
01128   pllsource = LL_RCC_PLL_GetMainSource();
01129
01130   switch (pllsource)
01131   {
01132     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01133       pllinputfreq = HSE_VALUE;
01134       break;
01135
01136     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01137     default:
01138       pllinputfreq = HSI_VALUE;
01139       break;
01140   }
01141   return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01142                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
01143 }
01144
01145 #if defined(FDCAN1) || defined(FDCAN2)
01146 /**
01147   * @brief  Return PLL clock frequency used for FDCAN domain
01148   * @retval PLL clock frequency (in Hz)
01149   */
01150 static uint32_t RCC_PLL_GetFreqDomain_FDCAN(void)
01151 {
01152   uint32_t pllinputfreq;
01153   uint32_t pllsource;
01154
01155   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
01156
01157      FDCAN Domain clock = PLL_VCO / PLLQ
01158   */
01159   pllsource = LL_RCC_PLL_GetMainSource();
01160
01161   switch (pllsource)
01162   {
01163     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01164       pllinputfreq = HSE_VALUE;
01165       break;
01166
01167     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01168     default:
01169       pllinputfreq = HSI_VALUE;
01170       break;
01171   }
01172   return __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01173                                          LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
01174 }
01175 #endif /* FDCAN1 || FDCAN2 */
01176
01177 /**
01178   * @brief  Return PLL clock frequency used for I2S1 domain
01179   * @retval PLL clock frequency (in Hz)
01180   */
01181 static uint32_t RCC_PLL_GetFreqDomain_I2S1(void)
01182 {
01183   uint32_t pllinputfreq;
01184   uint32_t pllsource;
01185
01186   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01187      I2S1 Domain clock = PLL_VCO / PLLP
01188   */
01189   pllsource = LL_RCC_PLL_GetMainSource();
01190
01191   switch (pllsource)
01192   {
01193     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01194       pllinputfreq = HSE_VALUE;
01195       break;
01196
01197     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01198     default:
01199       pllinputfreq = HSI_VALUE;
01200       break;
01201   }
01202   return __LL_RCC_CALC_PLLCLK_I2S1_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01203                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
01204 }
01205
01206 #if defined(RCC_CCIPR2_I2S2SEL)
01207 /**
01208   * @brief  Return PLL clock frequency used for I2S2 domain
01209   * @retval PLL clock frequency (in Hz)
01210   */
01211 static uint32_t RCC_PLL_GetFreqDomain_I2S2(void)
01212 {
01213   uint32_t pllinputfreq;
01214   uint32_t pllsource;
01215
01216   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01217      I2S2 Domain clock = PLL_VCO / PLLP
01218   */
01219   pllsource = LL_RCC_PLL_GetMainSource();
01220
01221   switch (pllsource)
01222   {
01223     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01224       pllinputfreq = HSE_VALUE;
01225       break;
01226
01227     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01228     default:
01229       pllinputfreq = HSI_VALUE;
01230       break;
01231   }
01232   return __LL_RCC_CALC_PLLCLK_I2S2_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01233                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
01234 }
01235 #endif /* RCC_CCIPR2_I2S2SEL */
01236
01237 #if defined(RNG)
01238 /**
01239   * @brief  Return PLL clock frequency used for RNG domain
01240   * @retval PLL clock frequency (in Hz)
01241   */
01242 static uint32_t RCC_PLL_GetFreqDomain_RNG(void)
01243 {
01244   uint32_t pllinputfreq;
01245   uint32_t pllsource;
01246
01247   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
01248
01249      RNG Domain clock = PLL_VCO / PLLQ
01250   */
01251   pllsource = LL_RCC_PLL_GetMainSource();
01252
01253   switch (pllsource)
01254   {
01255     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01256       pllinputfreq = HSE_VALUE;
01257       break;
01258
01259     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01260     default:
01261       pllinputfreq = HSI_VALUE;
01262       break;
01263   }
01264   return __LL_RCC_CALC_PLLCLK_RNG_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01265                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
01266 }
01267 #endif /* RNG */
01268
01269 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
01270 /**
01271   * @brief  Return PLL clock frequency used for USB domain
01272   * @retval PLL clock frequency (in Hz)
01273   */
01274 static uint32_t RCC_PLL_GetFreqDomain_USB(void)
01275 {
01276   uint32_t pllinputfreq;
01277   uint32_t pllsource;
01278
01279   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
01280
01281      RNG Domain clock = PLL_VCO / PLLQ
01282   */
01283   pllsource = LL_RCC_PLL_GetMainSource();
01284
01285   switch (pllsource)
01286   {
01287     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01288       pllinputfreq = HSE_VALUE;
01289       break;
01290
01291     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01292     default:
01293       pllinputfreq = HSI_VALUE;
01294       break;
01295   }
01296   return __LL_RCC_CALC_PLLCLK_USB_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01297                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
01298 }
01299 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
01300
01301 #if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL)
01302 /**
01303   * @brief  Return PLL clock frequency used for TIM1 domain
01304   * @retval PLL clock frequency (in Hz)
01305   */
01306 static uint32_t RCC_PLL_GetFreqDomain_TIM1(void)
01307 {
01308   uint32_t pllinputfreq;
01309   uint32_t pllsource;
01310
01311   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
01312
01313      TIM1 Domain clock = PLL_VCO / PLLQ
01314   */
01315   pllsource = LL_RCC_PLL_GetMainSource();
01316
01317   switch (pllsource)
01318   {
01319     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01320       pllinputfreq = HSE_VALUE;
01321       break;
01322
01323     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01324     default:
01325       pllinputfreq = HSI_VALUE;
01326       break;
01327   }
01328   return __LL_RCC_CALC_PLLCLK_TIM1_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01329                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
01330 }
01331 #endif /* RCC_PLLQ_SUPPORT */
01332
01333 #if defined(RCC_CCIPR_TIM15SEL)
01334 /**
01335   * @brief  Return PLL clock frequency used for TIM15 domain
01336   * @retval PLL clock frequency (in Hz)
01337   */
01338 static uint32_t RCC_PLL_GetFreqDomain_TIM15(void)
01339 {
01340   uint32_t pllinputfreq;
01341   uint32_t pllsource;
01342
01343   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
01344
01345      TIM15 Domain clock = PLL_VCO / PLLQ
01346   */
01347   pllsource = LL_RCC_PLL_GetMainSource();
01348
01349   switch (pllsource)
01350   {
01351     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01352       pllinputfreq = HSE_VALUE;
01353       break;
01354
01355     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01356     default:
01357       pllinputfreq = HSI_VALUE;
01358       break;
01359   }
01360   return __LL_RCC_CALC_PLLCLK_TIM15_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01361                                          LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
01362 }
01363 #endif /* RCC_CCIPR_TIM15SEL */
01364 /**
01365   * @}
01366   */
01367
01368 /**
01369   * @}
01370   */
01371
01372 #endif /* RCC */
01373
01374 /**
01375   * @}
01376   */
01377
01378 #endif /* USE_FULL_LL_DRIVER */
01379
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STM32G0C1xx HAL User Manual: stm32g0xx_ll_rcc.h Source File

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stm32g0xx_ll_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_rcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file in
00013   * the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   ******************************************************************************
00016   */
00017
00018 /* Define to prevent recursive inclusion -------------------------------------*/
00019 #ifndef STM32G0xx_LL_RCC_H
00020 #define STM32G0xx_LL_RCC_H
00021
00022 #ifdef __cplusplus
00023 extern "C" {
00024 #endif
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32g0xx.h"
00028
00029 /** @addtogroup STM32G0xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined(RCC)
00034
00035 /** @defgroup RCC_LL RCC
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
00042   * @{
00043   */
00044
00045
00046 /**
00047   * @}
00048   */
00049
00050 /* Private constants ---------------------------------------------------------*/
00051 /* Private macros ------------------------------------------------------------*/
00052 #if defined(USE_FULL_LL_DRIVER)
00053 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
00054   * @{
00055   */
00056 /**
00057   * @}
00058   */
00059 #endif /*USE_FULL_LL_DRIVER*/
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 #if defined(USE_FULL_LL_DRIVER)
00063 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
00064   * @{
00065   */
00066
00067 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
00068   * @{
00069   */
00070
00071 /**
00072   * @brief  RCC Clocks Frequency Structure
00073   */
00074 typedef struct
00075 {
00076   uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
00077   uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
00078   uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
00079 } LL_RCC_ClocksTypeDef;
00080
00081 /**
00082   * @}
00083   */
00084
00085 /**
00086   * @}
00087   */
00088 #endif /* USE_FULL_LL_DRIVER */
00089
00090 /* Exported constants --------------------------------------------------------*/
00091 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
00092   * @{
00093   */
00094
00095 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
00096   * @brief    Defines used to adapt values of different oscillators
00097   * @note     These values could be modified in the user environment according to
00098   *           HW set-up.
00099   * @{
00100   */
00101 #if !defined  (HSE_VALUE)
00102 #define HSE_VALUE    8000000U   /*!< Value of the HSE oscillator in Hz */
00103 #endif /* HSE_VALUE */
00104
00105 #if !defined  (HSI_VALUE)
00106 #define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
00107 #endif /* HSI_VALUE */
00108
00109 #if !defined  (LSE_VALUE)
00110 #define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
00111 #endif /* LSE_VALUE */
00112
00113 #if !defined  (LSI_VALUE)
00114 #define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
00115 #endif /* LSI_VALUE */
00116 #if !defined  (EXTERNAL_CLOCK_VALUE)
00117 #define EXTERNAL_CLOCK_VALUE    48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */
00118 #endif /* EXTERNAL_CLOCK_VALUE */
00119
00120 #if defined(RCC_HSI48_SUPPORT)
00121 #if !defined  (HSI48_VALUE)
00122 #define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
00123 #endif /* HSI48_VALUE */
00124 #endif /* RCC_HSI48_SUPPORT */
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
00130   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
00131   * @{
00132   */
00133 #define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
00134 #define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
00135 #define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
00136 #define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
00137 #define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
00138 #define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
00139 #define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
00140 #if defined(RCC_HSI48_SUPPORT)
00141 #define LL_RCC_CICR_HSI48RDYC              RCC_CICR_HSI48RDYC   /*!< HSI48 Ready Interrupt Clear */
00142 #endif /* RCC_HSI48_SUPPORT */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
00148   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
00149   * @{
00150   */
00151 #define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */
00152 #define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
00153 #define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
00154 #if defined(RCC_HSI48_SUPPORT)
00155 #define LL_RCC_CIFR_HSI48RDYF              RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
00156 #endif /* RCC_HSI48_SUPPORT */
00157 #define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
00158 #define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
00159 #define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
00160 #define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
00161 #define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
00162 #define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF    /*!< OBL reset flag */
00163 #define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
00164 #define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
00165 #define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
00166 #define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
00167 #define LL_RCC_CSR_PWRRSTF                 RCC_CSR_PWRRSTF    /*!< BOR or POR/PDR reset flag */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup RCC_LL_EC_IT IT Defines
00173   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
00174   * @{
00175   */
00176 #define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
00177 #define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
00178 #define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
00179 #define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
00180 #define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
00181 #if defined(RCC_HSI48_SUPPORT)
00182 #define LL_RCC_CIER_HSI48RDYIE             RCC_CIER_HSI48RDYIE    /*!< HSI48 Ready Interrupt Enable */
00183 #endif /* RCC_HSI48_SUPPORT */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
00189   * @{
00190   */
00191 #define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving capability */
00192 #define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */
00193 #define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */
00194 #define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection
00200   * @{
00201   */
00202 #define LL_RCC_LSCO_CLKSOURCE_LSI          0x00000000U                 /*!< LSI selection for low speed clock  */
00203 #define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL            /*!< LSE selection for low speed clock  */
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
00209   * @{
00210   */
00211 #define LL_RCC_SYS_CLKSOURCE_HSI           0x00000000U                        /*!< HSI selection as system clock */
00212 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_0                      /*!< HSE selection as system clock */
00213 #define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_1                      /*!< PLL selection as system clock */
00214 #define LL_RCC_SYS_CLKSOURCE_LSI           (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)    /*!< LSI selection used as system clock */
00215 #define LL_RCC_SYS_CLKSOURCE_LSE           RCC_CFGR_SW_2                      /*!< LSE selection used as system clock */
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
00221   * @{
00222   */
00223 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    0x00000000U                         /*!< HSI used as system clock */
00224 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_0                      /*!< HSE used as system clock */
00225 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_1                      /*!< PLL used as system clock */
00226 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSI    (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)   /*!< LSI used as system clock */
00227 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSE    RCC_CFGR_SWS_2                      /*!< LSE used as system clock */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
00233   * @{
00234   */
00235 #define LL_RCC_SYSCLK_DIV_1                0x00000000U                                                             /*!< SYSCLK not divided */
00236 #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_3                                                         /*!< SYSCLK divided by 2 */
00237 #define LL_RCC_SYSCLK_DIV_4                (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)                                     /*!< SYSCLK divided by 4 */
00238 #define LL_RCC_SYSCLK_DIV_8                (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)                                     /*!< SYSCLK divided by 8 */
00239 #define LL_RCC_SYSCLK_DIV_16               (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)                   /*!< SYSCLK divided by 16 */
00240 #define LL_RCC_SYSCLK_DIV_64               (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)                                     /*!< SYSCLK divided by 64 */
00241 #define LL_RCC_SYSCLK_DIV_128              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)                   /*!< SYSCLK divided by 128 */
00242 #define LL_RCC_SYSCLK_DIV_256              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)                   /*!< SYSCLK divided by 256 */
00243 #define LL_RCC_SYSCLK_DIV_512              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
00249   * @{
00250   */
00251 #define LL_RCC_APB1_DIV_1                  0x00000000U                                           /*!< HCLK not divided */
00252 #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE_2                                       /*!< HCLK divided by 2 */
00253 #define LL_RCC_APB1_DIV_4                  (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)                   /*!< HCLK divided by 4 */
00254 #define LL_RCC_APB1_DIV_8                  (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)                   /*!< HCLK divided by 8 */
00255 #define LL_RCC_APB1_DIV_16                 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup RCC_LL_EC_HSI_DIV  HSI division factor
00261   * @{
00262   */
00263 #define LL_RCC_HSI_DIV_1                  0x00000000U                                /*!< HSI not divided */
00264 #define LL_RCC_HSI_DIV_2                  RCC_CR_HSIDIV_0                            /*!< HSI divided by 2 */
00265 #define LL_RCC_HSI_DIV_4                  RCC_CR_HSIDIV_1                            /*!< HSI divided by 4 */
00266 #define LL_RCC_HSI_DIV_8                  (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)        /*!< HSI divided by 8 */
00267 #define LL_RCC_HSI_DIV_16                 RCC_CR_HSIDIV_2                            /*!< HSI divided by 16 */
00268 #define LL_RCC_HSI_DIV_32                 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0)        /*!< HSI divided by 32 */
00269 #define LL_RCC_HSI_DIV_64                 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1)        /*!< HSI divided by 64 */
00270 #define LL_RCC_HSI_DIV_128                RCC_CR_HSIDIV                              /*!< HSI divided by 128 */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
00276   * @{
00277   */
00278 #define LL_RCC_MCO1SOURCE_NOCLOCK          0x00000000U                            /*!< MCO output disabled, no clock on MCO */
00279 #define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
00280 #if defined(RCC_HSI48_SUPPORT)
00281 #define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_1                      /*!< HSI48 selection as MCO1 source */
00282 #endif /* RCC_HSI48_SUPPORT */
00283 #define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
00284 #define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
00285 #define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< Main PLL selection as MCO1 source */
00286 #define LL_RCC_MCO1SOURCE_LSI              (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
00287 #define LL_RCC_MCO1SOURCE_LSE              (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
00288 #if defined(RCC_CFGR_MCOSEL_3)
00289 #define LL_RCC_MCO1SOURCE_PLLPCLK         RCC_CFGR_MCOSEL_3                       /*!< PLLPCLK selection as MCO1 source */
00290 #define LL_RCC_MCO1SOURCE_PLLQCLK         (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)   /*!< PLLQCLK selection as MCO1 source */
00291 #define LL_RCC_MCO1SOURCE_RTCCLK          (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)   /*!< RTCCLK selection as MCO1 source */
00292 #define LL_RCC_MCO1SOURCE_RTC_WKUP        (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */
00293 #endif /* RCC_CFGR_MCOSEL_3 */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
00299   * @{
00300   */
00301 #define LL_RCC_MCO1_DIV_1                  0x00000000U                                                 /*!< MCO1 not divided */
00302 #define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_0                                           /*!< MCO1 divided by 2 */
00303 #define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_1                                           /*!< MCO1 divided by 4 */
00304 #define LL_RCC_MCO1_DIV_8                  (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)                     /*!< MCO1 divided by 8 */
00305 #define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_2                                           /*!< MCO1 divided by 16 */
00306 #define LL_RCC_MCO1_DIV_32                 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)                     /*!< MCO1 divided by 32 */
00307 #define LL_RCC_MCO1_DIV_64                 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)                     /*!< MCO1 divided by 64 */
00308 #define LL_RCC_MCO1_DIV_128                (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */
00309 #if defined(RCC_CFGR_MCOPRE_3)
00310 #define LL_RCC_MCO1_DIV_256                 RCC_CFGR_MCOPRE_3                                           /*!< MCO divided by 256 */
00311 #define LL_RCC_MCO1_DIV_512                (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)                      /*!< MCO divided by 512 */
00312 #define LL_RCC_MCO1_DIV_1024               (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)                      /*!< MCO divided by 1024 */
00313 #endif /* RCC_CFGR_MCOPRE_3 */
00314 /**
00315   * @}
00316   */
00317
00318 #if defined(RCC_MCO2_SUPPORT)
00319 /** @defgroup RCC_LL_EC_MCO2SOURCE  MCO2 SOURCE selection
00320   * @{
00321   */
00322 #define LL_RCC_MCO2SOURCE_NOCLOCK          0x00000000U                                                    /*!< MCO output disabled, no clock on MCO */
00323 #define LL_RCC_MCO2SOURCE_SYSCLK           RCC_CFGR_MCO2SEL_0                                             /*!< SYSCLK selection as MCO2 source */
00324 #if defined(RCC_HSI48_SUPPORT)
00325 #define LL_RCC_MCO2SOURCE_HSI48            RCC_CFGR_MCO2SEL_1                                             /*!< HSI48 selection as MCO2 source */
00326 #endif /* RCC_HSI48_SUPPORT */
00327 #define LL_RCC_MCO2SOURCE_HSI              (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)                      /*!< HSI16 selection as MCO2 source */
00328 #define LL_RCC_MCO2SOURCE_HSE              RCC_CFGR_MCO2SEL_2                                             /*!< HSE selection as MCO2 source */
00329 #define LL_RCC_MCO2SOURCE_PLLCLK           (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0)                      /*!< Main PLL "R" clock selection as MCO2 source */
00330 #define LL_RCC_MCO2SOURCE_LSI              (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1)                      /*!< LSI selection as MCO2 source */
00331 #define LL_RCC_MCO2SOURCE_LSE              (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */
00332 #define LL_RCC_MCO2SOURCE_PLLPCLK          RCC_CFGR_MCO2SEL_3                                             /*!< PLL "P" clock selection as MCO2 source */
00333 #define LL_RCC_MCO2SOURCE_PLLQCLK          (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0)                      /*!< PLL "Q" clock  selection as MCO2 source */
00334 #define LL_RCC_MCO2SOURCE_RTCCLK           (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1)                      /*!< RTC Clock selection as MCO2 source */
00335 #define LL_RCC_MCO2SOURCE_RTC_WKUP         (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< RTC Wakeup timer selection as MCO2 source */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup RCC_LL_EC_MCO2_DIV  MCO2 prescaler
00341   * @{
00342   */
00343 #define LL_RCC_MCO2_DIV_1                  0x00000000U                                                    /*!< MCO2 not divided */
00344 #define LL_RCC_MCO2_DIV_2                  RCC_CFGR_MCO2PRE_0                                             /*!< MCO2 divided by 2 */
00345 #define LL_RCC_MCO2_DIV_4                  RCC_CFGR_MCO2PRE_1                                             /*!< MCO2 divided by 4 */
00346 #define LL_RCC_MCO2_DIV_8                  (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 8 */
00347 #define LL_RCC_MCO2_DIV_16                 RCC_CFGR_MCO2PRE_2                                             /*!< MCO2 divided by 16 */
00348 #define LL_RCC_MCO2_DIV_32                 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 32 */
00349 #define LL_RCC_MCO2_DIV_64                 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)                      /*!< MCO2 divided by 64 */
00350 #define LL_RCC_MCO2_DIV_128                (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */
00351 #define LL_RCC_MCO2_DIV_256                RCC_CFGR_MCO2PRE_3                                             /*!< MCO2 divided by 256 */
00352 #define LL_RCC_MCO2_DIV_512                (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 512 */
00353 #define LL_RCC_MCO2_DIV_1024               (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)                      /*!< MCO2 divided by 1024 */
00354 /**
00355   * @}
00356   */
00357 #endif /* RCC_MCO2_SUPPORT */
00358
00359 #if defined(USE_FULL_LL_DRIVER)
00360 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
00361   * @{
00362   */
00363 #define LL_RCC_PERIPH_FREQUENCY_NO        0x00000000U                 /*!< No clock enabled for the peripheral            */
00364 #define LL_RCC_PERIPH_FREQUENCY_NA        0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
00365 /**
00366   * @}
00367   */
00368 #endif /* USE_FULL_LL_DRIVER */
00369
00370 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
00371   * @{
00372   */
00373 #define LL_RCC_USART1_CLKSOURCE_PCLK1      ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U)            /*!< PCLK1 clock used as USART1 clock source */
00374 #define LL_RCC_USART1_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)  /*!< SYSCLK clock used as USART1 clock source */
00375 #define LL_RCC_USART1_CLKSOURCE_HSI        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)  /*!< HSI clock used as USART1 clock source */
00376 #define LL_RCC_USART1_CLKSOURCE_LSE        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)    /*!< LSE clock used as USART1 clock source */
00377 #define LL_RCC_USART2_CLKSOURCE_PCLK1      ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U)            /*!< PCLK1 clock used as USART2 clock source */
00378 #define LL_RCC_USART2_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)  /*!< SYSCLK clock used as USART2 clock source */
00379 #define LL_RCC_USART2_CLKSOURCE_HSI        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)  /*!< HSI clock used as USART2 clock source */
00380 #define LL_RCC_USART2_CLKSOURCE_LSE        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)    /*!< LSE clock used as USART2 clock source */
00381 #if defined(RCC_CCIPR_USART3SEL)
00382 #define LL_RCC_USART3_CLKSOURCE_PCLK1      ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U)           /*!< PCLK1 clock used as USART3 clock source */
00383 #define LL_RCC_USART3_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
00384 #define LL_RCC_USART3_CLKSOURCE_HSI        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
00385 #define LL_RCC_USART3_CLKSOURCE_LSE        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)   /*!< LSE clock used as USART3 clock source */
00386 #endif /* RCC_CCIPR_USART3SEL */
00387 /**
00388   * @}
00389   */
00390
00391 #if defined(LPUART1) || defined(LPUART2)
00392 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
00393   * @{
00394   */
00395 #if defined(LPUART2)
00396 #define LL_RCC_LPUART2_CLKSOURCE_PCLK1     ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U)              /*!< PCLK1 clock used as LPUART2 clock source */
00397 #define LL_RCC_LPUART2_CLKSOURCE_SYSCLK    ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0)  /*!< SYSCLK clock used as LPUART2 clock source */
00398 #define LL_RCC_LPUART2_CLKSOURCE_HSI       ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1)  /*!< HSI clock used as LPUART2 clock source */
00399 #define LL_RCC_LPUART2_CLKSOURCE_LSE       ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL)    /*!< LSE clock used as LPUART2 clock source */
00400 #endif /* LPUART2 */
00401 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1     ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U)              /*!< PCLK1 clock used as LPUART1 clock source */
00402 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0)   /*!< SYSCLK clock used as LPUART1 clock source */
00403 #define LL_RCC_LPUART1_CLKSOURCE_HSI       ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1)   /*!< HSI clock used as LPUART1 clock source */
00404 #define LL_RCC_LPUART1_CLKSOURCE_LSE       ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL)     /*!< LSE clock used as LPUART1 clock source */
00405 /**
00406   * @}
00407   */
00408 #endif /* LPUART1 || LPUART2 */
00409
00410 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
00411   * @{
00412   */
00413 #define LL_RCC_I2C1_CLKSOURCE_PCLK1        ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U)          /*!< PCLK1 clock used as I2C1 clock source */
00414 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK       ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0)  /*!< SYSCLK clock used as I2C1 clock source */
00415 #define LL_RCC_I2C1_CLKSOURCE_HSI          ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1)  /*!< HSI clock used as I2C1 clock source */
00416 #if defined(RCC_CCIPR_I2C2SEL)
00417 #define LL_RCC_I2C2_CLKSOURCE_PCLK1        ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U)          /*!< PCLK1 clock used as I2C2 clock source */
00418 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK       ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0)  /*!< SYSCLK clock used as I2C2 clock source */
00419 #define LL_RCC_I2C2_CLKSOURCE_HSI          ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1)  /*!< HSI clock used as I2C2 clock source */
00420 #endif /* RCC_CCIPR_I2C2SEL */
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup RCC_LL_EC_I2Sx_CLKSOURCE Peripheral I2S clock source selection
00426   * @{
00427   */
00428 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00429 #define LL_RCC_I2S1_CLKSOURCE_SYSCLK      ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U)          /*!< SYSCLK clock used as I2S1 clock source */
00430 #define LL_RCC_I2S1_CLKSOURCE_PLL         ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0)  /*!< PLL clock used as I2S1 clock source */
00431 #define LL_RCC_I2S1_CLKSOURCE_HSI         ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1)  /*!< HSI clock used as I2S1 clock source */
00432 #define LL_RCC_I2S1_CLKSOURCE_PIN         ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL)    /*!< External clock used as I2S1 clock source */
00433 #define LL_RCC_I2S2_CLKSOURCE_SYSCLK      ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U)          /*!< SYSCLK clock used as I2S2 clock source */
00434 #define LL_RCC_I2S2_CLKSOURCE_PLL         ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0)  /*!< PLL clock used as I2S2 clock source */
00435 #define LL_RCC_I2S2_CLKSOURCE_HSI         ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1)  /*!< HSI clock used as I2S2 clock source */
00436 #define LL_RCC_I2S2_CLKSOURCE_PIN         ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL)    /*!< External clock used as I2S2 clock source */
00437 #else
00438 #define LL_RCC_I2S1_CLKSOURCE_SYSCLK      0x00000000U                  /*!< SYSCLK clock used as I2S1 clock source */
00439 #define LL_RCC_I2S1_CLKSOURCE_PLL         RCC_CCIPR_I2S1SEL_0          /*!< PLL clock used as I2S1 clock source */
00440 #define LL_RCC_I2S1_CLKSOURCE_HSI         RCC_CCIPR_I2S1SEL_1          /*!< HSI clock used as I2S1 clock source */
00441 #define LL_RCC_I2S1_CLKSOURCE_PIN         RCC_CCIPR_I2S1SEL            /*!< External clock used as I2S1 clock source */
00442 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00443
00444 /**
00445   * @}
00446   */
00447
00448 #if defined(RCC_CCIPR_TIM1SEL)
00449 /** @defgroup RCC_LL_EC_TIMx_CLKSOURCE Peripheral TIM clock source selection
00450   * @{
00451   */
00452 #define LL_RCC_TIM1_CLKSOURCE_PCLK1        (RCC_CCIPR_TIM1SEL   | (0x00000000U >> 16U))          /*!< PCLK1 clock used as TIM1 clock source */
00453 #define LL_RCC_TIM1_CLKSOURCE_PLL          (RCC_CCIPR_TIM1SEL   | (RCC_CCIPR_TIM1SEL >> 16U))    /*!< PLL used as TIM1 clock source */
00454 /**
00455   * @}
00456   */
00457 #endif /* RCC_CCIPR_TIM1SEL */
00458
00459 #if defined(RCC_CCIPR_TIM15SEL)
00460 /** @addtogroup RCC_LL_EC_TIMx_CLKSOURCE
00461   * @{
00462   */
00463 #define LL_RCC_TIM15_CLKSOURCE_PCLK1       (RCC_CCIPR_TIM15SEL  | (0x00000000U >> 16U))          /*!< PCLK1 clock used as TIM15 clock source */
00464 #define LL_RCC_TIM15_CLKSOURCE_PLL         (RCC_CCIPR_TIM15SEL  | (RCC_CCIPR_TIM15SEL >> 16U))   /*!< PLL used as TIM15 clock source */
00465 /**
00466   * @}
00467   */
00468 #endif /* RCC_CCIPR_TIM15SEL */
00469
00470 #if defined(LPTIM1) && defined(LPTIM2)
00471 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
00472   * @{
00473   */
00474 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U))           /*!< PCLK1 selected as LPTIM1 clock */
00475 #define LL_RCC_LPTIM1_CLKSOURCE_LSI        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */
00476 #define LL_RCC_LPTIM1_CLKSOURCE_HSI        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI selected as LPTIM1 clock */
00477 #define LL_RCC_LPTIM1_CLKSOURCE_LSE        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U))   /*!< LSE selected as LPTIM1 clock */
00478 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1      (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U))           /*!< PCLK1 selected as LPTIM2 clock */
00479 #define LL_RCC_LPTIM2_CLKSOURCE_LSI        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI selected as LPTIM2 clock */
00480 #define LL_RCC_LPTIM2_CLKSOURCE_HSI        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI selected as LPTIM2 clock */
00481 #define LL_RCC_LPTIM2_CLKSOURCE_LSE        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U))   /*!< LSE selected as LPTIM2 clock */
00482 /**
00483   * @}
00484   */
00485 #endif /* LPTIM1 && LPTIM2*/
00486
00487 #if defined(CEC)
00488 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE_HSI Peripheral CEC clock source selection
00489   * @{
00490   */
00491 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488    0x00000000U                   /*!< HSI oscillator clock divided by 488 used as CEC clock */
00492 #define LL_RCC_CEC_CLKSOURCE_LSE           RCC_CCIPR_CECSEL              /*!< LSE oscillator clock used as CEC clock */
00493
00494 /**
00495   * @}
00496   */
00497 #endif /* CEC */
00498
00499 #if defined(FDCAN1) || defined(FDCAN2)
00500 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE_HSI Peripheral FDCAN clock source selection
00501   * @{
00502   */
00503 #define LL_RCC_FDCAN_CLKSOURCE_PCLK1         0x00000000U                   /*!< PCLK1 oscillator clock used as FDCAN clock */
00504 #define LL_RCC_FDCAN_CLKSOURCE_PLL           RCC_CCIPR2_FDCANSEL_0          /*!< PLL "Q"  oscillator clock used as FDCAN clock */
00505 #define LL_RCC_FDCAN_CLKSOURCE_HSE           RCC_CCIPR2_FDCANSEL_1          /*!< HSE oscillator clock used as FDCAN clock */
00506
00507 /**
00508   * @}
00509   */
00510 #endif /* FDCAN1 || FDCAN2 */
00511
00512 #if defined(RNG)
00513 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
00514   * @{
00515   */
00516 #define LL_RCC_RNG_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RNG clock */
00517 #define LL_RCC_RNG_CLKSOURCE_HSI_DIV8      RCC_CCIPR_RNGSEL_0            /*!< HSI oscillator clock divided by 8 used as RNG clock, available on cut2.0 */
00518 #define LL_RCC_RNG_CLKSOURCE_SYSCLK        RCC_CCIPR_RNGSEL_1            /*!< SYSCLK divided by 1 used as RNG clock */
00519 #define LL_RCC_RNG_CLKSOURCE_PLL           RCC_CCIPR_RNGSEL              /*!< PLL used as RNG clock */
00520 /**
00521   * @}
00522   */
00523 #endif /* RNG */
00524
00525 #if defined(RNG)
00526 /** @defgroup RCC_LL_EC_RNG_CLK_DIV Peripheral RNG clock division factor
00527   * @{
00528   */
00529 #define LL_RCC_RNG_CLK_DIV1                0x00000000U                    /*!< RNG clock not divided  */
00530 #define LL_RCC_RNG_CLK_DIV2                RCC_CCIPR_RNGDIV_0             /*!< RNG clock divided by 2 */
00531 #define LL_RCC_RNG_CLK_DIV4                RCC_CCIPR_RNGDIV_1             /*!< RNG clock divided by 4 */
00532 #define LL_RCC_RNG_CLK_DIV8                RCC_CCIPR_RNGDIV               /*!< RNG clock divided by 8 */
00533 /**
00534   * @}
00535   */
00536 #endif /* RNG */
00537
00538 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00539 /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
00540   * @{
00541   */
00542 #if defined(RCC_HSI48_SUPPORT)
00543 #define LL_RCC_USB_CLKSOURCE_HSI48         0x00000000U            /*!< HSI48 clock used as USB clock source */
00544 #endif /* RCC_HSI48_SUPPORT */
00545 #define LL_RCC_USB_CLKSOURCE_HSE           RCC_CCIPR2_USBSEL_0  /*!< PLL clock used as USB clock source */
00546 #define LL_RCC_USB_CLKSOURCE_PLL           RCC_CCIPR2_USBSEL_1  /*!< PLL clock used as USB clock source */
00547 /**
00548   * @}
00549   */
00550 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00551
00552 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
00553   * @{
00554   */
00555 #define LL_RCC_ADC_CLKSOURCE_SYSCLK        0x00000000U                   /*!< SYSCLK used as ADC clock */
00556 #define LL_RCC_ADC_CLKSOURCE_PLL           RCC_CCIPR_ADCSEL_0            /*!< PLL used as ADC clock */
00557 #define LL_RCC_ADC_CLKSOURCE_HSI           RCC_CCIPR_ADCSEL_1            /*!< HSI used as ADC clock */
00558 /**
00559   * @}
00560   */
00561
00562 /** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source
00563   * @{
00564   */
00565 #define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
00566 #define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
00567 #if defined(RCC_CCIPR_USART3SEL)
00568 #define LL_RCC_USART3_CLKSOURCE            RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
00569 #endif /* RCC_CCIPR_USART3SEL */
00570 /**
00571   * @}
00572   */
00573
00574 #if defined(LPUART1)
00575 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
00576   * @{
00577   */
00578 #define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
00579 #if defined(LPUART2)
00580 #define LL_RCC_LPUART2_CLKSOURCE           RCC_CCIPR_LPUART2SEL /*!< LPUART2 Clock source selection */
00581 #endif /* LPUART2 */
00582 /**
00583   * @}
00584   */
00585 #endif /* LPUART1 */
00586
00587 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
00588   * @{
00589   */
00590 #define LL_RCC_I2C1_CLKSOURCE              RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */
00591 #if defined(RCC_CCIPR_I2C2SEL)
00592 #define LL_RCC_I2C2_CLKSOURCE              RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */
00593 #endif /* RCC_CCIPR_I2C2SEL */
00594 /**
00595   * @}
00596   */
00597
00598 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
00599   * @{
00600   */
00601 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00602 #define LL_RCC_I2S1_CLKSOURCE              RCC_CCIPR2_I2S1SEL /*!< I2S1 Clock source selection */
00603 #define LL_RCC_I2S2_CLKSOURCE              RCC_CCIPR2_I2S2SEL /*!< I2S2 Clock source selection */
00604 #else
00605 #define LL_RCC_I2S1_CLKSOURCE              RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */
00606 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00607 /**
00608   * @}
00609   */
00610
00611 #if defined(RCC_CCIPR_TIM1SEL)
00612 /** @defgroup RCC_LL_EC_TIMx Peripheral TIMx get clock source
00613   * @{
00614   */
00615 #define LL_RCC_TIM1_CLKSOURCE              RCC_CCIPR_TIM1SEL   /*!< TIM1 Clock source selection */
00616 #if defined(RCC_CCIPR_TIM15SEL)
00617 #define LL_RCC_TIM15_CLKSOURCE             RCC_CCIPR_TIM15SEL  /*!< TIM15 Clock source selection */
00618 #endif /* RCC_CCIPR_TIM15SEL */
00619 /**
00620   * @}
00621   */
00622 #endif /* RCC_CCIPR_TIM1SEL */
00623
00624 #if defined(LPTIM1) && defined(LPTIM2)
00625 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
00626   * @{
00627   */
00628 #define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL /*!< LPTIM2 Clock source selection */
00629 #define LL_RCC_LPTIM2_CLKSOURCE            RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
00630 /**
00631   * @}
00632   */
00633 #endif /* LPTIM1 && LPTIM2 */
00634
00635 #if defined(CEC)
00636 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
00637   * @{
00638   */
00639 #define LL_RCC_CEC_CLKSOURCE               RCC_CCIPR_CECSEL        /*!< CEC Clock source selection */
00640 /**
00641   * @}
00642   */
00643 #endif /* CEC */
00644
00645 #if defined(FDCAN1) || defined(FDCAN2)
00646 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
00647   * @{
00648   */
00649 #define LL_RCC_FDCAN_CLKSOURCE               RCC_CCIPR2_FDCANSEL        /*!< FDCAN Clock source selection */
00650 /**
00651   * @}
00652   */
00653 #endif /* FDCAN1 */
00654
00655 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00656 /** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
00657   * @{
00658   */
00659 #define LL_RCC_USB_CLKSOURCE               RCC_CCIPR2_USBSEL /*!< USB Clock source selection */
00660 /**
00661   * @}
00662   */
00663 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00664
00665 #if defined(RNG)
00666 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
00667   * @{
00668   */
00669 #define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_RNGSEL        /*!< RNG Clock source selection */
00670 /**
00671   * @}
00672   */
00673
00674 /** @defgroup RCC_LL_EC_RNG_DIV Peripheral RNG get clock division factor
00675   * @{
00676   */
00677 #define LL_RCC_RNG_CLKDIV                  RCC_CCIPR_RNGDIV        /*!< RNG Clock division factor */
00678 /**
00679   * @}
00680   */
00681 #endif /* RNG */
00682
00683 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
00684   * @{
00685   */
00686 #define LL_RCC_ADC_CLKSOURCE               RCC_CCIPR_ADCSEL        /*!< ADC Clock source selection */
00687 /**
00688   * @}
00689   */
00690
00691 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
00692   * @{
00693   */
00694 #define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
00695 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
00696 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
00697 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
00698 /**
00699   * @}
00700   */
00701
00702
00703 /** @defgroup RCC_LL_EC_PLLSOURCE  PLL entry clock source
00704   * @{
00705   */
00706 #define LL_RCC_PLLSOURCE_NONE              0x00000000U             /*!< No clock */
00707 #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
00708 #define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
00709 /**
00710   * @}
00711   */
00712
00713 /** @defgroup RCC_LL_EC_PLLM_DIV  PLL division factor (PLLM)
00714   * @{
00715   */
00716 #define LL_RCC_PLLM_DIV_1                  0x00000000U                                 /*!< PLL division factor by 1 */
00717 #define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_0)                        /*!< PLL division factor by 2 */
00718 #define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1)                        /*!< PLL division factor by 3 */
00719 #define LL_RCC_PLLM_DIV_4                  ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 4 */
00720 #define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2)                        /*!< PLL division factor by 5 */
00721 #define LL_RCC_PLLM_DIV_6                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 6 */
00722 #define LL_RCC_PLLM_DIV_7                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL division factor by 7 */
00723 #define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM)                          /*!< PLL division factor by 8 */
00724 /**
00725   * @}
00726   */
00727
00728 /** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
00729   * @{
00730   */
00731 #define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_0)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
00732 #define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
00733 #define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
00734 #define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
00735 #define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
00736 #define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
00737 #define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
00743   * @{
00744   */
00745 #define LL_RCC_PLLP_DIV_2                  (RCC_PLLCFGR_PLLP_0)                                              /*!< Main PLL division factor for PLLP output by 2 */
00746 #define LL_RCC_PLLP_DIV_3                  (RCC_PLLCFGR_PLLP_1)                                              /*!< Main PLL division factor for PLLP output by 3 */
00747 #define LL_RCC_PLLP_DIV_4                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)                           /*!< Main PLL division factor for PLLP output by 4 */
00748 #define LL_RCC_PLLP_DIV_5                  (RCC_PLLCFGR_PLLP_2)                                              /*!< Main PLL division factor for PLLP output by 5 */
00749 #define LL_RCC_PLLP_DIV_6                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)                           /*!< Main PLL division factor for PLLP output by 6 */
00750 #define LL_RCC_PLLP_DIV_7                  (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)                           /*!< Main PLL division factor for PLLP output by 7 */
00751 #define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)        /*!< Main PLL division factor for PLLP output by 8 */
00752 #define LL_RCC_PLLP_DIV_9                  (RCC_PLLCFGR_PLLP_3)                                              /*!< Main PLL division factor for PLLP output by 9 */
00753 #define LL_RCC_PLLP_DIV_10                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 10 */
00754 #define LL_RCC_PLLP_DIV_11                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 11 */
00755 #define LL_RCC_PLLP_DIV_12                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 12 */
00756 #define LL_RCC_PLLP_DIV_13                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 13 */
00757 #define LL_RCC_PLLP_DIV_14                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 14 */
00758 #define LL_RCC_PLLP_DIV_15                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 15 */
00759 #define LL_RCC_PLLP_DIV_16                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
00760 #define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLP_4)                                              /*!< Main PLL division factor for PLLP output by 17 */
00761 #define LL_RCC_PLLP_DIV_18                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 18 */
00762 #define LL_RCC_PLLP_DIV_19                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 19 */
00763 #define LL_RCC_PLLP_DIV_20                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 20 */
00764 #define LL_RCC_PLLP_DIV_21                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 21 */
00765 #define LL_RCC_PLLP_DIV_22                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 22 */
00766 #define LL_RCC_PLLP_DIV_23                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 23 */
00767 #define LL_RCC_PLLP_DIV_24                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
00768 #define LL_RCC_PLLP_DIV_25                 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 25 */
00769 #define LL_RCC_PLLP_DIV_26                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 26 */
00770 #define LL_RCC_PLLP_DIV_27                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 27*/
00771 #define LL_RCC_PLLP_DIV_28                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
00772 #define LL_RCC_PLLP_DIV_29                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 29 */
00773 #define LL_RCC_PLLP_DIV_30                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
00774 #define LL_RCC_PLLP_DIV_31                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
00775 #define LL_RCC_PLLP_DIV_32                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
00776 /**
00777   * @}
00778   */
00779
00780 #if defined(RCC_PLLQ_SUPPORT)
00781 /** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
00782   * @{
00783   */
00784 #define LL_RCC_PLLQ_DIV_2                  (RCC_PLLCFGR_PLLQ_0)                    /*!< Main PLL division factor for PLLQ output by 2 */
00785 #define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1)                    /*!< Main PLL division factor for PLLQ output by 3 */
00786 #define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
00787 #define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2)                    /*!< Main PLL division factor for PLLQ output by 5 */
00788 #define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
00789 #define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
00790 #define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)                      /*!< Main PLL division factor for PLLQ output by 8 */
00791 /**
00792   * @}
00793   */
00794 #endif /* RCC_PLLQ_SUPPORT */
00795
00796 /**
00797   * @}
00798   */
00799
00800 /* Exported macro ------------------------------------------------------------*/
00801 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
00802   * @{
00803   */
00804
00805 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
00806   * @{
00807   */
00808
00809 /**
00810   * @brief  Write a value in RCC register
00811   * @param  __REG__ Register to be written
00812   * @param  __VALUE__ Value to be written in the register
00813   * @retval None
00814   */
00815 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__))
00816
00817 /**
00818   * @brief  Read a value in RCC register
00819   * @param  __REG__ Register to be read
00820   * @retval Register value
00821   */
00822 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
00823 /**
00824   * @}
00825   */
00826
00827 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
00828   * @{
00829   */
00830
00831 /**
00832   * @brief  Helper macro to calculate the PLLCLK frequency on system domain
00833   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00834   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
00835   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
00836   * @param  __PLLM__ This parameter can be one of the following values:
00837   *         @arg @ref LL_RCC_PLLM_DIV_1
00838   *         @arg @ref LL_RCC_PLLM_DIV_2
00839   *         @arg @ref LL_RCC_PLLM_DIV_3
00840   *         @arg @ref LL_RCC_PLLM_DIV_4
00841   *         @arg @ref LL_RCC_PLLM_DIV_5
00842   *         @arg @ref LL_RCC_PLLM_DIV_6
00843   *         @arg @ref LL_RCC_PLLM_DIV_7
00844   *         @arg @ref LL_RCC_PLLM_DIV_8
00845   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
00846   * @param  __PLLR__ This parameter can be one of the following values:
00847   *         @arg @ref LL_RCC_PLLR_DIV_2
00848   *         @arg @ref LL_RCC_PLLR_DIV_3
00849   *         @arg @ref LL_RCC_PLLR_DIV_4
00850   *         @arg @ref LL_RCC_PLLR_DIV_5
00851   *         @arg @ref LL_RCC_PLLR_DIV_6
00852   *         @arg @ref LL_RCC_PLLR_DIV_7
00853   *         @arg @ref LL_RCC_PLLR_DIV_8
00854   * @retval PLL clock frequency (in Hz)
00855   */
00856 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)   \
00857   ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
00858    (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
00859
00860 /**
00861   * @brief  Helper macro to calculate the PLLPCLK frequency used on I2S domain
00862   * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00863   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
00864   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
00865   * @param  __PLLM__ This parameter can be one of the following values:
00866   *         @arg @ref LL_RCC_PLLM_DIV_1
00867   *         @arg @ref LL_RCC_PLLM_DIV_2
00868   *         @arg @ref LL_RCC_PLLM_DIV_3
00869   *         @arg @ref LL_RCC_PLLM_DIV_4
00870   *         @arg @ref LL_RCC_PLLM_DIV_5
00871   *         @arg @ref LL_RCC_PLLM_DIV_6
00872   *         @arg @ref LL_RCC_PLLM_DIV_7
00873   *         @arg @ref LL_RCC_PLLM_DIV_8
00874   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
00875   * @param  __PLLP__ This parameter can be one of the following values:
00876   *         @arg @ref LL_RCC_PLLP_DIV_2
00877   *         @arg @ref LL_RCC_PLLP_DIV_3
00878   *         @arg @ref LL_RCC_PLLP_DIV_4
00879   *         @arg @ref LL_RCC_PLLP_DIV_5
00880   *         @arg @ref LL_RCC_PLLP_DIV_6
00881   *         @arg @ref LL_RCC_PLLP_DIV_7
00882   *         @arg @ref LL_RCC_PLLP_DIV_8
00883   *         @arg @ref LL_RCC_PLLP_DIV_9
00884   *         @arg @ref LL_RCC_PLLP_DIV_10
00885   *         @arg @ref LL_RCC_PLLP_DIV_11
00886   *         @arg @ref LL_RCC_PLLP_DIV_12
00887   *         @arg @ref LL_RCC_PLLP_DIV_13
00888   *         @arg @ref LL_RCC_PLLP_DIV_14
00889   *         @arg @ref LL_RCC_PLLP_DIV_15
00890   *         @arg @ref LL_RCC_PLLP_DIV_16
00891   *         @arg @ref LL_RCC_PLLP_DIV_17
00892   *         @arg @ref LL_RCC_PLLP_DIV_18
00893   *         @arg @ref LL_RCC_PLLP_DIV_19
00894   *         @arg @ref LL_RCC_PLLP_DIV_20
00895   *         @arg @ref LL_RCC_PLLP_DIV_21
00896   *         @arg @ref LL_RCC_PLLP_DIV_22
00897   *         @arg @ref LL_RCC_PLLP_DIV_23
00898   *         @arg @ref LL_RCC_PLLP_DIV_24
00899   *         @arg @ref LL_RCC_PLLP_DIV_25
00900   *         @arg @ref LL_RCC_PLLP_DIV_26
00901   *         @arg @ref LL_RCC_PLLP_DIV_27
00902   *         @arg @ref LL_RCC_PLLP_DIV_28
00903   *         @arg @ref LL_RCC_PLLP_DIV_29
00904   *         @arg @ref LL_RCC_PLLP_DIV_30
00905   *         @arg @ref LL_RCC_PLLP_DIV_31
00906   *         @arg @ref LL_RCC_PLLP_DIV_32
00907   * @retval PLL clock frequency (in Hz)
00908   */
00909 #define __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)  \
00910   ((__INPUTFREQ__)  * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
00911    (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
00912
00913 #if defined(RCC_CCIPR2_I2S2SEL)
00914 /**
00915   * @brief  Helper macro to calculate the PLLPCLK frequency used on I2S2 domain
00916   * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00917   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
00918   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
00919   * @param  __PLLM__ This parameter can be one of the following values:
00920   *         @arg @ref LL_RCC_PLLM_DIV_1
00921   *         @arg @ref LL_RCC_PLLM_DIV_2
00922   *         @arg @ref LL_RCC_PLLM_DIV_3
00923   *         @arg @ref LL_RCC_PLLM_DIV_4
00924   *         @arg @ref LL_RCC_PLLM_DIV_5
00925   *         @arg @ref LL_RCC_PLLM_DIV_6
00926   *         @arg @ref LL_RCC_PLLM_DIV_7
00927   *         @arg @ref LL_RCC_PLLM_DIV_8
00928   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
00929   * @param  __PLLP__ This parameter can be one of the following values:
00930   *         @arg @ref LL_RCC_PLLP_DIV_2
00931   *         @arg @ref LL_RCC_PLLP_DIV_3
00932   *         @arg @ref LL_RCC_PLLP_DIV_4
00933   *         @arg @ref LL_RCC_PLLP_DIV_5
00934   *         @arg @ref LL_RCC_PLLP_DIV_6
00935   *         @arg @ref LL_RCC_PLLP_DIV_7
00936   *         @arg @ref LL_RCC_PLLP_DIV_8
00937   *         @arg @ref LL_RCC_PLLP_DIV_9
00938   *         @arg @ref LL_RCC_PLLP_DIV_10
00939   *         @arg @ref LL_RCC_PLLP_DIV_11
00940   *         @arg @ref LL_RCC_PLLP_DIV_12
00941   *         @arg @ref LL_RCC_PLLP_DIV_13
00942   *         @arg @ref LL_RCC_PLLP_DIV_14
00943   *         @arg @ref LL_RCC_PLLP_DIV_15
00944   *         @arg @ref LL_RCC_PLLP_DIV_16
00945   *         @arg @ref LL_RCC_PLLP_DIV_17
00946   *         @arg @ref LL_RCC_PLLP_DIV_18
00947   *         @arg @ref LL_RCC_PLLP_DIV_19
00948   *         @arg @ref LL_RCC_PLLP_DIV_20
00949   *         @arg @ref LL_RCC_PLLP_DIV_21
00950   *         @arg @ref LL_RCC_PLLP_DIV_22
00951   *         @arg @ref LL_RCC_PLLP_DIV_23
00952   *         @arg @ref LL_RCC_PLLP_DIV_24
00953   *         @arg @ref LL_RCC_PLLP_DIV_25
00954   *         @arg @ref LL_RCC_PLLP_DIV_26
00955   *         @arg @ref LL_RCC_PLLP_DIV_27
00956   *         @arg @ref LL_RCC_PLLP_DIV_28
00957   *         @arg @ref LL_RCC_PLLP_DIV_29
00958   *         @arg @ref LL_RCC_PLLP_DIV_30
00959   *         @arg @ref LL_RCC_PLLP_DIV_31
00960   *         @arg @ref LL_RCC_PLLP_DIV_32
00961   * @retval PLL clock frequency (in Hz)
00962   */
00963 #define __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)  \
00964   ((__INPUTFREQ__)  * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
00965    (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
00966 #endif /* RCC_CCIPR2_I2S2SEL */
00967
00968 /**
00969   * @brief  Helper macro to calculate the PLLPCLK frequency used on ADC domain
00970   * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00971   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
00972   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
00973   * @param  __PLLM__ This parameter can be one of the following values:
00974   *         @arg @ref LL_RCC_PLLM_DIV_1
00975   *         @arg @ref LL_RCC_PLLM_DIV_2
00976   *         @arg @ref LL_RCC_PLLM_DIV_3
00977   *         @arg @ref LL_RCC_PLLM_DIV_4
00978   *         @arg @ref LL_RCC_PLLM_DIV_5
00979   *         @arg @ref LL_RCC_PLLM_DIV_6
00980   *         @arg @ref LL_RCC_PLLM_DIV_7
00981   *         @arg @ref LL_RCC_PLLM_DIV_8
00982   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
00983   * @param  __PLLP__ This parameter can be one of the following values:
00984   *         @arg @ref LL_RCC_PLLP_DIV_2
00985   *         @arg @ref LL_RCC_PLLP_DIV_3
00986   *         @arg @ref LL_RCC_PLLP_DIV_4
00987   *         @arg @ref LL_RCC_PLLP_DIV_5
00988   *         @arg @ref LL_RCC_PLLP_DIV_6
00989   *         @arg @ref LL_RCC_PLLP_DIV_7
00990   *         @arg @ref LL_RCC_PLLP_DIV_8
00991   *         @arg @ref LL_RCC_PLLP_DIV_9
00992   *         @arg @ref LL_RCC_PLLP_DIV_10
00993   *         @arg @ref LL_RCC_PLLP_DIV_11
00994   *         @arg @ref LL_RCC_PLLP_DIV_12
00995   *         @arg @ref LL_RCC_PLLP_DIV_13
00996   *         @arg @ref LL_RCC_PLLP_DIV_14
00997   *         @arg @ref LL_RCC_PLLP_DIV_15
00998   *         @arg @ref LL_RCC_PLLP_DIV_16
00999   *         @arg @ref LL_RCC_PLLP_DIV_17
01000   *         @arg @ref LL_RCC_PLLP_DIV_18
01001   *         @arg @ref LL_RCC_PLLP_DIV_19
01002   *         @arg @ref LL_RCC_PLLP_DIV_20
01003   *         @arg @ref LL_RCC_PLLP_DIV_21
01004   *         @arg @ref LL_RCC_PLLP_DIV_22
01005   *         @arg @ref LL_RCC_PLLP_DIV_23
01006   *         @arg @ref LL_RCC_PLLP_DIV_24
01007   *         @arg @ref LL_RCC_PLLP_DIV_25
01008   *         @arg @ref LL_RCC_PLLP_DIV_26
01009   *         @arg @ref LL_RCC_PLLP_DIV_27
01010   *         @arg @ref LL_RCC_PLLP_DIV_28
01011   *         @arg @ref LL_RCC_PLLP_DIV_29
01012   *         @arg @ref LL_RCC_PLLP_DIV_30
01013   *         @arg @ref LL_RCC_PLLP_DIV_31
01014   *         @arg @ref LL_RCC_PLLP_DIV_32
01015   * @retval PLL clock frequency (in Hz)
01016   */
01017 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)  \
01018   ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
01019    (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
01020
01021 #if defined(RNG)
01022 /**
01023   * @brief  Helper macro to calculate the PLLQCLK frequency used on RNG domain
01024   * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01025   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
01026   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
01027   * @param  __PLLM__ This parameter can be one of the following values:
01028   *         @arg @ref LL_RCC_PLLM_DIV_1
01029   *         @arg @ref LL_RCC_PLLM_DIV_2
01030   *         @arg @ref LL_RCC_PLLM_DIV_3
01031   *         @arg @ref LL_RCC_PLLM_DIV_4
01032   *         @arg @ref LL_RCC_PLLM_DIV_5
01033   *         @arg @ref LL_RCC_PLLM_DIV_6
01034   *         @arg @ref LL_RCC_PLLM_DIV_7
01035   *         @arg @ref LL_RCC_PLLM_DIV_8
01036   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
01037   * @param  __PLLQ__ This parameter can be one of the following values:
01038   *         @arg @ref LL_RCC_PLLQ_DIV_2
01039   *         @arg @ref LL_RCC_PLLQ_DIV_3
01040   *         @arg @ref LL_RCC_PLLQ_DIV_4
01041   *         @arg @ref LL_RCC_PLLQ_DIV_5
01042   *         @arg @ref LL_RCC_PLLQ_DIV_6
01043   *         @arg @ref LL_RCC_PLLQ_DIV_7
01044   *         @arg @ref LL_RCC_PLLQ_DIV_8
01045   * @retval PLL clock frequency (in Hz)
01046   */
01047 #define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)   \
01048   ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /     \
01049    (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
01050 #endif /* RNG */
01051
01052 #if defined(RCC_PLLQ_SUPPORT)
01053 /**
01054   * @brief  Helper macro to calculate the PLLQCLK frequency used on TIM1 domain
01055   * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01056   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
01057   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
01058   * @param  __PLLM__ This parameter can be one of the following values:
01059   *         @arg @ref LL_RCC_PLLM_DIV_1
01060   *         @arg @ref LL_RCC_PLLM_DIV_2
01061   *         @arg @ref LL_RCC_PLLM_DIV_3
01062   *         @arg @ref LL_RCC_PLLM_DIV_4
01063   *         @arg @ref LL_RCC_PLLM_DIV_5
01064   *         @arg @ref LL_RCC_PLLM_DIV_6
01065   *         @arg @ref LL_RCC_PLLM_DIV_7
01066   *         @arg @ref LL_RCC_PLLM_DIV_8
01067   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
01068   * @param  __PLLQ__ This parameter can be one of the following values:
01069   *         @arg @ref LL_RCC_PLLQ_DIV_2
01070   *         @arg @ref LL_RCC_PLLQ_DIV_3
01071   *         @arg @ref LL_RCC_PLLQ_DIV_4
01072   *         @arg @ref LL_RCC_PLLQ_DIV_5
01073   *         @arg @ref LL_RCC_PLLQ_DIV_6
01074   *         @arg @ref LL_RCC_PLLQ_DIV_7
01075   *         @arg @ref LL_RCC_PLLQ_DIV_8
01076   * @retval PLL clock frequency (in Hz)
01077   */
01078 #define __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
01079   ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
01080    (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
01081 #if defined(TIM15)
01082 /**
01083   * @brief  Helper macro to calculate the PLLQCLK frequency used on TIM15 domain
01084   * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM15_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01085   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
01086   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
01087   * @param  __PLLM__ This parameter can be one of the following values:
01088   *         @arg @ref LL_RCC_PLLM_DIV_1
01089   *         @arg @ref LL_RCC_PLLM_DIV_2
01090   *         @arg @ref LL_RCC_PLLM_DIV_3
01091   *         @arg @ref LL_RCC_PLLM_DIV_4
01092   *         @arg @ref LL_RCC_PLLM_DIV_5
01093   *         @arg @ref LL_RCC_PLLM_DIV_6
01094   *         @arg @ref LL_RCC_PLLM_DIV_7
01095   *         @arg @ref LL_RCC_PLLM_DIV_8
01096   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
01097   * @param  __PLLQ__ This parameter can be one of the following values:
01098   *         @arg @ref LL_RCC_PLLQ_DIV_2
01099   *         @arg @ref LL_RCC_PLLQ_DIV_3
01100   *         @arg @ref LL_RCC_PLLQ_DIV_4
01101   *         @arg @ref LL_RCC_PLLQ_DIV_5
01102   *         @arg @ref LL_RCC_PLLQ_DIV_6
01103   *         @arg @ref LL_RCC_PLLQ_DIV_7
01104   *         @arg @ref LL_RCC_PLLQ_DIV_8
01105   * @retval PLL clock frequency (in Hz)
01106   */
01107 #define __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)  \
01108   ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /      \
01109    (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
01110 #endif /* TIM15 */
01111 #endif /* RCC_PLLQ_SUPPORT */
01112
01113 #if defined(FDCAN1) || defined(FDCAN2)
01114 /**
01115   * @brief  Helper macro to calculate the PLLQCLK frequency used on FDCAN domain
01116   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FDCAN_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01117   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
01118   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
01119   * @param  __PLLM__ This parameter can be one of the following values:
01120   *         @arg @ref LL_RCC_PLLM_DIV_1
01121   *         @arg @ref LL_RCC_PLLM_DIV_2
01122   *         @arg @ref LL_RCC_PLLM_DIV_3
01123   *         @arg @ref LL_RCC_PLLM_DIV_4
01124   *         @arg @ref LL_RCC_PLLM_DIV_5
01125   *         @arg @ref LL_RCC_PLLM_DIV_6
01126   *         @arg @ref LL_RCC_PLLM_DIV_7
01127   *         @arg @ref LL_RCC_PLLM_DIV_8
01128   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
01129   * @param  __PLLQ__ This parameter can be one of the following values:
01130   *         @arg @ref LL_RCC_PLLQ_DIV_2
01131   *         @arg @ref LL_RCC_PLLQ_DIV_3
01132   *         @arg @ref LL_RCC_PLLQ_DIV_4
01133   *         @arg @ref LL_RCC_PLLQ_DIV_5
01134   *         @arg @ref LL_RCC_PLLQ_DIV_6
01135   *         @arg @ref LL_RCC_PLLQ_DIV_7
01136   *         @arg @ref LL_RCC_PLLQ_DIV_8
01137   * @retval PLL clock frequency (in Hz)
01138   */
01139 #define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
01140   ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /     \
01141    (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
01142 #endif /* FDCAN1 || FDCAN2 */
01143
01144 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
01145 /**
01146   * @brief  Helper macro to calculate the PLLQCLK frequency used on USB domain
01147   * @note ex: @ref __LL_RCC_CALC_PLLCLK_USB_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01148   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
01149   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
01150   * @param  __PLLM__ This parameter can be one of the following values:
01151   *         @arg @ref LL_RCC_PLLM_DIV_1
01152   *         @arg @ref LL_RCC_PLLM_DIV_2
01153   *         @arg @ref LL_RCC_PLLM_DIV_3
01154   *         @arg @ref LL_RCC_PLLM_DIV_4
01155   *         @arg @ref LL_RCC_PLLM_DIV_5
01156   *         @arg @ref LL_RCC_PLLM_DIV_6
01157   *         @arg @ref LL_RCC_PLLM_DIV_7
01158   *         @arg @ref LL_RCC_PLLM_DIV_8
01159   * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
01160   * @param  __PLLQ__ This parameter can be one of the following values:
01161   *         @arg @ref LL_RCC_PLLQ_DIV_2
01162   *         @arg @ref LL_RCC_PLLQ_DIV_3
01163   *         @arg @ref LL_RCC_PLLQ_DIV_4
01164   *         @arg @ref LL_RCC_PLLQ_DIV_5
01165   *         @arg @ref LL_RCC_PLLQ_DIV_6
01166   *         @arg @ref LL_RCC_PLLQ_DIV_7
01167   *         @arg @ref LL_RCC_PLLQ_DIV_8
01168   * @retval PLL clock frequency (in Hz)
01169   */
01170 #define __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
01171   ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /   \
01172    (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
01173 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
01174
01175 /**
01176   * @brief  Helper macro to calculate the HCLK frequency
01177   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
01178   * @param  __AHBPRESCALER__ This parameter can be one of the following values:
01179   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01180   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01181   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01182   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01183   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01184   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01185   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01186   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01187   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01188   * @retval HCLK clock frequency (in Hz)
01189   */
01190 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__)  \
01191   ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos] & 0x1FU))
01192
01193 /**
01194   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
01195   * @param  __HCLKFREQ__ HCLK frequency
01196   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
01197   *         @arg @ref LL_RCC_APB1_DIV_1
01198   *         @arg @ref LL_RCC_APB1_DIV_2
01199   *         @arg @ref LL_RCC_APB1_DIV_4
01200   *         @arg @ref LL_RCC_APB1_DIV_8
01201   *         @arg @ref LL_RCC_APB1_DIV_16
01202   * @retval PCLK1 clock frequency (in Hz)
01203   */
01204 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__)  \
01205   ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE_Pos] & 0x1FU))
01206
01207 /**
01208   * @brief  Helper macro to calculate the HSISYS frequency
01209   * @param  __HSIDIV__ This parameter can be one of the following values:
01210   *         @arg @ref LL_RCC_HSI_DIV_1
01211   *         @arg @ref LL_RCC_HSI_DIV_2
01212   *         @arg @ref LL_RCC_HSI_DIV_4
01213   *         @arg @ref LL_RCC_HSI_DIV_8
01214   *         @arg @ref LL_RCC_HSI_DIV_16
01215   *         @arg @ref LL_RCC_HSI_DIV_32
01216   *         @arg @ref LL_RCC_HSI_DIV_64
01217   *         @arg @ref LL_RCC_HSI_DIV_128
01218   * @retval HSISYS clock frequency (in Hz)
01219   */
01220 #define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))
01221
01222 /**
01223   * @}
01224   */
01225
01226 /**
01227   * @}
01228   */
01229
01230 /* Exported functions --------------------------------------------------------*/
01231 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
01232   * @{
01233   */
01234
01235 /** @defgroup RCC_LL_EF_HSE HSE
01236   * @{
01237   */
01238
01239 /**
01240   * @brief  Enable the Clock Security System.
01241   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
01242   * @retval None
01243   */
01244 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
01245 {
01246   SET_BIT(RCC->CR, RCC_CR_CSSON);
01247 }
01248
01249 /**
01250   * @brief  Enable HSE external oscillator (HSE Bypass)
01251   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
01252   * @retval None
01253   */
01254 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
01255 {
01256   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
01257 }
01258
01259 /**
01260   * @brief  Disable HSE external oscillator (HSE Bypass)
01261   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
01262   * @retval None
01263   */
01264 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
01265 {
01266   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
01267 }
01268
01269 /**
01270   * @brief  Enable HSE crystal oscillator (HSE ON)
01271   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
01272   * @retval None
01273   */
01274 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
01275 {
01276   SET_BIT(RCC->CR, RCC_CR_HSEON);
01277 }
01278
01279 /**
01280   * @brief  Disable HSE crystal oscillator (HSE ON)
01281   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
01282   * @retval None
01283   */
01284 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
01285 {
01286   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
01287 }
01288
01289 /**
01290   * @brief  Check if HSE oscillator Ready
01291   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
01292   * @retval State of bit (1 or 0).
01293   */
01294 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
01295 {
01296   return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
01297 }
01298
01299 /**
01300   * @}
01301   */
01302
01303 /** @defgroup RCC_LL_EF_HSI HSI
01304   * @{
01305   */
01306
01307 /**
01308   * @brief  Enable HSI even in stop mode
01309   * @note HSI oscillator is forced ON even in Stop mode
01310   * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
01311   * @retval None
01312   */
01313 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
01314 {
01315   SET_BIT(RCC->CR, RCC_CR_HSIKERON);
01316 }
01317
01318 /**
01319   * @brief  Disable HSI in stop mode
01320   * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
01321   * @retval None
01322   */
01323 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
01324 {
01325   CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
01326 }
01327
01328 /**
01329   * @brief  Check if HSI in stop mode is enabled
01330   * @rmtoll CR           HSIKERON        LL_RCC_HSI_IsEnabledInStopMode
01331   * @retval State of bit (1 or 0).
01332   */
01333 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
01334 {
01335   return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
01336 }
01337
01338 /**
01339   * @brief  Enable HSI oscillator
01340   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
01341   * @retval None
01342   */
01343 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
01344 {
01345   SET_BIT(RCC->CR, RCC_CR_HSION);
01346 }
01347
01348 /**
01349   * @brief  Disable HSI oscillator
01350   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
01351   * @retval None
01352   */
01353 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
01354 {
01355   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
01356 }
01357
01358 /**
01359   * @brief  Check if HSI clock is ready
01360   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
01361   * @retval State of bit (1 or 0).
01362   */
01363 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
01364 {
01365   return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
01366 }
01367
01368 /**
01369   * @brief  Get HSI Calibration value
01370   * @note When HSITRIM is written, HSICAL is updated with the sum of
01371   *       HSITRIM and the factory trim value
01372   * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
01373   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
01374   */
01375 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
01376 {
01377   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
01378 }
01379
01380 /**
01381   * @brief  Set HSI Calibration trimming
01382   * @note user-programmable trimming value that is added to the HSICAL
01383   * @note Default value is 64, which, when added to the HSICAL value,
01384   *       should trim the HSI to 16 MHz +/- 1 %
01385   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
01386   * @param  Value Between Min_Data = 0 and Max_Data = 127
01387   * @retval None
01388   */
01389 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
01390 {
01391   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
01392 }
01393
01394 /**
01395   * @brief  Get HSI Calibration trimming
01396   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
01397   * @retval Between Min_Data = 0 and Max_Data = 127
01398   */
01399 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
01400 {
01401   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
01402 }
01403
01404 /**
01405   * @}
01406   */
01407
01408 #if defined(RCC_HSI48_SUPPORT)
01409 /** @defgroup RCC_LL_EF_HSI48 HSI48
01410   * @{
01411   */
01412
01413 /**
01414   * @brief  Enable HSI48
01415   * @rmtoll CR         HSI48ON       LL_RCC_HSI48_Enable
01416   * @retval None
01417   */
01418 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
01419 {
01420   SET_BIT(RCC->CR, RCC_CR_HSI48ON);
01421 }
01422
01423 /**
01424   * @brief  Disable HSI48
01425   * @rmtoll CR          HSI48ON       LL_RCC_HSI48_Disable
01426   * @retval None
01427   */
01428 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
01429 {
01430   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
01431 }
01432
01433 /**
01434   * @brief  Check if HSI48 oscillator Ready
01435   * @rmtoll CR          HSI48RDY      LL_RCC_HSI48_IsReady
01436   * @retval State of bit (1 or 0).
01437   */
01438 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
01439 {
01440   return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
01441 }
01442
01443 /**
01444   * @brief  Get HSI48 Calibration value
01445   * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
01446   * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
01447   */
01448 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
01449 {
01450   return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
01451 }
01452
01453 /**
01454   * @}
01455   */
01456 #endif /* RCC_HSI48_SUPPORT */
01457
01458 /** @defgroup RCC_LL_EF_LSE LSE
01459   * @{
01460   */
01461
01462 /**
01463   * @brief  Enable  Low Speed External (LSE) crystal.
01464   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
01465   * @retval None
01466   */
01467 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
01468 {
01469   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01470 }
01471
01472 /**
01473   * @brief  Disable  Low Speed External (LSE) crystal.
01474   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
01475   * @retval None
01476   */
01477 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
01478 {
01479   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01480 }
01481
01482 /**
01483   * @brief  Enable external clock source (LSE bypass).
01484   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
01485   * @retval None
01486   */
01487 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
01488 {
01489   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01490 }
01491
01492 /**
01493   * @brief  Disable external clock source (LSE bypass).
01494   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
01495   * @retval None
01496   */
01497 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
01498 {
01499   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01500 }
01501
01502 /**
01503   * @brief  Set LSE oscillator drive capability
01504   * @note The oscillator is in Xtal mode when it is not in bypass mode.
01505   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
01506   * @param  LSEDrive This parameter can be one of the following values:
01507   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01508   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01509   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01510   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01511   * @retval None
01512   */
01513 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
01514 {
01515   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
01516 }
01517
01518 /**
01519   * @brief  Get LSE oscillator drive capability
01520   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
01521   * @retval Returned value can be one of the following values:
01522   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01523   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01524   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01525   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01526   */
01527 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
01528 {
01529   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
01530 }
01531
01532 /**
01533   * @brief  Enable Clock security system on LSE.
01534   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
01535   * @retval None
01536   */
01537 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
01538 {
01539   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01540 }
01541
01542 /**
01543   * @brief  Disable Clock security system on LSE.
01544   * @note Clock security system can be disabled only after a LSE
01545   *       failure detection. In that case it MUST be disabled by software.
01546   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS
01547   * @retval None
01548   */
01549 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
01550 {
01551   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01552 }
01553
01554 /**
01555   * @brief  Check if LSE oscillator Ready
01556   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
01557   * @retval State of bit (1 or 0).
01558   */
01559 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
01560 {
01561   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
01562 }
01563
01564 /**
01565   * @brief  Check if CSS on LSE failure Detection
01566   * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
01567   * @retval State of bit (1 or 0).
01568   */
01569 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
01570 {
01571   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
01572 }
01573
01574 /**
01575   * @}
01576   */
01577
01578 /** @defgroup RCC_LL_EF_LSI LSI
01579   * @{
01580   */
01581
01582 /**
01583   * @brief  Enable LSI Oscillator
01584   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
01585   * @retval None
01586   */
01587 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
01588 {
01589   SET_BIT(RCC->CSR, RCC_CSR_LSION);
01590 }
01591
01592 /**
01593   * @brief  Disable LSI Oscillator
01594   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
01595   * @retval None
01596   */
01597 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
01598 {
01599   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
01600 }
01601
01602 /**
01603   * @brief  Check if LSI is Ready
01604   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
01605   * @retval State of bit (1 or 0).
01606   */
01607 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
01608 {
01609   return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
01610 }
01611
01612 /**
01613   * @}
01614   */
01615
01616 /** @defgroup RCC_LL_EF_LSCO LSCO
01617   * @{
01618   */
01619
01620 /**
01621   * @brief  Enable Low speed clock
01622   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable
01623   * @retval None
01624   */
01625 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
01626 {
01627   SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01628 }
01629
01630 /**
01631   * @brief  Disable Low speed clock
01632   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable
01633   * @retval None
01634   */
01635 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
01636 {
01637   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01638 }
01639
01640 /**
01641   * @brief  Configure Low speed clock selection
01642   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource
01643   * @param  Source This parameter can be one of the following values:
01644   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
01645   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
01646   * @retval None
01647   */
01648 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
01649 {
01650   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
01651 }
01652
01653 /**
01654   * @brief  Get Low speed clock selection
01655   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource
01656   * @retval Returned value can be one of the following values:
01657   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
01658   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
01659   */
01660 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
01661 {
01662   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
01663 }
01664
01665 /**
01666   * @}
01667   */
01668
01669 /** @defgroup RCC_LL_EF_System System
01670   * @{
01671   */
01672
01673 /**
01674   * @brief  Configure the system clock source
01675   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
01676   * @param  Source This parameter can be one of the following values:
01677   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
01678   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
01679   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
01680   *         @arg @ref LL_RCC_SYS_CLKSOURCE_LSI
01681   *         @arg @ref LL_RCC_SYS_CLKSOURCE_LSE
01682   * @retval None
01683   */
01684 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
01685 {
01686   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
01687 }
01688
01689 /**
01690   * @brief  Get the system clock source
01691   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
01692   * @retval Returned value can be one of the following values:
01693   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
01694   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
01695   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
01696   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI
01697   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE
01698   */
01699 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
01700 {
01701   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
01702 }
01703
01704 /**
01705   * @brief  Set AHB prescaler
01706   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
01707   * @param  Prescaler This parameter can be one of the following values:
01708   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01709   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01710   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01711   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01712   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01713   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01714   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01715   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01716   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01717   * @retval None
01718   */
01719 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
01720 {
01721   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
01722 }
01723
01724 /**
01725   * @brief  Set APB1 prescaler
01726   * @rmtoll CFGR         PPRE         LL_RCC_SetAPB1Prescaler
01727   * @param  Prescaler This parameter can be one of the following values:
01728   *         @arg @ref LL_RCC_APB1_DIV_1
01729   *         @arg @ref LL_RCC_APB1_DIV_2
01730   *         @arg @ref LL_RCC_APB1_DIV_4
01731   *         @arg @ref LL_RCC_APB1_DIV_8
01732   *         @arg @ref LL_RCC_APB1_DIV_16
01733   * @retval None
01734   */
01735 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
01736 {
01737   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
01738 }
01739
01740 /**
01741   * @brief  Set HSI16 division factor
01742   * @rmtoll CR         HSIDIV          LL_RCC_SetHSIDiv
01743   * @note  HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
01744   * system clock source.
01745   * @param  HSIDiv  This parameter can be one of the following values:
01746   *         @arg @ref LL_RCC_HSI_DIV_1
01747   *         @arg @ref LL_RCC_HSI_DIV_2
01748   *         @arg @ref LL_RCC_HSI_DIV_4
01749   *         @arg @ref LL_RCC_HSI_DIV_8
01750   *         @arg @ref LL_RCC_HSI_DIV_16
01751   *         @arg @ref LL_RCC_HSI_DIV_32
01752   *         @arg @ref LL_RCC_HSI_DIV_64
01753   *         @arg @ref LL_RCC_HSI_DIV_128
01754   * @retval None
01755   */
01756 __STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv)
01757 {
01758   MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv);
01759 }
01760 /**
01761   * @brief  Get AHB prescaler
01762   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
01763   * @retval Returned value can be one of the following values:
01764   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01765   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01766   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01767   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01768   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01769   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01770   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01771   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01772   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01773   */
01774 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
01775 {
01776   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
01777 }
01778
01779 /**
01780   * @brief  Get APB1 prescaler
01781   * @rmtoll CFGR         PPRE         LL_RCC_GetAPB1Prescaler
01782   * @retval Returned value can be one of the following values:
01783   *         @arg @ref LL_RCC_APB1_DIV_1
01784   *         @arg @ref LL_RCC_APB1_DIV_2
01785   *         @arg @ref LL_RCC_APB1_DIV_4
01786   *         @arg @ref LL_RCC_APB1_DIV_8
01787   *         @arg @ref LL_RCC_APB1_DIV_16
01788   */
01789 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
01790 {
01791   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
01792 }
01793
01794 /**
01795   * @brief  Get HSI16 Division factor
01796   * @rmtoll CR         HSIDIV         LL_RCC_GetHSIDiv
01797   * @note  HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
01798   * system clock source.
01799   * @retval Returned value can be one of the following values:
01800   *         @arg @ref LL_RCC_HSI_DIV_1
01801   *         @arg @ref LL_RCC_HSI_DIV_2
01802   *         @arg @ref LL_RCC_HSI_DIV_4
01803   *         @arg @ref LL_RCC_HSI_DIV_8
01804   *         @arg @ref LL_RCC_HSI_DIV_16
01805   *         @arg @ref LL_RCC_HSI_DIV_32
01806   *         @arg @ref LL_RCC_HSI_DIV_64
01807   *         @arg @ref LL_RCC_HSI_DIV_128
01808   */
01809 __STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void)
01810 {
01811   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV));
01812 }
01813 /**
01814   * @}
01815   */
01816
01817 /** @defgroup RCC_LL_EF_MCO1 MCO1
01818   * @{
01819   */
01820
01821 /**
01822   * @brief  Configure MCOx
01823   * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
01824   *         CFGR         MCOPRE        LL_RCC_ConfigMCO
01825   * @param  MCOxSource This parameter can be one of the following values:
01826   *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
01827   *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
01828   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
01829   *         @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
01830   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
01831   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
01832   *         @arg @ref LL_RCC_MCO1SOURCE_LSI
01833   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
01834   *         @arg @ref LL_RCC_MCO1SOURCE_PLLPCLK (*)
01835   *         @arg @ref LL_RCC_MCO1SOURCE_PLLQCLK (*)
01836   *         @arg @ref LL_RCC_MCO1SOURCE_RTCCLK (*)
01837   *         @arg @ref LL_RCC_MCO1SOURCE_RTC_WKUP (*)
01838   *
01839   *         (*) value not defined in all devices.
01840   * @param  MCOxPrescaler This parameter can be one of the following values:
01841   *         @arg @ref LL_RCC_MCO1_DIV_1
01842   *         @arg @ref LL_RCC_MCO1_DIV_2
01843   *         @arg @ref LL_RCC_MCO1_DIV_4
01844   *         @arg @ref LL_RCC_MCO1_DIV_8
01845   *         @arg @ref LL_RCC_MCO1_DIV_32
01846   *         @arg @ref LL_RCC_MCO1_DIV_64
01847   *         @arg @ref LL_RCC_MCO1_DIV_128
01848   * @retval None
01849   */
01850 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
01851 {
01852   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
01853 }
01854
01855 /**
01856   * @}
01857   */
01858
01859 #if defined(RCC_MCO2_SUPPORT)
01860 /** @defgroup RCC_LL_EF_MCO2 MCO2
01861   * @{
01862   */
01863
01864 /**
01865   * @brief  Configure MCO2
01866   * @rmtoll CFGR         MCO2SEL        LL_RCC_ConfigMCO2\n
01867   *         CFGR         MCO2PRE        LL_RCC_ConfigMCO2
01868   * @note  feature not available in all devices.
01869   * @param  MCOxSource This parameter can be one of the following values:
01870   *         @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK
01871   *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
01872   *         @arg @ref LL_RCC_MCO2SOURCE_HSI
01873   *         @arg @ref LL_RCC_MCO2SOURCE_HSI48
01874   *         @arg @ref LL_RCC_MCO2SOURCE_HSE
01875   *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
01876   *         @arg @ref LL_RCC_MCO2SOURCE_LSI
01877   *         @arg @ref LL_RCC_MCO2SOURCE_LSE
01878   *         @arg @ref LL_RCC_MCO2SOURCE_PLLPCLK
01879   *         @arg @ref LL_RCC_MCO2SOURCE_PLLQCLK
01880   *         @arg @ref LL_RCC_MCO2SOURCE_RTCCLK
01881   *         @arg @ref LL_RCC_MCO2SOURCE_RTC_WKUP
01882   *
01883   * @param  MCOxPrescaler This parameter can be one of the following values:
01884   *         @arg @ref LL_RCC_MCO2_DIV_1
01885   *         @arg @ref LL_RCC_MCO2_DIV_2
01886   *         @arg @ref LL_RCC_MCO2_DIV_4
01887   *         @arg @ref LL_RCC_MCO2_DIV_8
01888   *         @arg @ref LL_RCC_MCO2_DIV_16
01889   *         @arg @ref LL_RCC_MCO2_DIV_32
01890   *         @arg @ref LL_RCC_MCO2_DIV_64
01891   *         @arg @ref LL_RCC_MCO2_DIV_128
01892   *         @arg @ref LL_RCC_MCO2_DIV_256
01893   *         @arg @ref LL_RCC_MCO2_DIV_512
01894   *         @arg @ref LL_RCC_MCO2_DIV_1024
01895   * @retval None
01896   */
01897 __STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler)
01898 {
01899   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler);
01900 }
01901
01902 /**
01903   * @}
01904   */
01905 #endif /* RCC_MCO2_SUPPORT */
01906
01907 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
01908   * @{
01909   */
01910
01911 /**
01912   * @brief  Configure USARTx clock source
01913   * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
01914   * @param  USARTxSource This parameter can be one of the following values:
01915   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
01916   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
01917   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
01918   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
01919   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
01920   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
01921   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
01922   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
01923   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
01924   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
01925   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
01926   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
01927   *
01928   *         (*) value not defined in all devices.
01929   * @retval None
01930   */
01931 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
01932 {
01933   MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
01934 }
01935
01936 #if defined(LPUART1)
01937 /**
01938   * @brief  Configure LPUARTx clock source
01939   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
01940   * @rmtoll CCIPR        LPUART2SEL    LL_RCC_SetLPUARTClockSource
01941   * @param  LPUARTxSource This parameter can be one of the following values:
01942   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
01943   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
01944   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
01945   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
01946   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
01947   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
01948   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*)
01949   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*)
01950   * (*) feature not available on all devices
01951   * @retval None
01952   */
01953 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
01954 {
01955   MODIFY_REG(RCC->CCIPR, (LPUARTxSource >> 16U), (LPUARTxSource & 0x0000FFFFU));
01956 }
01957 #endif /* LPUART1 */
01958
01959 /**
01960   * @brief  Configure I2Cx clock source
01961   * @rmtoll CCIPR        I2C1SEL       LL_RCC_SetI2CClockSource
01962   * @param  I2CxSource This parameter can be one of the following values:
01963   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
01964   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
01965   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
01966   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
01967   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
01968   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
01969   *         (*) value not defined in all devices.
01970   * @retval None
01971   */
01972 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
01973 {
01974   MODIFY_REG(RCC->CCIPR, (I2CxSource >> 16U), (I2CxSource & 0x0000FFFFU));
01975 }
01976
01977 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
01978 /**
01979   * @brief  Configure TIMx clock source
01980   * @rmtoll CCIPR        TIMxSEL       LL_RCC_SetTIMClockSource
01981   * @param  TIMxSource This parameter can be one of the following values:
01982   *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
01983   *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
01984   * @if defined(STM32G081xx)
01985   *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL
01986   *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
01987   * @endif
01988   * @retval None
01989   */
01990 __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
01991 {
01992   MODIFY_REG(RCC->CCIPR, (TIMxSource & 0xFFFF0000U), (TIMxSource << 16));
01993 }
01994 #endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */
01995
01996 #if defined(LPTIM1) && defined(LPTIM2)
01997 /**
01998   * @brief  Configure LPTIMx clock source
01999   * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource
02000   * @param  LPTIMxSource This parameter can be one of the following values:
02001   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
02002   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
02003   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
02004   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
02005   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
02006   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
02007   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
02008   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
02009   * @retval None
02010   */
02011 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
02012 {
02013   MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
02014 }
02015 #endif /* LPTIM1 && LPTIM2 */
02016
02017 #if defined(CEC)
02018 /**
02019   * @brief  Configure CEC clock source
02020   * @rmtoll CCIPR        CECSEL        LL_RCC_SetCECClockSource
02021   * @param  CECxSource This parameter can be one of the following values:
02022   *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
02023   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
02024   * @retval None
02025   */
02026 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
02027 {
02028   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, CECxSource);
02029 }
02030 #endif /* CEC */
02031
02032 #if defined(RCC_CCIPR_RNGDIV)
02033 /**
02034   * @brief  Configure RNG division factor
02035   * @rmtoll CCIPR        RNGDIV        LL_RCC_SetRNGClockDiv
02036   * @param  RNGxDiv This parameter can be one of the following values:
02037   *         @arg @ref LL_RCC_RNG_CLK_DIV1
02038   *         @arg @ref LL_RCC_RNG_CLK_DIV2
02039   *         @arg @ref LL_RCC_RNG_CLK_DIV4
02040   *         @arg @ref LL_RCC_RNG_CLK_DIV8
02041   * @retval None
02042   */
02043 __STATIC_INLINE void LL_RCC_SetRNGClockDiv(uint32_t RNGxDiv)
02044 {
02045   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, RNGxDiv);
02046 }
02047 #endif /* RNG */
02048
02049 #if defined (RCC_CCIPR_RNGSEL)
02050 /**
02051   * @brief  Configure RNG clock source
02052   * @rmtoll CCIPR        RNGSEL        LL_RCC_SetRNGClockSource
02053   * @param  RNGxSource This parameter can be one of the following values:
02054   *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
02055   *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8
02056   *         @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK
02057   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
02058   * @retval None
02059   */
02060 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
02061 {
02062   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
02063 }
02064 #endif /* RNG */
02065
02066 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
02067 /**
02068   * @brief  Configure USB clock source
02069   * @rmtoll CCIPR2        CK48MSEL      LL_RCC_SetUSBClockSource
02070   * @param  USBxSource This parameter can be one of the following values:
02071   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
02072   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSE
02073   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
02074   *
02075   *         (*) value not defined in all devices.
02076   * @retval None
02077   */
02078 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
02079 {
02080   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, USBxSource);
02081 }
02082 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
02083
02084 #if defined (FDCAN1) || defined (FDCAN2)
02085 /**
02086   * @brief  Configure FDCAN clock source
02087   * @rmtoll CCIPR2        FDCANSEL        LL_RCC_SetFDCANClockSource
02088   * @param  FDCANxSource This parameter can be one of the following values:
02089   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
02090   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
02091   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
02092   * @retval None
02093   */
02094 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
02095 {
02096   MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, FDCANxSource);
02097 }
02098 #endif /* FDCAN1 || FDCAN2 */
02099
02100 /**
02101   * @brief  Configure ADC clock source
02102   * @rmtoll CCIPR        ADCSEL        LL_RCC_SetADCClockSource
02103   * @param  ADCxSource This parameter can be one of the following values:
02104   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
02105   *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
02106   *         @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
02107   * @retval None
02108   */
02109 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
02110 {
02111   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
02112 }
02113
02114 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
02115 /**
02116   * @brief  Configure I2Sx clock source
02117   * @rmtoll CCIPR2        I2SxSEL       LL_RCC_SetI2SClockSource
02118   * @param  I2SxSource This parameter can be one of the following values:
02119   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
02120   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
02121   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
02122   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
02123   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
02124   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
02125   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
02126   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
02127   * @retval None
02128   */
02129 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
02130 {
02131   MODIFY_REG(RCC->CCIPR2, (I2SxSource >> 16U), (I2SxSource & 0x0000FFFFU));
02132 }
02133
02134 #else
02135 /**
02136   * @brief  Configure I2Sx clock source
02137   * @rmtoll CCIPR        I2S1SEL       LL_RCC_SetI2SClockSource
02138   * @param  I2SxSource This parameter can be one of the following values:
02139   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
02140   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
02141   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
02142   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
02143   * @retval None
02144   */
02145 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
02146 {
02147   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource);
02148 }
02149 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
02150
02151 /**
02152   * @brief  Get USARTx clock source
02153   * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
02154   * @param  USARTx This parameter can be one of the following values:
02155   *         @arg @ref LL_RCC_USART1_CLKSOURCE
02156   *         @arg @ref LL_RCC_USART2_CLKSOURCE
02157   *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)
02158   * @retval Returned value can be one of the following values:
02159   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
02160   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
02161   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
02162   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
02163   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
02164   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
02165   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
02166   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
02167   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
02168   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
02169   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
02170   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
02171   * (*) feature not available on all devices
02172   */
02173 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
02174 {
02175   return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
02176 }
02177
02178 #if defined (LPUART2) || defined (LPUART1)
02179 /**
02180   * @brief  Get LPUARTx clock source
02181   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource\n
02182   *         CCIPR        LPUART2SEL    LL_RCC_GetLPUARTClockSource
02183   * @param  LPUARTx This parameter can be one of the following values:
02184   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
02185   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE (*)
02186   * @retval Returned value can be one of the following values:
02187   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
02188   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
02189   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
02190   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
02191   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
02192   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
02193   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*)
02194   *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*)
02195   * (*) feature not available on all devices
02196   */
02197 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
02198 {
02199   return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx) | (LPUARTx << 16U));
02200 }
02201 #endif /* LPUART2 || LPUART1 */
02202
02203 /**
02204   * @brief  Get I2Cx clock source
02205   * @rmtoll CCIPR        I2C1SEL       LL_RCC_GetI2CClockSource\n
02206   *         CCIPR        I2C2SEL       LL_RCC_GetI2CClockSource
02207   * @param  I2Cx This parameter can be one of the following values:
02208   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
02209   *         @arg @ref LL_RCC_I2C2_CLKSOURCE
02210   * @retval Returned value can be one of the following values:
02211   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
02212   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
02213   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
02214   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
02215   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
02216   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
02217   */
02218 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
02219 {
02220   return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx) | (I2Cx << 16U));
02221 }
02222
02223 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
02224 /**
02225   * @brief  Get TIMx clock source
02226   * @rmtoll CCIPR        TIMxSEL       LL_RCC_GetTIMClockSource
02227   * @param  TIMx This parameter can be one of the following values:
02228   *         @arg @ref LL_RCC_TIM1_CLKSOURCE
02229   *         @arg @ref LL_RCC_TIM15_CLKSOURCE
02230   * @retval Returned value can be one of the following values:
02231   *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
02232   *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
02233   * @if defined(STM32G081xx)
02234   *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL
02235   *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
02236   * @endif
02237   */
02238 __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
02239 {
02240   return (uint32_t)((READ_BIT(RCC->CCIPR, TIMx) >> 16U) | TIMx);
02241 }
02242 #endif /* RCC_CCIPR_TIM1SEL || RCC_CCIPR_TIM15SEL */
02243
02244 #if defined(LPTIM1) && defined(LPTIM2)
02245 /**
02246   * @brief  Get LPTIMx clock source
02247   * @rmtoll CCIPR        LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
02248             CCIPR        LPTIM2SEL     LL_RCC_GetLPTIMClockSource
02249   * @param  LPTIMx This parameter can be one of the following values:
02250   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
02251   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
02252   * @retval Returned value can be one of the following values:
02253   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
02254   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
02255   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
02256   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
02257   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
02258   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
02259   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
02260   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
02261   */
02262 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
02263 {
02264   return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
02265 }
02266 #endif /* LPTIM1 && LPTIM2 */
02267
02268 #if defined (RCC_CCIPR_CECSEL)
02269 /**
02270   * @brief  Get CEC clock source
02271   * @rmtoll CCIPR        CECSEL        LL_RCC_GetCECClockSource
02272   * @param  CECx This parameter can be one of the following values:
02273   *         @arg @ref LL_RCC_CEC_CLKSOURCE
02274   * @retval Returned value can be one of the following values:
02275   *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
02276   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
02277   */
02278 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
02279 {
02280   return (uint32_t)(READ_BIT(RCC->CCIPR, CECx));
02281 }
02282 #endif /* CEC */
02283
02284 #if defined(RCC_CCIPR2_FDCANSEL)
02285 /**
02286   * @brief  Get FDCAN clock source
02287   * @rmtoll CCIPR2        FDCANSEL        LL_RCC_GetFDCANClockSource
02288   * @param  FDCANx This parameter can be one of the following values:
02289   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
02290   * @retval Returned value can be one of the following values:
02291   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
02292   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
02293   */
02294 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
02295 {
02296   return (uint32_t)(READ_BIT(RCC->CCIPR2, FDCANx));
02297 }
02298 #endif /* RCC_CCIPR2_FDCANSEL */
02299
02300 #if defined(RNG)
02301 /**
02302   * @brief  Get RNGx clock source
02303   * @rmtoll CCIPR        RNGSEL        LL_RCC_GetRNGClockSource
02304   * @param  RNGx This parameter can be one of the following values:
02305   *         @arg @ref LL_RCC_RNG_CLKSOURCE
02306   * @retval Returned value can be one of the following values:
02307   *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
02308   *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8
02309   *         @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK
02310   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
02311   */
02312 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
02313 {
02314   return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
02315 }
02316 #endif /* RNG */
02317
02318 #if defined(RNG)
02319 /**
02320   * @brief  Get RNGx clock division factor
02321   * @rmtoll CCIPR        RNGDIV        LL_RCC_GetRNGClockDiv
02322   * @retval Returned value can be one of the following values:
02323   *         @arg @ref LL_RCC_RNG_CLK_DIV1
02324   *         @arg @ref LL_RCC_RNG_CLK_DIV2
02325   *         @arg @ref LL_RCC_RNG_CLK_DIV4
02326   *         @arg @ref LL_RCC_RNG_CLK_DIV8
02327   */
02328 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockDiv(void)
02329 {
02330   return (uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV));
02331 }
02332 #endif /* RNG */
02333
02334 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
02335 /**
02336   * @brief  Get USBx clock source
02337   * @rmtoll CCIPR2        CK48MSEL        LL_RCC_GetUSBClockSource
02338   * @param  USBx This parameter can be one of the following values:
02339   *         @arg @ref LL_RCC_USB_CLKSOURCE
02340   * @retval Returned value can be one of the following values:
02341   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
02342   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
02343   */
02344 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
02345 {
02346   return (uint32_t)(READ_BIT(RCC->CCIPR2, USBx));
02347 }
02348 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
02349
02350 /**
02351   * @brief  Get ADCx clock source
02352   * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource
02353   * @param  ADCx This parameter can be one of the following values:
02354   *         @arg @ref LL_RCC_ADC_CLKSOURCE
02355   * @retval Returned value can be one of the following values:
02356   *         @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
02357   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
02358   *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
02359   */
02360 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
02361 {
02362   return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
02363 }
02364
02365 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
02366 /**
02367   * @brief  Get I2Sx clock source
02368   * @rmtoll CCIPR2        I2S1SEL     LL_RCC_GetI2SClockSource\n
02369   *         CCIPR2        I2S2SEL     LL_RCC_GetI2SClockSource
02370   * @param  I2Sx This parameter can be one of the following values:
02371   *         @arg @ref LL_RCC_I2S1_CLKSOURCE
02372   *         @arg @ref LL_RCC_I2S2_CLKSOURCE
02373   * @retval Returned value can be one of the following values:
02374   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
02375   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
02376   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
02377   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
02378   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
02379   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
02380   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
02381   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
02382   */
02383 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
02384 {
02385   return (uint32_t)(READ_BIT(RCC->CCIPR2, I2Sx) | (I2Sx << 16U));
02386 }
02387 #else
02388 /**
02389   * @brief  Get I2Sx clock source
02390   * @rmtoll CCIPR        I2S1SEL        LL_RCC_GetI2SClockSource
02391   * @param  I2Sx This parameter can be one of the following values:
02392   *         @arg @ref LL_RCC_I2S1_CLKSOURCE
02393   * @retval Returned value can be one of the following values:
02394   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
02395   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
02396   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
02397   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
02398   */
02399 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
02400 {
02401   return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
02402 }
02403 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
02404 /**
02405   * @}
02406   */
02407
02408 /** @defgroup RCC_LL_EF_RTC RTC
02409   * @{
02410   */
02411
02412 /**
02413   * @brief  Set RTC Clock Source
02414   * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
02415   *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
02416   *       set). The BDRST bit can be used to reset them.
02417   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
02418   * @param  Source This parameter can be one of the following values:
02419   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02420   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02421   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02422   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02423   * @retval None
02424   */
02425 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
02426 {
02427   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
02428 }
02429
02430 /**
02431   * @brief  Get RTC Clock Source
02432   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
02433   * @retval Returned value can be one of the following values:
02434   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02435   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02436   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02437   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02438   */
02439 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
02440 {
02441   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
02442 }
02443
02444 /**
02445   * @brief  Enable RTC
02446   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
02447   * @retval None
02448   */
02449 __STATIC_INLINE void LL_RCC_EnableRTC(void)
02450 {
02451   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02452 }
02453
02454 /**
02455   * @brief  Disable RTC
02456   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
02457   * @retval None
02458   */
02459 __STATIC_INLINE void LL_RCC_DisableRTC(void)
02460 {
02461   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02462 }
02463
02464 /**
02465   * @brief  Check if RTC has been enabled or not
02466   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
02467   * @retval State of bit (1 or 0).
02468   */
02469 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
02470 {
02471   return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
02472 }
02473
02474 /**
02475   * @brief  Force the Backup domain reset
02476   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
02477   * @retval None
02478   */
02479 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
02480 {
02481   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02482 }
02483
02484 /**
02485   * @brief  Release the Backup domain reset
02486   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
02487   * @retval None
02488   */
02489 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
02490 {
02491   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02492 }
02493
02494 /**
02495   * @}
02496   */
02497
02498
02499 /** @defgroup RCC_LL_EF_PLL PLL
02500   * @{
02501   */
02502
02503 /**
02504   * @brief  Enable PLL
02505   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
02506   * @retval None
02507   */
02508 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
02509 {
02510   SET_BIT(RCC->CR, RCC_CR_PLLON);
02511 }
02512
02513 /**
02514   * @brief  Disable PLL
02515   * @note Cannot be disabled if the PLL clock is used as the system clock
02516   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
02517   * @retval None
02518   */
02519 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
02520 {
02521   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
02522 }
02523
02524 /**
02525   * @brief  Check if PLL Ready
02526   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
02527   * @retval State of bit (1 or 0).
02528   */
02529 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
02530 {
02531   return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
02532 }
02533
02534 /**
02535   * @brief  Configure PLL used for SYSCLK Domain
02536   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
02537   * @note PLLN/PLLR can be written only when PLL is disabled
02538   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
02539   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
02540   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
02541   *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS
02542   * @param  Source This parameter can be one of the following values:
02543   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02544   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02545   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02546   * @param  PLLM This parameter can be one of the following values:
02547   *         @arg @ref LL_RCC_PLLM_DIV_1
02548   *         @arg @ref LL_RCC_PLLM_DIV_2
02549   *         @arg @ref LL_RCC_PLLM_DIV_3
02550   *         @arg @ref LL_RCC_PLLM_DIV_4
02551   *         @arg @ref LL_RCC_PLLM_DIV_5
02552   *         @arg @ref LL_RCC_PLLM_DIV_6
02553   *         @arg @ref LL_RCC_PLLM_DIV_7
02554   *         @arg @ref LL_RCC_PLLM_DIV_8
02555   * @param  PLLN Between 8 and 86
02556   * @param  PLLR This parameter can be one of the following values:
02557   *         @arg @ref LL_RCC_PLLR_DIV_2
02558   *         @arg @ref LL_RCC_PLLR_DIV_3
02559   *         @arg @ref LL_RCC_PLLR_DIV_4
02560   *         @arg @ref LL_RCC_PLLR_DIV_5
02561   *         @arg @ref LL_RCC_PLLR_DIV_6
02562   *         @arg @ref LL_RCC_PLLR_DIV_7
02563   *         @arg @ref LL_RCC_PLLR_DIV_8
02564   * @retval None
02565   */
02566 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
02567 {
02568   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
02569              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
02570 }
02571
02572 /**
02573   * @brief  Configure PLL used for ADC domain clock
02574   * @note   PLL Source and PLLM Divider can be written only when PLL is disabled
02575   * @note   PLLN/PLLP can be written only when PLL is disabled
02576   * @note   User shall verify whether the PLL configuration is not done through
02577   *         other functions (ex: I2S1)
02578   * @note   This can be selected for ADC
02579   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_ADC\n
02580   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_ADC\n
02581   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_ADC\n
02582   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_ADC
02583   * @param  Source This parameter can be one of the following values:
02584   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02585   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02586   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02587   * @param  PLLM This parameter can be one of the following values:
02588   *         @arg @ref LL_RCC_PLLM_DIV_1
02589   *         @arg @ref LL_RCC_PLLM_DIV_2
02590   *         @arg @ref LL_RCC_PLLM_DIV_3
02591   *         @arg @ref LL_RCC_PLLM_DIV_4
02592   *         @arg @ref LL_RCC_PLLM_DIV_5
02593   *         @arg @ref LL_RCC_PLLM_DIV_6
02594   *         @arg @ref LL_RCC_PLLM_DIV_7
02595   *         @arg @ref LL_RCC_PLLM_DIV_8
02596   * @param  PLLN Between 8 and 86
02597   * @param  PLLP This parameter can be one of the following values:
02598   *         @arg @ref LL_RCC_PLLP_DIV_2
02599   *         @arg @ref LL_RCC_PLLP_DIV_3
02600   *         @arg @ref LL_RCC_PLLP_DIV_4
02601   *         @arg @ref LL_RCC_PLLP_DIV_5
02602   *         @arg @ref LL_RCC_PLLP_DIV_6
02603   *         @arg @ref LL_RCC_PLLP_DIV_7
02604   *         @arg @ref LL_RCC_PLLP_DIV_8
02605   *         @arg @ref LL_RCC_PLLP_DIV_9
02606   *         @arg @ref LL_RCC_PLLP_DIV_10
02607   *         @arg @ref LL_RCC_PLLP_DIV_11
02608   *         @arg @ref LL_RCC_PLLP_DIV_12
02609   *         @arg @ref LL_RCC_PLLP_DIV_13
02610   *         @arg @ref LL_RCC_PLLP_DIV_14
02611   *         @arg @ref LL_RCC_PLLP_DIV_15
02612   *         @arg @ref LL_RCC_PLLP_DIV_16
02613   *         @arg @ref LL_RCC_PLLP_DIV_17
02614   *         @arg @ref LL_RCC_PLLP_DIV_18
02615   *         @arg @ref LL_RCC_PLLP_DIV_19
02616   *         @arg @ref LL_RCC_PLLP_DIV_20
02617   *         @arg @ref LL_RCC_PLLP_DIV_21
02618   *         @arg @ref LL_RCC_PLLP_DIV_22
02619   *         @arg @ref LL_RCC_PLLP_DIV_23
02620   *         @arg @ref LL_RCC_PLLP_DIV_24
02621   *         @arg @ref LL_RCC_PLLP_DIV_25
02622   *         @arg @ref LL_RCC_PLLP_DIV_26
02623   *         @arg @ref LL_RCC_PLLP_DIV_27
02624   *         @arg @ref LL_RCC_PLLP_DIV_28
02625   *         @arg @ref LL_RCC_PLLP_DIV_29
02626   *         @arg @ref LL_RCC_PLLP_DIV_30
02627   *         @arg @ref LL_RCC_PLLP_DIV_31
02628   *         @arg @ref LL_RCC_PLLP_DIV_32
02629   * @retval None
02630   */
02631 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
02632 {
02633   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
02634              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
02635 }
02636
02637 /**
02638   * @brief  Configure PLL used for I2S1 domain clock
02639   * @note   PLL Source and PLLM Divider can be written only when PLL is disabled
02640   * @note   PLLN/PLLP can be written only when PLL is disabled
02641   * @note   User shall verify whether the PLL configuration is not done through
02642   *         other functions (ex: ADC)
02643   * @note   This can be selected for I2S1
02644   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S1\n
02645   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S1\n
02646   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S1\n
02647   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_I2S1
02648   * @param  Source This parameter can be one of the following values:
02649   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02650   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02651   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02652   * @param  PLLM This parameter can be one of the following values:
02653   *         @arg @ref LL_RCC_PLLM_DIV_1
02654   *         @arg @ref LL_RCC_PLLM_DIV_2
02655   *         @arg @ref LL_RCC_PLLM_DIV_3
02656   *         @arg @ref LL_RCC_PLLM_DIV_4
02657   *         @arg @ref LL_RCC_PLLM_DIV_5
02658   *         @arg @ref LL_RCC_PLLM_DIV_6
02659   *         @arg @ref LL_RCC_PLLM_DIV_7
02660   *         @arg @ref LL_RCC_PLLM_DIV_8
02661   * @param  PLLN Between 8 and 86
02662   * @param  PLLP This parameter can be one of the following values:
02663   *         @arg @ref LL_RCC_PLLP_DIV_2
02664   *         @arg @ref LL_RCC_PLLP_DIV_3
02665   *         @arg @ref LL_RCC_PLLP_DIV_4
02666   *         @arg @ref LL_RCC_PLLP_DIV_5
02667   *         @arg @ref LL_RCC_PLLP_DIV_6
02668   *         @arg @ref LL_RCC_PLLP_DIV_7
02669   *         @arg @ref LL_RCC_PLLP_DIV_8
02670   *         @arg @ref LL_RCC_PLLP_DIV_9
02671   *         @arg @ref LL_RCC_PLLP_DIV_10
02672   *         @arg @ref LL_RCC_PLLP_DIV_11
02673   *         @arg @ref LL_RCC_PLLP_DIV_12
02674   *         @arg @ref LL_RCC_PLLP_DIV_13
02675   *         @arg @ref LL_RCC_PLLP_DIV_14
02676   *         @arg @ref LL_RCC_PLLP_DIV_15
02677   *         @arg @ref LL_RCC_PLLP_DIV_16
02678   *         @arg @ref LL_RCC_PLLP_DIV_17
02679   *         @arg @ref LL_RCC_PLLP_DIV_18
02680   *         @arg @ref LL_RCC_PLLP_DIV_19
02681   *         @arg @ref LL_RCC_PLLP_DIV_20
02682   *         @arg @ref LL_RCC_PLLP_DIV_21
02683   *         @arg @ref LL_RCC_PLLP_DIV_22
02684   *         @arg @ref LL_RCC_PLLP_DIV_23
02685   *         @arg @ref LL_RCC_PLLP_DIV_24
02686   *         @arg @ref LL_RCC_PLLP_DIV_25
02687   *         @arg @ref LL_RCC_PLLP_DIV_26
02688   *         @arg @ref LL_RCC_PLLP_DIV_27
02689   *         @arg @ref LL_RCC_PLLP_DIV_28
02690   *         @arg @ref LL_RCC_PLLP_DIV_29
02691   *         @arg @ref LL_RCC_PLLP_DIV_30
02692   *         @arg @ref LL_RCC_PLLP_DIV_31
02693   *         @arg @ref LL_RCC_PLLP_DIV_32
02694   * @retval None
02695   */
02696 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
02697 {
02698   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
02699              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
02700 }
02701
02702 #if defined(RCC_CCIPR2_I2S2SEL)
02703 /**
02704   * @brief  Configure PLL used for I2S2 domain clock
02705   * @note   PLL Source and PLLM Divider can be written only when PLL is disabled
02706   * @note   PLLN/PLLP can be written only when PLL is disabled
02707   * @note   User shall verify whether the PLL configuration is not done through
02708   *         other functions (ex: ADC)
02709   * @note   This can be selected for I2S2
02710   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S2\n
02711   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S2\n
02712   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S2\n
02713   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_I2S2
02714   * @param  Source This parameter can be one of the following values:
02715   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02716   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02717   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02718   * @param  PLLM This parameter can be one of the following values:
02719   *         @arg @ref LL_RCC_PLLM_DIV_1
02720   *         @arg @ref LL_RCC_PLLM_DIV_2
02721   *         @arg @ref LL_RCC_PLLM_DIV_3
02722   *         @arg @ref LL_RCC_PLLM_DIV_4
02723   *         @arg @ref LL_RCC_PLLM_DIV_5
02724   *         @arg @ref LL_RCC_PLLM_DIV_6
02725   *         @arg @ref LL_RCC_PLLM_DIV_7
02726   *         @arg @ref LL_RCC_PLLM_DIV_8
02727   * @param  PLLN Between 8 and 86
02728   * @param  PLLP This parameter can be one of the following values:
02729   *         @arg @ref LL_RCC_PLLP_DIV_2
02730   *         @arg @ref LL_RCC_PLLP_DIV_3
02731   *         @arg @ref LL_RCC_PLLP_DIV_4
02732   *         @arg @ref LL_RCC_PLLP_DIV_5
02733   *         @arg @ref LL_RCC_PLLP_DIV_6
02734   *         @arg @ref LL_RCC_PLLP_DIV_7
02735   *         @arg @ref LL_RCC_PLLP_DIV_8
02736   *         @arg @ref LL_RCC_PLLP_DIV_9
02737   *         @arg @ref LL_RCC_PLLP_DIV_10
02738   *         @arg @ref LL_RCC_PLLP_DIV_11
02739   *         @arg @ref LL_RCC_PLLP_DIV_12
02740   *         @arg @ref LL_RCC_PLLP_DIV_13
02741   *         @arg @ref LL_RCC_PLLP_DIV_14
02742   *         @arg @ref LL_RCC_PLLP_DIV_15
02743   *         @arg @ref LL_RCC_PLLP_DIV_16
02744   *         @arg @ref LL_RCC_PLLP_DIV_17
02745   *         @arg @ref LL_RCC_PLLP_DIV_18
02746   *         @arg @ref LL_RCC_PLLP_DIV_19
02747   *         @arg @ref LL_RCC_PLLP_DIV_20
02748   *         @arg @ref LL_RCC_PLLP_DIV_21
02749   *         @arg @ref LL_RCC_PLLP_DIV_22
02750   *         @arg @ref LL_RCC_PLLP_DIV_23
02751   *         @arg @ref LL_RCC_PLLP_DIV_24
02752   *         @arg @ref LL_RCC_PLLP_DIV_25
02753   *         @arg @ref LL_RCC_PLLP_DIV_26
02754   *         @arg @ref LL_RCC_PLLP_DIV_27
02755   *         @arg @ref LL_RCC_PLLP_DIV_28
02756   *         @arg @ref LL_RCC_PLLP_DIV_29
02757   *         @arg @ref LL_RCC_PLLP_DIV_30
02758   *         @arg @ref LL_RCC_PLLP_DIV_31
02759   *         @arg @ref LL_RCC_PLLP_DIV_32
02760   * @retval None
02761   */
02762 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S2(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
02763 {
02764   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
02765              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
02766 }
02767 #endif /* RCC_CCIPR2_I2S2SEL */
02768
02769 #if defined(RNG)
02770 /**
02771   * @brief  Configure PLL used for RNG domain clock
02772   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
02773   * @note PLLN/PLLQ can be written only when PLL is disabled
02774   * @note   User shall verify whether the PLL configuration is not done through
02775   *         other functions (ex: TIM1, TIM15)
02776   * @note This  can be selected for RNG
02777   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_RNG\n
02778   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_RNG\n
02779   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_RNG\n
02780   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_RNG
02781   * @param  Source This parameter can be one of the following values:
02782   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02783   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02784   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02785   * @param  PLLM This parameter can be one of the following values:
02786   *         @arg @ref LL_RCC_PLLM_DIV_1
02787   *         @arg @ref LL_RCC_PLLM_DIV_2
02788   *         @arg @ref LL_RCC_PLLM_DIV_3
02789   *         @arg @ref LL_RCC_PLLM_DIV_4
02790   *         @arg @ref LL_RCC_PLLM_DIV_5
02791   *         @arg @ref LL_RCC_PLLM_DIV_6
02792   *         @arg @ref LL_RCC_PLLM_DIV_7
02793   *         @arg @ref LL_RCC_PLLM_DIV_8
02794   * @param  PLLN Between 8 and 86
02795   * @param  PLLQ This parameter can be one of the following values:
02796   *         @arg @ref LL_RCC_PLLQ_DIV_2
02797   *         @arg @ref LL_RCC_PLLQ_DIV_3
02798   *         @arg @ref LL_RCC_PLLQ_DIV_4
02799   *         @arg @ref LL_RCC_PLLQ_DIV_5
02800   *         @arg @ref LL_RCC_PLLQ_DIV_6
02801   *         @arg @ref LL_RCC_PLLQ_DIV_7
02802   *         @arg @ref LL_RCC_PLLQ_DIV_8
02803   * @retval None
02804   */
02805 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02806 {
02807   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
02808              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
02809 }
02810 #endif /* RNG */
02811
02812 #if defined(FDCAN1) || defined(FDCAN2)
02813 /**
02814   * @brief  Configure PLL used for FDCAN domain clock
02815   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
02816   * @note PLLN/PLLQ can be written only when PLL is disabled
02817   * @note   User shall verify whether the PLL configuration is not done through
02818   *         other functions (ex: TIM1, TIM15)
02819   * @note This  can be selected for FDCAN
02820   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_FDCAN\n
02821   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_FDCAN\n
02822   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_FDCAN\n
02823   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_FDCAN
02824   * @param  Source This parameter can be one of the following values:
02825   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02826   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02827   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02828   * @param  PLLM This parameter can be one of the following values:
02829   *         @arg @ref LL_RCC_PLLM_DIV_1
02830   *         @arg @ref LL_RCC_PLLM_DIV_2
02831   *         @arg @ref LL_RCC_PLLM_DIV_3
02832   *         @arg @ref LL_RCC_PLLM_DIV_4
02833   *         @arg @ref LL_RCC_PLLM_DIV_5
02834   *         @arg @ref LL_RCC_PLLM_DIV_6
02835   *         @arg @ref LL_RCC_PLLM_DIV_7
02836   *         @arg @ref LL_RCC_PLLM_DIV_8
02837   * @param  PLLN Between 8 and 86
02838   * @param  PLLQ This parameter can be one of the following values:
02839   *         @arg @ref LL_RCC_PLLQ_DIV_2
02840   *         @arg @ref LL_RCC_PLLQ_DIV_3
02841   *         @arg @ref LL_RCC_PLLQ_DIV_4
02842   *         @arg @ref LL_RCC_PLLQ_DIV_5
02843   *         @arg @ref LL_RCC_PLLQ_DIV_6
02844   *         @arg @ref LL_RCC_PLLQ_DIV_7
02845   *         @arg @ref LL_RCC_PLLQ_DIV_8
02846   * @retval None
02847   */
02848 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_FDCAN(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02849 {
02850   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
02851              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
02852 }
02853 #endif /* FDCAN1 || FDCAN2 */
02854
02855 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
02856 /**
02857   * @brief  Configure PLL used for USB domain clock
02858   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
02859   * @note PLLN/PLLQ can be written only when PLL is disabled
02860   * @note   User shall verify whether the PLL configuration is not done through
02861   *         other functions (ex: TIM1, TIM15)
02862   * @note This  can be selected for USB
02863   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_USB\n
02864   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_USB\n
02865   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_USB\n
02866   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_USB
02867   * @param  Source This parameter can be one of the following values:
02868   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02869   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02870   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02871   * @param  PLLM This parameter can be one of the following values:
02872   *         @arg @ref LL_RCC_PLLM_DIV_1
02873   *         @arg @ref LL_RCC_PLLM_DIV_2
02874   *         @arg @ref LL_RCC_PLLM_DIV_3
02875   *         @arg @ref LL_RCC_PLLM_DIV_4
02876   *         @arg @ref LL_RCC_PLLM_DIV_5
02877   *         @arg @ref LL_RCC_PLLM_DIV_6
02878   *         @arg @ref LL_RCC_PLLM_DIV_7
02879   *         @arg @ref LL_RCC_PLLM_DIV_8
02880   * @param  PLLN Between 8 and 86
02881   * @param  PLLQ This parameter can be one of the following values:
02882   *         @arg @ref LL_RCC_PLLQ_DIV_2
02883   *         @arg @ref LL_RCC_PLLQ_DIV_3
02884   *         @arg @ref LL_RCC_PLLQ_DIV_4
02885   *         @arg @ref LL_RCC_PLLQ_DIV_5
02886   *         @arg @ref LL_RCC_PLLQ_DIV_6
02887   *         @arg @ref LL_RCC_PLLQ_DIV_7
02888   *         @arg @ref LL_RCC_PLLQ_DIV_8
02889   * @retval None
02890   */
02891 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_USB(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02892 {
02893   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
02894              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
02895 }
02896 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
02897
02898 #if defined(RCC_PLLQ_SUPPORT)
02899 /**
02900   * @brief  Configure PLL used for TIM1 domain clock
02901   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
02902   * @note PLLN/PLLQ can be written only when PLL is disabled
02903   * @note   User shall verify whether the PLL configuration is not done through
02904   *         other functions (ex: RNG, TIM15)
02905   * @note This  can be selected for TIM1
02906   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_TIM1\n
02907   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_TIM1\n
02908   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_TIM1\n
02909   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_TIM1
02910   * @param  Source This parameter can be one of the following values:
02911   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02912   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02913   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02914   * @param  PLLM This parameter can be one of the following values:
02915   *         @arg @ref LL_RCC_PLLM_DIV_1
02916   *         @arg @ref LL_RCC_PLLM_DIV_2
02917   *         @arg @ref LL_RCC_PLLM_DIV_3
02918   *         @arg @ref LL_RCC_PLLM_DIV_4
02919   *         @arg @ref LL_RCC_PLLM_DIV_5
02920   *         @arg @ref LL_RCC_PLLM_DIV_6
02921   *         @arg @ref LL_RCC_PLLM_DIV_7
02922   *         @arg @ref LL_RCC_PLLM_DIV_8
02923   * @param  PLLN Between 8 and 86
02924   * @param  PLLQ This parameter can be one of the following values:
02925   *         @arg @ref LL_RCC_PLLQ_DIV_2
02926   *         @arg @ref LL_RCC_PLLQ_DIV_3
02927   *         @arg @ref LL_RCC_PLLQ_DIV_4
02928   *         @arg @ref LL_RCC_PLLQ_DIV_5
02929   *         @arg @ref LL_RCC_PLLQ_DIV_6
02930   *         @arg @ref LL_RCC_PLLQ_DIV_7
02931   *         @arg @ref LL_RCC_PLLQ_DIV_8
02932   * @retval None
02933   */
02934 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02935 {
02936   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
02937              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
02938 }
02939 #endif /* RCC_PLLQ_SUPPORT */
02940
02941 #if defined(RCC_PLLQ_SUPPORT) && defined(TIM15)
02942 /**
02943   * @brief  Configure PLL used for TIM15 domain clock
02944   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
02945   * @note PLLN/PLLQ can be written only when PLL is disabled
02946   * @note   User shall verify whether the PLL configuration is not done through
02947   *         other functions (ex: RNG, TIM1)
02948   * @note This  can be selected for TIM15
02949   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_TIM15\n
02950   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_TIM15\n
02951   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_TIM15\n
02952   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_TIM15
02953   * @param  Source This parameter can be one of the following values:
02954   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02955   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02956   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02957   * @param  PLLM This parameter can be one of the following values:
02958   *         @arg @ref LL_RCC_PLLM_DIV_1
02959   *         @arg @ref LL_RCC_PLLM_DIV_2
02960   *         @arg @ref LL_RCC_PLLM_DIV_3
02961   *         @arg @ref LL_RCC_PLLM_DIV_4
02962   *         @arg @ref LL_RCC_PLLM_DIV_5
02963   *         @arg @ref LL_RCC_PLLM_DIV_6
02964   *         @arg @ref LL_RCC_PLLM_DIV_7
02965   *         @arg @ref LL_RCC_PLLM_DIV_8
02966   * @param  PLLN Between 8 and 86
02967   * @param  PLLQ This parameter can be one of the following values:
02968   *         @arg @ref LL_RCC_PLLQ_DIV_2
02969   *         @arg @ref LL_RCC_PLLQ_DIV_3
02970   *         @arg @ref LL_RCC_PLLQ_DIV_4
02971   *         @arg @ref LL_RCC_PLLQ_DIV_5
02972   *         @arg @ref LL_RCC_PLLQ_DIV_6
02973   *         @arg @ref LL_RCC_PLLQ_DIV_7
02974   *         @arg @ref LL_RCC_PLLQ_DIV_8
02975   * @retval None
02976   */
02977 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM15(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02978 {
02979   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
02980              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
02981 }
02982 #endif /* RCC_PLLQ_SUPPORT && TIM15 */
02983
02984 /**
02985   * @brief  Get Main PLL multiplication factor for VCO
02986   * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
02987   * @retval Between 8 and 86
02988   */
02989 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
02990 {
02991   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
02992 }
02993
02994 /**
02995   * @brief  Get Main PLL division factor for PLLP
02996   * @note   used for PLLPCLK (ADC & I2S clock)
02997   * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
02998   * @retval Returned value can be one of the following values:
02999   *         @arg @ref LL_RCC_PLLP_DIV_2
03000   *         @arg @ref LL_RCC_PLLP_DIV_3
03001   *         @arg @ref LL_RCC_PLLP_DIV_4
03002   *         @arg @ref LL_RCC_PLLP_DIV_5
03003   *         @arg @ref LL_RCC_PLLP_DIV_6
03004   *         @arg @ref LL_RCC_PLLP_DIV_7
03005   *         @arg @ref LL_RCC_PLLP_DIV_8
03006   *         @arg @ref LL_RCC_PLLP_DIV_9
03007   *         @arg @ref LL_RCC_PLLP_DIV_10
03008   *         @arg @ref LL_RCC_PLLP_DIV_11
03009   *         @arg @ref LL_RCC_PLLP_DIV_12
03010   *         @arg @ref LL_RCC_PLLP_DIV_13
03011   *         @arg @ref LL_RCC_PLLP_DIV_14
03012   *         @arg @ref LL_RCC_PLLP_DIV_15
03013   *         @arg @ref LL_RCC_PLLP_DIV_16
03014   *         @arg @ref LL_RCC_PLLP_DIV_17
03015   *         @arg @ref LL_RCC_PLLP_DIV_18
03016   *         @arg @ref LL_RCC_PLLP_DIV_19
03017   *         @arg @ref LL_RCC_PLLP_DIV_20
03018   *         @arg @ref LL_RCC_PLLP_DIV_21
03019   *         @arg @ref LL_RCC_PLLP_DIV_22
03020   *         @arg @ref LL_RCC_PLLP_DIV_23
03021   *         @arg @ref LL_RCC_PLLP_DIV_24
03022   *         @arg @ref LL_RCC_PLLP_DIV_25
03023   *         @arg @ref LL_RCC_PLLP_DIV_26
03024   *         @arg @ref LL_RCC_PLLP_DIV_27
03025   *         @arg @ref LL_RCC_PLLP_DIV_28
03026   *         @arg @ref LL_RCC_PLLP_DIV_29
03027   *         @arg @ref LL_RCC_PLLP_DIV_30
03028   *         @arg @ref LL_RCC_PLLP_DIV_31
03029   *         @arg @ref LL_RCC_PLLP_DIV_32
03030   */
03031 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
03032 {
03033   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
03034 }
03035
03036 #if defined(RCC_PLLQ_SUPPORT)
03037 /**
03038   * @brief  Get Main PLL division factor for PLLQ
03039   * @note used for PLLQCLK selected for RNG, TIM1, TIM15 clock
03040   * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
03041   * @retval Returned value can be one of the following values:
03042   *         @arg @ref LL_RCC_PLLQ_DIV_2
03043   *         @arg @ref LL_RCC_PLLQ_DIV_3
03044   *         @arg @ref LL_RCC_PLLQ_DIV_4
03045   *         @arg @ref LL_RCC_PLLQ_DIV_5
03046   *         @arg @ref LL_RCC_PLLQ_DIV_6
03047   *         @arg @ref LL_RCC_PLLQ_DIV_7
03048   *         @arg @ref LL_RCC_PLLQ_DIV_8
03049   */
03050 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
03051 {
03052   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
03053 }
03054 #endif /* RCC_PLLQ_SUPPORT */
03055
03056 /**
03057   * @brief  Get Main PLL division factor for PLLR
03058   * @note used for PLLCLK (system clock)
03059   * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
03060   * @retval Returned value can be one of the following values:
03061   *         @arg @ref LL_RCC_PLLR_DIV_2
03062   *         @arg @ref LL_RCC_PLLR_DIV_3
03063   *         @arg @ref LL_RCC_PLLR_DIV_4
03064   *         @arg @ref LL_RCC_PLLR_DIV_5
03065   *         @arg @ref LL_RCC_PLLR_DIV_6
03066   *         @arg @ref LL_RCC_PLLR_DIV_7
03067   *         @arg @ref LL_RCC_PLLR_DIV_8
03068   */
03069 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
03070 {
03071   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
03072 }
03073
03074 /**
03075   * @brief  Configure PLL clock source
03076   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
03077   * @param PLLSource This parameter can be one of the following values:
03078   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03079   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03080   * @retval None
03081   */
03082 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
03083 {
03084   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
03085 }
03086
03087 /**
03088   * @brief  Get the oscillator used as PLL clock source.
03089   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
03090   * @retval Returned value can be one of the following values:
03091   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03092   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03093   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03094   */
03095 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
03096 {
03097   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
03098 }
03099
03100 /**
03101   * @brief  Get Division factor for the main PLL and other PLL
03102   * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
03103   * @retval Returned value can be one of the following values:
03104   *         @arg @ref LL_RCC_PLLM_DIV_1
03105   *         @arg @ref LL_RCC_PLLM_DIV_2
03106   *         @arg @ref LL_RCC_PLLM_DIV_3
03107   *         @arg @ref LL_RCC_PLLM_DIV_4
03108   *         @arg @ref LL_RCC_PLLM_DIV_5
03109   *         @arg @ref LL_RCC_PLLM_DIV_6
03110   *         @arg @ref LL_RCC_PLLM_DIV_7
03111   *         @arg @ref LL_RCC_PLLM_DIV_8
03112   */
03113 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
03114 {
03115   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
03116 }
03117
03118 /**
03119   * @brief  Enable PLL output mapped on ADC domain clock
03120   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_ADC
03121   * @note   User shall check that PLL enable is not done through
03122   *         other functions (ex: I2S1)
03123   * @retval None
03124   */
03125 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
03126 {
03127   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03128 }
03129
03130 /**
03131   * @brief  Disable PLL output mapped on ADC domain clock
03132   * @note Cannot be disabled if the PLL clock is used as the system clock
03133   * @note   User shall check that PLL is not used by any other peripheral
03134   *         (ex: I2S1)
03135   * @note In order to save power, when the PLLCLK  of the PLL is
03136   *       not used,  should be 0
03137   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_ADC
03138   * @retval None
03139   */
03140 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
03141 {
03142   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03143 }
03144
03145 /**
03146   * @brief  Check if PLL output mapped on ADC domain clock is enabled
03147   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_IsEnabledDomain_ADC
03148   * @retval State of bit (1 or 0).
03149   */
03150 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
03151 {
03152   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
03153 }
03154
03155 /**
03156   * @brief  Enable PLL output mapped on I2S domain clock
03157   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_I2S1
03158   * @note   User shall check that PLL enable is not done through
03159   *         other functions (ex: ADC)
03160   * @retval None
03161   */
03162 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1(void)
03163 {
03164   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03165 }
03166
03167 #if defined(RCC_CCIPR2_I2S2SEL)
03168 /**
03169   * @brief  Enable PLL output mapped on I2S2 domain clock
03170   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_I2S2
03171   * @note   User shall check that PLL enable is not done through
03172   *         other functions (ex: ADC)
03173   * @retval None
03174   */
03175 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S2(void)
03176 {
03177   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03178 }
03179 #endif /* RCC_CCIPR2_I2S2SEL */
03180
03181 /**
03182   * @brief  Disable PLL output mapped on I2S1 domain clock
03183   * @note Cannot be disabled if the PLL clock is used as the system clock
03184   * @note   User shall check that PLL is not used by any other peripheral
03185   *         (ex: RNG)
03186   * @note In order to save power, when the PLLCLK  of the PLL is
03187   *       not used,  should be 0
03188   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_I2S1
03189   * @retval None
03190   */
03191 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S1(void)
03192 {
03193   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03194 }
03195
03196 /**
03197   * @brief  Check if PLL output mapped on I2S1 domain clock is enabled
03198   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_IsEnabledDomain_I2S1
03199   * @retval State of bit (1 or 0).
03200   */
03201 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S1(void)
03202 {
03203   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
03204 }
03205
03206 #if defined(RCC_CCIPR2_I2S2SEL)
03207 /**
03208   * @brief  Disable PLL output mapped on I2S2 domain clock
03209   * @note Cannot be disabled if the PLL clock is used as the system clock
03210   * @note   User shall check that PLL is not used by any other peripheral
03211   *         (ex: RNG)
03212   * @note In order to save power, when the PLLCLK  of the PLL is
03213   *       not used,  should be 0
03214   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_I2S2
03215   * @retval None
03216   */
03217 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S2(void)
03218 {
03219   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03220 }
03221
03222 /**
03223   * @brief  Check if PLL output mapped on I2S2 domain clock is enabled
03224   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_IsEnabledDomain_I2S2
03225   * @retval State of bit (1 or 0).
03226   */
03227 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S2(void)
03228 {
03229   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
03230 }
03231 #endif /* RCC_CCIPR2_I2S2SEL */
03232
03233 #if defined(RNG)
03234 /**
03235   * @brief  Enable PLL output mapped on RNG domain clock
03236   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_RNG
03237   * @note   User shall check that PLL enable is not done through
03238   *         other functions (ex: TIM1, TIM15)
03239   * @retval None
03240   */
03241 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void)
03242 {
03243   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03244 }
03245
03246 /**
03247   * @brief  Disable PLL output mapped on RNG domain clock
03248   * @note Cannot be disabled if the PLL clock is used as the system clock
03249   * @note   User shall check that PLL is not used by any other peripheral
03250   *         (ex: TIM, TIM15)
03251   * @note In order to save power, when the PLLCLK  of the PLL is
03252   *       not used,  should be 0
03253   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_RNG
03254   * @retval None
03255   */
03256 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void)
03257 {
03258   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03259 }
03260
03261 /**
03262   * @brief  Check if PLL output mapped on RNG domain clock is enabled
03263   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_IsEnabledDomain_RNG
03264   * @retval State of bit (1 or 0).
03265   */
03266 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_RNG(void)
03267 {
03268   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
03269 }
03270 #endif /* RNG */
03271
03272 #if defined(FDCAN1) || defined(FDCAN2)
03273 /**
03274   * @brief  Enable PLL output mapped on FDCAN domain clock
03275   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_FDCAN
03276   * @note   User shall check that PLL enable is not done through
03277   *         other functions (ex: TIM1, TIM15)
03278   * @retval None
03279   */
03280 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_FDCAN(void)
03281 {
03282   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03283 }
03284
03285 /**
03286   * @brief  Disable PLL output mapped on FDCAN domain clock
03287   * @note Cannot be disabled if the PLL clock is used as the system clock
03288   * @note   User shall check that PLL is not used by any other peripheral
03289   *         (ex: TIM, TIM15)
03290   * @note In order to save power, when the PLLCLK  of the PLL is
03291   *       not used,  should be 0
03292   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_FDCAN
03293   * @retval None
03294   */
03295 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_FDCAN(void)
03296 {
03297   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03298 }
03299
03300 /**
03301   * @brief  Check if PLL output mapped on FDCAN domain clock is enabled
03302   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_IsEnabledDomain_FDCAN
03303   * @retval State of bit (1 or 0).
03304   */
03305 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_FDCAN(void)
03306 {
03307   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
03308 }
03309 #endif /* FDCAN1 || FDCAN2 */
03310
03311 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
03312 /**
03313   * @brief  Enable PLL output mapped on USB domain clock
03314   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_USB
03315   * @note   User shall check that PLL enable is not done through
03316   *         other functions (ex: TIM1, TIM15)
03317   * @retval None
03318   */
03319 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_USB(void)
03320 {
03321   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03322 }
03323
03324 /**
03325   * @brief  Disable PLL output mapped on USB domain clock
03326   * @note Cannot be disabled if the PLL clock is used as the system clock
03327   * @note   User shall check that PLL is not used by any other peripheral
03328   *         (ex: TIM, TIM15)
03329   * @note In order to save power, when the PLLCLK  of the PLL is
03330   *       not used,  should be 0
03331   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_USB
03332   * @retval None
03333   */
03334 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_USB(void)
03335 {
03336   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03337 }
03338
03339 /**
03340   * @brief  Check if PLL output mapped on USB domain clock is enabled
03341   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_IsEnabledDomain_USB
03342   * @retval State of bit (1 or 0).
03343   */
03344 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_USB(void)
03345 {
03346   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
03347 }
03348 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
03349
03350 #if defined(RCC_PLLQ_SUPPORT)
03351 /**
03352   * @brief  Enable PLL output mapped on TIM1 domain clock
03353   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_TIM1
03354   * @note   User shall check that PLL enable is not done through
03355   *         other functions (ex: RNG, TIM15)
03356   * @retval None
03357   */
03358 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1(void)
03359 {
03360   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03361 }
03362
03363 /**
03364   * @brief  Disable PLL output mapped on TIM1 domain clock
03365   * @note Cannot be disabled if the PLL clock is used as the system clock
03366   * @note   User shall check that PLL is not used by any other peripheral
03367   *         (ex: RNG, TIM15)
03368   * @note In order to save power, when the PLLCLK  of the PLL is
03369   *       not used,  should be 0
03370   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_TIM1
03371   * @retval None
03372   */
03373 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM1(void)
03374 {
03375   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03376 }
03377
03378 /**
03379   * @brief  Check if PLL output mapped on TIM1 domain clock is enabled
03380   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_IsEnabledDomain_TIM1
03381   * @retval State of bit (1 or 0).
03382   */
03383 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_TIM1(void)
03384 {
03385   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
03386 }
03387 #endif /* RCC_PLLQ_SUPPORT */
03388
03389 #if defined(RCC_PLLQ_SUPPORT) && defined(TIM15)
03390 /**
03391   * @brief  Enable PLL output mapped on TIM15 domain clock
03392   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_TIM15
03393   * @note   User shall check that PLL enable is not done through
03394   *         other functions (ex: RNG, TIM1)
03395   * @retval None
03396   */
03397 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15(void)
03398 {
03399   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03400 }
03401
03402 /**
03403   * @brief  Disable PLL output mapped on TIM15 domain clock
03404   * @note Cannot be disabled if the PLL clock is used as the system clock
03405   * @note   User shall check that PLL is not used by any other peripheral
03406   *         (ex: RNG, TIM1)
03407   * @note In order to save power, when the PLLCLK  of the PLL is
03408   *       not used,  should be 0
03409   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_TIM15
03410   * @retval None
03411   */
03412 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM15(void)
03413 {
03414   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03415 }
03416
03417 /**
03418   * @brief  Check if PLL output mapped on TIM15 domain clock is enabled
03419   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_IsEnabledDomain_TIM15
03420   * @retval State of bit (1 or 0).
03421   */
03422 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_TIM15(void)
03423 {
03424   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
03425 }
03426 #endif /* RCC_PLLQ_SUPPORT && TIM15 */
03427
03428 /**
03429   * @brief  Enable PLL output mapped on SYSCLK domain
03430   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
03431   * @retval None
03432   */
03433 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
03434 {
03435   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
03436 }
03437
03438 /**
03439   * @brief  Disable PLL output mapped on SYSCLK domain
03440   * @note Cannot be disabled if the PLL clock is used as the system clock
03441   * @note In order to save power, when the PLLCLK  of the PLL is
03442   *       not used, Main PLL  should be 0
03443   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS
03444   * @retval None
03445   */
03446 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
03447 {
03448   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
03449 }
03450
03451 /**
03452   * @brief  Check if PLL output mapped on SYSCLK domain clock is enabled
03453   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_IsEnabledDomain_SYS
03454   * @retval State of bit (1 or 0).
03455   */
03456 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
03457 {
03458   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
03459 }
03460
03461 /**
03462   * @}
03463   */
03464
03465
03466
03467 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
03468   * @{
03469   */
03470
03471 /**
03472   * @brief  Clear LSI ready interrupt flag
03473   * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
03474   * @retval None
03475   */
03476 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
03477 {
03478   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
03479 }
03480
03481 /**
03482   * @brief  Clear LSE ready interrupt flag
03483   * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
03484   * @retval None
03485   */
03486 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
03487 {
03488   SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
03489 }
03490
03491 /**
03492   * @brief  Clear HSI ready interrupt flag
03493   * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
03494   * @retval None
03495   */
03496 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
03497 {
03498   SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
03499 }
03500
03501 /**
03502   * @brief  Clear HSE ready interrupt flag
03503   * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
03504   * @retval None
03505   */
03506 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
03507 {
03508   SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
03509 }
03510
03511 /**
03512   * @brief  Clear PLL ready interrupt flag
03513   * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
03514   * @retval None
03515   */
03516 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
03517 {
03518   SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
03519 }
03520
03521 #if defined(RCC_HSI48_SUPPORT)
03522 /**
03523   * @brief  Clear HSI48 ready interrupt flag
03524   * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
03525   * @retval None
03526   */
03527 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
03528 {
03529   SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
03530 }
03531 #endif /* RCC_HSI48_SUPPORT */
03532 /**
03533   * @brief  Clear Clock security system interrupt flag
03534   * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
03535   * @retval None
03536   */
03537 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
03538 {
03539   SET_BIT(RCC->CICR, RCC_CICR_CSSC);
03540 }
03541
03542 /**
03543   * @brief  Clear LSE Clock security system interrupt flag
03544   * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
03545   * @retval None
03546   */
03547 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
03548 {
03549   SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
03550 }
03551
03552 /**
03553   * @brief  Check if LSI ready interrupt occurred or not
03554   * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
03555   * @retval State of bit (1 or 0).
03556   */
03557 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
03558 {
03559   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
03560 }
03561
03562 /**
03563   * @brief  Check if LSE ready interrupt occurred or not
03564   * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
03565   * @retval State of bit (1 or 0).
03566   */
03567 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
03568 {
03569   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
03570 }
03571
03572 /**
03573   * @brief  Check if HSI ready interrupt occurred or not
03574   * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
03575   * @retval State of bit (1 or 0).
03576   */
03577 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
03578 {
03579   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
03580 }
03581
03582 /**
03583   * @brief  Check if HSE ready interrupt occurred or not
03584   * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
03585   * @retval State of bit (1 or 0).
03586   */
03587 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
03588 {
03589   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
03590 }
03591
03592 /**
03593   * @brief  Check if PLL ready interrupt occurred or not
03594   * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
03595   * @retval State of bit (1 or 0).
03596   */
03597 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
03598 {
03599   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
03600 }
03601
03602 #if defined(RCC_HSI48_SUPPORT)
03603 /**
03604   * @brief  Check if HSI48 ready interrupt occurred or not
03605   * @rmtoll CIR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
03606   * @retval State of bit (1 or 0).
03607   */
03608 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
03609 {
03610   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
03611 }
03612 #endif /* RCC_HSI48_SUPPORT */
03613
03614 /**
03615   * @brief  Check if Clock security system interrupt occurred or not
03616   * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
03617   * @retval State of bit (1 or 0).
03618   */
03619 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
03620 {
03621   return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
03622 }
03623
03624 /**
03625   * @brief  Check if LSE Clock security system interrupt occurred or not
03626   * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
03627   * @retval State of bit (1 or 0).
03628   */
03629 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
03630 {
03631   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
03632 }
03633
03634 /**
03635   * @brief  Check if RCC flag Independent Watchdog reset is set or not.
03636   * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
03637   * @retval State of bit (1 or 0).
03638   */
03639 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
03640 {
03641   return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
03642 }
03643
03644 /**
03645   * @brief  Check if RCC flag Low Power reset is set or not.
03646   * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
03647   * @retval State of bit (1 or 0).
03648   */
03649 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
03650 {
03651   return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
03652 }
03653
03654 /**
03655   * @brief  Check if RCC flag Option byte reset is set or not.
03656   * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
03657   * @retval State of bit (1 or 0).
03658   */
03659 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
03660 {
03661   return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
03662 }
03663
03664 /**
03665   * @brief  Check if RCC flag Pin reset is set or not.
03666   * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
03667   * @retval State of bit (1 or 0).
03668   */
03669 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
03670 {
03671   return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
03672 }
03673
03674 /**
03675   * @brief  Check if RCC flag Software reset is set or not.
03676   * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
03677   * @retval State of bit (1 or 0).
03678   */
03679 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
03680 {
03681   return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
03682 }
03683
03684 /**
03685   * @brief  Check if RCC flag Window Watchdog reset is set or not.
03686   * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
03687   * @retval State of bit (1 or 0).
03688   */
03689 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
03690 {
03691   return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
03692 }
03693
03694 /**
03695   * @brief  Check if RCC flag BOR or POR/PDR reset is set or not.
03696   * @rmtoll CSR          PWRRSTF       LL_RCC_IsActiveFlag_PWRRST
03697   * @retval State of bit (1 or 0).
03698   */
03699 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void)
03700 {
03701   return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL);
03702 }
03703
03704 /**
03705   * @brief  Set RMVF bit to clear the reset flags.
03706   * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
03707   * @retval None
03708   */
03709 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
03710 {
03711   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
03712 }
03713
03714 /**
03715   * @}
03716   */
03717
03718 /** @defgroup RCC_LL_EF_IT_Management IT Management
03719   * @{
03720   */
03721
03722 /**
03723   * @brief  Enable LSI ready interrupt
03724   * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
03725   * @retval None
03726   */
03727 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
03728 {
03729   SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
03730 }
03731
03732 /**
03733   * @brief  Enable LSE ready interrupt
03734   * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
03735   * @retval None
03736   */
03737 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
03738 {
03739   SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
03740 }
03741
03742 /**
03743   * @brief  Enable HSI ready interrupt
03744   * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
03745   * @retval None
03746   */
03747 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
03748 {
03749   SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
03750 }
03751
03752 /**
03753   * @brief  Enable HSE ready interrupt
03754   * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
03755   * @retval None
03756   */
03757 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
03758 {
03759   SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
03760 }
03761
03762 /**
03763   * @brief  Enable PLL ready interrupt
03764   * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
03765   * @retval None
03766   */
03767 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
03768 {
03769   SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
03770 }
03771
03772 #if defined(RCC_HSI48_SUPPORT)
03773 /**
03774   * @brief  Enable HSI48 ready interrupt
03775   * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
03776   * @retval None
03777   */
03778 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
03779 {
03780   SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
03781 }
03782 #endif /* RCC_HSI48_SUPPORT */
03783
03784 /**
03785   * @brief  Disable LSI ready interrupt
03786   * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
03787   * @retval None
03788   */
03789 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
03790 {
03791   CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
03792 }
03793
03794 /**
03795   * @brief  Disable LSE ready interrupt
03796   * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
03797   * @retval None
03798   */
03799 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
03800 {
03801   CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
03802 }
03803
03804 /**
03805   * @brief  Disable HSI ready interrupt
03806   * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
03807   * @retval None
03808   */
03809 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
03810 {
03811   CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
03812 }
03813
03814 /**
03815   * @brief  Disable HSE ready interrupt
03816   * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
03817   * @retval None
03818   */
03819 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
03820 {
03821   CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
03822 }
03823
03824 /**
03825   * @brief  Disable PLL ready interrupt
03826   * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
03827   * @retval None
03828   */
03829 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
03830 {
03831   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
03832 }
03833
03834 #if defined(RCC_HSI48_SUPPORT)
03835 /**
03836   * @brief  Disable HSI48 ready interrupt
03837   * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
03838   * @retval None
03839   */
03840 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
03841 {
03842   CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
03843 }
03844 #endif /* RCC_HSI48_SUPPORT */
03845
03846 /**
03847   * @brief  Checks if LSI ready interrupt source is enabled or disabled.
03848   * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
03849   * @retval State of bit (1 or 0).
03850   */
03851 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
03852 {
03853   return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
03854 }
03855
03856 /**
03857   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
03858   * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
03859   * @retval State of bit (1 or 0).
03860   */
03861 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
03862 {
03863   return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
03864 }
03865
03866 /**
03867   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
03868   * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
03869   * @retval State of bit (1 or 0).
03870   */
03871 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
03872 {
03873   return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
03874 }
03875
03876 #if defined(RCC_HSI48_SUPPORT)
03877 /**
03878   * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
03879   * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnabledIT_HSI48RDY
03880   * @retval State of bit (1 or 0).
03881   */
03882 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
03883 {
03884   return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
03885 }
03886 #endif /* RCC_HSI48_SUPPORT */
03887
03888 /**
03889   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
03890   * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
03891   * @retval State of bit (1 or 0).
03892   */
03893 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
03894 {
03895   return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
03896 }
03897
03898 /**
03899   * @brief  Checks if PLL ready interrupt source is enabled or disabled.
03900   * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
03901   * @retval State of bit (1 or 0).
03902   */
03903 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
03904 {
03905   return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
03906 }
03907
03908 /**
03909   * @}
03910   */
03911
03912 #if defined(USE_FULL_LL_DRIVER)
03913 /** @defgroup RCC_LL_EF_Init De-initialization function
03914   * @{
03915   */
03916 ErrorStatus LL_RCC_DeInit(void);
03917 /**
03918   * @}
03919   */
03920
03921 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
03922   * @{
03923   */
03924 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
03925 uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
03926 uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
03927 #if defined(LPUART1) || defined(LPUART2)
03928 uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
03929 #endif /* LPUART1 */
03930 #if defined(LPTIM1) && defined(LPTIM2)
03931 uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
03932 #endif /* LPTIM1 && LPTIM2 */
03933 #if defined(RNG)
03934 uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
03935 #endif /* RNG */
03936 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
03937 uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
03938 #if defined(CEC)
03939 uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
03940 #endif /* CEC */
03941 #if defined(FDCAN1) || defined(FDCAN2)
03942 uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
03943 #endif /* FDCAN1 */
03944 uint32_t    LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
03945 uint32_t    LL_RCC_GetRTCClockFreq(void);
03946 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
03947 uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
03948 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
03949 /**
03950   * @}
03951   */
03952 #endif /* USE_FULL_LL_DRIVER */
03953
03954 /**
03955   * @}
03956   */
03957
03958 /**
03959   * @}
03960   */
03961
03962 #endif /* RCC */
03963
03964 /**
03965   * @}
03966   */
03967
03968 #ifdef __cplusplus
03969 }
03970 #endif
03971
03972 #endif /* STM32G0xx_LL_RCC_H */
03973
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rng.c Source File

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stm32g0xx_ll_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_rng.c
00004   * @author  MCD Application Team
00005   * @brief   RNG LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_rng.h"
00022 #include "stm32g0xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (RNG)
00035
00036 /** @addtogroup RNG_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @defgroup RNG_LL_Private_Macros RNG Private Macros
00045   * @{
00046   */
00047 #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
00048                                  ((__MODE__) == LL_RNG_CED_DISABLE))
00049
00050 /**
00051   * @}
00052   */
00053 /* Private function prototypes -----------------------------------------------*/
00054
00055 /* Exported functions --------------------------------------------------------*/
00056 /** @addtogroup RNG_LL_Exported_Functions
00057   * @{
00058   */
00059
00060 /** @addtogroup RNG_LL_EF_Init
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  De-initialize RNG registers (Registers restored to their default values).
00066   * @param  RNGx RNG Instance
00067   * @retval An ErrorStatus enumeration value:
00068   *          - SUCCESS: RNG registers are de-initialized
00069   *          - ERROR: not applicable
00070   */
00071 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
00072 {
00073   ErrorStatus status = SUCCESS;
00074
00075   /* Check the parameters */
00076   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00077   if (RNGx == RNG)
00078   {
00079     /* Enable RNG reset state */
00080     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG);
00081
00082     /* Release RNG from reset state */
00083     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG);
00084   }
00085   else
00086   {
00087     status = ERROR;
00088   }
00089
00090   return status;
00091 }
00092
00093 /**
00094   * @brief  Initialize RNG registers according to the specified parameters in RNG_InitStruct.
00095   * @param  RNGx RNG Instance
00096   * @param  RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
00097   *         that contains the configuration information for the specified RNG peripheral.
00098   * @retval An ErrorStatus enumeration value:
00099   *          - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
00100   *          - ERROR: not applicable
00101   */
00102 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
00103 {
00104   /* Check the parameters */
00105   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00106   assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
00107
00108   /* Clock Error Detection configuration */
00109   MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection);
00110
00111   return (SUCCESS);
00112 }
00113
00114 /**
00115   * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
00116   * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
00117   *                       whose fields will be set to default values.
00118   * @retval None
00119   */
00120 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
00121 {
00122   /* Set RNG_InitStruct fields to default values */
00123   RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
00124
00125 }
00126 /**
00127   * @}
00128   */
00129
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138 #endif /* RNG */
00139
00140 /**
00141   * @}
00142   */
00143
00144 #endif /* USE_FULL_LL_DRIVER */
00145
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rng.h Source File

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stm32g0xx_ll_rng.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_rng.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_RNG_H
00021 #define STM32G0xx_LL_RNG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (RNG)
00035
00036 /** @defgroup RNG_LL RNG
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 #if defined(USE_FULL_LL_DRIVER)
00047 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
00048   * @{
00049   */
00050
00051
00052 /**
00053   * @brief LL RNG Init Structure Definition
00054   */
00055 typedef struct
00056 {
00057   uint32_t         ClockErrorDetection; /*!< Clock error detection.
00058                                       This parameter can be one value of @ref RNG_LL_CED.
00059                                       This parameter can be modified using unitary
00060                                       functions @ref LL_RNG_EnableClkErrorDetect(). */
00061 } LL_RNG_InitTypeDef;
00062
00063 /**
00064   * @}
00065   */
00066 #endif /* USE_FULL_LL_DRIVER */
00067 /* Exported constants --------------------------------------------------------*/
00068 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
00069   * @{
00070   */
00071
00072 /** @defgroup RNG_LL_CED Clock Error Detection
00073   * @{
00074   */
00075 #define LL_RNG_CED_ENABLE         0x00000000U              /*!< Clock error detection enabled  */
00076 #define LL_RNG_CED_DISABLE        RNG_CR_CED               /*!< Clock error detection disabled */
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
00082   * @brief    Flags defines which can be used with LL_RNG_ReadReg function
00083   * @{
00084   */
00085 #define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
00086 #define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
00087 #define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
00088 #define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
00089 #define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
00090 /**
00091   * @}
00092   */
00093
00094 /** @defgroup RNG_LL_EC_IT IT Defines
00095   * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
00096   * @{
00097   */
00098 #define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
00099 /**
00100   * @}
00101   */
00102
00103 /**
00104   * @}
00105   */
00106
00107 /* Exported macro ------------------------------------------------------------*/
00108 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
00109   * @{
00110   */
00111
00112 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
00113   * @{
00114   */
00115
00116 /**
00117   * @brief  Write a value in RNG register
00118   * @param  __INSTANCE__ RNG Instance
00119   * @param  __REG__ Register to be written
00120   * @param  __VALUE__ Value to be written in the register
00121   * @retval None
00122   */
00123 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00124
00125 /**
00126   * @brief  Read a value in RNG register
00127   * @param  __INSTANCE__ RNG Instance
00128   * @param  __REG__ Register to be read
00129   * @retval Register value
00130   */
00131 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00132 /**
00133   * @}
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140
00141 /* Exported functions --------------------------------------------------------*/
00142 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
00143   * @{
00144   */
00145 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
00146   * @{
00147   */
00148
00149 /**
00150   * @brief  Enable Random Number Generation
00151   * @rmtoll CR           RNGEN         LL_RNG_Enable
00152   * @param  RNGx RNG Instance
00153   * @retval None
00154   */
00155 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
00156 {
00157   SET_BIT(RNGx->CR, RNG_CR_RNGEN);
00158 }
00159
00160 /**
00161   * @brief  Disable Random Number Generation
00162   * @rmtoll CR           RNGEN         LL_RNG_Disable
00163   * @param  RNGx RNG Instance
00164   * @retval None
00165   */
00166 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
00167 {
00168   CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
00169 }
00170
00171 /**
00172   * @brief  Check if Random Number Generator is enabled
00173   * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
00174   * @param  RNGx RNG Instance
00175   * @retval State of bit (1 or 0).
00176   */
00177 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
00178 {
00179   return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
00180 }
00181
00182 /**
00183   * @brief  Enable Clock Error Detection
00184   * @rmtoll CR           CED           LL_RNG_EnableClkErrorDetect
00185   * @param  RNGx RNG Instance
00186   * @retval None
00187   */
00188 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
00189 {
00190   CLEAR_BIT(RNGx->CR, RNG_CR_CED);
00191 }
00192
00193 /**
00194   * @brief  Disable RNG Clock Error Detection
00195   * @rmtoll CR           CED         LL_RNG_DisableClkErrorDetect
00196   * @param  RNGx RNG Instance
00197   * @retval None
00198   */
00199 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
00200 {
00201   SET_BIT(RNGx->CR, RNG_CR_CED);
00202 }
00203
00204 /**
00205   * @brief  Check if RNG Clock Error Detection is enabled
00206   * @rmtoll CR           CED         LL_RNG_IsEnabledClkErrorDetect
00207   * @param  RNGx RNG Instance
00208   * @retval State of bit (1 or 0).
00209   */
00210 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
00211 {
00212   return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
00213 }
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
00220   * @{
00221   */
00222
00223 /**
00224   * @brief  Indicate if the RNG Data ready Flag is set or not
00225   * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
00226   * @param  RNGx RNG Instance
00227   * @retval State of bit (1 or 0).
00228   */
00229 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
00230 {
00231   return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
00232 }
00233
00234 /**
00235   * @brief  Indicate if the Clock Error Current Status Flag is set or not
00236   * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
00237   * @param  RNGx RNG Instance
00238   * @retval State of bit (1 or 0).
00239   */
00240 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
00241 {
00242   return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
00243 }
00244
00245 /**
00246   * @brief  Indicate if the Seed Error Current Status Flag is set or not
00247   * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
00248   * @param  RNGx RNG Instance
00249   * @retval State of bit (1 or 0).
00250   */
00251 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
00252 {
00253   return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
00254 }
00255
00256 /**
00257   * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
00258   * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
00259   * @param  RNGx RNG Instance
00260   * @retval State of bit (1 or 0).
00261   */
00262 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
00263 {
00264   return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
00265 }
00266
00267 /**
00268   * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
00269   * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
00270   * @param  RNGx RNG Instance
00271   * @retval State of bit (1 or 0).
00272   */
00273 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
00274 {
00275   return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
00276 }
00277
00278 /**
00279   * @brief  Clear Clock Error interrupt Status (CEIS) Flag
00280   * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
00281   * @param  RNGx RNG Instance
00282   * @retval None
00283   */
00284 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
00285 {
00286   WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
00287 }
00288
00289 /**
00290   * @brief  Clear Seed Error interrupt Status (SEIS) Flag
00291   * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
00292   * @param  RNGx RNG Instance
00293   * @retval None
00294   */
00295 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
00296 {
00297   WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
00298 }
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup RNG_LL_EF_IT_Management IT Management
00305   * @{
00306   */
00307
00308 /**
00309   * @brief  Enable Random Number Generator Interrupt
00310   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00311   * @rmtoll CR           IE            LL_RNG_EnableIT
00312   * @param  RNGx RNG Instance
00313   * @retval None
00314   */
00315 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
00316 {
00317   SET_BIT(RNGx->CR, RNG_CR_IE);
00318 }
00319
00320 /**
00321   * @brief  Disable Random Number Generator Interrupt
00322   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00323   * @rmtoll CR           IE            LL_RNG_DisableIT
00324   * @param  RNGx RNG Instance
00325   * @retval None
00326   */
00327 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
00328 {
00329   CLEAR_BIT(RNGx->CR, RNG_CR_IE);
00330 }
00331
00332 /**
00333   * @brief  Check if Random Number Generator Interrupt is enabled
00334   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00335   * @rmtoll CR           IE            LL_RNG_IsEnabledIT
00336   * @param  RNGx RNG Instance
00337   * @retval State of bit (1 or 0).
00338   */
00339 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
00340 {
00341   return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
00342 }
00343
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup RNG_LL_EF_Data_Management Data Management
00349   * @{
00350   */
00351
00352 /**
00353   * @brief  Return32-bit Random Number value
00354   * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
00355   * @param  RNGx RNG Instance
00356   * @retval Generated 32-bit random value
00357   */
00358 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
00359 {
00360   return (uint32_t)(READ_REG(RNGx->DR));
00361 }
00362
00363 /**
00364   * @}
00365   */
00366
00367 #if defined(USE_FULL_LL_DRIVER)
00368 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
00369   * @{
00370   */
00371 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
00372 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
00373 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
00374
00375 /**
00376   * @}
00377   */
00378 #endif /* USE_FULL_LL_DRIVER */
00379
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
00387
00388 #endif /* RNG */
00389
00390 /**
00391   * @}
00392   */
00393
00394 #ifdef __cplusplus
00395 }
00396 #endif
00397
00398 #endif /* __STM32G0xx_LL_RNG_H */
00399
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rtc.c Source File

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stm32g0xx_ll_rtc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_rtc.h"
00022 #include "stm32g0xx_ll_cortex.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G0xx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined(RTC)
00034
00035 /** @addtogroup RTC_LL
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /** @addtogroup RTC_LL_Private_Constants
00043   * @{
00044   */
00045 /* Default values used for prescaler */
00046 #define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
00047 #define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
00048
00049 /* Values used for timeout */
00050 #define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
00051 #define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
00052 /**
00053   * @}
00054   */
00055
00056 /* Private macros ------------------------------------------------------------*/
00057 /** @addtogroup RTC_LL_Private_Macros
00058   * @{
00059   */
00060
00061 #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
00062                                       || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
00063
00064 #define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
00065
00066 #define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
00067
00068 #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
00069                                   || ((__VALUE__) == LL_RTC_FORMAT_BCD))
00070
00071 #define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
00072                                        || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
00073
00074 #define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
00075 #define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
00076 #define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
00077 #define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
00078
00079 #define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
00080                                    || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
00081                                    || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
00082                                    || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
00083                                    || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
00084                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
00085                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
00086
00087 #define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
00088
00089 #define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
00090
00091 #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
00092
00093 #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
00094                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
00095                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
00096                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
00097                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
00098                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
00099
00100 #define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
00101                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
00102                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
00103                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
00104                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
00105                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
00106
00107
00108 #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
00109                                                   ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
00110
00111 #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
00112                                                   ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
00113
00114
00115 /**
00116   * @}
00117   */
00118 /* Private function prototypes -----------------------------------------------*/
00119 /* Exported functions --------------------------------------------------------*/
00120 /** @addtogroup RTC_LL_Exported_Functions
00121   * @{
00122   */
00123
00124 /** @addtogroup RTC_LL_EF_Init
00125   * @{
00126   */
00127
00128 /**
00129   * @brief  De-Initializes the RTC registers to their default reset values.
00130   * @note   This function does not reset the RTC Clock source and RTC Backup Data
00131   *         registers.
00132   * @param  RTCx RTC Instance
00133   * @retval An ErrorStatus enumeration value:
00134   *          - SUCCESS: RTC registers are de-initialized
00135   *          - ERROR: RTC registers are not de-initialized
00136   */
00137 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
00138 {
00139   ErrorStatus status = ERROR;
00140
00141   /* Check the parameter */
00142   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00143
00144   /* Disable the write protection for RTC registers */
00145   LL_RTC_DisableWriteProtection(RTCx);
00146
00147   /* Set Initialization mode */
00148   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00149   {
00150     /* Reset TR, DR and CR registers */
00151     WRITE_REG(RTCx->TR,       0x00000000U);
00152 #if defined(RTC_WAKEUP_SUPPORT)
00153     WRITE_REG(RTCx->WUTR,     RTC_WUTR_WUT);
00154 #endif /* RTC_WAKEUP_SUPPORT */
00155     WRITE_REG(RTCx->DR  ,     (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00156     /* Reset All CR bits except CR[2:0] */
00157 #if defined(RTC_WAKEUP_SUPPORT)
00158     WRITE_REG(RTCx->CR, (READ_REG(RTCx->CR) & RTC_CR_WUCKSEL));
00159 #else
00160     WRITE_REG(RTCx->CR, 0x00000000U);
00161 #endif /* RTC_WAKEUP_SUPPORT */
00162     WRITE_REG(RTCx->PRER,     (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
00163     WRITE_REG(RTCx->ALRMAR,   0x00000000U);
00164     WRITE_REG(RTCx->ALRMBR,   0x00000000U);
00165     WRITE_REG(RTCx->SHIFTR,   0x00000000U);
00166     WRITE_REG(RTCx->CALR,     0x00000000U);
00167     WRITE_REG(RTCx->ALRMASSR, 0x00000000U);
00168     WRITE_REG(RTCx->ALRMBSSR, 0x00000000U);
00169
00170     /* Exit Initialization mode */
00171     LL_RTC_DisableInitMode(RTCx);
00172
00173     /* Wait till the RTC RSF flag is set */
00174     status = LL_RTC_WaitForSynchro(RTCx);
00175   }
00176
00177   /* Enable the write protection for RTC registers */
00178   LL_RTC_EnableWriteProtection(RTCx);
00179
00180   return status;
00181 }
00182
00183 /**
00184   * @brief  Initializes the RTC registers according to the specified parameters
00185   *         in RTC_InitStruct.
00186   * @param  RTCx RTC Instance
00187   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
00188   *         the configuration information for the RTC peripheral.
00189   * @note   The RTC Prescaler register is write protected and can be written in
00190   *         initialization mode only.
00191   * @retval An ErrorStatus enumeration value:
00192   *          - SUCCESS: RTC registers are initialized
00193   *          - ERROR: RTC registers are not initialized
00194   */
00195 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
00196 {
00197   ErrorStatus status = ERROR;
00198
00199   /* Check the parameters */
00200   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00201   assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
00202   assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
00203   assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
00204
00205   /* Disable the write protection for RTC registers */
00206   LL_RTC_DisableWriteProtection(RTCx);
00207
00208   /* Set Initialization mode */
00209   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00210   {
00211     /* Set Hour Format */
00212     LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
00213
00214     /* Configure Synchronous and Asynchronous prescaler factor */
00215     LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
00216     LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
00217
00218     /* Exit Initialization mode */
00219     LL_RTC_DisableInitMode(RTCx);
00220
00221     status = SUCCESS;
00222   }
00223   /* Enable the write protection for RTC registers */
00224   LL_RTC_EnableWriteProtection(RTCx);
00225
00226   return status;
00227 }
00228
00229 /**
00230   * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
00231   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
00232   * @retval None
00233   */
00234 void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
00235 {
00236   /* Set RTC_InitStruct fields to default values */
00237   RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
00238   RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
00239   RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
00240 }
00241
00242 /**
00243   * @brief  Set the RTC current time.
00244   * @param  RTCx RTC Instance
00245   * @param  RTC_Format This parameter can be one of the following values:
00246   *         @arg @ref LL_RTC_FORMAT_BIN
00247   *         @arg @ref LL_RTC_FORMAT_BCD
00248   * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
00249   *                        the time configuration information for the RTC.
00250   * @retval An ErrorStatus enumeration value:
00251   *          - SUCCESS: RTC Time register is configured
00252   *          - ERROR: RTC Time register is not configured
00253   */
00254 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
00255 {
00256   ErrorStatus status = ERROR;
00257
00258   /* Check the parameters */
00259   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00260   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00261
00262   if (RTC_Format == LL_RTC_FORMAT_BIN)
00263   {
00264     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00265     {
00266       assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
00267       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00268     }
00269     else
00270     {
00271       RTC_TimeStruct->TimeFormat = 0x00U;
00272       assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
00273     }
00274     assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
00275     assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
00276   }
00277   else
00278   {
00279     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00280     {
00281       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00282       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00283     }
00284     else
00285     {
00286       RTC_TimeStruct->TimeFormat = 0x00U;
00287       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00288     }
00289     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
00290     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
00291   }
00292
00293   /* Disable the write protection for RTC registers */
00294   LL_RTC_DisableWriteProtection(RTCx);
00295
00296   /* Set Initialization mode */
00297   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00298   {
00299     /* Check the input parameters format */
00300     if (RTC_Format != LL_RTC_FORMAT_BIN)
00301     {
00302       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
00303                          RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
00304     }
00305     else
00306     {
00307       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
00308                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
00309                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
00310     }
00311
00312     /* Exit Initialization mode */
00313     LL_RTC_DisableInitMode(RTCx);
00314
00315     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00316     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00317     {
00318       status = LL_RTC_WaitForSynchro(RTCx);
00319     }
00320     else
00321     {
00322       status = SUCCESS;
00323     }
00324   }
00325   /* Enable the write protection for RTC registers */
00326   LL_RTC_EnableWriteProtection(RTCx);
00327
00328   return status;
00329 }
00330
00331 /**
00332   * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
00333   * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
00334   * @retval None
00335   */
00336 void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
00337 {
00338   /* Time = 00h:00min:00sec */
00339   RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
00340   RTC_TimeStruct->Hours      = 0U;
00341   RTC_TimeStruct->Minutes    = 0U;
00342   RTC_TimeStruct->Seconds    = 0U;
00343 }
00344
00345 /**
00346   * @brief  Set the RTC current date.
00347   * @param  RTCx RTC Instance
00348   * @param  RTC_Format This parameter can be one of the following values:
00349   *         @arg @ref LL_RTC_FORMAT_BIN
00350   *         @arg @ref LL_RTC_FORMAT_BCD
00351   * @param  RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
00352   *                         the date configuration information for the RTC.
00353   * @retval An ErrorStatus enumeration value:
00354   *          - SUCCESS: RTC Day register is configured
00355   *          - ERROR: RTC Day register is not configured
00356   */
00357 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
00358 {
00359   ErrorStatus status = ERROR;
00360
00361   /* Check the parameters */
00362   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00363   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00364
00365   if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
00366   {
00367     RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
00368   }
00369   if (RTC_Format == LL_RTC_FORMAT_BIN)
00370   {
00371     assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
00372     assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
00373     assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
00374   }
00375   else
00376   {
00377     assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
00378     assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
00379     assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
00380   }
00381   assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
00382
00383   /* Disable the write protection for RTC registers */
00384   LL_RTC_DisableWriteProtection(RTCx);
00385
00386   /* Set Initialization mode */
00387   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00388   {
00389     /* Check the input parameters format */
00390     if (RTC_Format != LL_RTC_FORMAT_BIN)
00391     {
00392       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
00393     }
00394     else
00395     {
00396       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
00397                          __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
00398     }
00399
00400     /* Exit Initialization mode */
00401     LL_RTC_DisableInitMode(RTCx);
00402
00403     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00404     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00405     {
00406       status = LL_RTC_WaitForSynchro(RTCx);
00407     }
00408     else
00409     {
00410       status = SUCCESS;
00411     }
00412   }
00413   /* Enable the write protection for RTC registers */
00414   LL_RTC_EnableWriteProtection(RTCx);
00415
00416   return status;
00417 }
00418
00419 /**
00420   * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
00421   * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
00422   * @retval None
00423   */
00424 void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
00425 {
00426   /* Monday, January 01 xx00 */
00427   RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
00428   RTC_DateStruct->Day     = 1U;
00429   RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
00430   RTC_DateStruct->Year    = 0U;
00431 }
00432
00433 /**
00434   * @brief  Set the RTC Alarm A.
00435   * @note   The Alarm register can only be written when the corresponding Alarm
00436   *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
00437   * @param  RTCx RTC Instance
00438   * @param  RTC_Format This parameter can be one of the following values:
00439   *         @arg @ref LL_RTC_FORMAT_BIN
00440   *         @arg @ref LL_RTC_FORMAT_BCD
00441   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00442   *                         contains the alarm configuration parameters.
00443   * @retval An ErrorStatus enumeration value:
00444   *          - SUCCESS: ALARMA registers are configured
00445   *          - ERROR: ALARMA registers are not configured
00446   */
00447 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00448 {
00449   /* Check the parameters */
00450   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00451   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00452   assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
00453   assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00454
00455   if (RTC_Format == LL_RTC_FORMAT_BIN)
00456   {
00457     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00458     {
00459       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00460       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00461     }
00462     else
00463     {
00464       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00465       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00466     }
00467     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00468     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00469
00470     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00471     {
00472       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00473     }
00474     else
00475     {
00476       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00477     }
00478   }
00479   else
00480   {
00481     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00482     {
00483       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00484       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00485     }
00486     else
00487     {
00488       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00489       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00490     }
00491
00492     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00493     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00494
00495     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00496     {
00497       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00498     }
00499     else
00500     {
00501       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00502     }
00503   }
00504
00505   /* Disable the write protection for RTC registers */
00506   LL_RTC_DisableWriteProtection(RTCx);
00507
00508   /* Select weekday selection */
00509   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00510   {
00511     /* Set the date for ALARM */
00512     LL_RTC_ALMA_DisableWeekday(RTCx);
00513     if (RTC_Format != LL_RTC_FORMAT_BIN)
00514     {
00515       LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00516     }
00517     else
00518     {
00519       LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00520     }
00521   }
00522   else
00523   {
00524     /* Set the week day for ALARM */
00525     LL_RTC_ALMA_EnableWeekday(RTCx);
00526     LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00527   }
00528
00529   /* Configure the Alarm register */
00530   if (RTC_Format != LL_RTC_FORMAT_BIN)
00531   {
00532     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00533                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00534   }
00535   else
00536   {
00537     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00538                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00539                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00540                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00541   }
00542   /* Set ALARM mask */
00543   LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00544
00545   /* Enable the write protection for RTC registers */
00546   LL_RTC_EnableWriteProtection(RTCx);
00547
00548   return SUCCESS;
00549 }
00550
00551 /**
00552   * @brief  Set the RTC Alarm B.
00553   * @note   The Alarm register can only be written when the corresponding Alarm
00554   *         is disabled (@ref LL_RTC_ALMB_Disable function).
00555   * @param  RTCx RTC Instance
00556   * @param  RTC_Format This parameter can be one of the following values:
00557   *         @arg @ref LL_RTC_FORMAT_BIN
00558   *         @arg @ref LL_RTC_FORMAT_BCD
00559   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00560   *                         contains the alarm configuration parameters.
00561   * @retval An ErrorStatus enumeration value:
00562   *          - SUCCESS: ALARMB registers are configured
00563   *          - ERROR: ALARMB registers are not configured
00564   */
00565 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00566 {
00567   /* Check the parameters */
00568   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00569   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00570   assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
00571   assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00572
00573   if (RTC_Format == LL_RTC_FORMAT_BIN)
00574   {
00575     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00576     {
00577       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00578       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00579     }
00580     else
00581     {
00582       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00583       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00584     }
00585     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00586     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00587
00588     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00589     {
00590       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00591     }
00592     else
00593     {
00594       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00595     }
00596   }
00597   else
00598   {
00599     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00600     {
00601       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00602       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00603     }
00604     else
00605     {
00606       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00607       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00608     }
00609
00610     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00611     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00612
00613     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00614     {
00615       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00616     }
00617     else
00618     {
00619       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00620     }
00621   }
00622
00623   /* Disable the write protection for RTC registers */
00624   LL_RTC_DisableWriteProtection(RTCx);
00625
00626   /* Select weekday selection */
00627   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00628   {
00629     /* Set the date for ALARM */
00630     LL_RTC_ALMB_DisableWeekday(RTCx);
00631     if (RTC_Format != LL_RTC_FORMAT_BIN)
00632     {
00633       LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00634     }
00635     else
00636     {
00637       LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00638     }
00639   }
00640   else
00641   {
00642     /* Set the week day for ALARM */
00643     LL_RTC_ALMB_EnableWeekday(RTCx);
00644     LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00645   }
00646
00647   /* Configure the Alarm register */
00648   if (RTC_Format != LL_RTC_FORMAT_BIN)
00649   {
00650     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00651                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00652   }
00653   else
00654   {
00655     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00656                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00657                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00658                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00659   }
00660   /* Set ALARM mask */
00661   LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00662
00663   /* Enable the write protection for RTC registers */
00664   LL_RTC_EnableWriteProtection(RTCx);
00665
00666   return SUCCESS;
00667 }
00668
00669 /**
00670   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00671   *         Day = 1st day of the month/Mask = all fields are masked).
00672   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00673   * @retval None
00674   */
00675 void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00676 {
00677   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00678   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
00679   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00680   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00681   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00682
00683   /* Alarm Day Settings : Day = 1st day of the month */
00684   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
00685   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00686
00687   /* Alarm Masks Settings : Mask =  all fields are not masked */
00688   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
00689 }
00690
00691 /**
00692   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00693   *         Day = 1st day of the month/Mask = all fields are masked).
00694   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00695   * @retval None
00696   */
00697 void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00698 {
00699   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00700   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
00701   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00702   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00703   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00704
00705   /* Alarm Day Settings : Day = 1st day of the month */
00706   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
00707   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00708
00709   /* Alarm Masks Settings : Mask =  all fields are not masked */
00710   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
00711 }
00712
00713 /**
00714   * @brief  Enters the RTC Initialization mode.
00715   * @note   The RTC Initialization mode is write protected, use the
00716   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00717   * @param  RTCx RTC Instance
00718   * @retval An ErrorStatus enumeration value:
00719   *          - SUCCESS: RTC is in Init mode
00720   *          - ERROR: RTC is not in Init mode
00721   */
00722 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
00723 {
00724   __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
00725   ErrorStatus status = SUCCESS;
00726   uint32_t tmp;
00727
00728   /* Check the parameter */
00729   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00730
00731   /* Check if the Initialization mode is set */
00732   if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
00733   {
00734     /* Set the Initialization mode */
00735     LL_RTC_EnableInitMode(RTCx);
00736
00737     /* Wait till RTC is in INIT state and if Time out is reached exit */
00738     tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00739     while ((timeout != 0U) && (tmp != 1U))
00740     {
00741       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00742       {
00743         timeout --;
00744       }
00745       tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00746       if (timeout == 0U)
00747       {
00748         status = ERROR;
00749       }
00750     }
00751   }
00752   return status;
00753 }
00754
00755 /**
00756   * @brief  Exit the RTC Initialization mode.
00757   * @note   When the initialization sequence is complete, the calendar restarts
00758   *         counting after 4 RTCCLK cycles.
00759   * @note   The RTC Initialization mode is write protected, use the
00760   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00761   * @param  RTCx RTC Instance
00762   * @retval An ErrorStatus enumeration value:
00763   *          - SUCCESS: RTC exited from in Init mode
00764   *          - ERROR: Not applicable
00765   */
00766 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
00767 {
00768   /* Check the parameter */
00769   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00770
00771   /* Disable initialization mode */
00772   LL_RTC_DisableInitMode(RTCx);
00773
00774   return SUCCESS;
00775 }
00776
00777 /**
00778   * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
00779   *         synchronized with RTC APB clock.
00780   * @note   The RTC Resynchronization mode is write protected, use the
00781   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00782   * @note   To read the calendar through the shadow registers after Calendar
00783   *         initialization, calendar update or after wakeup from low power modes
00784   *         the software must first clear the RSF flag.
00785   *         The software must then wait until it is set again before reading
00786   *         the calendar, which means that the calendar registers have been
00787   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
00788   * @param  RTCx RTC Instance
00789   * @retval An ErrorStatus enumeration value:
00790   *          - SUCCESS: RTC registers are synchronised
00791   *          - ERROR: RTC registers are not synchronised
00792   */
00793 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
00794 {
00795   __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
00796   ErrorStatus status = SUCCESS;
00797   uint32_t tmp;
00798
00799   /* Check the parameter */
00800   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00801
00802   /* Clear RSF flag */
00803   LL_RTC_ClearFlag_RS(RTCx);
00804
00805   /* Wait the registers to be synchronised */
00806   tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00807   while ((timeout != 0U) && (tmp != 0U))
00808   {
00809     if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00810     {
00811       timeout--;
00812     }
00813     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00814     if (timeout == 0U)
00815     {
00816       status = ERROR;
00817     }
00818   }
00819
00820   if (status != ERROR)
00821   {
00822     timeout = RTC_SYNCHRO_TIMEOUT;
00823     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00824     while ((timeout != 0U) && (tmp != 1U))
00825     {
00826       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00827       {
00828         timeout--;
00829       }
00830       tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00831       if (timeout == 0U)
00832       {
00833         status = ERROR;
00834       }
00835     }
00836   }
00837
00838   return (status);
00839 }
00840
00841 /**
00842   * @}
00843   */
00844
00845 /**
00846   * @}
00847   */
00848
00849 /**
00850   * @}
00851   */
00852
00853 #endif /* defined(RTC) */
00854
00855 /**
00856   * @}
00857   */
00858
00859 #endif /* USE_FULL_LL_DRIVER */
00860
00861
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_rtc.h Source File

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stm32g0xx_ll_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_RTC_H
00021 #define STM32G0xx_LL_RTC_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(RTC)
00035
00036 /** @defgroup RTC_LL RTC
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @defgroup RTC_LL_Private_Constants RTC Private Constants
00044   * @{
00045   */
00046 /* Masks Definition */
00047 #define RTC_LL_INIT_MASK              0xFFFFFFFFU
00048 #define RTC_LL_RSF_MASK               0xFFFFFF5FU
00049
00050 /* Write protection defines */
00051 #define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
00052 #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
00053 #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
00054
00055 /* Defines used to combine date & time */
00056 #define RTC_OFFSET_WEEKDAY            (uint32_t)24U
00057 #define RTC_OFFSET_DAY                (uint32_t)16U
00058 #define RTC_OFFSET_MONTH              (uint32_t)8U
00059 #define RTC_OFFSET_HOUR               (uint32_t)16U
00060 #define RTC_OFFSET_MINUTE             (uint32_t)8U
00061
00062 /**
00063   * @}
00064   */
00065
00066 /* Private macros ------------------------------------------------------------*/
00067 #if defined(USE_FULL_LL_DRIVER)
00068 /** @defgroup RTC_LL_Private_Macros RTC Private Macros
00069   * @{
00070   */
00071 /**
00072   * @}
00073   */
00074 #endif /*USE_FULL_LL_DRIVER*/
00075
00076 /* Exported types ------------------------------------------------------------*/
00077 #if defined(USE_FULL_LL_DRIVER)
00078 /** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
00079   * @{
00080   */
00081
00082 /**
00083   * @brief  RTC Init structures definition
00084   */
00085 typedef struct
00086 {
00087   uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
00088                               This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
00089
00090                               This feature can be modified afterwards using unitary function
00091                               @ref LL_RTC_SetHourFormat(). */
00092
00093   uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
00094                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
00095
00096                               This feature can be modified afterwards using unitary function
00097                               @ref LL_RTC_SetAsynchPrescaler(). */
00098
00099   uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
00100                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
00101
00102                               This feature can be modified afterwards using unitary function
00103                               @ref LL_RTC_SetSynchPrescaler(). */
00104 } LL_RTC_InitTypeDef;
00105
00106 /**
00107   * @brief  RTC Time structure definition
00108   */
00109 typedef struct
00110 {
00111   uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
00112                             This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
00113
00114                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
00115
00116   uint8_t Hours;       /*!< Specifies the RTC Time Hours.
00117                             This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
00118                             This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
00119
00120                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
00121
00122   uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
00123                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00124
00125                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
00126
00127   uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
00128                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00129
00130                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
00131 } LL_RTC_TimeTypeDef;
00132
00133 /**
00134   * @brief  RTC Date structure definition
00135   */
00136 typedef struct
00137 {
00138   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00139                          This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
00140
00141                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
00142
00143   uint8_t Month;    /*!< Specifies the RTC Date Month.
00144                          This parameter can be a value of @ref RTC_LL_EC_MONTH
00145
00146                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
00147
00148   uint8_t Day;      /*!< Specifies the RTC Date Day.
00149                          This parameter must be a number between Min_Data = 1 and Max_Data = 31
00150
00151                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
00152
00153   uint8_t Year;     /*!< Specifies the RTC Date Year.
00154                          This parameter must be a number between Min_Data = 0 and Max_Data = 99
00155
00156                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
00157 } LL_RTC_DateTypeDef;
00158
00159 /**
00160   * @brief  RTC Alarm structure definition
00161   */
00162 typedef struct
00163 {
00164   LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
00165
00166   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00167                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
00168
00169                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
00170                                       or @ref LL_RTC_ALMB_SetMask() for ALARM B
00171                                  */
00172
00173   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
00174                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
00175
00176                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
00177                                       for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
00178                                  */
00179
00180   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
00181                                       If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
00182
00183                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
00184                                       for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
00185
00186                                       If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
00187
00188                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
00189                                       for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
00190                                  */
00191 } LL_RTC_AlarmTypeDef;
00192
00193 /**
00194   * @}
00195   */
00196 #endif /* USE_FULL_LL_DRIVER */
00197
00198 /* Exported constants --------------------------------------------------------*/
00199 /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
00200   * @{
00201   */
00202
00203 #if defined(USE_FULL_LL_DRIVER)
00204 /** @defgroup RTC_LL_EC_FORMAT FORMAT
00205   * @{
00206   */
00207 #define LL_RTC_FORMAT_BIN                  0x00000000U /*!< Binary data format */
00208 #define LL_RTC_FORMAT_BCD                  0x00000001U /*!< BCD data format */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
00214   * @{
00215   */
00216 #define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
00217 #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
00223   * @{
00224   */
00225 #define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
00226 #define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
00227 /**
00228   * @}
00229   */
00230
00231 #endif /* USE_FULL_LL_DRIVER */
00232
00233 /** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
00234   * @brief    Flags defines which can be used with LL_RTC_ReadReg function
00235   * @{
00236   */
00237 #define LL_RTC_SCR_ITSF                    RTC_SCR_CITSF
00238 #define LL_RTC_SCR_TSOVF                   RTC_SCR_CTSOVF
00239 #define LL_RTC_SCR_TSF                     RTC_SCR_CTSF
00240 #define LL_RTC_SCR_WUTF                    RTC_SCR_CWUTF
00241 #define LL_RTC_SCR_ALRBF                   RTC_SCR_CALRBF
00242 #define LL_RTC_SCR_ALRAF                   RTC_SCR_CALRAF
00243
00244 #define LL_RTC_ICSR_RECALPF                RTC_ICSR_RECALPF
00245 #define LL_RTC_ICSR_INITF                  RTC_ICSR_INITF
00246 #define LL_RTC_ICSR_RSF                    RTC_ICSR_RSF
00247 #define LL_RTC_ICSR_INITS                  RTC_ICSR_INITS
00248 #define LL_RTC_ICSR_SHPF                   RTC_ICSR_SHPF
00249 #define LL_RTC_ICSR_WUTWF                  RTC_ICSR_WUTWF
00250 #define LL_RTC_ICSR_ALRBWF                 RTC_ICSR_ALRBWF
00251 #define LL_RTC_ICSR_ALRAWF                 RTC_ICSR_ALRAWF
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup RTC_LL_EC_IT IT Defines
00257   * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
00258   * @{
00259   */
00260 #define LL_RTC_CR_TSIE                     RTC_CR_TSIE
00261 #define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
00262 #define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
00263 #define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
00269   * @{
00270   */
00271 #define LL_RTC_WEEKDAY_MONDAY              ((uint8_t)0x01U) /*!< Monday    */
00272 #define LL_RTC_WEEKDAY_TUESDAY             ((uint8_t)0x02U) /*!< Tuesday   */
00273 #define LL_RTC_WEEKDAY_WEDNESDAY           ((uint8_t)0x03U) /*!< Wednesday */
00274 #define LL_RTC_WEEKDAY_THURSDAY            ((uint8_t)0x04U) /*!< Thursday  */
00275 #define LL_RTC_WEEKDAY_FRIDAY              ((uint8_t)0x05U) /*!< Friday    */
00276 #define LL_RTC_WEEKDAY_SATURDAY            ((uint8_t)0x06U) /*!< Saturday  */
00277 #define LL_RTC_WEEKDAY_SUNDAY              ((uint8_t)0x07U) /*!< Sunday    */
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup RTC_LL_EC_MONTH  MONTH
00283   * @{
00284   */
00285 #define LL_RTC_MONTH_JANUARY               ((uint8_t)0x01U)  /*!< January   */
00286 #define LL_RTC_MONTH_FEBRUARY              ((uint8_t)0x02U)  /*!< February  */
00287 #define LL_RTC_MONTH_MARCH                 ((uint8_t)0x03U)  /*!< March     */
00288 #define LL_RTC_MONTH_APRIL                 ((uint8_t)0x04U)  /*!< April     */
00289 #define LL_RTC_MONTH_MAY                   ((uint8_t)0x05U)  /*!< May       */
00290 #define LL_RTC_MONTH_JUNE                  ((uint8_t)0x06U)  /*!< June      */
00291 #define LL_RTC_MONTH_JULY                  ((uint8_t)0x07U)  /*!< July      */
00292 #define LL_RTC_MONTH_AUGUST                ((uint8_t)0x08U)  /*!< August    */
00293 #define LL_RTC_MONTH_SEPTEMBER             ((uint8_t)0x09U)  /*!< September */
00294 #define LL_RTC_MONTH_OCTOBER               ((uint8_t)0x10U)  /*!< October   */
00295 #define LL_RTC_MONTH_NOVEMBER              ((uint8_t)0x11U)  /*!< November  */
00296 #define LL_RTC_MONTH_DECEMBER              ((uint8_t)0x12U)  /*!< December  */
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
00302   * @{
00303   */
00304 #define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
00305 #define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
00311   * @{
00312   */
00313 #define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
00314 #define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
00315 #define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
00316 #define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
00322   * @{
00323   */
00324 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  RTC_CR_TAMPALRM_TYPE  /*!< RTC_ALARM is open-drain output */
00325 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   0x00000000U           /*!< RTC_ALARM is push-pull output */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
00331   * @{
00332   */
00333 #define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
00334 #define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
00340   * @{
00341   */
00342 #define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
00343 #define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
00349   * @{
00350   */
00351 #define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
00352 #define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
00358   * @{
00359   */
00360 #define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
00361 #define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
00362 #define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
00363 #define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
00364 #define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
00365 #define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
00371   * @{
00372   */
00373 #define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00374 #define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
00380   * @{
00381   */
00382 #define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
00383 #define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
00384 #define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
00385 #define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
00386 #define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
00387 #define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
00393   * @{
00394   */
00395 #define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00396 #define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
00402   * @{
00403   */
00404 #define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
00405 #define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
00411   * @{
00412   */
00413 #define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
00414 #define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
00415 /**
00416   * @}
00417   */
00418
00419 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
00420   * @{
00421   */
00422 #define LL_RTC_TAMPER_1                    TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */
00423 #define LL_RTC_TAMPER_2                    TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */
00424 #if defined (TAMP_CR1_TAMP3E)
00425 #define LL_RTC_TAMPER_3                    TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */
00426 #endif /* TAMP_CR1_TAMP3E */
00427 /**
00428   * @}
00429   */
00430
00431 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
00432   * @{
00433   */
00434 #define LL_RTC_TAMPER_MASK_TAMPER1         TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
00435 #define LL_RTC_TAMPER_MASK_TAMPER2         TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00436 #if defined (TAMP_CR1_TAMP3E)
00437 #define LL_RTC_TAMPER_MASK_TAMPER3         TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. */
00438 #endif /* TAMP_CR1_TAMP3E */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
00444   * @{
00445   */
00446 #define LL_RTC_TAMPER_NOERASE_TAMPER1      TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
00447 #define LL_RTC_TAMPER_NOERASE_TAMPER2      TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
00448 #if defined (TAMP_CR1_TAMP3E)
00449 #define LL_RTC_TAMPER_NOERASE_TAMPER3      TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
00450 #endif /* TAMP_CR1_TAMP3E */
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
00456   * @{
00457   */
00458 #define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U            /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
00459 #define LL_RTC_TAMPER_DURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
00460 #define LL_RTC_TAMPER_DURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
00461 #define LL_RTC_TAMPER_DURATION_8RTCCLK     TAMP_FLTCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
00467   * @{
00468   */
00469 #define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U             /*!< Tamper filter is disabled */
00470 #define LL_RTC_TAMPER_FILTER_2SAMPLE       TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
00471 #define LL_RTC_TAMPER_FILTER_4SAMPLE       TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
00472 #define LL_RTC_TAMPER_FILTER_8SAMPLE       TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
00478   * @{
00479   */
00480 #define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                     /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
00481 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
00482 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
00483 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
00484 #define LL_RTC_TAMPER_SAMPLFREQDIV_2048    TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
00485 #define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
00486 #define LL_RTC_TAMPER_SAMPLFREQDIV_512     (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
00487 #define LL_RTC_TAMPER_SAMPLFREQDIV_256     TAMP_FLTCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
00488 /**
00489   * @}
00490   */
00491
00492 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
00493   * @{
00494   */
00495 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00496 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00497 #if defined (TAMP_CR1_TAMP3E)
00498 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
00499 #endif /* TAMP_CR1_TAMP3E */
00500 /**
00501   * @}
00502   */
00503
00504
00505 /** @defgroup RTC_LL_EC_INTERNAL  INTERNAL TAMPER
00506   * @{
00507   */
00508 #define LL_RTC_TAMPER_ITAMP3           TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */
00509 #define LL_RTC_TAMPER_ITAMP4           TAMP_CR1_ITAMP4E /*!< Internal tamper 4: HSE monitoring */
00510 #define LL_RTC_TAMPER_ITAMP5           TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */
00511 #define LL_RTC_TAMPER_ITAMP6           TAMP_CR1_ITAMP6E /*!< Internal tamper 6: Test mode entry */
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup RTC_LL_EC_BKP  BACKUP
00517   * @{
00518   */
00519 #define LL_RTC_BKP_DR0                     0x00000000U
00520 #define LL_RTC_BKP_DR1                     0x00000001U
00521 #define LL_RTC_BKP_DR2                     0x00000002U
00522 #define LL_RTC_BKP_DR3                     0x00000003U
00523 #define LL_RTC_BKP_DR4                     0x00000004U
00524 /**
00525   * @}
00526   */
00527
00528 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
00529   * @{
00530   */
00531 #define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
00532 #define LL_RTC_WAKEUPCLOCK_DIV_8           RTC_CR_WUCKSEL_0                      /*!< RTC/8 clock is selected */
00533 #define LL_RTC_WAKEUPCLOCK_DIV_4           RTC_CR_WUCKSEL_1                      /*!< RTC/4 clock is selected */
00534 #define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
00535 #define LL_RTC_WAKEUPCLOCK_CKSPRE          RTC_CR_WUCKSEL_2                      /*!< ck_spre (usually 1 Hz) clock is selected */
00536 #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
00542   * @{
00543   */
00544 #define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
00545 #define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
00546 #define LL_RTC_CALIB_OUTPUT_512HZ          RTC_CR_COE                 /*!< Calibration output is 512 Hz */
00547 /**
00548   * @}
00549   */
00550
00551 /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
00552   * @{
00553   */
00554 #define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
00555 #define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
00556 /**
00557   * @}
00558   */
00559
00560 /** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
00561   * @{
00562   */
00563 #define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
00564 #define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
00565 #define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
00566 /**
00567   * @}
00568   */
00569
00570 /**
00571   * @}
00572   */
00573
00574 /* Exported macro ------------------------------------------------------------*/
00575 /** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
00576   * @{
00577   */
00578
00579 /** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
00580   * @{
00581   */
00582
00583 /**
00584   * @brief  Write a value in RTC register
00585   * @param  __INSTANCE__ RTC Instance
00586   * @param  __REG__ Register to be written
00587   * @param  __VALUE__ Value to be written in the register
00588   * @retval None
00589   */
00590 #define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00591
00592 /**
00593   * @brief  Read a value in RTC register
00594   * @param  __INSTANCE__ RTC Instance
00595   * @param  __REG__ Register to be read
00596   * @retval Register value
00597   */
00598 #define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup RTC_LL_EM_Convert Convert helper Macros
00604   * @{
00605   */
00606
00607 /**
00608   * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
00609   * @param  __VALUE__ Byte to be converted
00610   * @retval Converted byte
00611   */
00612 #define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
00613
00614 /**
00615   * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
00616   * @param  __VALUE__ BCD value to be converted
00617   * @retval Converted byte
00618   */
00619 #define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))
00620
00621 /**
00622   * @}
00623   */
00624
00625 /** @defgroup RTC_LL_EM_Date Date helper Macros
00626   * @{
00627   */
00628
00629 /**
00630   * @brief  Helper macro to retrieve weekday.
00631   * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
00632   * @retval Returned value can be one of the following values:
00633   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
00634   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
00635   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
00636   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
00637   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
00638   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
00639   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
00640   */
00641 #define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
00642
00643 /**
00644   * @brief  Helper macro to retrieve Year in BCD format
00645   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00646   * @retval Year in BCD format (0x00 . . . 0x99)
00647   */
00648 #define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
00649
00650 /**
00651   * @brief  Helper macro to retrieve Month in BCD format
00652   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00653   * @retval Returned value can be one of the following values:
00654   *         @arg @ref LL_RTC_MONTH_JANUARY
00655   *         @arg @ref LL_RTC_MONTH_FEBRUARY
00656   *         @arg @ref LL_RTC_MONTH_MARCH
00657   *         @arg @ref LL_RTC_MONTH_APRIL
00658   *         @arg @ref LL_RTC_MONTH_MAY
00659   *         @arg @ref LL_RTC_MONTH_JUNE
00660   *         @arg @ref LL_RTC_MONTH_JULY
00661   *         @arg @ref LL_RTC_MONTH_AUGUST
00662   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
00663   *         @arg @ref LL_RTC_MONTH_OCTOBER
00664   *         @arg @ref LL_RTC_MONTH_NOVEMBER
00665   *         @arg @ref LL_RTC_MONTH_DECEMBER
00666   */
00667 #define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
00668
00669 /**
00670   * @brief  Helper macro to retrieve Day in BCD format
00671   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00672   * @retval Day in BCD format (0x01 . . . 0x31)
00673   */
00674 #define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
00675
00676 /**
00677   * @}
00678   */
00679
00680 /** @defgroup RTC_LL_EM_Time Time helper Macros
00681   * @{
00682   */
00683
00684 /**
00685   * @brief  Helper macro to retrieve hour in BCD format
00686   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00687   * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
00688   */
00689 #define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
00690
00691 /**
00692   * @brief  Helper macro to retrieve minute in BCD format
00693   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00694   * @retval Minutes in BCD format (0x00. . .0x59)
00695   */
00696 #define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
00697
00698 /**
00699   * @brief  Helper macro to retrieve second in BCD format
00700   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00701   * @retval Seconds in  format (0x00. . .0x59)
00702   */
00703 #define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
00704
00705 /**
00706   * @}
00707   */
00708
00709 /**
00710   * @}
00711   */
00712
00713 /* Exported functions --------------------------------------------------------*/
00714 /** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
00715   * @{
00716   */
00717
00718 /** @defgroup RTC_LL_EF_Configuration Configuration
00719   * @{
00720   */
00721
00722 /**
00723   * @brief  Set Hours format (24 hour/day or AM/PM hour format)
00724   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00725   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00726   * @rmtoll RTC_CR           FMT           LL_RTC_SetHourFormat
00727   * @param  RTCx RTC Instance
00728   * @param  HourFormat This parameter can be one of the following values:
00729   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00730   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00731   * @retval None
00732   */
00733 __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
00734 {
00735   MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
00736 }
00737
00738 /**
00739   * @brief  Get Hours format (24 hour/day or AM/PM hour format)
00740   * @rmtoll RTC_CR           FMT           LL_RTC_GetHourFormat
00741   * @param  RTCx RTC Instance
00742   * @retval Returned value can be one of the following values:
00743   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00744   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00745   */
00746 __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
00747 {
00748   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
00749 }
00750
00751 /**
00752   * @brief  Select the flag to be routed to RTC_ALARM output
00753   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00754   * @rmtoll RTC_CR           OSEL          LL_RTC_SetAlarmOutEvent
00755   * @param  RTCx RTC Instance
00756   * @param  AlarmOutput This parameter can be one of the following values:
00757   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00758   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00759   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00760   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00761   * @retval None
00762   */
00763 __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
00764 {
00765   MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
00766 }
00767
00768 /**
00769   * @brief  Get the flag to be routed to RTC_ALARM output
00770   * @rmtoll RTC_CR           OSEL          LL_RTC_GetAlarmOutEvent
00771   * @param  RTCx RTC Instance
00772   * @retval Returned value can be one of the following values:
00773   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00774   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00775   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00776   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00777   */
00778 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
00779 {
00780   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
00781 }
00782
00783 /**
00784   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
00785   * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType
00786   * @param  RTCx RTC Instance
00787   * @param  Output This parameter can be one of the following values:
00788   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00789   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00790   * @retval None
00791   */
00792 __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
00793 {
00794   MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);
00795 }
00796
00797 /**
00798   * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
00799   * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType
00800   * @param  RTCx RTC Instance
00801   * @retval Returned value can be one of the following values:
00802   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00803   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00804   */
00805 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
00806 {
00807   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
00808 }
00809
00810 /**
00811   * @brief  Enable initialization mode
00812   * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
00813   *         and prescaler register (RTC_PRER).
00814   *         Counters are stopped and start counting from the new value when INIT is reset.
00815   * @rmtoll RTC_ICSR          INIT          LL_RTC_EnableInitMode
00816   * @param  RTCx RTC Instance
00817   * @retval None
00818   */
00819 __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
00820 {
00821   /* Set the Initialization mode */
00822   WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);
00823 }
00824
00825 /**
00826   * @brief  Disable initialization mode (Free running mode)
00827   * @rmtoll RTC_ICSR          INIT          LL_RTC_DisableInitMode
00828   * @param  RTCx RTC Instance
00829   * @retval None
00830   */
00831 __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
00832 {
00833   /* Exit Initialization mode */
00834   WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);
00835 }
00836
00837 /**
00838   * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
00839   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00840   * @rmtoll RTC_CR           POL           LL_RTC_SetOutputPolarity
00841   * @param  RTCx RTC Instance
00842   * @param  Polarity This parameter can be one of the following values:
00843   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00844   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00845   * @retval None
00846   */
00847 __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
00848 {
00849   MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
00850 }
00851
00852 /**
00853   * @brief  Get Output polarity
00854   * @rmtoll RTC_CR           POL           LL_RTC_GetOutputPolarity
00855   * @param  RTCx RTC Instance
00856   * @retval Returned value can be one of the following values:
00857   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00858   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00859   */
00860 __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
00861 {
00862   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
00863 }
00864
00865 /**
00866   * @brief  Enable Bypass the shadow registers
00867   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00868   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
00869   * @param  RTCx RTC Instance
00870   * @retval None
00871   */
00872 __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
00873 {
00874   SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
00875 }
00876
00877 /**
00878   * @brief  Disable Bypass the shadow registers
00879   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
00880   * @param  RTCx RTC Instance
00881   * @retval None
00882   */
00883 __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
00884 {
00885   CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
00886 }
00887
00888 /**
00889   * @brief  Check if Shadow registers bypass is enabled or not.
00890   * @rmtoll RTC_CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
00891   * @param  RTCx RTC Instance
00892   * @retval State of bit (1 or 0).
00893   */
00894 __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
00895 {
00896   return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
00897 }
00898
00899 /**
00900   * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
00901   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00902   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00903   * @rmtoll RTC_CR           REFCKON       LL_RTC_EnableRefClock
00904   * @param  RTCx RTC Instance
00905   * @retval None
00906   */
00907 __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
00908 {
00909   SET_BIT(RTCx->CR, RTC_CR_REFCKON);
00910 }
00911
00912 /**
00913   * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
00914   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00915   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00916   * @rmtoll RTC_CR           REFCKON       LL_RTC_DisableRefClock
00917   * @param  RTCx RTC Instance
00918   * @retval None
00919   */
00920 __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
00921 {
00922   CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
00923 }
00924
00925 /**
00926   * @brief  Set Asynchronous prescaler factor
00927   * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
00928   * @param  RTCx RTC Instance
00929   * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
00930   * @retval None
00931   */
00932 __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
00933 {
00934   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
00935 }
00936
00937 /**
00938   * @brief  Set Synchronous prescaler factor
00939   * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
00940   * @param  RTCx RTC Instance
00941   * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
00942   * @retval None
00943   */
00944 __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
00945 {
00946   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
00947 }
00948
00949 /**
00950   * @brief  Get Asynchronous prescaler factor
00951   * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
00952   * @param  RTCx RTC Instance
00953   * @retval Value between Min_Data = 0 and Max_Data = 0x7F
00954   */
00955 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
00956 {
00957   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
00958 }
00959
00960 /**
00961   * @brief  Get Synchronous prescaler factor
00962   * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
00963   * @param  RTCx RTC Instance
00964   * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
00965   */
00966 __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
00967 {
00968   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
00969 }
00970
00971 /**
00972   * @brief  Enable the write protection for RTC registers.
00973   * @rmtoll RTC_WPR          KEY           LL_RTC_EnableWriteProtection
00974   * @param  RTCx RTC Instance
00975   * @retval None
00976   */
00977 __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
00978 {
00979   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
00980 }
00981
00982 /**
00983   * @brief  Disable the write protection for RTC registers.
00984   * @rmtoll RTC_WPR          KEY           LL_RTC_DisableWriteProtection
00985   * @param  RTCx RTC Instance
00986   * @retval None
00987   */
00988 __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
00989 {
00990   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
00991   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
00992 }
00993
00994 /**
00995   * @brief  Enable tamper output.
00996   * @note When the tamper output is enabled, all external and internal tamper flags
00997   *       are ORed and routed to the TAMPALRM output.
00998   * @rmtoll RTC_CR           TAMPOE       LL_RTC_EnableTamperOutput
00999   * @param  RTCx RTC Instance
01000   * @retval None
01001   */
01002 __STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)
01003 {
01004   SET_BIT(RTCx->CR, RTC_CR_TAMPOE);
01005 }
01006
01007 /**
01008   * @brief  Disable tamper output.
01009   * @rmtoll RTC_CR           TAMPOE       LL_RTC_DisableTamperOutput
01010   * @param  RTCx RTC Instance
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)
01014 {
01015   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);
01016 }
01017
01018 /**
01019   * @brief  Check if tamper output is enabled or not.
01020   * @rmtoll RTC_CR           TAMPOE       LL_RTC_IsTamperOutputEnabled
01021   * @param  RTCx RTC Instance
01022   * @retval State of bit (1 or 0).
01023   */
01024 __STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
01025 {
01026   return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL);
01027 }
01028
01029 /**
01030   * @brief  Enable internal pull-up in output mode.
01031   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
01032   * @param  RTCx RTC Instance
01033   * @retval None
01034   */
01035 __STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)
01036 {
01037   SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
01038 }
01039
01040 /**
01041   * @brief  Disable internal pull-up in output mode.
01042   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
01043   * @param  RTCx RTC Instance
01044   * @retval None
01045   */
01046 __STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)
01047 {
01048   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
01049 }
01050
01051 /**
01052   * @brief  Check if internal pull-up in output mode is enabled or not.
01053   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_IsAlarmPullUpEnabled
01054   * @param  RTCx RTC Instance
01055   * @retval State of bit (1 or 0).
01056   */
01057 __STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
01058 {
01059   return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL);
01060 }
01061
01062 /**
01063   * @brief  Enable RTC_OUT2 output
01064   * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)
01065   *       and COE (@ref LL_RTC_CAL_SetOutputFreq) settings.
01066   * @note RTC_OUT2 is not available ins VBAT mode.
01067   * @rmtoll RTC_CR           OUT2EN       LL_RTC_EnableOutput2
01068   * @param  RTCx RTC Instance
01069   * @retval None
01070   */
01071 __STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)
01072 {
01073   SET_BIT(RTCx->CR, RTC_CR_OUT2EN);
01074 }
01075
01076 /**
01077   * @brief  Disable RTC_OUT2 output
01078   * @rmtoll RTC_CR           OUT2EN       LL_RTC_DisableOutput2
01079   * @param  RTCx RTC Instance
01080   * @retval None
01081   */
01082 __STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)
01083 {
01084   CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);
01085 }
01086
01087 /**
01088   * @brief  Check if RTC_OUT2 output is enabled or not.
01089   * @rmtoll RTC_CR           OUT2EN       LL_RTC_IsOutput2Enabled
01090   * @param  RTCx RTC Instance
01091   * @retval State of bit (1 or 0).
01092   */
01093 __STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
01094 {
01095   return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL);
01096 }
01097
01098 /**
01099   * @}
01100   */
01101
01102 /** @defgroup RTC_LL_EF_Time Time
01103   * @{
01104   */
01105
01106 /**
01107   * @brief  Set time format (AM/24-hour or PM notation)
01108   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01109   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01110   * @rmtoll RTC_TR           PM            LL_RTC_TIME_SetFormat
01111   * @param  RTCx RTC Instance
01112   * @param  TimeFormat This parameter can be one of the following values:
01113   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01114   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01115   * @retval None
01116   */
01117 __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01118 {
01119   MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
01120 }
01121
01122 /**
01123   * @brief  Get time format (AM or PM notation)
01124   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01125   *       before reading this bit
01126   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01127   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01128   * @rmtoll RTC_TR           PM            LL_RTC_TIME_GetFormat
01129   * @param  RTCx RTC Instance
01130   * @retval Returned value can be one of the following values:
01131   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01132   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01133   */
01134 __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
01135 {
01136   return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
01137 }
01138
01139 /**
01140   * @brief  Set Hours in BCD format
01141   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01142   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01143   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
01144   * @rmtoll RTC_TR           HT            LL_RTC_TIME_SetHour\n
01145   *         RTC_TR           HU            LL_RTC_TIME_SetHour
01146   * @param  RTCx RTC Instance
01147   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01148   * @retval None
01149   */
01150 __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01151 {
01152   MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
01153              (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
01154 }
01155
01156 /**
01157   * @brief  Get Hours in BCD format
01158   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01159   *       before reading this bit
01160   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01161   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01162   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
01163   *       Binary format
01164   * @rmtoll RTC_TR           HT            LL_RTC_TIME_GetHour\n
01165   *         RTC_TR           HU            LL_RTC_TIME_GetHour
01166   * @param  RTCx RTC Instance
01167   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01168   */
01169 __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
01170 {
01171   return ((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
01172 }
01173
01174 /**
01175   * @brief  Set Minutes in BCD format
01176   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01177   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01178   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01179   * @rmtoll RTC_TR           MNT           LL_RTC_TIME_SetMinute\n
01180   *         RTC_TR           MNU           LL_RTC_TIME_SetMinute
01181   * @param  RTCx RTC Instance
01182   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01183   * @retval None
01184   */
01185 __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01186 {
01187   MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
01188              (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
01189 }
01190
01191 /**
01192   * @brief  Get Minutes in BCD format
01193   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01194   *       before reading this bit
01195   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01196   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01197   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
01198   *       to Binary format
01199   * @rmtoll RTC_TR           MNT           LL_RTC_TIME_GetMinute\n
01200   *         RTC_TR           MNU           LL_RTC_TIME_GetMinute
01201   * @param  RTCx RTC Instance
01202   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01203   */
01204 __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
01205 {
01206   return ((READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)))>> RTC_TR_MNU_Pos);
01207 }
01208
01209 /**
01210   * @brief  Set Seconds in BCD format
01211   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01212   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01213   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01214   * @rmtoll RTC_TR           ST            LL_RTC_TIME_SetSecond\n
01215   *         RTC_TR           SU            LL_RTC_TIME_SetSecond
01216   * @param  RTCx RTC Instance
01217   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01218   * @retval None
01219   */
01220 __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01221 {
01222   MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
01223              (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
01224 }
01225
01226 /**
01227   * @brief  Get Seconds in BCD format
01228   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01229   *       before reading this bit
01230   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01231   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01232   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
01233   *       to Binary format
01234   * @rmtoll RTC_TR           ST            LL_RTC_TIME_GetSecond\n
01235   *         RTC_TR           SU            LL_RTC_TIME_GetSecond
01236   * @param  RTCx RTC Instance
01237   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01238   */
01239 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
01240 {
01241   return ((READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU))) >> RTC_TR_SU_Pos);
01242 }
01243
01244 /**
01245   * @brief  Set time (hour, minute and second) in BCD format
01246   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01247   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01248   * @note TimeFormat and Hours should follow the same format
01249   * @rmtoll RTC_TR           PM            LL_RTC_TIME_Config\n
01250   *         RTC_TR           HT            LL_RTC_TIME_Config\n
01251   *         RTC_TR           HU            LL_RTC_TIME_Config\n
01252   *         RTC_TR           MNT           LL_RTC_TIME_Config\n
01253   *         RTC_TR           MNU           LL_RTC_TIME_Config\n
01254   *         RTC_TR           ST            LL_RTC_TIME_Config\n
01255   *         RTC_TR           SU            LL_RTC_TIME_Config
01256   * @param  RTCx RTC Instance
01257   * @param  Format12_24 This parameter can be one of the following values:
01258   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01259   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01260   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01261   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01262   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01263   * @retval None
01264   */
01265 __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
01266 {
01267   uint32_t temp;
01268
01269   temp = Format12_24                                                                            | \
01270          (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))       | \
01271          (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
01272          (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
01273   MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
01274 }
01275
01276 /**
01277   * @brief  Get time (hour, minute and second) in BCD format
01278   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01279   *       before reading this bit
01280   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01281   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01282   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01283   *       are available to get independently each parameter.
01284   * @rmtoll RTC_TR           HT            LL_RTC_TIME_Get\n
01285   *         RTC_TR           HU            LL_RTC_TIME_Get\n
01286   *         RTC_TR           MNT           LL_RTC_TIME_Get\n
01287   *         RTC_TR           MNU           LL_RTC_TIME_Get\n
01288   *         RTC_TR           ST            LL_RTC_TIME_Get\n
01289   *         RTC_TR           SU            LL_RTC_TIME_Get
01290   * @param  RTCx RTC Instance
01291   * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
01292   */
01293 __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
01294 {
01295   uint32_t temp;
01296
01297   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
01298   return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) |  \
01299                     (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
01300                     ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
01301 }
01302
01303 /**
01304   * @brief  Memorize whether the daylight saving time change has been performed
01305   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01306   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_EnableDayLightStore
01307   * @param  RTCx RTC Instance
01308   * @retval None
01309   */
01310 __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
01311 {
01312   SET_BIT(RTCx->CR, RTC_CR_BKP);
01313 }
01314
01315 /**
01316   * @brief  Disable memorization whether the daylight saving time change has been performed.
01317   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01318   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_DisableDayLightStore
01319   * @param  RTCx RTC Instance
01320   * @retval None
01321   */
01322 __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
01323 {
01324   CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
01325 }
01326
01327 /**
01328   * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
01329   * @rmtoll RTC_CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
01330   * @param  RTCx RTC Instance
01331   * @retval State of bit (1 or 0).
01332   */
01333 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
01334 {
01335   return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
01336 }
01337
01338 /**
01339   * @brief  Subtract 1 hour (winter time change)
01340   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01341   * @rmtoll RTC_CR           SUB1H         LL_RTC_TIME_DecHour
01342   * @param  RTCx RTC Instance
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
01346 {
01347   SET_BIT(RTCx->CR, RTC_CR_SUB1H);
01348 }
01349
01350 /**
01351   * @brief  Add 1 hour (summer time change)
01352   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01353   * @rmtoll RTC_CR           ADD1H         LL_RTC_TIME_IncHour
01354   * @param  RTCx RTC Instance
01355   * @retval None
01356   */
01357 __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
01358 {
01359   SET_BIT(RTCx->CR, RTC_CR_ADD1H);
01360 }
01361
01362 /**
01363   * @brief  Get Sub second value in the synchronous prescaler counter.
01364   * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
01365   *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
01366   *        SubSeconds value in second fraction ratio with time unit following
01367   *        generic formula:
01368   *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
01369   *        This conversion can be performed only if no shift operation is pending
01370   *        (ie. SHFP=0) when PREDIV_S >= SS.
01371   * @rmtoll RTC_SSR          SS            LL_RTC_TIME_GetSubSecond
01372   * @param  RTCx RTC Instance
01373   * @retval Sub second value (number between 0 and 65535)
01374   */
01375 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
01376 {
01377   return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
01378 }
01379
01380 /**
01381   * @brief  Synchronize to a remote clock with a high degree of precision.
01382   * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
01383   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01384   * @note   When REFCKON is set, firmware must not write to Shift control register.
01385   * @rmtoll RTC_SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
01386   *         RTC_SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
01387   * @param  RTCx RTC Instance
01388   * @param  ShiftSecond This parameter can be one of the following values:
01389   *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
01390   *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
01391   * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
01392   * @retval None
01393   */
01394 __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
01395 {
01396   WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
01397 }
01398
01399 /**
01400   * @}
01401   */
01402
01403 /** @defgroup RTC_LL_EF_Date Date
01404   * @{
01405   */
01406
01407 /**
01408   * @brief  Set Year in BCD format
01409   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
01410   * @rmtoll RTC_DR           YT            LL_RTC_DATE_SetYear\n
01411   *         RTC_DR           YU            LL_RTC_DATE_SetYear
01412   * @param  RTCx RTC Instance
01413   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01414   * @retval None
01415   */
01416 __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
01417 {
01418   MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
01419              (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
01420 }
01421
01422 /**
01423   * @brief  Get Year in BCD format
01424   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01425   *       before reading this bit
01426   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
01427   * @rmtoll RTC_DR           YT            LL_RTC_DATE_GetYear\n
01428   *         RTC_DR           YU            LL_RTC_DATE_GetYear
01429   * @param  RTCx RTC Instance
01430   * @retval Value between Min_Data=0x00 and Max_Data=0x99
01431   */
01432 __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
01433 {
01434   return ((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
01435 }
01436
01437 /**
01438   * @brief  Set Week day
01439   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_SetWeekDay
01440   * @param  RTCx RTC Instance
01441   * @param  WeekDay This parameter can be one of the following values:
01442   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01443   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01444   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01445   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01446   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01447   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01448   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01449   * @retval None
01450   */
01451 __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01452 {
01453   MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
01454 }
01455
01456 /**
01457   * @brief  Get Week day
01458   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01459   *       before reading this bit
01460   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_GetWeekDay
01461   * @param  RTCx RTC Instance
01462   * @retval Returned value can be one of the following values:
01463   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01464   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01465   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01466   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01467   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01468   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01469   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01470   */
01471 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
01472 {
01473   return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
01474 }
01475
01476 /**
01477   * @brief  Set Month in BCD format
01478   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
01479   * @rmtoll RTC_DR           MT            LL_RTC_DATE_SetMonth\n
01480   *         RTC_DR           MU            LL_RTC_DATE_SetMonth
01481   * @param  RTCx RTC Instance
01482   * @param  Month This parameter can be one of the following values:
01483   *         @arg @ref LL_RTC_MONTH_JANUARY
01484   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01485   *         @arg @ref LL_RTC_MONTH_MARCH
01486   *         @arg @ref LL_RTC_MONTH_APRIL
01487   *         @arg @ref LL_RTC_MONTH_MAY
01488   *         @arg @ref LL_RTC_MONTH_JUNE
01489   *         @arg @ref LL_RTC_MONTH_JULY
01490   *         @arg @ref LL_RTC_MONTH_AUGUST
01491   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01492   *         @arg @ref LL_RTC_MONTH_OCTOBER
01493   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01494   *         @arg @ref LL_RTC_MONTH_DECEMBER
01495   * @retval None
01496   */
01497 __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
01498 {
01499   MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
01500              (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
01501 }
01502
01503 /**
01504   * @brief  Get Month in BCD format
01505   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01506   *       before reading this bit
01507   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
01508   * @rmtoll RTC_DR           MT            LL_RTC_DATE_GetMonth\n
01509   *         RTC_DR           MU            LL_RTC_DATE_GetMonth
01510   * @param  RTCx RTC Instance
01511   * @retval Returned value can be one of the following values:
01512   *         @arg @ref LL_RTC_MONTH_JANUARY
01513   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01514   *         @arg @ref LL_RTC_MONTH_MARCH
01515   *         @arg @ref LL_RTC_MONTH_APRIL
01516   *         @arg @ref LL_RTC_MONTH_MAY
01517   *         @arg @ref LL_RTC_MONTH_JUNE
01518   *         @arg @ref LL_RTC_MONTH_JULY
01519   *         @arg @ref LL_RTC_MONTH_AUGUST
01520   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01521   *         @arg @ref LL_RTC_MONTH_OCTOBER
01522   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01523   *         @arg @ref LL_RTC_MONTH_DECEMBER
01524   */
01525 __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
01526 {
01527   return ((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos);
01528 }
01529
01530 /**
01531   * @brief  Set Day in BCD format
01532   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01533   * @rmtoll RTC_DR           DT            LL_RTC_DATE_SetDay\n
01534   *         RTC_DR           DU            LL_RTC_DATE_SetDay
01535   * @param  RTCx RTC Instance
01536   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01537   * @retval None
01538   */
01539 __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01540 {
01541   MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
01542              (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
01543 }
01544
01545 /**
01546   * @brief  Get Day in BCD format
01547   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01548   *       before reading this bit
01549   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01550   * @rmtoll RTC_DR           DT            LL_RTC_DATE_GetDay\n
01551   *         RTC_DR           DU            LL_RTC_DATE_GetDay
01552   * @param  RTCx RTC Instance
01553   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01554   */
01555 __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
01556 {
01557   return ((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
01558 }
01559
01560 /**
01561   * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
01562   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Config\n
01563   *         RTC_DR           MT            LL_RTC_DATE_Config\n
01564   *         RTC_DR           MU            LL_RTC_DATE_Config\n
01565   *         RTC_DR           DT            LL_RTC_DATE_Config\n
01566   *         RTC_DR           DU            LL_RTC_DATE_Config\n
01567   *         RTC_DR           YT            LL_RTC_DATE_Config\n
01568   *         RTC_DR           YU            LL_RTC_DATE_Config
01569   * @param  RTCx RTC Instance
01570   * @param  WeekDay This parameter can be one of the following values:
01571   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01572   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01573   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01574   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01575   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01576   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01577   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01578   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01579   * @param  Month This parameter can be one of the following values:
01580   *         @arg @ref LL_RTC_MONTH_JANUARY
01581   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01582   *         @arg @ref LL_RTC_MONTH_MARCH
01583   *         @arg @ref LL_RTC_MONTH_APRIL
01584   *         @arg @ref LL_RTC_MONTH_MAY
01585   *         @arg @ref LL_RTC_MONTH_JUNE
01586   *         @arg @ref LL_RTC_MONTH_JULY
01587   *         @arg @ref LL_RTC_MONTH_AUGUST
01588   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01589   *         @arg @ref LL_RTC_MONTH_OCTOBER
01590   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01591   *         @arg @ref LL_RTC_MONTH_DECEMBER
01592   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01593   * @retval None
01594   */
01595 __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
01596 {
01597   uint32_t temp;
01598
01599   temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
01600          (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
01601          (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
01602          (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
01603
01604   MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
01605 }
01606
01607 /**
01608   * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
01609   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01610   *       before reading this bit
01611   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
01612   * and __LL_RTC_GET_DAY are available to get independently each parameter.
01613   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Get\n
01614   *         RTC_DR           MT            LL_RTC_DATE_Get\n
01615   *         RTC_DR           MU            LL_RTC_DATE_Get\n
01616   *         RTC_DR           DT            LL_RTC_DATE_Get\n
01617   *         RTC_DR           DU            LL_RTC_DATE_Get\n
01618   *         RTC_DR           YT            LL_RTC_DATE_Get\n
01619   *         RTC_DR           YU            LL_RTC_DATE_Get
01620   * @param  RTCx RTC Instance
01621   * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
01622   */
01623 __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
01624 {
01625   uint32_t temp;
01626
01627   temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
01628   return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
01629                     (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
01630                     (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
01631                     ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
01632 }
01633
01634 /**
01635   * @}
01636   */
01637
01638 /** @defgroup RTC_LL_EF_ALARMA ALARMA
01639   * @{
01640   */
01641
01642 /**
01643   * @brief  Enable Alarm A
01644   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01645   * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Enable
01646   * @param  RTCx RTC Instance
01647   * @retval None
01648   */
01649 __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
01650 {
01651   SET_BIT(RTCx->CR, RTC_CR_ALRAE);
01652 }
01653
01654 /**
01655   * @brief  Disable Alarm A
01656   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01657   * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Disable
01658   * @param  RTCx RTC Instance
01659   * @retval None
01660   */
01661 __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
01662 {
01663   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
01664 }
01665
01666 /**
01667   * @brief  Specify the Alarm A masks.
01668   * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
01669   *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
01670   *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
01671   *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_SetMask
01672   * @param  RTCx RTC Instance
01673   * @param  Mask This parameter can be a combination of the following values:
01674   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01675   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01676   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01677   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01678   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01679   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01680   * @retval None
01681   */
01682 __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
01683 {
01684   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
01685 }
01686
01687 /**
01688   * @brief  Get the Alarm A masks.
01689   * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
01690   *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
01691   *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
01692   *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_GetMask
01693   * @param  RTCx RTC Instance
01694   * @retval Returned value can be can be a combination of the following values:
01695   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01696   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01697   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01698   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01699   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01700   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01701   */
01702 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
01703 {
01704   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
01705 }
01706
01707 /**
01708   * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
01709   * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
01710   * @param  RTCx RTC Instance
01711   * @retval None
01712   */
01713 __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
01714 {
01715   SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01716 }
01717
01718 /**
01719   * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
01720   * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
01721   * @param  RTCx RTC Instance
01722   * @retval None
01723   */
01724 __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
01725 {
01726   CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01727 }
01728
01729 /**
01730   * @brief  Set ALARM A Day in BCD format
01731   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01732   * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_SetDay\n
01733   *         RTC_ALRMAR       DU            LL_RTC_ALMA_SetDay
01734   * @param  RTCx RTC Instance
01735   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01736   * @retval None
01737   */
01738 __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01739 {
01740   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
01741              (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
01742 }
01743
01744 /**
01745   * @brief  Get ALARM A Day in BCD format
01746   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01747   * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_GetDay\n
01748   *         RTC_ALRMAR       DU            LL_RTC_ALMA_GetDay
01749   * @param  RTCx RTC Instance
01750   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01751   */
01752 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
01753 {
01754   return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
01755 }
01756
01757 /**
01758   * @brief  Set ALARM A Weekday
01759   * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
01760   * @param  RTCx RTC Instance
01761   * @param  WeekDay This parameter can be one of the following values:
01762   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01763   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01764   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01765   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01766   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01767   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01768   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01769   * @retval None
01770   */
01771 __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01772 {
01773   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
01774 }
01775
01776 /**
01777   * @brief  Get ALARM A Weekday
01778   * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
01779   * @param  RTCx RTC Instance
01780   * @retval Returned value can be one of the following values:
01781   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01782   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01783   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01784   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01785   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01786   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01787   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01788   */
01789 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
01790 {
01791   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
01792 }
01793
01794 /**
01795   * @brief  Set Alarm A time format (AM/24-hour or PM notation)
01796   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
01797   * @param  RTCx RTC Instance
01798   * @param  TimeFormat This parameter can be one of the following values:
01799   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01800   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01801   * @retval None
01802   */
01803 __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01804 {
01805   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
01806 }
01807
01808 /**
01809   * @brief  Get Alarm A time format (AM or PM notation)
01810   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
01811   * @param  RTCx RTC Instance
01812   * @retval Returned value can be one of the following values:
01813   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01814   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01815   */
01816 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
01817 {
01818   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
01819 }
01820
01821 /**
01822   * @brief  Set ALARM A Hours in BCD format
01823   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
01824   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_SetHour\n
01825   *         RTC_ALRMAR       HU            LL_RTC_ALMA_SetHour
01826   * @param  RTCx RTC Instance
01827   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01828   * @retval None
01829   */
01830 __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01831 {
01832   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
01833              (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
01834 }
01835
01836 /**
01837   * @brief  Get ALARM A Hours in BCD format
01838   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
01839   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetHour\n
01840   *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetHour
01841   * @param  RTCx RTC Instance
01842   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01843   */
01844 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
01845 {
01846   return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
01847 }
01848
01849 /**
01850   * @brief  Set ALARM A Minutes in BCD format
01851   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01852   * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
01853   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_SetMinute
01854   * @param  RTCx RTC Instance
01855   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01856   * @retval None
01857   */
01858 __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01859 {
01860   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
01861              (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
01862 }
01863
01864 /**
01865   * @brief  Get ALARM A Minutes in BCD format
01866   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
01867   * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
01868   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetMinute
01869   * @param  RTCx RTC Instance
01870   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01871   */
01872 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
01873 {
01874   return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
01875 }
01876
01877 /**
01878   * @brief  Set ALARM A Seconds in BCD format
01879   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01880   * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
01881   *         RTC_ALRMAR       SU            LL_RTC_ALMA_SetSecond
01882   * @param  RTCx RTC Instance
01883   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01884   * @retval None
01885   */
01886 __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01887 {
01888   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
01889              (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
01890 }
01891
01892 /**
01893   * @brief  Get ALARM A Seconds in BCD format
01894   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
01895   * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
01896   *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetSecond
01897   * @param  RTCx RTC Instance
01898   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01899   */
01900 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
01901 {
01902   return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
01903 }
01904
01905 /**
01906   * @brief  Set Alarm A Time (hour, minute and second) in BCD format
01907   * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
01908   *         RTC_ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
01909   *         RTC_ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
01910   *         RTC_ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
01911   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
01912   *         RTC_ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
01913   *         RTC_ALRMAR       SU            LL_RTC_ALMA_ConfigTime
01914   * @param  RTCx RTC Instance
01915   * @param  Format12_24 This parameter can be one of the following values:
01916   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01917   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01918   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01919   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01920   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01921   * @retval None
01922   */
01923 __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
01924 {
01925   uint32_t temp;
01926
01927   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
01928          (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
01929          (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
01930
01931   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
01932 }
01933
01934 /**
01935   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
01936   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01937   * are available to get independently each parameter.
01938   * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetTime\n
01939   *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetTime\n
01940   *         RTC_ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
01941   *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
01942   *         RTC_ALRMAR       ST            LL_RTC_ALMA_GetTime\n
01943   *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetTime
01944   * @param  RTCx RTC Instance
01945   * @retval Combination of hours, minutes and seconds.
01946   */
01947 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
01948 {
01949   return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
01950 }
01951
01952 /**
01953   * @brief  Set Alarm A Mask the most-significant bits starting at this bit
01954   * @note This register can be written only when ALRAE is reset in RTC_CR register,
01955   *       or in initialization mode.
01956   * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
01957   * @param  RTCx RTC Instance
01958   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
01959   * @retval None
01960   */
01961 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
01962 {
01963   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
01964 }
01965
01966 /**
01967   * @brief  Get Alarm A Mask the most-significant bits starting at this bit
01968   * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
01969   * @param  RTCx RTC Instance
01970   * @retval Value between Min_Data=0x00 and Max_Data=0xF
01971   */
01972 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
01973 {
01974   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
01975 }
01976
01977 /**
01978   * @brief  Set Alarm A Sub seconds value
01979   * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
01980   * @param  RTCx RTC Instance
01981   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
01982   * @retval None
01983   */
01984 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
01985 {
01986   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
01987 }
01988
01989 /**
01990   * @brief  Get Alarm A Sub seconds value
01991   * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
01992   * @param  RTCx RTC Instance
01993   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
01994   */
01995 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
01996 {
01997   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
01998 }
01999
02000 /**
02001   * @}
02002   */
02003
02004 /** @defgroup RTC_LL_EF_ALARMB ALARMB
02005   * @{
02006   */
02007
02008 /**
02009   * @brief  Enable Alarm B
02010   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02011   * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Enable
02012   * @param  RTCx RTC Instance
02013   * @retval None
02014   */
02015 __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
02016 {
02017   SET_BIT(RTCx->CR, RTC_CR_ALRBE);
02018 }
02019
02020 /**
02021   * @brief  Disable Alarm B
02022   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02023   * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Disable
02024   * @param  RTCx RTC Instance
02025   * @retval None
02026   */
02027 __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
02028 {
02029   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
02030 }
02031
02032 /**
02033   * @brief  Specify the Alarm B masks.
02034   * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
02035   *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
02036   *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
02037   *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_SetMask
02038   * @param  RTCx RTC Instance
02039   * @param  Mask This parameter can be a combination of the following values:
02040   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02041   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02042   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02043   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02044   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02045   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02046   * @retval None
02047   */
02048 __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
02049 {
02050   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
02051 }
02052
02053 /**
02054   * @brief  Get the Alarm B masks.
02055   * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
02056   *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
02057   *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
02058   *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_GetMask
02059   * @param  RTCx RTC Instance
02060   * @retval Returned value can be can be a combination of the following values:
02061   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02062   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02063   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02064   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02065   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02066   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02067   */
02068 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
02069 {
02070   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
02071 }
02072
02073 /**
02074   * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
02075   * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
02076   * @param  RTCx RTC Instance
02077   * @retval None
02078   */
02079 __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
02080 {
02081   SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02082 }
02083
02084 /**
02085   * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
02086   * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
02087   * @param  RTCx RTC Instance
02088   * @retval None
02089   */
02090 __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
02091 {
02092   CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02093 }
02094
02095 /**
02096   * @brief  Set ALARM B Day in BCD format
02097   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
02098   * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_SetDay\n
02099   *         RTC_ALRMBR       DU            LL_RTC_ALMB_SetDay
02100   * @param  RTCx RTC Instance
02101   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
02102   * @retval None
02103   */
02104 __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
02105 {
02106   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
02107              (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
02108 }
02109
02110 /**
02111   * @brief  Get ALARM B Day in BCD format
02112   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02113   * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_GetDay\n
02114   *         RTC_ALRMBR       DU            LL_RTC_ALMB_GetDay
02115   * @param  RTCx RTC Instance
02116   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02117   */
02118 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
02119 {
02120   return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
02121 }
02122
02123 /**
02124   * @brief  Set ALARM B Weekday
02125   * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
02126   * @param  RTCx RTC Instance
02127   * @param  WeekDay This parameter can be one of the following values:
02128   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02129   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02130   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02131   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02132   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02133   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02134   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02135   * @retval None
02136   */
02137 __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
02138 {
02139   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
02140 }
02141
02142 /**
02143   * @brief  Get ALARM B Weekday
02144   * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
02145   * @param  RTCx RTC Instance
02146   * @retval Returned value can be one of the following values:
02147   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02148   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02149   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02150   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02151   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02152   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02153   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02154   */
02155 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
02156 {
02157   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
02158 }
02159
02160 /**
02161   * @brief  Set ALARM B time format (AM/24-hour or PM notation)
02162   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
02163   * @param  RTCx RTC Instance
02164   * @param  TimeFormat This parameter can be one of the following values:
02165   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02166   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02167   * @retval None
02168   */
02169 __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
02170 {
02171   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
02172 }
02173
02174 /**
02175   * @brief  Get ALARM B time format (AM or PM notation)
02176   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
02177   * @param  RTCx RTC Instance
02178   * @retval Returned value can be one of the following values:
02179   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02180   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02181   */
02182 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
02183 {
02184   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
02185 }
02186
02187 /**
02188   * @brief  Set ALARM B Hours in BCD format
02189   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
02190   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_SetHour\n
02191   *         RTC_ALRMBR       HU            LL_RTC_ALMB_SetHour
02192   * @param  RTCx RTC Instance
02193   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02194   * @retval None
02195   */
02196 __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
02197 {
02198   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
02199              (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
02200 }
02201
02202 /**
02203   * @brief  Get ALARM B Hours in BCD format
02204   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02205   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetHour\n
02206   *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetHour
02207   * @param  RTCx RTC Instance
02208   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02209   */
02210 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
02211 {
02212   return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
02213 }
02214
02215 /**
02216   * @brief  Set ALARM B Minutes in BCD format
02217   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
02218   * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
02219   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_SetMinute
02220   * @param  RTCx RTC Instance
02221   * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
02222   * @retval None
02223   */
02224 __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
02225 {
02226   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
02227              (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
02228 }
02229
02230 /**
02231   * @brief  Get ALARM B Minutes in BCD format
02232   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02233   * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
02234   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetMinute
02235   * @param  RTCx RTC Instance
02236   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02237   */
02238 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
02239 {
02240   return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
02241 }
02242
02243 /**
02244   * @brief  Set ALARM B Seconds in BCD format
02245   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
02246   * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
02247   *         RTC_ALRMBR       SU            LL_RTC_ALMB_SetSecond
02248   * @param  RTCx RTC Instance
02249   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02250   * @retval None
02251   */
02252 __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
02253 {
02254   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
02255              (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
02256 }
02257
02258 /**
02259   * @brief  Get ALARM B Seconds in BCD format
02260   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02261   * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
02262   *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetSecond
02263   * @param  RTCx RTC Instance
02264   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02265   */
02266 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
02267 {
02268   return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
02269 }
02270
02271 /**
02272   * @brief  Set Alarm B Time (hour, minute and second) in BCD format
02273   * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
02274   *         RTC_ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
02275   *         RTC_ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
02276   *         RTC_ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
02277   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
02278   *         RTC_ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
02279   *         RTC_ALRMBR       SU            LL_RTC_ALMB_ConfigTime
02280   * @param  RTCx RTC Instance
02281   * @param  Format12_24 This parameter can be one of the following values:
02282   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02283   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02284   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02285   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02286   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02287   * @retval None
02288   */
02289 __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
02290 {
02291   uint32_t temp;
02292
02293   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
02294          (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
02295          (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
02296
02297   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
02298 }
02299
02300 /**
02301   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02302   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02303   * are available to get independently each parameter.
02304   * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetTime\n
02305   *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetTime\n
02306   *         RTC_ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
02307   *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
02308   *         RTC_ALRMBR       ST            LL_RTC_ALMB_GetTime\n
02309   *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetTime
02310   * @param  RTCx RTC Instance
02311   * @retval Combination of hours, minutes and seconds.
02312   */
02313 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
02314 {
02315   return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
02316 }
02317
02318 /**
02319   * @brief  Set Alarm B Mask the most-significant bits starting at this bit
02320   * @note This register can be written only when ALRBE is reset in RTC_CR register,
02321   *       or in initialization mode.
02322   * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
02323   * @param  RTCx RTC Instance
02324   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02325   * @retval None
02326   */
02327 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02328 {
02329   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
02330 }
02331
02332 /**
02333   * @brief  Get Alarm B Mask the most-significant bits starting at this bit
02334   * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
02335   * @param  RTCx RTC Instance
02336   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02337   */
02338 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
02339 {
02340   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
02341 }
02342
02343 /**
02344   * @brief  Set Alarm B Sub seconds value
02345   * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
02346   * @param  RTCx RTC Instance
02347   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02348   * @retval None
02349   */
02350 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02351 {
02352   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
02353 }
02354
02355 /**
02356   * @brief  Get Alarm B Sub seconds value
02357   * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
02358   * @param  RTCx RTC Instance
02359   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02360   */
02361 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
02362 {
02363   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
02364 }
02365
02366 /**
02367   * @}
02368   */
02369
02370 /** @defgroup RTC_LL_EF_Timestamp Timestamp
02371   * @{
02372   */
02373
02374 /**
02375   * @brief  Enable internal event timestamp
02376   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02377   * @rmtoll RTC_CR           ITSE          LL_RTC_TS_EnableInternalEvent
02378   * @param  RTCx RTC Instance
02379   * @retval None
02380   */
02381 __STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
02382 {
02383   SET_BIT(RTCx->CR, RTC_CR_ITSE);
02384 }
02385
02386 /**
02387   * @brief  Disable internal event timestamp
02388   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02389   * @rmtoll RTC_CR           ITSE          LL_RTC_TS_DisableInternalEvent
02390   * @param  RTCx RTC Instance
02391   * @retval None
02392   */
02393 __STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
02394 {
02395   CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
02396 }
02397
02398 /**
02399   * @brief  Enable Timestamp
02400   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02401   * @rmtoll RTC_CR           TSE           LL_RTC_TS_Enable
02402   * @param  RTCx RTC Instance
02403   * @retval None
02404   */
02405 __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
02406 {
02407   SET_BIT(RTCx->CR, RTC_CR_TSE);
02408 }
02409
02410 /**
02411   * @brief  Disable Timestamp
02412   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02413   * @rmtoll RTC_CR           TSE           LL_RTC_TS_Disable
02414   * @param  RTCx RTC Instance
02415   * @retval None
02416   */
02417 __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
02418 {
02419   CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
02420 }
02421
02422 /**
02423   * @brief  Set Time-stamp event active edge
02424   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02425   * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
02426   * @rmtoll RTC_CR           TSEDGE        LL_RTC_TS_SetActiveEdge
02427   * @param  RTCx RTC Instance
02428   * @param  Edge This parameter can be one of the following values:
02429   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02430   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02431   * @retval None
02432   */
02433 __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
02434 {
02435   MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
02436 }
02437
02438 /**
02439   * @brief  Get Time-stamp event active edge
02440   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02441   * @rmtoll RTC_CR           TSEDGE        LL_RTC_TS_GetActiveEdge
02442   * @param  RTCx RTC Instance
02443   * @retval Returned value can be one of the following values:
02444   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02445   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02446   */
02447 __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
02448 {
02449   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
02450 }
02451
02452 /**
02453   * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
02454   * @rmtoll RTC_TSTR         PM            LL_RTC_TS_GetTimeFormat
02455   * @param  RTCx RTC Instance
02456   * @retval Returned value can be one of the following values:
02457   *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
02458   *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
02459   */
02460 __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
02461 {
02462   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
02463 }
02464
02465 /**
02466   * @brief  Get Timestamp Hours in BCD format
02467   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02468   * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetHour\n
02469   *         RTC_TSTR         HU            LL_RTC_TS_GetHour
02470   * @param  RTCx RTC Instance
02471   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02472   */
02473 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
02474 {
02475   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
02476 }
02477
02478 /**
02479   * @brief  Get Timestamp Minutes in BCD format
02480   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02481   * @rmtoll RTC_TSTR         MNT           LL_RTC_TS_GetMinute\n
02482   *         RTC_TSTR         MNU           LL_RTC_TS_GetMinute
02483   * @param  RTCx RTC Instance
02484   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02485   */
02486 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
02487 {
02488   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
02489 }
02490
02491 /**
02492   * @brief  Get Timestamp Seconds in BCD format
02493   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02494   * @rmtoll RTC_TSTR         ST            LL_RTC_TS_GetSecond\n
02495   *         RTC_TSTR         SU            LL_RTC_TS_GetSecond
02496   * @param  RTCx RTC Instance
02497   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02498   */
02499 __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
02500 {
02501   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
02502 }
02503
02504 /**
02505   * @brief  Get Timestamp time (hour, minute and second) in BCD format
02506   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02507   * are available to get independently each parameter.
02508   * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetTime\n
02509   *         RTC_TSTR         HU            LL_RTC_TS_GetTime\n
02510   *         RTC_TSTR         MNT           LL_RTC_TS_GetTime\n
02511   *         RTC_TSTR         MNU           LL_RTC_TS_GetTime\n
02512   *         RTC_TSTR         ST            LL_RTC_TS_GetTime\n
02513   *         RTC_TSTR         SU            LL_RTC_TS_GetTime
02514   * @param  RTCx RTC Instance
02515   * @retval Combination of hours, minutes and seconds.
02516   */
02517 __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
02518 {
02519   return (uint32_t)(READ_BIT(RTCx->TSTR,
02520                              RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
02521 }
02522
02523 /**
02524   * @brief  Get Timestamp Week day
02525   * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetWeekDay
02526   * @param  RTCx RTC Instance
02527   * @retval Returned value can be one of the following values:
02528   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02529   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02530   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02531   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02532   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02533   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02534   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02535   */
02536 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
02537 {
02538   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
02539 }
02540
02541 /**
02542   * @brief  Get Timestamp Month in BCD format
02543   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
02544   * @rmtoll RTC_TSDR         MT            LL_RTC_TS_GetMonth\n
02545   *         RTC_TSDR         MU            LL_RTC_TS_GetMonth
02546   * @param  RTCx RTC Instance
02547   * @retval Returned value can be one of the following values:
02548   *         @arg @ref LL_RTC_MONTH_JANUARY
02549   *         @arg @ref LL_RTC_MONTH_FEBRUARY
02550   *         @arg @ref LL_RTC_MONTH_MARCH
02551   *         @arg @ref LL_RTC_MONTH_APRIL
02552   *         @arg @ref LL_RTC_MONTH_MAY
02553   *         @arg @ref LL_RTC_MONTH_JUNE
02554   *         @arg @ref LL_RTC_MONTH_JULY
02555   *         @arg @ref LL_RTC_MONTH_AUGUST
02556   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
02557   *         @arg @ref LL_RTC_MONTH_OCTOBER
02558   *         @arg @ref LL_RTC_MONTH_NOVEMBER
02559   *         @arg @ref LL_RTC_MONTH_DECEMBER
02560   */
02561 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
02562 {
02563   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
02564 }
02565
02566 /**
02567   * @brief  Get Timestamp Day in BCD format
02568   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02569   * @rmtoll RTC_TSDR         DT            LL_RTC_TS_GetDay\n
02570   *         RTC_TSDR         DU            LL_RTC_TS_GetDay
02571   * @param  RTCx RTC Instance
02572   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02573   */
02574 __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
02575 {
02576   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
02577 }
02578
02579 /**
02580   * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
02581   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
02582   * and __LL_RTC_GET_DAY are available to get independently each parameter.
02583   * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetDate\n
02584   *         RTC_TSDR         MT            LL_RTC_TS_GetDate\n
02585   *         RTC_TSDR         MU            LL_RTC_TS_GetDate\n
02586   *         RTC_TSDR         DT            LL_RTC_TS_GetDate\n
02587   *         RTC_TSDR         DU            LL_RTC_TS_GetDate
02588   * @param  RTCx RTC Instance
02589   * @retval Combination of Weekday, Day and Month
02590   */
02591 __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
02592 {
02593   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
02594 }
02595
02596 /**
02597   * @brief  Get time-stamp sub second value
02598   * @rmtoll RTC_TSSSR         SS            LL_RTC_TS_GetSubSecond
02599   * @param  RTCx RTC Instance
02600   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
02601   */
02602 __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
02603 {
02604   return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
02605 }
02606
02607 /**
02608   * @brief  Activate timestamp on tamper detection event
02609   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper
02610   * @param  RTCx RTC Instance
02611   * @retval None
02612   */
02613 __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
02614 {
02615   SET_BIT(RTCx->CR, RTC_CR_TAMPTS);
02616 }
02617
02618 /**
02619   * @brief  Disable timestamp on tamper detection event
02620   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_DisableOnTamper
02621   * @param  RTCx RTC Instance
02622   * @retval None
02623   */
02624 __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
02625 {
02626   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
02627 }
02628
02629
02630 /**
02631   * @}
02632   */
02633
02634 /** @defgroup RTC_LL_EF_Tamper Tamper
02635   * @{
02636   */
02637
02638 /**
02639   * @brief  Enable TAMPx input detection
02640   * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Enable\n
02641   *         TAMP_CR1       TAMP2E        LL_RTC_TAMPER_Enable\n
02642   *         TAMP_CR1       TAMP3E        LL_RTC_TAMPER_Enable
02643   * @param  TAMPx TAMP Instance
02644   * @param  Tamper This parameter can be a combination of the following values:
02645   *         @arg @ref LL_RTC_TAMPER_1
02646   *         @arg @ref LL_RTC_TAMPER_2
02647   *         @arg @ref LL_RTC_TAMPER_3 (*)
02648   *
02649   * @retval None
02650   */
02651 __STATIC_INLINE void LL_RTC_TAMPER_Enable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
02652 {
02653   SET_BIT(TAMPx->CR1, Tamper);
02654 }
02655
02656 /**
02657   * @brief  Clear TAMPx input detection
02658   * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Disable\n
02659   *         TAMP_CR1       TAMP2E        LL_RTC_TAMPER_Disable\n
02660   *         TAMP_CR1       TAMP3E        LL_RTC_TAMPER_Disable
02661   * @param  TAMPx TAMP Instance
02662   * @param  Tamper This parameter can be a combination of the following values:
02663   *         @arg @ref LL_RTC_TAMPER_1
02664   *         @arg @ref LL_RTC_TAMPER_2
02665   *         @arg @ref LL_RTC_TAMPER_2 (*)
02666   *
02667   * @retval None
02668   */
02669 __STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
02670 {
02671   CLEAR_BIT(TAMPx->CR1, Tamper);
02672 }
02673
02674 /**
02675   * @brief  Enable Tamper mask flag
02676   * @note Associated Tamper IT must not enabled when tamper mask is set.
02677   * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_EnableMask\n
02678   *         TAMP_CR2       TAMP2MF       LL_RTC_TAMPER_EnableMask\n
02679   *         TAMP_CR2       TAMP3MF       LL_RTC_TAMPER_EnableMask
02680   * @param  TAMPx TAMP Instance
02681   * @param  Mask This parameter can be a combination of the following values:
02682   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
02683   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
02684   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*)
02685   *
02686   * @retval None
02687   */
02688 __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)
02689 {
02690   SET_BIT(TAMPx->CR2, Mask);
02691 }
02692
02693 /**
02694   * @brief  Disable Tamper mask flag
02695   * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_DisableMask\n
02696   *         TAMP_CR2       TAMP2MF       LL_RTC_TAMPER_DisableMask\n
02697   *         TAMP_CR2       TAMP3MF       LL_RTC_TAMPER_DisableMask
02698   * @param  TAMPx TAMP Instance
02699   * @param  Mask This parameter can be a combination of the following values:
02700   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
02701   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
02702   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*)
02703   *
02704   * @retval None
02705   */
02706 __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)
02707 {
02708   CLEAR_BIT(TAMPx->CR2, Mask);
02709 }
02710
02711 /**
02712   * @brief  Enable backup register erase after Tamper event detection
02713   * @rmtoll TAMP_CR2       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
02714   *         TAMP_CR2       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
02715   *         TAMP_CR2       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP
02716   * @param  TAMPx TAMP Instance
02717   * @param  Tamper This parameter can be a combination of the following values:
02718   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
02719   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
02720   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
02721   *
02722   * @retval None
02723   */
02724 __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)
02725 {
02726   CLEAR_BIT(TAMPx->CR2, Tamper);
02727 }
02728
02729 /**
02730   * @brief  Disable backup register erase after Tamper event detection
02731   * @rmtoll TAMP_CR2       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
02732   *         TAMP_CR2       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
02733   *         TAMP_CR2       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP
02734   * @param  TAMPx TAMP Instance
02735   * @param  Tamper This parameter can be a combination of the following values:
02736   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
02737   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
02738   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
02739   *
02740   * @retval None
02741   */
02742 __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)
02743 {
02744   SET_BIT(TAMPx->CR2, Tamper);
02745 }
02746
02747 /**
02748   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
02749   * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
02750   * @param  TAMPx TAMP Instance
02751   * @retval None
02752   */
02753 __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(TAMP_TypeDef *TAMPx)
02754 {
02755   SET_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);
02756 }
02757
02758 /**
02759   * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
02760   * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
02761   * @param  TAMPx TAMP Instance
02762   * @retval None
02763   */
02764 __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(TAMP_TypeDef *TAMPx)
02765 {
02766   CLEAR_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);
02767 }
02768
02769 /**
02770   * @brief  Set RTC_TAMPx precharge duration
02771   * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
02772   * @param  TAMPx TAMP Instance
02773   * @param  Duration This parameter can be one of the following values:
02774   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02775   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02776   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02777   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02778   * @retval None
02779   */
02780 __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Duration)
02781 {
02782   MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
02783 }
02784
02785 /**
02786   * @brief  Get RTC_TAMPx precharge duration
02787   * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
02788   * @param  TAMPx TAMP Instance
02789   * @retval Returned value can be one of the following values:
02790   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02791   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02792   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02793   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02794   */
02795 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx)
02796 {
02797   return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH));
02798 }
02799
02800 /**
02801   * @brief  Set RTC_TAMPx filter count
02802   * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
02803   * @param  TAMPx TAMP Instance
02804   * @param  FilterCount This parameter can be one of the following values:
02805   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02806   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02807   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02808   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02809   * @retval None
02810   */
02811 __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t FilterCount)
02812 {
02813   MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
02814 }
02815
02816 /**
02817   * @brief  Get RTC_TAMPx filter count
02818   * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
02819   * @param  TAMPx TAMP Instance
02820   * @retval Returned value can be one of the following values:
02821   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02822   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02823   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02824   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02825   */
02826 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx)
02827 {
02828   return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT));
02829 }
02830
02831 /**
02832   * @brief  Set Tamper sampling frequency
02833   * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
02834   * @param  TAMPx TAMP Instance
02835   * @param  SamplingFreq This parameter can be one of the following values:
02836   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02837   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02838   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02839   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02840   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02841   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02842   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02843   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02844   * @retval None
02845   */
02846 __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
02847 {
02848   MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
02849 }
02850
02851 /**
02852   * @brief  Get Tamper sampling frequency
02853   * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
02854   * @param  TAMPx TAMP Instance
02855   * @retval Returned value can be one of the following values:
02856   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02857   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02858   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02859   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02860   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02861   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02862   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02863   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02864   */
02865 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx)
02866 {
02867   return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ));
02868 }
02869
02870 /**
02871   * @brief  Enable Active level for Tamper input
02872   * @rmtoll TAMP_CR2       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel\n
02873   *         TAMP_CR2       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel\n
02874   *         TAMP_CR2       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
02875   * @param  TAMPx TAMP Instance
02876   * @param  Tamper This parameter can be a combination of the following values:
02877   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02878   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02879   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
02880   *
02881   * @retval None
02882   */
02883 __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)
02884 {
02885   SET_BIT(TAMPx->CR2, Tamper);
02886 }
02887
02888 /**
02889   * @brief  Disable Active level for Tamper input
02890   * @rmtoll TAMP_CR2       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02891   *         TAMP_CR2       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02892   *         TAMP_CR2       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
02893   * @param  TAMPx TAMP Instance
02894   * @param  Tamper This parameter can be a combination of the following values:
02895   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02896   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02897   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
02898   *
02899   * @retval None
02900   */
02901 __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)
02902 {
02903   CLEAR_BIT(TAMPx->CR2, Tamper);
02904 }
02905
02906 /**
02907   * @}
02908   */
02909
02910 /** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper
02911   * @{
02912   */
02913
02914 /**
02915   * @brief  Enable internal tamper detection.
02916   * @rmtoll TAMP_CR1       ITAMP3E       LL_RTC_TAMPER_ITAMP_Enable\n
02917   *         TAMP_CR1       ITAMP4E       LL_RTC_TAMPER_ITAMP_Enable\n
02918   *         TAMP_CR1       ITAMP5E       LL_RTC_TAMPER_ITAMP_Enable\n
02919   *         TAMP_CR1       ITAMP6E       LL_RTC_TAMPER_ITAMP_Enable\n
02920   * @param  TAMPx TAMP Instance
02921   * @param  InternalTamper This parameter can be a combination of the following values:
02922   *         @arg @ref LL_RTC_TAMPER_ITAMP3
02923   *         @arg @ref LL_RTC_TAMPER_ITAMP4
02924   *         @arg @ref LL_RTC_TAMPER_ITAMP5
02925   *         @arg @ref LL_RTC_TAMPER_ITAMP6
02926   *
02927   * @retval None
02928   */
02929 __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(TAMP_TypeDef *TAMPx, uint32_t InternalTamper)
02930 {
02931   SET_BIT(TAMPx->CR1, InternalTamper);
02932 }
02933
02934 /**
02935   * @brief  Disable internal tamper detection.
02936   * @rmtoll TAMP_CR1       ITAMP3E       LL_RTC_TAMPER_ITAMP_Disable\n
02937   *         TAMP_CR1       ITAMP4E       LL_RTC_TAMPER_ITAMP_Disable\n
02938   *         TAMP_CR1       ITAMP5E       LL_RTC_TAMPER_ITAMP_Disable\n
02939   *         TAMP_CR1       ITAMP6E       LL_RTC_TAMPER_ITAMP_Disable\n
02940   * @param  TAMPx TAMP Instance
02941   * @param  InternalTamper This parameter can be a combination of the following values:
02942   *         @arg @ref LL_RTC_TAMPER_ITAMP3
02943   *         @arg @ref LL_RTC_TAMPER_ITAMP4
02944   *         @arg @ref LL_RTC_TAMPER_ITAMP5
02945   *         @arg @ref LL_RTC_TAMPER_ITAMP6
02946   *
02947   * @retval None
02948   */
02949 __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(TAMP_TypeDef *TAMPx, uint32_t InternalTamper)
02950 {
02951   CLEAR_BIT(TAMPx->CR1, InternalTamper);
02952 }
02953
02954 /**
02955   * @}
02956   */
02957
02958
02959 /** @defgroup RTC_LL_EF_Wakeup Wakeup
02960   * @{
02961   */
02962
02963 /**
02964   * @brief  Enable Wakeup timer
02965   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02966   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Enable
02967   * @param  RTCx RTC Instance
02968   * @retval None
02969   */
02970 __STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
02971 {
02972   SET_BIT(RTCx->CR, RTC_CR_WUTE);
02973 }
02974
02975 /**
02976   * @brief  Disable Wakeup timer
02977   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02978   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Disable
02979   * @param  RTCx RTC Instance
02980   * @retval None
02981   */
02982 __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
02983 {
02984   CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
02985 }
02986
02987 /**
02988   * @brief  Check if Wakeup timer is enabled or not
02989   * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_IsEnabled
02990   * @param  RTCx RTC Instance
02991   * @retval State of bit (1 or 0).
02992   */
02993 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
02994 {
02995   return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
02996 }
02997
02998 /**
02999   * @brief  Select Wakeup clock
03000   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03001   * @note   Bit can be written only when WUTE bit = 0 and WUTWF bit = 1
03002   * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
03003   * @param  RTCx RTC Instance
03004   * @param  WakeupClock This parameter can be one of the following values:
03005   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03006   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03007   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03008   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03009   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03010   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03011   * @retval None
03012   */
03013 __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
03014 {
03015   MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
03016 }
03017
03018 /**
03019   * @brief  Get Wakeup clock
03020   * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
03021   * @param  RTCx RTC Instance
03022   * @retval Returned value can be one of the following values:
03023   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03024   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03025   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03026   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03027   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03028   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03029   */
03030 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
03031 {
03032   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
03033 }
03034
03035 /**
03036   * @brief  Set Wakeup auto-reload value
03037   * @note   Bit can be written only when WUTWF is set to 1
03038   * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
03039   * @param  RTCx RTC Instance
03040   * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
03041   * @retval None
03042   */
03043 __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
03044 {
03045   MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
03046 }
03047
03048 /**
03049   * @brief  Get Wakeup auto-reload value
03050   * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
03051   * @param  RTCx RTC Instance
03052   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
03053   */
03054 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
03055 {
03056   return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
03057 }
03058
03059 /**
03060   * @}
03061   */
03062
03063 /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
03064   * @{
03065   */
03066
03067 /**
03068   * @brief  Writes a data in a specified Backup data register.
03069   * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_SetRegister
03070   * @param  TAMPx RTC Instance
03071   * @param  BackupRegister This parameter can be one of the following values:
03072   *         @arg @ref LL_RTC_BKP_DR0
03073   *         @arg @ref LL_RTC_BKP_DR1
03074   *         @arg @ref LL_RTC_BKP_DR2
03075   *         @arg @ref LL_RTC_BKP_DR3
03076   *         @arg @ref LL_RTC_BKP_DR4
03077   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03078   * @retval None
03079   */
03080 __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
03081 {
03082   __IO uint32_t *tmp;
03083
03084   tmp = &(TAMPx->BKP0R) + BackupRegister;
03085
03086   /* Write the specified register */
03087   *tmp = Data;
03088 }
03089
03090 /**
03091   * @brief  Reads data from the specified RTC Backup data Register.
03092   * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_GetRegister
03093   * @param  TAMPx RTC Instance
03094   * @param  BackupRegister This parameter can be one of the following values:
03095   *         @arg @ref LL_RTC_BKP_DR0
03096   *         @arg @ref LL_RTC_BKP_DR1
03097   *         @arg @ref LL_RTC_BKP_DR2
03098   *         @arg @ref LL_RTC_BKP_DR3
03099   *         @arg @ref LL_RTC_BKP_DR4
03100   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03101   */
03102 __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
03103 {
03104   const __IO uint32_t *tmp;
03105
03106   tmp = &(TAMPx->BKP0R) + BackupRegister;
03107
03108   /* Read the specified register */
03109   return *tmp;
03110 }
03111
03112 /**
03113   * @}
03114   */
03115
03116 /** @defgroup RTC_LL_EF_Calibration Calibration
03117   * @{
03118   */
03119
03120 /**
03121   * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
03122   * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03123   * @rmtoll RTC_CR           COE           LL_RTC_CAL_SetOutputFreq\n
03124   *         RTC_CR           COSEL         LL_RTC_CAL_SetOutputFreq
03125   * @param  RTCx RTC Instance
03126   * @param  Frequency This parameter can be one of the following values:
03127   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03128   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03129   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03130   * @retval None
03131   */
03132 __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
03133 {
03134   MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
03135 }
03136
03137 /**
03138   * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
03139   * @rmtoll RTC_CR           COE           LL_RTC_CAL_GetOutputFreq\n
03140   *         RTC_CR           COSEL         LL_RTC_CAL_GetOutputFreq
03141   * @param  RTCx RTC Instance
03142   * @retval Returned value can be one of the following values:
03143   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03144   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03145   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03146   */
03147 __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
03148 {
03149   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
03150 }
03151
03152 /**
03153   * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
03154   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03155   * @note   Bit can be written only when RECALPF is set to 0
03156   * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_SetPulse
03157   * @param  RTCx RTC Instance
03158   * @param  Pulse This parameter can be one of the following values:
03159   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
03160   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
03161   * @retval None
03162   */
03163 __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
03164 {
03165   MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
03166 }
03167
03168 /**
03169   * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
03170   * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_IsPulseInserted
03171   * @param  RTCx RTC Instance
03172   * @retval State of bit (1 or 0).
03173   */
03174 __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
03175 {
03176   return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
03177 }
03178
03179 /**
03180   * @brief  Set the calibration cycle period
03181   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03182   * @note   Bit can be written only when RECALPF is set to 0
03183   * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_SetPeriod\n
03184   *         RTC_CALR         CALW16        LL_RTC_CAL_SetPeriod
03185   * @param  RTCx RTC Instance
03186   * @param  Period This parameter can be one of the following values:
03187   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03188   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03189   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03190   * @retval None
03191   */
03192 __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
03193 {
03194   MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
03195 }
03196
03197 /**
03198   * @brief  Get the calibration cycle period
03199   * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_GetPeriod\n
03200   *         RTC_CALR         CALW16        LL_RTC_CAL_GetPeriod
03201   * @param  RTCx RTC Instance
03202   * @retval Returned value can be one of the following values:
03203   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03204   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03205   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03206   */
03207 __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
03208 {
03209   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
03210 }
03211
03212 /**
03213   * @brief  Set Calibration minus
03214   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03215   * @note   Bit can be written only when RECALPF is set to 0
03216   * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_SetMinus
03217   * @param  RTCx RTC Instance
03218   * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
03219   * @retval None
03220   */
03221 __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
03222 {
03223   MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
03224 }
03225
03226 /**
03227   * @brief  Get Calibration minus
03228   * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_GetMinus
03229   * @param  RTCx RTC Instance
03230   * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
03231   */
03232 __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
03233 {
03234   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
03235 }
03236
03237 /**
03238   * @}
03239   */
03240
03241 /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
03242   * @{
03243   */
03244
03245 /**
03246   * @brief  Get Internal Time-stamp flag
03247   * @rmtoll RTC_SR          ITSF          LL_RTC_IsActiveFlag_ITS
03248   * @param  RTCx RTC Instance
03249   * @retval State of bit (1 or 0).
03250   */
03251 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
03252 {
03253   return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1UL : 0UL);
03254 }
03255
03256 /**
03257   * @brief  Get Recalibration pending Flag
03258   * @rmtoll RTC_ICSR          RECALPF       LL_RTC_IsActiveFlag_RECALP
03259   * @param  RTCx RTC Instance
03260   * @retval State of bit (1 or 0).
03261   */
03262 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
03263 {
03264   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL);
03265 }
03266
03267 /**
03268   * @brief  Get Time-stamp overflow flag
03269   * @rmtoll RTC_SR          TSOVF         LL_RTC_IsActiveFlag_TSOV
03270   * @param  RTCx RTC Instance
03271   * @retval State of bit (1 or 0).
03272   */
03273 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
03274 {
03275   return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL);
03276 }
03277
03278 /**
03279   * @brief  Get Time-stamp flag
03280   * @rmtoll RTC_SR          TSF           LL_RTC_IsActiveFlag_TS
03281   * @param  RTCx RTC Instance
03282   * @retval State of bit (1 or 0).
03283   */
03284 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
03285 {
03286   return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL);
03287 }
03288
03289 /**
03290   * @brief  Get Wakeup timer flag
03291   * @rmtoll RTC_SR          WUTF          LL_RTC_IsActiveFlag_WUT
03292   * @param  RTCx RTC Instance
03293   * @retval State of bit (1 or 0).
03294   */
03295 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
03296 {
03297   return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL);
03298 }
03299
03300 /**
03301   * @brief  Get Alarm B flag
03302   * @rmtoll RTC_SR          ALRBF         LL_RTC_IsActiveFlag_ALRB
03303   * @param  RTCx RTC Instance
03304   * @retval State of bit (1 or 0).
03305   */
03306 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
03307 {
03308   return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL);
03309 }
03310
03311 /**
03312   * @brief  Get Alarm A flag
03313   * @rmtoll RTC_SR          ALRAF         LL_RTC_IsActiveFlag_ALRA
03314   * @param  RTCx RTC Instance
03315   * @retval State of bit (1 or 0).
03316   */
03317 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
03318 {
03319   return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL);
03320 }
03321
03322 /**
03323   * @brief  Clear Internal Time-stamp flag
03324   * @rmtoll RTC_SCR          CITSF          LL_RTC_ClearFlag_ITS
03325   * @param  RTCx RTC Instance
03326   * @retval None
03327   */
03328 __STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
03329 {
03330   SET_BIT(RTCx->SCR, RTC_SCR_CITSF);
03331 }
03332
03333 /**
03334   * @brief  Clear Time-stamp overflow flag
03335   * @rmtoll RTC_SCR          CTSOVF         LL_RTC_ClearFlag_TSOV
03336   * @param  RTCx RTC Instance
03337   * @retval None
03338   */
03339 __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
03340 {
03341   SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);
03342 }
03343
03344 /**
03345   * @brief  Clear Time-stamp flag
03346   * @rmtoll RTC_SCR          CTSF           LL_RTC_ClearFlag_TS
03347   * @param  RTCx RTC Instance
03348   * @retval None
03349   */
03350 __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
03351 {
03352   SET_BIT(RTCx->SCR, RTC_SCR_CTSF);
03353 }
03354
03355 /**
03356   * @brief  Clear Wakeup timer flag
03357   * @rmtoll RTC_SCR          CWUTF          LL_RTC_ClearFlag_WUT
03358   * @param  RTCx RTC Instance
03359   * @retval None
03360   */
03361 __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
03362 {
03363   SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);
03364 }
03365
03366 /**
03367   * @brief  Clear Alarm B flag
03368   * @rmtoll RTC_SCR          CALRBF         LL_RTC_ClearFlag_ALRB
03369   * @param  RTCx RTC Instance
03370   * @retval None
03371   */
03372 __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
03373 {
03374   SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);
03375 }
03376
03377 /**
03378   * @brief  Clear Alarm A flag
03379   * @rmtoll RTC_SCR          CALRAF         LL_RTC_ClearFlag_ALRA
03380   * @param  RTCx RTC Instance
03381   * @retval None
03382   */
03383 __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
03384 {
03385   SET_BIT(RTCx->SCR, RTC_SCR_CALRAF);
03386 }
03387
03388 /**
03389   * @brief  Get Initialization flag
03390   * @rmtoll RTC_ICSR          INITF         LL_RTC_IsActiveFlag_INIT
03391   * @param  RTCx RTC Instance
03392   * @retval State of bit (1 or 0).
03393   */
03394 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
03395 {
03396   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL);
03397 }
03398
03399 /**
03400   * @brief  Get Registers synchronization flag
03401   * @rmtoll RTC_ICSR          RSF           LL_RTC_IsActiveFlag_RS
03402   * @param  RTCx RTC Instance
03403   * @retval State of bit (1 or 0).
03404   */
03405 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
03406 {
03407   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL);
03408 }
03409
03410 /**
03411   * @brief  Clear Registers synchronization flag
03412   * @rmtoll RTC_ICSR          RSF           LL_RTC_ClearFlag_RS
03413   * @param  RTCx RTC Instance
03414   * @retval None
03415   */
03416 __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
03417 {
03418   WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
03419 }
03420
03421 /**
03422   * @brief  Get Initialization status flag
03423   * @rmtoll RTC_ICSR          INITS         LL_RTC_IsActiveFlag_INITS
03424   * @param  RTCx RTC Instance
03425   * @retval State of bit (1 or 0).
03426   */
03427 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
03428 {
03429   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL);
03430 }
03431
03432 /**
03433   * @brief  Get Shift operation pending flag
03434   * @rmtoll RTC_ICSR          SHPF          LL_RTC_IsActiveFlag_SHP
03435   * @param  RTCx RTC Instance
03436   * @retval State of bit (1 or 0).
03437   */
03438 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
03439 {
03440   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL);
03441 }
03442
03443 /**
03444   * @brief  Get Wakeup timer write flag
03445   * @rmtoll RTC_ICSR          WUTWF         LL_RTC_IsActiveFlag_WUTW
03446   * @param  RTCx RTC Instance
03447   * @retval State of bit (1 or 0).
03448   */
03449 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
03450 {
03451   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL);
03452 }
03453
03454 /**
03455   * @brief  Get Alarm B write flag
03456   * @rmtoll RTC_ICSR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
03457   * @param  RTCx RTC Instance
03458   * @retval State of bit (1 or 0).
03459   */
03460 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
03461 {
03462   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1UL : 0UL);
03463 }
03464
03465 /**
03466   * @brief  Get Alarm A write flag
03467   * @rmtoll RTC_ICSR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
03468   * @param  RTCx RTC Instance
03469   * @retval State of bit (1 or 0).
03470   */
03471 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
03472 {
03473   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL);
03474 }
03475
03476 /**
03477   * @brief  Get Alarm A masked flag.
03478   * @rmtoll RTC_MISR          ALRAMF        LL_RTC_IsActiveFlag_ALRAM
03479   * @param  RTCx RTC Instance
03480   * @retval State of bit (1 or 0).
03481   */
03482 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)
03483 {
03484   return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL);
03485 }
03486
03487 /**
03488   * @brief  Get Alarm B masked flag.
03489   * @rmtoll RTC_MISR          ALRBMF        LL_RTC_IsActiveFlag_ALRBM
03490   * @param  RTCx RTC Instance
03491   * @retval State of bit (1 or 0).
03492   */
03493 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)
03494 {
03495   return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL);
03496 }
03497
03498 /**
03499   * @brief  Get Wakeup timer masked flag.
03500   * @rmtoll RTC_MISR          WUTMF        LL_RTC_IsActiveFlag_WUTM
03501   * @param  RTCx RTC Instance
03502   * @retval State of bit (1 or 0).
03503   */
03504 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)
03505 {
03506   return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL);
03507 }
03508
03509 /**
03510   * @brief  Get Time-stamp masked flag.
03511   * @rmtoll RTC_MISR          TSMF        LL_RTC_IsActiveFlag_TSM
03512   * @param  RTCx RTC Instance
03513   * @retval State of bit (1 or 0).
03514   */
03515 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)
03516 {
03517   return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL);
03518 }
03519
03520 /**
03521   * @brief  Get Time-stamp overflow masked flag.
03522   * @rmtoll RTC_MISR          TSOVMF        LL_RTC_IsActiveFlag_TSOVM
03523   * @param  RTCx RTC Instance
03524   * @retval State of bit (1 or 0).
03525   */
03526 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)
03527 {
03528   return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL);
03529 }
03530
03531 /**
03532   * @brief  Get Internal Time-stamp masked flag.
03533   * @rmtoll RTC_MISR          ITSMF        LL_RTC_IsActiveFlag_ITSM
03534   * @param  RTCx RTC Instance
03535   * @retval State of bit (1 or 0).
03536   */
03537 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
03538 {
03539   return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL);
03540 }
03541
03542 /**
03543   * @brief  Get tamper 1 detection flag.
03544   * @rmtoll TAMP_SR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
03545   * @param  TAMPx TAMP Instance
03546   * @retval State of bit (1 or 0).
03547   */
03548 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx)
03549 {
03550   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL);
03551 }
03552
03553 /**
03554   * @brief  Get tamper 2 detection flag.
03555   * @rmtoll TAMP_SR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
03556   * @param  TAMPx TAMP Instance
03557   * @retval State of bit (1 or 0).
03558   */
03559 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx)
03560 {
03561   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL);
03562 }
03563
03564 #if defined (TAMP_CR1_TAMP3E)
03565 /**
03566   * @brief  Get tamper 3 detection flag.
03567   * @rmtoll TAMP_SR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
03568   * @param  TAMPx TAMP Instance
03569   * @retval State of bit (1 or 0).
03570   */
03571 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx)
03572 {
03573   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL);
03574 }
03575 #endif /* TAMP_CR1_TAMP3E */
03576 /**
03577   * @brief  Get internal tamper 3 detection flag.
03578   * @rmtoll TAMP_SR          ITAMP3F        LL_RTC_IsActiveFlag_ITAMP3
03579   * @param  TAMPx TAMP Instance
03580   * @retval State of bit (1 or 0).
03581   */
03582 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(TAMP_TypeDef *TAMPx)
03583 {
03584   return ((READ_BIT(TAMPx->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1UL : 0UL);
03585 }
03586
03587 /**
03588   * @brief  Get internal tamper 4 detection flag.
03589   * @rmtoll TAMP_SR          ITAMP3F        LL_RTC_IsActiveFlag_ITAMP4
03590   * @param  TAMPx TAMP Instance
03591   * @retval State of bit (1 or 0).
03592   */
03593 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(TAMP_TypeDef *TAMPx)
03594 {
03595   return ((READ_BIT(TAMPx->SR, TAMP_SR_ITAMP4F) == (TAMP_SR_ITAMP4F)) ? 1UL : 0UL);
03596 }
03597
03598 /**
03599   * @brief  Get internal tamper 5 detection flag.
03600   * @rmtoll TAMP_SR          ITAMP5F        LL_RTC_IsActiveFlag_ITAMP5
03601   * @param  TAMPx TAMP Instance
03602   * @retval State of bit (1 or 0).
03603   */
03604 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(TAMP_TypeDef *TAMPx)
03605 {
03606   return ((READ_BIT(TAMPx->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1UL : 0UL);
03607 }
03608
03609 /**
03610   * @brief  Get internal tamper 6 detection flag.
03611   * @rmtoll TAMP_SR          ITAMP6F        LL_RTC_IsActiveFlag_ITAMP6
03612   * @param  TAMPx TAMP Instance
03613   * @retval State of bit (1 or 0).
03614   */
03615 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(TAMP_TypeDef *TAMPx)
03616 {
03617   return ((READ_BIT(TAMPx->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1UL : 0UL);
03618 }
03619
03620
03621 /**
03622   * @brief  Get tamper 1 interrupt masked flag.
03623   * @rmtoll TAMP_MISR          TAMP1MF        LL_RTC_IsActiveFlag_TAMP1M
03624   * @param  TAMPx TAMP Instance
03625   * @retval State of bit (1 or 0).
03626   */
03627 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx)
03628 {
03629   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL);
03630 }
03631
03632 /**
03633   * @brief  Get tamper 2 interrupt masked flag.
03634   * @rmtoll TAMP_MISR          TAMP2MF        LL_RTC_IsActiveFlag_TAMP2M
03635   * @param  TAMPx TAMP Instance
03636   * @retval State of bit (1 or 0).
03637   */
03638 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx)
03639 {
03640   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL);
03641 }
03642
03643 #if defined (TAMP_CR1_TAMP3E)
03644 /**
03645   * @brief  Get tamper 3 interrupt masked flag.
03646   * @rmtoll TAMP_MISR          TAMP3MF        LL_RTC_IsActiveFlag_TAMP3M
03647   * @param  TAMPx TAMP Instance
03648   * @retval State of bit (1 or 0).
03649   */
03650 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx)
03651 {
03652   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL);
03653 }
03654 #endif /* TAMP_CR1_TAMP3E */
03655
03656 /**
03657   * @brief  Get internal tamper 3 interrupt masked flag.
03658   * @rmtoll TAMP_MISR          ITAMP3MF        LL_RTC_IsActiveFlag_ITAMP3M
03659   * @param  TAMPx TAMP Instance
03660   * @retval State of bit (1 or 0).
03661   */
03662 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(TAMP_TypeDef *TAMPx)
03663 {
03664   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1UL : 0UL);
03665 }
03666
03667 /**
03668   * @brief  Get internal tamper 4 interrupt masked flag.
03669   * @rmtoll TAMP_MISR          ITAMP4MF        LL_RTC_IsActiveFlag_ITAMP4M
03670   * @param  TAMPx TAMP Instance
03671   * @retval State of bit (1 or 0).
03672   */
03673 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(TAMP_TypeDef *TAMPx)
03674 {
03675   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_ITAMP4MF) == (TAMP_MISR_ITAMP4MF)) ? 1UL : 0UL);
03676 }
03677
03678 /**
03679   * @brief  Get internal tamper 5 interrupt masked flag.
03680   * @rmtoll TAMP_MISR          ITAMP5MF        LL_RTC_IsActiveFlag_ITAMP5M
03681   * @param  TAMPx TAMP Instance
03682   * @retval State of bit (1 or 0).
03683   */
03684 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(TAMP_TypeDef *TAMPx)
03685 {
03686   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1UL : 0UL);
03687 }
03688
03689 /**
03690   * @brief  Get internal tamper 6 interrupt masked flag.
03691   * @rmtoll TAMP_MISR          ITAMP6MF        LL_RTC_IsActiveFlag_ITAMP6M
03692   * @param  TAMPx TAMP Instance
03693   * @retval State of bit (1 or 0).
03694   */
03695 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(TAMP_TypeDef *TAMPx)
03696 {
03697   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1UL : 0UL);
03698 }
03699
03700
03701 /**
03702   * @brief  Clear tamper 1 detection flag.
03703   * @rmtoll TAMP_SCR          CTAMP1F         LL_RTC_ClearFlag_TAMP1
03704   * @param  TAMPx TAMP Instance
03705   * @retval None
03706   */
03707 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx)
03708 {
03709   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F);
03710 }
03711
03712 /**
03713   * @brief  Clear tamper 2 detection flag.
03714   * @rmtoll TAMP_SCR          CTAMP2F         LL_RTC_ClearFlag_TAMP2
03715   * @param  TAMPx TAMP Instance
03716   * @retval None
03717   */
03718 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx)
03719 {
03720   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F);
03721 }
03722
03723 #if defined (TAMP_CR1_TAMP3E)
03724 /**
03725   * @brief  Clear tamper 3 detection flag.
03726   * @rmtoll TAMP_SCR          CTAMP3F         LL_RTC_ClearFlag_TAMP3
03727   * @param  TAMPx TAMP Instance
03728   * @retval None
03729   */
03730 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(TAMP_TypeDef *TAMPx)
03731 {
03732   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F);
03733 }
03734 #endif /* TAMP_CR1_TAMP3E */
03735
03736 /**
03737   * @brief  Clear internal tamper 3 detection flag.
03738   * @rmtoll TAMP_SCR          CITAMP3F         LL_RTC_ClearFlag_ITAMP3
03739   * @param  TAMPx TAMP Instance
03740   * @retval None
03741   */
03742 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(TAMP_TypeDef *TAMPx)
03743 {
03744   SET_BIT(TAMPx->SCR, TAMP_SCR_CITAMP3F);
03745 }
03746
03747 /**
03748   * @brief  Clear internal tamper 4 detection flag.
03749   * @rmtoll TAMP_SCR          CITAMP4F         LL_RTC_ClearFlag_ITAMP4
03750   * @param  TAMPx TAMP Instance
03751   * @retval None
03752   */
03753 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4(TAMP_TypeDef *TAMPx)
03754 {
03755   SET_BIT(TAMPx->SCR, TAMP_SCR_CITAMP4F);
03756 }
03757
03758 /**
03759   * @brief  Clear internal tamper 5 detection flag.
03760   * @rmtoll TAMP_SCR          CITAMP5F         LL_RTC_ClearFlag_ITAMP5
03761   * @param  TAMPx TAMP Instance
03762   * @retval None
03763   */
03764 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(TAMP_TypeDef *TAMPx)
03765 {
03766   SET_BIT(TAMPx->SCR, TAMP_SCR_CITAMP5F);
03767 }
03768
03769 /**
03770   * @brief  Clear internal tamper 6 detection flag.
03771   * @rmtoll TAMP_SCR          CITAMP6F         LL_RTC_ClearFlag_ITAMP6
03772   * @param  TAMPx TAMP Instance
03773   * @retval None
03774   */
03775 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(TAMP_TypeDef *TAMPx)
03776 {
03777   SET_BIT(TAMPx->SCR, TAMP_SCR_CITAMP6F);
03778 }
03779
03780
03781 /**
03782   * @}
03783   */
03784
03785 /** @defgroup RTC_LL_EF_IT_Management IT_Management
03786   * @{
03787   */
03788
03789 /**
03790   * @brief  Enable Time-stamp interrupt
03791   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03792   * @rmtoll RTC_CR          TSIE         LL_RTC_EnableIT_TS
03793   * @param  RTCx RTC Instance
03794   * @retval None
03795   */
03796 __STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
03797 {
03798   SET_BIT(RTCx->CR, RTC_CR_TSIE);
03799 }
03800
03801 /**
03802   * @brief  Disable Time-stamp interrupt
03803   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03804   * @rmtoll RTC_CR          TSIE         LL_RTC_DisableIT_TS
03805   * @param  RTCx RTC Instance
03806   * @retval None
03807   */
03808 __STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
03809 {
03810   CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
03811 }
03812
03813 /**
03814   * @brief  Enable Wakeup timer interrupt
03815   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03816   * @rmtoll RTC_CR          WUTIE         LL_RTC_EnableIT_WUT
03817   * @param  RTCx RTC Instance
03818   * @retval None
03819   */
03820 __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
03821 {
03822   SET_BIT(RTCx->CR, RTC_CR_WUTIE);
03823 }
03824
03825 /**
03826   * @brief  Disable Wakeup timer interrupt
03827   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03828   * @rmtoll RTC_CR          WUTIE         LL_RTC_DisableIT_WUT
03829   * @param  RTCx RTC Instance
03830   * @retval None
03831   */
03832 __STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
03833 {
03834   CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
03835 }
03836
03837 /**
03838   * @brief  Enable Alarm B interrupt
03839   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03840   * @rmtoll RTC_CR           ALRBIE        LL_RTC_EnableIT_ALRB
03841   * @param  RTCx RTC Instance
03842   * @retval None
03843   */
03844 __STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
03845 {
03846   SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
03847 }
03848
03849 /**
03850   * @brief  Disable Alarm B interrupt
03851   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03852   * @rmtoll RTC_CR           ALRBIE        LL_RTC_DisableIT_ALRB
03853   * @param  RTCx RTC Instance
03854   * @retval None
03855   */
03856 __STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
03857 {
03858   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
03859 }
03860
03861 /**
03862   * @brief  Enable Alarm A interrupt
03863   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03864   * @rmtoll RTC_CR           ALRAIE        LL_RTC_EnableIT_ALRA
03865   * @param  RTCx RTC Instance
03866   * @retval None
03867   */
03868 __STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
03869 {
03870   SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
03871 }
03872
03873 /**
03874   * @brief  Disable Alarm A interrupt
03875   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03876   * @rmtoll RTC_CR           ALRAIE        LL_RTC_DisableIT_ALRA
03877   * @param  RTCx RTC Instance
03878   * @retval None
03879   */
03880 __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
03881 {
03882   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
03883 }
03884
03885 /**
03886   * @brief  Check if Time-stamp interrupt is enabled or not
03887   * @rmtoll RTC_CR           TSIE          LL_RTC_IsEnabledIT_TS
03888   * @param  RTCx RTC Instance
03889   * @retval State of bit (1 or 0).
03890   */
03891 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
03892 {
03893   return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
03894 }
03895
03896 /**
03897   * @brief  Check if Wakeup timer interrupt is enabled or not
03898   * @rmtoll RTC_CR           WUTIE         LL_RTC_IsEnabledIT_WUT
03899   * @param  RTCx RTC Instance
03900   * @retval State of bit (1 or 0).
03901   */
03902 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
03903 {
03904   return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
03905 }
03906
03907 /**
03908   * @brief  Check if Alarm B interrupt is enabled or not
03909   * @rmtoll RTC_CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
03910   * @param  RTCx RTC Instance
03911   * @retval State of bit (1 or 0).
03912   */
03913 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
03914 {
03915   return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
03916 }
03917
03918 /**
03919   * @brief  Check if Alarm A interrupt is enabled or not
03920   * @rmtoll RTC_CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
03921   * @param  RTCx RTC Instance
03922   * @retval State of bit (1 or 0).
03923   */
03924 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
03925 {
03926   return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
03927 }
03928
03929 /**
03930   * @brief  Enable tamper 1 interrupt.
03931   * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_EnableIT_TAMP1
03932   * @param  TAMPx TAMP Instance
03933   * @retval None
03934   */
03935 __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(TAMP_TypeDef *TAMPx)
03936 {
03937   SET_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
03938 }
03939
03940 /**
03941   * @brief  Disable tamper 1 interrupt.
03942   * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_DisableIT_TAMP1
03943   * @param  TAMPx TAMP Instance
03944   * @retval None
03945   */
03946 __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx)
03947 {
03948   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
03949 }
03950
03951 /**
03952   * @brief  Enable tamper 2 interrupt.
03953   * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_EnableIT_TAMP2
03954   * @param  TAMPx TAMP Instance
03955   * @retval None
03956   */
03957 __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(TAMP_TypeDef *TAMPx)
03958 {
03959   SET_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
03960 }
03961
03962 /**
03963   * @brief  Disable tamper 2 interrupt.
03964   * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_DisableIT_TAMP2
03965   * @param  TAMPx TAMP Instance
03966   * @retval None
03967   */
03968 __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx)
03969 {
03970   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
03971 }
03972
03973 #if defined (TAMP_CR1_TAMP3E)
03974 /**
03975   * @brief  Enable tamper 3 interrupt.
03976   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_EnableIT_TAMP3
03977   * @param  TAMPx TAMP Instance
03978   * @retval None
03979   */
03980 __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(TAMP_TypeDef *TAMPx)
03981 {
03982   SET_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
03983 }
03984
03985 /**
03986   * @brief  Disable tamper 3 interrupt.
03987   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_DisableIT_TAMP3
03988   * @param  TAMPx TAMP Instance
03989   * @retval None
03990   */
03991 __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(TAMP_TypeDef *TAMPx)
03992 {
03993   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
03994 }
03995 #endif /* TAMP_CR1_TAMP3E */
03996
03997 /**
03998   * @brief  Enable internal tamper 3 interrupt.
03999   * @rmtoll TAMP_IER           ITAMP3IE          LL_RTC_EnableIT_ITAMP3
04000   * @param  TAMPx TAMP Instance
04001   * @retval None
04002   */
04003 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(TAMP_TypeDef *TAMPx)
04004 {
04005   SET_BIT(TAMPx->IER, TAMP_IER_ITAMP3IE);
04006 }
04007
04008 /**
04009   * @brief  Disable internal tamper 3 interrupt.
04010   * @rmtoll TAMP_IER           ITAMP3IE          LL_RTC_DisableIT_ITAMP3
04011   * @param  TAMPx TAMP Instance
04012   * @retval None
04013   */
04014 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(TAMP_TypeDef *TAMPx)
04015 {
04016   CLEAR_BIT(TAMPx->IER, TAMP_IER_ITAMP3IE);
04017 }
04018
04019 /**
04020   * @brief  Enable internal tamper 4 interrupt.
04021   * @rmtoll TAMP_IER           ITAMP4IE          LL_RTC_EnableIT_ITAMP4
04022   * @param  TAMPx TAMP Instance
04023   * @retval None
04024   */
04025 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP4(TAMP_TypeDef *TAMPx)
04026 {
04027   SET_BIT(TAMPx->IER, TAMP_IER_ITAMP4IE);
04028 }
04029
04030 /**
04031   * @brief  Disable internal tamper 4 interrupt.
04032   * @rmtoll TAMP_IER           ITAMP4IE          LL_RTC_DisableIT_ITAMP4
04033   * @param  TAMPx TAMP Instance
04034   * @retval None
04035   */
04036 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP4(TAMP_TypeDef *TAMPx)
04037 {
04038   CLEAR_BIT(TAMPx->IER, TAMP_IER_ITAMP4IE);
04039 }
04040
04041 /**
04042   * @brief  Enable internal tamper 5 interrupt.
04043   * @rmtoll TAMP_IER           ITAMP5IE          LL_RTC_EnableIT_ITAMP5
04044   * @param  TAMPx TAMP Instance
04045   * @retval None
04046   */
04047 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(TAMP_TypeDef *TAMPx)
04048 {
04049   SET_BIT(TAMPx->IER, TAMP_IER_ITAMP5IE);
04050 }
04051
04052 /**
04053   * @brief  Disable internal tamper 5 interrupt.
04054   * @rmtoll TAMP_IER           ITAMP5IE          LL_RTC_DisableIT_ITAMP5
04055   * @param  TAMPx TAMP Instance
04056   * @retval None
04057   */
04058 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(TAMP_TypeDef *TAMPx)
04059 {
04060   CLEAR_BIT(TAMPx->IER, TAMP_IER_ITAMP5IE);
04061 }
04062
04063 /**
04064   * @brief  Enable internal tamper 6 interrupt.
04065   * @rmtoll TAMP_IER           ITAMP6IE          LL_RTC_EnableIT_ITAMP6
04066   * @param  TAMPx TAMP Instance
04067   * @retval None
04068   */
04069 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(TAMP_TypeDef *TAMPx)
04070 {
04071   SET_BIT(TAMPx->IER, TAMP_IER_ITAMP6IE);
04072 }
04073
04074 /**
04075   * @brief  Disable internal tamper 6 interrupt.
04076   * @rmtoll TAMP_IER           ITAMP6IE          LL_RTC_DisableIT_ITAMP6
04077   * @param  TAMPx TAMP Instance
04078   * @retval None
04079   */
04080 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(TAMP_TypeDef *TAMPx)
04081 {
04082   CLEAR_BIT(TAMPx->IER, TAMP_IER_ITAMP6IE);
04083 }
04084
04085
04086 /**
04087   * @brief  Check if tamper 1 interrupt is enabled or not.
04088   * @rmtoll TAMP_IER           TAMP1IE        LL_RTC_IsEnabledIT_TAMP1
04089   * @param  TAMPx TAMP Instance
04090   * @retval State of bit (1 or 0).
04091   */
04092 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx)
04093 {
04094   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL);
04095 }
04096
04097 /**
04098   * @brief  Check if tamper 2 interrupt is enabled or not.
04099   * @rmtoll TAMP_IER           TAMP2IE        LL_RTC_IsEnabledIT_TAMP2
04100   * @param  TAMPx TAMP Instance
04101   * @retval State of bit (1 or 0).
04102   */
04103 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx)
04104 {
04105   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL);
04106 }
04107
04108 #if defined (TAMP_CR1_TAMP3E)
04109 /**
04110   * @brief  Check if tamper 3 interrupt is enabled or not.
04111   * @rmtoll TAMP_IER           TAMP3IE        LL_RTC_IsEnabledIT_TAMP3
04112   * @param  TAMPx TAMP Instance
04113   * @retval State of bit (1 or 0).
04114   */
04115 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx)
04116 {
04117   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL);
04118 }
04119 #endif /* TAMP_CR1_TAMP3E */
04120
04121 /**
04122   * @brief  Check if internal tamper 3 interrupt is enabled or not.
04123   * @rmtoll TAMP_IER           ITAMP3IE        LL_RTC_IsEnabledIT_ITAMP3
04124   * @param  TAMPx TAMP Instance
04125   * @retval State of bit (1 or 0).
04126   */
04127 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(TAMP_TypeDef *TAMPx)
04128 {
04129   return ((READ_BIT(TAMPx->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1UL : 0UL);
04130 }
04131
04132 /**
04133   * @brief  Check if internal tamper 4 interrupt is enabled or not.
04134   * @rmtoll TAMP_IER           ITAMP4IE        LL_RTC_IsEnabledIT_ITAMP4
04135   * @param  TAMPx TAMP Instance
04136   * @retval State of bit (1 or 0).
04137   */
04138 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(TAMP_TypeDef *TAMPx)
04139 {
04140   return ((READ_BIT(TAMPx->IER, TAMP_IER_ITAMP4IE) == (TAMP_IER_ITAMP4IE)) ? 1UL : 0UL);
04141 }
04142
04143 /**
04144   * @brief  Check if internal tamper 5 interrupt is enabled or not.
04145   * @rmtoll TAMP_IER           ITAMP5IE        LL_RTC_IsEnabledIT_ITAMP5
04146   * @param  TAMPx TAMP Instance
04147   * @retval State of bit (1 or 0).
04148   */
04149 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(TAMP_TypeDef *TAMPx)
04150 {
04151   return ((READ_BIT(TAMPx->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1UL : 0UL);
04152 }
04153
04154 /**
04155   * @brief  Check if internal tamper 6 interrupt is enabled or not.
04156   * @rmtoll TAMP_IER           ITAMP6IE        LL_RTC_IsEnabledIT_ITAMP6
04157   * @param  TAMPx TAMP Instance
04158   * @retval State of bit (1 or 0).
04159   */
04160 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(TAMP_TypeDef *TAMPx)
04161 {
04162   return ((READ_BIT(TAMPx->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1UL : 0UL);
04163 }
04164
04165
04166 /**
04167   * @}
04168   */
04169
04170 #if defined(USE_FULL_LL_DRIVER)
04171 /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
04172   * @{
04173   */
04174
04175 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
04176 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
04177 void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
04178 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
04179 void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
04180 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
04181 void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
04182 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
04183 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
04184 void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
04185 void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
04186 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
04187 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
04188 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
04189
04190 /**
04191   * @}
04192   */
04193 #endif /* USE_FULL_LL_DRIVER */
04194
04195 /**
04196   * @}
04197   */
04198
04199 /**
04200   * @}
04201   */
04202
04203 #endif /* defined(RTC) */
04204
04205 /**
04206   * @}
04207   */
04208
04209 #ifdef __cplusplus
04210 }
04211 #endif
04212
04213 #endif /* STM32G0xx_LL_RTC_H */
04214
04215
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_spi.c Source File

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stm32g0xx_ll_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_spi.h"
00022 #include "stm32g0xx_ll_bus.h"
00023 #include "stm32g0xx_ll_rcc.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32G0xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
00036
00037 /** @addtogroup SPI_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
00046   * @{
00047   */
00048 /* SPI registers Masks */
00049 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
00050                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
00051                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
00052                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
00053                                             SPI_CR1_BIDIMODE)
00054 /**
00055   * @}
00056   */
00057
00058 /* Private macros ------------------------------------------------------------*/
00059 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
00060   * @{
00061   */
00062 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
00063                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
00064                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
00065                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
00066
00067 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
00068                                    || ((__VALUE__) == LL_SPI_MODE_SLAVE))
00069
00070 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
00071                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
00072                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
00073                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
00074                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
00075                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
00076                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
00077                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
00078                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
00079                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
00080                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
00081                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
00082                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
00083
00084 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
00085                                        || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
00086
00087 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
00088                                     || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
00089
00090 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
00091                                   || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
00092                                   || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
00093
00094 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
00095                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
00096                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
00097                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
00098                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
00099                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
00100                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
00101                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
00102
00103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
00104                                        || ((__VALUE__) == LL_SPI_MSB_FIRST))
00105
00106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
00107                                              || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
00108
00109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Private function prototypes -----------------------------------------------*/
00116
00117 /* Exported functions --------------------------------------------------------*/
00118 /** @addtogroup SPI_LL_Exported_Functions
00119   * @{
00120   */
00121
00122 /** @addtogroup SPI_LL_EF_Init
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  De-initialize the SPI registers to their default reset values.
00128   * @param  SPIx SPI Instance
00129   * @retval An ErrorStatus enumeration value:
00130   *          - SUCCESS: SPI registers are de-initialized
00131   *          - ERROR: SPI registers are not de-initialized
00132   */
00133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
00134 {
00135   ErrorStatus status = ERROR;
00136
00137   /* Check the parameters */
00138   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00139
00140 #if defined(SPI1)
00141   if (SPIx == SPI1)
00142   {
00143     /* Force reset of SPI clock */
00144     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
00145
00146     /* Release reset of SPI clock */
00147     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
00148
00149     status = SUCCESS;
00150   }
00151 #endif /* SPI1 */
00152 #if defined(SPI2)
00153   if (SPIx == SPI2)
00154   {
00155     /* Force reset of SPI clock */
00156     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
00157
00158     /* Release reset of SPI clock */
00159     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
00160
00161     status = SUCCESS;
00162   }
00163 #endif /* SPI2 */
00164 #if defined(SPI3)
00165   if (SPIx == SPI3)
00166   {
00167     /* Force reset of SPI clock */
00168     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
00169
00170     /* Release reset of SPI clock */
00171     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
00172
00173     status = SUCCESS;
00174   }
00175 #endif /* SPI3 */
00176
00177   return status;
00178 }
00179
00180 /**
00181   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
00182   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00183   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00184   * @param  SPIx SPI Instance
00185   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00186   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00187   */
00188 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
00189 {
00190   ErrorStatus status = ERROR;
00191
00192   /* Check the SPI Instance SPIx*/
00193   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00194
00195   /* Check the SPI parameters from SPI_InitStruct*/
00196   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
00197   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
00198   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
00199   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
00200   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
00201   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
00202   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
00203   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
00204   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
00205
00206   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
00207   {
00208     /*---------------------------- SPIx CR1 Configuration ------------------------
00209      * Configure SPIx CR1 with parameters:
00210      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
00211      * - Master/Slave Mode:  SPI_CR1_MSTR bit
00212      * - ClockPolarity:      SPI_CR1_CPOL bit
00213      * - ClockPhase:         SPI_CR1_CPHA bit
00214      * - NSS management:     SPI_CR1_SSM bit
00215      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
00216      * - BitOrder:           SPI_CR1_LSBFIRST bit
00217      * - CRCCalculation:     SPI_CR1_CRCEN bit
00218      */
00219     MODIFY_REG(SPIx->CR1,
00220                SPI_CR1_CLEAR_MASK,
00221                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
00222                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
00223                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
00224                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
00225
00226     /*---------------------------- SPIx CR2 Configuration ------------------------
00227      * Configure SPIx CR2 with parameters:
00228      * - DataWidth:          DS[3:0] bits
00229      * - NSS management:     SSOE bit
00230      */
00231     MODIFY_REG(SPIx->CR2,
00232                SPI_CR2_DS | SPI_CR2_SSOE,
00233                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
00234
00235     /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
00236     if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
00237     {
00238       LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
00239     }
00240
00241     /*---------------------------- SPIx CRCPR Configuration ----------------------
00242      * Configure SPIx CRCPR with parameters:
00243      * - CRCPoly:            CRCPOLY[15:0] bits
00244      */
00245     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
00246     {
00247       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
00248       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
00249     }
00250     status = SUCCESS;
00251   }
00252
00253 #if defined (SPI_I2S_SUPPORT)
00254   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
00255   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00256 #endif /* SPI_I2S_SUPPORT */
00257   return status;
00258 }
00259
00260 /**
00261   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
00262   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00263   * whose fields will be set to default values.
00264   * @retval None
00265   */
00266 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
00267 {
00268   /* Set SPI_InitStruct fields to default values */
00269   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
00270   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
00271   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
00272   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
00273   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
00274   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
00275   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
00276   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
00277   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
00278   SPI_InitStruct->CRCPoly           = 7U;
00279 }
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 #if defined(SPI_I2S_SUPPORT)
00294 /** @addtogroup I2S_LL
00295   * @{
00296   */
00297
00298 /* Private types -------------------------------------------------------------*/
00299 /* Private variables ---------------------------------------------------------*/
00300 /* Private constants ---------------------------------------------------------*/
00301 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
00302   * @{
00303   */
00304 /* I2S registers Masks */
00305 #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
00306                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
00307                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
00308
00309 #define I2S_I2SPR_CLEAR_MASK               0x0002U
00310 /**
00311   * @}
00312   */
00313 /* Private macros ------------------------------------------------------------*/
00314 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
00315   * @{
00316   */
00317
00318 #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
00319                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
00320                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
00321                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
00322
00323 #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
00324                                           || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
00325
00326 #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
00327                                           || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
00328                                           || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
00329                                           || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
00330                                           || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
00331
00332 #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
00333                                           || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
00334                                           || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
00335                                           || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
00336
00337 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
00338                                           || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
00339
00340 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
00341                                           && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
00342                                          || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
00343
00344 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
00345
00346 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
00347                                                || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
00348 /**
00349   * @}
00350   */
00351
00352 /* Private function prototypes -----------------------------------------------*/
00353
00354 /* Exported functions --------------------------------------------------------*/
00355 /** @addtogroup I2S_LL_Exported_Functions
00356   * @{
00357   */
00358
00359 /** @addtogroup I2S_LL_EF_Init
00360   * @{
00361   */
00362
00363 /**
00364   * @brief  De-initialize the SPI/I2S registers to their default reset values.
00365   * @param  SPIx SPI Instance
00366   * @retval An ErrorStatus enumeration value:
00367   *          - SUCCESS: SPI registers are de-initialized
00368   *          - ERROR: SPI registers are not de-initialized
00369   */
00370 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
00371 {
00372   return LL_SPI_DeInit(SPIx);
00373 }
00374
00375 /**
00376   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
00377   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00378   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00379   * @param  SPIx SPI Instance
00380   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00381   * @retval An ErrorStatus enumeration value:
00382   *          - SUCCESS: SPI registers are Initialized
00383   *          - ERROR: SPI registers are not Initialized
00384   */
00385 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
00386 {
00387   uint32_t i2sdiv = 2U;
00388   uint32_t i2sodd = 0U;
00389   uint32_t packetlength = 1U;
00390   uint32_t tmp;
00391   LL_RCC_ClocksTypeDef rcc_clocks;
00392   uint32_t sourceclock;
00393   ErrorStatus status = ERROR;
00394
00395   /* Check the I2S parameters */
00396   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00397   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
00398   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
00399   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
00400   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
00401   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
00402   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
00403
00404   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
00405   {
00406     /*---------------------------- SPIx I2SCFGR Configuration --------------------
00407      * Configure SPIx I2SCFGR with parameters:
00408      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
00409      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
00410      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
00411      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
00412      */
00413
00414     /* Write to SPIx I2SCFGR */
00415     MODIFY_REG(SPIx->I2SCFGR,
00416                I2S_I2SCFGR_CLEAR_MASK,
00417                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
00418                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
00419                SPI_I2SCFGR_I2SMOD);
00420
00421     /*---------------------------- SPIx I2SPR Configuration ----------------------
00422      * Configure SPIx I2SPR with parameters:
00423      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
00424      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
00425      */
00426
00427     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
00428      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
00429      */
00430     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
00431     {
00432       /* Check the frame length (For the Prescaler computing)
00433        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
00434        */
00435       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
00436       {
00437         /* Packet length is 32 bits */
00438         packetlength = 2U;
00439       }
00440
00441       /* I2S Clock source is System clock: Get System Clock frequency */
00442       LL_RCC_GetSystemClocksFreq(&rcc_clocks);
00443
00444       /* Get the source clock value: based on System Clock value */
00445       sourceclock = rcc_clocks.SYSCLK_Frequency;
00446
00447       /* Compute the Real divider depending on the MCLK output state with a floating point */
00448       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
00449       {
00450         /* MCLK output is enabled */
00451         tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
00452       }
00453       else
00454       {
00455         /* MCLK output is disabled */
00456         tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
00457       }
00458
00459       /* Remove the floating point */
00460       tmp = tmp / 10U;
00461
00462       /* Check the parity of the divider */
00463       i2sodd = (tmp & (uint16_t)0x0001U);
00464
00465       /* Compute the i2sdiv prescaler */
00466       i2sdiv = ((tmp - i2sodd) / 2U);
00467
00468       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00469       i2sodd = (i2sodd << 8U);
00470     }
00471
00472     /* Test if the divider is 1 or 0 or greater than 0xFF */
00473     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00474     {
00475       /* Set the default values */
00476       i2sdiv = 2U;
00477       i2sodd = 0U;
00478     }
00479
00480     /* Write to SPIx I2SPR register the computed value */
00481     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
00482
00483     status = SUCCESS;
00484   }
00485   return status;
00486 }
00487
00488 /**
00489   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
00490   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00491   *         whose fields will be set to default values.
00492   * @retval None
00493   */
00494 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
00495 {
00496   /*--------------- Reset I2S init structure parameters values -----------------*/
00497   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
00498   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
00499   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
00500   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
00501   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
00502   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
00503 }
00504
00505 /**
00506   * @brief  Set linear and parity prescaler.
00507   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
00508   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
00509   * @param  SPIx SPI Instance
00510   * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
00511   * @param  PrescalerParity This parameter can be one of the following values:
00512   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
00513   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
00514   * @retval None
00515   */
00516 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
00517 {
00518   /* Check the I2S parameters */
00519   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00520   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
00521   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
00522
00523   /* Write to SPIx I2SPR */
00524   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
00525 }
00526
00527 /**
00528   * @}
00529   */
00530
00531 /**
00532   * @}
00533   */
00534
00535 /**
00536   * @}
00537   */
00538 #endif /* SPI_I2S_SUPPORT */
00539
00540 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
00541
00542 /**
00543   * @}
00544   */
00545
00546 #endif /* USE_FULL_LL_DRIVER */
00547
Generated on Mon Jun 6 2022 10:29:03 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_spi.h Source File

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stm32g0xx_ll_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_SPI_H
00021 #define STM32G0xx_LL_SPI_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
00035
00036 /** @defgroup SPI_LL SPI
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043
00044 /* Exported types ------------------------------------------------------------*/
00045 #if defined(USE_FULL_LL_DRIVER)
00046 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  SPI Init structures definition
00052   */
00053 typedef struct
00054 {
00055   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
00056                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
00057
00058                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
00059
00060   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
00061                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
00062
00063                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
00064
00065   uint32_t DataWidth;               /*!< Specifies the SPI data width.
00066                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
00067
00068                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
00069
00070   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
00071                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
00072
00073                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
00074
00075   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
00076                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
00077
00078                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
00079
00080   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
00081                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
00082
00083                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
00084
00085   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
00086                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
00087                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
00088
00089                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
00090
00091   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
00092                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
00093
00094                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
00095
00096   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
00097                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
00098
00099                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
00100
00101   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
00102                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
00103
00104                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
00105
00106 } LL_SPI_InitTypeDef;
00107
00108 /**
00109   * @}
00110   */
00111 #endif /* USE_FULL_LL_DRIVER */
00112
00113 /* Exported constants --------------------------------------------------------*/
00114 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
00115   * @{
00116   */
00117
00118 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
00119   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
00120   * @{
00121   */
00122 #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
00123 #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
00124 #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
00125 #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
00126 #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
00127 #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
00128 #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
00129 /**
00130   * @}
00131   */
00132
00133 /** @defgroup SPI_LL_EC_IT IT Defines
00134   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
00135   * @{
00136   */
00137 #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
00138 #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
00139 #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup SPI_LL_EC_MODE Operation Mode
00145   * @{
00146   */
00147 #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
00148 #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
00154   * @{
00155   */
00156 #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
00157 #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup SPI_LL_EC_PHASE Clock Phase
00163   * @{
00164   */
00165 #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
00166 #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
00172   * @{
00173   */
00174 #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
00175 #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
00181   * @{
00182   */
00183 #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
00184 #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
00185 #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
00186 #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
00187 #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
00188 #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
00189 #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
00190 #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
00196   * @{
00197   */
00198 #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
00199 #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
00205   * @{
00206   */
00207 #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
00208 #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
00209 #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
00210 #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
00216   * @{
00217   */
00218 #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
00219 #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
00220 #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
00226   * @{
00227   */
00228 #define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
00229 #define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
00230 #define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
00231 #define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
00232 #define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
00233 #define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
00234 #define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
00235 #define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
00236 #define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
00237 #define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
00238 #define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
00239 #define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
00240 #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
00241 /**
00242   * @}
00243   */
00244 #if defined(USE_FULL_LL_DRIVER)
00245
00246 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
00247   * @{
00248   */
00249 #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
00250 #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
00251 /**
00252   * @}
00253   */
00254 #endif /* USE_FULL_LL_DRIVER */
00255
00256 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
00257   * @{
00258   */
00259 #define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
00260 #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
00266   * @{
00267   */
00268 #define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
00269 #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)  */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
00275   * @{
00276   */
00277 #define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
00278 #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
00279 #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
00280 #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
00286   * @{
00287   */
00288 #define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
00289 #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
00290 #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
00291 #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
00297   * @{
00298   */
00299 #define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
00300 #define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 /* Exported macro ------------------------------------------------------------*/
00311 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
00312   * @{
00313   */
00314
00315 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
00316   * @{
00317   */
00318
00319 /**
00320   * @brief  Write a value in SPI register
00321   * @param  __INSTANCE__ SPI Instance
00322   * @param  __REG__ Register to be written
00323   * @param  __VALUE__ Value to be written in the register
00324   * @retval None
00325   */
00326 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00327
00328 /**
00329   * @brief  Read a value in SPI register
00330   * @param  __INSTANCE__ SPI Instance
00331   * @param  __REG__ Register to be read
00332   * @retval Register value
00333   */
00334 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00335 /**
00336   * @}
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 /* Exported functions --------------------------------------------------------*/
00344 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
00345   * @{
00346   */
00347
00348 /** @defgroup SPI_LL_EF_Configuration Configuration
00349   * @{
00350   */
00351
00352 /**
00353   * @brief  Enable SPI peripheral
00354   * @rmtoll CR1          SPE           LL_SPI_Enable
00355   * @param  SPIx SPI Instance
00356   * @retval None
00357   */
00358 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
00359 {
00360   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
00361 }
00362
00363 /**
00364   * @brief  Disable SPI peripheral
00365   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
00366   * @rmtoll CR1          SPE           LL_SPI_Disable
00367   * @param  SPIx SPI Instance
00368   * @retval None
00369   */
00370 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
00371 {
00372   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
00373 }
00374
00375 /**
00376   * @brief  Check if SPI peripheral is enabled
00377   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
00378   * @param  SPIx SPI Instance
00379   * @retval State of bit (1 or 0).
00380   */
00381 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
00382 {
00383   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
00384 }
00385
00386 /**
00387   * @brief  Set SPI operation mode to Master or Slave
00388   * @note   This bit should not be changed when communication is ongoing.
00389   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
00390   *         CR1          SSI           LL_SPI_SetMode
00391   * @param  SPIx SPI Instance
00392   * @param  Mode This parameter can be one of the following values:
00393   *         @arg @ref LL_SPI_MODE_MASTER
00394   *         @arg @ref LL_SPI_MODE_SLAVE
00395   * @retval None
00396   */
00397 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
00398 {
00399   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
00400 }
00401
00402 /**
00403   * @brief  Get SPI operation mode (Master or Slave)
00404   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
00405   *         CR1          SSI           LL_SPI_GetMode
00406   * @param  SPIx SPI Instance
00407   * @retval Returned value can be one of the following values:
00408   *         @arg @ref LL_SPI_MODE_MASTER
00409   *         @arg @ref LL_SPI_MODE_SLAVE
00410   */
00411 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
00412 {
00413   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
00414 }
00415
00416 /**
00417   * @brief  Set serial protocol used
00418   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00419   * @rmtoll CR2          FRF           LL_SPI_SetStandard
00420   * @param  SPIx SPI Instance
00421   * @param  Standard This parameter can be one of the following values:
00422   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00423   *         @arg @ref LL_SPI_PROTOCOL_TI
00424   * @retval None
00425   */
00426 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
00427 {
00428   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
00429 }
00430
00431 /**
00432   * @brief  Get serial protocol used
00433   * @rmtoll CR2          FRF           LL_SPI_GetStandard
00434   * @param  SPIx SPI Instance
00435   * @retval Returned value can be one of the following values:
00436   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00437   *         @arg @ref LL_SPI_PROTOCOL_TI
00438   */
00439 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
00440 {
00441   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
00442 }
00443
00444 /**
00445   * @brief  Set clock phase
00446   * @note   This bit should not be changed when communication is ongoing.
00447   *         This bit is not used in SPI TI mode.
00448   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
00449   * @param  SPIx SPI Instance
00450   * @param  ClockPhase This parameter can be one of the following values:
00451   *         @arg @ref LL_SPI_PHASE_1EDGE
00452   *         @arg @ref LL_SPI_PHASE_2EDGE
00453   * @retval None
00454   */
00455 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
00456 {
00457   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
00458 }
00459
00460 /**
00461   * @brief  Get clock phase
00462   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
00463   * @param  SPIx SPI Instance
00464   * @retval Returned value can be one of the following values:
00465   *         @arg @ref LL_SPI_PHASE_1EDGE
00466   *         @arg @ref LL_SPI_PHASE_2EDGE
00467   */
00468 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
00469 {
00470   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
00471 }
00472
00473 /**
00474   * @brief  Set clock polarity
00475   * @note   This bit should not be changed when communication is ongoing.
00476   *         This bit is not used in SPI TI mode.
00477   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
00478   * @param  SPIx SPI Instance
00479   * @param  ClockPolarity This parameter can be one of the following values:
00480   *         @arg @ref LL_SPI_POLARITY_LOW
00481   *         @arg @ref LL_SPI_POLARITY_HIGH
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
00485 {
00486   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
00487 }
00488
00489 /**
00490   * @brief  Get clock polarity
00491   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
00492   * @param  SPIx SPI Instance
00493   * @retval Returned value can be one of the following values:
00494   *         @arg @ref LL_SPI_POLARITY_LOW
00495   *         @arg @ref LL_SPI_POLARITY_HIGH
00496   */
00497 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
00498 {
00499   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
00500 }
00501
00502 /**
00503   * @brief  Set baud rate prescaler
00504   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
00505   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
00506   * @param  SPIx SPI Instance
00507   * @param  BaudRate This parameter can be one of the following values:
00508   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00509   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00510   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00511   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00512   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00513   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00514   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00515   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00516   * @retval None
00517   */
00518 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
00519 {
00520   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
00521 }
00522
00523 /**
00524   * @brief  Get baud rate prescaler
00525   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
00526   * @param  SPIx SPI Instance
00527   * @retval Returned value can be one of the following values:
00528   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00529   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00530   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00531   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00532   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00533   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00534   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00535   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00536   */
00537 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
00538 {
00539   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
00540 }
00541
00542 /**
00543   * @brief  Set transfer bit order
00544   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00545   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
00546   * @param  SPIx SPI Instance
00547   * @param  BitOrder This parameter can be one of the following values:
00548   *         @arg @ref LL_SPI_LSB_FIRST
00549   *         @arg @ref LL_SPI_MSB_FIRST
00550   * @retval None
00551   */
00552 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
00553 {
00554   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
00555 }
00556
00557 /**
00558   * @brief  Get transfer bit order
00559   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
00560   * @param  SPIx SPI Instance
00561   * @retval Returned value can be one of the following values:
00562   *         @arg @ref LL_SPI_LSB_FIRST
00563   *         @arg @ref LL_SPI_MSB_FIRST
00564   */
00565 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
00566 {
00567   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
00568 }
00569
00570 /**
00571   * @brief  Set transfer direction mode
00572   * @note   For Half-Duplex mode, Rx Direction is set by default.
00573   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
00574   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
00575   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
00576   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
00577   * @param  SPIx SPI Instance
00578   * @param  TransferDirection This parameter can be one of the following values:
00579   *         @arg @ref LL_SPI_FULL_DUPLEX
00580   *         @arg @ref LL_SPI_SIMPLEX_RX
00581   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00582   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00583   * @retval None
00584   */
00585 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
00586 {
00587   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
00588 }
00589
00590 /**
00591   * @brief  Get transfer direction mode
00592   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
00593   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
00594   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
00595   * @param  SPIx SPI Instance
00596   * @retval Returned value can be one of the following values:
00597   *         @arg @ref LL_SPI_FULL_DUPLEX
00598   *         @arg @ref LL_SPI_SIMPLEX_RX
00599   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00600   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00601   */
00602 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
00603 {
00604   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
00605 }
00606
00607 /**
00608   * @brief  Set frame data width
00609   * @rmtoll CR2          DS            LL_SPI_SetDataWidth
00610   * @param  SPIx SPI Instance
00611   * @param  DataWidth This parameter can be one of the following values:
00612   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00613   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00614   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00615   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00616   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00617   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00618   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00619   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00620   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00621   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00622   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00623   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00624   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00625   * @retval None
00626   */
00627 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
00628 {
00629   MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
00630 }
00631
00632 /**
00633   * @brief  Get frame data width
00634   * @rmtoll CR2          DS            LL_SPI_GetDataWidth
00635   * @param  SPIx SPI Instance
00636   * @retval Returned value can be one of the following values:
00637   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00638   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00639   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00640   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00641   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00642   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00643   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00644   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00645   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00646   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00647   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00648   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00649   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00650   */
00651 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
00652 {
00653   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
00654 }
00655
00656 /**
00657   * @brief  Set threshold of RXFIFO that triggers an RXNE event
00658   * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
00659   * @param  SPIx SPI Instance
00660   * @param  Threshold This parameter can be one of the following values:
00661   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00662   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
00666 {
00667   MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
00668 }
00669
00670 /**
00671   * @brief  Get threshold of RXFIFO that triggers an RXNE event
00672   * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
00673   * @param  SPIx SPI Instance
00674   * @retval Returned value can be one of the following values:
00675   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00676   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00677   */
00678 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
00679 {
00680   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
00681 }
00682
00683 /**
00684   * @}
00685   */
00686
00687 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
00688   * @{
00689   */
00690
00691 /**
00692   * @brief  Enable CRC
00693   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00694   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
00695   * @param  SPIx SPI Instance
00696   * @retval None
00697   */
00698 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
00699 {
00700   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00701 }
00702
00703 /**
00704   * @brief  Disable CRC
00705   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00706   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
00707   * @param  SPIx SPI Instance
00708   * @retval None
00709   */
00710 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
00711 {
00712   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00713 }
00714
00715 /**
00716   * @brief  Check if CRC is enabled
00717   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00718   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
00719   * @param  SPIx SPI Instance
00720   * @retval State of bit (1 or 0).
00721   */
00722 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
00723 {
00724   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
00725 }
00726
00727 /**
00728   * @brief  Set CRC Length
00729   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00730   * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
00731   * @param  SPIx SPI Instance
00732   * @param  CRCLength This parameter can be one of the following values:
00733   *         @arg @ref LL_SPI_CRC_8BIT
00734   *         @arg @ref LL_SPI_CRC_16BIT
00735   * @retval None
00736   */
00737 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
00738 {
00739   MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
00740 }
00741
00742 /**
00743   * @brief  Get CRC Length
00744   * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
00745   * @param  SPIx SPI Instance
00746   * @retval Returned value can be one of the following values:
00747   *         @arg @ref LL_SPI_CRC_8BIT
00748   *         @arg @ref LL_SPI_CRC_16BIT
00749   */
00750 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
00751 {
00752   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
00753 }
00754
00755 /**
00756   * @brief  Set CRCNext to transfer CRC on the line
00757   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
00758   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
00759   * @param  SPIx SPI Instance
00760   * @retval None
00761   */
00762 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
00763 {
00764   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
00765 }
00766
00767 /**
00768   * @brief  Set polynomial for CRC calculation
00769   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
00770   * @param  SPIx SPI Instance
00771   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00772   * @retval None
00773   */
00774 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
00775 {
00776   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
00777 }
00778
00779 /**
00780   * @brief  Get polynomial for CRC calculation
00781   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
00782   * @param  SPIx SPI Instance
00783   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00784   */
00785 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
00786 {
00787   return (uint32_t)(READ_REG(SPIx->CRCPR));
00788 }
00789
00790 /**
00791   * @brief  Get Rx CRC
00792   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
00793   * @param  SPIx SPI Instance
00794   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00795   */
00796 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
00797 {
00798   return (uint32_t)(READ_REG(SPIx->RXCRCR));
00799 }
00800
00801 /**
00802   * @brief  Get Tx CRC
00803   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
00804   * @param  SPIx SPI Instance
00805   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00806   */
00807 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
00808 {
00809   return (uint32_t)(READ_REG(SPIx->TXCRCR));
00810 }
00811
00812 /**
00813   * @}
00814   */
00815
00816 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
00817   * @{
00818   */
00819
00820 /**
00821   * @brief  Set NSS mode
00822   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
00823   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
00824   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
00825   * @param  SPIx SPI Instance
00826   * @param  NSS This parameter can be one of the following values:
00827   *         @arg @ref LL_SPI_NSS_SOFT
00828   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00829   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00830   * @retval None
00831   */
00832 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
00833 {
00834   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
00835   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
00836 }
00837
00838 /**
00839   * @brief  Get NSS mode
00840   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
00841   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
00842   * @param  SPIx SPI Instance
00843   * @retval Returned value can be one of the following values:
00844   *         @arg @ref LL_SPI_NSS_SOFT
00845   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00846   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00847   */
00848 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
00849 {
00850   uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
00851   uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
00852   return (Ssm | Ssoe);
00853 }
00854
00855 /**
00856   * @brief  Enable NSS pulse management
00857   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00858   * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
00859   * @param  SPIx SPI Instance
00860   * @retval None
00861   */
00862 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
00863 {
00864   SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
00865 }
00866
00867 /**
00868   * @brief  Disable NSS pulse management
00869   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00870   * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
00871   * @param  SPIx SPI Instance
00872   * @retval None
00873   */
00874 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
00875 {
00876   CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
00877 }
00878
00879 /**
00880   * @brief  Check if NSS pulse is enabled
00881   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00882   * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
00883   * @param  SPIx SPI Instance
00884   * @retval State of bit (1 or 0).
00885   */
00886 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
00887 {
00888   return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
00889 }
00890
00891 /**
00892   * @}
00893   */
00894
00895 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
00896   * @{
00897   */
00898
00899 /**
00900   * @brief  Check if Rx buffer is not empty
00901   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
00902   * @param  SPIx SPI Instance
00903   * @retval State of bit (1 or 0).
00904   */
00905 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
00906 {
00907   return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
00908 }
00909
00910 /**
00911   * @brief  Check if Tx buffer is empty
00912   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
00913   * @param  SPIx SPI Instance
00914   * @retval State of bit (1 or 0).
00915   */
00916 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
00917 {
00918   return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
00919 }
00920
00921 /**
00922   * @brief  Get CRC error flag
00923   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
00924   * @param  SPIx SPI Instance
00925   * @retval State of bit (1 or 0).
00926   */
00927 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
00928 {
00929   return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
00930 }
00931
00932 /**
00933   * @brief  Get mode fault error flag
00934   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
00935   * @param  SPIx SPI Instance
00936   * @retval State of bit (1 or 0).
00937   */
00938 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
00939 {
00940   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
00941 }
00942
00943 /**
00944   * @brief  Get overrun error flag
00945   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
00946   * @param  SPIx SPI Instance
00947   * @retval State of bit (1 or 0).
00948   */
00949 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
00950 {
00951   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
00952 }
00953
00954 /**
00955   * @brief  Get busy flag
00956   * @note   The BSY flag is cleared under any one of the following conditions:
00957   * -When the SPI is correctly disabled
00958   * -When a fault is detected in Master mode (MODF bit set to 1)
00959   * -In Master mode, when it finishes a data transmission and no new data is ready to be
00960   * sent
00961   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
00962   * each data transfer.
00963   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
00964   * @param  SPIx SPI Instance
00965   * @retval State of bit (1 or 0).
00966   */
00967 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
00968 {
00969   return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
00970 }
00971
00972 /**
00973   * @brief  Get frame format error flag
00974   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
00975   * @param  SPIx SPI Instance
00976   * @retval State of bit (1 or 0).
00977   */
00978 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
00979 {
00980   return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
00981 }
00982
00983 /**
00984   * @brief  Get FIFO reception Level
00985   * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
00986   * @param  SPIx SPI Instance
00987   * @retval Returned value can be one of the following values:
00988   *         @arg @ref LL_SPI_RX_FIFO_EMPTY
00989   *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
00990   *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
00991   *         @arg @ref LL_SPI_RX_FIFO_FULL
00992   */
00993 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
00994 {
00995   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
00996 }
00997
00998 /**
00999   * @brief  Get FIFO Transmission Level
01000   * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
01001   * @param  SPIx SPI Instance
01002   * @retval Returned value can be one of the following values:
01003   *         @arg @ref LL_SPI_TX_FIFO_EMPTY
01004   *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
01005   *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
01006   *         @arg @ref LL_SPI_TX_FIFO_FULL
01007   */
01008 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
01009 {
01010   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
01011 }
01012
01013 /**
01014   * @brief  Clear CRC error flag
01015   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
01016   * @param  SPIx SPI Instance
01017   * @retval None
01018   */
01019 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
01020 {
01021   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
01022 }
01023
01024 /**
01025   * @brief  Clear mode fault error flag
01026   * @note   Clearing this flag is done by a read access to the SPIx_SR
01027   *         register followed by a write access to the SPIx_CR1 register
01028   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
01029   * @param  SPIx SPI Instance
01030   * @retval None
01031   */
01032 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
01033 {
01034   __IO uint32_t tmpreg_sr;
01035   tmpreg_sr = SPIx->SR;
01036   (void) tmpreg_sr;
01037   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
01038 }
01039
01040 /**
01041   * @brief  Clear overrun error flag
01042   * @note   Clearing this flag is done by a read access to the SPIx_DR
01043   *         register followed by a read access to the SPIx_SR register
01044   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
01045   * @param  SPIx SPI Instance
01046   * @retval None
01047   */
01048 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
01049 {
01050   __IO uint32_t tmpreg;
01051   tmpreg = SPIx->DR;
01052   (void) tmpreg;
01053   tmpreg = SPIx->SR;
01054   (void) tmpreg;
01055 }
01056
01057 /**
01058   * @brief  Clear frame format error flag
01059   * @note   Clearing this flag is done by reading SPIx_SR register
01060   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
01061   * @param  SPIx SPI Instance
01062   * @retval None
01063   */
01064 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
01065 {
01066   __IO uint32_t tmpreg;
01067   tmpreg = SPIx->SR;
01068   (void) tmpreg;
01069 }
01070
01071 /**
01072   * @}
01073   */
01074
01075 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
01076   * @{
01077   */
01078
01079 /**
01080   * @brief  Enable error interrupt
01081   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01082   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
01083   * @param  SPIx SPI Instance
01084   * @retval None
01085   */
01086 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
01087 {
01088   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01089 }
01090
01091 /**
01092   * @brief  Enable Rx buffer not empty interrupt
01093   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
01094   * @param  SPIx SPI Instance
01095   * @retval None
01096   */
01097 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
01098 {
01099   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01100 }
01101
01102 /**
01103   * @brief  Enable Tx buffer empty interrupt
01104   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
01105   * @param  SPIx SPI Instance
01106   * @retval None
01107   */
01108 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
01109 {
01110   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01111 }
01112
01113 /**
01114   * @brief  Disable error interrupt
01115   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01116   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
01117   * @param  SPIx SPI Instance
01118   * @retval None
01119   */
01120 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
01121 {
01122   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01123 }
01124
01125 /**
01126   * @brief  Disable Rx buffer not empty interrupt
01127   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
01128   * @param  SPIx SPI Instance
01129   * @retval None
01130   */
01131 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
01132 {
01133   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01134 }
01135
01136 /**
01137   * @brief  Disable Tx buffer empty interrupt
01138   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
01139   * @param  SPIx SPI Instance
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
01143 {
01144   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01145 }
01146
01147 /**
01148   * @brief  Check if error interrupt is enabled
01149   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
01150   * @param  SPIx SPI Instance
01151   * @retval State of bit (1 or 0).
01152   */
01153 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
01154 {
01155   return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
01156 }
01157
01158 /**
01159   * @brief  Check if Rx buffer not empty interrupt is enabled
01160   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
01161   * @param  SPIx SPI Instance
01162   * @retval State of bit (1 or 0).
01163   */
01164 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
01165 {
01166   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
01167 }
01168
01169 /**
01170   * @brief  Check if Tx buffer empty interrupt
01171   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
01172   * @param  SPIx SPI Instance
01173   * @retval State of bit (1 or 0).
01174   */
01175 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
01176 {
01177   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
01178 }
01179
01180 /**
01181   * @}
01182   */
01183
01184 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
01185   * @{
01186   */
01187
01188 /**
01189   * @brief  Enable DMA Rx
01190   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
01191   * @param  SPIx SPI Instance
01192   * @retval None
01193   */
01194 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
01195 {
01196   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01197 }
01198
01199 /**
01200   * @brief  Disable DMA Rx
01201   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
01202   * @param  SPIx SPI Instance
01203   * @retval None
01204   */
01205 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
01206 {
01207   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01208 }
01209
01210 /**
01211   * @brief  Check if DMA Rx is enabled
01212   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
01213   * @param  SPIx SPI Instance
01214   * @retval State of bit (1 or 0).
01215   */
01216 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
01217 {
01218   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
01219 }
01220
01221 /**
01222   * @brief  Enable DMA Tx
01223   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
01224   * @param  SPIx SPI Instance
01225   * @retval None
01226   */
01227 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
01228 {
01229   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01230 }
01231
01232 /**
01233   * @brief  Disable DMA Tx
01234   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
01235   * @param  SPIx SPI Instance
01236   * @retval None
01237   */
01238 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
01239 {
01240   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01241 }
01242
01243 /**
01244   * @brief  Check if DMA Tx is enabled
01245   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
01246   * @param  SPIx SPI Instance
01247   * @retval State of bit (1 or 0).
01248   */
01249 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
01250 {
01251   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
01252 }
01253
01254 /**
01255   * @brief  Set parity of  Last DMA reception
01256   * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
01257   * @param  SPIx SPI Instance
01258   * @param  Parity This parameter can be one of the following values:
01259   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01260   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01261   * @retval None
01262   */
01263 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
01264 {
01265   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
01266 }
01267
01268 /**
01269   * @brief  Get parity configuration for  Last DMA reception
01270   * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
01271   * @param  SPIx SPI Instance
01272   * @retval Returned value can be one of the following values:
01273   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01274   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01275   */
01276 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
01277 {
01278   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
01279 }
01280
01281 /**
01282   * @brief  Set parity of  Last DMA transmission
01283   * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
01284   * @param  SPIx SPI Instance
01285   * @param  Parity This parameter can be one of the following values:
01286   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01287   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01288   * @retval None
01289   */
01290 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
01291 {
01292   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
01293 }
01294
01295 /**
01296   * @brief  Get parity configuration for Last DMA transmission
01297   * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
01298   * @param  SPIx SPI Instance
01299   * @retval Returned value can be one of the following values:
01300   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01301   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01302   */
01303 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
01304 {
01305   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
01306 }
01307
01308 /**
01309   * @brief  Get the data register address used for DMA transfer
01310   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
01311   * @param  SPIx SPI Instance
01312   * @retval Address of data register
01313   */
01314 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
01315 {
01316   return (uint32_t) &(SPIx->DR);
01317 }
01318
01319 /**
01320   * @}
01321   */
01322
01323 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
01324   * @{
01325   */
01326
01327 /**
01328   * @brief  Read 8-Bits in the data register
01329   * @rmtoll DR           DR            LL_SPI_ReceiveData8
01330   * @param  SPIx SPI Instance
01331   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
01332   */
01333 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
01334 {
01335   return (*((__IO uint8_t *)&SPIx->DR));
01336 }
01337
01338 /**
01339   * @brief  Read 16-Bits in the data register
01340   * @rmtoll DR           DR            LL_SPI_ReceiveData16
01341   * @param  SPIx SPI Instance
01342   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01343   */
01344 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
01345 {
01346   return (uint16_t)(READ_REG(SPIx->DR));
01347 }
01348
01349 /**
01350   * @brief  Write 8-Bits in the data register
01351   * @rmtoll DR           DR            LL_SPI_TransmitData8
01352   * @param  SPIx SPI Instance
01353   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
01354   * @retval None
01355   */
01356 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
01357 {
01358 #if defined (__GNUC__)
01359   __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
01360   *spidr = TxData;
01361 #else
01362   *((__IO uint8_t *)&SPIx->DR) = TxData;
01363 #endif /* __GNUC__ */
01364 }
01365
01366 /**
01367   * @brief  Write 16-Bits in the data register
01368   * @rmtoll DR           DR            LL_SPI_TransmitData16
01369   * @param  SPIx SPI Instance
01370   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01371   * @retval None
01372   */
01373 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
01374 {
01375 #if defined (__GNUC__)
01376   __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
01377   *spidr = TxData;
01378 #else
01379   SPIx->DR = TxData;
01380 #endif /* __GNUC__ */
01381 }
01382
01383 /**
01384   * @}
01385   */
01386 #if defined(USE_FULL_LL_DRIVER)
01387 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
01388   * @{
01389   */
01390
01391 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
01392 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
01393 void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
01394
01395 /**
01396   * @}
01397   */
01398 #endif /* USE_FULL_LL_DRIVER */
01399 /**
01400   * @}
01401   */
01402
01403 /**
01404   * @}
01405   */
01406
01407 #if defined(SPI_I2S_SUPPORT)
01408 /** @defgroup I2S_LL I2S
01409   * @{
01410   */
01411
01412 /* Private variables ---------------------------------------------------------*/
01413 /* Private constants ---------------------------------------------------------*/
01414 /* Private macros ------------------------------------------------------------*/
01415
01416 /* Exported types ------------------------------------------------------------*/
01417 #if defined(USE_FULL_LL_DRIVER)
01418 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
01419   * @{
01420   */
01421
01422 /**
01423   * @brief  I2S Init structure definition
01424   */
01425
01426 typedef struct
01427 {
01428   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
01429                                          This parameter can be a value of @ref I2S_LL_EC_MODE
01430
01431                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
01432
01433   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
01434                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
01435
01436                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
01437
01438
01439   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
01440                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
01441
01442                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
01443
01444
01445   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
01446                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
01447
01448                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
01449
01450
01451   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
01452                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
01453
01454                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
01455                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
01456
01457
01458   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
01459                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
01460
01461                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
01462
01463 } LL_I2S_InitTypeDef;
01464
01465 /**
01466   * @}
01467   */
01468 #endif /*USE_FULL_LL_DRIVER*/
01469
01470 /* Exported constants --------------------------------------------------------*/
01471 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
01472   * @{
01473   */
01474
01475 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
01476   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
01477   * @{
01478   */
01479 #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
01480 #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
01481 #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
01482 #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
01483 #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
01484 #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
01485 /**
01486   * @}
01487   */
01488
01489 /** @defgroup SPI_LL_EC_IT IT Defines
01490   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
01491   * @{
01492   */
01493 #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
01494 #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
01495 #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
01496 /**
01497   * @}
01498   */
01499
01500 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
01501   * @{
01502   */
01503 #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
01504 #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
01505 #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
01506 #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
01507 /**
01508   * @}
01509   */
01510
01511 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
01512   * @{
01513   */
01514 #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
01515 #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
01516 /**
01517   * @}
01518   */
01519
01520 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
01521   * @{
01522   */
01523 #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
01524 #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
01525 #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
01526 #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
01527 #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
01528 /**
01529   * @}
01530   */
01531
01532 /** @defgroup I2S_LL_EC_MODE Operation Mode
01533   * @{
01534   */
01535 #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
01536 #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
01537 #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
01538 #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
01539 /**
01540   * @}
01541   */
01542
01543 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
01544   * @{
01545   */
01546 #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
01547 #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
01548 /**
01549   * @}
01550   */
01551
01552 #if defined(USE_FULL_LL_DRIVER)
01553
01554 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
01555   * @{
01556   */
01557 #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
01558 #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
01559 /**
01560   * @}
01561   */
01562
01563 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
01564   * @{
01565   */
01566
01567 #define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
01568 #define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
01569 #define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
01570 #define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
01571 #define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
01572 #define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
01573 #define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
01574 #define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
01575 #define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
01576 #define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
01577 /**
01578   * @}
01579   */
01580 #endif /* USE_FULL_LL_DRIVER */
01581
01582 /**
01583   * @}
01584   */
01585
01586 /* Exported macro ------------------------------------------------------------*/
01587 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
01588   * @{
01589   */
01590
01591 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
01592   * @{
01593   */
01594
01595 /**
01596   * @brief  Write a value in I2S register
01597   * @param  __INSTANCE__ I2S Instance
01598   * @param  __REG__ Register to be written
01599   * @param  __VALUE__ Value to be written in the register
01600   * @retval None
01601   */
01602 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01603
01604 /**
01605   * @brief  Read a value in I2S register
01606   * @param  __INSTANCE__ I2S Instance
01607   * @param  __REG__ Register to be read
01608   * @retval Register value
01609   */
01610 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01611 /**
01612   * @}
01613   */
01614
01615 /**
01616   * @}
01617   */
01618
01619
01620 /* Exported functions --------------------------------------------------------*/
01621
01622 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
01623   * @{
01624   */
01625
01626 /** @defgroup I2S_LL_EF_Configuration Configuration
01627   * @{
01628   */
01629
01630 /**
01631   * @brief  Select I2S mode and Enable I2S peripheral
01632   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
01633   *         I2SCFGR      I2SE          LL_I2S_Enable
01634   * @param  SPIx SPI Instance
01635   * @retval None
01636   */
01637 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
01638 {
01639   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
01640 }
01641
01642 /**
01643   * @brief  Disable I2S peripheral
01644   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
01645   * @param  SPIx SPI Instance
01646   * @retval None
01647   */
01648 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
01649 {
01650   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
01651 }
01652
01653 /**
01654   * @brief  Check if I2S peripheral is enabled
01655   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
01656   * @param  SPIx SPI Instance
01657   * @retval State of bit (1 or 0).
01658   */
01659 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
01660 {
01661   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
01662 }
01663
01664 /**
01665   * @brief  Set I2S data frame length
01666   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
01667   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
01668   * @param  SPIx SPI Instance
01669   * @param  DataFormat This parameter can be one of the following values:
01670   *         @arg @ref LL_I2S_DATAFORMAT_16B
01671   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
01672   *         @arg @ref LL_I2S_DATAFORMAT_24B
01673   *         @arg @ref LL_I2S_DATAFORMAT_32B
01674   * @retval None
01675   */
01676 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
01677 {
01678   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
01679 }
01680
01681 /**
01682   * @brief  Get I2S data frame length
01683   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
01684   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
01685   * @param  SPIx SPI Instance
01686   * @retval Returned value can be one of the following values:
01687   *         @arg @ref LL_I2S_DATAFORMAT_16B
01688   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
01689   *         @arg @ref LL_I2S_DATAFORMAT_24B
01690   *         @arg @ref LL_I2S_DATAFORMAT_32B
01691   */
01692 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
01693 {
01694   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
01695 }
01696
01697 /**
01698   * @brief  Set I2S clock polarity
01699   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
01700   * @param  SPIx SPI Instance
01701   * @param  ClockPolarity This parameter can be one of the following values:
01702   *         @arg @ref LL_I2S_POLARITY_LOW
01703   *         @arg @ref LL_I2S_POLARITY_HIGH
01704   * @retval None
01705   */
01706 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
01707 {
01708   SET_BIT(SPIx->I2SCFGR, ClockPolarity);
01709 }
01710
01711 /**
01712   * @brief  Get I2S clock polarity
01713   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
01714   * @param  SPIx SPI Instance
01715   * @retval Returned value can be one of the following values:
01716   *         @arg @ref LL_I2S_POLARITY_LOW
01717   *         @arg @ref LL_I2S_POLARITY_HIGH
01718   */
01719 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
01720 {
01721   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
01722 }
01723
01724 /**
01725   * @brief  Set I2S standard protocol
01726   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
01727   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
01728   * @param  SPIx SPI Instance
01729   * @param  Standard This parameter can be one of the following values:
01730   *         @arg @ref LL_I2S_STANDARD_PHILIPS
01731   *         @arg @ref LL_I2S_STANDARD_MSB
01732   *         @arg @ref LL_I2S_STANDARD_LSB
01733   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
01734   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
01735   * @retval None
01736   */
01737 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
01738 {
01739   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
01740 }
01741
01742 /**
01743   * @brief  Get I2S standard protocol
01744   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
01745   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
01746   * @param  SPIx SPI Instance
01747   * @retval Returned value can be one of the following values:
01748   *         @arg @ref LL_I2S_STANDARD_PHILIPS
01749   *         @arg @ref LL_I2S_STANDARD_MSB
01750   *         @arg @ref LL_I2S_STANDARD_LSB
01751   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
01752   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
01753   */
01754 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
01755 {
01756   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
01757 }
01758
01759 /**
01760   * @brief  Set I2S transfer mode
01761   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
01762   * @param  SPIx SPI Instance
01763   * @param  Mode This parameter can be one of the following values:
01764   *         @arg @ref LL_I2S_MODE_SLAVE_TX
01765   *         @arg @ref LL_I2S_MODE_SLAVE_RX
01766   *         @arg @ref LL_I2S_MODE_MASTER_TX
01767   *         @arg @ref LL_I2S_MODE_MASTER_RX
01768   * @retval None
01769   */
01770 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
01771 {
01772   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
01773 }
01774
01775 /**
01776   * @brief  Get I2S transfer mode
01777   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
01778   * @param  SPIx SPI Instance
01779   * @retval Returned value can be one of the following values:
01780   *         @arg @ref LL_I2S_MODE_SLAVE_TX
01781   *         @arg @ref LL_I2S_MODE_SLAVE_RX
01782   *         @arg @ref LL_I2S_MODE_MASTER_TX
01783   *         @arg @ref LL_I2S_MODE_MASTER_RX
01784   */
01785 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
01786 {
01787   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
01788 }
01789
01790 /**
01791   * @brief  Set I2S linear prescaler
01792   * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
01793   * @param  SPIx SPI Instance
01794   * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
01795   * @retval None
01796   */
01797 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
01798 {
01799   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
01800 }
01801
01802 /**
01803   * @brief  Get I2S linear prescaler
01804   * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
01805   * @param  SPIx SPI Instance
01806   * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
01807   */
01808 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
01809 {
01810   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
01811 }
01812
01813 /**
01814   * @brief  Set I2S parity prescaler
01815   * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
01816   * @param  SPIx SPI Instance
01817   * @param  PrescalerParity This parameter can be one of the following values:
01818   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
01819   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
01820   * @retval None
01821   */
01822 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
01823 {
01824   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
01825 }
01826
01827 /**
01828   * @brief  Get I2S parity prescaler
01829   * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
01830   * @param  SPIx SPI Instance
01831   * @retval Returned value can be one of the following values:
01832   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
01833   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
01834   */
01835 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
01836 {
01837   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
01838 }
01839
01840 /**
01841   * @brief  Enable the master clock output (Pin MCK)
01842   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
01843   * @param  SPIx SPI Instance
01844   * @retval None
01845   */
01846 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
01847 {
01848   SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
01849 }
01850
01851 /**
01852   * @brief  Disable the master clock output (Pin MCK)
01853   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
01854   * @param  SPIx SPI Instance
01855   * @retval None
01856   */
01857 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
01858 {
01859   CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
01860 }
01861
01862 /**
01863   * @brief  Check if the master clock output (Pin MCK) is enabled
01864   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
01865   * @param  SPIx SPI Instance
01866   * @retval State of bit (1 or 0).
01867   */
01868 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
01869 {
01870   return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
01871 }
01872
01873 #if defined(SPI_I2SCFGR_ASTRTEN)
01874 /**
01875   * @brief  Enable asynchronous start
01876   * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_EnableAsyncStart
01877   * @param  SPIx SPI Instance
01878   * @retval None
01879   */
01880 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
01881 {
01882   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
01883 }
01884
01885 /**
01886   * @brief  Disable  asynchronous start
01887   * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_DisableAsyncStart
01888   * @param  SPIx SPI Instance
01889   * @retval None
01890   */
01891 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
01892 {
01893   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
01894 }
01895
01896 /**
01897   * @brief  Check if asynchronous start is enabled
01898   * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_IsEnabledAsyncStart
01899   * @param  SPIx SPI Instance
01900   * @retval State of bit (1 or 0).
01901   */
01902 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
01903 {
01904   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
01905 }
01906 #endif /* SPI_I2SCFGR_ASTRTEN */
01907
01908 /**
01909   * @}
01910   */
01911
01912 /** @defgroup I2S_LL_EF_FLAG FLAG Management
01913   * @{
01914   */
01915
01916 /**
01917   * @brief  Check if Rx buffer is not empty
01918   * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
01919   * @param  SPIx SPI Instance
01920   * @retval State of bit (1 or 0).
01921   */
01922 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
01923 {
01924   return LL_SPI_IsActiveFlag_RXNE(SPIx);
01925 }
01926
01927 /**
01928   * @brief  Check if Tx buffer is empty
01929   * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
01930   * @param  SPIx SPI Instance
01931   * @retval State of bit (1 or 0).
01932   */
01933 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
01934 {
01935   return LL_SPI_IsActiveFlag_TXE(SPIx);
01936 }
01937
01938 /**
01939   * @brief  Get busy flag
01940   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
01941   * @param  SPIx SPI Instance
01942   * @retval State of bit (1 or 0).
01943   */
01944 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
01945 {
01946   return LL_SPI_IsActiveFlag_BSY(SPIx);
01947 }
01948
01949 /**
01950   * @brief  Get overrun error flag
01951   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
01952   * @param  SPIx SPI Instance
01953   * @retval State of bit (1 or 0).
01954   */
01955 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
01956 {
01957   return LL_SPI_IsActiveFlag_OVR(SPIx);
01958 }
01959
01960 /**
01961   * @brief  Get underrun error flag
01962   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
01963   * @param  SPIx SPI Instance
01964   * @retval State of bit (1 or 0).
01965   */
01966 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
01967 {
01968   return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
01969 }
01970
01971 /**
01972   * @brief  Get frame format error flag
01973   * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
01974   * @param  SPIx SPI Instance
01975   * @retval State of bit (1 or 0).
01976   */
01977 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
01978 {
01979   return LL_SPI_IsActiveFlag_FRE(SPIx);
01980 }
01981
01982 /**
01983   * @brief  Get channel side flag.
01984   * @note   0: Channel Left has to be transmitted or has been received\n
01985   *         1: Channel Right has to be transmitted or has been received\n
01986   *         It has no significance in PCM mode.
01987   * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
01988   * @param  SPIx SPI Instance
01989   * @retval State of bit (1 or 0).
01990   */
01991 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
01992 {
01993   return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
01994 }
01995
01996 /**
01997   * @brief  Clear overrun error flag
01998   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
01999   * @param  SPIx SPI Instance
02000   * @retval None
02001   */
02002 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
02003 {
02004   LL_SPI_ClearFlag_OVR(SPIx);
02005 }
02006
02007 /**
02008   * @brief  Clear underrun error flag
02009   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
02010   * @param  SPIx SPI Instance
02011   * @retval None
02012   */
02013 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
02014 {
02015   __IO uint32_t tmpreg;
02016   tmpreg = SPIx->SR;
02017   (void)tmpreg;
02018 }
02019
02020 /**
02021   * @brief  Clear frame format error flag
02022   * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
02023   * @param  SPIx SPI Instance
02024   * @retval None
02025   */
02026 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
02027 {
02028   LL_SPI_ClearFlag_FRE(SPIx);
02029 }
02030
02031 /**
02032   * @}
02033   */
02034
02035 /** @defgroup I2S_LL_EF_IT Interrupt Management
02036   * @{
02037   */
02038
02039 /**
02040   * @brief  Enable error IT
02041   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
02042   * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
02043   * @param  SPIx SPI Instance
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
02047 {
02048   LL_SPI_EnableIT_ERR(SPIx);
02049 }
02050
02051 /**
02052   * @brief  Enable Rx buffer not empty IT
02053   * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
02054   * @param  SPIx SPI Instance
02055   * @retval None
02056   */
02057 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
02058 {
02059   LL_SPI_EnableIT_RXNE(SPIx);
02060 }
02061
02062 /**
02063   * @brief  Enable Tx buffer empty IT
02064   * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
02065   * @param  SPIx SPI Instance
02066   * @retval None
02067   */
02068 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
02069 {
02070   LL_SPI_EnableIT_TXE(SPIx);
02071 }
02072
02073 /**
02074   * @brief  Disable error IT
02075   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
02076   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
02077   * @param  SPIx SPI Instance
02078   * @retval None
02079   */
02080 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
02081 {
02082   LL_SPI_DisableIT_ERR(SPIx);
02083 }
02084
02085 /**
02086   * @brief  Disable Rx buffer not empty IT
02087   * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
02088   * @param  SPIx SPI Instance
02089   * @retval None
02090   */
02091 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
02092 {
02093   LL_SPI_DisableIT_RXNE(SPIx);
02094 }
02095
02096 /**
02097   * @brief  Disable Tx buffer empty IT
02098   * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
02099   * @param  SPIx SPI Instance
02100   * @retval None
02101   */
02102 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
02103 {
02104   LL_SPI_DisableIT_TXE(SPIx);
02105 }
02106
02107 /**
02108   * @brief  Check if ERR IT is enabled
02109   * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
02110   * @param  SPIx SPI Instance
02111   * @retval State of bit (1 or 0).
02112   */
02113 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
02114 {
02115   return LL_SPI_IsEnabledIT_ERR(SPIx);
02116 }
02117
02118 /**
02119   * @brief  Check if RXNE IT is enabled
02120   * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
02121   * @param  SPIx SPI Instance
02122   * @retval State of bit (1 or 0).
02123   */
02124 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
02125 {
02126   return LL_SPI_IsEnabledIT_RXNE(SPIx);
02127 }
02128
02129 /**
02130   * @brief  Check if TXE IT is enabled
02131   * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
02132   * @param  SPIx SPI Instance
02133   * @retval State of bit (1 or 0).
02134   */
02135 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
02136 {
02137   return LL_SPI_IsEnabledIT_TXE(SPIx);
02138 }
02139
02140 /**
02141   * @}
02142   */
02143
02144 /** @defgroup I2S_LL_EF_DMA DMA Management
02145   * @{
02146   */
02147
02148 /**
02149   * @brief  Enable DMA Rx
02150   * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
02151   * @param  SPIx SPI Instance
02152   * @retval None
02153   */
02154 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
02155 {
02156   LL_SPI_EnableDMAReq_RX(SPIx);
02157 }
02158
02159 /**
02160   * @brief  Disable DMA Rx
02161   * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
02162   * @param  SPIx SPI Instance
02163   * @retval None
02164   */
02165 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
02166 {
02167   LL_SPI_DisableDMAReq_RX(SPIx);
02168 }
02169
02170 /**
02171   * @brief  Check if DMA Rx is enabled
02172   * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
02173   * @param  SPIx SPI Instance
02174   * @retval State of bit (1 or 0).
02175   */
02176 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
02177 {
02178   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
02179 }
02180
02181 /**
02182   * @brief  Enable DMA Tx
02183   * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
02184   * @param  SPIx SPI Instance
02185   * @retval None
02186   */
02187 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
02188 {
02189   LL_SPI_EnableDMAReq_TX(SPIx);
02190 }
02191
02192 /**
02193   * @brief  Disable DMA Tx
02194   * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
02195   * @param  SPIx SPI Instance
02196   * @retval None
02197   */
02198 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
02199 {
02200   LL_SPI_DisableDMAReq_TX(SPIx);
02201 }
02202
02203 /**
02204   * @brief  Check if DMA Tx is enabled
02205   * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
02206   * @param  SPIx SPI Instance
02207   * @retval State of bit (1 or 0).
02208   */
02209 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
02210 {
02211   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
02212 }
02213
02214 /**
02215   * @}
02216   */
02217
02218 /** @defgroup I2S_LL_EF_DATA DATA Management
02219   * @{
02220   */
02221
02222 /**
02223   * @brief  Read 16-Bits in data register
02224   * @rmtoll DR           DR            LL_I2S_ReceiveData16
02225   * @param  SPIx SPI Instance
02226   * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
02227   */
02228 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
02229 {
02230   return LL_SPI_ReceiveData16(SPIx);
02231 }
02232
02233 /**
02234   * @brief  Write 16-Bits in data register
02235   * @rmtoll DR           DR            LL_I2S_TransmitData16
02236   * @param  SPIx SPI Instance
02237   * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
02238   * @retval None
02239   */
02240 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
02241 {
02242   LL_SPI_TransmitData16(SPIx, TxData);
02243 }
02244
02245 /**
02246   * @}
02247   */
02248
02249 #if defined(USE_FULL_LL_DRIVER)
02250 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
02251   * @{
02252   */
02253
02254 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
02255 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
02256 void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
02257 void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
02258
02259 /**
02260   * @}
02261   */
02262 #endif /* USE_FULL_LL_DRIVER */
02263
02264 /**
02265   * @}
02266   */
02267
02268 /**
02269   * @}
02270   */
02271 #endif /* SPI_I2S_SUPPORT */
02272
02273 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
02274
02275 /**
02276   * @}
02277   */
02278
02279 #ifdef __cplusplus
02280 }
02281 #endif
02282
02283 #endif /* STM32G0xx_LL_SPI_H */
02284
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_system.h Source File

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stm32g0xx_ll_system.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_system.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SYSTEM LL module.
00006   *
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * Copyright (c) 2018 STMicroelectronics.
00011   * All rights reserved.
00012   *
00013   * This software is licensed under terms that can be found in the LICENSE file
00014   * in the root directory of this software component.
00015   * If no LICENSE file comes with this software, it is provided AS-IS.
00016   *
00017   ******************************************************************************
00018   @verbatim
00019   ==============================================================================
00020                      ##### How to use this driver #####
00021   ==============================================================================
00022     [..]
00023     The LL SYSTEM driver contains a set of generic APIs that can be
00024     used by user:
00025       (+) Some of the FLASH features need to be handled in the SYSTEM file.
00026       (+) Access to DBG registers
00027       (+) Access to SYSCFG registers
00028       (+) Access to VREFBUF registers
00029
00030   @endverbatim
00031   ******************************************************************************
00032   */
00033
00034 /* Define to prevent recursive inclusion -------------------------------------*/
00035 #ifndef STM32G0xx_LL_SYSTEM_H
00036 #define STM32G0xx_LL_SYSTEM_H
00037
00038 #ifdef __cplusplus
00039 extern "C" {
00040 #endif
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32g0xx.h"
00044
00045 /** @addtogroup STM32G0xx_LL_Driver
00046   * @{
00047   */
00048
00049 #if defined (FLASH) || defined (SYSCFG) || defined (DBG)
00050
00051 /** @defgroup SYSTEM_LL SYSTEM
00052   * @{
00053   */
00054
00055 /* Private types -------------------------------------------------------------*/
00056 /* Private variables ---------------------------------------------------------*/
00057
00058 /* Private constants ---------------------------------------------------------*/
00059 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
00060   * @{
00061   */
00062
00063 /**
00064   * @}
00065   */
00066
00067 /* Private macros ------------------------------------------------------------*/
00068
00069 /* Exported types ------------------------------------------------------------*/
00070 /* Exported constants --------------------------------------------------------*/
00071 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
00072   * @{
00073   */
00074
00075 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
00076   * @{
00077   */
00078 #define LL_SYSCFG_REMAP_FLASH               0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000 */
00079 #define LL_SYSCFG_REMAP_SYSTEMFLASH         SYSCFG_CFGR1_MEM_MODE_0                               /*!< System Flash memory mapped at 0x00000000 */
00080 #define LL_SYSCFG_REMAP_SRAM                (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)   /*!< Embedded SRAM mapped at 0x00000000 */
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup SYSTEM_LL_EC_PIN_RMP SYSCFG PIN RMP
00086   * @{
00087   */
00088 #define LL_SYSCFG_PIN_RMP_PA11              SYSCFG_CFGR1_PA11_RMP                           /*!< PA11 pad behaves as PA9 pin */
00089 #define LL_SYSCFG_PIN_RMP_PA12              SYSCFG_CFGR1_PA12_RMP                           /*!< PA12 pad behaves as PA10 pin */
00090 /**
00091   * @}
00092   */
00093
00094
00095 #if defined(SYSCFG_CFGR1_IR_MOD)
00096 /** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
00097   * @{
00098   */
00099 #define LL_SYSCFG_IR_MOD_TIM16       (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)    /*!< 00: Timer16 is selected as IRDA Modulation enveloppe source */
00100 #define LL_SYSCFG_IR_MOD_USART1      (SYSCFG_CFGR1_IR_MOD_0)                            /*!< 01: USART1 is selected as IRDA Modulation enveloppe source */
00101 #if defined(USART4)
00102 #define LL_SYSCFG_IR_MOD_USART4      (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART4 is selected as IRDA Modulation enveloppe source */
00103 #else
00104 #define LL_SYSCFG_IR_MOD_USART2      (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART2 is selected as IRDA Modulation enveloppe source */
00105 #endif /* USART4 */
00106 /**
00107   * @}
00108   */
00109 /** @defgroup SYSTEM_LL_EC_IR_POL SYSCFG IR Polarity
00110   * @{
00111   */
00112 #define LL_SYSCFG_IR_POL_NOT_INVERTED  0x00000000U                                     /*!< 0: Output of IRDA (IROut) not inverted */
00113 #define LL_SYSCFG_IR_POL_INVERTED     (SYSCFG_CFGR1_IR_POL)                            /*!< 1: Output of IRDA (IROut) inverted */
00114 /**
00115   * @}
00116   */
00117 #endif /* SYSCFG_CFGR1_IR_MOD */
00118
00119 #if defined(SYSCFG_CFGR1_BOOSTEN)
00120 /** @defgroup SYSTEM_LL_EC_BOOSTEN SYSCFG I/O analog switch voltage booster enable
00121   * @{
00122   */
00123 #define LL_SYSCFG_CFGR1_BOOSTEN       SYSCFG_CFGR1_BOOSTEN                             /*!< I/O analog switch voltage booster enable */
00124 /**
00125   * @}
00126   */
00127 #endif /* SYSCFG_CFGR1_BOOSTEN */
00128
00129 #if defined(SYSCFG_CFGR1_UCPD1_STROBE) ||  defined(SYSCFG_CFGR1_UCPD2_STROBE)
00130 /** @defgroup SYSTEM_LL_EC_UCPD_DBATTDIS SYSCFG UCPD Dead Battery feature Disable
00131   * @{
00132   */
00133 #define LL_SYSCFG_UCPD1_STROBE       SYSCFG_CFGR1_UCPD1_STROBE       /*!< UCPD1 STROBE sw configuration */
00134 #define LL_SYSCFG_UCPD2_STROBE       SYSCFG_CFGR1_UCPD2_STROBE       /*!< UCPD2 STROBE sw configuration */
00135 /**
00136   * @}
00137   */
00138 #endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */
00139
00140 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
00141   * @{
00142   */
00143 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< I2C PB6 Fast mode plus */
00144 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< I2C PB7 Fast mode plus */
00145 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< I2C PB8 Fast mode plus */
00146 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< I2C PB9 Fast mode plus */
00147 #if defined(SYSCFG_CFGR1_I2C1_FMP)
00148 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP /*!< Enable I2C1 Fast mode Plus  */
00149 #endif /*SYSCFG_CFGR1_I2C1_FMP*/
00150 #if defined(SYSCFG_CFGR1_I2C2_FMP)
00151 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP /*!< Enable I2C2 Fast mode plus  */
00152 #endif /*SYSCFG_CFGR1_I2C2_FMP*/
00153 #if defined(SYSCFG_CFGR1_I2C_PA9_FMP)
00154 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA9     SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9  */
00155 #endif /*SYSCFG_CFGR1_I2C_PA9_FMP*/
00156 #if defined(SYSCFG_CFGR1_I2C_PA10_FMP)
00157 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA10    SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */
00158 #endif /*SYSCFG_CFGR1_I2C_PA10_FMP*/
00159 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00160 #if defined(SYSCFG_CFGR1_I2C3_FMP)
00161 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP /*!< Enable I2C3 Fast mode plus  */
00162 #endif /*SYSCFG_CFGR1_I2C3_FMP*/
00163 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
00169   * @{
00170   */
00171 #define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL            /*!< Enables and locks the ECC error signal
00172                                                                            with Break Input of TIM1/15/16/17 */
00173 #if defined (PWR_PVD_SUPPORT)
00174 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL           /*!< Enables and locks the PVD connection
00175                                                                        with TIM1/15/16/17 Break Input and also
00176                                                                        the PVDE and PLS bits of the Power Control Interface */
00177 #endif /* PWR_PVD_SUPPORT */
00178 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY     SYSCFG_CFGR2_SPL            /*!< Enables and locks the SRAM_PARITY error signal
00179                                                                                 with Break Input of TIM1/15/16/17 */
00180 #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL            /*!< Enables and locks the LOCKUP (Hardfault) output of
00181                                                                            CortexM0 with Break Input of TIM1/15/16/17 */
00182 /**
00183   * @}
00184   */
00185
00186 #if defined(SYSCFG_CDEN_SUPPORT)
00187 /** @defgroup SYSTEM_LL_EC_CLAMPING_DIODE SYSCFG CLAMPING DIODE
00188   * @{
00189   */
00190 #define LL_SYSCFG_CFGR2_PA1_CDEN         SYSCFG_CFGR2_PA1_CDEN     /*!< Enables Clamping diode of PA1 */
00191 #define LL_SYSCFG_CFGR2_PA3_CDEN         SYSCFG_CFGR2_PA3_CDEN     /*!< Enables Clamping diode of PA3 */
00192 #define LL_SYSCFG_CFGR2_PA5_CDEN         SYSCFG_CFGR2_PA5_CDEN     /*!< Enables Clamping diode of PA5 */
00193 #define LL_SYSCFG_CFGR2_PA6_CDEN         SYSCFG_CFGR2_PA6_CDEN     /*!< Enables Clamping diode of PA6 */
00194 #define LL_SYSCFG_CFGR2_PA13_CDEN        SYSCFG_CFGR2_PA13_CDEN    /*!< Enables Clamping diode of PA13 */
00195 #define LL_SYSCFG_CFGR2_PB0_CDEN         SYSCFG_CFGR2_PB0_CDEN     /*!< Enables Clamping diode of PB0 */
00196 #define LL_SYSCFG_CFGR2_PB1_CDEN         SYSCFG_CFGR2_PB1_CDEN     /*!< Enables Clamping diode of PB1 */
00197 #define LL_SYSCFG_CFGR2_PB2_CDEN         SYSCFG_CFGR2_PB2_CDEN     /*!< Enables Clamping diode of PB2 */
00198 /**
00199   * @}
00200   */
00201 #endif /* SYSCFG_CDEN_SUPPORT */
00202
00203 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP  DBGMCU APB1 GRP1 STOP IP
00204   * @{
00205   */
00206 #if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
00207 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBG_APB_FZ1_DBG_TIM2_STOP        /*!< TIM2 counter stopped when core is halted */
00208 #endif /*DBG_APB_FZ1_DBG_TIM2_STOP*/
00209 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBG_APB_FZ1_DBG_TIM3_STOP        /*!< TIM3 counter stopped when core is halted */
00210 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00211 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBG_APB_FZ1_DBG_TIM4_STOP        /*!< TIM4 counter stopped when core is halted */
00212 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00213 #if defined(DBG_APB_FZ1_DBG_TIM6_STOP)
00214 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBG_APB_FZ1_DBG_TIM6_STOP        /*!< TIM6 counter stopped when core is halted */
00215 #endif /*DBG_APB_FZ1_DBG_TIM6_STOP*/
00216 #if defined(DBG_APB_FZ1_DBG_TIM7_STOP)
00217 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBG_APB_FZ1_DBG_TIM7_STOP        /*!< TIM7 counter stopped when core is halted  */
00218 #endif /*DBG_APB_FZ1_DBG_TIM7_STOP*/
00219 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBG_APB_FZ1_DBG_RTC_STOP         /*!< RTC Calendar frozen when core is halted */
00220 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBG_APB_FZ1_DBG_WWDG_STOP        /*!< Debug Window Watchdog stopped when Core is halted */
00221 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBG_APB_FZ1_DBG_IWDG_STOP        /*!< Debug Independent Watchdog stopped when Core is halted */
00222 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
00223 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00224 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
00225 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00226 #if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP)
00227 #define LL_DBGMCU_APB1_GRP1_LPTIM2_STOP    DBG_APB_FZ1_DBG_LPTIM2_STOP      /*!< LPTIM2 counter stopped when Core is halted */
00228 #endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */
00229 #if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP)
00230 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBG_APB_FZ1_DBG_LPTIM1_STOP      /*!< LPTIM1 counter stopped when Core is halted */
00231 #endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
00237   * @{
00238   */
00239 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBG_APB_FZ2_DBG_TIM1_STOP        /*!< TIM1 counter stopped when core is halted */
00240 #if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
00241 #define LL_DBGMCU_APB2_GRP1_TIM14_STOP     DBG_APB_FZ2_DBG_TIM14_STOP       /*!< TIM14 counter stopped when core is halted */
00242 #endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
00243 #if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
00244 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBG_APB_FZ2_DBG_TIM15_STOP       /*!< TIM15 counter stopped when core is halted  */
00245 #endif /*DBG_APB_FZ2_DBG_TIM15_STOP*/
00246 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBG_APB_FZ2_DBG_TIM16_STOP       /*!< TIM16 counter stopped when core is halted */
00247 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBG_APB_FZ2_DBG_TIM17_STOP       /*!< TIM17 counter stopped when core is halted */
00248 /**
00249   * @}
00250   */
00251
00252
00253 #if defined(VREFBUF)
00254 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
00255   * @{
00256   */
00257 #define LL_VREFBUF_VOLTAGE_SCALE0          0x00000000U            /*!< Voltage reference scale 0 (VREF_OUT1) */
00258 #define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
00259 /**
00260   * @}
00261   */
00262 #endif /* VREFBUF */
00263
00264 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
00265   * @{
00266   */
00267 #define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
00268 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_0     /*!< FLASH One Latency cycle */
00269 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_1     /*!< FLASH Two wait states */
00270 #define LL_FLASH_LATENCY_3                 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)     /*!< FLASH Three wait states */
00271 /**
00272   * @}
00273   */
00274
00275 /**
00276   * @}
00277   */
00278
00279 /* Exported macro ------------------------------------------------------------*/
00280
00281 /* Exported functions --------------------------------------------------------*/
00282 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
00283   * @{
00284   */
00285
00286 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
00287   * @{
00288   */
00289
00290 /**
00291   * @brief  Set memory mapping at address 0x00000000
00292   * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_SetRemapMemory
00293   * @param  Memory This parameter can be one of the following values:
00294   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00295   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00296   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00297   * @retval None
00298   */
00299 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
00300 {
00301   MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
00302 }
00303
00304 /**
00305   * @brief  Get memory mapping at address 0x00000000
00306   * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_GetRemapMemory
00307   * @retval Returned value can be one of the following values:
00308   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00309   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00310   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00311   */
00312 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
00313 {
00314   return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
00315 }
00316
00317 /**
00318   * @brief  Enable remap of a pin on different pad
00319   * @rmtoll SYSCFG_CFGR1 PA11_RMP  LL_SYSCFG_EnablePinRemap\n
00320   *         SYSCFG_CFGR1 PA12_RMP   LL_SYSCFG_EnablePinRemap\n
00321   * @param  PinRemap This parameter can be a combination of the following values:
00322   *         @arg @ref LL_SYSCFG_PIN_RMP_PA11
00323   *         @arg @ref LL_SYSCFG_PIN_RMP_PA12
00324   * @retval None
00325   */
00326 __STATIC_INLINE void LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)
00327 {
00328   SET_BIT(SYSCFG->CFGR1, PinRemap);
00329 }
00330
00331 /**
00332   * @brief  Enable remap of a pin on different pad
00333   * @rmtoll SYSCFG_CFGR1 PA11_RMP  LL_SYSCFG_DisablePinRemap\n
00334   *         SYSCFG_CFGR1 PA12_RMP   LL_SYSCFG_DisablePinRemap\n
00335   * @param  PinRemap This parameter can be a combination of the following values:
00336   *         @arg @ref LL_SYSCFG_PIN_RMP_PA11
00337   *         @arg @ref LL_SYSCFG_PIN_RMP_PA12
00338   * @retval None
00339   */
00340 __STATIC_INLINE void LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)
00341 {
00342   CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
00343 }
00344
00345 #if defined(SYSCFG_CFGR1_IR_MOD)
00346 /**
00347   * @brief  Set IR Modulation Envelope signal source.
00348   * @rmtoll SYSCFG_CFGR1 IR_MOD  LL_SYSCFG_SetIRModEnvelopeSignal
00349   * @param  Source This parameter can be one of the following values:
00350   *         @arg @ref LL_SYSCFG_IR_MOD_TIM16
00351   *         @arg @ref LL_SYSCFG_IR_MOD_USART1
00352   *         @arg @ref LL_SYSCFG_IR_MOD_USART4
00353   * @retval None
00354   */
00355 __STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
00356 {
00357   MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
00358 }
00359
00360 /**
00361   * @brief  Get IR Modulation Envelope signal source.
00362   * @rmtoll SYSCFG_CFGR1 IR_MOD  LL_SYSCFG_GetIRModEnvelopeSignal
00363   * @retval Returned value can be one of the following values:
00364   *         @arg @ref LL_SYSCFG_IR_MOD_TIM16
00365   *         @arg @ref LL_SYSCFG_IR_MOD_USART1
00366   *         @arg @ref LL_SYSCFG_IR_MOD_USART4
00367   */
00368 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
00369 {
00370   return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
00371 }
00372
00373 /**
00374   * @brief  Set IR Output polarity.
00375   * @rmtoll SYSCFG_CFGR1 IR_POL  LL_SYSCFG_SetIRPolarity
00376   * @param  Polarity This parameter can be one of the following values:
00377   *         @arg @ref LL_SYSCFG_IR_POL_INVERTED
00378   *         @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
00379   * @retval None
00380   */
00381 __STATIC_INLINE void LL_SYSCFG_SetIRPolarity(uint32_t Polarity)
00382 {
00383   MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL, Polarity);
00384 }
00385
00386 /**
00387   * @brief  Get IR Output polarity.
00388   * @rmtoll SYSCFG_CFGR1 IR_POL  LL_SYSCFG_GetIRPolarity
00389   * @retval Returned value can be one of the following values:
00390   *         @arg @ref LL_SYSCFG_IR_POL_INVERTED
00391   *         @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
00392   */
00393 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRPolarity(void)
00394 {
00395   return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL));
00396 }
00397 #endif /* SYSCFG_CFGR1_IR_MOD */
00398
00399 #if defined(SYSCFG_CFGR1_BOOSTEN)
00400 /**
00401   * @brief  Enable I/O analog switch voltage booster.
00402   * @note   When voltage booster is enabled, I/O analog switches are supplied
00403   *         by a dedicated voltage booster, from VDD power domain. This is
00404   *         the recommended configuration with low VDDA voltage operation.
00405   * @note   The I/O analog switch voltage booster is relevant for peripherals
00406   *         using I/O in analog input: ADC, COMP.
00407   *         However, COMP and OPAMP inputs have a high impedance and
00408   *         voltage booster do not impact performance significantly.
00409   *         Therefore, the voltage booster is mainly intended for
00410   *         usage with ADC.
00411   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
00412   * @retval None
00413   */
00414 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
00415 {
00416   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00417 }
00418
00419 /**
00420   * @brief  Disable I/O analog switch voltage booster.
00421   * @note   When voltage booster is enabled, I/O analog switches are supplied
00422   *         by a dedicated voltage booster, from VDD power domain. This is
00423   *         the recommended configuration with low VDDA voltage operation.
00424   * @note   The I/O analog switch voltage booster is relevant for peripherals
00425   *         using I/O in analog input: ADC, COMP.
00426   *         However, COMP and OPAMP inputs have a high impedance and
00427   *         voltage booster do not impact performance significantly.
00428   *         Therefore, the voltage booster is mainly intended for
00429   *         usage with ADC.
00430   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
00431   * @retval None
00432   */
00433 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
00434 {
00435   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00436 }
00437 #endif /* SYSCFG_CFGR1_BOOSTEN */
00438
00439 /**
00440   * @brief  Enable the I2C fast mode plus driving capability.
00441   * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6   LL_SYSCFG_EnableFastModePlus\n
00442   *         SYSCFG_CFGR1 I2C_FMP_PB7   LL_SYSCFG_EnableFastModePlus\n
00443   *         SYSCFG_CFGR1 I2C_FMP_PB8   LL_SYSCFG_EnableFastModePlus\n
00444   *         SYSCFG_CFGR1 I2C_FMP_PB9   LL_SYSCFG_EnableFastModePlus\n
00445   *         SYSCFG_CFGR1 I2C_FMP_I2C1  LL_SYSCFG_EnableFastModePlus\n
00446   *         SYSCFG_CFGR1 I2C_FMP_I2C2  LL_SYSCFG_EnableFastModePlus\n
00447   *         SYSCFG_CFGR1 I2C_FMP_I2C3  LL_SYSCFG_EnableFastModePlus\n
00448   *         SYSCFG_CFGR1 I2C_FMP_PA9   LL_SYSCFG_EnableFastModePlus\n
00449   *         SYSCFG_CFGR1 I2C_FMP_PA10  LL_SYSCFG_EnableFastModePlus
00450   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00451   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00452   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00453   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
00454   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
00455   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
00456   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00457   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
00458   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
00459   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
00460   *
00461   *         (*) value not defined in all devices
00462   * @retval None
00463   */
00464 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
00465 {
00466   SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00467 }
00468
00469 /**
00470   * @brief  Disable the I2C fast mode plus driving capability.
00471   * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6   LL_SYSCFG_DisableFastModePlus\n
00472   *         SYSCFG_CFGR1 I2C_FMP_PB7   LL_SYSCFG_DisableFastModePlus\n
00473   *         SYSCFG_CFGR1 I2C_FMP_PB8   LL_SYSCFG_DisableFastModePlus\n
00474   *         SYSCFG_CFGR1 I2C_FMP_PB9   LL_SYSCFG_DisableFastModePlus\n
00475   *         SYSCFG_CFGR1 I2C_FMP_I2C1  LL_SYSCFG_DisableFastModePlus\n
00476   *         SYSCFG_CFGR1 I2C_FMP_I2C2  LL_SYSCFG_DisableFastModePlus\n
00477   *         SYSCFG_CFGR1 I2C_FMP_I2C3  LL_SYSCFG_DisableFastModePlus\n
00478   *         SYSCFG_CFGR1 I2C_FMP_PA9   LL_SYSCFG_DisableFastModePlus\n
00479   *         SYSCFG_CFGR1 I2C_FMP_PA10  LL_SYSCFG_DisableFastModePlus
00480   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00481   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00482   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00483   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
00484   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
00485   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
00486   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00487   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
00488   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
00489   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
00490   *
00491   *         (*) value not defined in all devices
00492   * @retval None
00493   */
00494 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
00495 {
00496   CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00497 }
00498
00499 #if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
00500 /**
00501   * @brief  Disable dead battery behavior
00502   * @rmtoll SYSCFG_CFGR1 UCPD1_STROBE   LL_SYSCFG_DisableDBATT\n
00503   *         SYSCFG_CFGR1 UCPD2_STROBE   LL_SYSCFG_DisableDBATT
00504   * @param  ConfigDeadBattery This parameter can be a combination of the following values:
00505   *         @arg @ref LL_SYSCFG_UCPD1_STROBE\n
00506   *         @arg @ref LL_SYSCFG_UCPD2_STROBE
00507   *         (*) value not defined in all devices
00508   * @retval None
00509   */
00510 __STATIC_INLINE void LL_SYSCFG_DisableDBATT(uint32_t ConfigDeadBattery)
00511 {
00512   SET_BIT(SYSCFG->CFGR1, ConfigDeadBattery);
00513 }
00514 #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
00515
00516 #if defined(SYSCFG_ITLINE0_SR_EWDG)
00517 /**
00518   * @brief  Check if Window watchdog interrupt occurred or not.
00519   * @rmtoll SYSCFG_ITLINE0 SR_EWDG       LL_SYSCFG_IsActiveFlag_WWDG
00520   * @retval State of bit (1 or 0).
00521   */
00522 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
00523 {
00524   return ((READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)) ? 1UL : 0UL);
00525 }
00526 #endif /* SYSCFG_ITLINE0_SR_EWDG */
00527
00528 #if defined (PWR_PVD_SUPPORT)
00529 /**
00530   * @brief  Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
00531   * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT     LL_SYSCFG_IsActiveFlag_PVDOUT
00532   * @retval State of bit (1 or 0).
00533   */
00534 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
00535 {
00536   return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)) ? 1UL : 0UL);
00537 }
00538 #endif /* PWR_PVD_SUPPORT */
00539
00540 #if defined (PWR_PVM_SUPPORT)
00541 /**
00542   * @brief  Check if VDDUSB supply monitoring interrupt occurred or not (EXTI line 34).
00543   * @rmtoll SYSCFG_ITLINE1 SR_PVMOUT     LL_SYSCFG_IsActiveFlag_PVMOUT
00544   * @retval State of bit (1 or 0).
00545   */
00546 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVMOUT(void)
00547 {
00548   return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVMOUT) == (SYSCFG_ITLINE1_SR_PVMOUT)) ? 1UL : 0UL);
00549 }
00550 #endif /* PWR_PVM_SUPPORT */
00551
00552 #if defined(SYSCFG_ITLINE2_SR_RTC)
00553 /**
00554   * @brief  Check if RTC Wake Up interrupt occurred or not (EXTI line 19).
00555   * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP  LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
00556   * @retval State of bit (1 or 0).
00557   */
00558 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
00559 {
00560   return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC) == (SYSCFG_ITLINE2_SR_RTC)) ? 1UL : 0UL);
00561 }
00562 #endif /* SYSCFG_ITLINE2_SR_RTC */
00563
00564 #if defined(SYSCFG_ITLINE2_SR_TAMPER)
00565 /**
00566   * @brief  Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 21).
00567   * @rmtoll SYSCFG_ITLINE2 SR_TAMPER  LL_SYSCFG_IsActiveFlag_TAMPER
00568   * @retval State of bit (1 or 0).
00569   */
00570 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TAMPER(void)
00571 {
00572   return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_TAMPER) == (SYSCFG_ITLINE2_SR_TAMPER)) ? 1UL : 0UL);
00573 }
00574 #endif /* SYSCFG_ITLINE2_SR_TAMPER */
00575
00576 #if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
00577 /**
00578   * @brief  Check if Flash interface interrupt occurred or not.
00579   * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF  LL_SYSCFG_IsActiveFlag_FLASH_ITF
00580   * @retval State of bit (1 or 0).
00581   */
00582 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
00583 {
00584   return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)) ? 1UL : 0UL);
00585 }
00586 #endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
00587
00588 #if defined(SYSCFG_ITLINE3_SR_FLASH_ECC)
00589 /**
00590   * @brief  Check if Flash interface interrupt occurred or not.
00591   * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ECC  LL_SYSCFG_IsActiveFlag_FLASH_ECC
00592   * @retval State of bit (1 or 0).
00593   */
00594 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ECC(void)
00595 {
00596   return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ECC) == (SYSCFG_ITLINE3_SR_FLASH_ECC)) ? 1UL : 0UL);
00597 }
00598 #endif /* SYSCFG_ITLINE3_SR_FLASH_ECC */
00599
00600 #if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
00601 /**
00602   * @brief  Check if Reset and clock control interrupt occurred or not.
00603   * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL   LL_SYSCFG_IsActiveFlag_CLK_CTRL
00604   * @retval State of bit (1 or 0).
00605   */
00606 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
00607 {
00608   return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)) ? 1UL : 0UL);
00609 }
00610 #endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
00611
00612 #if defined(CRS)
00613 /**
00614   * @brief  Check if Reset and clock control interrupt occurred or not.
00615   * @rmtoll SYSCFG_ITLINE4 SR_CRS   LL_SYSCFG_IsActiveFlag_CRS
00616   * @retval State of bit (1 or 0).
00617   */
00618 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
00619 {
00620   return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)) ? 1UL : 0UL);
00621 }
00622 #endif /* CRS */
00623 #if defined(SYSCFG_ITLINE5_SR_EXTI0)
00624 /**
00625   * @brief  Check if EXTI line 0 interrupt occurred or not.
00626   * @rmtoll SYSCFG_ITLINE5 SR_EXTI0      LL_SYSCFG_IsActiveFlag_EXTI0
00627   * @retval State of bit (1 or 0).
00628   */
00629 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
00630 {
00631   return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)) ? 1UL : 0UL);
00632 }
00633 #endif /* SYSCFG_ITLINE5_SR_EXTI0 */
00634
00635 #if defined(SYSCFG_ITLINE5_SR_EXTI1)
00636 /**
00637   * @brief  Check if EXTI line 1 interrupt occurred or not.
00638   * @rmtoll SYSCFG_ITLINE5 SR_EXTI1      LL_SYSCFG_IsActiveFlag_EXTI1
00639   * @retval State of bit (1 or 0).
00640   */
00641 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
00642 {
00643   return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)) ? 1UL : 0UL);
00644 }
00645 #endif /* SYSCFG_ITLINE5_SR_EXTI1 */
00646
00647 #if defined(SYSCFG_ITLINE6_SR_EXTI2)
00648 /**
00649   * @brief  Check if EXTI line 2 interrupt occurred or not.
00650   * @rmtoll SYSCFG_ITLINE6 SR_EXTI2      LL_SYSCFG_IsActiveFlag_EXTI2
00651   * @retval State of bit (1 or 0).
00652   */
00653 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
00654 {
00655   return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)) ? 1UL : 0UL);
00656 }
00657 #endif /* SYSCFG_ITLINE6_SR_EXTI2 */
00658
00659 #if defined(SYSCFG_ITLINE6_SR_EXTI3)
00660 /**
00661   * @brief  Check if EXTI line 3 interrupt occurred or not.
00662   * @rmtoll SYSCFG_ITLINE6 SR_EXTI3      LL_SYSCFG_IsActiveFlag_EXTI3
00663   * @retval State of bit (1 or 0).
00664   */
00665 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
00666 {
00667   return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)) ? 1UL : 0UL);
00668 }
00669 #endif /* SYSCFG_ITLINE6_SR_EXTI3 */
00670
00671 #if defined(SYSCFG_ITLINE7_SR_EXTI4)
00672 /**
00673   * @brief  Check if EXTI line 4 interrupt occurred or not.
00674   * @rmtoll SYSCFG_ITLINE7 SR_EXTI4      LL_SYSCFG_IsActiveFlag_EXTI4
00675   * @retval State of bit (1 or 0).
00676   */
00677 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
00678 {
00679   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)) ? 1UL : 0UL);
00680 }
00681 #endif /* SYSCFG_ITLINE7_SR_EXTI4 */
00682
00683 #if defined(SYSCFG_ITLINE7_SR_EXTI5)
00684 /**
00685   * @brief  Check if EXTI line 5 interrupt occurred or not.
00686   * @rmtoll SYSCFG_ITLINE7 SR_EXTI5      LL_SYSCFG_IsActiveFlag_EXTI5
00687   * @retval State of bit (1 or 0).
00688   */
00689 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
00690 {
00691   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)) ? 1UL : 0UL);
00692 }
00693 #endif /* SYSCFG_ITLINE7_SR_EXTI5 */
00694
00695 #if defined(SYSCFG_ITLINE7_SR_EXTI6)
00696 /**
00697   * @brief  Check if EXTI line 6 interrupt occurred or not.
00698   * @rmtoll SYSCFG_ITLINE7 SR_EXTI6      LL_SYSCFG_IsActiveFlag_EXTI6
00699   * @retval State of bit (1 or 0).
00700   */
00701 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
00702 {
00703   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)) ? 1UL : 0UL);
00704 }
00705 #endif /* SYSCFG_ITLINE7_SR_EXTI6 */
00706
00707 #if defined(SYSCFG_ITLINE7_SR_EXTI7)
00708 /**
00709   * @brief  Check if EXTI line 7 interrupt occurred or not.
00710   * @rmtoll SYSCFG_ITLINE7 SR_EXTI7      LL_SYSCFG_IsActiveFlag_EXTI7
00711   * @retval State of bit (1 or 0).
00712   */
00713 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
00714 {
00715   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)) ? 1UL : 0UL);
00716 }
00717 #endif /* SYSCFG_ITLINE7_SR_EXTI7 */
00718
00719 #if defined(SYSCFG_ITLINE7_SR_EXTI8)
00720 /**
00721   * @brief  Check if EXTI line 8 interrupt occurred or not.
00722   * @rmtoll SYSCFG_ITLINE7 SR_EXTI8      LL_SYSCFG_IsActiveFlag_EXTI8
00723   * @retval State of bit (1 or 0).
00724   */
00725 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
00726 {
00727   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)) ? 1UL : 0UL);
00728 }
00729 #endif /* SYSCFG_ITLINE7_SR_EXTI8 */
00730
00731 #if defined(SYSCFG_ITLINE7_SR_EXTI9)
00732 /**
00733   * @brief  Check if EXTI line 9 interrupt occurred or not.
00734   * @rmtoll SYSCFG_ITLINE7 SR_EXTI9      LL_SYSCFG_IsActiveFlag_EXTI9
00735   * @retval State of bit (1 or 0).
00736   */
00737 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
00738 {
00739   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)) ? 1UL : 0UL);
00740 }
00741 #endif /* SYSCFG_ITLINE7_SR_EXTI9 */
00742
00743 #if defined(SYSCFG_ITLINE7_SR_EXTI10)
00744 /**
00745   * @brief  Check if EXTI line 10 interrupt occurred or not.
00746   * @rmtoll SYSCFG_ITLINE7 SR_EXTI10     LL_SYSCFG_IsActiveFlag_EXTI10
00747   * @retval State of bit (1 or 0).
00748   */
00749 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
00750 {
00751   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)) ? 1UL : 0UL);
00752 }
00753 #endif /* SYSCFG_ITLINE7_SR_EXTI10 */
00754
00755 #if defined(SYSCFG_ITLINE7_SR_EXTI11)
00756 /**
00757   * @brief  Check if EXTI line 11 interrupt occurred or not.
00758   * @rmtoll SYSCFG_ITLINE7 SR_EXTI11     LL_SYSCFG_IsActiveFlag_EXTI11
00759   * @retval State of bit (1 or 0).
00760   */
00761 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
00762 {
00763   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)) ? 1UL : 0UL);
00764 }
00765 #endif /* SYSCFG_ITLINE7_SR_EXTI11 */
00766
00767 #if defined(SYSCFG_ITLINE7_SR_EXTI12)
00768 /**
00769   * @brief  Check if EXTI line 12 interrupt occurred or not.
00770   * @rmtoll SYSCFG_ITLINE7 SR_EXTI12     LL_SYSCFG_IsActiveFlag_EXTI12
00771   * @retval State of bit (1 or 0).
00772   */
00773 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
00774 {
00775   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)) ? 1UL : 0UL);
00776 }
00777 #endif /* SYSCFG_ITLINE7_SR_EXTI12 */
00778
00779 #if defined(SYSCFG_ITLINE7_SR_EXTI13)
00780 /**
00781   * @brief  Check if EXTI line 13 interrupt occurred or not.
00782   * @rmtoll SYSCFG_ITLINE7 SR_EXTI13     LL_SYSCFG_IsActiveFlag_EXTI13
00783   * @retval State of bit (1 or 0).
00784   */
00785 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
00786 {
00787   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)) ? 1UL : 0UL);
00788 }
00789 #endif /* SYSCFG_ITLINE7_SR_EXTI13 */
00790
00791 #if defined(SYSCFG_ITLINE7_SR_EXTI14)
00792 /**
00793   * @brief  Check if EXTI line 14 interrupt occurred or not.
00794   * @rmtoll SYSCFG_ITLINE7 SR_EXTI14     LL_SYSCFG_IsActiveFlag_EXTI14
00795   * @retval State of bit (1 or 0).
00796   */
00797 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
00798 {
00799   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)) ? 1UL : 0UL);
00800 }
00801 #endif /* SYSCFG_ITLINE7_SR_EXTI14 */
00802
00803 #if defined(SYSCFG_ITLINE7_SR_EXTI15)
00804 /**
00805   * @brief  Check if EXTI line 15 interrupt occurred or not.
00806   * @rmtoll SYSCFG_ITLINE7 SR_EXTI15     LL_SYSCFG_IsActiveFlag_EXTI15
00807   * @retval State of bit (1 or 0).
00808   */
00809 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
00810 {
00811   return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)) ? 1UL : 0UL);
00812 }
00813 #endif /* SYSCFG_ITLINE7_SR_EXTI15 */
00814
00815 #if defined(SYSCFG_ITLINE8_SR_UCPD1)
00816 /**
00817   * @brief  Check if UCPD1 interrupt occurred or not.
00818   * @rmtoll SYSCFG_ITLINE8 SR_UCPD1    LL_SYSCFG_IsActiveFlag_UCPD1
00819   * @retval State of bit (1 or 0).
00820   */
00821 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_UCPD1(void)
00822 {
00823   return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_UCPD1) == (SYSCFG_ITLINE8_SR_UCPD1)) ? 1UL : 0UL);
00824 }
00825 #endif /* SYSCFG_ITLINE8_SR_UCPD1 */
00826
00827 #if defined(SYSCFG_ITLINE8_SR_UCPD2)
00828 /**
00829   * @brief  Check if UCPD2 interrupt occurred or not.
00830   * @rmtoll SYSCFG_ITLINE8 SR_UCPD2    LL_SYSCFG_IsActiveFlag_UCPD2
00831   * @retval State of bit (1 or 0).
00832   */
00833 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_UCPD2(void)
00834 {
00835   return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_UCPD2) == (SYSCFG_ITLINE8_SR_UCPD2)) ? 1UL : 0UL);
00836 }
00837 #endif /* SYSCFG_ITLINE8_SR_UCPD2 */
00838
00839 #if defined(SYSCFG_ITLINE8_SR_USB)
00840 /**
00841   * @brief  Check if USB interrupt occurred or not.
00842   * @rmtoll SYSCFG_ITLINE8 SR_USB    LL_SYSCFG_IsActiveFlag_USB
00843   * @retval State of bit (1 or 0).
00844   */
00845 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USB(void)
00846 {
00847   return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_USB) == (SYSCFG_ITLINE8_SR_USB)) ? 1UL : 0UL);
00848 }
00849 #endif /* SYSCFG_ITLINE8_SR_USB */
00850
00851 #if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
00852 /**
00853   * @brief  Check if DMA1 channel 1 interrupt occurred or not.
00854   * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1   LL_SYSCFG_IsActiveFlag_DMA1_CH1
00855   * @retval State of bit (1 or 0).
00856   */
00857 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
00858 {
00859   return ((READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)) ? 1UL : 0UL);
00860 }
00861 #endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
00862
00863 #if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
00864 /**
00865   * @brief  Check if DMA1 channel 2 interrupt occurred or not.
00866   * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2   LL_SYSCFG_IsActiveFlag_DMA1_CH2
00867   * @retval State of bit (1 or 0).
00868   */
00869 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
00870 {
00871   return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)) ? 1UL : 0UL);
00872 }
00873 #endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
00874
00875 #if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
00876 /**
00877   * @brief  Check if DMA1 channel 3 interrupt occurred or not.
00878   * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3   LL_SYSCFG_IsActiveFlag_DMA1_CH3
00879   * @retval State of bit (1 or 0).
00880   */
00881 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
00882 {
00883   return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)) ? 1UL : 0UL);
00884 }
00885 #endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
00886
00887 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
00888 /**
00889   * @brief  Check if DMA1 channel 4 interrupt occurred or not.
00890   * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4   LL_SYSCFG_IsActiveFlag_DMA1_CH4
00891   * @retval State of bit (1 or 0).
00892   */
00893 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
00894 {
00895   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)) ? 1UL : 0UL);
00896 }
00897 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
00898
00899 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
00900 /**
00901   * @brief  Check if DMA1 channel 5 interrupt occurred or not.
00902   * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5   LL_SYSCFG_IsActiveFlag_DMA1_CH5
00903   * @retval State of bit (1 or 0).
00904   */
00905 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
00906 {
00907   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)) ? 1UL : 0UL);
00908 }
00909 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
00910
00911 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
00912 /**
00913   * @brief  Check if DMA1 channel 6 interrupt occurred or not.
00914   * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6   LL_SYSCFG_IsActiveFlag_DMA1_CH6
00915   * @retval State of bit (1 or 0).
00916   */
00917 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
00918 {
00919   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)) ? 1UL : 0UL);
00920 }
00921 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
00922
00923 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
00924 /**
00925   * @brief  Check if DMA1 channel 7 interrupt occurred or not.
00926   * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7   LL_SYSCFG_IsActiveFlag_DMA1_CH7
00927   * @retval State of bit (1 or 0).
00928   */
00929 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
00930 {
00931   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)) ? 1UL : 0UL);
00932 }
00933 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
00934
00935 #if defined(SYSCFG_ITLINE11_SR_DMAMUX1)
00936 /**
00937   * @brief  Check if DMAMUX interrupt occurred or not.
00938   * @rmtoll SYSCFG_ITLINE11 SR_DMAMUX1   LL_SYSCFG_IsActiveFlag_DMAMUX
00939   * @retval State of bit (1 or 0).
00940   */
00941 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMAMUX(void)
00942 {
00943   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMAMUX1) == (SYSCFG_ITLINE11_SR_DMAMUX1)) ? 1UL : 0UL);
00944 }
00945 #endif /* SYSCFG_ITLINE11_SR_DMAMUX */
00946
00947 #if defined(SYSCFG_ITLINE11_SR_DMA2_CH1)
00948 /**
00949   * @brief  Check if DMA2_CH1 interrupt occurred or not.
00950   * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH1   LL_SYSCFG_IsActiveFlag_DMA2_CH1
00951   * @retval State of bit (1 or 0).
00952   */
00953 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
00954 {
00955   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH1) == (SYSCFG_ITLINE11_SR_DMA2_CH1)) ? 1UL : 0UL);
00956 }
00957 #endif /* SYSCFG_ITLINE11_SR_DMA2_CH1 */
00958
00959 #if defined(SYSCFG_ITLINE11_SR_DMA2_CH2)
00960 /**
00961   * @brief  Check if DMA2_CH2 interrupt occurred or not.
00962   * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH2   LL_SYSCFG_IsActiveFlag_DMA2_CH2
00963   * @retval State of bit (1 or 0).
00964   */
00965 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
00966 {
00967   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH2) == (SYSCFG_ITLINE11_SR_DMA2_CH2)) ? 1UL : 0UL);
00968 }
00969 #endif /* SYSCFG_ITLINE11_SR_DMA2_CH2 */
00970
00971 #if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
00972 /**
00973   * @brief  Check if DMA2_CH3 interrupt occurred or not.
00974   * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3   LL_SYSCFG_IsActiveFlag_DMA2_CH3
00975   * @retval State of bit (1 or 0).
00976   */
00977 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
00978 {
00979   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)) ? 1UL : 0UL);
00980 }
00981 #endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
00982
00983 #if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
00984 /**
00985   * @brief  Check if DMA2_CH4 interrupt occurred or not.
00986   * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4   LL_SYSCFG_IsActiveFlag_DMA2_CH4
00987   * @retval State of bit (1 or 0).
00988   */
00989 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
00990 {
00991   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)) ? 1UL : 0UL);
00992 }
00993 #endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
00994
00995 #if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
00996 /**
00997   * @brief  Check if DMA2_CH5 interrupt occurred or not.
00998   * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5   LL_SYSCFG_IsActiveFlag_DMA2_CH5
00999   * @retval State of bit (1 or 0).
01000   */
01001 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
01002 {
01003   return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)) ? 1UL : 0UL);
01004 }
01005 #endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
01006
01007 #if defined(SYSCFG_ITLINE12_SR_ADC)
01008 /**
01009   * @brief  Check if ADC interrupt occurred or not.
01010   * @rmtoll SYSCFG_ITLINE12 SR_ADC        LL_SYSCFG_IsActiveFlag_ADC
01011   * @retval State of bit (1 or 0).
01012   */
01013 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
01014 {
01015   return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)) ? 1UL : 0UL);
01016 }
01017 #endif /* SYSCFG_ITLINE12_SR_ADC */
01018
01019 #if defined(SYSCFG_ITLINE12_SR_COMP1)
01020 /**
01021   * @brief  Check if Comparator 1 interrupt occurred or not (EXTI line 21).
01022   * @rmtoll SYSCFG_ITLINE12 SR_COMP1      LL_SYSCFG_IsActiveFlag_COMP1
01023   * @retval State of bit (1 or 0).
01024   */
01025 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
01026 {
01027   return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)) ? 1UL : 0UL);
01028 }
01029 #endif /* SYSCFG_ITLINE12_SR_COMP1 */
01030
01031 #if defined(SYSCFG_ITLINE12_SR_COMP2)
01032 /**
01033   * @brief  Check if Comparator 2 interrupt occurred or not (EXTI line 22).
01034   * @rmtoll SYSCFG_ITLINE12 SR_COMP2      LL_SYSCFG_IsActiveFlag_COMP2
01035   * @retval State of bit (1 or 0).
01036   */
01037 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
01038 {
01039   return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)) ? 1UL : 0UL);
01040 }
01041 #endif /* SYSCFG_ITLINE12_SR_COMP2 */
01042
01043 #if defined(SYSCFG_ITLINE12_SR_COMP3)
01044 /**
01045   * @brief  Check if Comparator 3 interrupt occurred or not (EXTI line 20).
01046   * @rmtoll SYSCFG_ITLINE12 SR_COMP3      LL_SYSCFG_IsActiveFlag_COMP3
01047   * @retval State of bit (1 or 0).
01048   */
01049 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP3(void)
01050 {
01051   return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP3) == (SYSCFG_ITLINE12_SR_COMP3)) ? 1UL : 0UL);
01052 }
01053 #endif /* SYSCFG_ITLINE12_SR_COMP3 */
01054
01055 #if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
01056 /**
01057   * @brief  Check if Timer 1 break interrupt occurred or not.
01058   * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK   LL_SYSCFG_IsActiveFlag_TIM1_BRK
01059   * @retval State of bit (1 or 0).
01060   */
01061 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
01062 {
01063   return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)) ? 1UL : 0UL);
01064 }
01065 #endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
01066
01067 #if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
01068 /**
01069   * @brief  Check if Timer 1 update interrupt occurred or not.
01070   * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD   LL_SYSCFG_IsActiveFlag_TIM1_UPD
01071   * @retval State of bit (1 or 0).
01072   */
01073 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
01074 {
01075   return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)) ? 1UL : 0UL);
01076 }
01077 #endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
01078
01079 #if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
01080 /**
01081   * @brief  Check if Timer 1 trigger interrupt occurred or not.
01082   * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG   LL_SYSCFG_IsActiveFlag_TIM1_TRG
01083   * @retval State of bit (1 or 0).
01084   */
01085 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
01086 {
01087   return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)) ? 1UL : 0UL);
01088 }
01089 #endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
01090
01091 #if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
01092 /**
01093   * @brief  Check if Timer 1 commutation interrupt occurred or not.
01094   * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU   LL_SYSCFG_IsActiveFlag_TIM1_CCU
01095   * @retval State of bit (1 or 0).
01096   */
01097 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
01098 {
01099   return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)) ? 1UL : 0UL);
01100 }
01101 #endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
01102
01103 #if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
01104 /**
01105   * @brief  Check if Timer 1 capture compare interrupt occurred or not.
01106   * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC    LL_SYSCFG_IsActiveFlag_TIM1_CC
01107   * @retval State of bit (1 or 0).
01108   */
01109 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
01110 {
01111   return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)) ? 1UL : 0UL);
01112 }
01113 #endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
01114
01115 #if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
01116 /**
01117   * @brief  Check if Timer 2 interrupt occurred or not.
01118   * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB   LL_SYSCFG_IsActiveFlag_TIM2
01119   * @retval State of bit (1 or 0).
01120   */
01121 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
01122 {
01123   return ((READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB)) ? 1UL : 0UL);
01124 }
01125 #endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
01126
01127 #if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
01128 /**
01129   * @brief  Check if Timer 3 interrupt occurred or not.
01130   * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB   LL_SYSCFG_IsActiveFlag_TIM3
01131   * @retval State of bit (1 or 0).
01132   */
01133 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
01134 {
01135   return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)) ? 1UL : 0UL);
01136 }
01137 #endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
01138
01139 #if defined(SYSCFG_ITLINE16_SR_TIM4_GLB)
01140 /**
01141   * @brief  Check if Timer 3 interrupt occurred or not.
01142   * @rmtoll SYSCFG_ITLINE16 SR_TIM4_GLB   LL_SYSCFG_IsActiveFlag_TIM4
01143   * @retval State of bit (1 or 0).
01144   */
01145 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM4(void)
01146 {
01147   return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM4_GLB) == (SYSCFG_ITLINE16_SR_TIM4_GLB)) ? 1UL : 0UL);
01148 }
01149 #endif /* SYSCFG_ITLINE16_SR_TIM4_GLB */
01150
01151 #if defined(SYSCFG_ITLINE17_SR_DAC)
01152 /**
01153   * @brief  Check if DAC underrun interrupt occurred or not.
01154   * @rmtoll SYSCFG_ITLINE17 SR_DAC        LL_SYSCFG_IsActiveFlag_DAC
01155   * @retval State of bit (1 or 0).
01156   */
01157 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
01158 {
01159   return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)) ? 1UL : 0UL);
01160 }
01161 #endif /* SYSCFG_ITLINE17_SR_DAC */
01162
01163 #if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
01164 /**
01165   * @brief  Check if Timer 6 interrupt occurred or not.
01166   * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB   LL_SYSCFG_IsActiveFlag_TIM6
01167   * @retval State of bit (1 or 0).
01168   */
01169 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
01170 {
01171   return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB)) ? 1UL : 0UL);
01172 }
01173 #endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
01174
01175 #if defined(SYSCFG_ITLINE17_SR_LPTIM1_GLB)
01176 /**
01177   * @brief  Check if LPTIM1 interrupt occurred or not.
01178   * @rmtoll SYSCFG_ITLINE17 SR_LPTIM1_GLB   LL_SYSCFG_IsActiveFlag_LPTIM1
01179   * @retval State of bit (1 or 0).
01180   */
01181 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM1(void)
01182 {
01183   return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_LPTIM1_GLB) == (SYSCFG_ITLINE17_SR_LPTIM1_GLB)) ? 1UL : 0UL);
01184 }
01185 #endif /* SYSCFG_ITLINE17_SR_LPTIM1_GLB */
01186
01187 #if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
01188 /**
01189   * @brief  Check if Timer 7 interrupt occurred or not.
01190   * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB   LL_SYSCFG_IsActiveFlag_TIM7
01191   * @retval State of bit (1 or 0).
01192   */
01193 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
01194 {
01195   return ((READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB)) ? 1UL : 0UL);
01196 }
01197 #endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
01198
01199 #if defined(SYSCFG_ITLINE18_SR_LPTIM2_GLB)
01200 /**
01201   * @brief  Check if LPTIM2 interrupt occurred or not.
01202   * @rmtoll SYSCFG_ITLINE18 SR_LPTIM2_GLB   LL_SYSCFG_IsActiveFlag_LPTIM2
01203   * @retval State of bit (1 or 0).
01204   */
01205 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM2(void)
01206 {
01207   return ((READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_LPTIM2_GLB) == (SYSCFG_ITLINE18_SR_LPTIM2_GLB)) ? 1UL : 0UL);
01208 }
01209 #endif /* SYSCFG_ITLINE18_SR_LPTIM2_GLB */
01210
01211 #if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
01212 /**
01213   * @brief  Check if Timer 14 interrupt occurred or not.
01214   * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB  LL_SYSCFG_IsActiveFlag_TIM14
01215   * @retval State of bit (1 or 0).
01216   */
01217 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
01218 {
01219   return ((READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)) ? 1UL : 0UL);
01220 }
01221 #endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
01222
01223 #if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
01224 /**
01225   * @brief  Check if Timer 15 interrupt occurred or not.
01226   * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB  LL_SYSCFG_IsActiveFlag_TIM15
01227   * @retval State of bit (1 or 0).
01228   */
01229 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
01230 {
01231   return ((READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB)) ? 1UL : 0UL);
01232 }
01233 #endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
01234
01235 #if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
01236 /**
01237   * @brief  Check if Timer 16 interrupt occurred or not.
01238   * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB  LL_SYSCFG_IsActiveFlag_TIM16
01239   * @retval State of bit (1 or 0).
01240   */
01241 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
01242 {
01243   return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)) ? 1UL : 0UL);
01244 }
01245 #endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
01246
01247 #if defined(SYSCFG_ITLINE21_SR_FDCAN1_IT0)
01248 /**
01249   * @brief  Check if FDCAN1_IT0 interrupt occurred or not.
01250   * @rmtoll SYSCFG_ITLINE21 SR_FDCAN1_IT0  LL_SYSCFG_IsActiveFlag_FDCAN1_IT0
01251   * @retval State of bit (1 or 0).
01252   */
01253 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT0(void)
01254 {
01255   return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_FDCAN1_IT0) == (SYSCFG_ITLINE21_SR_FDCAN1_IT0)) ? 1UL : 0UL);
01256 }
01257 #endif /* SYSCFG_ITLINE21_SR_FDCAN1_IT0 */
01258 #if defined(SYSCFG_ITLINE21_SR_FDCAN2_IT0)
01259 /**
01260   * @brief  Check if FDCAN2_IT0 interrupt occurred or not.
01261   * @rmtoll SYSCFG_ITLINE21 SR_FDCAN2_IT0  LL_SYSCFG_IsActiveFlag_FDCAN2_IT0
01262   * @retval State of bit (1 or 0).
01263   */
01264 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN2_IT0(void)
01265 {
01266   return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_FDCAN2_IT0) == (SYSCFG_ITLINE21_SR_FDCAN2_IT0)) ? 1UL : 0UL);
01267 }
01268 #endif /* SYSCFG_ITLINE21_SR_FDCAN2_IT0 */
01269
01270 #if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
01271 /**
01272   * @brief  Check if Timer 17 interrupt occurred or not.
01273   * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB  LL_SYSCFG_IsActiveFlag_TIM17
01274   * @retval State of bit (1 or 0).
01275   */
01276 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
01277 {
01278   return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)) ? 1UL : 0UL);
01279 }
01280 #endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
01281
01282 #if defined(SYSCFG_ITLINE22_SR_FDCAN1_IT1)
01283 /**
01284   * @brief  Check if FDCAN1_IT1 interrupt occurred or not.
01285   * @rmtoll SYSCFG_ITLINE22 SR_FDCAN1_IT1  LL_SYSCFG_IsActiveFlag_FDCAN1_IT1
01286   * @retval State of bit (1 or 0).
01287   */
01288 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT1(void)
01289 {
01290   return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_FDCAN1_IT1) == (SYSCFG_ITLINE22_SR_FDCAN1_IT1)) ? 1UL : 0UL);
01291 }
01292 #endif /* SYSCFG_ITLINE22_SR_FDCAN1_IT1 */
01293 #if defined(SYSCFG_ITLINE22_SR_FDCAN2_IT1)
01294 /**
01295   * @brief  Check if FDCAN2_IT1 interrupt occurred or not.
01296   * @rmtoll SYSCFG_ITLINE22 SR_FDCAN2_IT1  LL_SYSCFG_IsActiveFlag_FDCAN2_IT1
01297   * @retval State of bit (1 or 0).
01298   */
01299 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN2_IT1(void)
01300 {
01301   return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_FDCAN2_IT1) == (SYSCFG_ITLINE22_SR_FDCAN2_IT1)) ? 1UL : 0UL);
01302 }
01303 #endif /* SYSCFG_ITLINE22_SR_FDCAN2_IT1 */
01304
01305 #if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
01306 /**
01307   * @brief  Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
01308   * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB   LL_SYSCFG_IsActiveFlag_I2C1
01309   * @retval State of bit (1 or 0).
01310   */
01311 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
01312 {
01313   return ((READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)) ? 1UL : 0UL);
01314 }
01315 #endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
01316
01317 #if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
01318 /**
01319   * @brief  Check if I2C2 interrupt occurred or not.
01320   * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB   LL_SYSCFG_IsActiveFlag_I2C2
01321   * @retval State of bit (1 or 0).
01322   */
01323 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
01324 {
01325   return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)) ? 1UL : 0UL);
01326 }
01327 #endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
01328
01329 #if defined(SYSCFG_ITLINE24_SR_I2C3_GLB)
01330 /**
01331   * @brief  Check if I2C3 interrupt occurred or not.
01332   * @rmtoll SYSCFG_ITLINE24 SR_I2C3_GLB   LL_SYSCFG_IsActiveFlag_I2C3
01333   * @retval State of bit (1 or 0).
01334   */
01335 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C3(void)
01336 {
01337   return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C3_GLB) == (SYSCFG_ITLINE24_SR_I2C3_GLB)) ? 1UL : 0UL);
01338 }
01339 #endif /* SYSCFG_ITLINE24_SR_I2C3_GLB */
01340
01341 #if defined(SYSCFG_ITLINE25_SR_SPI1)
01342 /**
01343   * @brief  Check if SPI1 interrupt occurred or not.
01344   * @rmtoll SYSCFG_ITLINE25 SR_SPI1       LL_SYSCFG_IsActiveFlag_SPI1
01345   * @retval State of bit (1 or 0).
01346   */
01347 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
01348 {
01349   return ((READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)) ? 1UL : 0UL);
01350 }
01351 #endif /* SYSCFG_ITLINE25_SR_SPI1 */
01352
01353 #if defined(SYSCFG_ITLINE26_SR_SPI2)
01354 /**
01355   * @brief  Check if SPI2 interrupt occurred or not.
01356   * @rmtoll SYSCFG_ITLINE26 SR_SPI2       LL_SYSCFG_IsActiveFlag_SPI2
01357   * @retval State of bit (1 or 0).
01358   */
01359 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
01360 {
01361   return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)) ? 1UL : 0UL);
01362 }
01363 #endif /* SYSCFG_ITLINE26_SR_SPI2 */
01364
01365 #if defined(SYSCFG_ITLINE26_SR_SPI3)
01366 /**
01367   * @brief  Check if SPI3 interrupt occurred or not.
01368   * @rmtoll SYSCFG_ITLINE26 SR_SPI3       LL_SYSCFG_IsActiveFlag_SPI3
01369   * @retval State of bit (1 or 0).
01370   */
01371 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI3(void)
01372 {
01373   return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI3) == (SYSCFG_ITLINE26_SR_SPI3)) ? 1UL : 0UL);
01374 }
01375 #endif /* SYSCFG_ITLINE26_SR_SPI3 */
01376
01377 #if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
01378 /**
01379   * @brief  Check if USART1 interrupt occurred or not, combined with EXTI line 25.
01380   * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB  LL_SYSCFG_IsActiveFlag_USART1
01381   * @retval State of bit (1 or 0).
01382   */
01383 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
01384 {
01385   return ((READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)) ? 1UL : 0UL);
01386 }
01387 #endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
01388
01389 #if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
01390 /**
01391   * @brief  Check if USART2 interrupt occurred or not, combined with EXTI line 26.
01392   * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB  LL_SYSCFG_IsActiveFlag_USART2
01393   * @retval State of bit (1 or 0).
01394   */
01395 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
01396 {
01397   return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)) ? 1UL : 0UL);
01398 }
01399 #endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
01400
01401 #if defined(SYSCFG_ITLINE28_SR_LPUART2_GLB)
01402 /**
01403   * @brief  Check if LPUART2 interrupt occurred or not, combined with EXTI line 26.
01404   * @rmtoll SYSCFG_ITLINE28 SR_LPUART2_GLB  LL_SYSCFG_IsActiveFlag_LPUART2
01405   * @retval State of bit (1 or 0).
01406   */
01407 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART2(void)
01408 {
01409   return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_LPUART2_GLB) == (SYSCFG_ITLINE28_SR_LPUART2_GLB)) ? 1UL : 0UL);
01410 }
01411 #endif /* SYSCFG_ITLINE28_SR_LPUART2_GLB */
01412
01413 #if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
01414 /**
01415   * @brief  Check if USART3 interrupt occurred or not, combined with EXTI line 28.
01416   * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB  LL_SYSCFG_IsActiveFlag_USART3
01417   * @retval State of bit (1 or 0).
01418   */
01419 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
01420 {
01421   return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB)) ? 1UL : 0UL);
01422 }
01423 #endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
01424
01425 #if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
01426 /**
01427   * @brief  Check if USART4 interrupt occurred or not.
01428   * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB  LL_SYSCFG_IsActiveFlag_USART4
01429   * @retval State of bit (1 or 0).
01430   */
01431 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
01432 {
01433   return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB)) ? 1UL : 0UL);
01434 }
01435 #endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
01436
01437 #if defined(SYSCFG_ITLINE29_SR_LPUART1_GLB)
01438 /**
01439   * @brief  Check if LPUART1 interrupt occurred or not.
01440   * @rmtoll SYSCFG_ITLINE29 SR_LPUART1_GLB  LL_SYSCFG_IsActiveFlag_LPUART1
01441   * @retval State of bit (1 or 0).
01442   */
01443 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART1(void)
01444 {
01445   return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_LPUART1_GLB) == (SYSCFG_ITLINE29_SR_LPUART1_GLB)) ? 1UL : 0UL);
01446 }
01447 #endif /* SYSCFG_ITLINE29_SR_LPUART1_GLB */
01448
01449 #if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
01450 /**
01451   * @brief  Check if USART5 interrupt occurred or not.
01452   * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB  LL_SYSCFG_IsActiveFlag_USART5
01453   * @retval State of bit (1 or 0).
01454   */
01455 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
01456 {
01457   return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB)) ? 1UL : 0UL);
01458 }
01459 #endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
01460
01461 #if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
01462 /**
01463   * @brief  Check if USART6 interrupt occurred or not.
01464   * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB  LL_SYSCFG_IsActiveFlag_USART6
01465   * @retval State of bit (1 or 0).
01466   */
01467 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
01468 {
01469   return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB)) ? 1UL : 0UL);
01470 }
01471 #endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
01472
01473 #if defined(SYSCFG_ITLINE30_SR_CEC)
01474 /**
01475   * @brief  Check if CEC interrupt occurred or not, combined with EXTI line 27.
01476   * @rmtoll SYSCFG_ITLINE30 SR_CEC        LL_SYSCFG_IsActiveFlag_CEC
01477   * @retval State of bit (1 or 0).
01478   */
01479 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
01480 {
01481   return ((READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)) ? 1UL : 0UL);
01482 }
01483 #endif /* SYSCFG_ITLINE30_SR_CEC */
01484
01485 #if defined(SYSCFG_ITLINE31_SR_AES)
01486 /**
01487   * @brief  Check if AES interrupt occurred or not
01488   * @rmtoll SYSCFG_ITLINE31 SR_AES        LL_SYSCFG_IsActiveFlag_AES
01489   * @retval State of bit (1 or 0).
01490   */
01491 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_AES(void)
01492 {
01493   return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_AES) == (SYSCFG_ITLINE31_SR_AES)) ? 1UL : 0UL);
01494 }
01495 #endif /* SYSCFG_ITLINE31_SR_AES */
01496
01497 #if defined(SYSCFG_ITLINE31_SR_RNG)
01498 /**
01499   * @brief  Check if RNG interrupt occurred or not, combined with EXTI line 31.
01500   * @rmtoll SYSCFG_ITLINE31 SR_RNG        LL_SYSCFG_IsActiveFlag_RNG
01501   * @retval State of bit (1 or 0).
01502   */
01503 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RNG(void)
01504 {
01505   return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_RNG) == (SYSCFG_ITLINE31_SR_RNG)) ? 1UL : 0UL);
01506 }
01507 #endif /* SYSCFG_ITLINE31_SR_RNG */
01508
01509 /**
01510   * @brief  Set connections to TIM1/15/16/17 Break inputs
01511   * @rmtoll SYSCFG_CFGR2 CLL   LL_SYSCFG_SetTIMBreakInputs\n
01512   *         SYSCFG_CFGR2 SPL   LL_SYSCFG_SetTIMBreakInputs\n
01513   *         SYSCFG_CFGR2 PVDL  LL_SYSCFG_SetTIMBreakInputs\n
01514   *         SYSCFG_CFGR2 ECCL  LL_SYSCFG_GetTIMBreakInputs
01515   * @param  Break This parameter can be a combination of the following values:
01516   * @ifnot STM32G070xx
01517   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
01518   * @endif
01519   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
01520   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
01521   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
01522   *
01523   *         (*) value not defined in all devices
01524   * @retval None
01525   */
01526 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
01527 {
01528 #if defined(SYSCFG_CFGR2_PVDL)
01529   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
01530 #else
01531   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_ECCL, Break);
01532 #endif /*SYSCFG_CFGR2_PVDL*/
01533 }
01534
01535 /**
01536   * @brief  Get connections to TIM1/15/16/17 Break inputs
01537   * @rmtoll SYSCFG_CFGR2 CLL   LL_SYSCFG_GetTIMBreakInputs\n
01538   *         SYSCFG_CFGR2 SPL   LL_SYSCFG_GetTIMBreakInputs\n
01539   *         SYSCFG_CFGR2 PVDL  LL_SYSCFG_GetTIMBreakInputs\n
01540   *         SYSCFG_CFGR2 ECCL  LL_SYSCFG_GetTIMBreakInputs
01541   * @retval Returned value can be can be a combination of the following values:
01542   * @ifnot STM32G070xx
01543   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
01544   * @endif
01545   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
01546   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
01547   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
01548   *
01549   *         (*) value not defined in all devices
01550   */
01551 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
01552 {
01553 #if defined(SYSCFG_CFGR2_PVDL)
01554   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
01555 #else
01556   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_ECCL));
01557 #endif /*SYSCFG_CFGR2_PVDL*/
01558 }
01559
01560 /**
01561   * @brief  Check if SRAM parity error detected
01562   * @rmtoll SYSCFG_CFGR2 SPF      LL_SYSCFG_IsActiveFlag_SP
01563   * @retval State of bit (1 or 0).
01564   */
01565 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
01566 {
01567   return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
01568 }
01569
01570 /**
01571   * @brief  Clear SRAM parity error flag
01572   * @rmtoll SYSCFG_CFGR2 SPF      LL_SYSCFG_ClearFlag_SP
01573   * @retval None
01574   */
01575 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
01576 {
01577   SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
01578 }
01579
01580 #if defined(SYSCFG_CDEN_SUPPORT)
01581 /**
01582   * @brief  Enable Clamping Diode on specific pin
01583   * @rmtoll SYSCFG_CFGR2 PA1_CDEN   LL_SYSCFG_EnableClampingDiode\n
01584   *         SYSCFG_CFGR2 PA3_CDEN   LL_SYSCFG_EnableClampingDiode\n
01585   *         SYSCFG_CFGR2 PA5_CDEN   LL_SYSCFG_EnableClampingDiode\n
01586   *         SYSCFG_CFGR2 PA6_CDEN   LL_SYSCFG_EnableClampingDiode\n
01587   *         SYSCFG_CFGR2 PA13_CDEN  LL_SYSCFG_EnableClampingDiode\n
01588   *         SYSCFG_CFGR2 PB0_CDEN   LL_SYSCFG_EnableClampingDiode\n
01589   *         SYSCFG_CFGR2 PB1_CDEN   LL_SYSCFG_EnableClampingDiode\n
01590   *         SYSCFG_CFGR1 PB2_CDEN   LL_SYSCFG_EnableClampingDiode
01591   * @param  ConfigClampingDiode This parameter can be a combination of the following values:
01592   *         @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
01593   *         @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
01594   *         @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
01595   *         @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
01596   *         @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
01597   *         @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
01598   *         @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
01599   *         @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
01600   * @retval None
01601   */
01602 __STATIC_INLINE void LL_SYSCFG_EnableClampingDiode(uint32_t ConfigClampingDiode)
01603 {
01604   SET_BIT(SYSCFG->CFGR2, ConfigClampingDiode);
01605 }
01606
01607 /**
01608   * @brief  Disable Clamping Diode on specific pin
01609   * @rmtoll SYSCFG_CFGR2 PA1_CDEN   LL_SYSCFG_DisableClampingDiode\n
01610   *         SYSCFG_CFGR2 PA3_CDEN   LL_SYSCFG_DisableClampingDiode\n
01611   *         SYSCFG_CFGR2 PA5_CDEN   LL_SYSCFG_DisableClampingDiode\n
01612   *         SYSCFG_CFGR2 PA6_CDEN   LL_SYSCFG_DisableClampingDiode\n
01613   *         SYSCFG_CFGR2 PA13_CDEN  LL_SYSCFG_DisableClampingDiode\n
01614   *         SYSCFG_CFGR2 PB0_CDEN   LL_SYSCFG_DisableClampingDiode\n
01615   *         SYSCFG_CFGR2 PB1_CDEN   LL_SYSCFG_DisableClampingDiode\n
01616   *         SYSCFG_CFGR1 PB2_CDEN   LL_SYSCFG_DisableClampingDiode
01617   * @param  ConfigClampingDiode This parameter can be a combination of the following values:
01618   *         @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
01619   *         @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
01620   *         @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
01621   *         @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
01622   *         @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
01623   *         @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
01624   *         @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
01625   *         @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
01626   * @retval None
01627   */
01628 __STATIC_INLINE void LL_SYSCFG_DisableClampingDiode(uint32_t ConfigClampingDiode)
01629 {
01630   CLEAR_BIT(SYSCFG->CFGR2, ConfigClampingDiode);
01631 }
01632 /**
01633   * @brief  Indicates whether clamping diode(s) is(are) enabled.
01634   * @rmtoll SYSCFG_CFGR2 PA1_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
01635   *         SYSCFG_CFGR2 PA3_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
01636   *         SYSCFG_CFGR2 PA5_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
01637   *         SYSCFG_CFGR2 PA6_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
01638   *         SYSCFG_CFGR2 PA13_CDEN  LL_SYSCFG_IsEnabledClampingDiode\n
01639   *         SYSCFG_CFGR2 PB0_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
01640   *         SYSCFG_CFGR2 PB1_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
01641   *         SYSCFG_CFGR1 PB2_CDEN   LL_SYSCFG_IsEnabledClampingDiode
01642   * @param  ConfigClampingDiode This parameter can be a combination of the following values:
01643   *         @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
01644   *         @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
01645   *         @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
01646   *         @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
01647   *         @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
01648   *         @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
01649   *         @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
01650   *         @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
01651   * @retval None
01652   */
01653 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledClampingDiode(uint32_t ConfigClampingDiode)
01654 {
01655   return ((READ_BIT(SYSCFG->CFGR2, ConfigClampingDiode) == (ConfigClampingDiode)) ? 1UL : 0UL);
01656 }
01657 #endif /* SYSCFG_CDEN_SUPPORT */
01658
01659 /**
01660   * @}
01661   */
01662
01663 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
01664   * @{
01665   */
01666
01667 /**
01668   * @brief  Return the device identifier
01669   * @note For STM32G081xx devices, the device ID is 0x460
01670   * @rmtoll DBG_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
01671   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
01672   */
01673 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
01674 {
01675   return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_DEV_ID));
01676 }
01677
01678 /**
01679   * @brief  Return the device revision identifier
01680   * @note This field indicates the revision of the device.
01681   * @rmtoll DBG_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
01682   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
01683   */
01684 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
01685 {
01686   return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_REV_ID) >> DBG_IDCODE_REV_ID_Pos);
01687 }
01688
01689 /**
01690   * @brief  Enable the Debug Module during STOP mode
01691   * @rmtoll DBG_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
01692   * @retval None
01693   */
01694 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
01695 {
01696   SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
01697 }
01698
01699 /**
01700   * @brief  Disable the Debug Module during STOP mode
01701   * @rmtoll DBG_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
01702   * @retval None
01703   */
01704 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
01705 {
01706   CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
01707 }
01708
01709 /**
01710   * @brief  Enable the Debug Module during STANDBY mode
01711   * @rmtoll DBG_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
01712   * @retval None
01713   */
01714 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
01715 {
01716   SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
01717 }
01718
01719 /**
01720   * @brief  Disable the Debug Module during STANDBY mode
01721   * @rmtoll DBG_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
01722   * @retval None
01723   */
01724 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
01725 {
01726   CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
01727 }
01728
01729 /**
01730   * @brief  Freeze APB1 peripherals (group1 peripherals)
01731   * @rmtoll DBG_APB_FZ1 DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01732   *         DBG_APB_FZ1 DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01733   *         DBG_APB_FZ1 DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01734   *         DBG_APB_FZ1 DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01735   *         DBG_APB_FZ1 DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01736   *         DBG_APB_FZ1 DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01737   *         DBG_APB_FZ1 DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01738   *         DBG_APB_FZ1 DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01739   *         DBG_APB_FZ1 DBG_I2C1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01740   *         DBG_APB_FZ1 DBG_I2C2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01741   *         DBG_APB_FZ1 DBG_LPTIM2_STOP         LL_DBGMCU_APB1_GRP1_FreezePeriph\n
01742   *         DBG_APB_FZ1 DBG_LPTIM1_STOP         LL_DBGMCU_APB1_GRP1_FreezePeriph
01743   * @param  Periphs This parameter can be a combination of the following values:
01744   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
01745   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
01746   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
01747   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
01748   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
01749   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01750   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01751   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01752   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01753   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
01754   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM2_STOP (*)
01755   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP (*)
01756   *
01757   *         (*) value not defined in all devices
01758   * @retval None
01759   */
01760 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
01761 {
01762   SET_BIT(DBG->APBFZ1, Periphs);
01763 }
01764
01765 /**
01766   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
01767   * @rmtoll DBG_APB_FZ1 DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01768   *         DBG_APB_FZ1 DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01769   *         DBG_APB_FZ1 DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01770   *         DBG_APB_FZ1 DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01771   *         DBG_APB_FZ1 DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01772   *         DBG_APB_FZ1 DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01773   *         DBG_APB_FZ1 DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01774   *         DBG_APB_FZ1 DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01775   *         DBG_APB_FZ1 DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01776   *         DBG_APB_FZ1 DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01777   *         DBG_APB_FZ1 DBG_LPTIM2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
01778   *         DBG_APB_FZ1 DBG_LPTIM1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
01779   * @param  Periphs This parameter can be a combination of the following values:
01780   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
01781   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
01782   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
01783   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
01784   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
01785   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01786   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01787   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01788   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01789   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
01790   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM2_STOP (*)
01791   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP (*)
01792   *
01793   *         (*) value not defined in all devices
01794   * @retval None
01795   */
01796 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
01797 {
01798   CLEAR_BIT(DBG->APBFZ1, Periphs);
01799 }
01800
01801 /**
01802   * @brief  Freeze APB2 peripherals
01803   * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01804   *         DBG_APB_FZ2 DBG_TIM14_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01805   *         DBG_APB_FZ2 DBG_TIM15_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01806   *         DBG_APB_FZ2 DBG_TIM16_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
01807   *         DBG_APB_FZ2 DBG_TIM17_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
01808   * @param  Periphs This parameter can be a combination of the following values:
01809   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01810   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM14_STOP
01811   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
01812   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01813   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
01814   *
01815   *         (*) value not defined in all devices
01816   * @retval None
01817   */
01818 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
01819 {
01820   SET_BIT(DBG->APBFZ2, Periphs);
01821 }
01822
01823 /**
01824   * @brief  Unfreeze APB2 peripherals
01825   * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01826   *         DBG_APB_FZ2 DBG_TIM14_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01827   *         DBG_APB_FZ2 DBG_TIM15_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01828   *         DBG_APB_FZ2 DBG_TIM16_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
01829   *         DBG_APB_FZ2 DBG_TIM17_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
01830   * @param  Periphs This parameter can be a combination of the following values:
01831   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01832   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM14_STOP
01833   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
01834   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01835   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
01836   *
01837   *         (*) value not defined in all devices
01838   * @retval None
01839   */
01840 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
01841 {
01842   CLEAR_BIT(DBG->APBFZ2, Periphs);
01843 }
01844 /**
01845   * @}
01846   */
01847
01848 #if defined(VREFBUF)
01849 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
01850   * @{
01851   */
01852
01853 /**
01854   * @brief  Enable Internal voltage reference
01855   * @rmtoll VREFBUF_CSR  VREFBUF_CSR_ENVR          LL_VREFBUF_Enable
01856   * @retval None
01857   */
01858 __STATIC_INLINE void LL_VREFBUF_Enable(void)
01859 {
01860   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01861 }
01862
01863 /**
01864   * @brief  Disable Internal voltage reference
01865   * @rmtoll VREFBUF_CSR  VREFBUF_CSR_ENVR          LL_VREFBUF_Disable
01866   * @retval None
01867   */
01868 __STATIC_INLINE void LL_VREFBUF_Disable(void)
01869 {
01870   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01871 }
01872
01873 /**
01874   * @brief  Enable high impedance (VREF+pin is high impedance)
01875   * @rmtoll VREFBUF_CSR  VREFBUF_CSR_HIZ           LL_VREFBUF_EnableHIZ
01876   * @retval None
01877   */
01878 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
01879 {
01880   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01881 }
01882
01883 /**
01884   * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
01885   * @rmtoll VREFBUF_CSR  VREFBUF_CSR_HIZ           LL_VREFBUF_DisableHIZ
01886   * @retval None
01887   */
01888 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
01889 {
01890   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01891 }
01892
01893 /**
01894   * @brief  Set the Voltage reference scale
01895   * @rmtoll VREFBUF_CSR  VREFBUF_CSR_VRS           LL_VREFBUF_SetVoltageScaling
01896   * @param  Scale This parameter can be one of the following values:
01897   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01898   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01899   * @retval None
01900   */
01901 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
01902 {
01903   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
01904 }
01905
01906 /**
01907   * @brief  Get the Voltage reference scale
01908   * @rmtoll VREFBUF_CSR  VREFBUF_CSR_VRS           LL_VREFBUF_GetVoltageScaling
01909   * @retval Returned value can be one of the following values:
01910   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01911   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01912   */
01913 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
01914 {
01915   return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
01916 }
01917
01918 /**
01919   * @brief  Check if Voltage reference buffer is ready
01920   * @rmtoll VREFBUF_CSR  VREFBUF_CSR_VRS           LL_VREFBUF_IsVREFReady
01921   * @retval State of bit (1 or 0).
01922   */
01923 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
01924 {
01925   return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
01926 }
01927
01928 /**
01929   * @brief  Get the trimming code for VREFBUF calibration
01930   * @rmtoll VREFBUF_CCR  VREFBUF_CCR_TRIM          LL_VREFBUF_GetTrimming
01931   * @retval Between 0 and 0x3F
01932   */
01933 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
01934 {
01935   return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
01936 }
01937
01938 /**
01939   * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
01940   * @note   VrefBuf voltage scale is calibrated in production for each device,
01941   *         using voltage scale 1. This calibration value is loaded
01942   *         as default trimming value at device power up.
01943   *         This trimming value can be fine tuned for voltage scales 0 and 1
01944   *         using this function.
01945   * @rmtoll VREFBUF_CCR  VREFBUF_CCR_TRIM          LL_VREFBUF_SetTrimming
01946   * @param  Value Between 0 and 0x3F
01947   * @retval None
01948   */
01949 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
01950 {
01951   WRITE_REG(VREFBUF->CCR, Value);
01952 }
01953
01954 /**
01955   * @}
01956   */
01957 #endif /* VREFBUF */
01958
01959 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
01960   * @{
01961   */
01962
01963 /**
01964   * @brief  Set FLASH Latency
01965   * @rmtoll FLASH_ACR    FLASH_ACR_LATENCY       LL_FLASH_SetLatency
01966   * @param  Latency This parameter can be one of the following values:
01967   *         @arg @ref LL_FLASH_LATENCY_0
01968   *         @arg @ref LL_FLASH_LATENCY_1
01969   *         @arg @ref LL_FLASH_LATENCY_2
01970   * @retval None
01971   */
01972 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
01973 {
01974   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
01975 }
01976
01977 /**
01978   * @brief  Get FLASH Latency
01979   * @rmtoll FLASH_ACR    FLASH_ACR_LATENCY       LL_FLASH_GetLatency
01980   * @retval Returned value can be one of the following values:
01981   *         @arg @ref LL_FLASH_LATENCY_0
01982   *         @arg @ref LL_FLASH_LATENCY_1
01983   *         @arg @ref LL_FLASH_LATENCY_2
01984   */
01985 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
01986 {
01987   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
01988 }
01989
01990 /**
01991   * @brief  Enable Prefetch
01992   * @rmtoll FLASH_ACR    FLASH_ACR_PRFTEN        LL_FLASH_EnablePrefetch
01993   * @retval None
01994   */
01995 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
01996 {
01997   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01998 }
01999
02000 /**
02001   * @brief  Disable Prefetch
02002   * @rmtoll FLASH_ACR    FLASH_ACR_PRFTEN        LL_FLASH_DisablePrefetch
02003   * @retval None
02004   */
02005 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
02006 {
02007   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
02008 }
02009
02010 /**
02011   * @brief  Check if Prefetch buffer is enabled
02012   * @rmtoll FLASH_ACR    FLASH_ACR_PRFTEN        LL_FLASH_IsPrefetchEnabled
02013   * @retval State of bit (1 or 0).
02014   */
02015 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
02016 {
02017   return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
02018 }
02019
02020 /**
02021   * @brief  Enable Instruction cache
02022   * @rmtoll FLASH_ACR    FLASH_ACR_ICEN          LL_FLASH_EnableInstCache
02023   * @retval None
02024   */
02025 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
02026 {
02027   SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
02028 }
02029
02030 /**
02031   * @brief  Disable Instruction cache
02032   * @rmtoll FLASH_ACR    FLASH_ACR_ICEN          LL_FLASH_DisableInstCache
02033   * @retval None
02034   */
02035 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
02036 {
02037   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
02038 }
02039
02040 /**
02041   * @brief  Enable Instruction cache reset
02042   * @note  bit can be written only when the instruction cache is disabled
02043   * @rmtoll FLASH_ACR    FLASH_ACR_ICRST         LL_FLASH_EnableInstCacheReset
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
02047 {
02048   SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
02049 }
02050
02051 /**
02052   * @brief  Disable Instruction cache reset
02053   * @rmtoll FLASH_ACR    FLASH_ACR_ICRST         LL_FLASH_DisableInstCacheReset
02054   * @retval None
02055   */
02056 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
02057 {
02058   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
02059 }
02060
02061 /**
02062   * @}
02063   */
02064
02065 /**
02066   * @}
02067   */
02068
02069 /**
02070   * @}
02071   */
02072
02073 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBG) */
02074
02075 /**
02076   * @}
02077   */
02078
02079 #ifdef __cplusplus
02080 }
02081 #endif
02082
02083 #endif /* STM32G0xx_LL_SYSTEM_H */
02084
02085
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_tim.c Source File

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stm32g0xx_ll_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_tim.h"
00022 #include "stm32g0xx_ll_bus.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) ||  defined (TIM14) ||  defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
00035
00036 /** @addtogroup TIM_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup TIM_LL_Private_Macros
00045   * @{
00046   */
00047 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
00048                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
00049                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
00050                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
00051                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
00052
00053 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
00054                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
00055                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
00056
00057 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
00058                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
00059                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
00060                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
00061                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
00062                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
00063                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
00064                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
00065                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
00066                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
00067                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
00068                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
00069                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
00070                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
00071
00072 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
00073                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
00074
00075 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
00076                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
00077
00078 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
00079                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
00080
00081 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
00082                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
00083                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
00084
00085 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
00086                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
00087                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
00088                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
00089
00090 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
00091                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
00092                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
00093                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
00094                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
00095                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
00096                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
00097                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
00098                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
00099                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
00100                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
00101                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
00102                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
00103                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
00104                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
00105                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
00106
00107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00108                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
00109                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
00110
00111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
00112                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
00113                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
00114
00115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00116                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
00117
00118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
00119                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
00120
00121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
00122                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
00123
00124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
00125                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
00126                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
00127                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
00128
00129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
00130                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
00131
00132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
00133                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
00134
00135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
00136                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
00137                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
00138                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
00139                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
00140                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
00141                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
00142                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
00143                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
00144                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
00145                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
00146                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
00147                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
00148                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
00149                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
00150                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
00151
00152 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
00153                                            || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
00154
00155 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
00156                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
00157
00158 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
00159                                               || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
00160
00161 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
00162                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
00163                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
00164                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
00165                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
00166                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
00167                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
00168                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
00169                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
00170                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
00171                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
00172                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
00173                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
00174                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
00175                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
00176                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
00177
00178 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
00179                                             || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
00180
00181 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
00182                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
00183 /**
00184   * @}
00185   */
00186
00187
00188 /* Private function prototypes -----------------------------------------------*/
00189 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
00190   * @{
00191   */
00192 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00193 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00194 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00195 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00196 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00197 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00198 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00199 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00200 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00201 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00202 /**
00203   * @}
00204   */
00205
00206 /* Exported functions --------------------------------------------------------*/
00207 /** @addtogroup TIM_LL_Exported_Functions
00208   * @{
00209   */
00210
00211 /** @addtogroup TIM_LL_EF_Init
00212   * @{
00213   */
00214
00215 /**
00216   * @brief  Set TIMx registers to their reset values.
00217   * @param  TIMx Timer instance
00218   * @retval An ErrorStatus enumeration value:
00219   *          - SUCCESS: TIMx registers are de-initialized
00220   *          - ERROR: invalid TIMx instance
00221   */
00222 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
00223 {
00224   ErrorStatus result = SUCCESS;
00225
00226   /* Check the parameters */
00227   assert_param(IS_TIM_INSTANCE(TIMx));
00228
00229   if (TIMx == TIM1)
00230   {
00231     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
00232     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
00233   }
00234 #if defined(TIM2)
00235   else if (TIMx == TIM2)
00236   {
00237     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
00238     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
00239   }
00240 #endif /* TIM2 */
00241 #if defined(TIM3)
00242   else if (TIMx == TIM3)
00243   {
00244     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
00245     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
00246   }
00247 #endif /* TIM3 */
00248 #if defined(TIM4)
00249   else if (TIMx == TIM4)
00250   {
00251     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
00252     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
00253   }
00254 #endif /* TIM4 */
00255 #if defined(TIM6)
00256   else if (TIMx == TIM6)
00257   {
00258     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
00259     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
00260   }
00261 #endif /* TIM6 */
00262 #if defined(TIM7)
00263   else if (TIMx == TIM7)
00264   {
00265     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
00266     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
00267   }
00268 #endif /* TIM7 */
00269   else if (TIMx == TIM14)
00270   {
00271     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14);
00272     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM14);
00273   }
00274 #if defined(TIM15)
00275   else if (TIMx == TIM15)
00276   {
00277     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
00278     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
00279   }
00280 #endif /* TIM15 */
00281   else if (TIMx == TIM16)
00282   {
00283     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
00284     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
00285   }
00286 #if defined(TIM17)
00287   else if (TIMx == TIM17)
00288   {
00289     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
00290     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
00291   }
00292 #endif /* TIM17 */
00293   else
00294   {
00295     result = ERROR;
00296   }
00297
00298   return result;
00299 }
00300
00301 /**
00302   * @brief  Set the fields of the time base unit configuration data structure
00303   *         to their default values.
00304   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
00305   * @retval None
00306   */
00307 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
00308 {
00309   /* Set the default configuration */
00310   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
00311   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
00312   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
00313   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
00314   TIM_InitStruct->RepetitionCounter = 0x00000000U;
00315 }
00316
00317 /**
00318   * @brief  Configure the TIMx time base unit.
00319   * @param  TIMx Timer Instance
00320   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
00321   *         (TIMx time base unit configuration data structure)
00322   * @retval An ErrorStatus enumeration value:
00323   *          - SUCCESS: TIMx registers are de-initialized
00324   *          - ERROR: not applicable
00325   */
00326 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
00327 {
00328   uint32_t tmpcr1;
00329
00330   /* Check the parameters */
00331   assert_param(IS_TIM_INSTANCE(TIMx));
00332   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
00333   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
00334
00335   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
00336
00337   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
00338   {
00339     /* Select the Counter Mode */
00340     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
00341   }
00342
00343   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
00344   {
00345     /* Set the clock division */
00346     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
00347   }
00348
00349   /* Write to TIMx CR1 */
00350   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
00351
00352   /* Set the Autoreload value */
00353   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
00354
00355   /* Set the Prescaler value */
00356   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
00357
00358   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
00359   {
00360     /* Set the Repetition Counter value */
00361     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
00362   }
00363
00364   /* Generate an update event to reload the Prescaler
00365      and the repetition counter value (if applicable) immediately */
00366   LL_TIM_GenerateEvent_UPDATE(TIMx);
00367
00368   return SUCCESS;
00369 }
00370
00371 /**
00372   * @brief  Set the fields of the TIMx output channel configuration data
00373   *         structure to their default values.
00374   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
00375   *         (the output channel configuration data structure)
00376   * @retval None
00377   */
00378 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00379 {
00380   /* Set the default configuration */
00381   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
00382   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
00383   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
00384   TIM_OC_InitStruct->CompareValue = 0x00000000U;
00385   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
00386   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
00387   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
00388   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
00389 }
00390
00391 /**
00392   * @brief  Configure the TIMx output channel.
00393   * @param  TIMx Timer Instance
00394   * @param  Channel This parameter can be one of the following values:
00395   *         @arg @ref LL_TIM_CHANNEL_CH1
00396   *         @arg @ref LL_TIM_CHANNEL_CH2
00397   *         @arg @ref LL_TIM_CHANNEL_CH3
00398   *         @arg @ref LL_TIM_CHANNEL_CH4
00399   *         @arg @ref LL_TIM_CHANNEL_CH5
00400   *         @arg @ref LL_TIM_CHANNEL_CH6
00401   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
00402   *         data structure)
00403   * @retval An ErrorStatus enumeration value:
00404   *          - SUCCESS: TIMx output channel is initialized
00405   *          - ERROR: TIMx output channel is not initialized
00406   */
00407 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00408 {
00409   ErrorStatus result = ERROR;
00410
00411   switch (Channel)
00412   {
00413     case LL_TIM_CHANNEL_CH1:
00414       result = OC1Config(TIMx, TIM_OC_InitStruct);
00415       break;
00416     case LL_TIM_CHANNEL_CH2:
00417       result = OC2Config(TIMx, TIM_OC_InitStruct);
00418       break;
00419     case LL_TIM_CHANNEL_CH3:
00420       result = OC3Config(TIMx, TIM_OC_InitStruct);
00421       break;
00422     case LL_TIM_CHANNEL_CH4:
00423       result = OC4Config(TIMx, TIM_OC_InitStruct);
00424       break;
00425     case LL_TIM_CHANNEL_CH5:
00426       result = OC5Config(TIMx, TIM_OC_InitStruct);
00427       break;
00428     case LL_TIM_CHANNEL_CH6:
00429       result = OC6Config(TIMx, TIM_OC_InitStruct);
00430       break;
00431     default:
00432       break;
00433   }
00434
00435   return result;
00436 }
00437
00438 /**
00439   * @brief  Set the fields of the TIMx input channel configuration data
00440   *         structure to their default values.
00441   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
00442   *         data structure)
00443   * @retval None
00444   */
00445 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
00446 {
00447   /* Set the default configuration */
00448   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
00449   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00450   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
00451   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
00452 }
00453
00454 /**
00455   * @brief  Configure the TIMx input channel.
00456   * @param  TIMx Timer Instance
00457   * @param  Channel This parameter can be one of the following values:
00458   *         @arg @ref LL_TIM_CHANNEL_CH1
00459   *         @arg @ref LL_TIM_CHANNEL_CH2
00460   *         @arg @ref LL_TIM_CHANNEL_CH3
00461   *         @arg @ref LL_TIM_CHANNEL_CH4
00462   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
00463   *         structure)
00464   * @retval An ErrorStatus enumeration value:
00465   *          - SUCCESS: TIMx output channel is initialized
00466   *          - ERROR: TIMx output channel is not initialized
00467   */
00468 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
00469 {
00470   ErrorStatus result = ERROR;
00471
00472   switch (Channel)
00473   {
00474     case LL_TIM_CHANNEL_CH1:
00475       result = IC1Config(TIMx, TIM_IC_InitStruct);
00476       break;
00477     case LL_TIM_CHANNEL_CH2:
00478       result = IC2Config(TIMx, TIM_IC_InitStruct);
00479       break;
00480     case LL_TIM_CHANNEL_CH3:
00481       result = IC3Config(TIMx, TIM_IC_InitStruct);
00482       break;
00483     case LL_TIM_CHANNEL_CH4:
00484       result = IC4Config(TIMx, TIM_IC_InitStruct);
00485       break;
00486     default:
00487       break;
00488   }
00489
00490   return result;
00491 }
00492
00493 /**
00494   * @brief  Fills each TIM_EncoderInitStruct field with its default value
00495   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
00496   *         configuration data structure)
00497   * @retval None
00498   */
00499 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00500 {
00501   /* Set the default configuration */
00502   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
00503   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
00504   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00505   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
00506   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
00507   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
00508   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00509   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
00510   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
00511 }
00512
00513 /**
00514   * @brief  Configure the encoder interface of the timer instance.
00515   * @param  TIMx Timer Instance
00516   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
00517   *         configuration data structure)
00518   * @retval An ErrorStatus enumeration value:
00519   *          - SUCCESS: TIMx registers are de-initialized
00520   *          - ERROR: not applicable
00521   */
00522 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00523 {
00524   uint32_t tmpccmr1;
00525   uint32_t tmpccer;
00526
00527   /* Check the parameters */
00528   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
00529   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
00530   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
00531   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
00532   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
00533   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
00534   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
00535   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
00536   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
00537   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
00538
00539   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00540   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00541
00542   /* Get the TIMx CCMR1 register value */
00543   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00544
00545   /* Get the TIMx CCER register value */
00546   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00547
00548   /* Configure TI1 */
00549   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00550   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
00551   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
00552   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
00553
00554   /* Configure TI2 */
00555   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
00556   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
00557   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
00558   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
00559
00560   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
00561   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00562   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
00563   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
00564   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00565
00566   /* Set encoder mode */
00567   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
00568
00569   /* Write to TIMx CCMR1 */
00570   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00571
00572   /* Write to TIMx CCER */
00573   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00574
00575   return SUCCESS;
00576 }
00577
00578 /**
00579   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
00580   *         structure to their default values.
00581   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
00582   *         configuration data structure)
00583   * @retval None
00584   */
00585 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00586 {
00587   /* Set the default configuration */
00588   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
00589   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
00590   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
00591   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
00592 }
00593
00594 /**
00595   * @brief  Configure the Hall sensor interface of the timer instance.
00596   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
00597   *       to the TI1 input channel
00598   * @note TIMx slave mode controller is configured in reset mode.
00599           Selected internal trigger is TI1F_ED.
00600   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
00601   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
00602   *       between 2 changes on the inputs. It gives information about motor speed.
00603   * @note Channel 2 is configured in output PWM 2 mode.
00604   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
00605   * @note OC2REF is selected as trigger output on TRGO.
00606   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
00607   *       when TIMx operates in Hall sensor interface mode.
00608   * @param  TIMx Timer Instance
00609   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
00610   *         interface configuration data structure)
00611   * @retval An ErrorStatus enumeration value:
00612   *          - SUCCESS: TIMx registers are de-initialized
00613   *          - ERROR: not applicable
00614   */
00615 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00616 {
00617   uint32_t tmpcr2;
00618   uint32_t tmpccmr1;
00619   uint32_t tmpccer;
00620   uint32_t tmpsmcr;
00621
00622   /* Check the parameters */
00623   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
00624   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
00625   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
00626   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
00627
00628   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00629   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00630
00631   /* Get the TIMx CR2 register value */
00632   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00633
00634   /* Get the TIMx CCMR1 register value */
00635   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00636
00637   /* Get the TIMx CCER register value */
00638   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00639
00640   /* Get the TIMx SMCR register value */
00641   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
00642
00643   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
00644   tmpcr2 |= TIM_CR2_TI1S;
00645
00646   /* OC2REF signal is used as trigger output (TRGO) */
00647   tmpcr2 |= LL_TIM_TRGO_OC2REF;
00648
00649   /* Configure the slave mode controller */
00650   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
00651   tmpsmcr |= LL_TIM_TS_TI1F_ED;
00652   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
00653
00654   /* Configure input channel 1 */
00655   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00656   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
00657   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
00658   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
00659
00660   /* Configure input channel 2 */
00661   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
00662   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
00663
00664   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
00665   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00666   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
00667   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00668
00669   /* Write to TIMx CR2 */
00670   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00671
00672   /* Write to TIMx SMCR */
00673   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
00674
00675   /* Write to TIMx CCMR1 */
00676   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00677
00678   /* Write to TIMx CCER */
00679   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00680
00681   /* Write to TIMx CCR2 */
00682   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
00683
00684   return SUCCESS;
00685 }
00686
00687 /**
00688   * @brief  Set the fields of the Break and Dead Time configuration data structure
00689   *         to their default values.
00690   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
00691   *         data structure)
00692   * @retval None
00693   */
00694 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00695 {
00696   /* Set the default configuration */
00697   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
00698   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
00699   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
00700   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
00701   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
00702   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
00703   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
00704   TIM_BDTRInitStruct->BreakAFMode     = LL_TIM_BREAK_AFMODE_INPUT;
00705   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
00706   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
00707   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
00708   TIM_BDTRInitStruct->Break2AFMode    = LL_TIM_BREAK2_AFMODE_INPUT;
00709   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
00710 }
00711
00712 /**
00713   * @brief  Configure the Break and Dead Time feature of the timer instance.
00714   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
00715   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
00716   *  can be necessary to configure all of them during the first write access to
00717   *  the TIMx_BDTR register.
00718   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
00719   *       a timer instance provides a break input.
00720   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
00721   *       a timer instance provides a second break input.
00722   * @param  TIMx Timer Instance
00723   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
00724   *         data structure)
00725   * @retval An ErrorStatus enumeration value:
00726   *          - SUCCESS: Break and Dead Time is initialized
00727   *          - ERROR: not applicable
00728   */
00729 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00730 {
00731   uint32_t tmpbdtr = 0;
00732
00733   /* Check the parameters */
00734   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
00735   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
00736   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
00737   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
00738   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
00739   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
00740   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
00741
00742   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
00743   the OSSI State, the dead time value and the Automatic Output Enable Bit */
00744
00745   /* Set the BDTR bits */
00746   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
00747   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
00748   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
00749   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
00750   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
00751   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
00752   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
00753   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
00754   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
00755   {
00756     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
00757     assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
00758     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
00759     MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
00760   }
00761
00762   if (IS_TIM_BKIN2_INSTANCE(TIMx))
00763   {
00764     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
00765     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
00766     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
00767     assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
00768
00769     /* Set the BREAK2 input related BDTR bit-fields */
00770     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
00771     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
00772     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
00773     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
00774   }
00775
00776   /* Set TIMx_BDTR */
00777   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
00778
00779   return SUCCESS;
00780 }
00781 /**
00782   * @}
00783   */
00784
00785 /**
00786   * @}
00787   */
00788
00789 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
00790   *  @brief   Private functions
00791   * @{
00792   */
00793 /**
00794   * @brief  Configure the TIMx output channel 1.
00795   * @param  TIMx Timer Instance
00796   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
00797   * @retval An ErrorStatus enumeration value:
00798   *          - SUCCESS: TIMx registers are de-initialized
00799   *          - ERROR: not applicable
00800   */
00801 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00802 {
00803   uint32_t tmpccmr1;
00804   uint32_t tmpccer;
00805   uint32_t tmpcr2;
00806
00807   /* Check the parameters */
00808   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
00809   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00810   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00811   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00812   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00813   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00814
00815   /* Disable the Channel 1: Reset the CC1E Bit */
00816   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
00817
00818   /* Get the TIMx CCER register value */
00819   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00820
00821   /* Get the TIMx CR2 register value */
00822   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00823
00824   /* Get the TIMx CCMR1 register value */
00825   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00826
00827   /* Reset Capture/Compare selection Bits */
00828   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
00829
00830   /* Set the Output Compare Mode */
00831   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
00832
00833   /* Set the Output Compare Polarity */
00834   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
00835
00836   /* Set the Output State */
00837   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
00838
00839   if (IS_TIM_BREAK_INSTANCE(TIMx))
00840   {
00841     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00842     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00843
00844     /* Set the complementary output Polarity */
00845     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
00846
00847     /* Set the complementary output State */
00848     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
00849
00850     /* Set the Output Idle state */
00851     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
00852
00853     /* Set the complementary output Idle state */
00854     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
00855   }
00856
00857   /* Write to TIMx CR2 */
00858   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00859
00860   /* Write to TIMx CCMR1 */
00861   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00862
00863   /* Set the Capture Compare Register value */
00864   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
00865
00866   /* Write to TIMx CCER */
00867   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00868
00869   return SUCCESS;
00870 }
00871
00872 /**
00873   * @brief  Configure the TIMx output channel 2.
00874   * @param  TIMx Timer Instance
00875   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
00876   * @retval An ErrorStatus enumeration value:
00877   *          - SUCCESS: TIMx registers are de-initialized
00878   *          - ERROR: not applicable
00879   */
00880 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00881 {
00882   uint32_t tmpccmr1;
00883   uint32_t tmpccer;
00884   uint32_t tmpcr2;
00885
00886   /* Check the parameters */
00887   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
00888   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00889   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00890   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00891   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00892   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00893
00894   /* Disable the Channel 2: Reset the CC2E Bit */
00895   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
00896
00897   /* Get the TIMx CCER register value */
00898   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00899
00900   /* Get the TIMx CR2 register value */
00901   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00902
00903   /* Get the TIMx CCMR1 register value */
00904   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00905
00906   /* Reset Capture/Compare selection Bits */
00907   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
00908
00909   /* Select the Output Compare Mode */
00910   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
00911
00912   /* Set the Output Compare Polarity */
00913   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
00914
00915   /* Set the Output State */
00916   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
00917
00918   if (IS_TIM_BREAK_INSTANCE(TIMx))
00919   {
00920     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00921     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00922
00923     /* Set the complementary output Polarity */
00924     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
00925
00926     /* Set the complementary output State */
00927     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
00928
00929     /* Set the Output Idle state */
00930     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
00931
00932     /* Set the complementary output Idle state */
00933     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
00934   }
00935
00936   /* Write to TIMx CR2 */
00937   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00938
00939   /* Write to TIMx CCMR1 */
00940   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00941
00942   /* Set the Capture Compare Register value */
00943   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
00944
00945   /* Write to TIMx CCER */
00946   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00947
00948   return SUCCESS;
00949 }
00950
00951 /**
00952   * @brief  Configure the TIMx output channel 3.
00953   * @param  TIMx Timer Instance
00954   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
00955   * @retval An ErrorStatus enumeration value:
00956   *          - SUCCESS: TIMx registers are de-initialized
00957   *          - ERROR: not applicable
00958   */
00959 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00960 {
00961   uint32_t tmpccmr2;
00962   uint32_t tmpccer;
00963   uint32_t tmpcr2;
00964
00965   /* Check the parameters */
00966   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
00967   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00968   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00969   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00970   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00971   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00972
00973   /* Disable the Channel 3: Reset the CC3E Bit */
00974   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
00975
00976   /* Get the TIMx CCER register value */
00977   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00978
00979   /* Get the TIMx CR2 register value */
00980   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00981
00982   /* Get the TIMx CCMR2 register value */
00983   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
00984
00985   /* Reset Capture/Compare selection Bits */
00986   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
00987
00988   /* Select the Output Compare Mode */
00989   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
00990
00991   /* Set the Output Compare Polarity */
00992   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
00993
00994   /* Set the Output State */
00995   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
00996
00997   if (IS_TIM_BREAK_INSTANCE(TIMx))
00998   {
00999     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01000     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01001
01002     /* Set the complementary output Polarity */
01003     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
01004
01005     /* Set the complementary output State */
01006     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
01007
01008     /* Set the Output Idle state */
01009     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
01010
01011     /* Set the complementary output Idle state */
01012     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
01013   }
01014
01015   /* Write to TIMx CR2 */
01016   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01017
01018   /* Write to TIMx CCMR2 */
01019   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01020
01021   /* Set the Capture Compare Register value */
01022   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
01023
01024   /* Write to TIMx CCER */
01025   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01026
01027   return SUCCESS;
01028 }
01029
01030 /**
01031   * @brief  Configure the TIMx output channel 4.
01032   * @param  TIMx Timer Instance
01033   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
01034   * @retval An ErrorStatus enumeration value:
01035   *          - SUCCESS: TIMx registers are de-initialized
01036   *          - ERROR: not applicable
01037   */
01038 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01039 {
01040   uint32_t tmpccmr2;
01041   uint32_t tmpccer;
01042   uint32_t tmpcr2;
01043
01044   /* Check the parameters */
01045   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01046   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01047   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01048   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01049   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01050   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01051
01052   /* Disable the Channel 4: Reset the CC4E Bit */
01053   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
01054
01055   /* Get the TIMx CCER register value */
01056   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01057
01058   /* Get the TIMx CR2 register value */
01059   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
01060
01061   /* Get the TIMx CCMR2 register value */
01062   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
01063
01064   /* Reset Capture/Compare selection Bits */
01065   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
01066
01067   /* Select the Output Compare Mode */
01068   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
01069
01070   /* Set the Output Compare Polarity */
01071   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
01072
01073   /* Set the Output State */
01074   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
01075
01076   if (IS_TIM_BREAK_INSTANCE(TIMx))
01077   {
01078     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01079     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01080
01081     /* Set the Output Idle state */
01082     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
01083   }
01084
01085   /* Write to TIMx CR2 */
01086   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01087
01088   /* Write to TIMx CCMR2 */
01089   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01090
01091   /* Set the Capture Compare Register value */
01092   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
01093
01094   /* Write to TIMx CCER */
01095   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01096
01097   return SUCCESS;
01098 }
01099
01100 /**
01101   * @brief  Configure the TIMx output channel 5.
01102   * @param  TIMx Timer Instance
01103   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
01104   * @retval An ErrorStatus enumeration value:
01105   *          - SUCCESS: TIMx registers are de-initialized
01106   *          - ERROR: not applicable
01107   */
01108 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01109 {
01110   uint32_t tmpccmr3;
01111   uint32_t tmpccer;
01112
01113   /* Check the parameters */
01114   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
01115   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01116   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01117   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01118   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01119   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01120
01121   /* Disable the Channel 5: Reset the CC5E Bit */
01122   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
01123
01124   /* Get the TIMx CCER register value */
01125   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01126
01127   /* Get the TIMx CCMR3 register value */
01128   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01129
01130   /* Select the Output Compare Mode */
01131   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
01132
01133   /* Set the Output Compare Polarity */
01134   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
01135
01136   /* Set the Output State */
01137   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
01138
01139   if (IS_TIM_BREAK_INSTANCE(TIMx))
01140   {
01141     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01142     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01143
01144     /* Set the Output Idle state */
01145     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
01146
01147   }
01148
01149   /* Write to TIMx CCMR3 */
01150   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01151
01152   /* Set the Capture Compare Register value */
01153   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
01154
01155   /* Write to TIMx CCER */
01156   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01157
01158   return SUCCESS;
01159 }
01160
01161 /**
01162   * @brief  Configure the TIMx output channel 6.
01163   * @param  TIMx Timer Instance
01164   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
01165   * @retval An ErrorStatus enumeration value:
01166   *          - SUCCESS: TIMx registers are de-initialized
01167   *          - ERROR: not applicable
01168   */
01169 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01170 {
01171   uint32_t tmpccmr3;
01172   uint32_t tmpccer;
01173
01174   /* Check the parameters */
01175   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
01176   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01177   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01178   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01179   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01180   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01181
01182   /* Disable the Channel 5: Reset the CC6E Bit */
01183   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
01184
01185   /* Get the TIMx CCER register value */
01186   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01187
01188   /* Get the TIMx CCMR3 register value */
01189   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01190
01191   /* Select the Output Compare Mode */
01192   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
01193
01194   /* Set the Output Compare Polarity */
01195   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
01196
01197   /* Set the Output State */
01198   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
01199
01200   if (IS_TIM_BREAK_INSTANCE(TIMx))
01201   {
01202     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01203     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01204
01205     /* Set the Output Idle state */
01206     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
01207   }
01208
01209   /* Write to TIMx CCMR3 */
01210   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01211
01212   /* Set the Capture Compare Register value */
01213   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
01214
01215   /* Write to TIMx CCER */
01216   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01217
01218   return SUCCESS;
01219 }
01220
01221 /**
01222   * @brief  Configure the TIMx input channel 1.
01223   * @param  TIMx Timer Instance
01224   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
01225   * @retval An ErrorStatus enumeration value:
01226   *          - SUCCESS: TIMx registers are de-initialized
01227   *          - ERROR: not applicable
01228   */
01229 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01230 {
01231   /* Check the parameters */
01232   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
01233   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01234   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01235   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01236   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01237
01238   /* Disable the Channel 1: Reset the CC1E Bit */
01239   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
01240
01241   /* Select the Input and set the filter and the prescaler value */
01242   MODIFY_REG(TIMx->CCMR1,
01243              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
01244              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01245
01246   /* Select the Polarity and set the CC1E Bit */
01247   MODIFY_REG(TIMx->CCER,
01248              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
01249              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
01250
01251   return SUCCESS;
01252 }
01253
01254 /**
01255   * @brief  Configure the TIMx input channel 2.
01256   * @param  TIMx Timer Instance
01257   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
01258   * @retval An ErrorStatus enumeration value:
01259   *          - SUCCESS: TIMx registers are de-initialized
01260   *          - ERROR: not applicable
01261   */
01262 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01263 {
01264   /* Check the parameters */
01265   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
01266   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01267   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01268   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01269   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01270
01271   /* Disable the Channel 2: Reset the CC2E Bit */
01272   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
01273
01274   /* Select the Input and set the filter and the prescaler value */
01275   MODIFY_REG(TIMx->CCMR1,
01276              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
01277              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01278
01279   /* Select the Polarity and set the CC2E Bit */
01280   MODIFY_REG(TIMx->CCER,
01281              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
01282              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
01283
01284   return SUCCESS;
01285 }
01286
01287 /**
01288   * @brief  Configure the TIMx input channel 3.
01289   * @param  TIMx Timer Instance
01290   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
01291   * @retval An ErrorStatus enumeration value:
01292   *          - SUCCESS: TIMx registers are de-initialized
01293   *          - ERROR: not applicable
01294   */
01295 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01296 {
01297   /* Check the parameters */
01298   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
01299   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01300   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01301   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01302   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01303
01304   /* Disable the Channel 3: Reset the CC3E Bit */
01305   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
01306
01307   /* Select the Input and set the filter and the prescaler value */
01308   MODIFY_REG(TIMx->CCMR2,
01309              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
01310              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01311
01312   /* Select the Polarity and set the CC3E Bit */
01313   MODIFY_REG(TIMx->CCER,
01314              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
01315              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
01316
01317   return SUCCESS;
01318 }
01319
01320 /**
01321   * @brief  Configure the TIMx input channel 4.
01322   * @param  TIMx Timer Instance
01323   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
01324   * @retval An ErrorStatus enumeration value:
01325   *          - SUCCESS: TIMx registers are de-initialized
01326   *          - ERROR: not applicable
01327   */
01328 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01329 {
01330   /* Check the parameters */
01331   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01332   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01333   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01334   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01335   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01336
01337   /* Disable the Channel 4: Reset the CC4E Bit */
01338   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
01339
01340   /* Select the Input and set the filter and the prescaler value */
01341   MODIFY_REG(TIMx->CCMR2,
01342              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
01343              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01344
01345   /* Select the Polarity and set the CC2E Bit */
01346   MODIFY_REG(TIMx->CCER,
01347              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
01348              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
01349
01350   return SUCCESS;
01351 }
01352
01353
01354 /**
01355   * @}
01356   */
01357
01358 /**
01359   * @}
01360   */
01361
01362 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
01363
01364 /**
01365   * @}
01366   */
01367
01368 #endif /* USE_FULL_LL_DRIVER */
01369
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_tim.h Source File

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stm32g0xx_ll_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef __STM32G0xx_LL_TIM_H
00021 #define __STM32G0xx_LL_TIM_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) ||  defined (TIM14) ||  defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
00035
00036 /** @defgroup TIM_LL TIM
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00043   * @{
00044   */
00045 static const uint8_t OFFSET_TAB_CCMRx[] =
00046 {
00047   0x00U,   /* 0: TIMx_CH1  */
00048   0x00U,   /* 1: TIMx_CH1N */
00049   0x00U,   /* 2: TIMx_CH2  */
00050   0x00U,   /* 3: TIMx_CH2N */
00051   0x04U,   /* 4: TIMx_CH3  */
00052   0x04U,   /* 5: TIMx_CH3N */
00053   0x04U,   /* 6: TIMx_CH4  */
00054   0x3CU,   /* 7: TIMx_CH5  */
00055   0x3CU    /* 8: TIMx_CH6  */
00056 };
00057
00058 static const uint8_t SHIFT_TAB_OCxx[] =
00059 {
00060   0U,            /* 0: OC1M, OC1FE, OC1PE */
00061   0U,            /* 1: - NA */
00062   8U,            /* 2: OC2M, OC2FE, OC2PE */
00063   0U,            /* 3: - NA */
00064   0U,            /* 4: OC3M, OC3FE, OC3PE */
00065   0U,            /* 5: - NA */
00066   8U,            /* 6: OC4M, OC4FE, OC4PE */
00067   0U,            /* 7: OC5M, OC5FE, OC5PE */
00068   8U             /* 8: OC6M, OC6FE, OC6PE */
00069 };
00070
00071 static const uint8_t SHIFT_TAB_ICxx[] =
00072 {
00073   0U,            /* 0: CC1S, IC1PSC, IC1F */
00074   0U,            /* 1: - NA */
00075   8U,            /* 2: CC2S, IC2PSC, IC2F */
00076   0U,            /* 3: - NA */
00077   0U,            /* 4: CC3S, IC3PSC, IC3F */
00078   0U,            /* 5: - NA */
00079   8U,            /* 6: CC4S, IC4PSC, IC4F */
00080   0U,            /* 7: - NA */
00081   0U             /* 8: - NA */
00082 };
00083
00084 static const uint8_t SHIFT_TAB_CCxP[] =
00085 {
00086   0U,            /* 0: CC1P */
00087   2U,            /* 1: CC1NP */
00088   4U,            /* 2: CC2P */
00089   6U,            /* 3: CC2NP */
00090   8U,            /* 4: CC3P */
00091   10U,           /* 5: CC3NP */
00092   12U,           /* 6: CC4P */
00093   16U,           /* 7: CC5P */
00094   20U            /* 8: CC6P */
00095 };
00096
00097 static const uint8_t SHIFT_TAB_OISx[] =
00098 {
00099   0U,            /* 0: OIS1 */
00100   1U,            /* 1: OIS1N */
00101   2U,            /* 2: OIS2 */
00102   3U,            /* 3: OIS2N */
00103   4U,            /* 4: OIS3 */
00104   5U,            /* 5: OIS3N */
00105   6U,            /* 6: OIS4 */
00106   8U,            /* 7: OIS5 */
00107   10U            /* 8: OIS6 */
00108 };
00109 /**
00110   * @}
00111   */
00112
00113 /* Private constants ---------------------------------------------------------*/
00114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00115   * @{
00116   */
00117
00118 /* Defines used for the bit position in the register and perform offsets */
00119 #if defined(COMP3)
00120 #define TIM_POSITION_BRK_SOURCE \
00121   ((Source == LL_TIM_BKIN_SOURCE_BKIN)    ? 0U :\
00122    (Source == LL_TIM_BKIN_SOURCE_BKCOMP1) ? 1U :\
00123    (Source == LL_TIM_BKIN_SOURCE_BKCOMP2) ? 2U :3U)
00124 #else
00125 #define TIM_POSITION_BRK_SOURCE            ((Source >> 1U) & 0x1FUL)
00126 #endif
00127
00128 /* Generic bit definitions for TIMx_AF1 register */
00129 #define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
00130 #define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
00131
00132
00133 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00134 #define DT_DELAY_1 ((uint8_t)0x7F)
00135 #define DT_DELAY_2 ((uint8_t)0x3F)
00136 #define DT_DELAY_3 ((uint8_t)0x1F)
00137 #define DT_DELAY_4 ((uint8_t)0x1F)
00138
00139 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00140 #define DT_RANGE_1 ((uint8_t)0x00)
00141 #define DT_RANGE_2 ((uint8_t)0x80)
00142 #define DT_RANGE_3 ((uint8_t)0xC0)
00143 #define DT_RANGE_4 ((uint8_t)0xE0)
00144
00145 /** Legacy definitions for compatibility purpose
00146 @cond 0
00147   */
00148 /**
00149 @endcond
00150   */
00151
00152 #define OCREF_CLEAR_SELECT_Pos (16U)
00153 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)                /*!< 0x00010000 */
00154 /**
00155   * @}
00156   */
00157
00158 /* Private macros ------------------------------------------------------------*/
00159 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00160   * @{
00161   */
00162 /** @brief  Convert channel id into channel index.
00163   * @param  __CHANNEL__ This parameter can be one of the following values:
00164   *         @arg @ref LL_TIM_CHANNEL_CH1
00165   *         @arg @ref LL_TIM_CHANNEL_CH1N
00166   *         @arg @ref LL_TIM_CHANNEL_CH2
00167   *         @arg @ref LL_TIM_CHANNEL_CH2N
00168   *         @arg @ref LL_TIM_CHANNEL_CH3
00169   *         @arg @ref LL_TIM_CHANNEL_CH3N
00170   *         @arg @ref LL_TIM_CHANNEL_CH4
00171   *         @arg @ref LL_TIM_CHANNEL_CH5
00172   *         @arg @ref LL_TIM_CHANNEL_CH6
00173   * @retval none
00174   */
00175 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00176   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00177    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00178    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00179    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00180    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00181    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
00182    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
00183    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
00184
00185 /** @brief  Calculate the deadtime sampling period(in ps).
00186   * @param  __TIMCLK__ timer input clock frequency (in Hz).
00187   * @param  __CKD__ This parameter can be one of the following values:
00188   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00189   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00190   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00191   * @retval none
00192   */
00193 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
00194   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
00195    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
00196    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
00197 /**
00198   * @}
00199   */
00200
00201
00202 /* Exported types ------------------------------------------------------------*/
00203 #if defined(USE_FULL_LL_DRIVER)
00204 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
00205   * @{
00206   */
00207
00208 /**
00209   * @brief  TIM Time Base configuration structure definition.
00210   */
00211 typedef struct
00212 {
00213   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00214                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00215
00216                                    This feature can be modified afterwards using unitary function
00217                                    @ref LL_TIM_SetPrescaler().*/
00218
00219   uint32_t CounterMode;       /*!< Specifies the counter mode.
00220                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
00221
00222                                    This feature can be modified afterwards using unitary function
00223                                    @ref LL_TIM_SetCounterMode().*/
00224
00225   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
00226                                    Auto-Reload Register at the next update event.
00227                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00228                                    Some timer instances may support 32 bits counters. In that case this parameter must
00229                                    be a number between 0x0000 and 0xFFFFFFFF.
00230
00231                                    This feature can be modified afterwards using unitary function
00232                                    @ref LL_TIM_SetAutoReload().*/
00233
00234   uint32_t ClockDivision;     /*!< Specifies the clock division.
00235                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
00236
00237                                    This feature can be modified afterwards using unitary function
00238                                    @ref LL_TIM_SetClockDivision().*/
00239
00240   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00241                                    reaches zero, an update event is generated and counting restarts
00242                                    from the RCR value (N).
00243                                    This means in PWM mode that (N+1) corresponds to:
00244                                       - the number of PWM periods in edge-aligned mode
00245                                       - the number of half PWM period in center-aligned mode
00246                                    GP timers: this parameter must be a number between Min_Data = 0x00 and
00247                                    Max_Data = 0xFF.
00248                                    Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
00249                                    Max_Data = 0xFFFF.
00250
00251                                    This feature can be modified afterwards using unitary function
00252                                    @ref LL_TIM_SetRepetitionCounter().*/
00253 } LL_TIM_InitTypeDef;
00254
00255 /**
00256   * @brief  TIM Output Compare configuration structure definition.
00257   */
00258 typedef struct
00259 {
00260   uint32_t OCMode;        /*!< Specifies the output mode.
00261                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
00262
00263                                This feature can be modified afterwards using unitary function
00264                                @ref LL_TIM_OC_SetMode().*/
00265
00266   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
00267                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00268
00269                                This feature can be modified afterwards using unitary functions
00270                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00271
00272   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
00273                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00274
00275                                This feature can be modified afterwards using unitary functions
00276                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00277
00278   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
00279                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00280
00281                                This feature can be modified afterwards using unitary function
00282                                LL_TIM_OC_SetCompareCHx (x=1..6).*/
00283
00284   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00285                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00286
00287                                This feature can be modified afterwards using unitary function
00288                                @ref LL_TIM_OC_SetPolarity().*/
00289
00290   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00291                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00292
00293                                This feature can be modified afterwards using unitary function
00294                                @ref LL_TIM_OC_SetPolarity().*/
00295
00296
00297   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00298                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00299
00300                                This feature can be modified afterwards using unitary function
00301                                @ref LL_TIM_OC_SetIdleState().*/
00302
00303   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00304                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00305
00306                                This feature can be modified afterwards using unitary function
00307                                @ref LL_TIM_OC_SetIdleState().*/
00308 } LL_TIM_OC_InitTypeDef;
00309
00310 /**
00311   * @brief  TIM Input Capture configuration structure definition.
00312   */
00313
00314 typedef struct
00315 {
00316
00317   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00318                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00319
00320                                This feature can be modified afterwards using unitary function
00321                                @ref LL_TIM_IC_SetPolarity().*/
00322
00323   uint32_t ICActiveInput; /*!< Specifies the input.
00324                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00325
00326                                This feature can be modified afterwards using unitary function
00327                                @ref LL_TIM_IC_SetActiveInput().*/
00328
00329   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
00330                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00331
00332                                This feature can be modified afterwards using unitary function
00333                                @ref LL_TIM_IC_SetPrescaler().*/
00334
00335   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00336                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00337
00338                                This feature can be modified afterwards using unitary function
00339                                @ref LL_TIM_IC_SetFilter().*/
00340 } LL_TIM_IC_InitTypeDef;
00341
00342
00343 /**
00344   * @brief  TIM Encoder interface configuration structure definition.
00345   */
00346 typedef struct
00347 {
00348   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
00349                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
00350
00351                                  This feature can be modified afterwards using unitary function
00352                                  @ref LL_TIM_SetEncoderMode().*/
00353
00354   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
00355                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00356
00357                                  This feature can be modified afterwards using unitary function
00358                                  @ref LL_TIM_IC_SetPolarity().*/
00359
00360   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
00361                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00362
00363                                  This feature can be modified afterwards using unitary function
00364                                  @ref LL_TIM_IC_SetActiveInput().*/
00365
00366   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
00367                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00368
00369                                  This feature can be modified afterwards using unitary function
00370                                  @ref LL_TIM_IC_SetPrescaler().*/
00371
00372   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
00373                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00374
00375                                  This feature can be modified afterwards using unitary function
00376                                  @ref LL_TIM_IC_SetFilter().*/
00377
00378   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
00379                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00380
00381                                  This feature can be modified afterwards using unitary function
00382                                  @ref LL_TIM_IC_SetPolarity().*/
00383
00384   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
00385                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00386
00387                                  This feature can be modified afterwards using unitary function
00388                                  @ref LL_TIM_IC_SetActiveInput().*/
00389
00390   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
00391                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00392
00393                                  This feature can be modified afterwards using unitary function
00394                                  @ref LL_TIM_IC_SetPrescaler().*/
00395
00396   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
00397                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00398
00399                                  This feature can be modified afterwards using unitary function
00400                                  @ref LL_TIM_IC_SetFilter().*/
00401
00402 } LL_TIM_ENCODER_InitTypeDef;
00403
00404 /**
00405   * @brief  TIM Hall sensor interface configuration structure definition.
00406   */
00407 typedef struct
00408 {
00409
00410   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
00411                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00412
00413                                     This feature can be modified afterwards using unitary function
00414                                     @ref LL_TIM_IC_SetPolarity().*/
00415
00416   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
00417                                     Prescaler must be set to get a maximum counter period longer than the
00418                                     time interval between 2 consecutive changes on the Hall inputs.
00419                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00420
00421                                     This feature can be modified afterwards using unitary function
00422                                     @ref LL_TIM_IC_SetPrescaler().*/
00423
00424   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
00425                                     This parameter can be a value of
00426                                     @ref TIM_LL_EC_IC_FILTER.
00427
00428                                     This feature can be modified afterwards using unitary function
00429                                     @ref LL_TIM_IC_SetFilter().*/
00430
00431   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
00432                                     A positive pulse (TRGO event) is generated with a programmable delay every time
00433                                     a change occurs on the Hall inputs.
00434                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00435
00436                                     This feature can be modified afterwards using unitary function
00437                                     @ref LL_TIM_OC_SetCompareCH2().*/
00438 } LL_TIM_HALLSENSOR_InitTypeDef;
00439
00440 /**
00441   * @brief  BDTR (Break and Dead Time) structure definition
00442   */
00443 typedef struct
00444 {
00445   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
00446                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
00447
00448                                       This feature can be modified afterwards using unitary function
00449                                       @ref LL_TIM_SetOffStates()
00450
00451                                       @note This bit-field cannot be modified as long as LOCK level 2 has been
00452                                        programmed. */
00453
00454   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
00455                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
00456
00457                                       This feature can be modified afterwards using unitary function
00458                                       @ref LL_TIM_SetOffStates()
00459
00460                                       @note This bit-field cannot be modified as long as LOCK level 2 has been
00461                                       programmed. */
00462
00463   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
00464                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
00465
00466                                       @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
00467                                       register has been written, their content is frozen until the next reset.*/
00468
00469   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
00470                                       switching-on of the outputs.
00471                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00472
00473                                       This feature can be modified afterwards using unitary function
00474                                       @ref LL_TIM_OC_SetDeadTime()
00475
00476                                       @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
00477                                        programmed. */
00478
00479   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
00480                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
00481
00482                                       This feature can be modified afterwards using unitary functions
00483                                       @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
00484
00485                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00486                                       programmed. */
00487
00488   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
00489                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
00490
00491                                       This feature can be modified afterwards using unitary function
00492                                       @ref LL_TIM_ConfigBRK()
00493
00494                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00495                                       programmed. */
00496
00497   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
00498                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
00499
00500                                       This feature can be modified afterwards using unitary function
00501                                       @ref LL_TIM_ConfigBRK()
00502
00503                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00504                                       programmed. */
00505
00506   uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
00507                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
00508
00509                                       This feature can be modified afterwards using unitary functions
00510                                       @ref LL_TIM_ConfigBRK()
00511
00512                                       @note Bidirectional break input is only supported by advanced timers instances.
00513
00514                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00515                                       programmed. */
00516
00517   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
00518                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
00519
00520                                       This feature can be modified afterwards using unitary functions
00521                                       @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
00522
00523                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00524                                       programmed. */
00525
00526   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
00527                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
00528
00529                                       This feature can be modified afterwards using unitary function
00530                                       @ref LL_TIM_ConfigBRK2()
00531
00532                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00533                                       programmed. */
00534
00535   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
00536                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
00537
00538                                       This feature can be modified afterwards using unitary function
00539                                       @ref LL_TIM_ConfigBRK2()
00540
00541                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00542                                       programmed. */
00543
00544   uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
00545                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
00546
00547                                       This feature can be modified afterwards using unitary functions
00548                                       @ref LL_TIM_ConfigBRK2()
00549
00550                                       @note Bidirectional break input is only supported by advanced timers instances.
00551
00552                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00553                                       programmed. */
00554
00555   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
00556                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
00557
00558                                       This feature can be modified afterwards using unitary functions
00559                                       @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
00560
00561                                       @note This bit-field can not be modified as long as LOCK level 1 has been
00562                                       programmed. */
00563 } LL_TIM_BDTR_InitTypeDef;
00564
00565 /**
00566   * @}
00567   */
00568 #endif /* USE_FULL_LL_DRIVER */
00569
00570 /* Exported constants --------------------------------------------------------*/
00571 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00572   * @{
00573   */
00574
00575 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00576   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
00577   * @{
00578   */
00579 #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
00580 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
00581 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
00582 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
00583 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
00584 #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
00585 #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
00586 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
00587 #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
00588 #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
00589 #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
00590 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
00591 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
00592 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
00593 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
00594 #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
00595 /**
00596   * @}
00597   */
00598
00599 #if defined(USE_FULL_LL_DRIVER)
00600 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
00601   * @{
00602   */
00603 #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
00604 #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
00605 /**
00606   * @}
00607   */
00608
00609 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
00610   * @{
00611   */
00612 #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
00613 #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
00614 /**
00615   * @}
00616   */
00617
00618 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
00619   * @{
00620   */
00621 #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
00622 #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
00623 /**
00624   * @}
00625   */
00626 #endif /* USE_FULL_LL_DRIVER */
00627
00628 /** @defgroup TIM_LL_EC_IT IT Defines
00629   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
00630   * @{
00631   */
00632 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
00633 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
00634 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
00635 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
00636 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
00637 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
00638 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
00639 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
00640 /**
00641   * @}
00642   */
00643
00644 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
00645   * @{
00646   */
00647 #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
00648 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
00654   * @{
00655   */
00656 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
00657 #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
00663   * @{
00664   */
00665 #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
00666 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
00667 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
00668 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
00669 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
00670 /**
00671   * @}
00672   */
00673
00674 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
00675   * @{
00676   */
00677 #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
00678 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
00679 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
00685   * @{
00686   */
00687 #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
00688 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
00689 /**
00690   * @}
00691   */
00692
00693 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
00694   * @{
00695   */
00696 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
00697 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
00703   * @{
00704   */
00705 #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
00706 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
00707 /**
00708   * @}
00709   */
00710
00711 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
00712   * @{
00713   */
00714 #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
00715 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
00716 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
00717 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
00718 /**
00719   * @}
00720   */
00721
00722 /** @defgroup TIM_LL_EC_CHANNEL Channel
00723   * @{
00724   */
00725 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00726 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00727 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00728 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00729 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00730 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00731 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00732 #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
00733 #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
00734 /**
00735   * @}
00736   */
00737
00738 #if defined(USE_FULL_LL_DRIVER)
00739 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
00740   * @{
00741   */
00742 #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
00743 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
00744 /**
00745   * @}
00746   */
00747 #endif /* USE_FULL_LL_DRIVER */
00748
00749 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
00750   * @{
00751   */
00752 #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
00753 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
00754 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
00755 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
00756 #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
00757 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
00758 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
00759 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
00760 #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
00761 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
00762 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
00763 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
00764 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
00765 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
00766 /**
00767   * @}
00768   */
00769
00770 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
00771   * @{
00772   */
00773 #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
00774 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
00775 /**
00776   * @}
00777   */
00778
00779 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
00780   * @{
00781   */
00782 #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
00783 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
00784 /**
00785   * @}
00786   */
00787
00788 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
00789   * @{
00790   */
00791 #define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00792 #define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00793 #define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00794 #define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00795 /**
00796   * @}
00797   */
00798
00799 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
00800   * @{
00801   */
00802 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
00803 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
00804 #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
00805 /**
00806   * @}
00807   */
00808
00809 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
00810   * @{
00811   */
00812 #define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
00813 #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
00814 #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
00815 #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
00816 /**
00817   * @}
00818   */
00819
00820 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
00821   * @{
00822   */
00823 #define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
00824 #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
00825 #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
00826 #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
00827 #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
00828 #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
00829 #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
00830 #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
00831 #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
00832 #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
00833 #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
00834 #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
00835 #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
00836 #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
00837 #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
00838 #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
00839 /**
00840   * @}
00841   */
00842
00843 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
00844   * @{
00845   */
00846 #define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
00847 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
00848 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
00849 /**
00850   * @}
00851   */
00852
00853 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
00854   * @{
00855   */
00856 #define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
00857 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
00858 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00859 /**
00860   * @}
00861   */
00862
00863 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
00864   * @{
00865   */
00866 #define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
00867 #define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
00868 #define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
00869 /**
00870   * @}
00871   */
00872
00873 /** @defgroup TIM_LL_EC_TRGO Trigger Output
00874   * @{
00875   */
00876 #define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
00877 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
00878 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
00879 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
00880 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
00881 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
00882 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
00883 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
00884 /**
00885   * @}
00886   */
00887
00888 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
00889   * @{
00890   */
00891 #define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
00892 #define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
00893 #define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
00894 #define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
00895 #define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
00896 #define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
00897 #define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
00898 #define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
00899 #define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
00900 #define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
00901 #define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
00902 #define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
00903 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
00904 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
00905 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
00906 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
00907 /**
00908   * @}
00909   */
00910
00911 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
00912   * @{
00913   */
00914 #define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
00915 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
00916 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
00917 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
00918 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
00919 /**
00920   * @}
00921   */
00922
00923 /** @defgroup TIM_LL_EC_TS Trigger Selection
00924   * @{
00925   */
00926 #define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
00927 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
00928 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
00929 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
00930 #if defined(USB_BASE)
00931 #define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
00932 #endif /* USB_BASE */
00933 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
00934 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
00935 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
00936 #define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
00937 /**
00938   * @}
00939   */
00940
00941 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
00942   * @{
00943   */
00944 #define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
00945 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
00951   * @{
00952   */
00953 #define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
00954 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
00955 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
00956 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
00957 /**
00958   * @}
00959   */
00960
00961 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
00962   * @{
00963   */
00964 #define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
00965 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
00966 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
00967 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
00968 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
00969 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
00970 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
00971 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
00972 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
00973 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
00974 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
00975 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
00976 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
00977 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
00978 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
00979 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
00980 /**
00981   * @}
00982   */
00983
00984 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
00985   * @{
00986   */
00987 #define LL_TIM_ETRSOURCE_GPIO                  0x00000000U                                                 /*!< ETR input is connected to GPIO */
00988 #if defined(COMP1) && defined(COMP2)
00989 #define LL_TIM_ETRSOURCE_COMP1                 TIM1_AF1_ETRSEL_0                                 /*!< ETR input is connected to COMP1_OUT */
00990 #define LL_TIM_ETRSOURCE_COMP2                 TIM1_AF1_ETRSEL_1                                 /*!< ETR input is connected to COMP2_OUT */
00991 #endif /* COMP1 && COMP2 */
00992 #if defined(COMP3)
00993 #define LL_TIM_ETRSOURCE_COMP3                 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP3_OUT */
00994 #endif /* COMP3 */
00995 #define LL_TIM_ETRSOURCE_ADC1_AWD1             (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
00996 #define LL_TIM_ETRSOURCE_ADC1_AWD2             TIM1_AF1_ETRSEL_2                                 /*!< ETR input is connected to ADC1 analog watchdog 2 */
00997 #define LL_TIM_ETRSOURCE_ADC1_AWD3             (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
00998 #define LL_TIM_ETRSOURCE_LSE                   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
00999 #define LL_TIM_ETRSOURCE_MCO                   TIM1_AF1_ETRSEL_2                                 /*!< ETR input is connected to MCO */
01000 #define LL_TIM_ETRSOURCE_MCO2                  (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MCO2 */
01001 /**
01002   * @}
01003   */
01004
01005 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
01006   * @{
01007   */
01008 #define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
01009 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
01010 /**
01011   * @}
01012   */
01013
01014 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
01015   * @{
01016   */
01017 #define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
01018 #define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
01019 #define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
01020 #define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
01021 #define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
01022 #define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
01023 #define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
01024 #define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
01025 #define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
01026 #define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
01027 #define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
01028 #define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
01029 #define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
01030 #define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
01031 #define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
01032 #define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
01033 /**
01034   * @}
01035   */
01036
01037 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
01038   * @{
01039   */
01040 #define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
01041 #define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
01042 /**
01043   * @}
01044   */
01045
01046 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
01047   * @{
01048   */
01049 #define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
01050 #define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
01051 #define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
01052 #define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
01053 #define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
01054 #define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
01055 #define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
01056 #define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
01057 #define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
01058 #define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
01059 #define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
01060 #define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
01061 #define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
01062 #define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
01063 #define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
01064 #define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
01065 /**
01066   * @}
01067   */
01068
01069 /** @defgroup TIM_LL_EC_OSSI OSSI
01070   * @{
01071   */
01072 #define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01073 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
01074 /**
01075   * @}
01076   */
01077
01078 /** @defgroup TIM_LL_EC_OSSR OSSR
01079   * @{
01080   */
01081 #define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01082 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
01083 /**
01084   * @}
01085   */
01086
01087 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
01088   * @{
01089   */
01090 #define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
01091 #define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
01092 /**
01093   * @}
01094   */
01095
01096 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
01097   * @{
01098   */
01099 #define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
01100 #if defined(COMP1) && defined(COMP2)
01101 #define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
01102 #define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
01103 #endif /* COMP1 && COMP2 */
01104 #if defined(COMP3)
01105 #define LL_TIM_BKIN_SOURCE_BKCOMP3             TIM1_AF1_BKCMP3E    /*!< internal signal: COMP3 output */
01106 #endif /* COMP3 */
01107 /**
01108   * @}
01109   */
01110
01111 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
01112   * @{
01113   */
01114 #define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
01115 #define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
01116 /**
01117   * @}
01118   */
01119
01120 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
01121   * @{
01122   */
01123 #define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
01124 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
01125 /**
01126   * @}
01127   */
01128
01129 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
01130   * @{
01131   */
01132 #define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
01133 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
01134 /**
01135   * @}
01136   */
01137
01138 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
01139   * @{
01140   */
01141 #define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
01142 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
01143 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
01144 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
01145 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
01146 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
01147 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
01148 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
01149 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
01150 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
01151 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
01152 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
01153 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
01154 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
01155 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
01156 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
01157 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
01158 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
01159 #define LL_TIM_DMABURST_BASEADDR_OR1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_OR1 register is the DMA base address for DMA burst */
01160 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
01161 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
01162 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
01163 #define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
01164 #define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
01165 #define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
01166 /**
01167   * @}
01168   */
01169
01170 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
01171   * @{
01172   */
01173 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
01174 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
01175 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
01176 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
01177 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
01178 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
01179 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
01180 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
01181 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
01182 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
01183 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
01184 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
01185 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
01186 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
01187 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
01188 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
01189 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
01190 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
01191 /**
01192   * @}
01193   */
01194
01195 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
01196   * @{
01197   */
01198 #define LL_TIM_TIM1_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM1 input 1 is connected to GPIO */
01199 #if defined(COMP1)
01200 #define LL_TIM_TIM1_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM1 input 1 is connected to COMP1_OUT */
01201 #endif /* COMP1 */
01202 /**
01203   * @}
01204   */
01205
01206 /** @defgroup TIM_LL_EC_TIM1_TI2_RMP  TIM1 Timer Input Ch2 Remap
01207   * @{
01208   */
01209 #define LL_TIM_TIM1_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM1 input 2 is connected to GPIO */
01210 #if defined(COMP2)
01211 #define LL_TIM_TIM1_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_0                                /*!< TIM1 input 2 is connected to COMP2_OUT */
01212 #endif /* COMP2 */
01213 /**
01214   * @}
01215   */
01216
01217 /** @defgroup TIM_LL_EC_TIM1_TI3_RMP  TIM1 Timer Input Ch3 Remap
01218   * @{
01219   */
01220 #define LL_TIM_TIM1_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM1 input 3 is connected to GPIO */
01221 #if defined(COMP3)
01222 #define LL_TIM_TIM1_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM1 input 3 is connected to COMP3_OUT */
01223 #endif  /* COMP3 */
01224 /**
01225   * @}
01226   */
01227
01228 #if defined(TIM2)
01229 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP  TIM2 Timer Input Ch1 Remap
01230   * @{
01231   */
01232 #define LL_TIM_TIM2_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 1 is connected to GPIO */
01233 #define LL_TIM_TIM2_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM2 input 1 is connected to COMP1_OUT */
01234 /**
01235   * @}
01236   */
01237
01238 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP  TIM2 Timer Input Ch2 Remap
01239   * @{
01240   */
01241 #define LL_TIM_TIM2_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 2 is connected to GPIO */
01242 #define LL_TIM_TIM2_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_0                                /*!< TIM2 input 2 is connected to COMP2_OUT */
01243 /**
01244   * @}
01245   */
01246
01247 /** @defgroup TIM_LL_EC_TIM2_TI3_RMP  TIM2 Timer Input Ch3 Remap
01248   * @{
01249   */
01250 #define LL_TIM_TIM2_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 3 is connected to GPIO */
01251 #if defined(COMP3)
01252 #define LL_TIM_TIM2_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM2 input 3 is connected to COMP3_OUT */
01253 #endif /* COMP3 */
01254 /**
01255   * @}
01256   */
01257 #endif /* TIM2 */
01258
01259 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
01260   * @{
01261   */
01262 #define LL_TIM_TIM3_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 1 is connected to GPIO */
01263 #if defined(COMP1)
01264 #define LL_TIM_TIM3_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM3 input 1 is connected to COMP1_OUT */
01265 #endif /* COMP1 */
01266 /**
01267   * @}
01268   */
01269
01270 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP  TIM3 Timer Input Ch2 Remap
01271   * @{
01272   */
01273 #define LL_TIM_TIM3_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 2 is connected to GPIO */
01274 #if defined(COMP2)
01275 #define LL_TIM_TIM3_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_0                                /*!< TIM3 input 2 is connected to COMP2_OUT */
01276 #endif /* COMP2 */
01277 /**
01278   * @}
01279   */
01280
01281 /** @defgroup TIM_LL_EC_TIM3_TI3_RMP  TIM3 Timer Input Ch3 Remap
01282   * @{
01283   */
01284 #define LL_TIM_TIM3_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 3 is connected to GPIO */
01285 #if defined(COMP3)
01286 #define LL_TIM_TIM3_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM3 input 3 is connected to COMP3_OUT */
01287 #endif /* COMP3 */
01288 /**
01289   * @}
01290   */
01291
01292 #if defined(TIM4)
01293 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP  TIM4 Timer Input Ch1 Remap
01294   * @{
01295   */
01296 #define LL_TIM_TIM4_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 1 is connected to GPIO */
01297 #if defined(COMP1)
01298 #define LL_TIM_TIM4_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM4 input 1 is connected to COMP1_OUT */
01299 #endif /* COMP1 */
01300 /**
01301   * @}
01302   */
01303
01304 /** @defgroup TIM_LL_EC_TIM4_TI2_RMP  TIM4 Timer Input Ch2 Remap
01305   * @{
01306   */
01307 #define LL_TIM_TIM4_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 2 is connected to GPIO */
01308 #if defined(COMP2)
01309 #define LL_TIM_TIM4_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_0                                /*!< TIM4 input 2 is connected to COMP2_OUT */
01310 #endif /* COMP2 */
01311 /**
01312   * @}
01313   */
01314
01315 /** @defgroup TIM_LL_EC_TIM4_TI3_RMP  TIM4 Timer Input Ch3 Remap
01316   * @{
01317   */
01318 #define LL_TIM_TIM4_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 3 is connected to GPIO */
01319 #if defined(COMP3)
01320 #define LL_TIM_TIM4_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM4 input 3 is connected to COMP3_OUT */
01321 #endif /* COMP3 */
01322 /**
01323   * @}
01324   */
01325 #endif /* TIM4 */
01326
01327 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP  TIM14 Timer Input Ch1 Remap
01328   * @{
01329   */
01330 #define LL_TIM_TIM14_TI1_RMP_GPIO     0x00000000U                                    /*!< TIM14 input 1 is connected to GPIO */
01331 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK  TIM_TISEL_TI1SEL_0                             /*!< TIM14 input 1 is connected to RTC clock */
01332 #define LL_TIM_TIM14_TI1_RMP_HSE_32   TIM_TISEL_TI1SEL_1                             /*!< TIM14 input 1 is connected to HSE/32 clock */
01333 #define LL_TIM_TIM14_TI1_RMP_MCO     (TIM_TISEL_TI1SEL_0  | TIM_TISEL_TI1SEL_1)     /*!< TIM14 input 1 is connected to MCO */
01334 #define LL_TIM_TIM14_TI1_RMP_MCO2    TIM_TISEL_TI1SEL_2                             /*!< TIM14 input 1 is connected to MCO2 */
01335 /**
01336   * @}
01337   */
01338
01339 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
01340   * @{
01341   */
01342 #if defined(TIM15)
01343 #define LL_TIM_TIM15_TI1_RMP_GPIO     0x00000000U                                    /*!< TIM15 input 1 is connected to GPIO */
01344 #if defined(TIM2)
01345 #define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0                             /*!< TIM15 input 1 is connected to TIM2 input 1 */
01346 #endif /* TIM2 */
01347 #if defined(TIM3)
01348 #define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1                             /*!< TIM15 input 1 is connected to TIM3 input 1 */
01349 #endif /* TIM3 */
01350 #endif /* TIM15 */
01351 /**
01352   * @}
01353   */
01354
01355 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
01356   * @{
01357   */
01358 #if defined(TIM15)
01359 #define LL_TIM_TIM15_TI2_RMP_GPIO     0x00000000U                                    /*!< TIM15 input 2 is connected to GPIO */
01360 #if defined(TIM2)
01361 #define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0                             /*!< TIM15 input 2 is connected to TIM2 input 2 */
01362 #endif /* TIM2 */
01363 #if defined(TIM3)
01364 #define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1                             /*!< TIM15 input 2 is connected to TIM3 input 2 */
01365 #endif /* TIM3 */
01366 #endif /* TIM15 */
01367 /**
01368   * @}
01369   */
01370
01371 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
01372   * @{
01373   */
01374 #define LL_TIM_TIM16_TI1_RMP_GPIO    0x00000000U                                     /*!< TIM16 input 1 is connected to GPIO */
01375 #define LL_TIM_TIM16_TI1_RMP_LSI     TIM_TISEL_TI1SEL_0                              /*!< TIM16 input 1 is connected to LSI */
01376 #define LL_TIM_TIM16_TI1_RMP_LSE     TIM_TISEL_TI1SEL_1                              /*!< TIM16 input 1 is connected to LSE */
01377 #define LL_TIM_TIM16_TI1_RMP_RTC_WK  (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)       /*!< TIM16 input 1 is connected to RTC_WAKEUP */
01378 #define LL_TIM_TIM16_TI1_RMP_MCO2    TIM_TISEL_TI1SEL_2                              /*!< TIM16 input 1 is connected to MCO2 */
01379 /**
01380   * @}
01381   */
01382
01383 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
01384   * @{
01385   */
01386 #define LL_TIM_TIM17_TI1_RMP_GPIO    0x00000000U                                     /*!< TIM17 input 1 is connected to GPIO */
01387 #define LL_TIM_TIM17_TI1_RMP_HSI48   TIM_TISEL_TI1SEL_0                              /*!< TIM17 input 1 is connected to HSI48/256 */
01388 #define LL_TIM_TIM17_TI1_RMP_HSE_32  TIM_TISEL_TI1SEL_1                              /*!< TIM17 input 1 is connected to HSE/32 clock */
01389 #define LL_TIM_TIM17_TI1_RMP_MCO    (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)        /*!< TIM17 input 1 is connected to MCO */
01390 #define LL_TIM_TIM17_TI1_RMP_MCO2    TIM_TISEL_TI1SEL_2                              /*!< TIM17 input 1 is connected to MCO2 */
01391 /**
01392   * @}
01393   */
01394
01395 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
01396   * @{
01397   */
01398 #define LL_TIM_OCREF_CLR_INT_ETR         OCREF_CLEAR_SELECT_Msk       /*!< OCREF_CLR_INT is connected to ETRF */
01399 #if defined(COMP1) && defined(COMP2)
01400 #define LL_TIM_OCREF_CLR_INT_COMP1       0x00000000U                  /*!< OCREF clear input is connected to COMP1_OUT */
01401 #if defined(COMP3)
01402 #define LL_TIM_OCREF_CLR_INT_COMP2       TIM1_OR1_OCREF_CLR_0         /*!< OCREF clear input is connected to COMP2_OUT */
01403 #define LL_TIM_OCREF_CLR_INT_COMP3       TIM1_OR1_OCREF_CLR_1         /*!< OCREF clear input is connected to COMP3_OUT */
01404 #else
01405 #define LL_TIM_OCREF_CLR_INT_COMP2       TIM1_OR1_OCREF_CLR           /*!< OCREF clear input is connected to COMP2_OUT */
01406 #endif /* COMP3 */
01407 #endif /* COMP1 & COMP2 */
01408 /**
01409   * @}
01410   */
01411
01412 /** Legacy definitions for compatibility purpose
01413 @cond 0
01414   */
01415 #define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
01416 /**
01417 @endcond
01418   */
01419 /**
01420   * @}
01421   */
01422
01423 /* Exported macro ------------------------------------------------------------*/
01424 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
01425   * @{
01426   */
01427
01428 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
01429   * @{
01430   */
01431 /**
01432   * @brief  Write a value in TIM register.
01433   * @param  __INSTANCE__ TIM Instance
01434   * @param  __REG__ Register to be written
01435   * @param  __VALUE__ Value to be written in the register
01436   * @retval None
01437   */
01438 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
01439
01440 /**
01441   * @brief  Read a value in TIM register.
01442   * @param  __INSTANCE__ TIM Instance
01443   * @param  __REG__ Register to be read
01444   * @retval Register value
01445   */
01446 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
01447 /**
01448   * @}
01449   */
01450
01451 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
01452   * @{
01453   */
01454
01455 /**
01456   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
01457   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
01458   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
01459   *        to TIMx_CNT register bit 31)
01460   * @param  __CNT__ Counter value
01461   * @retval UIF status bit
01462   */
01463 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
01464   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
01465
01466 /**
01467   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
01468   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
01469   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01470   * @param  __CKD__ This parameter can be one of the following values:
01471   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01472   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01473   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01474   * @param  __DT__ deadtime duration (in ns)
01475   * @retval DTG[0:7]
01476   */
01477 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
01478   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
01479     (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
01480     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
01481     (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
01482                                                  (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
01483     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
01484     (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
01485                                                  (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
01486     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
01487     (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
01488                                                  (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
01489     0U)
01490
01491 /**
01492   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
01493   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
01494   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01495   * @param  __CNTCLK__ counter clock frequency (in Hz)
01496   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
01497   */
01498 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
01499   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
01500
01501 /**
01502   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
01503   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
01504   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01505   * @param  __PSC__ prescaler
01506   * @param  __FREQ__ output signal frequency (in Hz)
01507   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01508   */
01509 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
01510   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
01511
01512 /**
01513   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
01514   *         active/inactive delay.
01515   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
01516   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01517   * @param  __PSC__ prescaler
01518   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01519   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
01520   */
01521 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
01522   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
01523               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
01524
01525 /**
01526   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
01527   *         (when the timer operates in one pulse mode).
01528   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
01529   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01530   * @param  __PSC__ prescaler
01531   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01532   * @param  __PULSE__ pulse duration (in us)
01533   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01534   */
01535 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01536   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
01537               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
01538
01539 /**
01540   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
01541   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
01542   * @param  __ICPSC__ This parameter can be one of the following values:
01543   *         @arg @ref LL_TIM_ICPSC_DIV1
01544   *         @arg @ref LL_TIM_ICPSC_DIV2
01545   *         @arg @ref LL_TIM_ICPSC_DIV4
01546   *         @arg @ref LL_TIM_ICPSC_DIV8
01547   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
01548   */
01549 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
01550   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
01551
01552
01553 /**
01554   * @}
01555   */
01556
01557
01558 /**
01559   * @}
01560   */
01561
01562 /* Exported functions --------------------------------------------------------*/
01563 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
01564   * @{
01565   */
01566
01567 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
01568   * @{
01569   */
01570 /**
01571   * @brief  Enable timer counter.
01572   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
01573   * @param  TIMx Timer instance
01574   * @retval None
01575   */
01576 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
01577 {
01578   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
01579 }
01580
01581 /**
01582   * @brief  Disable timer counter.
01583   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
01584   * @param  TIMx Timer instance
01585   * @retval None
01586   */
01587 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
01588 {
01589   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
01590 }
01591
01592 /**
01593   * @brief  Indicates whether the timer counter is enabled.
01594   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
01595   * @param  TIMx Timer instance
01596   * @retval State of bit (1 or 0).
01597   */
01598 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
01599 {
01600   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
01601 }
01602
01603 /**
01604   * @brief  Enable update event generation.
01605   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
01606   * @param  TIMx Timer instance
01607   * @retval None
01608   */
01609 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
01610 {
01611   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
01612 }
01613
01614 /**
01615   * @brief  Disable update event generation.
01616   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
01617   * @param  TIMx Timer instance
01618   * @retval None
01619   */
01620 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
01621 {
01622   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
01623 }
01624
01625 /**
01626   * @brief  Indicates whether update event generation is enabled.
01627   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
01628   * @param  TIMx Timer instance
01629   * @retval Inverted state of bit (0 or 1).
01630   */
01631 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
01632 {
01633   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
01634 }
01635
01636 /**
01637   * @brief  Set update event source
01638   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
01639   *       generate an update interrupt or DMA request if enabled:
01640   *        - Counter overflow/underflow
01641   *        - Setting the UG bit
01642   *        - Update generation through the slave mode controller
01643   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
01644   *       overflow/underflow generates an update interrupt or DMA request if enabled.
01645   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
01646   * @param  TIMx Timer instance
01647   * @param  UpdateSource This parameter can be one of the following values:
01648   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01649   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01650   * @retval None
01651   */
01652 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
01653 {
01654   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
01655 }
01656
01657 /**
01658   * @brief  Get actual event update source
01659   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
01660   * @param  TIMx Timer instance
01661   * @retval Returned value can be one of the following values:
01662   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01663   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01664   */
01665 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
01666 {
01667   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
01668 }
01669
01670 /**
01671   * @brief  Set one pulse mode (one shot v.s. repetitive).
01672   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
01673   * @param  TIMx Timer instance
01674   * @param  OnePulseMode This parameter can be one of the following values:
01675   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01676   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01677   * @retval None
01678   */
01679 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
01680 {
01681   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
01682 }
01683
01684 /**
01685   * @brief  Get actual one pulse mode.
01686   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
01687   * @param  TIMx Timer instance
01688   * @retval Returned value can be one of the following values:
01689   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01690   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01691   */
01692 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
01693 {
01694   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
01695 }
01696
01697 /**
01698   * @brief  Set the timer counter counting mode.
01699   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01700   *       check whether or not the counter mode selection feature is supported
01701   *       by a timer instance.
01702   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01703   *       requires a timer reset to avoid unexpected direction
01704   *       due to DIR bit readonly in center aligned mode.
01705   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
01706   *         CR1          CMS           LL_TIM_SetCounterMode
01707   * @param  TIMx Timer instance
01708   * @param  CounterMode This parameter can be one of the following values:
01709   *         @arg @ref LL_TIM_COUNTERMODE_UP
01710   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01711   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01712   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01713   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01714   * @retval None
01715   */
01716 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
01717 {
01718   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
01719 }
01720
01721 /**
01722   * @brief  Get actual counter mode.
01723   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01724   *       check whether or not the counter mode selection feature is supported
01725   *       by a timer instance.
01726   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
01727   *         CR1          CMS           LL_TIM_GetCounterMode
01728   * @param  TIMx Timer instance
01729   * @retval Returned value can be one of the following values:
01730   *         @arg @ref LL_TIM_COUNTERMODE_UP
01731   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01732   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01733   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01734   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01735   */
01736 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
01737 {
01738   uint32_t counter_mode;
01739
01740   counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
01741
01742   if (counter_mode == 0U)
01743   {
01744     counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01745   }
01746
01747   return counter_mode;
01748 }
01749
01750 /**
01751   * @brief  Enable auto-reload (ARR) preload.
01752   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
01753   * @param  TIMx Timer instance
01754   * @retval None
01755   */
01756 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
01757 {
01758   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
01759 }
01760
01761 /**
01762   * @brief  Disable auto-reload (ARR) preload.
01763   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
01764   * @param  TIMx Timer instance
01765   * @retval None
01766   */
01767 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
01768 {
01769   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
01770 }
01771
01772 /**
01773   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
01774   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
01775   * @param  TIMx Timer instance
01776   * @retval State of bit (1 or 0).
01777   */
01778 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
01779 {
01780   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
01781 }
01782
01783 /**
01784   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
01785   *         (when supported) and the digital filters.
01786   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01787   *       whether or not the clock division feature is supported by the timer
01788   *       instance.
01789   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
01790   * @param  TIMx Timer instance
01791   * @param  ClockDivision This parameter can be one of the following values:
01792   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01793   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01794   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01795   * @retval None
01796   */
01797 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
01798 {
01799   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
01800 }
01801
01802 /**
01803   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
01804   *         generators (when supported) and the digital filters.
01805   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01806   *       whether or not the clock division feature is supported by the timer
01807   *       instance.
01808   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
01809   * @param  TIMx Timer instance
01810   * @retval Returned value can be one of the following values:
01811   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01812   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01813   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01814   */
01815 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
01816 {
01817   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
01818 }
01819
01820 /**
01821   * @brief  Set the counter value.
01822   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01823   *       whether or not a timer instance supports a 32 bits counter.
01824   * @rmtoll CNT          CNT           LL_TIM_SetCounter
01825   * @param  TIMx Timer instance
01826   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01827   * @retval None
01828   */
01829 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
01830 {
01831   WRITE_REG(TIMx->CNT, Counter);
01832 }
01833
01834 /**
01835   * @brief  Get the counter value.
01836   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01837   *       whether or not a timer instance supports a 32 bits counter.
01838   * @rmtoll CNT          CNT           LL_TIM_GetCounter
01839   * @param  TIMx Timer instance
01840   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01841   */
01842 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
01843 {
01844   return (uint32_t)(READ_REG(TIMx->CNT));
01845 }
01846
01847 /**
01848   * @brief  Get the current direction of the counter
01849   * @rmtoll CR1          DIR           LL_TIM_GetDirection
01850   * @param  TIMx Timer instance
01851   * @retval Returned value can be one of the following values:
01852   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
01853   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
01854   */
01855 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
01856 {
01857   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01858 }
01859
01860 /**
01861   * @brief  Set the prescaler value.
01862   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
01863   * @note The prescaler can be changed on the fly as this control register is buffered. The new
01864   *       prescaler ratio is taken into account at the next update event.
01865   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
01866   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
01867   * @param  TIMx Timer instance
01868   * @param  Prescaler between Min_Data=0 and Max_Data=65535
01869   * @retval None
01870   */
01871 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
01872 {
01873   WRITE_REG(TIMx->PSC, Prescaler);
01874 }
01875
01876 /**
01877   * @brief  Get the prescaler value.
01878   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
01879   * @param  TIMx Timer instance
01880   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
01881   */
01882 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
01883 {
01884   return (uint32_t)(READ_REG(TIMx->PSC));
01885 }
01886
01887 /**
01888   * @brief  Set the auto-reload value.
01889   * @note The counter is blocked while the auto-reload value is null.
01890   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01891   *       whether or not a timer instance supports a 32 bits counter.
01892   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
01893   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
01894   * @param  TIMx Timer instance
01895   * @param  AutoReload between Min_Data=0 and Max_Data=65535
01896   * @retval None
01897   */
01898 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
01899 {
01900   WRITE_REG(TIMx->ARR, AutoReload);
01901 }
01902
01903 /**
01904   * @brief  Get the auto-reload value.
01905   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
01906   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01907   *       whether or not a timer instance supports a 32 bits counter.
01908   * @param  TIMx Timer instance
01909   * @retval Auto-reload value
01910   */
01911 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
01912 {
01913   return (uint32_t)(READ_REG(TIMx->ARR));
01914 }
01915
01916 /**
01917   * @brief  Set the repetition counter value.
01918   * @note For advanced timer instances RepetitionCounter can be up to 65535.
01919   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01920   *       whether or not a timer instance supports a repetition counter.
01921   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
01922   * @param  TIMx Timer instance
01923   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
01924   * @retval None
01925   */
01926 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
01927 {
01928   WRITE_REG(TIMx->RCR, RepetitionCounter);
01929 }
01930
01931 /**
01932   * @brief  Get the repetition counter value.
01933   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01934   *       whether or not a timer instance supports a repetition counter.
01935   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
01936   * @param  TIMx Timer instance
01937   * @retval Repetition counter value
01938   */
01939 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
01940 {
01941   return (uint32_t)(READ_REG(TIMx->RCR));
01942 }
01943
01944 /**
01945   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
01946   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
01947   *       in an atomic way.
01948   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
01949   * @param  TIMx Timer instance
01950   * @retval None
01951   */
01952 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
01953 {
01954   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01955 }
01956
01957 /**
01958   * @brief  Disable update interrupt flag (UIF) remapping.
01959   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
01960   * @param  TIMx Timer instance
01961   * @retval None
01962   */
01963 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
01964 {
01965   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01966 }
01967
01968 /**
01969   * @brief  Indicate whether update interrupt flag (UIF) copy is set.
01970   * @param  Counter Counter value
01971   * @retval State of bit (1 or 0).
01972   */
01973 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
01974 {
01975   return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
01976 }
01977
01978 /**
01979   * @}
01980   */
01981
01982 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
01983   * @{
01984   */
01985 /**
01986   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01987   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
01988   *       they are updated only when a commutation event (COM) occurs.
01989   * @note Only on channels that have a complementary output.
01990   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01991   *       whether or not a timer instance is able to generate a commutation event.
01992   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
01993   * @param  TIMx Timer instance
01994   * @retval None
01995   */
01996 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
01997 {
01998   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
01999 }
02000
02001 /**
02002   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
02003   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
02004   *       whether or not a timer instance is able to generate a commutation event.
02005   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
02006   * @param  TIMx Timer instance
02007   * @retval None
02008   */
02009 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
02010 {
02011   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
02012 }
02013
02014 /**
02015   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
02016   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
02017   *       whether or not a timer instance is able to generate a commutation event.
02018   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
02019   * @param  TIMx Timer instance
02020   * @param  CCUpdateSource This parameter can be one of the following values:
02021   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
02022   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
02023   * @retval None
02024   */
02025 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
02026 {
02027   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
02028 }
02029
02030 /**
02031   * @brief  Set the trigger of the capture/compare DMA request.
02032   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
02033   * @param  TIMx Timer instance
02034   * @param  DMAReqTrigger This parameter can be one of the following values:
02035   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
02036   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
02037   * @retval None
02038   */
02039 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
02040 {
02041   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
02042 }
02043
02044 /**
02045   * @brief  Get actual trigger of the capture/compare DMA request.
02046   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
02047   * @param  TIMx Timer instance
02048   * @retval Returned value can be one of the following values:
02049   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
02050   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
02051   */
02052 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
02053 {
02054   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
02055 }
02056
02057 /**
02058   * @brief  Set the lock level to freeze the
02059   *         configuration of several capture/compare parameters.
02060   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02061   *       the lock mechanism is supported by a timer instance.
02062   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
02063   * @param  TIMx Timer instance
02064   * @param  LockLevel This parameter can be one of the following values:
02065   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
02066   *         @arg @ref LL_TIM_LOCKLEVEL_1
02067   *         @arg @ref LL_TIM_LOCKLEVEL_2
02068   *         @arg @ref LL_TIM_LOCKLEVEL_3
02069   * @retval None
02070   */
02071 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
02072 {
02073   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
02074 }
02075
02076 /**
02077   * @brief  Enable capture/compare channels.
02078   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
02079   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
02080   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
02081   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
02082   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
02083   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
02084   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
02085   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
02086   *         CCER         CC6E          LL_TIM_CC_EnableChannel
02087   * @param  TIMx Timer instance
02088   * @param  Channels This parameter can be a combination of the following values:
02089   *         @arg @ref LL_TIM_CHANNEL_CH1
02090   *         @arg @ref LL_TIM_CHANNEL_CH1N
02091   *         @arg @ref LL_TIM_CHANNEL_CH2
02092   *         @arg @ref LL_TIM_CHANNEL_CH2N
02093   *         @arg @ref LL_TIM_CHANNEL_CH3
02094   *         @arg @ref LL_TIM_CHANNEL_CH3N
02095   *         @arg @ref LL_TIM_CHANNEL_CH4
02096   *         @arg @ref LL_TIM_CHANNEL_CH5
02097   *         @arg @ref LL_TIM_CHANNEL_CH6
02098   * @retval None
02099   */
02100 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
02101 {
02102   SET_BIT(TIMx->CCER, Channels);
02103 }
02104
02105 /**
02106   * @brief  Disable capture/compare channels.
02107   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
02108   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
02109   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
02110   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
02111   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
02112   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
02113   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
02114   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
02115   *         CCER         CC6E          LL_TIM_CC_DisableChannel
02116   * @param  TIMx Timer instance
02117   * @param  Channels This parameter can be a combination of the following values:
02118   *         @arg @ref LL_TIM_CHANNEL_CH1
02119   *         @arg @ref LL_TIM_CHANNEL_CH1N
02120   *         @arg @ref LL_TIM_CHANNEL_CH2
02121   *         @arg @ref LL_TIM_CHANNEL_CH2N
02122   *         @arg @ref LL_TIM_CHANNEL_CH3
02123   *         @arg @ref LL_TIM_CHANNEL_CH3N
02124   *         @arg @ref LL_TIM_CHANNEL_CH4
02125   *         @arg @ref LL_TIM_CHANNEL_CH5
02126   *         @arg @ref LL_TIM_CHANNEL_CH6
02127   * @retval None
02128   */
02129 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
02130 {
02131   CLEAR_BIT(TIMx->CCER, Channels);
02132 }
02133
02134 /**
02135   * @brief  Indicate whether channel(s) is(are) enabled.
02136   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
02137   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
02138   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
02139   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
02140   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
02141   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
02142   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
02143   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
02144   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
02145   * @param  TIMx Timer instance
02146   * @param  Channels This parameter can be a combination of the following values:
02147   *         @arg @ref LL_TIM_CHANNEL_CH1
02148   *         @arg @ref LL_TIM_CHANNEL_CH1N
02149   *         @arg @ref LL_TIM_CHANNEL_CH2
02150   *         @arg @ref LL_TIM_CHANNEL_CH2N
02151   *         @arg @ref LL_TIM_CHANNEL_CH3
02152   *         @arg @ref LL_TIM_CHANNEL_CH3N
02153   *         @arg @ref LL_TIM_CHANNEL_CH4
02154   *         @arg @ref LL_TIM_CHANNEL_CH5
02155   *         @arg @ref LL_TIM_CHANNEL_CH6
02156   * @retval State of bit (1 or 0).
02157   */
02158 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
02159 {
02160   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
02161 }
02162
02163 /**
02164   * @}
02165   */
02166
02167 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
02168   * @{
02169   */
02170 /**
02171   * @brief  Configure an output channel.
02172   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
02173   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
02174   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
02175   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
02176   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
02177   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
02178   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
02179   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
02180   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
02181   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
02182   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
02183   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
02184   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
02185   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
02186   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
02187   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
02188   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
02189   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
02190   * @param  TIMx Timer instance
02191   * @param  Channel This parameter can be one of the following values:
02192   *         @arg @ref LL_TIM_CHANNEL_CH1
02193   *         @arg @ref LL_TIM_CHANNEL_CH2
02194   *         @arg @ref LL_TIM_CHANNEL_CH3
02195   *         @arg @ref LL_TIM_CHANNEL_CH4
02196   *         @arg @ref LL_TIM_CHANNEL_CH5
02197   *         @arg @ref LL_TIM_CHANNEL_CH6
02198   * @param  Configuration This parameter must be a combination of all the following values:
02199   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
02200   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
02201   * @retval None
02202   */
02203 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02204 {
02205   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02206   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02207   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
02208   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
02209              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
02210   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
02211              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
02212 }
02213
02214 /**
02215   * @brief  Define the behavior of the output reference signal OCxREF from which
02216   *         OCx and OCxN (when relevant) are derived.
02217   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
02218   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
02219   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
02220   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
02221   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
02222   *         CCMR3        OC6M          LL_TIM_OC_SetMode
02223   * @param  TIMx Timer instance
02224   * @param  Channel This parameter can be one of the following values:
02225   *         @arg @ref LL_TIM_CHANNEL_CH1
02226   *         @arg @ref LL_TIM_CHANNEL_CH2
02227   *         @arg @ref LL_TIM_CHANNEL_CH3
02228   *         @arg @ref LL_TIM_CHANNEL_CH4
02229   *         @arg @ref LL_TIM_CHANNEL_CH5
02230   *         @arg @ref LL_TIM_CHANNEL_CH6
02231   * @param  Mode This parameter can be one of the following values:
02232   *         @arg @ref LL_TIM_OCMODE_FROZEN
02233   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02234   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02235   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02236   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02237   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02238   *         @arg @ref LL_TIM_OCMODE_PWM1
02239   *         @arg @ref LL_TIM_OCMODE_PWM2
02240   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02241   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02242   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02243   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02244   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
02245   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
02246   * @retval None
02247   */
02248 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
02249 {
02250   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02251   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02252   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
02253 }
02254
02255 /**
02256   * @brief  Get the output compare mode of an output channel.
02257   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
02258   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
02259   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
02260   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
02261   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
02262   *         CCMR3        OC6M          LL_TIM_OC_GetMode
02263   * @param  TIMx Timer instance
02264   * @param  Channel This parameter can be one of the following values:
02265   *         @arg @ref LL_TIM_CHANNEL_CH1
02266   *         @arg @ref LL_TIM_CHANNEL_CH2
02267   *         @arg @ref LL_TIM_CHANNEL_CH3
02268   *         @arg @ref LL_TIM_CHANNEL_CH4
02269   *         @arg @ref LL_TIM_CHANNEL_CH5
02270   *         @arg @ref LL_TIM_CHANNEL_CH6
02271   * @retval Returned value can be one of the following values:
02272   *         @arg @ref LL_TIM_OCMODE_FROZEN
02273   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02274   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02275   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02276   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02277   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02278   *         @arg @ref LL_TIM_OCMODE_PWM1
02279   *         @arg @ref LL_TIM_OCMODE_PWM2
02280   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02281   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02282   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02283   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02284   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
02285   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
02286   */
02287 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
02288 {
02289   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02290   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02291   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
02292 }
02293
02294 /**
02295   * @brief  Set the polarity of an output channel.
02296   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
02297   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
02298   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
02299   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
02300   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
02301   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
02302   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
02303   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
02304   *         CCER         CC6P          LL_TIM_OC_SetPolarity
02305   * @param  TIMx Timer instance
02306   * @param  Channel This parameter can be one of the following values:
02307   *         @arg @ref LL_TIM_CHANNEL_CH1
02308   *         @arg @ref LL_TIM_CHANNEL_CH1N
02309   *         @arg @ref LL_TIM_CHANNEL_CH2
02310   *         @arg @ref LL_TIM_CHANNEL_CH2N
02311   *         @arg @ref LL_TIM_CHANNEL_CH3
02312   *         @arg @ref LL_TIM_CHANNEL_CH3N
02313   *         @arg @ref LL_TIM_CHANNEL_CH4
02314   *         @arg @ref LL_TIM_CHANNEL_CH5
02315   *         @arg @ref LL_TIM_CHANNEL_CH6
02316   * @param  Polarity This parameter can be one of the following values:
02317   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02318   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02319   * @retval None
02320   */
02321 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
02322 {
02323   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02324   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
02325 }
02326
02327 /**
02328   * @brief  Get the polarity of an output channel.
02329   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
02330   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
02331   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
02332   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
02333   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
02334   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
02335   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
02336   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
02337   *         CCER         CC6P          LL_TIM_OC_GetPolarity
02338   * @param  TIMx Timer instance
02339   * @param  Channel This parameter can be one of the following values:
02340   *         @arg @ref LL_TIM_CHANNEL_CH1
02341   *         @arg @ref LL_TIM_CHANNEL_CH1N
02342   *         @arg @ref LL_TIM_CHANNEL_CH2
02343   *         @arg @ref LL_TIM_CHANNEL_CH2N
02344   *         @arg @ref LL_TIM_CHANNEL_CH3
02345   *         @arg @ref LL_TIM_CHANNEL_CH3N
02346   *         @arg @ref LL_TIM_CHANNEL_CH4
02347   *         @arg @ref LL_TIM_CHANNEL_CH5
02348   *         @arg @ref LL_TIM_CHANNEL_CH6
02349   * @retval Returned value can be one of the following values:
02350   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02351   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02352   */
02353 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
02354 {
02355   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02356   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02357 }
02358
02359 /**
02360   * @brief  Set the IDLE state of an output channel
02361   * @note This function is significant only for the timer instances
02362   *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
02363   *       can be used to check whether or not a timer instance provides
02364   *       a break input.
02365   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
02366   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02367   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
02368   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02369   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
02370   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
02371   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
02372   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
02373   *         CR2         OIS6          LL_TIM_OC_SetIdleState
02374   * @param  TIMx Timer instance
02375   * @param  Channel This parameter can be one of the following values:
02376   *         @arg @ref LL_TIM_CHANNEL_CH1
02377   *         @arg @ref LL_TIM_CHANNEL_CH1N
02378   *         @arg @ref LL_TIM_CHANNEL_CH2
02379   *         @arg @ref LL_TIM_CHANNEL_CH2N
02380   *         @arg @ref LL_TIM_CHANNEL_CH3
02381   *         @arg @ref LL_TIM_CHANNEL_CH3N
02382   *         @arg @ref LL_TIM_CHANNEL_CH4
02383   *         @arg @ref LL_TIM_CHANNEL_CH5
02384   *         @arg @ref LL_TIM_CHANNEL_CH6
02385   * @param  IdleState This parameter can be one of the following values:
02386   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02387   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02388   * @retval None
02389   */
02390 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
02391 {
02392   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02393   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
02394 }
02395
02396 /**
02397   * @brief  Get the IDLE state of an output channel
02398   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
02399   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02400   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
02401   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02402   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
02403   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
02404   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
02405   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
02406   *         CR2         OIS6          LL_TIM_OC_GetIdleState
02407   * @param  TIMx Timer instance
02408   * @param  Channel This parameter can be one of the following values:
02409   *         @arg @ref LL_TIM_CHANNEL_CH1
02410   *         @arg @ref LL_TIM_CHANNEL_CH1N
02411   *         @arg @ref LL_TIM_CHANNEL_CH2
02412   *         @arg @ref LL_TIM_CHANNEL_CH2N
02413   *         @arg @ref LL_TIM_CHANNEL_CH3
02414   *         @arg @ref LL_TIM_CHANNEL_CH3N
02415   *         @arg @ref LL_TIM_CHANNEL_CH4
02416   *         @arg @ref LL_TIM_CHANNEL_CH5
02417   *         @arg @ref LL_TIM_CHANNEL_CH6
02418   * @retval Returned value can be one of the following values:
02419   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02420   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02421   */
02422 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
02423 {
02424   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02425   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
02426 }
02427
02428 /**
02429   * @brief  Enable fast mode for the output channel.
02430   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
02431   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
02432   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
02433   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
02434   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
02435   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02436   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02437   * @param  TIMx Timer instance
02438   * @param  Channel This parameter can be one of the following values:
02439   *         @arg @ref LL_TIM_CHANNEL_CH1
02440   *         @arg @ref LL_TIM_CHANNEL_CH2
02441   *         @arg @ref LL_TIM_CHANNEL_CH3
02442   *         @arg @ref LL_TIM_CHANNEL_CH4
02443   *         @arg @ref LL_TIM_CHANNEL_CH5
02444   *         @arg @ref LL_TIM_CHANNEL_CH6
02445   * @retval None
02446   */
02447 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02448 {
02449   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02450   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02451   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02452
02453 }
02454
02455 /**
02456   * @brief  Disable fast mode for the output channel.
02457   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
02458   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
02459   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
02460   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
02461   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02462   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02463   * @param  TIMx Timer instance
02464   * @param  Channel This parameter can be one of the following values:
02465   *         @arg @ref LL_TIM_CHANNEL_CH1
02466   *         @arg @ref LL_TIM_CHANNEL_CH2
02467   *         @arg @ref LL_TIM_CHANNEL_CH3
02468   *         @arg @ref LL_TIM_CHANNEL_CH4
02469   *         @arg @ref LL_TIM_CHANNEL_CH5
02470   *         @arg @ref LL_TIM_CHANNEL_CH6
02471   * @retval None
02472   */
02473 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02474 {
02475   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02476   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02477   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02478
02479 }
02480
02481 /**
02482   * @brief  Indicates whether fast mode is enabled for the output channel.
02483   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
02484   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
02485   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
02486   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
02487   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
02488   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
02489   * @param  TIMx Timer instance
02490   * @param  Channel This parameter can be one of the following values:
02491   *         @arg @ref LL_TIM_CHANNEL_CH1
02492   *         @arg @ref LL_TIM_CHANNEL_CH2
02493   *         @arg @ref LL_TIM_CHANNEL_CH3
02494   *         @arg @ref LL_TIM_CHANNEL_CH4
02495   *         @arg @ref LL_TIM_CHANNEL_CH5
02496   *         @arg @ref LL_TIM_CHANNEL_CH6
02497   * @retval State of bit (1 or 0).
02498   */
02499 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
02500 {
02501   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02502   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02503   uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
02504   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02505 }
02506
02507 /**
02508   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
02509   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
02510   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
02511   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
02512   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
02513   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
02514   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
02515   * @param  TIMx Timer instance
02516   * @param  Channel This parameter can be one of the following values:
02517   *         @arg @ref LL_TIM_CHANNEL_CH1
02518   *         @arg @ref LL_TIM_CHANNEL_CH2
02519   *         @arg @ref LL_TIM_CHANNEL_CH3
02520   *         @arg @ref LL_TIM_CHANNEL_CH4
02521   *         @arg @ref LL_TIM_CHANNEL_CH5
02522   *         @arg @ref LL_TIM_CHANNEL_CH6
02523   * @retval None
02524   */
02525 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02526 {
02527   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02528   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02529   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02530 }
02531
02532 /**
02533   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
02534   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
02535   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
02536   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
02537   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
02538   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
02539   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
02540   * @param  TIMx Timer instance
02541   * @param  Channel This parameter can be one of the following values:
02542   *         @arg @ref LL_TIM_CHANNEL_CH1
02543   *         @arg @ref LL_TIM_CHANNEL_CH2
02544   *         @arg @ref LL_TIM_CHANNEL_CH3
02545   *         @arg @ref LL_TIM_CHANNEL_CH4
02546   *         @arg @ref LL_TIM_CHANNEL_CH5
02547   *         @arg @ref LL_TIM_CHANNEL_CH6
02548   * @retval None
02549   */
02550 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02551 {
02552   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02553   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02554   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02555 }
02556
02557 /**
02558   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
02559   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
02560   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
02561   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
02562   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
02563   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
02564   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
02565   * @param  TIMx Timer instance
02566   * @param  Channel This parameter can be one of the following values:
02567   *         @arg @ref LL_TIM_CHANNEL_CH1
02568   *         @arg @ref LL_TIM_CHANNEL_CH2
02569   *         @arg @ref LL_TIM_CHANNEL_CH3
02570   *         @arg @ref LL_TIM_CHANNEL_CH4
02571   *         @arg @ref LL_TIM_CHANNEL_CH5
02572   *         @arg @ref LL_TIM_CHANNEL_CH6
02573   * @retval State of bit (1 or 0).
02574   */
02575 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
02576 {
02577   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02578   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02579   uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
02580   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02581 }
02582
02583 /**
02584   * @brief  Enable clearing the output channel on an external event.
02585   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02586   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02587   *       or not a timer instance can clear the OCxREF signal on an external event.
02588   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
02589   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
02590   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
02591   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
02592   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
02593   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
02594   * @param  TIMx Timer instance
02595   * @param  Channel This parameter can be one of the following values:
02596   *         @arg @ref LL_TIM_CHANNEL_CH1
02597   *         @arg @ref LL_TIM_CHANNEL_CH2
02598   *         @arg @ref LL_TIM_CHANNEL_CH3
02599   *         @arg @ref LL_TIM_CHANNEL_CH4
02600   *         @arg @ref LL_TIM_CHANNEL_CH5
02601   *         @arg @ref LL_TIM_CHANNEL_CH6
02602   * @retval None
02603   */
02604 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02605 {
02606   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02607   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02608   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02609 }
02610
02611 /**
02612   * @brief  Disable clearing the output channel on an external event.
02613   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02614   *       or not a timer instance can clear the OCxREF signal on an external event.
02615   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
02616   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
02617   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
02618   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
02619   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
02620   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
02621   * @param  TIMx Timer instance
02622   * @param  Channel This parameter can be one of the following values:
02623   *         @arg @ref LL_TIM_CHANNEL_CH1
02624   *         @arg @ref LL_TIM_CHANNEL_CH2
02625   *         @arg @ref LL_TIM_CHANNEL_CH3
02626   *         @arg @ref LL_TIM_CHANNEL_CH4
02627   *         @arg @ref LL_TIM_CHANNEL_CH5
02628   *         @arg @ref LL_TIM_CHANNEL_CH6
02629   * @retval None
02630   */
02631 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02632 {
02633   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02634   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02635   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02636 }
02637
02638 /**
02639   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
02640   * @note This function enables clearing the output channel on an external event.
02641   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02642   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02643   *       or not a timer instance can clear the OCxREF signal on an external event.
02644   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
02645   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
02646   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
02647   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
02648   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
02649   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
02650   * @param  TIMx Timer instance
02651   * @param  Channel This parameter can be one of the following values:
02652   *         @arg @ref LL_TIM_CHANNEL_CH1
02653   *         @arg @ref LL_TIM_CHANNEL_CH2
02654   *         @arg @ref LL_TIM_CHANNEL_CH3
02655   *         @arg @ref LL_TIM_CHANNEL_CH4
02656   *         @arg @ref LL_TIM_CHANNEL_CH5
02657   *         @arg @ref LL_TIM_CHANNEL_CH6
02658   * @retval State of bit (1 or 0).
02659   */
02660 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
02661 {
02662   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02663   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02664   uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
02665   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02666 }
02667
02668 /**
02669   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
02670   *         the Ocx and OCxN signals).
02671   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02672   *       dead-time insertion feature is supported by a timer instance.
02673   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
02674   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
02675   * @param  TIMx Timer instance
02676   * @param  DeadTime between Min_Data=0 and Max_Data=255
02677   * @retval None
02678   */
02679 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
02680 {
02681   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
02682 }
02683
02684 /**
02685   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
02686   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02687   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02688   *       whether or not a timer instance supports a 32 bits counter.
02689   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02690   *       output channel 1 is supported by a timer instance.
02691   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
02692   * @param  TIMx Timer instance
02693   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02694   * @retval None
02695   */
02696 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
02697 {
02698   WRITE_REG(TIMx->CCR1, CompareValue);
02699 }
02700
02701 /**
02702   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
02703   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02704   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02705   *       whether or not a timer instance supports a 32 bits counter.
02706   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02707   *       output channel 2 is supported by a timer instance.
02708   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
02709   * @param  TIMx Timer instance
02710   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02711   * @retval None
02712   */
02713 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
02714 {
02715   WRITE_REG(TIMx->CCR2, CompareValue);
02716 }
02717
02718 /**
02719   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
02720   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02721   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02722   *       whether or not a timer instance supports a 32 bits counter.
02723   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02724   *       output channel is supported by a timer instance.
02725   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
02726   * @param  TIMx Timer instance
02727   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02728   * @retval None
02729   */
02730 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
02731 {
02732   WRITE_REG(TIMx->CCR3, CompareValue);
02733 }
02734
02735 /**
02736   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
02737   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02738   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02739   *       whether or not a timer instance supports a 32 bits counter.
02740   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02741   *       output channel 4 is supported by a timer instance.
02742   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
02743   * @param  TIMx Timer instance
02744   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02745   * @retval None
02746   */
02747 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
02748 {
02749   WRITE_REG(TIMx->CCR4, CompareValue);
02750 }
02751
02752 /**
02753   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
02754   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02755   *       output channel 5 is supported by a timer instance.
02756   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02757   * @param  TIMx Timer instance
02758   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02759   * @retval None
02760   */
02761 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
02762 {
02763   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
02764 }
02765
02766 /**
02767   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
02768   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02769   *       output channel 6 is supported by a timer instance.
02770   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02771   * @param  TIMx Timer instance
02772   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02773   * @retval None
02774   */
02775 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
02776 {
02777   WRITE_REG(TIMx->CCR6, CompareValue);
02778 }
02779
02780 /**
02781   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
02782   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02783   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02784   *       whether or not a timer instance supports a 32 bits counter.
02785   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02786   *       output channel 1 is supported by a timer instance.
02787   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
02788   * @param  TIMx Timer instance
02789   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02790   */
02791 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
02792 {
02793   return (uint32_t)(READ_REG(TIMx->CCR1));
02794 }
02795
02796 /**
02797   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
02798   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02799   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02800   *       whether or not a timer instance supports a 32 bits counter.
02801   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02802   *       output channel 2 is supported by a timer instance.
02803   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
02804   * @param  TIMx Timer instance
02805   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02806   */
02807 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
02808 {
02809   return (uint32_t)(READ_REG(TIMx->CCR2));
02810 }
02811
02812 /**
02813   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
02814   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02815   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02816   *       whether or not a timer instance supports a 32 bits counter.
02817   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02818   *       output channel 3 is supported by a timer instance.
02819   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
02820   * @param  TIMx Timer instance
02821   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02822   */
02823 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
02824 {
02825   return (uint32_t)(READ_REG(TIMx->CCR3));
02826 }
02827
02828 /**
02829   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
02830   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02831   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02832   *       whether or not a timer instance supports a 32 bits counter.
02833   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02834   *       output channel 4 is supported by a timer instance.
02835   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
02836   * @param  TIMx Timer instance
02837   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02838   */
02839 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
02840 {
02841   return (uint32_t)(READ_REG(TIMx->CCR4));
02842 }
02843
02844 /**
02845   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
02846   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02847   *       output channel 5 is supported by a timer instance.
02848   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02849   * @param  TIMx Timer instance
02850   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02851   */
02852 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
02853 {
02854   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
02855 }
02856
02857 /**
02858   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
02859   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02860   *       output channel 6 is supported by a timer instance.
02861   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02862   * @param  TIMx Timer instance
02863   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02864   */
02865 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
02866 {
02867   return (uint32_t)(READ_REG(TIMx->CCR6));
02868 }
02869
02870 /**
02871   * @brief  Select on which reference signal the OC5REF is combined to.
02872   * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
02873   *       whether or not a timer instance supports the combined 3-phase PWM mode.
02874   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02875   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02876   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
02877   * @param  TIMx Timer instance
02878   * @param  GroupCH5 This parameter can be a combination of the following values:
02879   *         @arg @ref LL_TIM_GROUPCH5_NONE
02880   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
02881   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
02882   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
02883   * @retval None
02884   */
02885 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
02886 {
02887   MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
02888 }
02889
02890 /**
02891   * @}
02892   */
02893
02894 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
02895   * @{
02896   */
02897 /**
02898   * @brief  Configure input channel.
02899   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02900   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
02901   *         CCMR1        IC1F          LL_TIM_IC_Config\n
02902   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02903   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02904   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02905   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02906   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02907   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02908   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02909   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02910   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02911   *         CCER         CC1P          LL_TIM_IC_Config\n
02912   *         CCER         CC1NP         LL_TIM_IC_Config\n
02913   *         CCER         CC2P          LL_TIM_IC_Config\n
02914   *         CCER         CC2NP         LL_TIM_IC_Config\n
02915   *         CCER         CC3P          LL_TIM_IC_Config\n
02916   *         CCER         CC3NP         LL_TIM_IC_Config\n
02917   *         CCER         CC4P          LL_TIM_IC_Config\n
02918   *         CCER         CC4NP         LL_TIM_IC_Config
02919   * @param  TIMx Timer instance
02920   * @param  Channel This parameter can be one of the following values:
02921   *         @arg @ref LL_TIM_CHANNEL_CH1
02922   *         @arg @ref LL_TIM_CHANNEL_CH2
02923   *         @arg @ref LL_TIM_CHANNEL_CH3
02924   *         @arg @ref LL_TIM_CHANNEL_CH4
02925   * @param  Configuration This parameter must be a combination of all the following values:
02926   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
02927   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
02928   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
02929   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
02930   * @retval None
02931   */
02932 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02933 {
02934   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02935   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02936   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
02937              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
02938              << SHIFT_TAB_ICxx[iChannel]);
02939   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02940              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
02941 }
02942
02943 /**
02944   * @brief  Set the active input.
02945   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
02946   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
02947   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
02948   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
02949   * @param  TIMx Timer instance
02950   * @param  Channel This parameter can be one of the following values:
02951   *         @arg @ref LL_TIM_CHANNEL_CH1
02952   *         @arg @ref LL_TIM_CHANNEL_CH2
02953   *         @arg @ref LL_TIM_CHANNEL_CH3
02954   *         @arg @ref LL_TIM_CHANNEL_CH4
02955   * @param  ICActiveInput This parameter can be one of the following values:
02956   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02957   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02958   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02959   * @retval None
02960   */
02961 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
02962 {
02963   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02964   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02965   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02966 }
02967
02968 /**
02969   * @brief  Get the current active input.
02970   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
02971   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
02972   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
02973   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
02974   * @param  TIMx Timer instance
02975   * @param  Channel This parameter can be one of the following values:
02976   *         @arg @ref LL_TIM_CHANNEL_CH1
02977   *         @arg @ref LL_TIM_CHANNEL_CH2
02978   *         @arg @ref LL_TIM_CHANNEL_CH3
02979   *         @arg @ref LL_TIM_CHANNEL_CH4
02980   * @retval Returned value can be one of the following values:
02981   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02982   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02983   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02984   */
02985 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
02986 {
02987   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02988   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02989   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02990 }
02991
02992 /**
02993   * @brief  Set the prescaler of input channel.
02994   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
02995   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
02996   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
02997   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
02998   * @param  TIMx Timer instance
02999   * @param  Channel This parameter can be one of the following values:
03000   *         @arg @ref LL_TIM_CHANNEL_CH1
03001   *         @arg @ref LL_TIM_CHANNEL_CH2
03002   *         @arg @ref LL_TIM_CHANNEL_CH3
03003   *         @arg @ref LL_TIM_CHANNEL_CH4
03004   * @param  ICPrescaler This parameter can be one of the following values:
03005   *         @arg @ref LL_TIM_ICPSC_DIV1
03006   *         @arg @ref LL_TIM_ICPSC_DIV2
03007   *         @arg @ref LL_TIM_ICPSC_DIV4
03008   *         @arg @ref LL_TIM_ICPSC_DIV8
03009   * @retval None
03010   */
03011 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
03012 {
03013   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03014   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03015   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
03016 }
03017
03018 /**
03019   * @brief  Get the current prescaler value acting on an  input channel.
03020   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
03021   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
03022   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
03023   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
03024   * @param  TIMx Timer instance
03025   * @param  Channel This parameter can be one of the following values:
03026   *         @arg @ref LL_TIM_CHANNEL_CH1
03027   *         @arg @ref LL_TIM_CHANNEL_CH2
03028   *         @arg @ref LL_TIM_CHANNEL_CH3
03029   *         @arg @ref LL_TIM_CHANNEL_CH4
03030   * @retval Returned value can be one of the following values:
03031   *         @arg @ref LL_TIM_ICPSC_DIV1
03032   *         @arg @ref LL_TIM_ICPSC_DIV2
03033   *         @arg @ref LL_TIM_ICPSC_DIV4
03034   *         @arg @ref LL_TIM_ICPSC_DIV8
03035   */
03036 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
03037 {
03038   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03039   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03040   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
03041 }
03042
03043 /**
03044   * @brief  Set the input filter duration.
03045   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
03046   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
03047   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
03048   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
03049   * @param  TIMx Timer instance
03050   * @param  Channel This parameter can be one of the following values:
03051   *         @arg @ref LL_TIM_CHANNEL_CH1
03052   *         @arg @ref LL_TIM_CHANNEL_CH2
03053   *         @arg @ref LL_TIM_CHANNEL_CH3
03054   *         @arg @ref LL_TIM_CHANNEL_CH4
03055   * @param  ICFilter This parameter can be one of the following values:
03056   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
03057   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
03058   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
03059   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
03060   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
03061   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
03062   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
03063   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
03064   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
03065   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
03066   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
03067   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
03068   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
03069   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
03070   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
03071   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
03072   * @retval None
03073   */
03074 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
03075 {
03076   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03077   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03078   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
03079 }
03080
03081 /**
03082   * @brief  Get the input filter duration.
03083   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
03084   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
03085   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
03086   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
03087   * @param  TIMx Timer instance
03088   * @param  Channel This parameter can be one of the following values:
03089   *         @arg @ref LL_TIM_CHANNEL_CH1
03090   *         @arg @ref LL_TIM_CHANNEL_CH2
03091   *         @arg @ref LL_TIM_CHANNEL_CH3
03092   *         @arg @ref LL_TIM_CHANNEL_CH4
03093   * @retval Returned value can be one of the following values:
03094   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
03095   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
03096   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
03097   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
03098   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
03099   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
03100   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
03101   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
03102   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
03103   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
03104   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
03105   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
03106   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
03107   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
03108   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
03109   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
03110   */
03111 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
03112 {
03113   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03114   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
03115   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
03116 }
03117
03118 /**
03119   * @brief  Set the input channel polarity.
03120   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
03121   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
03122   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
03123   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
03124   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
03125   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
03126   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
03127   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
03128   * @param  TIMx Timer instance
03129   * @param  Channel This parameter can be one of the following values:
03130   *         @arg @ref LL_TIM_CHANNEL_CH1
03131   *         @arg @ref LL_TIM_CHANNEL_CH2
03132   *         @arg @ref LL_TIM_CHANNEL_CH3
03133   *         @arg @ref LL_TIM_CHANNEL_CH4
03134   * @param  ICPolarity This parameter can be one of the following values:
03135   *         @arg @ref LL_TIM_IC_POLARITY_RISING
03136   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
03137   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
03138   * @retval None
03139   */
03140 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
03141 {
03142   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03143   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
03144              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
03145 }
03146
03147 /**
03148   * @brief  Get the current input channel polarity.
03149   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
03150   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
03151   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
03152   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
03153   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
03154   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
03155   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
03156   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
03157   * @param  TIMx Timer instance
03158   * @param  Channel This parameter can be one of the following values:
03159   *         @arg @ref LL_TIM_CHANNEL_CH1
03160   *         @arg @ref LL_TIM_CHANNEL_CH2
03161   *         @arg @ref LL_TIM_CHANNEL_CH3
03162   *         @arg @ref LL_TIM_CHANNEL_CH4
03163   * @retval Returned value can be one of the following values:
03164   *         @arg @ref LL_TIM_IC_POLARITY_RISING
03165   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
03166   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
03167   */
03168 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
03169 {
03170   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
03171   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
03172           SHIFT_TAB_CCxP[iChannel]);
03173 }
03174
03175 /**
03176   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
03177   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03178   *       a timer instance provides an XOR input.
03179   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
03180   * @param  TIMx Timer instance
03181   * @retval None
03182   */
03183 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
03184 {
03185   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
03186 }
03187
03188 /**
03189   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
03190   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03191   *       a timer instance provides an XOR input.
03192   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
03193   * @param  TIMx Timer instance
03194   * @retval None
03195   */
03196 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
03197 {
03198   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
03199 }
03200
03201 /**
03202   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
03203   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
03204   * a timer instance provides an XOR input.
03205   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
03206   * @param  TIMx Timer instance
03207   * @retval State of bit (1 or 0).
03208   */
03209 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
03210 {
03211   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
03212 }
03213
03214 /**
03215   * @brief  Get captured value for input channel 1.
03216   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03217   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03218   *       whether or not a timer instance supports a 32 bits counter.
03219   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
03220   *       input channel 1 is supported by a timer instance.
03221   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
03222   * @param  TIMx Timer instance
03223   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03224   */
03225 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
03226 {
03227   return (uint32_t)(READ_REG(TIMx->CCR1));
03228 }
03229
03230 /**
03231   * @brief  Get captured value for input channel 2.
03232   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03233   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03234   *       whether or not a timer instance supports a 32 bits counter.
03235   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
03236   *       input channel 2 is supported by a timer instance.
03237   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
03238   * @param  TIMx Timer instance
03239   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03240   */
03241 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
03242 {
03243   return (uint32_t)(READ_REG(TIMx->CCR2));
03244 }
03245
03246 /**
03247   * @brief  Get captured value for input channel 3.
03248   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03249   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03250   *       whether or not a timer instance supports a 32 bits counter.
03251   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
03252   *       input channel 3 is supported by a timer instance.
03253   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
03254   * @param  TIMx Timer instance
03255   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03256   */
03257 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
03258 {
03259   return (uint32_t)(READ_REG(TIMx->CCR3));
03260 }
03261
03262 /**
03263   * @brief  Get captured value for input channel 4.
03264   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03265   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03266   *       whether or not a timer instance supports a 32 bits counter.
03267   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
03268   *       input channel 4 is supported by a timer instance.
03269   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
03270   * @param  TIMx Timer instance
03271   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03272   */
03273 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
03274 {
03275   return (uint32_t)(READ_REG(TIMx->CCR4));
03276 }
03277
03278 /**
03279   * @}
03280   */
03281
03282 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
03283   * @{
03284   */
03285 /**
03286   * @brief  Enable external clock mode 2.
03287   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
03288   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03289   *       whether or not a timer instance supports external clock mode2.
03290   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
03291   * @param  TIMx Timer instance
03292   * @retval None
03293   */
03294 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
03295 {
03296   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03297 }
03298
03299 /**
03300   * @brief  Disable external clock mode 2.
03301   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03302   *       whether or not a timer instance supports external clock mode2.
03303   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
03304   * @param  TIMx Timer instance
03305   * @retval None
03306   */
03307 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
03308 {
03309   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03310 }
03311
03312 /**
03313   * @brief  Indicate whether external clock mode 2 is enabled.
03314   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03315   *       whether or not a timer instance supports external clock mode2.
03316   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
03317   * @param  TIMx Timer instance
03318   * @retval State of bit (1 or 0).
03319   */
03320 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
03321 {
03322   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
03323 }
03324
03325 /**
03326   * @brief  Set the clock source of the counter clock.
03327   * @note when selected clock source is external clock mode 1, the timer input
03328   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
03329   *       function. This timer input must be configured by calling
03330   *       the @ref LL_TIM_IC_Config() function.
03331   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
03332   *       whether or not a timer instance supports external clock mode1.
03333   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03334   *       whether or not a timer instance supports external clock mode2.
03335   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
03336   *         SMCR         ECE           LL_TIM_SetClockSource
03337   * @param  TIMx Timer instance
03338   * @param  ClockSource This parameter can be one of the following values:
03339   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
03340   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
03341   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
03342   * @retval None
03343   */
03344 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
03345 {
03346   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
03347 }
03348
03349 /**
03350   * @brief  Set the encoder interface mode.
03351   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
03352   *       whether or not a timer instance supports the encoder mode.
03353   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
03354   * @param  TIMx Timer instance
03355   * @param  EncoderMode This parameter can be one of the following values:
03356   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
03357   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
03358   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
03359   * @retval None
03360   */
03361 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
03362 {
03363   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
03364 }
03365
03366 /**
03367   * @}
03368   */
03369
03370 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
03371   * @{
03372   */
03373 /**
03374   * @brief  Set the trigger output (TRGO) used for timer synchronization .
03375   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
03376   *       whether or not a timer instance can operate as a master timer.
03377   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
03378   * @param  TIMx Timer instance
03379   * @param  TimerSynchronization This parameter can be one of the following values:
03380   *         @arg @ref LL_TIM_TRGO_RESET
03381   *         @arg @ref LL_TIM_TRGO_ENABLE
03382   *         @arg @ref LL_TIM_TRGO_UPDATE
03383   *         @arg @ref LL_TIM_TRGO_CC1IF
03384   *         @arg @ref LL_TIM_TRGO_OC1REF
03385   *         @arg @ref LL_TIM_TRGO_OC2REF
03386   *         @arg @ref LL_TIM_TRGO_OC3REF
03387   *         @arg @ref LL_TIM_TRGO_OC4REF
03388   * @retval None
03389   */
03390 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
03391 {
03392   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
03393 }
03394
03395 /**
03396   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
03397   * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
03398   *       whether or not a timer instance can be used for ADC synchronization.
03399   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
03400   * @param  TIMx Timer Instance
03401   * @param  ADCSynchronization This parameter can be one of the following values:
03402   *         @arg @ref LL_TIM_TRGO2_RESET
03403   *         @arg @ref LL_TIM_TRGO2_ENABLE
03404   *         @arg @ref LL_TIM_TRGO2_UPDATE
03405   *         @arg @ref LL_TIM_TRGO2_CC1F
03406   *         @arg @ref LL_TIM_TRGO2_OC1
03407   *         @arg @ref LL_TIM_TRGO2_OC2
03408   *         @arg @ref LL_TIM_TRGO2_OC3
03409   *         @arg @ref LL_TIM_TRGO2_OC4
03410   *         @arg @ref LL_TIM_TRGO2_OC5
03411   *         @arg @ref LL_TIM_TRGO2_OC6
03412   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
03413   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
03414   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
03415   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
03416   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
03417   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
03418   * @retval None
03419   */
03420 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
03421 {
03422   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
03423 }
03424
03425 /**
03426   * @brief  Set the synchronization mode of a slave timer.
03427   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03428   *       a timer instance can operate as a slave timer.
03429   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
03430   * @param  TIMx Timer instance
03431   * @param  SlaveMode This parameter can be one of the following values:
03432   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
03433   *         @arg @ref LL_TIM_SLAVEMODE_RESET
03434   *         @arg @ref LL_TIM_SLAVEMODE_GATED
03435   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
03436   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
03437   * @retval None
03438   */
03439 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
03440 {
03441   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
03442 }
03443
03444 /**
03445   * @brief  Set the selects the trigger input to be used to synchronize the counter.
03446   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03447   *       a timer instance can operate as a slave timer.
03448   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
03449   * @param  TIMx Timer instance
03450   * @param  TriggerInput This parameter can be one of the following values:
03451   *         @arg @ref LL_TIM_TS_ITR0
03452   *         @arg @ref LL_TIM_TS_ITR1
03453   *         @arg @ref LL_TIM_TS_ITR2
03454   *         @arg @ref LL_TIM_TS_ITR3
03455   *         @arg @ref LL_TIM_TS_ITR7 (*)
03456   *         @arg @ref LL_TIM_TS_TI1F_ED
03457   *         @arg @ref LL_TIM_TS_TI1FP1
03458   *         @arg @ref LL_TIM_TS_TI2FP2
03459   *         @arg @ref LL_TIM_TS_ETRF
03460   *
03461   *      (*)  Value not defined in all devices.
03462   * @retval None
03463   */
03464 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
03465 {
03466   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
03467 }
03468
03469 /**
03470   * @brief  Enable the Master/Slave mode.
03471   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03472   *       a timer instance can operate as a slave timer.
03473   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
03474   * @param  TIMx Timer instance
03475   * @retval None
03476   */
03477 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
03478 {
03479   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03480 }
03481
03482 /**
03483   * @brief  Disable the Master/Slave mode.
03484   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03485   *       a timer instance can operate as a slave timer.
03486   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
03487   * @param  TIMx Timer instance
03488   * @retval None
03489   */
03490 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
03491 {
03492   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03493 }
03494
03495 /**
03496   * @brief Indicates whether the Master/Slave mode is enabled.
03497   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03498   * a timer instance can operate as a slave timer.
03499   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
03500   * @param  TIMx Timer instance
03501   * @retval State of bit (1 or 0).
03502   */
03503 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
03504 {
03505   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
03506 }
03507
03508 /**
03509   * @brief  Configure the external trigger (ETR) input.
03510   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
03511   *       a timer instance provides an external trigger input.
03512   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
03513   *         SMCR         ETPS          LL_TIM_ConfigETR\n
03514   *         SMCR         ETF           LL_TIM_ConfigETR
03515   * @param  TIMx Timer instance
03516   * @param  ETRPolarity This parameter can be one of the following values:
03517   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
03518   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
03519   * @param  ETRPrescaler This parameter can be one of the following values:
03520   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
03521   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
03522   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
03523   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
03524   * @param  ETRFilter This parameter can be one of the following values:
03525   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
03526   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
03527   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
03528   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
03529   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
03530   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
03531   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
03532   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
03533   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
03534   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
03535   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
03536   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
03537   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
03538   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
03539   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
03540   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
03541   * @retval None
03542   */
03543 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
03544                                       uint32_t ETRFilter)
03545 {
03546   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
03547 }
03548
03549 /**
03550   * @brief  Select the external trigger (ETR) input source.
03551   * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
03552   *       not a timer instance supports ETR source selection.
03553   * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
03554   * @param  TIMx Timer instance
03555   * @param  ETRSource This parameter can be one of the following values:
03556   *         TIM1
03557   *
03558   *         @arg @ref LL_TIM_ETRSOURCE_GPIO
03559   *         @arg @ref LL_TIM_ETRSOURCE_COMP1 (**)
03560   *         @arg @ref LL_TIM_ETRSOURCE_COMP2 (**)
03561   *         @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
03562   *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
03563   *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
03564   *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
03565   *
03566   *         TIM2 (*)
03567   *
03568   *         @arg @ref LL_TIM_ETRSOURCE_GPIO
03569   *         @arg @ref LL_TIM_ETRSOURCE_COMP1
03570   *         @arg @ref LL_TIM_ETRSOURCE_COMP2
03571   *         @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
03572   *         @arg @ref LL_TIM_ETRSOURCE_LSE
03573   *         @arg @ref LL_TIM_ETRSOURCE_MCO (**)
03574   *         @arg @ref LL_TIM_ETRSOURCE_MCO2 (**)
03575   *
03576   *         TIM3
03577   *
03578   *         @arg @ref LL_TIM_ETRSOURCE_GPIO
03579   *         @arg @ref LL_TIM_ETRSOURCE_COMP1 (**)
03580   *         @arg @ref LL_TIM_ETRSOURCE_COMP2 (**)
03581   *         @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
03582   *
03583   *         TIM4 (*)
03584   *
03585   *         @arg @ref LL_TIM_ETRSOURCE_GPIO
03586   *         @arg @ref LL_TIM_ETRSOURCE_COMP1
03587   *         @arg @ref LL_TIM_ETRSOURCE_COMP2
03588   *         @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
03589   *
03590   *  (*) Timer instance not available on all devices \n
03591   *  (**) Value not defined in all devices. \n
03592   *
03593   * @retval None
03594   */
03595 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
03596 {
03597 #if defined(COMP3)
03598   uint32_t etrsel_shift = ((ETRSource == LL_TIM_ETRSOURCE_COMP3) ? 1u : 0u);
03599   if ((TIMx == TIM1) || (TIMx == TIM2))
03600   {
03601     MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
03602   }
03603   else
03604   {
03605     MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource >> etrsel_shift);
03606   }
03607 #else
03608   MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
03609 #endif /* COMP3 */
03610 }
03611
03612 /**
03613   * @}
03614   */
03615
03616 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
03617   * @{
03618   */
03619 /**
03620   * @brief  Enable the break function.
03621   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03622   *       a timer instance provides a break input.
03623   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
03624   * @param  TIMx Timer instance
03625   * @retval None
03626   */
03627 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
03628 {
03629   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03630 }
03631
03632 /**
03633   * @brief  Disable the break function.
03634   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
03635   * @param  TIMx Timer instance
03636   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03637   *       a timer instance provides a break input.
03638   * @retval None
03639   */
03640 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
03641 {
03642   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03643 }
03644
03645 /**
03646   * @brief  Configure the break input.
03647   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03648   *       a timer instance provides a break input.
03649   * @note Bidirectional mode is only supported by advanced timer instances.
03650   *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
03651   *       a timer instance is an advanced-control timer.
03652   * @note In bidirectional mode (BKBID bit set), the Break input is configured both
03653   *        in input mode and in open drain output mode. Any active Break event will
03654   *        assert a low logic level on the Break input to indicate an internal break
03655   *        event to external devices.
03656   * @note When bidirectional mode isn't supported, BreakAFMode must be set to
03657   *       LL_TIM_BREAK_AFMODE_INPUT.
03658   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
03659   *         BDTR         BKF           LL_TIM_ConfigBRK\n
03660   *         BDTR         BKBID         LL_TIM_ConfigBRK
03661   * @param  TIMx Timer instance
03662   * @param  BreakPolarity This parameter can be one of the following values:
03663   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
03664   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
03665   * @param  BreakFilter This parameter can be one of the following values:
03666   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
03667   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
03668   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
03669   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
03670   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
03671   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
03672   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
03673   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
03674   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
03675   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
03676   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
03677   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
03678   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
03679   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
03680   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
03681   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
03682   * @param  BreakAFMode This parameter can be one of the following values:
03683   *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
03684   *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
03685   * @retval None
03686   */
03687 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
03688                                       uint32_t BreakAFMode)
03689 {
03690   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
03691 }
03692
03693 /**
03694   * @brief  Disarm the break input (when it operates in bidirectional mode).
03695   * @note  The break input can be disarmed only when it is configured in
03696   *        bidirectional mode and when when MOE is reset.
03697   * @note  Purpose is to be able to have the input voltage back to high-state,
03698   *        whatever the time constant on the output .
03699   * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
03700   * @param  TIMx Timer instance
03701   * @retval None
03702   */
03703 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
03704 {
03705   SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
03706 }
03707
03708 /**
03709   * @brief  Re-arm the break input (when it operates in bidirectional mode).
03710   * @note  The Break input is automatically armed as soon as MOE bit is set.
03711   * @rmtoll BDTR         BKDSRM        LL_TIM_ReArmBRK
03712   * @param  TIMx Timer instance
03713   * @retval None
03714   */
03715 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
03716 {
03717   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
03718 }
03719
03720 /**
03721   * @brief  Enable the break 2 function.
03722   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03723   *       a timer instance provides a second break input.
03724   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
03725   * @param  TIMx Timer instance
03726   * @retval None
03727   */
03728 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
03729 {
03730   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03731 }
03732
03733 /**
03734   * @brief  Disable the break  2 function.
03735   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03736   *       a timer instance provides a second break input.
03737   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
03738   * @param  TIMx Timer instance
03739   * @retval None
03740   */
03741 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
03742 {
03743   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03744 }
03745
03746 /**
03747   * @brief  Configure the break 2 input.
03748   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03749   *       a timer instance provides a second break input.
03750   * @note Bidirectional mode is only supported by advanced timer instances.
03751   *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
03752   *       a timer instance is an advanced-control timer.
03753   * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
03754   *        in input mode and in open drain output mode. Any active Break event will
03755   *        assert a low logic level on the Break 2 input to indicate an internal break
03756   *        event to external devices.
03757   * @note When bidirectional mode isn't supported, Break2AFMode must be set to
03758   *       LL_TIM_BREAK2_AFMODE_INPUT.
03759   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
03760   *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
03761   *         BDTR         BK2BID        LL_TIM_ConfigBRK2
03762   * @param  TIMx Timer instance
03763   * @param  Break2Polarity This parameter can be one of the following values:
03764   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
03765   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
03766   * @param  Break2Filter This parameter can be one of the following values:
03767   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
03768   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
03769   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
03770   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
03771   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
03772   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
03773   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
03774   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
03775   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
03776   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
03777   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
03778   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
03779   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
03780   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
03781   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
03782   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
03783   * @param  Break2AFMode This parameter can be one of the following values:
03784   *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
03785   *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
03786   * @retval None
03787   */
03788 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
03789                                        uint32_t Break2AFMode)
03790 {
03791   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
03792 }
03793
03794 /**
03795   * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
03796   * @note  The break 2 input can be disarmed only when it is configured in
03797   *        bidirectional mode and when when MOE is reset.
03798   * @note  Purpose is to be able to have the input voltage back to high-state,
03799   *        whatever the time constant on the output.
03800   * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
03801   * @param  TIMx Timer instance
03802   * @retval None
03803   */
03804 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
03805 {
03806   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
03807 }
03808
03809 /**
03810   * @brief  Re-arm the break 2 input (when it operates in bidirectional mode).
03811   * @note  The Break 2 input is automatically armed as soon as MOE bit is set.
03812   * @rmtoll BDTR         BK2DSRM       LL_TIM_ReArmBRK2
03813   * @param  TIMx Timer instance
03814   * @retval None
03815   */
03816 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
03817 {
03818   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
03819 }
03820
03821 /**
03822   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
03823   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03824   *       a timer instance provides a break input.
03825   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
03826   *         BDTR         OSSR          LL_TIM_SetOffStates
03827   * @param  TIMx Timer instance
03828   * @param  OffStateIdle This parameter can be one of the following values:
03829   *         @arg @ref LL_TIM_OSSI_DISABLE
03830   *         @arg @ref LL_TIM_OSSI_ENABLE
03831   * @param  OffStateRun This parameter can be one of the following values:
03832   *         @arg @ref LL_TIM_OSSR_DISABLE
03833   *         @arg @ref LL_TIM_OSSR_ENABLE
03834   * @retval None
03835   */
03836 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
03837 {
03838   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
03839 }
03840
03841 /**
03842   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
03843   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03844   *       a timer instance provides a break input.
03845   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
03846   * @param  TIMx Timer instance
03847   * @retval None
03848   */
03849 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
03850 {
03851   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03852 }
03853
03854 /**
03855   * @brief  Disable automatic output (MOE can be set only by software).
03856   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03857   *       a timer instance provides a break input.
03858   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
03859   * @param  TIMx Timer instance
03860   * @retval None
03861   */
03862 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
03863 {
03864   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03865 }
03866
03867 /**
03868   * @brief  Indicate whether automatic output is enabled.
03869   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03870   *       a timer instance provides a break input.
03871   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
03872   * @param  TIMx Timer instance
03873   * @retval State of bit (1 or 0).
03874   */
03875 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
03876 {
03877   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
03878 }
03879
03880 /**
03881   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
03882   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03883   *       software and is reset in case of break or break2 event
03884   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03885   *       a timer instance provides a break input.
03886   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
03887   * @param  TIMx Timer instance
03888   * @retval None
03889   */
03890 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
03891 {
03892   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03893 }
03894
03895 /**
03896   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
03897   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03898   *       software and is reset in case of break or break2 event.
03899   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03900   *       a timer instance provides a break input.
03901   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
03902   * @param  TIMx Timer instance
03903   * @retval None
03904   */
03905 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
03906 {
03907   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03908 }
03909
03910 /**
03911   * @brief  Indicates whether outputs are enabled.
03912   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03913   *       a timer instance provides a break input.
03914   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
03915   * @param  TIMx Timer instance
03916   * @retval State of bit (1 or 0).
03917   */
03918 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
03919 {
03920   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
03921 }
03922
03923 /**
03924   * @brief  Enable the signals connected to the designated timer break input.
03925   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03926   *       or not a timer instance allows for break input selection.
03927   * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
03928   *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
03929   *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
03930   *         AF1          BKCMP3E       LL_TIM_EnableBreakInputSource\n
03931   *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
03932   *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
03933   *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
03934   *         AF2          BK2CMP3E      LL_TIM_EnableBreakInputSource
03935   * @param  TIMx Timer instance
03936   * @param  BreakInput This parameter can be one of the following values:
03937   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03938   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03939   * @param  Source This parameter can be one of the following values:
03940   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03941   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03942   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03943   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
03944   *
03945   *         (*)  Value not defined in all devices. \n
03946   *
03947   * @retval None
03948   */
03949 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
03950 {
03951   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03952   SET_BIT(*pReg, Source);
03953 }
03954
03955 /**
03956   * @brief  Disable the signals connected to the designated timer break input.
03957   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03958   *       or not a timer instance allows for break input selection.
03959   * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
03960   *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
03961   *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
03962   *         AF1          BKCMP3E       LL_TIM_DisableBreakInputSource\n
03963   *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
03964   *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
03965   *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
03966   *         AF2          BK2CMP3E      LL_TIM_DisableBreakInputSource
03967   * @param  TIMx Timer instance
03968   * @param  BreakInput This parameter can be one of the following values:
03969   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03970   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03971   * @param  Source This parameter can be one of the following values:
03972   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03973   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03974   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03975   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
03976   *
03977   *         (*)  Value not defined in all devices. \n
03978   *
03979   * @retval None
03980   */
03981 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
03982 {
03983   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03984   CLEAR_BIT(*pReg, Source);
03985 }
03986
03987 /**
03988   * @brief  Set the polarity of the break signal for the timer break input.
03989   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03990   *       or not a timer instance allows for break input selection.
03991   * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
03992   *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
03993   *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
03994   *         AF1          BKCMP3P       LL_TIM_SetBreakInputSourcePolarity\n
03995   *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
03996   *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
03997   *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity\n
03998   *         AF2          BK2CMP3P      LL_TIM_SetBreakInputSourcePolarity
03999   * @param  TIMx Timer instance
04000   * @param  BreakInput This parameter can be one of the following values:
04001   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
04002   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
04003   * @param  Source This parameter can be one of the following values:
04004   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
04005   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
04006   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
04007   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
04008   * @param  Polarity This parameter can be one of the following values:
04009   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
04010   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
04011   *
04012   *         (*)  Value not defined in all devices. \n
04013   *
04014   * @retval None
04015   */
04016 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
04017                                                         uint32_t Polarity)
04018 {
04019   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
04020   MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
04021 }
04022 /**
04023   * @}
04024   */
04025
04026 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
04027   * @{
04028   */
04029 /**
04030   * @brief  Configures the timer DMA burst feature.
04031   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
04032   *       not a timer instance supports the DMA burst mode.
04033   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
04034   *         DCR          DBA           LL_TIM_ConfigDMABurst
04035   * @param  TIMx Timer instance
04036   * @param  DMABurstBaseAddress This parameter can be one of the following values:
04037   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
04038   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
04039   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
04040   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
04041   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
04042   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
04043   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
04044   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
04045   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
04046   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
04047   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
04048   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
04049   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
04050   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
04051   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
04052   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
04053   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
04054   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
04055   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
04056   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
04057   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
04058   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
04059   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
04060   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
04061   *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
04062   * @param  DMABurstLength This parameter can be one of the following values:
04063   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
04064   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
04065   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
04066   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
04067   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
04068   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
04069   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
04070   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
04071   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
04072   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
04073   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
04074   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
04075   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
04076   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
04077   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
04078   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
04079   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
04080   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
04081   * @retval None
04082   */
04083 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
04084 {
04085   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
04086 }
04087
04088 /**
04089   * @}
04090   */
04091
04092 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
04093   * @{
04094   */
04095 /**
04096   * @brief  Remap TIM inputs (input channel, internal/external triggers).
04097   * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
04098   *       a some timer inputs can be remapped.
04099   * @rmtoll TIM1_TISEL    TI1SEL      LL_TIM_SetRemap\n
04100   *         TIM1_TISEL    TI2SEL      LL_TIM_SetRemap\n
04101   *         TIM2_TISEL    TI1SEL      LL_TIM_SetRemap\n
04102   *         TIM2_TISEL    TI2SEL      LL_TIM_SetRemap\n
04103   *         TIM3_TISEL    TI1SEL      LL_TIM_SetRemap\n
04104   *         TIM3_TISEL    TI2SEL      LL_TIM_SetRemap\n
04105   *         TIM4_TISEL    TI1SEL      LL_TIM_SetRemap\n
04106   *         TIM4_TISEL    TI2SEL      LL_TIM_SetRemap\n
04107   *         TIM4_TISEL    TI3SEL      LL_TIM_SetRemap\n
04108   *         TIM14_TISEL   TI1SEL      LL_TIM_SetRemap\n
04109   *         TIM15_TISEL   TI1SEL      LL_TIM_SetRemap\n
04110   *         TIM15_TISEL   TI2SEL      LL_TIM_SetRemap\n
04111   *         TIM16_TISEL   TI1SEL      LL_TIM_SetRemap\n
04112   *         TIM17_TISEL   TI1SEL      LL_TIM_SetRemap
04113   * @param  TIMx Timer instance
04114   * @param  Remap Remap param depends on the TIMx. Description available only
04115   *         in CHM version of the User Manual (not in .pdf).
04116   *         Otherwise see Reference Manual description of TISEL registers.
04117   *
04118   *         Below description summarizes "Timer Instance" and "Remap" param combinations:
04119   *
04120   *         TIM1: any combination of TI1_RMP and TI2_RMP where
04121   *
04122   *            . . TI1_RMP can be one of the following values
04123   *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
04124   *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (**)
04125   *
04126   *            . . TI2_RMP can be one of the following values
04127   *            @arg @ref LL_TIM_TIM1_TI2_RMP_GPIO
04128   *            @arg @ref LL_TIM_TIM1_TI2_RMP_COMP2 (**)
04129   *
04130   *            . . TI3_RMP can be one of the following values
04131   *            @arg @ref LL_TIM_TIM1_TI3_RMP_GPIO
04132   *            @arg @ref LL_TIM_TIM1_TI3_RMP_COMP3 (**)
04133   *
04134   *         TIM2: any combination of TI1_RMP and TI2_RMP where
04135   *
04136   *            . . TI1_RMP can be one of the following values
04137   *            @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
04138   *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1 (**)
04139   *
04140   *            . . TI2_RMP can be one of the following values
04141   *            @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
04142   *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2 (**)
04143   *
04144   *            . . TI3_RMP can be one of the following values
04145   *            @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
04146   *            @arg @ref LL_TIM_TIM2_TI3_RMP_COMP3 (**)
04147   *
04148   *         TIM3: any combination of TI1_RMP and TI2_RMP where
04149   *
04150   *            . . TI1_RMP can be one of the following values
04151   *            @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
04152   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 (**)
04153   *
04154   *            . . TI2_RMP can be one of the following values
04155   *            @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
04156   *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2 (**)
04157   *
04158   *            . . TI3_RMP can be one of the following values
04159   *            @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
04160   *            @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3 (**)
04161   *
04162   *         TIM4: any combination of TI1_RMP, TI2_RMP and TI3_RMP where  (*)
04163   *
04164   *            . . TI1_RMP can be one of the following values
04165   *            @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
04166   *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1 (**)
04167   *
04168   *            . . TI2_RMP can be one of the following values
04169   *            @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
04170   *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2 (**)
04171   *
04172   *            . . TI3_RMP can be one of the following values
04173   *            @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
04174   *            @arg @ref LL_TIM_TIM4_TI3_RMP_COMP3 (**)
04175   *
04176   *         TIM14: one of the following values
04177   *
04178   *            @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
04179   *            @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
04180   *            @arg @ref LL_TIM_TIM14_TI1_RMP_HSE_32
04181   *            @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
04182   *            @arg @ref LL_TIM_TIM14_TI1_RMP_MCO2 (**)
04183   *
04184   *         TIM15: any combination of TI1_RMP and TI2_RMP where
04185   *
04186   *            . . TI1_RMP can be one of the following values
04187   *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
04188   *            @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_IC1
04189   *            @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_IC1
04190   *
04191   *            . . TI2_RMP can be one of the following values
04192   *            @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
04193   *            @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_IC2
04194   *            @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_IC2
04195   *
04196   *         TIM16: one of the following values
04197   *
04198   *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
04199   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
04200   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
04201   *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
04202   *            @arg @ref LL_TIM_TIM16_TI1_RMP_MCO2(**)
04203   *
04204   *         TIM17: one of the following values
04205   *
04206   *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
04207   *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
04208   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
04209   *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSI48 (**)
04210   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO2(**)
04211   *
04212   *  (*) Timer instance not available on all devices \n
04213   *  (**) Value not defined in all devices. \n
04214   *
04215   * @retval None
04216   */
04217 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
04218 {
04219   MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
04220 }
04221
04222 /**
04223   * @}
04224   */
04225
04226 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
04227   * @{
04228   */
04229 /**
04230   * @brief  Set the OCREF clear input source
04231   * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
04232   * @note This function can only be used in Output compare and PWM modes.
04233   * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
04234   * @rmtoll OR1           OCREF_CLR           LL_TIM_SetOCRefClearInputSource
04235   * @param  TIMx Timer instance
04236   * @param  OCRefClearInputSource This parameter can be one of the following values:
04237   *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
04238   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 (*)
04239   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*)
04240   *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP3 (*)
04241   *
04242   *         (*)  Value not defined in all devices. \n
04243   *
04244   * @retval None
04245   */
04246 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
04247 {
04248   MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
04249              ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
04250   MODIFY_REG(TIMx->OR1, TIM1_OR1_OCREF_CLR, OCRefClearInputSource);
04251 }
04252 /**
04253   * @}
04254   */
04255
04256 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
04257   * @{
04258   */
04259 /**
04260   * @brief  Clear the update interrupt flag (UIF).
04261   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
04262   * @param  TIMx Timer instance
04263   * @retval None
04264   */
04265 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
04266 {
04267   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
04268 }
04269
04270 /**
04271   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
04272   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
04273   * @param  TIMx Timer instance
04274   * @retval State of bit (1 or 0).
04275   */
04276 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
04277 {
04278   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
04279 }
04280
04281 /**
04282   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
04283   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
04284   * @param  TIMx Timer instance
04285   * @retval None
04286   */
04287 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
04288 {
04289   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
04290 }
04291
04292 /**
04293   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
04294   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
04295   * @param  TIMx Timer instance
04296   * @retval State of bit (1 or 0).
04297   */
04298 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
04299 {
04300   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
04301 }
04302
04303 /**
04304   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
04305   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
04306   * @param  TIMx Timer instance
04307   * @retval None
04308   */
04309 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
04310 {
04311   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
04312 }
04313
04314 /**
04315   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
04316   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
04317   * @param  TIMx Timer instance
04318   * @retval State of bit (1 or 0).
04319   */
04320 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
04321 {
04322   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
04323 }
04324
04325 /**
04326   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
04327   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
04328   * @param  TIMx Timer instance
04329   * @retval None
04330   */
04331 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
04332 {
04333   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
04334 }
04335
04336 /**
04337   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
04338   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
04339   * @param  TIMx Timer instance
04340   * @retval State of bit (1 or 0).
04341   */
04342 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
04343 {
04344   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
04345 }
04346
04347 /**
04348   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
04349   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
04350   * @param  TIMx Timer instance
04351   * @retval None
04352   */
04353 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
04354 {
04355   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
04356 }
04357
04358 /**
04359   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
04360   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
04361   * @param  TIMx Timer instance
04362   * @retval State of bit (1 or 0).
04363   */
04364 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
04365 {
04366   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
04367 }
04368
04369 /**
04370   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
04371   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
04372   * @param  TIMx Timer instance
04373   * @retval None
04374   */
04375 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
04376 {
04377   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
04378 }
04379
04380 /**
04381   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
04382   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
04383   * @param  TIMx Timer instance
04384   * @retval State of bit (1 or 0).
04385   */
04386 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
04387 {
04388   return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
04389 }
04390
04391 /**
04392   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
04393   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
04394   * @param  TIMx Timer instance
04395   * @retval None
04396   */
04397 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
04398 {
04399   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
04400 }
04401
04402 /**
04403   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
04404   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
04405   * @param  TIMx Timer instance
04406   * @retval State of bit (1 or 0).
04407   */
04408 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
04409 {
04410   return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
04411 }
04412
04413 /**
04414   * @brief  Clear the commutation interrupt flag (COMIF).
04415   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
04416   * @param  TIMx Timer instance
04417   * @retval None
04418   */
04419 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
04420 {
04421   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
04422 }
04423
04424 /**
04425   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
04426   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
04427   * @param  TIMx Timer instance
04428   * @retval State of bit (1 or 0).
04429   */
04430 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
04431 {
04432   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
04433 }
04434
04435 /**
04436   * @brief  Clear the trigger interrupt flag (TIF).
04437   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
04438   * @param  TIMx Timer instance
04439   * @retval None
04440   */
04441 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
04442 {
04443   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
04444 }
04445
04446 /**
04447   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
04448   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
04449   * @param  TIMx Timer instance
04450   * @retval State of bit (1 or 0).
04451   */
04452 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
04453 {
04454   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
04455 }
04456
04457 /**
04458   * @brief  Clear the break interrupt flag (BIF).
04459   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
04460   * @param  TIMx Timer instance
04461   * @retval None
04462   */
04463 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
04464 {
04465   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
04466 }
04467
04468 /**
04469   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
04470   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
04471   * @param  TIMx Timer instance
04472   * @retval State of bit (1 or 0).
04473   */
04474 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
04475 {
04476   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
04477 }
04478
04479 /**
04480   * @brief  Clear the break 2 interrupt flag (B2IF).
04481   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
04482   * @param  TIMx Timer instance
04483   * @retval None
04484   */
04485 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
04486 {
04487   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
04488 }
04489
04490 /**
04491   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
04492   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
04493   * @param  TIMx Timer instance
04494   * @retval State of bit (1 or 0).
04495   */
04496 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
04497 {
04498   return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
04499 }
04500
04501 /**
04502   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
04503   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
04504   * @param  TIMx Timer instance
04505   * @retval None
04506   */
04507 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
04508 {
04509   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
04510 }
04511
04512 /**
04513   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
04514   *         (Capture/Compare 1 interrupt is pending).
04515   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
04516   * @param  TIMx Timer instance
04517   * @retval State of bit (1 or 0).
04518   */
04519 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
04520 {
04521   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
04522 }
04523
04524 /**
04525   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
04526   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
04527   * @param  TIMx Timer instance
04528   * @retval None
04529   */
04530 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
04531 {
04532   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
04533 }
04534
04535 /**
04536   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
04537   *         (Capture/Compare 2 over-capture interrupt is pending).
04538   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
04539   * @param  TIMx Timer instance
04540   * @retval State of bit (1 or 0).
04541   */
04542 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
04543 {
04544   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
04545 }
04546
04547 /**
04548   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
04549   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
04550   * @param  TIMx Timer instance
04551   * @retval None
04552   */
04553 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
04554 {
04555   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
04556 }
04557
04558 /**
04559   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
04560   *         (Capture/Compare 3 over-capture interrupt is pending).
04561   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
04562   * @param  TIMx Timer instance
04563   * @retval State of bit (1 or 0).
04564   */
04565 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
04566 {
04567   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
04568 }
04569
04570 /**
04571   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
04572   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
04573   * @param  TIMx Timer instance
04574   * @retval None
04575   */
04576 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
04577 {
04578   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
04579 }
04580
04581 /**
04582   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
04583   *         (Capture/Compare 4 over-capture interrupt is pending).
04584   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
04585   * @param  TIMx Timer instance
04586   * @retval State of bit (1 or 0).
04587   */
04588 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
04589 {
04590   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
04591 }
04592
04593 /**
04594   * @brief  Clear the system break interrupt flag (SBIF).
04595   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
04596   * @param  TIMx Timer instance
04597   * @retval None
04598   */
04599 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
04600 {
04601   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
04602 }
04603
04604 /**
04605   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
04606   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
04607   * @param  TIMx Timer instance
04608   * @retval State of bit (1 or 0).
04609   */
04610 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
04611 {
04612   return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
04613 }
04614
04615 /**
04616   * @}
04617   */
04618
04619 /** @defgroup TIM_LL_EF_IT_Management IT-Management
04620   * @{
04621   */
04622 /**
04623   * @brief  Enable update interrupt (UIE).
04624   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
04625   * @param  TIMx Timer instance
04626   * @retval None
04627   */
04628 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
04629 {
04630   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
04631 }
04632
04633 /**
04634   * @brief  Disable update interrupt (UIE).
04635   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
04636   * @param  TIMx Timer instance
04637   * @retval None
04638   */
04639 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
04640 {
04641   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
04642 }
04643
04644 /**
04645   * @brief  Indicates whether the update interrupt (UIE) is enabled.
04646   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
04647   * @param  TIMx Timer instance
04648   * @retval State of bit (1 or 0).
04649   */
04650 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
04651 {
04652   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
04653 }
04654
04655 /**
04656   * @brief  Enable capture/compare 1 interrupt (CC1IE).
04657   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
04658   * @param  TIMx Timer instance
04659   * @retval None
04660   */
04661 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
04662 {
04663   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04664 }
04665
04666 /**
04667   * @brief  Disable capture/compare 1  interrupt (CC1IE).
04668   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
04669   * @param  TIMx Timer instance
04670   * @retval None
04671   */
04672 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
04673 {
04674   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04675 }
04676
04677 /**
04678   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
04679   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
04680   * @param  TIMx Timer instance
04681   * @retval State of bit (1 or 0).
04682   */
04683 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
04684 {
04685   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
04686 }
04687
04688 /**
04689   * @brief  Enable capture/compare 2 interrupt (CC2IE).
04690   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
04691   * @param  TIMx Timer instance
04692   * @retval None
04693   */
04694 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
04695 {
04696   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04697 }
04698
04699 /**
04700   * @brief  Disable capture/compare 2  interrupt (CC2IE).
04701   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
04702   * @param  TIMx Timer instance
04703   * @retval None
04704   */
04705 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
04706 {
04707   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04708 }
04709
04710 /**
04711   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
04712   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
04713   * @param  TIMx Timer instance
04714   * @retval State of bit (1 or 0).
04715   */
04716 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
04717 {
04718   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
04719 }
04720
04721 /**
04722   * @brief  Enable capture/compare 3 interrupt (CC3IE).
04723   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
04724   * @param  TIMx Timer instance
04725   * @retval None
04726   */
04727 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
04728 {
04729   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04730 }
04731
04732 /**
04733   * @brief  Disable capture/compare 3  interrupt (CC3IE).
04734   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
04735   * @param  TIMx Timer instance
04736   * @retval None
04737   */
04738 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
04739 {
04740   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04741 }
04742
04743 /**
04744   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
04745   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
04746   * @param  TIMx Timer instance
04747   * @retval State of bit (1 or 0).
04748   */
04749 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
04750 {
04751   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
04752 }
04753
04754 /**
04755   * @brief  Enable capture/compare 4 interrupt (CC4IE).
04756   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
04757   * @param  TIMx Timer instance
04758   * @retval None
04759   */
04760 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
04761 {
04762   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04763 }
04764
04765 /**
04766   * @brief  Disable capture/compare 4  interrupt (CC4IE).
04767   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
04768   * @param  TIMx Timer instance
04769   * @retval None
04770   */
04771 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
04772 {
04773   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04774 }
04775
04776 /**
04777   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
04778   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
04779   * @param  TIMx Timer instance
04780   * @retval State of bit (1 or 0).
04781   */
04782 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
04783 {
04784   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
04785 }
04786
04787 /**
04788   * @brief  Enable commutation interrupt (COMIE).
04789   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
04790   * @param  TIMx Timer instance
04791   * @retval None
04792   */
04793 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
04794 {
04795   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
04796 }
04797
04798 /**
04799   * @brief  Disable commutation interrupt (COMIE).
04800   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
04801   * @param  TIMx Timer instance
04802   * @retval None
04803   */
04804 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
04805 {
04806   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
04807 }
04808
04809 /**
04810   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
04811   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
04812   * @param  TIMx Timer instance
04813   * @retval State of bit (1 or 0).
04814   */
04815 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
04816 {
04817   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
04818 }
04819
04820 /**
04821   * @brief  Enable trigger interrupt (TIE).
04822   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
04823   * @param  TIMx Timer instance
04824   * @retval None
04825   */
04826 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
04827 {
04828   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
04829 }
04830
04831 /**
04832   * @brief  Disable trigger interrupt (TIE).
04833   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
04834   * @param  TIMx Timer instance
04835   * @retval None
04836   */
04837 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
04838 {
04839   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
04840 }
04841
04842 /**
04843   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
04844   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
04845   * @param  TIMx Timer instance
04846   * @retval State of bit (1 or 0).
04847   */
04848 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
04849 {
04850   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
04851 }
04852
04853 /**
04854   * @brief  Enable break interrupt (BIE).
04855   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
04856   * @param  TIMx Timer instance
04857   * @retval None
04858   */
04859 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
04860 {
04861   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
04862 }
04863
04864 /**
04865   * @brief  Disable break interrupt (BIE).
04866   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
04867   * @param  TIMx Timer instance
04868   * @retval None
04869   */
04870 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
04871 {
04872   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
04873 }
04874
04875 /**
04876   * @brief  Indicates whether the break interrupt (BIE) is enabled.
04877   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
04878   * @param  TIMx Timer instance
04879   * @retval State of bit (1 or 0).
04880   */
04881 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
04882 {
04883   return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
04884 }
04885
04886 /**
04887   * @}
04888   */
04889
04890 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
04891   * @{
04892   */
04893 /**
04894   * @brief  Enable update DMA request (UDE).
04895   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
04896   * @param  TIMx Timer instance
04897   * @retval None
04898   */
04899 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04900 {
04901   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
04902 }
04903
04904 /**
04905   * @brief  Disable update DMA request (UDE).
04906   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
04907   * @param  TIMx Timer instance
04908   * @retval None
04909   */
04910 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04911 {
04912   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
04913 }
04914
04915 /**
04916   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
04917   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
04918   * @param  TIMx Timer instance
04919   * @retval State of bit (1 or 0).
04920   */
04921 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
04922 {
04923   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
04924 }
04925
04926 /**
04927   * @brief  Enable capture/compare 1 DMA request (CC1DE).
04928   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
04929   * @param  TIMx Timer instance
04930   * @retval None
04931   */
04932 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
04933 {
04934   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04935 }
04936
04937 /**
04938   * @brief  Disable capture/compare 1  DMA request (CC1DE).
04939   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
04940   * @param  TIMx Timer instance
04941   * @retval None
04942   */
04943 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
04944 {
04945   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04946 }
04947
04948 /**
04949   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
04950   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
04951   * @param  TIMx Timer instance
04952   * @retval State of bit (1 or 0).
04953   */
04954 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
04955 {
04956   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
04957 }
04958
04959 /**
04960   * @brief  Enable capture/compare 2 DMA request (CC2DE).
04961   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
04962   * @param  TIMx Timer instance
04963   * @retval None
04964   */
04965 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
04966 {
04967   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04968 }
04969
04970 /**
04971   * @brief  Disable capture/compare 2  DMA request (CC2DE).
04972   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
04973   * @param  TIMx Timer instance
04974   * @retval None
04975   */
04976 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
04977 {
04978   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04979 }
04980
04981 /**
04982   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
04983   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
04984   * @param  TIMx Timer instance
04985   * @retval State of bit (1 or 0).
04986   */
04987 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
04988 {
04989   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
04990 }
04991
04992 /**
04993   * @brief  Enable capture/compare 3 DMA request (CC3DE).
04994   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
04995   * @param  TIMx Timer instance
04996   * @retval None
04997   */
04998 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
04999 {
05000   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
05001 }
05002
05003 /**
05004   * @brief  Disable capture/compare 3  DMA request (CC3DE).
05005   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
05006   * @param  TIMx Timer instance
05007   * @retval None
05008   */
05009 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
05010 {
05011   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
05012 }
05013
05014 /**
05015   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
05016   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
05017   * @param  TIMx Timer instance
05018   * @retval State of bit (1 or 0).
05019   */
05020 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
05021 {
05022   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
05023 }
05024
05025 /**
05026   * @brief  Enable capture/compare 4 DMA request (CC4DE).
05027   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
05028   * @param  TIMx Timer instance
05029   * @retval None
05030   */
05031 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
05032 {
05033   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
05034 }
05035
05036 /**
05037   * @brief  Disable capture/compare 4  DMA request (CC4DE).
05038   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
05039   * @param  TIMx Timer instance
05040   * @retval None
05041   */
05042 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
05043 {
05044   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
05045 }
05046
05047 /**
05048   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
05049   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
05050   * @param  TIMx Timer instance
05051   * @retval State of bit (1 or 0).
05052   */
05053 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
05054 {
05055   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
05056 }
05057
05058 /**
05059   * @brief  Enable commutation DMA request (COMDE).
05060   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
05061   * @param  TIMx Timer instance
05062   * @retval None
05063   */
05064 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
05065 {
05066   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
05067 }
05068
05069 /**
05070   * @brief  Disable commutation DMA request (COMDE).
05071   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
05072   * @param  TIMx Timer instance
05073   * @retval None
05074   */
05075 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
05076 {
05077   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
05078 }
05079
05080 /**
05081   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
05082   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
05083   * @param  TIMx Timer instance
05084   * @retval State of bit (1 or 0).
05085   */
05086 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
05087 {
05088   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
05089 }
05090
05091 /**
05092   * @brief  Enable trigger interrupt (TDE).
05093   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
05094   * @param  TIMx Timer instance
05095   * @retval None
05096   */
05097 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
05098 {
05099   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
05100 }
05101
05102 /**
05103   * @brief  Disable trigger interrupt (TDE).
05104   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
05105   * @param  TIMx Timer instance
05106   * @retval None
05107   */
05108 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
05109 {
05110   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
05111 }
05112
05113 /**
05114   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
05115   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
05116   * @param  TIMx Timer instance
05117   * @retval State of bit (1 or 0).
05118   */
05119 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
05120 {
05121   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
05122 }
05123
05124 /**
05125   * @}
05126   */
05127
05128 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
05129   * @{
05130   */
05131 /**
05132   * @brief  Generate an update event.
05133   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
05134   * @param  TIMx Timer instance
05135   * @retval None
05136   */
05137 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
05138 {
05139   SET_BIT(TIMx->EGR, TIM_EGR_UG);
05140 }
05141
05142 /**
05143   * @brief  Generate Capture/Compare 1 event.
05144   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
05145   * @param  TIMx Timer instance
05146   * @retval None
05147   */
05148 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
05149 {
05150   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
05151 }
05152
05153 /**
05154   * @brief  Generate Capture/Compare 2 event.
05155   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
05156   * @param  TIMx Timer instance
05157   * @retval None
05158   */
05159 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
05160 {
05161   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
05162 }
05163
05164 /**
05165   * @brief  Generate Capture/Compare 3 event.
05166   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
05167   * @param  TIMx Timer instance
05168   * @retval None
05169   */
05170 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
05171 {
05172   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
05173 }
05174
05175 /**
05176   * @brief  Generate Capture/Compare 4 event.
05177   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
05178   * @param  TIMx Timer instance
05179   * @retval None
05180   */
05181 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
05182 {
05183   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
05184 }
05185
05186 /**
05187   * @brief  Generate commutation event.
05188   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
05189   * @param  TIMx Timer instance
05190   * @retval None
05191   */
05192 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
05193 {
05194   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
05195 }
05196
05197 /**
05198   * @brief  Generate trigger event.
05199   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
05200   * @param  TIMx Timer instance
05201   * @retval None
05202   */
05203 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
05204 {
05205   SET_BIT(TIMx->EGR, TIM_EGR_TG);
05206 }
05207
05208 /**
05209   * @brief  Generate break event.
05210   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
05211   * @param  TIMx Timer instance
05212   * @retval None
05213   */
05214 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
05215 {
05216   SET_BIT(TIMx->EGR, TIM_EGR_BG);
05217 }
05218
05219 /**
05220   * @brief  Generate break 2 event.
05221   * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
05222   * @param  TIMx Timer instance
05223   * @retval None
05224   */
05225 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
05226 {
05227   SET_BIT(TIMx->EGR, TIM_EGR_B2G);
05228 }
05229
05230 /**
05231   * @}
05232   */
05233
05234 #if defined(USE_FULL_LL_DRIVER)
05235 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
05236   * @{
05237   */
05238
05239 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
05240 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
05241 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
05242 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
05243 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
05244 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
05245 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
05246 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
05247 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
05248 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
05249 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
05250 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
05251 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
05252 /**
05253   * @}
05254   */
05255 #endif /* USE_FULL_LL_DRIVER */
05256
05257 /**
05258   * @}
05259   */
05260
05261 /**
05262   * @}
05263   */
05264
05265 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
05266
05267 /**
05268   * @}
05269   */
05270
05271 #ifdef __cplusplus
05272 }
05273 #endif
05274
05275 #endif /* __STM32G0xx_LL_TIM_H */
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_ucpd.c Source File

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stm32g0xx_ll_ucpd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_ucpd.c
00004   * @author  MCD Application Team
00005   * @brief   UCPD LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_ucpd.h"
00022 #include "stm32g0xx_ll_bus.h"
00023 #include "stm32g0xx_ll_rcc.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32G0xx_LL_Driver
00032   * @{
00033   */
00034 #if defined (UCPD1) || defined (UCPD2)
00035 /** @addtogroup UCPD_LL
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @defgroup UCPD_LL_Private_Constants UCPD Private Constants
00044   * @{
00045   */
00046
00047 /**
00048   * @}
00049   */
00050
00051 /* Private macros ------------------------------------------------------------*/
00052 /** @defgroup UCPD_LL_Private_Macros UCPD Private Macros
00053   * @{
00054   */
00055
00056
00057 /**
00058   * @}
00059   */
00060
00061 /* Private function prototypes -----------------------------------------------*/
00062
00063 /* Exported functions --------------------------------------------------------*/
00064 /** @addtogroup UCPD_LL_Exported_Functions
00065   * @{
00066   */
00067
00068 /** @addtogroup UCPD_LL_EF_Init
00069   * @{
00070   */
00071
00072 /**
00073   * @brief  De-initialize the UCPD registers to their default reset values.
00074   * @param  UCPDx ucpd Instance
00075   * @retval An ErrorStatus enumeration value:
00076   *          - SUCCESS: ucpd registers are de-initialized
00077   *          - ERROR: ucpd registers are not de-initialized
00078   */
00079 ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx)
00080 {
00081   ErrorStatus status = ERROR;
00082
00083   /* Check the parameters */
00084   assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
00085
00086   LL_UCPD_Disable(UCPDx);
00087
00088   if (UCPD1 == UCPDx)
00089   {
00090     /* Force reset of ucpd clock */
00091     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UCPD1);
00092
00093     /* Release reset of ucpd clock */
00094     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UCPD1);
00095
00096     /* Disable ucpd clock */
00097     LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UCPD1);
00098
00099     status = SUCCESS;
00100   }
00101   if (UCPD2 == UCPDx)
00102   {
00103     /* Force reset of ucpd clock */
00104     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UCPD2);
00105
00106     /* Release reset of ucpd clock */
00107     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UCPD2);
00108
00109     /* Disable ucpd clock */
00110     LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UCPD2);
00111
00112     status = SUCCESS;
00113   }
00114
00115   return status;
00116 }
00117
00118 /**
00119   * @brief  Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
00120   * @note   As some bits in ucpd configuration registers can only be written when the ucpd is disabled
00121   *         (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function.
00122   *         Otherwise, ERROR result will be returned.
00123   * @param  UCPDx UCPD Instance
00124   * @param  UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains
00125   *         the configuration information for the UCPD peripheral.
00126   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00127   */
00128 ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
00129 {
00130   /* Check the ucpd Instance UCPDx*/
00131   assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
00132
00133   if (UCPD1 == UCPDx)
00134   {
00135     LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UCPD1);
00136   }
00137
00138   if (UCPD2 == UCPDx)
00139   {
00140     LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UCPD2);
00141   }
00142
00143   LL_UCPD_Disable(UCPDx);
00144
00145   /*---------------------------- UCPDx CFG1 Configuration ------------------------*/
00146   MODIFY_REG(UCPDx->CFG1,
00147              UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV,
00148              UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin  << UCPD_CFG1_TRANSWIN_Pos) |
00149              (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv);
00150
00151   return SUCCESS;
00152 }
00153
00154 /**
00155   * @brief  Set each @ref LL_UCPD_InitTypeDef field to default value.
00156   * @param  UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure
00157   *         whose fields will be set to default values.
00158   * @retval None
00159   */
00160 void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct)
00161 {
00162   /* Set UCPD_InitStruct fields to default values */
00163   UCPD_InitStruct->psc_ucpdclk  = LL_UCPD_PSC_DIV2;
00164   UCPD_InitStruct->transwin     = 0x7;   /* Divide by 8                     */
00165   UCPD_InitStruct->IfrGap       = 0x10;  /* Divide by 17                    */
00166   UCPD_InitStruct->HbitClockDiv = 0x0D;  /* Divide by 14 to produce HBITCLK */
00167 }
00168
00169 /**
00170   * @}
00171   */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180 #endif /* defined (UCPD1) || defined (UCPD2) */
00181 /**
00182   * @}
00183   */
00184
00185 #endif /* USE_FULL_LL_DRIVER */
00186
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_ucpd.h Source File

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stm32g0xx_ll_ucpd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_ucpd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UCPD LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_UCPD_H
00021 #define STM32G0xx_LL_UCPD_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (UCPD1) || defined (UCPD2)
00035
00036 /** @defgroup UCPD_LL UCPD
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043
00044 /* Exported types ------------------------------------------------------------*/
00045 #if defined(USE_FULL_LL_DRIVER)
00046 /** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  UCPD Init structures definition
00052   */
00053 typedef struct
00054 {
00055   uint32_t psc_ucpdclk;         /*!< Specify the prescaler for the UCPD clock.
00056                                      This parameter can be a value of @ref UCPD_LL_EC_PSC.
00057                                      This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk().
00058                                 */
00059
00060   uint32_t transwin;            /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV)
00061                                    to achieve a legal tTransitionWindow (set according to peripheral clock to define
00062                                     an interval of between 12 and 20 us).
00063                                     This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
00064                                     This value can be modified afterwards using function @ref LL_UCPD_SetTransWin().
00065                                 */
00066
00067   uint32_t IfrGap;              /*!< Specify the definition of the clock divider (minus 1) in order to generate
00068                                     tInterframeGap from the peripheral clock.
00069                                     This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
00070                                     This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap().
00071                                 */
00072
00073   uint32_t HbitClockDiv;        /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock
00074                                      e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock :
00075                                      "UCPD1_CLK".
00076                                      This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
00077                                      This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv().
00078                                 */
00079
00080 } LL_UCPD_InitTypeDef;
00081
00082 /**
00083   * @}
00084   */
00085 #endif /* USE_FULL_LL_DRIVER */
00086
00087 /* Exported constants --------------------------------------------------------*/
00088 /** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
00089   * @{
00090   */
00091
00092 /** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
00093   * @brief    Flags defines which can be used with LL_ucpd_ReadReg function
00094   * @{
00095   */
00096 #define LL_UCPD_SR_TXIS             UCPD_SR_TXIS                  /*!< Transmit interrupt status                      */
00097 #define LL_UCPD_SR_TXMSGDISC        UCPD_SR_TXMSGDISC             /*!< Transmit message discarded interrupt           */
00098 #define LL_UCPD_SR_TXMSGSENT        UCPD_SR_TXMSGSENT             /*!< Transmit message sent interrupt                */
00099 #define LL_UCPD_SR_TXMSGABT         UCPD_SR_TXMSGABT              /*!< Transmit message abort interrupt               */
00100 #define LL_UCPD_SR_HRSTDISC         UCPD_SR_HRSTDISC              /*!< HRST discarded interrupt                       */
00101 #define LL_UCPD_SR_HRSTSENT         UCPD_SR_HRSTSENT              /*!< HRST sent interrupt                            */
00102 #define LL_UCPD_SR_TXUND            UCPD_SR_TXUND                 /*!< Tx data underrun condition interrupt           */
00103 #define LL_UCPD_SR_RXNE             UCPD_SR_RXNE                  /*!< Receive data register not empty interrupt      */
00104 #define LL_UCPD_SR_RXORDDET         UCPD_SR_RXORDDET              /*!< Rx ordered set (4 K-codes) detected interrupt  */
00105 #define LL_UCPD_SR_RXHRSTDET        UCPD_SR_RXHRSTDET             /*!< Rx Hard Reset detect interrupt                 */
00106 #define LL_UCPD_SR_RXOVR            UCPD_SR_RXOVR                 /*!< Rx data overflow interrupt                     */
00107 #define LL_UCPD_SR_RXMSGEND         UCPD_SR_RXMSGEND              /*!< Rx message received                            */
00108 #define LL_UCPD_SR_RXERR            UCPD_SR_RXERR                 /*!< Rx error                                       */
00109 #define LL_UCPD_SR_TYPECEVT1        UCPD_SR_TYPECEVT1             /*!< Type C voltage level event on CC1              */
00110 #define LL_UCPD_SR_TYPECEVT2        UCPD_SR_TYPECEVT2             /*!< Type C voltage level event on CC2              */
00111 #define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1      /*!<Status of DC level on CC1 pin                   */
00112 #define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2      /*!<Status of DC level on CC2 pin                   */
00113 #define LL_UCPD_SR_FRSEVT           UCPD_SR_FRSEVT                /*!<Fast Role Swap detection event                  */
00114
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup UCPD_LL_EC_IT IT Defines
00120   * @brief    IT defines which can be used with LL_UCPD_ReadReg and  LL_UCPD_WriteReg functions
00121   * @{
00122   */
00123 #define LL_UCPD_IMR_TXIS             UCPD_IMR_TXISIE              /*!< Enable transmit interrupt status                     */
00124 #define LL_UCPD_IMR_TXMSGDISC        UCPD_IMR_TXMSGDISCIE         /*!< Enable transmit message discarded interrupt          */
00125 #define LL_UCPD_IMR_TXMSGSENT        UCPD_IMR_TXMSGSENTIE         /*!< Enable transmit message sent interrupt               */
00126 #define LL_UCPD_IMR_TXMSGABT         UCPD_IMR_TXMSGABTIE          /*!< Enable transmit message abort interrupt              */
00127 #define LL_UCPD_IMR_HRSTDISC         UCPD_IMR_HRSTDISCIE          /*!< Enable HRST discarded interrupt                      */
00128 #define LL_UCPD_IMR_HRSTSENT         UCPD_IMR_HRSTSENTIE          /*!< Enable HRST sent interrupt                           */
00129 #define LL_UCPD_IMR_TXUND            UCPD_IMR_TXUNDIE             /*!< Enable tx data underrun condition interrupt          */
00130 #define LL_UCPD_IMR_RXNE             UCPD_IMR_RXNEIE              /*!< Enable Receive data register not empty interrupt     */
00131 #define LL_UCPD_IMR_RXORDDET         UCPD_IMR_RXORDDETIE          /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
00132 #define LL_UCPD_IMR_RXHRSTDET        UCPD_IMR_RXHRSTDETIE         /*!< Enable Rx Hard Reset detect interrupt                */
00133 #define LL_UCPD_IMR_RXOVR            UCPD_IMR_RXOVRIE             /*!< Enable Rx data overflow interrupt                    */
00134 #define LL_UCPD_IMR_RXMSGEND         UCPD_IMR_RXMSGENDIE          /*!< Enable Rx message received                           */
00135 #define LL_UCPD_IMR_TYPECEVT1        UCPD_IMR_TYPECEVT1IE         /*!< Enable Type C voltage level event on CC1             */
00136 #define LL_UCPD_IMR_TYPECEVT2        UCPD_IMR_TYPECEVT2IE         /*!< Enable Type C voltage level event on CC2             */
00137 #define LL_UCPD_IMR_FRSEVT           UCPD_IMR_FRSEVTIE            /*!< Enable fast Role Swap detection event                */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup UCPD_LL_EC_ORDERSET Ordered sets value
00144   * @brief    definition of the usual Ordered sets
00145   * @{
00146   */
00147 #define LL_UCPD_SYNC1 0x18u                                       /*!< K-code for Startsynch #1                             */
00148 #define LL_UCPD_SYNC2 0x11u                                       /*!< K-code for Startsynch #2                             */
00149 #define LL_UCPD_SYNC3 0x06u                                       /*!< K-code for Startsynch #3                             */
00150 #define LL_UCPD_RST1  0x07u                                       /*!< K-code for Hard Reset #1                             */
00151 #define LL_UCPD_RST2  0x19u                                       /*!< K-code for Hard Reset #2                             */
00152 #define LL_UCPD_EOP   0x0Du                                       /*!< K-code for EOP End of Packet                         */
00153
00154 #define LL_UCPD_ORDERED_SET_SOP         (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP Ordered set coding         */
00155 #define LL_UCPD_ORDERED_SET_SOP1        (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Ordered set coding        */
00156 #define LL_UCPD_ORDERED_SET_SOP2        (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP'' Ordered set coding       */
00157 #define LL_UCPD_ORDERED_SET_HARD_RESET  (LL_UCPD_RST1  | (LL_UCPD_RST1<<5u)  | (LL_UCPD_RST1<<10u)  | (LL_UCPD_RST2<<15u )) /*!< Hard Reset Ordered set coding  */
00158 #define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1  | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u)  | (LL_UCPD_SYNC3<<15u)) /*!< Cable Reset Ordered set coding */
00159 #define LL_UCPD_ORDERED_SET_SOP1_DEBUG  (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u)  | (LL_UCPD_RST2<<10u)  | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Debug Ordered set coding  */
00160 #define LL_UCPD_ORDERED_SET_SOP2_DEBUG  (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u)  | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP'' Debug Ordered set coding */
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup UCPD_LL_EC_MODE Role Mode
00166   * @{
00167   */
00168 #define LL_UCPD_ROLE_SNK             UCPD_CR_ANAMODE              /*!< Mode SNK Rd                                    */
00169 #define LL_UCPD_ROLE_SRC             0x0U                         /*!< Mode SRC Rp                                    */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup UCPD_LL_EC_RESISTOR Resistor value
00175   * @{
00176   */
00177 #define LL_UCPD_RESISTOR_DEFAULT    UCPD_CR_ANASUBMODE_0          /*!< Rp default                                     */
00178 #define LL_UCPD_RESISTOR_1_5A       UCPD_CR_ANASUBMODE_1          /*!< Rp 1.5 A                                       */
00179 #define LL_UCPD_RESISTOR_3_0A       UCPD_CR_ANASUBMODE            /*!< Rp 3.0 A                                       */
00180 #define LL_UCPD_RESISTOR_NONE       0x0U                          /*!< No resistor                                    */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup UCPD_LL_EC_CFG1_ORDERSET ordered set configuration
00186   * @{
00187   */
00188 #define LL_UCPD_ORDERSET_SOP         UCPD_CFG1_RXORDSETEN_0       /*!< SOP Ordered set detection enabled              */
00189 #define LL_UCPD_ORDERSET_SOP1        UCPD_CFG1_RXORDSETEN_1       /*!< SOP' Ordered set detection enabled             */
00190 #define LL_UCPD_ORDERSET_SOP2        UCPD_CFG1_RXORDSETEN_2       /*!< SOP'' Ordered set detection enabled            */
00191 #define LL_UCPD_ORDERSET_HARDRST     UCPD_CFG1_RXORDSETEN_3       /*!< Hard Reset Ordered set detection enabled       */
00192 #define LL_UCPD_ORDERSET_CABLERST    UCPD_CFG1_RXORDSETEN_4       /*!< Cable Reset Ordered set detection enabled      */
00193 #define LL_UCPD_ORDERSET_SOP1_DEBUG  UCPD_CFG1_RXORDSETEN_5       /*!< SOP' Debug Ordered set detection enabled       */
00194 #define LL_UCPD_ORDERSET_SOP2_DEBUG  UCPD_CFG1_RXORDSETEN_6       /*!< SOP'' Debug Ordered set detection enabled      */
00195 #define LL_UCPD_ORDERSET_SOP_EXT1    UCPD_CFG1_RXORDSETEN_7       /*!< SOP extension#1 Ordered set detection enabled  */
00196 #define LL_UCPD_ORDERSET_SOP_EXT2    UCPD_CFG1_RXORDSETEN_8       /*!< SOP extension#2 Ordered set detection enabled  */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup UCPD_LL_EC_CCxEVT  CCx event
00202   * @{
00203   */
00204 #define LL_UCPD_SNK_CC1_VOPEN      0x00u                                                      /*!< CC1 Sink Open state              */
00205 #define LL_UCPD_SNK_CC1_VRP        UCPD_SR_TYPEC_VSTATE_CC1_0                                 /*!< CC1 Sink vRP default state       */
00206 #define LL_UCPD_SNK_CC1_VRP15A     UCPD_SR_TYPEC_VSTATE_CC1_1                                 /*!< CC1 Sink vRP 1.5A state          */
00207 #define LL_UCPD_SNK_CC1_VRP30A     (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)  /*!< CC1 Sink vRP 3.0A state          */
00208
00209 #define LL_UCPD_SNK_CC2_VOPEN      0x00u                                                      /*!< CC2 Sink Open state              */
00210 #define LL_UCPD_SNK_CC2_VRP        UCPD_SR_TYPEC_VSTATE_CC2_0                                 /*!< CC2 Sink vRP default state       */
00211 #define LL_UCPD_SNK_CC2_VRP15A     UCPD_SR_TYPEC_VSTATE_CC2_1                                 /*!< CC2 Sink vRP 1.5A state          */
00212 #define LL_UCPD_SNK_CC2_VRP30A     (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)  /*!< CC2 Sink vRP 3.0A state          */
00213
00214 #define LL_UCPD_SRC_CC1_VRA        0x0U                                                      /*!< CC1 Source vRA state              */
00215 #define LL_UCPD_SRC_CC1_VRD        UCPD_SR_TYPEC_VSTATE_CC1_0                                /*!< CC1 Source vRD state              */
00216 #define LL_UCPD_SRC_CC1_OPEN       UCPD_SR_TYPEC_VSTATE_CC1_1                                /*!< CC1 Source Open state             */
00217
00218 #define LL_UCPD_SRC_CC2_VRA        0x0U                                                      /*!< CC2 Source vRA state              */
00219 #define LL_UCPD_SRC_CC2_VRD        UCPD_SR_TYPEC_VSTATE_CC2_0                                /*!< CC2 Source vRD state              */
00220 #define LL_UCPD_SRC_CC2_OPEN       UCPD_SR_TYPEC_VSTATE_CC2_1                                /*!< CC2 Source Open state             */
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
00226   * @{
00227   */
00228 #define LL_UCPD_PSC_DIV1            0x0u                                                     /*!< Bypass pre-scaling / divide by 1  */
00229 #define LL_UCPD_PSC_DIV2            UCPD_CFG1_PSC_UCPDCLK_0                                  /*!< Pre-scale clock by dividing by 2  */
00230 #define LL_UCPD_PSC_DIV4            UCPD_CFG1_PSC_UCPDCLK_1                                  /*!< Pre-scale clock by dividing by 4  */
00231 #define LL_UCPD_PSC_DIV8            (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)      /*!< Pre-scale clock by dividing by 8  */
00232 #define LL_UCPD_PSC_DIV16           UCPD_CFG1_PSC_UCPDCLK_2                                  /*!< Pre-scale clock by dividing by 16 */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup UCPD_LL_EC_CCENABLE CC pin enable
00238   * @{
00239   */
00240 #define LL_UCPD_CCENABLE_NONE       0x0U                                                     /*!< Neither PHY is activated (e.g. disabled state of source)          */
00241 #define LL_UCPD_CCENABLE_CC1        UCPD_CR_CCENABLE_0                                       /*!< Controls apply to only CC1                                        */
00242 #define LL_UCPD_CCENABLE_CC2        UCPD_CR_CCENABLE_1                                       /*!< Controls apply to only CC1                                        */
00243 #define LL_UCPD_CCENABLE_CC1CC2     (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)                /*!< Controls apply to both CC1 and CC2 (normal usage for sink/source) */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup UCPD_LL_EC_CCPIN CC pin selection
00249   * @{
00250   */
00251 #define LL_UCPD_CCPIN_CC1           0x0U                    /*!< Use CC1 IO for power delivery communication              */
00252 #define LL_UCPD_CCPIN_CC2           UCPD_CR_PHYCCSEL        /*!< Use CC2 IO for power delivery communication              */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup UCPD_LL_EC_RXMODE Receiver mode
00258   * @{
00259   */
00260 #define LL_UCPD_RXMODE_NORMAL           0x0U                /*!< Normal receive mode                                      */
00261 #define LL_UCPD_RXMODE_BIST_TEST_DATA   UCPD_CR_RXMODE      /*!< BIST receive mode (BIST Test Data Mode)                  */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup UCPD_LL_EC_TXMODE Type of Tx packet
00267   * @{
00268   */
00269 #define LL_UCPD_TXMODE_NORMAL           0x0U                /*!< Initiate the transfer of a Tx message                    */
00270 #define LL_UCPD_TXMODE_CABLE_RESET      UCPD_CR_TXMODE_0    /*!< Trigger a the transfer of a Cable Reset sequence         */
00271 #define LL_UCPD_TXMODE_BIST_CARRIER2    UCPD_CR_TXMODE_1    /*!< Trigger a BIST test sequence send (BIST Carrier Mode 2)  */
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup UCPD_LL_EC_RXORDSET Rx ordered set code detected
00277   * @{
00278   */
00279 #define LL_UCPD_RXORDSET_SOP             0x0U                                                                                 /*!< SOP code detected in receiver              */
00280 #define LL_UCPD_RXORDSET_SOP1            UCPD_RX_ORDSET_RXORDSET_0                                                            /*!< SOP' code detected in receiver             */
00281 #define LL_UCPD_RXORDSET_SOP2            UCPD_RX_ORDSET_RXORDSET_1                                                            /*!< SOP'' code detected in receiver            */
00282 #define LL_UCPD_RXORDSET_SOP1_DEBUG      (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)                              /*!< SOP' Debug code detected in receiver       */
00283 #define LL_UCPD_RXORDSET_SOP2_DEBUG      UCPD_RX_ORDSET_RXORDSET_2                                                            /*!< SOP'' Debug code detected in receiver      */
00284 #define LL_UCPD_RXORDSET_CABLE_RESET     (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)                              /*!< Cable Reset code detected in receiver      */
00285 #define LL_UCPD_RXORDSET_SOPEXT1         (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)                              /*!< SOP extension#1 code detected in receiver  */
00286 #define LL_UCPD_RXORDSET_SOPEXT2         (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)  /*!< SOP extension#2 code detected in receiver  */
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 /* Exported macro ------------------------------------------------------------*/
00296 /** @defgroup UCPD_LL_Exported_Macros UCPD Exported Macros
00297   * @{
00298   */
00299
00300 /** @defgroup UCPD_LL_EM_WRITE_READ Common Write and read registers Macros
00301   * @{
00302   */
00303
00304 /**
00305   * @brief  Write a value in UCPD register
00306   * @param  __INSTANCE__ UCPD Instance
00307   * @param  __REG__ Register to be written
00308   * @param  __VALUE__ Value to be written in the register
00309   * @retval None
00310   */
00311 #define LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00312
00313 /**
00314   * @brief  Read a value in UCPD register
00315   * @param  __INSTANCE__ UCPD Instance
00316   * @param  __REG__ Register to be read
00317   * @retval Register value
00318   */
00319 #define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 /* Exported functions --------------------------------------------------------*/
00329 /** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
00330   * @{
00331   */
00332
00333 /** @defgroup UCPD_LL_EF_Configuration Configuration
00334   * @{
00335   */
00336
00337 /** @defgroup UCPD_LL_EF_CFG1 CFG1 register
00338   * @{
00339   */
00340 /**
00341   * @brief  Enable UCPD peripheral
00342   * @rmtoll CFG1          UCPDEN           LL_UCPD_Enable
00343   * @param  UCPDx UCPD Instance
00344   * @retval None
00345   */
00346 __STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
00347 {
00348   SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
00349 }
00350
00351 /**
00352   * @brief  Disable UCPD peripheral
00353   * @note   When disabling the UCPD, follow the procedure described in the Reference Manual.
00354   * @rmtoll CFG1          UCPDEN           LL_UCPD_Disable
00355   * @param  UCPDx UCPD Instance
00356   * @retval None
00357   */
00358 __STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
00359 {
00360   CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
00361 }
00362
00363 /**
00364   * @brief  Check if UCPD peripheral is enabled
00365   * @rmtoll CFG1          UCPDEN           LL_UCPD_IsEnabled
00366   * @param  UCPDx UCPD Instance
00367   * @retval State of bit (1 or 0).
00368   */
00369 __STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx)
00370 {
00371   return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
00372 }
00373
00374 /**
00375   * @brief  Set the receiver ordered set detection enable
00376   * @rmtoll CFG1          RXORDSETEN          LL_UCPD_SetRxOrderSet
00377   * @param  UCPDx UCPD Instance
00378   * @param  OrderSet This parameter can be combination of the following values:
00379   *         @arg @ref LL_UCPD_ORDERSET_SOP
00380   *         @arg @ref LL_UCPD_ORDERSET_SOP1
00381   *         @arg @ref LL_UCPD_ORDERSET_SOP2
00382   *         @arg @ref LL_UCPD_ORDERSET_HARDRST
00383   *         @arg @ref LL_UCPD_ORDERSET_CABLERST
00384   *         @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
00385   *         @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
00386   *         @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
00387   *         @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
00388   * @retval None
00389   */
00390 __STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
00391 {
00392   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
00393 }
00394
00395 /**
00396   * @brief  Set the prescaler for ucpd clock
00397   * @rmtoll CFG1          UCPDCLK          LL_UCPD_SetPSCClk
00398   * @param  UCPDx UCPD Instance
00399   * @param  Psc This parameter can be one of the following values:
00400   *         @arg @ref LL_UCPD_PSC_DIV1
00401   *         @arg @ref LL_UCPD_PSC_DIV2
00402   *         @arg @ref LL_UCPD_PSC_DIV4
00403   *         @arg @ref LL_UCPD_PSC_DIV8
00404   *         @arg @ref LL_UCPD_PSC_DIV16
00405   * @retval None
00406   */
00407 __STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
00408 {
00409   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
00410 }
00411
00412 /**
00413   * @brief  Set the number of cycles (minus 1) of the half bit clock
00414   * @rmtoll CFG1          TRANSWIN          LL_UCPD_SetTransWin
00415   * @param  UCPDx UCPD Instance
00416   * @param  TransWin a value between Min_Data=0x1 and Max_Data=0x1F
00417   * @retval None
00418   */
00419 __STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
00420 {
00421   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
00422 }
00423
00424 /**
00425   * @brief  Set the clock divider value to generate an interframe gap
00426   * @rmtoll CFG1          IFRGAP          LL_UCPD_SetIfrGap
00427   * @param  UCPDx UCPD Instance
00428   * @param  IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
00429   * @retval None
00430   */
00431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
00432 {
00433   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
00434 }
00435
00436 /**
00437   * @brief  Set the clock divider value to generate an interframe gap
00438   * @rmtoll CFG1          HBITCLKDIV          LL_UCPD_SetHbitClockDiv
00439   * @param  UCPDx UCPD Instance
00440   * @param  HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
00441   * @retval None
00442   */
00443 __STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
00444 {
00445   MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
00446 }
00447
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup UCPD_LL_EF_CFG2 CFG2 register
00453   * @{
00454   */
00455
00456 /**
00457   * @brief  Enable the wakeup mode
00458   * @rmtoll CFG2          WUPEN          LL_UCPD_WakeUpEnable
00459   * @param  UCPDx UCPD Instance
00460   * @retval None
00461   */
00462 __STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
00463 {
00464   SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
00465 }
00466
00467 /**
00468   * @brief  Disable the wakeup mode
00469   * @rmtoll CFG2          WUPEN          LL_UCPD_WakeUpDisable
00470   * @param  UCPDx UCPD Instance
00471   * @retval None
00472   */
00473 __STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
00474 {
00475   CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
00476 }
00477
00478 /**
00479   * @brief  Force clock enable
00480   * @rmtoll CFG2          FORCECLK          LL_UCPD_ForceClockEnable
00481   * @param  UCPDx UCPD Instance
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
00485 {
00486   SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
00487 }
00488
00489 /**
00490   * @brief  Force clock disable
00491   * @rmtoll CFG2          FORCECLK          LL_UCPD_ForceClockDisable
00492   * @param  UCPDx UCPD Instance
00493   * @retval None
00494   */
00495 __STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
00496 {
00497   CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
00498 }
00499
00500 /**
00501   * @brief  RxFilter enable
00502   * @rmtoll CFG2          RXFILTDIS          LL_UCPD_RxFilterEnable
00503   * @param  UCPDx UCPD Instance
00504   * @retval None
00505   */
00506 __STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
00507 {
00508   CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
00509 }
00510
00511 /**
00512   * @brief  RxFilter disable
00513   * @rmtoll CFG2          RXFILTDIS          LL_UCPD_RxFilterDisable
00514   * @param  UCPDx UCPD Instance
00515   * @retval None
00516   */
00517 __STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
00518 {
00519   SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
00520 }
00521
00522 /**
00523   * @}
00524   */
00525
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup UCPD_LL_EF_CR CR register
00531   * @{
00532   */
00533 /**
00534   * @brief  Type C detector for CC2 enable
00535   * @rmtoll CR          CC2TCDIS          LL_UCPD_TypeCDetectionCC2Enable
00536   * @param  UCPDx UCPD Instance
00537   * @retval None
00538   */
00539 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
00540 {
00541   CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
00542 }
00543
00544 /**
00545   * @brief  Type C detector for CC2 disable
00546   * @rmtoll CR          CC2TCDIS          LL_UCPD_TypeCDetectionCC2Disable
00547   * @param  UCPDx UCPD Instance
00548   * @retval None
00549   */
00550 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
00551 {
00552   SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
00553 }
00554
00555 /**
00556   * @brief  Type C detector for CC1 enable
00557   * @rmtoll CR          CC1TCDIS          LL_UCPD_TypeCDetectionCC1Enable
00558   * @param  UCPDx UCPD Instance
00559   * @retval None
00560   */
00561 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
00562 {
00563   CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
00564 }
00565
00566 /**
00567   * @brief  Type C detector for CC1 disable
00568   * @rmtoll CR          CC1TCDIS          LL_UCPD_TypeCDetectionCC1Disable
00569   * @param  UCPDx UCPD Instance
00570   * @retval None
00571   */
00572 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
00573 {
00574   SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
00575 }
00576
00577 /**
00578   * @brief  Source Vconn discharge enable
00579   * @rmtoll CR          RDCH          LL_UCPD_VconnDischargeEnable
00580   * @param  UCPDx UCPD Instance
00581   * @retval None
00582   */
00583 __STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
00584 {
00585   SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
00586 }
00587
00588 /**
00589   * @brief  Source Vconn discharge disable
00590   * @rmtoll CR          RDCH          LL_UCPD_VconnDischargeDisable
00591   * @param  UCPDx UCPD Instance
00592   * @retval None
00593   */
00594 __STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
00595 {
00596   CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
00597 }
00598
00599 /**
00600   * @brief  Signal Fast Role Swap request
00601   * @rmtoll CR          FRSTX          LL_UCPD_VconnDischargeDisable
00602   * @param  UCPDx UCPD Instance
00603   * @retval None
00604   */
00605 __STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
00606 {
00607   SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
00608 }
00609
00610 /**
00611   * @brief  Fast Role swap RX detection enable
00612   * @rmtoll CR          FRSRXEN          LL_UCPD_FRSDetectionEnable
00613   * @param  UCPDx UCPD Instance
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx)
00617 {
00618   SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
00619 }
00620
00621 /**
00622   * @brief  Fast Role swap RX detection disable
00623   * @rmtoll CR          FRSRXEN          LL_UCPD_FRSDetectionDisable
00624   * @param  UCPDx UCPD Instance
00625   * @retval None
00626   */
00627 __STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx)
00628 {
00629   CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
00630 }
00631
00632 /**
00633   * @brief  Set cc enable
00634   * @rmtoll CR          CC1VCONNEN          LL_UCPD_SetccEnable
00635   * @param  UCPDx UCPD Instance
00636   * @param  CCEnable This parameter can be one of the following values:
00637   *         @arg @ref LL_UCPD_CCENABLE_NONE
00638   *         @arg @ref LL_UCPD_CCENABLE_CC1
00639   *         @arg @ref LL_UCPD_CCENABLE_CC2
00640   *         @arg @ref LL_UCPD_CCENABLE_CC1CC2
00641   * @retval None
00642   */
00643 __STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
00644 {
00645   MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
00646 }
00647
00648 /**
00649   * @brief  Set UCPD SNK role
00650   * @rmtoll CR        ANAMODE          LL_UCPD_SetSNKRole
00651   * @param  UCPDx UCPD Instance
00652   * @retval None
00653   */
00654 __STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
00655 {
00656   SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
00657 }
00658
00659 /**
00660   * @brief  Set UCPD SRC role
00661   * @rmtoll CR        ANAMODE          LL_UCPD_SetSRCRole
00662   * @param  UCPDx UCPD Instance
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
00666 {
00667   CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
00668 }
00669
00670 /**
00671   * @brief  Get UCPD Role
00672   * @rmtoll CR          ANAMODE          LL_UCPD_GetRole
00673   * @param  UCPDx UCPD Instance
00674   * @retval Returned value can be one of the following values:
00675   *         @arg @ref LL_UCPD_ROLE_SNK
00676   *         @arg @ref LL_UCPD_ROLE_SRC
00677   */
00678 __STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx)
00679 {
00680   return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
00681 }
00682
00683 /**
00684   * @brief  Set Rp resistor
00685   * @rmtoll CR        ANASUBMODE          LL_UCPD_SetRpResistor
00686   * @param  UCPDx UCPD Instance
00687   * @param  Resistor This parameter can be one of the following values:
00688   *         @arg @ref LL_UCPD_RESISTOR_DEFAULT
00689   *         @arg @ref LL_UCPD_RESISTOR_1_5A
00690   *         @arg @ref LL_UCPD_RESISTOR_3_0A
00691   *         @arg @ref LL_UCPD_RESISTOR_NONE
00692   * @retval None
00693   */
00694 __STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
00695 {
00696   MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE,  Resistor);
00697 }
00698
00699 /**
00700   * @brief  Set CC pin
00701   * @rmtoll CR        PHYCCSEL          LL_UCPD_SetCCPin
00702   * @param  UCPDx UCPD Instance
00703   * @param  CCPin This parameter can be one of the following values:
00704   *         @arg @ref LL_UCPD_CCPIN_CC1
00705   *         @arg @ref LL_UCPD_CCPIN_CC2
00706   * @retval None
00707   */
00708 __STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
00709 {
00710   MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL,  CCPin);
00711 }
00712
00713 /**
00714   * @brief  Rx enable
00715   * @rmtoll CR        PHYRXEN          LL_UCPD_RxEnable
00716   * @param  UCPDx UCPD Instance
00717   * @retval None
00718   */
00719 __STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
00720 {
00721   SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
00722 }
00723
00724 /**
00725   * @brief  Rx disable
00726   * @rmtoll CR        PHYRXEN          LL_UCPD_RxDisable
00727   * @param  UCPDx UCPD Instance
00728   * @retval None
00729   */
00730 __STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
00731 {
00732   CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
00733 }
00734
00735 /**
00736   * @brief  Set Rx mode
00737   * @rmtoll CR        RXMODE          LL_UCPD_SetRxMode
00738   * @param  UCPDx UCPD Instance
00739   * @param  RxMode This parameter can be one of the following values:
00740   *         @arg @ref LL_UCPD_RXMODE_NORMAL
00741   *         @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
00742   * @retval None
00743   */
00744 __STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
00745 {
00746   MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
00747 }
00748
00749 /**
00750   * @brief  Send Hard Reset
00751   * @rmtoll CR        TXHRST          LL_UCPD_SendHardReset
00752   * @param  UCPDx UCPD Instance
00753   * @retval None
00754   */
00755 __STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
00756 {
00757   SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
00758 }
00759
00760 /**
00761   * @brief  Send message
00762   * @rmtoll CR        TXSEND          LL_UCPD_SendMessage
00763   * @param  UCPDx UCPD Instance
00764   * @retval None
00765   */
00766 __STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
00767 {
00768   SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
00769 }
00770
00771 /**
00772   * @brief  Set Tx mode
00773   * @rmtoll CR        TXMODE          LL_UCPD_SetTxMode
00774   * @param  UCPDx UCPD Instance
00775   * @param  TxMode This parameter can be one of the following values:
00776   *         @arg @ref LL_UCPD_TXMODE_NORMAL
00777   *         @arg @ref LL_UCPD_TXMODE_CABLE_RESET
00778   *         @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
00779   * @retval None
00780   */
00781 __STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
00782 {
00783   MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
00784 }
00785
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
00791   * @{
00792   */
00793
00794 /**
00795   * @brief  Enable FRS interrupt
00796   * @rmtoll IMR          FRSEVTIE         LL_UCPD_EnableIT_FRS
00797   * @param  UCPDx UCPD Instance
00798   * @retval None
00799   */
00800 __STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx)
00801 {
00802   SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
00803 }
00804
00805 /**
00806   * @brief  Enable type c event on CC2
00807   * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_EnableIT_TypeCEventCC2
00808   * @param  UCPDx UCPD Instance
00809   * @retval None
00810   */
00811 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
00812 {
00813   SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
00814 }
00815
00816 /**
00817   * @brief  Enable type c event on CC1
00818   * @rmtoll IMR          TYPECEVT1IE        LL_UCPD_EnableIT_TypeCEventCC1
00819   * @param  UCPDx UCPD Instance
00820   * @retval None
00821   */
00822 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
00823 {
00824   SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
00825 }
00826
00827 /**
00828   * @brief  Enable Rx message end interrupt
00829   * @rmtoll IMR          RXMSGENDIE         LL_UCPD_EnableIT_RxMsgEnd
00830   * @param  UCPDx UCPD Instance
00831   * @retval None
00832   */
00833 __STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
00834 {
00835   SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
00836 }
00837
00838 /**
00839   * @brief  Enable Rx overrun interrupt
00840   * @rmtoll IMR          RXOVRIE         LL_UCPD_EnableIT_RxOvr
00841   * @param  UCPDx UCPD Instance
00842   * @retval None
00843   */
00844 __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
00845 {
00846   SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
00847 }
00848
00849 /**
00850   * @brief  Enable Rx hard resrt interrupt
00851   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_EnableIT_RxHRST
00852   * @param  UCPDx UCPD Instance
00853   * @retval None
00854   */
00855 __STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
00856 {
00857   SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
00858 }
00859
00860 /**
00861   * @brief  Enable Rx orderset interrupt
00862   * @rmtoll IMR          RXORDDETIE         LL_UCPD_EnableIT_RxOrderSet
00863   * @param  UCPDx UCPD Instance
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
00867 {
00868   SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
00869 }
00870
00871 /**
00872   * @brief  Enable Rx non empty interrupt
00873   * @rmtoll IMR          RXNEIE         LL_UCPD_EnableIT_RxNE
00874   * @param  UCPDx UCPD Instance
00875   * @retval None
00876   */
00877 __STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
00878 {
00879   SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
00880 }
00881
00882 /**
00883   * @brief  Enable TX underrun interrupt
00884   * @rmtoll IMR          TXUNDIE         LL_UCPD_EnableIT_TxUND
00885   * @param  UCPDx UCPD Instance
00886   * @retval None
00887   */
00888 __STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
00889 {
00890   SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
00891 }
00892
00893 /**
00894   * @brief  Enable hard reset sent interrupt
00895   * @rmtoll IMR          HRSTSENTIE         LL_UCPD_EnableIT_TxHRSTSENT
00896   * @param  UCPDx UCPD Instance
00897   * @retval None
00898   */
00899 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
00900 {
00901   SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
00902 }
00903
00904 /**
00905   * @brief  Enable hard reset discard interrupt
00906   * @rmtoll IMR          HRSTDISCIE         LL_UCPD_EnableIT_TxHRSTDISC
00907   * @param  UCPDx UCPD Instance
00908   * @retval None
00909   */
00910 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
00911 {
00912   SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
00913 }
00914
00915 /**
00916   * @brief  Enable Tx message abort interrupt
00917   * @rmtoll IMR          TXMSGABTIE         LL_UCPD_EnableIT_TxMSGABT
00918   * @param  UCPDx UCPD Instance
00919   * @retval None
00920   */
00921 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
00922 {
00923   SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
00924 }
00925
00926 /**
00927   * @brief  Enable Tx message sent interrupt
00928   * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_EnableIT_TxMSGSENT
00929   * @param  UCPDx UCPD Instance
00930   * @retval None
00931   */
00932 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
00933 {
00934   SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
00935 }
00936
00937 /**
00938   * @brief  Enable Tx message discarded interrupt
00939   * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_EnableIT_TxMSGDISC
00940   * @param  UCPDx UCPD Instance
00941   * @retval None
00942   */
00943 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
00944 {
00945   SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
00946 }
00947
00948 /**
00949   * @brief  Enable Tx data receive interrupt
00950   * @rmtoll IMR          TXISIE         LL_UCPD_EnableIT_TxIS
00951   * @param  UCPDx UCPD Instance
00952   * @retval None
00953   */
00954 __STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
00955 {
00956   SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
00957 }
00958
00959 /**
00960   * @brief  Disable FRS interrupt
00961   * @rmtoll IMR          FRSEVTIE         LL_UCPD_DisableIT_FRS
00962   * @param  UCPDx UCPD Instance
00963   * @retval None
00964   */
00965 __STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx)
00966 {
00967   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
00968 }
00969
00970 /**
00971   * @brief  Disable type c event on CC2
00972   * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_DisableIT_TypeCEventCC2
00973   * @param  UCPDx UCPD Instance
00974   * @retval None
00975   */
00976 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
00977 {
00978   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
00979 }
00980
00981 /**
00982   * @brief  Disable type c event on CC1
00983   * @rmtoll IMR          TYPECEVT1IE        LL_UCPD_DisableIT_TypeCEventCC1
00984   * @param  UCPDx UCPD Instance
00985   * @retval None
00986   */
00987 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
00988 {
00989   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
00990 }
00991
00992 /**
00993   * @brief  Disable Rx message end interrupt
00994   * @rmtoll IMR          RXMSGENDIE         LL_UCPD_DisableIT_RxMsgEnd
00995   * @param  UCPDx UCPD Instance
00996   * @retval None
00997   */
00998 __STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
00999 {
01000   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
01001 }
01002
01003 /**
01004   * @brief  Disable Rx overrun interrupt
01005   * @rmtoll IMR          RXOVRIE         LL_UCPD_DisableIT_RxOvr
01006   * @param  UCPDx UCPD Instance
01007   * @retval None
01008   */
01009 __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
01010 {
01011   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
01012 }
01013
01014 /**
01015   * @brief  Disable Rx hard resrt interrupt
01016   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_DisableIT_RxHRST
01017   * @param  UCPDx UCPD Instance
01018   * @retval None
01019   */
01020 __STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
01021 {
01022   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
01023 }
01024
01025 /**
01026   * @brief  Disable Rx orderset interrupt
01027   * @rmtoll IMR          RXORDDETIE         LL_UCPD_DisableIT_RxOrderSet
01028   * @param  UCPDx UCPD Instance
01029   * @retval None
01030   */
01031 __STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
01032 {
01033   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
01034 }
01035
01036 /**
01037   * @brief  Disable Rx non empty interrupt
01038   * @rmtoll IMR          RXNEIE         LL_UCPD_DisableIT_RxNE
01039   * @param  UCPDx UCPD Instance
01040   * @retval None
01041   */
01042 __STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
01043 {
01044   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
01045 }
01046
01047 /**
01048   * @brief  Disable TX underrun interrupt
01049   * @rmtoll IMR          TXUNDIE         LL_UCPD_DisableIT_TxUND
01050   * @param  UCPDx UCPD Instance
01051   * @retval None
01052   */
01053 __STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
01054 {
01055   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
01056 }
01057
01058 /**
01059   * @brief  Disable hard reset sent interrupt
01060   * @rmtoll IMR          HRSTSENTIE         LL_UCPD_DisableIT_TxHRSTSENT
01061   * @param  UCPDx UCPD Instance
01062   * @retval None
01063   */
01064 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
01065 {
01066   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
01067 }
01068
01069 /**
01070   * @brief  Disable hard reset discard interrupt
01071   * @rmtoll IMR          HRSTDISCIE         LL_UCPD_DisableIT_TxHRSTDISC
01072   * @param  UCPDx UCPD Instance
01073   * @retval None
01074   */
01075 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
01076 {
01077   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
01078 }
01079
01080 /**
01081   * @brief  Disable Tx message abort interrupt
01082   * @rmtoll IMR          TXMSGABTIE         LL_UCPD_DisableIT_TxMSGABT
01083   * @param  UCPDx UCPD Instance
01084   * @retval None
01085   */
01086 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
01087 {
01088   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
01089 }
01090
01091 /**
01092   * @brief  Disable Tx message sent interrupt
01093   * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_DisableIT_TxMSGSENT
01094   * @param  UCPDx UCPD Instance
01095   * @retval None
01096   */
01097 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
01098 {
01099   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
01100 }
01101
01102 /**
01103   * @brief  Disable Tx message discarded interrupt
01104   * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_DisableIT_TxMSGDISC
01105   * @param  UCPDx UCPD Instance
01106   * @retval None
01107   */
01108 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
01109 {
01110   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
01111 }
01112
01113 /**
01114   * @brief  Disable Tx data receive interrupt
01115   * @rmtoll IMR          TXISIE         LL_UCPD_DisableIT_TxIS
01116   * @param  UCPDx UCPD Instance
01117   * @retval None
01118   */
01119 __STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
01120 {
01121   CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
01122 }
01123
01124 /**
01125   * @brief  Check if FRS interrupt enabled
01126   * @rmtoll IMR          FRSEVTIE         LL_UCPD_DisableIT_FRS
01127   * @param  UCPDx UCPD Instance
01128   * @retval State of bit (1 or 0).
01129   */
01130 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx)
01131 {
01132   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL);
01133 }
01134
01135 /**
01136   * @brief  Check if type c event on CC2 enabled
01137   * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_DisableIT_TypeCEventCC2
01138   * @param  UCPDx UCPD Instance
01139   * @retval State of bit (1 or 0).
01140   */
01141 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
01142 {
01143   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
01144 }
01145
01146 /**
01147   * @brief  Check if type c event on CC1 enabled
01148   * @rmtoll IMR2          TYPECEVT1IE        LL_UCPD_IsEnableIT_TypeCEventCC1
01149   * @param  UCPDx UCPD Instance
01150   * @retval State of bit (1 or 0).
01151   */
01152 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
01153 {
01154   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
01155 }
01156
01157 /**
01158   * @brief  Check if Rx message end interrupt enabled
01159   * @rmtoll IMR          RXMSGENDIE         LL_UCPD_IsEnableIT_RxMsgEnd
01160   * @param  UCPDx UCPD Instance
01161   * @retval State of bit (1 or 0).
01162   */
01163 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
01164 {
01165   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
01166 }
01167
01168 /**
01169   * @brief  Check if Rx overrun interrupt enabled
01170   * @rmtoll IMR          RXOVRIE         LL_UCPD_IsEnableIT_RxOvr
01171   * @param  UCPDx UCPD Instance
01172   * @retval State of bit (1 or 0).
01173   */
01174 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx)
01175 {
01176   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
01177 }
01178
01179 /**
01180   * @brief  Check if Rx hard resrt interrupt enabled
01181   * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_IsEnableIT_RxHRST
01182   * @param  UCPDx UCPD Instance
01183   * @retval State of bit (1 or 0).
01184   */
01185 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx)
01186 {
01187   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
01188 }
01189
01190 /**
01191   * @brief  Check if Rx orderset interrupt enabled
01192   * @rmtoll IMR          RXORDDETIE         LL_UCPD_IsEnableIT_RxOrderSet
01193   * @param  UCPDx UCPD Instance
01194   * @retval State of bit (1 or 0).
01195   */
01196 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx)
01197 {
01198   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
01199 }
01200
01201 /**
01202   * @brief  Check if Rx non empty interrupt enabled
01203   * @rmtoll IMR          RXNEIE         LL_UCPD_IsEnableIT_RxNE
01204   * @param  UCPDx UCPD Instance
01205   * @retval State of bit (1 or 0).
01206   */
01207 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx)
01208 {
01209   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
01210 }
01211
01212 /**
01213   * @brief  Check if TX underrun interrupt enabled
01214   * @rmtoll IMR          TXUNDIE         LL_UCPD_IsEnableIT_TxUND
01215   * @param  UCPDx UCPD Instance
01216   * @retval State of bit (1 or 0).
01217   */
01218 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx)
01219 {
01220   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
01221 }
01222
01223 /**
01224   * @brief  Check if hard reset sent interrupt enabled
01225   * @rmtoll IMR          HRSTSENTIE         LL_UCPD_IsEnableIT_TxHRSTSENT
01226   * @param  UCPDx UCPD Instance
01227   * @retval State of bit (1 or 0).
01228   */
01229 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
01230 {
01231   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
01232 }
01233
01234 /**
01235   * @brief  Check if hard reset discard interrupt enabled
01236   * @rmtoll IMR          HRSTDISCIE         LL_UCPD_IsEnableIT_TxHRSTDISC
01237   * @param  UCPDx UCPD Instance
01238   * @retval State of bit (1 or 0).
01239   */
01240 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
01241 {
01242   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
01243 }
01244
01245 /**
01246   * @brief  Check if Tx message abort interrupt enabled
01247   * @rmtoll IMR          TXMSGABTIE         LL_UCPD_IsEnableIT_TxMSGABT
01248   * @param  UCPDx UCPD Instance
01249   * @retval State of bit (1 or 0).
01250   */
01251 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx)
01252 {
01253   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
01254 }
01255
01256 /**
01257   * @brief  Check if Tx message sent interrupt enabled
01258   * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_IsEnableIT_TxMSGSENT
01259   * @param  UCPDx UCPD Instance
01260   * @retval State of bit (1 or 0).
01261   */
01262 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
01263 {
01264   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
01265 }
01266
01267 /**
01268   * @brief  Check if Tx message discarded interrupt enabled
01269   * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_IsEnableIT_TxMSGDISC
01270   * @param  UCPDx UCPD Instance
01271   * @retval State of bit (1 or 0).
01272   */
01273 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
01274 {
01275   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
01276 }
01277
01278 /**
01279   * @brief  Check if Tx data receive interrupt enabled
01280   * @rmtoll IMR          TXISIE         LL_UCPD_IsEnableIT_TxIS
01281   * @param  UCPDx UCPD Instance
01282   * @retval State of bit (1 or 0).
01283   */
01284 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx)
01285 {
01286   return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
01287 }
01288
01289 /**
01290   * @}
01291   */
01292
01293 /** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
01294   * @{
01295   */
01296
01297 /**
01298   * @brief  Clear FRS interrupt
01299   * @rmtoll ICR          FRSEVTIE         LL_UCPD_ClearFlag_FRS
01300   * @param  UCPDx UCPD Instance
01301   * @retval None
01302   */
01303 __STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx)
01304 {
01305   SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF);
01306 }
01307
01308 /**
01309   * @brief  Clear type c event on CC2
01310   * @rmtoll IIMR          TYPECEVT2IE        LL_UCPD_ClearFlag_TypeCEventCC2
01311   * @param  UCPDx UCPD Instance
01312   * @retval None
01313   */
01314 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
01315 {
01316   SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
01317 }
01318
01319 /**
01320   * @brief  Clear type c event on CC1
01321   * @rmtoll IIMR          TYPECEVT1IE        LL_UCPD_ClearFlag_TypeCEventCC1
01322   * @param  UCPDx UCPD Instance
01323   * @retval None
01324   */
01325 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
01326 {
01327   SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
01328 }
01329
01330 /**
01331   * @brief  Clear Rx message end interrupt
01332   * @rmtoll ICR          RXMSGENDIE         LL_UCPD_ClearFlag_RxMsgEnd
01333   * @param  UCPDx UCPD Instance
01334   * @retval None
01335   */
01336 __STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
01337 {
01338   SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
01339 }
01340
01341 /**
01342   * @brief  Clear Rx overrun interrupt
01343   * @rmtoll ICR          RXOVRIE         LL_UCPD_ClearFlag_RxOvr
01344   * @param  UCPDx UCPD Instance
01345   * @retval None
01346   */
01347 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
01348 {
01349   SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
01350 }
01351
01352 /**
01353   * @brief  Clear Rx hard resrt interrupt
01354   * @rmtoll ICR          RXHRSTDETIE         LL_UCPD_ClearFlag_RxHRST
01355   * @param  UCPDx UCPD Instance
01356   * @retval None
01357   */
01358 __STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
01359 {
01360   SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
01361 }
01362
01363 /**
01364   * @brief  Clear Rx orderset interrupt
01365   * @rmtoll ICR          RXORDDETIE         LL_UCPD_ClearFlag_RxOrderSet
01366   * @param  UCPDx UCPD Instance
01367   * @retval None
01368   */
01369 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
01370 {
01371   SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
01372 }
01373
01374 /**
01375   * @brief  Clear TX underrun interrupt
01376   * @rmtoll ICR          TXUNDIE         LL_UCPD_ClearFlag_TxUND
01377   * @param  UCPDx UCPD Instance
01378   * @retval None
01379   */
01380 __STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
01381 {
01382   SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
01383 }
01384
01385 /**
01386   * @brief  Clear hard reset sent interrupt
01387   * @rmtoll ICR          HRSTSENTIE         LL_UCPD_ClearFlag_TxHRSTSENT
01388   * @param  UCPDx UCPD Instance
01389   * @retval None
01390   */
01391 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
01392 {
01393   SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
01394 }
01395
01396 /**
01397   * @brief  Clear hard reset discard interrupt
01398   * @rmtoll ICR          HRSTDISCIE         LL_UCPD_ClearFlag_TxHRSTDISC
01399   * @param  UCPDx UCPD Instance
01400   * @retval None
01401   */
01402 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
01403 {
01404   SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
01405 }
01406
01407 /**
01408   * @brief  Clear Tx message abort interrupt
01409   * @rmtoll ICR          TXMSGABTIE         LL_UCPD_ClearFlag_TxMSGABT
01410   * @param  UCPDx UCPD Instance
01411   * @retval None
01412   */
01413 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
01414 {
01415   SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
01416 }
01417
01418 /**
01419   * @brief  Clear Tx message sent interrupt
01420   * @rmtoll ICR          TXMSGSENTIE         LL_UCPD_ClearFlag_TxMSGSENT
01421   * @param  UCPDx UCPD Instance
01422   * @retval None
01423   */
01424 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
01425 {
01426   SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
01427 }
01428
01429 /**
01430   * @brief  Clear Tx message discarded interrupt
01431   * @rmtoll ICR          TXMSGDISCIE         LL_UCPD_ClearFlag_TxMSGDISC
01432   * @param  UCPDx UCPD Instance
01433   * @retval None
01434   */
01435 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
01436 {
01437   SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
01438 }
01439
01440 /**
01441   * @}
01442   */
01443
01444 /** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
01445   * @{
01446   */
01447
01448 /**
01449   * @brief  Check if FRS interrupt
01450   * @rmtoll SR          FRSEVT         LL_UCPD_IsActiveFlag_FRS
01451   * @param  UCPDx UCPD Instance
01452   * @retval None
01453   */
01454 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx)
01455 {
01456   return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL);
01457 }
01458
01459 /**
01460   * @brief  Check if type c event on CC2
01461   * @rmtoll SR          TYPECEVT2        LL_UCPD_IsActiveFlag_TypeCEventCC2
01462   * @param  UCPDx UCPD Instance
01463   * @retval None
01464   */
01465 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
01466 {
01467   return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
01468 }
01469
01470 /**
01471   * @brief  Check if type c event on CC1
01472   * @rmtoll SR          TYPECEVT1        LL_UCPD_IsActiveFlag_TypeCEventCC1
01473   * @param  UCPDx UCPD Instance
01474   * @retval None
01475   */
01476 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
01477 {
01478   return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
01479 }
01480
01481 /**
01482   * @brief  Check if Rx message end interrupt
01483   * @rmtoll SR          RXMSGEND         LL_UCPD_IsActiveFlag_RxMsgEnd
01484   * @param  UCPDx UCPD Instance
01485   * @retval None
01486   */
01487 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
01488 {
01489   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
01490 }
01491
01492 /**
01493   * @brief  Check if Rx overrun interrupt
01494   * @rmtoll SR          RXOVR         LL_UCPD_IsActiveFlag_RxOvr
01495   * @param  UCPDx UCPD Instance
01496   * @retval None
01497   */
01498 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
01499 {
01500   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
01501 }
01502
01503 /**
01504   * @brief  Check if Rx hard resrt interrupt
01505   * @rmtoll SR          RXHRSTDET         LL_UCPD_IsActiveFlag_RxHRST
01506   * @param  UCPDx UCPD Instance
01507   * @retval None
01508   */
01509 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
01510 {
01511   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
01512 }
01513
01514 /**
01515   * @brief  Check if Rx orderset interrupt
01516   * @rmtoll SR          RXORDDET         LL_UCPD_IsActiveFlag_RxOrderSet
01517   * @param  UCPDx UCPD Instance
01518   * @retval State of bit (1 or 0).
01519   */
01520 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx)
01521 {
01522   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
01523 }
01524
01525 /**
01526   * @brief  Check if Rx non empty interrupt
01527   * @rmtoll SR          RXNE         LL_UCPD_IsActiveFlag_RxNE
01528   * @param  UCPDx UCPD Instance
01529   * @retval State of bit (1 or 0).
01530   */
01531 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx)
01532 {
01533   return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
01534 }
01535
01536 /**
01537   * @brief  Check if TX underrun interrupt
01538   * @rmtoll SR          TXUND         LL_UCPD_IsActiveFlag_TxUND
01539   * @param  UCPDx UCPD Instance
01540   * @retval State of bit (1 or 0).
01541   */
01542 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx)
01543 {
01544   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
01545 }
01546
01547 /**
01548   * @brief  Check if hard reset sent interrupt
01549   * @rmtoll SR          HRSTSENT         LL_UCPD_IsActiveFlag_TxHRSTSENT
01550   * @param  UCPDx UCPD Instance
01551   * @retval State of bit (1 or 0).
01552   */
01553 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
01554 {
01555   return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
01556 }
01557
01558 /**
01559   * @brief  Check if hard reset discard interrupt
01560   * @rmtoll SR          HRSTDISC         LL_UCPD_IsActiveFlag_TxHRSTDISC
01561   * @param  UCPDx UCPD Instance
01562   * @retval State of bit (1 or 0).
01563   */
01564 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
01565 {
01566   return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
01567 }
01568
01569 /**
01570   * @brief  Check if Tx message abort interrupt
01571   * @rmtoll SR          TXMSGABT         LL_UCPD_IsActiveFlag_TxMSGABT
01572   * @param  UCPDx UCPD Instance
01573   * @retval State of bit (1 or 0).
01574   */
01575 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx)
01576 {
01577   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
01578 }
01579
01580 /**
01581   * @brief  Check if Tx message sent interrupt
01582   * @rmtoll SR          TXMSGSENT         LL_UCPD_IsActiveFlag_TxMSGSENT
01583   * @param  UCPDx UCPD Instance
01584   * @retval State of bit (1 or 0).
01585   */
01586 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
01587 {
01588   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
01589 }
01590
01591 /**
01592   * @brief  Check if Tx message discarded interrupt
01593   * @rmtoll SR         TXMSGDISC         LL_UCPD_IsActiveFlag_TxMSGDISC
01594   * @param  UCPDx UCPD Instance
01595   * @retval State of bit (1 or 0).
01596   */
01597 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
01598 {
01599   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
01600 }
01601
01602 /**
01603   * @brief  Check if Tx data receive interrupt
01604   * @rmtoll SR          TXIS         LL_UCPD_IsActiveFlag_TxIS
01605   * @param  UCPDx UCPD Instance
01606   * @retval State of bit (1 or 0).
01607   */
01608 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx)
01609 {
01610   return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
01611 }
01612
01613 /**
01614   * @brief  return the vstate value for CC2
01615   * @rmtoll SR          TXIS         LL_UCPD_GetTypeCVstateCC2
01616   * @param  UCPDx UCPD Instance
01617   * @retval val
01618   */
01619 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx)
01620 {
01621   return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
01622 }
01623
01624 /**
01625   * @brief  return the vstate value for CC1
01626   * @rmtoll SR          TXIS         LL_UCPD_GetTypeCVstateCC1
01627   * @param  UCPDx UCPD Instance
01628   * @retval val
01629   */
01630 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx)
01631 {
01632   return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
01633 }
01634
01635 /**
01636   * @}
01637   */
01638
01639
01640 /** @defgroup UCPD_LL_EF_DMA_Management DMA Management
01641   * @{
01642   */
01643
01644 /**
01645   * @brief  Rx DMA Enable
01646   * @rmtoll CFG1          RXDMAEN          LL_UCPD_RxDMAEnable
01647   * @param  UCPDx UCPD Instance
01648   * @retval None
01649   */
01650 __STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
01651 {
01652   SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
01653 }
01654
01655 /**
01656   * @brief  Rx DMA Disable
01657   * @rmtoll CFG1          RXDMAEN          LL_UCPD_RxDMADisable
01658   * @param  UCPDx UCPD Instance
01659   * @retval None
01660   */
01661 __STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
01662 {
01663   CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
01664 }
01665
01666 /**
01667   * @brief  Tx DMA Enable
01668   * @rmtoll CFG1          TXDMAEN          LL_UCPD_TxDMAEnable
01669   * @param  UCPDx UCPD Instance
01670   * @retval None
01671   */
01672 __STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
01673 {
01674   SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
01675 }
01676
01677 /**
01678   * @brief  Tx DMA Disable
01679   * @rmtoll CFG1          TXDMAEN          LL_UCPD_TxDMADisable
01680   * @param  UCPDx UCPD Instance
01681   * @retval None
01682   */
01683 __STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
01684 {
01685   CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
01686 }
01687
01688 /**
01689   * @brief  Check if DMA Tx is enabled
01690   * @rmtoll CR2          TXDMAEN       LL_UCPD_IsEnabledTxDMA
01691   * @param  UCPDx UCPD Instance
01692   * @retval State of bit (1 or 0).
01693   */
01694 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx)
01695 {
01696   return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
01697 }
01698
01699 /**
01700   * @brief  Check if DMA Rx is enabled
01701   * @rmtoll CR2          RXDMAEN       LL_UCPD_IsEnabledRxDMA
01702   * @param  UCPDx UCPD Instance
01703   * @retval State of bit (1 or 0).
01704   */
01705 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx)
01706 {
01707   return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
01708 }
01709
01710 /**
01711   * @}
01712   */
01713
01714 /** @defgroup UCPD_LL_EF_DATA_Management DATA Management
01715   * @{
01716   */
01717
01718 /**
01719   * @brief  write the orderset for Tx message
01720   * @rmtoll TX_ORDSET           TXORDSET            LL_UCPD_WriteTxOrderSet
01721   * @param  UCPDx UCPD Instance
01722   * @param  TxOrderSet one of the following value
01723   *         @arg @ref LL_UCPD_ORDERED_SET_SOP
01724   *         @arg @ref LL_UCPD_ORDERED_SET_SOP1
01725   *         @arg @ref LL_UCPD_ORDERED_SET_SOP2
01726   *         @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
01727   *         @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
01728   *         @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
01729   *         @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
01730   * @retval None
01731   */
01732 __STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
01733 {
01734   WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
01735 }
01736
01737 /**
01738   * @brief  write the Tx paysize
01739   * @rmtoll TX_PAYSZ          TXPAYSZ            LL_UCPD_WriteTxPaySize
01740   * @param  UCPDx UCPD Instance
01741   * @param  TxPaySize
01742   * @retval None.
01743   */
01744 __STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
01745 {
01746   WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
01747 }
01748
01749 /**
01750   * @brief  Write data
01751   * @rmtoll TXDR           DR            LL_UCPD_WriteData
01752   * @param  UCPDx UCPD Instance
01753   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
01754   * @retval None.
01755   */
01756 __STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
01757 {
01758   WRITE_REG(UCPDx->TXDR, Data);
01759 }
01760
01761 /**
01762   * @brief  read RX the orderset
01763   * @rmtoll RX_ORDSET           RXORDSET            LL_UCPD_ReadRxOrderSet
01764   * @param  UCPDx UCPD Instance
01765   * @retval RxOrderSet one of the following value
01766   *         @arg @ref LL_UCPD_RXORDSET_SOP
01767   *         @arg @ref LL_UCPD_RXORDSET_SOP1
01768   *         @arg @ref LL_UCPD_RXORDSET_SOP2
01769   *         @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
01770   *         @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
01771   *         @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
01772   *         @arg @ref LL_UCPD_RXORDSET_SOPEXT1
01773   *         @arg @ref LL_UCPD_RXORDSET_SOPEXT2
01774   */
01775 __STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx)
01776 {
01777   return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
01778 }
01779
01780 /**
01781   * @brief  Read the Rx paysize
01782   * @rmtoll RX_PAYSZ          RXPAYSZ            LL_UCPD_ReadRxPaySize
01783   * @param  UCPDx UCPD Instance
01784   * @retval RXPaysize.
01785   */
01786 __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx)
01787 {
01788   return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
01789 }
01790
01791 /**
01792   * @brief  Read data
01793   * @rmtoll RXDR           RXDATA            LL_UCPD_ReadData
01794   * @param  UCPDx UCPD Instance
01795   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
01796   */
01797 __STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx)
01798 {
01799   return READ_REG(UCPDx->RXDR);
01800 }
01801
01802 /**
01803   * @brief  Set Rx OrderSet Ext1
01804   * @rmtoll RX_ORDEXT1           RXSOPX1            LL_UCPD_SetRxOrdExt1
01805   * @param  UCPDx UCPD Instance
01806   * @param  SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
01807   * @retval None
01808   */
01809 __STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
01810 {
01811   WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
01812 }
01813
01814 /**
01815   * @brief  Set Rx OrderSet Ext2
01816   * @rmtoll RX_ORDEXT2           RXSOPX2            LL_UCPD_SetRxOrdExt2
01817   * @param  UCPDx UCPD Instance
01818   * @param  SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
01819   * @retval None
01820   */
01821 __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
01822 {
01823   WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
01824 }
01825
01826 /**
01827   * @}
01828   */
01829
01830 #if defined(USE_FULL_LL_DRIVER)
01831 /** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
01832   * @{
01833   */
01834
01835 ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
01836 ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
01837 void        LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
01838
01839 /**
01840   * @}
01841   */
01842 #endif /* USE_FULL_LL_DRIVER */
01843
01844 /**
01845   * @}
01846   */
01847
01848 #endif /* defined (UCPD1) || defined (UCPD2) */
01849
01850 /**
01851   * @}
01852   */
01853
01854 /**
01855   * @}
01856   */
01857
01858 #ifdef __cplusplus
01859 }
01860 #endif
01861
01862 #endif /* STM32G0xx_LL_UCPD_H */
01863
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_usart.c Source File

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stm32g0xx_ll_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 #if defined(USE_FULL_LL_DRIVER)
00019
00020 /* Includes ------------------------------------------------------------------*/
00021 #include "stm32g0xx_ll_usart.h"
00022 #include "stm32g0xx_ll_rcc.h"
00023 #include "stm32g0xx_ll_bus.h"
00024 #ifdef USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6)
00035
00036 /** @addtogroup USART_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup USART_LL_Private_Macros
00045   * @{
00046   */
00047
00048 #define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
00049                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
00050                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
00051                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
00052                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
00053                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
00054                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
00055                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
00056                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
00057                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
00058                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
00059                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
00060
00061 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
00062  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
00063 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
00064
00065 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
00066 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
00067
00068 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
00069                                           || ((__VALUE__) == LL_USART_DIRECTION_RX) \
00070                                           || ((__VALUE__) == LL_USART_DIRECTION_TX) \
00071                                           || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
00072
00073 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
00074                                        || ((__VALUE__) == LL_USART_PARITY_EVEN) \
00075                                        || ((__VALUE__) == LL_USART_PARITY_ODD))
00076
00077 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
00078                                           || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00079                                           || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00080
00081 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
00082                                              || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
00083
00084 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
00085                                                  || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
00086
00087 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
00088                                            || ((__VALUE__) == LL_USART_PHASE_2EDGE))
00089
00090 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
00091                                               || ((__VALUE__) == LL_USART_POLARITY_HIGH))
00092
00093 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
00094                                             || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
00095
00096 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
00097                                          || ((__VALUE__) == LL_USART_STOPBITS_1) \
00098                                          || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
00099                                          || ((__VALUE__) == LL_USART_STOPBITS_2))
00100
00101 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
00102                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
00103                                           || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
00104                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Private function prototypes -----------------------------------------------*/
00111
00112 /* Exported functions --------------------------------------------------------*/
00113 /** @addtogroup USART_LL_Exported_Functions
00114   * @{
00115   */
00116
00117 /** @addtogroup USART_LL_EF_Init
00118   * @{
00119   */
00120
00121 /**
00122   * @brief  De-initialize USART registers (Registers restored to their default values).
00123   * @param  USARTx USART Instance
00124   * @retval An ErrorStatus enumeration value:
00125   *          - SUCCESS: USART registers are de-initialized
00126   *          - ERROR: USART registers are not de-initialized
00127   */
00128 ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
00129 {
00130   ErrorStatus status = SUCCESS;
00131
00132   /* Check the parameters */
00133   assert_param(IS_UART_INSTANCE(USARTx));
00134
00135   if (USARTx == USART1)
00136   {
00137     /* Force reset of USART clock */
00138     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
00139
00140     /* Release reset of USART clock */
00141     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
00142   }
00143   else if (USARTx == USART2)
00144   {
00145     /* Force reset of USART clock */
00146     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
00147
00148     /* Release reset of USART clock */
00149     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
00150   }
00151 #if defined(USART3)
00152   else if (USARTx == USART3)
00153   {
00154     /* Force reset of USART clock */
00155     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
00156
00157     /* Release reset of USART clock */
00158     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
00159   }
00160 #endif /* USART3 */
00161 #if defined(USART4)
00162   else if (USARTx == USART4)
00163   {
00164     /* Force reset of USART clock */
00165     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
00166
00167     /* Release reset of USART clock */
00168     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
00169   }
00170 #endif /* USART4 */
00171 #if defined(USART5)
00172   else if (USARTx == USART5)
00173   {
00174     /* Force reset of USART clock */
00175     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
00176
00177     /* Release reset of USART clock */
00178     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
00179   }
00180 #endif /* USART5 */
00181 #if defined(USART6)
00182   else if (USARTx == USART6)
00183   {
00184     /* Force reset of USART clock */
00185     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART6);
00186
00187     /* Release reset of USART clock */
00188     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART6);
00189   }
00190 #endif /* USART6 */
00191   else
00192   {
00193     status = ERROR;
00194   }
00195
00196   return (status);
00197 }
00198
00199 /**
00200   * @brief  Initialize USART registers according to the specified
00201   *         parameters in USART_InitStruct.
00202   * @note   As some bits in USART configuration registers can only be written when
00203   *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
00204   *         this function. Otherwise, ERROR result will be returned.
00205   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
00206   * @param  USARTx USART Instance
00207   * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
00208   *         that contains the configuration information for the specified USART peripheral.
00209   * @retval An ErrorStatus enumeration value:
00210   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
00211   *          - ERROR: Problem occurred during USART Registers initialization
00212   */
00213 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
00214 {
00215   ErrorStatus status = ERROR;
00216   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00217 #if !defined(RCC_CCIPR_USART3SEL)&&!defined(RCC_CCIPR_USART4SEL)||(!defined(RCC_CCIPR_USART2SEL))||!defined(RCC_CCIPR_USART5SEL)||!defined(RCC_CCIPR_USART6SEL)
00218   LL_RCC_ClocksTypeDef RCC_Clocks;
00219 #endif /* USART clock selection flags */
00220
00221   /* Check the parameters */
00222   assert_param(IS_UART_INSTANCE(USARTx));
00223   assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
00224   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
00225   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
00226   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
00227   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
00228   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
00229   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
00230   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
00231
00232   /* USART needs to be in disabled state, in order to be able to configure some bits in
00233      CRx registers */
00234   if (LL_USART_IsEnabled(USARTx) == 0U)
00235   {
00236     /*---------------------------- USART CR1 Configuration ---------------------
00237      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
00238      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
00239      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
00240      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
00241      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
00242      */
00243     MODIFY_REG(USARTx->CR1,
00244                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00245                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
00246                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00247                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
00248
00249     /*---------------------------- USART CR2 Configuration ---------------------
00250      * Configure USARTx CR2 (Stop bits) with parameters:
00251      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
00252      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
00253      */
00254     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
00255
00256     /*---------------------------- USART CR3 Configuration ---------------------
00257      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
00258      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
00259      *   USART_InitStruct->HardwareFlowControl value.
00260      */
00261     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
00262
00263     /*---------------------------- USART BRR Configuration ---------------------
00264      * Retrieve Clock frequency used for USART Peripheral
00265      */
00266     if (USARTx == USART1)
00267     {
00268       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
00269     }
00270     else if (USARTx == USART2)
00271     {
00272 #if defined(RCC_CCIPR_USART2SEL)
00273       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
00274 #else
00275       /* USART2 clock is PCLK */
00276       LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
00277       periphclk = RCC_Clocks.PCLK1_Frequency;
00278 #endif /* USART2 Clock selector flag */
00279     }
00280 #if defined(USART3)
00281     else if (USARTx == USART3)
00282     {
00283 #if defined(RCC_CCIPR_USART3SEL)
00284       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
00285 #else
00286       /* USART3 clock is PCLK */
00287       LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
00288       periphclk = RCC_Clocks.PCLK1_Frequency;
00289 #endif /* USART3 Clock selector flag */
00290     }
00291 #endif /* USART3 */
00292 #if defined(USART4)
00293     else if (USARTx == USART4)
00294     {
00295 #if defined(RCC_CCIPR_USART4SEL)
00296       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART4_CLKSOURCE);
00297 #else
00298       /* USART4 clock is PCLK1 */
00299       LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
00300       periphclk = RCC_Clocks.PCLK1_Frequency;
00301 #endif /* RCC_CCIPR_USART4SEL */
00302     }
00303 #endif /* USART4 */
00304 #if defined(USART5)
00305     else if (USARTx == USART5)
00306     {
00307       /* USART5 clock is PCLK1 */
00308       LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
00309       periphclk = RCC_Clocks.PCLK1_Frequency;
00310     }
00311 #endif /* USART5 */
00312 #if defined(USART6)
00313     else if (USARTx == USART6)
00314     {
00315       /* USART6 clock is PCLK1 */
00316       LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
00317       periphclk = RCC_Clocks.PCLK1_Frequency;
00318     }
00319 #endif /* USART6 */
00320     else
00321     {
00322       /* Nothing to do, as error code is already assigned to ERROR value */
00323     }
00324
00325     /* Configure the USART Baud Rate :
00326        - prescaler value is required
00327        - valid baud rate value (different from 0) is required
00328        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00329     */
00330     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00331         && (USART_InitStruct->BaudRate != 0U))
00332     {
00333       status = SUCCESS;
00334       LL_USART_SetBaudRate(USARTx,
00335                            periphclk,
00336                            USART_InitStruct->PrescalerValue,
00337                            USART_InitStruct->OverSampling,
00338                            USART_InitStruct->BaudRate);
00339
00340       /* Check BRR is greater than or equal to 16d */
00341       assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
00342     }
00343
00344     /*---------------------------- USART PRESC Configuration -----------------------
00345      * Configure USARTx PRESC (Prescaler) with parameters:
00346      * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
00347      */
00348     LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
00349   }
00350   /* Endif (=> USART not in Disabled state => return ERROR) */
00351
00352   return (status);
00353 }
00354
00355 /**
00356   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
00357   * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
00358   *                         whose fields will be set to default values.
00359   * @retval None
00360   */
00361
00362 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
00363 {
00364   /* Set USART_InitStruct fields to default values */
00365   USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
00366   USART_InitStruct->BaudRate            = 9600U;
00367   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
00368   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
00369   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
00370   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
00371   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
00372   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
00373 }
00374
00375 /**
00376   * @brief  Initialize USART Clock related settings according to the
00377   *         specified parameters in the USART_ClockInitStruct.
00378   * @note   As some bits in USART configuration registers can only be written when
00379   *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
00380   *         this function. Otherwise, ERROR result will be returned.
00381   * @param  USARTx USART Instance
00382   * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00383   *         that contains the Clock configuration information for the specified USART peripheral.
00384   * @retval An ErrorStatus enumeration value:
00385   *          - SUCCESS: USART registers related to Clock settings are initialized according
00386   *                     to USART_ClockInitStruct content
00387   *          - ERROR: Problem occurred during USART Registers initialization
00388   */
00389 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00390 {
00391   ErrorStatus status = SUCCESS;
00392
00393   /* Check USART Instance and Clock signal output parameters */
00394   assert_param(IS_UART_INSTANCE(USARTx));
00395   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
00396
00397   /* USART needs to be in disabled state, in order to be able to configure some bits in
00398      CRx registers */
00399   if (LL_USART_IsEnabled(USARTx) == 0U)
00400   {
00401     /* Ensure USART instance is USART capable */
00402     assert_param(IS_USART_INSTANCE(USARTx));
00403
00404     /* Check clock related parameters */
00405     assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
00406     assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
00407     assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
00408
00409     /*---------------------------- USART CR2 Configuration -----------------------
00410      * Configure USARTx CR2 (Clock signal related bits) with parameters:
00411      * - Clock Output:                USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
00412      * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
00413      * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
00414      * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
00415      */
00416     MODIFY_REG(USARTx->CR2,
00417                USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
00418                USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
00419                USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
00420   }
00421   /* Else (USART not in Disabled state => return ERROR */
00422   else
00423   {
00424     status = ERROR;
00425   }
00426
00427   return (status);
00428 }
00429
00430 /**
00431   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
00432   * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00433   *                              whose fields will be set to default values.
00434   * @retval None
00435   */
00436 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00437 {
00438   /* Set LL_USART_ClockInitStruct fields with default values */
00439   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
00440   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput =
00441                                                                                   LL_USART_CLOCK_DISABLE */
00442   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput =
00443                                                                                   LL_USART_CLOCK_DISABLE */
00444   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput =
00445                                                                                   LL_USART_CLOCK_DISABLE */
00446 }
00447
00448 /**
00449   * @}
00450   */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /**
00457   * @}
00458   */
00459
00460 #endif /* USART1 || USART2 || USART3 || USART4 || USART5 || USART6 */
00461
00462 /**
00463   * @}
00464   */
00465
00466 #endif /* USE_FULL_LL_DRIVER */
00467
00468
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_usart.h Source File

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stm32g0xx_ll_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_USART_H
00021 #define STM32G0xx_LL_USART_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6)
00035
00036 /** @defgroup USART_LL USART
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /** @defgroup USART_LL_Private_Variables USART Private Variables
00043   * @{
00044   */
00045 /* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
00046 static const uint32_t USART_PRESCALER_TAB[] =
00047 {
00048   1UL,
00049   2UL,
00050   4UL,
00051   6UL,
00052   8UL,
00053   10UL,
00054   12UL,
00055   16UL,
00056   32UL,
00057   64UL,
00058   128UL,
00059   256UL
00060 };
00061 /**
00062   * @}
00063   */
00064
00065 /* Private constants ---------------------------------------------------------*/
00066 /* Private macros ------------------------------------------------------------*/
00067 #if defined(USE_FULL_LL_DRIVER)
00068 /** @defgroup USART_LL_Private_Macros USART Private Macros
00069   * @{
00070   */
00071 /**
00072   * @}
00073   */
00074 #endif /*USE_FULL_LL_DRIVER*/
00075
00076 /* Exported types ------------------------------------------------------------*/
00077 #if defined(USE_FULL_LL_DRIVER)
00078 /** @defgroup USART_LL_ES_INIT USART Exported Init structures
00079   * @{
00080   */
00081
00082 /**
00083   * @brief LL USART Init Structure definition
00084   */
00085 typedef struct
00086 {
00087   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00088                                            This parameter can be a value of @ref USART_LL_EC_PRESCALER.
00089
00090                                            This feature can be modified afterwards using unitary
00091                                            function @ref LL_USART_SetPrescaler().*/
00092
00093   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
00094
00095                                            This feature can be modified afterwards using unitary
00096                                            function @ref LL_USART_SetBaudRate().*/
00097
00098   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00099                                            This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
00100
00101                                            This feature can be modified afterwards using unitary
00102                                            function @ref LL_USART_SetDataWidth().*/
00103
00104   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00105                                            This parameter can be a value of @ref USART_LL_EC_STOPBITS.
00106
00107                                            This feature can be modified afterwards using unitary
00108                                            function @ref LL_USART_SetStopBitsLength().*/
00109
00110   uint32_t Parity;                    /*!< Specifies the parity mode.
00111                                            This parameter can be a value of @ref USART_LL_EC_PARITY.
00112
00113                                            This feature can be modified afterwards using unitary
00114                                            function @ref LL_USART_SetParity().*/
00115
00116   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00117                                            This parameter can be a value of @ref USART_LL_EC_DIRECTION.
00118
00119                                            This feature can be modified afterwards using unitary
00120                                            function @ref LL_USART_SetTransferDirection().*/
00121
00122   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00123                                            This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
00124
00125                                            This feature can be modified afterwards using unitary
00126                                            function @ref LL_USART_SetHWFlowCtrl().*/
00127
00128   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
00129                                            This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
00130
00131                                            This feature can be modified afterwards using unitary
00132                                            function @ref LL_USART_SetOverSampling().*/
00133
00134 } LL_USART_InitTypeDef;
00135
00136 /**
00137   * @brief LL USART Clock Init Structure definition
00138   */
00139 typedef struct
00140 {
00141   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
00142                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
00143
00144                                            USART HW configuration can be modified afterwards using unitary functions
00145                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
00146                                            For more details, refer to description of this function. */
00147
00148   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
00149                                            This parameter can be a value of @ref USART_LL_EC_POLARITY.
00150
00151                                            USART HW configuration can be modified afterwards using unitary
00152                                            functions @ref LL_USART_SetClockPolarity().
00153                                            For more details, refer to description of this function. */
00154
00155   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
00156                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
00157
00158                                            USART HW configuration can be modified afterwards using unitary
00159                                            functions @ref LL_USART_SetClockPhase().
00160                                            For more details, refer to description of this function. */
00161
00162   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
00163                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00164                                            This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
00165
00166                                            USART HW configuration can be modified afterwards using unitary
00167                                            functions @ref LL_USART_SetLastClkPulseOutput().
00168                                            For more details, refer to description of this function. */
00169
00170 } LL_USART_ClockInitTypeDef;
00171
00172 /**
00173   * @}
00174   */
00175 #endif /* USE_FULL_LL_DRIVER */
00176
00177 /* Exported constants --------------------------------------------------------*/
00178 /** @defgroup USART_LL_Exported_Constants USART Exported Constants
00179   * @{
00180   */
00181
00182 /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
00183   * @brief    Flags defines which can be used with LL_USART_WriteReg function
00184   * @{
00185   */
00186 #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
00187 #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
00188 #define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
00189 #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
00190 #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
00191 #define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
00192 #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
00193 #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
00194 #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
00195 #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
00196 #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
00197 #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
00198 #define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
00199 #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
00200 #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
00206   * @brief    Flags defines which can be used with LL_USART_ReadReg function
00207   * @{
00208   */
00209 #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
00210 #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
00211 #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
00212 #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
00213 #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
00214 #define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
00215 #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
00216 #define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
00217 #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
00218 #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
00219 #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
00220 #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
00221 #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
00222 #define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
00223 #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
00224 #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
00225 #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
00226 #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
00227 #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
00228 #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00229 #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00230 #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00231 #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00232 #define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
00233 #define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
00234 #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
00235 #define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
00236 #define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup USART_LL_EC_IT IT Defines
00242   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
00243   * @{
00244   */
00245 #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00246 #define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
00247 #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00248 #define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
00249 #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
00250 #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
00251 #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
00252 #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
00253 #define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
00254 #define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
00255 #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
00256 #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
00257 #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
00258 #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00259 #define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
00260 #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
00261 #define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00267   * @{
00268   */
00269 #define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
00270 #define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
00271 #define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
00272 #define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
00273 #define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
00274 #define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
00280   * @{
00281   */
00282 #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
00283 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00284 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00285 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup USART_LL_EC_PARITY Parity Control
00291   * @{
00292   */
00293 #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
00294 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
00295 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup USART_LL_EC_WAKEUP Wakeup
00301   * @{
00302   */
00303 #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
00304 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
00310   * @{
00311   */
00312 #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00313 #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00314 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
00320   * @{
00321   */
00322 #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
00323 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
00324 /**
00325   * @}
00326   */
00327
00328 #if defined(USE_FULL_LL_DRIVER)
00329 /** @defgroup USART_LL_EC_CLOCK Clock Signal
00330   * @{
00331   */
00332
00333 #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
00334 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
00335 /**
00336   * @}
00337   */
00338 #endif /*USE_FULL_LL_DRIVER*/
00339
00340 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
00341   * @{
00342   */
00343 #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
00344 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup USART_LL_EC_PHASE Clock Phase
00350   * @{
00351   */
00352 #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
00353 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
00359   * @{
00360   */
00361 #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
00362 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
00368   * @{
00369   */
00370 #define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
00371 #define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
00372 #define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
00373 #define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
00374 #define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
00375 #define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
00376 #define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
00377 #define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
00378 #define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
00379 #define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
00380 #define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
00381 #define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup USART_LL_EC_STOPBITS Stop Bits
00387   * @{
00388   */
00389 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
00390 #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
00391 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
00392 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
00398   * @{
00399   */
00400 #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
00401 #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00407   * @{
00408   */
00409 #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
00410 #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00416   * @{
00417   */
00418 #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
00419 #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
00425   * @{
00426   */
00427 #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00428 #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup USART_LL_EC_BITORDER Bit Order
00434   * @{
00435   */
00436 #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
00437 #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
00443   * @{
00444   */
00445 #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
00446 #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
00447 #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
00448 #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
00454   * @{
00455   */
00456 #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
00457 #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
00463   * @{
00464   */
00465 #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
00466 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00467 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00468 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
00474   * @{
00475   */
00476 #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
00477 #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00478 #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00479 /**
00480   * @}
00481   */
00482
00483 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
00484   * @{
00485   */
00486 #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
00487 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
00488 /**
00489   * @}
00490   */
00491
00492 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
00493   * @{
00494   */
00495 #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
00496 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
00497 /**
00498   * @}
00499   */
00500
00501 /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
00502   * @{
00503   */
00504 #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
00505 #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
00506 /**
00507   * @}
00508   */
00509
00510 /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
00511   * @{
00512   */
00513 #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
00514 #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
00515 /**
00516   * @}
00517   */
00518
00519 /**
00520   * @}
00521   */
00522
00523 /* Exported macro ------------------------------------------------------------*/
00524 /** @defgroup USART_LL_Exported_Macros USART Exported Macros
00525   * @{
00526   */
00527
00528 /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
00529   * @{
00530   */
00531
00532 /**
00533   * @brief  Write a value in USART register
00534   * @param  __INSTANCE__ USART Instance
00535   * @param  __REG__ Register to be written
00536   * @param  __VALUE__ Value to be written in the register
00537   * @retval None
00538   */
00539 #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00540
00541 /**
00542   * @brief  Read a value in USART register
00543   * @param  __INSTANCE__ USART Instance
00544   * @param  __REG__ Register to be read
00545   * @retval Register value
00546   */
00547 #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00553   * @{
00554   */
00555
00556 /**
00557   * @brief  Compute USARTDIV value according to Peripheral Clock and
00558   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
00559   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00560   * @param  __PRESCALER__ This parameter can be one of the following values:
00561   *         @arg @ref LL_USART_PRESCALER_DIV1
00562   *         @arg @ref LL_USART_PRESCALER_DIV2
00563   *         @arg @ref LL_USART_PRESCALER_DIV4
00564   *         @arg @ref LL_USART_PRESCALER_DIV6
00565   *         @arg @ref LL_USART_PRESCALER_DIV8
00566   *         @arg @ref LL_USART_PRESCALER_DIV10
00567   *         @arg @ref LL_USART_PRESCALER_DIV12
00568   *         @arg @ref LL_USART_PRESCALER_DIV16
00569   *         @arg @ref LL_USART_PRESCALER_DIV32
00570   *         @arg @ref LL_USART_PRESCALER_DIV64
00571   *         @arg @ref LL_USART_PRESCALER_DIV128
00572   *         @arg @ref LL_USART_PRESCALER_DIV256
00573   * @param  __BAUDRATE__ Baud rate value to achieve
00574   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
00575   */
00576 #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
00577   (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
00578     + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00579
00580 /**
00581   * @brief  Compute USARTDIV value according to Peripheral Clock and
00582   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
00583   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00584   * @param  __PRESCALER__ This parameter can be one of the following values:
00585   *         @arg @ref LL_USART_PRESCALER_DIV1
00586   *         @arg @ref LL_USART_PRESCALER_DIV2
00587   *         @arg @ref LL_USART_PRESCALER_DIV4
00588   *         @arg @ref LL_USART_PRESCALER_DIV6
00589   *         @arg @ref LL_USART_PRESCALER_DIV8
00590   *         @arg @ref LL_USART_PRESCALER_DIV10
00591   *         @arg @ref LL_USART_PRESCALER_DIV12
00592   *         @arg @ref LL_USART_PRESCALER_DIV16
00593   *         @arg @ref LL_USART_PRESCALER_DIV32
00594   *         @arg @ref LL_USART_PRESCALER_DIV64
00595   *         @arg @ref LL_USART_PRESCALER_DIV128
00596   *         @arg @ref LL_USART_PRESCALER_DIV256
00597   * @param  __BAUDRATE__ Baud rate value to achieve
00598   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
00599   */
00600 #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
00601   ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
00602     + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00603
00604 /**
00605   * @}
00606   */
00607
00608 /**
00609   * @}
00610   */
00611
00612 /* Exported functions --------------------------------------------------------*/
00613
00614 /** @defgroup USART_LL_Exported_Functions USART Exported Functions
00615   * @{
00616   */
00617
00618 /** @defgroup USART_LL_EF_Configuration Configuration functions
00619   * @{
00620   */
00621
00622 /**
00623   * @brief  USART Enable
00624   * @rmtoll CR1          UE            LL_USART_Enable
00625   * @param  USARTx USART Instance
00626   * @retval None
00627   */
00628 __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
00629 {
00630   SET_BIT(USARTx->CR1, USART_CR1_UE);
00631 }
00632
00633 /**
00634   * @brief  USART Disable (all USART prescalers and outputs are disabled)
00635   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
00636   *         and current operations are discarded. The configuration of the USART is kept, but all the status
00637   *         flags, in the USARTx_ISR are set to their default values.
00638   * @rmtoll CR1          UE            LL_USART_Disable
00639   * @param  USARTx USART Instance
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
00643 {
00644   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
00645 }
00646
00647 /**
00648   * @brief  Indicate if USART is enabled
00649   * @rmtoll CR1          UE            LL_USART_IsEnabled
00650   * @param  USARTx USART Instance
00651   * @retval State of bit (1 or 0).
00652   */
00653 __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
00654 {
00655   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
00656 }
00657
00658 /**
00659   * @brief  FIFO Mode Enable
00660   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00661   *         FIFO mode feature is supported by the USARTx instance.
00662   * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
00663   * @param  USARTx USART Instance
00664   * @retval None
00665   */
00666 __STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
00667 {
00668   SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00669 }
00670
00671 /**
00672   * @brief  FIFO Mode Disable
00673   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00674   *         FIFO mode feature is supported by the USARTx instance.
00675   * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
00676   * @param  USARTx USART Instance
00677   * @retval None
00678   */
00679 __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
00680 {
00681   CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00682 }
00683
00684 /**
00685   * @brief  Indicate if FIFO Mode is enabled
00686   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00687   *         FIFO mode feature is supported by the USARTx instance.
00688   * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
00689   * @param  USARTx USART Instance
00690   * @retval State of bit (1 or 0).
00691   */
00692 __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx)
00693 {
00694   return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
00695 }
00696
00697 /**
00698   * @brief  Configure TX FIFO Threshold
00699   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00700   *         FIFO mode feature is supported by the USARTx instance.
00701   * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
00702   * @param  USARTx USART Instance
00703   * @param  Threshold This parameter can be one of the following values:
00704   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00705   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00706   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00707   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00708   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00709   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00710   * @retval None
00711   */
00712 __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00713 {
00714   ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00715 }
00716
00717 /**
00718   * @brief  Return TX FIFO Threshold Configuration
00719   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00720   *         FIFO mode feature is supported by the USARTx instance.
00721   * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
00722   * @param  USARTx USART Instance
00723   * @retval Returned value can be one of the following values:
00724   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00725   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00726   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00727   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00728   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00729   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00730   */
00731 __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx)
00732 {
00733   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00734 }
00735
00736 /**
00737   * @brief  Configure RX FIFO Threshold
00738   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00739   *         FIFO mode feature is supported by the USARTx instance.
00740   * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
00741   * @param  USARTx USART Instance
00742   * @param  Threshold This parameter can be one of the following values:
00743   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00744   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00745   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00746   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00747   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00748   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00749   * @retval None
00750   */
00751 __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00752 {
00753   ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00754 }
00755
00756 /**
00757   * @brief  Return RX FIFO Threshold Configuration
00758   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00759   *         FIFO mode feature is supported by the USARTx instance.
00760   * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
00761   * @param  USARTx USART Instance
00762   * @retval Returned value can be one of the following values:
00763   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00764   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00765   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00766   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00767   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00768   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00769   */
00770 __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx)
00771 {
00772   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00773 }
00774
00775 /**
00776   * @brief  Configure TX and RX FIFOs Threshold
00777   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00778   *         FIFO mode feature is supported by the USARTx instance.
00779   * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
00780   *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
00781   * @param  USARTx USART Instance
00782   * @param  TXThreshold This parameter can be one of the following values:
00783   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00784   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00785   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00786   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00787   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00788   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00789   * @param  RXThreshold This parameter can be one of the following values:
00790   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00791   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00792   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00793   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00794   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00795   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00796   * @retval None
00797   */
00798 __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00799 {
00800   ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
00801                     (RXThreshold << USART_CR3_RXFTCFG_Pos));
00802 }
00803
00804 /**
00805   * @brief  USART enabled in STOP Mode.
00806   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
00807   *         USART clock selection is HSI or LSE in RCC.
00808   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00809   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00810   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
00811   * @param  USARTx USART Instance
00812   * @retval None
00813   */
00814 __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
00815 {
00816   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
00817 }
00818
00819 /**
00820   * @brief  USART disabled in STOP Mode.
00821   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
00822   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00823   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00824   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
00825   * @param  USARTx USART Instance
00826   * @retval None
00827   */
00828 __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
00829 {
00830   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
00831 }
00832
00833 /**
00834   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
00835   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00836   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00837   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
00838   * @param  USARTx USART Instance
00839   * @retval State of bit (1 or 0).
00840   */
00841 __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
00842 {
00843   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
00844 }
00845
00846 /**
00847   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00848   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
00849   * @param  USARTx USART Instance
00850   * @retval None
00851   */
00852 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
00853 {
00854   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
00855 }
00856
00857 /**
00858   * @brief  Receiver Disable
00859   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
00860   * @param  USARTx USART Instance
00861   * @retval None
00862   */
00863 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
00864 {
00865   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
00866 }
00867
00868 /**
00869   * @brief  Transmitter Enable
00870   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
00871   * @param  USARTx USART Instance
00872   * @retval None
00873   */
00874 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
00875 {
00876   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
00877 }
00878
00879 /**
00880   * @brief  Transmitter Disable
00881   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
00882   * @param  USARTx USART Instance
00883   * @retval None
00884   */
00885 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
00886 {
00887   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
00888 }
00889
00890 /**
00891   * @brief  Configure simultaneously enabled/disabled states
00892   *         of Transmitter and Receiver
00893   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
00894   *         CR1          TE            LL_USART_SetTransferDirection
00895   * @param  USARTx USART Instance
00896   * @param  TransferDirection This parameter can be one of the following values:
00897   *         @arg @ref LL_USART_DIRECTION_NONE
00898   *         @arg @ref LL_USART_DIRECTION_RX
00899   *         @arg @ref LL_USART_DIRECTION_TX
00900   *         @arg @ref LL_USART_DIRECTION_TX_RX
00901   * @retval None
00902   */
00903 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
00904 {
00905   ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00906 }
00907
00908 /**
00909   * @brief  Return enabled/disabled states of Transmitter and Receiver
00910   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
00911   *         CR1          TE            LL_USART_GetTransferDirection
00912   * @param  USARTx USART Instance
00913   * @retval Returned value can be one of the following values:
00914   *         @arg @ref LL_USART_DIRECTION_NONE
00915   *         @arg @ref LL_USART_DIRECTION_RX
00916   *         @arg @ref LL_USART_DIRECTION_TX
00917   *         @arg @ref LL_USART_DIRECTION_TX_RX
00918   */
00919 __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
00920 {
00921   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00922 }
00923
00924 /**
00925   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
00926   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00927   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00928   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
00929   * @rmtoll CR1          PS            LL_USART_SetParity\n
00930   *         CR1          PCE           LL_USART_SetParity
00931   * @param  USARTx USART Instance
00932   * @param  Parity This parameter can be one of the following values:
00933   *         @arg @ref LL_USART_PARITY_NONE
00934   *         @arg @ref LL_USART_PARITY_EVEN
00935   *         @arg @ref LL_USART_PARITY_ODD
00936   * @retval None
00937   */
00938 __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
00939 {
00940   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00941 }
00942
00943 /**
00944   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00945   * @rmtoll CR1          PS            LL_USART_GetParity\n
00946   *         CR1          PCE           LL_USART_GetParity
00947   * @param  USARTx USART Instance
00948   * @retval Returned value can be one of the following values:
00949   *         @arg @ref LL_USART_PARITY_NONE
00950   *         @arg @ref LL_USART_PARITY_EVEN
00951   *         @arg @ref LL_USART_PARITY_ODD
00952   */
00953 __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
00954 {
00955   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00956 }
00957
00958 /**
00959   * @brief  Set Receiver Wake Up method from Mute mode.
00960   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
00961   * @param  USARTx USART Instance
00962   * @param  Method This parameter can be one of the following values:
00963   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00964   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00965   * @retval None
00966   */
00967 __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
00968 {
00969   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
00970 }
00971
00972 /**
00973   * @brief  Return Receiver Wake Up method from Mute mode
00974   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
00975   * @param  USARTx USART Instance
00976   * @retval Returned value can be one of the following values:
00977   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00978   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00979   */
00980 __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
00981 {
00982   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
00983 }
00984
00985 /**
00986   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
00987   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
00988   *         CR1          M1            LL_USART_SetDataWidth
00989   * @param  USARTx USART Instance
00990   * @param  DataWidth This parameter can be one of the following values:
00991   *         @arg @ref LL_USART_DATAWIDTH_7B
00992   *         @arg @ref LL_USART_DATAWIDTH_8B
00993   *         @arg @ref LL_USART_DATAWIDTH_9B
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
00997 {
00998   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
00999 }
01000
01001 /**
01002   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
01003   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
01004   *         CR1          M1            LL_USART_GetDataWidth
01005   * @param  USARTx USART Instance
01006   * @retval Returned value can be one of the following values:
01007   *         @arg @ref LL_USART_DATAWIDTH_7B
01008   *         @arg @ref LL_USART_DATAWIDTH_8B
01009   *         @arg @ref LL_USART_DATAWIDTH_9B
01010   */
01011 __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
01012 {
01013   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
01014 }
01015
01016 /**
01017   * @brief  Allow switch between Mute Mode and Active mode
01018   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
01019   * @param  USARTx USART Instance
01020   * @retval None
01021   */
01022 __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
01023 {
01024   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
01025 }
01026
01027 /**
01028   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
01029   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
01030   * @param  USARTx USART Instance
01031   * @retval None
01032   */
01033 __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
01034 {
01035   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
01036 }
01037
01038 /**
01039   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
01040   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
01041   * @param  USARTx USART Instance
01042   * @retval State of bit (1 or 0).
01043   */
01044 __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
01045 {
01046   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
01047 }
01048
01049 /**
01050   * @brief  Set Oversampling to 8-bit or 16-bit mode
01051   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
01052   * @param  USARTx USART Instance
01053   * @param  OverSampling This parameter can be one of the following values:
01054   *         @arg @ref LL_USART_OVERSAMPLING_16
01055   *         @arg @ref LL_USART_OVERSAMPLING_8
01056   * @retval None
01057   */
01058 __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
01059 {
01060   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
01061 }
01062
01063 /**
01064   * @brief  Return Oversampling mode
01065   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
01066   * @param  USARTx USART Instance
01067   * @retval Returned value can be one of the following values:
01068   *         @arg @ref LL_USART_OVERSAMPLING_16
01069   *         @arg @ref LL_USART_OVERSAMPLING_8
01070   */
01071 __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
01072 {
01073   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
01074 }
01075
01076 /**
01077   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
01078   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01079   *         Synchronous mode is supported by the USARTx instance.
01080   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
01081   * @param  USARTx USART Instance
01082   * @param  LastBitClockPulse This parameter can be one of the following values:
01083   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01084   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01085   * @retval None
01086   */
01087 __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
01088 {
01089   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
01090 }
01091
01092 /**
01093   * @brief  Retrieve Clock pulse of the last data bit output configuration
01094   *         (Last bit Clock pulse output to the SCLK pin or not)
01095   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01096   *         Synchronous mode is supported by the USARTx instance.
01097   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
01098   * @param  USARTx USART Instance
01099   * @retval Returned value can be one of the following values:
01100   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01101   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01102   */
01103 __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
01104 {
01105   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
01106 }
01107
01108 /**
01109   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
01110   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01111   *         Synchronous mode is supported by the USARTx instance.
01112   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
01113   * @param  USARTx USART Instance
01114   * @param  ClockPhase This parameter can be one of the following values:
01115   *         @arg @ref LL_USART_PHASE_1EDGE
01116   *         @arg @ref LL_USART_PHASE_2EDGE
01117   * @retval None
01118   */
01119 __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
01120 {
01121   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
01122 }
01123
01124 /**
01125   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
01126   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01127   *         Synchronous mode is supported by the USARTx instance.
01128   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
01129   * @param  USARTx USART Instance
01130   * @retval Returned value can be one of the following values:
01131   *         @arg @ref LL_USART_PHASE_1EDGE
01132   *         @arg @ref LL_USART_PHASE_2EDGE
01133   */
01134 __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
01135 {
01136   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
01137 }
01138
01139 /**
01140   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
01141   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01142   *         Synchronous mode is supported by the USARTx instance.
01143   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
01144   * @param  USARTx USART Instance
01145   * @param  ClockPolarity This parameter can be one of the following values:
01146   *         @arg @ref LL_USART_POLARITY_LOW
01147   *         @arg @ref LL_USART_POLARITY_HIGH
01148   * @retval None
01149   */
01150 __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
01151 {
01152   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
01153 }
01154
01155 /**
01156   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
01157   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01158   *         Synchronous mode is supported by the USARTx instance.
01159   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
01160   * @param  USARTx USART Instance
01161   * @retval Returned value can be one of the following values:
01162   *         @arg @ref LL_USART_POLARITY_LOW
01163   *         @arg @ref LL_USART_POLARITY_HIGH
01164   */
01165 __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
01166 {
01167   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
01168 }
01169
01170 /**
01171   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
01172   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01173   *         Synchronous mode is supported by the USARTx instance.
01174   * @note   Call of this function is equivalent to following function call sequence :
01175   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
01176   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
01177   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
01178   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
01179   *         CR2          CPOL          LL_USART_ConfigClock\n
01180   *         CR2          LBCL          LL_USART_ConfigClock
01181   * @param  USARTx USART Instance
01182   * @param  Phase This parameter can be one of the following values:
01183   *         @arg @ref LL_USART_PHASE_1EDGE
01184   *         @arg @ref LL_USART_PHASE_2EDGE
01185   * @param  Polarity This parameter can be one of the following values:
01186   *         @arg @ref LL_USART_POLARITY_LOW
01187   *         @arg @ref LL_USART_POLARITY_HIGH
01188   * @param  LBCPOutput This parameter can be one of the following values:
01189   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01190   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01191   * @retval None
01192   */
01193 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
01194 {
01195   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
01196 }
01197
01198 /**
01199   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
01200   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01201   *         FIFO mode feature is supported by the USARTx instance.
01202   * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
01203   * @param  USARTx USART Instance
01204   * @param  PrescalerValue This parameter can be one of the following values:
01205   *         @arg @ref LL_USART_PRESCALER_DIV1
01206   *         @arg @ref LL_USART_PRESCALER_DIV2
01207   *         @arg @ref LL_USART_PRESCALER_DIV4
01208   *         @arg @ref LL_USART_PRESCALER_DIV6
01209   *         @arg @ref LL_USART_PRESCALER_DIV8
01210   *         @arg @ref LL_USART_PRESCALER_DIV10
01211   *         @arg @ref LL_USART_PRESCALER_DIV12
01212   *         @arg @ref LL_USART_PRESCALER_DIV16
01213   *         @arg @ref LL_USART_PRESCALER_DIV32
01214   *         @arg @ref LL_USART_PRESCALER_DIV64
01215   *         @arg @ref LL_USART_PRESCALER_DIV128
01216   *         @arg @ref LL_USART_PRESCALER_DIV256
01217   * @retval None
01218   */
01219 __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01220 {
01221   MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
01222 }
01223
01224 /**
01225   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
01226   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01227   *         FIFO mode feature is supported by the USARTx instance.
01228   * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
01229   * @param  USARTx USART Instance
01230   * @retval Returned value can be one of the following values:
01231   *         @arg @ref LL_USART_PRESCALER_DIV1
01232   *         @arg @ref LL_USART_PRESCALER_DIV2
01233   *         @arg @ref LL_USART_PRESCALER_DIV4
01234   *         @arg @ref LL_USART_PRESCALER_DIV6
01235   *         @arg @ref LL_USART_PRESCALER_DIV8
01236   *         @arg @ref LL_USART_PRESCALER_DIV10
01237   *         @arg @ref LL_USART_PRESCALER_DIV12
01238   *         @arg @ref LL_USART_PRESCALER_DIV16
01239   *         @arg @ref LL_USART_PRESCALER_DIV32
01240   *         @arg @ref LL_USART_PRESCALER_DIV64
01241   *         @arg @ref LL_USART_PRESCALER_DIV128
01242   *         @arg @ref LL_USART_PRESCALER_DIV256
01243   */
01244 __STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx)
01245 {
01246   return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
01247 }
01248
01249 /**
01250   * @brief  Enable Clock output on SCLK pin
01251   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01252   *         Synchronous mode is supported by the USARTx instance.
01253   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
01254   * @param  USARTx USART Instance
01255   * @retval None
01256   */
01257 __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
01258 {
01259   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
01260 }
01261
01262 /**
01263   * @brief  Disable Clock output on SCLK pin
01264   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01265   *         Synchronous mode is supported by the USARTx instance.
01266   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
01267   * @param  USARTx USART Instance
01268   * @retval None
01269   */
01270 __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
01271 {
01272   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
01273 }
01274
01275 /**
01276   * @brief  Indicate if Clock output on SCLK pin is enabled
01277   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
01278   *         Synchronous mode is supported by the USARTx instance.
01279   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
01280   * @param  USARTx USART Instance
01281   * @retval State of bit (1 or 0).
01282   */
01283 __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
01284 {
01285   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
01286 }
01287
01288 /**
01289   * @brief  Set the length of the stop bits
01290   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
01291   * @param  USARTx USART Instance
01292   * @param  StopBits This parameter can be one of the following values:
01293   *         @arg @ref LL_USART_STOPBITS_0_5
01294   *         @arg @ref LL_USART_STOPBITS_1
01295   *         @arg @ref LL_USART_STOPBITS_1_5
01296   *         @arg @ref LL_USART_STOPBITS_2
01297   * @retval None
01298   */
01299 __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
01300 {
01301   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01302 }
01303
01304 /**
01305   * @brief  Retrieve the length of the stop bits
01306   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
01307   * @param  USARTx USART Instance
01308   * @retval Returned value can be one of the following values:
01309   *         @arg @ref LL_USART_STOPBITS_0_5
01310   *         @arg @ref LL_USART_STOPBITS_1
01311   *         @arg @ref LL_USART_STOPBITS_1_5
01312   *         @arg @ref LL_USART_STOPBITS_2
01313   */
01314 __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
01315 {
01316   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
01317 }
01318
01319 /**
01320   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
01321   * @note   Call of this function is equivalent to following function call sequence :
01322   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
01323   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
01324   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
01325   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
01326   *         CR1          PCE           LL_USART_ConfigCharacter\n
01327   *         CR1          M0            LL_USART_ConfigCharacter\n
01328   *         CR1          M1            LL_USART_ConfigCharacter\n
01329   *         CR2          STOP          LL_USART_ConfigCharacter
01330   * @param  USARTx USART Instance
01331   * @param  DataWidth This parameter can be one of the following values:
01332   *         @arg @ref LL_USART_DATAWIDTH_7B
01333   *         @arg @ref LL_USART_DATAWIDTH_8B
01334   *         @arg @ref LL_USART_DATAWIDTH_9B
01335   * @param  Parity This parameter can be one of the following values:
01336   *         @arg @ref LL_USART_PARITY_NONE
01337   *         @arg @ref LL_USART_PARITY_EVEN
01338   *         @arg @ref LL_USART_PARITY_ODD
01339   * @param  StopBits This parameter can be one of the following values:
01340   *         @arg @ref LL_USART_STOPBITS_0_5
01341   *         @arg @ref LL_USART_STOPBITS_1
01342   *         @arg @ref LL_USART_STOPBITS_1_5
01343   *         @arg @ref LL_USART_STOPBITS_2
01344   * @retval None
01345   */
01346 __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
01347                                               uint32_t StopBits)
01348 {
01349   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01350   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01351 }
01352
01353 /**
01354   * @brief  Configure TX/RX pins swapping setting.
01355   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
01356   * @param  USARTx USART Instance
01357   * @param  SwapConfig This parameter can be one of the following values:
01358   *         @arg @ref LL_USART_TXRX_STANDARD
01359   *         @arg @ref LL_USART_TXRX_SWAPPED
01360   * @retval None
01361   */
01362 __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
01363 {
01364   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
01365 }
01366
01367 /**
01368   * @brief  Retrieve TX/RX pins swapping configuration.
01369   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
01370   * @param  USARTx USART Instance
01371   * @retval Returned value can be one of the following values:
01372   *         @arg @ref LL_USART_TXRX_STANDARD
01373   *         @arg @ref LL_USART_TXRX_SWAPPED
01374   */
01375 __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
01376 {
01377   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
01378 }
01379
01380 /**
01381   * @brief  Configure RX pin active level logic
01382   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
01383   * @param  USARTx USART Instance
01384   * @param  PinInvMethod This parameter can be one of the following values:
01385   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01386   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01387   * @retval None
01388   */
01389 __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01390 {
01391   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01392 }
01393
01394 /**
01395   * @brief  Retrieve RX pin active level logic configuration
01396   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
01397   * @param  USARTx USART Instance
01398   * @retval Returned value can be one of the following values:
01399   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01400   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01401   */
01402 __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
01403 {
01404   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
01405 }
01406
01407 /**
01408   * @brief  Configure TX pin active level logic
01409   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
01410   * @param  USARTx USART Instance
01411   * @param  PinInvMethod This parameter can be one of the following values:
01412   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01413   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01414   * @retval None
01415   */
01416 __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01417 {
01418   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01419 }
01420
01421 /**
01422   * @brief  Retrieve TX pin active level logic configuration
01423   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
01424   * @param  USARTx USART Instance
01425   * @retval Returned value can be one of the following values:
01426   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01427   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01428   */
01429 __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
01430 {
01431   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
01432 }
01433
01434 /**
01435   * @brief  Configure Binary data logic.
01436   * @note   Allow to define how Logical data from the data register are send/received :
01437   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01438   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
01439   * @param  USARTx USART Instance
01440   * @param  DataLogic This parameter can be one of the following values:
01441   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01442   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01443   * @retval None
01444   */
01445 __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
01446 {
01447   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
01448 }
01449
01450 /**
01451   * @brief  Retrieve Binary data configuration
01452   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
01453   * @param  USARTx USART Instance
01454   * @retval Returned value can be one of the following values:
01455   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01456   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01457   */
01458 __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
01459 {
01460   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
01461 }
01462
01463 /**
01464   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01465   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01466   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01467   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
01468   * @param  USARTx USART Instance
01469   * @param  BitOrder This parameter can be one of the following values:
01470   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01471   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01472   * @retval None
01473   */
01474 __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
01475 {
01476   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01477 }
01478
01479 /**
01480   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01481   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01482   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01483   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
01484   * @param  USARTx USART Instance
01485   * @retval Returned value can be one of the following values:
01486   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01487   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01488   */
01489 __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
01490 {
01491   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
01492 }
01493
01494 /**
01495   * @brief  Enable Auto Baud-Rate Detection
01496   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01497   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01498   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
01499   * @param  USARTx USART Instance
01500   * @retval None
01501   */
01502 __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
01503 {
01504   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
01505 }
01506
01507 /**
01508   * @brief  Disable Auto Baud-Rate Detection
01509   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01510   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01511   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
01512   * @param  USARTx USART Instance
01513   * @retval None
01514   */
01515 __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
01516 {
01517   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
01518 }
01519
01520 /**
01521   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
01522   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01523   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01524   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
01525   * @param  USARTx USART Instance
01526   * @retval State of bit (1 or 0).
01527   */
01528 __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
01529 {
01530   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
01531 }
01532
01533 /**
01534   * @brief  Set Auto Baud-Rate mode bits
01535   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01536   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01537   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
01538   * @param  USARTx USART Instance
01539   * @param  AutoBaudRateMode This parameter can be one of the following values:
01540   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01541   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01542   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01543   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01544   * @retval None
01545   */
01546 __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
01547 {
01548   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
01549 }
01550
01551 /**
01552   * @brief  Return Auto Baud-Rate mode
01553   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01554   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01555   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
01556   * @param  USARTx USART Instance
01557   * @retval Returned value can be one of the following values:
01558   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01559   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01560   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01561   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01562   */
01563 __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
01564 {
01565   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
01566 }
01567
01568 /**
01569   * @brief  Enable Receiver Timeout
01570   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
01571   * @param  USARTx USART Instance
01572   * @retval None
01573   */
01574 __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
01575 {
01576   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
01577 }
01578
01579 /**
01580   * @brief  Disable Receiver Timeout
01581   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
01582   * @param  USARTx USART Instance
01583   * @retval None
01584   */
01585 __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
01586 {
01587   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
01588 }
01589
01590 /**
01591   * @brief  Indicate if Receiver Timeout feature is enabled
01592   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
01593   * @param  USARTx USART Instance
01594   * @retval State of bit (1 or 0).
01595   */
01596 __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
01597 {
01598   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
01599 }
01600
01601 /**
01602   * @brief  Set Address of the USART node.
01603   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01604   *         for wake up with address mark detection.
01605   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01606   *         (b7-b4 should be set to 0)
01607   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01608   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01609   *         for wake up with 7-bit address mark detection.
01610   *         The MSB of the character sent by the transmitter should be equal to 1.
01611   *         It may also be used for character detection during normal reception,
01612   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01613   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01614   *         value and CMF flag is set on match)
01615   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
01616   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
01617   * @param  USARTx USART Instance
01618   * @param  AddressLen This parameter can be one of the following values:
01619   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01620   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01621   * @param  NodeAddress 4 or 7 bit Address of the USART node.
01622   * @retval None
01623   */
01624 __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
01625 {
01626   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01627              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01628 }
01629
01630 /**
01631   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
01632   * @note   If 4-bit Address Detection is selected in ADDM7,
01633   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01634   *         If 7-bit Address Detection is selected in ADDM7,
01635   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01636   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
01637   * @param  USARTx USART Instance
01638   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
01639   */
01640 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
01641 {
01642   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01643 }
01644
01645 /**
01646   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01647   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
01648   * @param  USARTx USART Instance
01649   * @retval Returned value can be one of the following values:
01650   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01651   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01652   */
01653 __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
01654 {
01655   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
01656 }
01657
01658 /**
01659   * @brief  Enable RTS HW Flow Control
01660   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01661   *         Hardware Flow control feature is supported by the USARTx instance.
01662   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
01663   * @param  USARTx USART Instance
01664   * @retval None
01665   */
01666 __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01667 {
01668   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
01669 }
01670
01671 /**
01672   * @brief  Disable RTS HW Flow Control
01673   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01674   *         Hardware Flow control feature is supported by the USARTx instance.
01675   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
01676   * @param  USARTx USART Instance
01677   * @retval None
01678   */
01679 __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01680 {
01681   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
01682 }
01683
01684 /**
01685   * @brief  Enable CTS HW Flow Control
01686   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01687   *         Hardware Flow control feature is supported by the USARTx instance.
01688   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
01689   * @param  USARTx USART Instance
01690   * @retval None
01691   */
01692 __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01693 {
01694   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
01695 }
01696
01697 /**
01698   * @brief  Disable CTS HW Flow Control
01699   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01700   *         Hardware Flow control feature is supported by the USARTx instance.
01701   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
01702   * @param  USARTx USART Instance
01703   * @retval None
01704   */
01705 __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01706 {
01707   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
01708 }
01709
01710 /**
01711   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01712   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01713   *         Hardware Flow control feature is supported by the USARTx instance.
01714   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
01715   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
01716   * @param  USARTx USART Instance
01717   * @param  HardwareFlowControl This parameter can be one of the following values:
01718   *         @arg @ref LL_USART_HWCONTROL_NONE
01719   *         @arg @ref LL_USART_HWCONTROL_RTS
01720   *         @arg @ref LL_USART_HWCONTROL_CTS
01721   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01722   * @retval None
01723   */
01724 __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
01725 {
01726   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01727 }
01728
01729 /**
01730   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01731   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01732   *         Hardware Flow control feature is supported by the USARTx instance.
01733   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
01734   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
01735   * @param  USARTx USART Instance
01736   * @retval Returned value can be one of the following values:
01737   *         @arg @ref LL_USART_HWCONTROL_NONE
01738   *         @arg @ref LL_USART_HWCONTROL_RTS
01739   *         @arg @ref LL_USART_HWCONTROL_CTS
01740   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01741   */
01742 __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
01743 {
01744   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01745 }
01746
01747 /**
01748   * @brief  Enable One bit sampling method
01749   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
01750   * @param  USARTx USART Instance
01751   * @retval None
01752   */
01753 __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
01754 {
01755   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01756 }
01757
01758 /**
01759   * @brief  Disable One bit sampling method
01760   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
01761   * @param  USARTx USART Instance
01762   * @retval None
01763   */
01764 __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
01765 {
01766   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01767 }
01768
01769 /**
01770   * @brief  Indicate if One bit sampling method is enabled
01771   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
01772   * @param  USARTx USART Instance
01773   * @retval State of bit (1 or 0).
01774   */
01775 __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
01776 {
01777   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
01778 }
01779
01780 /**
01781   * @brief  Enable Overrun detection
01782   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
01783   * @param  USARTx USART Instance
01784   * @retval None
01785   */
01786 __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
01787 {
01788   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01789 }
01790
01791 /**
01792   * @brief  Disable Overrun detection
01793   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
01794   * @param  USARTx USART Instance
01795   * @retval None
01796   */
01797 __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
01798 {
01799   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01800 }
01801
01802 /**
01803   * @brief  Indicate if Overrun detection is enabled
01804   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
01805   * @param  USARTx USART Instance
01806   * @retval State of bit (1 or 0).
01807   */
01808 __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
01809 {
01810   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
01811 }
01812
01813 /**
01814   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01815   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01816   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01817   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
01818   * @param  USARTx USART Instance
01819   * @param  Type This parameter can be one of the following values:
01820   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01821   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01822   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01823   * @retval None
01824   */
01825 __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
01826 {
01827   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
01828 }
01829
01830 /**
01831   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01832   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01833   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01834   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
01835   * @param  USARTx USART Instance
01836   * @retval Returned value can be one of the following values:
01837   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01838   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01839   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01840   */
01841 __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
01842 {
01843   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
01844 }
01845
01846 /**
01847   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01848   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01849   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01850   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01851   *         (Baud rate value != 0)
01852   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01853   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01854   * @param  USARTx USART Instance
01855   * @param  PeriphClk Peripheral Clock
01856   * @param  PrescalerValue This parameter can be one of the following values:
01857   *         @arg @ref LL_USART_PRESCALER_DIV1
01858   *         @arg @ref LL_USART_PRESCALER_DIV2
01859   *         @arg @ref LL_USART_PRESCALER_DIV4
01860   *         @arg @ref LL_USART_PRESCALER_DIV6
01861   *         @arg @ref LL_USART_PRESCALER_DIV8
01862   *         @arg @ref LL_USART_PRESCALER_DIV10
01863   *         @arg @ref LL_USART_PRESCALER_DIV12
01864   *         @arg @ref LL_USART_PRESCALER_DIV16
01865   *         @arg @ref LL_USART_PRESCALER_DIV32
01866   *         @arg @ref LL_USART_PRESCALER_DIV64
01867   *         @arg @ref LL_USART_PRESCALER_DIV128
01868   *         @arg @ref LL_USART_PRESCALER_DIV256
01869   * @param  OverSampling This parameter can be one of the following values:
01870   *         @arg @ref LL_USART_OVERSAMPLING_16
01871   *         @arg @ref LL_USART_OVERSAMPLING_8
01872   * @param  BaudRate Baud Rate
01873   * @retval None
01874   */
01875 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01876                                           uint32_t OverSampling,
01877                                           uint32_t BaudRate)
01878 {
01879   uint32_t usartdiv;
01880   uint32_t brrtemp;
01881
01882   if (PrescalerValue > LL_USART_PRESCALER_DIV256)
01883   {
01884     /* Do not overstep the size of USART_PRESCALER_TAB */
01885   }
01886   else if (BaudRate == 0U)
01887   {
01888     /* Can Not divide per 0 */
01889   }
01890   else if (OverSampling == LL_USART_OVERSAMPLING_8)
01891   {
01892     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
01893     brrtemp = usartdiv & 0xFFF0U;
01894     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
01895     USARTx->BRR = brrtemp;
01896   }
01897   else
01898   {
01899     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
01900   }
01901 }
01902
01903 /**
01904   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01905   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01906   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01907   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01908   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01909   * @param  USARTx USART Instance
01910   * @param  PeriphClk Peripheral Clock
01911   * @param  PrescalerValue This parameter can be one of the following values:
01912   *         @arg @ref LL_USART_PRESCALER_DIV1
01913   *         @arg @ref LL_USART_PRESCALER_DIV2
01914   *         @arg @ref LL_USART_PRESCALER_DIV4
01915   *         @arg @ref LL_USART_PRESCALER_DIV6
01916   *         @arg @ref LL_USART_PRESCALER_DIV8
01917   *         @arg @ref LL_USART_PRESCALER_DIV10
01918   *         @arg @ref LL_USART_PRESCALER_DIV12
01919   *         @arg @ref LL_USART_PRESCALER_DIV16
01920   *         @arg @ref LL_USART_PRESCALER_DIV32
01921   *         @arg @ref LL_USART_PRESCALER_DIV64
01922   *         @arg @ref LL_USART_PRESCALER_DIV128
01923   *         @arg @ref LL_USART_PRESCALER_DIV256
01924   * @param  OverSampling This parameter can be one of the following values:
01925   *         @arg @ref LL_USART_OVERSAMPLING_16
01926   *         @arg @ref LL_USART_OVERSAMPLING_8
01927   * @retval Baud Rate
01928   */
01929 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01930                                               uint32_t OverSampling)
01931 {
01932   uint32_t usartdiv;
01933   uint32_t brrresult = 0x0U;
01934   uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
01935
01936   usartdiv = USARTx->BRR;
01937
01938   if (usartdiv == 0U)
01939   {
01940     /* Do not perform a division by 0 */
01941   }
01942   else if (OverSampling == LL_USART_OVERSAMPLING_8)
01943   {
01944     usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
01945     if (usartdiv != 0U)
01946     {
01947       brrresult = (periphclkpresc * 2U) / usartdiv;
01948     }
01949   }
01950   else
01951   {
01952     if ((usartdiv & 0xFFFFU) != 0U)
01953     {
01954       brrresult = periphclkpresc / usartdiv;
01955     }
01956   }
01957   return (brrresult);
01958 }
01959
01960 /**
01961   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
01962   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
01963   * @param  USARTx USART Instance
01964   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01965   * @retval None
01966   */
01967 __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
01968 {
01969   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
01970 }
01971
01972 /**
01973   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
01974   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
01975   * @param  USARTx USART Instance
01976   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01977   */
01978 __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
01979 {
01980   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
01981 }
01982
01983 /**
01984   * @brief  Set Block Length value in reception
01985   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
01986   * @param  USARTx USART Instance
01987   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
01988   * @retval None
01989   */
01990 __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
01991 {
01992   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
01993 }
01994
01995 /**
01996   * @brief  Get Block Length value in reception
01997   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
01998   * @param  USARTx USART Instance
01999   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02000   */
02001 __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
02002 {
02003   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
02004 }
02005
02006 /**
02007   * @}
02008   */
02009
02010 /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
02011   * @{
02012   */
02013
02014 /**
02015   * @brief  Enable IrDA mode
02016   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02017   *         IrDA feature is supported by the USARTx instance.
02018   * @rmtoll CR3          IREN          LL_USART_EnableIrda
02019   * @param  USARTx USART Instance
02020   * @retval None
02021   */
02022 __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
02023 {
02024   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02025 }
02026
02027 /**
02028   * @brief  Disable IrDA mode
02029   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02030   *         IrDA feature is supported by the USARTx instance.
02031   * @rmtoll CR3          IREN          LL_USART_DisableIrda
02032   * @param  USARTx USART Instance
02033   * @retval None
02034   */
02035 __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
02036 {
02037   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
02038 }
02039
02040 /**
02041   * @brief  Indicate if IrDA mode is enabled
02042   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02043   *         IrDA feature is supported by the USARTx instance.
02044   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
02045   * @param  USARTx USART Instance
02046   * @retval State of bit (1 or 0).
02047   */
02048 __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
02049 {
02050   return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
02051 }
02052
02053 /**
02054   * @brief  Configure IrDA Power Mode (Normal or Low Power)
02055   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02056   *         IrDA feature is supported by the USARTx instance.
02057   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
02058   * @param  USARTx USART Instance
02059   * @param  PowerMode This parameter can be one of the following values:
02060   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02061   *         @arg @ref LL_USART_IRDA_POWER_LOW
02062   * @retval None
02063   */
02064 __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
02065 {
02066   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
02067 }
02068
02069 /**
02070   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
02071   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02072   *         IrDA feature is supported by the USARTx instance.
02073   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
02074   * @param  USARTx USART Instance
02075   * @retval Returned value can be one of the following values:
02076   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02077   *         @arg @ref LL_USART_PHASE_2EDGE
02078   */
02079 __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
02080 {
02081   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
02082 }
02083
02084 /**
02085   * @brief  Set Irda prescaler value, used for dividing the USART clock source
02086   *         to achieve the Irda Low Power frequency (8 bits value)
02087   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02088   *         IrDA feature is supported by the USARTx instance.
02089   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
02090   * @param  USARTx USART Instance
02091   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
02092   * @retval None
02093   */
02094 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02095 {
02096   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
02097 }
02098
02099 /**
02100   * @brief  Return Irda prescaler value, used for dividing the USART clock source
02101   *         to achieve the Irda Low Power frequency (8 bits value)
02102   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02103   *         IrDA feature is supported by the USARTx instance.
02104   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
02105   * @param  USARTx USART Instance
02106   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
02107   */
02108 __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
02109 {
02110   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02111 }
02112
02113 /**
02114   * @}
02115   */
02116
02117 /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
02118   * @{
02119   */
02120
02121 /**
02122   * @brief  Enable Smartcard NACK transmission
02123   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02124   *         Smartcard feature is supported by the USARTx instance.
02125   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
02126   * @param  USARTx USART Instance
02127   * @retval None
02128   */
02129 __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
02130 {
02131   SET_BIT(USARTx->CR3, USART_CR3_NACK);
02132 }
02133
02134 /**
02135   * @brief  Disable Smartcard NACK transmission
02136   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02137   *         Smartcard feature is supported by the USARTx instance.
02138   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
02139   * @param  USARTx USART Instance
02140   * @retval None
02141   */
02142 __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
02143 {
02144   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
02145 }
02146
02147 /**
02148   * @brief  Indicate if Smartcard NACK transmission is enabled
02149   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02150   *         Smartcard feature is supported by the USARTx instance.
02151   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
02152   * @param  USARTx USART Instance
02153   * @retval State of bit (1 or 0).
02154   */
02155 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
02156 {
02157   return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
02158 }
02159
02160 /**
02161   * @brief  Enable Smartcard mode
02162   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02163   *         Smartcard feature is supported by the USARTx instance.
02164   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
02165   * @param  USARTx USART Instance
02166   * @retval None
02167   */
02168 __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
02169 {
02170   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02171 }
02172
02173 /**
02174   * @brief  Disable Smartcard mode
02175   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02176   *         Smartcard feature is supported by the USARTx instance.
02177   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
02178   * @param  USARTx USART Instance
02179   * @retval None
02180   */
02181 __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
02182 {
02183   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
02184 }
02185
02186 /**
02187   * @brief  Indicate if Smartcard mode is enabled
02188   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02189   *         Smartcard feature is supported by the USARTx instance.
02190   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
02191   * @param  USARTx USART Instance
02192   * @retval State of bit (1 or 0).
02193   */
02194 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
02195 {
02196   return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
02197 }
02198
02199 /**
02200   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02201   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02202   *         Smartcard feature is supported by the USARTx instance.
02203   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
02204   *         In transmission mode, it specifies the number of automatic retransmission retries, before
02205   *         generating a transmission error (FE bit set).
02206   *         In reception mode, it specifies the number or erroneous reception trials, before generating a
02207   *         reception error (RXNE and PE bits set)
02208   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
02209   * @param  USARTx USART Instance
02210   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
02211   * @retval None
02212   */
02213 __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
02214 {
02215   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
02216 }
02217
02218 /**
02219   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02220   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02221   *         Smartcard feature is supported by the USARTx instance.
02222   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
02223   * @param  USARTx USART Instance
02224   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
02225   */
02226 __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
02227 {
02228   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
02229 }
02230
02231 /**
02232   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
02233   *         source to provide the SMARTCARD Clock (5 bits value)
02234   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02235   *         Smartcard feature is supported by the USARTx instance.
02236   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
02237   * @param  USARTx USART Instance
02238   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
02239   * @retval None
02240   */
02241 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02242 {
02243   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
02244 }
02245
02246 /**
02247   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
02248   *         source to provide the SMARTCARD Clock (5 bits value)
02249   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02250   *         Smartcard feature is supported by the USARTx instance.
02251   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
02252   * @param  USARTx USART Instance
02253   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
02254   */
02255 __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
02256 {
02257   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02258 }
02259
02260 /**
02261   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
02262   *         (GT[7:0] bits : Guard time value)
02263   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02264   *         Smartcard feature is supported by the USARTx instance.
02265   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
02266   * @param  USARTx USART Instance
02267   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
02268   * @retval None
02269   */
02270 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
02271 {
02272   MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
02273 }
02274
02275 /**
02276   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
02277   *         (GT[7:0] bits : Guard time value)
02278   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02279   *         Smartcard feature is supported by the USARTx instance.
02280   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
02281   * @param  USARTx USART Instance
02282   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
02283   */
02284 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
02285 {
02286   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
02287 }
02288
02289 /**
02290   * @}
02291   */
02292
02293 /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
02294   * @{
02295   */
02296
02297 /**
02298   * @brief  Enable Single Wire Half-Duplex mode
02299   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02300   *         Half-Duplex mode is supported by the USARTx instance.
02301   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
02302   * @param  USARTx USART Instance
02303   * @retval None
02304   */
02305 __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
02306 {
02307   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02308 }
02309
02310 /**
02311   * @brief  Disable Single Wire Half-Duplex mode
02312   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02313   *         Half-Duplex mode is supported by the USARTx instance.
02314   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
02315   * @param  USARTx USART Instance
02316   * @retval None
02317   */
02318 __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
02319 {
02320   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
02321 }
02322
02323 /**
02324   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
02325   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02326   *         Half-Duplex mode is supported by the USARTx instance.
02327   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
02328   * @param  USARTx USART Instance
02329   * @retval State of bit (1 or 0).
02330   */
02331 __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
02332 {
02333   return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
02334 }
02335
02336 /**
02337   * @}
02338   */
02339
02340 /** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
02341   * @{
02342   */
02343 /**
02344   * @brief  Enable SPI Synchronous Slave mode
02345   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02346   *         SPI Slave mode feature is supported by the USARTx instance.
02347   * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
02348   * @param  USARTx USART Instance
02349   * @retval None
02350   */
02351 __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
02352 {
02353   SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
02354 }
02355
02356 /**
02357   * @brief  Disable SPI Synchronous Slave mode
02358   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02359   *         SPI Slave mode feature is supported by the USARTx instance.
02360   * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
02361   * @param  USARTx USART Instance
02362   * @retval None
02363   */
02364 __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
02365 {
02366   CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
02367 }
02368
02369 /**
02370   * @brief  Indicate if  SPI Synchronous Slave mode is enabled
02371   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02372   *         SPI Slave mode feature is supported by the USARTx instance.
02373   * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
02374   * @param  USARTx USART Instance
02375   * @retval State of bit (1 or 0).
02376   */
02377 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx)
02378 {
02379   return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
02380 }
02381
02382 /**
02383   * @brief  Enable SPI Slave Selection using NSS input pin
02384   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02385   *         SPI Slave mode feature is supported by the USARTx instance.
02386   * @note   SPI Slave Selection depends on NSS input pin
02387   *         (The slave is selected when NSS is low and deselected when NSS is high).
02388   * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
02389   * @param  USARTx USART Instance
02390   * @retval None
02391   */
02392 __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
02393 {
02394   CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02395 }
02396
02397 /**
02398   * @brief  Disable SPI Slave Selection using NSS input pin
02399   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02400   *         SPI Slave mode feature is supported by the USARTx instance.
02401   * @note   SPI Slave will be always selected and NSS input pin will be ignored.
02402   * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
02403   * @param  USARTx USART Instance
02404   * @retval None
02405   */
02406 __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
02407 {
02408   SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02409 }
02410
02411 /**
02412   * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
02413   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02414   *         SPI Slave mode feature is supported by the USARTx instance.
02415   * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
02416   * @param  USARTx USART Instance
02417   * @retval State of bit (1 or 0).
02418   */
02419 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx)
02420 {
02421   return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
02422 }
02423
02424 /**
02425   * @}
02426   */
02427
02428 /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
02429   * @{
02430   */
02431
02432 /**
02433   * @brief  Set LIN Break Detection Length
02434   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02435   *         LIN feature is supported by the USARTx instance.
02436   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
02437   * @param  USARTx USART Instance
02438   * @param  LINBDLength This parameter can be one of the following values:
02439   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02440   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02441   * @retval None
02442   */
02443 __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
02444 {
02445   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
02446 }
02447
02448 /**
02449   * @brief  Return LIN Break Detection Length
02450   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02451   *         LIN feature is supported by the USARTx instance.
02452   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
02453   * @param  USARTx USART Instance
02454   * @retval Returned value can be one of the following values:
02455   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02456   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02457   */
02458 __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
02459 {
02460   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
02461 }
02462
02463 /**
02464   * @brief  Enable LIN mode
02465   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02466   *         LIN feature is supported by the USARTx instance.
02467   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
02468   * @param  USARTx USART Instance
02469   * @retval None
02470   */
02471 __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
02472 {
02473   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02474 }
02475
02476 /**
02477   * @brief  Disable LIN mode
02478   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02479   *         LIN feature is supported by the USARTx instance.
02480   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
02481   * @param  USARTx USART Instance
02482   * @retval None
02483   */
02484 __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
02485 {
02486   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
02487 }
02488
02489 /**
02490   * @brief  Indicate if LIN mode is enabled
02491   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02492   *         LIN feature is supported by the USARTx instance.
02493   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
02494   * @param  USARTx USART Instance
02495   * @retval State of bit (1 or 0).
02496   */
02497 __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
02498 {
02499   return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
02500 }
02501
02502 /**
02503   * @}
02504   */
02505
02506 /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
02507   * @{
02508   */
02509
02510 /**
02511   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02512   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02513   *         Driver Enable feature is supported by the USARTx instance.
02514   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
02515   * @param  USARTx USART Instance
02516   * @param  Time Value between Min_Data=0 and Max_Data=31
02517   * @retval None
02518   */
02519 __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
02520 {
02521   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
02522 }
02523
02524 /**
02525   * @brief  Return DEDT (Driver Enable De-Assertion Time)
02526   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02527   *         Driver Enable feature is supported by the USARTx instance.
02528   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
02529   * @param  USARTx USART Instance
02530   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02531   */
02532 __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
02533 {
02534   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
02535 }
02536
02537 /**
02538   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02539   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02540   *         Driver Enable feature is supported by the USARTx instance.
02541   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
02542   * @param  USARTx USART Instance
02543   * @param  Time Value between Min_Data=0 and Max_Data=31
02544   * @retval None
02545   */
02546 __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
02547 {
02548   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
02549 }
02550
02551 /**
02552   * @brief  Return DEAT (Driver Enable Assertion Time)
02553   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02554   *         Driver Enable feature is supported by the USARTx instance.
02555   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
02556   * @param  USARTx USART Instance
02557   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02558   */
02559 __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
02560 {
02561   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
02562 }
02563
02564 /**
02565   * @brief  Enable Driver Enable (DE) Mode
02566   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02567   *         Driver Enable feature is supported by the USARTx instance.
02568   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
02569   * @param  USARTx USART Instance
02570   * @retval None
02571   */
02572 __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
02573 {
02574   SET_BIT(USARTx->CR3, USART_CR3_DEM);
02575 }
02576
02577 /**
02578   * @brief  Disable Driver Enable (DE) Mode
02579   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02580   *         Driver Enable feature is supported by the USARTx instance.
02581   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
02582   * @param  USARTx USART Instance
02583   * @retval None
02584   */
02585 __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
02586 {
02587   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
02588 }
02589
02590 /**
02591   * @brief  Indicate if Driver Enable (DE) Mode is enabled
02592   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02593   *         Driver Enable feature is supported by the USARTx instance.
02594   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
02595   * @param  USARTx USART Instance
02596   * @retval State of bit (1 or 0).
02597   */
02598 __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
02599 {
02600   return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
02601 }
02602
02603 /**
02604   * @brief  Select Driver Enable Polarity
02605   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02606   *         Driver Enable feature is supported by the USARTx instance.
02607   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
02608   * @param  USARTx USART Instance
02609   * @param  Polarity This parameter can be one of the following values:
02610   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02611   *         @arg @ref LL_USART_DE_POLARITY_LOW
02612   * @retval None
02613   */
02614 __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
02615 {
02616   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
02617 }
02618
02619 /**
02620   * @brief  Return Driver Enable Polarity
02621   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02622   *         Driver Enable feature is supported by the USARTx instance.
02623   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
02624   * @param  USARTx USART Instance
02625   * @retval Returned value can be one of the following values:
02626   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02627   *         @arg @ref LL_USART_DE_POLARITY_LOW
02628   */
02629 __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
02630 {
02631   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
02632 }
02633
02634 /**
02635   * @}
02636   */
02637
02638 /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
02639   * @{
02640   */
02641
02642 /**
02643   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
02644   * @note   In UART mode, the following bits must be kept cleared:
02645   *           - LINEN bit in the USART_CR2 register,
02646   *           - CLKEN bit in the USART_CR2 register,
02647   *           - SCEN bit in the USART_CR3 register,
02648   *           - IREN bit in the USART_CR3 register,
02649   *           - HDSEL bit in the USART_CR3 register.
02650   * @note   Call of this function is equivalent to following function call sequence :
02651   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02652   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02653   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02654   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02655   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02656   * @note   Other remaining configurations items related to Asynchronous Mode
02657   *         (as Baud Rate, Word length, Parity, ...) should be set using
02658   *         dedicated functions
02659   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
02660   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
02661   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
02662   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
02663   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
02664   * @param  USARTx USART Instance
02665   * @retval None
02666   */
02667 __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
02668 {
02669   /* In Asynchronous mode, the following bits must be kept cleared:
02670   - LINEN, CLKEN bits in the USART_CR2 register,
02671   - SCEN, IREN and HDSEL bits in the USART_CR3 register.
02672   */
02673   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02674   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02675 }
02676
02677 /**
02678   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
02679   * @note   In Synchronous mode, the following bits must be kept cleared:
02680   *           - LINEN bit in the USART_CR2 register,
02681   *           - SCEN bit in the USART_CR3 register,
02682   *           - IREN bit in the USART_CR3 register,
02683   *           - HDSEL bit in the USART_CR3 register.
02684   *         This function also sets the USART in Synchronous mode.
02685   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
02686   *         Synchronous mode is supported by the USARTx instance.
02687   * @note   Call of this function is equivalent to following function call sequence :
02688   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02689   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02690   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02691   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02692   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02693   * @note   Other remaining configurations items related to Synchronous Mode
02694   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
02695   *         dedicated functions
02696   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
02697   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
02698   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
02699   *         CR3          IREN          LL_USART_ConfigSyncMode\n
02700   *         CR3          HDSEL         LL_USART_ConfigSyncMode
02701   * @param  USARTx USART Instance
02702   * @retval None
02703   */
02704 __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
02705 {
02706   /* In Synchronous mode, the following bits must be kept cleared:
02707   - LINEN bit in the USART_CR2 register,
02708   - SCEN, IREN and HDSEL bits in the USART_CR3 register.
02709   */
02710   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02711   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02712   /* set the UART/USART in Synchronous mode */
02713   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
02714 }
02715
02716 /**
02717   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
02718   * @note   In LIN mode, the following bits must be kept cleared:
02719   *           - STOP and CLKEN bits in the USART_CR2 register,
02720   *           - SCEN bit in the USART_CR3 register,
02721   *           - IREN bit in the USART_CR3 register,
02722   *           - HDSEL bit in the USART_CR3 register.
02723   *         This function also set the UART/USART in LIN mode.
02724   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02725   *         LIN feature is supported by the USARTx instance.
02726   * @note   Call of this function is equivalent to following function call sequence :
02727   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02728   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02729   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02730   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02731   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02732   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
02733   * @note   Other remaining configurations items related to LIN Mode
02734   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
02735   *         dedicated functions
02736   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
02737   *         CR2          STOP          LL_USART_ConfigLINMode\n
02738   *         CR2          LINEN         LL_USART_ConfigLINMode\n
02739   *         CR3          IREN          LL_USART_ConfigLINMode\n
02740   *         CR3          SCEN          LL_USART_ConfigLINMode\n
02741   *         CR3          HDSEL         LL_USART_ConfigLINMode
02742   * @param  USARTx USART Instance
02743   * @retval None
02744   */
02745 __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
02746 {
02747   /* In LIN mode, the following bits must be kept cleared:
02748   - STOP and CLKEN bits in the USART_CR2 register,
02749   - IREN, SCEN and HDSEL bits in the USART_CR3 register.
02750   */
02751   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
02752   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
02753   /* Set the UART/USART in LIN mode */
02754   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02755 }
02756
02757 /**
02758   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
02759   * @note   In Half Duplex mode, the following bits must be kept cleared:
02760   *           - LINEN bit in the USART_CR2 register,
02761   *           - CLKEN bit in the USART_CR2 register,
02762   *           - SCEN bit in the USART_CR3 register,
02763   *           - IREN bit in the USART_CR3 register,
02764   *         This function also sets the UART/USART in Half Duplex mode.
02765   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02766   *         Half-Duplex mode is supported by the USARTx instance.
02767   * @note   Call of this function is equivalent to following function call sequence :
02768   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02769   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02770   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02771   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02772   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
02773   * @note   Other remaining configurations items related to Half Duplex Mode
02774   *         (as Baud Rate, Word length, Parity, ...) should be set using
02775   *         dedicated functions
02776   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
02777   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
02778   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
02779   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
02780   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
02781   * @param  USARTx USART Instance
02782   * @retval None
02783   */
02784 __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
02785 {
02786   /* In Half Duplex mode, the following bits must be kept cleared:
02787   - LINEN and CLKEN bits in the USART_CR2 register,
02788   - SCEN and IREN bits in the USART_CR3 register.
02789   */
02790   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02791   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
02792   /* set the UART/USART in Half Duplex mode */
02793   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02794 }
02795
02796 /**
02797   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
02798   * @note   In Smartcard mode, the following bits must be kept cleared:
02799   *           - LINEN bit in the USART_CR2 register,
02800   *           - IREN bit in the USART_CR3 register,
02801   *           - HDSEL bit in the USART_CR3 register.
02802   *         This function also configures Stop bits to 1.5 bits and
02803   *         sets the USART in Smartcard mode (SCEN bit).
02804   *         Clock Output is also enabled (CLKEN).
02805   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02806   *         Smartcard feature is supported by the USARTx instance.
02807   * @note   Call of this function is equivalent to following function call sequence :
02808   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02809   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02810   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02811   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02812   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02813   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
02814   * @note   Other remaining configurations items related to Smartcard Mode
02815   *         (as Baud Rate, Word length, Parity, ...) should be set using
02816   *         dedicated functions
02817   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
02818   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
02819   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
02820   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
02821   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
02822   * @param  USARTx USART Instance
02823   * @retval None
02824   */
02825 __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
02826 {
02827   /* In Smartcard mode, the following bits must be kept cleared:
02828   - LINEN bit in the USART_CR2 register,
02829   - IREN and HDSEL bits in the USART_CR3 register.
02830   */
02831   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02832   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
02833   /* Configure Stop bits to 1.5 bits */
02834   /* Synchronous mode is activated by default */
02835   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
02836   /* set the UART/USART in Smartcard mode */
02837   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02838 }
02839
02840 /**
02841   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
02842   * @note   In IRDA mode, the following bits must be kept cleared:
02843   *           - LINEN bit in the USART_CR2 register,
02844   *           - STOP and CLKEN bits in the USART_CR2 register,
02845   *           - SCEN bit in the USART_CR3 register,
02846   *           - HDSEL bit in the USART_CR3 register.
02847   *         This function also sets the UART/USART in IRDA mode (IREN bit).
02848   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02849   *         IrDA feature is supported by the USARTx instance.
02850   * @note   Call of this function is equivalent to following function call sequence :
02851   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02852   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02853   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02854   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02855   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02856   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
02857   * @note   Other remaining configurations items related to Irda Mode
02858   *         (as Baud Rate, Word length, Power mode, ...) should be set using
02859   *         dedicated functions
02860   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
02861   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
02862   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
02863   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
02864   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
02865   *         CR3          IREN          LL_USART_ConfigIrdaMode
02866   * @param  USARTx USART Instance
02867   * @retval None
02868   */
02869 __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
02870 {
02871   /* In IRDA mode, the following bits must be kept cleared:
02872   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
02873   - SCEN and HDSEL bits in the USART_CR3 register.
02874   */
02875   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
02876   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
02877   /* set the UART/USART in IRDA mode */
02878   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02879 }
02880
02881 /**
02882   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
02883   *         (several USARTs connected in a network, one of the USARTs can be the master,
02884   *         its TX output connected to the RX inputs of the other slaves USARTs).
02885   * @note   In MultiProcessor mode, the following bits must be kept cleared:
02886   *           - LINEN bit in the USART_CR2 register,
02887   *           - CLKEN bit in the USART_CR2 register,
02888   *           - SCEN bit in the USART_CR3 register,
02889   *           - IREN bit in the USART_CR3 register,
02890   *           - HDSEL bit in the USART_CR3 register.
02891   * @note   Call of this function is equivalent to following function call sequence :
02892   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02893   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02894   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02895   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02896   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02897   * @note   Other remaining configurations items related to Multi processor Mode
02898   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
02899   *         dedicated functions
02900   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
02901   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
02902   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
02903   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
02904   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
02905   * @param  USARTx USART Instance
02906   * @retval None
02907   */
02908 __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
02909 {
02910   /* In Multi Processor mode, the following bits must be kept cleared:
02911   - LINEN and CLKEN bits in the USART_CR2 register,
02912   - IREN, SCEN and HDSEL bits in the USART_CR3 register.
02913   */
02914   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02915   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
02916 }
02917
02918 /**
02919   * @}
02920   */
02921
02922 /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
02923   * @{
02924   */
02925
02926 /**
02927   * @brief  Check if the USART Parity Error Flag is set or not
02928   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
02929   * @param  USARTx USART Instance
02930   * @retval State of bit (1 or 0).
02931   */
02932 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
02933 {
02934   return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
02935 }
02936
02937 /**
02938   * @brief  Check if the USART Framing Error Flag is set or not
02939   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
02940   * @param  USARTx USART Instance
02941   * @retval State of bit (1 or 0).
02942   */
02943 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
02944 {
02945   return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
02946 }
02947
02948 /**
02949   * @brief  Check if the USART Noise error detected Flag is set or not
02950   * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
02951   * @param  USARTx USART Instance
02952   * @retval State of bit (1 or 0).
02953   */
02954 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
02955 {
02956   return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
02957 }
02958
02959 /**
02960   * @brief  Check if the USART OverRun Error Flag is set or not
02961   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
02962   * @param  USARTx USART Instance
02963   * @retval State of bit (1 or 0).
02964   */
02965 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
02966 {
02967   return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
02968 }
02969
02970 /**
02971   * @brief  Check if the USART IDLE line detected Flag is set or not
02972   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
02973   * @param  USARTx USART Instance
02974   * @retval State of bit (1 or 0).
02975   */
02976 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
02977 {
02978   return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
02979 }
02980
02981 /* Legacy define */
02982 #define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
02983
02984 /**
02985   * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
02986   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
02987   *         FIFO mode feature is supported by the USARTx instance.
02988   * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
02989   * @param  USARTx USART Instance
02990   * @retval State of bit (1 or 0).
02991   */
02992 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx)
02993 {
02994   return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
02995 }
02996
02997 /**
02998   * @brief  Check if the USART Transmission Complete Flag is set or not
02999   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
03000   * @param  USARTx USART Instance
03001   * @retval State of bit (1 or 0).
03002   */
03003 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
03004 {
03005   return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
03006 }
03007
03008 /* Legacy define */
03009 #define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
03010
03011 /**
03012   * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
03013   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03014   *         FIFO mode feature is supported by the USARTx instance.
03015   * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
03016   * @param  USARTx USART Instance
03017   * @retval State of bit (1 or 0).
03018   */
03019 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx)
03020 {
03021   return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
03022 }
03023
03024 /**
03025   * @brief  Check if the USART LIN Break Detection Flag is set or not
03026   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03027   *         LIN feature is supported by the USARTx instance.
03028   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
03029   * @param  USARTx USART Instance
03030   * @retval State of bit (1 or 0).
03031   */
03032 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
03033 {
03034   return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
03035 }
03036
03037 /**
03038   * @brief  Check if the USART CTS interrupt Flag is set or not
03039   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03040   *         Hardware Flow control feature is supported by the USARTx instance.
03041   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
03042   * @param  USARTx USART Instance
03043   * @retval State of bit (1 or 0).
03044   */
03045 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
03046 {
03047   return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
03048 }
03049
03050 /**
03051   * @brief  Check if the USART CTS Flag is set or not
03052   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03053   *         Hardware Flow control feature is supported by the USARTx instance.
03054   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
03055   * @param  USARTx USART Instance
03056   * @retval State of bit (1 or 0).
03057   */
03058 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
03059 {
03060   return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
03061 }
03062
03063 /**
03064   * @brief  Check if the USART Receiver Time Out Flag is set or not
03065   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
03066   * @param  USARTx USART Instance
03067   * @retval State of bit (1 or 0).
03068   */
03069 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
03070 {
03071   return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
03072 }
03073
03074 /**
03075   * @brief  Check if the USART End Of Block Flag is set or not
03076   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03077   *         Smartcard feature is supported by the USARTx instance.
03078   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
03079   * @param  USARTx USART Instance
03080   * @retval State of bit (1 or 0).
03081   */
03082 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
03083 {
03084   return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
03085 }
03086
03087 /**
03088   * @brief  Check if the SPI Slave Underrun error flag is set or not
03089   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03090   *         SPI Slave mode feature is supported by the USARTx instance.
03091   * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
03092   * @param  USARTx USART Instance
03093   * @retval State of bit (1 or 0).
03094   */
03095 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx)
03096 {
03097   return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
03098 }
03099
03100 /**
03101   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
03102   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03103   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03104   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
03105   * @param  USARTx USART Instance
03106   * @retval State of bit (1 or 0).
03107   */
03108 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
03109 {
03110   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
03111 }
03112
03113 /**
03114   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
03115   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03116   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03117   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
03118   * @param  USARTx USART Instance
03119   * @retval State of bit (1 or 0).
03120   */
03121 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
03122 {
03123   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
03124 }
03125
03126 /**
03127   * @brief  Check if the USART Busy Flag is set or not
03128   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
03129   * @param  USARTx USART Instance
03130   * @retval State of bit (1 or 0).
03131   */
03132 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
03133 {
03134   return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
03135 }
03136
03137 /**
03138   * @brief  Check if the USART Character Match Flag is set or not
03139   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
03140   * @param  USARTx USART Instance
03141   * @retval State of bit (1 or 0).
03142   */
03143 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
03144 {
03145   return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
03146 }
03147
03148 /**
03149   * @brief  Check if the USART Send Break Flag is set or not
03150   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
03151   * @param  USARTx USART Instance
03152   * @retval State of bit (1 or 0).
03153   */
03154 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
03155 {
03156   return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
03157 }
03158
03159 /**
03160   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
03161   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
03162   * @param  USARTx USART Instance
03163   * @retval State of bit (1 or 0).
03164   */
03165 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
03166 {
03167   return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
03168 }
03169
03170 /**
03171   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
03172   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03173   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03174   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
03175   * @param  USARTx USART Instance
03176   * @retval State of bit (1 or 0).
03177   */
03178 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
03179 {
03180   return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
03181 }
03182
03183 /**
03184   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
03185   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
03186   * @param  USARTx USART Instance
03187   * @retval State of bit (1 or 0).
03188   */
03189 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
03190 {
03191   return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
03192 }
03193
03194 /**
03195   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
03196   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
03197   * @param  USARTx USART Instance
03198   * @retval State of bit (1 or 0).
03199   */
03200 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
03201 {
03202   return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
03203 }
03204
03205 /**
03206   * @brief  Check if the USART TX FIFO Empty Flag is set or not
03207   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03208   *         FIFO mode feature is supported by the USARTx instance.
03209   * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
03210   * @param  USARTx USART Instance
03211   * @retval State of bit (1 or 0).
03212   */
03213 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx)
03214 {
03215   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
03216 }
03217
03218 /**
03219   * @brief  Check if the USART RX FIFO Full Flag is set or not
03220   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03221   *         FIFO mode feature is supported by the USARTx instance.
03222   * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
03223   * @param  USARTx USART Instance
03224   * @retval State of bit (1 or 0).
03225   */
03226 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx)
03227 {
03228   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
03229 }
03230
03231 /**
03232   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
03233   * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
03234   * @param  USARTx USART Instance
03235   * @retval State of bit (1 or 0).
03236   */
03237 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
03238 {
03239   return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
03240 }
03241
03242 /**
03243   * @brief  Check if the USART TX FIFO Threshold Flag is set or not
03244   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03245   *         FIFO mode feature is supported by the USARTx instance.
03246   * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
03247   * @param  USARTx USART Instance
03248   * @retval State of bit (1 or 0).
03249   */
03250 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx)
03251 {
03252   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
03253 }
03254
03255 /**
03256   * @brief  Check if the USART RX FIFO Threshold Flag is set or not
03257   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03258   *         FIFO mode feature is supported by the USARTx instance.
03259   * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
03260   * @param  USARTx USART Instance
03261   * @retval State of bit (1 or 0).
03262   */
03263 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx)
03264 {
03265   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
03266 }
03267
03268 /**
03269   * @brief  Clear Parity Error Flag
03270   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
03271   * @param  USARTx USART Instance
03272   * @retval None
03273   */
03274 __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
03275 {
03276   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
03277 }
03278
03279 /**
03280   * @brief  Clear Framing Error Flag
03281   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
03282   * @param  USARTx USART Instance
03283   * @retval None
03284   */
03285 __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
03286 {
03287   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
03288 }
03289
03290 /**
03291   * @brief  Clear Noise Error detected Flag
03292   * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
03293   * @param  USARTx USART Instance
03294   * @retval None
03295   */
03296 __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
03297 {
03298   WRITE_REG(USARTx->ICR, USART_ICR_NECF);
03299 }
03300
03301 /**
03302   * @brief  Clear OverRun Error Flag
03303   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
03304   * @param  USARTx USART Instance
03305   * @retval None
03306   */
03307 __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
03308 {
03309   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
03310 }
03311
03312 /**
03313   * @brief  Clear IDLE line detected Flag
03314   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
03315   * @param  USARTx USART Instance
03316   * @retval None
03317   */
03318 __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
03319 {
03320   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
03321 }
03322
03323 /**
03324   * @brief  Clear TX FIFO Empty Flag
03325   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03326   *         FIFO mode feature is supported by the USARTx instance.
03327   * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
03328   * @param  USARTx USART Instance
03329   * @retval None
03330   */
03331 __STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
03332 {
03333   WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
03334 }
03335
03336 /**
03337   * @brief  Clear Transmission Complete Flag
03338   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
03339   * @param  USARTx USART Instance
03340   * @retval None
03341   */
03342 __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
03343 {
03344   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
03345 }
03346
03347 /**
03348   * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
03349   * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
03350   * @param  USARTx USART Instance
03351   * @retval None
03352   */
03353 __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
03354 {
03355   WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
03356 }
03357
03358 /**
03359   * @brief  Clear LIN Break Detection Flag
03360   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03361   *         LIN feature is supported by the USARTx instance.
03362   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
03363   * @param  USARTx USART Instance
03364   * @retval None
03365   */
03366 __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
03367 {
03368   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
03369 }
03370
03371 /**
03372   * @brief  Clear CTS Interrupt Flag
03373   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03374   *         Hardware Flow control feature is supported by the USARTx instance.
03375   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
03376   * @param  USARTx USART Instance
03377   * @retval None
03378   */
03379 __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
03380 {
03381   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
03382 }
03383
03384 /**
03385   * @brief  Clear Receiver Time Out Flag
03386   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
03387   * @param  USARTx USART Instance
03388   * @retval None
03389   */
03390 __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
03391 {
03392   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
03393 }
03394
03395 /**
03396   * @brief  Clear End Of Block Flag
03397   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03398   *         Smartcard feature is supported by the USARTx instance.
03399   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
03400   * @param  USARTx USART Instance
03401   * @retval None
03402   */
03403 __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
03404 {
03405   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
03406 }
03407
03408 /**
03409   * @brief  Clear SPI Slave Underrun Flag
03410   * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03411   *         SPI Slave mode feature is supported by the USARTx instance.
03412   * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
03413   * @param  USARTx USART Instance
03414   * @retval None
03415   */
03416 __STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
03417 {
03418   WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
03419 }
03420
03421 /**
03422   * @brief  Clear Character Match Flag
03423   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
03424   * @param  USARTx USART Instance
03425   * @retval None
03426   */
03427 __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
03428 {
03429   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
03430 }
03431
03432 /**
03433   * @brief  Clear Wake Up from stop mode Flag
03434   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03435   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03436   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
03437   * @param  USARTx USART Instance
03438   * @retval None
03439   */
03440 __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
03441 {
03442   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
03443 }
03444
03445 /**
03446   * @}
03447   */
03448
03449 /** @defgroup USART_LL_EF_IT_Management IT_Management
03450   * @{
03451   */
03452
03453 /**
03454   * @brief  Enable IDLE Interrupt
03455   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
03456   * @param  USARTx USART Instance
03457   * @retval None
03458   */
03459 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
03460 {
03461   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03462 }
03463
03464 /* Legacy define */
03465 #define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
03466
03467 /**
03468   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
03469   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03470   *         FIFO mode feature is supported by the USARTx instance.
03471   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
03472   * @param  USARTx USART Instance
03473   * @retval None
03474   */
03475 __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03476 {
03477   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03478 }
03479
03480 /**
03481   * @brief  Enable Transmission Complete Interrupt
03482   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
03483   * @param  USARTx USART Instance
03484   * @retval None
03485   */
03486 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
03487 {
03488   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
03489 }
03490
03491 /* Legacy define */
03492 #define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
03493
03494 /**
03495   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
03496   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03497   *         FIFO mode feature is supported by the USARTx instance.
03498   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
03499   * @param  USARTx USART Instance
03500   * @retval None
03501   */
03502 __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03503 {
03504   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03505 }
03506
03507 /**
03508   * @brief  Enable Parity Error Interrupt
03509   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
03510   * @param  USARTx USART Instance
03511   * @retval None
03512   */
03513 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
03514 {
03515   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
03516 }
03517
03518 /**
03519   * @brief  Enable Character Match Interrupt
03520   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
03521   * @param  USARTx USART Instance
03522   * @retval None
03523   */
03524 __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
03525 {
03526   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
03527 }
03528
03529 /**
03530   * @brief  Enable Receiver Timeout Interrupt
03531   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
03532   * @param  USARTx USART Instance
03533   * @retval None
03534   */
03535 __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
03536 {
03537   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
03538 }
03539
03540 /**
03541   * @brief  Enable End Of Block Interrupt
03542   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03543   *         Smartcard feature is supported by the USARTx instance.
03544   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
03545   * @param  USARTx USART Instance
03546   * @retval None
03547   */
03548 __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
03549 {
03550   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
03551 }
03552
03553 /**
03554   * @brief  Enable TX FIFO Empty Interrupt
03555   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03556   *         FIFO mode feature is supported by the USARTx instance.
03557   * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
03558   * @param  USARTx USART Instance
03559   * @retval None
03560   */
03561 __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
03562 {
03563   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03564 }
03565
03566 /**
03567   * @brief  Enable RX FIFO Full Interrupt
03568   * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
03569   * @param  USARTx USART Instance
03570   * @retval None
03571   */
03572 __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
03573 {
03574   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03575 }
03576
03577 /**
03578   * @brief  Enable LIN Break Detection Interrupt
03579   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03580   *         LIN feature is supported by the USARTx instance.
03581   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
03582   * @param  USARTx USART Instance
03583   * @retval None
03584   */
03585 __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
03586 {
03587   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
03588 }
03589
03590 /**
03591   * @brief  Enable Error Interrupt
03592   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03593   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03594   *           0: Interrupt is inhibited
03595   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03596   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
03597   * @param  USARTx USART Instance
03598   * @retval None
03599   */
03600 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
03601 {
03602   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
03603 }
03604
03605 /**
03606   * @brief  Enable CTS Interrupt
03607   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03608   *         Hardware Flow control feature is supported by the USARTx instance.
03609   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
03610   * @param  USARTx USART Instance
03611   * @retval None
03612   */
03613 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
03614 {
03615   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
03616 }
03617
03618 /**
03619   * @brief  Enable Wake Up from Stop Mode Interrupt
03620   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03621   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03622   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
03623   * @param  USARTx USART Instance
03624   * @retval None
03625   */
03626 __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
03627 {
03628   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
03629 }
03630
03631 /**
03632   * @brief  Enable TX FIFO Threshold Interrupt
03633   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03634   *         FIFO mode feature is supported by the USARTx instance.
03635   * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
03636   * @param  USARTx USART Instance
03637   * @retval None
03638   */
03639 __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
03640 {
03641   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03642 }
03643
03644 /**
03645   * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
03646   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03647   *         Smartcard feature is supported by the USARTx instance.
03648   * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
03649   * @param  USARTx USART Instance
03650   * @retval None
03651   */
03652 __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
03653 {
03654   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03655 }
03656
03657 /**
03658   * @brief  Enable RX FIFO Threshold Interrupt
03659   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03660   *         FIFO mode feature is supported by the USARTx instance.
03661   * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
03662   * @param  USARTx USART Instance
03663   * @retval None
03664   */
03665 __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
03666 {
03667   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03668 }
03669
03670 /**
03671   * @brief  Disable IDLE Interrupt
03672   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
03673   * @param  USARTx USART Instance
03674   * @retval None
03675   */
03676 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
03677 {
03678   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03679 }
03680
03681 /* Legacy define */
03682 #define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
03683
03684 /**
03685   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
03686   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03687   *         FIFO mode feature is supported by the USARTx instance.
03688   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
03689   * @param  USARTx USART Instance
03690   * @retval None
03691   */
03692 __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03693 {
03694   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03695 }
03696
03697 /**
03698   * @brief  Disable Transmission Complete Interrupt
03699   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
03700   * @param  USARTx USART Instance
03701   * @retval None
03702   */
03703 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
03704 {
03705   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
03706 }
03707
03708 /* Legacy define */
03709 #define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
03710
03711 /**
03712   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
03713   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03714   *         FIFO mode feature is supported by the USARTx instance.
03715   * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
03716   * @param  USARTx USART Instance
03717   * @retval None
03718   */
03719 __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03720 {
03721   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03722 }
03723
03724 /**
03725   * @brief  Disable Parity Error Interrupt
03726   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
03727   * @param  USARTx USART Instance
03728   * @retval None
03729   */
03730 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
03731 {
03732   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
03733 }
03734
03735 /**
03736   * @brief  Disable Character Match Interrupt
03737   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
03738   * @param  USARTx USART Instance
03739   * @retval None
03740   */
03741 __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
03742 {
03743   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
03744 }
03745
03746 /**
03747   * @brief  Disable Receiver Timeout Interrupt
03748   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
03749   * @param  USARTx USART Instance
03750   * @retval None
03751   */
03752 __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
03753 {
03754   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
03755 }
03756
03757 /**
03758   * @brief  Disable End Of Block Interrupt
03759   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03760   *         Smartcard feature is supported by the USARTx instance.
03761   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
03762   * @param  USARTx USART Instance
03763   * @retval None
03764   */
03765 __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
03766 {
03767   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
03768 }
03769
03770 /**
03771   * @brief  Disable TX FIFO Empty Interrupt
03772   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03773   *         FIFO mode feature is supported by the USARTx instance.
03774   * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
03775   * @param  USARTx USART Instance
03776   * @retval None
03777   */
03778 __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
03779 {
03780   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03781 }
03782
03783 /**
03784   * @brief  Disable RX FIFO Full Interrupt
03785   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03786   *         FIFO mode feature is supported by the USARTx instance.
03787   * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
03788   * @param  USARTx USART Instance
03789   * @retval None
03790   */
03791 __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
03792 {
03793   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03794 }
03795
03796 /**
03797   * @brief  Disable LIN Break Detection Interrupt
03798   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03799   *         LIN feature is supported by the USARTx instance.
03800   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
03801   * @param  USARTx USART Instance
03802   * @retval None
03803   */
03804 __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
03805 {
03806   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
03807 }
03808
03809 /**
03810   * @brief  Disable Error Interrupt
03811   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03812   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03813   *           0: Interrupt is inhibited
03814   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03815   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
03816   * @param  USARTx USART Instance
03817   * @retval None
03818   */
03819 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
03820 {
03821   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
03822 }
03823
03824 /**
03825   * @brief  Disable CTS Interrupt
03826   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03827   *         Hardware Flow control feature is supported by the USARTx instance.
03828   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
03829   * @param  USARTx USART Instance
03830   * @retval None
03831   */
03832 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
03833 {
03834   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
03835 }
03836
03837 /**
03838   * @brief  Disable Wake Up from Stop Mode Interrupt
03839   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03840   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03841   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
03842   * @param  USARTx USART Instance
03843   * @retval None
03844   */
03845 __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
03846 {
03847   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
03848 }
03849
03850 /**
03851   * @brief  Disable TX FIFO Threshold Interrupt
03852   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03853   *         FIFO mode feature is supported by the USARTx instance.
03854   * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
03855   * @param  USARTx USART Instance
03856   * @retval None
03857   */
03858 __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
03859 {
03860   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03861 }
03862
03863 /**
03864   * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
03865   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03866   *         Smartcard feature is supported by the USARTx instance.
03867   * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
03868   * @param  USARTx USART Instance
03869   * @retval None
03870   */
03871 __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
03872 {
03873   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03874 }
03875
03876 /**
03877   * @brief  Disable RX FIFO Threshold Interrupt
03878   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03879   *         FIFO mode feature is supported by the USARTx instance.
03880   * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
03881   * @param  USARTx USART Instance
03882   * @retval None
03883   */
03884 __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
03885 {
03886   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03887 }
03888
03889 /**
03890   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
03891   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
03892   * @param  USARTx USART Instance
03893   * @retval State of bit (1 or 0).
03894   */
03895 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
03896 {
03897   return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
03898 }
03899
03900 /* Legacy define */
03901 #define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
03902
03903 /**
03904   * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
03905   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03906   *         FIFO mode feature is supported by the USARTx instance.
03907   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
03908   * @param  USARTx USART Instance
03909   * @retval State of bit (1 or 0).
03910   */
03911 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx)
03912 {
03913   return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
03914 }
03915
03916 /**
03917   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
03918   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
03919   * @param  USARTx USART Instance
03920   * @retval State of bit (1 or 0).
03921   */
03922 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
03923 {
03924   return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
03925 }
03926
03927 /* Legacy define */
03928 #define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
03929
03930 /**
03931   * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
03932   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03933   *         FIFO mode feature is supported by the USARTx instance.
03934   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
03935   * @param  USARTx USART Instance
03936   * @retval State of bit (1 or 0).
03937   */
03938 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx)
03939 {
03940   return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
03941 }
03942
03943 /**
03944   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
03945   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
03946   * @param  USARTx USART Instance
03947   * @retval State of bit (1 or 0).
03948   */
03949 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
03950 {
03951   return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
03952 }
03953
03954 /**
03955   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
03956   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
03957   * @param  USARTx USART Instance
03958   * @retval State of bit (1 or 0).
03959   */
03960 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
03961 {
03962   return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
03963 }
03964
03965 /**
03966   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
03967   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
03968   * @param  USARTx USART Instance
03969   * @retval State of bit (1 or 0).
03970   */
03971 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
03972 {
03973   return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
03974 }
03975
03976 /**
03977   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
03978   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03979   *         Smartcard feature is supported by the USARTx instance.
03980   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
03981   * @param  USARTx USART Instance
03982   * @retval State of bit (1 or 0).
03983   */
03984 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
03985 {
03986   return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
03987 }
03988
03989 /**
03990   * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
03991   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03992   *         FIFO mode feature is supported by the USARTx instance.
03993   * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
03994   * @param  USARTx USART Instance
03995   * @retval State of bit (1 or 0).
03996   */
03997 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx)
03998 {
03999   return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
04000 }
04001
04002 /**
04003   * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
04004   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04005   *         FIFO mode feature is supported by the USARTx instance.
04006   * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
04007   * @param  USARTx USART Instance
04008   * @retval State of bit (1 or 0).
04009   */
04010 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx)
04011 {
04012   return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
04013 }
04014
04015 /**
04016   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
04017   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
04018   *         LIN feature is supported by the USARTx instance.
04019   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
04020   * @param  USARTx USART Instance
04021   * @retval State of bit (1 or 0).
04022   */
04023 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
04024 {
04025   return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
04026 }
04027
04028 /**
04029   * @brief  Check if the USART Error Interrupt is enabled or disabled.
04030   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
04031   * @param  USARTx USART Instance
04032   * @retval State of bit (1 or 0).
04033   */
04034 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
04035 {
04036   return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
04037 }
04038
04039 /**
04040   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
04041   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
04042   *         Hardware Flow control feature is supported by the USARTx instance.
04043   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
04044   * @param  USARTx USART Instance
04045   * @retval State of bit (1 or 0).
04046   */
04047 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
04048 {
04049   return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
04050 }
04051
04052 /**
04053   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
04054   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
04055   *         Wake-up from Stop mode feature is supported by the USARTx instance.
04056   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
04057   * @param  USARTx USART Instance
04058   * @retval State of bit (1 or 0).
04059   */
04060 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
04061 {
04062   return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
04063 }
04064
04065 /**
04066   * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
04067   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04068   *         FIFO mode feature is supported by the USARTx instance.
04069   * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
04070   * @param  USARTx USART Instance
04071   * @retval State of bit (1 or 0).
04072   */
04073 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx)
04074 {
04075   return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
04076 }
04077
04078 /**
04079   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
04080   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
04081   *         Smartcard feature is supported by the USARTx instance.
04082   * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
04083   * @param  USARTx USART Instance
04084   * @retval State of bit (1 or 0).
04085   */
04086 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
04087 {
04088   return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
04089 }
04090
04091 /**
04092   * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
04093   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04094   *         FIFO mode feature is supported by the USARTx instance.
04095   * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
04096   * @param  USARTx USART Instance
04097   * @retval State of bit (1 or 0).
04098   */
04099 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx)
04100 {
04101   return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
04102 }
04103
04104 /**
04105   * @}
04106   */
04107
04108 /** @defgroup USART_LL_EF_DMA_Management DMA_Management
04109   * @{
04110   */
04111
04112 /**
04113   * @brief  Enable DMA Mode for reception
04114   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
04115   * @param  USARTx USART Instance
04116   * @retval None
04117   */
04118 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
04119 {
04120   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
04121 }
04122
04123 /**
04124   * @brief  Disable DMA Mode for reception
04125   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
04126   * @param  USARTx USART Instance
04127   * @retval None
04128   */
04129 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
04130 {
04131   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
04132 }
04133
04134 /**
04135   * @brief  Check if DMA Mode is enabled for reception
04136   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
04137   * @param  USARTx USART Instance
04138   * @retval State of bit (1 or 0).
04139   */
04140 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
04141 {
04142   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
04143 }
04144
04145 /**
04146   * @brief  Enable DMA Mode for transmission
04147   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
04148   * @param  USARTx USART Instance
04149   * @retval None
04150   */
04151 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
04152 {
04153   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
04154 }
04155
04156 /**
04157   * @brief  Disable DMA Mode for transmission
04158   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
04159   * @param  USARTx USART Instance
04160   * @retval None
04161   */
04162 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
04163 {
04164   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
04165 }
04166
04167 /**
04168   * @brief  Check if DMA Mode is enabled for transmission
04169   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
04170   * @param  USARTx USART Instance
04171   * @retval State of bit (1 or 0).
04172   */
04173 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
04174 {
04175   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
04176 }
04177
04178 /**
04179   * @brief  Enable DMA Disabling on Reception Error
04180   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
04181   * @param  USARTx USART Instance
04182   * @retval None
04183   */
04184 __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
04185 {
04186   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
04187 }
04188
04189 /**
04190   * @brief  Disable DMA Disabling on Reception Error
04191   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
04192   * @param  USARTx USART Instance
04193   * @retval None
04194   */
04195 __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
04196 {
04197   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
04198 }
04199
04200 /**
04201   * @brief  Indicate if DMA Disabling on Reception Error is disabled
04202   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
04203   * @param  USARTx USART Instance
04204   * @retval State of bit (1 or 0).
04205   */
04206 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
04207 {
04208   return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
04209 }
04210
04211 /**
04212   * @brief  Get the data register address used for DMA transfer
04213   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
04214   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
04215   * @param  USARTx USART Instance
04216   * @param  Direction This parameter can be one of the following values:
04217   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
04218   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
04219   * @retval Address of data register
04220   */
04221 __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
04222 {
04223   uint32_t data_reg_addr;
04224
04225   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
04226   {
04227     /* return address of TDR register */
04228     data_reg_addr = (uint32_t) &(USARTx->TDR);
04229   }
04230   else
04231   {
04232     /* return address of RDR register */
04233     data_reg_addr = (uint32_t) &(USARTx->RDR);
04234   }
04235
04236   return data_reg_addr;
04237 }
04238
04239 /**
04240   * @}
04241   */
04242
04243 /** @defgroup USART_LL_EF_Data_Management Data_Management
04244   * @{
04245   */
04246
04247 /**
04248   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
04249   * @rmtoll RDR          RDR           LL_USART_ReceiveData8
04250   * @param  USARTx USART Instance
04251   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
04252   */
04253 __STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
04254 {
04255   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
04256 }
04257
04258 /**
04259   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
04260   * @rmtoll RDR          RDR           LL_USART_ReceiveData9
04261   * @param  USARTx USART Instance
04262   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
04263   */
04264 __STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
04265 {
04266   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
04267 }
04268
04269 /**
04270   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
04271   * @rmtoll TDR          TDR           LL_USART_TransmitData8
04272   * @param  USARTx USART Instance
04273   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
04274   * @retval None
04275   */
04276 __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
04277 {
04278   USARTx->TDR = Value;
04279 }
04280
04281 /**
04282   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
04283   * @rmtoll TDR          TDR           LL_USART_TransmitData9
04284   * @param  USARTx USART Instance
04285   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
04286   * @retval None
04287   */
04288 __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
04289 {
04290   USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
04291 }
04292
04293 /**
04294   * @}
04295   */
04296
04297 /** @defgroup USART_LL_EF_Execution Execution
04298   * @{
04299   */
04300
04301 /**
04302   * @brief  Request an Automatic Baud Rate measurement on next received data frame
04303   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
04304   *         Auto Baud Rate detection feature is supported by the USARTx instance.
04305   * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
04306   * @param  USARTx USART Instance
04307   * @retval None
04308   */
04309 __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
04310 {
04311   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
04312 }
04313
04314 /**
04315   * @brief  Request Break sending
04316   * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
04317   * @param  USARTx USART Instance
04318   * @retval None
04319   */
04320 __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
04321 {
04322   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
04323 }
04324
04325 /**
04326   * @brief  Put USART in mute mode and set the RWU flag
04327   * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
04328   * @param  USARTx USART Instance
04329   * @retval None
04330   */
04331 __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
04332 {
04333   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
04334 }
04335
04336 /**
04337   * @brief  Request a Receive Data and FIFO flush
04338   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04339   *         FIFO mode feature is supported by the USARTx instance.
04340   * @note   Allows to discard the received data without reading them, and avoid an overrun
04341   *         condition.
04342   * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
04343   * @param  USARTx USART Instance
04344   * @retval None
04345   */
04346 __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
04347 {
04348   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
04349 }
04350
04351 /**
04352   * @brief  Request a Transmit data and FIFO flush
04353   * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04354   *         FIFO mode feature is supported by the USARTx instance.
04355   * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
04356   * @param  USARTx USART Instance
04357   * @retval None
04358   */
04359 __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
04360 {
04361   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
04362 }
04363
04364 /**
04365   * @}
04366   */
04367
04368 #if defined(USE_FULL_LL_DRIVER)
04369 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
04370   * @{
04371   */
04372 ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
04373 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
04374 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
04375 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04376 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04377 /**
04378   * @}
04379   */
04380 #endif /* USE_FULL_LL_DRIVER */
04381
04382 /**
04383   * @}
04384   */
04385
04386 /**
04387   * @}
04388   */
04389
04390 #endif /* USART1 || USART2 || USART3 || USART4 || USART5 || USART6 */
04391
04392 /**
04393   * @}
04394   */
04395
04396 #ifdef __cplusplus
04397 }
04398 #endif
04399
04400 #endif /* STM32G0xx_LL_USART_H */
04401
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_utils.c Source File

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stm32g0xx_ll_utils.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_utils.c
00004   * @author  MCD Application Team
00005   * @brief   UTILS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018 /* Includes ------------------------------------------------------------------*/
00019 #include "stm32g0xx_ll_utils.h"
00020 #include "stm32g0xx_ll_rcc.h"
00021 #include "stm32g0xx_ll_system.h"
00022 #include "stm32g0xx_ll_pwr.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif /* USE_FULL_ASSERT */
00028
00029 /** @addtogroup STM32G0xx_LL_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup UTILS_LL
00034   * @{
00035   */
00036
00037 /* Private types -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private constants ---------------------------------------------------------*/
00040 /** @addtogroup UTILS_LL_Private_Constants
00041   * @{
00042   */
00043 #define UTILS_MAX_FREQUENCY          64000000U     /*!< Maximum frequency for system clock, in Hz */
00044
00045 /* Defines used for PLL range */
00046 #define UTILS_PLLVCO_INPUT_MIN       4000000U      /*!< Frequency min for PLLVCO input, in Hz   */
00047 #define UTILS_PLLVCO_INPUT_MAX       8000000U      /*!< Frequency max for PLLVCO input, in Hz   */
00048 #define UTILS_PLLVCO_OUTPUT_MIN      64000000U     /*!< Frequency min for PLLVCO output, in Hz  */
00049 #define UTILS_PLLVCO_OUTPUT_MAX      344000000U    /*!< Frequency max for PLLVCO output, in Hz  */
00050
00051 /* Defines used for HSE range */
00052 #define UTILS_HSE_FREQUENCY_MIN      4000000U      /*!< Frequency min for HSE frequency, in Hz   */
00053 #define UTILS_HSE_FREQUENCY_MAX      48000000U     /*!< Frequency max for HSE frequency, in Hz   */
00054
00055 /* Defines used for FLASH latency according to HCLK Frequency */
00056 #define UTILS_SCALE1_LATENCY1_FREQ  24000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
00057 #define UTILS_SCALE1_LATENCY2_FREQ  48000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
00058 #define UTILS_SCALE1_LATENCY3_FREQ  64000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
00059 /**
00060   * @}
00061   */
00062
00063 /* Private macros ------------------------------------------------------------*/
00064 /** @addtogroup UTILS_LL_Private_Macros
00065   * @{
00066   */
00067 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
00068                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
00069                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
00070                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
00071                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
00072                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
00073                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
00074                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
00075                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
00076
00077 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
00078                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
00079                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
00080                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
00081                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
00082
00083 #define IS_LL_UTILS_HSI_DIV(__VALUE__)  (((__VALUE__) == LL_RCC_HSI_DIV_1)  \
00084                                       || ((__VALUE__) == LL_RCC_HSI_DIV_2)  \
00085                                       || ((__VALUE__) == LL_RCC_HSI_DIV_4)  \
00086                                       || ((__VALUE__) == LL_RCC_HSI_DIV_8)  \
00087                                       || ((__VALUE__) == LL_RCC_HSI_DIV_16) \
00088                                       || ((__VALUE__) == LL_RCC_HSI_DIV_32) \
00089                                       || ((__VALUE__) == LL_RCC_HSI_DIV_64) \
00090                                       || ((__VALUE__) == LL_RCC_HSI_DIV_128))
00091
00092 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
00093                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
00094                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
00095                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
00096                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
00097                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
00098                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
00099                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
00100
00101 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
00102
00103 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
00104                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \
00105                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
00106                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \
00107                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
00108                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \
00109                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
00110
00111 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
00112
00113 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
00114
00115 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY)
00116
00117 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
00118                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
00119
00120 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
00121 /**
00122   * @}
00123   */
00124 /* Private function prototypes -----------------------------------------------*/
00125 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
00126   * @{
00127   */
00128 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
00129                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
00130 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00131 static ErrorStatus UTILS_PLL_IsBusy(void);
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported functions --------------------------------------------------------*/
00137 /** @addtogroup UTILS_LL_Exported_Functions
00138   * @{
00139   */
00140
00141 /** @addtogroup UTILS_LL_EF_DELAY
00142   * @{
00143   */
00144
00145 /**
00146   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00147   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00148   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00149   * @param  HCLKFrequency HCLK frequency in Hz
00150   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
00151   * @retval None
00152   */
00153 void LL_Init1msTick(uint32_t HCLKFrequency)
00154 {
00155   /* Use frequency provided in argument */
00156   LL_InitTick(HCLKFrequency, 1000U);
00157 }
00158
00159 /**
00160   * @brief  This function provides accurate delay (in milliseconds) based
00161   *         on SysTick counter flag
00162   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
00163   *         and use rather osDelay service.
00164   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
00165   *         will configure Systick to 1ms
00166   * @param  Delay specifies the delay time length, in milliseconds.
00167   * @retval None
00168   */
00169 void LL_mDelay(uint32_t Delay)
00170 {
00171   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
00172    uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
00173   /* Add this code to indicate that local variable is not used */
00174   ((void)tmp);
00175   tmpDelay  = Delay;
00176   /* Add a period to guaranty minimum wait */
00177   if (tmpDelay  < LL_MAX_DELAY)
00178   {
00179     tmpDelay ++;
00180   }
00181
00182   while (tmpDelay  != 0U)
00183   {
00184     if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
00185     {
00186       tmpDelay --;
00187     }
00188   }
00189 }
00190
00191 /**
00192   * @}
00193   */
00194
00195 /** @addtogroup UTILS_EF_SYSTEM
00196   *  @brief    System Configuration functions
00197   *
00198   @verbatim
00199  ===============================================================================
00200            ##### System Configuration functions #####
00201  ===============================================================================
00202     [..]
00203          System, AHB and APB buses clocks configuration
00204
00205          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 64000000 Hz.
00206   @endverbatim
00207   @internal
00208              Depending on the device voltage range, the maximum frequency should be
00209              adapted accordingly:
00210
00211              (++)  Table 1. HCLK clock frequency.
00212              (++)  +-------------------------------------------------------+
00213              (++)  | Latency         |    HCLK clock frequency (MHz)       |
00214              (++)  |                 |-------------------------------------|
00215              (++)  |                 | voltage range 1  | voltage range 2  |
00216              (++)  |                 |   1.08V - 1.32V  |  0.9 V - 1.10V   |
00217              (++)  |-----------------|------------------|------------------|
00218              (++)  |0WS(1 CPU cycles)|      HCLK <= 24  |      HCLK <= 8   |
00219              (++)  |-----------------|------------------|------------------|
00220              (++)  |1WS(2 CPU cycles)|      HCLK <= 48  |      HCLK <= 16  |
00221              (++)  |-----------------|------------------|------------------|
00222              (++)  |2WS(3 CPU cycles)|      HCLK <= 64  |        -         |
00223              (++)  |-----------------|------------------|------------------|
00224
00225   @endinternal
00226   * @{
00227   */
00228
00229 /**
00230   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00231   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00232   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00233   * @retval None
00234   */
00235 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
00236 {
00237   /* HCLK clock frequency */
00238   SystemCoreClock = HCLKFrequency;
00239 }
00240
00241 /**
00242   * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
00243   * @note   The application need to ensure that PLL is disabled.
00244   * @note   Function is based on the following formula:
00245   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
00246   *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
00247   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00248   *         - PLLR: ensure that max frequency at 64000000 Hz is reach (PLLVCO_output / PLLR)
00249   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00250   *                             the configuration information for the PLL.
00251   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00252   *                             the configuration information for the BUS prescalers.
00253   * @retval An ErrorStatus enumeration value:
00254   *          - SUCCESS: Max frequency configuration done
00255   *          - ERROR: Max frequency configuration not done
00256   */
00257 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00258                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00259 {
00260   ErrorStatus status;
00261   uint32_t pllfreq;
00262
00263   /* Check if one of the PLL is enabled */
00264   if (UTILS_PLL_IsBusy() == SUCCESS)
00265   {
00266     /* Calculate the new PLL output frequency */
00267     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
00268
00269     /* Enable HSI if not enabled */
00270     if (LL_RCC_HSI_IsReady() != 1U)
00271     {
00272       LL_RCC_HSI_Enable();
00273       while (LL_RCC_HSI_IsReady() != 1U)
00274       {
00275         /* Wait for HSI ready */
00276       }
00277     }
00278
00279     /* Configure PLL */
00280     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00281                                 UTILS_PLLInitStruct->PLLR);
00282
00283     /* Enable PLL and switch system clock to PLL */
00284     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00285   }
00286   else
00287   {
00288     /* Current PLL configuration cannot be modified */
00289     status = ERROR;
00290   }
00291
00292   return status;
00293 }
00294
00295 /**
00296   * @brief  This function configures system clock with HSE as clock source of the PLL
00297   * @note   The application need to ensure that PLL is disabled.
00298   * @note   Function is based on the following formula:
00299   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
00300   *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
00301   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00302   *         - PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
00303   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
00304   * @param  HSEBypass This parameter can be one of the following values:
00305   *         @arg @ref LL_UTILS_HSEBYPASS_ON
00306   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
00307   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00308   *                             the configuration information for the PLL.
00309   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00310   *                             the configuration information for the BUS prescalers.
00311   * @retval An ErrorStatus enumeration value:
00312   *          - SUCCESS: Max frequency configuration done
00313   *          - ERROR: Max frequency configuration not done
00314   */
00315 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00316                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00317 {
00318   ErrorStatus status;
00319   uint32_t pllfreq;
00320
00321   /* Check the parameters */
00322   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
00323   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
00324
00325   /* Check if one of the PLL is enabled */
00326   if (UTILS_PLL_IsBusy() == SUCCESS)
00327   {
00328     /* Calculate the new PLL output frequency */
00329     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
00330
00331     /* Enable HSE if not enabled */
00332     if (LL_RCC_HSE_IsReady() != 1U)
00333     {
00334       /* Check if need to enable HSE bypass feature or not */
00335       if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
00336       {
00337         LL_RCC_HSE_EnableBypass();
00338       }
00339       else
00340       {
00341         LL_RCC_HSE_DisableBypass();
00342       }
00343
00344       /* Enable HSE */
00345       LL_RCC_HSE_Enable();
00346       while (LL_RCC_HSE_IsReady() != 1U)
00347       {
00348         /* Wait for HSE ready */
00349       }
00350     }
00351
00352     /* Configure PLL */
00353     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00354                                 UTILS_PLLInitStruct->PLLR);
00355
00356     /* Enable PLL and switch system clock to PLL */
00357     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00358   }
00359   else
00360   {
00361     /* Current PLL configuration cannot be modified */
00362     status = ERROR;
00363   }
00364
00365   return status;
00366 }
00367
00368 /**
00369   * @brief  Update number of Flash wait states in line with new frequency and current
00370   *         voltage range.
00371   * @param  HCLKFrequency  HCLK frequency
00372   * @retval An ErrorStatus enumeration value:
00373   *          - SUCCESS: Latency has been modified
00374   *          - ERROR: Latency cannot be modified
00375   */
00376 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
00377 {
00378   uint32_t timeout;
00379   uint32_t getlatency;
00380   uint32_t latency;
00381   ErrorStatus status;
00382
00383   /* Frequency cannot be equal to 0 or greater than max clock */
00384   if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ))
00385   {
00386     status = ERROR;
00387   }
00388   else
00389   {
00390     if (HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
00391     {
00392       /* 48 < HCLK <= 64 => 2WS (3 CPU cycles) */
00393       latency = LL_FLASH_LATENCY_2;
00394     }
00395     else
00396     {
00397       if (HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
00398       {
00399         /* 24 < HCLK <= 48 => 1WS (2 CPU cycles) */
00400         latency = LL_FLASH_LATENCY_1;
00401       }
00402       else
00403       {
00404         /* else HCLKFrequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
00405         latency = LL_FLASH_LATENCY_0;
00406       }
00407     }
00408
00409     LL_FLASH_SetLatency(latency);
00410
00411     /* Check that the new number of wait states is taken into account to access the Flash
00412        memory by reading the FLASH_ACR register */
00413     timeout = 2u;
00414     do
00415     {
00416       /* Wait for Flash latency to be updated */
00417       getlatency = LL_FLASH_GetLatency();
00418       timeout--;
00419     } while ((getlatency != latency) && (timeout > 0u));
00420
00421     if(getlatency != latency)
00422     {
00423       status = ERROR;
00424     }
00425     else
00426     {
00427       status = SUCCESS;
00428     }
00429   }
00430
00431   return status;
00432 }
00433
00434 /**
00435   * @}
00436   */
00437
00438 /**
00439   * @}
00440   */
00441
00442 /** @addtogroup UTILS_LL_Private_Functions
00443   * @{
00444   */
00445
00446 /**
00447   * @brief  Function to check that PLL can be modified
00448   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
00449   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00450   *                             the configuration information for the PLL.
00451   * @retval PLL output frequency (in Hz)
00452   */
00453 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
00454 {
00455   uint32_t pllfreq;
00456
00457   /* Check the parameters */
00458   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00459   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00460   assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
00461
00462   /* Check different PLL parameters according to RM                          */
00463   /*  - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz.   */
00464   pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
00465   assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
00466
00467   /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
00468   pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
00469   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
00470
00471   /*  - PLLR: ensure that max frequency at 64000000 Hz is reached                   */
00472   pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U));
00473   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
00474
00475   return pllfreq;
00476 }
00477
00478 /**
00479   * @brief  Function to check that PLL can be modified
00480   * @retval An ErrorStatus enumeration value:
00481   *          - SUCCESS: PLL modification can be done
00482   *          - ERROR: PLL is busy
00483   */
00484 static ErrorStatus UTILS_PLL_IsBusy(void)
00485 {
00486   ErrorStatus status = SUCCESS;
00487
00488   /* Check if PLL is busy*/
00489   if (LL_RCC_PLL_IsReady() != 0U)
00490   {
00491     /* PLL configuration cannot be modified */
00492     status = ERROR;
00493   }
00494
00495   return status;
00496 }
00497
00498 /**
00499   * @brief  Function to enable PLL and switch system clock to PLL
00500   * @param  SYSCLK_Frequency SYSCLK frequency
00501   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00502   *                             the configuration information for the BUS prescalers.
00503   * @retval An ErrorStatus enumeration value:
00504   *          - SUCCESS: No problem to switch system to PLL
00505   *          - ERROR: Problem to switch system to PLL
00506   */
00507 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00508 {
00509   ErrorStatus status = SUCCESS;
00510   uint32_t hclk_frequency;
00511
00512   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
00513   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
00514
00515   /* Calculate HCLK frequency */
00516   hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
00517
00518   /* Increasing the number of wait states because of higher CPU frequency */
00519   if (SystemCoreClock < hclk_frequency)
00520   {
00521     /* Set FLASH latency to highest latency */
00522     status = LL_SetFlashLatency(hclk_frequency);
00523   }
00524
00525   /* Update system clock configuration */
00526   if (status == SUCCESS)
00527   {
00528     /* Enable PLL */
00529     LL_RCC_PLL_Enable();
00530     LL_RCC_PLL_EnableDomain_SYS();
00531     while (LL_RCC_PLL_IsReady() != 1U)
00532     {
00533       /* Wait for PLL ready */
00534     }
00535
00536     /* Sysclk activation on the main PLL */
00537     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00538     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
00539     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
00540     {
00541       /* Wait for system clock switch to PLL */
00542     }
00543
00544     /* Set APB1 & APB2 prescaler*/
00545     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
00546   }
00547
00548   /* Decreasing the number of wait states because of lower CPU frequency */
00549   if (SystemCoreClock > hclk_frequency)
00550   {
00551     /* Set FLASH latency to lowest latency */
00552     status = LL_SetFlashLatency(hclk_frequency);
00553   }
00554
00555   /* Update SystemCoreClock variable */
00556   if (status == SUCCESS)
00557   {
00558     LL_SetSystemCoreClock(hclk_frequency);
00559   }
00560
00561   return status;
00562 }
00563
00564 /**
00565   * @}
00566   */
00567
00568 /**
00569   * @}
00570   */
00571
00572 /**
00573   * @}
00574   */
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_utils.h Source File

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stm32g0xx_ll_utils.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_utils.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UTILS LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   @verbatim
00018   ==============================================================================
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021     [..]
00022     The LL UTILS driver contains a set of generic APIs that can be
00023     used by user:
00024       (+) Device electronic signature
00025       (+) Timing functions
00026       (+) PLL configuration functions
00027
00028   @endverbatim
00029   ******************************************************************************
00030   */
00031
00032 /* Define to prevent recursive inclusion -------------------------------------*/
00033 #ifndef STM32G0xx_LL_UTILS_H
00034 #define STM32G0xx_LL_UTILS_H
00035
00036 #ifdef __cplusplus
00037 extern "C" {
00038 #endif
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32g0xx.h"
00042
00043 /** @addtogroup STM32G0xx_LL_Driver
00044   * @{
00045   */
00046
00047 /** @defgroup UTILS_LL UTILS
00048   * @{
00049   */
00050
00051 /* Private types -------------------------------------------------------------*/
00052 /* Private variables ---------------------------------------------------------*/
00053
00054 /* Private constants ---------------------------------------------------------*/
00055 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
00056   * @{
00057   */
00058
00059 /* Max delay can be used in LL_mDelay */
00060 #define LL_MAX_DELAY                  0xFFFFFFFFU
00061
00062 /**
00063  * @brief Unique device ID register base address
00064  */
00065 #define UID_BASE_ADDRESS              UID_BASE
00066
00067 /**
00068  * @brief Flash size data register base address
00069  */
00070 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
00071
00072 /**
00073  * @brief Package data register base address
00074  */
00075 #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
00076
00077 /**
00078   * @}
00079   */
00080
00081 /* Private macros ------------------------------------------------------------*/
00082 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
00083   * @{
00084   */
00085 /**
00086   * @}
00087   */
00088 /* Exported types ------------------------------------------------------------*/
00089 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
00090   * @{
00091   */
00092 /**
00093   * @brief  UTILS PLL structure definition
00094   */
00095 typedef struct
00096 {
00097   uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
00098                         This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
00099
00100                         This feature can be modified afterwards using unitary function
00101                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00102
00103   uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
00104                         This parameter must be a number between Min_Data = 8 and Max_Data = 86
00105
00106                         This feature can be modified afterwards using unitary function
00107                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00108
00109   uint32_t PLLR;   /*!< Division for the main system clock.
00110                         This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
00111
00112                         This feature can be modified afterwards using unitary function
00113                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00114 } LL_UTILS_PLLInitTypeDef;
00115
00116 /**
00117   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
00118   */
00119 typedef struct
00120 {
00121   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00122                                        This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00123
00124                                        This feature can be modified afterwards using unitary function
00125                                        @ref LL_RCC_SetAHBPrescaler(). */
00126
00127   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00128                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
00129
00130                                        This feature can be modified afterwards using unitary function
00131                                        @ref LL_RCC_SetAPB1Prescaler(). */
00132 } LL_UTILS_ClkInitTypeDef;
00133
00134 /**
00135   * @}
00136   */
00137
00138 /* Exported constants --------------------------------------------------------*/
00139 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
00140   * @{
00141   */
00142
00143 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
00144   * @{
00145   */
00146 #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
00147 #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
00153   * @{
00154   */
00155 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00156 #define LL_UTILS_PACKAGETYPE_QFP100         0x00000000U /*!< LQFP100  package type                               */
00157 #define LL_UTILS_PACKAGETYPE_QFN32_GP       0x00000001U /*!< LQFP32/UFQFPN32 General purpose (GP)                */
00158 #define LL_UTILS_PACKAGETYPE_QFN32_N        0x00000002U /*!< LQFP32/UFQFPN32 N-version                           */
00159 #define LL_UTILS_PACKAGETYPE_QFN48_GP       0x00000004U /*!< LQFP48/UFQPN48 General purpose (GP)                 */
00160 #define LL_UTILS_PACKAGETYPE_QFN48_N        0x00000005U /*!< LQFP48/UFQPN48 N-version                            */
00161 #define LL_UTILS_PACKAGETYPE_WLCSP52        0x00000006U /*!< WLCSP52                                             */
00162 #define LL_UTILS_PACKAGETYPE_QFN64_GP       0x00000007U /*!< LQFP64 General purpose (GP)                         */
00163 #define LL_UTILS_PACKAGETYPE_QFN64_N        0x00000008U /*!< LQFP64 N-version                                    */
00164 #define LL_UTILS_PACKAGETYPE_BGA64_N        0x0000000AU /*!< UFBGA64 N-version                                   */
00165 #define LL_UTILS_PACKAGETYPE_QFP80          0x0000000BU /*!< LQFP80  package type                                */
00166 #define LL_UTILS_PACKAGETYPE_BGA100         0x0000000CU /*!< UBGA100  package type                               */
00167 #elif defined(STM32G061xx) || defined(STM32G051xx) || defined(STM32G050xx) || defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
00168 #define LL_UTILS_PACKAGETYPE_SO8            0x00000001U /*!< SO8 package type                                    */
00169 #define LL_UTILS_PACKAGETYPE_WLCSP18        0x00000002U /*!< WLCSP18 package type                                */
00170 #define LL_UTILS_PACKAGETYPE_TSSOP20        0x00000003U /*!< TSSOP20 package type                                */
00171 #define LL_UTILS_PACKAGETYPE_QFP28          0x00000004U /*!< UFQFPN28 package type                               */
00172 #define LL_UTILS_PACKAGETYPE_QFN32          0x00000005U /*!< UFQFPN32 / LQFP32 package type                      */
00173 #define LL_UTILS_PACKAGETYPE_QFN48          0x00000007U /*!< UFQFPN48 / LQFP48 package type                      */
00174 #elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
00175 #define LL_UTILS_PACKAGETYPE_QFN28_GP       0x00000000U /*!< UFQFPN28 general purpose (GP) package type          */
00176 #define LL_UTILS_PACKAGETYPE_QFN28_PD       0x00000001U /*!< UFQFPN28 Power Delivery (PD)                        */
00177 #define LL_UTILS_PACKAGETYPE_QFN32_GP       0x00000004U /*!< UFQFPN32 / LQFP32 general purpose (GP) package type */
00178 #define LL_UTILS_PACKAGETYPE_QFN32_PD       0x00000005U /*!< UFQFPN32 / LQFP32 Power Delivery (PD) package type  */
00179 #define LL_UTILS_PACKAGETYPE_QFN48          0x00000008U /*!< UFQFPN48 / LQFP488 package type                     */
00180 #define LL_UTILS_PACKAGETYPE_QFP64          0x0000000CU /*!< LQPF64 package type                                 */
00181 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported macro ------------------------------------------------------------*/
00191
00192 /* Exported functions --------------------------------------------------------*/
00193 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
00194   * @{
00195   */
00196
00197 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
00198   * @{
00199   */
00200
00201 /**
00202   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
00203   * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
00204   */
00205 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
00206 {
00207   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
00208 }
00209
00210 /**
00211   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
00212   * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
00213   */
00214 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
00215 {
00216   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
00217 }
00218
00219 /**
00220   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
00221   * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
00222   */
00223 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
00224 {
00225   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
00226 }
00227
00228 /**
00229   * @brief  Get Flash memory size
00230   * @note   This bitfield indicates the size of the device Flash memory expressed in
00231   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
00232   * @retval FLASH_SIZE[15:0]: Flash memory size
00233   */
00234 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
00235 {
00236   return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
00237 }
00238
00239 /**
00240   * @brief  Get Package type
00241   * @retval PKG[3:0]: Package type - This parameter can be a value of @ref UTILS_EC_PACKAGETYPE
00242   * @if defined(STM32G0C1xx)
00243   *         @arg @ref LL_UTILS_PACKAGETYPE_QFP100
00244   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP
00245   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32_N
00246   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48_GP
00247   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48_N
00248   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP52
00249   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN64_GP
00250   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN64_N
00251   *         @arg @ref LL_UTILS_PACKAGETYPE_BGA64_N
00252   *         @arg @ref LL_UTILS_PACKAGETYPE_QFP80
00253   *         @arg @ref LL_UTILS_PACKAGETYPE_BGA100
00254   * @elif defined(STM32G061xx) || defined(STM32G041xx)
00255   *         @arg @ref LL_UTILS_PACKAGETYPE_SO8
00256   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP18
00257   *         @arg @ref LL_UTILS_PACKAGETYPE_TSSOP20
00258   *         @arg @ref LL_UTILS_PACKAGETYPE_QFP28
00259   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32
00260   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48
00261   * @elif defined(STM32G081xx)
00262   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN28_GP
00263   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN28_PD
00264   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP
00265   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32_PD
00266   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48
00267   *         @arg @ref LL_UTILS_PACKAGETYPE_QFP64
00268   * @endif
00269   *
00270   */
00271 __STATIC_INLINE uint32_t LL_GetPackageType(void)
00272 {
00273 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
00274   return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
00275 #else
00276   return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0xFU);
00277 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
00278 }
00279
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup UTILS_LL_EF_DELAY DELAY
00285   * @{
00286   */
00287
00288 /**
00289   * @brief  This function configures the Cortex-M SysTick source of the time base.
00290   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00291   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
00292   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00293   * @param  Ticks Number of ticks
00294   * @retval None
00295   */
00296 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
00297 {
00298   /* Configure the SysTick to have interrupt in 1ms time base */
00299   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
00300   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
00301   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00302                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
00303 }
00304
00305 void        LL_Init1msTick(uint32_t HCLKFrequency);
00306 void        LL_mDelay(uint32_t Delay);
00307
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup UTILS_EF_SYSTEM SYSTEM
00313   * @{
00314   */
00315
00316 void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
00317 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00318                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00319 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00320                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00321 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
00322
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 #ifdef __cplusplus
00340 }
00341 #endif
00342
00343 #endif /* STM32G0xx_LL_UTILS_H */
Generated on Mon Jun 6 2022 10:29:04 for STM32G0C1xx HAL User Manual by doxygen 1.7.6.1


STM32G0C1xx HAL User Manual: stm32g0xx_ll_wwdg.h Source File

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stm32g0xx_ll_wwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32g0xx_ll_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * Copyright (c) 2018 STMicroelectronics.
00010   * All rights reserved.
00011   *
00012   * This software is licensed under terms that can be found in the LICENSE file
00013   * in the root directory of this software component.
00014   * If no LICENSE file comes with this software, it is provided AS-IS.
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32G0xx_LL_WWDG_H
00021 #define STM32G0xx_LL_WWDG_H
00022
00023 #ifdef __cplusplus
00024 extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32g0xx.h"
00029
00030 /** @addtogroup STM32G0xx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (WWDG)
00035
00036 /** @defgroup WWDG_LL WWDG
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /* Exported types ------------------------------------------------------------*/
00045 /* Exported constants --------------------------------------------------------*/
00046 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
00047   * @{
00048   */
00049
00050 /** @defgroup WWDG_LL_EC_IT IT Defines
00051   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
00052   * @{
00053   */
00054 #define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI
00055 /**
00056   * @}
00057   */
00058
00059 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
00060   * @{
00061   */
00062 #define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */
00063 #define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */
00064 #define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */
00065 #define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */
00066 #define LL_WWDG_PRESCALER_16                WWDG_CFR_WDGTB_2                                          /*!< WWDG counter clock = (PCLK1/4096)/16 */
00067 #define LL_WWDG_PRESCALER_32                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)                     /*!< WWDG counter clock = (PCLK1/4096)/32 */
00068 #define LL_WWDG_PRESCALER_64                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/64 */
00069 #define LL_WWDG_PRESCALER_128               (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)  /*!< WWDG counter clock = (PCLK1/4096)/128 */
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 /* Exported macro ------------------------------------------------------------*/
00079 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
00080   * @{
00081   */
00082 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
00083   * @{
00084   */
00085 /**
00086   * @brief  Write a value in WWDG register
00087   * @param  __INSTANCE__ WWDG Instance
00088   * @param  __REG__ Register to be written
00089   * @param  __VALUE__ Value to be written in the register
00090   * @retval None
00091   */
00092 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00093
00094 /**
00095   * @brief  Read a value in WWDG register
00096   * @param  __INSTANCE__ WWDG Instance
00097   * @param  __REG__ Register to be read
00098   * @retval Register value
00099   */
00100 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00101 /**
00102   * @}
00103   */
00104
00105 /**
00106   * @}
00107   */
00108
00109 /* Exported functions --------------------------------------------------------*/
00110 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
00111   * @{
00112   */
00113
00114 /** @defgroup WWDG_LL_EF_Configuration Configuration
00115   * @{
00116   */
00117 /**
00118   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
00119   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
00120   *         then it cannot be disabled again except by a reset.
00121   *         This bit is set by software and only cleared by hardware after a reset.
00122   *         When WDGA = 1, the watchdog can generate a reset.
00123   * @rmtoll CR           WDGA          LL_WWDG_Enable
00124   * @param  WWDGx WWDG Instance
00125   * @retval None
00126   */
00127 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
00128 {
00129   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
00130 }
00131
00132 /**
00133   * @brief  Checks if Window Watchdog is enabled
00134   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
00135   * @param  WWDGx WWDG Instance
00136   * @retval State of bit (1 or 0).
00137   */
00138 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
00139 {
00140   return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
00141 }
00142
00143 /**
00144   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
00145   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
00146   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
00147   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
00148   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
00149   * @rmtoll CR           T             LL_WWDG_SetCounter
00150   * @param  WWDGx WWDG Instance
00151   * @param  Counter 0..0x7F (7 bit counter value)
00152   * @retval None
00153   */
00154 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
00155 {
00156   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
00157 }
00158
00159 /**
00160   * @brief  Return current Watchdog Counter Value (7 bits counter value)
00161   * @rmtoll CR           T             LL_WWDG_GetCounter
00162   * @param  WWDGx WWDG Instance
00163   * @retval 7 bit Watchdog Counter value
00164   */
00165 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
00166 {
00167   return (READ_BIT(WWDGx->CR, WWDG_CR_T));
00168 }
00169
00170 /**
00171   * @brief  Set the time base of the prescaler (WDGTB).
00172   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
00173   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
00174   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
00175   * @param  WWDGx WWDG Instance
00176   * @param  Prescaler This parameter can be one of the following values:
00177   *         @arg @ref LL_WWDG_PRESCALER_1
00178   *         @arg @ref LL_WWDG_PRESCALER_2
00179   *         @arg @ref LL_WWDG_PRESCALER_4
00180   *         @arg @ref LL_WWDG_PRESCALER_8
00181   *         @arg @ref LL_WWDG_PRESCALER_16
00182   *         @arg @ref LL_WWDG_PRESCALER_32
00183   *         @arg @ref LL_WWDG_PRESCALER_64
00184   *         @arg @ref LL_WWDG_PRESCALER_128
00185   * @retval None
00186   */
00187 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
00188 {
00189   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
00190 }
00191
00192 /**
00193   * @brief  Return current Watchdog Prescaler Value
00194   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
00195   * @param  WWDGx WWDG Instance
00196   * @retval Returned value can be one of the following values:
00197   *         @arg @ref LL_WWDG_PRESCALER_1
00198   *         @arg @ref LL_WWDG_PRESCALER_2
00199   *         @arg @ref LL_WWDG_PRESCALER_4
00200   *         @arg @ref LL_WWDG_PRESCALER_8
00201   *         @arg @ref LL_WWDG_PRESCALER_16
00202   *         @arg @ref LL_WWDG_PRESCALER_32
00203   *         @arg @ref LL_WWDG_PRESCALER_64
00204   *         @arg @ref LL_WWDG_PRESCALER_128
00205   */
00206 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
00207 {
00208   return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
00209 }
00210
00211 /**
00212   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
00213   * @note   This window value defines when write in the WWDG_CR register
00214   *         to program Watchdog counter is allowed.
00215   *         Watchdog counter value update must occur only when the counter value
00216   *         is lower than the Watchdog window register value.
00217   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
00218   *         (in the control register) is refreshed before the downcounter has reached
00219   *         the watchdog window register value.
00220   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
00221   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
00222   * @rmtoll CFR          W             LL_WWDG_SetWindow
00223   * @param  WWDGx WWDG Instance
00224   * @param  Window 0x00..0x7F (7 bit Window value)
00225   * @retval None
00226   */
00227 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
00228 {
00229   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
00230 }
00231
00232 /**
00233   * @brief  Return current Watchdog Window Value (7 bits value)
00234   * @rmtoll CFR          W             LL_WWDG_GetWindow
00235   * @param  WWDGx WWDG Instance
00236   * @retval 7 bit Watchdog Window value
00237   */
00238 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
00239 {
00240   return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
00241 }
00242
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
00248   * @{
00249   */
00250 /**
00251   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
00252   * @note   This bit is set by hardware when the counter has reached the value 0x40.
00253   *         It must be cleared by software by writing 0.
00254   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
00255   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
00256   * @param  WWDGx WWDG Instance
00257   * @retval State of bit (1 or 0).
00258   */
00259 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
00260 {
00261   return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
00262 }
00263
00264 /**
00265   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
00266   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
00267   * @param  WWDGx WWDG Instance
00268   * @retval None
00269   */
00270 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
00271 {
00272   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
00273 }
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
00280   * @{
00281   */
00282 /**
00283   * @brief  Enable the Early Wakeup Interrupt.
00284   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
00285   *         This interrupt is only cleared by hardware after a reset
00286   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
00287   * @param  WWDGx WWDG Instance
00288   * @retval None
00289   */
00290 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
00291 {
00292   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
00293 }
00294
00295 /**
00296   * @brief  Check if Early Wakeup Interrupt is enabled
00297   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
00298   * @param  WWDGx WWDG Instance
00299   * @retval State of bit (1 or 0).
00300   */
00301 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
00302 {
00303   return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
00304 }
00305
00306 /**
00307   * @}
00308   */
00309
00310 /**
00311   * @}
00312   */
00313
00314 /**
00315   * @}
00316   */
00317
00318 #endif /* WWDG */
00319
00320 /**
00321   * @}
00322   */
00323
00324 #ifdef __cplusplus
00325 }
00326 #endif
00327
00328 #endif /* STM32G0xx_LL_WWDG_H */
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STM32G0C1xx HAL User Manual: userManualMainpage.txt File Reference

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